{ "full_text": "\n\n<>\n\nJune 2024\nRM0090 Rev 21\n1/1757\n1\nRM0090\nReference manual\nSTM32F405/415, STM32F407/417, STM32F427/437 and\nSTM32F429/439 advanced Arm®-based 32-bit MCUs\nIntroduction\nThis reference manual targets application developers. It provides complete information on \nhow to use the STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx and \nSTM32F43xxx microcontroller memory and peripherals.\nThe STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx and STM32F43xxx constitute \na family of microcontrollers with different memory sizes, packages and peripherals.\nFor ordering information, mechanical and electrical device characteristics please refer to the \ndatasheets.\nFor information on the Arm® Cortex®-M4 with FPU core, please refer to the Cortex®-M4 with \nFPU Technical Reference Manual.\nThe STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx and STM32F43xxx \nmicrocontrollers include ST state-of-the-art patented technology.\nRelated documents\nAvailable from STMicroelectronics web site (www.st.com):\n•\nSTM32F40x and STM32F41x datasheets\n•\nSTM32F42x and STM32F43x datasheets\n•\nSTM32F40x and STM32F41x errata sheets\n•\nSTM32F42x and STM32F43x errata sheets\n•\nFor information on the Arm® Cortex®-M4 with FPU, refer to the STM32F3xx/F4xxx \nCortex®-M4 with FPU programming manual (PM0214).\nwww.st.com\n\n\n<>\n\nContents\nRM0090\n2/1757\nRM0090 Rev 21\nContents\n1\nDocumentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57\n1.1\nList of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57\n1.2\nGlossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58\n1.3\nPeripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58\n2\nMemory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59\n2.1\nSystem architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59\n2.1.1\nI-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62\n2.1.2\nD-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62\n2.1.3\nS-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62\n2.1.4\nDMA memory bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63\n2.1.5\nDMA peripheral bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63\n2.1.6\nEthernet DMA bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63\n2.1.7\nUSB OTG HS DMA bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63\n2.1.8\nLCD-TFT controller DMA bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63\n2.1.9\nDMA2D bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63\n2.1.10\nBusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63\n2.1.11\nAHB/APB bridges (APB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64\n2.2\nMemory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64\n2.3\nMemory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64\n2.3.1\nEmbedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68\n2.3.2\nFlash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68\n2.3.3\nBit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68\n2.4\nBoot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69\n3\nEmbedded flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73\n3.1\nIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73\n3.2\nMain features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73\n3.3\nEmbedded flash memory in \nSTM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . . . . . . 74\n3.4\nEmbedded flash memory in STM32F42xxx and STM32F43xxx . . . . . . . 76\n3.5\nRead interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80\n3.5.1\nRelation between CPU clock frequency and flash memory read time . . 80\n\n\n<>\n\nRM0090 Rev 21\n3/1757\nRM0090\nContents\n39\n3.5.2\nAdaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 82\n3.6\nErase and program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84\n3.6.1\nUnlocking the Flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 84\n3.6.2\nProgram/erase parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85\n3.6.3\nErase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85\n3.6.4\nProgramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86\n3.6.5\nRead-while-write (RWW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87\n3.6.6\nInterrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88\n3.7\nOption bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88\n3.7.1\nDescription of user option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88\n3.7.2\nProgramming user option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92\n3.7.3\nRead protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93\n3.7.4\nWrite protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95\n3.7.5\nProprietary code readout protection (PCROP) . . . . . . . . . . . . . . . . . . . 96\n3.8\nOne-time programmable bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98\n3.9\nFlash interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99\n3.9.1\nFlash access control register (FLASH_ACR) \nfor STM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . . 99\n3.9.2\nFlash access control register (FLASH_ACR) \nfor STM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . 100\n3.9.3\nFlash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101\n3.9.4\nFlash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . 101\n3.9.5\nFlash status register (FLASH_SR) for \nSTM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . . . . 102\n3.9.6\nFlash status register (FLASH_SR) for \nSTM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . 103\n3.9.7\nFlash control register (FLASH_CR) for \nSTM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . . . . 104\n3.9.8\nFlash control register (FLASH_CR) for \nSTM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . 106\n3.9.9\nFlash option control register (FLASH_OPTCR) for \nSTM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . . . . 107\n3.9.10\nFlash option control register (FLASH_OPTCR) \nfor STM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . 109\n3.9.11\nFlash option control register (FLASH_OPTCR1) \nfor STM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . 111\n3.9.12\nFlash interface register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112\n4\nCRC calculation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114\n\n\n<>\n\nContents\nRM0090\n4/1757\nRM0090 Rev 21\n4.1\nCRC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114\n4.2\nCRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114\n4.3\nCRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115\n4.4\nCRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115\n4.4.1\nData register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115\n4.4.2\nIndependent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . 115\n4.4.3\nControl register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116\n4.4.4\nCRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116\n5\nPower controller (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117\n5.1\nPower supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117\n5.1.1\nIndependent A/D converter supply and reference voltage . . . . . . . . . . 118\n5.1.2\nBattery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119\n5.1.3\nVoltage regulator for STM32F405xx/07xx and STM32F415xx/17xx . . 121\n5.1.4\nVoltage regulator for STM32F42xxx and STM32F43xxx . . . . . . . . . . . 122\n5.2\nPower supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125\n5.2.1\nPower-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . 125\n5.2.2\nBrownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126\n5.2.3\nProgrammable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 126\n5.3\nLow-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127\n5.3.1\nSlowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129\n5.3.2\nPeripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129\n5.3.3\nSleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130\n5.3.4\nStop mode (STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . 131\n5.3.5\nStop mode (STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . 134\n5.3.6\nStandby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137\n5.3.7\nProgramming the RTC alternate functions to wake up the device from\nthe Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139\n5.4\nPower control registers (STM32F405xx/07xx and STM32F415xx/17xx) 142\n5.4.1\nPWR power control register (PWR_CR) \nfor STM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . 142\n5.4.2\nPWR power control/status register (PWR_CSR) \nfor STM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . 143\n5.5\nPower control registers (STM32F42xxx and STM32F43xxx) . . . . . . . . . 146\n5.5.1\nPWR power control register (PWR_CR) \nfor STM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . 146\n5.5.2\nPWR power control/status register (PWR_CSR)\nfor STM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . 149\n\n\n<>\n\nRM0090 Rev 21\n5/1757\nRM0090\nContents\n39\n5.6\nPWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151\n6\nReset and clock control for \nSTM32F42xxx and STM32F43xxx (RCC) . . . . . . . . . . . . . . . . . . . . . . . 152\n6.1\nReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152\n6.1.1\nSystem reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152\n6.1.2\nPower reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152\n6.1.3\nBackup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153\n6.2\nClocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153\n6.2.1\nHSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156\n6.2.2\nHSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157\n6.2.3\nPLL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157\n6.2.4\nLSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158\n6.2.5\nLSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158\n6.2.6\nSystem clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158\n6.2.7\nClock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159\n6.2.8\nRTC/AWU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159\n6.2.9\nWatchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160\n6.2.10\nClock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160\n6.2.11\nInternal/external clock measurement using TIM5/TIM11 . . . . . . . . . . . 160\n6.3\nRCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163\n6.3.1\nRCC clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 163\n6.3.2\nRCC PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . 165\n6.3.3\nRCC clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . 167\n6.3.4\nRCC clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . 169\n6.3.5\nRCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . 172\n6.3.6\nRCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . 175\n6.3.7\nRCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . 176\n6.3.8\nRCC APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . 176\n6.3.9\nRCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . 180\n6.3.10\nRCC AHB1 peripheral clock register (RCC_AHB1ENR) . . . . . . . . . . . 182\n6.3.11\nRCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . 184\n6.3.12\nRCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . . 185\n6.3.13\nRCC APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . 185\n6.3.14\nRCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . 189\n6.3.15\nRCC AHB1 peripheral clock enable in low power mode register\n(RCC_AHB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191\n\n\n<>\n\nContents\nRM0090\n6/1757\nRM0090 Rev 21\n6.3.16\nRCC AHB2 peripheral clock enable in low power mode register\n(RCC_AHB2LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194\n6.3.17\nRCC AHB3 peripheral clock enable in low power mode register\n(RCC_AHB3LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195\n6.3.18\nRCC APB1 peripheral clock enable in low power mode register\n(RCC_APB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195\n6.3.19\nRCC APB2 peripheral clock enabled in low power mode register\n(RCC_APB2LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199\n6.3.20\nRCC Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . 201\n6.3.21\nRCC clock control & status register (RCC_CSR) . . . . . . . . . . . . . . . . 202\n6.3.22\nRCC spread spectrum clock generation register (RCC_SSCGR) . . . . 204\n6.3.23\nRCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . . . . . . 205\n6.3.24\nRCC PLL configuration register (RCC_PLLSAICFGR) . . . . . . . . . . . . 208\n6.3.25\nRCC Dedicated Clock Configuration Register (RCC_DCKCFGR) . . . 209\n6.3.26\nRCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212\n7\nReset and clock control for \nSTM32F405xx/07xx and STM32F415xx/17xx(RCC) . . . . . . . . . . . . . . 215\n7.1\nReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215\n7.1.1\nSystem reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215\n7.1.2\nPower reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216\n7.1.3\nBackup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216\n7.2\nClocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217\n7.2.1\nHSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219\n7.2.2\nHSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220\n7.2.3\nPLL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221\n7.2.4\nLSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221\n7.2.5\nLSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222\n7.2.6\nSystem clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222\n7.2.7\nClock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222\n7.2.8\nRTC/AWU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223\n7.2.9\nWatchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223\n7.2.10\nClock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224\n7.2.11\nInternal/external clock measurement using TIM5/TIM11 . . . . . . . . . . . 224\n7.3\nRCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226\n7.3.1\nRCC clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 226\n7.3.2\nRCC PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . 228\n7.3.3\nRCC clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . 230\n\n\n<>\n\nRM0090 Rev 21\n7/1757\nRM0090\nContents\n39\n7.3.4\nRCC clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . 232\n7.3.5\nRCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . 235\n7.3.6\nRCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . 238\n7.3.7\nRCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . 239\n7.3.8\nRCC APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . 239\n7.3.9\nRCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . 242\n7.3.10\nRCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . 244\n7.3.11\nRCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . 246\n7.3.12\nRCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . . 247\n7.3.13\nRCC APB1 peripheral clock enable register\n(RCC_APB1ENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247\n7.3.14\nRCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . 250\n7.3.15\nRCC AHB1 peripheral clock enable in low power mode register\n(RCC_AHB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252\n7.3.16\nRCC AHB2 peripheral clock enable in low power mode register\n(RCC_AHB2LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254\n7.3.17\nRCC AHB3 peripheral clock enable in low power mode register\n(RCC_AHB3LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255\n7.3.18\nRCC APB1 peripheral clock enable in low power mode register\n(RCC_APB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256\n7.3.19\nRCC APB2 peripheral clock enabled in low power mode \n register (RCC_APB2LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259\n7.3.20\nRCC Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . 261\n7.3.21\nRCC clock control & status register (RCC_CSR) . . . . . . . . . . . . . . . . 262\n7.3.22\nRCC spread spectrum clock generation register (RCC_SSCGR) . . . . 264\n7.3.23\nRCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . . . . . . 265\n7.3.24\nRCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267\n8\nGeneral-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270\n8.1\nGPIO introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270\n8.2\nGPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270\n8.3\nGPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270\n8.3.1\nGeneral-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272\n8.3.2\nI/O pin multiplexer and mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273\n8.3.3\nI/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277\n8.3.4\nI/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277\n8.3.5\nI/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277\n8.3.6\nGPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277\n8.3.7\nI/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278\n\n\n<>\n\nContents\nRM0090\n8/1757\nRM0090 Rev 21\n8.3.8\nExternal interrupt/wake-up lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278\n8.3.9\nInput configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278\n8.3.10\nOutput configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279\n8.3.11\nAlternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280\n8.3.12\nAnalog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281\n8.3.13\nUsing the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15\nport pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281\n8.3.14\nUsing the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins . . . . 281\n8.3.15\nSelection of RTC_AF1 and RTC_AF2 alternate functions . . . . . . . . . . 282\n8.4\nGPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284\n8.4.1\nGPIO port mode register (GPIOx_MODER) (x = A..I/J/K) . . . . . . . . . . 284\n8.4.2\nGPIO port output type register (GPIOx_OTYPER) \n(x = A..I/J/K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284\n8.4.3\nGPIO port output speed register (GPIOx_OSPEEDR)\n(x = A..I/J/K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285\n8.4.4\nGPIO port pull-up/pull-down register (GPIOx_PUPDR)\n(x = A..I/J/K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285\n8.4.5\nGPIO port input data register (GPIOx_IDR) (x = A..I/J/K) . . . . . . . . . . 286\n8.4.6\nGPIO port output data register (GPIOx_ODR) (x = A..I/J/K) . . . . . . . . 286\n8.4.7\nGPIO port bit set/reset register (GPIOx_BSRR) (x = A..I/J/K) . . . . . . . 287\n8.4.8\nGPIO port configuration lock register (GPIOx_LCKR)\n(x = A..I/J/K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287\n8.4.9\nGPIO alternate function low register (GPIOx_AFRL) (x = A..I/J/K) . . . 288\n8.4.10\nGPIO alternate function high register (GPIOx_AFRH)\n(x = A..I/J) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289\n8.4.11\nGPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290\n9\nSystem configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 292\n9.1\nI/O compensation cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292\n9.2\nSYSCFG registers for STM32F405xx/07xx and STM32F415xx/17xx . . 292\n9.2.1\nSYSCFG memory remap register (SYSCFG_MEMRMP) . . . . . . . . . . 292\n9.2.2\nSYSCFG peripheral mode configuration register (SYSCFG_PMC) . . 293\n9.2.3\nSYSCFG external interrupt configuration register 1\n(SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294\n9.2.4\nSYSCFG external interrupt configuration register 2\n(SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294\n9.2.5\nSYSCFG external interrupt configuration register 3\n(SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295\n9.2.6\nSYSCFG external interrupt configuration register 4\n(SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296\n\n\n<>\n\nRM0090 Rev 21\n9/1757\nRM0090\nContents\n39\n9.2.7\nCompensation cell control register (SYSCFG_CMPCR) . . . . . . . . . . . 296\n9.2.8\nSYSCFG register maps for \nSTM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . . . . 297\n9.3\nSYSCFG registers for STM32F42xxx and STM32F43xxx . . . . . . . . . . . 297\n9.3.1\nSYSCFG memory remap register (SYSCFG_MEMRMP) . . . . . . . . . . 297\n9.3.2\nSYSCFG peripheral mode configuration register (SYSCFG_PMC) . . 299\n9.3.3\nSYSCFG external interrupt configuration register 1\n(SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300\n9.3.4\nSYSCFG external interrupt configuration register 2\n(SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301\n9.3.5\nSYSCFG external interrupt configuration register 3\n(SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301\n9.3.6\nSYSCFG external interrupt configuration register 4\n(SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302\n9.3.7\nCompensation cell control register (SYSCFG_CMPCR) . . . . . . . . . . . 303\n9.3.8\nSYSCFG register maps for STM32F42xxx and STM32F43xxx . . . . . . 304\n10\nDMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305\n10.1\nDMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305\n10.2\nDMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305\n10.3\nDMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307\n10.3.1\nGeneral description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307\n10.3.2\nDMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309\n10.3.3\nChannel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310\n10.3.4\nArbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311\n10.3.5\nDMA streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312\n10.3.6\nSource, destination and transfer modes . . . . . . . . . . . . . . . . . . . . . . . 312\n10.3.7\nPointer incrementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315\n10.3.8\nCircular mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316\n10.3.9\nDouble buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316\n10.3.10\nProgrammable data width, packing/unpacking, endianess . . . . . . . . . 317\n10.3.11\nSingle and burst transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319\n10.3.12\nFIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320\n10.3.13\nDMA transfer completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322\n10.3.14\nDMA transfer suspension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323\n10.3.15\nFlow controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324\n10.3.16\nSummary of the possible DMA configurations . . . . . . . . . . . . . . . . . . . 325\n10.3.17\nStream configuration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325\n\n\n<>\n\nContents\nRM0090\n10/1757\nRM0090 Rev 21\n10.3.18\nError management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326\n10.4\nDMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327\n10.5\nDMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328\n10.5.1\nDMA low interrupt status register (DMA_LISR) . . . . . . . . . . . . . . . . . . 328\n10.5.2\nDMA high interrupt status register (DMA_HISR) . . . . . . . . . . . . . . . . . 329\n10.5.3\nDMA low interrupt flag clear register (DMA_LIFCR) . . . . . . . . . . . . . . 330\n10.5.4\nDMA high interrupt flag clear register (DMA_HIFCR) . . . . . . . . . . . . . 330\n10.5.5\nDMA stream x configuration register (DMA_SxCR) (x = 0..7) . . . . . . . 331\n10.5.6\nDMA stream x number of data register (DMA_SxNDTR) (x = 0..7) . . . 334\n10.5.7\nDMA stream x peripheral address register (DMA_SxPAR) (x = 0..7) . 335\n10.5.8\nDMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7) 335\n10.5.9\nDMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7) 335\n10.5.10\nDMA stream x FIFO control register (DMA_SxFCR) (x = 0..7) . . . . . . 336\n10.5.11\nDMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338\n11\nChrom-Art Accelerator™ controller (DMA2D) . . . . . . . . . . . . . . . . . . 342\n11.1\nDMA2D introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342\n11.2\nDMA2D main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343\n11.3\nDMA2D functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343\n11.3.1\nGeneral description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343\n11.3.2\nDMA2D control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344\n11.3.3\nDMA2D foreground and background FIFOs . . . . . . . . . . . . . . . . . . . . 344\n11.3.4\nDMA2D foreground and background pixel format converter (PFC) . . . 345\n11.3.5\nDMA2D foreground and background CLUT interface . . . . . . . . . . . . . 347\n11.3.6\nDMA2D blender . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348\n11.3.7\nDMA2D output PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348\n11.3.8\nDMA2D output FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349\n11.3.9\nDMA2D AHB master port timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349\n11.3.10\nDMA2D transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350\n11.3.11\nDMA2D configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350\n11.3.12\nDMA2D transfer control (start, suspend, abort and completion) . . . . . 353\n11.3.13\nWatermark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354\n11.3.14\nError management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354\n11.3.15\nAHB dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354\n11.4\nDMA2D interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354\n11.5\nDMA2D registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355\n\n\n<>\n\nRM0090 Rev 21\n11/1757\nRM0090\nContents\n39\n11.5.1\nDMA2D control register (DMA2D_CR) . . . . . . . . . . . . . . . . . . . . . . . . 355\n11.5.2\nDMA2D Interrupt Status Register (DMA2D_ISR) . . . . . . . . . . . . . . . . 357\n11.5.3\nDMA2D interrupt flag clear register (DMA2D_IFCR) . . . . . . . . . . . . . . 358\n11.5.4\nDMA2D foreground memory address register (DMA2D_FGMAR) . . . 359\n11.5.5\nDMA2D foreground offset register (DMA2D_FGOR) . . . . . . . . . . . . . . 359\n11.5.6\nDMA2D background memory address register (DMA2D_BGMAR) . . 360\n11.5.7\nDMA2D background offset register (DMA2D_BGOR) . . . . . . . . . . . . . 360\n11.5.8\nDMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . . 361\n11.5.9\nDMA2D foreground color register (DMA2D_FGCOLR) . . . . . . . . . . . . 363\n11.5.10\nDMA2D background PFC control register (DMA2D_BGPFCCR) . . . . 364\n11.5.11\nDMA2D background color register (DMA2D_BGCOLR) . . . . . . . . . . . 366\n11.5.12\nDMA2D foreground CLUT memory address register\n(DMA2D_FGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366\n11.5.13\nDMA2D background CLUT memory address register\n(DMA2D_BGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367\n11.5.14\nDMA2D output PFC control register (DMA2D_OPFCCR) . . . . . . . . . . 367\n11.5.15\nDMA2D output color register (DMA2D_OCOLR) . . . . . . . . . . . . . . . . . 368\n11.5.16\nDMA2D output memory address register (DMA2D_OMAR) . . . . . . . . 369\n11.5.17\nDMA2D output offset register (DMA2D_OOR) . . . . . . . . . . . . . . . . . . 370\n11.5.18\nDMA2D number of line register (DMA2D_NLR) . . . . . . . . . . . . . . . . . 370\n11.5.19\nDMA2D line watermark register (DMA2D_LWR) . . . . . . . . . . . . . . . . . 371\n11.5.20\nDMA2D AHB master timer configuration register (DMA2D_AMTCR) . 371\n11.5.21\nDMA2D register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372\n12\nInterrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374\n12.1\nNested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 374\n12.1.1\nNVIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374\n12.1.2\nSysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374\n12.1.3\nInterrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374\n12.2\nExternal interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . 374\n12.2.1\nEXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382\n12.2.2\nEXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383\n12.2.3\nWake-up event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383\n12.2.4\nFunctional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383\n12.2.5\nExternal interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . 385\n12.3\nEXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387\n12.3.1\nInterrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 387\n\n\n<>\n\nContents\nRM0090\n12/1757\nRM0090 Rev 21\n12.3.2\nEvent mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387\n12.3.3\nRising trigger selection register (EXTI_RTSR) . . . . . . . . . . . . . . . . . . 388\n12.3.4\nFalling trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . . . . . 388\n12.3.5\nSoftware interrupt event register (EXTI_SWIER) . . . . . . . . . . . . . . . . 389\n12.3.6\nPending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389\n12.3.7\nEXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390\n13\nAnalog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391\n13.1\nADC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391\n13.2\nADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391\n13.3\nADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392\n13.3.1\nADC on-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393\n13.3.2\nADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393\n13.3.3\nChannel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393\n13.3.4\nSingle conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394\n13.3.5\nContinuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395\n13.3.6\nTiming diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395\n13.3.7\nAnalog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395\n13.3.8\nScan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396\n13.3.9\nInjected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397\n13.3.10\nDiscontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398\n13.4\nData alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399\n13.5\nChannel-wise programmable sampling time . . . . . . . . . . . . . . . . . . . . . 400\n13.6\nConversion on external trigger and trigger polarity . . . . . . . . . . . . . . . . 400\n13.7\nFast conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402\n13.8\nData management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403\n13.8.1\nUsing the DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403\n13.8.2\nManaging a sequence of conversions without using the DMA . . . . . . 403\n13.8.3\nConversions without DMA and without overrun detection . . . . . . . . . . 404\n13.9\nMulti ADC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404\n13.9.1\nInjected simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407\n13.9.2\nRegular simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408\n13.9.3\nInterleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410\n13.9.4\nAlternate trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411\n13.9.5\nCombined regular/injected simultaneous mode . . . . . . . . . . . . . . . . . . 413\n13.9.6\nCombined regular simultaneous + alternate trigger mode . . . . . . . . . . 414\n\n\n<>\n\nRM0090 Rev 21\n13/1757\nRM0090\nContents\n39\n13.10 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415\n13.11 Battery charge monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417\n13.12 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417\n13.13 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418\n13.13.1\nADC status register (ADC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418\n13.13.2\nADC control register 1 (ADC_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 419\n13.13.3\nADC control register 2 (ADC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 421\n13.13.4\nADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 423\n13.13.5\nADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 423\n13.13.6\nADC injected channel data offset register x (ADC_JOFRx) (x=1..4) . . 424\n13.13.7\nADC watchdog higher threshold register (ADC_HTR) . . . . . . . . . . . . . 424\n13.13.8\nADC watchdog lower threshold register (ADC_LTR) . . . . . . . . . . . . . . 425\n13.13.9\nADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 425\n13.13.10 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 426\n13.13.11 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 426\n13.13.12 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 427\n13.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . . . . . . . . . . . 428\n13.13.14 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 428\n13.13.15 ADC Common status register (ADC_CSR) . . . . . . . . . . . . . . . . . . . . . 429\n13.13.16 ADC common control register (ADC_CCR) . . . . . . . . . . . . . . . . . . . . . 430\n13.13.17 ADC common regular data register for dual and triple modes\n(ADC_CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433\n13.13.18 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433\n14\nDigital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436\n14.1\nDAC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436\n14.2\nDAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436\n14.3\nDAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438\n14.3.1\nDAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438\n14.3.2\nDAC output buffer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438\n14.3.3\nDAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438\n14.3.4\nDAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439\n14.3.5\nDAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440\n14.3.6\nDAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440\n14.3.7\nDMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441\n14.3.8\nNoise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441\n14.3.9\nTriangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442\n\n\n<>\n\nContents\nRM0090\n14/1757\nRM0090 Rev 21\n14.4\nDual DAC channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443\n14.4.1\nIndependent trigger without wave generation . . . . . . . . . . . . . . . . . . . 444\n14.4.2\nIndependent trigger with single LFSR generation . . . . . . . . . . . . . . . . 444\n14.4.3\nIndependent trigger with different LFSR generation . . . . . . . . . . . . . . 444\n14.4.4\nIndependent trigger with single triangle generation . . . . . . . . . . . . . . . 445\n14.4.5\nIndependent trigger with different triangle generation . . . . . . . . . . . . . 445\n14.4.6\nSimultaneous software start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445\n14.4.7\nSimultaneous trigger without wave generation . . . . . . . . . . . . . . . . . . 446\n14.4.8\nSimultaneous trigger with single LFSR generation . . . . . . . . . . . . . . . 446\n14.4.9\nSimultaneous trigger with different LFSR generation . . . . . . . . . . . . . 446\n14.4.10\nSimultaneous trigger with single triangle generation . . . . . . . . . . . . . . 447\n14.4.11\nSimultaneous trigger with different triangle generation . . . . . . . . . . . . 447\n14.5\nDAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448\n14.5.1\nDAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448\n14.5.2\nDAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . 451\n14.5.3\nDAC channel1 12-bit right-aligned data holding register\n(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451\n14.5.4\nDAC channel1 12-bit left aligned data holding register\n(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452\n14.5.5\nDAC channel1 8-bit right aligned data holding register\n(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452\n14.5.6\nDAC channel2 12-bit right aligned data holding register\n(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453\n14.5.7\nDAC channel2 12-bit left aligned data holding register \n(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453\n14.5.8\nDAC channel2 8-bit right-aligned data holding register\n(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453\n14.5.9\nDual DAC 12-bit right-aligned data holding register\n(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454\n14.5.10\nDUAL DAC 12-bit left aligned data holding register\n(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454\n14.5.11\nDUAL DAC 8-bit right aligned data holding register\n(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455\n14.5.12\nDAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 455\n14.5.13\nDAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 455\n14.5.14\nDAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456\n14.5.15\nDAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456\n15\nDigital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458\n\n\n<>\n\nRM0090 Rev 21\n15/1757\nRM0090\nContents\n39\n15.1\nDCMI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458\n15.2\nDCMI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458\n15.3\nDCMI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458\n15.4\nDCMI clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458\n15.5\nDCMI functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459\n15.5.1\nDMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460\n15.5.2\nDCMI physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460\n15.5.3\nSynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462\n15.5.4\nCapture modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465\n15.5.5\nCrop feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466\n15.5.6\nJPEG format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468\n15.5.7\nFIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468\n15.6\nData format description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468\n15.6.1\nData formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468\n15.6.2\nMonochrome format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469\n15.6.3\nRGB format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469\n15.6.4\nYCbCr format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469\n15.7\nDCMI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470\n15.8\nDCMI register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470\n15.8.1\nDCMI control register 1 (DCMI_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 470\n15.8.2\nDCMI status register (DCMI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473\n15.8.3\nDCMI raw interrupt status register (DCMI_RIS) . . . . . . . . . . . . . . . . . 474\n15.8.4\nDCMI interrupt enable register (DCMI_IER) . . . . . . . . . . . . . . . . . . . . 475\n15.8.5\nDCMI masked interrupt status register (DCMI_MIS) . . . . . . . . . . . . . . 476\n15.8.6\nDCMI interrupt clear register (DCMI_ICR) . . . . . . . . . . . . . . . . . . . . . . 477\n15.8.7\nDCMI embedded synchronization code register (DCMI_ESCR) . . . . . 478\n15.8.8\nDCMI embedded synchronization unmask register (DCMI_ESUR) . . 479\n15.8.9\nDCMI crop window start (DCMI_CWSTRT) . . . . . . . . . . . . . . . . . . . . . 480\n15.8.10\nDCMI crop window size (DCMI_CWSIZE) . . . . . . . . . . . . . . . . . . . . . . 480\n15.8.11\nDCMI data register (DCMI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481\n15.8.12\nDCMI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481\n16\nLCD-TFT controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483\n16.1\nIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483\n16.2\nLTDC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483\n16.3\nLTDC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484\n\n\n<>\n\nContents\nRM0090\n16/1757\nRM0090 Rev 21\n16.3.1\nLTDC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484\n16.3.2\nLTDC reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484\n16.3.3\nLCD-TFT pins and signal interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 486\n16.4\nLTDC programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486\n16.4.1\nLTDC Global configuration parameters . . . . . . . . . . . . . . . . . . . . . . . . 486\n16.4.2\nLayer programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489\n16.5\nLTDC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493\n16.6\nLTDC programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495\n16.7\nLTDC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496\n16.7.1\nLTDC Synchronization Size Configuration Register (LTDC_SSCR) . . 496\n16.7.2\nLTDC Back Porch Configuration Register (LTDC_BPCR) . . . . . . . . . . 496\n16.7.3\nLTDC Active Width Configuration Register (LTDC_AWCR) . . . . . . . . . 497\n16.7.4\nLTDC Total Width Configuration Register (LTDC_TWCR) . . . . . . . . . . 498\n16.7.5\nLTDC Global Control Register (LTDC_GCR) . . . . . . . . . . . . . . . . . . . . 498\n16.7.6\nLTDC Shadow Reload Configuration Register (LTDC_SRCR) . . . . . . 500\n16.7.7\nLTDC Background Color Configuration Register (LTDC_BCCR) . . . . 500\n16.7.8\nLTDC Interrupt Enable Register (LTDC_IER) . . . . . . . . . . . . . . . . . . . 501\n16.7.9\nLTDC Interrupt Status Register (LTDC_ISR) . . . . . . . . . . . . . . . . . . . . 502\n16.7.10\nLTDC Interrupt Clear Register (LTDC_ICR) . . . . . . . . . . . . . . . . . . . . . 502\n16.7.11\nLTDC Line Interrupt Position Configuration Register (LTDC_LIPCR) . 503\n16.7.12\nLTDC Current Position Status Register (LTDC_CPSR) . . . . . . . . . . . . 503\n16.7.13\nLTDC Current Display Status Register (LTDC_CDSR) . . . . . . . . . . . . 504\n16.7.14\nLTDC Layerx Control Register (LTDC_LxCR) (where x=1..2) . . . . . . . 505\n16.7.15\nLTDC Layerx Window Horizontal Position Configuration Register\n(LTDC_LxWHPCR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 506\n16.7.16\nLTDC Layerx Window Vertical Position Configuration Register\n(LTDC_LxWVPCR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 507\n16.7.17\nLTDC Layerx Color Keying Configuration Register (LTDC_LxCKCR)\n(where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508\n16.7.18\nLTDC Layerx Pixel Format Configuration Register (LTDC_LxPFCR)\n(where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508\n16.7.19\nLTDC Layerx Constant Alpha Configuration Register (LTDC_LxCACR)\n(where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509\n16.7.20\nLTDC Layerx Default Color Configuration Register (LTDC_LxDCCR)\n(where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509\n16.7.21\nLTDC Layerx Blending Factors Configuration Register (LTDC_LxBFCR)\n(where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511\n16.7.22\nLTDC Layerx Color Frame Buffer Address Register (LTDC_LxCFBAR)\n(where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512\n\n\n<>\n\nRM0090 Rev 21\n17/1757\nRM0090\nContents\n39\n16.7.23\nLTDC Layerx Color Frame Buffer Length Register (LTDC_LxCFBLR)\n(where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512\n16.7.24\nLTDC Layerx ColorFrame Buffer Line Number Register\n(LTDC_LxCFBLNR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 513\n16.7.25\nLTDC Layerx CLUT Write Register (LTDC_LxCLUTWR) \n(where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514\n16.7.26\nLTDC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515\n17\nAdvanced-control timers (TIM1 and TIM8) . . . . . . . . . . . . . . . . . . . . . 518\n17.1\nTIM1 and TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518\n17.2\nTIM1 and TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519\n17.3\nTIM1 and TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . 521\n17.3.1\nTime-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521\n17.3.2\nCounter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523\n17.3.3\nRepetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532\n17.3.4\nClock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535\n17.3.5\nCapture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538\n17.3.6\nInput capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541\n17.3.7\nPWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542\n17.3.8\nForced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542\n17.3.9\nOutput compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543\n17.3.10\nPWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544\n17.3.11\nComplementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 547\n17.3.12\nUsing the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549\n17.3.13\nClearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 552\n17.3.14\n6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553\n17.3.15\nOne-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554\n17.3.16\nEncoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555\n17.3.17\nTimer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558\n17.3.18\nInterfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558\n17.3.19\nTIMx and external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 560\n17.3.20\nTimer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563\n17.3.21\nDebug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563\n17.4\nTIM1 and TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564\n17.4.1\nTIM1 and TIM8 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . 564\n17.4.2\nTIM1 and TIM8 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . 565\n17.4.3\nTIM1 and TIM8 slave mode control register (TIMx_SMCR) . . . . . . . . 568\n17.4.4\nTIM1 and TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . 570\n\n\n<>\n\nContents\nRM0090\n18/1757\nRM0090 Rev 21\n17.4.5\nTIM1 and TIM8 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . 572\n17.4.6\nTIM1 and TIM8 event generation register (TIMx_EGR) . . . . . . . . . . . . 573\n17.4.7\nTIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . 575\n17.4.8\nTIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . 577\n17.4.9\nTIM1 and TIM8 capture/compare enable register (TIMx_CCER) . . . . 579\n17.4.10\nTIM1 and TIM8 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 583\n17.4.11\nTIM1 and TIM8 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 583\n17.4.12\nTIM1 and TIM8 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . 583\n17.4.13\nTIM1 and TIM8 repetition counter register (TIMx_RCR) . . . . . . . . . . . 584\n17.4.14\nTIM1 and TIM8 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . 584\n17.4.15\nTIM1 and TIM8 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . 585\n17.4.16\nTIM1 and TIM8 capture/compare register 3 (TIMx_CCR3) . . . . . . . . . 585\n17.4.17\nTIM1 and TIM8 capture/compare register 4 (TIMx_CCR4) . . . . . . . . . 586\n17.4.18\nTIM1 and TIM8 break and dead-time register (TIMx_BDTR) . . . . . . . 586\n17.4.19\nTIM1 and TIM8 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . 588\n17.4.20\nTIM1 and TIM8 DMA address for full transfer (TIMx_DMAR) . . . . . . . 589\n17.4.21\nTIM1 and TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590\n18\nGeneral-purpose timers (TIM2 to TIM5) . . . . . . . . . . . . . . . . . . . . . . . . 592\n18.1\nTIM2 to TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592\n18.2\nTIM2 to TIM5 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592\n18.3\nTIM2 to TIM5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594\n18.3.1\nTime-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594\n18.3.2\nCounter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595\n18.3.3\nClock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605\n18.3.4\nCapture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608\n18.3.5\nInput capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610\n18.3.6\nPWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611\n18.3.7\nForced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612\n18.3.8\nOutput compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612\n18.3.9\nPWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613\n18.3.10\nOne-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616\n18.3.11\nClearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 617\n18.3.12\nEncoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618\n18.3.13\nTimer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621\n18.3.14\nTimers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 621\n18.3.15\nTimer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624\n\n\n<>\n\nRM0090 Rev 21\n19/1757\nRM0090\nContents\n39\n18.3.16\nDebug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629\n18.4\nTIM2 to TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630\n18.4.1\nTIMx control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 630\n18.4.2\nTIMx control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 632\n18.4.3\nTIMx slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . 633\n18.4.4\nTIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 635\n18.4.5\nTIMx status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636\n18.4.6\nTIMx event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 638\n18.4.7\nTIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 639\n18.4.8\nTIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . 642\n18.4.9\nTIMx capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . 643\n18.4.10\nTIMx counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645\n18.4.11\nTIMx prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645\n18.4.12\nTIMx auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 645\n18.4.13\nTIMx capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 646\n18.4.14\nTIMx capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 646\n18.4.15\nTIMx capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . 647\n18.4.16\nTIMx capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . 647\n18.4.17\nTIMx DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . 648\n18.4.18\nTIMx DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . 649\n18.4.19\nTIM2 option register (TIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649\n18.4.20\nTIM5 option register (TIM5_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650\n18.4.21\nTIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651\n19\nGeneral-purpose timers (TIM9 to TIM14) . . . . . . . . . . . . . . . . . . . . . . . 653\n19.1\nTIM9 to TIM14 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653\n19.2\nTIM9 to TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653\n19.2.1\nTIM9/TIM12 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653\n19.2.2\nTIM10/TIM11 and TIM13/TIM14 main features . . . . . . . . . . . . . . . . . . 654\n19.3\nTIM9 to TIM14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 656\n19.3.1\nTime-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656\n19.3.2\nCounter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658\n19.3.3\nClock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661\n19.3.4\nCapture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663\n19.3.5\nInput capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664\n19.3.6\nPWM input mode (only for TIM9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . 666\n19.3.7\nForced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667\n\n\n<>\n\nContents\nRM0090\n20/1757\nRM0090 Rev 21\n19.3.8\nOutput compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667\n19.3.9\nPWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668\n19.3.10\nOne-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669\n19.3.11\nTIM9/12 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . 671\n19.3.12\nTimer synchronization (TIM9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674\n19.3.13\nDebug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674\n19.4\nTIM9 and TIM12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675\n19.4.1\nTIM9/12 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 675\n19.4.2\nTIM9/12 slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . 676\n19.4.3\nTIM9/12 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . . 677\n19.4.4\nTIM9/12 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 679\n19.4.5\nTIM9/12 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . 680\n19.4.6\nTIM9/12 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . 681\n19.4.7\nTIM9/12 capture/compare enable register (TIMx_CCER) . . . . . . . . . . 684\n19.4.8\nTIM9/12 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685\n19.4.9\nTIM9/12 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685\n19.4.10\nTIM9/12 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . 685\n19.4.11\nTIM9/12 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . 686\n19.4.12\nTIM9/12 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . 686\n19.4.13\nTIM9/12 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687\n19.5\nTIM10/11/13/14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689\n19.5.1\nTIM10/11/13/14 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . 689\n19.5.2\nTIM10/11/13/14 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . 690\n19.5.3\nTIM10/11/13/14 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . 690\n19.5.4\nTIM10/11/13/14 event generation register (TIMx_EGR) . . . . . . . . . . . 691\n19.5.5\nTIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) . . 691\n19.5.6\nTIM10/11/13/14 capture/compare enable register (TIMx_CCER) . . . . 694\n19.5.7\nTIM10/11/13/14 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 695\n19.5.8\nTIM10/11/13/14 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 695\n19.5.9\nTIM10/11/13/14 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . 695\n19.5.10\nTIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . 696\n19.5.11\nTIM11 option register 1 (TIM11_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . 696\n19.5.12\nTIM10/11/13/14 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697\n20\nBasic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699\n20.1\nTIM6 and TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699\n20.2\nTIM6 and TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699\n\n\n<>\n\nRM0090 Rev 21\n21/1757\nRM0090\nContents\n39\n20.3\nTIM6 and TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . 700\n20.3.1\nTime-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700\n20.3.2\nCounting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702\n20.3.3\nClock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704\n20.3.4\nDebug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705\n20.4\nTIM6 and TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705\n20.4.1\nTIM6 and TIM7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . 705\n20.4.2\nTIM6 and TIM7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . 707\n20.4.3\nTIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . 707\n20.4.4\nTIM6 and TIM7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . 708\n20.4.5\nTIM6 and TIM7 event generation register (TIMx_EGR) . . . . . . . . . . . . 708\n20.4.6\nTIM6 and TIM7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 708\n20.4.7\nTIM6 and TIM7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 709\n20.4.8\nTIM6 and TIM7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . 709\n20.4.9\nTIM6 and TIM7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710\n21\nIndependent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711\n21.1\nIWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .711\n21.2\nIWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .711\n21.3\nIWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .711\n21.3.1\nHardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711\n21.3.2\nRegister access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711\n21.3.3\nDebug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712\n21.4\nIWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713\n21.4.1\nKey register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713\n21.4.2\nPrescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713\n21.4.3\nReload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714\n21.4.4\nStatus register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714\n21.4.5\nIWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715\n22\nWindow watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716\n22.1\nWWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716\n22.2\nWWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716\n22.3\nWWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716\n22.4\nHow to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 718\n22.5\nDebug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719\n\n\n<>\n\nContents\nRM0090\n22/1757\nRM0090 Rev 21\n22.6\nWWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720\n22.6.1\nControl register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720\n22.6.2\nConfiguration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 721\n22.6.3\nStatus register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721\n22.6.4\nWWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722\n23\nCryptographic processor (CRYP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723\n23.1\nCRYP introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723\n23.2\nCRYP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723\n23.3\nCRYP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725\n23.3.1\nDES/TDES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726\n23.3.2\nAES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731\n23.3.3\nData type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742\n23.3.4\nInitialization vectors - CRYP_IV0...1(L/R) . . . . . . . . . . . . . . . . . . . . . . 745\n23.3.5\nCRYP busy state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746\n23.3.6\nProcedure to perform an encryption or a decryption . . . . . . . . . . . . . . 747\n23.3.7\nContext swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748\n23.4\nCRYP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750\n23.5\nCRYP DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751\n23.6\nCRYP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751\n23.6.1\nCRYP control register (CRYP_CR) for STM32F415/417xx . . . . . . . . . 751\n23.6.2\nCRYP control register (CRYP_CR) for STM32F415/417xx . . . . . . . . . 753\n23.6.3\nCRYP status register (CRYP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756\n23.6.4\nCRYP data input register (CRYP_DIN) . . . . . . . . . . . . . . . . . . . . . . . . 757\n23.6.5\nCRYP data output register (CRYP_DOUT) . . . . . . . . . . . . . . . . . . . . . 758\n23.6.6\nCRYP DMA control register (CRYP_DMACR) . . . . . . . . . . . . . . . . . . . 759\n23.6.7\nCRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . . . . . . . . 759\n23.6.8\nCRYP raw interrupt status register (CRYP_RISR) . . . . . . . . . . . . . . . 760\n23.6.9\nCRYP masked interrupt status register (CRYP_MISR) . . . . . . . . . . . . 760\n23.6.10\nCRYP key registers (CRYP_K0...3(L/R)R) . . . . . . . . . . . . . . . . . . . . . 761\n23.6.11\nCRYP initialization vector registers (CRYP_IV0...1(L/R)R) . . . . . . . . . 763\n23.6.12\nCRYP context swap registers (CRYP_CSGCMCCM0..7R and\nCRYP_CSGCM0..7R) for STM32F42xxx and STM32F43xxx . . . . . . . 765\n23.6.13\nCRYP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766\n24\nRandom number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770\n24.1\nRNG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770\n\n\n<>\n\nRM0090 Rev 21\n23/1757\nRM0090\nContents\n39\n24.2\nRNG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770\n24.3\nRNG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770\n24.3.1\nOperation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771\n24.3.2\nError management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771\n24.4\nRNG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771\n24.4.1\nRNG control register (RNG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772\n24.4.2\nRNG status register (RNG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772\n24.4.3\nRNG data register (RNG_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773\n24.4.4\nRNG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774\n25\nHash processor (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775\n25.1\nHASH introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775\n25.2\nHASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775\n25.3\nHASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776\n25.3.1\nDuration of the processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778\n25.3.2\nData type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778\n25.3.3\nMessage digest computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780\n25.3.4\nMessage padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781\n25.3.5\nHash operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782\n25.3.6\nHMAC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782\n25.3.7\nContext swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783\n25.3.8\nHASH interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785\n25.4\nHASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785\n25.4.1\nHASH control register (HASH_CR) for STM32F415/417xx . . . . . . . . . 785\n25.4.2\nHASH control register (HASH_CR) for STM32F43xxx . . . . . . . . . . . . 788\n25.4.3\nHASH data input register (HASH_DIN) . . . . . . . . . . . . . . . . . . . . . . . . 791\n25.4.4\nHASH start register (HASH_STR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792\n25.4.5\nHASH digest registers (HASH_HR0..4/5/6/7) . . . . . . . . . . . . . . . . . . . 793\n25.4.6\nHASH interrupt enable register (HASH_IMR) . . . . . . . . . . . . . . . . . . . 795\n25.4.7\nHASH status register (HASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796\n25.4.8\nHASH context swap registers (HASH_CSRx) . . . . . . . . . . . . . . . . . . . 797\n25.4.9\nHASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798\n26\nReal-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801\n26.1\nIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801\n26.2\nRTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802\n\n\n<>\n\nContents\nRM0090\n24/1757\nRM0090 Rev 21\n26.3\nRTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804\n26.3.1\nClock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804\n26.3.2\nReal-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805\n26.3.3\nProgrammable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805\n26.3.4\nPeriodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805\n26.3.5\nRTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 806\n26.3.6\nReading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808\n26.3.7\nResetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809\n26.3.8\nRTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809\n26.3.9\nRTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810\n26.3.10\nRTC coarse digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811\n26.3.11\nRTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812\n26.3.12\nTimestamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814\n26.3.13\nTamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814\n26.3.14\nCalibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816\n26.3.15\nAlarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816\n26.4\nRTC and low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817\n26.5\nRTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817\n26.6\nRTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819\n26.6.1\nRTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819\n26.6.2\nRTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820\n26.6.3\nRTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821\n26.6.4\nRTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . . 823\n26.6.5\nRTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . . 826\n26.6.6\nRTC wake-up timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . 826\n26.6.7\nRTC calibration register (RTC_CALIBR) . . . . . . . . . . . . . . . . . . . . . . . 827\n26.6.8\nRTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . . 828\n26.6.9\nRTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . . 829\n26.6.10\nRTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . . 830\n26.6.11\nRTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . . 830\n26.6.12\nRTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . . 831\n26.6.13\nRTC time stamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . 831\n26.6.14\nRTC time stamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . . 832\n26.6.15\nRTC timestamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . . 833\n26.6.16\nRTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . . 833\n26.6.17\nRTC tamper and alternate function configuration register\n(RTC_TAFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835\n\n\n<>\n\nRM0090 Rev 21\n25/1757\nRM0090\nContents\n39\n26.6.18\nRTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . . 837\n26.6.19\nRTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . . 838\n26.6.20\nRTC backup registers (RTC_BKPxR) . . . . . . . . . . . . . . . . . . . . . . . . . 839\n26.6.21\nRTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839\n27\nInter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 842\n27.1\nI2C introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842\n27.2\nI2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842\n27.3\nI2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843\n27.3.1\nMode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843\n27.3.2\nI2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846\n27.3.3\nI2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849\n27.3.4\nError conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854\n27.3.5\nProgrammable noise filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855\n27.3.6\nSDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856\n27.3.7\nSMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856\n27.3.8\nDMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859\n27.3.9\nPacket error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860\n27.4\nI2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861\n27.5\nI2C debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863\n27.6\nI2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863\n27.6.1\nI2C Control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863\n27.6.2\nI2C Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865\n27.6.3\nI2C Own address register 1 (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . 867\n27.6.4\nI2C Own address register 2 (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . 867\n27.6.5\nI2C Data register (I2C_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868\n27.6.6\nI2C Status register 1 (I2C_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868\n27.6.7\nI2C Status register 2 (I2C_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871\n27.6.8\nI2C Clock control register (I2C_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . 873\n27.6.9\nI2C TRISE register (I2C_TRISE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874\n27.6.10\nI2C FLTR register (I2C_FLTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874\n27.6.11\nI2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875\n28\nSerial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876\n28.1\nSPI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876\n28.2\nSPI and I2S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877\n\n\n<>\n\nContents\nRM0090\n26/1757\nRM0090 Rev 21\n28.2.1\nSPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877\n28.2.2\nI2S features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878\n28.3\nSPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879\n28.3.1\nGeneral description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879\n28.3.2\nConfiguring the SPI in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 883\n28.3.3\nConfiguring the SPI in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 885\n28.3.4\nConfiguring the SPI for half-duplex communication . . . . . . . . . . . . . . . 887\n28.3.5\nData transmission and reception procedures . . . . . . . . . . . . . . . . . . . 888\n28.3.6\nCRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894\n28.3.7\nStatus flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896\n28.3.8\nDisabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897\n28.3.9\nSPI communication using DMA (direct memory addressing) . . . . . . . . 898\n28.3.10\nError flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900\n28.3.11\nSPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901\n28.4\nI2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902\n28.4.1\nI2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902\n28.4.2\nI2S full duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903\n28.4.3\nSupported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904\n28.4.4\nClock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910\n28.4.5\nI2S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912\n28.4.6\nI2S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914\n28.4.7\nStatus flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916\n28.4.8\nError flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917\n28.4.9\nI2S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918\n28.4.10\nDMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918\n28.5\nSPI and I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919\n28.5.1\nSPI control register 1 (SPI_CR1) (not used in I2S mode) . . . . . . . . . . 919\n28.5.2\nSPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921\n28.5.3\nSPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922\n28.5.4\nSPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923\n28.5.5\nSPI CRC polynomial register (SPI_CRCPR) (not used in I2S\nmode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924\n28.5.6\nSPI RX CRC register (SPI_RXCRCR) (not used in I2S mode) . . . . . . 924\n28.5.7\nSPI TX CRC register (SPI_TXCRCR) (not used in I2S mode) . . . . . . . 925\n28.5.8\nSPI_I2S configuration register (SPI_I2SCFGR) . . . . . . . . . . . . . . . . . . 925\n28.5.9\nSPI_I2S prescaler register (SPI_I2SPR) . . . . . . . . . . . . . . . . . . . . . . . 927\n28.5.10\nSPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928\n\n\n<>\n\nRM0090 Rev 21\n27/1757\nRM0090\nContents\n39\n29\nSerial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929\n29.1\nIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929\n29.2\nMain features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930\n29.3\nFunctional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931\n29.4\nMain SAI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932\n29.5\nSAI synchronization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933\n29.6\nAudio data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933\n29.7\nFrame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933\n29.7.1\nFrame length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934\n29.7.2\nFrame synchronization polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934\n29.7.3\nFrame synchronization active level length . . . . . . . . . . . . . . . . . . . . . . 935\n29.7.4\nFrame synchronization offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935\n29.7.5\nFS signal role . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935\n29.8\nSlot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936\n29.9\nSAI clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938\n29.10 Internal FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939\n29.11 AC’97 link controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942\n29.12 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943\n29.12.1\nMute mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943\n29.12.2\nMONO/STEREO function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943\n29.12.3\nCompanding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944\n29.12.4\nOutput data line management on an inactive slot . . . . . . . . . . . . . . . . 945\n29.13 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947\n29.13.1\nFIFO overrun/underrun (OVRUDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 947\n29.13.2\nAnticipated frame synchronisation detection (AFSDET) . . . . . . . . . . . 949\n29.13.3\nLate frame synchronization detection . . . . . . . . . . . . . . . . . . . . . . . . . 949\n29.13.4\nCodec not ready (CNRDY AC’97) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950\n29.13.5\nWrong clock configuration in master mode (with NODIV = 0) . . . . . . . 950\n29.14 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951\n29.15 Disabling the SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951\n29.16 SAI DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952\n29.17 SAI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953\n29.17.1\nSAI x configuration register 1 (SAI_xCR1) where x is A or B . . . . . . . . 953\n29.17.2\nSAI x configuration register 2 (SAI_xCR2) where x is A or B . . . . . . . . 956\n29.17.3\nSAI x frame configuration register (SAI_XFRCR) where x is A or B . . 958\n\n\n<>\n\nContents\nRM0090\n28/1757\nRM0090 Rev 21\n29.17.4\nSAI x slot register (SAI_xSLOTR) where x is A or B . . . . . . . . . . . . . . 960\n29.17.5\nSAI x interrupt mask register (SAI_xIM) where x is A or B . . . . . . . . . . 961\n29.17.6\nSAI x status register (SAI_xSR) where x is A or B . . . . . . . . . . . . . . . . 963\n29.17.7\nSAI x clear flag register (SAI_xCLRFR) where X is A or B . . . . . . . . . 965\n29.17.8\nSAI x data register (SAI_xDR) where x is A or B . . . . . . . . . . . . . . . . . 966\n29.17.9\nSAI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966\n30\nUniversal synchronous asynchronous receiver\ntransmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968\n30.1\nUSART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968\n30.2\nUSART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968\n30.3\nUSART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969\n30.3.1\nUSART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972\n30.3.2\nTransmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973\n30.3.3\nReceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976\n30.3.4\nFractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981\n30.3.5\nUSART receiver tolerance to clock deviation . . . . . . . . . . . . . . . . . . . . 991\n30.3.6\nMultiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992\n30.3.7\nParity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994\n30.3.8\nLIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 995\n30.3.9\nUSART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997\n30.3.10\nSingle-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 999\n30.3.11\nSmartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000\n30.3.12\nIrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002\n30.3.13\nContinuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . 1004\n30.3.14\nHardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006\n30.4\nUSART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009\n30.5\nUSART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010\n30.6\nUSART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010\n30.6.1\nStatus register (USART_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010\n30.6.2\nData register (USART_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013\n30.6.3\nBaud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013\n30.6.4\nControl register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013\n30.6.5\nControl register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016\n30.6.6\nControl register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017\n30.6.7\nGuard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . 1020\n30.6.8\nUSART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021\n\n\n<>\n\nRM0090 Rev 21\n29/1757\nRM0090\nContents\n39\n31\nSecure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . 1022\n31.1\nSDIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022\n31.2\nSDIO bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023\n31.3\nSDIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025\n31.3.1\nSDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026\n31.3.2\nSDIO APB2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036\n31.4\nCard functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037\n31.4.1\nCard identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037\n31.4.2\nCard reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037\n31.4.3\nOperating voltage range validation . . . . . . . . . . . . . . . . . . . . . . . . . . 1037\n31.4.4\nCard identification process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038\n31.4.5\nBlock write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039\n31.4.6\nBlock read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040\n31.4.7\nStream access, stream write and stream read \n(MultiMediaCard only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040\n31.4.8\nErase: group erase and sector erase . . . . . . . . . . . . . . . . . . . . . . . . 1042\n31.4.9\nWide bus selection or deselection . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042\n31.4.10\nProtection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042\n31.4.11\nCard status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045\n31.4.12\nSD status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048\n31.4.13\nSD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052\n31.4.14\nCommands and responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053\n31.5\nResponse formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057\n31.5.1\nR1 (normal response command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057\n31.5.2\nR1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057\n31.5.3\nR2 (CID, CSD register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057\n31.5.4\nR3 (OCR register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058\n31.5.5\nR4 (Fast I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058\n31.5.6\nR4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059\n31.5.7\nR5 (interrupt request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059\n31.5.8\nR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060\n31.6\nSDIO I/O card-specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060\n31.6.1\nSDIO I/O read wait operation by SDIO_D2 signaling . . . . . . . . . . . . 1061\n31.6.2\nSDIO read wait operation by stopping SDIO_CK . . . . . . . . . . . . . . . 1061\n31.6.3\nSDIO suspend/resume operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061\n31.6.4\nSDIO interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061\n\n\n<>\n\nContents\nRM0090\n30/1757\nRM0090 Rev 21\n31.7\nCE-ATA specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062\n31.7.1\nCommand completion signal disable . . . . . . . . . . . . . . . . . . . . . . . . . 1062\n31.7.2\nCommand completion signal enable . . . . . . . . . . . . . . . . . . . . . . . . . 1062\n31.7.3\nCE-ATA interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062\n31.7.4\nAborting CMD61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062\n31.8\nHW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063\n31.9\nSDIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063\n31.9.1\nSDIO power control register (SDIO_POWER) . . . . . . . . . . . . . . . . . . 1063\n31.9.2\nSDI clock control register (SDIO_CLKCR) . . . . . . . . . . . . . . . . . . . . 1064\n31.9.3\nSDIO argument register (SDIO_ARG) . . . . . . . . . . . . . . . . . . . . . . . . 1065\n31.9.4\nSDIO command register (SDIO_CMD) . . . . . . . . . . . . . . . . . . . . . . . 1065\n31.9.5\nSDIO command response register (SDIO_RESPCMD) . . . . . . . . . . 1066\n31.9.6\nSDIO response 1..4 register (SDIO_RESPx) . . . . . . . . . . . . . . . . . . 1067\n31.9.7\nSDIO data timer register (SDIO_DTIMER) . . . . . . . . . . . . . . . . . . . . 1067\n31.9.8\nSDIO data length register (SDIO_DLEN) . . . . . . . . . . . . . . . . . . . . . 1068\n31.9.9\nSDIO data control register (SDIO_DCTRL) . . . . . . . . . . . . . . . . . . . . 1069\n31.9.10\nSDIO data counter register (SDIO_DCOUNT) . . . . . . . . . . . . . . . . . 1070\n31.9.11\nSDIO status register (SDIO_STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071\n31.9.12\nSDIO interrupt clear register (SDIO_ICR) . . . . . . . . . . . . . . . . . . . . . 1072\n31.9.13\nSDIO mask register (SDIO_MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . 1074\n31.9.14\nSDIO FIFO counter register (SDIO_FIFOCNT) . . . . . . . . . . . . . . . . . 1076\n31.9.15\nSDIO data FIFO register (SDIO_FIFO) . . . . . . . . . . . . . . . . . . . . . . . 1077\n31.9.16\nSDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077\n32\nController area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079\n32.1\nbxCAN introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079\n32.2\nbxCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079\n32.3\nbxCAN general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080\n32.3.1\nCAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080\n32.3.2\nControl, status and configuration registers . . . . . . . . . . . . . . . . . . . . 1081\n32.3.3\nTx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081\n32.3.4\nAcceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081\n32.4\nbxCAN operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082\n32.4.1\nInitialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083\n32.4.2\nNormal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083\n32.4.3\nSleep mode (low-power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083\n\n\n<>\n\nRM0090 Rev 21\n31/1757\nRM0090\nContents\n39\n32.5\nTest mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084\n32.5.1\nSilent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084\n32.5.2\nLoop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085\n32.5.3\nLoop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . 1085\n32.6\nDebug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086\n32.7\nbxCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086\n32.7.1\nTransmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086\n32.7.2\nTime triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 1088\n32.7.3\nReception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088\n32.7.4\nIdentifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090\n32.7.5\nMessage storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094\n32.7.6\nError management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096\n32.7.7\nBit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096\n32.8\nbxCAN interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098\n32.9\nCAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1100\n32.9.1\nRegister access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100\n32.9.2\nCAN control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100\n32.9.3\nCAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110\n32.9.4\nCAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117\n32.9.5\nbxCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121\n33\nEthernet (ETH): media access control (MAC) with\nDMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125\n33.1\nEthernet introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1125\n33.2\nEthernet main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1125\n33.2.1\nMAC core features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126\n33.2.2\nDMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127\n33.2.3\nPTP features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127\n33.3\nEthernet pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1128\n33.4\nEthernet functional description: SMI, MII and RMII . . . . . . . . . . . . . . . .1129\n33.4.1\nStation management interface: SMI . . . . . . . . . . . . . . . . . . . . . . . . . 1129\n33.4.2\nMedia-independent interface: MII . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132\n33.4.3\nReduced media-independent interface: RMII . . . . . . . . . . . . . . . . . . 1134\n33.4.4\nMII/RMII selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135\n33.5\nEthernet functional description: MAC 802.3 . . . . . . . . . . . . . . . . . . . . . .1136\n33.5.1\nMAC 802.3 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137\n\n\n<>\n\nContents\nRM0090\n32/1757\nRM0090 Rev 21\n33.5.2\nMAC frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140\n33.5.3\nMAC frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147\n33.5.4\nMAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152\n33.5.5\nMAC filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153\n33.5.6\nMAC loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1156\n33.5.7\nMAC management counters: MMC . . . . . . . . . . . . . . . . . . . . . . . . . . 1156\n33.5.8\nPower management: PMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1157\n33.5.9\nPrecision time protocol (IEEE1588 PTP) . . . . . . . . . . . . . . . . . . . . . . 1160\n33.6\nEthernet functional description: DMA controller operation . . . . . . . . . . .1166\n33.6.1\nInitialization of a transfer using DMA . . . . . . . . . . . . . . . . . . . . . . . . . 1167\n33.6.2\nHost bus burst access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167\n33.6.3\nHost data buffer alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168\n33.6.4\nBuffer size calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168\n33.6.5\nDMA arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169\n33.6.6\nError response to DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169\n33.6.7\nTx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169\n33.6.8\nRx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181\n33.6.9\nDMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192\n33.7\nEthernet interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1193\n33.8\nEthernet register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1194\n33.8.1\nMAC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194\n33.8.2\nMMC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213\n33.8.3\nIEEE 1588 time stamp registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218\n33.8.4\nDMA register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226\n33.8.5\nEthernet register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239\n34\nUSB on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . . . . . . . . . . 1243\n34.1\nOTG_FS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243\n34.2\nOTG_FS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1244\n34.2.1\nGeneral features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1244\n34.2.2\nHost-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245\n34.2.3\nPeripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245\n34.3\nOTG_FS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246\n34.3.1\nOTG pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246\n34.3.2\nOTG full-speed core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246\n34.3.3\nFull-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1247\n\n\n<>\n\nRM0090 Rev 21\n33/1757\nRM0090\nContents\n39\n34.4\nOTG dual role device (DRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248\n34.4.1\nID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248\n34.4.2\nHNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248\n34.4.3\nSRP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249\n34.5\nUSB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249\n34.5.1\nSRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250\n34.5.2\nPeripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250\n34.5.3\nPeripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251\n34.6\nUSB host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253\n34.6.1\nSRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254\n34.6.2\nUSB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254\n34.6.3\nHost channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256\n34.6.4\nHost scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257\n34.7\nSOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258\n34.7.1\nHost SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258\n34.7.2\nPeripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259\n34.8\nOTG low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259\n34.9\nDynamic update of the OTG_FS_HFIR register . . . . . . . . . . . . . . . . . . 1260\n34.10 USB data FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261\n34.11 Peripheral FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262\n34.11.1\nPeripheral Rx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262\n34.11.2\nPeripheral Tx FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263\n34.12 Host FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263\n34.12.1\nHost Rx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263\n34.12.2\nHost Tx FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264\n34.13 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264\n34.13.1\nDevice mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264\n34.13.2\nHost mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265\n34.14 USB system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265\n34.15 OTG_FS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266\n34.16 OTG_FS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . 1268\n34.16.1\nCSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269\n34.16.2\nOTG_FS global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274\n34.16.3\nHost-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295\n34.16.4\nDevice-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305\n\n\n<>\n\nContents\nRM0090\n34/1757\nRM0090 Rev 21\n34.16.5\nOTG_FS power and clock gating control register\n(OTG_FS_PCGCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1328\n34.16.6\nOTG_FS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1329\n34.17 OTG_FS programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1338\n34.17.1\nCore initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1338\n34.17.2\nHost initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1339\n34.17.3\nDevice initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1339\n34.17.4\nHost programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1340\n34.17.5\nDevice programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356\n34.17.6\nOperational model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358\n34.17.7\nWorst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1376\n34.17.8\nOTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377\n35\nUSB on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . . . . . . . . . . 1384\n35.1\nOTG_HS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384\n35.2\nOTG_HS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384\n35.2.1\nGeneral features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385\n35.2.2\nHost-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386\n35.2.3\nPeripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386\n35.3\nOTG_HS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386\n35.3.1\nOTG pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387\n35.3.2\nHigh-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387\n35.3.3\nEmbedded Full-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388\n35.4\nOTG dual-role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388\n35.4.1\nID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388\n35.4.2\nHNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388\n35.4.3\nSRP dual-role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1389\n35.5\nUSB functional description in peripheral mode . . . . . . . . . . . . . . . . . . 1389\n35.5.1\nSRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1389\n35.5.2\nPeripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1390\n35.5.3\nPeripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1391\n35.6\nUSB functional description on host mode . . . . . . . . . . . . . . . . . . . . . . 1394\n35.6.1\nSRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394\n35.6.2\nUSB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395\n35.6.3\nHost channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396\n35.6.4\nHost scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1398\n\n\n<>\n\nRM0090 Rev 21\n35/1757\nRM0090\nContents\n39\n35.7\nSOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399\n35.7.1\nHost SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399\n35.7.2\nPeripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399\n35.8\nOTG_HS low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400\n35.9\nDynamic update of the OTG_HS_HFIR register . . . . . . . . . . . . . . . . . 1401\n35.10 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402\n35.10.1\nPeripheral mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402\n35.10.2\nHost mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402\n35.11 OTG_HS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1403\n35.12 OTG_HS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . 1405\n35.12.1\nCSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1405\n35.12.2\nOTG_HS global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410\n35.12.3\nHost-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433\n35.12.4\nDevice-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446\n35.12.5\nOTG_HS power and clock gating control register\n(OTG_HS_PCGCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475\n35.12.6\nOTG_HS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475\n35.13 OTG_HS programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490\n35.13.1\nCore initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490\n35.13.2\nHost initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491\n35.13.3\nDevice initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492\n35.13.4\nDMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492\n35.13.5\nHost programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492\n35.13.6\nDevice programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518\n35.13.7\nOperational model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520\n35.13.8\nWorst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1539\n35.13.9\nOTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541\n36\nFlexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . 1547\n36.1\nFSMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547\n36.2\nBlock diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1548\n36.3\nAHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1548\n36.3.1\nSupported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 1549\n36.4\nExternal device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1550\n36.4.1\nNOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1550\n36.4.2\nNAND/PC Card address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551\n\n\n<>\n\nContents\nRM0090\n36/1757\nRM0090 Rev 21\n36.5\nNOR flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1552\n36.5.1\nExternal memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1553\n36.5.2\nSupported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 1555\n36.5.3\nGeneral timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1556\n36.5.4\nNOR flash/PSRAM controller asynchronous transactions . . . . . . . . . 1557\n36.5.5\nSynchronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1574\n36.5.6\nNOR/PSRAM control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1580\n36.6\nNAND Flash/PC Card controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1587\n36.6.1\nExternal memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588\n36.6.2\nNAND Flash / PC Card supported memories and transactions . . . . . 1590\n36.6.3\nTiming diagrams for NAND and PC Card . . . . . . . . . . . . . . . . . . . . . 1590\n36.6.4\nNAND Flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1591\n36.6.5\nNAND Flash prewait functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . 1592\n36.6.6\nComputation of the error correction code (ECC)\nin NAND Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1593\n36.6.7\nPC Card/CompactFlash operations . . . . . . . . . . . . . . . . . . . . . . . . . . 1594\n36.6.8\nNAND Flash/PC Card control registers . . . . . . . . . . . . . . . . . . . . . . . 1596\n36.6.9\nFSMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603\n37\nFlexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605\n37.1\nFMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605\n37.2\nBlock diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606\n37.3\nAHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607\n37.3.1\nSupported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 1608\n37.4\nExternal device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609\n37.4.1\nNOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610\n37.4.2\nNAND Flash memory/PC Card address mapping . . . . . . . . . . . . . . . 1611\n37.4.3\nSDRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612\n37.5\nNOR Flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1615\n37.5.1\nExternal memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1616\n37.5.2\nSupported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 1618\n37.5.3\nGeneral timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1620\n37.5.4\nNOR Flash/PSRAM controller asynchronous transactions . . . . . . . . 1620\n37.5.5\nSynchronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1637\n37.5.6\nNOR/PSRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643\n37.6\nNAND Flash/PC Card controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650\n37.6.1\nExternal memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651\n\n\n<>\n\nRM0090 Rev 21\n37/1757\nRM0090\nContents\n39\n37.6.2\nNAND Flash / PC Card supported memories and transactions . . . . . 1653\n37.6.3\nTiming diagrams for NAND Flash memory and PC Card . . . . . . . . . 1653\n37.6.4\nNAND Flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654\n37.6.5\nNAND Flash prewait functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655\n37.6.6\nComputation of the error correction code (ECC) \nin NAND Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656\n37.6.7\nPC Card/CompactFlash operations . . . . . . . . . . . . . . . . . . . . . . . . . . 1657\n37.6.8\nNAND Flash/PC Card controller registers . . . . . . . . . . . . . . . . . . . . . 1659\n37.7\nSDRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666\n37.7.1\nSDRAM controller main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666\n37.7.2\nSDRAM External memory interface signals . . . . . . . . . . . . . . . . . . . . 1666\n37.7.3\nSDRAM controller functional description . . . . . . . . . . . . . . . . . . . . . . 1667\n37.7.4\nLow power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674\n37.7.5\nSDRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1677\n37.8\nFMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1683\n38\nDebug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1686\n38.1\nOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1686\n38.2\nReference Arm® documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1687\n38.3\nSWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . 1687\n38.3.1\nMechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . 1688\n38.4\nPinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1688\n38.4.1\nSWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689\n38.4.2\nFlexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689\n38.4.3\nInternal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . 1689\n38.4.4\nUsing serial wire and releasing the unused debug pins as GPIOs . . 1691\n38.5\nSTM32F4xx JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 1691\n38.6\nID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693\n38.6.1\nMCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693\n38.6.2\nBoundary scan TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1694\n38.6.3\nCortex®-M4 with FPU TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1694\n38.6.4\nCortex®-M4 with FPU JEDEC-106 ID code . . . . . . . . . . . . . . . . . . . . 1694\n38.7\nJTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1694\n38.8\nSW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696\n38.8.1\nSW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696\n38.8.2\nSW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696\n\n\n<>\n\nContents\nRM0090\n38/1757\nRM0090 Rev 21\n38.8.3\nSW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . 1697\n38.8.4\nDP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697\n38.8.5\nSW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698\n38.8.6\nSW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698\n38.9\nAHB-AP (AHB access port) - valid for both JTAG-DP\nand SW-DP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699\n38.10 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700\n38.11 Capability of the debugger host to connect under system reset . . . . . 1701\n38.12 FPB (Flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1701\n38.13 DWT (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702\n38.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . 1702\n38.14.1\nGeneral description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702\n38.14.2\nTime stamp packets, synchronization and overflow packets . . . . . . . 1702\n38.15 ETM (Embedded Trace Macrocell™) . . . . . . . . . . . . . . . . . . . . . . . . . . 1704\n38.15.1\nETM general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704\n38.15.2\nETM signal protocol and packet types . . . . . . . . . . . . . . . . . . . . . . . . 1704\n38.15.3\nMain ETM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705\n38.15.4\nETM configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705\n38.16 MCU debug component (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . . 1705\n38.16.1\nDebug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 1705\n38.16.2\nDebug support for timers, watchdog, bxCAN and I2C . . . . . . . . . . . . 1706\n38.16.3\nDebug MCU configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 1706\n38.16.4\nDebug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . . . . . 1708\n38.16.5\nDebug MCU APB2 Freeze register (DBGMCU_APB2_FZ) . . . . . . . . 1709\n38.17 TPIU (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710\n38.17.1\nIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710\n38.17.2\nTRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711\n38.17.3\nTPUI formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712\n38.17.4\nTPUI frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . 1713\n38.17.5\nTransmission of the synchronization frame packet . . . . . . . . . . . . . . 1713\n38.17.6\nSynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713\n38.17.7\nAsynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714\n38.17.8\nTRACECLKIN connection inside the STM32F4xx . . . . . . . . . . . . . . . 1714\n38.17.9\nTPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714\n38.17.10 Example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715\n38.18 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1716\n\n\n<>\n\nRM0090 Rev 21\n39/1757\nRM0090\nContents\n39\n39\nDevice electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1717\n39.1\nUnique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1717\n39.2\nFlash size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718\n40\nImportant security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719\n41\nRevision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720\n\n\n<>\n\nList of tables\nRM0090\n40/1757\nRM0090 Rev 21\nList of tables\nTable 1.\nSTM32F4xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64\nTable 2.\nBoot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69\nTable 3.\nMemory mapping vs. Boot mode/physical remap\nin STM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71\nTable 4.\nMemory mapping vs. Boot mode/physical remap\nin STM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71\nTable 5.\nFlash module organization (STM32F40x and STM32F41x) . . . . . . . . . . . . . . . . . . . . . . . . 75\nTable 6.\nFlash module - 2 Mbyte dual bank organization (STM32F42xxx and STM32F43xxx) . . . . 77\nTable 7.\n1 Mbyte flash memory single bank vs dual bank organization\n (STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78\nTable 8.\n1 Mbyte single bank flash memory organization\n(STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78\nTable 9.\n1 Mbyte dual bank flash memory organization (STM32F42xxx and STM32F43xxx) . . . . . 79\nTable 10.\n512 Kbyte single bank flash memory organization\n(STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80\nTable 11.\nNumber of wait states according to CPU clock (HCLK) frequency \n(STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81\nTable 12.\nNumber of wait states according to CPU clock (HCLK) frequency\n (STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81\nTable 13.\nMaximum program/erase parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85\nTable 14.\nFlash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88\nTable 15.\nOption byte organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88\nTable 16.\nDescription of the option bytes (STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . 89\nTable 17.\nDescription of the option bytes \n(STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90\nTable 18.\nAccess versus read protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95\nTable 19.\nOTP area organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98\nTable 20.\nFlash register map and reset values\n(STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112\nTable 21.\nFlash register map and reset values (STM32F42xxx and STM32F43xxx). . . . . . . . . . . . 112\nTable 22.\nCRC calculation unit register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116\nTable 23.\nVoltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . 123\nTable 24.\nLow-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129\nTable 25.\nSleep-now entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130\nTable 26.\nSleep-on-exit entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131\nTable 27.\nStop operating modes\n(STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132\nTable 28.\nStop mode entry and exit (for STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . . 133\nTable 29.\nStop operating modes (STM32F42xxx and STM32F43xxx). . . . . . . . . . . . . . . . . . . . . . . 135\nTable 30.\nStop mode entry and exit (STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . . . . 137\nTable 31.\nStandby mode entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138\nTable 32.\nPWR - register map and reset values for\nSTM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151\nTable 33.\nPWR - register map and reset values for STM32F42xxx and STM32F43xxx . . . . . . . . . 151\nTable 34.\nRCC register map and reset values for STM32F42xxx and STM32F43xxx . . . . . . . . . . . 212\nTable 35.\nRCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267\nTable 36.\nPort bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271\nTable 37.\nFlexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274\n\n\n<>\n\nRM0090 Rev 21\n41/1757\nRM0090\nList of tables\n46\nTable 38.\nRTC_AF1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282\nTable 39.\nRTC_AF2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283\nTable 40.\nGPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290\nTable 41.\nSYSCFG register map and reset values\n(STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297\nTable 42.\nSYSCFG register map and reset values (STM32F42xxx and STM32F43xxx). . . . . . . . . 304\nTable 43.\nDMA1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310\nTable 44.\nDMA2 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311\nTable 45.\nSource and destination address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312\nTable 46.\nSource and destination address registers in Double buffer mode (DBM=1). . . . . . . . . . . 317\nTable 47.\nPacking/unpacking & endian behavior (bit PINC = MINC = 1) . . . . . . . . . . . . . . . . . . . . . 318\nTable 48.\nRestriction on NDT versus PSIZE and MSIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319\nTable 49.\nFIFO threshold configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321\nTable 50.\nPossible DMA configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325\nTable 51.\nDMA interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327\nTable 52.\nDMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338\nTable 53.\nSupported color mode in input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345\nTable 54.\nData order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346\nTable 55.\nAlpha mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347\nTable 56.\nSupported CLUT color mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348\nTable 57.\nCLUT data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348\nTable 58.\nSupported color mode in output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349\nTable 59.\nData order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349\nTable 60.\nDMA2D interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354\nTable 61.\nDMA2D register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372\nTable 62.\nVector table for STM32F405xx/07xx and STM32F415xx/17xx. . . . . . . . . . . . . . . . . . . . . 375\nTable 63.\nVector table for STM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378\nTable 64.\nExternal interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 390\nTable 65.\nExternal interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 390\nTable 66.\nADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393\nTable 67.\nAnalog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396\nTable 68.\nConfiguring the trigger polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400\nTable 69.\nExternal trigger for regular channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401\nTable 70.\nExternal trigger for injected channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402\nTable 71.\nADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417\nTable 72.\nADC global register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433\nTable 73.\nADC register map and reset values for each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434\nTable 74.\nADC register map and reset values (common ADC registers) . . . . . . . . . . . . . . . . . . . . . 435\nTable 75.\nDAC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437\nTable 76.\nExternal triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440\nTable 77.\nDAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456\nTable 78.\nDCMI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458\nTable 79.\nDCMI signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460\nTable 80.\nPositioning of captured data bytes in 32-bit words (8-bit width) . . . . . . . . . . . . . . . . . . . . 461\nTable 81.\nPositioning of captured data bytes in 32-bit words (10-bit width) . . . . . . . . . . . . . . . . . . . 461\nTable 82.\nPositioning of captured data bytes in 32-bit words (12-bit width) . . . . . . . . . . . . . . . . . . . 462\nTable 83.\nPositioning of captured data bytes in 32-bit words (14-bit width) . . . . . . . . . . . . . . . . . . . 462\nTable 84.\nData storage in monochrome progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . 469\nTable 85.\nData storage in RGB progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469\nTable 86.\nData storage in YCbCr progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470\nTable 87.\nDCMI interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470\nTable 88.\nDCMI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481\n\n\n<>\n\nList of tables\nRM0090\n42/1757\nRM0090 Rev 21\nTable 89.\nLTDC registers versus clock domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485\nTable 90.\nLCD-TFT pins and signal interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486\nTable 91.\nPixel Data mapping versus Color Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490\nTable 92.\nLTDC interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494\nTable 93.\nLTDC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515\nTable 94.\nCounting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556\nTable 95.\nTIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570\nTable 96.\nOutput control bits for complementary OCx and OCxN channels with\nbreak feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582\nTable 97.\nTIM1 and TIM8 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590\nTable 98.\nCounting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619\nTable 99.\nTIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635\nTable 100.\nOutput control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644\nTable 101.\nTIM2 to TIM5 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651\nTable 102.\nTIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677\nTable 103.\nOutput control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685\nTable 104.\nTIM9/12 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687\nTable 105.\nOutput control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694\nTable 106.\nTIM10/11/13/14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697\nTable 107.\nTIM6 and TIM7 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710\nTable 108.\nMin/max IWDG timeout period (in ms) at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . 712\nTable 109.\nIWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715\nTable 110.\nMinimum and maximum timeout values at 30 MHz (fPCLK1). . . . . . . . . . . . . . . . . . . . . . . 719\nTable 111.\nWWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722\nTable 112.\nNumber of cycles required to process each 128-bit block\n(STM32F415/417xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723\nTable 113.\nNumber of cycles required to process each 128-bit block\n(STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723\nTable 114.\nData types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743\nTable 115.\nCRYP register map and reset values for STM32F415/417xx. . . . . . . . . . . . . . . . . . . . . . 766\nTable 116.\nCRYP register map and reset values for STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . 767\nTable 117.\nRNG register map and reset map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774\nTable 118.\nHASH register map and reset values on STM32F415/417xx . . . . . . . . . . . . . . . . . . . . . . 798\nTable 119.\nHASH register map and reset values on STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . 799\nTable 120.\nEffect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817\nTable 121.\nInterrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818\nTable 122.\nRTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839\nTable 123.\nMaximum DNF[3:0] value to be compliant with Thd:dat(max) . . . . . . . . . . . . . . . . . . . . . 855\nTable 124.\nSMBus vs. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857\nTable 125.\nI2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861\nTable 126.\nI2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875\nTable 127.\nSPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901\nTable 128.\nAudio frequency precision (for PLLM VCO = 1 MHz or 2 MHz) . . . . . . . . . . . . . . . . . . . . 912\nTable 129.\nI2S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918\nTable 130.\nSPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928\nTable 131.\nExample of possible audio frequency sampling range . . . . . . . . . . . . . . . . . . . . . . . . . . . 939\nTable 132.\nInterrupt sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951\nTable 133.\nSAI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966\nTable 134.\nNoise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980\nTable 135.\nError calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 12 MHz,\noversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983\nTable 136.\nError calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK =12 MHz,\n\n\n<>\n\nRM0090 Rev 21\n43/1757\nRM0090\nList of tables\n46\noversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984\nTable 137.\nError calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz,\noversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984\nTable 138.\nError calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz,\noversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985\nTable 139.\nError calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,\noversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986\nTable 140.\nError calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,\noversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986\nTable 141.\nError calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,\noversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987\nTable 142.\nError calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,\noversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988\nTable 143.\nError calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 Hz,\noversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989\nTable 144.\nError calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 MHz,\noversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990\nTable 145.\nUSART receiver’s tolerance when DIV fraction is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991\nTable 146.\nUSART receiver tolerance when DIV_Fraction is different from 0 . . . . . . . . . . . . . . . . . . 992\nTable 147.\nFrame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994\nTable 148.\nUSART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009\nTable 149.\nUSART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010\nTable 150.\nUSART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021\nTable 151.\nSDIO I/O definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026\nTable 152.\nCommand format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030\nTable 153.\nShort response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031\nTable 154.\nLong response format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031\nTable 155.\nCommand path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031\nTable 156.\nData token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034\nTable 157.\nTransmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035\nTable 158.\nReceive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036\nTable 159.\nCard status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046\nTable 160.\nSD status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049\nTable 161.\nSpeed class code field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050\nTable 162.\nPerformance move field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050\nTable 163.\nAU_SIZE field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051\nTable 164.\nMaximum AU size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051\nTable 165.\nErase size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051\nTable 166.\nErase timeout field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052\nTable 167.\nErase offset field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052\nTable 168.\nBlock-oriented write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054\nTable 169.\nBlock-oriented write protection commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055\nTable 170.\nErase commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055\nTable 171.\nI/O mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056\nTable 172.\nLock card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056\nTable 173.\nApplication-specific commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056\nTable 174.\nR1 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057\nTable 175.\nR2 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058\nTable 176.\nR3 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058\nTable 177.\nR4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058\nTable 178.\nR4b response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059\nTable 179.\nR5 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059\n\n\n<>\n\nList of tables\nRM0090\n44/1757\nRM0090 Rev 21\nTable 180.\nR6 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060\nTable 181.\nResponse type and SDIO_RESPx registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067\nTable 182.\nSDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077\nTable 183.\nTransmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094\nTable 184.\nReceive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094\nTable 185.\nbxCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121\nTable 186.\nAlternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128\nTable 187.\nManagement frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130\nTable 188.\nClock range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132\nTable 189.\nTX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133\nTable 190.\nRX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134\nTable 191.\nFrame statuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149\nTable 192.\nDestination address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155\nTable 193.\nSource address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1156\nTable 194.\nReceive descriptor 0 - encoding for bits 7, 5 and 0 (normal descriptor\nformat only, EDFE=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187\nTable 195.\nTime stamp snapshot dependency on registers bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220\nTable 196.\nEthernet register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239\nTable 197.\nOTG_FS input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246\nTable 198.\nCompatibility of STM32 low power modes with the OTG . . . . . . . . . . . . . . . . . . . . . . . . 1259\nTable 199.\nCore global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269\nTable 200.\nHost-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270\nTable 201.\nDevice-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271\nTable 202.\nData FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272\nTable 203.\nPower and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273\nTable 204.\nTRDT values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279\nTable 205.\nMinimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307\nTable 206.\nOTG_FS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1329\nTable 207.\nOTG_HS input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387\nTable 208.\nCompatibility of STM32 low power modes with the OTG . . . . . . . . . . . . . . . . . . . . . . . . 1400\nTable 209.\nCore global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406\nTable 210.\nHost-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407\nTable 211.\nDevice-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408\nTable 212.\nData FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410\nTable 213.\nPower and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410\nTable 214.\nTRDT values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417\nTable 215.\nMinimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1449\nTable 216.\nOTG_HS register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475\nTable 217.\nNOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551\nTable 218.\nExternal memory address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551\nTable 219.\nMemory mapping and timing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551\nTable 220.\nNAND bank selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1552\nTable 221.\nProgrammable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1553\nTable 222.\nNonmultiplexed I/O NOR flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1553\nTable 223.\nMultiplexed I/O NOR flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1554\nTable 224.\nNonmultiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1554\nTable 225.\nMultiplexed I/O PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1555\nTable 226.\nNOR flash/PSRAM controller: example of supported memories and transactions. . . . . 1555\nTable 227.\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558\nTable 228.\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559\nTable 229.\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560\nTable 230.\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561\n\n\n<>\n\nRM0090 Rev 21\n45/1757\nRM0090\nList of tables\n46\nTable 231.\nFSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561\nTable 232.\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563\nTable 233.\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564\nTable 234.\nFSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564\nTable 235.\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566\nTable 236.\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566\nTable 237.\nFSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1567\nTable 238.\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1568\nTable 239.\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1569\nTable 240.\nFSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1569\nTable 241.\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571\nTable 242.\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571\nTable 243.\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1576\nTable 244.\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577\nTable 245.\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1578\nTable 246.\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1579\nTable 247.\nProgrammable NAND/PC Card access parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588\nTable 248.\n8-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588\nTable 249.\n16-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1589\nTable 250.\n16-bit PC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1589\nTable 251.\nSupported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1590\nTable 252.\n16-bit PC-Card signals and access type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1595\nTable 253.\nECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1602\nTable 254.\nFSMC register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603\nTable 255.\nNOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610\nTable 256.\nNOR/PSRAM External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1611\nTable 257.\nNAND/PC Card memory mapping and timing registers . . . . . . . . . . . . . . . . . . . . . . . . . 1611\nTable 258.\nNAND bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612\nTable 259.\nSDRAM bank selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612\nTable 260.\nSDRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612\nTable 261.\nSDRAM address mapping with 8-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613\nTable 262.\nSDRAM address mapping with 16-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . 1614\nTable 263.\nSDRAM address mapping with 32-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . 1614\nTable 264.\nProgrammable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1616\nTable 265.\nNon-multiplexed I/O NOR Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617\nTable 266.\n16-bit multiplexed I/O NOR Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617\nTable 267.\nNon-multiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617\nTable 268.\n16-Bit multiplexed I/O PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1618\nTable 269.\nNOR Flash/PSRAM: Example of supported memories and transactions . . . . . . . . . . . . 1619\nTable 270.\nFMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622\nTable 271.\nFMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622\nTable 272.\nFMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624\nTable 273.\nFMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1625\nTable 274.\nFMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1625\nTable 275.\nFMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627\nTable 276.\nFMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628\nTable 277.\nFMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628\nTable 278.\nFMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1630\nTable 279.\nFMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1630\nTable 280.\nFMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631\nTable 281.\nFMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632\nTable 282.\nFMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633\n\n\n<>\n\nList of tables\nRM0090\n46/1757\nRM0090 Rev 21\nTable 283.\nFMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633\nTable 284.\nFMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635\nTable 285.\nFMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635\nTable 286.\nFMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640\nTable 287.\nFMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640\nTable 288.\nFMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641\nTable 289.\nFMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642\nTable 290.\nProgrammable NAND Flash/PC Card access parameters . . . . . . . . . . . . . . . . . . . . . . . 1651\nTable 291.\n8-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651\nTable 292.\n16-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652\nTable 293.\n16-bit PC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652\nTable 294.\nSupported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653\nTable 295.\n16-bit PC-Card signals and access type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658\nTable 296.\nECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665\nTable 297.\nSDRAM signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666\nTable 298.\nFMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1683\nTable 299.\nSWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689\nTable 300.\nFlexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689\nTable 301.\nJTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1694\nTable 302.\n32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . 1695\nTable 303.\nPacket request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696\nTable 304.\nACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697\nTable 305.\nDATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697\nTable 306.\nSW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698\nTable 307.\n Cortex®-M4 with FPU AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699\nTable 308.\nCore debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700\nTable 309.\nMain ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703\nTable 310.\nMain ETM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705\nTable 311.\nAsynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711\nTable 312.\nSynchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711\nTable 313.\nFlexible TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712\nTable 314.\nImportant TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714\nTable 315.\nDBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1716\nTable 316.\nDocument revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720\n\n\n<>\n\nRM0090 Rev 21\n47/1757\nRM0090\nList of figures\n56\nList of figures\nFigure 1.\nSystem architecture for STM32F405xx/07xx and STM32F415xx/17xx devices. . . . . . . . . 60\nFigure 2.\nSystem architecture for STM32F42xxx and STM32F43xxx devices . . . . . . . . . . . . . . . . . 62\nFigure 3.\nFlash memory interface connection inside system architecture\n (STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73\nFigure 4.\nFlash memory interface connection inside system architecture\n(STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74\nFigure 5.\nSequential 32-bit instruction execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83\nFigure 6.\nRDP levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95\nFigure 7.\nPCROP levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97\nFigure 8.\nCRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114\nFigure 9.\nPower supply overview for STM32F405xx/07xx and STM32F415xx/17xx. . . . . . . . . . . . 117\nFigure 10.\nPower supply overview for STM32F42xxx and STM32F43xxx. . . . . . . . . . . . . . . . . . . . . 118\nFigure 11.\nBackup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121\nFigure 12.\nPower-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125\nFigure 13.\nBOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126\nFigure 14.\nPVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127\nFigure 15.\nSimplified diagram of the reset circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153\nFigure 16.\nClock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154\nFigure 17.\nHSE/ LSE clock sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156\nFigure 18.\nFrequency measurement with TIM5 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . . 161\nFigure 19.\nFrequency measurement with TIM11 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . 162\nFigure 20.\nSimplified diagram of the reset circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216\nFigure 21.\nClock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218\nFigure 22.\nHSE/ LSE clock sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220\nFigure 23.\nFrequency measurement with TIM5 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . . 225\nFigure 24.\nFrequency measurement with TIM11 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . 225\nFigure 25.\nBasic structure of a five-volt tolerant I/O port bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271\nFigure 26.\nSelecting an alternate function on STM32F405xx/07xx and STM32F415xx/17xx . . . . 275\nFigure 27.\nSelecting an alternate function on STM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . 276\nFigure 28.\nInput floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279\nFigure 29.\nOutput configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280\nFigure 30.\nAlternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280\nFigure 31.\nHigh impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281\nFigure 32.\nDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307\nFigure 33.\nSystem implementation of the two DMA controllers \n(STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308\nFigure 34.\nSystem implementation of the two DMA controllers\n(STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309\nFigure 35.\nChannel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310\nFigure 36.\nPeripheral-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313\nFigure 37.\nMemory-to-peripheral mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314\nFigure 38.\nMemory-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315\nFigure 39.\nFIFO structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320\nFigure 40.\nDMA2D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344\nFigure 41.\nExternal interrupt/event controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383\nFigure 42.\nExternal interrupt/event GPIO mapping\n(STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385\nFigure 43.\nExternal interrupt/event GPIO mapping (STM32F42xxx and STM32F43xxx) . . . . . . . . . 386\n\n\n<>\n\nList of figures\nRM0090\n48/1757\nRM0090 Rev 21\nFigure 44.\nSingle ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392\nFigure 45.\nTiming diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395\nFigure 46.\nAnalog watchdog’s guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396\nFigure 47.\nInjected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397\nFigure 48.\nRight alignment of 12-bit data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399\nFigure 49.\nLeft alignment of 12-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399\nFigure 50.\nLeft alignment of 6-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399\nFigure 51.\nMulti ADC block diagram(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405\nFigure 52.\nInjected simultaneous mode on 4 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . . 408\nFigure 53.\nInjected simultaneous mode on 4 channels: triple ADC mode . . . . . . . . . . . . . . . . . . . . . 408\nFigure 54.\nRegular simultaneous mode on 16 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . 409\nFigure 55.\nRegular simultaneous mode on 16 channels: triple ADC mode . . . . . . . . . . . . . . . . . . . . 409\nFigure 56.\nInterleaved mode on 1 channel in continuous conversion mode: dual ADC mode. . . . . . 410\nFigure 57.\nInterleaved mode on 1 channel in continuous conversion mode: triple ADC mode . . . . . 411\nFigure 58.\nAlternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412\nFigure 59.\nAlternate trigger: 4 injected channels (each ADC) in discontinuous mode. . . . . . . . . . . . 413\nFigure 60.\nAlternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413\nFigure 61.\nAlternate + regular simultaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414\nFigure 62.\nCase of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415\nFigure 63.\nTemperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 416\nFigure 64.\nDAC channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437\nFigure 65.\nData registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439\nFigure 66.\nData registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439\nFigure 67.\nTiming diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 440\nFigure 68.\nDAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442\nFigure 69.\nDAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 442\nFigure 70.\nDAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443\nFigure 71.\nDAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 443\nFigure 72.\nDCMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459\nFigure 73.\nTop-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460\nFigure 74.\nDCMI signal waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461\nFigure 75.\nTiming diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463\nFigure 76.\nFrame capture waveforms in Snapshot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465\nFigure 77.\nFrame capture waveforms in continuous grab mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466\nFigure 78.\nCoordinates and size of the window after cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467\nFigure 79.\nData capture waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467\nFigure 80.\nPixel raster scan order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468\nFigure 81.\nLTDC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484\nFigure 82.\nLCD-TFT Synchronous timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487\nFigure 83.\nLayer window programmable parameters: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490\nFigure 84.\nBlending two layers with background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493\nFigure 85.\nInterrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494\nFigure 86.\nAdvanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520\nFigure 87.\nCounter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 522\nFigure 88.\nCounter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 522\nFigure 89.\nCounter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523\nFigure 90.\nCounter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524\nFigure 91.\nCounter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524\nFigure 92.\nCounter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524\nFigure 93.\nCounter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 525\nFigure 94.\nCounter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 525\nFigure 95.\nCounter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527\n\n\n<>\n\nRM0090 Rev 21\n49/1757\nRM0090\nList of figures\n56\nFigure 96.\nCounter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527\nFigure 97.\nCounter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528\nFigure 98.\nCounter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528\nFigure 99.\nCounter timing diagram, update event when repetition counter is not used. . . . . . . . . . . 529\nFigure 100. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 530\nFigure 101. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530\nFigure 102. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 531\nFigure 103. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531\nFigure 104. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 532\nFigure 105. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . . . . . . . . . . 532\nFigure 106. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 534\nFigure 107. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 535\nFigure 108. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536\nFigure 109. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537\nFigure 110. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537\nFigure 111. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538\nFigure 112. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 539\nFigure 113. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539\nFigure 114. Output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 540\nFigure 115. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 540\nFigure 116. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542\nFigure 117. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544\nFigure 118. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545\nFigure 119. Center-aligned PWM waveforms (ARR=8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546\nFigure 120. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548\nFigure 121. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 548\nFigure 122. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 548\nFigure 123. Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551\nFigure 124. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552\nFigure 125. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553\nFigure 126. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554\nFigure 127. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 557\nFigure 128. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 557\nFigure 129. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559\nFigure 130. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560\nFigure 131. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561\nFigure 132. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562\nFigure 133. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 563\nFigure 134. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593\nFigure 135. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 595\nFigure 136. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 595\nFigure 137. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596\nFigure 138. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596\nFigure 139. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597\nFigure 140. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597\nFigure 141. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 598\nFigure 142. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 598\nFigure 143. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599\nFigure 144. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600\nFigure 145. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600\nFigure 146. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600\nFigure 147. Counter timing diagram, Update event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601\n\n\n<>\n\nList of figures\nRM0090\n50/1757\nRM0090 Rev 21\nFigure 148. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 602\nFigure 149. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602\nFigure 150. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 603\nFigure 151. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603\nFigure 152. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 604\nFigure 153. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . . . . . . . . . . 604\nFigure 154. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 605\nFigure 155. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606\nFigure 156. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607\nFigure 157. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607\nFigure 158. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608\nFigure 159. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 608\nFigure 160. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609\nFigure 161. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 609\nFigure 162. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611\nFigure 163. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613\nFigure 164. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614\nFigure 165. Center-aligned PWM waveforms (ARR=8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615\nFigure 166. Example of one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616\nFigure 167. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618\nFigure 168. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 620\nFigure 169. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 620\nFigure 170. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621\nFigure 171. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622\nFigure 172. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623\nFigure 173. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 624\nFigure 174. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624\nFigure 175. Gating timer 2 with OC1REF of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625\nFigure 176. Gating timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626\nFigure 177. Triggering timer 2 with update of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627\nFigure 178. Triggering timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628\nFigure 179. Triggering timer 1 and 2 with timer 1 TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629\nFigure 180. General-purpose timer block diagram (TIM9 and TIM12) . . . . . . . . . . . . . . . . . . . . . . . . 654\nFigure 181. General-purpose timer block diagram (TIM10/11/13/14)\n. . . . . . . . . . . . . . . . . . . . . . . . 655\nFigure 182. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 657\nFigure 183. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 657\nFigure 184. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658\nFigure 185. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659\nFigure 186. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659\nFigure 187. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659\nFigure 188. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 660\nFigure 189. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 660\nFigure 190. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 661\nFigure 191. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662\nFigure 192. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662\nFigure 193. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 663\nFigure 194. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664\nFigure 195. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 664\nFigure 196. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666\nFigure 197. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668\nFigure 198. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669\nFigure 199. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670\n\n\n<>\n\nRM0090 Rev 21\n51/1757\nRM0090\nList of figures\n56\nFigure 200. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672\nFigure 201. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673\nFigure 202. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673\nFigure 203. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699\nFigure 204. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 701\nFigure 205. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 701\nFigure 206. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702\nFigure 207. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703\nFigure 208. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703\nFigure 209. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703\nFigure 210. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not\npreloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704\nFigure 211. Counter timing diagram, update event when ARPE=1 (TIMx_ARR\npreloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704\nFigure 212. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 705\nFigure 213. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712\nFigure 214. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717\nFigure 215. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718\nFigure 216. Block diagram (STM32F415/417xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725\nFigure 217. Block diagram (STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726\nFigure 218. DES/TDES-ECB mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728\nFigure 219. DES/TDES-ECB mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728\nFigure 220. DES/TDES-CBC mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730\nFigure 221. DES/TDES-CBC mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731\nFigure 222. AES-ECB mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732\nFigure 223. AES-ECB mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733\nFigure 224. AES-CBC mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734\nFigure 225. AES-CBC mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735\nFigure 226. AES-CTR mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736\nFigure 227. AES-CTR mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737\nFigure 228. Initial counter block structure for the Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737\nFigure 229. 64-bit block construction according to DATATYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744\nFigure 230. Initialization vectors use in the TDES-CBC encryption. . . . . . . . . . . . . . . . . . . . . . . . . . . 746\nFigure 231. CRYP interrupt mapping diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751\nFigure 232. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770\nFigure 233. Block diagram for STM32F415/417xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776\nFigure 234. Block diagram for STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777\nFigure 235. Bit, byte and half-word swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779\nFigure 236. HASH interrupt mapping diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785\nFigure 237. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803\nFigure 238. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844\nFigure 239. I2C block diagram for STM32F40x/41x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845\nFigure 240. I2C block diagram for STM32F42x/43x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846\nFigure 241. Transfer sequence diagram for slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848\nFigure 242. Transfer sequence diagram for slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849\nFigure 243. Transfer sequence diagram for master transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852\nFigure 244. Transfer sequence diagram for master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853\nFigure 245. I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862\nFigure 246. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879\nFigure 247. Single master/ single slave application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880\nFigure 248. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882\nFigure 249. TI mode - Slave mode, single transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884\n\n\n<>\n\nList of figures\nRM0090\n52/1757\nRM0090 Rev 21\nFigure 250. TI mode - Slave mode, continuous transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885\nFigure 251. TI mode - master mode, single transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886\nFigure 252. TI mode - master mode, continuous transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887\nFigure 253. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and\nRXONLY=0) in case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890\nFigure 254. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0,\nRXONLY=0) in case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891\nFigure 255. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0)\nin case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892\nFigure 256. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of \ncontinuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892\nFigure 257. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1)\nin case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893\nFigure 258. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) \nin case of discontinuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894\nFigure 259. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899\nFigure 260. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899\nFigure 261. TI mode frame format error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901\nFigure 262. I2S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902\nFigure 263. I2S full duplex block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903\nFigure 264. I2S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . . . . . . . . . . . . . . 905\nFigure 265. I2S Philips standard waveforms (24-bit frame with CPOL = 0). . . . . . . . . . . . . . . . . . . . . 905\nFigure 266. Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905\nFigure 267. Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906\nFigure 268. I2S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . . . . . . 906\nFigure 269. Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906\nFigure 270. MSB justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . . . . . . . . . . . . . . 907\nFigure 271. MSB justified 24-bit frame length with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907\nFigure 272. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0. . . . . . . . . . . . . . . . 907\nFigure 273. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . 908\nFigure 274. LSB justified 24-bit frame length with CPOL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908\nFigure 275. Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908\nFigure 276. Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909\nFigure 277. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 909\nFigure 278. Example of LSB justified 16-bit extended to 32-bit packet frame . . . . . . . . . . . . . . . . . . . 909\nFigure 279. PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910\nFigure 280. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 910\nFigure 281. Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911\nFigure 282. I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911\nFigure 283. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931\nFigure 284. Audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933\nFigure 285. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . . . . . . . . 935\nFigure 286. FS role is start of frame (FSDEF = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936\nFigure 287. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . . . . . . . . . . . . . . . . . . . . . . 937\nFigure 288. First bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937\nFigure 289. Audio block clock generator overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938\nFigure 290. AC’97 audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942\nFigure 291. Data companding hardware in an audio block in the SAI . . . . . . . . . . . . . . . . . . . . . . . . . 944\nFigure 292. Tristate strategy on SD output line on an inactive slot . . . . . . . . . . . . . . . . . . . . . . . . . . . 946\nFigure 293. Tristate on output data line in a protocol like I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947\nFigure 294. Overrun detection error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948\nFigure 295. FIFO underrun event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949\n\n\n<>\n\nRM0090 Rev 21\n53/1757\nRM0090\nList of figures\n56\nFigure 296. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971\nFigure 297. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972\nFigure 298. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974\nFigure 299. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975\nFigure 300. Start bit detection when oversampling by 16 or 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976\nFigure 301. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979\nFigure 302. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980\nFigure 303. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993\nFigure 304. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993\nFigure 305. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . . . . . . . . . . . . . . 996\nFigure 306. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 997\nFigure 307. USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998\nFigure 308. USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998\nFigure 309. USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999\nFigure 310. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999\nFigure 311. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000\nFigure 312. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001\nFigure 313. IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003\nFigure 314. IrDA data modulation (3/16) -Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003\nFigure 315. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005\nFigure 316. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006\nFigure 317. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006\nFigure 318. RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007\nFigure 319. CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008\nFigure 320. USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009\nFigure 321. SDIO “no response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023\nFigure 322. SDIO (multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023\nFigure 323. SDIO (multiple) block write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024\nFigure 324. SDIO sequential read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024\nFigure 325. SDIO sequential write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024\nFigure 326. SDIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025\nFigure 327. SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026\nFigure 328. Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027\nFigure 329. SDIO adapter command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028\nFigure 330. Command path state machine (CPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029\nFigure 331. SDIO command transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030\nFigure 332. Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032\nFigure 333. Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033\nFigure 334. CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080\nFigure 335. Dual CAN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082\nFigure 336. bxCAN operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084\nFigure 337. bxCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085\nFigure 338. bxCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085\nFigure 339. bxCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086\nFigure 340. Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088\nFigure 341. Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089\nFigure 342. Filter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . 1091\nFigure 343. Example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092\nFigure 344. Filtering mechanism - Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093\nFigure 345. CAN error state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095\nFigure 346. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097\nFigure 347. CAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098\n\n\n<>\n\nList of figures\nRM0090\n54/1757\nRM0090 Rev 21\nFigure 348. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099\nFigure 349. RX and TX mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110\nFigure 350. ETH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129\nFigure 351. SMI interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130\nFigure 352. MDIO timing and frame structure - Write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131\nFigure 353. MDIO timing and frame structure - Read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132\nFigure 354. Media independent interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132\nFigure 355. MII clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134\nFigure 356. Reduced media-independent interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135\nFigure 357. RMII clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135\nFigure 358. Clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136\nFigure 359. Address field format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138\nFigure 360. MAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139\nFigure 361. Tagged MAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140\nFigure 362. Transmission bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146\nFigure 363. Transmission with no collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146\nFigure 364. Transmission with collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147\nFigure 365. Frame transmission in MMI and RMII modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147\nFigure 366. Receive bit order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151\nFigure 367. Reception with no error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152\nFigure 368. Reception with errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152\nFigure 369. Reception with false carrier indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152\nFigure 370. MAC core interrupt masking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153\nFigure 371. Wake-up frame filter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1157\nFigure 372. Networked time synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161\nFigure 373. System time update using the Fine correction method. . . . . . . . . . . . . . . . . . . . . . . . . . 1163\nFigure 374. PTP trigger output to TIM2 ITR1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165\nFigure 375. PPS output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166\nFigure 376. Descriptor ring and chain structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167\nFigure 377. TxDMA operation in Default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171\nFigure 378. TxDMA operation in OSF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173\nFigure 379. Normal transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174\nFigure 380. Enhanced transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180\nFigure 381. Receive DMA operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182\nFigure 382. Normal Rx DMA descriptor structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184\nFigure 383. Enhanced receive descriptor field format with IEEE1588 time stamp enabled. . . . . . . . 1190\nFigure 384. Interrupt scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193\nFigure 385. Ethernet MAC remote wake-up frame filter register (ETH_MACRWUFFR) . . . . . . . . . . 1203\nFigure 386. OTG full-speed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246\nFigure 387. OTG A-B device connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248\nFigure 388. USB peripheral-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250\nFigure 389. USB host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254\nFigure 390. SOF connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258\nFigure 391. Updating OTG_FS_HFIR dynamically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261\nFigure 392. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . 1262\nFigure 393. Host-mode FIFO address mapping and AHB FIFO access mapping. . . . . . . . . . . . . . . 1263\nFigure 394. Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267\nFigure 395. CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269\nFigure 396. Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341\nFigure 397. Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342\nFigure 398. Normal bulk/control OUT/SETUP and bulk/control IN transactions . . . . . . . . . . . . . . . . 1343\nFigure 399. Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346\n\n\n<>\n\nRM0090 Rev 21\n55/1757\nRM0090\nList of figures\n56\nFigure 400. Normal interrupt OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348\nFigure 401. Normal isochronous OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353\nFigure 402. Receive FIFO packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1359\nFigure 403. Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361\nFigure 404. Bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368\nFigure 405. TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377\nFigure 406. A-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378\nFigure 407. B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1379\nFigure 408. A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1380\nFigure 409. B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1382\nFigure 410. USB OTG interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387\nFigure 411. USB host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394\nFigure 412. SOF trigger output to TIM2 ITR1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399\nFigure 413. Updating OTG_HS_HFIR dynamically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401\nFigure 414. Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404\nFigure 415. CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406\nFigure 416. Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495\nFigure 417. Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1496\nFigure 418. Normal bulk/control OUT/SETUP and bulk/control IN transactions - DMA\nmode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497\nFigure 419. Normal bulk/control OUT/SETUP and bulk/control IN transactions - Slave\nmode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1498\nFigure 420. Bulk/control IN transactions - DMA mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501\nFigure 421. Bulk/control IN transactions - Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502\nFigure 422. Normal interrupt OUT/IN transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504\nFigure 423. Normal interrupt OUT/IN transactions - Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505\nFigure 424. Normal isochronous OUT/IN transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . 1510\nFigure 425. Normal isochronous OUT/IN transactions - Slave mode . . . . . . . . . . . . . . . . . . . . . . . . 1511\nFigure 426. Receive FIFO packet read in slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522\nFigure 427. Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524\nFigure 428. Slave mode bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531\nFigure 429. TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1540\nFigure 430. A-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541\nFigure 431. B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542\nFigure 432. A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1543\nFigure 433. B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1545\nFigure 434. FSMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1548\nFigure 435. FSMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1550\nFigure 436. Mode1 read accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1557\nFigure 437. Mode1 write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558\nFigure 438. ModeA read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559\nFigure 439. ModeA write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560\nFigure 440. Mode2 and mode B read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562\nFigure 441. Mode2 write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562\nFigure 442. Mode B write accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563\nFigure 443. Mode C read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1565\nFigure 444. Mode C write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1565\nFigure 445. Mode D read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1567\nFigure 446. Mode D write accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1568\nFigure 447. Multiplexed read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1570\nFigure 448. Multiplexed write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1570\nFigure 449. Asynchronous wait during a read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1573\n\n\n<>\n\nList of figures\nRM0090\n56/1757\nRM0090 Rev 21\nFigure 450. Asynchronous wait during a write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1573\nFigure 451. Wait configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575\nFigure 452. Synchronous multiplexed read mode - NOR, PSRAM (CRAM) . . . . . . . . . . . . . . . . . . . 1576\nFigure 453. Synchronous multiplexed write mode - PSRAM (CRAM) . . . . . . . . . . . . . . . . . . . . . . . . 1578\nFigure 454. NAND/PC Card controller timing for common memory access . . . . . . . . . . . . . . . . . . . 1591\nFigure 455. Access to non ‘CE don’t care’ NAND-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1592\nFigure 456. FMC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607\nFigure 457. FMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610\nFigure 458. Mode1 read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621\nFigure 459. Mode1 write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621\nFigure 460. ModeA read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1623\nFigure 461. ModeA write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624\nFigure 462. Mode2 and mode B read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1626\nFigure 463. Mode2 write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1626\nFigure 464. ModeB write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627\nFigure 465. ModeC read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629\nFigure 466. ModeC write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629\nFigure 467. ModeD read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631\nFigure 468. ModeD write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632\nFigure 469. Muxed read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634\nFigure 470. Muxed write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634\nFigure 471. Asynchronous wait during a read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 1636\nFigure 472. Asynchronous wait during a write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 1637\nFigure 473. Wait configuration waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639\nFigure 474. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . . . . . . . 1639\nFigure 475. Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . . . . . . . . . . . . 1641\nFigure 476. NAND Flash/PC Card controller waveforms for common memory access. . . . . . . . . . . 1654\nFigure 477. Access to non ‘CE don’t care’ NAND-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655\nFigure 478. Burst write SDRAM access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668\nFigure 479. Burst read SDRAM access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669\nFigure 480. Logic diagram of Read access with RBURST bit set (CAS=2, RPIPE=0) . . . . . . . . . . . 1670\nFigure 481. Read access crossing row boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672\nFigure 482. Write access crossing row boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672\nFigure 483. Self-refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1675\nFigure 484. Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1676\nFigure 485. Block diagram of STM32 MCU and Cortex®-M4 with FPU-level debug support . . . . . . 1686\nFigure 486. SWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1688\nFigure 487. JTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692\nFigure 488. TPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710\n\n\n<>\n\nRM0090 Rev 21\n57/1757\nRM0090\nDocumentation conventions\n113\n1 \nDocumentation conventions\nThe STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx and STM32F43xxx devices \nhave an Arm®(a) Cortex®-M4 with FPU core.\n1.1 \nList of abbreviations for registers\nThe following abbreviations are used in register descriptions:\n \na.\nArm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.\nread/write (rw)\nSoftware can read and write to these bits.\nread-only (r)\nSoftware can only read these bits. \nwrite-only (w)\nSoftware can only write to this bit. Reading the bit returns the reset \nvalue.\nread/clear (rc_w1)\nSoftware can read as well as clear this bit by writing 1. Writing ‘0’ has \nno effect on the bit value.\nread/clear (rc_w0)\nSoftware can read as well as clear this bit by writing 0. Writing ‘1’ has \nno effect on the bit value.\nread/clear by read \n(rc_r)\nSoftware can read this bit. Reading this bit automatically clears it to ‘0’. \nWriting ‘0’ has no effect on the bit value.\nread/set (rs)\nSoftware can read as well as set this bit. Writing ‘0’ has no effect on the \nbit value.\nread-only write \ntrigger (rt_w)\nSoftware can read this bit. Writing ‘0’ or ‘1’ triggers an event but has no \neffect on the bit value.\ntoggle (t)\nSoftware can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect.\nReserved (Res.)\nReserved bit, must be kept at reset value.\n\n\n<>\n\nDocumentation conventions\nRM0090\n58/1757\nRM0090 Rev 21\n1.2 \nGlossary\nThis section gives a brief definition of acronyms and abbreviations used in this document:\n•\nThe CPU core integrates two debug ports:\n–\nJTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the \nJoint Test Action Group (JTAG) protocol.\n–\nSWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on \nthe Serial Wire Debug (SWD) protocol.\nFor both the JTAG and SWD protocols, please refer to the Cortex®-M4 with FPU \nTechnical Reference Manual\n•\nWord: data/instruction of 32-bit length.\n•\nHalf word: data/instruction of 16-bit length.\n•\nByte: data of 8-bit length.\n•\nDouble word: data of 64-bit length.\n•\nIAP (in-application programming): IAP is the ability to reprogram the flash memory of a \nmicrocontroller while the user program is running.\n•\nICP (in-circuit programming): ICP is the ability to program the flash memory of a \nmicrocontroller using the JTAG protocol, the SWD protocol or the bootloader while the \ndevice is mounted on the user application board.\n•\nI-Code: this bus connects the Instruction bus of the CPU core to the Flash instruction \ninterface. Prefetch is performed on this bus.\n•\nD-Code: this bus connects the D-Code bus (literal load and debug access) of the CPU \nto the Flash data interface.\n•\nOption bytes: product configuration bits stored in the flash memory.\n•\nOBL: option byte loader.\n•\nAHB: advanced high-performance bus.\n•\nCPU: refers to the Cortex®-M4 with FPU core.\n1.3 \nPeripheral availability\nFor peripheral availability and number across all STM32F405xx/07xx and \nSTM32F415xx/17xx sales types, please refer to the STM32F405xx/07xx and \nSTM32F415xx/17xx datasheets.\nFor peripheral availability and number across all STM32F42xxx and STM32F43xxx sales \ntypes, please refer to the STM32F42xxx and STM32F43xxx datasheets.\n\n\n<>\n\nRM0090 Rev 21\n59/1757\nRM0090\nMemory and bus architecture\n113\n2 \nMemory and bus architecture\n2.1 \nSystem architecture\nIn STM32F405xx/07xx and STM32F415xx/17xx, the main system consists of 32-bit \nmultilayer AHB bus matrix that interconnects:\nThe main system consists of 32-bit multilayer AHB bus matrix that interconnects:\n•\nEight masters:\n–\nCortex®-M4 with FPU core I-bus, D-bus and S-bus\n–\nDMA1 memory bus\n–\nDMA2 memory bus\n–\nDMA2 peripheral bus\n–\nEthernet DMA bus\n–\nUSB OTG HS DMA bus\n•\nSeven slaves:\n–\nInternal flash memory ICode bus\n–\nInternal flash memory DCode bus\n–\nMain internal SRAM1 (112 KB)\n–\nAuxiliary internal SRAM2 (16 KB)\n–\nAHB1 peripherals including AHB to APB bridges and APB peripherals\n–\nAHB2 peripherals\n–\nFSMC\nThe bus matrix provides access from a master to a slave, enabling concurrent access and \nefficient operation even when several high-speed peripherals work simultaneously. The 64-\nKbyte CCM (core coupled memory) data RAM is not part of the bus matrix and can be \naccessed only through the CPU. This architecture is shown in Figure 1.\n\n\n<>\n\nMemory and bus architecture\nRM0090\n60/1757\nRM0090 Rev 21\nFigure 1. System architecture for STM32F405xx/07xx and STM32F415xx/17xx devices\nARM\nCortex-M4\nGP\nDMA1\nGP\nDMA2\nMAC\nEthernet\nUSB OTG\nHS\nBus matrix-S\nICODE\nDCODE\nACCEL\nFlash\nmemory\nSRAM1 \n112 Kbyte\nSRAM2\n16 Kbyte\nAHB1\nperipherals\nAHB2\nFSMC\nStatic MemCtl\nI-bus\nD-bus\nS-bus\nDMA_P1\nDMA_MEM1\nDMA_MEM2\nDMA_P2\nETHERNET_M\nUSB_HS_M\nai18490e\nCCM data RAM \n64-Kbyte\nAPB1\nAPB2\nperipherals\n\n\n<>\n\nRM0090 Rev 21\n61/1757\nRM0090\nMemory and bus architecture\n113\nIn the STM32F42xx and STM32F43xx devices, the main system consists of 32-bit multilayer \nAHB bus matrix that interconnects:\n•\nTen masters:\n–\nCortex®-M4 with FPU core I-bus, D-bus and S-bus\n–\nDMA1 memory bus\n–\nDMA2 memory bus\n–\nDMA2 peripheral bus\n–\nEthernet DMA bus\n–\nUSB OTG HS DMA bus\n–\nLCD Controller DMA-bus\n–\nDMA2D (Chrom-Art Accelerator™) memory bus\n•\nEight slaves:\n–\nInternal flash memory ICode bus\n–\nInternal flash memory DCode bus\n–\nMain internal SRAM1 (112 KB)\n–\nAuxiliary internal SRAM2 (16 KB)\n–\nAuxiliary internal SRAM3 (64 KB)\n–\nAHB1peripherals including AHB to APB bridges and APB peripherals\n–\nAHB2 peripherals\n–\nFMC\nThe bus matrix provides access from a master to a slave, enabling concurrent access and \nefficient operation even when several high-speed peripherals work simultaneously. The 64-\nKbyte CCM (core coupled memory) data RAM is not part of the bus matrix and can be \naccessed only through the CPU. This architecture is shown in Figure 2.\n\n\n<>\n\nMemory and bus architecture\nRM0090\n62/1757\nRM0090 Rev 21\nFigure 2. System architecture for STM32F42xxx and STM32F43xxx devices\n2.1.1 \nI-bus\nThis bus connects the Instruction bus of the Cortex®-M4 with FPU core to the BusMatrix. \nThis bus is used by the core to fetch instructions. The target of this bus is a memory \ncontaining code (internal flash memory/SRAM or external memories through the \nFSMC/FMC).\n2.1.2 \nD-bus\nThis bus connects the databus of the Cortex®-M4 with FPU to the 64-Kbyte CCM data RAM \nto the BusMatrix. This bus is used by the core for literal load and debug access. The target \nof this bus is a memory containing code or data (internal flash memory or external memories \nthrough the FSMC/FMC).\n2.1.3 \nS-bus\nThis bus connects the system bus of the Cortex®-M4 with FPU core to a BusMatrix. This \nbus is used to access data located in a peripheral or in SRAM. Instructions may also be \nfetched on this bus (less efficient than ICode). The targets of this bus are the internal \nSRAM1, SRAM2 and SRAM3, the AHB1 peripherals including the APB peripherals, the \nAHB2 peripherals and the external memories through the FSMC/FMC.\nARM\nCortex-M4\nGP\nDMA1\nGP\nDMA2\nMAC\nEthernet\nUSB OTG\nHS\nBus matrix-S\nICODE\nDCODE\nACCEL\nFlash\nmemory\nSRAM1 \n112 Kbyte\nSRAM2\n16 Kbyte\nAHB2\nperipherals\nAHB1\nperipherals\nFMC external\nMemCtl\nI-bus\nD-bus\nS-bus\nDMA_P1\nDMA_MEM1\nDMA_MEM2\nDMA_P2\nETHERNET_M\nUSB_HS_M\nMS30421V7\nCCM data RAM \n64-Kbyte\nAPB1\nAPB2\nSRAM3 \n64 Kbyte\nLCD-TFT\nChrom ART Accelerator(DMA2D)\nLCD-TFT_M\nDMA2D\n\n\n<>\n\nRM0090 Rev 21\n63/1757\nRM0090\nMemory and bus architecture\n113\n2.1.4 \nDMA memory bus\nThis bus connects the DMA memory bus master interface to the BusMatrix. It is used by the \nDMA to perform transfer to/from memories. The targets of this bus are data memories: \ninternal SRAMs (SRAM1, SRAM2 and SRAM3) and external memories through the \nFSMC/FMC.\n2.1.5 \nDMA peripheral bus\nThis bus connects the DMA peripheral master bus interface to the BusMatrix. This bus is \nused by the DMA to access AHB peripherals or to perform memory-to-memory transfers. \nThe targets of this bus are the AHB and APB peripherals plus data memories: internal \nSRAMs (SRAM1, SRAM2 and SRAM3) and external memories through the FSMC/FMC.\n2.1.6 \nEthernet DMA bus\nThis bus connects the Ethernet DMA master interface to the BusMatrix. This bus is used by \nthe Ethernet DMA to load/store data to a memory. The targets of this bus are data \nmemories: internal SRAMs (SRAM1, SRAM2, SRAM3), internal flash memory, and external \nmemories through the FSMC/FMC.\n2.1.7 \nUSB OTG HS DMA bus\nThis bus connects the USB OTG HS DMA master interface to the BusMatrix. This bus is \nused by the USB OTG DMA to load/store data to a memory. The targets of this bus are data \nmemories: internal SRAMs (SRAM1, SRAM2, SRAM3), internal flash memory, and external \nmemories through the FSMC/FMC.\n2.1.8 \nLCD-TFT controller DMA bus\nThis bus connects the LCD controller DMA master interface to the BusMatrix. It is used by \nthe LCD-TFT DMA to load/store data to a memory. The targets of this bus are data \nmemories: internal SRAMs (SRAM1, SRAM2, SRAM3), external memories through FMC, \nand internal flash memory.\n2.1.9 \nDMA2D bus\nThis bus connect the DMA2D master interface to the BusMatrix. This bus is used by the \nDMA2D graphic Accelerator to load/store data to a memory. The targets of this bus are data \nmemories: internal SRAMs (SRAM1, SRAM2, SRAM3), external memories through FMC, \nand internal flash memory.\n2.1.10 \nBusMatrix\nThe BusMatrix manages the access arbitration between masters. The arbitration uses a \nround-robin algorithm.\n\n\n<>\n\nMemory and bus architecture\nRM0090\n64/1757\nRM0090 Rev 21\n2.1.11 \nAHB/APB bridges (APB)\nThe two AHB/APB bridges, APB1 and APB2, provide full synchronous connections between \nthe AHB and the two APB buses, allowing flexible selection of the peripheral frequency.\nRefer to the device datasheets for more details on APB1 and APB2 maximum frequencies, \nand to Table 1 for the address mapping of AHB and APB peripherals.\nAfter each device reset, all peripheral clocks are disabled (except for the SRAM and flash \nmemory interface). Before using a peripheral you have to enable its clock in the \nRCC_AHBxENR or RCC_APBxENR register.\nNote:\nWhen a 16- or an 8-bit access is performed on an APB register, the access is transformed \ninto a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.\n2.2 \nMemory organization\nProgram memory, data memory, registers and I/O ports are organized within the same linear \n4 Gbyte address space.\nThe bytes are coded in memory in little endian format. The lowest numbered byte in a word \nis considered the word’s least significant byte and the highest numbered byte, the word’s \nmost significant.\nFor the detailed mapping of peripheral registers, please refer to the related chapters.\nThe addressable memory space is divided into 8 main blocks, each of 512 MB.\nAll the memory areas that are not allocated to on-chip memories and peripherals are \nconsidered “Reserved”). Refer to the memory map figure in the product datasheet.\n2.3 \nMemory map\nSee the datasheet corresponding to your device for a comprehensive diagram of the \nmemory map. Table 1 gives the boundary addresses of the peripherals available in all \nSTM32F4xx devices.\n \nTable 1. STM32F4xx register boundary addresses\nBoundary address\nPeripheral\nBus\nRegister map\n0xA000 0000 - 0xA000 0FFF\nFSMC control register \n(STM32F405xx/07xx \nand \nSTM32F415xx/17xx)/\nFMC control register \n(STM32F42xxx and \nSTM32F43xxx)\nAHB3\nSection 36.6.9: FSMC register map on page 1603\nSection 37.8: FMC register map on page 1683\n\n\n<>\n\nRM0090 Rev 21\n65/1757\nRM0090\nMemory and bus architecture\n113\n0x5006 0800 - 0x5006 0BFF\nRNG\nAHB2\nSection 24.4.4: RNG register map on page 774\n0x5006 0400 - 0x5006 07FF\nHASH\nSection 25.4.9: HASH register map on page 798\n0x5006 0000 - 0x5006 03FF\nCRYP\nSection 23.6.13: CRYP register map on page 766\n0x5005 0000 - 0x5005 03FF\nDCMI\nSection 15.8.12: DCMI register map on page 481\n0x5000 0000 - 0x5003 FFFF\nUSB OTG FS\nSection 34.16.6: OTG_FS register map on \npage 1329\n0x4004 0000 - 0x4007 FFFF\nUSB OTG HS\nAHB1\nSection 35.12.6: OTG_HS register map on \npage 1475\n0x4002 B000 - 0x4002 BBFF\nDMA2D\nSection 11.5: DMA2D registers on page 355\n0x4002 8000 - 0x4002 93FF\nETHERNET MAC\nSection 33.8.5: Ethernet register maps on \npage 1239\n0x4002 6400 - 0x4002 67FF\nDMA2\nSection 10.5.11: DMA register map on page 338\n0x4002 6000 - 0x4002 63FF\nDMA1\n0x4002 4000 - 0x4002 4FFF\nBKPSRAM\n-\n0x4002 3C00 - 0x4002 3FFF\nFlash interface \nregister\nSection 3.9: Flash interface registers\n0x4002 3800 - 0x4002 3BFF\nRCC\nSection 7.3.24: RCC register map on page 267\n0x4002 3000 - 0x4002 33FF\nCRC\nSection 4.4.4: CRC register map on page 116\n0x4002 2800 - 0x4002 2BFF\nGPIOK\nSection 8.4.11: GPIO register map on page 290\n0x4002 2400 - 0x4002 27FF\nGPIOJ\n0x4002 2000 - 0x4002 23FF\nGPIOI\nSection 8.4.11: GPIO register map on page 290\n0x4002 1C00 - 0x4002 1FFF\nGPIOH\n0x4002 1800 - 0x4002 1BFF\nGPIOG\n0x4002 1400 - 0x4002 17FF\nGPIOF\n0x4002 1000 - 0x4002 13FF\nGPIOE\n0x4002 0C00 - 0x4002 0FFF\nGPIOD\n0x4002 0800 - 0x4002 0BFF\nGPIOC\n0x4002 0400 - 0x4002 07FF\nGPIOB\n0x4002 0000 - 0x4002 03FF\nGPIOA\n0x4001 6800 - 0x4001 6BFF\nLCD-TFT\nAPB2\nSection 16.7.26: LTDC register map on page 515\n0x4001 5800 - 0x4001 5BFF\nSAI1\nSection 29.17.9: SAI register map on page 966\n0x4001 5400 - 0x4001 57FF\nSPI6\nAPB2\nSection 28.5.10: SPI register map on page 928\n0x4001 5000 - 0x4001 53FF\nSPI5\nTable 1. STM32F4xx register boundary addresses (continued)\nBoundary address\nPeripheral\nBus\nRegister map\n\n\n<>\n\nMemory and bus architecture\nRM0090\n66/1757\nRM0090 Rev 21\n0x4001 4800 - 0x4001 4BFF\nTIM11\nAPB2\nSection 19.5.12: TIM10/11/13/14 register map on \npage 697\n0x4001 4400 - 0x4001 47FF\nTIM10\n0x4001 4000 - 0x4001 43FF\nTIM9\nSection 19.4.13: TIM9/12 register map on \npage 687\n0x4001 3C00 - 0x4001 3FFF\nEXTI\nSection 12.3.7: EXTI register map on page 390\n0x4001 3800 - 0x4001 3BFF\nSYSCFG\nSection 9.2.8: SYSCFG register maps for \nSTM32F405xx/07xx and STM32F415xx/17xx on \npage 297 and Section 9.3.8: SYSCFG register \nmaps for STM32F42xxx and STM32F43xxx on \npage 304\n0x4001 3400 - 0x4001 37FF\nSPI4\nAPB2\nSection 28.5.10: SPI register map on page 928\n0x4001 3000 - 0x4001 33FF\nSPI1\nAPB2\nSection 28.5.10: SPI register map on page 928\n0x4001 2C00 - 0x4001 2FFF\nSDIO\nSection 31.9.16: SDIO register map on page 1077\n0x4001 2000 - 0x4001 23FF\nADC1 - ADC2 - ADC3\nSection 13.13.18: ADC register map on page 433\n0x4001 1400 - 0x4001 17FF\nUSART6\nSection 30.6.8: USART register map on page 1021\n0x4001 1000 - 0x4001 13FF\nUSART1\n0x4001 0400 - 0x4001 07FF\nTIM8\nSection 17.4.21: TIM1 and TIM8 register map on \npage 590\n0x4001 0000 - 0x4001 03FF\nTIM1\n0x4000 7C00 - 0x4000 7FFF\nUART8\nAPB1\nSection 30.6.8: USART register map on page 1021\n0x4000 7800 - 0x4000 7BFF\nUART7\nTable 1. STM32F4xx register boundary addresses (continued)\nBoundary address\nPeripheral\nBus\nRegister map\n\n\n<>\n\nRM0090 Rev 21\n67/1757\nRM0090\nMemory and bus architecture\n113\n0x4000 7400 - 0x4000 77FF\nDAC\nAPB1\nSection 14.5.15: DAC register map on page 456\n0x4000 7000 - 0x4000 73FF\nPWR\nSection 5.6: PWR register map on page 151\n0x4000 6800 - 0x4000 6BFF\nCAN2\nSection 32.9.5: bxCAN register map on page 1121\n0x4000 6400 - 0x4000 67FF\nCAN1\n0x4000 5C00 - 0x4000 5FFF\nI2C3\nSection 27.6.11: I2C register map on page 875\n0x4000 5800 - 0x4000 5BFF\nI2C2\n0x4000 5400 - 0x4000 57FF\nI2C1\n0x4000 5000 - 0x4000 53FF\nUART5\nSection 30.6.8: USART register map on page 1021\n0x4000 4C00 - 0x4000 4FFF\nUART4\n0x4000 4800 - 0x4000 4BFF\nUSART3 \n0x4000 4400 - 0x4000 47FF\nUSART2\n0x4000 4000 - 0x4000 43FF\nI2S3ext\nSection 28.5.10: SPI register map on page 928\n0x4000 3C00 - 0x4000 3FFF\nSPI3 / I2S3\n0x4000 3800 - 0x4000 3BFF\nSPI2 / I2S2\n0x4000 3400 - 0x4000 37FF\nI2S2ext\n0x4000 3000 - 0x4000 33FF\nIWDG\nSection 21.4.5: IWDG register map on page 715\n0x4000 2C00 - 0x4000 2FFF\nWWDG\nSection 22.6.4: WWDG register map on page 722\n0x4000 2800 - 0x4000 2BFF\nRTC & BKP Registers\nSection 26.6.21: RTC register map on page 839\n0x4000 2000 - 0x4000 23FF\nTIM14\nSection 19.5.12: TIM10/11/13/14 register map on \npage 697\n0x4000 1C00 - 0x4000 1FFF\nTIM13\n0x4000 1800 - 0x4000 1BFF\nTIM12\nSection 19.4.13: TIM9/12 register map on \npage 687\n0x4000 1400 - 0x4000 17FF\nTIM7\nSection 20.4.9: TIM6 and TIM7 register map on \npage 710\n0x4000 1000 - 0x4000 13FF\nTIM6\n0x4000 0C00 - 0x4000 0FFF\nTIM5\nSection 18.4.21: TIMx register map on page 651\n0x4000 0800 - 0x4000 0BFF\nTIM4\n0x4000 0400 - 0x4000 07FF\nTIM3\n0x4000 0000 - 0x4000 03FF\nTIM2\nTable 1. STM32F4xx register boundary addresses (continued)\nBoundary address\nPeripheral\nBus\nRegister map\n\n\n<>\n\nMemory and bus architecture\nRM0090\n68/1757\nRM0090 Rev 21\n2.3.1 \nEmbedded SRAM\nThe STM32F405xx/07xx and STM32F415xx/17xx feature 4 Kbytes of backup SRAM (see \nSection 5.1.2: Battery backup domain) plus 192 Kbytes of system SRAM.\nThe STM32F42xxx and STM32F43xxx feature 4 Kbytes of backup SRAM (see \nSection 5.1.2: Battery backup domain) plus 256 Kbytes of system SRAM.\nThe embedded SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). \nRead and write operations are performed at CPU speed with 0 wait state. The embedded \nSRAM is divided into up to three blocks:\n•\nSRAM1 and SRAM2 mapped at address 0x2000 0000 and accessible by all AHB \nmasters.\n•\nSRAM3 (available on STM32F42xxx and STM32F43xxx) mapped at address \n0x2002 0000 and accessible by all AHB masters. \n•\nCCM (core coupled memory) mapped at address 0x1000 0000 and accessible only by \nthe CPU through the D-bus.\nThe AHB masters support concurrent SRAM accesses (from the Ethernet or the USB OTG \nHS): for instance, the Ethernet MAC can read/write from/to SRAM2 while the CPU is \nreading/writing from/to SRAM1 or SRAM3.\nThe CPU can access the SRAM1 through the System bus or through the I-Code/D-Code \nbuses when boot from SRAM is selected or when physical remap is selected (Section 9.2.1: \nSYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller). To get \nthe max performance on SRAM execution, physical remap should be selected (boot or \nsoftware selection).\n2.3.2 \nFlash memory overview\nThe flash memory interface manages CPU AHB I-Code and D-Code accesses to the flash \nmemory. It implements the erase and program flash memory operations and the read and \nwrite protection mechanisms. It accelerates code execution with a system of instruction \nprefetch and cache lines.\nThe flash memory is organized as follows:\n•\nA main memory block divided into sectors.\n•\nSystem memory from which the device boots in System memory boot mode\n•\n512 OTP (one-time programmable) bytes for user data.\n•\nOption bytes to configure read and write protection, BOR level, watchdog \nsoftware/hardware and reset when the device is in Standby or Stop mode.\nRefer to Section 3: Embedded flash memory interface for more details.\n2.3.3 \nBit banding\nThe Cortex®-M4 with FPU memory map includes two bit-band regions. These regions map \neach word in an alias region of memory to a bit in a bit-band region of memory. Writing to a \nword in the alias region has the same effect as a read-modify-write operation on the \ntargeted bit in the bit-band region.\nIn the STM32F4xx devices both the peripheral registers and the SRAM are mapped to a bit-\nband region, so that single bit-band write and read operations are allowed. The operations \n\n\n<>\n\nRM0090 Rev 21\n69/1757\nRM0090\nMemory and bus architecture\n113\nare only available for Cortex®-M4 with FPU accesses, and not from other bus masters (e.g. \nDMA).\nA mapping formula shows how to reference each word in the alias region to a corresponding \nbit in the bit-band region. The mapping formula is:\nbit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4)\nwhere:\n–\nbit_word_addr is the address of the word in the alias memory region that maps to \nthe targeted bit\n–\nbit_band_base is the starting address of the alias region\n–\nbyte_offset is the number of the byte in the bit-band region that contains the \ntargeted bit\n–\nbit_number is the bit position (0-7) of the targeted bit\nExample\nThe following example shows how to map bit 2 of the byte located at SRAM address \n0x20000300 to the alias region:\n0x22006008 = 0x22000000 + (0x300*32) + (2*4)\nWriting to address 0x22006008 has the same effect as a read-modify-write operation on bit \n2 of the byte at SRAM address 0x20000300.\nReading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM \naddress 0x20000300 (0x01: bit set; 0x00: bit reset).\nFor more information on bit-banding, please refer to the Cortex®-M4 with FPU programming \nmanual (see Related documents on page 1).\n2.4 \nBoot configuration\nDue to its fixed memory map, the code area starts from address 0x0000 0000 (accessed \nthrough the ICode/DCode buses) while the data area (SRAM) starts from address \n0x2000 0000 (accessed through the system bus). The Cortex®-M4 with FPU CPU always \nfetches the reset vector on the ICode bus, which implies to have the boot space available \nonly in the code area (typically, flash memory). STM32F4xx microcontrollers implement a \nspecial mechanism to be able to boot from other memories (like the internal SRAM).\nIn the STM32F4xx, three different boot modes can be selected through the BOOT[1:0] pins \nas shown in Table 2.\n \nTable 2. Boot modes\nBoot mode selection pins\nBoot mode\nAliasing\nBOOT1\nBOOT0\nx\n0\nMain flash memory\nMain flash memory is selected as the boot space\n0\n1\nSystem memory\nSystem memory is selected as the boot space\n1\n1\nEmbedded SRAM\nEmbedded SRAM is selected as the boot space\n\n\n<>\n\nMemory and bus architecture\nRM0090\n70/1757\nRM0090 Rev 21\nThe values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It \nis up to the user to set the BOOT1 and BOOT0 pins after reset to select the required boot \nmode.\nBOOT0 is a dedicated pin while BOOT1 is shared with a GPIO pin. Once BOOT1 has been \nsampled, the corresponding GPIO pin is free and can be used for other purposes.\nThe BOOT pins are also resampled when the device exits the Standby mode. Consequently, \nthey must be kept in the required Boot mode configuration when the device is in the Standby \nmode. After this startup delay is over, the CPU fetches the top-of-stack value from address \n0x0000 0000, then starts code execution from the boot memory starting from 0x0000 0004.\nNote:\nWhen the device boots from SRAM, in the application initialization code, you have to \nrelocate the vector table in SRAM using the NVIC exception table and the offset register.\nIn STM32F42xxx and STM32F43xxx devices, when booting from the main flash memory, \nthe application software can either boot from bank 1 or from bank 2. By default, boot from \nbank 1 is selected.\nTo select boot from flash memory bank 2, set the BFB2 bit in the user option bytes. When \nthis bit is set and the boot pins are in the boot from main flash memory configuration, the \ndevice boots from system memory, and the boot loader jumps to execute the user \napplication programmed in flash memory bank 2. For further details, please refer to \nAN2606.\nEmbedded bootloader\nThe embedded bootloader mode is used to reprogram the flash memory using one of the \nfollowing serial interfaces:\n•\nUSART1 (PA9/PA10)\n•\nUSART3 (PB10/11 and PC10/11)\n•\nCAN2 (PB5/13)\n•\nUSB OTG FS (PA11/12) in Device mode (DFU: device firmware upgrade).\nThe USART peripherals operate at the internal 16 MHz oscillator (HSI) frequency, while the \nCAN and USB OTG FS require an external clock (HSE) multiple of 1 MHz (ranging from 4 to \n26 MHz).\nThe embedded bootloader code is located in system memory. It is programmed by ST \nduring production. For additional information, refer to application note AN2606.\nPhysical remap in STM32F405xx/07xx and STM32F415xx/17xx\nOnce the boot pins are selected, the application software can modify the memory \naccessible in the code area (in this way the code can be executed through the ICode bus in \nplace of the System bus). This modification is performed by programming the Section 9.2.1: \nSYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller.\nThe following memories can thus be remapped:\n•\nMain flash memory\n•\nSystem memory\n•\nEmbedded SRAM1 (112 KB)\n•\nFSMC bank 1 (NOR/PSRAM 1 and 2)\n\n\n<>\n\nRM0090 Rev 21\n71/1757\nRM0090\nMemory and bus architecture\n113\n \nPhysical remap in STM32F42xxx and STM32F43xxx\nOnce the boot pins are selected, the application software can modify the memory \naccessible in the code area (in this way the code can be executed through the ICode bus in \nplace of the System bus). This modification is performed by programming the Section 9.2.1: \nSYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller.\nThe following memories can thus be remapped:\n•\nMain flash memory\n•\nSystem memory\n•\nEmbedded SRAM1 (112 KB)\n•\nFMC bank 1 (NOR/PSRAM 1 and 2)\n•\nFMC SDRAM bank 1\n \nTable 3. Memory mapping vs. Boot mode/physical remap\nin STM32F405xx/07xx and STM32F415xx/17xx\nAddresses\nBoot/Remap in \nmain flash memory\nBoot/Remap in \nembedded SRAM\nBoot/Remap in \nSystem memory\nRemap in FSMC\n0x2001 C000 - 0x2001 FFFF\nSRAM2 (16 KB)\nSRAM2 (16 KB)\nSRAM2 (16 KB)\nSRAM2 (16 KB)\n0x2000 0000 - 0x2001 BFFF\nSRAM1 (112 KB)\nSRAM1 (112 KB)\nSRAM1 (112 KB)\nSRAM1 (112 KB)\n0x1FFF 0000 - 0x1FFF 77FF\nSystem memory\nSystem memory\nSystem memory\nSystem memory\n0x0810 0000 - 0x0FFF FFFF\nReserved\nReserved\nReserved\nReserved\n0x0800 0000 - 0x080F FFFF\nFlash memory\nFlash memory\nFlash memory\nFlash memory\n0x0400 0000 - 0x07FF FFFF\nReserved\nReserved\nReserved\nFSMC bank 1 \nNOR/PSRAM 2 \n(128 MB Aliased)\n0x0000 0000 - \n0x000F FFFF(1)(2)\nFlash (1 MB) Aliased\nSRAM1 (112 KB) \nAliased\nSystem memory \n(30 KB) Aliased\nFSMC bank 1 \nNOR/PSRAM 1 \n(128 MB Aliased)\n1.\nWhen the FSMC is remapped at address 0x0000 0000, only the first two regions of bank 1 memory controller (bank 1 \nNOR/PSRAM 1 and NOR/PSRAM 2) can be remapped. In remap mode, the CPU can access the external memory via \nICode bus instead of System bus which boosts up the performance.\n2.\nEven when aliased in the boot memory space, the related memory is still accessible at its original memory space.\nTable 4. Memory mapping vs. Boot mode/physical remap\nin STM32F42xxx and STM32F43xxx\nAddresses\nBoot/Remap in \nmain flash memory\nBoot/Remap in \nembedded SRAM\nBoot/Remap in \nSystem memory\nRemap in FMC\n0x2002 0000 - 0x2002 FFFF\nSRAM3 (64 KB)\nSRAM3 (64 KB)\nSRAM3 (64 KB)\nSRAM3 (64 KB)\n0x2001 C000 - 0x2001 FFFF\nSRAM2 (16 KB)\nSRAM2 (16 KB)\nSRAM2 (16 KB)\nSRAM2 (16 KB)\n0x2000 0000 - 0x2001 BFFF\nSRAM1 (112 KB)\nSRAM1 (112 KB)\nSRAM1 (112 KB)\nSRAM1 (112 KB)\n0x1FFF 0000 - 0x1FFF 77FF\nSystem memory\nSystem memory\nSystem memory\nSystem memory\n0x0810 0000 - 0x0FFF FFFF\nReserved\nReserved\nReserved\nReserved\n0x0800 0000 - 0x081F FFFF\nFlash memory\nFlash memory\nFlash memory\nFlash memory\n\n\n<>\n\nMemory and bus architecture\nRM0090\n72/1757\nRM0090 Rev 21\n0x0400 0000 - 0x07FF FFFF\nReserved\nReserved\nReserved\nFMC bank 1 \nNOR/PSRAM 2 \n(128 MB Aliased) \n0x0000 0000 - \n0x001F FFFF(1)(2)\nFlash (2 MB) Aliased\nSRAM1 (112 KB) \nAliased\nSystem memory \n(30 KB) Aliased\nFMC bank 1 \nNOR/PSRAM 1 \n(128 MB Aliased)\nor FMC SDRAM \nbank 1 (128 MB \nAliased)\n1.\nWhen the FMC is remapped at address 0x0000 0000, only the first two regions of bank 1 memory controller (bank 1 \nNOR/PSRAM 1 and NOR/PSRAM 2) or SDRAM bank 1 can be remapped. In remap mode, the CPU can access the \nexternal memory via ICode bus instead of System bus which boosts up the performance.\n2.\nEven when aliased in the boot memory space, the related memory is still accessible at its original memory space.\nTable 4. Memory mapping vs. Boot mode/physical remap\nin STM32F42xxx and STM32F43xxx (continued)\nAddresses\nBoot/Remap in \nmain flash memory\nBoot/Remap in \nembedded SRAM\nBoot/Remap in \nSystem memory\nRemap in FMC\n\n\n<>\n\nRM0090 Rev 21\n73/1757\nRM0090\nEmbedded flash memory interface\n113\n3 \nEmbedded flash memory interface\n3.1 \nIntroduction\nThe flash memory interface manages CPU AHB I-Code and D-Code accesses to the flash \nmemory. It implements the erase and program flash memory operations and the read and \nwrite protection mechanisms.\nThe flash memory interface accelerates code execution with a system of instruction prefetch \nand cache lines.\n3.2 \nMain features\n•\nFlash memory read operations\n•\nFlash memory program/erase operations\n•\nRead / write protections\n•\nPrefetch on I-Code\n•\n64 cache lines of 128 bits on I-Code\n•\n8 cache lines of 128 bits on D-Code\nFigure 3 shows the flash memory interface connection inside the system architecture.\nFigure 3. Flash memory interface connection inside system architecture\n (STM32F405xx/07xx and STM32F415xx/17xx)\nCortex\ncore\nEthernet\nUSB HS\nDMA1\nDMA2\nD-code bus\nI-Code bus\nCortex-M4 with FPU\nI-Code\nD-Code\nS bus\nAHB \nperiph1\nFlash \nmemory\nFlash interface\n \nSRAM and\nExternal \nmemories \nAHB\nperiph2\nFLITF registers\nAHB\n32-bit\ninstruction \nbus\nAccess to instruction in Flash memory\nAccess to data and literal pool in Flash memory \nFLITF register access\n \nMS30468V3\nCCM data \nRAM\nAHB\n32-bit\ndata bus\nAHB\n32-bit\nsystem bus\nFlash \nmemory\nbus \n128 bits\n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n74/1757\nRM0090 Rev 21\nFigure 4. Flash memory interface connection inside system architecture\n(STM32F42xxx and STM32F43xxx)\n3.3 \nEmbedded flash memory in \nSTM32F405xx/07xx and STM32F415xx/17xx\nThe flash memory has the following main features:\n•\nCapacity up to 1 Mbyte\n•\n128 bits wide data read\n•\nByte, half-word, word and double word write\n•\nSector and mass erase\n•\nMemory organization\nThe flash memory is organized as follows:\n–\nA main memory block divided into 4 sectors of 16 Kbytes, 1 sector of 64 Kbytes, \nand 7 sectors of 128 Kbytes\n–\nSystem memory from which the device boots in System memory boot mode\n–\n512 OTP (one-time programmable) bytes for user data\nThe OTP area contains 16 additional bytes used to lock the corresponding OTP \ndata block.\n–\nOption bytes to configure read and write protection, BOR level, watchdog \nsoftware/hardware and reset when the device is in Standby or Stop mode.\n•\nLow-power modes (for details refer to the Power control (PWR) section of the reference \nmanual)\nCortex\ncore\nEthernet\nUSB HS\nDMA1\nDMA2\nD-code bus\nI-Code bus\nCortex-M4 with FPU\nI-Code\nD-Code\nS bus\nAHB\nperiph1\nFlash \nmemory\nFlash interface\n \nSRAM and\nexternal \nmemories \nAHB\nperiph2\nFLITF registers\nAHB\n32-bit\ninstruction \nbus\nAccess to instruction in Flash memory\nAccess to data and literal pool in Flash memory \nFLITF register access\n \nMS30466V3\nCCM data \nRAM\nAHB\n32-bit\ndata bus\nAHB\n32-bit\nsystem bus\nFlash \nmemory\nbus \n128 bits\nDMA2D\nLCD-TFT\n\n\n<>\n\nRM0090 Rev 21\n75/1757\nRM0090\nEmbedded flash memory interface\n113\n \nTable 5. Flash module organization (STM32F40x and STM32F41x)\nBlock\nName\nBlock base addresses\nSize\nMain memory\nSector 0\n0x0800 0000 - 0x0800 3FFF\n16 Kbytes\nSector 1\n0x0800 4000 - 0x0800 7FFF\n16 Kbytes\nSector 2\n0x0800 8000 - 0x0800 BFFF\n16 Kbytes\nSector 3\n0x0800 C000 - 0x0800 FFFF\n16 Kbytes\nSector 4\n0x0801 0000 - 0x0801 FFFF\n64 Kbytes\nSector 5\n0x0802 0000 - 0x0803 FFFF\n128 Kbytes\nSector 6\n0x0804 0000 - 0x0805 FFFF\n128 Kbytes\n.\n.\n.\n.\n.\n.\n.\n.\n.\nSector 11\n0x080E 0000 - 0x080F FFFF\n128 Kbytes\nSystem memory\n0x1FFF 0000 - 0x1FFF 77FF\n30 Kbytes\nOTP area \n0x1FFF 7800 - 0x1FFF 7A0F\n528 bytes\nOption bytes\n0x1FFF C000 - 0x1FFF C00F\n16 bytes\n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n76/1757\nRM0090 Rev 21\n3.4 \nEmbedded flash memory in STM32F42xxx and STM32F43xxx\nThe flash memory has the following main features:\n•\nCapacity up to 2 Mbyte with dual bank architecture supporting read-while-write \ncapability (RWW)\n•\n128 bits wide data read\n•\nByte, half-word, word and double word write\n•\nSector, bank, and mass erase (both banks)\n•\nDual bank memory organization\nThe dual bank organization is available only on 1 Mbyte and 2 Mbyte devices.\nThe flash memory is organized as follows:\n–\nFor each bank, a main memory block (1 Mbyte) divided into 4 sectors of 16 \nKbytes, 1 sector of 64 Kbytes, and 7 sectors of 128 Kbytes\n–\nSystem memory from which the device boots in System memory boot mode\n–\n512 OTP (one-time programmable) bytes for user data\nThe OTP area contains 16 additional bytes used to lock the corresponding OTP \ndata block.\n–\nOption bytes to configure read and write protection, BOR level, watchdog, dual \nbank boot mode, dual bank feature, software/hardware and reset when the device \nis in Standby or Stop mode.\n•\nDual bank organization on 1 Mbyte devices\nThe dual bank feature on 1 Mbyte devices is enabled by setting the DB1M option bit.\nTo obtain a dual bank flash memory, the last 512 Kbytes of the single bank (sectors \n[8:11]) are re-structured in the same way as the first 512 Kbytes. \nThe sector numbering of dual bank memory organization is different from the single \nbank: the single bank memory contains 12 sectors whereas the dual bank memory \ncontains 16 sectors (see Table 7: 1 Mbyte flash memory single bank vs dual bank \norganization (STM32F42xxx and STM32F43xxx)). \nFor erase operation, the right sector numbering must be considered according the \nDB1M option bit.\n–\nWhen the DB1M bit is reset, the erase operation must be performed on the default \nsector number.\n–\nWhen the DB1M bit is set, to perform an erase operation on bank 2, the sector \nnumber must be programmed (sector number from 12 to 19). Refer to FLASH_CR \nregister for SNB (Sector number) configuration.\nRefer to Table 8: 1 Mbyte single bank flash memory organization (STM32F42xxx and \nSTM32F43xxx) and Table 9: 1 Mbyte dual bank flash memory organization (STM32F42xxx \nand STM32F43xxx) for details on 1 Mbyte single bank and 1 Mbyte dual bank \norganizations.\n\n\n<>\n\nRM0090 Rev 21\n77/1757\nRM0090\nEmbedded flash memory interface\n113\n \nTable 6. Flash module - 2 Mbyte dual bank organization (STM32F42xxx and STM32F43xxx)\nBlock\nBank\nName\nBlock base addresses\nSize\nMain memory\nBank 1\nSector 0\n0x0800 0000 - 0x0800 3FFF\n16 Kbytes\nSector 1\n0x0800 4000 - 0x0800 7FFF\n16 Kbytes\nSector 2\n0x0800 8000 - 0x0800 BFFF\n16 Kbytes\nSector 3\n0x0800 C000 - 0x0800 FFFF\n16 Kbyte\nSector 4\n0x0801 0000 - 0x0801 FFFF\n64 Kbytes\nSector 5\n0x0802 0000 - 0x0803 FFFF\n128 Kbytes\nSector 6\n0x0804 0000 - 0x0805 FFFF \n128 Kbytes\n .\n - \n - \n .\n - \n - \n - \n - \n - \nSector 11\n0x080E 0000 - 0x080F FFFF\n128 Kbytes\nBank 2\nSector 12\n0x0810 0000 - 0x0810 3FFF\n16 Kbytes\nSector 13\n0x0810 4000 - 0x0810 7FFF\n16 Kbytes\nSector 14\n0x0810 8000 - 0x0810 BFFF\n16 Kbytes\nSector 15\n0x0810 C000 - 0x0810 FFFF\n16 Kbytes\nSector 16\n0x0811 0000 - 0x0811 FFFF\n64 Kbytes\nSector 17\n0x0812 0000 - 0x0813 FFFF\n128 Kbytes\nSector 18\n0x0814 0000 - 0x0815 FFFF\n128 Kbytes\n.\n.\n.\n.\n.\n.\n.\n.\n.\nSector 23\n0x081E 0000 - 0x081F FFFF\n128 Kbytes\nSystem memory\n0x1FFF 0000 - 0x1FFF 77FF\n30 Kbytes\nOTP\n0x1FFF 7800 - 0x1FFF 7A0F\n528 bytes\nOption bytes \nBank 1\n0x1FFF C000 - 0x1FFF C00F \n16 bytes\nBank 2\n0x1FFE C000 - 0x1FFE C00F\n16 bytes\n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n78/1757\nRM0090 Rev 21\n \n \nTable 7. 1 Mbyte flash memory single bank vs dual bank organization\n (STM32F42xxx and STM32F43xxx)\n 1 Mbyte single bank flash memory (default)\n1 Mbyte dual bank flash memory\nDB1M=0\nDB1M=1\nMain memory\nSector number\nSector size\nMain memory\nSector number\nSector size\n1MB\nSector 0\n16 Kbytes\nBank 1\n512KB\nSector 0\n16 Kbytes\nSector 1\n16 Kbytes\nSector 1\n16 Kbytes\nSector 2\n16 Kbytes\nSector 2\n16 Kbytes\nSector 3\n16 Kbytes\nSector 3\n16 Kbytes\nSector 4\n64 Kbytes\nSector 4\n64 Kbytes\nSector 5\n128 Kbytes\nSector 5\n128 Kbytes\nSector 6\n128 Kbytes\nSector 6\n128 Kbytes\nSector 7\n128 Kbytes\nSector 7\n128 Kbytes\nSector 8\n128 Kbytes\nBank 2\n512KB\nSector 12\n16 Kbytes\nSector 9\n128 Kbytes\nSector 13\n16 Kbytes\nSector 10\n128 Kbytes\nSector 14\n16 Kbytes\nSector 11\n128 Kbytes\nSector 15\n16 Kbytes\n-\n-\nSector 16\n64 Kbytes\n-\n-\nSector 17\n128 Kbytes\n-\n-\nSector 18\n128 Kbytes\n-\n-\nSector 19\n128 Kbytes\nTable 8. 1 Mbyte single bank flash memory organization\n(STM32F42xxx and STM32F43xxx)\nBlock\nBank\nName\nBlock base addresses\nSize\nMain memory\nSingle bank \nSector 0\n0x0800 0000 - 0x0800 3FFF\n16 Kbytes\nSector 1\n0x0800 4000 - 0x0800 7FFF\n16 Kbytes\nSector 2\n0x0800 8000 - 0x0800 BFFF\n16 Kbytes\nSector 3\n0x0800 C000 - 0x0800 FFFF\n16 Kbytes\nSector 4\n0x0801 0000 - 0x0801 FFFF\n64 Kbytes\nSector 5\n0x0802 0000 - 0x0803 FFFF\n128 Kbytes\nSector 6\n0x0804 0000 - 0x0805 FFFF \n128 Kbytes\nSector 7\n0x0806 0000 - 0x0807 FFFF \n128 Kbytes\nSector 8\n0x0808 0000 - 0x0809 FFFF\n128 Kbytes\nSector 9\n0x080A 0000 - 0x080B FFFF\n128 Kbytes\nSector 10\n0x080C 0000 - 0x080D FFFF\n128 Kbytes\nSector 11\n0x080E 0000 - 0x080F FFFF\n128 Kbytes\n\n\n<>\n\nRM0090 Rev 21\n79/1757\nRM0090\nEmbedded flash memory interface\n113\n \nSystem memory\n0x1FFF 0000 - 0x1FFFF 77FF\n30 Kbytes\nOTP\n0x1FFF 7800 - 0x1FFF 7A0F\n528 bytes\nOption bytes \n0x1FFF C000 - 0x1FFF C00F \n16 bytes\n0x1FFE C000 - 0x1FFE C00F\n16 bytes\nTable 8. 1 Mbyte single bank flash memory organization\n(STM32F42xxx and STM32F43xxx) (continued)\nBlock\nBank\nName\nBlock base addresses\nSize\nTable 9. 1 Mbyte dual bank flash memory organization (STM32F42xxx and STM32F43xxx)\nBlock\nName\nBlock base addresses\nSize\nMain memory\nBank 1\nSector 0\n0x0800 0000 - 0x0800 3FFF\n16 Kbytes\nSector 1\n0x0800 4000 - 0x0800 7FFF\n16 Kbytes\nSector 2\n0x0800 8000 - 0x0800 BFFF\n16 Kbytes\nSector 3\n0x0800 C000 - 0x0800 FFFF\n16 Kbyte\nSector 4\n0x0801 0000 - 0x0801 FFFF\n64 Kbytes\nSector 5\n0x0802 0000 - 0x0803 FFFF\n128 Kbytes\nSector 6\n0x0804 0000 - 0x0805 FFFF \n128 Kbytes\n Sector 7\n0x0806 0000 - 0x0807 FFFF \n128 Kbytes\nBank 2\nSector 12\n0x0808 0000 - 0x0808 3FFF\n16 Kbytes\nSector 13\n0x0808 4000 - 0x0808 7FFF\n16 Kbytes\nSector 14\n0x0808 0000 - 0x0808 BFFF\n16 Kbytes\nSector 15\n0x0808 C000 - 0x0808 FFFF\n16 Kbytes\nSector 16\n0x0809 0000 - 0x0809 FFFF\n64 Kbytes\nSector 17\n0x080A 0000 - 0x080B FFFF\n128 Kbytes\nSector 18\n0x080C 0000 - 0x080D FFFF\n128 Kbytes\nSector 19\n0x080E 0000 - 0x080F FFFF\n128 Kbytes\nSystem memory\n0x1FFF 0000 - 0x1FFF 77FF\n30 Kbytes\nOTP\n0x1FFF 7800 - 0x1FFF 7A0F\n528 bytes\nOption bytes \nBank 1\n0x1FFF C000 - 0x1FFF C00F \n16 bytes\nBank 2\n0x1FFE C000 - 0x1FFE C00F\n16 bytes\n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n80/1757\nRM0090 Rev 21\n \n3.5 \nRead interface\n3.5.1 \nRelation between CPU clock frequency and flash memory read time\nTo correctly read data from flash memory, the number of wait states (LATENCY) must be \ncorrectly programmed in the Flash access control register (FLASH_ACR) according to the \nfrequency of the CPU clock (HCLK) and the supply voltage of the device. \nThe prefetch buffer must be disabled when the supply voltage is below 2.1 V. The \ncorrespondence between wait states and CPU clock frequency is given in Table 11 and \nTable 12.\nNote:\nOn STM32F405xx/07xx and STM32F415xx/17xx devices: \n- when VOS = '0', the maximum value of fHCLK = 144 MHz. \n- when VOS = '1', the maximum value of fHCLK = 168 MHz. \nOn STM32F42xxx and STM32F43xxx devices:\n- when VOS[1:0] = '0x01', the maximum value of fHCLK is 120 MHz.\n- when VOS[1:0] = '0x10', the maximum value of fHCLK is 144 MHz. It can be extended to \n168 MHz by activating the over-drive mode.\n- when VOS[1:0] = '0x11, the maximum value of fHCLK is 168 MHz. It can be extended to \n180 MHz by activating the over-drive mode. \n- The over-drive mode is not available when VDD ranges from 1.8 to 2.1 V. \nRefer to Section 5.1.4: Voltage regulator for STM32F42xxx and STM32F43xxx for details on \nhow to activate the over-drive mode. \nTable 10. 512 Kbyte single bank flash memory organization\n(STM32F42xxx and STM32F43xxx)\nBlock\nBank\nName\n Block base addresses\nSize\nMain memory\nSingle Bank\nSector 0\n0x0800 0000 - 0x0800 3FFF\n16 Kbytes\nSector 1\n0x0800 4000 - 0x0800 7FFF\n16 Kbytes\nSector 2\n0x0800 8000 - 0x0800 BFFF\n16 Kbytes\nSector 3\n 0x0800 C000 - 0x0800 FFFF\n16 Kbytes\nSector 4\n0x0801 0000 - 0x0801 FFFF\n64 Kbytes\nSector 5\n0x0802 0000 - 0x0803 FFFF\n128 Kbytes\nSector 6\n0x0804 0000 - 0x0805 FFFF\n128 Kbytes\nSector 7\n0x0806 0000 - 0x0807 FFFF\n128 Kbytes\nSystem memory\n0x1FFF 0000 - 0x1FFFF 77FF\n30 Kbytes\nOTP\n0x1FFF 7800 - 0x1FFF 7A0F\n528 bytes\nOption bytes\n0x1FFF C000 - 0x1FFF C00F\n16 bytes\n0x1FFE C000 - 0x1FFE C00F\n16 bytes\n\n\n<>\n\nRM0090 Rev 21\n81/1757\nRM0090\nEmbedded flash memory interface\n113\nAfter reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is configured in the \nFLASH_ACR register.\nIt is highly recommended to use the following software sequences to tune the number of \nwait states needed to access the flash memory with the CPU frequency.\nTable 11. Number of wait states according to CPU clock (HCLK) frequency \n(STM32F405xx/07xx and STM32F415xx/17xx)\nWait states (WS)\n(LATENCY)\nHCLK (MHz)\nVoltage range\n2.7 V - 3.6 V\nVoltage range\n2.4 V - 2.7 V\nVoltage range\n2.1 V - 2.4 V\nVoltage range\n1.8 V - 2.1 V\nPrefetch OFF\n0 WS (1 CPU cycle)\n0 < HCLK ≤ 30\n0 < HCLK ≤ 24\n0 < HCLK ≤ 22\n0 < HCLK ≤ 20\n1 WS (2 CPU cycles)\n30 < HCLK ≤ 60\n24 < HCLK ≤ 48\n22 < HCLK ≤ 44\n20 >\n\nEmbedded flash memory interface\nRM0090\n82/1757\nRM0090 Rev 21\nIncreasing the CPU frequency\n1.\nProgram the new number of wait states to the LATENCY bits in the FLASH_ACR \nregister\n2. \nCheck that the new number of wait states is taken into account to access the flash \nmemory by reading the FLASH_ACR register\n3. \nModify the CPU clock source by writing the SW bits in the RCC_CFGR register\n4. \nIf needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR\n5. \nCheck that the new CPU clock source or/and the new CPU clock prescaler value is/are \ntaken into account by reading the clock source status (SWS bits) or/and the AHB \nprescaler value (HPRE bits), respectively, in the RCC_CFGR register.\nDecreasing the CPU frequency\n1.\nModify the CPU clock source by writing the SW bits in the RCC_CFGR register\n2. \nIf needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR\n3. \nCheck that the new CPU clock source or/and the new CPU clock prescaler value is/are \ntaken into account by reading the clock source status (SWS bits) or/and the AHB \nprescaler value (HPRE bits), respectively, in the RCC_CFGR register\n4. \nProgram the new number of wait states to the LATENCY bits in FLASH_ACR\n5. \nCheck that the new number of wait states is used to access the flash memory by \nreading the FLASH_ACR register\nNote:\nA change in CPU clock configuration or wait state (WS) configuration may not be effective \nstraight away. To make sure that the current CPU clock frequency is the one you have \nconfigured, you can check the AHB prescaler factor and clock source status values. To \nmake sure that the number of WS you have programmed is effective, you can read the \nFLASH_ACR register.\n3.5.2 \nAdaptive real-time memory accelerator (ART Accelerator™)\nThe proprietary Adaptive real-time (ART) memory accelerator is optimized for STM32 \nindustry-standard Arm® Cortex®-M4 with FPU processors. It balances the inherent \nperformance advantage of the Arm® Cortex®-M4 with FPU over flash memory technologies, \nwhich normally requires the processor to wait for the flash memory at higher operating \nfrequencies. \nTo release the processor full performance, the accelerator implements an instruction \nprefetch queue and branch cache which increases program execution speed from the 128-\nbit flash memory. Based on CoreMark benchmark, the performance achieved thanks to the \nART accelerator is equivalent to 0 wait state program execution from flash memory at a \nCPU frequency up to 180 MHz.\nInstruction prefetch\nEach flash memory read operation provides 128 bits from either four instructions of 32 bits \nor 8 instructions of 16 bits according to the program launched. So, in case of sequential \ncode, at least four CPU cycles are needed to execute the previous read instruction line. \nPrefetch on the I-Code bus can be used to read the next sequential instruction line from the \nflash memory while the current instruction line is being requested by the CPU. Prefetch is \nenabled by setting the PRFTEN bit in the FLASH_ACR register. This feature is useful if at \nleast one wait state is needed to access the flash memory. \n\n\n<>\n\nRM0090 Rev 21\n83/1757\nRM0090\nEmbedded flash memory interface\n113\nFigure 5 shows the execution of sequential 32-bit instructions with and without prefetch \nwhen 3 WSs are needed to access the flash memory. \nFigure 5. Sequential 32-bit instruction execution\n@\n@\n@\n@\nF\nF\nF\nF\nD\nD\nD\nD\nE\nE\nE\nE\n@\n@\n@\n@\nF\nF\nF\nF\nD\nD\nD\nE\nE\n1\n1\n1\n1\n2\n2\n2\n2\n3\n3\n3\n3\n4\n4\n4\n4\n5\n5\n5\n5\n6\n6\n6\n6\n7\n7\n7\n8\n8\nRead ins 1, 2, 3, 4\nGives ins 1, 2, 3, 4\nRead ins 5, 6, 7, 8\nGives ins 5, 6, 7, 8\nins 1\nfetch\nins 2\nfetch\nins 3\nfetch\nins 4\nfetch\nins 5\nfetch\nins 6\nfetch\nins 7\nfetch\nins 8\nfetch\nWAIT\nWAIT\nD\nE\n4\n4\n@\n@\nF\nF\nF\nF\nD\nD\nD\nE\nE\n5\n5\n5\n6\n6\n6\n7\n7\n7\n8\n8\n@\n@\n@\n@\n@\nF\nF\nF\nF\nD\nD\nD\nE\nE\nWait data\n@\n1\n1\n1\n1\n2\n2\n2\n2\n3\n3\n3\n4\n4\n5\nE\n3\nRead ins 1, 2, 3, 4 Gives ins 1, 2, 3, 4\nGives ins 5, 6, 7, 8\nRead ins 5, 6, 7, 8\nRead ins 9, 10, ...\nins 4\nins 5\nfetch\nins 6 ins 7\nWithout prefetch\nWith prefetch\nF\nD\nE\n@\nCortex-M4 pipeline\nAHB protocol\n@ : address requested\nF: Fetch stage\nD: Decode stage\nE: Execute stage\nins 1\nfetch\nins 2\nfetch\nins 3\nfetch fetch\nfetch fetch\nins 8\nfetch\nMS31831V1\n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n84/1757\nRM0090 Rev 21\nWhen the code is not sequential (branch), the instruction may not be present in the currently \nused instruction line or in the prefetched instruction line. In this case (miss), the penalty in \nterms of number of cycles is at least equal to the number of wait states.\nInstruction cache memory\nTo limit the time lost due to jumps, it is possible to retain 64 lines of 128 bits in an instruction \ncache memory. This feature can be enabled by setting the instruction cache enable (ICEN) \nbit in the FLASH_ACR register. Each time a miss occurs (requested data not present in the \ncurrently used instruction line, in the prefetched instruction line or in the instruction cache \nmemory), the line read is copied into the instruction cache memory. If some data contained \nin the instruction cache memory are requested by the CPU, they are provided without \ninserting any delay. Once all the instruction cache memory lines have been filled, the LRU \n(least recently used) policy is used to determine the line to replace in the instruction memory \ncache. This feature is particularly useful in case of code containing loops.\nData management\nLiteral pools are fetched from flash memory through the D-Code bus during the execution \nstage of the CPU pipeline. The CPU pipeline is consequently stalled until the requested \nliteral pool is provided. To limit the time lost due to literal pools, accesses through the AHB \ndatabus D-Code have priority over accesses through the AHB instruction bus I-Code. \nIf some literal pools are frequently used, the data cache memory can be enabled by setting \nthe data cache enable (DCEN) bit in the FLASH_ACR register. This feature works like the \ninstruction cache memory, but the retained data size is limited to 8 rows of 128 bits.\nNote:\nData in user configuration sector are not cacheable.\n3.6 \nErase and program operations\nFor any flash memory program operation (erase or program), the CPU clock frequency \n(HCLK) must be at least 1 MHz. The contents of the flash memory are not guaranteed if a \ndevice reset occurs during a flash memory operation. \nAny attempt to read the flash memory on STM32F4xx while it is being written or erased, \ncauses the bus to stall. Read operations are processed correctly once the program \noperation has completed. This means that code or data fetches cannot be performed while \na write/erase operation is ongoing.\nOn STM32F42xxx and STM32F43xxx devices, two banks are available allowing read \noperation from one bank while a write/erase operation is performed to the other bank.\n3.6.1 \nUnlocking the Flash control register\nAfter reset, write is not allowed in the Flash control register (FLASH_CR) to protect the flash \nmemory against possible unwanted operations due, for example, to electric disturbances. \nThe following sequence is used to unlock this register:\n1.\nWrite KEY1 = 0x45670123 in the Flash key register (FLASH_KEYR)\n2. \nWrite KEY2 = 0xCDEF89AB in the Flash key register (FLASH_KEYR)\nAny wrong sequence returns a bus error and lock up the FLASH_CR register until the next \nreset.\n\n\n<>\n\nRM0090 Rev 21\n85/1757\nRM0090\nEmbedded flash memory interface\n113\nThe FLASH_CR register can be locked again by software by setting the LOCK bit in the \nFLASH_CR register.\nNote:\nThe FLASH_CR register is not accessible in write mode when the BSY bit in the FLASH_SR \nregister is set. Any attempt to write to it with the BSY bit set causes the AHB bus to stall until \nthe BSY bit is cleared.\n3.6.2 \nProgram/erase parallelism\nThe parallelism size is configured through the PSIZE field in the FLASH_CR register. It \nrepresents the number of bytes to be programmed each time a write operation occurs to the \nflash memory. PSIZE is limited by the supply voltage and by whether the external VPP \nsupply is used or not. It must therefore be correctly configured in the FLASH_CR register \nbefore any programming/erasing operation. \nA flash memory erase operation can only be performed by sector, bank or for the whole \nflash memory (mass erase). The erase time depends on PSIZE programmed value. For \nmore details on the erase time, refer to the electrical characteristics section of the device \ndatasheet.\nTable 13 provides the correct maximum PSIZE values. \n \nNote:\nAny program or erase operation started with inconsistent program parallelism/voltage range \nsettings may lead to unpredicted results. Even if a subsequent read operation indicates that \nthe logical value was effectively written to the memory, this value may not be retained.\nTo use VPP, an external high-voltage supply (between 8 and 9 V) must be applied to the VPP \npad. The external supply must be able to sustain this voltage range even if the DC \nconsumption exceeds 10 mA. It is advised to limit the use of VPP to initial programming on \nthe factory line. The VPP supply must not be applied for more than an hour, otherwise the \nflash memory might be damaged.\n3.6.3 \nErase\nThe flash memory erase operation can be performed at sector level or on the whole flash \nmemory (Mass Erase). Mass Erase does not affect the OTP sector or the configuration \nsector.\nSector Erase\nTo erase a sector, follow the procedure below:\nTable 13. Maximum program/erase parallelism\nVoltage range 2.7 - 3.6 V \nwith External VPP\nVoltage range\n2.7 - 3.6 V\nVoltage range\n2.4 - 2.7 V\nVoltage range\n2.1 - 2.4 V\nVoltage range\n1.8 V - 2.1 V\nMax. \nparallelism size\nx64\nx32\nx16\nx8\nPSIZE(1:0)\n11\n10\n01\n00\n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n86/1757\nRM0090 Rev 21\n1.\nCheck that no flash memory operation is ongoing by checking the BSY bit in the \nFLASH_SR register\n2. \nSet the SER bit and select the sector out of the 12 sectors (for STM32F405xx/07xx and \nSTM32F415xx/17xx) and out of 24 (for STM32F42xxx and STM32F43xxx) in the main \nmemory block you wish to erase (SNB) in the FLASH_CR register\n3. \nSet the STRT bit in the FLASH_CR register\n4. \nWait for the BSY bit to be cleared\nBank erase in STM32F42xxx and STM32F43xxx devices\nTo erase bank 1 or bank 2, follow the procedure below:\n1.\nCheck that no flash memory operation is ongoing by checking the BSY bit in the \nFLASH_SR register\n2. \nSet MER or MER1 bit accordingly in the FLASH_CR register\n3. \nSet the STRT bit in the FLASH_CR register\n4. \nWait for the BSY bit to be reset.\nMass Erase\nTo perform Mass Erase, the following sequence is recommended:\n1.\nCheck that no flash memory operation is ongoing by checking the BSY bit in the \nFLASH_SR register\n2. \nSet the MER bit in the FLASH_CR register (on STM32F405xx/07xx and \nSTM32F415xx/17xx devices)\n3. \nSet both the MER and MER1 bits in the FLASH_CR register (on STM32F42xxx and \nSTM32F43xxx devices).\n4. \nSet the STRT bit in the FLASH_CR register\n5. \nWait for the BSY bit to be cleared\nNote:\nIf MERx and SER bits are both set in the FLASH_CR register, mass erase is performed.\nIf both MERx and SER bits are reset and the STRT bit is set, an unpredictable behavior may \noccur without generating any error flag. This condition should be forbidden.\n3.6.4 \nProgramming\nStandard programming\nThe flash memory programming sequence is as follows:\n1.\nCheck that no main flash memory operation is ongoing by checking the BSY bit in the \nFLASH_SR register.\n2. \nSet the PG bit in the FLASH_CR register\n3. \nPerform the data write operation(s) to the desired memory address (inside main \nmemory block or OTP area):\n–\nByte access in case of x8 parallelism\n–\nHalf-word access in case of x16 parallelism\n–\nWord access in case of x32 parallelism\n–\nDouble word access in case of x64 parallelism\n4. \nWait for the BSY bit to be cleared.\n\n\n<>\n\nRM0090 Rev 21\n87/1757\nRM0090\nEmbedded flash memory interface\n113\nNote:\nSuccessive write operations are possible without the need of an erase operation when \nchanging bits from ‘1’ to ‘0’. Writing ‘1’ requires a flash memory erase operation.\nIf an erase and a program operation are requested simultaneously, the erase operation is \nperformed first. \nProgramming errors\nIt is not allowed to program data to the flash memory that would cross the 128-bit row \nboundary. In such a case, the write operation is not performed and a program alignment \nerror flag (PGAERR) is set in the FLASH_SR register.\nThe write access type (byte, half-word, word or double word) must correspond to the type of \nparallelism chosen (x8, x16, x32 or x64). If not, the write operation is not performed and a \nprogram parallelism error flag (PGPERR) is set in the FLASH_SR register.\nIf the standard programming sequence is not respected (for example, if there is an attempt \nto write to a flash memory address when the PG bit is not set), the operation is aborted and \na program sequence error flag (PGSERR) is set in the FLASH_SR register.\nProgramming and caches\nIf a flash memory write access concerns some data in the data cache, the Flash write \naccess modifies the data in the flash memory and the data in the cache.\nIf an erase operation in flash memory also concerns data in the data or instruction cache, \nyou have to make sure that these data are rewritten before they are accessed during code \nexecution. If this cannot be done safely, it is recommended to flush the caches by setting the \nDCRST and ICRST bits in the FLASH_CR register.\nNote:\nThe I/D cache should be flushed only when it is disabled (I/DCEN = 0).\n3.6.5 \nRead-while-write (RWW)\nIn STM32F42xxx and STM32F43xxx devices, the flash memory is divided into two banks \nallowing read-while-write operations. This feature allows to perform a read operation from \none bank while an erase or program operation is performed to the other bank. \nNote:\nWrite-while-write operations are not allowed. As an exampled, It is not possible to perform \nan erase operation on one bank while programming the other one.\nRead from bank 1 while erasing bank 2\nWhile executing a program code from bank 1, it is possible to perform an erase operation on \nbank 2 (and vice versa). Follow the procedure below:\n1.\nCheck that no flash memory operation is ongoing by checking the BSY bit in the \nFLASH_SR register (BSY is active when erase/program operation is on going to \nbank 1 or bank 2)\n2. \nSet MER or MER1 bit in the FLASH_CR register\n3. \nSet the STRT bit in the FLASH_CR register \n4. \nWait for the BSY bit to be reset (or use the EOP interrupt).\nRead from bank 1 while programming bank 2\nWhile executing a program code (over the I-Code bus) from bank 1,it is possible to perform \nan program operation to the bank 2 (and vice versa). Follow the procedure below:\n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n88/1757\nRM0090 Rev 21\n1.\nCheck that no flash memory operation is ongoing by checking the BSY bit in the \nFLASH_SR register (BSY is active when erase/program operation is on going on bank \n1 or bank 2) \n2. \nSet the PG bit in the FLASH_CR register\n3. \nPerform the data write operation(s) to the desired memory address inside main \nmemory block or OTP area\n4. \nWait for the BSY bit to be reset.\n3.6.6 \nInterrupts\nSetting the end of operation interrupt enable bit (EOPIE) in the FLASH_CR register enables \ninterrupt generation when an erase or program operation ends, that is when the busy bit \n(BSY) in the FLASH_SR register is cleared (operation completed, correctly or not). In this \ncase, the end of operation (EOP) bit in the FLASH_SR register is set.\nIf an error occurs during a program, an erase, or a read operation request, one of the \nfollowing error flags is set in the FLASH_SR register:\n•\nPGAERR, PGPERR, PGSERR (Program error flags)\n•\nWRPERR (Protection error flag)\n•\nRDERR (Read protection error flag) for STM32F42xxx and STM32F43xxx devices \nonly.\nIn this case, if the error interrupt enable bit (ERRIE) is set in the FLASH_CR register, an \ninterrupt is generated and the operation error bit (OPERR) is set in the FLASH_SR register.\nNote:\nIf several successive errors are detected (for example, in case of DMA transfer to the flash \nmemory), the error flags cannot be cleared until the end of the successive write requests.\n \n3.7 \nOption bytes\n3.7.1 \nDescription of user option bytes\nThe option bytes are configured by the end user depending on the application requirements. \nTable 15 shows the organization of these bytes inside the user configuration sector.\n \nTable 14. Flash interrupt request\nInterrupt event\nEvent flag\nEnable control bit\nEnd of operation\nEOP\nEOPIE\nWrite protection error\nWRPERR\nERRIE\nProgramming error \nPGAERR, PGPERR, PGSERR\nERRIE\nRead protection error\nRDERR\nERRIE\nTable 15. Option byte organization\nAddress\n[63:16]\n[15:0]\n0x1FFF C000\nReserved\nROP & user option bytes (RDP & USER)\n0x1FFF C008\nReserved\nSPRMOD and Write protection nWRP bits for \nsectors 0 to 11\n\n\n<>\n\nRM0090 Rev 21\n89/1757\nRM0090\nEmbedded flash memory interface\n113\n0x1FFE C000\nReserved\nReserved\n0x1FFE C008\nReserved\nSPRMOD and Write protection nWRP bits for \nsectors 12 to 23\nTable 16. Description of the option bytes (STM32F405xx/07xx and \nSTM32F415xx/17xx)\nOption bytes (word, address 0x1FFF C000)\nRDP: Read protection option byte.\nThe read protection is used to protect the software code stored in flash memory.\nBits 15:8\n0xAA: Level 0, no protection\n0xCC: Level 2, chip protection (debug and boot from RAM features disabled)\nOthers: Level 1, read protection of memories (debug features limited)\nUSER: User option byte\nThis byte is used to configure the following features:\n– Select the watchdog event: Hardware or software\n– Reset event when entering the Stop mode\n– Reset event when entering the Standby mode\nBit 7\nnRST_STDBY\n0: Reset generated when entering the Standby mode\n1: No reset generated\nBit 6\nnRST_STOP\n0: Reset generated when entering the Stop mode\n1: No reset generated\nBit 5\nWDG_SW\n0: Hardware independent watchdog\n1: Software independent watchdog\nBit 4\n0x1: Not used\nBits 3:2\nBOR_LEV: BOR reset Level \nThese bits contain the supply level threshold that activates/releases the reset. \nThey can be written to program a new BOR level value into flash memory. \n00: BOR Level 3 (VBOR3), brownout threshold level 3\n01: BOR Level 2 (VBOR2), brownout threshold level 2\n10: BOR Level 1 (VBOR1), brownout threshold level 1\n11: BOR off, POR/PDR reset threshold level is applied\nNote: For full details on BOR characteristics, refer to the “Electrical characteristics” \nsection of the product datasheet.\nBits 1:0\n0x3: Not used\nTable 15. Option byte organization (continued)\nAddress\n[63:16]\n[15:0]\n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n90/1757\nRM0090 Rev 21\n \nOption bytes (word, address 0x1FFF C008)\nBits 15:12\n0xF: Not used\nnWRP: Flash memory write protection option bytes\nSectors 0 to 11 can be write protected.\nBits 11:0\nnWRPi\n0: Write protection active on selected sector\n1: Write protection not active on selected sector\nTable 17. Description of the option bytes \n(STM32F42xxx and STM32F43xxx) \nOption bytes (word, address 0x1FFF C000)\nRDP: Read protection option byte.\nThe read protection is used to protect the software code stored in flash memory.\nBit 15:8\n0xAA: Level 0, no protection\n0xCC: Level 2, chip protection (debug and boot from RAM features disabled)\nOthers: Level 1, read protection of memories (debug features limited)\nUSER: User option byte\nThis byte is used to configure the following features:\nSelect the watchdog event: Hardware or software\nReset event when entering the Stop mode\nReset event when entering the Standby mode\nBit 7\nnRST_STDBY\n0: Reset generated when entering the Standby mode\n1: No reset generated\nBit 6\nnRST_STOP\n0: Reset generated when entering the Stop mode\n1: No reset generated\nBit 5\nWDG_SW\n0: Hardware independent watchdog\n1: Software independent watchdog\nBit 4\nBFB2: Dual bank boot\n0: Boot from flash memory bank 1 or system memory depending on boot pin state \n(Default).\n1: Boot always from system memory (Dual bank boot mode).\nTable 16. Description of the option bytes (STM32F405xx/07xx and \nSTM32F415xx/17xx) (continued)\n\n\n<>\n\nRM0090 Rev 21\n91/1757\nRM0090\nEmbedded flash memory interface\n113\nBits 3:2\nBOR_LEV: BOR reset Level\nThese bits contain the supply level threshold that activates/releases the reset.\nThey can be written to program a new BOR level value into flash memory.\n00: BOR Level 3 (VBOR3), brownout threshold level 3\n01: BOR Level 2 (VBOR2), brownout threshold level 2\n10: BOR Level 1 (VBOR1), brownout threshold level 1\n11: BOR off, POR/PDR reset threshold level is applied\nNote: For full details on BOR characteristics, refer to the “Electrical characteristics” \nsection of the product datasheet.\nBits 1:0\n0x3: Not used\nOption bytes (word, address 0x1FFF C008)\nBit 15\nSPRMOD: Selection of protection mode of nWPRi bits\n0: nWPRi bits used for sector i write protection (Default)\n1: nWPRi bits used for sector i PCROP protection (Sector) \nBit 14\nDB1M: Dual bank 1 Mbyte flash memory devices\n0: 1 Mbyte single flash memory (contiguous addresses in bank 1)\n1: 1 Mbyte dual bank flash memory. The flash memory is organized as two banks of \n512 Kbytes each (see Table 7: 1 Mbyte flash memory single bank vs dual bank \norganization (STM32F42xxx and STM32F43xxx) and Table 9: 1 Mbyte dual bank \nflash memory organization (STM32F42xxx and STM32F43xxx)). To perform an erase \noperation, the right sector must be programmed (see Table 7 for information on the \nsector numbering scheme).\nBits 13:12\n0x3: not used\nnWRP: Flash memory write protection option bytes for bank 1. Sectors 0 to 11 can be write \nprotected.\nBits 11:0\nnWRPi:\nIf SPRMOD is reset (default value):\n0: Write protection active on sector i. \n1: Write protection not active on sector i. \nIf SPRMOD is set (active):\n0: PCROP protection not active on sector i.\n1: PCROP protection active on sector i.\nOption bytes (word, address 0x1FFE C000)\nBit 15:0\n0xFFFF: not used\nTable 17. Description of the option bytes \n(STM32F42xxx and STM32F43xxx) (continued) \n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n92/1757\nRM0090 Rev 21\n3.7.2 \nProgramming user option bytes\nTo run any operation on this sector, the option lock bit (OPTLOCK) in the Flash option \ncontrol register (FLASH_OPTCR) must be cleared. To be allowed to clear this bit, you have \nto perform the following sequence:\n1.\nWrite OPTKEY1 = 0x0819 2A3B in the Flash option key register (FLASH_OPTKEYR)\n2. \nWrite OPTKEY2 = 0x4C5D 6E7F in the Flash option key register (FLASH_OPTKEYR)\nThe user option bytes can be protected against unwanted erase/program operations by \nsetting the OPTLOCK bit by software.\nModifying user option bytes on STM32F405xx/07xx and STM32F415xx/17xx\nTo modify the user option value, follow the sequence below:\n1.\nCheck that no flash memory operation is ongoing by checking the BSY bit in the \nFLASH_SR register\n2. \nWrite the desired option value in the FLASH_OPTCR register.\n3. \nSet the option start bit (OPTSTRT) in the FLASH_OPTCR register\n4. \nWait for the BSY bit to be cleared.\nNote:\nThe value of an option is automatically modified by first erasing the user configuration sector \nand then programming all the option bytes with the values contained in the FLASH_OPTCR \nregister.\nModifying user option bytes on STM32F42xxx and STM32F43xxx\nThe user option bytes for bank 1 and bank 2 cannot be modified independently. They must \nbe updated concurrently. \nTo modify the user option byte value, follow the sequence below:\n1.\nCheck that no flash memory operation is ongoing by checking the BSY bit in the \nFLASH_SR register\n2. \nWrite the bank 2 option byte value in the FLASH_OPTCR1 register\n3. \nWrite the bank 1 option byte value in the FLASH_OPTCR register.\n4. \nSet the option start bit (OPTSTRT) in the FLASH_OPTCR register\n5. \nWait for the BSY bit to be cleared\nOption bytes (word, address 0x1FFE C008)\nBit 15:12\n0xF: not used\nnWRP: Flash memory write protection option bytes for bank 2. Sectors 12 to 23 can be write \nprotected.\nBits 11: 0\nnWRPi:\nIf SPRMOD is reset (default value):\n0: Write protection active on sector i. \n1: Write protection not active on sector i. \nIf SPRMOD is set (active):\n0: PCROP protection not active on sector i.\n1: PCROP protection active on sector i.\nTable 17. Description of the option bytes \n(STM32F42xxx and STM32F43xxx) (continued) \n\n\n<>\n\nRM0090 Rev 21\n93/1757\nRM0090\nEmbedded flash memory interface\n113\nNote:\nThe value of an option byte is automatically modified by first erasing the user configuration \nsector (bank 1 and 2) and then programming all the option bytes with the values contained \nin the FLASH_OPTCR and FLASH_OPTCR1 registers.\n3.7.3 \nRead protection (RDP)\nThe user area in the flash memory can be protected against read operations by an \nentrusted code. Three read protection levels are defined:\n•\nLevel 0: no read protection\nWhen the read protection level is set to Level 0 by writing 0xAA into the read protection \noption byte (RDP), all read/write operations (if no write protection is set) from/to the \nflash memory or the backup SRAM are possible in all boot configurations (Flash user \nboot, debug or boot from RAM).\n•\nLevel 1: read protection enabled\nIt is the default read protection level after option byte erase. The read protection Level \n1 is activated by writing any value (except for 0xAA and 0xCC used to set Level 0 and \nLevel 2, respectively) into the RDP option byte. When the read protection Level 1 is set:\n–\nNo access (read, erase, program) to flash memory or backup SRAM can be \nperformed while the debug feature is connected or while booting from RAM or \nsystem memory bootloader. A bus error is generated in case of read request. \n–\nWhen booting from flash memory, accesses (read, erase, program) to flash \nmemory and backup SRAM from user code are allowed. \nWhen Level 1 is active, programming the protection option byte (RDP) to Level 0 \ncauses the flash memory and the backup SRAM to be mass-erased. As a result the \nuser code area is cleared before the read protection is removed. The mass erase only \nerases the user code area. The other option bytes including write protections remain \nunchanged from before the mass-erase operation. The OTP area is not affected by \nmass erase and remains unchanged. Mass erase is performed only when Level 1 is \nactive and Level 0 requested. When the protection level is increased (0->1, 1->2, 0->2) \nthere is no mass erase.\n•\nLevel 2: debug/chip read protection disabled\nThe read protection Level 2 is activated by writing 0xCC to the RDP option byte. When \nthe read protection Level 2 is set:\n–\nAll protections provided by Level 1 are active. \n–\nBooting from RAM or system memory bootloader is no more allowed.\n–\nJTAG, SWV (single-wire viewer), ETM, and boundary scan are disabled.\n–\nUser option bytes can no longer be changed.\n–\nWhen booting from flash memory, accesses (read, erase and program) to flash \nmemory and backup SRAM from user code are allowed.\nMemory read protection Level 2 is an irreversible operation. When Level 2 is activated, \nthe level of protection cannot be decreased to Level 0 or Level 1.\n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n94/1757\nRM0090 Rev 21\nNote:\nIf the read protection is set while the debugger is still connected (or has been connected \nsince the last power-on) through JTAG/SWD, apply a POR (power-on reset) instead of a \nsystem reset. \nIf the read protection is programmed by software (executing from SRAM), perform a POR to \nreload the option byte and clear the detected intrusion. This can be done with a transition \nStandby mode followed by a wake-up.\nThe JTAG port is permanently disabled when Level 2 is active (acting as a JTAG fuse). As a \nconsequence, boundary scan cannot be performed. STMicroelectronics is not able to \nperform analysis on defective parts on which the Level 2 protection has been set. \n\n\n<>\n\nRM0090 Rev 21\n95/1757\nRM0090\nEmbedded flash memory interface\n113\n --\nFigure 6 shows how to go from one RDP level to another.\nFigure 6. RDP levels\n3.7.4 \nWrite protections\nUp to 24 user sectors in flash memory can be protected against unwanted write operations \ndue to loss of program counter contexts. When the non-write protection nWRPi bit (0 ≤i ≤11) \nin the FLASH_OPTCR or FLASH_OPTCR1 registers is low, the corresponding sector \nTable 18. Access versus read protection level\nMemory area\nProtection \nLevel\nDebug features, Boot from RAM or \nfrom System memory bootloader \nBooting from flash memory\nRead \nWrite \nErase \nRead \nWrite \nErase \nMain Flash Memory \nand Backup SRAM\nLevel 1\nNO\nNO(1)\nYES\nLevel 2\nNO\nYES\nOption Bytes\nLevel 1\nYES\nYES\nLevel 2\nNO\nNO\nOTP\nLevel 1\nNO\nNA\nYES\nNA\nLevel 2\nNO\nNA\nYES\nNA\n1.\nThe main flash memory and backup SRAM are only erased when the RDP changes from level 1 to 0. The OTP area \nremains unchanged.\nLevel 1\nRDP /= AAh\nRDP /= CCh\ndefault\nOptions write (RDP level increase) includes\n- Options erase\n- New options program\nOptions write (RDP level decrease) includes\n- Mass erase\n- Options erase\n- New options program\nOptions write (RDP level identical) includes\n- Options erase\n- New options program\nRDP = AAh\nOthers option(s) modified\nRDP /= AAh & /= CCh\nOthers options modified\nWrite options\nincluding\nRDP = AAh\nWrite options\nincluding\nRDP = CCh\nWrite options\nincluding\nRDP = CCh\nWrite options including\nRDP /= CCh & /= AAh\nLevel 2\nRDP = CCh\nLevel 0 \nRDP = AAh\nMS47541V1\n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n96/1757\nRM0090 Rev 21\ncannot be erased or programmed. Consequently, a mass erase cannot be performed if one \nof the sectors is write-protected.\nIf an erase/program operation to a write-protected part of the flash memory is attempted \n(sector protected by write protection bit, OTP part locked or part of the flash memory that \ncan never be written like the ICP), the write protection error flag (WRPERR) is set in the \nFLASH_SR register.\nOn STM32F42xxx and STM32F43xxx devices, when the PCROP mode is set, the active \nlevel of nWRPi is high, and the corresponding sector i is write protected when nWRPi is \nhigh. A PCROP sector is automatically write protected.\nNote:\nWhen the memory read protection level is selected (RDP level = 1), it is not possible to \nprogram or erase flash memory sector i if the CPU debug features are connected (JTAG or \nsingle wire) or boot code is being executed from RAM, even if nWRPi = 1.\nWrite protection error flag\nIf an erase/program operation to a write protected area of the flash memory is performed, \nthe Write Protection Error flag (WRPERR) is set in the FLASH_SR register.\nIf an erase operation is requested, the WRPERR bit is set when:\n•\nMass, bank, sector erase are configured (MER or MER/MER1 and SER = 1)\n•\nA sector erase is requested and the Sector Number SNB field is not valid\n•\nA mass erase is requested while at least one of the user sector is write protected by \noption bit (MER or MER/MER1 = 1 and nWRPi = 0 with 0 ≤ i ≤ 11 bits in the \nFLASH_OPTCRx register\n•\nA sector erase is requested on a write protected sector. (SER = 1, SNB = i and \nnWRPi = 0 with 0 ≤ i ≤ 11 bits in the FLASH_OPTCRx register) \n•\nThe flash memory is readout protected and an intrusion is detected.\nIf a program operation is requested, the WRPERR bit is set when:\n•\nA write operation is performed on system memory or on the reserved part of the user \nspecific sector. \n•\nA write operation is performed to the user configuration sector\n•\nA write operation is performed on a sector write protected by option bit.\n•\nA write operation is requested on an OTP area which is already locked\n•\nThe flash memory is read protected and an intrusion is detected.\n3.7.5 \nProprietary code readout protection (PCROP)\nThe proprietary readout protection (PCROP) is available only on STM32F42xxx and \nSTM32F43xxx devices. \nFlash memory user sectors (0 to 23) can be protected against D-bus read accesses by \nusing the proprietary readout protection (PCROP). \nThe PCROP protection is selected as follows, through the SPRMOD option bit in the \nFLASH_OPTCR register:\n•\nSPRMOD = 0: nWRPi control the write protection of respective user sectors\n•\nSPRMOD = 1: nWRPi control the read and write protection (PCROP) of respective \nuser sectors. \n\n\n<>\n\nRM0090 Rev 21\n97/1757\nRM0090\nEmbedded flash memory interface\n113\nWhen a sector is readout protected (PCROP mode activated), it can only be accessed for \ncode fetch through ICODE Bus on Flash interface:\n•\nAny read access performed through the D-bus triggers a RDERR flag error.\n•\nAny program/erase operation on a PCROPed sector triggers a WRPERR flag error.\nFigure 7. PCROP levels\nThe deactivation of the SPRMOD and/or the unprotection of PCROPed user sectors can \nonly occur when, at the same time, the RDP level changes from 1 to 0. If this condition is not \nrespected, the user option byte modification is cancelled and the write error WRPERR flag \nis set. The modification of the users option bytes (BOR_LEV, RST_STDBY, ..) is allowed \nsince none of the active nWRPi bits is reset and SPRMOD is kept active.\nNote:\nThe active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).\nIf SPRMOD = 1 and nWRPi =1, then user sector i of bank 1, respectively bank 2 is \nread/write protected (PCROP).\nLevel 1\nLevel 2\nRDP = 0xCC\nRDP /= 0xAA\nRDP /= 0xCC\ndefault\nUser option sector erase \nProgram new options\nGlobal mass erase \nUser option section erase\nProgram new options \nWrite options\nSPMOD = active\nand valid nWRPi*\nNo restriction on \nWrite options\nWrite options\nSPMOD = active\nand valid nWRPi* \nLevel 0\nRDP = 0xAA\nWrite options\nSPMOD = active\nand valid nWRPi* \nWrite options\nSPMOD = active\nand valid nWRPi*\nWrite options\nSPMOD = active\nand valid nWRPi*\n* Valid nWRPi means that none of the nWRP bits set can be reset (transition from 1 to 0)\nMS30467V1\n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n98/1757\nRM0090 Rev 21\n3.8 \nOne-time programmable bytes\nTable 19 shows the organization of the one-time programmable (OTP) part of the OTP area.\n \nThe OTP area is divided into 16 OTP data blocks of 32 bytes and one lock OTP block of 16 \nbytes. The OTP data and lock blocks cannot be erased. The lock block contains 16 bytes \nLOCKBi (0 ≤ i ≤ 15) to lock the corresponding OTP data block (blocks 0 to 15). Each OTP \ndata block can be programmed until the value 0x00 is programmed in the corresponding \nOTP lock byte. The lock bytes must only contain 0x00 and 0xFF values, otherwise the OTP \nbytes might not be taken into account correctly.\nTable 19. OTP area organization\nBlock\n[128:96]\n[95:64]\n[63:32]\n[31:0]\nAddress byte 0\n0\nOTP0\nOTP0\nOTP0\nOTP0\n0x1FFF 7800\nOTP0\nOTP0\nOTP0\nOTP0\n0x1FFF 7810\n1\nOTP1\nOTP1\nOTP1\nOTP1\n0x1FFF 7820\nOTP1\nOTP1\nOTP1\nOTP1\n0x1FFF 7830\n.\n.\n.\n.\n.\n.\n.\n.\n.\n15\nOTP15\nOTP15\nOTP15\nOTP15\n0x1FFF 79E0\nOTP15\nOTP15\nOTP15\nOTP15\n0x1FFF 79F0\nLock block\nLOCKB15 ... \nLOCKB12\nLOCKB11 ... \nLOCKB8\nLOCKB7 ... \nLOCKB4\nLOCKB3 ... \nLOCKB0\n0x1FFF 7A00\n\n\n<>\n\nRM0090 Rev 21\n99/1757\nRM0090\nEmbedded flash memory interface\n113\n3.9 \nFlash interface registers\n3.9.1 \nFlash access control register (FLASH_ACR) \nfor STM32F405xx/07xx and STM32F415xx/17xx\nThe Flash access control register is used to enable/disable the acceleration features and \ncontrol the flash memory access time according to CPU frequency.\nAddress offset: 0x00\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDCRST\nICRST\nDCEN\nICEN\nPRFTEN\nReserved\nLATENCY[2:0]\nrw\nw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:13 Reserved, must be kept cleared.\nBit 12 DCRST: Data cache reset\n0: Data cache is not reset\n1: Data cache is reset\nThis bit can be written only when the D cache is disabled.\nBit 11 ICRST: Instruction cache reset\n0: Instruction cache is not reset\n1: Instruction cache is reset\nThis bit can be written only when the I cache is disabled.\nBit 10 DCEN: Data cache enable\n0: Data cache is disabled\n1: Data cache is enabled\nBit 9 ICEN: Instruction cache enable\n0: Instruction cache is disabled\n1: Instruction cache is enabled\nBit 8 PRFTEN: Prefetch enable\n0: Prefetch is disabled\n1: Prefetch is enabled\nBits 7:3 Reserved, must be kept cleared.\nBits 2:0 LATENCY[2:0]: Latency\nThese bits represent the ratio of the CPU clock period to the flash memory access time.\n000: Zero wait state\n001: One wait state\n010: Two wait states\n011: Three wait states\n100: Four wait states\n101: Five wait states\n110: Six wait states\n111: Seven wait states\n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n100/1757\nRM0090 Rev 21\n3.9.2 \nFlash access control register (FLASH_ACR) \nfor STM32F42xxx and STM32F43xxx\nThe Flash access control register is used to enable/disable the acceleration features and \ncontrol the flash memory access time according to CPU frequency.\nAddress offset: 0x00\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDCRST\nICRST\nDCEN\nICEN\nPRFTEN\nReserved\nLATENCY[3:0]\nrw\nw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:13 Reserved, must be kept cleared.\nBit 12 DCRST: Data cache reset\n0: Data cache is not reset\n1: Data cache is reset\nThis bit can be written only when the D cache is disabled.\nBit 11 ICRST: Instruction cache reset\n0: Instruction cache is not reset\n1: Instruction cache is reset\nThis bit can be written only when the I cache is disabled.\nBit 10 DCEN: Data cache enable\n0: Data cache is disabled\n1: Data cache is enabled\nBit 9 ICEN: Instruction cache enable\n0: Instruction cache is disabled\n1: Instruction cache is enabled\nBit 8 PRFTEN: Prefetch enable\n0: Prefetch is disabled\n1: Prefetch is enabled\nBits 7:4 Reserved, must be kept cleared.\nBits 3:0 LATENCY[3:0]: Latency\nThese bits represent the ratio of the CPU clock period to the flash memory access time.\n0000: Zero wait state\n0001: One wait state\n0010: Two wait states\n...\n1110: Fourteen wait states\n1111: Fifteen wait states\n\n\n<>\n\nRM0090 Rev 21\n101/1757\nRM0090\nEmbedded flash memory interface\n113\n3.9.3 \nFlash key register (FLASH_KEYR)\nThe Flash key register is used to allow access to the Flash control register and so, to allow \nprogram and erase operations.\nAddress offset: 0x04\nReset value: 0x0000 0000\nAccess: no wait state, word access\n \n \n3.9.4 \nFlash option key register (FLASH_OPTKEYR)\nThe Flash option key register is used to allow program and erase operations in the user \nconfiguration sector.\nAddress offset: 0x08\nReset value: 0x0000 0000\nAccess: no wait state, word access\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nKEY[31:16]\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nKEY[15:0]\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBits 31:0 FKEYR[31:0]: FPEC key\nThe following values must be programmed consecutively to unlock the FLASH_CR register \nand allow programming/erasing it:\na) \nKEY1 = 0x45670123 \nb) \nKEY2 = 0xCDEF89AB \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nOPTKEYR[31:16\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOPTKEYR[15:0]\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBits 31:0 OPTKEYR[31:0]: Option byte key\nThe following values must be programmed consecutively to unlock the FLASH_OPTCR \nregister and allow programming it:\na) \nOPTKEY1 = 0x08192A3B \nb) \nOPTKEY2 = 0x4C5D6E7F \n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n102/1757\nRM0090 Rev 21\n3.9.5 \nFlash status register (FLASH_SR) for \nSTM32F405xx/07xx and STM32F415xx/17xx \nThe Flash status register gives information on ongoing program and erase operations.\nAddress offset: 0x0C\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nBSY\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPGSERR PGPERR PGAERR WRPERR\nReserved\nOPERR\nEOP\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nBits 31:17 Reserved, must be kept cleared.\nBit 16 BSY: Busy\nThis bit indicates that a flash memory operation is in progress. It is set at the beginning of a \nflash memory operation and cleared when the operation finishes or an error occurs.\n0: no flash memory operation ongoing\n1: Flash memory operation ongoing\nBits 15:8 Reserved, must be kept cleared.\nBit 7 PGSERR: Programming sequence error\nSet by hardware when a write access to the flash memory is performed by the code while the \ncontrol register has not been correctly configured.\nCleared by writing 1.\nBit 6 PGPERR: Programming parallelism error\nSet by hardware when the size of the access (byte, half-word, word, double word) during the \nprogram sequence does not correspond to the parallelism configuration PSIZE (x8, x16, x32, \nx64).\nCleared by writing 1.\nBit 5 PGAERR: Programming alignment error\nSet by hardware when the data to program cannot be contained in the same 128-bit flash \nmemory row.\nCleared by writing 1.\nBit 4 WRPERR: Write protection error\nSet by hardware when an address to be erased/programmed belongs to a write-protected part \nof the flash memory.\nCleared by writing 1.\n\n\n<>\n\nRM0090 Rev 21\n103/1757\nRM0090\nEmbedded flash memory interface\n113\n \n3.9.6 \nFlash status register (FLASH_SR) for \nSTM32F42xxx and STM32F43xxx\nThe Flash status register gives information on ongoing program and erase operations.\nAddress offset: 0x0C\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n \n \nBits 3:2 Reserved, must be kept cleared.\nBit 1 OPERR: Operation error\nSet by hardware when a flash operation (programming / erase /read) request is detected and \ncan not be run because of parallelism, alignment, or write protection error. This bit is set only if \nerror interrupts are enabled (ERRIE = 1).\nBit 0 EOP: End of operation\nSet by hardware when one or more flash memory operations (program/erase) has/have \ncompleted successfully. It is set only if the end of operation interrupts are enabled (EOPIE = 1).\nCleared by writing a 1.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nBSY\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRDERR PGSERR PGPERR PGAERR WRPERR\nReserved\nOPERR\nEOP\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nBits 31:17 Reserved, must be kept cleared.\nBit 16 BSY: Busy\nThis bit indicates that a flash memory operation is in progress to/from one bank. It is set at the \nbeginning of a flash memory operation and cleared when the operation finishes or an error \noccurs.\n0: no flash memory operation ongoing\n1: Flash memory operation ongoing\nBits 15:9 Reserved, must be kept cleared.\nBit 8 RDERR: Proprietary readout protection (PCROP) error\nSet by hardware when a read access through the D-bus is performed to an address belonging \nto a proprietary readout protected Flash sector. \nCleared by writing 1.\nBit 7 PGSERR: Programming sequence error\nSet by hardware when a write access to the flash memory is performed by the code while the \ncontrol register has not been correctly configured.\nCleared by writing 1.\n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n104/1757\nRM0090 Rev 21\n \n3.9.7 \nFlash control register (FLASH_CR) for \nSTM32F405xx/07xx and STM32F415xx/17xx\nThe Flash control register is used to configure and start flash memory operations.\nAddress offset: 0x10\nReset value: 0x8000 0000\nAccess: no wait state when no flash memory operation is ongoing, word, half-word and byte \naccess.\n \nBit 6 PGPERR: Programming parallelism error\nSet by hardware when the size of the access (byte, half-word, word, double word) during the \nprogram sequence does not correspond to the parallelism configuration PSIZE (x8, x16, x32, \nx64).\nCleared by writing 1.\nBit 5 PGAERR: Programming alignment error\nSet by hardware when the data to program cannot be contained in the same 128-bit flash \nmemory row.\nCleared by writing 1.\nBit 4 WRPERR: Write protection error\nSet by hardware when an address to be erased/programmed belongs to a write-protected part \nof the flash memory.\nCleared by writing 1.\nBits 3:2 Reserved, must be kept cleared.\nBit 1 OPERR: Operation error\nSet by hardware when a flash operation (programming/erase/read) request is detected and \ncan not be run because of parallelism, alignment, write or read (PCROP) protection error. This \nbit is set only if error interrupts are enabled (ERRIE = 1).\nBit 0 EOP: End of operation\nSet by hardware when one or more flash memory operations (program/erase) has/have \ncompleted successfully. It is set only if the end of operation interrupts are enabled (EOPIE = 1).\nCleared by writing a 1.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nLOCK\nReserved\nERRIE\nEOPIE\nReserved\nSTRT\nrs\nrw\nrw\nrs\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPSIZE[1:0]\nRes.\nSNB[3:0]\nMER\nSER\nPG\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n105/1757\nRM0090\nEmbedded flash memory interface\n113\n \nBit 31 LOCK: Lock\nWrite to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is \ncleared by hardware after detecting the unlock sequence.\nIn the event of an unsuccessful unlock operation, this bit remains set until the next reset.\nBits 30:26 Reserved, must be kept cleared.\nBit 25 ERRIE: Error interrupt enable\nThis bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is set \nto 1.\n0: Error interrupt generation disabled\n1: Error interrupt generation enabled\nBit 24 EOPIE: End of operation interrupt enable\nThis bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes to \n1.\n0: Interrupt generation disabled\n1: Interrupt generation enabled\nBits 23:17 Reserved, must be kept cleared.\nBit 16 STRT: Start\nThis bit triggers an erase operation when set. It is set only by software and cleared when the \nBSY bit is cleared.\nBits 15:10 Reserved, must be kept cleared.\nBits 9:8 PSIZE[1:0]: Program size\nThese bits select the program parallelism.\n00 program x8\n01 program x16\n10 program x32\n11 program x64\nBit 7 Reserved, must be kept cleared.\nBits 6:3 SNB[3:0]: Sector number\nThese bits select the sector to erase.\n0000 sector 0\n0001 sector 1\n...\n1011 sector 11\nOthers not allowed\nBit 2 MER: Mass Erase\nErase activated for all user sectors.\nBit 1 SER: Sector Erase\nSector Erase activated.\nBit 0 PG: Programming\nFlash programming activated.\n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n106/1757\nRM0090 Rev 21\n3.9.8 \nFlash control register (FLASH_CR) for \nSTM32F42xxx and STM32F43xxx\nThe Flash control register is used to configure and start flash memory operations.\nAddress offset: 0x10\nReset value: 0x8000 0000\nAccess: no wait state when no flash memory operation is ongoing, word, half-word and byte \naccess.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nLOCK\nReserved\nERRIE\nEOPIE\nReserved\nSTRT\nrs\nrw\nrw\nrs\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMER1\nReserved\nPSIZE[1:0]\nSNB[4:0]\nMER\nSER\nPG\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 LOCK: Lock\nWrite to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is \ncleared by hardware after detecting the unlock sequence.\nIn the event of an unsuccessful unlock operation, this bit remains set until the next reset.\nBits 30:26 Reserved, must be kept cleared.\nBit 25 ERRIE: Error interrupt enable\nThis bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is set \nto 1.\n0: Error interrupt generation disabled\n1: Error interrupt generation enabled\nBit 24 EOPIE: End of operation interrupt enable\nThis bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes to \n1.\n0: Interrupt generation disabled\n1: Interrupt generation enabled\nBits 23:17 Reserved, must be kept cleared.\nBit 16 STRT: Start\nThis bit triggers an erase operation when set. It is set only by software and cleared when the \nBSY bit is cleared.\nBit 15 MER1: Mass Erase of bank 2 sectors\nErase activated for bank 2 user sectors 12 to 23.\nBits 14:10 Reserved, must be kept cleared.\nBits 9:8 PSIZE[1:0]: Program size\nThese bits select the program parallelism.\n00 program x8\n01 program x16\n10 program x32\n11 program x64\n\n\n<>\n\nRM0090 Rev 21\n107/1757\nRM0090\nEmbedded flash memory interface\n113\n3.9.9 \nFlash option control register (FLASH_OPTCR) for \nSTM32F405xx/07xx and STM32F415xx/17xx\nThe FLASH_OPTCR register is used to modify the user option bytes.\nAddress offset: 0x14\nReset value: 0x0FFF AAED. The option bits are loaded with values from flash memory at \nreset release.\nAccess: no wait state when no flash memory operation is ongoing, word, half-word and byte \naccess.\n \nBits 7:3 SNB[3:0]: Sector number\nThese bits select the sector to erase.\n0000: sector 0\n0001: sector 1\n...\n01011: sector 11\n01100: not allowed\n01101: not allowed\n01110: not allowed\n01111: not allowed\n10000: section 12\n10001: section 13\n...\n11011 sector 23\n11100: not allowed \n11101: not allowed\n11110: not allowed\n11111: not allowed\nBit 2 MER: Mass Erase of bank 1 sectors\nErase activated of bank 1 sectors.\nBit 1 SER: Sector Erase\nSector Erase activated.\nBit 0 PG: Programming\nFlash programming activated.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nnWRP[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRDP[7:0]\nnRST_\nSTDBY\nnRST_\nSTOP\nWDG_\nSW\nReserve\nd\nBOR_LEV\nOPTST\nRT\nOPTLO\nCK\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrs\nrs\n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n108/1757\nRM0090 Rev 21\n \nBits 31:28 Reserved, must be kept cleared.\nBits 27:16 nWRP[11:0]: Not write protect\nThese bits contain the value of the write-protection option bytes after reset. They can be \nwritten to program a new write protect value into flash memory. \n0: Write protection active on selected sector\n1: Write protection inactive on selected sector\nBits 15:8 RDP[7:0]: Read protect\nThese bits contain the value of the read-protection option level after reset. They can be written \nto program a new read protection value into flash memory.\n0xAA: Level 0, read protection not active\n0xCC: Level 2, chip read protection active\nOthers: Level 1, read protection of memories active\nBits 7:5 USER[2:0]: User option bytes\nThese bits contain the value of the user option byte after reset. They can be written to program \na new user option byte value into flash memory.\nBit 7: nRST_STDBY\nBit 6: nRST_STOP\nBit 5: WDG_SW\nNote: When changing the WDG mode from hardware to software or from software to \nhardware, a system reset is required to make the change effective.\nBit 4 Reserved, must be kept cleared. Always read as “0”.\nBits 3:2 BOR_LEV[1:0]: BOR reset Level\nThese bits contain the supply level threshold that activates/releases the reset. They can be \nwritten to program a new BOR level. By default, BOR is off. When the supply voltage (VDD) \ndrops below the selected BOR level, a device reset is generated.\n00: BOR Level 3 (VBOR3), brownout threshold level 3\n01: BOR Level 2 (VBOR2), brownout threshold level 2\n10: BOR Level 1 (VBOR1), brownout threshold level 1\n11: BOR off, POR/PDR reset threshold level is applied\nNote: For full details about BOR characteristics, refer to the “Electrical characteristics” section \nin the device datasheet.\nBit 1 OPTSTRT: Option start\nThis bit triggers a user option operation when set. It is set only by software and cleared when \nthe BSY bit is cleared.\nBit 0 OPTLOCK: Option lock\nWrite to 1 only. When this bit is set, it indicates that the FLASH_OPTCR register is locked. This \nbit is cleared by hardware after detecting the unlock sequence.\nIn the event of an unsuccessful unlock operation, this bit remains set until the next reset.\n\n\n<>\n\nRM0090 Rev 21\n109/1757\nRM0090\nEmbedded flash memory interface\n113\n3.9.10 \nFlash option control register (FLASH_OPTCR) \nfor STM32F42xxx and STM32F43xxx\nThe FLASH_OPTCR register is used to modify the user option bytes.\nAddress offset: 0x14\nReset value: 0x0FFF AAED. The option bits are loaded with values from flash memory at \nreset release.\nAccess: no wait state when no flash memory operation is ongoing, word, half-word and byte \naccess.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nSPR\nMOD\nDB1M\nReserved\nnWRP[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRDP[7:0]\nnRST_\nSTDBY\nnRST_\nSTOP\nWDG_\nSW\nBFB2\nBOR_LEV\nOPTST\nRT\nOPTLO\nCK\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrs\nrs\nBit 31 SPRMOD: Selection of protection mode for nWPRi bits\n0: PCROP disabled. nWPRi bits used for Write protection on sector i.\n1: PCROP enabled. nWPRi bits used for PCROP protection on sector i\nBit 30 DB1M: Dual-bank on 1 Mbyte flash memory devices \n0: 1 Mbyte single bank flash memory (contiguous addresses in bank1)\n1: 1 Mbyte dual bank flash memory. The flash memory is organized as two banks of \n512 Kbytes each (see Table 7: 1 Mbyte flash memory single bank vs dual bank organization \n(STM32F42xxx and STM32F43xxx) and Table 9: 1 Mbyte dual bank flash memory \norganization (STM32F42xxx and STM32F43xxx)). To perform an erase operation, the right \nsector must be programmed (see Table 7 for information on the sector numbering scheme). \nNote: If DB1M is set and an erase operation is performed on Bank 2 while the default sector \nnumber is selected (as an example, sector 8 is configured instead of sector 12), the \nerase operation on Bank 2 sector is not performed. \nBits 29:28 Reserved, must be kept cleared.\nBits 27:16 nWRP[11:0]: Not write protect\nThese bits contain the value of the write-protection and read-protection (PCROP) option bytes \nfor sectors 0 to 11 after reset. They can be written to program a new write-protect or PCROP \nvalue into flash memory.\nIf SPRMOD is reset:\n0: Write protection active on sector i\n1: Write protection not active on sector i\nIf SPRMOD is set:\n0: PCROP protection not active on sector i\n1: PCROP protection active on sector i\nBits 15:8 RDP[7:0]: Read protect\nThese bits contain the value of the read-protection option level after reset. They can be written \nto program a new read protection value into flash memory.\n0xAA: Level 0, read protection not active\n0xCC: Level 2, chip read protection active\nOthers: Level 1, read protection of memories active\n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n110/1757\nRM0090 Rev 21\nBits 7:5 USER: User option bytes\nThese bits contain the value of the user option byte after reset. They can be written to program \na new user option byte value into flash memory.\nBit 7: nRST_STDBY\nBit 6: nRST_STOP\nBit 5: WDG_SW\nNote: When changing the WDG mode from hardware to software or from software to \nhardware, a system reset is required to make the change effective.\nBit 4 BFB2: Dual-bank Boot option byte\n0: Dual-bank boot disabled. Boot can be performed either from flash memory bank 1 or from \nsystem memory depending on boot pin state (default)\n1: Dual-bank boot enabled. Boot is always performed from system memory.\nNote: For STM32F42xx and STM32F43xx 1MB part numbers, this option bit must be kept \ncleared when DB1M=0. \nBits 3:2 BOR_LEV: BOR reset Level\nThese bits contain the supply level threshold that activates/releases the reset. They can be \nwritten to program a new BOR level. By default, BOR is off. When the supply voltage (VDD) \ndrops below the selected BOR level, a device reset is generated.\n00: BOR Level 3 (VBOR3), brownout threshold level 3\n01: BOR Level 2 (VBOR2), brownout threshold level 2\n10: BOR Level 1 (VBOR1), brownout threshold level 1\n11: BOR off, POR/PDR reset threshold level is applied\nNote: For full details on BOR characteristics, refer to the “Electrical characteristics” section of \nthe product datasheet.\nBit 1 OPTSTRT: Option start\nThis bit triggers a user option operation when set. It is set only by software and cleared when \nthe BSY bit is cleared.\nBit 0 OPTLOCK: Option lock\nWrite to 1 only. When this bit is set, it indicates that the FLASH_OPTCR register is locked. This \nbit is cleared by hardware after detecting the unlock sequence.\nIn the event of an unsuccessful unlock operation, this bit remains set until the next reset.\n\n\n<>\n\nRM0090 Rev 21\n111/1757\nRM0090\nEmbedded flash memory interface\n113\n3.9.11 \nFlash option control register (FLASH_OPTCR1) \nfor STM32F42xxx and STM32F43xxx \nThis register is available only on STM32F42xxx and STM32F43xxx.\nThe FLASH_OPTCR1 register is used to modify the user option bytes for bank 2.\nAddress offset: 0x18\nReset value: 0x0FFF 0000. The option bits are loaded with values from flash memory at \nreset release.\nAccess: no wait state when no flash memory operation is ongoing, word, half-word and byte \naccess.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nnWRP[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBits 31:28 Reserved, must be kept cleared.\nBits 27:16 nWRP[11:0]: Not write protect\nThese bits contain the value of the write-protection and read-protection (PCROP) option bytes \nfor sectors 0 to 11 after reset. They can be written to program a new write-protect or PCROP \nvalue into flash memory.\nIf SPRMOD is reset (default value):\n0: Write protection active on sector i. \n1: Write protection not active on sector i. \nIf SPRMOD is set:\n0: PCROP protection not active on sector i. \n1: PCROP protection active on sector i.\nBits 15:0 Reserved, must be kept cleared.\n\n\n<>\n\nEmbedded flash memory interface\nRM0090\n112/1757\nRM0090 Rev 21\n3.9.12 \nFlash interface register map\n \nTable 20. Flash register map and reset values\n(STM32F405xx/07xx and STM32F415xx/17xx)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nFLASH_ACR\nReserved\nDCRST\nICRST\nDCEN\nICEN\nPRFTEN\nReserved\nLATENCY\n[2:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nFLASH_\nKEYR\nKEY[31:16]\nKEY[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nFLASH_OPT\nKEYR\nOPTKEYR[31:16]\nOPTKEYR[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nFLASH_SR\nReserved\nBSY\nReserved\nPGSERR\nPGPERR\nPGAERR\nWRPERR\nReserved\nOPERR\nEOP\nReset value\n0\n0\n0\n0\n0\n0\n0\n0x10\nFLASH_CR\nLOCK\nReserved\nEOPIE\nReserved\nSTRT\nReserved\nPSIZE[1:0]\nReserved\nSNB[3:0]\nMER\nSER\nPG\nReset value\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nFLASH_\nOPTCR\nReserved\nnWRP[11:0]\nRDP[7:0]\nnRST_STDBY\nnRST_STOP\nWDG_SW\nReserved\nBOR_LEV[1:0]\nOPTSTRT\nOPTLOCK\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0\n1\n0\n1\n0\n1\n0\n1\n1\n1\n1\n1\n0\n1\nTable 21. Flash register map and reset values (STM32F42xxx and STM32F43xxx)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nFLASH_ACR\nReserved\nDCRST\nICRST\nDCEN\nICEN\nPRFTEN\nReserved\nLATENCY[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nFLASH_KEYR\nKEY[31:16]\nKEY[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nFLASH_\nOPTKEYR\nOPTKEYR[31:16]\nOPTKEYR[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nFLASH_SR\nReserved\nBSY\nReserved\nRDERR\nPGSERR\nPGPERR\nPGAERR\nWRPERR\nReserved\nOPERR\nEOP\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n\n\n<>\n\nRM0090 Rev 21\n113/1757\nRM0090\nEmbedded flash memory interface\n113\n0x10\nFLASH_CR\nLOCK\nReserved\nEOPIE\nReserved\nSTRT\nMER1\nReserved\nPSIZE[1:0]\nSNB[4:0]\nMER\nSER\nPG\nReset value\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nFLASH_OPTCR\nSPRMOD\nDB1M\nReserved\nnWRP[11:0]\nRDP[7:0]\nnRST_STDBY\nnRST_STOP\nWDG_SW\nBFB2\nBOR_LEV[1:0]\nOPTSTRT\nOPTLOCK\nReset value\n0\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0\n1\n0\n1\n0\n1\n0\n1\n1\n1\n0\n1\n1\n0\n1\n0x18\nFLASH_\nOPTCR1\nReserved\nnWRP[11:0]\nReserved\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\nTable 21. Flash register map and reset values (STM32F42xxx and STM32F43xxx) (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nCRC calculation unit\nRM0090\n114/1757\nRM0090 Rev 21\n4 \nCRC calculation unit\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n4.1 \nCRC introduction\nThe CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit \ndata word and a fixed generator polynomial.\nAmong other applications, CRC-based techniques are used to verify data transmission or \nstorage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of \nverifying the flash memory integrity. The CRC calculation unit helps compute a signature of \nthe software during runtime, to be compared with a reference signature generated at link-\ntime and stored at a given memory location.\n4.2 \nCRC main features\n•\nUses CRC-32 (Ethernet) polynomial: 0x4C11DB7\n–\nX32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X + 1\n•\nSingle input/output 32-bit data register\n•\nCRC computation done in 4 AHB clock cycles (HCLK)\n•\nGeneral-purpose 8-bit register (can be used for temporary storage)\nThe block diagram is shown in Figure 8.\nFigure 8. CRC calculation unit block diagram\nAHB bus\n32-bit (read access)\nData register (output)\nCRC computation (polynomial: 0x4C11DB7)\n32-bit (write access)\nData register (input)\nai14968\n\n\n<>\n\nRM0090 Rev 21\n115/1757\nRM0090\nCRC calculation unit\n116\n4.3 \nCRC functional description\nThe CRC calculation unit mainly consists of a single 32-bit data register, which:\n•\nis used as an input register to enter new data in the CRC calculator (when writing into \nthe register)\n•\nholds the result of the previous CRC calculation (when reading the register)\nEach write operation into the data register creates a combination of the previous CRC value \nand the new one (CRC computation is done on the whole 32-bit data word, and not byte per \nbyte).\nThe write operation is stalled until the end of the CRC computation, thus allowing back-to-\nback write accesses or consecutive write and read accesses.\nThe CRC calculator can be reset to 0xFFFF FFFF with the RESET control bit in the \nCRC_CR register. This operation does not affect the contents of the CRC_IDR register.\n4.4 \nCRC registers\nThe CRC calculation unit contains two data registers and a control register.The peripheral \nThe CRC registers have to be accessed by words (32 bits).\n4.4.1 \nData register (CRC_DR)\nAddress offset: 0x00\nReset value: 0xFFFF FFFF\n \n4.4.2 \nIndependent data register (CRC_IDR)\nAddress offset: 0x04\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDR [31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDR [15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 Data register bits\nUsed as an input register when writing new data into the CRC calculator.\nHolds the previous CRC calculation result when it is read.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nIDR[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nCRC calculation unit\nRM0090\n116/1757\nRM0090 Rev 21\n \n4.4.3 \nControl register (CRC_CR)\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n4.4.4 \nCRC register map\nThe following table provides the CRC register map and reset values. \n \nBits 31:8 Reserved, must be kept at reset value.\nBits 7:0 General-purpose 8-bit data register bits\nCan be used as a temporary storage location for one byte.\nThis register is not affected by CRC resets generated by the RESET bit in the CRC_CR \nregister.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRESET\nw\nBits 31:1 Reserved, must be kept at reset value.\nBit 0 RESET bit\nResets the CRC calculation unit and sets the data register to 0xFFFF FFFF.\nThis bit can only be set, it is automatically cleared by hardware.\nTable 22. CRC calculation unit register map and reset values\nOffset\nRegister\n31-24\n23-16\n15-8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nCRC_DR\nData register\nReset \nvalue\n0xFFFF FFFF\n0x04\nCRC_IDR\nReserved\nIndependent data register\nReset \nvalue\n0x00\n0x08\nCRC_CR\nReserved\nRESET\nReset \nvalue\n0\n\n\n<>\n\nRM0090 Rev 21\n117/1757\nRM0090\nPower controller (PWR)\n151\n5 \nPower controller (PWR)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n5.1 \nPower supplies\nThe device requires a 1.8 to 3.6 V operating voltage supply (VDD). An embedded linear \nvoltage regulator is used to supply the internal 1.2 V digital power.\nThe real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM) \ncan be powered from the VBAT voltage when the main VDD supply is powered off. \nNote:\nDepending on the operating power supply range, some peripheral may be used with limited \nfunctionality and performance. For more details refer to section “General operating \nconditions” in STM32F4xx datasheets.\nFigure 9. Power supply overview for STM32F405xx/07xx and STM32F415xx/17xx\n1.\nVDDA and VSSA must be connected to VDD and VSS, respectively. \nMS19911V2\nBackup circuitry\n(OSC32K,RTC,\nWakeup logic\nBackup registers,\nbackup RAM)\nKernel logic \n(CPU, digital \n& RAM) \nAnalog:\nRCs, \nPLL,..\nPower \nswitch\nVBAT\nGPIOs\nOUT\nIN\n15 × 100 nF\n+ 1 × 4.7 μF\nVBAT =\n1.65 to 3.6V\nVoltage \nregulator\nVDDA\nADC\nLevel shifter\nIO\nLogic\nVDD\n100 nF\n+ 1 μF\nFlash memory\nVCAP_1\nVCAP_2\n2 × 2.2 μF\nBYPASS_REG\nPDR_ON\nReset \ncontroller\nVDD\n1/2/...14/15\nVSS\n1/2/...14/15\nVDD\nVREF+\nVREF-\nVSSA\nVREF\n100 nF\n+ 1 μF\n\n\n<>\n\nPower controller (PWR)\nRM0090\n118/1757\nRM0090 Rev 21\nFigure 10. Power supply overview for STM32F42xxx and STM32F43xxx\n1.\nVDDA and VSSA must be connected to VDD and VSS, respectively. \n5.1.1 \nIndependent A/D converter supply and reference voltage\nTo improve conversion accuracy, the ADC has an independent power supply which can be \nseparately filtered and shielded from noise on the PCB.\n•\nThe ADC voltage supply input is available on a separate VDDA pin. \n•\nAn isolated supply ground connection is provided on VSSA pin. \nTo ensure a better accuracy of low voltage inputs, the user can connect a separate external \nreference voltage ADC input on VREF. The voltage on VREF ranges from 1.8 V to VDDA.\nMS30482V2\nVDD\n1/2/...14/20\nAnalog: \nRCs, PLL,\n...\nPower switch\nVBAT\nGP I/Os\nOUT\nIN\nKernel logic \n(CPU, \ndigital \n& RAM) \nBackup circuitry\n(OSC32K,RTC,\nBackup registers,\nbackup RAM)\nWakeup logic\n19 × 100 nF\n+ 1 × 4.7 μF\nVBAT =\n 1.65 to 3.6V\n \nVoltage\nregulator\nVSS \n1/2/...14/20\nVDDA\nVREF+\nVREF-\nVSSA\nADC\nLevel shifter\nIO\nLogic\nVDD\n+ 1 μF\nVREF\n100 nF\n+ 1 μF\nVDD\nFlash memory\nVCAP_1\nVCAP_2\n2 × 2.2 μF\nBYPASS_REG\nPDR_ON\nReset \ncontroller\n100 nF\n\n\n<>\n\nRM0090 Rev 21\n119/1757\nRM0090\nPower controller (PWR)\n151\n5.1.2 \nBattery backup domain\nBackup domain description\nTo retain the content of the RTC backup registers, backup SRAM, and supply the RTC when \nVDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a \nbattery or by another source.\nTo allow the RTC to operate even when the main digital supply (VDD) is turned off, the VBAT \npin powers the following blocks:\n•\nThe RTC\n•\nThe LSE oscillator\n•\nThe backup SRAM when the low-power backup regulator is enabled\n•\nPC13 to PC15 I/Os, plus PI8 I/O (when available) \nThe switch to the VBAT supply is controlled by the power-down reset embedded in the Reset \nblock.\nWarning:\nDuring tRSTTEMPO (temporization at VDD startup) or after a PDR \nis detected, the power switch between VBAT and VDD remains \nconnected to VBAT.\nDuring the startup phase, if VDD is established in less than \ntRSTTEMPO (Refer to the datasheet for the value of tRSTTEMPO) \nand VDD > VBAT + 0.6 V, a current may be injected into VBAT \nthrough an internal diode connected between VDD and the \npower switch (VBAT).\nIf the power supply/battery connected to the VBAT pin cannot \nsupport this current injection, it is strongly recommended to \nconnect an external low-drop diode between this power \nsupply and the VBAT pin.\nIf no external battery is used in the application, it is recommended to connect the VBAT pin \nto VDD supply, and add a 100 nF external decoupling ceramic capacitor on VBAT pin.\nWhen the backup domain is supplied by VDD (analog switch connected to VDD), the \nfollowing functions are available:\n•\nPC14 and PC15 can be used as either GPIO or LSE pins\n•\nPC13 can be used as a GPIOas the RTC_AF1 pin (refer to Table 38: RTC_AF1 pin for \nmore details about this pin configuration)\nNote:\nDue to the fact that the switch only sinks a limited amount of current (3 mA), the use of PI8 \nand PC13 to PC15 GPIOs in output mode is restricted: the speed has to be limited to 2 MHz \nwith a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to \ndrive an LED).\n\n\n<>\n\nPower controller (PWR)\nRM0090\n120/1757\nRM0090 Rev 21\nWhen the backup domain is supplied by VBAT (analog switch connected to VBAT because \nVDD is not present), the following functions are available:\n•\nPC14 and PC15 can be used as LSE pins only\n•\nPC13 can be used as the RTC_AF1 pin (refer to Table 38: RTC_AF1 pin for more \ndetails about this pin configuration)\n•\nPI8 can be used as RTC_AF2\nBackup domain access\nAfter reset, the backup domain (RTC registers, RTC backup register and backup SRAM) is \nprotected against possible unwanted write accesses. To enable access to the backup \ndomain, proceed as follows:\n•\nAccess to the RTC and RTC backup registers\n1.\nEnable the power interface clock by setting the PWREN bits in the RCC_APB1ENR \nregister (see Section 7.3.13 and Section 6.3.13)\n2. \nSet the DBP bit in the Section 5.4.1 and PWR power control register (PWR_CR) for \nSTM32F42xxx and STM32F43xxx to enable access to the backup domain\n3. \nSelect the RTC clock source: see Section 7.2.8: RTC/AWU clock\n4. \nEnable the RTC clock by programming the RTCEN [15] bit in the Section 7.3.20: RCC \nBackup domain control register (RCC_BDCR)\n•\nAccess to the backup SRAM\n1.\nEnable the power interface clock by setting the PWREN bits in the RCC_APB1ENR \nregister (see Section 7.3.13 and Section 6.3.13 for STM32F405xx/07xx and \nSTM32F415xx/17xx and STM32F42xxx and STM32F43xxx, respectively)\n2. \nSet the DBP bit in the PWR power control register (PWR_CR) for STM32F405xx/07xx \nand STM32F415xx/17xx and PWR power control register (PWR_CR) for \nSTM32F42xxx and STM32F43xxx to enable access to the backup domain\n3. \nEnable the backup SRAM clock by setting BKPSRAMEN bit in the RCC AHB1 \nperipheral clock enable register (RCC_AHB1ENR).\nRTC and RTC backup registers\nThe real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-\nof-day clock/calendar, two programmable alarm interrupts, and a periodic programmable \nwake-up flag with interrupt capability. The RTC contains 20 backup data registers (80 bytes) \nwhich are reset when a tamper detection event occurs. For more details refer to Section 26: \nReal-time clock (RTC).\nBackup SRAM\nThe backup domain includes 4 Kbytes of backup SRAM addressed in 32-bit, 16-bit or 8-bit \nmode. Its content is retained even in Standby or VBAT mode when the low-power backup \nregulator is enabled. It can be considered as an internal EEPROM when VBAT is always \npresent.\nWhen the backup domain is supplied by VDD (analog switch connected to VDD), the backup \nSRAM is powered from VDD which replaces the VBAT power supply to save battery life.\nWhen the backup domain is supplied by VBAT (analog switch connected to VBAT because \nVDD is not present), the backup SRAM is powered by a dedicated low-power regulator. This \nregulator can be ON or OFF depending whether the application needs the backup SRAM \nfunction in Standby and VBAT modes or not. The power-down of this regulator is controlled \n\n\n<>\n\nRM0090 Rev 21\n121/1757\nRM0090\nPower controller (PWR)\n151\nby a dedicated bit, the BRE control bit of the PWR_CSR register (see Section 5.4.2: PWR \npower control/status register (PWR_CSR) for STM32F405xx/07xx and \nSTM32F415xx/17xx). \nThe backup SRAM is not mass erased by an tamper event. When the Flash memory is read \nprotected, the backup SRAM is also read protected to prevent confidential data, such as \ncryptographic private key, from being accessed. When the protection level change from \nlevel 1 to level 0 is requested, the backup SRAM content is erased.\nFigure 11. Backup domain\n5.1.3 \nVoltage regulator for STM32F405xx/07xx and STM32F415xx/17xx\nAn embedded linear voltage regulator supplies all the digital circuitries except for the backup \ndomain and the Standby circuitry. The regulator output voltage is around 1.2 V.\nThis voltage regulator requires one or two external capacitors to be connected to one or two \ndedicated pins, VCAP_1 and VCAP_2 available in all packages. Specific pins must be \nconnected either to VSS or VDD to activate or deactivate the voltage regulator. These pins \ndepend on the package.\nWhen activated by software, the voltage regulator is always enabled after Reset. It works in \nthree different modes depending on the application modes.\n•\nIn Run mode, the regulator supplies full power to the 1.2 V domain (core, memories \nand digital peripherals). In this mode, the regulator output voltage (around 1.2 V) can \nbe scaled by software to different voltage values:\nScale 1 or scale 2 can be configured on the fly through VOS (bit 15 of the \nPWR_CR register). \nThe voltage scaling allows optimizing the power consumption when the device is \nclocked below the maximum system frequency. \n•\nIn Stop mode, the main regulator or the low-power regulator supplies to the 1.2 V \ndomain, thus preserving the content of registers and internal SRAM. The voltage \nMS30430V1\nVoltage regulator\n3.3 -> 1.2 V\n1.2 V domain\nBackup SRAM\ninterface\nPower switch\nLP voltage regulator\n3.3 -> 1.2 V\nBackup SRAM\n1.2 V\nRTC\nLSE 32.768 Hz\nBackup domain\n\n\n<>\n\nPower controller (PWR)\nRM0090\n122/1757\nRM0090 Rev 21\nregulator can be put either in main regulator mode (MR) or in low-power mode (LPR). \nThe programmed voltage scale remains the same during Stop mode:\nThe programmed voltage scale remains the same during Stop mode (see \nSection 5.4.1: PWR power control register (PWR_CR) for STM32F405xx/07xx \nand STM32F415xx/17xx).\n•\nIn Standby mode, the regulator is powered down. The content of the registers and \nSRAM are lost except for the Standby circuitry and the backup domain.\nNote:\nFor more details, refer to the voltage regulator section in the STM32F405xx/07xx and \nSTM32F415xx/17xx datasheets. \n5.1.4 \nVoltage regulator for STM32F42xxx and STM32F43xxx\nAn embedded linear voltage regulator supplies all the digital circuitries except for the backup \ndomain and the Standby circuitry. The regulator output voltage is around 1.2 V.\nThis voltage regulator requires two external capacitors to be connected to two dedicated \npins, VCAP_1 and VCAP_2 available in all packages. Specific pins must be connected \neither to VSS or VDD to activate or deactivate the voltage regulator. These pins depend on \nthe package.\nWhen activated by software, the voltage regulator is always enabled after Reset. It works in \nthree different modes depending on the application modes (Run, Stop, or Standby mode).\n•\nIn Run mode, the main regulator supplies full power to the 1.2 V domain (core, \nmemories and digital peripherals). In this mode, the regulator output voltage (around \n1.2 V) can be scaled by software to different voltage values (scale 1, scale 2, and scale \n3 can be configured through VOS[1:0] bits of the PWR_CR register). The scale can be \nmodified only when the PLL is OFF and the HSI or HSE clock source is selected as \nsystem clock source. The new value programmed is active only when the PLL is ON. \nWhen the PLL is OFF, the voltage scale 3 is automatically selected.\nThe voltage scaling allows optimizing the power consumption when the device is \nclocked below the maximum system frequency. After exit from Stop mode, the voltage \n\n\n<>\n\nRM0090 Rev 21\n123/1757\nRM0090\nPower controller (PWR)\n151\nscale 3 is automatically selected.(see Section 5.4.1: PWR power control register \n(PWR_CR) for STM32F405xx/07xx and STM32F415xx/17xx.\n2 operating modes are available:\n–\nNormal mode: The CPU and core logic operate at maximum frequency at a given \nvoltage scaling (scale 1, scale 2 or scale 3)\n–\nOver-drive mode: This mode allows the CPU and the core logic to operate at a \nhigher frequency than the normal mode for the voltage scaling scale 1 and scale \n2.\n•\nIn Stop mode: the main regulator or low-power regulator supplies a low-power voltage \nto the 1.2V domain, thus preserving the content of registers and internal SRAM.\nThe voltage regulator can be put either in main regulator mode (MR) or in low-power \nmode (LPR). Both modes can be configured by software as follows:\n–\nNormal mode: the 1.2 V domain is preserved in nominal leakage mode. It is the \ndefault mode when the main regulator (MR) or the low-power regulator (LPR) is \nenabled.\n–\nUnder-drive mode: the 1.2 V domain is preserved in reduced leakage mode. This \nmode is only available with the main regulator or in low-power regulator mode \n(see Table 23). \n•\nIn Standby mode: the regulator is powered down. The content of the registers and \nSRAM are lost except for the Standby circuitry and the backup domain.\nNote:\nOver-drive and under-drive mode are not available when the regulator is bypassed.\nFor more details, refer to the voltage regulator section in the STM32F42xxx and \nSTM32F43xxx datasheets.\n Table 23. Voltage regulator configuration mode versus device operating mode(1)\n1.\n‘-’ means that the corresponding configuration is not available. \nVoltage regulator \nconfiguration\nRun mode\nSleep mode\nStop mode\nStandby mode\nNormal mode\nMR\nMR\nMR or LPR\n-\nOver-drive \nmode(2)\n2.\nThe over-drive mode is not available when VDD = 1.8 to 2.1 V.\nMR\nMR\n-\n-\nUnder-drive mode\n-\n-\nMR or LPR\n-\nPower-down \nmode\n-\n-\n-\nYes\n\n\n<>\n\nPower controller (PWR)\nRM0090\n124/1757\nRM0090 Rev 21\nEntering Over-drive mode\nIt is recommended to enter Over-drive mode when the application is not running critical \ntasks and when the system clock source is either HSI or HSE. To optimize the configuration \ntime, enable the Over-drive mode during the PLL lock phase. \nTo enter Over-drive mode, follow the sequence below:\n1.\nSelect HSI or HSE as system clock.\n2. \nConfigure RCC_PLLCFGR register and set PLLON bit of RCC_CR register.\n3. \nSet ODEN bit of PWR_CR register to enable the Over-drive mode and wait for the \nODRDY flag to be set in the PWR_CSR register.\n4. \nSet the ODSW bit in the PWR_CR register to switch the voltage regulator from Normal \nmode to Over-drive mode. The System is stalled during the switch but the PLL clock \nsystem is still running during locking phase.\n5. \nWait for the ODSWRDY flag in the PWR_CSR to be set.\n6. \nSelect the required Flash latency as well as AHB and APB prescalers.\n7. \nWait for PLL lock.\n8. \nSwitch the system clock to the PLL.\n9. \nEnable the peripherals that are not generated by the System PLL (I2S clock, LCD-TFT \nclock, SAI1 clock, USB_48MHz clock....).\nNote:\nThe PLLI2S and PLLSAI can be configured at the same time as the system PLL.\nDuring the Over-drive switch activation, no peripheral clocks should be enabled. The \nperipheral clocks must be enabled once the Over-drive mode is activated.\nEntering Stop mode disables the Over-drive mode, as well as the PLL. The application \nsoftware has to configure again the Over-drive mode and the PLL after exiting from Stop \nmode.\nExiting from Over-drive mode\nIt is recommended to exit from Over-drive mode when the application is not running critical \ntasks and when the system clock source is either HSI or HSE.There are two sequences that \nallow exiting from over-drive mode: \n•\nBy resetting simultaneously the ODEN and ODSW bits bit in the PWR_CR register \n(sequence 1)\n•\nBy resetting first the ODSW bit to switch the voltage regulator to Normal mode and then \nresetting the ODEN bit to disable the Over-drive mode (sequence 2).\nExample of sequence 1:\n1.\nSelect HSI or HSE as system clock source.\n2. \nDisable the peripheral clocks that are not generated by the System PLL (I2S clock, \nLCD-TFT clock, SAI1 clock, USB_48MHz clock,....)\n3. \nReset simultaneously the ODEN and the ODSW bits in the PWR_CR register to switch \nback the voltage regulator to Normal mode and disable the Over-drive mode.\n4. \nWait for the ODWRDY flag of PWR_CSR to be reset.\n\n\n<>\n\nRM0090 Rev 21\n125/1757\nRM0090\nPower controller (PWR)\n151\nExample of sequence 2:\n1.\nSelect HSI or HSE as system clock source. \n2. \nDisable the peripheral clocks that are not generated by the System PLL (I2S clock, \nLCD-TFT clock, SAI1 clock, USB_48MHz clock,....).\n3. \nReset the ODSW bit in the PWR_CR register to switch back the voltage regulator to \nNormal mode. The system clock is stalled during voltage switching.\n4. \nWait for the ODWRDY flag of PWR_CSR to be reset.\n5. \nReset the ODEN bit in the PWR_CR register to disable the Over-drive mode.\nNote:\nDuring step 3, the ODEN bit remains set and the Over-drive mode is still enabled but not \nactive (ODSW bit is reset). If the ODEN bit is reset instead, the Over-drive mode is disabled \nand the voltage regulator is switched back to the initial voltage.\n5.2 \nPower supply supervisor\n5.2.1 \nPower-on reset (POR)/power-down reset (PDR)\nThe device has an integrated POR/PDR circuitry that allows proper operation starting\nfrom 1.8 V.\nThe device remains in Reset mode when VDD/VDDA is below a specified threshold, \nVPOR/PDR, without the need for an external reset circuit. For more details concerning the \npower on/power-down reset threshold, refer to the electrical characteristics of the \ndatasheet. \nFigure 12. Power-on reset/power-down reset waveform\nMSv30431V2\nVDD/VDDA\n40 mV\nhysteresis\nPOR\nPOR\nReset\nTemporization\ntRSTTEMPO\n\n\n<>\n\nPower controller (PWR)\nRM0090\n126/1757\nRM0090 Rev 21\n5.2.2 \nBrownout reset (BOR)\nDuring power on, the Brownout reset (BOR) keeps the device under reset until the supply \nvoltage reaches the specified VBOR threshold.\nVBOR is configured through device option bytes. By default, BOR is off. 3 programmable \nVBOR threshold levels can be selected:\n•\nBOR Level 3 (VBOR3). Brownout threshold level 3.\n•\nBOR Level 2 (VBOR2). Brownout threshold level 2.\n•\nBOR Level 1 (VBOR1). Brownout threshold level 1.\nNote:\nFor full details about BOR characteristics, refer to the \"Electrical characteristics\" section in \nthe device datasheet.\nWhen the supply voltage (VDD) drops below the selected VBOR threshold, a device reset is \ngenerated.\nThe BOR can be disabled by programming the device option bytes. In this case, the \npower-on and power-down is then monitored by the POR/ PDR (see Section 5.2.1: Power-\non reset (POR)/power-down reset (PDR)).\nThe BOR threshold hysteresis is ~100 mV (between the rising and the falling edge of the \nsupply voltage).\nFigure 13. BOR thresholds\n5.2.3 \nProgrammable voltage detector (PVD)\nYou can use the PVD to monitor the VDD power supply by comparing it to a threshold \nselected by the PLS[2:0] bits in the PWR power control register (PWR_CR) for \nMS30433V1\nVDD/VDDA\n100 mV\nhysteresis\nBOR threshold\nReset\n\n\n<>\n\nRM0090 Rev 21\n127/1757\nRM0090\nPower controller (PWR)\n151\nSTM32F405xx/07xx and STM32F415xx/17xx and PWR power control register (PWR_CR) \nfor STM32F42xxx and STM32F43xxx.\nThe PVD is enabled by setting the PVDE bit.\nA PVDO flag is available, in the PWR power control/status register (PWR_CSR) for \nSTM32F405xx/07xx and STM32F415xx/17xx, to indicate if VDD is higher or lower than the \nPVD threshold. This event is internally connected to the EXTI line16 and can generate an \ninterrupt if enabled through the EXTI registers. The PVD output interrupt can be generated \nwhen VDD drops below the PVD threshold and/or when VDD rises above the PVD threshold \ndepending on EXTI line16 rising/falling edge configuration. As an example the service \nroutine could perform emergency shutdown tasks.\nFigure 14. PVD thresholds\n5.3 \nLow-power modes\nBy default, the microcontroller is in Run mode after a system or a power-on reset. In Run \nmode the CPU is clocked by HCLK and the program code is executed. Several low-power \nmodes are available to save power when the CPU does not need to be kept running, for \nexample when waiting for an external event. It is up to the user to select the mode that gives \nthe best compromise between low-power consumption, short startup time and available \nwake-up sources.\nThe devices feature three low-power modes:\n•\nSleep mode (Cortex®-M4 with FPU core stopped, peripherals kept running)\n•\nStop mode (all clocks are stopped)\n•\nStandby mode (1.2 V domain powered off)\nMS30432V2\nVDD\n100 mV\nhysteresis\nPVD threshold\nPVD output\n\n\n<>\n\nPower controller (PWR)\nRM0090\n128/1757\nRM0090 Rev 21\nIn addition, the power consumption in Run mode can be reduce by one of the following \nmeans:\n•\nSlowing down the system clocks\n•\nGating the clocks to the APBx and AHBx peripherals when they are unused.\nEntering low-power mode\nLow-power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or \nWFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M4 with \nFPU System Control register is set on Return from ISR.\nEntering Low-power mode through WFI or WFE is executed only if no interrupt is pending or \nno event is pending.\nExiting low-power mode\nThe MCU exits from Sleep and Stop modes low-power mode depending on the way the low-\npower mode was entered:\n•\nIf the WFI instruction or Return from ISR was used to enter the low-power mode, any \nperipheral interrupt acknowledged by the NVIC can wake up the device.\n•\nIf the WFE instruction is used to enter the low-power mode, the MCU exits the low-\npower mode as soon as an event occurs. The wake-up event can be generated either \nby:\n–\nNVIC IRQ interrupt:\nWhen SEVONPEND = 0 in the Cortex®-M4 with FPU System Control register: by \nenabling an interrupt in the peripheral control register and in the NVIC. When the \nMCU resumes from WFE, the peripheral interrupt pending bit and the NVIC \nperipheral IRQ channel pending bit (in the NVIC interrupt clear pending register) \nhave to be cleared. Only NVIC interrupts with sufficient priority wakes up and \ninterrupts the MCU.\nWhen SEVONPEND = 1 in the Cortex®-M4 with FPU System Control register: by \nenabling an interrupt in the peripheral control register and optionally in the NVIC. \nWhen the MCU resumes from WFE, the peripheral interrupt pending bit and when \nenabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear \npending register) have to be cleared. All NVIC interrupts wakes up the MCU, even \nthe disabled ones. Only enabled NVIC interrupts with sufficient priority wakes up \nand interrupts the MCU.\n–\nEvent\nThis is done by configuring a EXTI line in event mode. When the CPU resumes \nfrom WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or \nthe NVIC IRQ channel pending bit as the pending bits corresponding to the event \nline is not set. It may be necessary to clear the interrupt flag in the peripheral.\nThe MCU exits from Standby low-power mode through an external reset (NRST pin), an \nIWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs (see \nFigure 237: RTC block diagram).\nAfter waking up from Standby mode, program execution restarts in the same way as after a \nReset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).\n\n\n<>\n\nRM0090 Rev 21\n129/1757\nRM0090\nPower controller (PWR)\n151\nOnly enabled NVIC interrupts with sufficient priority wakes up and interrupts the MCU.\n5.3.1 \nSlowing down system clocks\nIn Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be \nreduced by programming the prescaler registers. These prescalers can also be used to slow \ndown peripherals before entering Sleep mode. \nFor more details refer to Section 7.3.3: RCC clock configuration register (RCC_CFGR).\n5.3.2 \nPeripheral clock gating\nIn Run mode, the HCLKx and PCLKx for individual peripherals and memories can be \nstopped at any time to reduce power consumption. \nTo further reduce power consumption in Sleep mode the peripheral clocks can be disabled \nprior to executing the WFI or WFE instructions.\nTable 24. Low-power mode summary\nMode name\nEntry\nWake-up\nEffect on 1.2 V \ndomain clocks\nEffect on \nVDD \ndomain \nclocks\nVoltage regulator\nSleep\n(Sleep now or \nSleep-on-\nexit)\nWFI or Return \nfrom ISR\nAny interrupt\nCPU CLK OFF\nno effect on other \nclocks or analog \nclock sources\nNone\nON\nWFE\nWake-up event\nStop\nPDDS and LPDS \nbits + \nSLEEPDEEP bit \n+ WFI, Return \nfrom ISR or WFE\nAny EXTI line (configured \nin the EXTI registers, \ninternal and external lines)\nAll 1.2 V domain \nclocks OFF\nHSI and \nHSE \noscillator\ns OFF\nON or in low- power \nmode (depends on \nPWR power control \nregister (PWR_CR) \nfor \nSTM32F405xx/07x\nx and \nSTM32F415xx/17x\nx and PWR power \ncontrol register \n(PWR_CR) for \nSTM32F405xx/07x\nx and \nSTM32F415xx/17x\nxPWR power \ncontrol register \n(PWR_CR) for \nSTM32F42xxx and \nSTM32F43xxx\nStandby\nPDDS bit + \nSLEEPDEEP bit \n+ WFI, Return \nfrom ISR or WFE \nWKUP pin rising edge, \nRTC alarm (Alarm A or \nAlarm B), RTC Wake-up \nevent, RTC tamper \nevents, RTC time stamp \nevent, external reset in \nNRST pin, IWDG reset\nOFF\n\n\n<>\n\nPower controller (PWR)\nRM0090\n130/1757\nRM0090 Rev 21\nPeripheral clock gating is controlled by the AHB1 peripheral clock enable register \n(RCC_AHB1ENR), AHB2 peripheral clock enable register (RCC_AHB2ENR), AHB3 \nperipheral clock enable register (RCC_AHB3ENR) (see Section 7.3.10: RCC AHB1 \nperipheral clock enable register (RCC_AHB1ENR), Section 7.3.11: RCC AHB2 peripheral \nclock enable register (RCC_AHB2ENR), Section 7.3.12: RCC AHB3 peripheral clock \nenable register (RCC_AHB3ENR) for STM32F405xx/07xx and STM32F415xx/17xx, and \nSection 6.3.10: RCC AHB1 peripheral clock register (RCC_AHB1ENR), Section 6.3.11: \nRCC AHB2 peripheral clock enable register (RCC_AHB2ENR), and Section 6.3.12: RCC \nAHB3 peripheral clock enable register (RCC_AHB3ENR) for STM32F42xxx and \nSTM32F43xxx).\nDisabling the peripherals clocks in Sleep mode can be performed automatically by resetting \nthe corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers.\n5.3.3 \nSleep mode\nEntering Sleep mode\nThe Sleep mode is entered according to Section : Entering low-power mode, when the \nSLEEPDEEP bit in the Cortex®-M4 with FPU System Control register is cleared.\nRefer to Table 25 and Table 26 for details on how to enter Sleep mode.\nNote:\nAll interrupt pending bits must be cleared before the sleep mode entry.\nExiting Sleep mode\nThe Sleep mode is exited according to Section : Exiting low-power mode.\nRefer to Table 25 and Table 26 for more details on how to exit Sleep mode.\n \nTable 25. Sleep-now entry and exit\nSleep-now mode\nDescription\nMode entry\nWFI (Wait for Interrupt) or WFE (Wait for Event) while:\n– SLEEPDEEP = 0, and\n– No interrupt (for WFI) or event (for WFE) is pending.\nRefer to the Cortex®-M4 with FPU System Control register. \nOn Return from ISR while: \n– SLEEPDEEP = 0 and \n– SLEEPONEXIT = 1,\n– No interrupt is pending.\nRefer to the Cortex®-M4 with FPU System Control register. \n\n\n<>\n\nRM0090 Rev 21\n131/1757\nRM0090\nPower controller (PWR)\n151\n \n5.3.4 \nStop mode (STM32F405xx/07xx and STM32F415xx/17xx)\nThe Stop mode is based on the Cortex®-M4 with FPU deepsleep mode combined with \nperipheral clock gating. The voltage regulator can be configured either in normal or low-\npower mode. In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI \nand the HSE RC oscillators are disabled. Internal SRAM and register contents are \npreserved. \nBy setting the FPDS bit in the PWR_CR register, the Flash memory also enters power-down \nmode when the device enters Stop mode. When the Flash memory is in power-down mode, \nan additional startup delay is incurred when waking up from Stop mode (see Table 27: Stop \noperating modes (STM32F405xx/07xx and STM32F415xx/17xx) and Section 5.4.1: PWR \npower control register (PWR_CR) for STM32F405xx/07xx and STM32F415xx/17xx).\nMode exit\nIf WFI or Return from ISR was used for entry:\nInterrupt: Refer to Table 62: Vector table for STM32F405xx/07xx and \nSTM32F415xx/17xx and Table 63: Vector table for STM32F42xxx and \nSTM32F43xxx\nIf WFE was used for entry and SEVONPEND = 0\nWake-up event: Refer to Section 12.2.3: Wake-up event management\nf WFE was used for entry and SEVONPEND = 1\nInterrupt even when disabled in NVIC: refer to Table 62: Vector table for \nSTM32F405xx/07xx and STM32F415xx/17xx and Table 63: Vector table \nfor STM32F42xxx and STM32F43xxx or Wake-up event (see \nSection 12.2.3: Wake-up event management).\nWake-up latency\nNone\nTable 26. Sleep-on-exit entry and exit\nSleep-on-exit\nDescription\nMode entry\nWFI (Wait for Interrupt) or WFE (Wait for Event) while:\n– SLEEPDEEP = 0, and\n– No interrupt (for WFI) or event (for WFE) is pending.\nRefer to the Cortex®-M4 with FPU System Control register. \nOn Return from ISR while: \n– SLEEPDEEP = 0, and \n– SLEEPONEXIT = 1, and\n– No interrupt is pending.\nRefer to the Cortex®-M4 with FPU System Control register. \nMode exit\nInterrupt: refer to Table 62: Vector table for STM32F405xx/07xx and \nSTM32F415xx/17xx and Table 63: Vector table for STM32F42xxx and \nSTM32F43xxx\nWake-up latency\nNone\nTable 25. Sleep-now entry and exit (continued)\nSleep-now mode\nDescription\n\n\n<>\n\nPower controller (PWR)\nRM0090\n132/1757\nRM0090 Rev 21\n \nEntering Stop mode (for STM32F405xx/07xx and STM32F415xx/17xx)\nThe Stop mode is entered according to Section : Entering low-power mode, when the \nSLEEPDEEP bit in the Cortex®-M4 with FPU System Control register is set.\nRefer to Table 28 for details on how to enter the Stop mode.\nTo further reduce power consumption in Stop mode, the internal voltage regulator can be put \nin low-power mode. This is configured by the LPDS bit of the PWR power control register \n(PWR_CR) for STM32F405xx/07xx and STM32F415xx/17xx and PWR power control \nregister (PWR_CR) for STM32F42xxx and STM32F43xxx.\nIf Flash memory programming is ongoing, the Stop mode entry is delayed until the memory \naccess is finished. \nIf an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB \naccess is finished.\nIn Stop mode, the following features can be selected by programming individual control bits:\n•\nIndependent watchdog (IWDG): the IWDG is started by writing to its Key register or by \nhardware option. Once started it cannot be stopped except by a Reset. See \nSection 21.3 in Section 21: Independent watchdog (IWDG).\n•\nReal-time clock (RTC): this is configured by the RTCEN bit in the Section 7.3.20: RCC \nBackup domain control register (RCC_BDCR)\n•\nInternal RC oscillator (LSI RC): this is configured by the LSION bit in the \nSection 7.3.21: RCC clock control & status register (RCC_CSR).\n•\nExternal 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the \nSection 7.3.20: RCC Backup domain control register (RCC_BDCR).\nThe ADC or DAC can also consume power during the Stop mode, unless they are disabled \nbefore entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit \nin the DAC_CR register must both be written to 0.\nTable 27. Stop operating modes\n(STM32F405xx/07xx and STM32F415xx/17xx)\nStop mode\nLPDS bit \nFPDS bit\nWake-up latency\n STOP MR\n(Main regulator)\n0\n0\nHSI RC startup time\n STOP MR-FPD\n0\n1\nHSI RC startup time +\nFlash wake-up time from Power \nDown mode\n STOP LP\n1\n0\nHSI RC startup time +\nregulator wake-up time from LP \nmode\n STOP LP-FPD\n1\n1\nHSI RC startup time +\nFlash wake-up time from Power \nDown mode +\nregulator wake-up time from LP \nmode\n\n\n<>\n\nRM0090 Rev 21\n133/1757\nRM0090\nPower controller (PWR)\n151\nNote:\nIf the application needs to disable the external clock before entering Stop mode, the HSEON \nbit must first be disabled and the system clock switched to HSI.\nOtherwise, if the HSEON bit is kept enabled while the external clock (external oscillator) can \nbe removed before entering stop mode, the clock security system (CSS) feature must be \nenabled to detect any external oscillator failure and avoid a malfunction behavior when \nentering stop mode.\nExiting Stop mode (for STM32F405xx/07xx and STM32F415xx/17xx)\nThe Stop mode is exited according to Section : Exiting low-power mode.\nRefer to Table 28 for more details on how to exit Stop mode.\nWhen exiting Stop mode by issuing an interrupt or a wake-up event, the HSI RC oscillator is \nselected as system clock. \nWhen the voltage regulator operates in low-power mode, an additional startup delay is \nincurred when waking up from Stop mode. By keeping the internal regulator ON during Stop \nmode, the consumption is higher although the startup time is reduced.\n Table 28. Stop mode entry and exit (for STM32F405xx/07xx and STM32F415xx/17xx)\nStop mode\nDescription\nMode entry\nWFI (Wait for Interrupt) or WFE (Wait for Event) while:\n– No interrupt (for WFI) or event (for WFE) is pending,\n– SLEEPDEEP bit is set in Cortex®-M4 with FPU System Control register,\n– PDDS bit is cleared in Power Control register (PWR_CR),\n– Select the voltage regulator mode by configuring LPDS bit in PWR_CR.\nOn Return from ISR:\n– No interrupt is pending,\n– SLEEPDEEP bit is set in Cortex®-M4 with FPU System Control register,\n– SLEEPONEXIT = 1, \n– PDDS bit is cleared in Power Control register (PWR_CR).\nNote: To enter Stop mode, all EXTI Line pending bits (in Pending register \n(EXTI_PR)), all peripheral interrupts pending bits, the RTC Alarm \n(Alarm A and Alarm B), RTC wake-up, RTC tamper, and RTC time \nstamp flags, must be reset. Otherwise, the Stop mode entry \nprocedure is ignored and program execution continues.\n\n\n<>\n\nPower controller (PWR)\nRM0090\n134/1757\nRM0090 Rev 21\n5.3.5 \nStop mode (STM32F42xxx and STM32F43xxx)\nThe Stop mode is based on the Cortex®-M4 with FPU deepsleep mode combined with \nperipheral clock gating. The voltage regulator can be configured either in normal or low-\npower mode. In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI \nand the HSE RC oscillators are disabled. Internal SRAM and register contents are \npreserved. \nIn Stop mode, the power consumption can be further reduced by using additional settings in \nthe PWR_CR register. However this induces an additional startup delay when waking up \nfrom Stop mode (see Table 29).\nMode exit\nIf WFI or Return from ISR was used for entry:\nAny EXTI lines configured in Interrupt mode (the corresponding EXTI \nInterrupt vector must be enabled in the NVIC). The interrupt source can \nbe external interrupts or peripherals with wake-up capability. Refer to \nTable 62: Vector table for STM32F405xx/07xx and STM32F415xx/17xx \non page 375 and Table 63: Vector table for STM32F42xxx and \nSTM32F43xxx.\nIf WFE was used for entry and SEVONPEND = 0\nAny EXTI lines configured in event mode. Refer to Section 12.2.3: Wake-\nup event management on page 383.\nIf WFE was used for entry and SEVONPEND = 1: \n– Any EXTI lines configured in Interrupt mode (even if the corresponding \nEXTI Interrupt vector is disabled in the NVIC). The interrupt source can \nbe an external interrupt or a peripheral with wake-up capability. Refer to \nTable 62: Vector table for STM32F405xx/07xx and STM32F415xx/17xx \non page 375 and Table 63: Vector table for STM32F42xxx and \nSTM32F43xxx.\n– Wake-up event: refer to Section 12.2.3: Wake-up event management on \npage 383.\nWake-up latency\nTable 27: Stop operating modes (STM32F405xx/07xx and \nSTM32F415xx/17xx)\nTable 28. Stop mode entry and exit (for STM32F405xx/07xx and STM32F415xx/17xx) \nStop mode\nDescription\n\n\n<>\n\nRM0090 Rev 21\n135/1757\nRM0090\nPower controller (PWR)\n151\n \nEntering Stop mode (STM32F42xxx and STM32F43xxx)\nThe Stop mode is entered according to Section : Entering low-power mode, when the \nSLEEPDEEP bit in the Cortex®-M4 with FPU System Control register is set.\nRefer to Table 30 for details on how to enter the Stop mode.\nWhen the microcontroller enters in Stop mode, the voltage scale 3 is automatically selected. \nTo further reduce power consumption in Stop mode, the internal voltage regulator can be put \nin low voltage mode. This is configured by the LPDS, MRUDS, LPUDS and UDEN bits of \nthe PWR power control register (PWR_CR) for STM32F405xx/07xx and \nSTM32F415xx/17xx.\nIf Flash memory programming is ongoing, the Stop mode entry is delayed until the memory \naccess is finished. \nIf an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB \naccess is finished.\nIf the Over-drive mode was enabled before entering Stop mode, it is automatically disabled \nduring when the Stop mode is activated.\nTable 29. Stop operating modes (STM32F42xxx and STM32F43xxx)\nVoltage Regulator Mode \nUDEN[1:0] \nbits \nMRUDS \nbit \nLPUDS \nbit\nLPDS \nbit \nFPDS \nbit\nWake-up latency\nNormal \nmode\nSTOP MR\n(Main Regulator)\n - \n0\n - \n0\n0\nHSI RC startup time\nSTOP MR- FPD\n - \n0\n - \n0\n1\nHSI RC startup time +\nFlash wake-up time from power-\ndown mode\nSTOP LP\n - \n0\n0\n1\n0\nHSI RC startup time +\nregulator wake-up time from LP \nmode\nSTOP LP-FPD\n - \n - \n0\n1\n1\nHSI RC startup time +\nFlash wake-up time from power-\ndown mode +\nregulator wake-up time from LP \nmode\nUnder-\ndrive \nMode\nSTOP UMR-\nFPD\n3\n1\n - \n0\n - \nHSI RC startup time +\nFlash wake-up time from power-\ndown mode +\nMain regulator wake-up time from \nunder-drive mode + Core logic to \nnominal mode\nSTOP ULP-FPD\n3\n - \n1\n1\n - \nHSI RC startup time +\nFlash wake-up time from power-\ndown mode +\nregulator wake-up time from LP \nunder-drive mode + Core logic to \nnominal mode\n\n\n<>\n\nPower controller (PWR)\nRM0090\n136/1757\nRM0090 Rev 21\nIn Stop mode, the following features can be selected by programming individual control bits:\n•\nIndependent watchdog (IWDG): the IWDG is started by writing to its Key register or by \nhardware option. Once started it cannot be stopped except by a Reset. See \nSection 21.3 in Section 21: Independent watchdog (IWDG).\n•\nReal-time clock (RTC): this is configured by the RTCEN bit in the Section 7.3.20: RCC \nBackup domain control register (RCC_BDCR)\n•\nInternal RC oscillator (LSI RC): this is configured by the LSION bit in the \nSection 7.3.21: RCC clock control & status register (RCC_CSR).\n•\nExternal 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the \nRCC Backup domain control register (RCC_BDCR).\nThe ADC or DAC can also consume power during the Stop mode, unless they are disabled \nbefore entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit \nin the DAC_CR register must both be written to 0.\nNote:\nBefore entering Stop mode, it is recommended to enable the clock security system (CSS) \nfeature to prevent external oscillator (HSE) failure from impacting the internal MCU \nbehavior.\nExiting Stop mode (STM32F42xxx and STM32F43xxx)\nThe Stop mode is exited according to Section : Exiting low-power mode.\nRefer to Table 30 for more details on how to exit Stop mode.\nWhen exiting Stop mode by issuing an interrupt or a wake-up event, the HSI RC oscillator is \nselected as system clock. \nIf the Under-drive mode was enabled, it is automatically disabled after exiting Stop mode.\nWhen the voltage regulator operates in low voltage mode, an additional startup delay is \nincurred when waking up from Stop mode. By keeping the internal regulator ON during Stop \nmode, the consumption is higher although the startup time is reduced.\nWhen the voltage regulator operates in Under-drive mode, an additional startup delay is \ninduced when waking up from Stop mode.\n\n\n<>\n\nRM0090 Rev 21\n137/1757\nRM0090\nPower controller (PWR)\n151\n \n5.3.6 \nStandby mode\nThe Standby mode allows to achieve the lowest power consumption. It is based on the \nCortex®-M4 with FPU deepsleep mode, with the voltage regulator disabled. The 1.2 V \ndomain is consequently powered off. The PLLs, the HSI oscillator and the HSE oscillator are \nalso switched off. SRAM and register contents are lost except for registers in the backup \ndomain (RTC registers, RTC backup register and backup SRAM), and Standby circuitry (see \nFigure 9).\nTable 30. Stop mode entry and exit (STM32F42xxx and STM32F43xxx)\nStop mode\nDescription\nMode entry\nWFI (Wait for Interrupt) or WFE (Wait for Event) while:\n– No interrupt or event is pending,\n– SLEEPDEEP bit is set in Cortex®-M4 with FPU System Control register,\n– PDDS bit is cleared in Power Control register (PWR_CR),\n– Select the voltage regulator mode by configuring LPDS, MRUDS, LPUDS \nand UDEN bits in PWR_CR (see Table 29: Stop operating modes \n(STM32F42xxx and STM32F43xxx)).\nOn Return from ISR while:\n– No interrupt is pending,\n– SLEEPDEEP bit is set in Cortex®-M4 with FPU System Control register, \nand\n– SLEEPONEXIT = 1, and\n– PDDS is cleared in PWR_CR1.\nNote: To enter Stop mode, all EXTI Line pending bits (in Pending register \n(EXTI_PR)), all peripheral interrupts pending bits, the RTC Alarm \n(Alarm A and Alarm B), RTC wake-up, RTC tamper, and RTC time \nstamp flags, must be reset. Otherwise, the Stop mode entry \nprocedure is ignored and program execution continues.\nMode exit\nIf WFI or Return from ISR was used for entry:\nAll EXTI lines configured in Interrupt mode (the corresponding EXTI \nInterrupt vector must be enabled in the NVIC). The interrupt source can \nbe external interrupts or peripherals with wake-up capability. Refer to \nTable 62: Vector table for STM32F405xx/07xx and STM32F415xx/17xx \non page 375.\nIf WFE was used for entry and SEVONPEND = 0:\nAll EXTI Lines configured in event mode. Refer to Section 12.2.3: Wake-\nup event management on page 383\nIf WFE was used for entry and SEVONPEND = 1: \n– Any EXTI lines configured in Interrupt mode (even if the corresponding \nEXTI Interrupt vector is disabled in the NVIC). The interrupt source can \nbe external interrupts or peripherals with wake-up capability. Refer to \nTable 62: Vector table for STM32F405xx/07xx and STM32F415xx/17xx \non page 375 and Table 63: Vector table for STM32F42xxx and \nSTM32F43xxx.\n– Wake-up event: refer to Section 12.2.3: Wake-up event management on \npage 383.\nWake-up latency\nRefer to Table 29: Stop operating modes (STM32F42xxx and \nSTM32F43xxx)\n\n\n<>\n\nPower controller (PWR)\nRM0090\n138/1757\nRM0090 Rev 21\nEntering Standby mode\nThe Standby mode is entered according to Section : Entering low-power mode, when the \nSLEEPDEEP bit in the Cortex®-M4 with FPU System Control register is set. \nRefer to Table 31 for more details on how to enter Standby mode.\nIn Standby mode, the following features can be selected by programming individual control \nbits:\n•\nIndependent watchdog (IWDG): the IWDG is started by writing to its Key register or by \nhardware option. Once started it cannot be stopped except by a reset. See \nSection 21.3 in Section 21: Independent watchdog (IWDG).\n•\nReal-time clock (RTC): this is configured by the RTCEN bit in the backup domain \ncontrol register (RCC_BDCR) \n•\nInternal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status \nregister (RCC_CSR). \n•\nExternal 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the \nbackup domain control register (RCC_BDCR)\nExiting Standby mode\nThe Standby mode is exited according to Section : Exiting low-power mode. The SBF status \nflag in PWR_CR (see Section 5.4.2: PWR power control/status register (PWR_CSR) for \nSTM32F405xx/07xx and STM32F415xx/17xx) indicates that the MCU was in Standby \nmode. All registers are reset after wake-up from Standby except for PWR_CR.\nRefer to Table 31 for more details on how to exit Standby mode.\n \n \nTable 31. Standby mode entry and exit\nStandby mode\nDescription\nMode entry\nWFI (Wait for Interrupt) or WFE (Wait for Event) while:\n– SLEEPDEEP is set in Cortex®-M4 with FPU System Control register,\n– PDDS bit is set in Power Control register (PWR_CR),\n– No interrupt (for WFI) or event (for WFE) is pending,\n– WUF bit is cleared in Power Control register (PWR_CR),\n– the RTC flag corresponding to the chosen wake-up source (RTC Alarm \nA, RTC Alarm B, RTC wake-up, Tamper or Timestamp flags) is cleared\nOn return from ISR while:\n– SLEEPDEEP bit is set in Cortex®-M4 with FPU System Control register, \nand\n– SLEEPONEXIT = 1, and\n– PDDS bit is set in Power Control register (PWR_CR), and\n– No interrupt is pending,\n– WUF bit is cleared in Power Control/Status register (PWR_SR),\n– The RTC flag corresponding to the chosen wake-up source (RTC Alarm \nA, RTC Alarm B, RTC wake-up, Tamper or Timestamp flags) is cleared.\nMode exit\nWKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up, \ntamper event, time stamp event, external reset in NRST pin, IWDG reset.\nWake-up latency\nReset phase.\n\n\n<>\n\nRM0090 Rev 21\n139/1757\nRM0090\nPower controller (PWR)\n151\nI/O states in Standby mode\nIn Standby mode, all I/O pins are high impedance except for:\n•\nReset pad (still available)\n•\nRTC_AF1 pin (PC13) if configured for tamper, time stamp, RTC Alarm out, or RTC \nclock calibration out\n•\nWKUP pin (PA0), if enabled\nDebug mode\nBy default, the debug connection is lost if the application puts the MCU in Stop or Standby \nmode while the debug features are used. This is due to the fact that the Cortex®-M4 with \nFPU core is no longer clocked.\nHowever, by setting some configuration bits in the DBGMCU_CR register, the software can \nbe debugged even when using the low-power modes extensively. For more details, refer to \nSection 38.16.1: Debug support for low-power modes.\n5.3.7 \nProgramming the RTC alternate functions to wake up the device from\nthe Stop and Standby modes\nThe MCU can be woken up from a low-power mode by an RTC alternate function.\nThe RTC alternate functions are the RTC alarms (Alarm A and Alarm B), RTC wake-up, \nRTC tamper event detection and RTC time stamp event detection.\nThese RTC alternate functions can wake up the system from the Stop and Standby low-\npower modes.\nThe system can also wake up from low-power modes without depending on an external \ninterrupt (Auto-wake-up mode), by using the RTC alarm or the RTC wake-up events.\nThe RTC provides a programmable time base for waking up from the Stop or Standby mode \nat regular intervals.\nFor this purpose, two of the three alternate RTC clock sources can be selected by \nprogramming the RTCSEL[1:0] bits in the Section 7.3.20: RCC Backup domain control \nregister (RCC_BDCR):\n•\nLow-power 32.768 kHz external crystal oscillator (LSE OSC)\nThis clock source provides a precise time base with a very low-power consumption \n(additional consumption of less than 1 µA under typical conditions)\n•\nLow-power internal RC oscillator (LSI RC)\nThis clock source has the advantage of saving the cost of the 32.768 kHz crystal. This \ninternal RC oscillator is designed to use minimum power.\n\n\n<>\n\nPower controller (PWR)\nRM0090\n140/1757\nRM0090 Rev 21\nRTC alternate functions to wake up the device from the Stop mode\n•\nTo wake up the device from the Stop mode with an RTC alarm event, it is necessary to:\na) \nConfigure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event \nmodes)\nb) \nEnable the RTC Alarm Interrupt in the RTC_CR register\nc) \nConfigure the RTC to generate the RTC alarm\n•\nTo wake up the device from the Stop mode with an RTC tamper or time stamp event, it \nis necessary to:\na) \nConfigure the EXTI Line 21 to be sensitive to rising edges (Interrupt or Event \nmodes)\nb) \nEnable the RTC time stamp Interrupt in the RTC_CR register or the RTC tamper \ninterrupt in the RTC_TAFCR register\nc) \nConfigure the RTC to detect the tamper or time stamp event\n•\nTo wake up the device from the Stop mode with an RTC wake-up event, it is necessary \nto:\na) \nConfigure the EXTI Line 22 to be sensitive to rising edges (Interrupt or Event \nmodes)\nb) \nEnable the RTC wake-up interrupt in the RTC_CR register\nc) \nConfigure the RTC to generate the RTC Wake-up event \nRTC alternate functions to wake up the device from the Standby mode\n•\nTo wake up the device from the Standby mode with an RTC alarm event, it is necessary \nto:\na) \nEnable the RTC alarm interrupt in the RTC_CR register\nb) \nConfigure the RTC to generate the RTC alarm\n•\nTo wake up the device from the Standby mode with an RTC tamper or time stamp \nevent, it is necessary to:\na) \nEnable the RTC time stamp interrupt in the RTC_CR register or the RTC tamper \ninterrupt in the RTC_TAFCR register\nb) \nConfigure the RTC to detect the tamper or time stamp event\n•\nTo wake up the device from the Standby mode with an RTC wake-up event, it is \nnecessary to:\na) \nEnable the RTC wake-up interrupt in the RTC_CR register\nb) \nConfigure the RTC to generate the RTC wake-up event\nSafe RTC alternate function wake-up flag clearing sequence\nIf the selected RTC alternate function is set before the PWR wake-up flag (WUTF) is \ncleared, it is not detected on the next event as detection is made once on the rising edge.\nTo avoid bouncing on the pins onto which the RTC alternate functions are mapped, and exit \ncorrectly from the Stop and Standby modes, it is recommended to follow the sequence \nbelow before entering the Standby mode:\n•\nWhen using RTC alarm to wake up the device from the low-power modes:\na) \nDisable the RTC alarm interrupt (ALRAIE or ALRBIE bits in the RTC_CR register)\nb) \nClear the RTC alarm (ALRAF/ALRBF) flag\n\n\n<>\n\nRM0090 Rev 21\n141/1757\nRM0090\nPower controller (PWR)\n151\nc) \nClear the PWR Wake-up (WUF) flag\nd) \nEnable the RTC alarm interrupt\ne) \nRe-enter the low-power mode\n•\nWhen using RTC wake-up to wake up the device from the low-power modes:\na) \nDisable the RTC Wake-up interrupt (WUTIE bit in the RTC_CR register)\nb) \nClear the RTC Wake-up (WUTF) flag\nc) \nClear the PWR Wake-up (WUF) flag\nd) \nEnable the RTC Wake-up interrupt\ne) \nRe-enter the low-power mode\n•\nWhen using RTC tamper to wake up the device from the low-power modes:\na) \nDisable the RTC tamper interrupt (TAMPIE bit in the RTC_TAFCR register)\nb) \nClear the Tamper (TAMP1F/TSF) flag\nc) \nClear the PWR Wake-up (WUF) flag\nd) \nEnable the RTC tamper interrupt\ne) \nRe-enter the low-power mode\n•\nWhen using RTC time stamp to wake up the device from the low-power modes:\na) \nDisable the RTC time stamp interrupt (TSIE bit in RTC_CR)\nb) \nClear the RTC time stamp (TSF) flag\nc) \nClear the PWR Wake-up (WUF) flag\nd) \nEnable the RTC TimeStamp interrupt\ne) \nRe-enter the low-power mode\n\n\n<>\n\nPower controller (PWR)\nRM0090\n142/1757\nRM0090 Rev 21\n5.4 \nPower control registers (STM32F405xx/07xx and \nSTM32F415xx/17xx)\n5.4.1 \nPWR power control register (PWR_CR) \nfor STM32F405xx/07xx and STM32F415xx/17xx\nAddress offset: 0x00\nReset value: 0x0000 4000 (reset by wake-up from Standby mode)\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nVOS\nReserved\nFPDS\nDBP\nPLS[2:0]\nPVDE\nCSBF\nCWUF\nPDDS\nLPDS\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nw\nw\nrw\nrw\nBits 31:15 Reserved, must be kept at reset value.\nBit 14 VOS: Regulator voltage scaling output selection\nThis bit controls the main internal voltage regulator output voltage to achieve a trade-off \nbetween performance and power consumption when the device does not operate at the \nmaximum frequency.\n0: Scale 2 mode\n1: Scale 1 mode (default value at reset) \nBits 13:10 Reserved, must be kept at reset value.\nBit 9 FPDS: Flash power-down in Stop mode\nWhen set, the Flash memory enters power-down mode when the device enters Stop mode. \nThis allows to achieve a lower consumption in stop mode but a longer restart time.\n0: Flash memory not in power-down when the device is in Stop mode\n1: Flash memory in power-down when the device is in Stop mode\nBit 8 DBP: Disable backup domain write protection\nIn reset state, the RCC_BDCR register, the RTC registers (including the backup registers), \nand the BRE bit of the PWR_CSR register, are protected against parasitic write access. This \nbit must be set to enable write access to these registers.\n0: Access to RTC and RTC Backup registers and backup SRAM disabled\n1: Access to RTC and RTC Backup registers and backup SRAM enabled\nNote: Depending on the APB1 prescaler, there is a delay between writing to DBP and the \neffective disabling/enabling of the backup domain protection. Therefore, a dummy read \noperation to the PWR_CR register is required just after writing to the DBP bit.\n\n\n<>\n\nRM0090 Rev 21\n143/1757\nRM0090\nPower controller (PWR)\n151\n5.4.2 \nPWR power control/status register (PWR_CSR) \nfor STM32F405xx/07xx and STM32F415xx/17xx\nAddress offset: 0x04\nReset value: 0x0000 0000 (not reset by wake-up from Standby mode)\nAdditional APB cycles are needed to read this register versus a standard APB read.\n \nBits 7:5 PLS[2:0]: PVD level selection\nThese bits are written by software to select the voltage threshold detected by the \nprogrammable voltage detector\n000: 2.0 V\n001: 2.1 V\n010: 2.3 V\n011: 2.5 V\n100: 2.6 V\n101: 2.7 V\n110: 2.8 V\n111: 2.9 V\nNote: Refer to the electrical characteristics of the datasheet for more details.\nBit 4 PVDE: Programmable voltage detector enable\nThis bit is set and cleared by software. \n0: PVD disabled\n1: PVD enabled\nBit 3 CSBF: Clear standby flag\nThis bit is always read as 0.\n0: No effect\n1: Clear the SBF Standby Flag (write).\nBit 2 CWUF: Clear wake-up flag\nThis bit is always read as 0.\n0: No effect\n1: Clear the WUF Wake-up Flag after 2 System clock cycles\nBit 1 PDDS: Power-down deepsleep\nThis bit is set and cleared by software. It works together with the LPDS bit. \n0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the \nLPDS bit.\n1: Enter Standby mode when the CPU enters deepsleep. \nBit 0 LPDS: Low-power deepsleep\nThis bit is set and cleared by software. It works together with the PDDS bit.\n0: Voltage regulator on during Stop mode\n1: Voltage regulator in low-power mode during Stop mode\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes\nVOS\nRDY\nReserved\nBRE\nEWUP\nReserved\nBRR\nPVDO\nSBF\nWUF\nr\nrw\nrw\nr\nr\nr\nr\n\n\n<>\n\nPower controller (PWR)\nRM0090\n144/1757\nRM0090 Rev 21\n \nBits 31:15 Reserved, must be kept at reset value.\nBit 14 VOSRDY: Regulator voltage scaling output selection ready bit\n0: Not ready \n1: Ready\nBits 13:10 Reserved, must be kept at reset value.\nBit 9 BRE: Backup regulator enable\nWhen set, the Backup regulator (used to maintain backup SRAM content in Standby and \nVBAT modes) is enabled. If BRE is reset, the backup regulator is switched off. The backup \nSRAM can still be used but its content is lost in the Standby and VBAT modes. Once set, the \napplication must wait that the Backup Regulator Ready flag (BRR) is set to indicate that the \ndata written into the RAM is maintained in the Standby and VBAT modes.\n0: Backup regulator disabled\n1: Backup regulator enabled\nNote: This bit is not reset when the device wakes up from Standby mode, by a system reset, \nor by a power reset.\nThe DBP bit of the PWR_CR register must be set before BRE can be written.\nBit 8 EWUP: Enable WKUP pin\nThis bit is set and cleared by software.\n0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wake up \nthe device from Standby mode.\n1: WKUP pin is used for wake-up from Standby mode and forced in input pull down \nconfiguration (rising edge on WKUP pin wakes-up the system from Standby mode).\nNote: This bit is reset by a system reset.\nBits 7:4 Reserved, must be kept at reset value.\nBit 3 BRR: Backup regulator ready\nSet by hardware to indicate that the Backup Regulator is ready.\n0: Backup Regulator not ready\n1: Backup Regulator ready\nNote: This bit is not reset when the device wakes up from Standby mode or by a system reset \nor power reset.\nBit 2 PVDO: PVD output\nThis bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit. \n0: VDD is higher than the PVD threshold selected with the PLS[2:0] bits. \n1: VDD is lower than the PVD threshold selected with the PLS[2:0] bits.\nNote: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after \nStandby or reset until the PVDE bit is set.\nBit 1 SBF: Standby flag\nThis bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down \nreset) or by setting the CSBF bit in the PWR_CR register.\n0: Device has not been in Standby mode\n1: Device has been in Standby mode\n\n\n<>\n\nRM0090 Rev 21\n145/1757\nRM0090\nPower controller (PWR)\n151\nBit 0 WUF: Wake-up flag\nThis bit is set by hardware and cleared either by a system reset or by setting the CWUF bit in \nthe PWR_CR register.\n0: No wake-up event occurred\n1: A wake-up event was received from the WKUP pin or from the RTC alarm (Alarm A or \nAlarm B), RTC Tamper event, RTC TimeStamp event or RTC Wake-up).\nNote: An additional wake-up event is detected if the WKUP pin is enabled (by setting the \nEWUP bit) when the WKUP pin level is already high.\n\n\n<>\n\nPower controller (PWR)\nRM0090\n146/1757\nRM0090 Rev 21\n5.5 \nPower control registers (STM32F42xxx and STM32F43xxx)\n5.5.1 \nPWR power control register (PWR_CR) \nfor STM32F42xxx and STM32F43xxx\nAddress offset: 0x00\nReset value: 0x0000 C000 (reset by wake-up from Standby mode)\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nUDEN[1:0]\nODSWE\nN\nODEN\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nVOS[1:0]\nADCDC1\nRes.\nMRUDS\nLPUDS\nFPDS\nDBP\nPLS[2:0]\nPVDE\nCSBF\nCWUF\nPDDS\nLPDS\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrc_w1\nrc_w1\nrw\nrw\nBits 31:20 Reserved, must be kept at reset value.\nBits 19:18 UDEN[1:0]: Under-drive enable in stop mode\nThese bits are set by software. They allow to achieve a lower power consumption in Stop \nmode but with a longer wake-up time.\nWhen set, the digital area has less leakage consumption when the device enters Stop mode.\n00: Under-drive disable\n01: Reserved\n10: Reserved\n11:Under-drive enable\nBit 17 ODSWEN: Over-drive switching enabled.\nThis bit is set by software. It is cleared automatically by hardware after exiting from Stop \nmode or when the ODEN bit is reset. When set, It is used to switch to Over-drive mode.\nTo set or reset the ODSWEN bit, the HSI or HSE must be selected as system clock. \nThe ODSWEN bit must only be set when the ODRDY flag is set to switch to Over-drive \nmode. \n0: Over-drive switching disabled\n1: Over-drive switching enabled\nNote: On any over-drive switch (enabled or disabled), the system clock is stalled during the \ninternal voltage set up. \nBit 16 ODEN: Over-drive enable \nThis bit is set by software. It is cleared automatically by hardware after exiting from Stop \nmode. It is used to enabled the Over-drive mode in order to reach a higher frequency. \nTo set or reset the ODEN bit, the HSI or HSE must be selected as system clock. When the \nODEN bit is set, the application must first wait for the Over-drive ready flag (ODRDY) to be \nset before setting the ODSWEN bit.\n0: Over-drive disabled\n1: Over-drive enabled\n\n\n<>\n\nRM0090 Rev 21\n147/1757\nRM0090\nPower controller (PWR)\n151\nBits 15:14 VOS[1:0]: Regulator voltage scaling output selection\nThese bits control the main internal voltage regulator output voltage to achieve a trade-off \nbetween performance and power consumption when the device does not operate at the \nmaximum frequency (refer to the STM32F42xx and STM32F43xx datasheets for more \ndetails).\nThese bits can be modified only when the PLL is OFF. The new value programmed is active \nonly when the PLL is ON. When the PLL is OFF, the voltage scale 3 is automatically \nselected.\n00: Reserved (Scale 3 mode selected)\n01: Scale 3 mode\n10: Scale 2 mode\n11: Scale 1 mode (reset value)\nBit 13 ADCDC1: \n0: No effect. \n1: Refer to AN4073 for details on how to use this bit. \nNote: This bit can only be set when operating at supply voltage range 2.7 to 3.6V and when \nthe Prefetch is OFF. \nBit 12 Reserved, must be kept at reset value.\nBit 11 MRUDS: Main regulator in deepsleep under-drive mode\nThis bit is set and cleared by software. \n0: Main regulator ON when the device is in Stop mode\n1: Main Regulator in under-drive mode and Flash memory in power-down when the device is \nin Stop under-drive mode. \nBit 10 LPUDS: Low-power regulator in deepsleep under-drive mode\nThis bit is set and cleared by software. \n0: Low-power regulator ON if LPDS bit is set when the device is in Stop mode\n1: Low-power regulator in under-drive mode if LPDS bit is set and Flash memory in power-\ndown when the device is in Stop under-drive mode.\nBit 9 FPDS: Flash power-down in Stop mode\nWhen set, the Flash memory enters power-down mode when the device enters Stop mode. \nThis allows to achieve a lower consumption in stop mode but a longer restart time.\n0: Flash memory not in power-down when the device is in Stop mode\n1: Flash memory in power-down when the device is in Stop mode\nBit 8 DBP: Disable backup domain write protection\nIn reset state, the RCC_BDCR register, the RTC registers (including the backup registers), \nand the BRE bit of the PWR_CSR register, are protected against parasitic write access. This \nbit must be set to enable write access to these registers.\n0: Access to RTC and RTC Backup registers and backup SRAM disabled\n1: Access to RTC and RTC Backup registers and backup SRAM enabled\n\n\n<>\n\nPower controller (PWR)\nRM0090\n148/1757\nRM0090 Rev 21\nBits 7:5 PLS[2:0]: PVD level selection\nThese bits are written by software to select the voltage threshold detected by the \nprogrammable voltage detector\n000: 2.0 V\n001: 2.1 V\n010: 2.3 V\n011: 2.5 V\n100: 2.6 V\n101: 2.7 V\n110: 2.8 V\n111: 2.9 V\nNote: Refer to the electrical characteristics of the datasheet for more details.\nBit 4 PVDE: Programmable voltage detector enable\nThis bit is set and cleared by software. \n0: PVD disabled\n1: PVD enabled\nBit 3 CSBF: Clear standby flag\nThis bit is always read as 0.\n0: No effect\n1: Clear the SBF Standby Flag (write).\nBit 2 CWUF: Clear wake-up flag\nThis bit is always read as 0.\n0: No effect\n1: Clear the WUF Wake-up Flag after 2 System clock cycles\nBit 1 PDDS: Power-down deepsleep\nThis bit is set and cleared by software. It works together with the LPDS bit. \n0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the \nLPDS bit.\n1: Enter Standby mode when the CPU enters deepsleep. \nBit 0 LPDS: Low-power deepsleep\nThis bit is set and cleared by software. It works together with the PDDS bit.\n0:Main voltage regulator ON during Stop mode\n1: Low-power voltage regulator ON during Stop mode\n\n\n<>\n\nRM0090 Rev 21\n149/1757\nRM0090\nPower controller (PWR)\n151\n5.5.2 \nPWR power control/status register (PWR_CSR)\nfor STM32F42xxx and STM32F43xxx\nAddress offset: 0x04\nReset value: 0x0000 0000 (not reset by wake-up from Standby mode)\nAdditional APB cycles are needed to read this register versus a standard APB read.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nUDRDY[1:0]\nODSWRDY\nODRDY\nrc_w1\nrc_w1\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes\nVOS\nRDY\nReserved\nBRE\nEWUP\nReserved.\nBRR\nPVDO\nSBF\nWUF\nr\nrw\nrw\nr\nr\nr\nr\nBits 31:20 Reserved, must be kept at reset value.\nBits 19:18 UDRDY[1:0]: Under-drive ready flag\nThese bits are set by hardware when MCU entered stop Under-drive mode and exited. \nWhen the under-drive mode is enabled, these bits are not set as long as the MCU has not \nentered stop mode yet. They are cleared by programming them to 1.\n00: Under-drive is disabled\n01: Reserved\n10: Reserved\n11:Under-drive mode is activated in Stop mode.\nBit 17 ODSWRDY: Over-drive mode switching ready\n0: Over-drive mode is not active.\n1: Over-drive mode is active on digital area on 1.2 V domain\nBit 16 ODRDY: Over-drive mode ready\n0: Over-drive mode not ready.\n1: Over-drive mode ready\nBit 14 VOSRDY: Regulator voltage scaling output selection ready bit\n0: Not ready \n1: Ready\nBits 13:10 Reserved, must be kept at reset value.\nBit 9 BRE: Backup regulator enable\nWhen set, the Backup regulator (used to maintain backup SRAM content in Standby and \nVBAT modes) is enabled. If BRE is reset, the backup regulator is switched off. The backup \nSRAM can still be used but its content is lost in the Standby and VBAT modes. Once set, the \napplication must wait that the Backup Regulator Ready flag (BRR) is set to indicate that the \ndata written into the RAM is maintained in the Standby and VBAT modes.\n0: Backup regulator disabled\n1: Backup regulator enabled\nNote: This bit is not reset when the device wakes up from Standby mode, by a system reset, \nor by a power reset.\nThe DBP bit of the PWR_CR register must be set before BRE can be written.\n\n\n<>\n\nPower controller (PWR)\nRM0090\n150/1757\nRM0090 Rev 21\nBit 8 EWUP: Enable WKUP pin\nThis bit is set and cleared by software.\n0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wake up \nthe device from Standby mode.\n1: WKUP pin is used for wake-up from Standby mode and forced in input pull down \nconfiguration (rising edge on WKUP pin wakes-up the system from Standby mode).\nNote: This bit is reset by a system reset.\nBits 7:4 Reserved, must be kept at reset value.\nBit 3 BRR: Backup regulator ready\nSet by hardware to indicate that the Backup Regulator is ready.\n0: Backup Regulator not ready\n1: Backup Regulator ready\nNote: This bit is not reset when the device wakes up from Standby mode or by a system reset \nor power reset.\nBit 2 PVDO: PVD output\nThis bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit. \n0: VDD is higher than the PVD threshold selected with the PLS[2:0] bits. \n1: VDD is lower than the PVD threshold selected with the PLS[2:0] bits.\nNote: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after \nStandby or reset until the PVDE bit is set.\nBit 1 SBF: Standby flag\nThis bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down \nreset) or by setting the CSBF bit in the PWR power control register (PWR_CR) for \nSTM32F405xx/07xx and STM32F415xx/17xx\n0: Device has not been in Standby mode\n1: Device has been in Standby mode\nBit 0 WUF: Wake-up flag\nThis bit is set by hardware and cleared either by a system reset or by setting the CWUF bit in \nthe PWR_CR register.\n0: No wake-up event occurred\n1: A wake-up event was received from the WKUP pin or from the RTC alarm (Alarm A or \nAlarm B), RTC Tamper event, RTC TimeStamp event or RTC Wake-up).\nNote: An additional wake-up event is detected if the WKUP pin is enabled (by setting the \nEWUP bit) when the WKUP pin level is already high.\n\n\n<>\n\nRM0090 Rev 21\n151/1757\nRM0090\nPower controller (PWR)\n151\n5.6 \nPWR register map\nThe following table summarizes the PWR registers.\n \n \nRefer to Section 2.3: Memory map for the register boundary addresses.\nTable 32. PWR - register map and reset values for\nSTM32F405xx/07xx and STM32F415xx/17xx\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x000\nPWR_CR\nReserved\nVOS\nReserved\nFPDS\nDBP\nPLS[2:0]\nPVDE\nCSBF\nCWUF\nPDDS\nLPDS\nReset value\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x004\nPWR_CSR\nReserved\nVOSRDY\nReserved\nBRE\nEWUP\nReserved\nBRR\nPVDO\nSBF\nWUF\nReset value\n0\n0\n0\n0\n0\n0\n0\nTable 33. PWR - register map and reset values for STM32F42xxx and STM32F43xxx\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x000\nPWR_CR\nReserved\nUDEN[1:0]\nODSWEN\nODEN\nVOS[1:0]\nADCDC1\nReserved\nMRUDS\nLPUDS\nFPDS\nDBP\nPLS[2:0]\nPVDE\nCSBF\nCWUF\nPDDS\nLPDS\nReset value\n0\n0\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x004\nPWR_CSR\nReserved\nUDRDY[1:0]\nODSWRDY\nODRDY\nReserved\nVOSRDY\nReserved\nBRE\nEWUP\nReserved\nBRR\nPVDO\nSBF\nWUF\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n152/1757\nRM0090 Rev 21\n6 \nReset and clock control for \nSTM32F42xxx and STM32F43xxx (RCC)\n6.1 \nReset\nThere are three types of reset, defined as system Reset, power Reset and backup domain \nReset. \n6.1.1 \nSystem reset\nA system reset sets all registers to their reset values unless specified otherwise in the \nregister description (see Figure 10).\nA system reset is generated when one of the following events occurs:\n1.\nA low level on the NRST pin (external reset)\n2. \nWindow watchdog end of count condition (WWDG reset)\n3. \nIndependent watchdog end of count condition (IWDG reset)\n4. \nA software reset (SW reset) (see Software reset)\n5. \nLow-power management reset (see Low-power management reset)\nSoftware reset\nThe reset source can be identified by checking the reset flags in the RCC clock control & \nstatus register (RCC_CSR).\nThe SYSRESETREQ bit in Cortex®-M4 with FPU Application Interrupt and Reset Control \nRegister must be set to force a software reset on the device. Refer to the Cortex®-M4 with \nFPU technical reference manual for more details.\nLow-power management reset\nThere are two ways of generating a low-power management reset:\n1.\nReset generated when entering the Standby mode:\nThis type of reset is enabled by resetting the nRST_STDBY bit in the user option bytes. \nIn this case, whenever a Standby mode entry sequence is successfully executed, the \ndevice is reset instead of entering the Standby mode.\n2. \nReset when entering the Stop mode:\nThis type of reset is enabled by resetting the nRST_STOP bit in the user option bytes. \nIn this case, whenever a Stop mode entry sequence is successfully executed, the \ndevice is reset instead of entering the Stop mode.\n6.1.2 \nPower reset\nA power reset is generated when one of the following events occurs: \n1.\nPower-on/power-down reset (POR/PDR reset) or brownout (BOR) reset\n2. \nWhen exiting the Standby mode\nA power reset sets all registers to their reset values except the Backup domain (see \nFigure 10)\n\n\n<>\n\nRM0090 Rev 21\n153/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nThese sources act on the NRST pin and it is always kept low during the delay phase. The \nRESET service routine vector is fixed at address 0x0000_0004 in the memory map.\nThe system reset signal provided to the device is output on the NRST pin. The pulse \ngenerator guarantees a minimum reset pulse duration of 20 µs for each internal reset \nsource. In case of an external reset, the reset pulse is generated while the NRST pin is \nasserted low.\nFigure 15. Simplified diagram of the reset circuit\nThe Backup domain has two specific resets that affect only the Backup domain (see \nFigure 10).\n6.1.3 \nBackup domain reset\nThe backup domain reset sets all RTC registers, the RCC_BDCR register, and the BRE bit \nof the PWR_CSR register to their reset values. The BKPSRAM is not affected by this reset. \nThe only way of resetting the BKPSRAM is through the Flash interface by requesting a \nprotection level change from 1 to 0.\nA backup domain reset is generated when one of the following events occurs:\n1.\nSoftware reset, triggered by setting the BDRST bit in the RCC Backup domain control \nregister (RCC_BDCR). \n2. \nVDD or VBAT power on, if both supplies have previously been powered off.\nNote:\nThe DBP bit of the PWR_CR register must be set to generate a backup domain reset.\n6.2 \nClocks\nThree different clock sources can be used to drive the system clock (SYSCLK):\n•\nHSI oscillator clock\n•\nHSE oscillator clock\n•\nMain PLL (PLL) clock\nThe devices have the two following secondary clock sources:\n•\n32 kHz low-speed internal RC (LSI RC) which drives the independent watchdog and, \noptionally, the RTC used for Auto-wakeup from the Stop/Standby mode.\n•\n32.768 kHz low-speed external crystal (LSE crystal) which optionally drives the RTC \nclock (RTCCLK)\nNRST\nRPU\nVDD/VDDA\nWWDG reset\nIWDG reset\nPulse\ngenerator\nPower reset\nExternal\nreset\n(min 20 μs)\nSystem reset\nFilter\nSoftware reset\nLow-power management reset\nai16095c\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n154/1757\nRM0090 Rev 21\nEach clock source can be switched on or off independently when it is not used, to optimize \npower consumption.\nFigure 16. Clock tree\n1.\nFor full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in \nthe device datasheet.\n2.\nWhen TIMPRE bit of the RCC_DCKCFGR register is reset, if APBx prescaler is 1, then TIMxCLK = PCLKx, otherwise \nTIMxCLK = 2x PCLKx. \n3.\nWhen TIMPRE bit in the RCC_DCKCFGR register is set, if APBx prescaler is 1,2 or 4, then TIMxCLK = HCLK, otherwise \nTIMxCLK = 4x PCLKx.\nMSv30434V3\nPLL\nMII_RMII_SEL in SYSCFG_PMC to Ethernet MAC\nLSE\nETH_MII_TX_CLK_MII\nOTG_HS_ULPI_CK\nPLLI2SCLK\nFCLK Cortex\nfree-running clock\nAPBx peripheral clocks\n48 MHz\nclocks\nUSBHS\nULPI clock\nEthernet\nPTP clock\nMCO1\nMCO2\nETH_MII_RX_CLK_MI\nI\nOSC32_IN\nOSC32_OUT\nTo Independent\nwatchdog\nLSE\nLSI\nto RTC\nRTCCLK\nRTCSEL[1:0]\nIWDGCLK\nOSC_IN\nOSC_OUT\nPLLCLK\nHSI\nHSI\nHSE\nSW\nSYSCLK\n180 MHz\nmax\nHCLK\nto AHB bus, core,\nmemory and DMA\n180 MHz max.\nto Cortex System timer\nClock \nenable \nPLL48CK\nI2S clocks\nAHB\nPRESC\n/1,2,..512\nMACRMIICLK\nMACTXCLK\nMACRXCLK\nWatchdog\nenable\nRTC\nenable\nPeripheral\nclock enable\n/2 to 31\nPLLI2S\nSYSCLK\nExt. clock \nI2SSRC\nHSE_RTC\nHSE\nI2S_CKIN\nPHY Ethernet\n25 to 50 MHz\nUSB2.0 PHY\n24 to 60 MHz\nPLLSAI\nPLLSAICLK\nPLLLCDCLK\nPLLSAICLK\nSAI1_A clock\nSAI1_B clock\nLCD-TFT \nclock\nLSI RC\n32 kHz\nLSE OSC\n32.768 kHz\n/1 to 5\n/1 to 5\n16 MHz\nHSI RC\n4-26 MHz\nHSE OSC\nVCO\nxN\n/P\n/Q\n/R\n/M\nVCO\nxN\n/P\n/Q\n/R\nDIV\nDIV\nDIV\nVCO\nxN\n/P\n/Q\n/R\n/2,20\nPeripheral\nclock enable\nPeripheral\nclock enable\nPeripheral\nclock enable\nPeripheral\nclock enable\nPeripheral\nclock enable\nPeripheral\nclock enable\nPeripheral\nclock enable\nPeripheral\nclock enable\nPeripheral\nclock enable\nAPBx\nPRESC\n/1,2,4,8,16\nAPBx timer clocks\nif (APBx presc = \n1x1 else x2\nPeripheral clock \nenable\nPeripheral clock \nenable\n/8\n\n\n<>\n\nRM0090 Rev 21\n155/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nThe clock controller provides a high degree of flexibility to the application in the choice of the \nexternal crystal or the oscillator to run the core and peripherals at the highest frequency \nand, guarantee the appropriate frequency for peripherals that need a specific clock like \nEthernet, USB OTG FS and HS, I2S, SAI, LTDC, and SDIO.\nSeveral prescalers are used to configure the AHB frequency, the high-speed APB (APB2) \nand the low-speed APB (APB1) domains. The maximum frequency of the AHB domain is \n180 MHz. The maximum allowed frequency of the high-speed APB2 domain is 90 MHz. The \nmaximum allowed frequency of the low-speed APB1 domain is 45 MHz\nAll peripheral clocks are derived from the system clock (SYSCLK) except for:\n•\nThe USB OTG FS clock (48 MHz), the random analog generator (RNG) clock \n(≤48 MHz) and the SDIO clock (≤ 48 MHz) which are coming from a specific output of \nPLL (PLL48CLK)\n•\nI2S clock\nTo achieve high-quality audio performance, the I2S clock can be derived either from a \nspecific PLL (PLLI2S) or from an external clock mapped on the I2S_CKIN pin. For \nmore information about I2S clock frequency and precision, refer to Section 28.4.4: \nClock generator.\n•\nSAI1 clock\nThe SAI1 clock is generated from a specific PLL (PLLSAI or PLLI2S) or from an \nexternal clock mapped on the I2S_CKIN pin. \nThe PLLSAI can be used as clock source for SAI1 peripheral in case the PLLI2S is \nprogrammed to achieve another audio sampling frequency (49.152 MHz or \n11.2896 MHz), and the application requires both frequencies at the same time.\n•\nLTDC clock\nThe LTDC clock is generated from a specific PLL (PLLSAI).\n•\nThe USB OTG HS (60 MHz) clock which is provided from the external PHY\n•\nThe Ethernet MAC clocks (TX, RX and RMII) which are provided from the external \nPHY. For further information on the Ethernet configuration, please refer to \nSection 33.4.4: MII/RMII selection in the Ethernet peripheral description. When the \nEthernet is used, the AHB clock frequency must be at least 25 MHz.\nThe RCC feeds the external clock of the Cortex System Timer (SysTick) with the AHB clock \n(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock \n(HCLK), configurable in the SysTick control and status register.\nThe timer clock frequencies for STM32F42xxx and STM32F43xxx are automatically set by \nhardware. There are two cases depending on the value of TIMPRE bit in RCC_CFGR \nregister:\n•\nIf TIMPRE bit in RCC_DKCFGR register is reset:\nIf the APB prescaler is configured to a division factor of 1, the timer clock frequencies \n(TIMxCLK) are set to PCLKx. Otherwise, the timer clock frequencies are twice the \nfrequency of the APB domain to which the timers are connected: TIMxCLK = 2xPCLKx.\n•\nIf TIMPRE bit in RCC_DKCFGR register is set:\nIf the APB prescaler is configured to a division factor of 1, 2 or 4, the timer clock \nfrequencies (TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies is four \ntimes the frequency of the APB domain to which the timers are connected: TIMxCLK = \n4xPCLKx.\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n156/1757\nRM0090 Rev 21\nFCLK acts as Cortex®-M4 with FPU free-running clock. For more details, refer to the \nCortex®-M4 with FPU technical reference manual.\n6.2.1 \nHSE clock\nThe high speed external clock signal (HSE) can be generated from two possible clock \nsources:\n•\nHSE external crystal/ceramic resonator\n•\nHSE external user clock\nThe resonator and the load capacitors have to be placed as close as possible to the \noscillator pins in order to minimize output distortion and startup stabilization time. The \nloading capacitance values must be adjusted according to the selected oscillator.\n \nExternal source (HSE bypass)\nIn this mode, an external clock source must be provided. You select this mode by setting the \nHSEBYP and HSEON bits in the RCC clock control register (RCC_CR). The external clock \nsignal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the \nOSC_OUT pin should be left HI-Z. See Figure 17.\nExternal crystal/ceramic resonator (HSE crystal)\nThe HSE has the advantage of producing a very accurate rate on the main clock.\nThe associated hardware configuration is shown in Figure 17. Refer to the electrical \ncharacteristics section of the datasheet for more details.\nThe HSERDY flag in the RCC clock control register (RCC_CR) indicates if the high-speed \nexternal oscillator is stable or not. At startup, the clock is not released until this bit is set by \nhardware. An interrupt can be generated if enabled in the RCC clock interrupt register \n(RCC_CIR).\nFigure 17. HSE/ LSE clock sources\nHardware configuration\nExternal clock\nCrystal/ceramic \nresonators\nOSC_OUT\nExternal\nsource\n(HI-Z)\nOSC_IN\nOSC_OUT\nLoad\ncapacitors\nCL2\nCL1\n\n\n<>\n\nRM0090 Rev 21\n157/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nThe HSE Crystal can be switched on and off using the HSEON bit in the RCC clock control \nregister (RCC_CR).\n6.2.2 \nHSI clock\nThe HSI clock signal is generated from an internal 16 MHz RC oscillator and can be used \ndirectly as a system clock, or used as PLL input.\nThe HSI RC oscillator has the advantage of providing a clock source at low cost (no external \ncomponents). It also has a faster startup time than the HSE crystal oscillator however, even \nwith calibration the frequency is less accurate than an external crystal oscillator or ceramic \nresonator. \nCalibration\nRC oscillator frequencies can vary from one chip to another due to manufacturing process \nvariations, this is why each device is factory calibrated by ST for 1% accuracy at TA= 25 °C.\nAfter reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the RCC clock \ncontrol register (RCC_CR). \nIf the application is subject to voltage or temperature variations this may affect the RC \noscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0] \nbits in the RCC clock control register (RCC_CR).\nThe HSIRDY flag in the RCC clock control register (RCC_CR) indicates if the HSI RC is \nstable or not. At startup, the HSI RC output clock is not released until this bit is set by \nhardware. \nThe HSI RC can be switched on and off using the HSION bit in the RCC clock control \nregister (RCC_CR).\nThe HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal \noscillator fails. Refer to Section 6.2.7: Clock security system (CSS) on page 159.\n6.2.3 \nPLL configuration\nThe STM32F4xx devices feature three PLLs:\n•\nA main PLL (PLL) clocked by the HSE or HSI oscillator and featuring two different \noutput clocks:\n–\nThe first output is used to generate the high speed system clock (up to 180 MHz)\n–\nThe second output is used to generate the clock for the USB OTG FS (48 MHz), \nthe random analog generator (≤ 48 MHz) and the SDIO (≤ 48 MHz). \n•\nTwo dedicated PLLs (PLLI2S and PLLSAI) used to generate an accurate clock to \nachieve high-quality audio performance on the I2S and SAI1 interfaces. PLLSAI is also \nused for the LCD-TFT clock.\nSince the main-PLL configuration parameters cannot be changed once PLL is enabled, it is \nrecommended to configure PLL before enabling it (selection of the HSI or HSE oscillator as \nPLL clock source, and configuration of division factors M, N, P, and Q). \nThe PLLI2S and PLLSAI use the same input clock as PLL (PLLM[5:0] and PLLSRC bits are \ncommon to both PLLs). However, the PLLI2S and PLLSAI have dedicated enable/disable \nand division factors (N and R) configuration bits. Once the PLLI2S and PLLSAI are enabled, \nthe configuration parameters cannot be changed.\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n158/1757\nRM0090 Rev 21\nThe three PLLs are disabled by hardware when entering Stop and Standby modes, or when \nan HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock. RCC \nPLL configuration register (RCC_PLLCFGR),RCC clock configuration register \n(RCC_CFGR), and RCC Dedicated Clock Configuration Register (RCC_DCKCFGR) can be \nused to configure PLL, PLLI2S, and PLLSAI.\n6.2.4 \nLSE clock\nThe LSE clock is generated from a 32.768 kHz low-speed external crystal or ceramic \nresonator. It has the advantage providing a low-power but highly accurate clock source to \nthe real-time clock peripheral (RTC) for clock/calendar or other timing functions. \nThe LSE oscillator is switched on and off using the LSEON bit in RCC Backup domain \ncontrol register (RCC_BDCR). \nThe LSERDY flag in the RCC Backup domain control register (RCC_BDCR) indicates if the \nLSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released \nuntil this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock \ninterrupt register (RCC_CIR).\nExternal source (LSE bypass)\nIn this mode, an external clock source must be provided. It must have a frequency up to \n1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the RCC Backup \ndomain control register (RCC_BDCR). The external clock signal (square, sinus or triangle) \nwith ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be \nleft HI-Z. See Figure 17.\n6.2.5 \nLSI clock\nThe LSI RC acts as an low-power clock source that can be kept running in Stop and \nStandby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The \nclock frequency is around 32 kHz. For more details, refer to the electrical characteristics \nsection of the datasheets.\nThe LSI RC can be switched on and off using the LSION bit in the RCC clock control & \nstatus register (RCC_CSR).\nThe LSIRDY flag in the RCC clock control & status register (RCC_CSR) indicates if the low-\nspeed internal oscillator is stable or not. At startup, the clock is not released until this bit is \nset by hardware. An interrupt can be generated if enabled in the RCC clock interrupt register \n(RCC_CIR).\n6.2.6 \nSystem clock (SYSCLK) selection\nAfter a system reset, the HSI oscillator is selected as the system clock. When a clock source \nis used directly or through PLL as the system clock, it is not possible to stop it.\nA switch from one clock source to another occurs only if the target clock source is ready \n(clock stable after startup delay or PLL locked). If a clock source that is not yet ready is \nselected, the switch occurs when the clock source is ready. Status bits in the RCC clock \ncontrol register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently \nused as the system clock.\n\n\n<>\n\nRM0090 Rev 21\n159/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.2.7 \nClock security system (CSS)\nThe clock security system can be activated by software. In this case, the clock detector is \nenabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.\nIf a failure is detected on the HSE clock, this oscillator is automatically disabled, a clock \nfailure event is sent to the break inputs of advanced-control timers TIM1 and TIM8, and an \ninterrupt is generated to inform the software about the failure (clock security system \ninterrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the \nCortex®-M4 with FPU NMI (non-maskable interrupt) exception vector.\nNote:\nWhen the CSS is enabled, if the HSE clock happens to fail, the CSS generates an interrupt, \nwhich causes the automatic generation of an NMI. The NMI is executed indefinitely unless \nthe CSS interrupt pending bit is cleared. As a consequence, the application has to clear the \nCSS interrupt in the NMI ISR by setting the CSSC bit in the Clock interrupt register \n(RCC_CIR).\nIf the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that \nit is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is \ndetected, then the system clock switches to the HSI oscillator and the HSE oscillator is \ndisabled. \nIf the HSE oscillator clock was the clock source of PLL used as the system clock when the \nfailure occurred, PLL is also disabled. In this case, if the PLLI2S was enabled, it is also \ndisabled when the HSE fails. \n6.2.8 \nRTC/AWU clock\nOnce the RTCCLK clock source has been selected, the only possible way of modifying the \nselection is to reset the power domain.\nThe RTCCLK clock source can be either the HSE 1 MHz (HSE divided by a programmable \nprescaler), the LSE or the LSI clock. This is selected by programming the RTCSEL[1:0] bits \nin the RCC Backup domain control register (RCC_BDCR) and the RTCPRE[4:0] bits in RCC \nclock configuration register (RCC_CFGR). This selection cannot be modified without \nresetting the Backup domain.\nIf the LSE is selected as the RTC clock, the RTC operates normally if the backup or the \nsystem supply disappears. If the LSI is selected as the AWU clock, the AWU state is not \nguaranteed if the system supply disappears. If the HSE oscillator divided by a value \nbetween 2 and 31 is used as the RTC clock, the RTC state is not guaranteed if the backup \nor the system supply disappears.\nThe LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. As a \nconsequence:\n•\nIf LSE is selected as the RTC clock:\n–\nThe RTC continues to work even if the VDD supply is switched off, provided the \nVBAT supply is maintained. \n•\nIf LSI is selected as the Auto-wakeup unit (AWU) clock:\n–\nThe AWU state is not guaranteed if the VDD supply is powered off. Refer to \nSection 6.2.5: LSI clock on page 158 for more details on LSI calibration.\n•\nIf the HSE clock is used as the RTC clock:\n–\nThe RTC state is not guaranteed if the VDD supply is powered off or if the internal \nvoltage regulator is powered off (removing power from the 1.2 V domain).\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n160/1757\nRM0090 Rev 21\nNote:\nTo read the RTC calendar register when the APB1 clock frequency is less than seven times \nthe RTC clock frequency (fAPB1 < 7xfRTCLCK), the software must read the calendar time and \ndate registers twice. The data are correct if the second read access to RTC_TR gives the \nsame result than the first one. Otherwise a third read access must be performed.\n6.2.9 \nWatchdog clock\nIf the independent watchdog (IWDG) is started by either hardware option or software \naccess, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator \ntemporization, the clock is provided to the IWDG.\n6.2.10 \nClock-out capability\nTwo microcontroller clock output (MCO) pins are available:\n•\nMCO1\nYou can output four different clock sources onto the MCO1 pin (PA8) using the \nconfigurable prescaler (from 1 to 5):\n–\nHSI clock\n–\nLSE clock\n–\nHSE clock\n–\nPLL clock\nThe desired clock source is selected using the MCO1PRE[2:0] and MCO1[1:0] bits in \nthe RCC clock configuration register (RCC_CFGR).\n•\nMCO2\nYou can output four different clock sources onto the MCO2 pin (PC9) using the \nconfigurable prescaler (from 1 to 5):\n–\nHSE clock\n–\nPLL clock\n–\nSystem clock (SYSCLK)\n–\nPLLI2S clock\nThe desired clock source is selected using the MCO2PRE[2:0] and MCO2 bits in the \nRCC clock configuration register (RCC_CFGR).\nFor the different MCO pins, the corresponding GPIO port has to be programmed in alternate \nfunction mode.\nThe selected clock to output onto MCO must not exceed 100 MHz (the maximum I/O \nspeed).\n6.2.11 \nInternal/external clock measurement using TIM5/TIM11\nIt is possible to indirectly measure the frequencies of all on-board clock source generators \nby means of the input capture of TIM5 channel4 and TIM11 channel1 as shown in Figure 18 \nand Figure 19.\nInternal/external clock measurement using TIM5 channel4\nTIM5 has an input multiplexer which allows choosing whether the input capture is triggered \nby the I/O or by an internal clock. This selection is performed through the TI4_RMP [1:0] bits \nin the TIM5_OR register.\n\n\n<>\n\nRM0090 Rev 21\n161/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nThe primary purpose of having the LSE connected to the channel4 input capture is to be \nable to precisely measure the HSI (this requires to have the HSI used as the system clock \nsource). The number of HSI clock counts between consecutive edges of the LSE signal \nprovides a measurement of the internal clock period. Taking advantage of the high precision \nof LSE crystals (typically a few tens of ppm) we can determine the internal clock frequency \nwith the same resolution, and trim the source to compensate for manufacturing-process \nand/or temperature- and voltage-related frequency deviations.\nThe HSI oscillator has dedicated, user-accessible calibration bits for this purpose.\nThe basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the \nprecision is therefore tightly linked to the ratio between the two clock sources. The greater \nthe ratio, the better the measurement.\nIt is also possible to measure the LSI frequency: this is useful for applications that do not \nhave a crystal. The ultralow-power LSI oscillator has a large manufacturing process \ndeviation: by measuring it versus the HSI clock source, it is possible to determine its \nfrequency with the precision of the HSI. The measured value can be used to have more \naccurate RTC time base timeouts (when LSI is used as the RTC clock source) and/or an \nIWDG timeout with an acceptable accuracy.\nUse the following procedure to measure the LSI frequency:\n1.\nEnable the TIM5 timer and configure channel4 in Input capture mode.\n2. \nThis bit is set the TI4_RMP bits in the TIM5_OR register to 0x01 to connect the LSI \nclock internally to TIM5 channel4 input capture for calibration purposes.\n3. \nMeasure the LSI clock frequency using the TIM5 capture/compare 4 event or interrupt.\n4. \nUse the measured LSI frequency to update the prescaler of the RTC depending on the \ndesired time base and/or to compute the IWDG timeout.\nFigure 18. Frequency measurement with TIM5 in Input capture mode\nInternal/external clock measurement using TIM11 channel1\nTIM11 has an input multiplexer which allows choosing whether the input capture is triggered \nby the I/O or by an internal clock. This selection is performed through TI1_RMP [1:0] bits in \nthe TIM11_OR register. The HSE_RTC clock (HSE divided by a programmable prescaler) is \nconnected to channel 1 input capture to have a rough indication of the external crystal \nfrequency. This requires that the HSI is the system clock source. This can be useful for \ninstance to ensure compliance with the IEC 60730/IEC 61335 standards which require to be \nable to determine harmonic or subharmonic frequencies (–50/+100% deviations). \nTIM5\nTI4\nTI4_RMP[1:0]\nGPIO\nRTC_WakeUp_IT\nLSE\nLSI\nai17741V2\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n162/1757\nRM0090 Rev 21\nFigure 19. Frequency measurement with TIM11 in Input capture mode\nTIM11\nTI1\nTI1_RMP[1:0]\nGPIO\nHSE_RTC(1 MHz)\nai18433\n\n\n<>\n\nRM0090 Rev 21\n163/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3 \nRCC registers\nRefer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in \nregister descriptions.\n6.3.1 \nRCC clock control register (RCC_CR)\nAddress offset: 0x00\nReset value: 0x0000 XX83 where X is undefined.\nAccess: no wait state, word, half-word and byte access\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPLLSAI\nRDY\nPLLSAI\nON\nPLLI2S\nRDY\nPLLI2S\nON\nPLLRD\nY\nPLLON\nReserved\nCSS \nON\nHSE \nBYP\nHSE\nRDY\nHSE \nON\nr\nrw\nr\nrw\nr\nrw\nrw\nrw\nr\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nHSICAL[7:0]\nHSITRIM[4:0]\nRes.\nHSI \nRDY\nHSION\nr\nr\nr\nr\nr\nr\nr\nr\nrw\nrw\nrw\nrw\nrw\nr\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBit 29 PLLSAIRDY: PLLSAI clock ready flag\nSet by hardware to indicate that the PLLSAI is locked.\n0: PLLSAI unlocked\n1: PLLSAI locked\nBit 28 PLLSAION: PLLSAI enable\nSet and cleared by software to enable PLLSAI.\nCleared by hardware when entering Stop or Standby mode. \n0: PLLSAI OFF\n1: PLLSAI ON\nBit 27 PLLI2SRDY: PLLI2S clock ready flag\nSet by hardware to indicate that the PLLI2S is locked.\n0: PLLI2S unlocked\n1: PLLI2S locked\nBit 26 PLLI2SON: PLLI2S enable\nSet and cleared by software to enable PLLI2S.\nCleared by hardware when entering Stop or Standby mode. \n0: PLLI2S OFF\n1: PLLI2S ON\nBit 25 PLLRDY: Main PLL (PLL) clock ready flag\nSet by hardware to indicate that PLL is locked.\n0: PLL unlocked\n1: PLL locked\nBit 24 PLLON: Main PLL (PLL) enable\nSet and cleared by software to enable PLL.\nCleared by hardware when entering Stop or Standby mode. This bit cannot be reset if PLL \nclock is used as the system clock.\n0: PLL OFF\n1: PLL ON\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n164/1757\nRM0090 Rev 21\nBits 23:20 Reserved, must be kept at reset value.\nBit 19 CSSON: Clock security system enable\nSet and cleared by software to enable the clock security system. When CSSON is set, the \nclock detector is enabled by hardware when the HSE oscillator is ready, and disabled by \nhardware if an oscillator failure is detected.\n0: Clock security system OFF (Clock detector OFF)\n1: Clock security system ON (Clock detector ON if HSE oscillator is stable, OFF if not)\nBit 18 HSEBYP: HSE clock bypass\nSet and cleared by software to bypass the oscillator with an external clock. The external \nclock must be enabled with the HSEON bit, to be used by the device.\nThe HSEBYP bit can be written only if the HSE oscillator is disabled.\n0: HSE oscillator not bypassed\n1: HSE oscillator bypassed with an external clock\nBit 17 HSERDY: HSE clock ready flag\nSet by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is cleared, \nHSERDY goes low after 6 HSE oscillator clock cycles.\n0: HSE oscillator not ready\n1: HSE oscillator ready\nBit 16 HSEON: HSE clock enable\nSet and cleared by software.\nCleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This \nbit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.\n0: HSE oscillator OFF\n1: HSE oscillator ON\nBits 15:8 HSICAL[7:0]: Internal high-speed clock calibration\nThese bits are initialized automatically at startup.\nBits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming\nThese bits provide an additional user-programmable trimming value that is added to the \nHSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature \nthat influence the frequency of the internal HSI RC.\nBit 2 Reserved, must be kept at reset value.\nBit 1 HSIRDY: Internal high-speed clock ready flag\nSet by hardware to indicate that the HSI oscillator is stable. After the HSION bit is cleared, \nHSIRDY goes low after 6 HSI clock cycles.\n0: HSI oscillator not ready\n1: HSI oscillator ready\nBit 0 HSION: Internal high-speed clock enable\nSet and cleared by software.\nSet by hardware to force the HSI oscillator ON when leaving the Stop or Standby mode or in \ncase of a failure of the HSE oscillator used directly or indirectly as the system clock. This bit \ncannot be cleared if the HSI is used directly or indirectly as the system clock.\n0: HSI oscillator OFF\n1: HSI oscillator ON\n\n\n<>\n\nRM0090 Rev 21\n165/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.2 \nRCC PLL configuration register (RCC_PLLCFGR)\nAddress offset: 0x04\nReset value: 0x2400 3010\nAccess: no wait state, word, half-word and byte access.\nThis register is used to configure the PLL clock outputs according to the formulas:\n•\nf(VCO clock) = f(PLL clock input) × (PLLN / PLLM)\n•\nf(PLL general clock output) = f(VCO clock) / PLLP\n•\nf(USB OTG FS, SDIO, RNG clock output) = f(VCO clock) / PLLQ\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPLLQ3\nPLLQ2\nPLLQ1\nPLLQ0\nReserv\ned\nPLLSR\nC\nReserved\nPLLP1\nPLLP0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserv\ned\nPLLN\nPLLM5\nPLLM4\nPLLM3\nPLLM2\nPLLM1\nPLLM0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBits 27:24 PLLQ: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator \nclocks\nSet and cleared by software to control the frequency of USB OTG FS clock, the random \nnumber generator clock and the SDIO clock. These bits should be written only if PLL is \ndisabled.\nCaution: The USB OTG FS requires a 48 MHz clock to work correctly. The SDIO and the \nrandom number generator need a frequency lower than or equal to 48 MHz to work \ncorrectly.\nUSB OTG FS clock frequency = VCO frequency / PLLQ with 2 ≤ PLLQ ≤ 15\n0000: PLLQ = 0, wrong configuration\n0001: PLLQ = 1, wrong configuration\n0010: PLLQ = 2\n0011: PLLQ = 3\n0100: PLLQ = 4\n...\n1111: PLLQ = 15\nBit 23 Reserved, must be kept at reset value.\nBit 22 PLLSRC: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source\nSet and cleared by software to select PLL and PLLI2S clock source. This bit can be written \nonly when PLL and PLLI2S are disabled.\n0: HSI clock selected as PLL and PLLI2S clock entry\n1: HSE oscillator clock selected as PLL and PLLI2S clock entry\nBits 21:18 Reserved, must be kept at reset value.\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n166/1757\nRM0090 Rev 21\nBits 17:16 PLLP: Main PLL (PLL) division factor for main system clock\nSet and cleared by software to control the frequency of the general PLL output clock. These \nbits can be written only if PLL is disabled.\nCaution: The software has to set these bits correctly not to exceed 180 MHz on this domain.\nPLL output clock frequency = VCO frequency / PLLP with PLLP = 2, 4, 6, or 8\n00: PLLP = 2\n01: PLLP = 4\n10: PLLP = 6\n11: PLLP = 8\nBits 14:6 PLLN: Main PLL (PLL) multiplication factor for VCO\nSet and cleared by software to control the multiplication factor of the VCO. These bits can \nbe written only when PLL is disabled. Only half-word and word accesses are allowed to \nwrite these bits.\nCaution: The software has to set these bits correctly to ensure that the VCO output \nfrequency is between 100 and 432 MHz. \nVCO output frequency = VCO input frequency × PLLN with 50 ≤ PLLN ≤ 432\n000000000: PLLN = 0, wrong configuration \n000000001: PLLN = 1, wrong configuration\n...\n000110010: PLLN = 50\n...\n001100011: PLLN = 99\n001100100: PLLN = 100\n... \n110110000: PLLN = 432\n110110001: PLLN = 433, wrong configuration\n... \n111111111: PLLN = 511, wrong configuration \nNote: Multiplication factors ranging from 50 and 99 are possible for VCO input frequency \nhigher than 1 MHz. However care must be taken that the minimum VCO output \nfrequency respects the value specified above. \nBits 5:0 PLLM: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock\nSet and cleared by software to divide the PLL and PLLI2S input clock before the VCO. \nThese bits can be written only when the PLL and PLLI2S are disabled.\nCaution: The software has to set these bits correctly to ensure that the VCO input frequency \nranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit \nPLL jitter. \nVCO input frequency = PLL input clock frequency / PLLM with 2 ≤ PLLM ≤ 63\n000000: PLLM = 0, wrong configuration\n000001: PLLM = 1, wrong configuration\n000010: PLLM = 2\n000011: PLLM = 3\n000100: PLLM = 4\n...\n111110: PLLM = 62\n111111: PLLM = 63\n\n\n<>\n\nRM0090 Rev 21\n167/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.3 \nRCC clock configuration register (RCC_CFGR)\nAddress offset: 0x08\nReset value: 0x0000 0000\nAccess: 0 ≤ wait state ≤ 2, word, half-word and byte access\n1 or 2 wait states inserted only if the access occurs during a clock source switch.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMCO2\nMCO2 PRE[2:0]\nMCO1 PRE[2:0]\nI2SSC\nR\nMCO1\nRTCPRE[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPPRE2[2:0]\nPPRE1[2:0]\nReserved\nHPRE[3:0]\nSWS1\nSWS0\nSW1\nSW0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nr\nr\nrw\nrw\nBits 31:30 MCO2[1:0]: Microcontroller clock output 2\nSet and cleared by software. Clock source selection may generate glitches on MCO2. It is \nhighly recommended to configure these bits only after reset before enabling the external \noscillators and the PLLs.\n00: System clock (SYSCLK) selected\n01: PLLI2S clock selected\n10: HSE oscillator clock selected\n11: PLL clock selected\nBits 27:29 MCO2PRE: MCO2 prescaler\nSet and cleared by software to configure the prescaler of the MCO2. Modification of this \nprescaler may generate glitches on MCO2. It is highly recommended to change this \nprescaler only after reset before enabling the external oscillators and the PLLs.\n0xx: no division\n100: division by 2\n101: division by 3\n110: division by 4\n111: division by 5\nBits 24:26 MCO1PRE: MCO1 prescaler\nSet and cleared by software to configure the prescaler of the MCO1. Modification of this \nprescaler may generate glitches on MCO1. It is highly recommended to change this \nprescaler only after reset before enabling the external oscillators and the PLL.\n0xx: no division\n100: division by 2\n101: division by 3\n110: division by 4\n111: division by 5\nBit 23 I2SSRC: I2S clock selection\nSet and cleared by software. This bit allows to select the I2S clock source between the \nPLLI2S clock and the external clock. It is highly recommended to change this bit only after \nreset and before enabling the I2S module.\n0: PLLI2S clock used as I2S clock source\n1: External clock mapped on the I2S_CKIN pin used as I2S clock source\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n168/1757\nRM0090 Rev 21\nBits 22:21 MCO1: Microcontroller clock output 1\nSet and cleared by software. Clock source selection may generate glitches on MCO1. It is \nhighly recommended to configure these bits only after reset before enabling the external \noscillators and PLL.\n00: HSI clock selected\n01: LSE oscillator selected\n10: HSE oscillator clock selected\n11: PLL clock selected\nBits 20:16 RTCPRE: HSE division factor for RTC clock\nSet and cleared by software to divide the HSE clock input clock to generate a 1 MHz clock \nfor RTC.\nCaution: The software has to set these bits correctly to ensure that the clock supplied to the \nRTC is 1 MHz. These bits must be configured if needed before selecting the RTC \nclock source.\n00000: no clock\n00001: no clock\n00010: HSE/2\n00011: HSE/3\n00100: HSE/4\n...\n11110: HSE/30\n11111: HSE/31\nBits 15:13 PPRE2: APB high-speed prescaler (APB2)\nSet and cleared by software to control APB high-speed clock division factor.\nCaution: The software has to set these bits correctly not to exceed 90 MHz on this domain. \nThe clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after \nPPRE2 write.\n0xx: AHB clock not divided\n100: AHB clock divided by 2\n101: AHB clock divided by 4\n110: AHB clock divided by 8\n111: AHB clock divided by 16\nBits 12:10 PPRE1: APB Low speed prescaler (APB1)\nSet and cleared by software to control APB low-speed clock division factor.\nCaution: The software has to set these bits correctly not to exceed 45 MHz on this domain. \nThe clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after \nPPRE1 write.\n0xx: AHB clock not divided\n100: AHB clock divided by 2\n101: AHB clock divided by 4\n110: AHB clock divided by 8\n111: AHB clock divided by 16\nBits 9:8 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n169/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.4 \nRCC clock interrupt register (RCC_CIR)\nAddress offset: 0x0C\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n \nBits 7:4 HPRE: AHB prescaler\nSet and cleared by software to control AHB clock division factor.\nCaution: The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after \nHPRE write.\nCaution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.\n0xxx: system clock not divided\n1000: system clock divided by 2\n1001: system clock divided by 4\n1010: system clock divided by 8\n1011: system clock divided by 16\n1100: system clock divided by 64\n1101: system clock divided by 128\n1110: system clock divided by 256\n1111: system clock divided by 512\nBits 3:2 SWS: System clock switch status\nSet and cleared by hardware to indicate which clock source is used as the system clock.\n00: HSI oscillator used as the system clock\n01: HSE oscillator used as the system clock\n10: PLL used as the system clock\n11: not applicable\nBits 1:0 SW: System clock switch\nSet and cleared by software to select the system clock source.\nSet by hardware to force the HSI selection when leaving the Stop or Standby mode or in \ncase of failure of the HSE oscillator used directly or indirectly as the system clock.\n00: HSI oscillator selected as system clock\n01: HSE oscillator selected as system clock\n10: PLL selected as system clock\n11: not allowed\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nCSSC\nPLLSAI\nRDYC\nPLLI2S \nRDYC\nPLL \nRDYC\nHSE \nRDYC\nHSI \nRDYC\nLSE \nRDYC\nLSI \nRDYC\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserv\ned\nPLLSAI\nRDYIE\nPLLI2S \nRDYIE\nPLL \nRDYIE\nHSE \nRDYIE\nHSI \nRDYIE\nLSE \nRDYIE\nLSI \nRDYIE\nCSSF\nPLLSAI\nRDYF\nPLLI2S\nRDYF\nPLL \nRDYF\nHSE \nRDYF\nHSI \nRDYF\nLSE \nRDYF\nLSI \nRDYF\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nr\nr\nr\nr\nr\nr\nr\nr\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n170/1757\nRM0090 Rev 21\n \nBits 31:24 Reserved, must be kept at reset value.\nBit 23 CSSC: Clock security system interrupt clear\nThis bit is set by software to clear the CSSF flag.\n0: No effect\n1: Clear CSSF flag\nBit 22 PLLSAIRDYC: PLLSAI Ready Interrupt Clear\nThis bit is set by software to clear PLLSAIRDYF flag. It is reset by hardware when the \nPLLSAIRDYF is cleared.\n0: PLLSAIRDYF not cleared\n1: PLLSAIRDYF cleared\nBit 21 PLLI2SRDYC: PLLI2S ready interrupt clear\nThis bit is set by software to clear the PLLI2SRDYF flag.\n0: No effect\n1: PLLI2SRDYF cleared\nBit 20 PLLRDYC: Main PLL(PLL) ready interrupt clear\nThis bit is set by software to clear the PLLRDYF flag.\n0: No effect\n1: PLLRDYF cleared\nBit 19 HSERDYC: HSE ready interrupt clear\nThis bit is set by software to clear the HSERDYF flag.\n0: No effect\n1: HSERDYF cleared\nBit 18 HSIRDYC: HSI ready interrupt clear\nThis bit is set software to clear the HSIRDYF flag.\n0: No effect\n1: HSIRDYF cleared\nBit 17 LSERDYC: LSE ready interrupt clear\nThis bit is set by software to clear the LSERDYF flag.\n0: No effect\n1: LSERDYF cleared\nBit 16 LSIRDYC: LSI ready interrupt clear\nThis bit is set by software to clear the LSIRDYF flag.\n0: No effect\n1: LSIRDYF cleared\nBit 15 Reserved, must be kept at reset value.\nBit 14 PLLSAIRDYIE: PLLSAI Ready Interrupt Enable\nThis bit is set and reset by software to enable/disable interrupt caused by PLLSAI lock.\n0: PLLSAI lock interrupt disabled\n1: PLLSAI lock interrupt enabled\nBit 13 PLLI2SRDYIE: PLLI2S ready interrupt enable\nThis bit is set and cleared by software to enable/disable interrupt caused by PLLI2S lock.\n0: PLLI2S lock interrupt disabled\n1: PLLI2S lock interrupt enabled\n\n\n<>\n\nRM0090 Rev 21\n171/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable\nThis bit is set and cleared by software to enable/disable interrupt caused by PLL lock.\n0: PLL lock interrupt disabled\n1: PLL lock interrupt enabled\nBit 11 HSERDYIE: HSE ready interrupt enable\nThis bit is set and cleared by software to enable/disable interrupt caused by the HSE \noscillator stabilization.\n0: HSE ready interrupt disabled\n1: HSE ready interrupt enabled\nBit 10 HSIRDYIE: HSI ready interrupt enable\nThis bit is set and cleared by software to enable/disable interrupt caused by the HSI \noscillator stabilization.\n0: HSI ready interrupt disabled\n1: HSI ready interrupt enabled\nBit 9 LSERDYIE: LSE ready interrupt enable\nThis bit is set and cleared by software to enable/disable interrupt caused by the LSE \noscillator stabilization.\n0: LSE ready interrupt disabled\n1: LSE ready interrupt enabled\nBit 8 LSIRDYIE: LSI ready interrupt enable\nThis bit is set and cleared by software to enable/disable interrupt caused by LSI oscillator \nstabilization.\n0: LSI ready interrupt disabled\n1: LSI ready interrupt enabled\nBit 7 CSSF: Clock security system interrupt flag\nThis bit is set by hardware when a failure is detected in the HSE oscillator.\nIt is cleared by software by setting the CSSC bit.\n0: No clock security interrupt caused by HSE clock failure\n1: Clock security interrupt caused by HSE clock failure\nBit 6 PLLSAIRDYF: PLLSAI Ready Interrupt flag\nThis bit is set by hardware when the PLLSAI is locked and PLLSAIRDYIE is set.\nIt is cleared by software by setting the PLLSAIRDYC bit.\n0: No clock ready interrupt caused by PLLSAI lock\n1: Clock ready interrupt caused by PLLSAI lock\nBit 5 PLLI2SRDYF: PLLI2S ready interrupt flag\nThis bit is set by hardware when the PLLI2S is locked and PLLI2SRDYIE is set.\nIt is cleared by software by setting the PLLRI2SDYC bit.\n0: No clock ready interrupt caused by PLLI2S lock\n1: Clock ready interrupt caused by PLLI2S lock\nBit 4 PLLRDYF: Main PLL (PLL) ready interrupt flag\nThis bit is set by hardware when PLL is locked and PLLRDYIE is set.\nIt is cleared by software setting the PLLRDYC bit.\n0: No clock ready interrupt caused by PLL lock\n1: Clock ready interrupt caused by PLL lock\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n172/1757\nRM0090 Rev 21\n6.3.5 \nRCC AHB1 peripheral reset register (RCC_AHB1RSTR)\nAddress offset: 0x10\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \nBit 3 HSERDYF: HSE ready interrupt flag\nThis bit is set by hardware when External High Speed clock becomes stable and \nHSERDYIE is set.\nIt is cleared by software by setting the HSERDYC bit.\n0: No clock ready interrupt caused by the HSE oscillator\n1: Clock ready interrupt caused by the HSE oscillator\nBit 2 HSIRDYF: HSI ready interrupt flag\nThis bit is set by hardware when the Internal High Speed clock becomes stable and \nHSIRDYIE is set.\nIt is cleared by software by setting the HSIRDYC bit.\n0: No clock ready interrupt caused by the HSI oscillator\n1: Clock ready interrupt caused by the HSI oscillator\nBit 1 LSERDYF: LSE ready interrupt flag\nThis bit is set by hardware when the External Low Speed clock becomes stable and \nLSERDYIE is set.\nIt is cleared by software by setting the LSERDYC bit.\n0: No clock ready interrupt caused by the LSE oscillator\n1: Clock ready interrupt caused by the LSE oscillator\nBit 0 LSIRDYF: LSI ready interrupt flag\nThis bit is set by hardware when the internal low speed clock becomes stable and \nLSIRDYIE is set.\nIt is cleared by software by setting the LSIRDYC bit.\n0: No clock ready interrupt caused by the LSI oscillator\n1: Clock ready interrupt caused by the LSI oscillator\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nOTGH\nS\nRST\nReserved\nETHMAC\nRST\nRes.\nDMA2D\nRST\nDMA2\nRST\nDMA1\nRST\nReserved\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCRCR\nST\nRes.\nGPIOK\nRST\nGPIOJ\nRST\nGPIOI\nRST\nGPIOH\nRST\nGPIOGG\nRST\nGPIOF\nRST\nGPIOE\nRST\nGPIOD\nRST\nGPIOC\nRST\nGPIOB\nRST\nGPIOA\nRST\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBit 29 OTGHSRST: USB OTG HS module reset\nThis bit is set and cleared by software.\n0: does not reset the USB OTG HS module\n1: resets the USB OTG HS module\nBits 28:26 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n173/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 25 ETHMACRST: Ethernet MAC reset\nThis bit is set and cleared by software.\n0: does not reset Ethernet MAC\n1: resets Ethernet MAC\nBit 24 Reserved, must be kept at reset value.\nBit 23 DMA2DRST: DMA2D reset\nThis bit is set and reset by software.\n0: does not reset DMA2D\n1: resets DMA2D\nBit 22 DMA2RST: DMA2 reset\nThis bit is set and cleared by software.\n0: does not reset DMA2\n1: resets DMA2\nBit 21 DMA1RST: DMA2 reset\nThis bit is set and cleared by software.\n0: does not reset DMA2\n1: resets DMA2\nBits 20:13 Reserved, must be kept at reset value.\nBit 12 CRCRST: CRC reset\nThis bit is set and cleared by software.\n0: does not reset CRC\n1: resets CRC\nBit 11 Reserved, must be kept at reset value.\nBit 10 GPIOKRST: IO port K reset\nThis bit is set and cleared by software.\n0: does not reset IO port K\n1: resets IO port K\nBit 9 GPIOJRST: IO port J reset\nThis bit is set and cleared by software.\n0: does not reset IO port J\n1: resets IO port J\nBit 8 GPIOIRST: IO port I reset\nThis bit is set and cleared by software.\n0: does not reset IO port I\n1: resets IO port I\nBit 7 GPIOHRST: IO port H reset\nThis bit is set and cleared by software.\n0: does not reset IO port H\n1: resets IO port H\nBit 6 GPIOGRST: IO port G reset\nThis bit is set and cleared by software.\n0: does not reset IO port G\n1: resets IO port G\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n174/1757\nRM0090 Rev 21\nBit 5 GPIOFRST: IO port F reset\nThis bit is set and cleared by software.\n0: does not reset IO port F\n1: resets IO port F\nBit 4 GPIOERST: IO port E reset\nThis bit is set and cleared by software.\n0: does not reset IO port E\n1: resets IO port E\nBit 3 GPIODRST: IO port D reset\nThis bit is set and cleared by software.\n0: does not reset IO port D\n1: resets IO port D\nBit 2 GPIOCRST: IO port C reset\nThis bit is set and cleared by software.\n0: does not reset IO port C\n1: resets IO port C\nBit 1 GPIOBRST: IO port B reset\nThis bit is set and cleared by software.\n0: does not reset IO port B\n1:resets IO port B\nBit 0 GPIOARST: IO port A reset\nThis bit is set and cleared by software.\n0: does not reset IO port A\n1: resets IO port A\n\n\n<>\n\nRM0090 Rev 21\n175/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.6 \nRCC AHB2 peripheral reset register (RCC_AHB2RSTR)\nAddress offset: 0x14\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOTGFS\nRST\nRNG\nRST\nHASH\nRST\nCRYP\nRST\nReserved\nDCMI\nRST\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBit 7 OTGFSRST: USB OTG FS module reset\nSet and cleared by software.\n0: does not reset the USB OTG FS module\n1: resets the USB OTG FS module\nBit 6 RNGRST: Random number generator module reset\nSet and cleared by software.\n0: does not reset the random number generator module\n1: resets the random number generator module\nBit 5 HASHRST: Hash module reset\nSet and cleared by software.\n0: does not reset the HASH module\n1: resets the HASH module\nBit 4 CRYPRST: Cryptographic module reset\nSet and cleared by software.\n0: does not reset the cryptographic module\n1: resets the cryptographic module\nBits 3:1 Reserved, must be kept at reset value.\nBit 0 DCMIRST: Camera interface reset\nSet and cleared by software.\n0: does not reset the Camera interface\n1: resets the Camera interface \n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n176/1757\nRM0090 Rev 21\n6.3.7 \nRCC AHB3 peripheral reset register (RCC_AHB3RSTR)\nAddress offset: 0x18\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n6.3.8 \nRCC APB1 peripheral reset register (RCC_APB1RSTR)\nAddress offset: 0x20\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFMCRST\nrw\nBits 31:1 Reserved, must be kept at reset value.\nBit 0 FMCRST: Flexible memory controller module reset\nSet and cleared by software.\n0: does not reset the FMC module\n1: resets the FMC module\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nUART8R\nST\nUART7R\nST\nDACRST\nPWR\nRST\nReser-\nved\nCAN2\nRST\nCAN1\nRST\nReser-\nved\nI2C3\nRST\nI2C2\nRST\nI2C1\nRST\nUART5 \nRST\nUART4\nRST\nUART3\nRST\nUART2\nRST\nReser-\nved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSPI3\nRST\nSPI2\nRST\nReserved\nWWDG\nRST\nReserved\nTIM14\nRST\nTIM13\nRST\nTIM12\nRST\nTIM7\nRST\nTIM6\nRST\nTIM5\nRST\nTIM4\nRST\nTIM3\nRST\nTIM2\nRST\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n177/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 31 UART8RST: UART8 reset\nSet and cleared by software.\n0: does not reset UART8\n1: resets UART8\nBit 30 UART7RST: UART7 reset\nSet and cleared by software.\n0: does not reset UART7\n1: resets UART7\nBit 29 DACRST: DAC reset\nSet and cleared by software.\n0: does not reset the DAC interface\n1: resets the DAC interface\nBit 28 PWRRST: Power interface reset\nSet and cleared by software.\n0: does not reset the power interface\n1: resets the power interface\nBit 27 Reserved, must be kept at reset value.\nBit 26 CAN2RST: CAN2 reset\nSet and cleared by software.\n0: does not reset CAN2\n1: resets CAN2\nBit 25 CAN1RST: CAN1 reset\nSet and cleared by software.\n0: does not reset CAN1\n1: resets CAN1\nBit 24 Reserved, must be kept at reset value.\nBit 23 I2C3RST: I2C3 reset\nSet and cleared by software.\n0: does not reset I2C3\n1: resets I2C3\nBit 22 I2C2RST: I2C2 reset\nSet and cleared by software.\n0: does not reset I2C2\n1: resets I2C2\nBit 21 I2C1RST: I2C1 reset\nSet and cleared by software.\n0: does not reset I2C1\n1: resets I2C1\nBit 20 UART5RST: UART5 reset\nSet and cleared by software.\n0: does not reset UART5\n1: resets UART5\nBit 19 UART4RST: USART4 reset\nSet and cleared by software.\n0: does not reset UART4\n1: resets UART4\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n178/1757\nRM0090 Rev 21\nBit 18 USART3RST: USART3 reset\nSet and cleared by software.\n0: does not reset USART3\n1: resets USART3\nBit 17 USART2RST: USART2 reset\nSet and cleared by software.\n0: does not reset USART2\n1: resets USART2\nBit 16 Reserved, must be kept at reset value.\nBit 15 SPI3RST: SPI3 reset\nSet and cleared by software.\n0: does not reset SPI3\n1: resets SPI3\nBit 14 SPI2RST: SPI2 reset\nSet and cleared by software.\n0: does not reset SPI2\n1: resets SPI2\nBits 13:12 Reserved, must be kept at reset value.\nBit 11 WWDGRST: Window watchdog reset\nSet and cleared by software.\n0: does not reset the window watchdog\n1: resets the window watchdog\nBits 10:9 Reserved, must be kept at reset value.\nBit 8 TIM14RST: TIM14 reset\nSet and cleared by software.\n0: does not reset TIM14\n1: resets TIM14\nBit 7 TIM13RST: TIM13 reset\nSet and cleared by software.\n0: does not reset TIM13\n1: resets TIM13\nBit 6 TIM12RST: TIM12 reset\nSet and cleared by software.\n0: does not reset TIM12\n1: resets TIM12\nBit 5 TIM7RST: TIM7 reset\nSet and cleared by software.\n0: does not reset TIM7\n1: resets TIM7\nBit 4 TIM6RST: TIM6 reset\nSet and cleared by software.\n0: does not reset TIM6\n1: resets TIM6\n\n\n<>\n\nRM0090 Rev 21\n179/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 3 TIM5RST: TIM5 reset\nSet and cleared by software.\n0: does not reset TIM5\n1: resets TIM5\nBit 2 TIM4RST: TIM4 reset\nSet and cleared by software.\n0: does not reset TIM4\n1: resets TIM4\nBit 1 TIM3RST: TIM3 reset\nSet and cleared by software.\n0: does not reset TIM3\n1: resets TIM3\nBit 0 TIM2RST: TIM2 reset\nSet and cleared by software.\n0: does not reset TIM2\n1: resets TIM2\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n180/1757\nRM0090 Rev 21\n6.3.9 \nRCC APB2 peripheral reset register (RCC_APB2RSTR)\nAddress offset: 0x24\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nLTD\nCRST\nReserved\nSAI1\nRST\nSPI6\nRST\nSPI5\nRST\nRes.\nTIM11\nRST\nTIM10\nRST\nTIM9\nRST\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReser-\nved\nSYSCF\nG RST\nSPI4\nRST\nSPI1\nRST\nSDIO\nRST\nReserved\nADC\nRST\nReserved\nUSART\n6\nRST\nUSART\n1\nRST\nReserved\nTIM8\nRST\nTIM1\nRST\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:27 Reserved, must be kept at reset value.\nBit 26 LTDCRST: LTDC reset\nThis bit is set and reset by software.\n0: does not reset LCD-TFT\n1: resets LCD-TFT\nBits 27:23 Reserved, must be kept at reset value.\nBit 22 SAI1RST: SAI1 reset\nThis bit is set and reset by software.\n0: does not reset SAI1\n1: resets SAI1\nBit 21 SPI6RST: SPI6 reset\nThis bit is set and cleared by software.\n0: does not reset SPI6\n1: resets SPI6\nBit 20 SPI5RST: SPI5 reset\nThis bit is set and cleared by software.\n0: does not reset SPI5\n1: resets SPI5\nBit 19 Reserved, must be kept at reset value.\nBit 18 TIM11RST: TIM11 reset\nThis bit is set and cleared by software.\n0: does not reset TIM11\n1: resets TIM14\nBit 17 TIM10RST: TIM10 reset\nThis bit is set and cleared by software.\n0: does not reset TIM10\n1: resets TIM10\nBit 16 TIM9RST: TIM9 reset\nThis bit is set and cleared by software.\n0: does not reset TIM9\n1: resets TIM9\n\n\n<>\n\nRM0090 Rev 21\n181/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 15 Reserved, must be kept at reset value.\nBit 14 SYSCFGRST: System configuration controller reset\nThis bit is set and cleared by software.\n0: does not reset the System configuration controller\n1: resets the System configuration controller\nBit 13 SPI4RST: SPI4 reset\nThis bit is set and cleared by software.\n0: does not reset SPI4\n1: resets SPI4\nBit 12 SPI1RST: SPI1 reset\nThis bit is set and cleared by software.\n0: does not reset SPI1\n1: resets SPI1\nBit 11 SDIORST: SDIO reset\nThis bit is set and cleared by software.\n0: does not reset the SDIO module\n1: resets the SDIO module\nBits 10:9 Reserved, must be kept at reset value.\nBit 8 ADCRST: ADC interface reset (common to all ADCs)\nThis bit is set and cleared by software.\n0: does not reset the ADC interface\n1: resets the ADC interface\nBits 7:6 Reserved, must be kept at reset value.\nBit 5 USART6RST: USART6 reset\nThis bit is set and cleared by software.\n0: does not reset USART6\n1: resets USART6\nBit 4\nUSART1RST: USART1 reset\nThis bit is set and cleared by software.\n0: does not reset USART1\n1: resets USART1\nBits 3:2 Reserved, must be kept at reset value.\nBit 1 TIM8RST: TIM8 reset\nThis bit is set and cleared by software.\n0: does not reset TIM8\n1: resets TIM8\nBit 0 TIM1RST: TIM1 reset\nThis bit is set and cleared by software.\n0: does not reset TIM1\n1: resets TIM1\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n182/1757\nRM0090 Rev 21\n6.3.10 \nRCC AHB1 peripheral clock register (RCC_AHB1ENR)\nAddress offset: 0x30\nReset value: 0x0010 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReser-\nved\nOTGH\nS \nULPIE\nN\nOTGH\nSEN\nETHM\nACPTP\nEN\nETHM\nACRXE\nN\nETHM\nACTXE\nN\nETHMA\nCEN\nRes.\nDMA2D\nEN\nDMA2E\nN\nDMA1E\nN\nCCMDAT\nARAMEN\nRes.\nBKPSR\nAMEN\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCRCE\nN\nRes.\nGPIOK\nEN\nGPIOJ\nEN\nGPIOIE\nN\nGPIOH\nEN\nGPIOG\nEN\nGPIOFE\nN\nGPIOEEN\nGPIOD\nEN\nGPIOC\nEN\nGPIO\nBEN\nGPIO\nAEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBit 30 OTGHSULPIEN: USB OTG HSULPI clock enable\nThis bit is set and cleared by software. It must be cleared when the OTG_HS is used in FS \nmode.\n0: USB OTG HS ULPI clock disabled\n1: USB OTG HS ULPI clock enabled\nBit 29 OTGHSEN: USB OTG HS clock enable\nThis bit is set and cleared by software.\n0: USB OTG HS clock disabled\n1: USB OTG HS clock enabled\nBit 28 ETHMACPTPEN: Ethernet PTP clock enable\nThis bit is set and cleared by software.\n0: Ethernet PTP clock disabled\n1: Ethernet PTP clock enabled\nBit 27 ETHMACRXEN: Ethernet Reception clock enable\nThis bit is set and cleared by software.\n0: Ethernet Reception clock disabled\n1: Ethernet Reception clock enabled\nBit 26 ETHMACTXEN: Ethernet Transmission clock enable\nThis bit is set and cleared by software.\n0: Ethernet Transmission clock disabled\n1: Ethernet Transmission clock enabled\nBit 25 ETHMACEN: Ethernet MAC clock enable\nThis bit is set and cleared by software.\n0: Ethernet MAC clock disabled\n1: Ethernet MAC clock enabled\nBit 24 Reserved, must be kept at reset value.\nBit 23 DMA2DEN: DMA2D clock enable\nThis bit is set and cleared by software.\n0: DMA2D clock disabled\n1: DMA2D clock enabled\n\n\n<>\n\nRM0090 Rev 21\n183/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 22 DMA2EN: DMA2 clock enable\nThis bit is set and cleared by software.\n0: DMA2 clock disabled\n1: DMA2 clock enabled\nBit 21 DMA1EN: DMA1 clock enable\nThis bit is set and cleared by software.\n0: DMA1 clock disabled\n1: DMA1 clock enabled\nBit 20 CCMDATARAMEN: CCM data RAM clock enable\nThis bit is set and cleared by software. \n0: CCM data RAM clock disabled\n1: CCM data RAM clock enabled\nBit 19 Reserved, must be kept at reset value.\nBit 18 BKPSRAMEN: Backup SRAM interface clock enable\nThis bit is set and cleared by software.\n0: Backup SRAM interface clock disabled\n1: Backup SRAM interface clock enabled\nBits 17:13 Reserved, must be kept at reset value.\nBit 12 CRCEN: CRC clock enable\nThis bit is set and cleared by software.\n0: CRC clock disabled\n1: CRC clock enabled\nBit 11 Reserved, must be kept at reset value.\nBit 10 GPIOKEN: IO port K clock enable\nThis bit is set and cleared by software.\n0: IO port K clock disabled\n1: IO port K clock enabled\nBit 9 GPIOJEN: IO port J clock enable\nThis bit is set and cleared by software.\n0: IO port J clock disabled\n1: IO port J clock enabled\nBit 8 GPIOIEN: IO port I clock enable\nThis bit is set and cleared by software.\n0: IO port I clock disabled\n1: IO port I clock enabled\nBit 7 GPIOHEN: IO port H clock enable\nThis bit is set and cleared by software.\n0: IO port H clock disabled\n1: IO port H clock enabled\nBit 6 GPIOGEN: IO port G clock enable\nThis bit is set and cleared by software.\n0: IO port G clock disabled\n1: IO port G clock enabled\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n184/1757\nRM0090 Rev 21\n6.3.11 \nRCC AHB2 peripheral clock enable register (RCC_AHB2ENR)\nAddress offset: 0x34\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \nBit 5 GPIOFEN: IO port F clock enable\nThis bit is set and cleared by software.\n0: IO port F clock disabled\n1: IO port F clock enabled\nBit 4 GPIOEEN: IO port E clock enable\nThis bit is set and cleared by software.\n0: IO port E clock disabled\n1: IO port E clock enabled\nBit 3 GPIODEN: IO port D clock enable\nThis bit is set and cleared by software.\n0: IO port D clock disabled\n1: IO port D clock enabled\nBit 2 GPIOCEN: IO port C clock enable\nThis bit is set and cleared by software.\n0: IO port C clock disabled\n1: IO port C clock enabled\nBit 1 GPIOBEN: IO port B clock enable\nThis bit is set and cleared by software.\n0: IO port B clock disabled\n1: IO port B clock enabled\nBit 0 GPIOAEN: IO port A clock enable\nThis bit is set and cleared by software.\n0: IO port A clock disabled\n1: IO port A clock enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOTGFS\nEN\nRNG\nEN\nHASH\nEN\nCRYP\nEN\nReserved\nDCMI\nEN\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBit 7 OTGFSEN: USB OTG FS clock enable\nThis bit is set and cleared by software.\n0: USB OTG FS clock disabled\n1: USB OTG FS clock enabled\nBit 6 RNGEN: Random number generator clock enable\nThis bit is set and cleared by software.\n0: Random number generator clock disabled\n1: Random number generator clock enabled\n\n\n<>\n\nRM0090 Rev 21\n185/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.12 \nRCC AHB3 peripheral clock enable register (RCC_AHB3ENR)\nAddress offset: 0x38\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n6.3.13 \nRCC APB1 peripheral clock enable register (RCC_APB1ENR)\nAddress offset: 0x40\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \nBit 5 HASHEN: Hash modules clock enable\nThis bit is set and cleared by software.\n0: Hash modules clock disabled\n1: Hash modules clock enabled\nBit 4 CRYPEN: Cryptographic modules clock enable\nThis bit is set and cleared by software.\n0: cryptographic module clock disabled\n1: cryptographic module clock enabled\nBits 3:1 Reserved, must be kept at reset value.\nBit 0 DCMIEN: Camera interface enable\nThis bit is set and cleared by software.\n0: Camera interface clock disabled\n1: Camera interface clock enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFMCEN\nrw\nBits 31:1 Reserved, must be kept at reset value.\nBit 0 FMCEN: Flexible memory controller module clock enable\nThis bit is set and cleared by software.\n0: FMC module clock disabled\n1: FMC module clock enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nUART8\nEN\nUART7\nEN\nDAC\nEN\nPWR\nEN\nReser-\nved\nCAN2\nEN\nCAN1\nEN\nReser-\nved\nI2C3\nEN\nI2C2\nEN\nI2C1\nEN\nUART5\nEN\nUART4\nEN\nUSART\n3\nEN\nUSART\n2\nEN\nReser-\nved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSPI3\nEN\nSPI2\nEN\nReserved\nWWDG\nEN\nReserved\nTIM14\nEN\nTIM13\nEN\nTIM12\nEN\nTIM7\nEN\nTIM6 \nEN\nTIM5\nEN\nTIM4\nEN\nTIM3\nEN\nTIM2\nEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n186/1757\nRM0090 Rev 21\n \nBit 31 UART8EN: UART8 clock enable\nThis bit is set and cleared by software.\n0: UART8 clock disabled\n1: UART8 clock enabled\nBit 30 UART7EN: UART7 clock enable\nThis bit is set and cleared by software.\n0: UART7 clock disabled\n1: UART7 clock enabled\nBit 29 DACEN: DAC interface clock enable\nThis bit is set and cleared by software.\n0: DAC interface clock disabled\n1: DAC interface clock enable\nBit 28 PWREN: Power interface clock enable\nThis bit is set and cleared by software.\n0: Power interface clock disabled\n1: Power interface clock enable\nBit 27 Reserved, must be kept at reset value.\nBit 26 CAN2EN: CAN 2 clock enable\nThis bit is set and cleared by software.\n0: CAN 2 clock disabled\n1: CAN 2 clock enabled\nBit 25 CAN1EN: CAN 1 clock enable\nThis bit is set and cleared by software.\n0: CAN 1 clock disabled\n1: CAN 1 clock enabled\nBit 24 Reserved, must be kept at reset value.\nBit 23 I2C3EN: I2C3 clock enable\nThis bit is set and cleared by software.\n0: I2C3 clock disabled\n1: I2C3 clock enabled\nBit 22 I2C2EN: I2C2 clock enable\nThis bit is set and cleared by software.\n0: I2C2 clock disabled\n1: I2C2 clock enabled\nBit 21 I2C1EN: I2C1 clock enable\nThis bit is set and cleared by software.\n0: I2C1 clock disabled\n1: I2C1 clock enabled\nBit 20 UART5EN: UART5 clock enable\nThis bit is set and cleared by software.\n0: UART5 clock disabled\n1: UART5 clock enabled\nBit 19 UART4EN: UART4 clock enable\nThis bit is set and cleared by software.\n0: UART4 clock disabled\n1: UART4 clock enabled\n\n\n<>\n\nRM0090 Rev 21\n187/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 18 USART3EN: USART3 clock enable\nThis bit is set and cleared by software.\n0: USART3 clock disabled\n1: USART3 clock enabled\nBit 17 USART2EN: USART2 clock enable\nThis bit is set and cleared by software.\n0: USART2 clock disabled\n1: USART2 clock enabled\nBit 16 Reserved, must be kept at reset value.\nBit 15 SPI3EN: SPI3 clock enable\nThis bit is set and cleared by software.\n0: SPI3 clock disabled\n1: SPI3 clock enabled\nBit 14 SPI2EN: SPI2 clock enable\nThis bit is set and cleared by software.\n0: SPI2 clock disabled\n1: SPI2 clock enabled\nBits 13:12 Reserved, must be kept at reset value.\nBit 11 WWDGEN: Window watchdog clock enable\nThis bit is set and cleared by software.\n0: Window watchdog clock disabled\n1: Window watchdog clock enabled\nBit 10:9 Reserved, must be kept at reset value.\nBit 8 TIM14EN: TIM14 clock enable\nThis bit is set and cleared by software.\n0: TIM14 clock disabled\n1: TIM14 clock enabled\nBit 7 TIM13EN: TIM13 clock enable\nThis bit is set and cleared by software.\n0: TIM13 clock disabled\n1: TIM13 clock enabled\nBit 6 TIM12EN: TIM12 clock enable\nThis bit is set and cleared by software.\n0: TIM12 clock disabled\n1: TIM12 clock enabled\nBit 5 TIM7EN: TIM7 clock enable\nThis bit is set and cleared by software.\n0: TIM7 clock disabled\n1: TIM7 clock enabled\nBit 4 TIM6EN: TIM6 clock enable\nThis bit is set and cleared by software.\n0: TIM6 clock disabled\n1: TIM6 clock enabled\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n188/1757\nRM0090 Rev 21\nBit 3 TIM5EN: TIM5 clock enable\nThis bit is set and cleared by software.\n0: TIM5 clock disabled\n1: TIM5 clock enabled\nBit 2 TIM4EN: TIM4 clock enable\nThis bit is set and cleared by software.\n0: TIM4 clock disabled\n1: TIM4 clock enabled\nBit 1 TIM3EN: TIM3 clock enable\nThis bit is set and cleared by software.\n0: TIM3 clock disabled\n1: TIM3 clock enabled\nBit 0 TIM2EN: TIM2 clock enable\nThis bit is set and cleared by software.\n0: TIM2 clock disabled\n1: TIM2 clock enabled\n\n\n<>\n\nRM0090 Rev 21\n189/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.14 \nRCC APB2 peripheral clock enable register (RCC_APB2ENR)\nAddress offset: 0x44\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nLTDC\nEN\nReserved\nSAI1EN SPI6EN SPI5EN\nRes.\nTIM11\nEN\nTIM10\nEN\nTIM9\nEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReser-\nved\nSYSCF\nG EN\nSPI4E\nN\nSPI1\nEN\nSDIO\nEN\nADC3\nEN\nADC2\nEN\nADC1\nEN\nReserved\nUSART\n6\nEN\nUSART\n1\nEN\nReserved\nTIM8\nEN\nTIM1\nEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:27 Reserved, must be kept at reset value.\nBit 26 LTDCEN: LTDC clock enable\nThis bit is set and cleared by software.\n0: LTDC clock disabled\n1: LTDC clock enabled\nBits 27: 23 Reserved, must be kept at reset value.\nBit 22 SAI1EN: SAI1 clock enable\nThis bit is set and cleared by software.\n0: SAI1 clock disabled\n1: SAI1 clock enabled\nBit 21 SPI6EN: SPI6 clock enable\nThis bit is set and cleared by software.\n0: SPI6 clock disabled\n1: SPI6 clock enabled\nBit 20 SPI5EN: SPI5 clock enable\nThis bit is set and cleared by software.\n0: SPI5 clock disabled\n1: SPI5 clock enabled\nBit 18 TIM11EN: TIM11 clock enable\nThis bit is set and cleared by software.\n0: TIM11 clock disabled\n1: TIM11 clock enabled\nBit 17 TIM10EN: TIM10 clock enable\nThis bit is set and cleared by software.\n0: TIM10 clock disabled\n1: TIM10 clock enabled\nBit 16 TIM9EN: TIM9 clock enable\nThis bit is set and cleared by software.\n0: TIM9 clock disabled\n1: TIM9 clock enabled\nBit 15 Reserved, must be kept at reset value.\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n190/1757\nRM0090 Rev 21\nBit 14 SYSCFGEN: System configuration controller clock enable\nThis bit is set and cleared by software.\n0: System configuration controller clock disabled\n1: System configuration controller clock enabled\nBit 13 SPI4EN: SPI4 clock enable\nThis bit is set and cleared by software.\n0: SPI4 clock disabled\n1: SPI4 clock enabled\nBit 12 SPI1EN: SPI1 clock enable\nThis bit is set and cleared by software.\n0: SPI1 clock disabled\n1: SPI1 clock enabled\nBit 11 SDIOEN: SDIO clock enable\nThis bit is set and cleared by software.\n0: SDIO module clock disabled\n1: SDIO module clock enabled\nBit 10 ADC3EN: ADC3 clock enable\nThis bit is set and cleared by software.\n0: ADC3 clock disabled\n1: ADC3 clock enabled\nBit 9\nADC2EN: ADC2 clock enable\nThis bit is set and cleared by software.\n0: ADC2 clock disabled\n1: ADC2 clock enabled\nBit 8\nADC1EN: ADC1 clock enable\nThis bit is set and cleared by software.\n0: ADC1 clock disabled\n1: ADC1 clock enabled\nBits 7:6 Reserved, must be kept at reset value.\nBit 5 USART6EN: USART6 clock enable\nThis bit is set and cleared by software.\n0: USART6 clock disabled\n1: USART6 clock enabled\nBit 4 USART1EN: USART1 clock enable\nThis bit is set and cleared by software.\n0: USART1 clock disabled\n1: USART1 clock enabled\nBits 3:2 Reserved, must be kept at reset value.\nBit 1 TIM8EN: TIM8 clock enable\nThis bit is set and cleared by software.\n0: TIM8 clock disabled\n1: TIM8 clock enabled\nBit 0 TIM1EN: TIM1 clock enable\nThis bit is set and cleared by software.\n0: TIM1 clock disabled\n1: TIM1 clock enabled\n\n\n<>\n\nRM0090 Rev 21\n191/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.15 \nRCC AHB1 peripheral clock enable in low power mode register\n(RCC_AHB1LPENR)\nAddress offset: 0x50\nReset value: 0x7EEF 97FF\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nRes.\nOTGHS\nULPILPE\nN\nOTGH\nS\nLPEN\nETHPT\nP\nLPEN\nETHRX\nLPEN\nETHTX\nLPEN\nETHMA\nC\nLPEN\nRes.\nDMA2D\nLPEN\nDMA2\nLPEN\nDMA1\nLPEN\nRes.\nSRAM3\nLPEN\nBKPSRA\nM\nLPEN\nSRAM\n2\nLPEN\nSRAM\n1\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFLITF\nLPEN\nReserved\nCRC\nLPEN\nRes.\nGPIOK\nLPEN\nGPIOIJ\nLPEN\nGPIOI\nLPEN\nGPIOH\nLPEN\nGPIOG\nG\nLPEN\nGPIO\nF\nLPEN\nGPIOE\nLPEN\nGPIOD\nLPEN\nGPIOC\nLPEN\nGPIOB\nLPEN\nGPIOA\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBit 30 OTGHSULPILPEN: USB OTG HS ULPI clock enable during Sleep mode\nThis bit is set and cleared by software. It must be cleared when the OTG_HS is used in FS \nmode.\n0: USB OTG HS ULPI clock disabled during Sleep mode\n1: USB OTG HS ULPI clock enabled during Sleep mode\nBit 29 OTGHSLPEN: USB OTG HS clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: USB OTG HS clock disabled during Sleep mode\n1: USB OTG HS clock enabled during Sleep mode\nBit 28 ETHMACPTPLPEN: Ethernet PTP clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Ethernet PTP clock disabled during Sleep mode\n1: Ethernet PTP clock enabled during Sleep mode\nBit 27 ETHMACRXLPEN: Ethernet reception clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Ethernet reception clock disabled during Sleep mode\n1: Ethernet reception clock enabled during Sleep mode\nBit 26 ETHMACTXLPEN: Ethernet transmission clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Ethernet transmission clock disabled during sleep mode\n1: Ethernet transmission clock enabled during sleep mode\nBit 25 ETHMACLPEN: Ethernet MAC clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Ethernet MAC clock disabled during Sleep mode\n1: Ethernet MAC clock enabled during Sleep mode\nBit 24 Reserved, must be kept at reset value.\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n192/1757\nRM0090 Rev 21\nBit 23 DMA2DLPEN: DMA2D clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: DMA2D clock disabled during Sleep mode\n1: DMA2D clock enabled during Sleep mode\nBit 22 DMA2LPEN: DMA2 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: DMA2 clock disabled during Sleep mode\n1: DMA2 clock enabled during Sleep mode\nBit 21 DMA1LPEN: DMA1 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: DMA1 clock disabled during Sleep mode\n1: DMA1 clock enabled during Sleep mode\nBit 20 Reserved, must be kept at reset value.\nBit 19 SRAM3LPEN: SRAM3 interface clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SRAM3 interface clock disabled during Sleep mode\n1: SRAM3 interface clock enabled during Sleep mode\nBit 18 BKPSRAMLPEN: Backup SRAM interface clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Backup SRAM interface clock disabled during Sleep mode\n1: Backup SRAM interface clock enabled during Sleep mode\nBit 17 SRAM2LPEN: SRAM2 interface clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SRAM2 interface clock disabled during Sleep mode\n1: SRAM2 interface clock enabled during Sleep mode\nBit 16 SRAM1LPEN: SRAM1 interface clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SRAM1 interface clock disabled during Sleep mode\n1: SRAM1 interface clock enabled during Sleep mode\nBit 15 FLITFLPEN: Flash interface clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Flash interface clock disabled during Sleep mode\n1: Flash interface clock enabled during Sleep mode\nBits 14:13 Reserved, must be kept at reset value.\nBit 12 CRCLPEN: CRC clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: CRC clock disabled during Sleep mode\n1: CRC clock enabled during Sleep mode\nBit 11 Reserved, must be kept at reset value.\nBit 10 GPIOKLPEN: IO port K clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port K clock disabled during Sleep mode\n1: IO port K clock enabled during Sleep mode\n\n\n<>\n\nRM0090 Rev 21\n193/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 9 GPIOJLPEN: IO port J clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port J clock disabled during Sleep mode\n1: IO port J clock enabled during Sleep mode\nBit 8 GPIOILPEN: IO port I clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port I clock disabled during Sleep mode\n1: IO port I clock enabled during Sleep mode\nBit 7\nGPIOHLPEN: IO port H clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port H clock disabled during Sleep mode\n1: IO port H clock enabled during Sleep mode\nBits 6 GPIOGLPEN: IO port G clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port G clock disabled during Sleep mode\n1: IO port G clock enabled during Sleep mode\nBit 5 GPIOFLPEN: IO port F clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port F clock disabled during Sleep mode\n1: IO port F clock enabled during Sleep mode\nBit 4 GPIOELPEN: IO port E clock enable during Sleep mode\nSet and cleared by software.\n0: IO port E clock disabled during Sleep mode\n1: IO port E clock enabled during Sleep mode\nBit 3 GPIODLPEN: IO port D clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port D clock disabled during Sleep mode\n1: IO port D clock enabled during Sleep mode\nBit 2 GPIOCLPEN: IO port C clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port C clock disabled during Sleep mode\n1: IO port C clock enabled during Sleep mode\nBit 1 GPIOBLPEN: IO port B clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port B clock disabled during Sleep mode\n1: IO port B clock enabled during Sleep mode\nBit 0 GPIOALPEN: IO port A clock enable during sleep mode\nThis bit is set and cleared by software.\n0: IO port A clock disabled during Sleep mode\n1: IO port A clock enabled during Sleep mode\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n194/1757\nRM0090 Rev 21\n6.3.16 \nRCC AHB2 peripheral clock enable in low power mode register\n(RCC_AHB2LPENR)\nAddress offset: 0x54\nReset value: 0x0000 00F1\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOTGFS\nLPEN\nRNG\nLPEN\nHASH\nLPEN\nCRYP\nLPEN\nReserved\nDCMI\nLPEN\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBit 7 OTGFSLPEN: USB OTG FS clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: USB OTG FS clock disabled during Sleep mode\n1: USB OTG FS clock enabled during Sleep mode\nBit 6 RNGLPEN: Random number generator clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Random number generator clock disabled during Sleep mode\n1: Random number generator clock enabled during Sleep mode\nBit 5 HASHLPEN: Hash modules clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Hash modules clock disabled during Sleep mode\n1: Hash modules clock enabled during Sleep mode\nBit 4 CRYPLPEN: Cryptography modules clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: cryptography modules clock disabled during Sleep mode\n1: cryptography modules clock enabled during Sleep mode\nBits 3:1 Reserved, must be kept at reset value.\nBit 0 DCMILPEN: Camera interface enable during Sleep mode\nThis bit is set and cleared by software.\n0: Camera interface clock disabled during Sleep mode\n1: Camera interface clock enabled during Sleep mode\n\n\n<>\n\nRM0090 Rev 21\n195/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.17 \nRCC AHB3 peripheral clock enable in low power mode register\n(RCC_AHB3LPENR)\nAddress offset: 0x58\nReset value: 0x0000 0001\nAccess: no wait state, word, half-word and byte access.\n \n \n6.3.18 \nRCC APB1 peripheral clock enable in low power mode register\n(RCC_APB1LPENR)\nAddress offset: 0x60\nReset value: 0xF6FE C9FF\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFMC\nLPEN\nrw\nBits 31:1Reserved, must be kept at reset value.\nBit 0\nFMCLPEN: Flexible memory controller module clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: FMC module clock disabled during Sleep mode\n1: FMC module clock enabled during Sleep mode\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nUART8\nLPEN\nUART7\nLPEN\nDAC\nLPEN\nPWR\nLPEN\nRESER\nVED\nCAN2\nLPEN\nCAN1\nLPEN\nReser-\nved\nI2C3\nLPEN\nI2C2\nLPEN\nI2C1\nLPEN\nUART5\nLPEN\nUART4\nLPEN\nUSART\n3\nLPEN\nUSART\n2\nLPEN\nReser-\nved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSPI3\nLPEN\nSPI2\nLPEN\nReserved\nWWDG\nLPEN\nReserved\nTIM14\nLPEN\nTIM13\nLPEN\nTIM12\nLPEN\nTIM7\nLPEN\nTIM6 \nLPEN\nTIM5\nLPEN\nTIM4\nLPEN\nTIM3\nLPEN\nTIM2\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n196/1757\nRM0090 Rev 21\nBit 31 UART8LPEN: UART8 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: UART8 clock disabled during Sleep mode\n1: UART8 clock enabled during Sleep mode\nBit 30 UART7LPEN: UART7 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: UART7 clock disabled during Sleep mode\n1: UART7 clock enabled during Sleep mode\nBit 29 DACLPEN: DAC interface clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: DAC interface clock disabled during Sleep mode\n1: DAC interface clock enabled during Sleep mode\nBit 28 PWRLPEN: Power interface clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Power interface clock disabled during Sleep mode\n1: Power interface clock enabled during Sleep mode\nBit 27 Reserved, must be kept at reset value.\nBit 26 CAN2LPEN: CAN 2 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: CAN 2 clock disabled during sleep mode\n1: CAN 2 clock enabled during sleep mode\nBit 25 CAN1LPEN: CAN 1 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: CAN 1 clock disabled during Sleep mode\n1: CAN 1 clock enabled during Sleep mode\nBit 24 Reserved, must be kept at reset value.\nBit 23 I2C3LPEN: I2C3 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: I2C3 clock disabled during Sleep mode\n1: I2C3 clock enabled during Sleep mode\nBit 22 I2C2LPEN: I2C2 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: I2C2 clock disabled during Sleep mode\n1: I2C2 clock enabled during Sleep mode\nBit 21 I2C1LPEN: I2C1 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: I2C1 clock disabled during Sleep mode\n1: I2C1 clock enabled during Sleep mode\nBit 20 UART5LPEN: UART5 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: UART5 clock disabled during Sleep mode\n1: UART5 clock enabled during Sleep mode\nBit 19 UART4LPEN: UART4 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: UART4 clock disabled during Sleep mode\n1: UART4 clock enabled during Sleep mode\n\n\n<>\n\nRM0090 Rev 21\n197/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 18\nUSART3LPEN: USART3 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: USART3 clock disabled during Sleep mode\n1: USART3 clock enabled during Sleep mode\nBit 17 USART2LPEN: USART2 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: USART2 clock disabled during Sleep mode\n1: USART2 clock enabled during Sleep mode\nBit 16 Reserved, must be kept at reset value.\nBit 15 SPI3LPEN: SPI3 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SPI3 clock disabled during Sleep mode\n1: SPI3 clock enabled during Sleep mode\nBit 14 SPI2LPEN: SPI2 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SPI2 clock disabled during Sleep mode\n1: SPI2 clock enabled during Sleep mode\nBits 13:12 Reserved, must be kept at reset value.\nBit 11 WWDGLPEN: Window watchdog clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Window watchdog clock disabled during sleep mode\n1: Window watchdog clock enabled during sleep mode\nBits 10:9 Reserved, must be kept at reset value.\nBit 8 TIM14LPEN: TIM14 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM14 clock disabled during Sleep mode\n1: TIM14 clock enabled during Sleep mode\nBit 7 TIM13LPEN: TIM13 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM13 clock disabled during Sleep mode\n1: TIM13 clock enabled during Sleep mode\nBit 6 TIM12LPEN: TIM12 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM12 clock disabled during Sleep mode\n1: TIM12 clock enabled during Sleep mode\nBit 5 TIM7LPEN: TIM7 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM7 clock disabled during Sleep mode\n1: TIM7 clock enabled during Sleep mode\nBit 4 TIM6LPEN: TIM6 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM6 clock disabled during Sleep mode\n1: TIM6 clock enabled during Sleep mode\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n198/1757\nRM0090 Rev 21\nBit 3 TIM5LPEN: TIM5 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM5 clock disabled during Sleep mode\n1: TIM5 clock enabled during Sleep mode\nBit 2 TIM4LPEN: TIM4 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM4 clock disabled during Sleep mode\n1: TIM4 clock enabled during Sleep mode\nBit 1 TIM3LPEN: TIM3 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM3 clock disabled during Sleep mode\n1: TIM3 clock enabled during Sleep mode\nBit 0\nTIM2LPEN: TIM2 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM2 clock disabled during Sleep mode\n1: TIM2 clock enabled during Sleep mode\n\n\n<>\n\nRM0090 Rev 21\n199/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.19 \nRCC APB2 peripheral clock enabled in low power mode register\n(RCC_APB2LPENR)\nAddress offset: 0x64\nReset value: 0x0x0477 7F33 \nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nLTDC\nLPEN\nReserved\nSAI1\nLPEN\nSPI6\nLPEN\nSPI5\nLPEN\nReser-\nved\nTIM11\nLPEN\nTIM10\nLPEN\nTIM9\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReser-\nved\nSYSC\nFG\nLPEN\nSPI4\nLPEN\nSPI1\nLPEN\nSDIO\nLPEN\nADC3\nLPEN\nADC2\nLPEN\nADC1\nLPEN\nReserved\nUSART\n6\nLPEN\nUSART\n1\nLPEN\nReserved\nTIM8\nLPEN\nTIM1\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:27 Reserved, must be kept at reset value.\nBit 26 LTDCLPEN: LTDC clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: LTDC clock disabled during Sleep mode\n1: LTDC clock enabled during Sleep mode\nBits 25:23 Reserved, must be kept at reset value.\nBit 22 SAI1LPEN: SAI1 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SAI1 clock disabled during Sleep mode\n1: SAI1 clock enabled during Sleep mode\nBit 21 SPI6LPEN: SPI6 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SPI6 clock disabled during Sleep mode\n1: SPI6 clock enabled during Sleep mode\nBit 20 SPI5LPEN: SPI5 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SPI5 clock disabled during Sleep mode\n1: SPI5 clock enabled during Sleep mode\nBit 19 Reserved, must be kept at reset value.\nBit 18 TIM11LPEN: TIM11 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM11 clock disabled during Sleep mode\n1: TIM11 clock enabled during Sleep mode\nBit 17 TIM10LPEN: TIM10 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM10 clock disabled during Sleep mode\n1: TIM10 clock enabled during Sleep mode\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n200/1757\nRM0090 Rev 21\nBit 16 TIM9LPEN: TIM9 clock enable during sleep mode\nThis bit is set and cleared by software.\n0: TIM9 clock disabled during Sleep mode\n1: TIM9 clock enabled during Sleep mode\nBit 15 Reserved, must be kept at reset value.\nBit 14 SYSCFGLPEN: System configuration controller clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: System configuration controller clock disabled during Sleep mode\n1: System configuration controller clock enabled during Sleep mode\nBit 13 SPI4LPEN: SPI4 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SPI4 clock disabled during Sleep mode\n1: SPI4 clock enabled during Sleep mode\nBit 12 SPI1LPEN: SPI1 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SPI1 clock disabled during Sleep mode\n1: SPI1 clock enabled during Sleep mode\nBit 11 SDIOLPEN: SDIO clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SDIO module clock disabled during Sleep mode\n1: SDIO module clock enabled during Sleep mode\nBit 10 ADC3LPEN: ADC 3 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: ADC 3 clock disabled during Sleep mode\n1: ADC 3 clock enabled during Sleep mode\nBit 9 ADC2LPEN: ADC2 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: ADC2 clock disabled during Sleep mode\n1: ADC2 clock enabled during Sleep mode\nBit 8 ADC1LPEN: ADC1 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: ADC1 clock disabled during Sleep mode\n1: ADC1 clock enabled during Sleep mode\nBits 7:6 Reserved, must be kept at reset value.\nBit 5 USART6LPEN: USART6 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: USART6 clock disabled during Sleep mode\n1: USART6 clock enabled during Sleep mode\nBit 4 USART1LPEN: USART1 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: USART1 clock disabled during Sleep mode\n1: USART1 clock enabled during Sleep mode\n\n\n<>\n\nRM0090 Rev 21\n201/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.20 \nRCC Backup domain control register (RCC_BDCR)\nAddress offset: 0x70\nReset value: 0x0000 0000, reset by Backup domain reset.\nAccess: 0 ≤ wait state ≤ 3, word, half-word and byte access\nWait states are inserted in case of successive accesses to this register.\nThe LSEON, LSEBYP, RTCSEL and RTCEN bits in the RCC Backup domain control \nregister (RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are \nwrite-protected and the DBP bit in the PWR power control register (PWR_CR) for \nSTM32F42xxx and STM32F43xxx has to be set before these can be modified. Refer to \nSection 6.1.1: System reset on page 152 for further information. These bits are only reset \nafter a Backup domain Reset (see Section 6.1.3: Backup domain reset). Any internal or \nexternal Reset has no effect on these bits.\n \n \nBits 3:2 Reserved, must be kept at reset value.\nBit 1 TIM8LPEN: TIM8 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM8 clock disabled during Sleep mode\n1: TIM8 clock enabled during Sleep mode\nBit 0 TIM1LPEN: TIM1 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM1 clock disabled during Sleep mode\n1: TIM1 clock enabled during Sleep mode\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nBDRST\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRTCEN\nReserved\nRTCSEL[1:0]\nReserved\nLSEBY\nP\nLSERD\nY\nLSEON\nrw\nrw\nrw\nrw\nr\nrw\nBits 31:17 Reserved, must be kept at reset value.\nBit 16 BDRST: Backup domain software reset\nThis bit is set and cleared by software.\n0: Reset not activated\n1: Resets the entire Backup domain\nNote: The BKPSRAM is not affected by this reset, the only way of resetting the BKPSRAM is \nthrough the Flash interface when a protection level change from level 1 to level 0 is \nrequested.\nThe backup domain software reset does not take effect until the DBP bit of the \nPWR_CR register is set.\nBit 15 RTCEN: RTC clock enable\nThis bit is set and cleared by software.\n0: RTC clock disabled\n1: RTC clock enabled\nBits 14:10 Reserved, must be kept at reset value.\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n202/1757\nRM0090 Rev 21\n6.3.21 \nRCC clock control & status register (RCC_CSR)\nAddress offset: 0x74\nReset value: 0x0E00 0000, reset by system reset, except reset flags by power reset only.\nAccess: 0 ≤ wait state ≤ 3, word, half-word and byte access\nWait states are inserted in case of successive accesses to this register.\n \nBits 9:8 RTCSEL[1:0]: RTC clock source selection\nThese bits are set by software to select the clock source for the RTC. Once the RTC clock \nsource has been selected, it cannot be changed anymore unless the Backup domain is \nreset. The BDRST bit can be used to reset them.\n00: No clock\n01: LSE oscillator clock used as the RTC clock\n10: LSI oscillator clock used as the RTC clock\n11: HSE oscillator clock divided by a programmable prescaler (selection through the \nRTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC \nclock\nBits 7:3 Reserved, must be kept at reset value.\nBit 2 LSEBYP: External low-speed oscillator bypass\nThis bit is set and cleared by software to bypass the oscillator. This bit can be written only \nwhen the LSE clock is disabled.\n0: LSE oscillator not bypassed\n1: LSE oscillator bypassed\nBit 1 LSERDY: External low-speed oscillator ready\nThis bit is set and cleared by hardware to indicate when the external 32 kHz oscillator is \nstable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed \noscillator clock cycles.\n0: LSE clock not ready\n1: LSE clock ready\nBit 0 LSEON: External low-speed oscillator enable\nThis bit is set and cleared by software.\n0: LSE clock OFF\n1: LSE clock ON\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nLPWR\nRSTF\nWWDG\nRSTF\nIWDG\nRSTF\nSFT\nRSTF\nPOR\nRSTF\nPIN\nRSTF\nBORRS\nTF\nRMVF\nReserved\nr\nr\nr\nr\nr\nr\nr\nrt_w\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLSIRDY\nLSION\nr\nrw\n\n\n<>\n\nRM0090 Rev 21\n203/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n \nBit 31 LPWRRSTF: Low-power reset flag\nThis bit is set by hardware when a Low-power management reset occurs.\nCleared by writing to the RMVF bit.\n0: No Low-power management reset occurred\n1: Low-power management reset occurred\nFor further information on Low-power management reset, refer to Low-power management \nreset.\nBit 30 WWDGRSTF: Window watchdog reset flag\nThis bit is set by hardware when a window watchdog reset occurs.\nCleared by writing to the RMVF bit.\n0: No window watchdog reset occurred\n1: Window watchdog reset occurred\nBit 29 IWDGRSTF: Independent watchdog reset flag\nThis bit is set by hardware when an independent watchdog reset from VDD domain occurs.\nCleared by writing to the RMVF bit.\n0: No watchdog reset occurred\n1: Watchdog reset occurred\nBit 28 SFTRSTF: Software reset flag\nThis bit is set by hardware when a software reset occurs.\nCleared by writing to the RMVF bit.\n0: No software reset occurred\n1: Software reset occurred\nBit 27 PORRSTF: POR/PDR reset flag\nThis bit is set by hardware when a POR/PDR reset occurs.\nCleared by writing to the RMVF bit.\n0: No POR/PDR reset occurred\n1: POR/PDR reset occurred\nBit 26 PINRSTF: PIN reset flag\nThis bit is set by hardware when a reset from the NRST pin occurs.\nCleared by writing to the RMVF bit.\n0: No reset from NRST pin occurred\n1: Reset from NRST pin occurred\nBit 25 BORRSTF: BOR reset flag\nCleared by software by writing the RMVF bit.\nThis bit is set by hardware when a POR/PDR or BOR reset occurs.\n0: No POR/PDR or BOR reset occurred\n1: POR/PDR or BOR reset occurred\nBit 24 RMVF: Remove reset flag\nThis bit is set by software to clear the reset flags.\n0: No effect\n1: Clear the reset flags\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n204/1757\nRM0090 Rev 21\n6.3.22 \nRCC spread spectrum clock generation register (RCC_SSCGR)\nAddress offset: 0x80\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\nThe spread spectrum clock generation is available only for the main PLL.\nThe RCC_SSCGR register must be written either before the main PLL is enabled or after \nthe main PLL disabled.\nNote:\nFor full details about PLL spread spectrum clock generation (SSCG) characteristics, refer to \nthe “Electrical characteristics” section in your device datasheet. \n \n \nBits 23:2 Reserved, must be kept at reset value.\nBit 1 LSIRDY: Internal low-speed oscillator ready\nThis bit is set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is \nstable. After the LSION bit is cleared, LSIRDY goes low after 3 LSI clock cycles.\n0: LSI RC oscillator not ready\n1: LSI RC oscillator ready\nBit 0 LSION: Internal low-speed oscillator enable\nThis bit is set and cleared by software.\n0: LSI RC oscillator OFF\n1: LSI RC oscillator ON\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nSSCG\nEN\nSPR\nEAD\nSEL\nReserved\nINCSTEP\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nINCSTEP\nMODPER\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 SSCGEN: Spread spectrum modulation enable\nThis bit is set and cleared by software.\n0: Spread spectrum modulation DISABLE. (To write after clearing CR[24]=PLLON bit)\n1: Spread spectrum modulation ENABLE. (To write before setting CR[24]=PLLON bit)\nBit 30 SPREADSEL: Spread Select\nThis bit is set and cleared by software.\nTo write before to set CR[24]=PLLON bit.\n0: Center spread\n1: Down spread\n\n\n<>\n\nRM0090 Rev 21\n205/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.23 \nRCC PLLI2S configuration register (RCC_PLLI2SCFGR)\nAddress offset: 0x84\nReset value: 0x2400 3000\nAccess: no wait state, word, half-word and byte access.\nThis register is used to configure the PLLI2S clock outputs according to the formulas:\nf(VCO clock) = f(PLLI2S clock input) × (PLLI2SN / PLLM)\nf(PLL I2S clock output) = f(VCO clock) / PLLI2SR\n \nBits 29:28 Reserved, must be kept at reset value.\nBits 27:13 INCSTEP: Incrementation step\nThese bits are set and cleared by software. To write before setting CR[24]=PLLON bit.\nConfiguration input for modulation profile amplitude.\nBits 12:0 MODPER: Modulation period\nThese bits are set and cleared by software. To write before setting CR[24]=PLLON bit.\nConfiguration input for modulation profile period.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserv\ned\nPLLI2S\nR2\nPLLI2S\nR1\nPLLI2S\nR0\nPLLI2SQ\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserv\ned\nPLLI2SN\n8\nPLLI2SN\n7\nPLLI2SN\n6\nPLLI2SN\n5\nPLLI2SN\n4\nPLLI2SN\n3\nPLLI2SN\n2\nPLLI2SN\n1\nPLLI2SN\n0\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n206/1757\nRM0090 Rev 21\nBit 31 Reserved, must be kept at reset value.\nBits 30:28 PLLI2SR: PLLI2S division factor for I2S clocks\nThese bits are set and cleared by software to control the I2S clock frequency. These bits \nshould be written only if the PLLI2S is disabled. The factor must be chosen in accordance \nwith the prescaler values inside the I2S peripherals, to reach 0.3% error when using \nstandard crystals and 0% error with audio crystals. For more information about I2S clock \nfrequency and precision, refer to Section 28.4.4: Clock generator in the I2S chapter.\nCaution: The I2Ss requires a frequency lower than or equal to 192 MHz to work correctly.\nI2S clock frequency = VCO frequency / PLLR with 2 ≤ PLLR ≤ 7\n000: PLLR = 0, wrong configuration\n001: PLLR = 1, wrong configuration\n010: PLLR = 2\n...\n111: PLLR = 7\nBits 27:24 PLLI2SQ: PLLI2S division factor for SAI1 clock\nThese bits are set and cleared by software to control the SAI1 clock frequency.\nThey should be written when the PLLI2S is disabled.\nSAI1 clock frequency = VCO frequency / PLLI2SQ with 2 <= PLLI2SIQ <= 15\n0000: PLLI2SQ = 0, wrong configuration\n0001: PLLI2SQ = 1, wrong configuration\n0010: PLLI2SQ = 2\n0011: PLLI2SQ = 3\n0100: PLLI2SQ = 4\n0101: PLLI2SQ = 5\n...\n1111: PLLI2SQ = 15\n\n\n<>\n\nRM0090 Rev 21\n207/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBits 23:15 Reserved, must be kept at reset value.\nBits 14:6 PLLI2SN: PLLI2S multiplication factor for VCO\nThese bits are set and cleared by software to control the multiplication factor of the VCO. \nThese bits can be written only when PLLI2S is disabled. Only half-word and word accesses \nare allowed to write these bits.\nCaution: The software has to set these bits correctly to ensure that the VCO output \nfrequency is between 100 and 432 MHz. \nVCO output frequency = VCO input frequency × PLLI2SN with 50 ≤ PLLI2SN ≤ 432\n000000000: PLLI2SN = 0, wrong configuration \n000000001: PLLI2SN = 1, wrong configuration\n...\n000110010: PLLI2SN = 50\n...\n001100011: PLLI2SN = 99 \n001100100: PLLI2SN = 100\n001100101: PLLI2SN = 101\n001100110: PLLI2SN = 102\n... \n110110000: PLLI2SN = 432\n110110001: PLLI2SN = 433, wrong configuration\n... \n111111111: PLLI2SN = 511, wrong configuration \nNote: Multiplication factors ranging from 50 and 99 are possible for VCO input frequency \nhigher than 1 MHz. However care must be taken that the minimum VCO output \nfrequency respects the value specified above. \nBits 5:0 Reserved, must be kept at reset value.\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n208/1757\nRM0090 Rev 21\n6.3.24 \nRCC PLL configuration register (RCC_PLLSAICFGR)\nAddress offset: 0x88\nReset value: 0x2400 3000\nAccess: no wait state, word, half-word and byte access.\nThis register is used to configure the PLLSAI clock outputs according to the formulas:\n•\nf(VCO clock) = f(PLLSAI clock input) × (PLLSAIN / PLLM)\n•\nf(PLLSAI1 clock output) = f(VCO clock) / PLLSAIQ\n•\nf(PLL LCD clock output) = f(VCO clock) / PLLSAIR\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPLLSAIR\nPLLSAIQ\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPLLSAIN\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBits 30:28 PLLSAIR: PLLSAI division factor for LCD clock\nSet and reset by software to control the LCD clock frequency.\nThese bits should be written when the PLLSAI is disabled.\nLCD clock frequency = VCO frequency / PLLSAIR with 2 ≤ PLLSAIR ≤ 7\n000: PLLSAIR = 0, wrong configuration\n001: PLLSAIR = 1, wrong configuration\n010: PLLSAIR = 2\n...\n111: PLLSAIR = 7\nBits 27:24 PLLSAIQ: PLLSAI division factor for SAI1 clock\nSet and reset by software to control the frequency of SAI1 clock.\nThese bits should be written when the PLLSAI is disabled.\nSAI1 clock frequency = VCO frequency / PLLSAIQ with 2 ≤ PLLSAIQ ≤15\n0000: PLLSAIQ = 0, wrong configuration\n0001: PLLSAIQ = 1, wrong configuration\n...\n0010: PLLSAIQ = 2\n0011: PLLSAIQ = 3\n0100: PLLSAIQ = 4\n0101: PLLSAIQ = 5\n...\n1111: PLLSAIQ = 15\n\n\n<>\n\nRM0090 Rev 21\n209/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n \n6.3.25 \nRCC Dedicated Clock Configuration Register (RCC_DCKCFGR)\nAddress offset: 0x8C\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\nThe RCC_DCKCFGR register allows to configure the timer clock prescalers and the PLLSAI \nand PLLI2S output clock dividers for SAI1 and LTDC peripherals according to the following \nformula:\nf(PLLSAIDIVQ clock output) = f(PLLSAI_Q) / PLLSAIDIVQ\nf(PLLSAIDIVR clock output) = f(PLLSAI_R) / PLLSAIDIVR\nf(PLLI2SDIVQ clock output) = f(PLLI2S_Q) / PLLI2SDIVQ\n \n \nBits 23:15 Reserved, must be kept at reset value.\nBits 14:6 PLLSAIN: PLLSAI division factor for VCO\nThese bits are set and cleared by software to control the multiplication factor of the VCO. \nThese bits can be written only when PLLSAI is disabled. Only half-word and word accesses \nare allowed to write these bits.\nCaution: The software has to set these bits correctly to ensure that the VCO output frequency \nis between 100 and 432 MHz. \nVCO output frequency = VCO input frequency × PLLISAIN with 50 ≤ PLLISAIN ≤ 432\n000000000: PLLISAIN = 0, wrong configuration \n000000001: PLLISAIN = 1, wrong configuration\n...\n000110010: PLLISAIN = 50\n...\n001100011: PLLISAIN = 99 \n001100100: PLLISAIN = 100\n001100101: PLLISAIN = 101\n001100110: PLLISAIN = 102\n... \n110110000: PLLISAIN = 432\n110110001: PLLISAIN = 433, wrong configuration\n... \n111111111: PLLISAIN = 511, wrong configuration \nNote: Multiplication factors ranging from 50 and 99 are possible for VCO input frequency \nhigher than 1 MHz. However care must be taken that the minimum VCO output \nfrequency respects the value specified above. \nBits 5:0 Reserved, must be kept at reset value\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTIMPRE\nSAI1BSRC\nSAI1ASRC\nReserved\nPLLSAIDIVR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPLLSAIDIVQ\nReserved\nPLLS2DIVQ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n210/1757\nRM0090 Rev 21\nBits 31:25 Reserved, must be kept at reset value.\nBit 24 TIMPRE: Timers clocks prescalers selection\nThis bit is set and reset by software to control the clock frequency of all the timers connected \nto APB1 and APB2 domain.\n0: If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a \ndivision factor of 1, TIMxCLK = PCLKx. Otherwise, the timer clock frequencies are set to \ntwice to the frequency of the APB domain to which the timers are connected:\nTIMxCLK = 2xPCLKx.\n1:If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a \ndivision factor of 1, 2 or 4, TIMxCLK = HCLK. Otherwise, the timer clock frequencies are set \nto four times to the frequency of the APB domain to which the timers are connected:\nTIMxCLK = 4xPCLKx.\nBits 23:22 SAI1BSRC: SAI1-B clock source selection\nThese bits are set and cleared by software to control the SAI1-B clock frequency.\nThey should be written when the PLLSAI and PLLI2S are disabled.\n00: SAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ\n01: SAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ\n10: SAI1-B clock frequency = Alternate function input frequency\n11: wrong configuration\nBits 21:20 SAI1ASRC: SAI1-A clock source selection\nThese bits are set and cleared by software to control the SAI1-A clock frequency.\nThey should be written when the PLLSAI and PLLI2S are disabled.\n00: SAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ\n01: SAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ\n10: SAI1-A clock frequency = Alternate function input frequency\n11: wrong configuration\nBits 19: 18 Reserved, must be kept at reset value.\nBits 17:16 PLLSAIDIVR: division factor for LCD_CLK\nThese bits are set and cleared by software to control the frequency of LCD_CLK.\nThey should be written only if PLLSAI is disabled.\nLCD_CLK frequency = f(PLLSAI_R) / PLLSAIDIVR with 2 ≤ PLLSAIDIVR ≤ 16\n00: PLLSAIDIVR = /2\n01: PLLSAIDIVR = /4\n10: PLLSAIDIVR = /8\n11: PLLSAIDIVR = /16\nBits 15: 13 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n211/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBits 12:8 PLLSAIDIVQ: PLLSAI division factor for SAI1 clock\nThese bits are set and reset by software to control the SAI1 clock frequency.\nThey should be written only if PLLSAI is disabled.\nSAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ with 1 ≤ PLLSAIDIVQ ≤ 31\n00000: PLLSAIDIVQ = /1\n00001: PLLSAIDIVQ = /2\n00010: PLLSAIDIVQ = /3\n00011: PLLSAIDIVQ = /4\n00100: PLLSAIDIVQ = /5\n...\n11111: PLLSAIDIVQ = /32\nBits 7:5 Reserved, must be kept at reset value.\nBits 4:0 PLLI2SDIVQ: PLLI2S division factor for SAI1 clock\nThese bits are set and reset by software to control the SAI1 clock frequency.\nThey should be written only if PLLI2S is disabled.\nSAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ with 1 <= PLLI2SDIVQ <= 31\n00000: PLLI2SDIVQ = /1\n00001: PLLI2SDIVQ = /2\n00010: PLLI2SDIVQ = /3\n00011: PLLI2SDIVQ = /4\n00100: PLLI2SDIVQ = /5\n...\n11111: PLLI2SDIVQ = /32\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n212/1757\nRM0090 Rev 21\n6.3.26 \nRCC register map\nTable 34 gives the register map and reset values.\n \nTable 34. RCC register map and reset values for STM32F42xxx and STM32F43xxx\nAddr. \noffset\nRegister \nname\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nRCC_CR\nReserved\nPLL SAIRDY\nPLL SAION\nPLL I2SRDY\nPLL I2SON\nPLL RDY\nPLL ON\nReserved\nCSSON\nHSEBYP\nHSERDY\nHSEON\nHSICAL 7\nHSICAL 6\nHSICAL 5\nHSICAL 4\nHSICAL 3\nHSICAL 2\nHSICAL 1\nHSICAL 0\nHSITRIM 4\nHSITRIM 3\nHSITRIM 2\nHSITRIM 1\nHSITRIM 0\nReserved\nHSIRDY\nHSION\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nX\nX\nX\nX\nX\nX\nX\nX\n1\n0\n0\n0\n0\n0\n1\n1\n0x04\nRCC_\nPLLCFGR\nReserved\nPLLQ 3\nPLLQ 2\nPLLQ 1\nPLLQ 0\nReserved\nPLLSRC\nReserved\nPLLP 1\nPLLP 0\nReserved\nPLLN 8\nPLLN 7\nPLLN 6\nPLLN 5\nPLLN 4\nPLLN 3\nPLLN 2\nPLLN 1\nPLLN 0\nPLLM 5\nPLLM 4\nPLLM 3\nPLLM 2\nPLLM 1\nPLLM 0\nReset value\n0\n1\n0\n0\n0\n0\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0x08\nRCC_CFGR\nMCO2 1\nMCO2 0\nMCO2PRE2\nMCO2PRE1\nMCO2PRE0\nMCO1PRE2\nMCO1PRE1\nMCO1PRE0\nI2SSRC\nMCO1 1\nMCO1 0\nRTCPRE 4\nRTCPRE 3\nRTCPRE 2\nRTCPRE 1\nRTCPRE 0\nPPRE2 2\nPPRE2 1\n PPRE2 0\n PPRE1 2\nPPRE1 1\nPPRE1 0\nReserved\nHPRE 3\nHPRE 2\nHPRE 1\nHPRE 0\nSWS 1\nSWS 0\nSW 1\nSW 0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nRCC_CIR\nReserved\nCSSC\nPLLSAIRDYC\nPLLI2SRDYC\nPLLRDYC\nHSERDYC\nHSIRDYC\nLSERDYC\nLSIRDYC\nReserved\nPLLSAIRDYIE\nPLLI2SRDYIE\nPLLRDYIE\nHSERDYIE\nHSIRDYIE\nLSERDYIE\nLSIRDYIE\nCSSF\nPLLSAIRDYF\nPLLI2SRDYF\nPLLRDYF\nHSERDYF\nHSIRDYF\nLSERDYF\nLSIRDYF\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nRCC_\nAHB1RSTR\nReserved\nOTGHSRST\nReserved\nETHMACRST\nReserved\nDMA2DRST\nDMA2RST\nDMA1RST\nReserved\nCRCRST\nReserved\nGPIOKRST\nGPIOJRST\nGPIOIRST\nGPIOHRST\nGPIOGRST\nGPIOFRST\nGPIOERST\nGPIODRST\nGPIOCRST\nGPIOBRST\nGPIOARST\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nRCC_\nAHB2RSTR\nReserved\nOTGFSRS\nRNGRST\nHSAHRST\nCRYPRST\nReserved\nDCMIRST\nReset value\n0\n0\n0\n0\n0\n0x18\nRCC_\nAHB3RSTR\nReserved\nFMCRS\nReset value\n0\n0x1C\nReserved \nReserved\n0x20\nRCC_\nAPB1RSTR\nUART8RST\nUART7RST\nDACRST\nPWRRST\nReserved\nCAN2RST\nCAN1RST\nReserved\nI2C3RST\nI2C2RST\nI2C1RST\nUART5RST\nUART4RST\nUART3RST\nUART2RST\nReserved\nSPI3RST\nSPI2RST\nReserved\nWWDGRST\nReserved\nTIM14RST\nTIM13RST\nTIM12RST\nTIM7RST\nTIM6RST\nTIM5RST\nTIM4RST\nTIM3RST\nTIM2RST\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x24\nRCC_\nAPB2RSTR\nReserved\nLTDCRST\nReserved\nSAI1RST\nSPI6RST\nSPI5RST\nReserved\nTIM11RST\nTIM10RST\nTIM9RST\nReserved\nSYSCFGRST\nSP45RST\nSPI1RST\nSDIORST\nReserved\nADCRST\nReserved\nUSART6RST\nUSART1RST\nReserved\nTIM8RST\nTIM1RST\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nReserved\nReserved\n0x2C\nReserved\nReserved\n0x30\nRCC_\nAHB1ENR\nReserved\nOTGHSULPIEN\nOTGHSEN\nETHMACPTPEN\nETHMACRXEN\nETHMACTXEN\nETHMACEN\nReserved\nDMA2DEN\nDMA2EN\nDMA1EN\nCCMDATARAMEN\nReserved\nBKPSRAMEN\nReserved\nCRCEN\nReserved\nGPIOKEN\nGPIOJEN\nGPIOIEN\nGPIOHEN\nGPIOGEN\nGPIOFEN\nGPIOEEN\nGPIODEN\nGPIOCEN\nGPIOBEN\nGPIOAEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n\n\n<>\n\nRM0090 Rev 21\n213/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n0x34\nRCC_\nAHB2ENR\nReserved\nOTGFSEN\nRNGEN\nHASHEN\nCRYPEN\nReserved\nDCMIEN\nReset value\n0\n0\n0\n0\n0\n0x38\nRCC_\nAHB3ENR\nReserved\nFMCEN\nReset value\n0\n0x3C\nReserved\nReserved\n0x40\nRCC_\nAPB1ENR\nUART8EN\nUART7EN\nDACEN\nPWREN\nReserved\nCAN2EN\nCAN1EN\nReserved\nI2C3EN\nI2C2EN\nI2C1EN\nUART5EN\nUART4EN\nUSART3EN\nUSART2EN\nReserved\nSPI3EN\nSPI2EN\nReserved\nWWDGEN\nReserved\nTIM14EN\nTIM13EN\nTIM12EN\nTIM7EN\nTIM6EN\nTIM5EN\nTIM4EN\nTIM3EN\nTIM2EN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x44\nRCC_\nAPB2ENR\nReserved\nLTDCEN\nReserved\nSAI1EN\nSPI6EN\nSPI5EN\nReserved\nTIM11EN\nTIM10EN\nTIM9EN\nReserved\nSYSCFGEN\nSPI4EN\nSPI1EN\nSDIOEN\nADC3EN\nADC2EN\nADC1EN\nReserved\nUSART6EN\nUSART1EN\nReserved\nTIM8EN\nTIM1EN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x48\nReserved\nReserved\n0x4C\nReserved\nReserved\n0x50\nRCC_\nAHB1LPENR\nReserved\nOTGHSULPILPEN\nOTGHSLPEN\nETHMACPTPLPEN\nETHMACRXLPEN\nETHMACTXLPEN\nETHMACLPEN\nReserved\nDMA2DLPEN\nDMA2LPEN\nDMA1LPEN\nReserved\nSRAM3LPEN\nBKPSRAMLPEN\nSRAM2LPEN\nSRAM1LPEN\nFLITFLPEN\nReserved\nCRCLPEN\nReserved\nGPIOKLPEN\nGPIOJLPEN\nGPIOILPEN\nGPIOHLPEN\nGPIOGLPEN\nGPIOFLPEN\nGPIOELPEN\nGPIODLPEN\nGPIOCLPEN\nGPIOBLPEN\nGPIOALPEN\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x54\nRCC_\nAHB2LPENR\nReserved\nOTGFSLPEN\nRNGLPEN\nHASHLPEN\nCRYPLPEN\nReserved\nDCMILPEN\nReset value\n1\n1\n1\n1\n1\n0x58\nRCC_\nAHB3LPENR\nReserved\nFMCLPEN\nReset value\n1\n0x5C\nReserved\nReserved\n0x60\nRCC_\nAPB1LPENR\nUART8LPEN\nUART7LPEN\nDACLPEN\nPWRLPEN\nReserved\nCAN2LPEN\nCAN1LPEN\nReserved\nI2C3LPEN\nI2C2LPEN\nI2C1LPEN\nUART5LPEN\nUART4LPEN\nUSART3LPEN\nUSART2LPEN\nReserved\nSPI3LPEN\nSPI2LPEN\nReserved\nWWDGLPEN\nReserved\nTIM14LPEN\nTIM13LPEN\nTIM12LPEN\nTIM7LPEN\nTIM6LPEN\nTIM5LPEN\nTIM4LPEN\nTIM3LPEN\nTIM2LPEN\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x64\nRCC_\nAPB2LPENR\nReserved\nLTDCLPEN\nReserved\nSAI1LPEN\nSPI6LPEN\nSPI5LPEN\nReserved\nTIM11LPEN\nTIM10LPEN\nTIM9LPEN\nReserved\nSYSCFGLPEN\nSPI4LPEN\nSPI1LPEN\nSDIOLPEN\nADC3LPEN\nADC2LPEN\nADC1LPEN\nReserved\nUSART6LPEN\nUSART1LPEN\nReserved\nTIM8LPEN\nTIM1LPEN\nReset value\n1\n1\n0\n1\n1\n0\n1\n1\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x68\nReserved\nReserved\n0x6C\nReserved\nReserved\n0x70\nRCC_BDCR\nReserved\nBDRST\nRTCEN\nReserved\nRTCSEL 1\nRTCSEL 0\nReserved\nLSEBYP\nLSERDY\nLSEON\nReset value\n0\n0\n0\n0\n0\n0\n0\nTable 34. RCC register map and reset values for STM32F42xxx and STM32F43xxx (continued) \nAddr. \noffset\nRegister \nname\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n214/1757\nRM0090 Rev 21\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x74\nRCC_CSR\nLPWRRSTF\nWWDGRSTF\nWDGRSTF\nSFTRSTF\nPORRSTF\nPADRSTF\nBORRSTF\nRMVF\nReserved\nLSIRDY\nLSION\nReset value\n0\n0\n0\n0\n1\n1\n1\n1\n0\n0\n0x78\nReserved\nReserved\n0x7C\nReserved\nReserved\n0x80\nRCC_SSCGR\nSSCGEN\nSPREADSEL\nReserved\nINCSTEP\nMODPER\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x84\nRCC_\nPLLI2SCFGR\nReserved\nPLLI2SRx\nPLLI2SQ\nReserved\nPLLI2SNx\nReserved\nReset value\n0\n1\n0\n0\n1\n0\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\n0x88\nRCC_\nPLLSAICFGR\nReserved\nPLLSAIR\nPLLSAIQ\nReserved\nPLLSAIN\nReserved\nReset value\n0\n1\n0\n0\n1\n0\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\n0x8C\nRCC_\nDCKCFGR\nReserved\nTIMPRE\nSAI1BSCR\nSAI1ASCR\nReserved\nPLLSAIDIVR\nReserved\n0\n0\n0\n0\n0\nReserved\nPLLI2SDIVQ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 34. RCC register map and reset values for STM32F42xxx and STM32F43xxx (continued) \nAddr. \noffset\nRegister \nname\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n215/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n7 \nReset and clock control for \nSTM32F405xx/07xx and STM32F415xx/17xx(RCC)\n7.1 \nReset\nThere are three types of reset, defined as system Reset, power Reset and backup domain \nReset. \n7.1.1 \nSystem reset\nA system reset sets all registers to their reset values unless specified otherwise in the \nregister description (see Figure 9).\nA system reset is generated when one of the following events occurs:\n1.\nA low level on the NRST pin (external reset)\n2. \nWindow watchdog end of count condition (WWDG reset)\n3. \nIndependent watchdog end of count condition (IWDG reset)\n4. \nA software reset (SW reset) (see Software reset)\n5. \nLow-power management reset (see Low-power management reset)\nSoftware reset\nThe reset source can be identified by checking the reset flags in the RCC clock control & \nstatus register (RCC_CSR).\nThe SYSRESETREQ bit in Cortex®-M4 with FPU Application Interrupt and Reset Control \nRegister must be set to force a software reset on the device. Refer to the Cortex®-M4 with \nFPU technical reference manual for more details.\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n216/1757\nRM0090 Rev 21\nLow-power management reset\nThere are two ways of generating a low-power management reset:\n1.\nReset generated when entering the Standby mode:\nThis type of reset is enabled by resetting the nRST_STDBY bit in the user option bytes. \nIn this case, whenever a Standby mode entry sequence is successfully executed, the \ndevice is reset instead of entering the Standby mode.\n2. \nReset when entering the Stop mode:\nThis type of reset is enabled by resetting the nRST_STOP bit in the user option bytes. \nIn this case, whenever a Stop mode entry sequence is successfully executed, the \ndevice is reset instead of entering the Stop mode.\n7.1.2 \nPower reset\nA power reset is generated when one of the following events occurs: \n1.\nPower-on/power-down reset (POR/PDR reset) or brownout (BOR) reset\n2. \nWhen exiting the Standby mode\nA power reset sets all registers to their reset values except the Backup domain (see \nFigure 9)\nThese sources act on the NRST pin and it is always kept low during the delay phase. The \nRESET service routine vector is fixed at address 0x0000_0004 in the memory map.\nThe system reset signal provided to the device is output on the NRST pin. The pulse \ngenerator guarantees a minimum reset pulse duration of 20 µs for each internal reset \nsource. In case of an external reset, the reset pulse is generated while the NRST pin is \nasserted low.\nFigure 20. Simplified diagram of the reset circuit\nThe Backup domain has two specific resets that affect only the Backup domain (see \nFigure 9).\n7.1.3 \nBackup domain reset\nThe backup domain reset sets all RTC registers, the RCC_BDCR register, and the BRE bit \nof the PWR_CSR register to their reset values. The BKPSRAM is not affected by this reset. \nThe only way of resetting the BKPSRAM is through the Flash interface by requesting a \nprotection level change from 1 to 0.\nNRST\nRPU\nVDD/VDDA\nWWDG reset\nIWDG reset\nPulse\ngenerator\nPower reset\nExternal\nreset\n(min 20 μs)\nSystem reset\nFilter\nSoftware reset\nLow-power management reset\nai16095c\n\n\n<>\n\nRM0090 Rev 21\n217/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nA backup domain reset is generated when one of the following events occurs:\n1.\nSoftware reset, triggered by setting the BDRST bit in the RCC Backup domain control \nregister (RCC_BDCR). \n2. \nVDD or VBAT power on, if both supplies have previously been powered off.\nNote:\nThe DBP bit of the PWR_CR register must be set to generate a backup domain reset.\n7.2 \nClocks\nThree different clock sources can be used to drive the system clock (SYSCLK):\n•\nHSI oscillator clock\n•\nHSE oscillator clock\n•\nMain PLL (PLL) clock\nThe devices have the two following secondary clock sources:\n•\n32 kHz low-speed internal RC (LSI RC) which drives the independent watchdog and, \noptionally, the RTC used for Auto-wakeup from the Stop/Standby mode.\n•\n32.768 kHz low-speed external crystal (LSE crystal) which optionally drives the RTC \nclock (RTCCLK)\nEach clock source can be switched on or off independently when it is not used, to optimize \npower consumption.\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n218/1757\nRM0090 Rev 21\nFigure 21. Clock tree\n1.\nFor full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in \nthe device datasheet.\nThe clock controller provides a high degree of flexibility to the application in the choice of the \nexternal crystal or the oscillator to run the core and peripherals at the highest frequency \nand, guarantee the appropriate frequency for peripherals that need a specific clock like \nEthernet, USB OTG FS and HS, I2S and SDIO.\nai16088e\nMII_RMII_SEL in SYSCFG_PMC to Ethernet MAC\nLSE\nETH_MII_TX_CLK_MII\nOTG_HS_ULPI_CK\nPLLI2SCLK\nFCLK Cortex free-\nrunning clock\nAPBx peripheral clocks\nAPBx timer clocks\n48 MHz\nclocks\nUSBHS\nULPI clock\nEthernet PTP clock\nMCO1\nMCO2\nETH_MII_RX_\nCLK_MII\nOSC32_IN\nOSC32_OUT\nto Independent watchdog\nLSE\nLSI\nto RTC\nRTCCLK\nRTCSEL[1:0] \nIWDGCLK\nOSC_IN\nOSC_OUT\nPLLCLK\nHSI\nHSI\nHSE\nSW\nSYSCLK\n168 MHz \nmax \nHCLK \nto AHB bus, core, memory and DMA\n168 MHz max.\nto Cortex System timer\nClock \nenable\nPLL48CK\nI2S clocks\nMACRMIICLK\nMACTXCLK\nMACRXCLK\nPeripheral \nclock enable\nWatchdog \nenable\nRTC \nenable\nPeripheral \nclock enable\n/2to31\nPLLI2S\nSYSCLK\nExt. clock \nI2SSRC\nHSE_RTC\nHSE\nI2S_CKIN\nUSB2.0 PHY\n24 to 60 \nMHz\nPHY Ethernet \n25 to 50 MHz\n/2,20\nPeripheral \nclock enable\nPeripheral \nclock enable\nPeripheral clock \nenable\nPeripheral \nclock enable\n4-26 MHz \nHSE OSC\n/M\n/1 to 5\n/1 to 5\n16 MHz \nHSI RC\nAHB \nPRESC\n/1,2,..512\nPeripheral \nclock enable\n/Q\n/P\n/R\nPLL\nVCO\n/Q\n/P\nPeripheral \nclock enable\n/8\nLSE RC\n32.768 kHz\nAPB \nPRESC\n/1,2,4,8,16\nPeripheral \nclock enable\nif (APBx presc = 1x1\n else x2 \nVCO\nxN\nxN\n/R\nLSE RC\n32 kHz\n\n\n<>\n\nRM0090 Rev 21\n219/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nSeveral prescalers are used to configure the AHB frequency, the high-speed APB (APB2) \nand the low-speed APB (APB1) domains. The maximum frequency of the AHB domain is \n168 MHz. The maximum allowed frequency of the high-speed APB2 domain is 84 MHz. The \nmaximum allowed frequency of the low-speed APB1 domain is 42 MHz\nAll peripheral clocks are derived from the system clock (SYSCLK) except for:\n•\nThe USB OTG FS clock (48 MHz), the random analog generator (RNG) clock \n(≤48 MHz) and the SDIO clock (≤ 48 MHz) which are coming from a specific output of \nPLL (PLL48CLK)\n•\nThe I2S clock\nTo achieve high-quality audio performance, the I2S clock can be derived either from a \nspecific PLL (PLLI2S) or from an external clock mapped on the I2S_CKIN pin. For \nmore information about I2S clock frequency and precision, refer to Section 28.4.4: \nClock generator.\n•\nThe USB OTG HS (60 MHz) clock which is provided from the external PHY\n•\nThe Ethernet MAC clocks (TX, RX and RMII) which are provided from the external \nPHY. For further information on the Ethernet configuration, please refer to \nSection 33.4.4: MII/RMII selection in the Ethernet peripheral description. When the \nEthernet is used, the AHB clock frequency must be at least 25 MHz.\nThe RCC feeds the external clock of the Cortex System Timer (SysTick) with the AHB clock \n(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock \n(HCLK), configurable in the SysTick control and status register.\nThe timer clock frequencies are automatically set by hardware. There are two cases:\n1.\nIf the APB prescaler is 1, the timer clock frequencies are set to the same frequency as \nthat of the APB domain to which the timers are connected.\n2. \nOtherwise, they are set to twice (×2) the frequency of the APB domain to which the \ntimers are connected.\nFCLK acts as Cortex®-M4 with FPU free-running clock. For more details, refer to the \nCortex®-M4 with FPU technical reference manual.\n7.2.1 \nHSE clock\nThe high speed external clock signal (HSE) can be generated from two possible clock \nsources:\n•\nHSE external crystal/ceramic resonator\n•\nHSE external user clock\nThe resonator and the load capacitors have to be placed as close as possible to the \noscillator pins in order to minimize output distortion and startup stabilization time. The \nloading capacitance values must be adjusted according to the selected oscillator.\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n220/1757\nRM0090 Rev 21\n \nExternal source (HSE bypass)\nIn this mode, an external clock source must be provided. You select this mode by setting the \nHSEBYP and HSEON bits in the RCC clock control register (RCC_CR). The external clock \nsignal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the \nOSC_OUT pin should be left HI-Z. See Figure 22.\nExternal crystal/ceramic resonator (HSE crystal)\nThe HSE has the advantage of producing a very accurate rate on the main clock.\nThe associated hardware configuration is shown in Figure 22. Refer to the electrical \ncharacteristics section of the datasheet for more details.\nThe HSERDY flag in the RCC clock control register (RCC_CR) indicates if the high-speed \nexternal oscillator is stable or not. At startup, the clock is not released until this bit is set by \nhardware. An interrupt can be generated if enabled in the RCC clock interrupt register \n(RCC_CIR).\nThe HSE Crystal can be switched on and off using the HSEON bit in the RCC clock control \nregister (RCC_CR).\n7.2.2 \nHSI clock\nThe HSI clock signal is generated from an internal 16 MHz RC oscillator and can be used \ndirectly as a system clock, or used as PLL input.\nThe HSI RC oscillator has the advantage of providing a clock source at low cost (no external \ncomponents). It also has a faster startup time than the HSE crystal oscillator however, even \nwith calibration the frequency is less accurate than an external crystal oscillator or ceramic \nresonator. \nFigure 22. HSE/ LSE clock sources\nHardware configuration\nExternal clock\nCrystal/ceramic \nresonators\nOSC_OUT\nExternal\nsource\n(HI-Z)\nOSC_IN\nOSC_OUT\nLoad\ncapacitors\nCL2\nCL1\n\n\n<>\n\nRM0090 Rev 21\n221/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nCalibration\nRC oscillator frequencies can vary from one chip to another due to manufacturing process \nvariations, this is why each device is factory calibrated by ST for 1% accuracy at TA= 25 °C.\nAfter reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the RCC clock \ncontrol register (RCC_CR). \nIf the application is subject to voltage or temperature variations this may affect the RC \noscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0] \nbits in the RCC clock control register (RCC_CR).\nThe HSIRDY flag in the RCC clock control register (RCC_CR) indicates if the HSI RC is \nstable or not. At startup, the HSI RC output clock is not released until this bit is set by \nhardware. \nThe HSI RC can be switched on and off using the HSION bit in the RCC clock control \nregister (RCC_CR).\nThe HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal \noscillator fails. Refer to Section 7.2.7: Clock security system (CSS) on page 222.\n7.2.3 \nPLL configuration\nThe STM32F4xx devices feature two PLLs:\n•\nA main PLL (PLL) clocked by the HSE or HSI oscillator and featuring two different \noutput clocks:\n–\nThe first output is used to generate the high speed system clock (up to 168 MHz)\n–\nThe second output is used to generate the clock for the USB OTG FS (48 MHz), \nthe random analog generator (≤48 MHz) and the SDIO (≤ 48 MHz). \n•\nA dedicated PLL (PLLI2S) used to generate an accurate clock to achieve high-quality \naudio performance on the I2S interface. \nSince the main-PLL configuration parameters cannot be changed once PLL is enabled, it is \nrecommended to configure PLL before enabling it (selection of the HSI or HSE oscillator as \nPLL clock source, and configuration of division factors M, N, P, and Q). \nThe PLLI2S uses the same input clock as PLL (PLLM[5:0] and PLLSRC bits are common to \nboth PLLs). However, the PLLI2S has dedicated enable/disable and division factors (N and \nR) configuration bits. Once the PLLI2S is enabled, the configuration parameters cannot be \nchanged.\nThe two PLLs are disabled by hardware when entering Stop and Standby modes, or when \nan HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock. RCC \nPLL configuration register (RCC_PLLCFGR) and RCC clock configuration register \n(RCC_CFGR) can be used to configure PLL and PLLI2S, respectively.\n7.2.4 \nLSE clock\nThe LSE clock is generated from a 32.768 kHz low-speed external crystal or ceramic \nresonator. It has the advantage providing a low-power but highly accurate clock source to \nthe real-time clock peripheral (RTC) for clock/calendar or other timing functions. \nThe LSE oscillator is switched on and off using the LSEON bit in RCC Backup domain \ncontrol register (RCC_BDCR). \n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n222/1757\nRM0090 Rev 21\nThe LSERDY flag in the RCC Backup domain control register (RCC_BDCR) indicates if the \nLSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released \nuntil this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock \ninterrupt register (RCC_CIR).\nExternal source (LSE bypass)\nIn this mode, an external clock source must be provided. It must have a frequency up to \n1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the RCC Backup \ndomain control register (RCC_BDCR). The external clock signal (square, sinus or triangle) \nwith ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be \nleft HI-Z. See Figure 22.\n7.2.5 \nLSI clock\nThe LSI RC acts as an low-power clock source that can be kept running in Stop and \nStandby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The \nclock frequency is around 32 kHz. For more details, refer to the electrical characteristics \nsection of the datasheets.\nThe LSI RC can be switched on and off using the LSION bit in the RCC clock control & \nstatus register (RCC_CSR).\nThe LSIRDY flag in the RCC clock control & status register (RCC_CSR) indicates if the low-\nspeed internal oscillator is stable or not. At startup, the clock is not released until this bit is \nset by hardware. An interrupt can be generated if enabled in the RCC clock interrupt register \n(RCC_CIR).\n7.2.6 \nSystem clock (SYSCLK) selection\nAfter a system reset, the HSI oscillator is selected as the system clock. When a clock source \nis used directly or through PLL as the system clock, it is not possible to stop it.\nA switch from one clock source to another occurs only if the target clock source is ready \n(clock stable after startup delay or PLL locked). If a clock source that is not yet ready is \nselected, the switch occurs when the clock source is ready. Status bits in the RCC clock \ncontrol register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently \nused as the system clock.\n7.2.7 \nClock security system (CSS)\nThe clock security system can be activated by software. In this case, the clock detector is \nenabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.\nIf a failure is detected on the HSE clock, this oscillator is automatically disabled, a clock \nfailure event is sent to the break inputs of advanced-control timers TIM1 and TIM8, and an \ninterrupt is generated to inform the software about the failure (clock security system \ninterrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the \nCortex®-M4 with FPU NMI (non-maskable interrupt) exception vector.\nNote:\nWhen the CSS is enabled, if the HSE clock happens to fail, the CSS generates an interrupt, \nwhich causes the automatic generation of an NMI. The NMI is executed indefinitely unless \nthe CSS interrupt pending bit is cleared. As a consequence, the application has to clear the \nCSS interrupt in the NMI ISR by setting the CSSC bit in the Clock interrupt register \n(RCC_CIR).\n\n\n<>\n\nRM0090 Rev 21\n223/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nIf the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that \nit is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is \ndetected, then the system clock switches to the HSI oscillator and the HSE oscillator is \ndisabled. \nIf the HSE oscillator clock was the clock source of PLL used as the system clock when the \nfailure occurred, PLL is also disabled. In this case, if the PLLI2S was enabled, it is also \ndisabled when the HSE fails. \n7.2.8 \nRTC/AWU clock\nOnce the RTCCLK clock source has been selected, the only possible way of modifying the \nselection is to reset the power domain.\nThe RTCCLK clock source can be either the HSE 1 MHz (HSE divided by a programmable \nprescaler), the LSE or the LSI clock. This is selected by programming the RTCSEL[1:0] bits \nin the RCC Backup domain control register (RCC_BDCR) and the RTCPRE[4:0] bits in RCC \nclock configuration register (RCC_CFGR). This selection cannot be modified without \nresetting the Backup domain.\nIf the LSE is selected as the RTC clock, the RTC operates normally if the backup or the \nsystem supply disappears. If the LSI is selected as the AWU clock, the AWU state is not \nguaranteed if the system supply disappears. If the HSE oscillator divided by a value \nbetween 2 and 31 is used as the RTC clock, the RTC state is not guaranteed if the backup \nor the system supply disappears.\nThe LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. As a \nconsequence:\n•\nIf LSE is selected as the RTC clock:\n–\nThe RTC continues to work even if the VDD supply is switched off, provided the \nVBAT supply is maintained. \n•\nIf LSI is selected as the Auto-wakeup unit (AWU) clock:\n–\nThe AWU state is not guaranteed if the VDD supply is powered off. Refer to \nSection 7.2.5: LSI clock on page 222 for more details on LSI calibration.\n•\nIf the HSE clock is used as the RTC clock:\n–\nThe RTC state is not guaranteed if the VDD supply is powered off or if the internal \nvoltage regulator is powered off (removing power from the 1.2 V domain).\nNote:\nTo read the RTC calendar register when the APB1 clock frequency is less than seven times \nthe RTC clock frequency (fAPB1 < 7xfRTCLCK), the software must read the calendar time and \ndate registers twice. The data are correct if the second read access to RTC_TR gives the \nsame result than the first one. Otherwise a third read access must be performed.\n7.2.9 \nWatchdog clock\nIf the independent watchdog (IWDG) is started by either hardware option or software \naccess, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator \ntemporization, the clock is provided to the IWDG.\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n224/1757\nRM0090 Rev 21\n7.2.10 \nClock-out capability\nTwo microcontroller clock output (MCO) pins are available:\n•\nMCO1\nYou can output four different clock sources onto the MCO1 pin (PA8) using the \nconfigurable prescaler (from 1 to 5):\n–\nHSI clock\n–\nLSE clock\n–\nHSE clock\n–\nPLL clock\nThe desired clock source is selected using the MCO1PRE[2:0] and MCO1[1:0] bits in \nthe RCC clock configuration register (RCC_CFGR).\n•\nMCO2\nYou can output four different clock sources onto the MCO2 pin (PC9) using the \nconfigurable prescaler (from 1 to 5):\n–\nHSE clock\n–\nPLL clock\n–\nSystem clock (SYSCLK)\n–\nPLLI2S clock\nThe desired clock source is selected using the MCO2PRE[2:0] and MCO2 bits in the \nRCC clock configuration register (RCC_CFGR).\nFor the different MCO pins, the corresponding GPIO port has to be programmed in alternate \nfunction mode.\nThe selected clock to output onto MCO must not exceed 100 MHz (the maximum I/O \nspeed).\n7.2.11 \nInternal/external clock measurement using TIM5/TIM11\nIt is possible to indirectly measure the frequencies of all on-board clock source generators \nby means of the input capture of TIM5 channel4 and TIM11 channel1 as shown in Figure 23 \nand Figure 24.\nInternal/external clock measurement using TIM5 channel4\nTIM5 has an input multiplexer which allows choosing whether the input capture is triggered \nby the I/O or by an internal clock. This selection is performed through the TI4_RMP [1:0] bits \nin the TIM5_OR register.\nThe primary purpose of having the LSE connected to the channel4 input capture is to be \nable to precisely measure the HSI (this requires to have the HSI used as the system clock \nsource). The number of HSI clock counts between consecutive edges of the LSE signal \nprovides a measurement of the internal clock period. Taking advantage of the high precision \nof LSE crystals (typically a few tens of ppm) we can determine the internal clock frequency \nwith the same resolution, and trim the source to compensate for manufacturing-process \nand/or temperature- and voltage-related frequency deviations.\nThe HSI oscillator has dedicated, user-accessible calibration bits for this purpose.\n\n\n<>\n\nRM0090 Rev 21\n225/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nThe basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the \nprecision is therefore tightly linked to the ratio between the two clock sources. The greater \nthe ratio, the better the measurement.\nIt is also possible to measure the LSI frequency: this is useful for applications that do not \nhave a crystal. The ultralow-power LSI oscillator has a large manufacturing process \ndeviation: by measuring it versus the HSI clock source, it is possible to determine its \nfrequency with the precision of the HSI. The measured value can be used to have more \naccurate RTC time base timeouts (when LSI is used as the RTC clock source) and/or an \nIWDG timeout with an acceptable accuracy.\nUse the following procedure to measure the LSI frequency:\n1.\nEnable the TIM5 timer and configure channel4 in Input capture mode.\n2. \nSet the TI4_RMP bits in the TIM5_OR register to 0x01 to connect the LSI clock \ninternally to TIM5 channel4 input capture for calibration purposes.\n3. \nMeasure the LSI clock frequency using the TIM5 capture/compare 4 event or interrupt.\n4. \nUse the measured LSI frequency to update the prescaler of the RTC depending on the \ndesired time base and/or to compute the IWDG timeout.\nFigure 23. Frequency measurement with TIM5 in Input capture mode\nInternal/external clock measurement using TIM11 channel1\nTIM11 has an input multiplexer which allows choosing whether the input capture is triggered \nby the I/O or by an internal clock. This selection is performed through TI1_RMP [1:0] bits in \nthe TIM11_OR register. The HSE_RTC clock (HSE divided by a programmable prescaler) is \nconnected to channel 1 input capture to have a rough indication of the external crystal \nfrequency. This requires that the HSI is the system clock source. This can be useful for \ninstance to ensure compliance with the IEC 60730/IEC 61335 standards which require to be \nable to determine harmonic or subharmonic frequencies (–50/+100% deviations). \nFigure 24. Frequency measurement with TIM11 in Input capture mode\nTIM5\nTI4\nTI4_RMP[1:0]\nGPIO\nRTC_WakeUp_IT\nLSE\nLSI\nai17741V2\nTIM11\nTI1\nTI1_RMP[1:0]\nGPIO\nHSE_RTC(1 MHz)\nai18433\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n226/1757\nRM0090 Rev 21\n7.3 \nRCC registers\nRefer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in \nregister descriptions.\n7.3.1 \nRCC clock control register (RCC_CR)\nAddress offset: 0x00\nReset value: 0x0000 XX83 where X is undefined.\nAccess: no wait state, word, half-word and byte access\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPLLI2S\nRDY\nPLLI2S\nON\nPLLRD\nY\nPLLON\nReserved\nCSS \nON\nHSE \nBYP\nHSE\nRDY\nHSE \nON\nr\nrw\nr\nrw\nrw\nrw\nr\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nHSICAL[7:0]\nHSITRIM[4:0]\nRes.\nHSI \nRDY\nHSION\nr\nr\nr\nr\nr\nr\nr\nr\nrw\nrw\nrw\nrw\nrw\nr\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBit 27 PLLI2SRDY: PLLI2S clock ready flag\nSet by hardware to indicate that the PLLI2S is locked.\n0: PLLI2S unlocked\n1: PLLI2S locked\nBit 26 PLLI2SON: PLLI2S enable\nSet and cleared by software to enable PLLI2S.\nCleared by hardware when entering Stop or Standby mode. \n0: PLLI2S OFF\n1: PLLI2S ON\nBit 25 PLLRDY: Main PLL (PLL) clock ready flag\nSet by hardware to indicate that PLL is locked.\n0: PLL unlocked\n1: PLL locked\nBit 24 PLLON: Main PLL (PLL) enable\nSet and cleared by software to enable PLL.\nCleared by hardware when entering Stop or Standby mode. This bit cannot be reset if PLL \nclock is used as the system clock.\n0: PLL OFF\n1: PLL ON\nBits 23:20 Reserved, must be kept at reset value.\nBit 19 CSSON: Clock security system enable\nSet and cleared by software to enable the clock security system. When CSSON is set, the \nclock detector is enabled by hardware when the HSE oscillator is ready, and disabled by \nhardware if an oscillator failure is detected.\n0: Clock security system OFF (Clock detector OFF)\n1: Clock security system ON (Clock detector ON if HSE oscillator is stable, OFF if not)\n\n\n<>\n\nRM0090 Rev 21\n227/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 18 HSEBYP: HSE clock bypass\nSet and cleared by software to bypass the oscillator with an external clock. The external \nclock must be enabled with the HSEON bit, to be used by the device.\nThe HSEBYP bit can be written only if the HSE oscillator is disabled.\n0: HSE oscillator not bypassed\n1: HSE oscillator bypassed with an external clock\nBit 17 HSERDY: HSE clock ready flag\nSet by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is cleared, \nHSERDY goes low after 6 HSE oscillator clock cycles.\n0: HSE oscillator not ready\n1: HSE oscillator ready\nBit 16 HSEON: HSE clock enable\nSet and cleared by software.\nCleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This \nbit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.\n0: HSE oscillator OFF\n1: HSE oscillator ON\nBits 15:8 HSICAL[7:0]: Internal high-speed clock calibration\nThese bits are initialized automatically at startup.\nBits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming\nThese bits provide an additional user-programmable trimming value that is added to the \nHSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature \nthat influence the frequency of the internal HSI RC.\nBit 2 Reserved, must be kept at reset value.\nBit 1 HSIRDY: Internal high-speed clock ready flag\nSet by hardware to indicate that the HSI oscillator is stable. After the HSION bit is cleared, \nHSIRDY goes low after 6 HSI clock cycles.\n0: HSI oscillator not ready\n1: HSI oscillator ready\nBit 0 HSION: Internal high-speed clock enable\nSet and cleared by software.\nSet by hardware to force the HSI oscillator ON when leaving the Stop or Standby mode or in \ncase of a failure of the HSE oscillator used directly or indirectly as the system clock. This bit \ncannot be cleared if the HSI is used directly or indirectly as the system clock.\n0: HSI oscillator OFF\n1: HSI oscillator ON\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n228/1757\nRM0090 Rev 21\n7.3.2 \nRCC PLL configuration register (RCC_PLLCFGR)\nAddress offset: 0x04\nReset value: 0x2400 3010\nAccess: no wait state, word, half-word and byte access.\nThis register is used to configure the PLL clock outputs according to the formulas:\n•\nf(VCO clock) = f(PLL clock input) × (PLLN / PLLM)\n•\nf(PLL general clock output) = f(VCO clock) / PLLP\n•\nf(USB OTG FS, SDIO, RNG clock output) = f(VCO clock) / PLLQ\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPLLQ3\nPLLQ2\nPLLQ1\nPLLQ0\nReserv\ned\nPLLSR\nC\nReserved\nPLLP1\nPLLP0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserv\ned\nPLLN\nPLLM5\nPLLM4\nPLLM3\nPLLM2\nPLLM1\nPLLM0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBits 27:24 PLLQ: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator \nclocks\nSet and cleared by software to control the frequency of USB OTG FS clock, the random \nnumber generator clock and the SDIO clock. These bits should be written only if PLL is \ndisabled.\nCaution: The USB OTG FS requires a 48 MHz clock to work correctly. The SDIO and the \nrandom number generator need a frequency lower than or equal to 48 MHz to work \ncorrectly.\nUSB OTG FS clock frequency = VCO frequency / PLLQ with 2 ≤ PLLQ ≤ 15\n0000: PLLQ = 0, wrong configuration\n0001: PLLQ = 1, wrong configuration\n0010: PLLQ = 2\n0011: PLLQ = 3\n0100: PLLQ = 4\n...\n1111: PLLQ = 15\nBit 23 Reserved, must be kept at reset value.\nBit 22 PLLSRC: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source\nSet and cleared by software to select PLL and PLLI2S clock source. This bit can be written \nonly when PLL and PLLI2S are disabled.\n0: HSI clock selected as PLL and PLLI2S clock entry\n1: HSE oscillator clock selected as PLL and PLLI2S clock entry\nBits 21:18 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n229/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBits 17:16 PLLP: Main PLL (PLL) division factor for main system clock\nSet and cleared by software to control the frequency of the general PLL output clock. These \nbits can be written only if PLL is disabled.\nCaution: The software has to set these bits correctly not to exceed 168 MHz on this domain.\nPLL output clock frequency = VCO frequency / PLLP with PLLP = 2, 4, 6, or 8\n00: PLLP = 2\n01: PLLP = 4\n10: PLLP = 6\n11: PLLP = 8\nBits 14:6 PLLN: Main PLL (PLL) multiplication factor for VCO\nSet and cleared by software to control the multiplication factor of the VCO. These bits can \nbe written only when PLL is disabled. Only half-word and word accesses are allowed to \nwrite these bits.\nCaution: The software has to set these bits correctly to ensure that the VCO output \nfrequency is between 100 and 432 MHz. \nVCO output frequency = VCO input frequency × PLLN with 50 ≤ PLLN ≤ 432\n000000000: PLLN = 0, wrong configuration \n000000001: PLLN = 1, wrong configuration\n...\n000110010: PLLN = 50\n...\n001100011: PLLN = 99\n001100100: PLLN = 100\n... \n110110000: PLLN = 432\n110110001: PLLN = 433, wrong configuration\n... \n111111111: PLLN = 511, wrong configuration \nNote: Multiplication factors ranging from 50 and 99 are possible for VCO input frequency \nhigher than 1 MHz. However care must be taken that the minimum VCO output \nfrequency respects the value specified above. \nBits 5:0 PLLM: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock\nSet and cleared by software to divide the PLL and PLLI2S input clock before the VCO. \nThese bits can be written only when the PLL and PLLI2S are disabled.\nCaution: The software has to set these bits correctly to ensure that the VCO input frequency \nranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit \nPLL jitter. \nVCO input frequency = PLL input clock frequency / PLLM with 2 ≤ PLLM ≤ 63\n000000: PLLM = 0, wrong configuration\n000001: PLLM = 1, wrong configuration\n000010: PLLM = 2\n000011: PLLM = 3\n000100: PLLM = 4\n...\n111110: PLLM = 62\n111111: PLLM = 63\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n230/1757\nRM0090 Rev 21\n7.3.3 \nRCC clock configuration register (RCC_CFGR)\nAddress offset: 0x08\nReset value: 0x0000 0000\nAccess: 0 ≤ wait state ≤ 2, word, half-word and byte access\n1 or 2 wait states inserted only if the access occurs during a clock source switch.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMCO2\nMCO2 PRE[2:0]\nMCO1 PRE[2:0]\nI2SSC\nR\nMCO1\nRTCPRE[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPPRE2[2:0]\nPPRE1[2:0]\nReserved\nHPRE[3:0]\nSWS1\nSWS0\nSW1\nSW0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nr\nr\nrw\nrw\nBits 31:30 MCO2[1:0]: Microcontroller clock output 2\nSet and cleared by software. Clock source selection may generate glitches on MCO2. It is \nhighly recommended to configure these bits only after reset before enabling the external \noscillators and the PLLs.\n00: System clock (SYSCLK) selected\n01: PLLI2S clock selected\n10: HSE oscillator clock selected\n11: PLL clock selected\nBits 27:29 MCO2PRE: MCO2 prescaler\nSet and cleared by software to configure the prescaler of the MCO2. Modification of this \nprescaler may generate glitches on MCO2. It is highly recommended to change this \nprescaler only after reset before enabling the external oscillators and the PLLs.\n0xx: no division\n100: division by 2\n101: division by 3\n110: division by 4\n111: division by 5\nBits 24:26 MCO1PRE: MCO1 prescaler\nSet and cleared by software to configure the prescaler of the MCO1. Modification of this \nprescaler may generate glitches on MCO1. It is highly recommended to change this \nprescaler only after reset before enabling the external oscillators and the PLL.\n0xx: no division\n100: division by 2\n101: division by 3\n110: division by 4\n111: division by 5\nBit 23 I2SSRC: I2S clock selection\nSet and cleared by software. This bit allows to select the I2S clock source between the \nPLLI2S clock and the external clock. It is highly recommended to change this bit only after \nreset and before enabling the I2S module.\n0: PLLI2S clock used as I2S clock source\n1: External clock mapped on the I2S_CKIN pin used as I2S clock source\n\n\n<>\n\nRM0090 Rev 21\n231/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBits 22:21 MCO1: Microcontroller clock output 1\nSet and cleared by software. Clock source selection may generate glitches on MCO1. It is \nhighly recommended to configure these bits only after reset before enabling the external \noscillators and PLL.\n00: HSI clock selected\n01: LSE oscillator selected\n10: HSE oscillator clock selected\n11: PLL clock selected\nBits 20:16 RTCPRE: HSE division factor for RTC clock\nSet and cleared by software to divide the HSE clock input clock to generate a 1 MHz clock \nfor RTC.\nCaution: The software has to set these bits correctly to ensure that the clock supplied to the \nRTC is 1 MHz. These bits must be configured if needed before selecting the RTC \nclock source.\n00000: no clock\n00001: no clock\n00010: HSE/2\n00011: HSE/3\n00100: HSE/4\n...\n11110: HSE/30\n11111: HSE/31\nBits 15:13 PPRE2: APB high-speed prescaler (APB2)\nSet and cleared by software to control APB high-speed clock division factor.\nCaution: The software has to set these bits correctly not to exceed 84 MHz on this domain. \nThe clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after \nPPRE2 write.\n0xx: AHB clock not divided\n100: AHB clock divided by 2\n101: AHB clock divided by 4\n110: AHB clock divided by 8\n111: AHB clock divided by 16\nBits 12:10 PPRE1: APB Low speed prescaler (APB1)\nSet and cleared by software to control APB low-speed clock division factor.\nCaution: The software has to set these bits correctly not to exceed 42 MHz on this domain. \nThe clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after \nPPRE1 write.\n0xx: AHB clock not divided\n100: AHB clock divided by 2\n101: AHB clock divided by 4\n110: AHB clock divided by 8\n111: AHB clock divided by 16\nBits 9:8 Reserved, must be kept at reset value.\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n232/1757\nRM0090 Rev 21\n7.3.4 \nRCC clock interrupt register (RCC_CIR)\nAddress offset: 0x0C\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n \nBits 7:4 HPRE: AHB prescaler\nSet and cleared by software to control AHB clock division factor.\nCaution: The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after \nHPRE write.\nCaution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.\n0xxx: system clock not divided\n1000: system clock divided by 2\n1001: system clock divided by 4\n1010: system clock divided by 8\n1011: system clock divided by 16\n1100: system clock divided by 64\n1101: system clock divided by 128\n1110: system clock divided by 256\n1111: system clock divided by 512\nBits 3:2 SWS: System clock switch status\nSet and cleared by hardware to indicate which clock source is used as the system clock.\n00: HSI oscillator used as the system clock\n01: HSE oscillator used as the system clock\n10: PLL used as the system clock\n11: not applicable\nBits 1:0 SW: System clock switch\nSet and cleared by software to select the system clock source.\nSet by hardware to force the HSI selection when leaving the Stop or Standby mode or in \ncase of failure of the HSE oscillator used directly or indirectly as the system clock.\n00: HSI oscillator selected as system clock\n01: HSE oscillator selected as system clock\n10: PLL selected as system clock\n11: not allowed\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nCSSC\nReserv\ned\nPLLI2S \nRDYC\nPLL \nRDYC\nHSE \nRDYC\nHSI \nRDYC\nLSE \nRDYC\nLSI \nRDYC\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPLLI2S \nRDYIE\nPLL \nRDYIE\nHSE \nRDYIE\nHSI \nRDYIE\nLSE \nRDYIE\nLSI \nRDYIE\nCSSF\nReserv\ned\nPLLI2S\nRDYF\nPLL \nRDYF\nHSE \nRDYF\nHSI \nRDYF\nLSE \nRDYF\nLSI \nRDYF\nrw\nrw\nrw\nrw\nrw\nrw\nr\nr\nr\nr\nr\nr\nr\n\n\n<>\n\nRM0090 Rev 21\n233/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n \nBits 31:24 Reserved, must be kept at reset value.\nBit 23 CSSC: Clock security system interrupt clear\nThis bit is set by software to clear the CSSF flag.\n0: No effect\n1: Clear CSSF flag\nBits 22 Reserved, must be kept at reset value.\nBit 21 PLLI2SRDYC: PLLI2S ready interrupt clear\nThis bit is set by software to clear the PLLI2SRDYF flag.\n0: No effect\n1: PLLI2SRDYF cleared\nBit 20 PLLRDYC: Main PLL(PLL) ready interrupt clear\nThis bit is set by software to clear the PLLRDYF flag.\n0: No effect\n1: PLLRDYF cleared\nBit 19 HSERDYC: HSE ready interrupt clear\nThis bit is set by software to clear the HSERDYF flag.\n0: No effect\n1: HSERDYF cleared\nBit 18 HSIRDYC: HSI ready interrupt clear\nThis bit is set software to clear the HSIRDYF flag.\n0: No effect\n1: HSIRDYF cleared\nBit 17 LSERDYC: LSE ready interrupt clear\nThis bit is set by software to clear the LSERDYF flag.\n0: No effect\n1: LSERDYF cleared\nBit 16 LSIRDYC: LSI ready interrupt clear\nThis bit is set by software to clear the LSIRDYF flag.\n0: No effect\n1: LSIRDYF cleared\nBits 15:12 Reserved, must be kept at reset value.\nBit 13 PLLI2SRDYIE: PLLI2S ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by PLLI2S lock.\n0: PLLI2S lock interrupt disabled\n1: PLLI2S lock interrupt enabled\nBit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by PLL lock.\n0: PLL lock interrupt disabled\n1: PLL lock interrupt enabled\nBit 11 HSERDYIE: HSE ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by the HSE oscillator \nstabilization.\n0: HSE ready interrupt disabled\n1: HSE ready interrupt enabled\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n234/1757\nRM0090 Rev 21\nBit 10 HSIRDYIE: HSI ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by the HSI oscillator \nstabilization.\n0: HSI ready interrupt disabled\n1: HSI ready interrupt enabled\nBit 9 LSERDYIE: LSE ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by the LSE oscillator \nstabilization.\n0: LSE ready interrupt disabled\n1: LSE ready interrupt enabled\nBit 8 LSIRDYIE: LSI ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by LSI oscillator \nstabilization.\n0: LSI ready interrupt disabled\n1: LSI ready interrupt enabled\nBit 7 CSSF: Clock security system interrupt flag\nSet by hardware when a failure is detected in the HSE oscillator.\nCleared by software setting the CSSC bit.\n0: No clock security interrupt caused by HSE clock failure\n1: Clock security interrupt caused by HSE clock failure\nBits 6 Reserved, must be kept at reset value.\nBit 5 PLLI2SRDYF: PLLI2S ready interrupt flag\nSet by hardware when the PLLI2S locks and PLLI2SRDYIE is set.\nCleared by software setting the PLLRI2SDYC bit.\n0: No clock ready interrupt caused by PLLI2S lock\n1: Clock ready interrupt caused by PLLI2S lock\nBit 4 PLLRDYF: Main PLL (PLL) ready interrupt flag\nSet by hardware when PLL locks and PLLRDYIE is set.\nCleared by software setting the PLLRDYC bit.\n0: No clock ready interrupt caused by PLL lock\n1: Clock ready interrupt caused by PLL lock\nBit 3 HSERDYF: HSE ready interrupt flag\nSet by hardware when External High Speed clock becomes stable and HSERDYIE is set.\nCleared by software setting the HSERDYC bit.\n0: No clock ready interrupt caused by the HSE oscillator\n1: Clock ready interrupt caused by the HSE oscillator\n\n\n<>\n\nRM0090 Rev 21\n235/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n7.3.5 \nRCC AHB1 peripheral reset register (RCC_AHB1RSTR)\nAddress offset: 0x10\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \nBit 2 HSIRDYF: HSI ready interrupt flag\nSet by hardware when the Internal High Speed clock becomes stable and HSIRDYIE is \nset.\nCleared by software setting the HSIRDYC bit.\n0: No clock ready interrupt caused by the HSI oscillator\n1: Clock ready interrupt caused by the HSI oscillator\nBit 1 LSERDYF: LSE ready interrupt flag\nSet by hardware when the External Low Speed clock becomes stable and LSERDYIE is \nset.\nCleared by software setting the LSERDYC bit.\n0: No clock ready interrupt caused by the LSE oscillator\n1: Clock ready interrupt caused by the LSE oscillator\nBit 0 LSIRDYF: LSI ready interrupt flag\nSet by hardware when the internal low speed clock becomes stable and LSIRDYIE is set.\nCleared by software setting the LSIRDYC bit.\n0: No clock ready interrupt caused by the LSI oscillator\n1: Clock ready interrupt caused by the LSI oscillator\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nOTGH\nS\nRST\nReserved\nETHMAC\nRST\nReserved\nDMA2\nRST\nDMA1\nRST\nReserved\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCRCR\nST\nReserved\nGPIOI\nRST\nGPIOH\nRST\nGPIOGG\nRST\nGPIOF\nRST\nGPIOE\nRST\nGPIOD\nRST\nGPIOC\nRST\nGPIOB\nRST\nGPIOA\nRST\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBit 29 OTGHSRST: USB OTG HS module reset\nSet and cleared by software.\n0: does not reset the USB OTG HS module\n1: resets the USB OTG HS module\nBits 28:26 Reserved, must be kept at reset value.\nBit 25 ETHMACRST: Ethernet MAC reset\nSet and cleared by software.\n0: does not reset Ethernet MAC\n1: resets Ethernet MAC\nBits 24:23 Reserved, must be kept at reset value.\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n236/1757\nRM0090 Rev 21\nBit 22 DMA2RST: DMA2 reset\nSet and cleared by software.\n0: does not reset DMA2\n1: resets DMA2\nBit 21 DMA1RST: DMA1 reset\nSet and cleared by software.\n0: does not reset DMA1\n1: resets DMA1\nBits 20:13 Reserved, must be kept at reset value.\nBit 12 CRCRST: CRC reset\nSet and cleared by software.\n0: does not reset CRC\n1: resets CRC\nBits 11:9 Reserved, must be kept at reset value.\nBit 8 GPIOIRST: IO port I reset\nSet and cleared by software.\n0: does not reset IO port I\n1: resets IO port I\nBit 7 GPIOHRST: IO port H reset\nSet and cleared by software.\n0: does not reset IO port H\n1: resets IO port H\nBits 6 GPIOGRST: IO port G reset\nSet and cleared by software.\n0: does not reset IO port G\n1: resets IO port G\nBit 5 GPIOFRST: IO port F reset\nSet and cleared by software.\n0: does not reset IO port F\n1: resets IO port F\nBit 4 GPIOERST: IO port E reset\nSet and cleared by software.\n0: does not reset IO port E\n1: resets IO port E\nBit 3 GPIODRST: IO port D reset\nSet and cleared by software.\n0: does not reset IO port D\n1: resets IO port D\n\n\n<>\n\nRM0090 Rev 21\n237/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 2 GPIOCRST: IO port C reset\nSet and cleared by software.\n0: does not reset IO port C\n1: resets IO port C\nBit 1 GPIOBRST: IO port B reset\nSet and cleared by software.\n0: does not reset IO port B\n1:resets IO port B\nBit 0 GPIOARST: IO port A reset\nSet and cleared by software.\n0: does not reset IO port A\n1: resets IO port A\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n238/1757\nRM0090 Rev 21\n7.3.6 \nRCC AHB2 peripheral reset register (RCC_AHB2RSTR)\nAddress offset: 0x14\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOTGFS\nRST\nRNG\nRST\nHASH\nRST\nCRYP\nRST\nReserved\nDCMI\nRST\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBit 7 OTGFSRST: USB OTG FS module reset\nSet and cleared by software.\n0: does not reset the USB OTG FS module\n1: resets the USB OTG FS module\nBit 6 RNGRST: Random number generator module reset\nSet and cleared by software.\n0: does not reset the random number generator module\n1: resets the random number generator module\nBit 5 HASHRST: Hash module reset\nSet and cleared by software.\n0: does not reset the HASH module\n1: resets the HASH module\nBit 4 CRYPRST: Cryptographic module reset\nSet and cleared by software.\n0: does not reset the cryptographic module\n1: resets the cryptographic module\nBits 3:1 Reserved, must be kept at reset value.\nBit 0 DCMIRST: Camera interface reset\nSet and cleared by software.\n0: does not reset the Camera interface\n1: resets the Camera interface \n\n\n<>\n\nRM0090 Rev 21\n239/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n7.3.7 \nRCC AHB3 peripheral reset register (RCC_AHB3RSTR)\nAddress offset: 0x18\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n7.3.8 \nRCC APB1 peripheral reset register (RCC_APB1RSTR)\nAddress offset: 0x20\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFSMCRST\nrw\nBits 31:1 Reserved, must be kept at reset value.\nBit 0 FSMCRST: Flexible static memory controller module reset\nSet and cleared by software.\n0: does not reset the FSMC module\n1: resets the FSMC module\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nDACRST\nPWR\nRST\nReser-\nved\nCAN2\nRST\nCAN1\nRST\nReser-\nved\nI2C3\nRST\nI2C2\nRST\nI2C1\nRST\nUART5 \nRST\nUART4\nRST\nUART3\nRST\nUART2\nRST\nReser-\nved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSPI3\nRST\nSPI2\nRST\nReserved\nWWDG\nRST\nReserved\nTIM14\nRST\nTIM13\nRST\nTIM12\nRST\nTIM7\nRST\nTIM6\nRST\nTIM5\nRST\nTIM4\nRST\nTIM3\nRST\nTIM2\nRST\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBit 29 DACRST: DAC reset\nSet and cleared by software.\n0: does not reset the DAC interface\n1: resets the DAC interface\nBit 28 PWRRST: Power interface reset\nSet and cleared by software.\n0: does not reset the power interface\n1: resets the power interface\nBit 27 Reserved, must be kept at reset value.\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n240/1757\nRM0090 Rev 21\nBit 26 CAN2RST: CAN2 reset\nSet and cleared by software.\n0: does not reset CAN2\n1: resets CAN2\nBit 25 CAN1RST: CAN1 reset\nSet and cleared by software.\n0: does not reset CAN1\n1: resets CAN1\nBit 24 Reserved, must be kept at reset value.\nBit 23 I2C3RST: I2C3 reset\nSet and cleared by software.\n0: does not reset I2C3\n1: resets I2C3\nBit 22 I2C2RST: I2C2 reset\nSet and cleared by software.\n0: does not reset I2C2\n1: resets I2C2\nBit 21 I2C1RST: I2C1 reset\nSet and cleared by software.\n0: does not reset I2C1\n1: resets I2C1\nBit 20 UART5RST: UART5 reset\nSet and cleared by software.\n0: does not reset UART5\n1: resets UART5\nBit 19 UART4RST: USART4 reset\nSet and cleared by software.\n0: does not reset UART4\n1: resets UART4\nBit 18 USART3RST: USART3 reset\nSet and cleared by software.\n0: does not reset USART3\n1: resets USART3\nBit 17 USART2RST: USART2 reset\nSet and cleared by software.\n0: does not reset USART2\n1: resets USART2\nBit 16 Reserved, must be kept at reset value.\nBit 15 SPI3RST: SPI3 reset\nSet and cleared by software.\n0: does not reset SPI3\n1: resets SPI3\nBit 14 SPI2RST: SPI2 reset\nSet and cleared by software.\n0: does not reset SPI2\n1: resets SPI2\n\n\n<>\n\nRM0090 Rev 21\n241/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBits 13:12 Reserved, must be kept at reset value.\nBit 11 WWDGRST: Window watchdog reset\nSet and cleared by software.\n0: does not reset the window watchdog\n1: resets the window watchdog\nBits 10:9 Reserved, must be kept at reset value.\nBit 8 TIM14RST: TIM14 reset\nSet and cleared by software.\n0: does not reset TIM14\n1: resets TIM14\nBit 7 TIM13RST: TIM13 reset\nSet and cleared by software.\n0: does not reset TIM13\n1: resets TIM13\nBit 6 TIM12RST: TIM12 reset\nSet and cleared by software.\n0: does not reset TIM12\n1: resets TIM12\nBit 5 TIM7RST: TIM7 reset\nSet and cleared by software.\n0: does not reset TIM7\n1: resets TIM7\nBit 4 TIM6RST: TIM6 reset\nSet and cleared by software.\n0: does not reset TIM6\n1: resets TIM6\nBit 3 TIM5RST: TIM5 reset\nSet and cleared by software.\n0: does not reset TIM5\n1: resets TIM5\nBit 2 TIM4RST: TIM4 reset\nSet and cleared by software.\n0: does not reset TIM4\n1: resets TIM4\nBit 1 TIM3RST: TIM3 reset\nSet and cleared by software.\n0: does not reset TIM3\n1: resets TIM3\nBit 0 TIM2RST: TIM2 reset\nSet and cleared by software.\n0: does not reset TIM2\n1: resets TIM2\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n242/1757\nRM0090 Rev 21\n7.3.9 \nRCC APB2 peripheral reset register (RCC_APB2RSTR)\nAddress offset: 0x24\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTIM11\nRST\nTIM10\nRST\nTIM9\nRST\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReser-\nved\nSYSCF\nG RST\nReser-\nved\nSPI1\nRST\nSDIO\nRST\nReserved\nADC\nRST\nReserved\nUSART\n6\nRST\nUSART\n1\nRST\nReserved\nTIM8\nRST\nTIM1\nRST\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:19 Reserved, must be kept at reset value.\nBit 18 TIM11RST: TIM11 reset\nSet and cleared by software.\n0: does not reset TIM11\n1: resets TIM14\nBit 17 TIM10RST: TIM10 reset\nSet and cleared by software.\n0: does not reset TIM10\n1: resets TIM10\nBit 16 TIM9RST: TIM9 reset\nSet and cleared by software.\n0: does not reset TIM9\n1: resets TIM9\nBit 15 Reserved, must be kept at reset value.\nBit 14 SYSCFGRST: System configuration controller reset\nSet and cleared by software.\n0: does not reset the System configuration controller\n1: resets the System configuration controller\nBit 13 Reserved, must be kept at reset value.\nBit 12 SPI1RST: SPI1 reset\nSet and cleared by software.\n0: does not reset SPI1\n1: resets SPI1\nBit 11 SDIORST: SDIO reset\nSet and cleared by software.\n0: does not reset the SDIO module\n1: resets the SDIO module\nBits 10:9 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n243/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 8 ADCRST: ADC interface reset (common to all ADCs)\nSet and cleared by software.\n0: does not reset the ADC interface\n1: resets the ADC interface\nBits 7:6 Reserved, must be kept at reset value.\nBit 5 USART6RST: USART6 reset\nSet and cleared by software.\n0: does not reset USART6\n1: resets USART6\nBit 4\nUSART1RST: USART1 reset\nSet and cleared by software.\n0: does not reset USART1\n1: resets USART1\nBits 3:2 Reserved, must be kept at reset value.\nBit 1 TIM8RST: TIM8 reset\nSet and cleared by software.\n0: does not reset TIM8\n1: resets TIM8\nBit 0 TIM1RST: TIM1 reset\nSet and cleared by software.\n0: does not reset TIM1\n1: resets TIM1\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n244/1757\nRM0090 Rev 21\n7.3.10 \nRCC AHB1 peripheral clock enable register (RCC_AHB1ENR)\nAddress offset: 0x30\nReset value: 0x0010 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReser-\nved\nOTGH\nS \nULPIE\nN\nOTGH\nSEN\nETHM\nACPTP\nEN\nETHM\nACRXE\nN\nETHM\nACTXE\nN\nETHMA\nCEN\nReserved\nDMA2E\nN\nDMA1E\nN\nCCMDAT\nARAMEN\nRes.\nBKPSR\nAMEN\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCRCE\nN\nReserved\nGPIOIE\nN\nGPIOH\nEN\nGPIOG\nEN\nGPIOFE\nN\nGPIOEEN\nGPIOD\nEN\nGPIOC\nEN\nGPIO\nBEN\nGPIO\nAEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBit 30 OTGHSULPIEN: USB OTG HSULPI clock enable\nSet and cleared by software. This bit must be cleared when the OTG_HS is used in FS \nmode.\n0: USB OTG HS ULPI clock disabled\n1: USB OTG HS ULPI clock enabled\nBit 29 OTGHSEN: USB OTG HS clock enable\nSet and cleared by software.\n0: USB OTG HS clock disabled\n1: USB OTG HS clock enabled\nBit 28 ETHMACPTPEN: Ethernet PTP clock enable\nSet and cleared by software.\n0: Ethernet PTP clock disabled\n1: Ethernet PTP clock enabled\nBit 27 ETHMACRXEN: Ethernet Reception clock enable\nSet and cleared by software.\n0: Ethernet Reception clock disabled\n1: Ethernet Reception clock enabled\nBit 26 ETHMACTXEN: Ethernet Transmission clock enable\nSet and cleared by software.\n0: Ethernet Transmission clock disabled\n1: Ethernet Transmission clock enabled\nBit 25 ETHMACEN: Ethernet MAC clock enable\nSet and cleared by software.\n0: Ethernet MAC clock disabled\n1: Ethernet MAC clock enabled\nBits 24:23 Reserved, must be kept at reset value.\nBit 22 DMA2EN: DMA2 clock enable\nSet and cleared by software.\n0: DMA2 clock disabled\n1: DMA2 clock enabled\n\n\n<>\n\nRM0090 Rev 21\n245/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 21 DMA1EN: DMA1 clock enable\nSet and cleared by software.\n0: DMA1 clock disabled\n1: DMA1 clock enabled\nBit 20 CCMDATARAMEN: CCM data RAM clock enable\nSet and cleared by software. \n0: CCM data RAM clock disabled\n1: CCM data RAM clock enabled\nBit 19 Reserved, must be kept at reset value.\nBit 18 BKPSRAMEN: Backup SRAM interface clock enable\nSet and cleared by software.\n0: Backup SRAM interface clock disabled\n1: Backup SRAM interface clock enabled\nBits 17:13 Reserved, must be kept at reset value.\nBit 12 CRCEN: CRC clock enable\nSet and cleared by software.\n0: CRC clock disabled\n1: CRC clock enabled\nBits 11:9 Reserved, must be kept at reset value.\nBit 8 GPIOIEN: IO port I clock enable\nSet and cleared by software.\n0: IO port I clock disabled\n1: IO port I clock enabled\nBit 7 GPIOHEN: IO port H clock enable\nSet and cleared by software.\n0: IO port H clock disabled\n1: IO port H clock enabled\nBit 6 GPIOGEN: IO port G clock enable\nSet and cleared by software.\n0: IO port G clock disabled\n1: IO port G clock enabled\nBit 5 GPIOFEN: IO port F clock enable\nSet and cleared by software.\n0: IO port F clock disabled\n1: IO port F clock enabled\nBit 4 GPIOEEN: IO port E clock enable\nSet and cleared by software.\n0: IO port E clock disabled\n1: IO port E clock enabled\nBit 3 GPIODEN: IO port D clock enable\nSet and cleared by software.\n0: IO port D clock disabled\n1: IO port D clock enabled\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n246/1757\nRM0090 Rev 21\n7.3.11 \nRCC AHB2 peripheral clock enable register (RCC_AHB2ENR)\nAddress offset: 0x34\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \nBit 2 GPIOCEN: IO port C clock enable\nSet and cleared by software.\n0: IO port C clock disabled\n1: IO port C clock enabled\nBit 1 GPIOBEN: IO port B clock enable\nSet and cleared by software.\n0: IO port B clock disabled\n1: IO port B clock enabled\nBit 0 GPIOAEN: IO port A clock enable\nSet and cleared by software.\n0: IO port A clock disabled\n1: IO port A clock enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOTGFS\nEN\nRNG\nEN\nHASH\nEN\nCRYP\nEN\nReserved\nDCMI\nEN\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBit 7 OTGFSEN: USB OTG FS clock enable\nSet and cleared by software.\n0: USB OTG FS clock disabled\n1: USB OTG FS clock enabled\nBit 6 RNGEN: Random number generator clock enable\nSet and cleared by software.\n0: Random number generator clock disabled\n1: Random number generator clock enabled\nBit 5 HASHEN: Hash modules clock enable\nSet and cleared by software.\n0: Hash modules clock disabled\n1: Hash modules clock enabled\n\n\n<>\n\nRM0090 Rev 21\n247/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n7.3.12 \nRCC AHB3 peripheral clock enable register (RCC_AHB3ENR)\nAddress offset: 0x38\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n7.3.13 \nRCC APB1 peripheral clock enable register\n(RCC_APB1ENR)\nAddress offset: 0x40\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \nBit 4 CRYPEN: Cryptographic modules clock enable\nSet and cleared by software.\n0: cryptographic module clock disabled\n1: cryptographic module clock enabled\nBits 3:1 Reserved, must be kept at reset value.\nBit 0 DCMIEN: Camera interface enable\nSet and cleared by software.\n0: Camera interface clock disabled\n1: Camera interface clock enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFSMCEN\nrw\nBits 31:1 Reserved, must be kept at reset value.\nBit 0 FSMCEN: Flexible static memory controller module clock enable\nSet and cleared by software.\n0: FSMC module clock disabled\n1: FSMC module clock enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nDAC\nEN\nPWR\nEN\nReser-\nved\nCAN2\nEN\nCAN1\nEN\nReser-\nved\nI2C3\nEN\nI2C2\nEN\nI2C1\nEN\nUART5\nEN\nUART4\nEN\nUSART\n3\nEN\nUSART\n2\nEN\nReser-\nved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSPI3\nEN\nSPI2\nEN\nReserved\nWWDG\nEN\nReserved\nTIM14\nEN\nTIM13\nEN\nTIM12\nEN\nTIM7\nEN\nTIM6 \nEN\nTIM5\nEN\nTIM4\nEN\nTIM3\nEN\nTIM2\nEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n248/1757\nRM0090 Rev 21\n \nBits 31:30 Reserved, must be kept at reset value.\nBit 29 DACEN: DAC interface clock enable\nSet and cleared by software.\n0: DAC interface clock disabled\n1: DAC interface clock enable\nBit 28 PWREN: Power interface clock enable\nSet and cleared by software.\n0: Power interface clock disabled\n1: Power interface clock enable\nBit 27 Reserved, must be kept at reset value.\nBit 26 CAN2EN: CAN 2 clock enable\nSet and cleared by software.\n0: CAN 2 clock disabled\n1: CAN 2 clock enabled\nBit 25 CAN1EN: CAN 1 clock enable\nSet and cleared by software.\n0: CAN 1 clock disabled\n1: CAN 1 clock enabled\nBit 24 Reserved, must be kept at reset value.\nBit 23 I2C3EN: I2C3 clock enable\nSet and cleared by software.\n0: I2C3 clock disabled\n1: I2C3 clock enabled\nBit 22 I2C2EN: I2C2 clock enable\nSet and cleared by software.\n0: I2C2 clock disabled\n1: I2C2 clock enabled\nBit 21 I2C1EN: I2C1 clock enable\nSet and cleared by software.\n0: I2C1 clock disabled\n1: I2C1 clock enabled\nBit 20 UART5EN: UART5 clock enable\nSet and cleared by software.\n0: UART5 clock disabled\n1: UART5 clock enabled\nBit 19 UART4EN: UART4 clock enable\nSet and cleared by software.\n0: UART4 clock disabled\n1: UART4 clock enabled\nBit 18 USART3EN: USART3 clock enable\nSet and cleared by software.\n0: USART3 clock disabled\n1: USART3 clock enabled\n\n\n<>\n\nRM0090 Rev 21\n249/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 17 USART2EN: USART2 clock enable\nSet and cleared by software.\n0: USART2 clock disabled\n1: USART2 clock enabled\nBit 16 Reserved, must be kept at reset value.\nBit 15 SPI3EN: SPI3 clock enable\nSet and cleared by software.\n0: SPI3 clock disabled\n1: SPI3 clock enabled\nBit 14 SPI2EN: SPI2 clock enable\nSet and cleared by software.\n0: SPI2 clock disabled\n1: SPI2 clock enabled\nBits 13:12 Reserved, must be kept at reset value.\nBit 11 WWDGEN: Window watchdog clock enable\nSet and cleared by software.\n0: Window watchdog clock disabled\n1: Window watchdog clock enabled\nBits 10:9 Reserved, must be kept at reset value.\nBit 8 TIM14EN: TIM14 clock enable\nSet and cleared by software.\n0: TIM14 clock disabled\n1: TIM14 clock enabled\nBit 7 TIM13EN: TIM13 clock enable\nSet and cleared by software.\n0: TIM13 clock disabled\n1: TIM13 clock enabled\nBit 6 TIM12EN: TIM12 clock enable\nSet and cleared by software.\n0: TIM12 clock disabled\n1: TIM12 clock enabled\nBit 5 TIM7EN: TIM7 clock enable\nSet and cleared by software.\n0: TIM7 clock disabled\n1: TIM7 clock enabled\nBit 4 TIM6EN: TIM6 clock enable\nSet and cleared by software.\n0: TIM6 clock disabled\n1: TIM6 clock enabled\nBit 3 TIM5EN: TIM5 clock enable\nSet and cleared by software.\n0: TIM5 clock disabled\n1: TIM5 clock enabled\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n250/1757\nRM0090 Rev 21\n \n7.3.14 \nRCC APB2 peripheral clock enable register (RCC_APB2ENR)\nAddress offset: 0x44\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \nBit 2 TIM4EN: TIM4 clock enable\nSet and cleared by software.\n0: TIM4 clock disabled\n1: TIM4 clock enabled\nBit 1 TIM3EN: TIM3 clock enable\nSet and cleared by software.\n0: TIM3 clock disabled\n1: TIM3 clock enabled\nBit 0 TIM2EN: TIM2 clock enable\nSet and cleared by software.\n0: TIM2 clock disabled\n1: TIM2 clock enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTIM11\nEN\nTIM10\nEN\nTIM9\nEN\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReser-\nved\nSYSCF\nG EN\nReser-\nved\nSPI1\nEN\nSDIO\nEN\nADC3\nEN\nADC2\nEN\nADC1\nEN\nReserved\nUSART\n6\nEN\nUSART\n1\nEN\nReserved\nTIM8\nEN\nTIM1\nEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:19 Reserved, must be kept at reset value.\nBit 18 TIM11EN: TIM11 clock enable\nSet and cleared by software.\n0: TIM11 clock disabled\n1: TIM11 clock enabled\nBit 17 TIM10EN: TIM10 clock enable\nSet and cleared by software.\n0: TIM10 clock disabled\n1: TIM10 clock enabled\nBit 16 TIM9EN: TIM9 clock enable\nSet and cleared by software.\n0: TIM9 clock disabled\n1: TIM9 clock enabled\nBit 15 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n251/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 14 SYSCFGEN: System configuration controller clock enable\nSet and cleared by software.\n0: System configuration controller clock disabled\n1: System configuration controller clock enabled\nBit 13 Reserved, must be kept at reset value.\nBit 12 SPI1EN: SPI1 clock enable\nSet and cleared by software.\n0: SPI1 clock disabled\n1: SPI1 clock enabled\nBit 11 SDIOEN: SDIO clock enable\nSet and cleared by software.\n0: SDIO module clock disabled\n1: SDIO module clock enabled\nBit 10 ADC3EN: ADC3 clock enable\nSet and cleared by software.\n0: ADC3 clock disabled\n1: ADC3 clock disabled\nBit 9\nADC2EN: ADC2 clock enable\nSet and cleared by software.\n0: ADC2 clock disabled\n1: ADC2 clock disabled\nBit 8\nADC1EN: ADC1 clock enable\nSet and cleared by software.\n0: ADC1 clock disabled\n1: ADC1 clock disabled\nBits 7:6 Reserved, must be kept at reset value.\nBit 5 USART6EN: USART6 clock enable\nSet and cleared by software.\n0: USART6 clock disabled\n1: USART6 clock enabled\nBit 4 USART1EN: USART1 clock enable\nSet and cleared by software.\n0: USART1 clock disabled\n1: USART1 clock enabled\nBits 3:2 Reserved, must be kept at reset value.\nBit 1 TIM8EN: TIM8 clock enable\nSet and cleared by software.\n0: TIM8 clock disabled\n1: TIM8 clock enabled\nBit 0 TIM1EN: TIM1 clock enable\nSet and cleared by software.\n0: TIM1 clock disabled\n1: TIM1 clock enabled\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n252/1757\nRM0090 Rev 21\n7.3.15 \nRCC AHB1 peripheral clock enable in low power mode register\n(RCC_AHB1LPENR)\nAddress offset: 0x50\nReset value: 0x7E67 91FF\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReser\n-ved\nOTGHS\nULPILPE\nN\nOTGH\nS\nLPEN\nETHPT\nP\nLPEN\nETHRX\nLPEN\nETHTX\nLPEN\nETHMA\nC\nLPEN\nReserved\nDMA2\nLPEN\nDMA1\nLPEN\nReserved\nBKPSRA\nM\nLPEN\nSRAM\n2\nLPEN\nSRAM\n1\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFLITF\nLPEN\nReserved\nCRC\nLPEN\nReserved\nGPIOI\nLPEN\nGPIOH\nLPEN\nGPIOG\nG\nLPEN\nGPIO\nF\nLPEN\nGPIOE\nLPEN\nGPIOD\nLPEN\nGPIOC\nLPEN\nGPIOB\nLPEN\nGPIOA\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBit 30 OTGHSULPILPEN: USB OTG HS ULPI clock enable during Sleep mode\nSet and cleared by software. This bit must be cleared when the OTG_HS is used in FS \nmode.\n0: USB OTG HS ULPI clock disabled during Sleep mode\n1: USB OTG HS ULPI clock enabled during Sleep mode\nBit 29 OTGHSLPEN: USB OTG HS clock enable during Sleep mode\nSet and cleared by software.\n0: USB OTG HS clock disabled during Sleep mode\n1: USB OTG HS clock enabled during Sleep mode\nBit 28 ETHMACPTPLPEN: Ethernet PTP clock enable during Sleep mode\nSet and cleared by software.\n0: Ethernet PTP clock disabled during Sleep mode\n1: Ethernet PTP clock enabled during Sleep mode\nBit 27 ETHMACRXLPEN: Ethernet reception clock enable during Sleep mode\nSet and cleared by software.\n0: Ethernet reception clock disabled during Sleep mode\n1: Ethernet reception clock enabled during Sleep mode\nBit 26 ETHMACTXLPEN: Ethernet transmission clock enable during Sleep mode\nSet and cleared by software.\n0: Ethernet transmission clock disabled during sleep mode\n1: Ethernet transmission clock enabled during sleep mode\nBit 25 ETHMACLPEN: Ethernet MAC clock enable during Sleep mode\nSet and cleared by software.\n0: Ethernet MAC clock disabled during Sleep mode\n1: Ethernet MAC clock enabled during Sleep mode\nBits 24:23 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n253/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 22 DMA2LPEN: DMA2 clock enable during Sleep mode\nSet and cleared by software.\n0: DMA2 clock disabled during Sleep mode\n1: DMA2 clock enabled during Sleep mode\nBit 21 DMA1LPEN: DMA1 clock enable during Sleep mode\nSet and cleared by software.\n0: DMA1 clock disabled during Sleep mode\n1: DMA1 clock enabled during Sleep mode\nBits 20:19 Reserved, must be kept at reset value.\nBit 18 BKPSRAMLPEN: Backup SRAM interface clock enable during Sleep mode\nSet and cleared by software.\n0: Backup SRAM interface clock disabled during Sleep mode\n1: Backup SRAM interface clock enabled during Sleep mode\nBit 17 SRAM2LPEN: SRAM 2 interface clock enable during Sleep mode\nSet and cleared by software.\n0: SRAM 2 interface clock disabled during Sleep mode\n1: SRAM 2 interface clock enabled during Sleep mode\nBit 16 SRAM1LPEN: SRAM 1interface clock enable during Sleep mode\nSet and cleared by software.\n0: SRAM 1 interface clock disabled during Sleep mode\n1: SRAM 1 interface clock enabled during Sleep mode\nBit 15 FLITFLPEN: Flash interface clock enable during Sleep mode\nSet and cleared by software.\n0: Flash interface clock disabled during Sleep mode\n1: Flash interface clock enabled during Sleep mode\nBits 14:13 Reserved, must be kept at reset value.\nBit 12 CRCLPEN: CRC clock enable during Sleep mode\nSet and cleared by software.\n0: CRC clock disabled during Sleep mode\n1: CRC clock enabled during Sleep mode\nBits 11:9 Reserved, must be kept at reset value.\nBit 8 GPIOILPEN: IO port I clock enable during Sleep mode\nSet and cleared by software.\n0: IO port I clock disabled during Sleep mode\n1: IO port I clock enabled during Sleep mode\nBit 7\nGPIOHLPEN: IO port H clock enable during Sleep mode\nSet and cleared by software.\n0: IO port H clock disabled during Sleep mode\n1: IO port H clock enabled during Sleep mode\nBits 6 GPIOGLPEN: IO port G clock enable during Sleep mode\nSet and cleared by software.\n0: IO port G clock disabled during Sleep mode\n1: IO port G clock enabled during Sleep mode\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n254/1757\nRM0090 Rev 21\n7.3.16 \nRCC AHB2 peripheral clock enable in low power mode register\n(RCC_AHB2LPENR)\nAddress offset: 0x54\nReset value: 0x0000 00F1\nAccess: no wait state, word, half-word and byte access.\n \nBit 5 GPIOFLPEN: IO port F clock enable during Sleep mode\nSet and cleared by software.\n0: IO port F clock disabled during Sleep mode\n1: IO port F clock enabled during Sleep mode\nBit 4 GPIOELPEN: IO port E clock enable during Sleep mode\nSet and cleared by software.\n0: IO port E clock disabled during Sleep mode\n1: IO port E clock enabled during Sleep mode\nBit 3 GPIODLPEN: IO port D clock enable during Sleep mode\nSet and cleared by software.\n0: IO port D clock disabled during Sleep mode\n1: IO port D clock enabled during Sleep mode\nBit 2 GPIOCLPEN: IO port C clock enable during Sleep mode\nSet and cleared by software.\n0: IO port C clock disabled during Sleep mode\n1: IO port C clock enabled during Sleep mode\nBit 1 GPIOBLPEN: IO port B clock enable during Sleep mode\nSet and cleared by software.\n0: IO port B clock disabled during Sleep mode\n1: IO port B clock enabled during Sleep mode\nBit 0 GPIOALPEN: IO port A clock enable during sleep mode\nSet and cleared by software.\n0: IO port A clock disabled during Sleep mode\n1: IO port A clock enabled during Sleep mode\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOTGFS\nLPEN\nRNG\nLPEN\nHASH\nLPEN\nCRYP\nLPEN\nReserved\nDCMI\nLPEN\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n255/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n \n7.3.17 \nRCC AHB3 peripheral clock enable in low power mode register\n(RCC_AHB3LPENR)\nAddress offset: 0x58\nReset value: 0x0000 0001\nAccess: no wait state, word, half-word and byte access.\n \n \nBits 31:8 Reserved, must be kept at reset value.\nBit 7 OTGFSLPEN: USB OTG FS clock enable during Sleep mode\nSet and cleared by software.\n0: USB OTG FS clock disabled during Sleep mode\n1: USB OTG FS clock enabled during Sleep mode\nBit 6 RNGLPEN: Random number generator clock enable during Sleep mode\nSet and cleared by software.\n0: Random number generator clock disabled during Sleep mode\n1: Random number generator clock enabled during Sleep mode\nBit 5 HASHLPEN: Hash modules clock enable during Sleep mode\nSet and cleared by software.\n0: Hash modules clock disabled during Sleep mode\n1: Hash modules clock enabled during Sleep mode\nBit 4 CRYPLPEN: Cryptography modules clock enable during Sleep mode\nSet and cleared by software.\n0: cryptography modules clock disabled during Sleep mode\n1: cryptography modules clock enabled during Sleep mode\nBits 3:1 Reserved, must be kept at reset value.\nBit 0 DCMILPEN: Camera interface enable during Sleep mode\nSet and cleared by software.\n0: Camera interface clock disabled during Sleep mode\n1: Camera interface clock enabled during Sleep mode\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFSMC\nLPEN\nrw\nBits 31:1Reserved, must be kept at reset value.\nBit 0\nFSMCLPEN: Flexible static memory controller module clock enable during Sleep mode\nSet and cleared by software.\n0: FSMC module clock disabled during Sleep mode\n1: FSMC module clock enabled during Sleep mode\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n256/1757\nRM0090 Rev 21\n7.3.18 \nRCC APB1 peripheral clock enable in low power mode register\n(RCC_APB1LPENR)\nAddress offset: 0x60\nReset value: 0x36FE C9FF\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nDAC\nLPEN\nPWR\nLPEN\nRESER\nVED\nCAN2\nLPEN\nCAN1\nLPEN\nReser-\nved\nI2C3\nLPEN\nI2C2\nLPEN\nI2C1\nLPEN\nUART5\nLPEN\nUART4\nLPEN\nUSART\n3\nLPEN\nUSART\n2\nLPEN\nReser-\nved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSPI3\nLPEN\nSPI2\nLPEN\nReserved\nWWDG\nLPEN\nReserved\nTIM14\nLPEN\nTIM13\nLPEN\nTIM12\nLPEN\nTIM7\nLPEN\nTIM6 \nLPEN\nTIM5\nLPEN\nTIM4\nLPEN\nTIM3\nLPEN\nTIM2\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBit 29 DACLPEN: DAC interface clock enable during Sleep mode\nSet and cleared by software.\n0: DAC interface clock disabled during Sleep mode\n1: DAC interface clock enabled during Sleep mode\nBit 28 PWRLPEN: Power interface clock enable during Sleep mode\nSet and cleared by software.\n0: Power interface clock disabled during Sleep mode\n1: Power interface clock enabled during Sleep mode\nBit 27 Reserved, must be kept at reset value.\nBit 26 CAN2LPEN: CAN 2 clock enable during Sleep mode\nSet and cleared by software.\n0: CAN 2 clock disabled during sleep mode\n1: CAN 2 clock enabled during sleep mode\nBit 25 CAN1LPEN: CAN 1 clock enable during Sleep mode\nSet and cleared by software.\n0: CAN 1 clock disabled during Sleep mode\n1: CAN 1 clock enabled during Sleep mode\nBit 24 Reserved, must be kept at reset value.\nBit 23 I2C3LPEN: I2C3 clock enable during Sleep mode\nSet and cleared by software.\n0: I2C3 clock disabled during Sleep mode\n1: I2C3 clock enabled during Sleep mode\nBit 22 I2C2LPEN: I2C2 clock enable during Sleep mode\nSet and cleared by software.\n0: I2C2 clock disabled during Sleep mode\n1: I2C2 clock enabled during Sleep mode\n\n\n<>\n\nRM0090 Rev 21\n257/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 21 I2C1LPEN: I2C1 clock enable during Sleep mode\nSet and cleared by software.\n0: I2C1 clock disabled during Sleep mode\n1: I2C1 clock enabled during Sleep mode\nBit 20 UART5LPEN: UART5 clock enable during Sleep mode\nSet and cleared by software.\n0: UART5 clock disabled during Sleep mode\n1: UART5 clock enabled during Sleep mode\nBit 19 UART4LPEN: UART4 clock enable during Sleep mode\nSet and cleared by software.\n0: UART4 clock disabled during Sleep mode\n1: UART4 clock enabled during Sleep mode\nBit 18\nUSART3LPEN: USART3 clock enable during Sleep mode\nSet and cleared by software.\n0: USART3 clock disabled during Sleep mode\n1: USART3 clock enabled during Sleep mode\nBit 17 USART2LPEN: USART2 clock enable during Sleep mode\nSet and cleared by software.\n0: USART2 clock disabled during Sleep mode\n1: USART2 clock enabled during Sleep mode\nBit 16 Reserved, must be kept at reset value.\nBit 15 SPI3LPEN: SPI3 clock enable during Sleep mode\nSet and cleared by software.\n0: SPI3 clock disabled during Sleep mode\n1: SPI3 clock enabled during Sleep mode\nBit 14 SPI2LPEN: SPI2 clock enable during Sleep mode\nSet and cleared by software.\n0: SPI2 clock disabled during Sleep mode\n1: SPI2 clock enabled during Sleep mode\nBits 13:12 Reserved, must be kept at reset value.\nBit 11 WWDGLPEN: Window watchdog clock enable during Sleep mode\nSet and cleared by software.\n0: Window watchdog clock disabled during sleep mode\n1: Window watchdog clock enabled during sleep mode\nBits 10:9 Reserved, must be kept at reset value.\nBit 8 TIM14LPEN: TIM14 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM14 clock disabled during Sleep mode\n1: TIM14 clock enabled during Sleep mode\nBit 7 TIM13LPEN: TIM13 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM13 clock disabled during Sleep mode\n1: TIM13 clock enabled during Sleep mode\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n258/1757\nRM0090 Rev 21\nBit 6 TIM12LPEN: TIM12 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM12 clock disabled during Sleep mode\n1: TIM12 clock enabled during Sleep mode\nBit 5 TIM7LPEN: TIM7 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM7 clock disabled during Sleep mode\n1: TIM7 clock enabled during Sleep mode\nBit 4 TIM6LPEN: TIM6 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM6 clock disabled during Sleep mode\n1: TIM6 clock enabled during Sleep mode\nBit 3 TIM5LPEN: TIM5 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM5 clock disabled during Sleep mode\n1: TIM5 clock enabled during Sleep mode\nBit 2 TIM4LPEN: TIM4 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM4 clock disabled during Sleep mode\n1: TIM4 clock enabled during Sleep mode\nBit 1 TIM3LPEN: TIM3 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM3 clock disabled during Sleep mode\n1: TIM3 clock enabled during Sleep mode\nBit 0\nTIM2LPEN: TIM2 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM2 clock disabled during Sleep mode\n1: TIM2 clock enabled during Sleep mode\n\n\n<>\n\nRM0090 Rev 21\n259/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n7.3.19 \nRCC APB2 peripheral clock enabled in low power mode \n register (RCC_APB2LPENR)\nAddress offset: 0x64\nReset value: 0x0007 5F33\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTIM11\nLPEN\nTIM10\nLPEN\nTIM9\nLPEN\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReser-\nved\nSYSC\nFG\nLPEN\nReser-\nved\nSPI1\nLPEN\nSDIO\nLPEN\nADC3\nLPEN\nADC2\nLPEN\nADC1\nLPEN\nReserved\nUSART\n6\nLPEN\nUSART\n1\nLPEN\nReserved\nTIM8\nLPEN\nTIM1\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:19 Reserved, must be kept at reset value.\nBit 18 TIM11LPEN: TIM11 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM11 clock disabled during Sleep mode\n1: TIM11 clock enabled during Sleep mode\nBit 17 TIM10LPEN: TIM10 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM10 clock disabled during Sleep mode\n1: TIM10 clock enabled during Sleep mode\nBit 16 TIM9LPEN: TIM9 clock enable during sleep mode\nSet and cleared by software.\n0: TIM9 clock disabled during Sleep mode\n1: TIM9 clock enabled during Sleep mode\nBit 15 Reserved, must be kept at reset value.\nBit 14 SYSCFGLPEN: System configuration controller clock enable during Sleep mode\nSet and cleared by software.\n0: System configuration controller clock disabled during Sleep mode\n1: System configuration controller clock enabled during Sleep mode\nBit 13 Reserved, must be kept at reset value.\nBit 12 SPI1LPEN: SPI1 clock enable during Sleep mode\nSet and cleared by software.\n0: SPI1 clock disabled during Sleep mode\n1: SPI1 clock enabled during Sleep mode\nBit 11 SDIOLPEN: SDIO clock enable during Sleep mode\nSet and cleared by software.\n0: SDIO module clock disabled during Sleep mode\n1: SDIO module clock enabled during Sleep mode\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n260/1757\nRM0090 Rev 21\nBit 10 ADC3LPEN: ADC 3 clock enable during Sleep mode\nSet and cleared by software.\n0: ADC 3 clock disabled during Sleep mode\n1: ADC 3 clock disabled during Sleep mode\nBit 9 ADC2LPEN: ADC2 clock enable during Sleep mode\nSet and cleared by software.\n0: ADC2 clock disabled during Sleep mode\n1: ADC2 clock disabled during Sleep mode\nBit 8 ADC1LPEN: ADC1 clock enable during Sleep mode\nSet and cleared by software.\n0: ADC1 clock disabled during Sleep mode\n1: ADC1 clock disabled during Sleep mode\nBits 7:6 Reserved, must be kept at reset value.\nBit 5 USART6LPEN: USART6 clock enable during Sleep mode\nSet and cleared by software.\n0: USART6 clock disabled during Sleep mode\n1: USART6 clock enabled during Sleep mode\nBit 4 USART1LPEN: USART1 clock enable during Sleep mode\nSet and cleared by software.\n0: USART1 clock disabled during Sleep mode\n1: USART1 clock enabled during Sleep mode\nBits 3:2 Reserved, must be kept at reset value.\nBit 1 TIM8LPEN: TIM8 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM8 clock disabled during Sleep mode\n1: TIM8 clock enabled during Sleep mode\nBit 0 TIM1LPEN: TIM1 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM1 clock disabled during Sleep mode\n1: TIM1 clock enabled during Sleep mode\n\n\n<>\n\nRM0090 Rev 21\n261/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n7.3.20 \nRCC Backup domain control register (RCC_BDCR)\nAddress offset: 0x70\nReset value: 0x0000 0000, reset by Backup domain reset.\nAccess: 0 ≤ wait state ≤ 3, word, half-word and byte access\nWait states are inserted in case of successive accesses to this register.\nThe LSEON, LSEBYP, RTCSEL and RTCEN bits in the RCC Backup domain control \nregister (RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are \nwrite-protected and the DBP bit in the PWR power control register (PWR_CR) for \nSTM32F405xx/07xx and STM32F415xx/17xx has to be set before these can be modified. \nRefer to Section 7.1.1: System reset on page 215 for further information. These bits are only \nreset after a Backup domain Reset (see Section 7.1.3: Backup domain reset). Any internal \nor external Reset has no effect on these bits.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nBDRST\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRTCEN\nReserved\nRTCSEL[1:0]\nReserved\nLSEBY\nP\nLSERD\nY\nLSEON\nrw\nrw\nrw\nrw\nr\nrw\nBits 31:17 Reserved, must be kept at reset value.\nBit 16 BDRST: Backup domain software reset\nSet and cleared by software.\n0: Reset not activated\n1: Resets the entire Backup domain\nNote: The BKPSRAM is not affected by this reset, the only way of resetting the BKPSRAM is \nthrough the Flash interface when a protection level change from level 1 to level 0 is \nrequested.\nThe backup domain software reset does not take effect until the DBP bit of the \nPWR_CR register is set.\nBit 15 RTCEN: RTC clock enable\nSet and cleared by software.\n0: RTC clock disabled\n1: RTC clock enabled\nBits 14:10 Reserved, must be kept at reset value.\nBits 9:8 RTCSEL[1:0]: RTC clock source selection\nSet by software to select the clock source for the RTC. Once the RTC clock source has been \nselected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit \ncan be used to reset them.\n00: No clock\n01: LSE oscillator clock used as the RTC clock\n10: LSI oscillator clock used as the RTC clock\n11: HSE oscillator clock divided by a programmable prescaler (selection through the \nRTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC \nclock\nBits 7:3 Reserved, must be kept at reset value.\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n262/1757\nRM0090 Rev 21\n7.3.21 \nRCC clock control & status register (RCC_CSR)\nAddress offset: 0x74\nReset value: 0x0E00 0000, reset by system reset, except reset flags by power reset only.\nAccess: 0 ≤ wait state ≤ 3, word, half-word and byte access\nWait states are inserted in case of successive accesses to this register.\n \n \nBit 2 LSEBYP: External low-speed oscillator bypass\nSet and cleared by software to bypass the oscillator. This bit can be written only when the \nLSE clock is disabled.\n0: LSE oscillator not bypassed\n1: LSE oscillator bypassed\nBit 1 LSERDY: External low-speed oscillator ready\nSet and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After \nthe LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock \ncycles.\n0: LSE clock not ready\n1: LSE clock ready\nBit 0 LSEON: External low-speed oscillator enable\nSet and cleared by software.\n0: LSE clock OFF\n1: LSE clock ON\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nLPWR\nRSTF\nWWDG\nRSTF\nIWDG\nRSTF\nSFT\nRSTF\nPOR\nRSTF\nPIN\nRSTF\nBORRS\nTF\nRMVF\nReserved\nr\nr\nr\nr\nr\nr\nr\nrt_w\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLSIRDY\nLSION\nr\nrw\nBit 31 LPWRRSTF: Low-power reset flag\nSet by hardware when a Low-power management reset occurs.\nCleared by writing to the RMVF bit.\n0: No Low-power management reset occurred\n1: Low-power management reset occurred\nFor further information on Low-power management reset, refer to Low-power management \nreset.\nBit 30 WWDGRSTF: Window watchdog reset flag\nSet by hardware when a window watchdog reset occurs.\nCleared by writing to the RMVF bit.\n0: No window watchdog reset occurred\n1: Window watchdog reset occurred\nBit 29 IWDGRSTF: Independent watchdog reset flag\nSet by hardware when an independent watchdog reset from VDD domain occurs.\nCleared by writing to the RMVF bit.\n0: No watchdog reset occurred\n1: Watchdog reset occurred\n\n\n<>\n\nRM0090 Rev 21\n263/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 28 SFTRSTF: Software reset flag\nSet by hardware when a software reset occurs.\nCleared by writing to the RMVF bit.\n0: No software reset occurred\n1: Software reset occurred\nBit 27 PORRSTF: POR/PDR reset flag\nSet by hardware when a POR/PDR reset occurs.\nCleared by writing to the RMVF bit.\n0: No POR/PDR reset occurred\n1: POR/PDR reset occurred\nBit 26 PINRSTF: PIN reset flag\nSet by hardware when a reset from the NRST pin occurs.\nCleared by writing to the RMVF bit.\n0: No reset from NRST pin occurred\n1: Reset from NRST pin occurred\nBit 25 BORRSTF: BOR reset flag\nCleared by software by writing the RMVF bit.\nSet by hardware when a POR/PDR or BOR reset occurs.\n0: No POR/PDR or BOR reset occurred\n1: POR/PDR or BOR reset occurred\nBit 24 RMVF: Remove reset flag\nSet by software to clear the reset flags.\n0: No effect\n1: Clear the reset flags\nBits 23:2 Reserved, must be kept at reset value.\nBit 1 LSIRDY: Internal low-speed oscillator ready\nSet and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable. \nAfter the LSION bit is cleared, LSIRDY goes low after 3 LSI clock cycles.\n0: LSI RC oscillator not ready\n1: LSI RC oscillator ready\nBit 0 LSION: Internal low-speed oscillator enable\nSet and cleared by software.\n0: LSI RC oscillator OFF\n1: LSI RC oscillator ON\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n264/1757\nRM0090 Rev 21\n7.3.22 \nRCC spread spectrum clock generation register (RCC_SSCGR)\nAddress offset: 0x80\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\nThe spread spectrum clock generation is available only for the main PLL.\nThe RCC_SSCGR register must be written either before the main PLL is enabled or after \nthe main PLL disabled.\nNote:\nFor full details about PLL spread spectrum clock generation (SSCG) characteristics, refer to \nthe “Electrical characteristics” section in your device datasheet. \n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nSSCG\nEN\nSPR\nEAD\nSEL\nReserved\nINCSTEP\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nINCSTEP\nMODPER\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 SSCGEN: Spread spectrum modulation enable\nSet and cleared by software.\n0: Spread spectrum modulation DISABLE. (To write after clearing CR[24]=PLLON bit)\n1: Spread spectrum modulation ENABLE. (To write before setting CR[24]=PLLON bit)\nBit 30 SPREADSEL: Spread Select\nSet and cleared by software.\nTo write before to set CR[24]=PLLON bit.\n0: Center spread\n1: Down spread\nBits 29:28 Reserved, must be kept at reset value.\nBits 27:13 INCSTEP: Incrementation step\nSet and cleared by software. To write before setting CR[24]=PLLON bit.\nConfiguration input for modulation profile amplitude.\nBits 12:0 MODPER: Modulation period\nSet and cleared by software. To write before setting CR[24]=PLLON bit.\nConfiguration input for modulation profile period.\n\n\n<>\n\nRM0090 Rev 21\n265/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n7.3.23 \nRCC PLLI2S configuration register (RCC_PLLI2SCFGR)\nAddress offset: 0x84\nReset value: 0x2000 3000\nAccess: no wait state, word, half-word and byte access.\nThis register is used to configure the PLLI2S clock outputs according to the formulas:\n•\nf(VCO clock) = f(PLLI2S clock input) × (PLLI2SN / PLLM)\n•\nf(PLL I2S clock output) = f(VCO clock) / PLLI2SR\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserv\ned\nPLLI2S\nR2\nPLLI2S\nR1\nPLLI2S\nR0\nReserved\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserv\ned\nPLLI2SN\n8\nPLLI2SN\n7\nPLLI2SN\n6\nPLLI2SN\n5\nPLLI2SN\n4\nPLLI2SN\n3\nPLLI2SN\n2\nPLLI2SN\n1\nPLLI2SN\n0\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBits 30:28 PLLI2SR: PLLI2S division factor for I2S clocks\nSet and cleared by software to control the I2S clock frequency. These bits should be written \nonly if the PLLI2S is disabled. The factor must be chosen in accordance with the prescaler \nvalues inside the I2S peripherals, to reach 0.3% error when using standard crystals and 0% \nerror with audio crystals. For more information about I2S clock frequency and precision, \nrefer to Section 28.4.4: Clock generator in the I2S chapter.\nCaution: The I2Ss requires a frequency lower than or equal to 192 MHz to work correctly.\nI2S clock frequency = VCO frequency / PLLR with 2 ≤ PLLR ≤ 7\n000: PLLR = 0, wrong configuration\n001: PLLR = 1, wrong configuration\n010: PLLR = 2\n...\n111: PLLR = 7\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n266/1757\nRM0090 Rev 21\nBits 27:15 Reserved, must be kept at reset value.\nBits 14:6 PLLI2SN: PLLI2S multiplication factor for VCO\nThese bits are set and cleared by software to control the multiplication factor of the VCO. \nThese bits can be written only when PLLI2S is disabled. Only half-word and word accesses \nare allowed to write these bits.\nCaution: The software has to set these bits correctly to ensure that the VCO output \nfrequency is between 100 and 432 MHz. \nVCO output frequency = VCO input frequency × PLLI2SN with 50 ≤ PLLI2SN ≤ 432\n000000000: PLLI2SN = 0, wrong configuration \n000000001: PLLI2SN = 1, wrong configuration\n...\n000110010: PLLI2SN = 50\n...\n001100011: PLLI2SN = 99 \n001100100: PLLI2SN = 100\n001100101: PLLI2SN = 101\n001100110: PLLI2SN = 102\n... \n110110000: PLLI2SN = 432\n110110001: PLLI2SN = 433, wrong configuration\n... \n111111111: PLLI2SN = 511, wrong configuration \nNote: Multiplication factors ranging from 50 and 99 are possible for VCO input frequency \nhigher than 1 MHz. However care must be taken that the minimum VCO output \nfrequency respects the value specified above. \nBits 5:0 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n267/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n7.3.24 \nRCC register map\nTable 35 gives the register map and reset values.\n \nTable 35. RCC register map and reset values \nAddr. \noffset\nRegister \nname\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nRCC_CR\nReserved\nPLL I2SRDY\nPLL I2SON\nPLL RDY\nPLL ON\nReserved\nCSSON\nHSEBYP\nHSERDY\nHSEON\nHSICAL 7\nHSICAL 6\nHSICAL 5\nHSICAL 4\nHSICAL 3\nHSICAL 2\nHSICAL 1\nHSICAL 0\nHSITRIM 4\nHSITRIM 3\nHSITRIM 2\nHSITRIM 1\nHSITRIM 0\nReserved\nHSIRDY\nHSION\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\nX\nX\nX\nX\nX\nX\nX\nX\n1\n0\n0\n0\n0\n0\n1\n1\n0x04\nRCC_\nPLLCFGR\nReserved\nPLLQ 3\nPLLQ 2\nPLLQ 1\nPLLQ 0\nReserved\nPLLSRC\nReserved\nPLLP 1\nPLLP 0\nReserved\nPLLN 8\nPLLN 7\nPLLN 6\nPLLN 5\nPLLN 4\nPLLN 3\nPLLN 2\nPLLN 1\nPLLN 0\nPLLM 5\nPLLM 4\nPLLM 3\nPLLM 2\nPLLM 1\nPLLM 0\nReset value\n0\n1\n0\n0\n0\n0\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0x08\nRCC_CFGR\nMCO2 1\nMCO2 0\nMCO2PRE2\nMCO2PRE1\nMCO2PRE0\nMCO1PRE2\nMCO1PRE1\nMCO1PRE0\nI2SSRC\nMCO1 1\nMCO1 0\nRTCPRE 4\nRTCPRE 3\nRTCPRE 2\nRTCPRE 1\nRTCPRE 0\nPPRE2 2\nPPRE2 1\n PPRE2 0\n PPRE1 2\nPPRE1 1\nPPRE1 0\nReserved\nHPRE 3\nHPRE 2\nHPRE 1\nHPRE 0\nSWS 1\nSWS 0\nSW 1\nSW 0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nRCC_CIR\nReserved\nCSSC\nReserved\nPLLI2SRDYC\nPLLRDYC\nHSERDYC\nHSIRDYC\nLSERDYC\nLSIRDYC\nReserved\nPLLI2SRDYIE\nPLLRDYIE\nHSERDYIE\nHSIRDYIE\nLSERDYIE\nLSIRDYIE\nCSSF\nReserved\nPLLI2SRDYF\nPLLRDYF\nHSERDYF\nHSIRDYF\nLSERDYF\nLSIRDYF\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nRCC_\nAHB1RSTR\nReserved\nOTGHSRST\nReserved\nETHMACRST\nReserved\nDMA2RST\nDMA1RST\nReserved\nCRCRST\nReserved\nGPIOIRST\nGPIOHRST\nGPIOGRST\nGPIOFRST\nGPIOERST\nGPIODRST\nGPIOCRST\nGPIOBRST\nGPIOARST\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nRCC_\nAHB2RSTR\nReserved\nOTGFSRS\nRNGRST\nHSAHRST\nCRYPRST\nReserved\nDCMIRST\nReset value\n0x18\nRCC_\nAHB3RSTR\nReserved\nFSMCRST\nReset value\n0\n0x1C\nReserved\nReserved\n0x20\nRCC_\nAPB1RSTR\nReserved\nDACRST\nPWRRST\nReserved\nCAN2RST\nCAN1RST\nReserved\nI2C3RST\nI2C2RST\nI2C1RST\nUART5RST\nUART4RST\nUART3RST\nUART2RST\nReserved\nSPI3RST\nSPI2RST\nReserved\nWWDGRST\nReserved\nTIM14RST\nTIM13RST\nTIM12RST\nTIM7RST\nTIM6RST\nTIM5RST\nTIM4RST\nTIM3RST\nTIM2RST\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x24\nRCC_\nAPB2RSTR\nReserved\nTIM11RST\nTIM10RST\nTIM9RST\nReserved\nSYSCFGRST\nReserved\nSPI1RST\nSDIORST\nReserved\nADCRST\nReserved\nUSART6RST\nUSART1RST\nReserved\nTIM8RST\nTIM1RST\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nReserved\nReserved\n0x2C\nReserved\nReserved\n0x30\nRCC_\nAHB1ENR\nReserved\nOTGHSULPIEN\nOTGHSEN\nETHMACPTPEN\nETHMACRXEN\nETHMACTXEN\nETHMACEN\nReserved\nDMA2EN\nDMA1EN\nCCMDATARAMEN\nReserved\nBKPSRAMEN\nReserved\nCRCEN\nReserved\nGPIOIEN\nGPIOHEN\nGPIOGEN\nGPIOFEN\nGPIOEEN\nGPIODEN\nGPIOCEN\nGPIOBEN\nGPIOAEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n\n\n<>\n\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n268/1757\nRM0090 Rev 21\n0x34\nRCC_\nAHB2ENR\nReserved\nOTGFSEN\nRNGEN\nHASHEN\nCRYPEN\nReserved\nDCMIEN\nReset value\n0\n0\n0\n0\n0\n0x38\nRCC_\nAHB3ENR\nReserved\nFSMCEN\nReset value\n0\n0x3C\nReserved\nReserved\n0x40\nRCC_\nAPB1ENR\nReserved\nDACEN\nPWREN\nReserved\nCAN2EN\nCAN1EN\nReserved\nI2C3EN\nI2C2EN\nI2C1EN\nUART5EN\nUART4EN\nUSART3EN\nUSART2EN\nReserved\nSPI3EN\nSPI2EN\nReserved\nWWDGEN\nReserved\nTIM14EN\nTIM13EN\nTIM12EN\nTIM7EN\nTIM6EN\nTIM5EN\nTIM4EN\nTIM3EN\nTIM2EN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x44\nRCC_\nAPB2ENR\nReserved\nTIM11EN\nTIM10EN\nTIM9EN\nReserved\nSYSCFGEN\nReserved\nSPI1EN\nSDIOEN\nADC3EN\nADC2EN\nADC1EN\nReserved\nUSART6EN\nUSART1EN\nReserved\nTIM8EN\nTIM1EN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x48\nReserved\nReserved\n0x4C\nReserved\nReserved\n0x50\nRCC_\nAHB1LPENR\nReserved\nOTGHSULPILPEN\nOTGHSLPEN\nETHMACPTPLPEN\nETHMACRXLPEN\nETHMACTXLPEN\nETHMACLPEN\nReserved\nDMA2LPEN\nDMA1LPEN\nReserved\nBKPSRAMLPEN\nSRAM2LPEN\nSRAM1LPEN\nFLITFLPEN\nReserved\nCRCLPEN\nReserved\nGPIOILPEN\nGPIOHLPEN\nGPIOGLPEN\nGPIOFLPEN\nGPIOELPEN\nGPIODLPEN\nGPIOCLPEN\nGPIOBLPEN\nGPIOALPEN\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x54\nRCC_\nAHB2LPENR\nReserved\nOTGFSLPEN\nRNGLPEN\nHASHLPEN\nCRYPLPEN\nReserved\nDCMILPEN\nReset value\n1\n1\n1\n1\n1\n0x58\nRCC_\nAHB3LPENR\nReserved\nFSMCLPEN\nReset value\n1\n0x5C\nReserved\nReserved\n0x60\nRCC_\nAPB1LPENR\nReserved\nDACLPEN\nPWRLPEN\nReserved\nCAN2LPEN\nCAN1LPEN\nReserved\nI2C3LPEN\nI2C2LPEN\nI2C1LPEN\nUART5LPEN\nUART4LPEN\nUSART3LPEN\nUSART2LPEN\nReserved\nSPI3LPEN\nSPI2LPEN\nReserved\nWWDGLPEN\nReserved\nTIM14LPEN\nTIM13LPEN\nTIM12LPEN\nTIM7LPEN\nTIM6LPEN\nTIM5LPEN\nTIM4LPEN\nTIM3LPEN\nTIM2LPEN\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x64\nRCC_\nAPB2LPENR\nReserved\nTIM11LPEN\nTIM10LPEN\nTIM9LPEN\nReserved\nSYSCFGLPEN\nReserved\nSPI1LPEN\nSDIOLPEN\nADC3LPEN\nADC2LPEN\nADC1LPEN\nReserved\nUSART6LPEN\nUSART1LPEN\nReserved\nTIM8LPEN\nTIM1LPEN\nReset value\n1\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x68\nReserved\nReserved\n0x6C\nReserved\nReserved\n0x70\nRCC_BDCR\nReserved\nBDRST\nRTCEN\nReserved\nRTCSEL 1\nRTCSEL 0\nReserved\nLSEBYP\nLSERDY\nLSEON\nReset value\n0\n0\n0\n0\n0\n0\n0\nTable 35. RCC register map and reset values (continued)\nAddr. \noffset\nRegister \nname\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n269/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x74\nRCC_CSR\nLPWRRSTF\nWWDGRSTF\nWDGRSTF\nSFTRSTF\nPORRSTF\nPADRSTF\nBORRSTF\nRMVF\nReserved\nLSIRDY\nLSION\nReset value\n0\n0\n0\n0\n1\n1\n1\n1\n0\n0\n0x78\nReserved\nReserved\n0x7C\nReserved\nReserved\n0x80\nRCC_SSCGR\nSSCGEN\nSPREADSEL\nReserved\nINCSTEP\nMODPER\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x84\nRCC_\nPLLI2SCFGR\nReserved\nPLLI2SRx\nReserved\nPLLI2SNx\nReserved\nReset value\n0\n1\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\nTable 35. RCC register map and reset values (continued)\nAddr. \noffset\nRegister \nname\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nGeneral-purpose I/Os (GPIO)\nRM0090\n270/1757\nRM0090 Rev 21\n8 \nGeneral-purpose I/Os (GPIO)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n8.1 \nGPIO introduction\nEach general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, \nGPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers \n(GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking \nregister (GPIOx_LCKR) and two 32-bit alternate function selection register (GPIOx_AFRH \nand GPIOx_AFRL).\n8.2 \nGPIO main features\n•\nUp to 16 I/Os under control\n•\nOutput states: push-pull or open drain + pull-up/down\n•\nOutput data from output data register (GPIOx_ODR) or peripheral (alternate function \noutput)\n•\nSpeed selection for each I/O\n•\nInput states: floating, pull-up/down, analog\n•\nInput data to input data register (GPIOx_IDR) or peripheral (alternate function input)\n•\nBit set and reset register (GPIOx_BSRR) for bitwise write access to GPIOx_ODR\n•\nLocking mechanism (GPIOx_LCKR) provided to freeze the I/O configuration\n•\nAnalog function\n•\nAlternate function input/output selection registers (at most 16 AFs per I/O)\n•\nFast toggle capable of changing every two clock cycles\n•\nHighly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several \nperipheral functions\n8.3 \nGPIO functional description\nSubject to the specific hardware characteristics of each I/O port listed in the datasheet, each \nport bit of the general-purpose I/O (GPIO) ports can be individually configured by software in \nseveral modes:\n•\nInput floating \n•\nInput pull-up\n•\nInput-pull-down\n•\nAnalog\n•\nOutput open-drain with pull-up or pull-down capability\n•\nOutput push-pull with pull-up or pull-down capability\n•\nAlternate function push-pull with pull-up or pull-down capability\n•\nAlternate function open-drain with pull-up or pull-down capability\n\n\n<>\n\nRM0090 Rev 21\n271/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\nEach I/O port bit is freely programmable, however the I/O port registers have to be \naccessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is \nto allow atomic read/modify accesses to any of the GPIO registers. In this way, there is no \nrisk of an IRQ occurring between the read and the modify access.\nFigure 25 shows the basic structure of a 5 V tolerant I/O port bit. Table 40 gives the possible \nport bit configurations.\nFigure 25. Basic structure of a five-volt tolerant I/O port bit\n1.\nVDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD.\n \nTable 36. Port bit configuration table(1)\nMODER(i)\n[1:0]\nOTYPER(i)\nOSPEEDR(i)\n[B:A]\nPUPDR(i)\n[1:0]\nI/O configuration\n01\n0\nSPEED\n[B:A]\n0\n0\nGP output\nPP\n0\n0\n1\nGP output\nPP + PU\n0\n1\n0\nGP output\nPP + PD\n0\n1\n1\nReserved \n1\n0\n0\nGP output\nOD \n1\n0\n1\nGP output\nOD + PU\n1\n1\n0\nGP output\nOD + PD\n1\n1\n1\nReserved (GP output OD)\nAlternate function output\nAlternate function input\nPush-pull,\nopen-drain or\ndisabled\nOutput data register\nRead/write\nFrom on-chip \nperipheral\nTo on-chip \nperipheral\nOutput\ncontrol\nAnalog\non/off\nPull\nPull\non/off\nI/O pin\nVDD\nVDD\nVSS\nVSS\nTTL Schmitt \n trigger\nVSS\nVDD_FT\n(1)\nProtection\ndiode\nProtection\ndiode\non/off\nInput driver\nOutput driver\ndown\nup\nP-MOS\nN-MOS\nRead\nBit set/reset registers\nWrite\nAnalog\nInput data register\nai15939b\n\n\n<>\n\nGeneral-purpose I/Os (GPIO)\nRM0090\n272/1757\nRM0090 Rev 21\n8.3.1 \nGeneral-purpose I/O (GPIO)\nDuring and just after reset, the alternate functions are not active and the I/O ports are \nconfigured in input floating mode.\nThe debug pins are in AF pull-up/pull-down after reset:\n•\nPA15: JTDI in pull-up\n•\nPA14: JTCK/SWCLK in pull-down\n•\nPA13: JTMS/SWDAT in pull-up\n•\nPB4: NJTRST in pull-up\n•\nPB3: JTDO in floating state\nWhen the pin is configured as output, the value written to the output data register \n(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull \nmode or open-drain mode (only the N-MOS is activated when 0 is output).\nThe input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB1 \nclock cycle.\nAll GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or \nnot depending on the value in the GPIOx_PUPDR register.\n10\n0\nSPEED\n[B:A]\n0\n0\nAF\nPP\n0\n0\n1\nAF\nPP + PU\n0\n1\n0\nAF\nPP + PD\n0\n1\n1\nReserved\n1\n0\n0\nAF\nOD\n1\n0\n1\nAF\nOD + PU\n1\n1\n0\nAF\nOD + PD\n1\n1\n1\nReserved\n00\nx\nx\nx\n0\n0\nInput\nFloating\nx\nx\nx\n0\n1\nInput\nPU\nx\nx\nx\n1\n0\nInput\nPD\nx\nx\nx\n1\n1\nReserved (input floating)\n11\nx\nx\nx\n0\n0\nInput/output\nAnalog\nx\nx\nx\n0\n1\nReserved\nx\nx\nx\n1\n0\nx\nx\nx\n1\n1\n1.\nGP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate \nfunction.\nTable 36. Port bit configuration table(1) (continued)\nMODER(i)\n[1:0]\nOTYPER(i)\nOSPEEDR(i)\n[B:A]\nPUPDR(i)\n[1:0]\nI/O configuration\n\n\n<>\n\nRM0090 Rev 21\n273/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\n8.3.2 \nI/O pin multiplexer and mapping\nThe microcontroller I/O pins are connected to onboard peripherals/modules through a \nmultiplexer that allows only one peripheral’s alternate function (AF) connected to an I/O pin \nat a time. In this way, there can be no conflict between peripherals sharing the same I/O pin.\nEach I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that can \nbe configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) \nregisters:\n•\nAfter reset all I/Os are connected to the system’s alternate function 0 (AF0)\n•\nThe peripherals’ alternate functions are mapped from AF1 to AF13\n•\nCortex®-M4 with FPU EVENTOUT is mapped on AF15\nThis structure is shown in Figure 26 below.\nIn addition to this flexible I/O multiplexing architecture, each peripheral has alternate \nfunctions mapped onto different I/O pins to optimize the number of peripherals available in \nsmaller packages.\nTo use an I/O in a given configuration, proceed as follows:\n•\nSystem function\nConnect the I/O to AF0 and configure it depending on the function used:\n–\nJTAG/SWD, after each device reset these pins are assigned as dedicated pins \nimmediately usable by the debugger host (not controlled by the GPIO controller)\n–\nRTC_REFIN: this pin should be configured in Input floating mode\n–\nMCO1 and MCO2: these pins have to be configured in alternate function mode.\nNote:\nThe user can disable some or all of the JTAG/SWD pins and so release the associated pins \nfor GPIO usage (released pins highlighted in gray in the table).\nFor more details refer to Section 7.2.10: Clock-out capability and Section 6.2.10: Clock-out \ncapability.\n\n\n<>\n\nGeneral-purpose I/Os (GPIO)\nRM0090\n274/1757\nRM0090 Rev 21\n \n•\nGPIO\nConfigure the desired I/O as output or input in the GPIOx_MODER register.\n•\nPeripheral alternate function\nFor the ADC and DAC, configure the desired I/O as analog in the GPIOx_MODER \nregister.\nFor other peripherals:\n–\nConfigure the desired I/O as an alternate function in the GPIOx_MODER register\n–\nSelect the type, pull-up/pull-down and output speed via the GPIOx_OTYPER, \nGPIOx_PUPDR and GPIOx_OSPEEDR registers, respectively\n–\nConnect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register\n•\nEVENTOUT\nConfigure the I/O pin used to output the Cortex®-M4 with FPU EVENTOUT signal by \nconnecting it to AF15\nNote:\nEVENTOUT is not mapped onto the following I/O pins: PC13, PC14, PC15, PH0, PH1 and \nPI8.\nRefer to the “Alternate function mapping” table in the datasheets for the detailed mapping of \nthe system and peripherals’ alternate function I/O pins.\nTable 37. Flexible SWJ-DP pin assignment\nAvailable debug ports\nSWJ I/O pin assigned\nPA13 /\nJTMS/\nSWDIO\nPA14 /\nJTCK/\nSWCLK\nPA15 /\nJTDI\nPB3 / \nJTDO\nPB4/\nNJTRST\nFull SWJ (JTAG-DP + SW-DP) - Reset state\nX\nX\nX\nX\nX\nFull SWJ (JTAG-DP + SW-DP) but without \nNJTRST\nX\nX\nX\nX\nJTAG-DP Disabled and SW-DP Enabled\nX\nX\nJTAG-DP Disabled and SW-DP Disabled\nReleased\n\n\n<>\n\nRM0090 Rev 21\n275/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\nFigure 26. Selecting an alternate function on STM32F405xx/07xx and \nSTM32F415xx/17xx \n1.\nConfigured in FS.\nai17538\nFor pins 0 to 7, the GPIOx_AFRL[31:0] register selects the dedicated alternate function \nAF0 (system)\nAF1 (TIM1/TIM2)\nAF2 (TIM3..5)\nAF3 (TIM8..11)\nAF4 (I2C1..3)\nAF5 (SPI1/SPI2)\nAF6 (SPI3)\nAF7 (USART1..3)\nAF8 (USART4..6)\nAF9 (CAN1/CAN2, TIM12..14)\nAF10 (OTG_FS, OTG_HS)\nAF11 (ETH)\nAF12 (FSMC, SDIO, OTG_HS(1))\nAF13 (DCMI)\nAF14\nAF15 (EVENTOUT)\nPin x (x = 0..7)\nAFRL[31:0]\nFor pins 8 to 15, the GPIOx_AFRH[31:0] register selects the dedicated alternate function \nAF0 (system)\nAF1 (TIM1/TIM2)\nAF2 (TIM3..5)\nAF3 (TIM8..11)\nAF4 (I2C1..3)\nAF5 (SPI1/SPI2)\nAF6 (SPI3)\nAF7 (USART1..3)\nAF8 (USART4..6)\nAF9 (CAN1/CAN2, TIM12..14)\nAF10 (OTG_FS, OTG_HS)\nAF11 (ETH)\nAF12 (FSMC, SDIO, OTG_HS(1))\nAF13 (DCMI)\nAF14\nAF15 (EVENTOUT)\nPin x (x = 8..15)\nAFRH[31:0]\n1\n1\n\n\n<>\n\nGeneral-purpose I/Os (GPIO)\nRM0090\n276/1757\nRM0090 Rev 21\nFigure 27. Selecting an alternate function on STM32F42xxx and STM32F43xxx \n1.\nConfigured in FS.\nMS60208V1\nFor pins 0 to 7, the GPIOx_AFRL[31:0] register selects the dedicated alternate function \nAF0 (system)\nAF1 (TIM1/TIM2)\nAF2 (TIM3..5)\nAF3 (TIM8..11)\nAF4 (I2C1..3)\nAF5 (SPI1/2/3/4/5/6)\nAF6 (SPI2/3/SAI1)\nAF7 (USART1..3)\nAF8 (USART4..8)\nAF9 (CAN1/CAN2, LTDC, TIM12..14)\nAF10 (OTG_FS, OTG_HS)\nAF11 (ETH)\nAF12 (FMC, SDIO, OTG_HS(1))\nAF13 (DCMI)\nAF14 (LTDC)\nAF15 (EVENTOUT)\nPin x (x = 0..7)\nAFRL[31:0]\nFor pins 8 to 15, the GPIOx_AFRH[31:0] register selects the dedicated alternate function \nAF0 (system)\nAF1 (TIM1/TIM2)\nAF2 (TIM3..5)\nAF3 (TIM8..11)\nAF4 (I2C1..3)\nAF5 (SPI1/2/4/5/6)\nAF6 (SPI2/3/SAI1)\nAF7 (USART1..3)\nAF8 (USART4..8)\nAF9 (CAN1/CAN2, TIM12..14)\nAF10 (OTG_FS, OTG_HS)\nAF11 (ETH)\nAF12 (FMC, SDIO, OTG_HS(1))\nAF13 (DCMI)\nAF14 (LTDC)\nAF15 (EVENTOUT)\nPin x (x = 8..15)\nAFRH[31:0]\n1\n1\n\n\n<>\n\nRM0090 Rev 21\n277/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\n8.3.3 \nI/O port control registers\nEach of the GPIOs has four 32-bit memory-mapped control registers (GPIOx_MODER, \nGPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. \nThe GPIOx_MODER register is used to select the I/O direction (input, output, AF, analog). \nThe GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type \n(push-pull or open-drain) and speed (the I/O speed pins are directly connected to the \ncorresponding GPIOx_OSPEEDR register bits whatever the I/O direction). The \nGPIOx_PUPDR register is used to select the pull-up/pull-down whatever the I/O direction.\n8.3.4 \nI/O port data registers\nEach GPIO has two 16-bit memory-mapped data registers: input and output data registers \n(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write \naccessible. The data input through the I/O are stored into the input data register \n(GPIOx_IDR), a read-only register.\nSee Section 8.4.5: GPIO port input data register (GPIOx_IDR) (x = A..I/J/K) and \nSection 8.4.6: GPIO port output data register (GPIOx_ODR) (x = A..I/J/K) for the register \ndescriptions.\n8.3.5 \nI/O data bitwise handling\nThe bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to \nset and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset \nregister has twice the size of GPIOx_ODR.\nTo each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BSRR(i) and \nBSRR(i+SIZE). When written to 1, bit BSRR(i) sets the corresponding ODR(i) bit. When \nwritten to 1, bit BSRR(i+SIZE) resets the ODR(i) corresponding bit.\nWriting any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in \nGPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set \naction takes priority.\nUsing the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a \n“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always \nbe accessed directly. The GPIOx_BSRR register provides a way of performing atomic \nbitwise handling.\nThere is no need for the software to disable interrupts when programming the GPIOx_ODR \nat bit level: it is possible to modify one or more bits in a single atomic AHB1 write access.\n8.3.6 \nGPIO locking mechanism\nIt is possible to freeze the GPIO control registers by applying a specific write sequence to \nthe GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER, \nGPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\nTo write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When \nthe right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used \nto lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must \nbe the same). When the LOCK sequence has been applied to a port bit, the value of the port \nbit can no longer be modified until the next MCU or peripheral reset. Each GPIOx_LCKR bit \n\n\n<>\n\nGeneral-purpose I/Os (GPIO)\nRM0090\n278/1757\nRM0090 Rev 21\nfreezes the corresponding bit in the control registers (GPIOx_MODER, GPIOx_OTYPER, \nGPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH).\nThe LOCK sequence (refer to Section 8.4.8: GPIO port configuration lock register \n(GPIOx_LCKR) (x = A..I/J/K)) can only be performed using a word (32-bit long) access to \nthe GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same \ntime as the [15:0] bits.\nFor more details refer to LCKR register description in Section 8.4.8: GPIO port configuration \nlock register (GPIOx_LCKR) (x = A..I/J/K).\n8.3.7 \nI/O alternate function input/output\nTwo registers are provided to select one out of the sixteen alternate function inputs/outputs \navailable for each I/O. With these registers, you can connect an alternate function to some \nother pin as required by your application.\nThis means that a number of possible peripheral functions are multiplexed on each GPIO \nusing the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can \nthus select any one of the possible functions for each I/O. The AF selection signal being \ncommon to the alternate function input and alternate function output, a single channel is \nselected for the alternate function input/output of one I/O.\nTo know which functions are multiplexed on each GPIO pin, refer to the datasheets.\nNote:\nThe application is allowed to select one of the possible peripheral functions for each I/O at a \ntime.\n8.3.8 \nExternal interrupt/wake-up lines\nAll ports have external interrupt capability. To use external interrupt lines, the port must be \nconfigured in input mode, refer to Section 12.2: External interrupt/event controller (EXTI) \nand Section 12.2.3: Wake-up event management.\n8.3.9 \nInput configuration\nWhen the I/O port is programmed as Input:\n•\nthe output buffer is disabled\n•\nthe Schmitt trigger input is activated\n•\nthe pull-up and pull-down resistors are activated depending on the value in the \nGPIOx_PUPDR register\n•\nThe data present on the I/O pin are sampled into the input data register every AHB1 \nclock cycle\n•\nA read access to the input data register provides the I/O State\nFigure 28 shows the input configuration of the I/O port bit.\n\n\n<>\n\nRM0090 Rev 21\n279/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\nFigure 28. Input floating/pull up/pull down configurations\n8.3.10 \nOutput configuration\nWhen the I/O port is programmed as output:\n•\nThe output buffer is enabled:\n–\nOpen drain mode: A “0” in the Output register activates the N-MOS whereas a “1” \nin the Output register leaves the port in Hi-Z (the P-MOS is never activated)\n–\nPush-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in \nthe Output register activates the P-MOS\n•\nThe Schmitt trigger input is activated\n•\nThe weak pull-up and pull-down resistors are activated or not depending on the value \nin the GPIOx_PUPDR register\n•\nThe data present on the I/O pin are sampled into the input data register every AHB1 \nclock cycle\n•\nA read access to the input data register gets the I/O state\n•\nA read access to the output data register gets the last written value\nFigure 29 shows the output configuration of the I/O port bit.\non/off\npull\npull\non/off\nI/O pin\nVDD\nVSS\nTTL Schmitt \n trigger\nVSS\nVDD\nprotection\ndiode\nprotection\ndiode\non\ninput driver\noutput driver\ndown\nup\nInput data register\nOutput data register\nRead/write\nRead\nBit set/reset registers\nWrite\nai15940b\n\n\n<>\n\nGeneral-purpose I/Os (GPIO)\nRM0090\n280/1757\nRM0090 Rev 21\nFigure 29. Output configuration\n8.3.11 \nAlternate function configuration\nWhen the I/O port is programmed as alternate function:\n•\nThe output buffer can be configured as open-drain or push-pull\n•\nThe output buffer is driven by the signal coming from the peripheral (transmitter enable \nand data)\n•\nThe Schmitt trigger input is activated\n•\nThe weak pull-up and pull-down resistors are activated or not depending on the value \nin the GPIOx_PUPDR register\n•\nThe data present on the I/O pin are sampled into the input data register every AHB1 \nclock cycle\n•\nA read access to the input data register gets the I/O state\nFigure 30 shows the Alternate function configuration of the I/O port bit.\nFigure 30. Alternate function configuration\nPush-pull or\nOpen-drain\nOutput\ncontrol\nVDD\nVSS\nTTL Schmitt \n trigger\non\nInput driver\nOutput driver\nP-MOS\nN-MOS\nInput data register\nOutput data register\nRead/write\nRead\nBit set/reset registers\nWrite\non/off\npull\npull\non/off\nVDD\nVSS\nVSS\nVDD\nprotection\ndiode\nprotection\ndiode\ndown\nup\nI/O pin\nai15941b\nAlternate function output\nAlternate function input\npush-pull or\nopen-drain\nFrom on-chip \nperipheral\nTo on-chip \nperipheral\nOutput\ncontrol\nVDD\nVSS\nTTL Schmitt \n trigger\non\nInput driver\nOutput driver\nP-MOS\nN-MOS\nInput data register\nOutput data register\nRead/write\nRead\nBit set/reset registers\nWrite\non/off\non/off\nVDD\nVSS\nVSS\nVDD\nprotection\ndiode\nprotection\ndiode\nPull\nPull\nI/O pin\ndown\nup\nai15942b\n\n\n<>\n\nRM0090 Rev 21\n281/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\n8.3.12 \nAnalog configuration\nWhen the I/O port is programmed as analog configuration:\n•\nThe output buffer is disabled\n•\nThe Schmitt trigger input is deactivated, providing zero consumption for every analog \nvalue of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).\n•\nThe weak pull-up and pull-down resistors are disabled\n•\nRead access to the input data register gets the value “0”\nNote:\nIn the analog configuration, the I/O pins cannot be 5 Volt tolerant.\nFigure 31 shows the high-impedance, analog-input configuration of the I/O port bit.\nFigure 31. High impedance-analog configuration\n8.3.13 \nUsing the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15\nport pins\nThe LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose \nPC14 and PC15 I/Os, respectively, when the LSE oscillator is off. The PC14 and PC15 I/Os \nare only configured as LSE oscillator pins OSC32_IN and OSC32_OUT when the LSE \noscillator is ON. This is done by setting the LSEON bit in the RCC_BDCR register. The LSE \nhas priority over the GPIO function.\nNote:\nThe PC14/PC15 GPIO functionality is lost when the 1.2 V domain is powered off (by the \ndevice entering the standby mode) or when the backup domain is supplied by VBAT (VDD no \nmore supplied). In this case the I/Os are set in analog input mode.\n8.3.14 \nUsing the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins\nThe HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 \nI/Os, respectively, when the HSE oscillator is OFF. (after reset, the HSE oscillator is off). The \nPH0/PH1 I/Os are only configured as OSC_IN/OSC_OUT HSE oscillator pins when the \nHSE oscillator is ON. This is done by setting the HSEON bit in the RCC_CR register. The \nHSE has priority over the GPIO function.\nFrom on-chip \nperipheral\nTo on-chip \nperipheral\nAnalog\n trigger\noff\nInput driver\n0\nInput data register\nOutput data register\nRead/write\nRead\nBit set/reset registers\nWrite\nAnalog\nVSS\nVDD\nprotection\ndiode\nprotection\ndiode\nI/O pin\nai15943\nTTL Schmitt \n\n\n<>\n\nGeneral-purpose I/Os (GPIO)\nRM0090\n282/1757\nRM0090 Rev 21\n8.3.15 \nSelection of RTC_AF1 and RTC_AF2 alternate functions\nThe STM32F4xx feature two GPIO pins RTC_AF1 and RTC_AF2 that can be used for the \ndetection of a tamper or time stamp event, or RTC_ALARM, or RTC_CALIB RTC outputs.\n•\nThe RTC_AF1 (PC13) can be used for the following purposes:\nRTC_ALARM output: this output can be RTC Alarm A, RTC Alarm B or RTC Wake-up \ndepending on the OSEL[1:0] bits in the RTC_CR register\n•\nRTC_CALIB output: this feature is enabled by setting the COE[23] in the RTC_CR \nregister\n•\nRTC_TAMP1: tamper event detection\n•\nRTC_TS: time stamp event detection\nThe RTC_AF2 (PI8) can be used for the following purposes:\n•\nRTC_TAMP1: tamper event detection\n•\nRTC_TAMP2: tamper event detection\n•\nRTC_TS: time stamp event detection\nThe selection of the corresponding pin is performed through the RTC_TAFCR register as \nfollows:\n•\nTAMP1INSEL is used to select which pin is used as the RTC_TAMP1 tamper input\n•\nTSINSEL is used to select which pin is used as the RTC_TS time stamp input\n•\nALARMOUTTYPE is used to select whether the RTC_ALARM is output in push-pull or \nopen-drain mode\nThe output mechanism follows the priority order listed in Table 38 and Table 39.\n \nTable 38. RTC_AF1 pin(1)\nPin \nconfiguration \nand function\nRTC_ALARM \nenabled\nRTC_CALIB \nenabled\nTamper \nenabled\nTime \nstamp \nenabled\nTAMP1INSEL \nTAMPER1 \npin selection\nTSINSEL \nTIMESTAMP \npin \nselection\nALARMOUTTYPE \nRTC_ALARM \nconfiguration\nAlarm out \noutput OD\n1\nDon’t care\nDon’t \ncare\nDon’t \ncare\nDon’t care\nDon’t care\n0\nAlarm out \noutput PP\n1\nDon’t care\nDon’t \ncare\nDon’t \ncare\nDon’t care\nDon’t care\n1\nCalibration \nout output PP\n0\n1\nDon’t \ncare\nDon’t \ncare\nDon’t care\nDon’t care\nDon’t care\nTAMPER1 \ninput floating\n0\n0\n1\n0\n0\nDon’t care\nDon’t care\nTIMESTAMP \nand \nTAMPER1 \ninput floating\n0\n0\n1\n1\n0\n0\nDon’t care\nTIMESTAMP \ninput floating\n0\n0\n0\n1\nDon’t care\n0\nDon’t care\nStandard \nGPIO\n0\n0\n0\n0\nDon’t care\nDon’t care\nDon’t care\n1.\nOD: open drain; PP: push-pull.\n\n\n<>\n\nRM0090 Rev 21\n283/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\nTable 39. RTC_AF2 pin\nPin configuration and function\nTamper \nenabled\n Time \nstamp \nenabled\nTAMP1INSEL \nTAMPER1 \npin selection\nTSINSEL \nTIMESTAMP \npin \nselection\nALARMOUTTYPE \nRTC_ALARM \nconfiguration\nTAMPER1 input floating\n1\n0\n1\nDon’t care\nDon’t care\nTIMESTAMP and TAMPER1 input \nfloating\n1\n1\n1\n1\nDon’t care\nTIMESTAMP input floating\n0\n1\nDon’t care\n1\nDon’t care\nStandard GPIO\n0\n0\nDon’t care\nDon’t care\nDon’t care\n\n\n<>\n\nGeneral-purpose I/Os (GPIO)\nRM0090\n284/1757\nRM0090 Rev 21\n8.4 \nGPIO registers\nThis section gives a detailed description of the GPIO registers.\nFor a summary of register bits, register address offsets and reset values, refer to Table 40.\nThe GPIO registers can be accessed by byte (8 bits), half-words (16 bits) or words (32 bits). \n8.4.1 \nGPIO port mode register (GPIOx_MODER) (x = A..I/J/K)\nAddress offset: 0x00\nReset values:\n•\n0xA800 0000 for port A\n•\n0x0000 0280 for port B\n•\n0x0000 0000 for other ports\n \n \n8.4.2 \nGPIO port output type register (GPIOx_OTYPER) \n(x = A..I/J/K)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMODER15[1:0]\nMODER14[1:0]\nMODER13[1:0]\nMODER12[1:0]\nMODER11[1:0]\nMODER10[1:0]\nMODER9[1:0]\nMODER8[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMODER7[1:0]\nMODER6[1:0]\nMODER5[1:0]\nMODER4[1:0]\nMODER3[1:0]\nMODER2[1:0]\nMODER1[1:0]\nMODER0[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 2y:2y+1 MODERy[1:0]: Port x configuration bits (y = 0..15)\nThese bits are written by software to configure the I/O direction mode.\n00: Input (reset state)\n01: General purpose output mode\n10: Alternate function mode\n11: Analog mode\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOT15\nOT14\nOT13\nOT12\nOT11\nOT10\nOT9\nOT8\nOT7\nOT6\nOT5\nOT4\nOT3\nOT2\nOT1\nOT0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 OTy: Port x configuration bits (y = 0..15)\nThese bits are written by software to configure the output type of the I/O port.\n0: Output push-pull (reset state)\n1: Output open-drain\n\n\n<>\n\nRM0090 Rev 21\n285/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\n8.4.3 \nGPIO port output speed register (GPIOx_OSPEEDR)\n(x = A..I/J/K)\nAddress offset: 0x08\nReset values:\n•\n0x0C00 0000 for port A\n•\n0x0000 00C0 for port B\n•\n0x0000 0000 for other ports\n \n \n8.4.4 \nGPIO port pull-up/pull-down register (GPIOx_PUPDR)\n(x = A..I/J/K)\nAddress offset: 0x0C\nReset values:\n•\n0x6400 0000 for port A\n•\n0x0000 0100 for port B\n•\n0x0000 0000 for other ports\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nOSPEEDR15\n[1:0]\nOSPEEDR14\n[1:0]\nOSPEEDR13\n[1:0]\nOSPEEDR12\n[1:0]\nOSPEEDR11\n[1:0]\nOSPEEDR10\n[1:0]\nOSPEEDR9\n[1:0]\nOSPEEDR8\n[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOSPEEDR7[1:0]\nOSPEEDR6[1:0]\nOSPEEDR5[1:0]\nOSPEEDR4[1:0]\nOSPEEDR3[1:0]\nOSPEEDR2[1:0]\nOSPEEDR1\n[1:0]\nOSPEEDR0\n1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 2y:2y+1 OSPEEDRy[1:0]: Port x configuration bits (y = 0..15)\nThese bits are written by software to configure the I/O output speed.\n00: Low speed\n01: Medium speed\n10: High speed\n11: Very high speed\nNote: Refer to the product datasheets for the values of OSPEEDRy bits versus VDD \nrange and external load.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nPUPDR15[1:0]\nPUPDR14[1:0]\nPUPDR13[1:0]\nPUPDR12[1:0]\nPUPDR11[1:0]\nPUPDR10[1:0]\nPUPDR9[1:0]\nPUPDR8[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPUPDR7[1:0]\nPUPDR6[1:0]\nPUPDR5[1:0]\nPUPDR4[1:0]\nPUPDR3[1:0]\nPUPDR2[1:0]\nPUPDR1[1:0]\nPUPDR0[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nGeneral-purpose I/Os (GPIO)\nRM0090\n286/1757\nRM0090 Rev 21\n \n8.4.5 \nGPIO port input data register (GPIOx_IDR) (x = A..I/J/K)\nAddress offset: 0x10\nReset value: 0x0000 XXXX (where X means undefined)\n \n \n8.4.6 \nGPIO port output data register (GPIOx_ODR) (x = A..I/J/K)\nAddress offset: 0x14\nReset value: 0x0000 0000\n \n \nBits 2y:2y+1 PUPDRy[1:0]: Port x configuration bits (y = 0..15)\nThese bits are written by software to configure the I/O pull-up or pull-down\n00: No pull-up, pull-down\n01: Pull-up\n10: Pull-down\n11: Reserved\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nIDR15\nIDR14\nIDR13\nIDR12\nIDR11\nIDR10\nIDR9\nIDR8\nIDR7\nIDR6\nIDR5\nIDR4\nIDR3\nIDR2\nIDR1\nIDR0\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 IDRy: Port input data (y = 0..15)\nThese bits are read-only and can be accessed in word mode only. They contain the input \nvalue of the corresponding I/O port.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nODR15\nODR14\nODR13\nODR12\nODR11\nODR10\nODR9\nODR8\nODR7\nODR6\nODR5\nODR4\nODR3\nODR2\nODR1\nODR0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 ODRy: Port output data (y = 0..15)\nThese bits can be read and written by software.\nNote: For atomic bit set/reset, the ODR bits can be individually set and reset by writing to the \nGPIOx_BSRR register (x = A..I/J/K).\n\n\n<>\n\nRM0090 Rev 21\n287/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\n8.4.7 \nGPIO port bit set/reset register (GPIOx_BSRR) (x = A..I/J/K)\nAddress offset: 0x18\nReset value: 0x0000 0000\n \n \n8.4.8 \nGPIO port configuration lock register (GPIOx_LCKR)\n(x = A..I/J/K)\nThis register is used to lock the configuration of the port bits when a correct write sequence \nis applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the \nGPIO. During the write sequence, the value of LCKR[15:0] must not change. When the \nLOCK sequence has been applied on a port bit, the value of this port bit can no longer be \nmodified until the next MCU or peripheral reset.\nNote:\nA specific write sequence is used to write to the GPIOx_LCKR register. Only word access \n(32-bit long) is allowed during this write sequence.\nEach lock bit freezes a specific configuration register (control and alternate function \nregisters).\nAddress offset: 0x1C\nReset value: 0x0000 0000\nAccess: 32-bit word only, read/write register\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nBR15\nBR14\nBR13\nBR12\nBR11\nBR10\nBR9\nBR8\nBR7\nBR6\nBR5\nBR4\nBR3\nBR2\nBR1\nBR0\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nBS15\nBS14\nBS13\nBS12\nBS11\nBS10\nBS9\nBS8\nBS7\nBS6\nBS5\nBS4\nBS3\nBS2\nBS1\nBS0\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBits 31:16 BRy: Port x reset bit y (y = 0..15)\nThese bits are write-only and can be accessed in word, half-word or byte mode. A read to \nthese bits returns the value 0x0000.\n0: No action on the corresponding ODRx bit\n1: Resets the corresponding ODRx bit\nNote: If both BSx and BRx are set, BSx has priority.\nBits 15:0 BSy: Port x set bit y (y= 0..15)\nThese bits are write-only and can be accessed in word, half-word or byte mode. A read to \nthese bits returns the value 0x0000.\n0: No action on the corresponding ODRx bit\n1: Sets the corresponding ODRx bit\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nLCKK\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nLCK15\nLCK14\nLCK13\nLCK12\nLCK11\nLCK10\nLCK9\nLCK8\nLCK7\nLCK6\nLCK5\nLCK4\nLCK3\nLCK2\nLCK1\nLCK0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nGeneral-purpose I/Os (GPIO)\nRM0090\n288/1757\nRM0090 Rev 21\n \n8.4.9 \nGPIO alternate function low register (GPIOx_AFRL) (x = A..I/J/K)\nAddress offset: 0x20\nReset value: 0x0000 0000\n \n \nBits 31:17 Reserved, must be kept at reset value.\nBit 16 LCKK[16]: Lock key\nThis bit can be read any time. It can only be modified using the lock key write sequence.\n0: Port configuration lock key not active\n1: Port configuration lock key active. The GPIOx_LCKR register is locked until an MCU reset \nor a peripheral reset occurs.\nLOCK key write sequence:\nWR LCKR[16] = ‘1’ + LCKR[15:0]\nWR LCKR[16] = ‘0’ + LCKR[15:0]\nWR LCKR[16] = ‘1’ + LCKR[15:0]\nRD LCKR\nRD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active)\nNote: During the LOCK key write sequence, the value of LCK[15:0] must not change.\nAny error in the lock sequence aborts the lock.\nAfter the first lock sequence on any bit of the port, any read access on the LCKK bit \nreturns ‘1’ until the next CPU reset.\nBits 15:0 LCKy: Port x lock bit y (y= 0..15)\nThese bits are read/write but can only be written when the LCKK bit is ‘0.\n0: Port configuration not locked\n1: Port configuration locked\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nAFRL7[3:0]\nAFRL6[3:0]\nAFRL5[3:0]\nAFRL4[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nAFRL3[3:0]\nAFRL2[3:0]\nAFRL1[3:0]\nAFRL0[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 AFRLy: Alternate function selection for port x bit y (y = 0..7)\nThese bits are written by software to configure alternate function I/Os\nAFRLy selection:\n0000: AF0\n0001: AF1\n0010: AF2\n0011: AF3\n0100: AF4\n0101: AF5\n0110: AF6\n0111: AF7\n1000: AF8\n1001: AF9\n1010: AF10\n1011: AF11\n1100: AF12\n1101: AF13\n1110: AF14\n1111: AF15\n\n\n<>\n\nRM0090 Rev 21\n289/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\n8.4.10 \nGPIO alternate function high register (GPIOx_AFRH)\n(x = A..I/J)\nAddress offset: 0x24\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nAFRH15[3:0]\nAFRH14[3:0]\nAFRH13[3:0]\nAFRH12[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nAFRH11[3:0]\nAFRH10[3:0]\nAFRH9[3:0]\nAFRH8[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 AFRHy: Alternate function selection for port x bit y (y = 8..15)\nThese bits are written by software to configure alternate function I/Os\nAFRHy selection:\n0000: AF0\n0001: AF1\n0010: AF2\n0011: AF3\n0100: AF4\n0101: AF5\n0110: AF6\n0111: AF7\n1000: AF8\n1001: AF9\n1010: AF10\n1011: AF11\n1100: AF12\n1101: AF13\n1110: AF14\n1111: AF15\n\n\n<>\n\nGeneral-purpose I/Os (GPIO)\nRM0090\n290/1757\nRM0090 Rev 21\n8.4.11 \nGPIO register map\nThe following table gives the GPIO register map and the reset values. \n \nTable 40. GPIO register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nGPIOA_\nMODER\nMODER15[1:0]\nMODER14[1:0]\nMODER13[1:0]\nMODER12[1:0]\nMODER11[1:0]\nMODER10[1:0]\nMODER9[1:0]\nMODER8[1:0]\nMODER7[1:0]\nMODER6[1:0]\nMODER5[1:0]\nMODER4[1:0]\nMODER3[1:0]\nMODER2[1:0]\nMODER1[1:0]\nMODER0[1:0]\nReset value\n1\n0\n1\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00\nGPIOB_\nMODER\nMODER15[1:0]\nMODER14[1:0]\nMODER13[1:0]\nMODER12[1:0]\nMODER11[1:0]\nMODER10[1:0]\nMODER9[1:0]\nMODER8[1:0]\nMODER7[1:0]\nMODER6[1:0]\nMODER5[1:0]\nMODER4[1:0]\nMODER3[1:0]\nMODER2[1:0]\nMODER1[1:0]\nMODER0[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0x00\nGPIOx_MODER \n(where x = \nC..I/J/K)\nMODER15[1:0]\nMODER14[1:0]\nMODER13[1:0]\nMODER12[1:0]\nMODER11[1:0]\nMODER10[1:0]\nMODER9[1:0]\nMODER8[1:0]\nMODER7[1:0]\nMODER6[1:0]\nMODER5[1:0]\nMODER4[1:0]\nMODER3[1:0]\nMODER2[1:0]\nMODER1[1:0]\nMODER0[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nGPIOx_\nOTYPER\n(where x = \nA..I/J/K)\nReserved\nOT15\nOT14\nOT13\nOT12\nOT11\nOT10\nOT9\nOT8\nOT7\nOT6\nOT5\nOT4\nOT3\nOT2\nOT1\nOT0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nGPIOx_\nOSPEEDR \n(where x = \nA..I/J/K except \nB)\nOSPEEDR15[1:0]\nOSPEEDR14[1:0]\nOSPEEDR13[1:0]\nOSPEEDR12[1:0]\nOSPEEDR11[1:0]\nOSPEEDR10[1:0]\nOSPEEDR9[1:0]\nOSPEEDR8[1:0]\nOSPEEDR7[1:0]\nOSPEEDR6[1:0]\nOSPEEDR5[1:0]\nOSPEEDR4[1:0]\nOSPEEDR3[1:0]\nOSPEEDR2[1:0]\nOSPEEDR1[1:0]\nOSPEEDR0[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nGPIOB_\nOSPEEDR\nOSPEEDR15[1:0]\nOSPEEDR14[1:0]\nOSPEEDR13[1:0]\nOSPEEDR12[1:0]\nOSPEEDR11[1:0]\nOSPEEDR10[1:0]\nOSPEEDR9[1:0]\nOSPEEDR8[1:0]\nOSPEEDR7[1:0]\nOSPEEDR6[1:0]\nOSPEEDR5[1:0]\nOSPEEDR4[1:0]\nOSPEEDR3[1:0]\nOSPEEDR2[1:0]\nOSPEEDR1[1:0]\nOSPEEDR0[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\n0x0C\nGPIOA_PUPDR\nPUPDR15[1:0]\nPUPDR14[1:0]\nPUPDR13[1:0]\nPUPDR12[1:0]\nPUPDR11[1:0]\nPUPDR10[1:0]\nPUPDR9[1:0]\nPUPDR8[1:0]\nPUPDR7[1:0]\nPUPDR6[1:0]\nPUPDR5[1:0]\nPUPDR4[1:0]\nPUPDR3[1:0]\nPUPDR2[1:0]\nPUPDR1[1:0]\nPUPDR0[1:0]\nReset value\n0\n1\n1\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nGPIOB_PUPDR\nPUPDR15[1:0]\nPUPDR14[1:0]\nPUPDR13[1:0]\nPUPDR12[1:0]\nPUPDR11[1:0]\nPUPDR10[1:0]\nPUPDR9[1:0]\nPUPDR8[1:0]\nPUPDR7[1:0]\nPUPDR6[1:0]\nPUPDR5[1:0]\nPUPDR4[1:0]\nPUPDR3[1:0]\nPUPDR2[1:0]\nPUPDR1[1:0]\nPUPDR0[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n\n\n<>\n\nRM0090 Rev 21\n291/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x0C\nGPIOx_PUPDR \n(where x = \nC..I/J/K)\nPUPDR15[1:0]\nPUPDR14[1:0]\nPUPDR13[1:0]\nPUPDR12[1:0]\nPUPDR11[1:0]\nPUPDR10[1:0]\nPUPDR9[1:0]\nPUPDR8[1:0]\nPUPDR7[1:0]\nPUPDR6[1:0]\nPUPDR5[1:0]\nPUPDR4[1:0]\nPUPDR3[1:0]\nPUPDR2[1:0]\nPUPDR1[1:0]\nPUPDR0[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nGPIOx_IDR \n(where x = \nA..I/J/K)\nReserved\nIDR15\nIDR14\nIDR13\nIDR12\nIDR11\nIDR10\nIDR9\nIDR8\nIDR7\nIDR6\nIDR5\nIDR4\nIDR3\nIDR2\nIDR1\nIDR0\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x14\nGPIOx_ODR \n(where x = \nA..I/J/K)\nReserved\nODR15\nODR14\nODR13\nODR12\nODR11\nODR10\nODR9\nODR8\nODR7\nODR6\nODR5\nODR4\nODR3\nODR2\nODR1\nODR0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x18\nGPIOx_BSRR \n(where x = \nA..I/J/K)\nBR15\nBR14\nBR13\nBR12\nBR11\nBR10\nBR9\nBR8\nBR7\nBR6\nBR5\nBR4\nBR3\nBR2\nBR1\nBR0\nBS15\nBS14\nBS13\nBS12\nBS11\nBS10\nBS9\nBS8\nBS7\nBS6\nBS5\nBS4\nBS3\nBS2\nBS1\nBS0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nGPIOx_LCKR \n(where x = \nA..I/J/K)\nReserved\nLCKK\nLCK15\nLCK14\nLCK13\nLCK12\nLCK11\nLCK10\nLCK9\nLCK8\nLCK7\nLCK6\nLCK5\nLCK4\nLCK3\nLCK2\nLCK1\nLCK0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nGPIOx_AFRL \n(where x = \nA..I/J/K)\nAFRL7[3:0]\nAFRL6[3:0]\nAFRL5[3:0]\nAFRL4[3:0]\nAFRL3[3:0]\nAFRL2[3:0]\nAFRL1[3:0]\nAFRL0[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x24\nGPIOx_AFRH \n(where x = \nA..I/J)\nAFRH15[3:0]\nAFRH14[3:0]\nAFRH13[3:0]\nAFRH12[3:0]\nAFRH11[3:0]\nAFRH10[3:0]\nAFRH9[3:0]\nAFRH8[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 40. GPIO register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nSystem configuration controller (SYSCFG)\nRM0090\n292/1757\nRM0090 Rev 21\n9 \nSystem configuration controller (SYSCFG)\nThe system configuration controller is mainly used to remap the memory accessible in the \ncode area, select the Ethernet PHY interface and manage the external interrupt line \nconnection to the GPIOs.\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n9.1 \nI/O compensation cell\nBy default the I/O compensation cell is not used. However when the I/O output buffer speed \nis configured in 50 MHz or 100 MHz mode, it is recommended to use the compensation cell \nfor slew rate control on I/O tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power \nsupply.\nWhen the compensation cell is enabled, a READY flag is set to indicate that the \ncompensation cell is ready and can be used. The I/O compensation cell can be used only \nwhen the supply voltage ranges from 2.4 to 3.6 V.\n9.2 \nSYSCFG registers for STM32F405xx/07xx and \nSTM32F415xx/17xx\n9.2.1 \nSYSCFG memory remap register (SYSCFG_MEMRMP)\nThis register is used for specific configurations on memory remap:\n•\nTwo bits are used to configure the type of memory accessible at address 0x0000 0000. \nThese bits are used to select the physical remap by software and so, bypass the BOOT \npins.\n•\nAfter reset these bits take the value selected by the BOOT pins. When booting from \nmain Flash memory with BOOT pins set to 10 [(BOOT1,BOOT0) = (1,0)] this register \ntakes the value 0x00.\nWhen the FSMC is remapped at address 0x0000 0000, only the first two regions of Bank 1 \nmemory controller (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) can be remapped. In remap \nmode, the CPU can access the external memory via ICode bus instead of System bus \nwhich boosts up the performance. \nAddress offset: 0x00\nReset value: 0x0000 000X (X is the memory mode selected by the BOOT pins)\n )\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMEM_MODE\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n293/1757\nRM0090\nSystem configuration controller (SYSCFG)\n304\n \n9.2.2 \nSYSCFG peripheral mode configuration register (SYSCFG_PMC)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n \nBits 31:2 Reserved, must be kept at reset value.\nBits 1:0 MEM_MODE: Memory mapping selection\nSet and cleared by software. This bit controls the memory internal mapping at \naddress 0x0000 0000. After reset these bits take the value selected by the Boot \npins (except for FSMC).\n00: Main Flash memory mapped at 0x0000 0000\n01: System Flash memory mapped at 0x0000 0000\n10: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000\n11: Embedded SRAM (SRAM1) mapped at 0x0000 0000\nNote: Refer to Section 2.3: Memory map for details about the memory mapping at \naddress 0x0000 0000.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nMII_RMII\n_SEL\nReserved\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBits 31:24 Reserved, must be kept at reset value.\nBit 23 MII_RMII_SEL: Ethernet PHY interface selection\nSet and Cleared by software.These bits control the PHY interface for the \nEthernet MAC.\n0: MII interface is selected\n1: RMII PHY interface is selected\nNote: This configuration must be done while the MAC is under reset and before \nenabling the MAC clocks.\nBits 22:0 Reserved, must be kept at reset value.\n\n\n<>\n\nSystem configuration controller (SYSCFG)\nRM0090\n294/1757\nRM0090 Rev 21\n9.2.3 \nSYSCFG external interrupt configuration register 1\n(SYSCFG_EXTICR1)\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n \n9.2.4 \nSYSCFG external interrupt configuration register 2\n(SYSCFG_EXTICR2)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXTI3[3:0]\nEXTI2[3:0]\nEXTI1[3:0]\nEXTI0[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3)\nThese bits are written by software to select the source input for the EXTIx \nexternal interrupt. \n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n0111: PH[x] pin\n1000: PI[x] pin\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXTI7[3:0]\nEXTI6[3:0]\nEXTI5[3:0]\nEXTI4[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n295/1757\nRM0090\nSystem configuration controller (SYSCFG)\n304\n \n9.2.5 \nSYSCFG external interrupt configuration register 3\n(SYSCFG_EXTICR3)\nAddress offset: 0x10\nReset value: 0x0000 0000\n \n \nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7)\nThese bits are written by software to select the source input for the EXTIx \nexternal interrupt.\n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n0111: PH[x] pin\n1000: PI[x] pin\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXTI11[3:0]\nEXTI10[3:0]\nEXTI9[3:0]\nEXTI8[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x = 8 to 11)\nThese bits are written by software to select the source input for the EXTIx external \ninterrupt.\n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n0111: PH[x] pin\n1000: PI[x] pin\n\n\n<>\n\nSystem configuration controller (SYSCFG)\nRM0090\n296/1757\nRM0090 Rev 21\n9.2.6 \nSYSCFG external interrupt configuration register 4\n(SYSCFG_EXTICR4)\nAddress offset: 0x14\nReset value: 0x0000 0000\n \n9.2.7 \nCompensation cell control register (SYSCFG_CMPCR)\nAddress offset: 0x20\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXTI15[3:0]\nEXTI14[3:0]\nEXTI13[3:0]\nEXTI12[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15)\nThese bits are written by software to select the source input for the EXTIx external \ninterrupt.\n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n0111: PH[x] pin\nNote: PI[15:12] are not used.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nREADY\nReserved\nCMP_PD\nr\nrw\nBits 31:9 Reserved, must be kept at reset value.\nBit 8 READY: Compensation cell ready flag\n0: I/O compensation cell not ready\n1: O compensation cell ready\nBits 7:2 Reserved, must be kept at reset value.\nBit 0 CMP_PD: Compensation cell power-down\n0: I/O compensation cell power-down mode\n1: I/O compensation cell enabled\n\n\n<>\n\nRM0090 Rev 21\n297/1757\nRM0090\nSystem configuration controller (SYSCFG)\n304\n9.2.8 \nSYSCFG register maps for \nSTM32F405xx/07xx and STM32F415xx/17xx\nThe following table gives the SYSCFG register map and the reset values.\n \nRefer to Section 2.3: Memory map for the register boundary addresses.\n9.3 \nSYSCFG registers for STM32F42xxx and STM32F43xxx\n9.3.1 \nSYSCFG memory remap register (SYSCFG_MEMRMP)\nThis register is used for specific configurations on memory remap:\n•\nThree bits are used to configure the type of memory accessible at address \n0x0000 0000. These bits are used to select the physical remap by software and so, \nbypass the BOOT pins.\n•\nAfter reset these bits take the value selected by the BOOT pins. When booting from \nmain Flash memory with BOOT pins set to 10 [(BOOT1,BOOT0) = (1,0)] this register \ntakes the value 0x00.\n•\nOther bits are used to swap FMC SDRAM Bank 1/2 with FMC Bank 3/4 and configure \nthe Flash Bank 1/2 mapping\nTable 41. SYSCFG register map and reset values\n(STM32F405xx/07xx and STM32F415xx/17xx)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nSYSCFG_\nMEMRMP\nReserved\nMEM_MODE\nReset value\nx\nx\n0x04\nSYSCFG_PMC\nReserved\nMII_RMII_SEL\nReserved\nReserved\nReset value\n0\n0x08\nSYSCFG_EXTICR1\nReserved\nEXTI3[3:0]\nEXTI2[3:0]\nEXTI1[3:0]\nEXTI0[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nSYSCFG_EXTICR2\nReserved\nEXTI7[3:0]\nEXTI6[3:0]\nEXTI5[3:0]\nEXTI4[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nSYSCFG_EXTICR3\nReserved\nEXTI11[3:0]\nEXTI10[3:0]\nEXTI9[3:0]\nEXTI8[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nSYSCFG_EXTICR4\nReserved\nEXTI15[3:0]\nEXTI14[3:0]\nEXTI13[3:0]\nEXTI12[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nSYSCFG_CMPCR\nReserved\nREADY\nReserved\nCMP_PD\nReset value\n0\n0\n\n\n<>\n\nSystem configuration controller (SYSCFG)\nRM0090\n298/1757\nRM0090 Rev 21\nThere are two possible FMC remap at address 0x0000 0000:\n•\nFMC Bank 1 (NOR/PSRAM 1 and 2) remap:\nOnly the first two regions of Bank 1 memory controller (Bank1 NOR/PSRAM 1 and \nNOR/PSRAM 2) can be remapped.\n•\nFMC SDRAM Bank 1 remap.\nIn remap mode at address 0x0000 0000, the CPU can access the external memory via \nICode bus instead of System bus which boosts up the performance.\nAddress offset: 0x00\nReset value: 0x0000 000X (X is the memory mode selected by the BOOT pins)\nNote:\nBooting from NOR Flash memory or SDRAM is not allowed. The regions can only be \nmapped at 0x0000 0000 through software remap.\n )\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSWP_FMC\nRes.\nFB_\nMODE\nReserved\nMEM_MODE[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:10 SWP_FMC: FMC memory mapping swap\nSet and cleared by software. These bits are used to swap the FMC SDRAM \nBank 1/2 and FMC Bank 3/4 (SDRAM Bank 1/2 and NAND Bank 2/PCCARD \nBank) in order to enable the code execution from SDRAM Banks without a \nphysical remapping at 0x0000 0000 address.\n00: No FMC memory mapping swap\n01: SDRAM banks and NAND Bank 2/PCCARD mapping are swapped. SDRAM \nBank 1 and 2 are mapped at NAND Bank 2 (0x8000 0000) and PCCARD Bank \n(0x9000 0000) address, respectively. NAND Bank 2 and PCCARD Bank are \nmapped at 0xC000 0000 and 0xD000 0000, respectively. \n10: Reserved\n11: Reserved\nBit 9 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n299/1757\nRM0090\nSystem configuration controller (SYSCFG)\n304\n9.3.2 \nSYSCFG peripheral mode configuration register (SYSCFG_PMC)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n \nBit 8 FB_MODE: Flash Bank mode selection\nSet and cleared by software. This bit controls the Flash Bank 1/2 mapping.\n0: Flash Bank 1 is mapped at 0x0800 0000 (and aliased at 0x0000 0000) and \nFlash Bank 2 is mapped at 0x0810 0000 (and aliased at 0x0010 0000)\n1: Flash Bank 2 is mapped at 0x0800 0000 (and aliased at 0x0000 0000) and \nFlash Bank 1 is mapped at 0x0810 0000 (and aliased at 0x0010 0000)\nBits 7:3 Reserved, must be kept at reset value.\nBits 2:0 MEM_MODE: Memory mapping selection\nSet and cleared by software. This bit controls the memory internal mapping at \naddress 0x0000 0000. After reset these bits take the value selected by the Boot \npins (except for FMC).\n000: Main Flash memory mapped at 0x0000 0000\n001: System Flash memory mapped at 0x0000 0000\n010: FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000\n011: Embedded SRAM (SRAM1) mapped at 0x0000 0000\n100: FMC/SDRAM Bank 1 mapped at 0x0000 0000\nOther configurations are reserved\nNote: Refer to Section 2.3: Memory map for details about the memory mapping at \naddress 0x0000 0000.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nMII_RMII\n_SEL\nReserved\nADCxDC2\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBits 31:24 Reserved, must be kept at reset value.\nBit 23 MII_RMII_SEL: Ethernet PHY interface selection\nSet and Cleared by software.These bits control the PHY interface for the \nEthernet MAC.\n0: MII interface is selected\n1: RMII PHY interface is selected\nNote: This configuration must be done while the MAC is under reset and before \nenabling the MAC clocks.\n\n\n<>\n\nSystem configuration controller (SYSCFG)\nRM0090\n300/1757\nRM0090 Rev 21\n9.3.3 \nSYSCFG external interrupt configuration register 1\n(SYSCFG_EXTICR1)\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n \nBits 22:19 Reserved, must be kept at reset value.\nBits 18:16 ADCxDC2:\n0: No effect. \n1: Refer to AN4073 on how to use this bit. \nNote: These bits can be set only if the following conditions are met:\n- ADC clock higher or equal to 30 MHz.\n- Only one ADCxDC2 bit must be selected if ADC conversions do not start \nat the same time and the sampling times differ. \n- These bits must not be set when the ADCDC1 bit is set in PWR_CR \nregister.\nBits 15:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXTI3[3:0]\nEXTI2[3:0]\nEXTI1[3:0]\nEXTI0[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3)\nThese bits are written by software to select the source input for the EXTIx \nexternal interrupt. \n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n0111: PH[x] pin\n1000: PI[x] pin\n1001: PJ[x] pin\n1010: PK[x] pin\n\n\n<>\n\nRM0090 Rev 21\n301/1757\nRM0090\nSystem configuration controller (SYSCFG)\n304\n9.3.4 \nSYSCFG external interrupt configuration register 2\n(SYSCFG_EXTICR2)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n \n \n9.3.5 \nSYSCFG external interrupt configuration register 3\n(SYSCFG_EXTICR3)\nAddress offset: 0x10\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXTI7[3:0]\nEXTI6[3:0]\nEXTI5[3:0]\nEXTI4[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7)\nThese bits are written by software to select the source input for the EXTIx \nexternal interrupt.\n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n0111: PH[x] pin\n1000: PI[x] pin\n1001: PJ[x] pin\n1010: PK[x] pin\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXTI11[3:0]\nEXTI10[3:0]\nEXTI9[3:0]\nEXTI8[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nSystem configuration controller (SYSCFG)\nRM0090\n302/1757\nRM0090 Rev 21\n \n9.3.6 \nSYSCFG external interrupt configuration register 4\n(SYSCFG_EXTICR4)\nAddress offset: 0x14\nReset value: 0x0000 0000\n \nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x = 8 to 11)\nThese bits are written by software to select the source input for the EXTIx \nexternal interrupt.\n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n0111: PH[x] pin\n1000: PI[x] pin\n1001: PJ[x] pin\nNote: PK[11:8] are not used.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXTI15[3:0]\nEXTI14[3:0]\nEXTI13[3:0]\nEXTI12[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15)\nThese bits are written by software to select the source input for the EXTIx external \ninterrupt.\n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n0111: PH[x] pin\n1000: PI[x] pin\n1001: PJ[x] pin\nNote: PK[15:12] are not used.\n\n\n<>\n\nRM0090 Rev 21\n303/1757\nRM0090\nSystem configuration controller (SYSCFG)\n304\n9.3.7 \nCompensation cell control register (SYSCFG_CMPCR)\nAddress offset: 0x20\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nREADY\nReserved\nCMP_PD\nr\nrw\nBits 31:9 Reserved, must be kept at reset value.\nBit 8 READY: Compensation cell ready flag\n0: I/O compensation cell not ready\n1: O compensation cell ready\nBits 7:2 Reserved, must be kept at reset value.\nBit 0 CMP_PD: Compensation cell power-down\n0: I/O compensation cell power-down mode\n1: I/O compensation cell enabled\n\n\n<>\n\nSystem configuration controller (SYSCFG)\nRM0090\n304/1757\nRM0090 Rev 21\n9.3.8 \nSYSCFG register maps for STM32F42xxx and STM32F43xxx\nThe following table gives the SYSCFG register map and the reset values.\n \nRefer to Section 2.3: Memory map for the register boundary addresses.\nTable 42. SYSCFG register map and reset values (STM32F42xxx and STM32F43xxx)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nSYSCFG_\nMEMRMP\nReserved\nSWP_FMC\nReserved\nFB_MODE\nReserved\nMEM_\nMODE\nReset value\n0\n0\n0\nx\nx\nx\n0x04\nSYSCFG_PMC\nReserved\nMII_RMII_SEL\nReserved\nADC3DC2\nADC2DC2\nADC1DC2\nReserved\nReset value\n0\n0\n0\n0\n0x08\nSYSCFG_EXTICR1\nReserved\nEXTI3[3:0]\nEXTI2[3:0]\nEXTI1[3:0]\nEXTI0[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nSYSCFG_EXTICR2\nReserved\nEXTI7[3:0]\nEXTI6[3:0]\nEXTI5[3:0]\nEXTI4[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nSYSCFG_EXTICR3\nReserved\nEXTI11[3:0]\nEXTI10[3:0]\nEXTI9[3:0]\nEXTI8[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nSYSCFG_EXTICR4\nReserved\nEXTI15[3:0]\nEXTI14[3:0]\nEXTI13[3:0]\nEXTI12[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nSYSCFG_CMPCR\nReserved\nREADY\nReserved\nCMP_PD\nReset value\n0\n0\n\n\n<>\n\nRM0090 Rev 21\n305/1757\nRM0090\nDMA controller (DMA)\n341\n10 \nDMA controller (DMA)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n10.1 \nDMA introduction\nDirect memory access (DMA) is used in order to provide high-speed data transfer between \nperipherals and memory and between memory and memory. Data can be quickly moved by \nDMA without any CPU action. This keeps CPU resources free for other operations.\nThe DMA controller combines a powerful dual AHB master bus architecture with \nindependent FIFO to optimize the bandwidth of the system, based on a complex bus matrix \narchitecture.\nThe two DMA controllers have 16 streams in total (8 for each controller), each dedicated to \nmanaging memory access requests from one or more peripherals. Each stream can have \nup to 8 channels (requests) in total. And each has an arbiter for handling the priority \nbetween DMA requests.\n10.2 \nDMA main features\nThe main DMA features are:\n•\nDual AHB master bus architecture, one dedicated to memory accesses and one \ndedicated to peripheral accesses\n•\nAHB slave programming interface supporting only 32-bit accesses\n•\n8 streams for each DMA controller, up to 8 channels (requests) per stream\n•\nFour-word depth 32 first-in, first-out memory buffers (FIFOs) per stream, that can be \nused in FIFO mode or direct mode:\n–\nFIFO mode: with threshold level software selectable between 1/4, 1/2 or 3/4 of the \nFIFO size\n–\nDirect mode \nEach DMA request immediately initiates a transfer from/to the memory. When it is \nconfigured in direct mode (FIFO disabled), to transfer data in memory-to-\nperipheral mode, the DMA preloads only one data from the memory to the internal \n\n\n<>\n\nDMA controller (DMA)\nRM0090\n306/1757\nRM0090 Rev 21\nFIFO to ensure an immediate data transfer as soon as a DMA request is triggered \nby a peripheral.\n•\nEach stream can be configured by hardware to be:\n–\na regular channel that supports peripheral-to-memory, memory-to-peripheral and \nmemory-to-memory transfers\n–\na double buffer channel that also supports double buffering on the memory side\n•\nEach of the 8 streams are connected to dedicated hardware DMA channels (requests)\n•\nPriorities between DMA stream requests are software-programmable (4 levels \nconsisting of very high, high, medium, low) or hardware in case of equality (request 0 \nhas priority over request 1, etc.)\n•\nEach stream also supports software trigger for memory-to-memory transfers (only \navailable for the DMA2 controller)\n•\nEach stream request can be selected among up to 8 possible channel requests. This \nselection is software-configurable and allows several peripherals to initiate DMA \nrequests\n•\nThe number of data items to be transferred can be managed either by the DMA \ncontroller or by the peripheral:\n–\nDMA flow controller: the number of data items to be transferred is software-\nprogrammable from 1 to 65535\n–\nPeripheral flow controller: the number of data items to be transferred is unknown \nand controlled by the source or the destination peripheral that signals the end of \nthe transfer by hardware\n•\nIndependent source and destination transfer width (byte, half-word, word): when the \ndata widths of the source and destination are not equal, the DMA automatically \npacks/unpacks the necessary transfers to optimize the bandwidth. This feature is only \navailable in FIFO mode\n•\nIncrementing or non-incrementing addressing for source and destination\n•\nSupports incremental burst transfers of 4, 8 or 16 beats. The size of the burst is \nsoftware-configurable, usually equal to half the FIFO size of the peripheral\n•\nEach stream supports circular buffer management\n•\n5 event flags (DMA Half Transfer, DMA Transfer complete, DMA Transfer Error, DMA \nFIFO Error, Direct Mode Error) logically ORed together in a single interrupt request for \neach stream\n\n\n<>\n\nRM0090 Rev 21\n307/1757\nRM0090\nDMA controller (DMA)\n341\n10.3 \nDMA functional description\n10.3.1 \nGeneral description\nFigure 32 shows the block diagram of a DMA.\nFigure 32. DMA block diagram\nThe DMA controller performs direct memory transfer: as an AHB master, it can take the \ncontrol of the AHB bus matrix to initiate AHB transactions.\nIt can carry out the following transactions:\n•\nperipheral-to-memory\n•\nmemory-to-peripheral\n•\nmemory-to-memory\nThe DMA controller provides two AHB master ports: the AHB memory port, intended to be \nconnected to memories and the AHB peripheral port, intended to be connected to \nperipherals. However, to allow memory-to-memory transfers, the AHB peripheral port must \nalso have access to the memories.\nThe AHB slave port is used to program the DMA controller (it supports only 32-bit \naccesses).\nAHB master\nMemory port\nFIFO \nAHB master\nPeripheral port\nSTREAM 0\nFIFO \nSTREAM 1\nSTREAM 0\nSTREAM 1\nFIFO \nSTREAM 2\nSTREAM 2\nFIFO \nSTREAM 7\nSTREAM 7\nREQ_STREAM0\nREQ_STR0_CH0\nREQ_STR0_CH1\nDMA controller\nFIFO \nSTREAM 3\nSTREAM 3\nFIFO \nSTREAM 4\nSTREAM 4\nFIFO \nSTREAM 5\nSTREAM 5\nFIFO \nSTREAM 6\nSTREAM 6\nArbiter\nREQ_STREAM1\nREQ_STREAM2\nREQ_STREAM3\nREQ_STREAM4\nREQ_STREAM5\nREQ_STREAM6\nREQ_STREAM7\nREQ_STR0_CH7\nREQ_STR1_CH0\nREQ_STR1_CH1\nREQ_STR1_CH7\nREQ_STR7_CH0\nREQ_STR7_CH1\nREQ_STR7_CH7\nAHB slave\nprogramming\ninterface\nProgramming port\nChannel\nselection\nai15945\n\n\n<>\n\nDMA controller (DMA)\nRM0090\n308/1757\nRM0090 Rev 21\nSee Figure 33 and Figure 34 for the implementation of the system of two DMA controllers.\nFigure 33. System implementation of the two DMA controllers \n(STM32F405xx/07xx and STM32F415xx/17xx)\n1.\nThe DMA1 controller AHB peripheral port is not connected to the bus matrix like DMA2 controller. As a result, only DMA2 \nstreams are able to perform memory-to-memory transfers.\nMS19927V2\nDMA controller 1\nAHB periph\nArbiter\nAHB memory\nFIFO\nDMA controller 2\nAHB memory\nBus matrix \n(AHB \nArbiter\nAHB periph\nMAPPING\nFIFO\nExternal memory\nFlash\nmemory\n112 KB SRAM\nAHB2 peripherals\nmultilayer)\nAHB-APB \nbridge2\n(dual AHB)\nAPB2\nAPB2\nAHB-APB \nbridge1\n(dual AHB)\nAPB1\nAPB1\nperipherals\nAHB slave\nAHB slave\nport\nport\nport\nport\ncontroller (FSMC)\nDMA request\nperipherals\n16 KB SRAM\nAHB1 peripherals\nTo AHB2\nperipherals\nTo AHB2\nperipherals\nDCODE\nICODE\n\n\n<>\n\nRM0090 Rev 21\n309/1757\nRM0090\nDMA controller (DMA)\n341\nFigure 34. System implementation of the two DMA controllers\n(STM32F42xxx and STM32F43xxx) \n1.\nThe DMA1 controller AHB peripheral port is not connected to the bus matrix like in the case of the DMA2 \ncontroller, thus only DMA2 streams are able to perform memory-to-memory transfers.\n10.3.2 \nDMA transactions\nA DMA transaction consists of a sequence of a given number of data transfers. The number \nof data items to be transferred and their width (8-bit, 16-bit or 32-bit) are software-\nprogrammable.\nEach DMA transfer consists of three operations:\n•\nA loading from the peripheral data register or a location in memory, addressed through \nthe DMA_SxPAR or DMA_SxM0AR register\n•\nA storage of the data loaded to the peripheral data register or a location in memory \naddressed through the DMA_SxPAR or DMA_SxM0AR register\n•\nA post-decrement of the DMA_SxNDTR register, which contains the number of \ntransactions that still have to be performed\nMS30438V1\nDMA controller 1\nAHB periph\nArbiter\nAHB memory\nFIFO\nDMA controller 2\nAHB memory\nBus Matrix\n(AHB multilayer)\n \nArbiter\nAHB periph\nMAPPING\nFIFO\nExternal memory\nFlash\nmemory\n112 KB SRAM\nAHB2 peripherals\nAHB-APB \nbridge2\n(dual AHB)\nAPB2\nAPB2\nAHB-APB \nbridge1\n(dual AHB)\nAPB1\nAPB1\nperipherals\nAHB slave\nAHB slave\nport\nport\nport\nport\ncontroller (FMC)\nDMA request\nperipherals\n16 KB SRAM\nAHB1 peripherals\nTo AHB2\nperipherals\nTo AHB2\nperipherals\nDCODE\nICODE\n64 KB SRAM\n\n\n<>\n\nDMA controller (DMA)\nRM0090\n310/1757\nRM0090 Rev 21\nAfter an event, the peripheral sends a request signal to the DMA controller. The DMA \ncontroller serves the request depending on the channel priorities. As soon as the DMA \ncontroller accesses the peripheral, an Acknowledge signal is sent to the peripheral by the \nDMA controller. The peripheral releases its request as soon as it gets the Acknowledge \nsignal from the DMA controller. Once the request has been deasserted by the peripheral, \nthe DMA controller releases the Acknowledge signal. If there are more requests, the \nperipheral can initiate the next transaction.\n10.3.3 \nChannel selection\nEach stream is associated with a DMA request that can be selected out of 8 possible \nchannel requests. The selection is controlled by the CHSEL[2:0] bits in the DMA_SxCR \nregister.\nFigure 35. Channel selection\nThe 8 requests from the peripherals (TIM, ADC, SPI, I2C, etc.) are independently connected \nto each channel and their connection depends on the product implementation.\nSee the following table(s) for examples of DMA request mappings.\n \nREQ_STREAMx\nREQ_STRx_CH7\nCHSEL[2:0]\n31\n27\n25\n0\nDMA_SxCR\nai15947b\nREQ_STRx_CH6\nREQ_STRx_CH5\nREQ_STRx_CH4\nREQ_STRx_CH3\nREQ_STRx_CH2\nREQ_STRx_CH1\nREQ_STRx_CH0\nTable 43. DMA1 request mapping\nPeripheral \nrequests\nStream 0\nStream 1\nStream 2\nStream 3 \nStream 4\nStream 5\nStream 6\nStream 7\nChannel 0\nSPI3_RX\n-\nSPI3_RX\nSPI2_RX\nSPI2_TX\nSPI3_TX\n-\nSPI3_TX\nChannel 1\nI2C1_RX\n-\nTIM7_UP\n-\nTIM7_UP\nI2C1_RX\nI2C1_TX\nI2C1_TX\nChannel 2\nTIM4_CH1\n-\nI2S3_EXT_\nRX\nTIM4_CH2\nI2S2_EXT_\nTX\nI2S3_EXT_\nTX\nTIM4_UP\nTIM4_CH3\nChannel 3\nI2S3_EXT_\nRX\nTIM2_UP\nTIM2_CH3\nI2C3_RX\nI2S2_EXT_\nRX\nI2C3_TX\nTIM2_CH1\nTIM2_CH2\nTIM2_CH4\nTIM2_UP\nTIM2_CH4\nChannel 4\nUART5_RX\nUSART3_RX\nUART4_RX\nUSART3_TX\nUART4_TX\nUSART2_RX\nUSART2_TX\nUART5_TX\nChannel 5\nUART8_TX(1)\nUART7_TX(1)\nTIM3_CH4\nTIM3_UP\nUART7_RX(1)\nTIM3_CH1\nTIM3_TRIG\nTIM3_CH2\nUART8_RX(1)\nTIM3_CH3\n\n\n<>\n\nRM0090 Rev 21\n311/1757\nRM0090\nDMA controller (DMA)\n341\n \n \n \n10.3.4 \nArbiter\nAn arbiter manages the 8 DMA stream requests based on their priority for each of the two \nAHB master ports (memory and peripheral ports) and launches the peripheral/memory \naccess sequences.\nPriorities are managed in two stages:\n•\nSoftware: each stream priority can be configured in the DMA_SxCR register. There are \nfour levels:\n–\nVery high priority\n–\nHigh priority\n–\nMedium priority\n–\nLow priority\n•\nHardware: If two requests have the same software priority level, the stream with the \nlower number takes priority over the stream with the higher number. For example, \nStream 2 takes priority over Stream 4.\nChannel 6\nTIM5_CH3\nTIM5_UP\nTIM5_CH4\nTIM5_TRIG\nTIM5_CH1\nTIM5_CH4\nTIM5_TRIG\nTIM5_CH2\n-\nTIM5_UP\n-\nChannel 7\n-\nTIM6_UP\nI2C2_RX\nI2C2_RX\nUSART3_TX\nDAC1\nDAC2\nI2C2_TX\n1.\nThese requests are available on STM32F42xxx and STM32F43xxx only. \nTable 43. DMA1 request mapping (continued)\nPeripheral \nrequests\nStream 0\nStream 1\nStream 2\nStream 3 \nStream 4\nStream 5\nStream 6\nStream 7\nTable 44. DMA2 request mapping\nPeripheral \nrequests\nStream 0\nStream 1\nStream 2\nStream 3\nStream 4\nStream 5\nStream 6\nStream 7\nChannel 0\nADC1\n-SAI1_A(1)\nTIM8_CH1\nTIM8_CH2\nTIM8_CH3\n-SAI1_A(1)\nADC1\nSAI1_B(1)-\nTIM1_CH1\nTIM1_CH2\nTIM1_CH3\n-\nChannel 1\n-\nDCMI\nADC2\nADC2\nSAI1_B(1)-\n-SPI6_TX(1)\nSPI6_RX(1)-\nDCMI\nChannel 2\nADC3\nADC3\n-\nSPI5_RX(1)-\n-SPI5_TX(1)\nCRYP_OUT\nCRYP_IN\nHASH_IN\nChannel 3\nSPI1_RX\n-\nSPI1_RX\nSPI1_TX\n-\nSPI1_TX\n-\n-\nChannel 4\nSPI4_RX(1)-\n-SPI4_TX(1)\nUSART1_RX\nSDIO\n-\nUSART1_RX\nSDIO\nUSART1_TX\nChannel 5\n-\nUSART6_RX\nUSART6_RX\nSPI4_RX(1)-\n-SPI4_TX(1)\n-\nUSART6_TX\nUSART6_TX\nChannel 6\nTIM1_TRIG\nTIM1_CH1\nTIM1_CH2\nTIM1_CH1\nTIM1_CH4\nTIM1_TRIG\nTIM1_COM\nTIM1_UP\nTIM1_CH3\n-\nChannel 7\n-\nTIM8_UP\nTIM8_CH1\nTIM8_CH2\nTIM8_CH3\nSPI5_RX(1)-\nSPI5_TX(1)-\nTIM8_CH4\nTIM8_TRIG\nTIM8_COM\n1.\nThese requests are available on STM32F42xxx and STM32F43xxx. \n\n\n<>\n\nDMA controller (DMA)\nRM0090\n312/1757\nRM0090 Rev 21\n10.3.5 \nDMA streams\nEach of the 8 DMA controller streams provides a unidirectional transfer link between a \nsource and a destination.\nEach stream can be configured to perform:\n•\nRegular type transactions: memory-to-peripherals, peripherals-to-memory or memory-\nto-memory transfers\n•\nDouble-buffer type transactions: double buffer transfers using two memory pointers for \nthe memory (while the DMA is reading/writing from/to a buffer, the application can \nwrite/read to/from the other buffer).\nThe amount of data to be transferred (up to 65535) is programmable and related to the \nsource width of the peripheral that requests the DMA transfer connected to the peripheral \nAHB port. The register that contains the amount of data items to be transferred is \ndecremented after each transaction.\n10.3.6 \nSource, destination and transfer modes\nBoth source and destination transfers can address peripherals and memories in the entire \n4 GB area, at addresses comprised between 0x0000 0000 and 0xFFFF FFFF.\nThe direction is configured using the DIR[1:0] bits in the DMA_SxCR register and offers \nthree possibilities: memory-to-peripheral, peripheral-to-memory or memory-to-memory \ntransfers. Table 45 describes the corresponding source and destination addresses.\n \nWhen the data width (programmed in the PSIZE or MSIZE bits in the DMA_SxCR register) \nis a half-word or a word, respectively, the peripheral or memory address written into the \nDMA_SxPAR or DMA_SxM0AR/M1AR registers has to be aligned on a word or half-word \naddress boundary, respectively.\nPeripheral-to-memory mode\nFigure 36 describes this mode.\nWhen this mode is enabled (by setting the bit EN in the DMA_SxCR register), each time a \nperipheral request occurs, the stream initiates a transfer from the source to fill the FIFO.\nWhen the threshold level of the FIFO is reached, the contents of the FIFO are drained and \nstored into the destination.\nThe transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral \nrequests the end of transfers (in case of a peripheral flow controller) or when the EN bit in \nthe DMA_SxCR register is cleared by software.\nTable 45. Source and destination address\nBits DIR[1:0] of the \nDMA_SxCR register\nDirection\nSource address\nDestination address\n00\nPeripheral-to-memory\nDMA_SxPAR\nDMA_SxM0AR\n01\nMemory-to-peripheral\nDMA_SxM0AR\nDMA_SxPAR\n10\nMemory-to-memory\nDMA_SxPAR\nDMA_SxM0AR\n11\nreserved\n-\n-\n\n\n<>\n\nRM0090 Rev 21\n313/1757\nRM0090\nDMA controller (DMA)\n341\nIn direct mode (when the DMDIS value in the DMA_SxFCR register is ‘0’), the threshold \nlevel of the FIFO is not used: after each single data transfer from the peripheral to the FIFO, \nthe corresponding data are immediately drained and stored into the destination.\nThe stream has access to the AHB source or destination port only if the arbitration of the \ncorresponding stream is won. This arbitration is performed using the priority defined for \neach stream using the PL[1:0] bits in the DMA_SxCR register.\nFigure 36. Peripheral-to-memory mode\n1.\nFor double-buffer mode.\nMemory-to-peripheral mode\nFigure 37 describes this mode.\nWhen this mode is enabled (by setting the EN bit in the DMA_SxCR register), the stream \nimmediately initiates transfers from the source to entirely fill the FIFO.\nEach time a peripheral request occurs, the contents of the FIFO are drained and stored into \nthe destination. When the level of the FIFO is lower than or equal to the predefined \nthreshold level, the FIFO is fully reloaded with data from the memory.\nThe transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral \nrequests the end of transfers (in case of a peripheral flow controller) or when the EN bit in \nthe DMA_SxCR register is cleared by software.\nIn direct mode (when the DMDIS value in the DMA_SxFCR register is '0'), the threshold \nlevel of the FIFO is not used. Once the stream is enabled, the DMA preloads the first data to \ntransfer into an internal FIFO. As soon as the peripheral requests a data transfer, the DMA \ntransfers the preloaded value into the configured destination. It then reloads again the \nPeripheral bus\nREQ_STREAMx\nArbiter\nFIFO\nAHB peripheral\nport\nMemory bus\nMemory\ndestination\nFIFO\nlevel\nPeripheral\nsource\nDMA_SxPAR\nPeripheral DMA request\nDMA controller\nDMA_SxM0AR\nDMA_SxM1AR(1)\nAHB memory\nport\nMS47543V1\n\n\n<>\n\nDMA controller (DMA)\nRM0090\n314/1757\nRM0090 Rev 21\nempty internal FIFO with the next data to be transfer. The preloaded data size corresponds \nto the value of the PSIZE bitfield in the DMA_SxCR register. \nThe stream has access to the AHB source or destination port only if the arbitration of the \ncorresponding stream is won. This arbitration is performed using the priority defined for \neach stream using the PL[1:0] bits in the DMA_SxCR register.\nFigure 37. Memory-to-peripheral mode\n1.\nFor double-buffer mode.\nMemory-to-memory mode\nThe DMA channels can also work without being triggered by a request from a peripheral. \nThis is the memory-to-memory mode, described in Figure 38.\nWhen the stream is enabled by setting the Enable bit (EN) in the DMA_SxCR register, the \nstream immediately starts to fill the FIFO up to the threshold level. When the threshold level \nis reached, the FIFO contents are drained and stored into the destination.\nThe transfer stops once the DMA_SxNDTR register reaches zero or when the EN bit in the \nDMA_SxCR register is cleared by software.\nThe stream has access to the AHB source or destination port only if the arbitration of the \ncorresponding stream is won. This arbitration is performed using the priority defined for \neach stream using the PL[1:0] bits in the DMA_SxCR register.\nNote:\nWhen memory-to-memory mode is used, the Circular and direct modes are not allowed.\nOnly the DMA2 controller is able to perform memory-to-memory transfers.\nPeripheral bus\nMemory bus\nREQ_STREAMx\nArbiter\nDMA_SxM1AR(1)\nFIFO\nAHB memory\nport\nAHB peripheral\nport\nDMA_SxPAR\nFIFO\nlevel\nDMA controller\nDMA_SxM0AR\nsource\ndestination\nPeripheral\nMemory\nPeripheral DMA request\nai15949\n\n\n<>\n\nRM0090 Rev 21\n315/1757\nRM0090\nDMA controller (DMA)\n341\nFigure 38. Memory-to-memory mode\n1.\nFor double-buffer mode.\n10.3.7 \nPointer incrementation\nPeripheral and memory pointers can optionally be automatically post-incremented or kept \nconstant after each transfer depending on the PINC and MINC bits in the DMA_SxCR \nregister.\nDisabling the Increment mode is useful when the peripheral source or destination data are \naccessed through a single register.\nIf the Increment mode is enabled, the address of the next transfer is the address of the \nprevious one incremented by 1 (for bytes), 2 (for half-words) or 4 (for words) depending on \nthe data width programmed in the PSIZE or MSIZE bits in the DMA_SxCR register.\nIn order to optimize the packing operation, it is possible to fix the increment offset size for \nthe peripheral address whatever the size of the data transferred on the AHB peripheral port. \nThe PINCOS bit in the DMA_SxCR register is used to align the increment offset size with \nthe data size on the peripheral AHB port, or on a 32-bit address (the address is then \nincremented by 4). The PINCOS bit has an impact on the AHB peripheral port only.\nIf PINCOS bit is set, the address of the next transfer is the address of the previous one \nincremented by 4 (automatically aligned on a 32-bit address) whatever the PSIZE value. \nThe AHB memory port, however, is not impacted by this operation.\nMemory bus\nPeripheral bus\nStream enable\nArbiter\nDMA_SxM1AR(1)\nFIFO\nAHB memory\nport\nAHB peripheral\nport\nDMA_SxPAR\nFIFO\nlevel\nDMA controller\nDMA_SxM0AR\ndestination\nsource\nMemory 1\nMemory 2\nFIFO\nai15950\n\n\n<>\n\nDMA controller (DMA)\nRM0090\n316/1757\nRM0090 Rev 21\n10.3.8 \nCircular mode\nThe Circular mode is available to handle circular buffers and continuous data flows (e.g. \nADC scan mode). This feature can be enabled using the CIRC bit in the DMA_SxCR \nregister.\nWhen the circular mode is activated, the number of data items to be transferred is \nautomatically reloaded with the initial value programmed during the stream configuration \nphase, and the DMA requests continue to be served.\nNote:\nIn the circular mode, it is mandatory to respect the following rule in case of a burst mode \nconfigured for memory:\nDMA_SxNDTR = Multiple of ((Mburst beat) × (Msize)/(Psize)), where:\n–\n(Mburst beat) = 4, 8 or 16 (depending on the MBURST bits in the DMA_SxCR \nregister)\n–\n((Msize)/(Psize)) = 1, 2, 4, 1/2 or 1/4 (Msize and Psize represent the MSIZE and \nPSIZE bits in the DMA_SxCR register. They are byte dependent)\n–\nDMA_SxNDTR = Number of data items to transfer on the AHB peripheral port\nFor example: Mburst beat = 8 (INCR8), MSIZE = ‘00’ (byte) and PSIZE = ‘01’ (half-word), in \nthis case: DMA_SxNDTR must be a multiple of (8 × 1/2 = 4).\nIf this formula is not respected, the DMA behavior and data integrity are not guaranteed.\nNDTR must also be a multiple of the Peripheral burst size multiplied by the peripheral data \nsize, otherwise this could result in a bad DMA behavior.\n10.3.9 \nDouble buffer mode\nThis mode is available for all the DMA1 and DMA2 streams.\nThe Double buffer mode is enabled by setting the DBM bit in the DMA_SxCR register.\nA double-buffer stream works as a regular (single buffer) stream with the difference that it \nhas two memory pointers. When the Double buffer mode is enabled, the Circular mode is \nautomatically enabled (CIRC bit in DMA_SxCR is don’t care) and at each end of transaction, \nthe memory pointers are swapped.\nIn this mode, the DMA controller swaps from one memory target to another at each end of \ntransaction. This allows the software to process one memory area while the second memory \narea is being filled/used by the DMA transfer. The double-buffer stream can work in both \ndirections (the memory can be either the source or the destination) as described in \nTable 46: Source and destination address registers in Double buffer mode (DBM=1).\nNote:\nIn Double buffer mode, it is possible to update the base address for the AHB memory port \non-the-fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled, by respecting the \nfollowing conditions:\n•\nWhen the CT bit is ‘0’ in the DMA_SxCR register, the DMA_SxM1AR register can be \nwritten. Attempting to write to this register while CT = '1' sets an error flag (TEIF) and \nthe stream is automatically disabled.\n•\nWhen the CT bit is ‘1’ in the DMA_SxCR register, the DMA_SxM0AR register can be \nwritten. Attempting to write to this register while CT = '0', sets an error flag (TEIF) and \nthe stream is automatically disabled.\nTo avoid any error condition, it is advised to change the base address as soon as the TCIF \nflag is asserted because, at this point, the targeted memory must have changed from \n\n\n<>\n\nRM0090 Rev 21\n317/1757\nRM0090\nDMA controller (DMA)\n341\nmemory 0 to 1 (or from 1 to 0) depending on the value of CT in the DMA_SxCR register in \naccordance with one of the two above conditions.\nFor all the other modes (except the Double buffer mode), the memory address registers are \nwrite-protected as soon as the stream is enabled.\n \n10.3.10 \nProgrammable data width, packing/unpacking, endianess\nThe number of data items to be transferred has to be programmed into DMA_SxNDTR \n(number of data items to transfer bit, NDT) before enabling the stream (except when the \nflow controller is the peripheral, PFCTRL bit in DMA_SxCR is set).\nWhen using the internal FIFO, the data widths of the source and destination data are \nprogrammable through the PSIZE and MSIZE bits in the DMA_SxCR register (can be 8-, \n16- or 32-bit).\nWhen PSIZE and MSIZE are not equal:\n•\nThe data width of the number of data items to transfer, configured in the DMA_SxNDTR \nregister is equal to the width of the peripheral bus (configured by the PSIZE bits in the \nDMA_SxCR register). For instance, in case of peripheral-to-memory, memory-to-\nperipheral or memory-to-memory transfers and if the PSIZE[1:0] bits are configured for \nhalf-word, the number of bytes to be transferred is equal to 2 × NDT.\n•\nThe DMA controller only copes with little-endian addressing for both source and \ndestination. This is described in Table 47: Packing/unpacking & endian behavior (bit \nPINC = MINC = 1).\nThis packing/unpacking procedure may present a risk of data corruption when the operation \nis interrupted before the data are completely packed/unpacked. So, to ensure data \ncoherence, the stream may be configured to generate burst transfers: in this case, each \ngroup of transfers belonging to a burst are indivisible (refer to Section 10.3.11: Single and \nburst transfers).\nIn direct mode (DMDIS = 0 in the DMA_SxFCR register), the packing/unpacking of data is \nnot possible. In this case, it is not allowed to have different source and destination transfer \ndata widths: both are equal and defined by the PSIZE bits in the DMA_SxCR MSIZE bits are \ndon’t care).\nTable 46. Source and destination address registers in Double buffer mode (DBM=1)\nBits DIR[1:0] of the \nDMA_SxCR register\nDirection\nSource address\nDestination address\n00\nPeripheral-to-memory\nDMA_SxPAR\nDMA_SxM0AR / \nDMA_SxM1AR\n01\nMemory-to-peripheral\nDMA_SxM0AR / \nDMA_SxM1AR\nDMA_SxPAR\n10\nNot allowed(1)\n1.\nWhen the Double buffer mode is enabled, the Circular mode is automatically enabled. Since the memory-\nto-memory mode is not compatible with the Circular mode, when the Double buffer mode is enabled, it is \nnot allowed to configure the memory-to-memory mode.\n11\nReserved\n-\n-\n\n\n<>\n\nDMA controller (DMA)\nRM0090\n318/1757\nRM0090 Rev 21\n \nNote:\nPeripheral port may be the source or the destination (it could also be the memory source in \nthe case of memory-to-memory transfer).\nPSIZE, MSIZE and NDT[15:0] have to be configured so as to ensure that the last transfer is \nnot incomplete. This can occur when the data width of the peripheral port (PSIZE bits) is \nlower than the data width of the memory port (MSIZE bits). This constraint is summarized in \nTable 48.\nTable 47. Packing/unpacking & endian behavior (bit PINC = MINC = 1)\nAHB \nmemory \nport \nwidth\nAHB \nperipheral \nport width\nNumber \nof data \nitems to \ntransfer \n(NDT)\n-\nMemory \ntransfer \nnumber\nMemory port \naddress / byte \nlane\nPeripher\nal \ntransfer \nnumber\nPeripheral port address / byte lane\n-\nPINCOS = 1\nPINCOS = 0\n8\n8\n4\n-\n1\n2\n3\n4\n0x0 / B0[7:0]\n0x1 / B1[7:0]\n0x2 / B2[7:0]\n0x3 / B3[7:0]\n1\n2\n3\n4\n0x0 / B0[7:0]\n0x4 / B1[7:0]\n0x8 / B2[7:0]\n0xC / B3[7:0]\n0x0 / B0[7:0]\n0x1 / B1[7:0]\n0x2 / B2[7:0]\n0x3 / B3[7:0]\n8\n16\n2\n-\n1\n2\n3\n4\n0x0 / B0[7:0]\n0x1 / B1[7:0]\n0x2 / B2[7:0]\n0x3 / B3[7:0]\n1\n2\n0x0 / B1|B0[15:0]\n0x4 / B3|B2[15:0]\n0x0 / B1|B0[15:0]\n0x2 / B3|B2[15:0]\n8\n32\n1\n-\n1\n2\n3\n4\n0x0 / B0[7:0]\n0x1 / B1[7:0]\n0x2 / B2[7:0]\n0x3 / B3[7:0]\n1\n0x0 / B3|B2|B1|B0[31:0]\n0x0 / B3|B2|B1|B0[31:0]\n16\n8\n4\n-\n1\n2\n0x0 / B1|B0[15:0]\n0x2 / B3|B2[15:0]\n1\n2\n3\n4\n0x0 / B0[7:0]\n0x4 / B1[7:0]\n0x8 / B2[7:0]\n0xC / B3[7:0]\n0x0 / B0[7:0]\n0x1 / B1[7:0]\n0x2 / B2[7:0]\n0x3 / B3[7:0]\n16\n16\n2\n-\n1\n2\n0x0 / B1|B0[15:0]\n0x2 / B1|B0[15:0]\n1\n2\n0x0 / B1|B0[15:0]\n0x4 / B3|B2[15:0]\n0x0 / B1|B0[15:0]\n0x2 / B3|B2[15:0]\n16\n32\n1\n-\n1\n2\n0x0 / B1|B0[15:0]\n0x2 / B3|B2[15:0]\n1\n0x0 / B3|B2|B1|B0[31:0]\n0x0 / B3|B2|B1|B0[31:0]\n32\n8\n4\n-\n1\n0x0 / B3|B2|B1|B0[31:0]\n1\n2\n3\n4\n0x0 / B0[7:0]\n0x4 / B1[7:0]\n0x8 / B2[7:0]\n0xC / B3[7:0]\n0x0 / B0[7:0]\n0x1 / B1[7:0]\n0x2 / B2[7:0]\n0x3 / B3[7:0]\n32\n16\n2\n-\n1\n0x0 /B3|B2|B1|B0[31:0]\n1\n2 \n0x0 / B1|B0[15:0]\n0x4 / B3|B2[15:0]\n0x0 / B1|B0[15:0]\n0x2 / B3|B2[15:0]\n32\n32\n1\n- 1\n0x0 /B3|B2|B1|B0 [31:0]\n1\n0x0 /B3|B2|B1|B0 [31:0]\n0x0 / B3|B2|B1|B0[31:0]\n\n\n<>\n\nRM0090 Rev 21\n319/1757\nRM0090\nDMA controller (DMA)\n341\n \n10.3.11 \nSingle and burst transfers\nThe DMA controller can generate single transfers or incremental burst transfers of 4, 8 or 16 \nbeats. \nThe size of the burst is configured by software independently for the two AHB ports by using \nthe MBURST[1:0] and PBURST[1:0] bits in the DMA_SxCR register.\nThe burst size indicates the number of beats in the burst, not the number of bytes \ntransferred.\nTo ensure data coherence, each group of transfers that form a burst are indivisible: AHB \ntransfers are locked and the arbiter of the AHB bus matrix does not degrant the DMA master \nduring the sequence of the burst transfer.\nDepending on the single or burst configuration, each DMA request initiates a different \nnumber of transfers on the AHB peripheral port:\n•\nWhen the AHB peripheral port is configured for single transfers, each DMA request \ngenerates a data transfer of a byte, half-word or word depending on the PSIZE[1:0] bits \nin the DMA_SxCR register\n•\nWhen the AHB peripheral port is configured for burst transfers, each DMA request \ngenerates 4,8 or 16 beats of byte, half word or word transfers depending on the \nPBURST[1:0] and PSIZE[1:0] bits in the DMA_SxCR register.\nThe same as above has to be considered for the AHB memory port considering the \nMBURST and MSIZE bits.\nIn direct mode, the stream can only generate single transfers and the MBURST[1:0] and \nPBURST[1:0] bits are forced by hardware.\nThe address pointers (DMA_SxPAR or DMA_SxM0AR registers) must be chosen so as to \nensure that all transfers within a burst block are aligned on the address boundary equal to \nthe size of the transfer.\nThe burst configuration has to be selected in order to respect the AHB protocol, where \nbursts must not cross the 1 KB address boundary because the minimum address space that \ncan be allocated to a single slave is 1 KB. This means that the 1 KB address boundary \nshould not be crossed by a burst block transfer, otherwise an AHB error would be \ngenerated, that is not reported by the DMA registers.\nTable 48. Restriction on NDT versus PSIZE and MSIZE\nPSIZE[1:0] of DMA_SxCR\nMSIZE[1:0] of DMA_SxCR\nNDT[15:0] of DMA_SxNDTR\n00 (8-bit)\n01 (16-bit)\nmust be a multiple of 2\n00 (8-bit)\n10 (32-bit)\nmust be a multiple of 4\n01 (16-bit)\n10 (32-bit)\nmust be a multiple of 2\n\n\n<>\n\nDMA controller (DMA)\nRM0090\n320/1757\nRM0090 Rev 21\n10.3.12 \nFIFO\nFIFO structure\nThe FIFO is used to temporarily store data coming from the source before transmitting them \nto the destination.\nEach stream has an independent 4-word FIFO and the threshold level is software-\nconfigurable between 1/4, 1/2, 3/4 or full.\nTo enable the use of the FIFO threshold level, the direct mode must be disabled by setting \nthe DMDIS bit in the DMA_SxFCR register.\nThe structure of the FIFO differs depending on the source and destination data widths, and \nis described in Figure 39: FIFO structure.\nFigure 39. FIFO structure \nSource: byte\n4 words\nbyte lane 0\nbyte lane 1\nbyte lane 2\nbyte lane 3\n1/4\n1/2\n3/4\nFull\nEmpty\nB0\nB1\nB2\nB3\nB4\nB5\nB6\nB7\nB8\nB9\nB10\nB 11\nB12\nB13\nB14\nB15\nDestination: word\nSource: byte\nDestination: half-word\n4 words\nbyte lane 0\nbyte lane 1\nbyte lane 2\nbyte lane 3\n1/4\n1/2\n3/4\nFull\nEmpty\nB0\nB1\nB2\nB3\nB4\nB5\nB6\nB7\nB8\nB9\nB10\nB 11\nB12\nB13\nB14\nB15\nW0\nW1\nW2\nW3\nH0\nH1\nH2\nH3\nH4\nH5\nH6\nH7\nSource: half-word\nDestination: word\n4 words\nbyte lane 0\nbyte lane 1\nbyte lane 2\nbyte lane 3\n1/4\n1/2\n3/4\nFull\nEmpty\nH0\nW0\nW1\nW2\nW3\nH1\nH2\nH3\nH4\nH5\nH6\nH7\nB15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0\nB15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0\nH7 H6 H5 H4 H3 H2 H1 H0\nH7, H6, H5, H4, H3, H2, H1, H0\nW3, W2, W1, W0\nW3, W2, W1, W0\nSource: half-word\n4-words\nbyte lane 0\nbyte lane 1\nbyte lane 2\nbyte lane 3\n1/4\n1/2\n3/4\nFull\nEmpty\nDestination: byte\nH7 H6 H5 H4 H3 H2 H1 H0\nB0\nB1\nB2\nB3\nB4\nB5\nB6\nB7\nB8\nB9\nB10\nB 11\nB12\nB13\nB14\nB15\nH0\nH1\nH2\nH3\nH4\nH5\nH6\nH7\nB15 B14 B13 B12 B11 B10 B9 B8 \nB7 B6 B5 B4 B3 B2 B1 B0\nai15951\n\n\n<>\n\nRM0090 Rev 21\n321/1757\nRM0090\nDMA controller (DMA)\n341\nFIFO threshold and burst configuration\nCaution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR \nregister) and the size of the memory burst (MBURST[1:0] of the DMA_SxCR register): The \ncontent pointed by the FIFO threshold must exactly match to an integer number of memory \nburst transfers. If this is not in the case, a FIFO error (flag FEIFx of the DMA_HISR or \nDMA_LISR register) is generated when the stream is enabled, then the stream is \nautomatically disabled. The allowed and forbidden configurations are described in the \nTable 49: FIFO threshold configurations.\n \nIn all cases, the burst size multiplied by the data size must not exceed the FIFO size (data \nsize can be: 1 (byte), 2 (half-word) or 4 (word)).\nIncomplete Burst transfer at the end of a DMA transfer may happen if one of the following \nconditions occurs:\n•\nFor the AHB peripheral port configuration: the total number of data items (set in the \nDMA_SxNDTR register) is not a multiple of the burst size multiplied by the data size\n•\nFor the AHB memory port configuration: the number of remaining data items in the \nFIFO to be transferred to the memory is not a multiple of the burst size multiplied by the \ndata size\nIn such cases, the remaining data to be transferred is managed in single mode by the DMA, \neven if a burst transaction was requested during the DMA stream configuration.\nNote:\nWhen burst transfers are requested on the peripheral AHB port and the FIFO is used \n(DMDIS = 1 in the DMA_SxCR register), it is mandatory to respect the following rule to \navoid permanent underrun or overrun conditions, depending on the DMA stream direction:\nIf (PBURST × PSIZE) = FIFO_SIZE (4 words), FIFO_Threshold = 3/4 is forbidden with \nPSIZE = 1, 2 or 4 and PBURST = 4, 8 or 16.\nThis rule ensures that enough FIFO space at a time is free to serve the request from the \nperipheral.\nTable 49. FIFO threshold configurations\nMSIZE\nFIFO level\nMBURST = INCR4\nMBURST = INCR8\nMBURST = INCR16\nByte\n1/4\n1 burst of 4 beats\nforbidden\nforbidden\n1/2\n2 bursts of 4 beats\n1 burst of 8 beats\n3/4\n3 bursts of 4 beats\nforbidden\nFull\n4 bursts of 4 beats\n2 bursts of 8 beats\n1 burst of 16 beats\nHalf-word\n1/4\nforbidden\nforbidden\nforbidden\n1/2\n1 burst of 4 beats\n3/4\nforbidden\nFull\n2 bursts of 4 beats\n1 burst of 8 beats\nWord\n1/4\nforbidden\nforbidden\n1/2\n3/4\nFull\n1 burst of 4 beats\n\n\n<>\n\nDMA controller (DMA)\nRM0090\n322/1757\nRM0090 Rev 21\nFIFO flush\nThe FIFO can be flushed when the stream is disabled by resetting the EN bit in the \nDMA_SxCR register and when the stream is configured to manage peripheral-to-memory or \nmemory-to-memory transfers: If some data are still present in the FIFO when the stream is \ndisabled, the DMA controller continues transferring the remaining data to the destination \n(even though stream is effectively disabled). When this flush is completed, the transfer \ncomplete status bit (TCIFx) in the DMA_LISR or DMA_HISR register is set.\nThe remaining data counter DMA_SxNDTR keeps the value in this case to indicate how \nmany data items are currently available in the destination memory.\nNote that during the FIFO flush operation, if the number of remaining data items in the FIFO \nto be transferred to memory (in bytes) is less than the memory data width (for example 2 \nbytes in FIFO while MSIZE is configured to word), data is sent with the data width set in the \nMSIZE bit in the DMA_SxCR register. This means that memory is written with an undesired \nvalue. The software may read the DMA_SxNDTR register to determine the memory area \nthat contains the good data (start address and last address).\nIf the number of remaining data items in the FIFO is lower than a burst size (if the MBURST \nbits in DMA_SxCR register are set to configure the stream to manage burst on the AHB \nmemory port), single transactions are generated to complete the FIFO flush.\nDirect mode\nBy default, the FIFO operates in direct mode (DMDIS bit in the DMA_SxFCR is reset) and \nthe FIFO threshold level is not used. This mode is useful when the system requires an \nimmediate and single transfer to or from the memory after each DMA request.\nWhen the DMA is configured in direct mode (FIFO disabled), to transfer data in memory-to-\nperipheral mode, the DMA preloads one data from the memory to the internal FIFO to \nensure an immediate data transfer as soon as a DMA request is triggered by a peripheral.\nTo avoid saturating the FIFO, it is recommended to configure the corresponding stream with \na high priority.\nThis mode is restricted to transfers where:\n•\nThe source and destination transfer widths are equal and both defined by the \nPSIZE[1:0] bits in DMA_SxCR (MSIZE[1:0] bits are don’t care)\n•\nBurst transfers are not possible (PBURST[1:0] and MBURST[1:0] bits in DMA_SxCR \nare don’t care)\nDirect mode must not be used when implementing memory-to-memory transfers.\n10.3.13 \nDMA transfer completion\nDifferent events can generate an end of transfer by setting the TCIFx bit in the DMA_LISR \nor DMA_HISR status register:\n•\nIn DMA flow controller mode:\n–\nThe DMA_SxNDTR counter has reached zero in the memory-to-peripheral mode\n–\nThe stream is disabled before the end of transfer (by clearing the EN bit in the \nDMA_SxCR register) and (when transfers are peripheral-to-memory or memory-\n\n\n<>\n\nRM0090 Rev 21\n323/1757\nRM0090\nDMA controller (DMA)\n341\nto-memory) all the remaining data have been flushed from the FIFO into the \nmemory\n•\nIn Peripheral flow controller mode:\n–\nThe last external burst or single request has been generated from the peripheral \nand (when the DMA is operating in peripheral-to-memory mode) the remaining \ndata have been transferred from the FIFO into the memory\n–\nThe stream is disabled by software, and (when the DMA is operating in peripheral-\nto-memory mode) the remaining data have been transferred from the FIFO into \nthe memory\nNote:\nThe transfer completion is dependent on the remaining data in FIFO to be transferred into \nmemory only in the case of peripheral-to-memory mode. This condition is not applicable in \nmemory-to-peripheral mode.\nIf the stream is configured in noncircular mode, after the end of the transfer (that is when the \nnumber of data to be transferred reaches zero), the DMA is stopped (EN bit in DMA_SxCR \nregister is cleared by Hardware) and no DMA request is served unless the software \nreprograms the stream and re-enables it (by setting the EN bit in the DMA_SxCR register).\n10.3.14 \nDMA transfer suspension\nAt any time, a DMA transfer can be suspended to be restarted later on or to be definitively \ndisabled before the end of the DMA transfer.\nThere are two cases:\n•\nThe stream disables the transfer with no later-on restart from the point where it was \nstopped. There is no particular action to do, except to clear the EN bit in the \nDMA_SxCR register to disable the stream. The stream may take time to be disabled \n(ongoing transfer is completed first). The transfer complete interrupt flag (TCIF in the \nDMA_LISR or DMA_HISR register) is set in order to indicate the end of transfer. The \nvalue of the EN bit in DMA_SxCR is now ‘0’ to confirm the stream interruption. The \nDMA_SxNDTR register contains the number of remaining data items at the moment \nwhen the stream was stopped so that the software can determine how many data items \nhave been transferred before the stream was interrupted.\n•\nThe stream suspends the transfer before the number of remaining data items to be \ntransferred in the DMA_SxNDTR register reaches 0. The aim is to restart the transfer \nlater by re-enabling the stream. In order to restart from the point where the transfer was \nstopped, the software has to read the DMA_SxNDTR register after disabling the stream \nby writing the EN bit in DMA_SxCR register (and then checking that it is at ‘0’) to know \nthe number of data items already collected. Then:\n–\nThe peripheral and/or memory addresses have to be updated in order to adjust \nthe address pointers\n–\nThe SxNDTR register has to be updated with the remaining number of data items \nto be transferred (the value read when the stream was disabled)\n–\nThe stream may then be re-enabled to restart the transfer from the point it was \nstopped\nNote:\nNote that a Transfer complete interrupt flag (TCIF in DMA_LISR or DMA_HISR) is set to \nindicate the end of transfer due to the stream interruption.\n\n\n<>\n\nDMA controller (DMA)\nRM0090\n324/1757\nRM0090 Rev 21\n10.3.15 \nFlow controller\nThe entity that controls the number of data to be transferred is known as the flow controller. \nThis flow controller is configured independently for each stream using the PFCTRL bit in the \nDMA_SxCR register.\nThe flow controller can be:\n•\nThe DMA controller: in this case, the number of data items to be transferred is \nprogrammed by software into the DMA_SxNDTR register before the DMA stream is \nenabled.\n•\nThe peripheral source or destination: this is the case when the number of data items to \nbe transferred is unknown. The peripheral indicates by hardware to the DMA controller \nwhen the last data are being transferred. This feature is only supported for peripherals \nwhich are able to signal the end of the transfer, that is:\n–\nSDIO\nWhen the peripheral flow controller is used for a given stream, the value written into the \nDMA_SxNDTR has no effect on the DMA transfer. Actually, whatever the value written, it is \nforced by hardware to 0xFFFF as soon as the stream is enabled, to respect the following \nschemes:\n•\nAnticipated stream interruption: EN bit in DMA_SxCR register is reset to 0 by the \nsoftware to stop the stream before the last data hardware signal (single or burst) is sent \nby the peripheral. In such a case, the stream is switched off and the FIFO flush is \ntriggered in the case of a peripheral-to-memory DMA transfer. The TCIFx flag of the \ncorresponding stream is set in the status register to indicate the DMA completion. To \nknow the number of data items transferred during the DMA transfer, read the \nDMA_SxNDTR register and apply the following formula:\n–\nNumber_of_data_transferred = 0xFFFF – DMA_SxNDTR\n•\nNormal stream interruption due to the reception of a last data hardware signal: the \nstream is automatically interrupted when the peripheral requests the last transfer \n(single or burst) and when this transfer is complete. the TCIFx flag of the corresponding \nstream is set in the status register to indicate the DMA transfer completion. To know the \nnumber of data items transferred, read the DMA_SxNDTR register and apply the same \nformula as above.\n•\nThe DMA_SxNDTR register reaches 0: the TCIFx flag of the corresponding stream is \nset in the status register to indicate the forced DMA transfer completion. The stream is \nautomatically switched off even though the last data hardware signal (single or burst) \nhas not been yet asserted. The already transferred data are not lost. This means that a \nmaximum of 65535 data items can be managed by the DMA in a single transaction, \neven in peripheral flow control mode.\nNote:\nWhen configured in memory-to-memory mode, the DMA is always the flow controller and \nthe PFCTRL bit is forced to 0 by hardware.\nThe Circular mode is forbidden in the peripheral flow controller mode.\n\n\n<>\n\nRM0090 Rev 21\n325/1757\nRM0090\nDMA controller (DMA)\n341\n10.3.16 \nSummary of the possible DMA configurations\nTable 50 summarizes the different possible DMA configurations.\n \n10.3.17 \nStream configuration procedure\nThe following sequence should be followed to configure a DMA stream x (where x is the \nstream number):\n1.\nIf the stream is enabled, disable it by resetting the EN bit in the DMA_SxCR register, \nthen read this bit in order to confirm that there is no ongoing stream operation. Writing \nthis bit to 0 is not immediately effective since it is actually written to 0 once all the \ncurrent transfers have finished. When the EN bit is read as 0, this means that the \nstream is ready to be configured. It is therefore necessary to wait for the EN bit to be \ncleared before starting any stream configuration. All the stream dedicated bits set in the \nstatus register (DMA_LISR and DMA_HISR) from the previous data block DMA \ntransfer should be cleared before the stream can be re-enabled.\n2. \nSet the peripheral port register address in the DMA_SxPAR register. The data are \nmoved from/ to this address to/ from the peripheral port after the peripheral event.\n3. \nSet the memory address in the DMA_SxMA0R register (and in the DMA_SxMA1R \nregister in the case of a double buffer mode). The data are written to or read from this \nmemory after the peripheral event.\n4. \nConfigure the total number of data items to be transferred in the DMA_SxNDTR \nregister. After each peripheral event or each beat of the burst, this value is \ndecremented.\n5. \nSelect the DMA channel (request) using CHSEL[2:0] in the DMA_SxCR register.\n6. \nIf the peripheral is intended to be the flow controller and if it supports this feature, set \nthe PFCTRL bit in the DMA_SxCR register.\n7. \nConfigure the stream priority using the PL[1:0] bits in the DMA_SxCR register.\n8. \nConfigure the FIFO usage (enable or disable, threshold in transmission and reception)\n9. \nConfigure the data transfer direction, peripheral and memory incremented/fixed mode, \nsingle or burst transactions, peripheral and memory data widths, Circular mode, \nTable 50. Possible DMA configurations\nDMA transfer \nmode\nSource\nDestination\nFlow \ncontroller\nCircular \nmode\nTransfer \ntype\nDirect \nmode\nDouble \nbuffer mode\nPeripheral-to-\nmemory\nAHB\nperipheral port\nAHB\nmemory port\nDMA\npossible\nsingle\npossible\npossible\nburst\nforbidden\nPeripheral\nforbidden\nsingle\npossible\nforbidden\nburst\nforbidden\nMemory-to-\nperipheral\nAHB \nmemory port\nAHB \nperipheral port\nDMA\npossible\nsingle\npossible\npossible\nburst\nforbidden\nPeripheral\nforbidden\nsingle\npossible\nforbidden\nburst\nforbidden\nMemory-to-\nmemory\nAHB\nperipheral port\nAHB \nmemory port\nDMA only \nforbidden\nsingle\nforbidden\nforbidden\nburst\n\n\n<>\n\nDMA controller (DMA)\nRM0090\n326/1757\nRM0090 Rev 21\nDouble buffer mode and interrupts after half and/or full transfer, and/or errors in the \nDMA_SxCR register.\n10. Activate the stream by setting the EN bit in the DMA_SxCR register.\nAs soon as the stream is enabled, it can serve any DMA request from the peripheral \nconnected to the stream.\nOnce half the data have been transferred on the AHB destination port, the half-transfer flag \n(HTIF) is set and an interrupt is generated if the half-transfer interrupt enable bit (HTIE) is \nset. At the end of the transfer, the transfer complete flag (TCIF) is set and an interrupt is \ngenerated if the transfer complete interrupt enable bit (TCIE) is set.\nWarning:\nTo switch off a peripheral connected to a DMA stream \nrequest, it is mandatory to, first, switch off the DMA stream to \nwhich the peripheral is connected, then to wait for EN bit = 0. \nOnly then can the peripheral be safely disabled.\n10.3.18 \nError management\nThe DMA controller can detect the following errors:\n•\nTransfer error: the transfer error interrupt flag (TEIFx) is set when:\n–\nA bus error occurs during a DMA read or a write access\n–\nA write access is requested by software on a memory address register in Double \nbuffer mode whereas the stream is enabled and the current target memory is the \none impacted by the write into the memory address register (refer to \nSection 10.3.9: Double buffer mode)\n•\nFIFO error: the FIFO error interrupt flag (FEIFx) is set if:\n–\nA FIFO underrun condition is detected\n–\nA FIFO overrun condition is detected (no detection in memory-to-memory mode \nbecause requests and transfers are internally managed by the DMA)\n–\nThe stream is enabled while the FIFO threshold level is not compatible with the \nsize of the memory burst (refer to Table 49: FIFO threshold configurations)\n•\nDirect mode error: the direct mode error interrupt flag (DMEIFx) can only be set in the \nperipheral-to-memory mode while operating in direct mode and when the MINC bit in \nthe DMA_SxCR register is cleared. This flag is set when a DMA request occurs while \nthe previous data have not yet been fully transferred into the memory (because the \nmemory bus was not granted). In this case, the flag indicates that 2 data items were be \ntransferred successively to the same destination address, which could be an issue if \nthe destination is not able to manage this situation\nIn direct mode, the FIFO error flag can also be set under the following conditions:\n•\nIn the peripheral-to-memory mode, the FIFO can be saturated (overrun) if the memory \nbus is not granted for several peripheral requests\n•\nIn the memory-to-peripheral mode, an underrun condition may occur if the memory bus \nhas not been granted before a peripheral request occurs\nIf the TEIFx or the FEIFx flag is set due to incompatibility between burst size and FIFO \nthreshold level, the faulty stream is automatically disabled through a hardware clear of its \nEN bit in the corresponding stream configuration register (DMA_SxCR).\n\n\n<>\n\nRM0090 Rev 21\n327/1757\nRM0090\nDMA controller (DMA)\n341\nIf the DMEIFx or the FEIFx flag is set due to an overrun or underrun condition, the faulty \nstream is not automatically disabled and it is up to the software to disable or not the stream \nby resetting the EN bit in the DMA_SxCR register. This is because there is no data loss \nwhen this kind of errors occur.\nWhen the stream's error interrupt flag (TEIF, FEIF, DMEIF) in the DMA_LISR or DMA_HISR \nregister is set, an interrupt is generated if the corresponding interrupt enable bit (TEIE, \nFEIE, DMIE) in the DMA_SxCR or DMA_SxFCR register is set.\nNote:\nWhen a FIFO overrun or underrun condition occurs, the data are not lost because the \nperipheral request is not acknowledged by the stream until the overrun or underrun \ncondition is cleared. If this acknowledge takes too much time, the peripheral itself may \ndetect an overrun or underrun condition of its internal buffer and data might be lost.\n10.4 \nDMA interrupts\nFor each DMA stream, an interrupt can be produced on the following events:\n•\nHalf-transfer reached\n•\nTransfer complete\n•\nTransfer error\n•\nFifo error (overrun, underrun or FIFO level error)\n•\nDirect mode error\nSeparate interrupt enable control bits are available for flexibility as shown in Table 51.\n \nNote:\nBefore setting an Enable control bit to ‘1’, the corresponding event flag should be cleared, \notherwise an interrupt is immediately generated.\nTable 51. DMA interrupt requests\nInterrupt event\nEvent flag\nEnable control bit\nHalf-transfer\nHTIF\nHTIE\nTransfer complete\nTCIF\nTCIE\nTransfer error\nTEIF\nTEIE\nFIFO overrun/underrun\nFEIF\nFEIE\nDirect mode error\nDMEIF\nDMEIE\n\n\n<>\n\nDMA controller (DMA)\nRM0090\n328/1757\nRM0090 Rev 21\n10.5 \nDMA registers\nThe DMA registers have to be accessed by words (32 bits). \n10.5.1 \nDMA low interrupt status register (DMA_LISR)\nAddress offset: 0x00\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTCIF3\nHTIF3\nTEIF3\nDMEIF3\nReserv\ned\nFEIF3\nTCIF2\nHTIF2\nTEIF2\nDMEIF2\nReserv\ned\nFEIF2\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTCIF1\nHTIF1\nTEIF1\nDMEIF1\nReserv\ned\nFEIF1\nTCIF0\nHTIF0\nTEIF0\nDMEIF0\nReserv\ned\nFEIF0\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:28, 15:12 Reserved, must be kept at reset value.\nBits 27, 21, 11, 5 TCIFx: Stream x transfer complete interrupt flag (x = 3..0)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_LIFCR register.\n0: No transfer complete event on stream x\n1: A transfer complete event occurred on stream x\nBits 26, 20, 10, 4 HTIFx: Stream x half transfer interrupt flag (x=3..0)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_LIFCR register.\n0: No half transfer event on stream x\n1: A half transfer event occurred on stream x\nBits 25, 19, 9, 3 TEIFx: Stream x transfer error interrupt flag (x=3..0)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_LIFCR register.\n0: No transfer error on stream x\n1: A transfer error occurred on stream x\nBits 24, 18, 8, 2 DMEIFx: Stream x direct mode error interrupt flag (x=3..0)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_LIFCR register.\n0: No Direct Mode Error on stream x\n1: A Direct Mode Error occurred on stream x\nBits 23, 17, 7, 1 Reserved, must be kept at reset value.\nBits 22, 16, 6, 0 FEIFx: Stream x FIFO error interrupt flag (x=3..0)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_LIFCR register.\n0: No FIFO Error event on stream x\n1: A FIFO Error event occurred on stream x\n\n\n<>\n\nRM0090 Rev 21\n329/1757\nRM0090\nDMA controller (DMA)\n341\n10.5.2 \nDMA high interrupt status register (DMA_HISR)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTCIF7\nHTIF7\nTEIF7\nDMEIF7\nReserv\ned\nFEIF7\nTCIF6\nHTIF6\nTEIF6\nDMEIF6\nReserv\ned\nFEIF6\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTCIF5\nHTIF5\nTEIF5\nDMEIF5\nReserv\ned\nFEIF5\nTCIF4\nHTIF4\nTEIF4\nDMEIF4\nReserv\ned\nFEIF4\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:28, 15:12 Reserved, must be kept at reset value.\nBits 27, 21, 11, 5 TCIFx: Stream x transfer complete interrupt flag (x=7..4)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_HIFCR register.\n0: No transfer complete event on stream x\n1: A transfer complete event occurred on stream x\nBits 26, 20, 10, 4 HTIFx: Stream x half transfer interrupt flag (x=7..4)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_HIFCR register.\n0: No half transfer event on stream x\n1: A half transfer event occurred on stream x\nBits 25, 19, 9, 3 TEIFx: Stream x transfer error interrupt flag (x=7..4)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_HIFCR register.\n0: No transfer error on stream x\n1: A transfer error occurred on stream x\nBits 24, 18, 8, 2 DMEIFx: Stream x direct mode error interrupt flag (x=7..4)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_HIFCR register.\n0: No Direct mode error on stream x\n1: A Direct mode error occurred on stream x\nBits 23, 17, 7, 1 Reserved, must be kept at reset value.\nBits 22, 16, 6, 0 FEIFx: Stream x FIFO error interrupt flag (x=7..4)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_HIFCR register.\n0: No FIFO error event on stream x\n1: A FIFO error event occurred on stream x\n\n\n<>\n\nDMA controller (DMA)\nRM0090\n330/1757\nRM0090 Rev 21\n10.5.3 \nDMA low interrupt flag clear register (DMA_LIFCR)\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n \n10.5.4 \nDMA high interrupt flag clear register (DMA_HIFCR)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nCTCIF3 CHTIF3 CTEIF3 CDMEIF3\nReserved\nCFEIF3\nCTCIF2\nCHTIF2\nCTEIF2\nCDMEIF2\nReserved\nCFEIF2\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCTCIF1 CHTIF1 CTEIF1 CDMEIF1\nReserved\nCFEIF1\nCTCIF0\nCHTIF0\nCTEIF0\nCDMEIF0\nReserved\nCFEIF0\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBits 31:28, 15:12 Reserved, must be kept at reset value.\nBits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 3..0)\nWriting 1 to this bit clears the corresponding TCIFx flag in the DMA_LISR register\nBits 26, 20, 10, 4 CHTIFx: Stream x clear half transfer interrupt flag (x = 3..0)\nWriting 1 to this bit clears the corresponding HTIFx flag in the DMA_LISR register\nBits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 3..0)\nWriting 1 to this bit clears the corresponding TEIFx flag in the DMA_LISR register\nBits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 3..0)\nWriting 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR register\nBits 23, 17, 7, 1 Reserved, must be kept at reset value.\nBits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 3..0)\nWriting 1 to this bit clears the corresponding CFEIFx flag in the DMA_LISR register\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nCTCIF7 CHTIF7 CTEIF7 CDMEIF7\nReserved\nCFEIF7\nCTCIF6\nCHTIF6\nCTEIF6\nCDMEIF6\nReserved\nCFEIF6\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCTCIF5 CHTIF5 CTEIF5 CDMEIF5\nReserved\nCFEIF5\nCTCIF4\nCHTIF4\nCTEIF4\nCDMEIF4\nReserved\nCFEIF4\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBits 31:28, 15:12 Reserved, must be kept at reset value.\nBits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 7..4)\nWriting 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register\nBits 26, 20, 10, 4 CHTIFx: Stream x clear half transfer interrupt flag (x = 7..4)\nWriting 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register\nBits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 7..4)\nWriting 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register\n\n\n<>\n\nRM0090 Rev 21\n331/1757\nRM0090\nDMA controller (DMA)\n341\n10.5.5 \nDMA stream x configuration register (DMA_SxCR) (x = 0..7)\nThis register is used to configure the concerned stream.\nAddress offset: 0x10 + 0x18 × stream number\nReset value: 0x0000 0000\n \nBits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 7..4)\nWriting 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register\nBits 23, 17, 7, 1 Reserved, must be kept at reset value.\nBits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 7..4)\nWriting 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nCHSEL[2:0]\nMBURST [1:0]\nPBURST[1:0]\nReser-\nved\nCT\nDBM\nPL[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBits 27:25 CHSEL[2:0]: Channel selection\nThese bits are set and cleared by software.\n000: channel 0 selected\n001: channel 1 selected\n010: channel 2 selected\n011: channel 3 selected\n100: channel 4 selected\n101: channel 5 selected\n110: channel 6 selected\n111: channel 7 selected\nThese bits are protected and can be written only if EN is ‘0’\nBits 24:23 MBURST: Memory burst transfer configuration\nThese bits are set and cleared by software.\n00: single transfer\n01: INCR4 (incremental burst of 4 beats)\n10: INCR8 (incremental burst of 8 beats)\n11: INCR16 (incremental burst of 16 beats)\nThese bits are protected and can be written only if EN is ‘0’\nIn direct mode, these bits are forced to 0x0 by hardware as soon as bit EN= '1'.\nBits 22:21 PBURST[1:0]: Peripheral burst transfer configuration\nThese bits are set and cleared by software.\n00: single transfer\n01: INCR4 (incremental burst of 4 beats)\n10: INCR8 (incremental burst of 8 beats)\n11: INCR16 (incremental burst of 16 beats)\nThese bits are protected and can be written only if EN is ‘0’\nIn direct mode, these bits are forced to 0x0 by hardware.\nBit 20 Reserved, must be kept at reset value.\n\n\n<>\n\nDMA controller (DMA)\nRM0090\n332/1757\nRM0090 Rev 21\nBit 19 CT: Current target (only in double buffer mode)\nThis bits is set and cleared by hardware. It can also be written by software.\n0: The current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer)\n1: The current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer)\nThis bit can be written only if EN is ‘0’ to indicate the target memory area of the first transfer. \nOnce the stream is enabled, this bit operates as a status flag indicating which memory area \nis the current target.\nBit 18 DBM: Double buffer mode\nThis bits is set and cleared by software.\n0: No buffer switching at the end of transfer\n1: Memory target switched at the end of the DMA transfer\nThis bit is protected and can be written only if EN is ‘0’.\nBits 17:16 PL[1:0]: Priority level\nThese bits are set and cleared by software.\n00: Low\n01: Medium\n10: High\n11: Very high\nThese bits are protected and can be written only if EN is ‘0’.\nBit 15 PINCOS: Peripheral increment offset size\nThis bit is set and cleared by software\n0: The offset size for the peripheral address calculation is linked to the PSIZE\n1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment).\nThis bit has no meaning if bit PINC = '0'.\nThis bit is protected and can be written only if EN = '0'.\nThis bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct \nmode is selected or if PBURST are different from “00”.\nBits 14:13 MSIZE[1:0]: Memory data size\nThese bits are set and cleared by software.\n00: byte (8-bit)\n01: half-word (16-bit)\n10: word (32-bit)\n11: reserved\nThese bits are protected and can be written only if EN is ‘0’.\nIn direct mode, MSIZE is forced by hardware to the same value as PSIZE as soon as bit EN \n= '1'.\nBits 12:11 PSIZE[1:0]: Peripheral data size\nThese bits are set and cleared by software.\n00: Byte (8-bit)\n01: Half-word (16-bit)\n10: Word (32-bit)\n11: reserved\nThese bits are protected and can be written only if EN is ‘0’\nBit 10 MINC: Memory increment mode\nThis bit is set and cleared by software.\n0: Memory address pointer is fixed\n1: Memory address pointer is incremented after each data transfer (increment is done \naccording to MSIZE)\nThis bit is protected and can be written only if EN is ‘0’.\n\n\n<>\n\nRM0090 Rev 21\n333/1757\nRM0090\nDMA controller (DMA)\n341\nBit 9 PINC: Peripheral increment mode\nThis bit is set and cleared by software.\n0: Peripheral address pointer is fixed\n1: Peripheral address pointer is incremented after each data transfer (increment is done \naccording to PSIZE)\nThis bit is protected and can be written only if EN is ‘0’.\nBit 8 CIRC: Circular mode\nThis bit is set and cleared by software and can be cleared by hardware.\n0: Circular mode disabled\n1: Circular mode enabled\nWhen the peripheral is the flow controller (bit PFCTRL=1) and the stream is enabled (bit \nEN=1), then this bit is automatically forced by hardware to 0. \nIt is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is \nenabled (bit EN ='1').\nBits 7:6 DIR[1:0]: Data transfer direction\nThese bits are set and cleared by software.\n00: Peripheral-to-memory\n01: Memory-to-peripheral\n10: Memory-to-memory\n11: reserved\nThese bits are protected and can be written only if EN is ‘0’.\nBit 5 PFCTRL: Peripheral flow controller\nThis bit is set and cleared by software.\n0: The DMA is the flow controller\n1: The peripheral is the flow controller\nThis bit is protected and can be written only if EN is ‘0’.\nWhen the memory-to-memory mode is selected (bits DIR[1:0]=10), then this bit is \nautomatically forced to 0 by hardware.\nBit 4 TCIE: Transfer complete interrupt enable\nThis bit is set and cleared by software.\n0: TC interrupt disabled\n1: TC interrupt enabled\nBit 3 HTIE: Half transfer interrupt enable\nThis bit is set and cleared by software.\n0: HT interrupt disabled\n1: HT interrupt enabled\nBit 2 TEIE: Transfer error interrupt enable\nThis bit is set and cleared by software.\n0: TE interrupt disabled\n1: TE interrupt enabled\nBit 1 DMEIE: Direct mode error interrupt enable\nThis bit is set and cleared by software.\n0: DME interrupt disabled\n1: DME interrupt enabled\n\n\n<>\n\nDMA controller (DMA)\nRM0090\n334/1757\nRM0090 Rev 21\n10.5.6 \nDMA stream x number of data register (DMA_SxNDTR) (x = 0..7)\nAddress offset: 0x14 + 0x18 × stream number\nReset value: 0x0000 0000\n \n \nBit 0 EN: Stream enable / flag stream ready when read low\nThis bit is set and cleared by software.\n0: Stream disabled\n1: Stream enabled\nThis bit may be cleared by hardware:\n–\non a DMA end of transfer (stream ready to be configured)\n–\nif a transfer error occurs on the AHB master buses\n–\nwhen the FIFO threshold on memory AHB port is not compatible with the size of the \nburst\nWhen this bit is read as 0, the software is allowed to program the Configuration and FIFO \nbits registers. It is forbidden to write these registers when the EN bit is read as 1.\nNote: Before setting EN bit to '1' to start a new transfer, the event flags corresponding to the \nstream in DMA_LISR or DMA_HISR register must be cleared. \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nNDT[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 NDT[15:0]: Number of data items to transfer\nNumber of data items to be transferred (0 up to 65535). This register can be written only \nwhen the stream is disabled. When the stream is enabled, this register is read-only, \nindicating the remaining data items to be transmitted. This register decrements after each \nDMA transfer.\nOnce the transfer has completed, this register can either stay at zero (when the stream is in \nnormal mode) or be reloaded automatically with the previously programmed value in the \nfollowing cases:\n–\nwhen the stream is configured in Circular mode.\n–\nwhen the stream is enabled again by setting EN bit to '1'\nIf the value of this register is zero, no transaction can be served even if the stream is \nenabled.\n\n\n<>\n\nRM0090 Rev 21\n335/1757\nRM0090\nDMA controller (DMA)\n341\n10.5.7 \nDMA stream x peripheral address register (DMA_SxPAR) (x = 0..7)\nAddress offset: 0x18 + 0x18 × stream number\nReset value: 0x0000 0000\n \n \n10.5.8 \nDMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7)\nAddress offset: 0x1C + 0x18 × stream number\nReset value: 0x0000 0000\n \n \n10.5.9 \nDMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7)\nAddress offset: 0x20 + 0x18 × stream number\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nPAR[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPAR[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 PAR[31:0]: Peripheral address\nBase address of the peripheral data register from/to which the data are read/written.\nThese bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR register.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nM0A[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nM0A[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 M0A[31:0]: Memory 0 address\nBase address of Memory area 0 from/to which the data are read/written.\nThese bits are write-protected. They can be written only if:\n–\nthe stream is disabled (bit EN= '0' in the DMA_SxCR register) or\n–\nthe stream is enabled (EN=’1’ in DMA_SxCR register) and bit CT = '1' in the \nDMA_SxCR register (in Double buffer mode).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nM1A[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nM1A[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nDMA controller (DMA)\nRM0090\n336/1757\nRM0090 Rev 21\n \n10.5.10 \nDMA stream x FIFO control register (DMA_SxFCR) (x = 0..7)\nAddress offset: 0x24 + 0x18 × stream number\nReset value: 0x0000 0021\nBits 31:0 M1A[31:0]: Memory 1 address (used in case of Double buffer mode)\nBase address of Memory area 1 from/to which the data are read/written.\nThis register is used only for the Double buffer mode.\nThese bits are write-protected. They can be written only if:\n–\nthe stream is disabled (bit EN= '0' in the DMA_SxCR register) or\n–\nthe stream is enabled (EN=’1’ in DMA_SxCR register) and bit CT = '0' in the \nDMA_SxCR register.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFEIE\nReser\nved\nFS[2:0]\nDMDIS\nFTH[1:0]\nrw\nr\nr\nr\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBit 7 FEIE: FIFO error interrupt enable\nThis bit is set and cleared by software.\n0: FE interrupt disabled\n1: FE interrupt enabled\nBit 6 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n337/1757\nRM0090\nDMA controller (DMA)\n341\nBits 5:3 FS[2:0]: FIFO status\nThese bits are read-only.\n000: 0 < fifo_level < 1/4 \n001: 1/4 ≤ fifo_level < 1/2 \n010: 1/2 ≤ fifo_level < 3/4\n011: 3/4 ≤ fifo_level < full\n100: FIFO is empty\n101: FIFO is full\nothers: no meaning\nThese bits are not relevant in the direct mode (DMDIS bit is zero).\nBit 2 DMDIS: Direct mode disable\nThis bit is set and cleared by software. It can be set by hardware.\n0: Direct mode enabled\n1: Direct mode disabled\nThis bit is protected and can be written only if EN is ‘0’.\nThis bit is set by hardware if the memory-to-memory mode is selected (DIR bit in \nDMA_SxCR are “10”) and the EN bit in the DMA_SxCR register is ‘1’ because the direct \nmode is not allowed in the memory-to-memory configuration.\nBits 1:0 FTH[1:0]: FIFO threshold selection\nThese bits are set and cleared by software.\n00: 1/4 full FIFO\n01: 1/2 full FIFO\n10: 3/4 full FIFO\n11: full FIFO\nThese bits are not used in the direct mode when the DMIS value is zero.\nThese bits are protected and can be written only if EN is ‘0’.\n\n\n<>\n\nDMA controller (DMA)\nRM0090\n338/1757\nRM0090 Rev 21\n10.5.11 \nDMA register map\nTable 52 summarizes the DMA registers.\nTable 52. DMA register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x0000\nDMA_LISR\nReserved\nTCIF3\nHTIF3\nTEIF3\nDMEIF3\nReserved\nFEIF3\nTCIF2\nHTIF2\nTEIF2\nDMEIF2\nReserved\nFEIF2\nReserved\nTCIF1\nHTIF1\nTEIF1\nDMEIF1\nReserved\nFEIF1\nTCIF0\nHTIF0\nTEIF0\nDMEIF0\nReserved\nFEIF0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0004\nDMA_HISR\nReserved\nTCIF7\nHTIF7\nTEIF7\nDMEIF7\nReserved\nFEIF7\nTCIF6\nHTIF6\nTEIF6\nDMEIF6\nReserved\nFEIF6\nReserved\nTCIF5\nHTIF5\nTEIF5\nDMEIF5\nReserved\nFEIF5\nTCIF4\nHTIF4\nTEIF4\nDMEIF4\nReserved\nFEIF4\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0008\nDMA_LIFCR\nReserved\nCTCIF3\nCHTIF3\nTEIF3\nCDMEIF3\nReserved\nCFEIF3\nCTCIF2\nCHTIF2\nCTEIF2\nCDMEIF2\nReserved\nCFEIF2\nReserved\nCTCIF1\nCHTIF1\nCTEIF1\nCDMEIF1\nReserved\nCFEIF1\nCTCIF0\nCHTIF0\nCTEIF0\nCDMEIF0\nReserved\nCFEIF0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\nReserved\n0\n0\n0\n0\n0\nReserved\n0\n0\n0\n0\n0\nReserved\n0\n0x000C\nDMA_HIFCR\nReserved\nCTCIF7\nCHTIF7\nCTEIF7\nCDMEIF7\nReserved\nCFEIF7\nCTCIF6\nCHTIF6\nCTEIF6\nCDMEIF6\n-\nCFEIF6\nReserved\nCTCIF5\nCHTIF5\nCTEIF5\nCDMEIF5\n-\nCFEIF5\nCTCIF4\nCHTIF4\nCTEIF4\nCDMEIF4\n-\nCFEIF4\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n-\n0\n0\n0\n0\n0\n-\n0\n0\n0\n0\n0\n-\n0\n0x0010\nDMA_S0CR\nReserved\nCHSEL[2:0]\nMBURST[1:0] \nPBURST[1:0] \nReserved\nCT\nDBM\nPL[1:0]\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0014\nDMA_S0NDTR\nReserved\nNDT[15:.]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0018\nDMA_S0PAR\nPA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x001C\nDMA_S0M0AR\nM0A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0020\nDMA_S0M1AR\nM1A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0024\nDMA_S0FCR\nReserved\nFEIE\nReserved\nFS[2:0]\nDMDIS\nFTH\n[1:0]\nReset value\n0\n1\n0\n0\n0\n0\n1\n0x0028\nDMA_S1CR\nReserved\nCHSEL\n[2:0]\nMBURST[1:]\nPBURST[1:0]\nReserved\nCT\nDBM\nPL[1:0]\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x002C\nDMA_S1NDTR\nReserved\nNDT[15:.]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n\n\n<>\n\nRM0090 Rev 21\n339/1757\nRM0090\nDMA controller (DMA)\n341\n0x0030\nDMA_S1PAR\nPA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0034\nDMA_S1M0AR\nM0A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0038\nDMA_S1M1AR\nM1A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x003C\nDMA_S1FCR\nReserved\nFEIE\nReserved\nFS[2:0]\nDMDIS\nFTH\n[1:0]\nReset value\n0\n1\n0\n0\n0\n0\n1\n0x0040\nDMA_S2CR\nReserved\nCHSEL\n[2:0]\nMBURST[1:0]\nPBURST[1:0]\nReserved\nCT\nDBM\nPL[1:0]\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR\n[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0044\nDMA_S2NDTR\nReserved\nNDT[15:.]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0048\nDMA_S2PAR\nPA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x004C\nDMA_S2M0AR\nM0A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0050\nDMA_S2M1AR\nM1A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0054\nDMA_S2FCR\nReserved\nFEIE\nReserved\nFS[2:0]\nDMDIS\nFTH\n[1:0]\nReset value\n0\n1\n0\n0\n0\n0\n1\n0x0058\nDMA_S3CR\nReserved\nCHSEL[2:0]\nMBURST[1:0]\nPBURST[1:0]\nReserved\nCT\nDBM\nPL[1:0]\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x005C\nDMA_S3NDTR\nReserved\nNDT[15:.]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0060\nDMA_S3PAR\nPA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0064\nDMA_S3M0AR\nM0A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 52. DMA register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nDMA controller (DMA)\nRM0090\n340/1757\nRM0090 Rev 21\n0x0068\nDMA_S3M1AR\nM1A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x006C\nDMA_S3FCR\nReserved\nFEIE\nReserved\nFS[2:0]\nDMDIS\nFTH\n[1:0]\nReset value\n0\n1\n0\n0\n0\n0\n1\n0x0070\nDMA_S4CR\nReserved\nCHSEL[2:0]\nMBURST[1:0]\nPBURST[1:0]\nReserved\nCT\nDBM\nPL[1:0]\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR\n[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0074\nDMA_S4NDTR\nReserved\nNDT[15:.]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0078\nDMA_S4PAR\nPA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x007C\nDMA_S4M0AR\nM0A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0080\nDMA_S4M1AR\nM1A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0084\nDMA_S4FCR\nReserved\nFEIE\nReserved\nFS[2:0]\nDMDIS\nFTH\n[1:0]\nReset value\n0\n1\n0\n0\n0\n0\n1\n0x0088\nDMA_S5CR\nReserved\nCHSEL[2:0]\nMBURST[1:0]\nPBURST[1:0]\nReserved\nCT\nDBM\nPL[1:0]\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x008C\nDMA_S5NDTR\nReserved\nNDT[15:.]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0090\nDMA_S5PAR\nPA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0094\nDMA_S5M0AR\nM0A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0098\nDMA_S5M1AR\nM1A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x009C\nDMA_S5FCR\nReserved\nFEIE\nReserved\nFS[2:0]\nDMDIS\nFTH\n[1:0]\nReset value\n0\n1\n0\n0\n0\n0\n1\n0x00A0\nDMA_S6CR\nReserved\nCHSEL[2:0]\nMBURST[1:0]\nPBURST[1:0]\nReserved\nCT\nDBM\nPL[1:0]\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00A4\nDMA_S6NDTR\nReserved\nNDT[15:.]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00A8\nDMA_S6PAR\nPA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 52. DMA register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n341/1757\nRM0090\nDMA controller (DMA)\n341\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x00AC\nDMA_S6M0AR\nM0A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00B0\nDMA_S6M1AR\nM1A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00B4\nDMA_S6FCR\nReserved\nFEIE\nReserved\nFS[2:0]\nDMDIS\nFTH\n[1:0]\nReset value\n0\n1\n0\n0\n0\n0\n1\n0x00B8\nDMA_S7CR\nReserved\nCHSEL[2:0]\nMBURST[1:0]\nPBURST[1:0]\nReserved\nCT\nDBM\nPL[1:0]\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n-\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00BC\nDMA_S7NDTR\nReserved\nNDT[15:.]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00C0\nDMA_S7PAR\nPA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00C4\nDMA_S7M0AR\nM0A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00C8\nDMA_S7M1AR\nM1A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00CC\nDMA_S7FCR\nReserved\nFEIE\nReserved\nFS[2:0]\nDMDIS\nFTH\n[1:0]\nReset value\n0\n1\n0\n0\n0\n0\n1\nTable 52. DMA register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nChrom-Art Accelerator™ controller (DMA2D)\nRM0090\n342/1757\nRM0090 Rev 21\n11 \nChrom-Art Accelerator™ controller (DMA2D)\n11.1 \nDMA2D introduction\nThe Chrom-Art Accelerator™ (DMA2D) is a specialized DMA dedicated to image \nmanipulation. It can perform the following operations:\n•\nFilling a part or the whole of a destination image with a specific color\n•\nCopying a part or the whole of a source image into a part or the whole of a destination \nimage\n•\nCopying a part or the whole of a source image into a part or the whole of a destination \nimage with a pixel format conversion\n•\nBlending a part and/or two complete source images with different pixel format and copy \nthe result into a part or the whole of a destination image with a different color format.\nAll the classical color coding schemes are supported from 4-bit up to 32-bit per pixel with \nindexed or direct color mode. The DMA2D has its own dedicated memories for CLUTs (color \nlook-up tables).\n\n\n<>\n\nRM0090 Rev 21\n343/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.2 \nDMA2D main features\nThe main DMA2D features are:\n•\nSingle AHB master bus architecture.\n•\nAHB slave programming interface supporting 8/16/32-bit accesses (except for CLUT \naccesses which are 32-bit).\n•\nUser programmable working area size\n•\nUser programmable offset for sources and destination areas\n•\nUser programmable sources and destination addresses on the whole memory space\n•\nUp to 2 sources with blending operation\n•\nAlpha value can be modified (source value, fixed value or modulated value)\n•\nUser programmable source and destination color format\n•\nUp to 11 color formats supported from 4-bit up to 32-bit per pixel with indirect or direct \ncolor coding\n•\n2 internal memories for CLUT storage in indirect color mode\n•\nAutomatic CLUT loading or CLUT programming via the CPU\n•\nUser programmable CLUT size\n•\nInternal timer to control AHB bandwidth\n•\n4 operating modes: register-to-memory, memory-to-memory, memory-to-memory with \npixel format conversion, and memory-to-memory with pixel format conversion and \nblending\n•\nArea filling with a fixed color\n•\nCopy from an area to another\n•\nCopy with pixel format conversion between source and destination images\n•\nCopy from two sources with independent color format and blending\n•\nAbort and suspend of DMA2D operations\n•\nWatermark interrupt on a user programmable destination line\n•\nInterrupt generation on bus error or access conflict\n•\nInterrupt generation on process completion\n11.3 \nDMA2D functional description\n11.3.1 \nGeneral description\nThe DMA2D controller performs direct memory transfer. As an AHB master, it can take the \ncontrol of the AHB bus matrix to initiate AHB transactions.\nThe DMA2D can operate in the following modes: \n•\nRegister-to-memory\n•\nMemory-to-memory\n•\nMemory-to-memory with Pixel Format Conversion\n•\nMemory-to-memory with Pixel Format Conversion and Blending\nThe AHB slave port is used to program the DMA2D controller.\nThe block diagram of the DMA2D is shown in Figure 40: DMA2D block diagram. \n\n\n<>\n\nChrom-Art Accelerator™ controller (DMA2D)\nRM0090\n344/1757\nRM0090 Rev 21\nFigure 40. DMA2D block diagram\n11.3.2 \nDMA2D control\nThe DMA2D controller is configured through the DMA2D Control Register (DMA2D_CR) \nwhich allows selecting: \nThe user application can perform the following operations:\n•\nSelect the operating mode\n•\nEnable/disable the DMA2D interrupt\n•\nStart/suspend/abort ongoing data transfers\n11.3.3 \nDMA2D foreground and background FIFOs\nThe DMA2D foreground (FG) FG FIFO and background (BG) FIFO fetch the input data to \nbe copied and/or processed.\nThe FIFOs fetch the pixels according to the color format defined in their respective pixel \nformat converter (PFC).\nMS30439V1\nBG PFC\n32\nAHB SLAVE\nAHB MASTER\n256x32-bit\nRAM\nCLUT itf\n256x32-bit\nRAM\nCLUT itf\nExpander\nExpander\n32\nRGB\nα 8\nColor mode\nX\n8-bit α\nα mode\nα 32\nBG\nFIFO\nFG PFC\n32\nExpander\nExpander\n32\nRGB\nα 8\nColor mode\nX\n8-bit α\nα mode\nα 32\nFG\nFIFO\nBLENDER\n32\n32\nα\nRed\nGreen\nBlue\n32\nOUT PFC\nColor mode\nConverter\n32/24/16\nOUT \nFIFO\nColor\n\n\n<>\n\nRM0090 Rev 21\n345/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\nThey are programmed through a set of control registers:\n•\nDMA2D foreground memory address register (DMA2D_FGMAR)\n•\nDMA2D foreground offset register (DMA2D_FGOR)\n•\nDMA2D background memory address register (DMA2D_BGMAR)\n•\nDMA2D background offset register (DMA2D_BGBOR)\n•\nDMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR)\nWhen the DMA2D operates in register-to-memory mode, none of the FIFOs is activated.\nWhen the DMA2D operates in memory-to-memory mode (no pixel format conversion nor \nblending operation), only the FG FIFO is activated and acts as a buffer.\nWhen the DMA2D operates in memory-to-memory operation with pixel format conversion \n(no blending operation), the BG FIFO is not activated.\n11.3.4 \nDMA2D foreground and background pixel format converter (PFC)\nDMA2D foreground pixel format converter (PFC) and background pixel format converter \nperform the pixel format conversion to generate a 32-bit per pixel value. The PFC can also \nmodify the alpha channel.\nThe first stage of the converter converts the color format. The original color format of the \nforeground pixel and background pixels are configured through the CM[3:0] bits of the \nDMA2D_FGPFCCR and DMA2D_BGPFCCR, respectively.\nThe supported input formats are given in Table 53: Supported color mode in input.\n \nTable 53. Supported color mode in input\nCM[3:0]\nColor mode\n0000\nARGB8888\n0001\nRGB888\n0010\nRGB565\n0011\nARGB1555\n0100\nARGB4444\n0101\nL8\n0110\nAL44\n0111\nAL88\n1000\nL4\n1001\nA8\n1010\nA4\n\n\n<>\n\nChrom-Art Accelerator™ controller (DMA2D)\nRM0090\n346/1757\nRM0090 Rev 21\nThe color format are coded as follows: \n•\nAlpha value field: transparency\n0xFF value corresponds to an opaque pixel and 0x00 to a transparent one. \n•\nR field for Red\n•\nG field for Green\n•\nB field for Blue\n•\nL field: luminance\nThis field is the index to a CLUT to retrieve the three/four RGB/ARGB components.\nIf the original format was direct color mode, then the extension to 8-bit per channel is \nperformed by copying the MSBs into the LSBs. This ensures a perfect linearity of the \nconversion.\nIf the original format does not include an alpha channel, the alpha value is automatically set \nto 0xFF (opaque).\nIf the original format is indirect color mode, a CLUT is required and each pixel format \nconverter is associated with a 256 entry 32-bit CLUT.\nFor the specific alpha mode A4 and A8, no color information is stored nor indexed. The color \nto be used for the image generation is fixed and is defined in the DMA2D_FGCOLR for \nforeground pixels and in the DMA2D_BGCOLR register for background pixels. \nThe order of the fields in the system memory is defined in Table 54: Data order in memory.\n \nThe 24-bit RGB888 aligned on 32-bit is supported through the ARGB8888 mode.\nOnce the 32-bit value is generated, the alpha channel can be modified according to the \nAM[1:0] field of the DMA2D_FGPFCCR/DMA2D_BGPFCCR registers as shown in \nTable 55: Alpha mode configuration.\nTable 54. Data order in memory\nColor Mode\n@ + 3\n@ + 2\n@ + 1\n@ + 0\nARGB8888\nA0[7:0]\nR0[7:0]\nG0[7:0]\nB0[7:0]\nRGB888\nB1[7:0]\nR0[7:0]\nG0[7:0]\nB0[7:0]\nG2[7:0]\nB2[7:0]\nR1[7:0]\nG1[7:0]\nR3[7:0]\nG3[7:0]\nB3[7:0]\nR2[7:0]\nRGB565\nR1[4:0]G1[5:3]\nG1[2:0]B1[4:0]\nR0[4:0]G0[5:3]\nG0[2:0]B0[4:0]\nARGB1555\nA1[0]R1[4:0]G1[4:3]\nG1[2:0]B1[4:0]\nA0[0]R0[4:0]G0[4:3]\nG0[2:0]B0[4:0]\nARGB4444\nA1[3:0]R1[3:0]\nG1[3:0]B1[3:0]\nA0[3:0]R0[3:0]\nG0[3:0]B0[3:0]\nL8\nL3[7:0]\nL2[7:0]\nL1[7:0]\nL0[7:0]\nAL44\nA3[3:0]L3[3:0]\nA2[3:0]L2[3:0]\nA1[3:0]L1[3:0]\nA0[3:0]L0[3:0]\nAL88\nA1[7:0]\nL1[7:0]\nA0[7:0]\nL0[7:0]\nL4\nL7[3:0]L6[3:0]\nL5[3:0]L4[3:0]\nL3[3:0]L2[3:0]\nL1[3:0]L0[3:0]\nA8\nA3[7:0]\nA2[7:0]\nA1[7:0]\nA0[7:0]\nA4\nA7[3:0]A6[3:0]\nA5[3:0]A4[3:0]\nA3[3:0]A2[3:0]\nA1[3:0]A0[3:0]\n\n\n<>\n\nRM0090 Rev 21\n347/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\nThe alpha channel can be:\n•\nkept as it is (no modification),\n•\nreplaced by the ALPHA[7:0] value of DMA2D_FGPFCCR/DMA2D_BGPFCCR,\n•\nor replaced by the original alpha value multiplied by the ALPHA[7:0] value of \nDMA2D_FGPFCCR/DMA2D_BGPFCCR divided by 255.\n \n11.3.5 \nDMA2D foreground and background CLUT interface\nThe CLUT interface manages the CLUT memory access and the automatic loading of the \nCLUT.\nThree kinds of accesses are possible:\n•\nCLUT read by the PFC during pixel format conversion operation\n•\nCLUT accessed through the AHB slave port when the CPU is reading or writing data \ninto the CLUT\n•\nCLUT written through the AHB master port when an automatic loading of the CLUT is \nperformed\nThe CLUT memory loading can be done in two different ways:\n•\nAutomatic loading\nThe following sequence should be followed to load the CLUT: \na) \nProgram the CLUT address into the DMA2D_FGCMAR register (foreground \nCLUT) or DMA2D_BGCMAR register (background CLUT)\nb) \nProgram the CLUT size in the CS[7:0] field of the DMA2D_FGPFCCR register \n(foreground CLUT) or DMA2D_BGPFCCR register (background CLUT). \nc) \nSet the START bit of the DMA2D_FGPFCCR register (foreground CLUT) or \nDMA2D_BGPFCCR register (background CLUT) to start the transfer. During this \nautomatic loading process, the CLUT is not accessible by the CPU. If a conflict \noccurs, a CLUT access error interrupt is raised assuming CAEIE is set to ‘1’ in \nDMA2D_CR. \n•\nManual loading\nThe application has to program the CLUT manually through the DMA2D AHB slave \nport to which the local CLUT memory is mapped.The foreground CLUT is located at \naddress offset 0x0400 and the background CLUT at address offset 0x0800.\nThe CLUT format can be 24 or 32 bits. It is configured through the CCM bit of the \nDMA2D_FGPFCCR register (foreground CLUT) or DMA2D_BGPFCCR register \n(background CLUT) as shown in Table 56: Supported CLUT color mode.\nTable 55. Alpha mode configuration\nAM[1:0]\nAlpha mode\n00\nNo modification\n01\nReplaced by value in DMA2D_xxPFCCR\n10\nReplaced by original value multiplied by the value in DMA2D_xxPFCCR / 255\n11\nReserved\n\n\n<>\n\nChrom-Art Accelerator™ controller (DMA2D)\nRM0090\n348/1757\nRM0090 Rev 21\n \nThe way the CLUT data are organized in the system memory is specified in Table 57: CLUT \ndata order in memory.\n \n11.3.6 \nDMA2D blender\nThe DMA2D blender blends the source pixels by pair to compute the resulting pixel.\nThe blending is performed according to the following equation:\nNo configuration register is required by the blender. The blender usage depends on the \nDMA2D operating mode defined in MODE[1:0] field of the DMA2D_CR register.\n11.3.7 \nDMA2D output PFC\nThe output PFC performs the pixel format conversion from 32 bits to the output format \ndefined in the CM[2:0] field of the DMA2D output pixel format converter configuration \nregister (DMA2D_OPFCCR).\nThe supported output formats are given in Table 58: Supported color mode in output\nTable 56. Supported CLUT color mode\nCCM\nCLUT color mode\n0\n32-bit ARGB8888\n1\n24-bit RGB888\nTable 57. CLUT data order in memory\nCLUT Color Mode\n@ + 3\n@ + 2\n@ + 1\n@ + 0\nARGB8888\nA0[7:0]\nR0[7:0]\nG0[7:0]\nB0[7:0]\nRGB888\nB1[7:0]\nR0[7:0]\nG0[7:0]\nB0[7:0]\nG2[7:0]\nB2[7:0]\nR1[7:0]\nG1[7:0]\nR3[7:0]\nG3[7:0]\nB3[7:0]\nR2[7:0]\nCOUT =\nwith αMult = \nCFG.αFG + CBG.αBG - CBG.αMult\nαOUT\n255\nαFG . αBG\nwith C = R or G or B\nαOUT = αFG + αBG - αMult \nDivision is rounded to the nearest lower integer\n\n\n<>\n\nRM0090 Rev 21\n349/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n \n11.3.8 \nDMA2D output FIFO\nThe output FIFO programs the pixels according to the color format defined in the output \nPFC.\nThe destination area is defined through a set of control registers: \n•\nDMA2D output memory address register (DMA2D_OMAR)\n•\nDMA2D output offset register (DMA2D_OOR)\n•\nDMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR)\nIf the DMA2D operates in register-to-memory mode, the configured output rectangle is filled \nby the color specified in the DMA2D output color register (DMA2D_OCOLR) which contains \na fixed 32-bit, 24-bit or 16-bit value. The format is selected by the CM[2:0] field of the \nDMA2D_OPFCCR register.\nThe data are stored into the memory in the order defined in Table 59: Data order in memory\n \nThe RGB888 aligned on 32-bit is supported through the ARGB8888 mode.\n11.3.9 \nDMA2D AHB master port timer\nAn 8-bit timer is embedded into the AHB master port to provide an optional limitation of the \nbandwidth on the crossbar.\nThis timer is clocked by the AHB clock and counts a dead time between two consecutive \naccesses. This limits the bandwidth usage.\nTable 58. Supported color mode in output\nCM[2:0]\nColor mode\n000\nARGB8888\n001\nRGB888\n010\nRGB565\n011\nARGB1555\n100\nARGB4444\nTable 59. Data order in memory\nColor Mode\n@ + 3\n@ + 2\n@ + 1\n@ + 0\nARGB8888\nA0[7:0]\nR0[7:0]\nG0[7:0]\nB0[7:0]\nRGB888\nB1[7:0]\nR0[7:0]\nG0[7:0]\nB0[7:0]\nG2[7:0]\nB2[7:0]\nR1[7:0]\nG1[7:0]\nR3[7:0]\nG3[7:0]\nB3[7:0]\nR2[7:0]\nRGB565\nR1[4:0]G1[5:3]\nG1[2:0]B1[4:0]\nR0[4:0]G0[5:3]\nG0[2:0]B0[4:0]\nARGB1555\nA1[0]R1[4:0]G1[4:3]\nG1[2:0]B1[4:0]\nA0[0]R0[4:0]G0[4:3]\nG0[2:0]B0[4:0]\nARGB4444\nA1[3:0]R1[3:0]\nG1[3:0]B1[3:0]\nA0[3:0]R0[3:0]\nG0[3:0]B0[3:0]\n\n\n<>\n\nChrom-Art Accelerator™ controller (DMA2D)\nRM0090\n350/1757\nRM0090 Rev 21\nThe timer enabling and the dead time value are configured through the AHB master port \ntimer configuration register (DMA2D_AMPTCR).\n11.3.10 \nDMA2D transactions\nDMA2D transactions consist of a sequence of a given number of data transfers. The \nnumber of data and the width can be programmed by software.\nEach DMA2D data transfer is composed of up to 4 steps: \n1.\nData loading from the memory location pointed by the DMA2D_FGMAR register and \npixel format conversion as defined in DMA2D_FGCR.\n2. \nData loading from a memory location pointed by the DMA2D_BGMAR register and \npixel format conversion as defined in DMA2D_BGCR.\n3. \nBlending of all retrieved pixels according to the alpha channels resulting of the PFC \noperation on alpha values.\n4. \nPixel format conversion of the resulting pixels according to the DMA2D_OCR register \nand programming of the data to the memory location addressed through the \nDMA2D_OMAR register.\n11.3.11 \nDMA2D configuration\nBoth source and destination data transfers can target peripherals and memories in the \nwhole 4 Gbyte memory area, at addresses ranging between 0x0000 0000 and \n0xFFFF FFFF. \nThe DMA2D can operate in any of the four following modes selected through MODE[1:0] \nbits of the DMA2D_CR register:\n•\nRegister-to-memory \n•\nMemory-to-memory \n•\nMemory-to-memory with PFC\n•\nMemory-to-memory with PFC and blending\nRegister-to-memory\nThe register-to-memory mode is used to fill a user defined area with a predefined color.\nThe color format is set in the DMA2D_OPFCCR.\nThe DMA2D does not perform any data fetching from any source. It just writes the color \ndefined in the DMA2D_OCOLR register to the area located at the address pointed by the \nDMA2D_OMAR and defined in the DMA2D_NLR and DMA2D_OOR.\nMemory-to-memory \nIn memory-to-memory mode, the DMA2D does not perform any graphical data \ntransformation. The foreground input FIFO acts as a buffer and the data are transferred \nfrom the source memory location defined in DMA2D_FGMAR to the destination memory \nlocation pointed by DMA2D_OMAR.\nThe color mode programmed in the CM[3:0] bits of the DMA2D_FGPFCCR register defines \nthe number of bits per pixel for both input and output.\n\n\n<>\n\nRM0090 Rev 21\n351/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\nThe size of the area to be transferred is defined by the DMA2D_NLR and DMA2D_FGOR \nregisters for the source, and by DMA2D_NLR and DMA2D_OOR registers for the \ndestination.\nMemory-to-memory with PFC \nIn this mode, the DMA2D performs a pixel format conversion of the source data and stores \nthem in the destination memory location.\nThe size of the areas to be transferred are defined by the DMA2D_NLR and DMA2D_FGOR \nregisters for the source, and by DMA2D_NLR and DMA2D_OOR registers for the \ndestination.\nData are fetched from the location defined in the DMA2D_FGMAR register and processed \nby the foreground PFC. The original pixel format is configured through the \nDMA2D_FGPFCCR register.\nIf the original pixel format is direct color mode, then the color channels are all expanded to 8 \nbits. \nIf the pixel format is indirect color mode, the associated CLUT has to be loaded into the \nCLUT memory. \nThe CLUT loading can be done automatically by following the sequence below: \n1.\nSet the CLUT address into the DMA2D_FGCMAR.\n2. \nSet the CLUT size in the CS[7:0] bits of the DMA2D_FGPFCCR register.\n3. \nSet the CLUT format (24 or 32 bits) in the CCM bit of the DMA2D_FGPFCCR register.\n4. \nStart the CLUT loading by setting the START bit of the DMA2D_FGPFCCR register. \nOnce the CLUT loading is complete, the CTCIF flag of the DMA2D_IFR register is raised, \nand an interrupt is generated if the CTCIE bit is set in DMA2D_CR. The automatic CLUT \nloading process can not work in parallel with classical DMA2D transfers.\nThe CLUT can also be filled by the CPU or by any other master through the APB port. The \naccess to the CLUT is not possible when a DMA2D transfer is ongoing and uses the CLUT \n(indirect color format).\nIn parallel to the color conversion process, the alpha value can be added or changed \ndepending on the value programmed in the DMA2D_FGPFCCR register. If the original \nimage does not have an alpha channel, a default alpha value of 0xFF is automatically added \nto obtain a fully opaque pixel. The alpha value can be modified according to the AM[1:0] bits \nof the DMA2D_FGPFCCR register:\n•\nIt can be unchanged.\n•\nIt can be replaced by the value defined in the ALPHA[7:0] value of the \nDMA2D_FGPFCCR register.\n•\nIt can be replaced by the original value multiplied by the ALPHA[7:0] value of the \nDMA2D_FGPFCCR register divided by 255.\nThe resulting 32-bit data are encoded by the OUT PFC into the format specified by the \nCM[2:0] field of the DMA2D_OPFCCR register. The output pixel format cannot be the \nindirect mode since no CLUT generation process is supported. \nThe processed data are written into the destination memory location pointed by \nDMA2D_OMAR.\n\n\n<>\n\nChrom-Art Accelerator™ controller (DMA2D)\nRM0090\n352/1757\nRM0090 Rev 21\nMemory-to-memory with PFC and blending\nIn this mode, 2 sources are fetched in the foreground FIFO and background FIFO from the \nmemory locations defined by DMA2D_FGMAR and DMA2D_BGMAR.\nThe two pixel format converters have to be configured as described in the memory-to-\nmemory mode. Their configurations can be different as each pixel format converter are \nindependent and have their own CLUT memory.\nOnce each pixel has been converted into 32 bits by their respective PFCs, they are blended \naccording to the equation below:\nThe resulting 32-bit pixel value is encoded by the output PFC according to the specified \noutput format, and the data are written into the destination memory location pointed by \nDMA2D_OMAR.\nConfiguration error detection\nThe DMA2D checks that the configuration is correct before any transfer. The configuration \nerror interrupt flag is set by hardware when a wrong configuration is detected when a new \ntransfer/automatic loading starts. An interrupt is then generated if the CEIE bit of the \nDMA2D_CR is set.\nCOUT =\nwith αMult = \nCFG.αFG + CBG.αBG - CBG.αMult\nαOUT\n255\nαFG . αBG\nwith C = R or G or B\nαOUT = αFG + αBG - αMult \nDivision are rounded to the nearest lower integer\n\n\n<>\n\nRM0090 Rev 21\n353/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\nThe wrong configurations that can be detected are listed below:\n•\nForeground CLUT automatic loading: MA bits of DMA2D_FGCMAR not aligned with \nCCM of DMA2D_FGPFCCR.\n•\nBackground CLUT automatic loading: MA of DMA2D_BGCMAR not aligned with CCM \nof DMA2D_BGPFCCR\n•\nMemory transfer (except in register-to-memory mode): MA of DMA2D_FGMAR not \naligned with CM of DMA2D_FGPFCCR\n•\nMemory transfer (except in register-to-memory mode): CM in DMA2D_FGPFCCR are \ninvalid \n•\nMemory transfer (except in register-to-memory mode): PL bits of DMA2D_NLR odd \nwhile CM of DMA2D_FGPFCCR is A4 or L4 \n•\nMemory transfer (except in register-to-memory mode): LO bits in DMA2D_FGOR odd \nwhile CM of DMA2D_FGPFCCR is A4 or L4\n•\nMemory transfer (only in blending mode): MA bits in DMA2D_BGMAR are not aligned \nwith the CM of DMA2D_BGPFCCR \n•\nMemory transfer: CM of DMA2D_BGPFCCR invalid (only in blending mode)\n•\nMemory transfer (only in blending mode): PL bits of DMA2D_NLR odd while CM of \nDMA2D_BGPFCCR is A4 or L4 \n•\nMemory transfer (only in blending mode): LO bits of DMA2D_BGOR odd while CM of \nDMA2D_BGPFCCR is A4 or L4 \n•\nMemory transfer (except in memory to memory mode): MA bits in DMA2D_OMAR are \nnot aligned with CM bits in DMA2D_OPFCCR.\n•\nMemory transfer (except in memory to memory mode): CM bits in DMA2D_OPFCCR \ninvalid \n•\nMemory transfer: NL bits in DMA2D_NLR = 0 \n•\nMemory transfer: PL bits in DMA2D_NLR = 0\n11.3.12 \nDMA2D transfer control (start, suspend, abort and completion)\nOnce the DMA2D is configured, the transfer can be launched by setting the START bit of the \nDMA2D_CR register. Once the transfer is completed, the START bit is automatically reset \nand the TCIF flag of the DMA2D_ISR register is raised. An interrupt can be generated if the \nTCIE bit of the DMA2D_CR is set.\nThe user application can suspend the DMA2D at any time by setting the SUSP bit of the \nDMA2D_CR register. The transaction can then be aborted by setting the ABORT bit of the \nDMA2D_CR register or can be restarted by resetting the SUSP bit of the DMA2D_CR \nregister.\nThe user application can abort at any time an ongoing transaction by setting the ABORT bit \nof the DMA2D_CR register. In this case, the TCIF flag is not raised.\nAutomatic CLUT transfers can also be aborted or suspended by using the ABORT or the \nSUSP bit of the DMA2D_CR register.\n\n\n<>\n\nChrom-Art Accelerator™ controller (DMA2D)\nRM0090\n354/1757\nRM0090 Rev 21\n11.3.13 \nWatermark\nA watermark can be programmed to generate an interrupt when the last pixel of a given line \nhas been written to the destination memory area.\nThe line number is defined in the LW[15:0] field of the DMA2D_LWR register.\nWhen the last pixel of this line has been transferred, the TWIF flag of the DMA2D_ISR \nregister is raised and an interrupt is generated if the TWIE bit of the DMA2D_CR is set.\n11.3.14 \nError management\nTwo kind of errors can be triggered:\n•\nAHB master port errors signalled by the TEIF flag of the DMA2D_ISR register.\n•\nConflicts caused by CLUT access (CPU trying to access the CLUT while a CLUT \nloading or a DMA2D transfer is ongoing) signalled by the CAEIF flag of the \nDMA2D_ISR register.\nBoth flags are associated to their own interrupt enable flag in the DMA2D_CR register to \ngenerate an interrupt if need be (TEIE and CAEIE).\n11.3.15 \nAHB dead time\nTo limit the AHB bandwidth usage, a dead time between two consecutive AHB accesses \ncan be programmed. \nThis feature can be enabled by setting the EN bit in the DMA2D_AMTCR register.\nThe dead time value is stored in the DT[7:0] field of the DMA2D_AMTCR register. This \nvalue represents the guaranteed minimum number of cycles between two consecutive \ntransactions on the AHB bus.\nThe update of the dead time value while the DMA2D is running is taken into account for the \nnext AHB transfer.\n11.4 \nDMA2D interrupts\nAn interrupt can be generated on the following events: \n•\nConfiguration error\n•\nCLUT transfer complete\n•\nCLUT access error\n•\nTransfer watermark reached \n•\nTransfer complete\n•\nTransfer error\nSeparate interrupt enable bits are available for flexibility.\n \nTable 60. DMA2D interrupt requests\nInterrupt event\nEvent flag\nEnable control bit\nConfiguration error\nCEIF\nCEIE\nCLUT transfer complete\nCTCIF\nCTCIE\n\n\n<>\n\nRM0090 Rev 21\n355/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.5 \nDMA2D registers\n11.5.1 \nDMA2D control register (DMA2D_CR)\nAddress offset: 0x0000\nReset value: 0x0000 0000\n \nCLUT access error\nCAEIF\nCAEIE\nTransfer watermark\nTWF\nTWIE\nTransfer complete\nTCIF\nTCIE\nTransfer error\nTEIF\nTEIE\nTable 60. DMA2D interrupt requests (continued)\nInterrupt event\nEvent flag\nEnable control bit\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nMODE\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCEIE\nCTCIE CAEIE\nTWIE\nTCIE\nTEIE\nReserved\nABORT\nSUSP\nSTART\nrw\nrw\nrw\nrw\nrw\nrw\nrs\nrw\nrs\nBits 31:18 Reserved, must be kept at reset value\nBits 17:16 MODE: DMA2D mode\nThis bit is set and cleared by software. It cannot be modified while a transfer is ongoing.\n00: Memory-to-memory (FG fetch only)\n01: Memory-to-memory with PFC (FG fetch only with FG PFC active)\n10: Memory-to-memory with blending (FG and BG fetch with PFC and blending)\n11: Register-to-memory (no FG nor BG, only output stage active)\nBits 15:14 Reserved, must be kept at reset value\nBit 13 CEIE: Configuration Error Interrupt Enable\nThis bit is set and cleared by software.\n0: CE interrupt disable\n1: CE interrupt enable\nBit 12 CTCIE: CLUT transfer complete interrupt enable\nThis bit is set and cleared by software.\n0: CTC interrupt disable\n1: CTC interrupt enable\nBit 11 CAEIE: CLUT access error interrupt enable\nThis bit is set and cleared by software.\n0: CAE interrupt disable\n1: CAE interrupt enable\n\n\n<>\n\nChrom-Art Accelerator™ controller (DMA2D)\nRM0090\n356/1757\nRM0090 Rev 21\nBit 10 TWIE: Transfer watermark interrupt enable\nThis bit is set and cleared by software.\n0: TW interrupt disable\n1: TW interrupt enable\nBit 9 TCIE: Transfer complete interrupt enable\nThis bit is set and cleared by software.\n0: TC interrupt disable\n1: TC interrupt enable\nBit 8 TEIE: Transfer error interrupt enable\nThis bit is set and cleared by software.\n0: TE interrupt disable\n1: TE interrupt enable\nBits 7:3 Reserved, must be kept at reset value\nBit 2 ABORT: Abort\nThis bit can be used to abort the current transfer. This bit is set by software and is \nautomatically reset by hardware when the START bit is reset.\n0: No transfer abort requested\n1: Transfer abort requested\nBit 1 SUSP: Suspend\nThis bit can be used to suspend the current transfer. This bit is set and reset by \nsoftware. It is automatically reset by hardware when the START bit is reset.\n0: Transfer not suspended\n1: Transfer suspended\nBit 0 START: Start\nThis bit can be used to launch the DMA2D according to the parameters loaded in the \nvarious configuration registers. This bit is automatically reset by the following events:\n–\nAt the end of the transfer \n–\nWhen the data transfer is aborted by the user application by setting the ABORT \nbit in DMA2D_CR\n–\nWhen a data transfer error occurs\n–\nWhen the data transfer has not started due to a configuration error or another \ntransfer operation already ongoing (automatic CLUT loading).\n\n\n<>\n\nRM0090 Rev 21\n357/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.5.2 \nDMA2D Interrupt Status Register (DMA2D_ISR)\nAddress offset: 0x0004\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCEIF\nCTCIF\nCAEIF\nTWIF\nTCIF\nTEIF\nr\nr\nr\nr\nr\nr\nBits 31:6 Reserved, must be kept at reset value\nBit 5 CEIF: Configuration error interrupt flag\nThis bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or \nDMA2D_BGPFCCR is set and a wrong configuration has been programmed.\nBit 4 CTCIF: CLUT transfer complete interrupt flag\nThis bit is set when the CLUT copy from a system memory area to the internal DMA2D \nmemory is complete.\nBit 3 CAEIF: CLUT access error interrupt flag\nThis bit is set when the CPU accesses the CLUT while the CLUT is being automatically \ncopied from a system memory to the internal DMA2D.\nBit 2 TWIF: Transfer watermark interrupt flag\nThis bit is set when the last pixel of the watermarked line has been transferred.\nBit 1 TCIF: Transfer complete interrupt flag\nThis bit is set when a DMA2D transfer operation is complete (data transfer only).\nBit 0 TEIF: Transfer error interrupt flag\nThis bit is set when an error occurs during a DMA transfer (data transfer or automatic \nCLUT loading).\n\n\n<>\n\nChrom-Art Accelerator™ controller (DMA2D)\nRM0090\n358/1757\nRM0090 Rev 21\n11.5.3 \nDMA2D interrupt flag clear register (DMA2D_IFCR)\nAddress offset: 0x0008\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCCEIF\nCCTCIF CAECIF\nCTWIF\nCTCIF\nCTEIF\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nBits 31:6 Reserved, must be kept at reset value\nBit 5 CCEIF: Clear configuration error interrupt flag\nProgramming this bit to 1 clears the CEIF flag in the DMA2D_ISR register\nBit 4 CCTCIF: Clear CLUT transfer complete interrupt flag\nProgramming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register\nBit 3 CAECIF: Clear CLUT access error interrupt flag\nProgramming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register\nBit 2 CTWIF: Clear transfer watermark interrupt flag\nProgramming this bit to 1 clears the TWIF flag in the DMA2D_ISR register\nBit 1 CTCIF: Clear transfer complete interrupt flag\nProgramming this bit to 1 clears the TCIF flag in the DMA2D_ISR register\nBit 0 CTEIF: Clear Transfer error interrupt flag\nProgramming this bit to 1 clears the TEIF flag in the DMA2D_ISR register\n\n\n<>\n\nRM0090 Rev 21\n359/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.5.4 \nDMA2D foreground memory address register (DMA2D_FGMAR)\nAddress offset: 0x000C\nReset value: 0x0000 0000\n \n11.5.5 \nDMA2D foreground offset register (DMA2D_FGOR)\nAddress offset: 0x0010\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMA[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMA[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 MA[31: 0]: Memory address\nAddress of the data used for the foreground image. This register can only be written \nwhen data transfers are disabled. Once the data transfer has started, this register is \nread-only.\nThe address alignment must match the image format selected e.g. a 32-bit per pixel \nformat must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-\nbit per pixel format must be 8-bit aligned.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLO[13:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:14 Reserved, must be kept at reset value\nBits 13:0 LO[13: 0]: Line offset\nLine offset used for the foreground expressed in pixel. This value is used to generate \nthe address. It is added at the end of each line to determine the starting address of the \nnext line.\nThese bits can only be written when data transfers are disabled. Once a data transfer \nhas started, they become read-only.\nIf the image format is 4-bit per pixel, the line offset must be even.\n\n\n<>\n\nChrom-Art Accelerator™ controller (DMA2D)\nRM0090\n360/1757\nRM0090 Rev 21\n11.5.6 \nDMA2D background memory address register (DMA2D_BGMAR)\nAddress offset: 0x0014\nReset value: 0x0000 0000\n \n11.5.7 \nDMA2D background offset register (DMA2D_BGOR)\nAddress offset: 0x0018\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMA[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMA[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31: 0 MA[31: 0]: Memory address\nAddress of the data used for the background image. This register can only be written \nwhen data transfers are disabled. Once a data transfer has started, this register is read-\nonly.\nThe address alignment must match the image format selected e.g. a 32-bit per pixel \nformat must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-\nbit per pixel format must be 8-bit aligned.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLO[13:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:14 Reserved, must be kept at reset value\nBits 13:0 LO[13: 0]: Line offset\nLine offset used for the background image (expressed in pixel). This value is used for \nthe address generation. It is added at the end of each line to determine the starting \naddress of the next line.\nThese bits can only be written when data transfers are disabled. Once data transfer has \nstarted, they become read-only.\nIf the image format is 4-bit per pixel, the line offset must be even.\n\n\n<>\n\nRM0090 Rev 21\n361/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.5.8 \nDMA2D foreground PFC control register (DMA2D_FGPFCCR)\nAddress offset: 0x001C\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nALPHA[7:0]\nReserved\nAM[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCS[7:0]\nReserved\nSTART\nCCM\nCM[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrs\nrw\nrw\nrw\nrw\nrw\nBits 31:24 ALPHA[7: 0]: Alpha value\nThese bits define a fixed alpha channel value which can replace the original alpha value \nor be multiplied by the original alpha value according to the alpha mode selected \nthrough the AM[1:0] bits. \nThese bits can only be written when data transfers are disabled. Once a transfer has \nstarted, they become read-only.\nBits 23:18 Reserved, must be kept at reset value\nBits 17:16 AM[1: 0]: Alpha mode\nThese bits select the alpha channel value to be used for the foreground image. They \ncan only be written data the transfer are disabled. Once the transfer has started, they \nbecome read-only.\n00: No modification of the foreground image alpha channel value\n01: Replace original foreground image alpha channel value by ALPHA[7: 0]\n10: Replace original foreground image alpha channel value by ALPHA[7:0] multiplied \nwith original alpha channel value\nother configurations are meaningless\nBits 15:8 CS[7: 0]: CLUT size\nThese bits define the size of the CLUT used for the foreground image. Once the CLUT \ntransfer has started, this field is read-only.\nThe number of CLUT entries is equal to CS[7:0] + 1.\nBits 7:6 Reserved, must be kept at reset value\n\n\n<>\n\nChrom-Art Accelerator™ controller (DMA2D)\nRM0090\n362/1757\nRM0090 Rev 21\nBit 5 START: Start\nThis bit can be set to start the automatic loading of the CLUT. It is automatically reset:\n–\nat the end of the transfer \n–\nwhen the transfer is aborted by the user application by setting the ABORT bit in \nDMA2D_CR\n–\nwhen a transfer error occurs\n–\nwhen the transfer has not started due to a configuration error or another \ntransfer operation already ongoing (data transfer or automatic background \nCLUT transfer).\nBit 4 CCM: CLUT color mode\nThis bit defines the color format of the CLUT. It can only be written when the transfer is \ndisabled. Once the CLUT transfer has started, this bit is read-only.\n0: ARGB8888\n1: RGB888\nothers: meaningless\nBits 3:0 CM[3: 0]: Color mode\nThese bits defines the color format of the foreground image. They can only be written \nwhen data transfers are disabled. Once the transfer has started, they are read-only.\n0000: ARGB8888\n0001: RGB888\n0010: RGB565\n0011: ARGB1555\n0100: ARGB4444\n0101: L8\n0110: AL44\n0111: AL88\n1000: L4\n1001: A8\n1010: A4\nothers: meaningless\n\n\n<>\n\nRM0090 Rev 21\n363/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.5.9 \nDMA2D foreground color register (DMA2D_FGCOLR)\nAddress offset: 0x0020\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nRED[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nGREEN[7:0]\nBLUE[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value\nBits 23:16 RED[7: 0]: Red Value\nThese bits defines the red value for the A4 or A8 mode of the foreground image. They \ncan only be written when data transfers are disabled. Once the transfer has started, \nthey are read-only.\nBits 15:8 GREEN[7: 0]: Green Value\nThese bits defines the green value for the A4 or A8 mode of the foreground image. They \ncan only be written when data transfers are disabled. Once the transfer has started, \nThey are read-only.\nBits 7:0 BLUE[7: 0]: Blue Value\nThese bits defines the blue value for the A4 or A8 mode of the foreground image. They \ncan only be written when data transfers are disabled. Once the transfer has started, \nThey are read-only.\n\n\n<>\n\nChrom-Art Accelerator™ controller (DMA2D)\nRM0090\n364/1757\nRM0090 Rev 21\n11.5.10 \nDMA2D background PFC control register (DMA2D_BGPFCCR)\nAddress offset: 0x0024\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nALPHA[7:0]\nReserved\nAM[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCS[7:0]\nReserved\nSTART\nCCM\nCM[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrs\nrw\nrw\nrw\nrw\nrw\nBits 31:24 ALPHA[7: 0]: Alpha value\nThese bits define a fixed alpha channel value which can replace the original alpha value \nor be multiplied with the original alpha value according to the alpha mode selected with \nbits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the \ntransfer has started, they are read-only.\nBits 23:18 Reserved, must be kept at reset value\nBits 17:16 AM[1: 0]: Alpha mode\nThese bits define which alpha channel value to be used for the background image. \nThese bits can only be written when data transfers are disabled. Once the transfer has \nstarted, they are read-only.\n00: No modification of the foreground image alpha channel value\n01: Replace original background image alpha channel value by ALPHA[7: 0]\n10: Replace original background image alpha channel value by ALPHA[7:0] multiplied \nwith original alpha channel value\nothers: meaningless\nBits 15:8 CS[7: 0]: CLUT size\nThese bits define the size of the CLUT used for the BG. Once the CLUT transfer has \nstarted, this field is read-only.\nThe number of CLUT entries is equal to CS[7:0] + 1.\nBits 7:6 Reserved, must be kept at reset value\n\n\n<>\n\nRM0090 Rev 21\n365/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\nBit 5 START: Start\nThis bit is set to start the automatic loading of the CLUT. This bit is automatically reset:\n–\nat the end of the transfer \n–\nwhen the transfer is aborted by the user application by setting the ABORT bit in \nthe DMA2D_CR\n–\nwhen a transfer error occurs\n–\nwhen the transfer has not started due to a configuration error or another \ntransfer operation already on going (data transfer or automatic foreground \nCLUT transfer).\nBit 4 CCM: CLUT Color mode\nThese bits define the color format of the CLUT. This register can only be written when \nthe transfer is disabled. Once the CLUT transfer has started, this bit is read-only.\n0: ARGB8888\n1: RGB888\nothers: meaningless\nBits 3:0 CM[3: 0]: Color mode\nThese bits define the color format of the foreground image. These bits can only be \nwritten when data transfers are disabled. Once the transfer has started, they are read-\nonly.\n0000: ARGB8888\n0001: RGB888\n0010: RGB565\n0011: ARGB1555\n0100: ARGB4444\n0101: L8\n0110: AL44\n0111: AL88\n1000: L4\n1001: A8\n1010: A4\nothers: meaningless\n\n\n<>\n\nChrom-Art Accelerator™ controller (DMA2D)\nRM0090\n366/1757\nRM0090 Rev 21\n11.5.11 \nDMA2D background color register (DMA2D_BGCOLR)\nAddress offset: 0x0028\nReset value: 0x0000 0000\n \n11.5.12 \nDMA2D foreground CLUT memory address register\n(DMA2D_FGCMAR)\nAddress offset: 0x002C\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nRED[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nGREEN[7:0]\nBLUE[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value\nBits 23:16 RED[7: 0]: Red Value\nThese bits define the red value for the A4 or A8 mode of the background. These bits \ncan only be written when data transfers are disabled. Once the transfer has started, \nthey are read-only.\nBits 15:8 GREEN[7: 0]: Green Value\nThese bits define the green value for the A4 or A8 mode of the background. These bits \ncan only be written when data transfers are disabled. Once the transfer has started, \nthey are read-only.\nBits 7:0 BLUE[7: 0]: Blue Value\nThese bits define the blue value for the A4 or A8 mode of the background. These bits \ncan only be written when data transfers are disabled. Once the transfer has started, \nthey are read-only.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMA[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMA[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31: 0 MA[31: 0]: Memory Address\nAddress of the data used for the CLUT address dedicated to the foreground image. This \nregister can only be written when no transfer is ongoing. Once the CLUT transfer has \nstarted, this register is read-only.\nIf the foreground CLUT format is 32-bit, the address must be 32-bit aligned.\n\n\n<>\n\nRM0090 Rev 21\n367/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.5.13 \nDMA2D background CLUT memory address register\n(DMA2D_BGCMAR)\nAddress offset: 0x0030\nReset value: 0x0000 0000\n \n11.5.14 \nDMA2D output PFC control register (DMA2D_OPFCCR)\nAddress offset: 0x0034\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMA[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMA[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31: 0 MA[31: 0]: Memory address\nAddress of the data used for the CLUT address dedicated to the background image. \nThis register can only be written when no transfer is on going. Once the CLUT transfer \nhas started, this register is read-only.\nIf the background CLUT format is 32-bit, the address must be 32-bit aligned.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCM[2:0]\nrw\nrw\nrw\nBits 31: 3 Reserved, must be kept at reset value\nBits 2: 0 CM[2: 0]: Color mode\nThese bits define the color format of the output image. These bits can only be written \nwhen data transfers are disabled. Once the transfer has started, they are read-only.\n000: ARGB8888\n001: RGB888\n010: RGB565\n011: ARGB1555\n100: ARGB4444\nothers: meaningless\n\n\n<>\n\nChrom-Art Accelerator™ controller (DMA2D)\nRM0090\n368/1757\nRM0090 Rev 21\n11.5.15 \nDMA2D output color register (DMA2D_OCOLR)\nAddress offset: 0x0038\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nALPHA[7:0]\nRED[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nGREEN[7:0]\nBLUE[7:0]\nRED[4:0]\nGREEN[5:0]\nBLUE[4:0]\nA\nRED[4:0]\nGREEN[4:0]\nBLUE[4:0]\nALPHA[3:0]\nRED[3:0]\nGREEN[3:0]\nBLUE[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 ALPHA[7: 0]: Alpha Channel Value\nThese bits define the alpha channel of the output color. These bits can only be written \nwhen data transfers are disabled. Once the transfer has started, they are read-only.\nBits 23:16 RED[7: 0]: Red Value\nThese bits define the red value of the output image. These bits can only be written when \ndata transfers are disabled. Once the transfer has started, they are read-only.\nBits 15:8 GREEN[7: 0]: Green Value\nThese bits define the green value of the output image. These bits can only be written \nwhen data transfers are disabled. Once the transfer has started, they are read-only.\nBits 7:0 BLUE[7: 0]: Blue Value\nThese bits define the blue value of the output image. These bits can only be written \nwhen data transfers are disabled. Once the transfer has started, they are read-only.\n\n\n<>\n\nRM0090 Rev 21\n369/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.5.16 \nDMA2D output memory address register (DMA2D_OMAR)\nAddress offset: 0x003C\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMA[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMA[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31: 0 MA[31: 0]: Memory Address\nAddress of the data used for the output FIFO. These bits can only be written when data \ntransfers are disabled. Once the transfer has started, they are read-only.\nThe address alignment must match the image format selected e.g. a 32-bit per pixel \nformat must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned.\n\n\n<>\n\nChrom-Art Accelerator™ controller (DMA2D)\nRM0090\n370/1757\nRM0090 Rev 21\n11.5.17 \nDMA2D output offset register (DMA2D_OOR)\nAddress offset: 0x0040\nReset value: 0x0000 0000\n \n11.5.18 \nDMA2D number of line register (DMA2D_NLR)\nAddress offset: 0x0044\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLO[13:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:14 Reserved, must be kept at reset value\nBits 13:0 LO[13: 0]: Line Offset\nLine offset used for the output (expressed in pixels). This value is used for the address \ngeneration. It is added at the end of each line to determine the starting address of the \nnext line. These bits can only be written when data transfers are disabled. Once the \ntransfer has started, they are read-only.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPL[13:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nNL[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value\nBits 29:16 PL[13: 0]: Pixel per lines\nNumber of pixels per lines of the area to be transferred. These bits can only be written \nwhen data transfers are disabled. Once the transfer has started, they are read-only.\nIf any of the input image format is 4-bit per pixel, pixel per lines must be even.\nBits 15:0 NL[15: 0]: Number of lines\nNumber of lines of the area to be transferred. These bits can only be written when data \ntransfers are disabled. Once the transfer has started, they are read-only.\n\n\n<>\n\nRM0090 Rev 21\n371/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.5.19 \nDMA2D line watermark register (DMA2D_LWR)\nAddress offset: 0x0048\nReset value: 0x0000 0000\n \n11.5.20 \nDMA2D AHB master timer configuration register (DMA2D_AMTCR)\nAddress offset: 0x004C\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nLW[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value\nBits 15:0 LW[15:0]: Line watermark \nThese bits allow to configure the line watermark for interrupt generation. \nAn interrupt is raised when the last pixel of the watermarked line has been transferred. \nThese bits can only be written when data transfers are disabled. Once the transfer has \nstarted, they are read-only.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDT[7:0]\nReserved\nEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved\nBits 15:8 DT[7: 0]: Dead Time\nDead time value in the AHB clock cycle inserted between two consecutive accesses on \nthe AHB master port. These bits represent the minimum guaranteed number of cycles \nbetween two consecutive AHB accesses.\nBits 7:1 Reserved\nBit 0 EN: Enable\nEnables the dead time functionality.\n\n\n<>\n\nChrom-Art Accelerator™ controller (DMA2D)\nRM0090\n372/1757\nRM0090 Rev 21\n11.5.21 \nDMA2D register map\nThe following table summarizes the DMA2D registers. Refer to Section 2.3: Memory map \nfor the DMA2D register base address.\n \nTable 61. DMA2D register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x0000\nDMA2D_CR\nReserved\nMODE[1:0]\nReserved\nCEIE\nCTCIE\nCAEIE\nTWIE\nTCIE\nTEIE\nReserved\nABORT\nSUSP\nSTART\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0004\nDMA2D_ISR\nReserved\nCEIF\nCTCIF\nCAEIF\nTWIF\nTCIF\nTEIF\nReset value\n0\n0\n0\n0\n0\n0\n0x0008\nDMA2D_IFCR\nReserved\nCCEIF\nCCTCIF\nCAECIF\nCTWIF\nCTCIF\nCTEIF\nReset value\n0\n0\n0\n0\n0\n0\n0x000C\nDMA2D_FGMAR\nMA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0010\nDMA2D_FGOR\nReserved\nLO[13:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0014\nDMA2D_BGMAR\nMA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0018\nDMA2D_BGOR\nReserved\nLO[13:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x001C\nDMA2D_FGPFCCR\nALPHA[7:0]\nReserved\nAM[1:0]\nCS[7:0]\nRes\nSTART\nCCM\nCM[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0020\nDMA2D_FGCOLR\nAPLHA[7:0]\nRED[7:0]\nGREEN[7:0]\nBLUE[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0024\nDMA2D_BGPFCCR\nALPHA[7:0]\nReserved\nAM[1:0]\nCS[7:0]\nRes\nSTART\nCCM\nCM[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0028\nDMA2D_BGCOLR\nAPLHA[7:0]\nRED[7:0]\nGREEN[7:0]\nBLUE[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x002C\nDMA2D_FGCMAR\nMA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0030\nDMA2D_BGCMAR\nMA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0034\nDMA2D_OPFCCR\nReserved\nCM[2:0]\nReset value\n0\n0\n0\n0x0038\nDMA2D_OCOLR\nAPLHA[7:0]\nRED[7:0]\nGREEN[7:0]\nBLUE[7:0]\nReserved\nRED[4:0]\nGREEN[6:0]\nBLUE[4:0]\nReserved\nA\nRED[4:0]\nGREEN[4:0]\nBLUE[4:0]\nReserved\nALPHA[3:0]\nRED[3:0]\nGREEN[3:0]\nBLUE[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x003C\nDMA2D_OMAR\nMA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n\n\n<>\n\nRM0090 Rev 21\n373/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n0x0040\nDMA2D_OOR\nReserved\nLO[13:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0044\nDMA2D_NLR\nRes\nPL[13:0]\nNL[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0048\nDMA2D_LWR\nReserved\nLW[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x004C\nDMA2D_AMTCR\nReserved\nDT[7:0]\nReserved\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0050-\nOx03FF\n-\nReserved\n0x0400-\n0x07FF\nDMA2D_FGCLUT\nAPLHA[7:0][255:0]\nRED[7:0][255:0]\nGREEN[7:0][255:0]\nBLUE[7:0][255:0]\nReset value\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\n0x0800-\n0x0BFF\nDMA2D_BGCLUT\nAPLHA[7:0][255:0]\nRED[7:0][255:0]\nGREEN[7:0][255:0]\nBLUE[7:0][255:0]\nReset value\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nTable 61. DMA2D register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nInterrupts and events\nRM0090\n374/1757\nRM0090 Rev 21\n12 \nInterrupts and events\nThis Section applies to the whole STM32F4xx family, unless otherwise specified.\n12.1 \nNested vectored interrupt controller (NVIC)\n12.1.1 \nNVIC features\nThe nested vector interrupt controller NVIC includes the following features:\n•\n82 maskable interrupt channels for STM32F405xx/07xx and STM32F415xx/17xx, and \nup to 91 maskable interrupt channels for STM32F42xxx and STM32F43xxx (not \nincluding the 16 interrupt lines of Cortex®-M4 with FPU)\n•\n16 programmable priority levels (4 bits of interrupt priority are used)\n•\nlow-latency exception and interrupt handling\n•\npower management control\n•\nimplementation of system control registers\nThe NVIC and the processor core interface are closely coupled, which enables low latency \ninterrupt processing and efficient processing of late arriving interrupts.\nAll interrupts including the core exceptions are managed by the NVIC. For more information \non exceptions and NVIC programming, refer to programming manual PM0214.\n12.1.2 \nSysTick calibration value register\nThe SysTick calibration value is fixed to 18750, which gives a reference time base of 1 ms \nwith the SysTick clock set to 18.75 MHz (HCLK/8, with HCLK set to 150 MHz). \n12.1.3 \nInterrupt and exception vectors\nSee Table 62 and Table 63, for the vector table for the STM32F405xx/07xx and \nSTM32F415xx/17xx and STM32F42xxx and STM32F43xxx devices.\n12.2 \nExternal interrupt/event controller (EXTI)\nThe external interrupt/event controller consists of up to 23 edge detectors for generating \nevent/interrupt requests. Each input line can be independently configured to select the type \n(interrupt or event) and the corresponding trigger event (rising or falling or both). Each line \ncan also masked independently. A pending register maintains the status line of the interrupt \nrequests.\nThe grey rows in the following tables describe the vectors without specific position.\n\n\n<>\n\nRM0090 Rev 21\n375/1757\nRM0090\nInterrupts and events\n390\n Table 62. Vector table for STM32F405xx/07xx and STM32F415xx/17xx\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\n-\n-\n-\n-\nReserved\n0x0000 0000\n-\n-3\nfixed\nReset\nReset\n0x0000 0004\n-\n-2\nfixed\nNMI\nNon maskable interrupt. The RCC \nClock Security System (CSS) is linked \nto the NMI vector.\n0x0000 0008\n-\n-1\nfixed\nHardFault\nAll class of fault\n0x0000 000C\n-\n0\nsettable\nMemManage\nMemory management\n0x0000 0010\n-\n1\nsettable\nBusFault\nPre-fetch fault, memory access fault\n0x0000 0014\n-\n2\nsettable\nUsageFault\nUndefined instruction or illegal state\n0x0000 0018\n-\n-\n-\n-\nReserved\n0x0000 001C - 0x0000 \n002B\n-\n3\nsettable\nSVCall\nSystem service call via SWI \ninstruction\n0x0000 002C\n-\n4\nsettable\nDebug Monitor\nDebug Monitor\n0x0000 0030\n-\n-\n-\n-\nReserved\n0x0000 0034\n-\n5\nsettable\nPendSV\nPendable request for system service\n0x0000 0038\n-\n6\nsettable\nSysTick\nSystem tick timer\n0x0000 003C\n0\n7\nsettable\nWWDG\nWindow Watchdog interrupt\n0x0000 0040\n1\n8\nsettable\nPVD\nPVD through EXTI line detection \ninterrupt\n0x0000 0044\n2\n9\nsettable\nTAMP_STAMP\nTamper and TimeStamp interrupts \nthrough the EXTI line\n0x0000 0048\n3\n10\nsettable\nRTC_WKUP\nRTC Wake-up interrupt through the \nEXTI line\n0x0000 004C\n4\n11\nsettable\nFLASH\nFlash global interrupt\n0x0000 0050\n5\n12\nsettable\nRCC\nRCC global interrupt\n0x0000 0054\n6\n13\nsettable\nEXTI0\nEXTI Line0 interrupt\n0x0000 0058\n7\n14\nsettable\nEXTI1\nEXTI Line1 interrupt\n0x0000 005C\n8\n15\nsettable\nEXTI2\nEXTI Line2 interrupt\n0x0000 0060\n9\n16\nsettable\nEXTI3\nEXTI Line3 interrupt\n0x0000 0064\n10\n17\nsettable\nEXTI4\nEXTI Line4 interrupt\n0x0000 0068\n11\n18\nsettable\nDMA1_Stream0\nDMA1 Stream0 global interrupt \n0x0000 006C\n\n\n<>\n\nInterrupts and events\nRM0090\n376/1757\nRM0090 Rev 21\n12\n19\nsettable\nDMA1_Stream1\nDMA1 Stream1 global interrupt\n0x0000 0070\n13\n20\nsettable\nDMA1_Stream2\nDMA1 Stream2 global interrupt\n0x0000 0074\n14\n21\nsettable\nDMA1_Stream3\nDMA1 Stream3 global interrupt\n0x0000 0078\n15\n22\nsettable\nDMA1_Stream4\nDMA1 Stream4 global interrupt\n0x0000 007C\n16\n23\nsettable\nDMA1_Stream5\nDMA1 Stream5 global interrupt\n0x0000 0080\n17\n24\nsettable\nDMA1_Stream6\nDMA1 Stream6 global interrupt\n0x0000 0084\n18\n25\nsettable\nADC\nADC1, ADC2 and ADC3 global \ninterrupts\n0x0000 0088\n19\n26\nsettable\nCAN1_TX\nCAN1 TX interrupts\n0x0000 008C\n20\n27\nsettable\nCAN1_RX0\nCAN1 RX0 interrupts\n0x0000 0090\n21\n28\nsettable\nCAN1_RX1\nCAN1 RX1 interrupt\n0x0000 0094\n22\n29\nsettable\nCAN1_SCE\nCAN1 SCE interrupt\n0x0000 0098\n23\n30\nsettable\nEXTI9_5\nEXTI Line[9:5] interrupts\n0x0000 009C\n24\n31\nsettable\nTIM1_BRK_TIM9\nTIM1 Break interrupt and TIM9 global \ninterrupt\n0x0000 00A0\n25\n32\nsettable\nTIM1_UP_TIM10\nTIM1 Update interrupt and TIM10 \nglobal interrupt\n0x0000 00A4\n26\n33\nsettable\nTIM1_TRG_COM_TIM11\nTIM1 Trigger and Commutation \ninterrupts and TIM11 global interrupt\n0x0000 00A8\n27\n34\nsettable\nTIM1_CC\nTIM1 Capture Compare interrupt\n0x0000 00AC\n28\n35\nsettable\nTIM2\nTIM2 global interrupt\n0x0000 00B0\n29\n36\nsettable\nTIM3\nTIM3 global interrupt\n0x0000 00B4\n30\n37\nsettable\nTIM4\nTIM4 global interrupt\n0x0000 00B8\n31\n38\nsettable\nI2C1_EV\nI2C1 event interrupt\n0x0000 00BC\n32\n39\nsettable\nI2C1_ER\nI2C1 error interrupt\n0x0000 00C0\n33\n40\nsettable\nI2C2_EV\nI2C2 event interrupt\n0x0000 00C4\n34\n41\nsettable\nI2C2_ER\nI2C2 error interrupt\n0x0000 00C8\n35\n42\nsettable\nSPI1\nSPI1 global interrupt\n0x0000 00CC\n36\n43\nsettable\nSPI2\nSPI2 global interrupt\n0x0000 00D0\n37\n44\nsettable\nUSART1\nUSART1 global interrupt\n0x0000 00D4\n38\n45\nsettable\nUSART2\nUSART2 global interrupt\n0x0000 00D8\n39\n46\nsettable\nUSART3\nUSART3 global interrupt\n0x0000 00DC\nTable 62. Vector table for STM32F405xx/07xx and STM32F415xx/17xx (continued)\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\n\n\n<>\n\nRM0090 Rev 21\n377/1757\nRM0090\nInterrupts and events\n390\n40\n47\nsettable\nEXTI15_10\nEXTI Line[15:10] interrupts\n0x0000 00E0\n41\n48\nsettable\nRTC_Alarm\nRTC Alarms (A and B) through EXTI \nline interrupt\n0x0000 00E4\n42\n49\nsettable\nOTG_FS_WKUP\nUSB On-The-Go FS Wake-up through \nEXTI line interrupt\n0x0000 00E8\n43\n50\nsettable\nTIM8_BRK_TIM12\nTIM8 Break interrupt and TIM12 \nglobal interrupt\n0x0000 00EC\n44\n51\nsettable\nTIM8_UP_TIM13\nTIM8 Update interrupt and TIM13 \nglobal interrupt\n0x0000 00F0\n45\n52\nsettable\nTIM8_TRG_COM_TIM14 TIM8 Trigger and Commutation \ninterrupts and TIM14 global interrupt\n0x0000 00F4\n46\n53\nsettable\nTIM8_CC\nTIM8 Capture Compare interrupt\n0x0000 00F8\n47\n54\nsettable\nDMA1_Stream7\nDMA1 Stream7 global interrupt \n0x0000 00FC\n48\n55\nsettable\nFSMC\nFSMC global interrupt\n0x0000 0100\n49\n56\nsettable\nSDIO\nSDIO global interrupt\n0x0000 0104\n50\n57\nsettable\nTIM5\nTIM5 global interrupt\n0x0000 0108\n51\n58\nsettable\nSPI3\nSPI3 global interrupt\n0x0000 010C\n52\n59\nsettable\nUART4\nUART4 global interrupt\n0x0000 0110\n53\n60\nsettable\nUART5\nUART5 global interrupt\n0x0000 0114\n54\n61\nsettable\nTIM6_DAC\nTIM6 global interrupt,\nDAC1 and DAC2 underrun error \ninterrupts\n0x0000 0118\n55\n62\nsettable\nTIM7\nTIM7 global interrupt\n0x0000 011C\n56\n63\nsettable\nDMA2_Stream0\nDMA2 Stream0 global interrupt \n0x0000 0120\n57\n64\nsettable\nDMA2_Stream1\nDMA2 Stream1 global interrupt\n0x0000 0124\n58\n65\nsettable\nDMA2_Stream2\nDMA2 Stream2 global interrupt\n0x0000 0128\n59\n66\nsettable\nDMA2_Stream3\nDMA2 Stream3 global interrupt\n0x0000 012C\n60\n67\nsettable\nDMA2_Stream4\nDMA2 Stream4 global interrupt\n0x0000 0130\n61\n68\nsettable\nETH\nEthernet global interrupt \n0x0000 0134\n62\n69\nsettable\nETH_WKUP\nEthernet Wake-up through EXTI line \ninterrupt\n0x0000 0138\n63\n70\nsettable\nCAN2_TX\nCAN2 TX interrupts\n0x0000 013C\n64\n71\nsettable\nCAN2_RX0\nCAN2 RX0 interrupts\n0x0000 0140\nTable 62. Vector table for STM32F405xx/07xx and STM32F415xx/17xx (continued)\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\n\n\n<>\n\nInterrupts and events\nRM0090\n378/1757\nRM0090 Rev 21\n \n65\n72\nsettable\nCAN2_RX1\nCAN2 RX1 interrupt\n0x0000 0144\n66\n73\nsettable\nCAN2_SCE\nCAN2 SCE interrupt\n0x0000 0148\n67\n74\nsettable\nOTG_FS\nUSB On The Go FS global interrupt\n0x0000 014C\n68\n75\nsettable\nDMA2_Stream5\nDMA2 Stream5 global interrupt \n0x0000 0150\n69\n76\nsettable\nDMA2_Stream6\nDMA2 Stream6 global interrupt \n0x0000 0154\n70\n77\nsettable\nDMA2_Stream7\nDMA2 Stream7 global interrupt \n0x0000 0158\n71\n78\nsettable\nUSART6\nUSART6 global interrupt \n0x0000 015C\n72\n79\nsettable\nI2C3_EV\nI2C3 event interrupt\n0x0000 0160\n73\n80\nsettable\nI2C3_ER\nI2C3 error interrupt\n0x0000 0164\n74\n81\nsettable\nOTG_HS_EP1_OUT\nUSB On The Go HS End Point 1 Out \nglobal interrupt \n0x0000 0168\n75\n82\nsettable\nOTG_HS_EP1_IN\nUSB On The Go HS End Point 1 In \nglobal interrupt \n0x0000 016C\n76\n83\nsettable\nOTG_HS_WKUP\nUSB On The Go HS Wake-up through \nEXTI interrupt \n0x0000 0170\n77\n84\nsettable\nOTG_HS\nUSB On The Go HS global interrupt \n0x0000 0174\n78\n85\nsettable\nDCMI\nDCMI global interrupt \n0x0000 0178\n79\n86\nsettable\nCRYP\nCRYP crypto global interrupt\n0x0000 017C\n80\n87\nsettable\nHASH_RNG\nHash and Rng global interrupt \n0x0000 0180\n81\n88\nsettable\nFPU\nFPU global interrupt\n0x0000 0184\nTable 62. Vector table for STM32F405xx/07xx and STM32F415xx/17xx (continued)\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\nTable 63. Vector table for STM32F42xxx and STM32F43xxx\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\n-\n-\n-\n-\nReserved\n0x0000 0000\n-\n-3\nfixed\nReset\nReset\n0x0000 0004\n-\n-2\nfixed\nNMI\nNon maskable interrupt, Clock Security \nSystem\n0x0000 0008\n\n\n<>\n\nRM0090 Rev 21\n379/1757\nRM0090\nInterrupts and events\n390\n-\n-1\nfixed\nHardFault\nAll class of fault\n0x0000 000C\n-\n0\nsettable\nMemManage\nMemory management\n0x0000 0010\n-\n1\nsettable\nBusFault\nPre-fetch fault, memory access fault\n0x0000 0014\n-\n2\nsettable\nUsageFault\nUndefined instruction or illegal state\n0x0000 0018\n-\n-\n-\n-\nReserved\n0x0000 001C - \n0x0000 002B\n-\n3\nsettable\nSVCall\nSystem Service call via SWI instruction\n0x0000 002C\n-\n4\nsettable\nDebug Monitor\nDebug Monitor\n0x0000 0030\n-\n-\n-\nReserved\n0x0000 0034\n-\n5\nsettable\nPendSV\nPendable request for system service\n0x0000 0038\n-\n6\nsettable\nSystick\nSystem tick timer\n0x0000 003C\n0\n7\nsettable\nWWDG\nWindow Watchdog interrupt\n0x0000 0040\n1\n8\nsettable\nPVD\nPVD through EXTI line detection interrupt\n0x0000 0044\n2\n9\nsettable\nTAMP_STAMP\nTamper and TimeStamp interrupts through \nthe EXTI line\n0x0000 0048\n3\n10\nsettable\nRTC_WKUP\nRTC Wake-up interrupt through the EXTI \nline\n0x0000 004C\n4\n11\nsettable\nFLASH\nFlash global interrupt\n0x0000 0050\n5\n12\nsettable\nRCC\nRCC global interrupt\n0x0000 0054\n6\n13\nsettable\nEXTI0\nEXTI Line0 interrupt\n0x0000 0058\n7\n14\nsettable\nEXTI1\nEXTI Line1 interrupt\n0x0000 005C\n8\n15\nsettable\nEXTI2\nEXTI Line2 interrupt\n0x0000 0060\n9\n16\nsettable\nEXTI3\nEXTI Line3 interrupt\n0x0000 0064\n10\n17\nsettable\nEXTI4\nEXTI Line4 interrupt\n0x0000 0068\n11\n18\nsettable\nDMA1_Stream0\nDMA1 Stream0 global interrupt \n0x0000 006C\n12\n19\nsettable\nDMA1_Stream1\nDMA1 Stream1 global interrupt\n0x0000 0070\n13\n20\nsettable\nDMA1_Stream2\nDMA1 Stream2 global interrupt\n0x0000 0074\n14\n21\nsettable\nDMA1_Stream3\nDMA1 Stream3 global interrupt\n0x0000 0078\n15\n22\nsettable\nDMA1_Stream4\nDMA1 Stream4 global interrupt\n0x0000 007C\n16\n23\nsettable\nDMA1_Stream5\nDMA1 Stream5 global interrupt\n0x0000 0080\n17\n24\nsettable\nDMA1_Stream6\nDMA1 Stream6 global interrupt\n0x0000 0084\nTable 63. Vector table for STM32F42xxx and STM32F43xxx (continued)\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\n\n\n<>\n\nInterrupts and events\nRM0090\n380/1757\nRM0090 Rev 21\n18\n25\nsettable\nADC\nADC1, ADC2 and ADC3 global interrupts\n0x0000 0088\n19\n26\nsettable\nCAN1_TX\nCAN1 TX interrupts\n0x0000 008C\n20\n27\nsettable\nCAN1_RX0\nCAN1 RX0 interrupts\n0x0000 0090\n21\n28\nsettable\nCAN1_RX1\nCAN1 RX1 interrupt\n0x0000 0094\n22\n29\nsettable\nCAN1_SCE\nCAN1 SCE interrupt\n0x0000 0098\n23\n30\nsettable\nEXTI9_5\nEXTI Line[9:5] interrupts\n0x0000 009C\n24\n31\nsettable\nTIM1_BRK_TIM9\nTIM1 Break interrupt and TIM9 global \ninterrupt\n0x0000 00A0\n25\n32\nsettable\nTIM1_UP_TIM10\nTIM1 Update interrupt and TIM10 global \ninterrupt\n0x0000 00A4\n26\n33\nsettable\nTIM1_TRG_COM_TIM11\nTIM1 Trigger and Commutation interrupts \nand TIM11 global interrupt\n0x0000 00A8\n27\n34\nsettable\nTIM1_CC\nTIM1 Capture Compare interrupt\n0x0000 00AC\n28\n35\nsettable\nTIM2\nTIM2 global interrupt\n0x0000 00B0\n29\n36\nsettable\nTIM3\nTIM3 global interrupt\n0x0000 00B4\n30\n37\nsettable\nTIM4\nTIM4 global interrupt\n0x0000 00B8\n31\n38\nsettable\nI2C1_EV\nI2C1 event interrupt\n0x0000 00BC\n32\n39\nsettable\nI2C1_ER\nI2C1 error interrupt\n0x0000 00C0\n33\n40\nsettable\nI2C2_EV\nI2C2 event interrupt\n0x0000 00C4\n34\n41\nsettable\nI2C2_ER\nI2C2 error interrupt\n0x0000 00C8\n35\n42\nsettable\nSPI1\nSPI1 global interrupt\n0x0000 00CC\n36\n43\nsettable\nSPI2\nSPI2 global interrupt\n0x0000 00D0\n37\n44\nsettable\nUSART1\nUSART1 global interrupt\n0x0000 00D4\n38\n45\nsettable\nUSART2\nUSART2 global interrupt\n0x0000 00D8\n39\n46\nsettable\nUSART3\nUSART3 global interrupt\n0x0000 00DC\n40\n47\nsettable\nEXTI15_10\nEXTI Line[15:10] interrupts\n0x0000 00E0\n41\n48\nsettable\nRTC_Alarm\nRTC Alarms (A and B) through EXTI line \ninterrupt\n0x0000 00E4\n42\n49\nsettable\nOTG_FS_WKUP\nUSB On-The-Go FS Wake-up through EXTI \nline interrupt\n0x0000 00E8\n43\n50\nsettable\nTIM8_BRK_TIM12\nTIM8 Break interrupt and TIM12 global \ninterrupt\n0x0000 00EC\nTable 63. Vector table for STM32F42xxx and STM32F43xxx (continued)\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\n\n\n<>\n\nRM0090 Rev 21\n381/1757\nRM0090\nInterrupts and events\n390\n44\n51\nsettable\nTIM8_UP_TIM13\nTIM8 Update interrupt and TIM13 global \ninterrupt\n0x0000 00F0\n45\n52\nsettable\nTIM8_TRG_COM_TIM1\n4\nTIM8 Trigger and Commutation interrupts \nand TIM14 global interrupt\n0x0000 00F4\n46\n53\nsettable\nTIM8_CC\nTIM8 Capture Compare interrupt\n0x0000 00F8\n47\n54\nsettable\nDMA1_Stream7\nDMA1 Stream7 global interrupt \n0x0000 00FC\n48\n55\nsettable\nFSMC\nFSMC global interrupt\n0x0000 0100\n49\n56\nsettable\nSDIO\nSDIO global interrupt\n0x0000 0104\n50\n57\nsettable\nTIM5\nTIM5 global interrupt\n0x0000 0108\n51\n58\nsettable\nSPI3\nSPI3 global interrupt\n0x0000 010C\n52\n59\nsettable\nUART4\nUART4 global interrupt\n0x0000 0110\n53\n60\nsettable\nUART5\nUART5 global interrupt\n0x0000 0114\n54\n61\nsettable\nTIM6_DAC\nTIM6 global interrupt,\nDAC1 and DAC2 underrun error interrupts\n0x0000 0118\n55\n62\nsettable\nTIM7\nTIM7 global interrupt\n0x0000 011C\n56\n63\nsettable\nDMA2_Stream0\nDMA2 Stream0 global interrupt \n0x0000 0120\n57\n64\nsettable\nDMA2_Stream1\nDMA2 Stream1 global interrupt\n0x0000 0124\n58\n65\nsettable\nDMA2_Stream2\nDMA2 Stream2 global interrupt\n0x0000 0128\n59\n66\nsettable\nDMA2_Stream3\nDMA2 Stream3 global interrupt\n0x0000 012C\n60\n67\nsettable\nDMA2_Stream4\nDMA2 Stream4 global interrupt\n0x0000 0130\n61\n68\nsettable\nETH\nEthernet global interrupt \n0x0000 0134\n62\n69\nsettable\nETH_WKUP\nEthernet Wake-up through EXTI line \ninterrupt\n0x0000 0138\n63\n70\nsettable\nCAN2_TX\nCAN2 TX interrupts\n0x0000 013C\n64\n71\nsettable\nCAN2_RX0\nCAN2 RX0 interrupts\n0x0000 0140\n65\n72\nsettable\nCAN2_RX1\nCAN2 RX1 interrupt\n0x0000 0144\n66\n73\nsettable\nCAN2_SCE\nCAN2 SCE interrupt\n0x0000 0148\n67\n74\nsettable\nOTG_FS\nUSB On The Go FS global interrupt\n0x0000 014C\n68\n75\nsettable\nDMA2_Stream5\nDMA2 Stream5 global interrupt \n0x0000 0150\n69\n76\nsettable\nDMA2_Stream6\nDMA2 Stream6 global interrupt \n0x0000 0154\n70\n77\nsettable\nDMA2_Stream7\nDMA2 Stream7 global interrupt \n0x0000 0158\n71\n78\nsettable\nUSART6\nUSART6 global interrupt \n0x0000 015C\nTable 63. Vector table for STM32F42xxx and STM32F43xxx (continued)\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\n\n\n<>\n\nInterrupts and events\nRM0090\n382/1757\nRM0090 Rev 21\n12.2.1 \nEXTI main features\nThe main features of the EXTI controller are the following:\n•\nindependent trigger and mask on each interrupt/event line\n•\ndedicated status bit for each interrupt line \n•\ngeneration of up to 23 software event/interrupt requests\n•\ndetection of external signals with a pulse width lower than the APB2 clock period. Refer \nto the electrical characteristics section of the STM32F4xx datasheets for details on this \nparameter.\n72\n79\nsettable\nI2C3_EV\nI2C3 event interrupt\n0x0000 0160\n73\n80\nsettable\nI2C3_ER\nI2C3 error interrupt\n0x0000 0164\n74\n81\nsettable\nOTG_HS_EP1_OUT\nUSB On The Go HS End Point 1 Out global \ninterrupt \n0x0000 0168\n75\n82\nsettable\nOTG_HS_EP1_IN\nUSB On The Go HS End Point 1 In global \ninterrupt \n0x0000 016C\n76\n83\nsettable\nOTG_HS_WKUP\nUSB On The Go HS Wake-up through EXTI \ninterrupt \n0x0000 0170\n77\n84\nsettable\nOTG_HS\nUSB On The Go HS global interrupt \n0x0000 0174\n78\n85\nsettable\nDCMI\nDCMI global interrupt \n0x0000 0178\n79\n86\nsettable\nCRYP\nCRYP crypto global interrupt\n0x0000 017C\n80\n87\nsettable\nHASH_RNG\nHash and Rng global interrupt \n0x0000 0180\n81\n88\nSettable\nFPU\nFPU global interrupt\n0x0000 0184\n82\n89\nsettable\nUART7\nUART 7 global interrupt\n0x0000 0188\n83\n90\nsettable\nUART8\nUART 8 global interrupt\n0x0000 018C\n84\n91\nsettable\nSPI4\nSPI 4 global interrupt\n0x0000 0190\n85\n92\nsettable\nSPI5\nSPI 5 global interrupt\n0x0000 0194\n86\n93\nsettable\nSPI6\nSPI 6 global interrupt\n0x0000 0198\n87\n94\nsettable\nSAI1\nSAI1 global interrupt\n0x0000 019C\n88\n95\nsettable\nLCD-TFT\nLTDC global interrupt\n0x0000 01A0\n89\n96\nsettable\nLCD-TFT\nLTDC global Error interrupt\n0x0000 01A4\n90\n97\nsettable\nDMA2D\nDMA2D global interrupt\n0x0000 01A8\nTable 63. Vector table for STM32F42xxx and STM32F43xxx (continued)\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\n\n\n<>\n\nRM0090 Rev 21\n383/1757\nRM0090\nInterrupts and events\n390\n12.2.2 \nEXTI block diagram\nFigure 41 shows the block diagram.\nFigure 41. External interrupt/event controller block diagram\n12.2.3 \nWake-up event management\nThe STM32F4xx are able to handle external or internal events in order to wake up the core \n(WFE). The wake-up event can be generated either by:\n•\nenabling an interrupt in the peripheral control register but not in the NVIC, and enabling \nthe SEVONPEND bit in the Cortex®-M4 with FPU System Control register. When the \nMCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC \nIRQ channel pending bit (in the NVIC interrupt clear pending register) have to be \ncleared.\n•\nor configuring an external or internal EXTI line in event mode. When the CPU resumes \nfrom WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC \nIRQ channel pending bit as the pending bit corresponding to the event line is not set.\nTo use an external line as a wake-up event, refer to Section 12.2.4: Functional description.\n12.2.4 \nFunctional description\nTo generate the interrupt, the interrupt line should be configured and enabled. This is done \nby programming the two trigger registers with the desired edge detection and by enabling \nthe interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register. \nWhen the selected edge occurs on the external interrupt line, an interrupt request is \nPeripheral interface\nEdge detect \ncircuit\nAMBA APB bus\nPCLK2\n23\n23\n23\n23\n23\n23\n23\nTo NVIC interrupt\ncontroller\nSoftware \ninterrupt \nevent \nregister\nRising \ntrigger \nselection \nregister\n23\nEvent\nmask\nregister\nPulse \ngenerator\n23\n23\n23\n23\nInput\nline\nPending\nrequest\nregister\n23\nMS32662V1\nInterrupt\nmask\nregister\nFalling\ntrigger \nselection \nregister\n\n\n<>\n\nInterrupts and events\nRM0090\n384/1757\nRM0090 Rev 21\ngenerated. The pending bit corresponding to the interrupt line is also set. This request is \nreset by writing a ‘1’ in the pending register.\nTo generate the event, the event line should be configured and enabled. This is done by \nprogramming the two trigger registers with the desired edge detection and by enabling the \nevent request by writing a ‘1’ to the corresponding bit in the event mask register. When the \nselected edge occurs on the event line, an event pulse is generated. The pending bit \ncorresponding to the event line is not set.\nAn interrupt/event request can also be generated by software by writing a ‘1’ in the software \ninterrupt/event register.\nHardware interrupt selection\nTo configure the 23 lines as interrupt sources, use the following procedure:\n•\nConfigure the mask bits of the 23 interrupt lines (EXTI_IMR)\n•\nConfigure the Trigger selection bits of the interrupt lines (EXTI_RTSR and EXTI_FTSR)\n•\nConfigure the enable and mask bits that control the NVIC IRQ channel mapped to the \nexternal interrupt controller (EXTI) so that an interrupt coming from one of the 23 lines \ncan be correctly acknowledged.\nHardware event selection\nTo configure the 23 lines as event sources, use the following procedure:\n•\nConfigure the mask bits of the 23 event lines (EXTI_EMR)\n•\nConfigure the Trigger selection bits of the event lines (EXTI_RTSR and EXTI_FTSR)\nSoftware interrupt/event selection\nThe 23 lines can be configured as software interrupt/event lines. The following is the \nprocedure to generate a software interrupt.\n•\nConfigure the mask bits of the 23 interrupt/event lines (EXTI_IMR, EXTI_EMR)\n•\nSet the required bit in the software interrupt register (EXTI_SWIER)\n\n\n<>\n\nRM0090 Rev 21\n385/1757\nRM0090\nInterrupts and events\n390\n12.2.5 \nExternal interrupt/event line mapping\nUp to 140 GPIOs (STM32F405xx/07xx and STM32F415xx/17xx), 168 GPIOs \n(STM32F42xxx and STM32F43xxx) are connected to the 16 external interrupt/event lines in \nthe following manner:\nFigure 42. External interrupt/event GPIO mapping\n(STM32F405xx/07xx and STM32F415xx/17xx)\nPA0\nPB0\nPC0\nPD0\nPE0\nPF0\nPG0\nPH0\nPI0\nPA1\nPB1\nPC1\nPD1\nPE1\nPF1\nPG1\nPH1\nPI1\nPA15\nPB15\nPC15\nPD15\nPE15\nPF15\nPG15\nPH15\nEXTI0\nEXTI1\nEXTI15\nEXTI15[3:0] bits in the SYSCFG_EXTICR4 register\n. . .\nEXTI1[3:0] bits in the SYSCFG_EXTICR1 register\nEXTI0[3:0] bits in the SYSCFG_EXTICR1 register\nai15897\n\n\n<>\n\nInterrupts and events\nRM0090\n386/1757\nRM0090 Rev 21\nFigure 43. External interrupt/event GPIO mapping (STM32F42xxx and STM32F43xxx)\nThe seven other EXTI lines are connected as follows:\n•\nEXTI line 16 is connected to the PVD output\n•\nEXTI line 17 is connected to the RTC Alarm event\n•\nEXTI line 18 is connected to the USB OTG FS Wake-up event\n•\nEXTI line 19 is connected to the Ethernet Wake-up event\n•\nEXTI line 20 is connected to the USB OTG HS (configured in FS) Wake-up event\n•\nEXTI line 21 is connected to the RTC Tamper and TimeStamp events\n•\nEXTI line 22 is connected to the RTC Wake-up event\nPA0\nPB0\nPC0\nPD0\nPE0\nPF0\nPG0\nPH0\nPI0\nPA1\nPB1\nPC1\nPD1\nPE1\nPF1\nPG1\nPH1\nPI1\nPA15\nPB15\nPC15\nPD15\nPE15\nPF15\nPG15\nPH15\nEXTI0\nEXTI1\nEXTI15\nEXTI15[3:0] bits in the SYSCFG_EXTICR4 register\nEXTI1[3:0] bits in the SYSCFG_EXTICR1 register\nEXTI0[3:0] bits in the SYSCFG_EXTICR1 register\nMS30440V1\nPJ0\nPK0\nPJ1\nPK1\nPJ15\n\n\n<>\n\nRM0090 Rev 21\n387/1757\nRM0090\nInterrupts and events\n390\n12.3 \nEXTI registers\nRefer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in \nregister descriptions.\n12.3.1 \nInterrupt mask register (EXTI_IMR)\nAddress offset: 0x00\nReset value: 0x0000 0000\n \n \n12.3.2 \nEvent mask register (EXTI_EMR)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nMR22\nMR21\nMR20\nMR19\nMR18\nMR17\nMR16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMR15\nMR14\nMR13\nMR12\nMR11\nMR10\nMR9\nMR8\nMR7\nMR6\nMR5\nMR4\nMR3\nMR2\nMR1\nMR0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:23 Reserved, must be kept at reset value.\nBits 22:0 MRx: Interrupt mask on line x\n0: Interrupt request from line x is masked\n1: Interrupt request from line x is not masked\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nMR22\nMR21\nMR20\nMR19\nMR18\nMR17\nMR16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMR15\nMR14\nMR13\nMR12\nMR11\nMR10\nMR9\nMR8\nMR7\nMR6\nMR5\nMR4\nMR3\nMR2\nMR1\nMR0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:23 Reserved, must be kept at reset value.\nBits 22:0 MRx: Event mask on line x\n0: Event request from line x is masked\n1: Event request from line x is not masked\n\n\n<>\n\nInterrupts and events\nRM0090\n388/1757\nRM0090 Rev 21\n12.3.3 \nRising trigger selection register (EXTI_RTSR)\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n \nNote:\nThe external wake-up lines are edge triggered, no glitch must be generated on these lines.\nIf a rising edge occurs on the external interrupt line while writing to the EXTI_RTSR register, \nthe pending bit is be set.\nRising and falling edge triggers can be set for the same interrupt line. In this configuration, \nboth generate a trigger condition.\n12.3.4 \nFalling trigger selection register (EXTI_FTSR)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n \n \nNote:\nThe external wake-up lines are edge triggered, no glitch must be generated on these lines.\nIf a falling edge occurs on the external interrupt line while writing to the EXTI_FTSR register, \nthe pending bit is not set.\nRising and falling edge triggers can be set for the same interrupt line. In this configuration, \nboth generate a trigger condition.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTR22\nTR21\nTR20\nTR19\nTR18\nTR17\nTR16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTR15\nTR14\nTR13\nTR12\nTR11\nTR10\nTR9\nTR8\nTR7\nTR6\nTR5\nTR4\nTR3\nTR2\nTR1\nTR0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:23 Reserved, must be kept at reset value.\nBits 22:0 TRx: Rising trigger event configuration bit of line x\n0: Rising trigger disabled (for Event and Interrupt) for input line\n1: Rising trigger enabled (for Event and Interrupt) for input line\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTR22\nTR21\nTR20\nTR19\nTR18\nTR17\nTR16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTR15\nTR14\nTR13\nTR12\nTR11\nTR10\nTR9\nTR8\nTR7\nTR6\nTR5\nTR4\nTR3\nTR2\nTR1\nTR0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:23 Reserved, must be kept at reset value.\nBits 22:0 TRx: Falling trigger event configuration bit of line x\n0: Falling trigger disabled (for Event and Interrupt) for input line\n1: Falling trigger enabled (for Event and Interrupt) for input line.\n\n\n<>\n\nRM0090 Rev 21\n389/1757\nRM0090\nInterrupts and events\n390\n12.3.5 \nSoftware interrupt event register (EXTI_SWIER)\nAddress offset: 0x10\nReset value: 0x0000 0000\n \n \n12.3.6 \nPending register (EXTI_PR)\nAddress offset: 0x14\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nSWIER\n22\nSWIER\n21\nSWIER\n20\nSWIER\n19\nSWIER\n18\nSWIER\n17\nSWIER\n16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSWIER\n15\nSWIER\n14\nSWIER\n13\nSWIER\n12\nSWIER\n11\nSWIER\n10\nSWIER\n9\nSWIER\n8\nSWIER\n7\nSWIER\n6\nSWIER\n5\nSWIER\n4\nSWIER\n3\nSWIER\n2\nSWIER\n1\nSWIER\n0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:23 Reserved, must be kept at reset value.\nBits 22:0 SWIERx: Software Interrupt on line x\nIf interrupt are enabled on line x in the EXTI_IMR register, writing '1' to SWIERx bit when it is \nset at '0' sets the corresponding pending bit in the EXTI_PR register, thus resulting in an \ninterrupt request generation. \nThis bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to the bit).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPR22\nPR21\nPR20\nPR19\nPR18\nPR17\nPR16\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPR15\nPR14\nPR13\nPR12\nPR11\nPR10\nPR9\nPR8\nPR7\nPR6\nPR5\nPR4\nPR3\nPR2\nPR1\nPR0\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nBits 31:23 Reserved, must be kept at reset value.\nBits 22:0 PRx: Pending bit\n0: No trigger request occurred\n1: selected trigger request occurred\nThis bit is set when the selected edge event arrives on the external interrupt line. \nThis bit is cleared by programming it to ‘1’. \n\n\n<>\n\nInterrupts and events\nRM0090\n390/1757\nRM0090 Rev 21\n12.3.7 \nEXTI register map\nTable 65 gives the EXTI register map and the reset values.\n \n \nRefer to Section 2.3: Memory map for the register boundary addresses.\nTable 64. External interrupt/event controller register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nEXTI_IMR\nReserved\nMR[22:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nEXTI_EMR\nReserved\nMR[22:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nEXTI_RTSR\nReserved\nTR[22:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nEXTI_FTSR\nReserved\nTR[22:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nEXTI_SWIER\nReserved\nSWIER[22:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nEXTI_PR\nReserved\nPR[22:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n\n\n<>\n\nRM0090 Rev 21\n391/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13 \nAnalog-to-digital converter (ADC)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n13.1 \nADC introduction\nThe 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 \nmultiplexed channels allowing it to measure signals from 16 external sources, two internal \nsources, and the VBAT channel. The A/D conversion of the channels can be performed in \nsingle, continuous, scan or discontinuous mode. The result of the ADC is stored into a left- \nor right-aligned 16-bit data register.\nThe analog watchdog feature allows the application to detect if the input voltage goes \nbeyond the user-defined, higher or lower thresholds.\n13.2 \nADC main features\n•\n12-bit, 10-bit, 8-bit or 6-bit configurable resolution\n•\nInterrupt generation at the end of conversion, end of injected conversion, and in case of \nanalog watchdog or overrun events\n•\nSingle and continuous conversion modes\n•\nScan mode for automatic conversion of channel 0 to channel ‘n’\n•\nData alignment with in-built data coherency\n•\nChannel-wise programmable sampling time\n•\nExternal trigger option with configurable polarity for both regular and injected \nconversions\n•\nDiscontinuous mode\n•\nDual/Triple mode (on devices with 2 ADCs or more)\n•\nConfigurable DMA data storage in Dual/Triple ADC mode\n•\nConfigurable delay between conversions in Dual/Triple interleaved mode\n•\nADC conversion type (refer to the datasheets)\n•\nADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at slower \nspeed\n•\nADC input range: VREF– ≤ VIN ≤ VREF+\n•\nDMA request generation during regular channel conversion\nFigure 44 shows the block diagram of the ADC.\nNote:\nVREF–, if available (depending on package), must be tied to VSSA.\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n392/1757\nRM0090 Rev 21\n13.3 \nADC functional description\nFigure 44 shows a single ADC block diagram and Table 66 gives the ADC pin description.\nFigure 44. Single ADC block diagram\nADCx_IN0\nADCx_IN1\nAnalog to digital\nconverter\nADCx_IN15\nAnalog\nmux\nADCCLK\nADC Interrupt to NVIC\nGPIO\nports \nAnalog watchdog\nAddress/data bus\nLower threshold (12 bits)\nCompare result \nHigher threshold (12 bits)\nFlags\nenable bits\nEOC\nAWD\nAnalog watchdog event\nVDDA\nVSSA\nVREF+\nVREF-\nInterrupt\nEXTI_11\nTIM3_CH2\nFrom ADC prescaler\n (16 bits)\nEnd of conversion \n channels\nInjected\n channels\nEnd of injected conversion \nJEOC\nEOCIE\nAWDIE \nJEOCIE\nup to 4\nup to 16\nRegular data register\n (4 x 16 bits)\nInjected data registers\nRegular\nStart trigger\n(regular group)\nEXTSEL[3:0] bits\nEXTEN\nTIM3_CH4\nEXTI_15\nTIM1_TRGO\nTIM2_CH1\nTIM2_TRGO\nStart trigger\n(injected group)\nJEXTSEL[3:0] bits\nTIM1_CH4\nJEXTEN\n[1:0] bits\n[1:0] bits\nDMA request\nTemp. sensor\nVREFINT\nOVR OVRIE\nDMA overrun\nVBAT\nTIM5_CH4\nTIM5_TRGO\nTIM4_CH2\nTIM4_CH3\nTIM4_TRGO\nTIM4_CH1\nTIM8_CH3\nTIM8_CH4\nTIM8_CH2\nTIM2_CH3\nTIM2_CH4\nTIM1_CH2\nTIM1_CH3\nTIM2_CH2\nTIM1_CH1\nTIM5_CH1\nTIM5_CH2\nTIM3_CH1\nTIM3_TRGO\nTIM4_CH4\nTIM2_TRGO\nTIM8_CH1\nTIM8_TRGO\nTIM5_CH3\nai16046\n\n\n<>\n\nRM0090 Rev 21\n393/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n \n13.3.1 \nADC on-off control\nThe ADC is powered on by setting the ADON bit in the ADC_CR2 register. When the ADON \nbit is set for the first time, it wakes up the ADC from the Power-down mode.\nConversion starts when either the SWSTART or the JSWSTART bit is set.\nYou can stop conversion and put the ADC in power down mode by clearing the ADON bit. In \nthis mode the ADC consumes almost no power (only a few µA). \n13.3.2 \nADC clock\nThe ADC features two clock schemes: \n•\nClock for the analog circuitry: ADCCLK, common to all ADCs\nThis clock is generated from the APB2 clock divided by a programmable prescaler that \nallows the ADC to work at fPCLK2/2, /4, /6 or /8. Refer to the datasheets for the \nmaximum value of ADCCLK. \n•\nClock for the digital interface (used for registers read/write access) \nThis clock is equal to the APB2 clock. The digital interface clock can be \nenabled/disabled individually for each ADC through the RCC APB2 peripheral clock \nenable register (RCC_APB2ENR).\n13.3.3 \nChannel selection\nThere are 16 multiplexed channels. It is possible to organize the conversions in two groups: \nregular and injected. A group consists of a sequence of conversions that can be done on \nany channel and in any order. For instance, it is possible to implement the conversion \nsequence in the following order: ADC_IN3, ADC_IN8, ADC_IN2, ADC_IN2, ADC_IN0, \nADC_IN2, ADC_IN2, ADC_IN15.\n•\nA regular group is composed of up to 16 conversions. The regular channels and their \norder in the conversion sequence must be selected in the ADC_SQRx registers. The \ntotal number of conversions in the regular group must be written in the L[3:0] bits in the \nADC_SQR1 register.\n•\nAn injected group is composed of up to 4 conversions. The injected channels and \ntheir order in the conversion sequence must be selected in the ADC_JSQR register. \nTable 66. ADC pins\nName\nSignal type\nRemarks\nVREF+\nInput, analog reference \npositive\nThe higher/positive reference voltage for the ADC,\n1.8 V ≤ VREF+ ≤ VDDA\nVDDA\nInput, analog supply\nAnalog power supply equal to VDD and \n2.4 V ≤ VDDA ≤ VDD (3.6 V) for full speed\n1.8 V ≤ VDDA ≤ VDD (3.6 V) for reduced speed\nVREF–\nInput, analog reference \nnegative\nThe lower/negative reference voltage for the ADC, \nVREF– = VSSA\nVSSA\nInput, analog supply \nground\nGround for analog power supply equal to VSS\nADCx_IN[15:0]\nAnalog input signals\n16 analog input channels\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n394/1757\nRM0090 Rev 21\nThe total number of conversions in the injected group must be written in the L[1:0] bits \nin the ADC_JSQR register.\nIf the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current \nconversion is reset and a new start pulse is sent to the ADC to convert the newly chosen \ngroup.\nTemperature sensor, VREFINT and VBAT internal channels\n•\nFor the STM32F40x and STM32F41x devices, the temperature sensor is internally \nconnected to channel ADC1_IN16. \nThe internal reference voltage VREFINT is connected to ADC1_IN17. \n•\nFor the STM32F42x and STM32F43x devices, the temperature sensor is internally \nconnected to ADC1_IN18 channel which is shared with VBAT. Only one conversion, \ntemperature sensor or VBAT, must be selected at a time. When the temperature sensor \nand VBAT conversion are set simultaneously, only the VBAT conversion is performed. \nThe internal reference voltage VREFINT is connected to ADC1_IN17.\nThe VBAT channel (connected to channel ADC1_IN18) can also be converted as an injected \nor regular channel.\nNote:\nThe temperature sensor, VREFINT and the VBAT channel are available only on the master \nADC1 peripheral.\n13.3.4 \nSingle conversion mode\nIn Single conversion mode the ADC does one conversion. This mode is started with the \nCONT bit at 0 by either:\n•\nsetting the SWSTART bit in the ADC_CR2 register (for a regular channel only)\n•\nsetting the JSWSTART bit (for an injected channel)\n•\nexternal trigger (for a regular or injected channel)\nOnce the conversion of the selected channel is complete:\n•\nIf a regular channel was converted:\n–\nThe converted data are stored into the 16-bit ADC_DR register\n–\nThe EOC (end of conversion) flag is set\n–\nAn interrupt is generated if the EOCIE bit is set\n•\nIf an injected channel was converted:\n–\nThe converted data are stored into the 16-bit ADC_JDR1 register\n–\nThe JEOC (end of conversion injected) flag is set\n–\nAn interrupt is generated if the JEOCIE bit is set\nThen the ADC stops.\n\n\n<>\n\nRM0090 Rev 21\n395/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.3.5 \nContinuous conversion mode\nIn continuous conversion mode, the ADC starts a new conversion as soon as it finishes one. \nThis mode is started with the CONT bit at 1 either by external trigger or by setting the \nSWSTART bit in the ADC_CR2 register (for regular channels only).\nAfter each conversion:\n•\nIf a regular group of channels was converted:\n–\nThe last converted data are stored into the 16-bit ADC_DR register\n–\nThe EOC (end of conversion) flag is set\n–\nAn interrupt is generated if the EOCIE bit is set\nNote:\nInjected channels cannot be converted continuously. The only exception is when an injected \nchannel is configured to be converted automatically after regular channels in continuous \nmode (using JAUTO bit), refer to Auto-injection section).\n13.3.6 \nTiming diagram\nAs shown in Figure 45, the ADC needs a stabilization time of tSTAB before it starts \nconverting accurately. After the start of the ADC conversion and after 15 clock cycles, the \nEOC flag is set and the 16-bit ADC data register contains the result of the conversion.\nFigure 45. Timing diagram \n13.3.7 \nAnalog watchdog\nThe AWD analog watchdog status bit is set if the analog voltage converted by the ADC is \nbelow a lower threshold or above a higher threshold. These thresholds are programmed in \nthe 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can \nbe enabled by using the AWDIE bit in the ADC_CR1 register.\nThe threshold value is independent of the alignment selected by the ALIGN bit in the \nADC_CR2 register. The analog voltage is compared to the lower and higher thresholds \nbefore alignment.\nTable 67 shows how the ADC_CR1 register should be configured to enable the analog \nwatchdog on one or more channels.\nADC_CLK\nEOC\nNext ADC conversion\nADC conversion\nConversion time \ntSTAB\nADC\nSoftware clears the EOC bit\n \n(total conv. time)\nStart 1st conversion\nStart next conversion\nai16047b\nADON\nSWSTART/\nJSWSTART\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n396/1757\nRM0090 Rev 21\nFigure 46. Analog watchdog’s guarded area\n \n13.3.8 \nScan mode\nThis mode is used to scan a group of analog channels.\nThe Scan mode is selected by setting the SCAN bit in the ADC_CR1 register. Once this bit \nhas been set, the ADC scans all the channels selected in the ADC_SQRx registers (for \nregular channels) or in the ADC_JSQR register (for injected channels). A single conversion \nis performed for each channel of the group. After each end of conversion, the next channel \nin the group is converted automatically. If the CONT bit is set, regular channel conversion \ndoes not stop at the last selected channel in the group but continues again from the first \nselected channel.\nIf the DMA bit is set, the direct memory access (DMA) controller is used to transfer the data \nconverted from the regular group of channels (stored in the ADC_DR register) to SRAM \nafter each regular channel conversion.\nThe EOC bit is set in the ADC_SR register:\n•\nAt the end of each regular group sequence if the EOCS bit is cleared to 0\n•\nAt the end of each regular channel conversion if the EOCS bit is set to 1\nThe data converted from an injected channel are always stored into the ADC_JDRx \nregisters.\nTable 67. Analog watchdog channel selection\nChannels guarded by the analog \nwatchdog\nADC_CR1 register control bits (x = don’t care)\nAWDSGL bit\nAWDEN bit\nJAWDEN bit\nNone\nx\n0\n0\nAll injected channels\n0\n0\n1\nAll regular channels\n0\n1\n0\nAll regular and injected channels\n0\n1\n1\nSingle(1) injected channel\n1.\nSelected by the AWDCH[4:0] bits\n1\n0\n1\nSingle(1) regular channel\n1\n1\n0\nSingle (1) regular or injected channel\n1\n1\n1\nAnalog voltage\nHigher threshold\nLower threshold\nGuarde d area\nHTR\nLTR\nai16048\n\n\n<>\n\nRM0090 Rev 21\n397/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.3.9 \nInjected channel management\nTriggered injection\nTo use triggered injection, the JAUTO bit must be cleared in the ADC_CR1 register.\n1.\nStart the conversion of a group of regular channels either by external trigger or by \nsetting the SWSTART bit in the ADC_CR2 register.\n2. \nIf an external injected trigger occurs or if the JSWSTART bit is set during the \nconversion of a regular group of channels, the current conversion is reset and the \ninjected channel sequence switches to Scan-once mode.\n3. \nThen, the regular conversion of the regular group of channels is resumed from the last \ninterrupted regular conversion.\nIf a regular event occurs during an injected conversion, the injected conversion is not \ninterrupted but the regular sequence is executed at the end of the injected sequence. \nFigure 47 shows the corresponding timing diagram.\nNote:\nWhen using triggered injection, one must ensure that the interval between trigger events is \nlonger than the injection sequence. For instance, if the sequence length is 30 ADC clock \ncycles (that is two conversions with a sampling time of 3 clock periods), the minimum \ninterval between triggers must be 31 ADC clock cycles.\nAuto-injection\nIf the JAUTO bit is set, then the channels in the injected group are automatically converted \nafter the regular group of channels. This can be used to convert a sequence of up to 20 \nconversions programmed in the ADC_SQRx and ADC_JSQR registers.\nIn this mode, external trigger on injected channels must be disabled.\nIf the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected \nchannels are continuously converted.\nNote:\nIt is not possible to use both the auto-injected and discontinuous modes simultaneously.\nFigure 47. Injected conversion latency\n1.\nThe maximum latency value can be found in the electrical characteristics of the STM32F40x and \nSTM32F41x datasheets.\nADCCLK\nInjection event\nReset ADC\nSOC\nmax latency (1)\nai16049\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n398/1757\nRM0090 Rev 21\n13.3.10 \nDiscontinuous mode\nRegular group\nThis mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to \nconvert a short sequence of n conversions (n ≤ 8) that is part of the sequence of conversions \nselected in the ADC_SQRx registers. The value of n is specified by writing to the \nDISCNUM[2:0] bits in the ADC_CR1 register.\nWhen an external trigger occurs, it starts the next n conversions selected in the ADC_SQRx \nregisters until all the conversions in the sequence are done. The total sequence length is \ndefined by the L[3:0] bits in the ADC_SQR1 register.\nExample:\n•\nn = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10\n•\n1st trigger: sequence converted 0, 1, 2. An EOC event is generated at each \nconversion.\n•\n2nd trigger: sequence converted 3, 6, 7. An EOC event is generated at each \nconversion\n•\n3rd trigger: sequence converted 9, 10.An EOC event is generated at each conversion\n•\n4th trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion\nNote:\nWhen a regular group is converted in discontinuous mode, no rollover occurs.\nWhen all subgroups are converted, the next trigger starts the conversion of the first \nsubgroup. In the example above, the 4th trigger reconverts the channels 0, 1 and 2 in the \n1st subgroup.\nInjected group\nThis mode is enabled by setting the JDISCEN bit in the ADC_CR1 register. It can be used to \nconvert the sequence selected in the ADC_JSQR register, channel by channel, after an \nexternal trigger event.\nWhen an external trigger occurs, it starts the next channel conversions selected in the \nADC_JSQR registers until all the conversions in the sequence are done. The total sequence \nlength is defined by the JL[1:0] bits in the ADC_JSQR register.\nExample:\nn = 1, channels to be converted = 1, 2, 3\n1st trigger: channel 1 converted \n2nd trigger: channel 2 converted \n3rd trigger: channel 3 converted and JEOC event generated\n4th trigger: channel 1\nNote:\nWhen all injected channels are converted, the next trigger starts the conversion of the first \ninjected channel. In the example above, the 4th trigger reconverts the 1st injected channel \n1.\nIt is not possible to use both the auto-injected and discontinuous modes simultaneously.\nDiscontinuous mode must not be set for regular and injected groups at the same time. \nDiscontinuous mode must be enabled only for the conversion of one group.\n\n\n<>\n\nRM0090 Rev 21\n399/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.4 \nData alignment\nThe ALIGN bit in the ADC_CR2 register selects the alignment of the data stored after \nconversion. Data can be right- or left-aligned as shown in Figure 48 and Figure 49.\nThe converted data value from the injected group of channels is decreased by the user-\ndefined offset written in the ADC_JOFRx registers so the result can be a negative value. \nThe SEXT bit represents the extended sign value.\nFor channels in a regular group, no offset is subtracted so only twelve bits are significant.\nFigure 48. Right alignment of 12-bit data\nFigure 49. Left alignment of 12-bit data\nSpecial case: when left-aligned, the data are aligned on a half-word basis except when the \nresolution is set to 6-bit. in that case, the data are aligned on a byte basis as shown in \nFigure 50.\nFigure 50. Left alignment of 6-bit data\nD7\nD8\n D9\nD6\nD5\n D4\nD3\n D2\n D1\n D0\n D10\n D11\n SEXT\n SEXT\n SEXT\n SEXT\nD7\nD8\n D10\n D11\n Injected group\n Regular group\n0\n0\n0\n0\n D9\nD6\nD5\n D4\nD3\n D2\n D1\n D0\nai16050\nD4\nD5\n D6 \nD3\nD2\n D1\nD0\n 0 0 0\n D7\n D8\nD9\n D10\n D11\n SEXT\n Injected group\n Regular group\nai16051\nD11\nD10\nD9\nD8\nD7\nD6\nD5\nD4\nD3\nD2\nD1\nD0\n0\n0\n0\n0\nD4\nD5\n SEXT\n SEXT\nSEXT\nSEXT\n SEXT\n SEXT\n Injected group\n Regular group\nai16052\n0\n0\n0\n0\n0\n0\nD5\nD4\nD3\nD2\nD1\nD0\n0\n0\n0\n0\n SEXT\n SEXT\nD3\nD2\nD1\nD0\n0\n SEXT\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n400/1757\nRM0090 Rev 21\n13.5 \nChannel-wise programmable sampling time\nThe ADC samples the input voltage for a number of ADCCLK cycles that can be modified \nusing the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can \nbe sampled with a different sampling time.\nThe total conversion time is calculated as follows:\nTconv = Sampling time + 12 cycles\nExample:\nWith ADCCLK = 30 MHz and sampling time = 3 cycles:\nTconv = 3 + 12 = 15 cycles = 0.5 µs with APB2 at 60 MHz\n13.6 \nConversion on external trigger and trigger polarity\nConversion can be triggered by an external event (e.g. timer capture, EXTI line). If the \nEXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected \nconversion) are different from “0b00”, then external events are able to trigger a conversion \nwith the selected polarity. Table 68 provides the correspondence between the EXTEN[1:0] \nand JEXTEN[1:0] values and the trigger polarity.\n \nNote:\nThe polarity of the external trigger can be changed on the fly.\nThe EXTSEL[3:0] and JEXTSEL[3:0] control bits are used to select which out of 16 possible \nevents can trigger conversion for the regular and injected groups.\nTable 69 gives the possible external trigger for regular conversion.\nTable 68. Configuring the trigger polarity\nSource\nEXTEN[1:0] / JEXTEN[1:0]\nTrigger detection disabled\n00\nDetection on the rising edge\n01\nDetection on the falling edge\n10\nDetection on both the rising and falling edges\n11\n\n\n<>\n\nRM0090 Rev 21\n401/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n \nTable 70 gives the possible external trigger for injected conversion.\nTable 69. External trigger for regular channels\nSource\nType\nEXTSEL[3:0]\nTIM1_CH1 event \nInternal signal from on-chip \ntimers\n0000\nTIM1_CH2 event\n0001\nTIM1_CH3 event\n0010\nTIM2_CH2 event\n0011\nTIM2_CH3 event\n0100\nTIM2_CH4 event\n0101\nTIM2_TRGO event\n0110\nTIM3_CH1 event\n0111\nTIM3_TRGO event\n1000\nTIM4_CH4 event\n1001\nTIM5_CH1 event \n1010\nTIM5_CH2 event\n1011\nTIM5_CH3 event\n1100\nTIM8_CH1 event\n1101\nTIM8_TRGO event\n1110\nEXTI line11\nExternal pin\n1111\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n402/1757\nRM0090 Rev 21\n \nSoftware source trigger events can be generated by setting SWSTART (for regular \nconversion) or JSWSTART (for injected conversion) in ADC_CR2.\nA regular group conversion can be interrupted by an injected trigger.\nNote:\nThe trigger selection can be changed on the fly. However, when the selection changes, \nthere is a time frame of 1 APB clock cycle during which the trigger detection is disabled. \nThis is to avoid spurious detection during transitions.\n13.7 \nFast conversion mode\nIt is possible to perform faster conversion by reducing the ADC resolution. The RES bits are \nused to select the number of bits available in the data register. The minimum conversion \ntime for each resolution is then as follows:\n•\n12 bits: 3 + 12 = 15 ADCCLK cycles\n•\n10 bits: 3 + 10 = 13 ADCCLK cycles\n•\n8 bits: 3 + 8 = 11 ADCCLK cycles\n•\n6 bits: 3 + 6 = 9 ADCCLK cycles\nTable 70. External trigger for injected channels\nSource\nConnection type\nJEXTSEL[3:0]\nTIM1_CH4 event \nInternal signal from on-chip \ntimers\n0000\nTIM1_TRGO event\n0001\nTIM2_CH1 event\n0010\nTIM2_TRGO event\n0011\nTIM3_CH2 event\n0100\nTIM3_CH4 event\n0101\nTIM4_CH1 event \n0110\nTIM4_CH2 event\n0111\nTIM4_CH3 event\n1000\nTIM4_TRGO event\n1001\nTIM5_CH4 event\n1010\nTIM5_TRGO event\n1011\nTIM8_CH2 event\n1100\nTIM8_CH3 event\n1101\nTIM8_CH4 event\n1110\nEXTI line15\nExternal pin\n1111\n\n\n<>\n\nRM0090 Rev 21\n403/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.8 \nData management\n13.8.1 \nUsing the DMA\nSince converted regular channel values are stored into a unique data register, it is useful to \nuse DMA for conversion of more than one regular channel. This avoids the loss of the data \nalready stored in the ADC_DR register.\nWhen the DMA mode is enabled (DMA bit set to 1 in the ADC_CR2 register), after each \nconversion of a regular channel, a DMA request is generated. This allows the transfer of the \nconverted data from the ADC_DR register to the destination location selected by the \nsoftware.\nDespite this, if data are lost (overrun), the OVR bit in the ADC_SR register is set and an \ninterrupt is generated (if the OVRIE enable bit is set). DMA transfers are then disabled and \nDMA requests are no longer accepted. In this case, if a DMA request is made, the regular \nconversion in progress is aborted and further regular triggers are ignored. It is then \nnecessary to clear the OVR flag and the DMAEN bit in the used DMA stream, and to re-\ninitialize both the DMA and the ADC to have the wanted converted channel data transferred \nto the right memory location. Only then can the conversion be resumed and the data \ntransfer, enabled again. Injected channel conversions are not impacted by overrun errors.\nWhen OVR = 1 in DMA mode, the DMA requests are blocked after the last valid data have \nbeen transferred, which means that all the data transferred to the RAM can be considered \nas valid.\nAt the end of the last DMA transfer (number of transfers configured in the DMA controller’s \nDMA_SxNDTR register):\n•\nNo new DMA request is issued to the DMA controller if the DDS bit is cleared to 0 in the \nADC_CR2 register (this avoids generating an overrun error). However the DMA bit is \nnot cleared by hardware. It must be written to 0, then to 1 to start a new transfer.\n•\nRequests can continue to be generated if the DDS bit is set to 1. This allows \nconfiguring the DMA in double-buffer circular mode.\nTo recover the ADC from OVR state when the DMA is used, follow the steps below:\n1.\nReinitialize the DMA (adjust destination address and NDTR counter)\n2. \nClear the ADC OVR bit in ADC_SR register\n3. \nTrigger the ADC to start the conversion.\n13.8.2 \nManaging a sequence of conversions without using the DMA\nIf the conversions are slow enough, the conversion sequence can be handled by the \nsoftware. In this case the EOCS bit must be set in the ADC_CR2 register for the EOC status \nbit to be set at the end of each conversion, and not only at the end of the sequence. When \nEOCS = 1, overrun detection is automatically enabled. Thus, each time a conversion is \ncomplete, EOC is set and the ADC_DR register can be read. The overrun management is \nthe same as when the DMA is used.\nTo recover the ADC from OVR state when the EOCS is set, follow the steps below:\n1.\nClear the ADC OVR bit in ADC_SR register\n2. \nTrigger the ADC to start the conversion.\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n404/1757\nRM0090 Rev 21\n13.8.3 \nConversions without DMA and without overrun detection\nIt may be useful to let the ADC convert one or more channels without reading the data each \ntime (if there is an analog watchdog for instance). For that, the DMA must be disabled \n(DMA = 0) and the EOC bit must be set at the end of a sequence only (EOCS = 0). In this \nconfiguration, overrun detection is disabled.\n13.9 \nMulti ADC mode\nIn devices with two ADCs or more, the Dual (with two ADCs) and Triple (with three ADCs) \nADC modes can be used (see Figure 51).\nIn multi ADC mode, the start of conversion is triggered alternately or simultaneously by the \nADC1 master to the ADC2 and ADC3 slaves, depending on the mode selected by the \nMULTI[4:0] bits in the ADC_CCR register.\nNote:\nIn multi ADC mode, when configuring conversion trigger by an external event, the \napplication must set trigger by the master only and disable trigger by slaves to prevent \nspurious triggers that would start unwanted slave conversions.\nThe four possible modes below are implemented:\n•\nInjected simultaneous mode\n•\nRegular simultaneous mode\n•\nInterleaved mode\n•\nAlternate trigger mode\nIt is also possible to use the previous modes combined in the following ways:\n•\nInjected simultaneous mode + Regular simultaneous mode\n•\nRegular simultaneous mode + Alternate trigger mode\nNote:\nIn multi ADC mode, the converted data can be read on the multi-mode data register \n(ADC_CDR). The status bits can be read in the multi-mode status register (ADC_CSR).\n\n\n<>\n\nRM0090 Rev 21\n405/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\nFigure 51. Multi ADC block diagram(1)\n1.\nAlthough external triggers are present on ADC2 and ADC3 they are not shown in this diagram.\n2.\nIn the Dual ADC mode, the ADC3 slave part is not present.\n3.\nIn Triple ADC mode, the ADC common data register (ADC_CDR) contains the ADC1, ADC2 and ADC3’s \nregular converted data. All 32 register bits are used according to a selected storage order.\nIn Dual ADC mode, the ADC common data register (ADC_CDR) contains both the ADC1 and ADC2’s \nregular converted data. All 32 register bits are used.\nADCx_IN0\nADCx_IN1\nADCx_IN15\nGPIO\nPorts \nAddress/data bus\nEXTI_11\nEXTI_15\nInjected data registers\n (4 x 16 bits)\nRegular\n channels\nInjected\n channels\nADC3(2) (Slave)\n (12 bits)\nInjected data registers\n (4 x 16 bits)\nRegular\n channels\nInjected\n channels\nADC1 (Master)\nDual/Triple\ninternal triggers \nStart trigger mux\n \n(regular group)\n(injected group)\nStart trigger mux\n control\nTemp. sensor\nVREFINT\nRegular data register\n (16 bits)\nRegular data register\n (16 bits)\nCommon regular data register\n (32 bits)(3)\nVBAT\nCommon part\n mode\nADC2 (Slave)\n (12 bits)\nInjected data registers\n (4 x 16 bits)\nRegular\n channels\nInjected\n channels\nRegular data register\n (16 bits)\nai16053\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n406/1757\nRM0090 Rev 21\n•\nDMA requests in Multi ADC mode:\nIn Multi ADC mode the DMA may be configured to transfer converted data in three \ndifferent modes. In all cases, the DMA streams to use are those connected to the ADC:\n–\nDMA mode 1: On each DMA request (one data item is available), a half-word \nrepresenting an ADC-converted data item is transferred.\nIn Triple ADC mode, ADC1 data are transferred on the first request, ADC2 data \nare transferred on the second request and ADC3 data are transferred on the third \nrequest; the sequence is repeated. So the DMA first transfers ADC1 data followed \nby ADC2 data followed by ADC3 data and so on.\nDMA mode 1 is used in regular simultaneous triple mode only.\nExample:\nRegular simultaneous triple mode: 3 consecutive DMA requests are generated \n(one for each converted data item)\n1st request: ADC_CDR[31:0] = ADC1_DR[15:0]\n2nd request: ADC_CDR[31:0] = ADC2_DR[15:0]\n3rd request: ADC_CDR[31:0] = ADC3_DR[15:0]\n4th request: ADC_CDR[31:0] = ADC1_DR[15:0]\n–\nDMA mode 2: On each DMA request (two data items are available) two half-\nwords representing two ADC-converted data items are transferred as a word.\nIn Dual ADC mode, both ADC2 and ADC1 data are transferred on the first request \n(ADC2 data take the upper half-word and ADC1 data take the lower half-word) and \nso on.\nIn Triple ADC mode, three DMA requests are generated. On the first request, both \nADC2 and ADC1 data are transferred (ADC2 data take the upper half-word and \nADC1 data take the lower half-word). On the second request, both ADC1 and \nADC3 data are transferred (ADC1 data take the upper half-word and ADC3 data \ntake the lower half-word).On the third request, both ADC3 and ADC2 data are \ntransferred (ADC3 data take the upper half-word and ADC2 data take the lower \nhalf-word) and so on.\nDMA mode 2 is used in interleaved mode and in regular simultaneous mode (for \nDual ADC mode only).\nExample:\na) \nInterleaved dual mode: a DMA request is generated each time 2 data items are \navailable:\n1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0] \n2nd request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0] \nb) \nInterleaved triple mode: a DMA request is generated each time 2 data items are \navailable\n1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0] \n2nd request: ADC_CDR[31:0] = ADC1_DR[15:0] | ADC3_DR[15:0] \n3rd request: ADC_CDR[31:0] = ADC3_DR[15:0] | ADC2_DR[15:0] \n4th request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]\n–\nDMA mode 3: This mode is similar to the DMA mode 2. The only differences are \nthat the on each DMA request (two data items are available) two bytes \n\n\n<>\n\nRM0090 Rev 21\n407/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\nrepresenting two ADC converted data items are transferred as a half-word. The \ndata transfer order is similar to that of the DMA mode 2.\nDMA mode 3 is used in interleaved mode in 6-bit and 8-bit resolutions (dual and \ntriple mode).\nExample:\na) \nInterleaved dual mode: a DMA request is generated each time 2 data items are \navailable\n1st request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]\n2nd request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]\nb) \nInterleaved triple mode: a DMA request is generated each time 2 data items are \navailable\n1st request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]\n2nd request: ADC_CDR[15:0] = ADC1_DR[7:0] | ADC3_DR[7:0]\n3rd request: ADC_CDR[15:0] = ADC3_DR[7:0] | ADC2_DR[7:0]\n4th request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]\nOverrun detection: If an overrun is detected on one of the concerned ADCs (ADC1 and \nADC2 in dual and triple modes, ADC3 in triple mode only), the DMA requests are no longer \nissued to ensure that all the data transferred to the RAM are valid. It may happen that the \nEOC bit corresponding to one ADC remains set because the data register of this ADC \ncontains valid data.\n13.9.1 \nInjected simultaneous mode\nThis mode converts an injected group of channels. The external trigger source comes from \nthe injected group multiplexer of ADC1 (selected by the JEXTSEL[3:0] bits in the ADC1_CR2 \nregister). A simultaneous trigger is provided to ADC2 and ADC3.\nNote:\nDo not convert the same channel on the two/three ADCs (no overlapping sampling times for \nthe two/three ADCs when converting the same channel).\nIn simultaneous mode, one must convert sequences with the same length or ensure that the \ninterval between triggers is longer than the longer of the 2 sequences (Dual ADC mode) /3 \nsequences (Triple ADC mode). Otherwise, the ADC with the shortest sequence may restart \nwhile the ADC with the longest sequence is completing the previous conversions.\nRegular conversions can be performed on one or all ADCs. In that case, they are \nindependent of each other and are interrupted when an injected event occurs. They are \nresumed at the end of the injected conversion group.\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n408/1757\nRM0090 Rev 21\nDual ADC mode\nAt the end of conversion event on ADC1 or ADC2:\n•\nThe converted data are stored into the ADC_JDRx registers of each ADC interface.\n•\nA JEOC interrupt is generated (if enabled on one of the two ADC interfaces) when the \nADC1/ADC2’s injected channels have all been converted.\nFigure 52. Injected simultaneous mode on 4 channels: dual ADC mode\nTriple ADC mode\nAt the end of conversion event on ADC1, ADC2 or ADC3:\n•\nThe converted data are stored into the ADC_JDRx registers of each ADC interface.\n•\nA JEOC interrupt is generated (if enabled on one of the three ADC interfaces) when the \nADC1/ADC2/ADC3’s injected channels have all been converted.\nFigure 53. Injected simultaneous mode on 4 channels: triple ADC mode\n13.9.2 \nRegular simultaneous mode\nThis mode is performed on a regular group of channels. The external trigger source comes \nfrom the regular group multiplexer of ADC1 (selected by the EXTSEL[3:0] bits in the \nADC1_CR2 register). A simultaneous trigger is provided to ADC2 and ADC3.\nNote:\nDo not convert the same channel on the two/three ADCs (no overlapping sampling times for \nthe two/three ADCs when converting the same channel).\nIn regular simultaneous mode, one must convert sequences with the same length or ensure \nthat the interval between triggers is longer than the long conversion time of the 2 sequences \n(Dual ADC mode) /3 sequences (Triple ADC mode). Otherwise, the ADC with the shortest \nsequence may restart while the ADC with the longest sequence is completing the previous \nconversions.\nInjected conversions must be disabled.\nCH0\nCH1\nCH2\nCH3\nCH15\nCH14\nCH13\nCH12\nADC1\nADC2\nTrigger\nEnd of conversion on ADC1 and ADC2\nConversion\nSampling\nCH15\nCH0\n...\n...\nai16054\nCH0\nCH1\nCH2\nCH3\nCH15\nCH14\nCH13\nCH12\nADC1\nADC2\nTrigger\nEnd of conversion on ADC1, ADC2 and ADC3\nConversion\nSampling\nCH15\nCH0\n...\n...\nai16055\nCH10\nCH12\nCH8\nCH5\nADC3\nCH2\n...\n\n\n<>\n\nRM0090 Rev 21\n409/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\nDual ADC mode\nAt the end of conversion event on ADC1 or ADC2:\n•\nA 32-bit DMA transfer request is generated (if DMA[1:0] bits in the ADC_CCR register \nare equal to 0b10). This request transfers the ADC2 converted data stored in the upper \nhalf-word of the ADC_CDR 32-bit register to the SRAM and then the ADC1 converted \ndata stored in the lower half-word of ADC_CDR to the SRAM.\n•\nAn EOC interrupt is generated (if enabled on one of the two ADC interfaces) when the \nADC1/ADC2’s regular channels have all been converted.\nFigure 54. Regular simultaneous mode on 16 channels: dual ADC mode\nTriple ADC mode\nAt the end of conversion event on ADC1, ADC2 or ADC3:\n•\nThree 32-bit DMA transfer requests are generated (if DMA[1:0] bits in the ADC_CCR \nregister are equal to 0b01). Three transfers then take place from the ADC_CDR 32-bit \nregister to SRAM: first the ADC1 converted data, then the ADC2 converted data and \nfinally the ADC3 converted data. The process is repeated for each new three \nconversions.\n•\nAn EOC interrupt is generated (if enabled on one of the three ADC interfaces) when the \nADC1/ADC2/ADC3’s regular channels are have all been converted.\nFigure 55. Regular simultaneous mode on 16 channels: triple ADC mode\nCH0\nCH1\nCH2\nCH3\nCH15\nCH14\nCH13\nCH12\nADC1\nADC2\nTrigger\nEnd of conversion on ADC1 and ADC2\nConversion\nSampling\nCH15\nCH0\n...\n...\nai16054\nCH0\nCH1\nCH2\nCH3\nCH15\nCH14\nCH13\nCH12\nADC1\nADC2\nTrigger\nEnd of conversion on ADC1, ADC2 and ADC3\nConversion\nSampling\nCH15\nCH0\n...\n...\nai16055\nCH10\nCH12\nCH8\nCH5\nADC3\nCH2\n...\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n410/1757\nRM0090 Rev 21\n13.9.3 \nInterleaved mode\nThis mode can be started only on a regular group (usually one channel). The external \ntrigger source comes from the regular channel multiplexer of ADC1.\nDual ADC mode\nAfter an external trigger occurs:\n•\nADC1 starts immediately\n•\nADC2 starts after a delay of several ADC clock cycles\nThe minimum delay which separates 2 conversions in interleaved mode is configured in the \nDELAY bits in the ADC_CCR register. However, an ADC cannot start a conversion if the \ncomplementary ADC is still sampling its input (only one ADC can sample the input signal at \na given time). In this case, the delay becomes the sampling time + 2 ADC clock cycles. For \ninstance, if DELAY = 5 clock cycles and the sampling takes 15 clock cycles on both ADCs, \nthen 17 clock cycles separate conversions on ADC1 and ADC2).\nIf the CONT bit is set on both ADC1 and ADC2, the selected regular channels of both ADCs \nare continuously converted.\nNote:\nIf the conversion sequence is interrupted (for instance when DMA end of transfer occurs), \nthe multi-ADC sequencer must be reset by configuring it in independent mode first (bits \nDUAL[4:0] = 00000) before reprogramming the interleaved mode.\nAfter an EOC interrupt is generated by ADC2 (if enabled through the EOCIE bit) a 32-bit \nDMA transfer request is generated (if the DMA[1:0] bits in ADC_CCR are equal to 0b10). \nThis request first transfers the ADC2 converted data stored in the upper half-word of the \nADC_CDR 32-bit register into SRAM, then the ADC1 converted data stored in the register’s \nlower half-word into SRAM.\nFigure 56. Interleaved mode on 1 channel in continuous conversion mode: dual ADC \nmode\nTriple ADC mode\nAfter an external trigger occurs:\n•\nADC1 starts immediately and\n•\nADC2 starts after a delay of several ADC clock cycles\n•\nADC3 starts after a delay of several ADC clock cycles referred to the ADC2 conversion\nThe minimum delay which separates 2 conversions in interleaved mode is configured in the \nDELAY bits in the ADC_CCR register. However, an ADC cannot start a conversion if the \ncomplementary ADC is still sampling its input (only one ADC can sample the input signal at \nCH0\nCH0\nADC1\nADC2\nTrigger\nEnd of conversion on ADC2\nCH0\nCH0\n...\n...\n8 ADCCLK\ncycles\nEnd of conversion on ADC1\nConversion\nSampling\nai16056\n\n\n<>\n\nRM0090 Rev 21\n411/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\na given time). In this case, the delay becomes the sampling time + 2 ADC clock cycles. For \ninstance, if DELAY = 5 clock cycles and the sampling takes 15 clock cycles on the three \nADCs, then 17 clock cycles separate the conversions on ADC1, ADC2 and ADC3).\nIf the CONT bit is set on ADC1, ADC2 and ADC3, the selected regular channels of all ADCs \nare continuously converted.\nNote:\nIf the conversion sequence is interrupted (for instance when DMA end of transfer occurs), \nthe multi-ADC sequencer must be reset by configuring it in independent mode first (bits \nDUAL[4:0] = 00000) before reprogramming the interleaved mode.\nIn this mode a DMA request is generated each time 2 data items are available, (if the \nDMA[1:0] bits in the ADC_CCR register are equal to 0b10). The request first transfers the \nfirst converted data stored in the lower half-word of the ADC_CDR 32-bit register to SRAM, \nthen it transfers the second converted data stored in ADC_CDR’s upper half-word to SRAM. \nThe sequence is the following:\n•\n1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0] \n•\n2nd request: ADC_CDR[31:0] = ADC1_DR[15:0] | ADC3_DR[15:0] \n•\n3rd request: ADC_CDR[31:0] = ADC3_DR[15:0] | ADC2_DR[15:0] \n•\n4th request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0], ...\nFigure 57. Interleaved mode on 1 channel in continuous conversion mode: triple ADC \nmode\n13.9.4 \nAlternate trigger mode\nThis mode can be started only on an injected group. The source of external trigger comes \nfrom the injected group multiplexer of ADC1.\nNote:\nRegular conversions can be enabled on one or all ADCs. In this case the regular \nconversions are independent of each other. A regular conversion is interrupted when the \nADC1\nADC2\nTrigger\nEnd of conversion on ADC3\n...\n...\n6 ADCCLK\ncycles\nEnd of conversion on ADC1\n...\nADC3\nEnd of conversion on ADC2\nDMA request every 2 conversions\nCH0\nConversion\nSampling\nai16058\nCH0\nCH0\nCH0\nCH0\nCH0\nCH0\nCH0\nCH0\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n412/1757\nRM0090 Rev 21\nADC has to perform an injected conversion. It is resumed when the injected conversion is \nfinished.\nIf the conversion sequence is interrupted (for instance when DMA end of transfer occurs), \nthe multi-ADC sequencer must be reset by configuring it in independent mode first (bits \nDUAL[4:0] = 00000) before reprogramming the interleaved mode.\nThe time interval between 2 trigger events must be greater than or equal to 1 ADC clock \nperiod. The minimum time interval between 2 trigger events that start conversions on the \nsame ADC is the same as in the single ADC mode.\nDual ADC mode\n•\nWhen the 1st trigger occurs, all injected ADC1 channels in the group are converted\n•\nWhen the 2nd trigger occurs, all injected ADC2 channels in the group are converted\n•\nand so on\nA JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group \nhave been converted.\nA JEOC interrupt, if enabled, is generated after all injected ADC2 channels in the group \nhave been converted.\nIf another external trigger occurs after all injected channels in the group have been \nconverted then the alternate trigger process restarts by converting the injected ADC1 \nchannels in the group.\nFigure 58. Alternate trigger: injected group of each ADC\nIf the injected discontinuous mode is enabled for both ADC1 and ADC2:\n•\nWhen the 1st trigger occurs, the first injected ADC1 channel is converted.\n•\nWhen the 2nd trigger occurs, the first injected ADC2 channel are converted \n•\nand so on\nA JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group \nhave been converted.\nA JEOC interrupt, if enabled, is generated after all injected ADC2 channels in the group \nhave been converted.\nIf another external trigger occurs after all injected channels in the group have been \nconverted then the alternate trigger process restarts.\nADC1\nADC2\n1st trigger\n2nd trigger\n3rd trigger\n4th trigger\n(n)th trigger\n(n+1)th trigger\nEOC, JEOC\non ADC1\nEOC, JEOC\non ADC1\n. . .\nEOC, JEOC\non ADC2\nEOC, JEOC\non ADC2\nConversion\nSampling\nai16059\n\n\n<>\n\nRM0090 Rev 21\n413/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\nFigure 59. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode\nTriple ADC mode\n•\nWhen the 1st trigger occurs, all injected ADC1 channels in the group are converted.\n•\nWhen the 2nd trigger occurs, all injected ADC2 channels in the group are converted.\n•\nWhen the 3rd trigger occurs, all injected ADC3 channels in the group are converted.\n•\nand so on\nA JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group \nhave been converted.\nA JEOC interrupt, if enabled, is generated after all injected ADC2 channels in the group \nhave been converted.\nA JEOC interrupt, if enabled, is generated after all injected ADC3 channels in the group \nhave been converted.\nIf another external trigger occurs after all injected channels in the group have been \nconverted then the alternate trigger process restarts by converting the injected ADC1 \nchannels in the group.\nFigure 60. Alternate trigger: injected group of each ADC\n13.9.5 \nCombined regular/injected simultaneous mode\nIt is possible to interrupt the simultaneous conversion of a regular group to start the \nsimultaneous conversion of an injected group.\nNote:\nIn combined regular/injected simultaneous mode, one must convert sequences with the \nsame length or ensure that the interval between triggers is longer than the long conversion \ntime of the 2 sequences (Dual ADC mode) /3 sequences (Triple ADC mode). Otherwise, the \nADC1\nADC2\n1st trigger\nConversion\nSampling\n2nd trigger\n3rd trigger\n4th trigger\n5th trigger\n6th trigger\n7th trigger\n8th trigger\nJEOC on ADC2\nJEOC on ADC1\nai16060\nADC1\nADC2\n1st trigger\nConversion\nSampling\n2nd trigger\n4th trigger\n3rd trigger\n(n)th trigger\n(n+1)th trigger\nEOC, JEOC\non ADC1\nEOC, JEOC\non ADC1\n. . .\nEOC, JEOC\non ADC2\nEOC, JEOC\non ADC3\n5th trigger\n(n+2)th trigger\nai16061\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n414/1757\nRM0090 Rev 21\nADC with the shortest sequence may restart while the ADC with the longest sequence is \ncompleting the previous conversions.\n13.9.6 \nCombined regular simultaneous + alternate trigger mode\nIt is possible to interrupt the simultaneous conversion of a regular group to start the alternate \ntrigger conversion of an injected group. Figure 61 shows the behavior of an alternate trigger \ninterrupting a simultaneous regular conversion.\nThe injected alternate conversion is immediately started after the injected event. If regular \nconversion is already running, in order to ensure synchronization after the injected \nconversion, the regular conversion of all (master/slave) ADCs is stopped and resumed \nsynchronously at the end of the injected conversion.\nNote:\nIn combined regular simultaneous + alternate trigger mode, one must convert sequences \nwith the same length or ensure that the interval between triggers is longer than the long \nconversion time of the 2 sequences (Dual ADC mode) /3 sequences (Triple ADC mode). \nOtherwise, the ADC with the shortest sequence may restart while the ADC with the longest \nsequence is completing the previous conversions.\nIf the conversion sequence is interrupted (for instance when DMA end of transfer occurs), \nthe multi-ADC sequencer must be reset by configuring it in independent mode first (bits \nDUAL[4:0] = 00000) before reprogramming the interleaved mode.\nFigure 61. Alternate + regular simultaneous\nIf a trigger occurs during an injected conversion that has interrupted a regular conversion, it \nis ignored. Figure 62 shows the behavior in this case (2nd trigger is ignored).\nADC1 reg\nCH0\nCH1\nCH2\nCH0\nCH2\nCH3\nCH0\nADC1 inj\nADC2 reg\nADC2 inj\n1st trigger\n2nd trigger\nsynchro not lost\nCH3\nCH5\nCH6\nCH6\nCH7\nCH3\nCH4\nCH7\nCH8\nai16062\n\n\n<>\n\nRM0090 Rev 21\n415/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\nFigure 62. Case of trigger occurring during injected conversion\n13.10 \nTemperature sensor\nThe temperature sensor can be used to measure the junction temperature (TJ) of the \ndevice.\n•\nOn STM32F40x and STM32F41x devices, the temperature sensor is internally \nconnected to ADC1_IN16 channel which is used to convert the sensor output voltage \nto a digital value.\n•\nOn STM32F42x and STM32F43x devices, the temperature sensor is internally \nconnected to the same input channel, ADC1_IN18, as VBAT: ADC1_IN18 is used to \nconvert the sensor output voltage or VBAT into a digital value. Only one conversion, \ntemperature sensor or VBAT, must be selected at a time. When the temperature sensor \nand the VBAT conversion are set simultaneously, only the VBAT conversion is \nperformed.\nFigure 63 shows the block diagram of the temperature sensor.\nWhen not in use, the sensor can be put in power down mode.\nNote:\nThe TSVREFE bit must be set to enable the conversion of both internal channels: the \nADC1_IN16 or ADC1_IN18 (temperature sensor) and the ADC1_IN17 (VREFINT). \nMain features\n•\nSupported temperature range: –40 to 125 °C\n•\nPrecision: ±1.5 °C \nADC1 reg\nCH0\nCH1\nCH2\nCH0\nCH2\nCH3\nCH0\nADC1 inj\nADC2 reg\nADC2 inj\n1st trigger\n2nd trigger\nCH3\nCH5\nCH6\nCH6\nCH7\nCH3\nCH4\nCH7\nCH8\nai16063\nCH0\n2nd trigger\n3rd trigger\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n416/1757\nRM0090 Rev 21\nFigure 63. Temperature sensor and VREFINT channel block diagram \n1.\nVSENSE is input to ADC1_IN16 for the STM23F40x and STM32F41x devices and to ADC1_IN18 for the \nSTM32F42x and STM32F43x devices.\nReading the temperature\nTo use the sensor:\n3. \nSelect ADC1_IN16 or ADC1_IN18 input channel. \n4. \nSelect a sampling time greater than the minimum sampling time specified in the \ndatasheet.\n5. \nSet the TSVREFE bit in the ADC_CCR register to wake up the temperature sensor \nfrom power down mode\n6. \nStart the ADC conversion by setting the SWSTART bit (or by external trigger)\n7. \nRead the resulting VSENSE data in the ADC data register\n8. \nCalculate the temperature using the following formula:\nTemperature (in °C) = {(VSENSE – V25) / Avg_Slope} + 25\nWhere:\n–\nV25 = VSENSE value for 25° C\n–\nAvg_Slope = average slope of the temperature vs. VSENSE curve (given in mV/°C \nor µV/°C)\nRefer to the datasheet’s electrical characteristics section for the actual values of V25 \nand Avg_Slope.\nNote:\nThe sensor has a startup time after waking from power down mode before it can output \nVSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize \nthe delay, the ADON and TSVREFE bits should be set at the same time.\nThe temperature sensor output voltage changes linearly with temperature. The offset of this \nlinear function depends on each chip due to process variation (up to 45 °C from one chip to \nanother).\nMS31830V1\nTemperature \nsensor\nVSENSE\nTSVREFE control bit\nADC1 \nAddress/data bus\n \nVREFINT\nADC1_IN16/\nADC1_IN18(1)\nInternal\npower block\nADC1_IN17\nconverted data\n\n\n<>\n\nRM0090 Rev 21\n417/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\nThe internal temperature sensor is more suited for applications that detect temperature \nvariations instead of absolute temperatures. If accurate temperature reading is required, an \nexternal temperature sensor should be used.\n13.11 \nBattery charge monitoring\nThe VBATE bit in the ADC_CCR register is used to switch to the battery voltage. As the \nVBAT voltage could be higher than VDDA, to ensure the correct operation of the ADC, the \nVBAT pin is internally connected to a bridge divider.\nWhen the VBATE is set, the bridge is automatically enabled to connect:\n•\nVBAT/2 to the ADC1_IN18 input channel, on STM32F40xx and STM32F41xx devices\n•\nVBAT/4 to the ADC1_IN18 input channel, on STM32F42xx and STM32F43xx devices\nNote:\nOn STM32F42xx and STM32F43xx devices, VBAT and temperature sensor are connected \nto the same ADC internal channel (ADC1_IN18). Only one conversion, either temperature \nsensor or VBAT, must be selected at a time. When both conversion are enabled \nsimultaneously, only the VBAT conversion is performed.\n13.12 \nADC interrupts\nAn interrupt can be produced on the end of conversion for regular and injected groups, \nwhen the analog watchdog status bit is set and when the overrun status bit is set. Separate \ninterrupt enable bits are available for flexibility.\nTwo other flags are present in the ADC_SR register, but there is no interrupt associated with \nthem:\n•\nJSTRT (Start of conversion for channels of an injected group)\n•\nSTRT (Start of conversion for channels of a regular group)\n \nTable 71. ADC interrupts\nInterrupt event\nEvent flag\nEnable control bit\nEnd of conversion of a regular group\nEOC\nEOCIE\nEnd of conversion of an injected group\nJEOC\nJEOCIE\nAnalog watchdog status bit is set\nAWD\nAWDIE\nOverrun\nOVR\nOVRIE\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n418/1757\nRM0090 Rev 21\n13.13 \nADC registers\nRefer to Section 1.1: List of abbreviations for registers for registers for a list of abbreviations \nused in register descriptions.\nThe peripheral registers must be written at word level (32 bits). Read accesses can be done \nby bytes (8 bits), half-words (16 bits) or words (32 bits). \n13.13.1 \nADC status register (ADC_SR)\nAddress offset: 0x00\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOVR\nSTRT\nJSTRT\nJEOC \nEOC\nAWD\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nBits 31:6 Reserved, must be kept at reset value.\nBit 5 OVR: Overrun\nThis bit is set by hardware when data are lost (either in single mode or in dual/triple mode). It \nis cleared by software. Overrun detection is enabled only when DMA = 1 or EOCS = 1.\n0: No overrun occurred\n1: Overrun has occurred\nBit 4 STRT: Regular channel start flag\nThis bit is set by hardware when regular channel conversion starts. It is cleared by software.\n0: No regular channel conversion started\n1: Regular channel conversion has started\nBit 3 JSTRT: Injected channel start flag\nThis bit is set by hardware when injected group conversion starts. It is cleared by software.\n0: No injected group conversion started\n1: Injected group conversion has started\nBit 2 JEOC: Injected channel end of conversion\nThis bit is set by hardware at the end of the conversion of all injected channels in the group. \nIt is cleared by software.\n0: Conversion is not complete\n1: Conversion complete\nBit 1 EOC: Regular channel end of conversion\nThis bit is set by hardware at the end of the conversion of a regular group of channels. It is \ncleared by software or by reading the ADC_DR register.\n0: Conversion not complete (EOCS=0), or sequence of conversions not complete (EOCS=1)\n1: Conversion complete (EOCS=0), or sequence of conversions complete (EOCS=1)\nBit 0 AWD: Analog watchdog flag\nThis bit is set by hardware when the converted voltage crosses the values programmed in \nthe ADC_LTR and ADC_HTR registers. It is cleared by software.\n0: No analog watchdog event occurred\n1: Analog watchdog event occurred\n\n\n<>\n\nRM0090 Rev 21\n419/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.13.2 \nADC control register 1 (ADC_CR1)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nOVRIE\nRES\nAWDEN\nJAWDEN\nReserved\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDISCNUM[2:0]\nJDISCE\nN\nDISC \nEN\nJAUTO AWDSG\nL\nSCAN\nJEOCIE\nAWDIE\nEOCIE\nAWDCH[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:27 Reserved, must be kept at reset value.\nBit 26 OVRIE: Overrun interrupt enable\nThis bit is set and cleared by software to enable/disable the Overrun interrupt. \n0: Overrun interrupt disabled\n1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.\nBits 25:24 RES[1:0]: Resolution\nThese bits are written by software to select the resolution of the conversion.\n00: 12-bit (15 ADCCLK cycles)\n01: 10-bit (13 ADCCLK cycles)\n10: 8-bit (11 ADCCLK cycles)\n11: 6-bit (9 ADCCLK cycles)\nBit 23 AWDEN: Analog watchdog enable on regular channels\nThis bit is set and cleared by software.\n0: Analog watchdog disabled on regular channels\n1: Analog watchdog enabled on regular channels\nBit 22 JAWDEN: Analog watchdog enable on injected channels\nThis bit is set and cleared by software.\n0: Analog watchdog disabled on injected channels\n1: Analog watchdog enabled on injected channels\nBits 21:16 Reserved, must be kept at reset value.\nBits 15:13 DISCNUM[2:0]: Discontinuous mode channel count\nThese bits are written by software to define the number of regular channels to be converted \nin discontinuous mode, after receiving an external trigger.\n000: 1 channel\n001: 2 channels\n...\n111: 8 channels\nBit 12 JDISCEN: Discontinuous mode on injected channels\nThis bit is set and cleared by software to enable/disable discontinuous mode on the injected \nchannels of a group.\n0: Discontinuous mode on injected channels disabled\n1: Discontinuous mode on injected channels enabled\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n420/1757\nRM0090 Rev 21\nBit 11 DISCEN: Discontinuous mode on regular channels\nThis bit is set and cleared by software to enable/disable Discontinuous mode on regular \nchannels.\n0: Discontinuous mode on regular channels disabled\n1: Discontinuous mode on regular channels enabled\nBit 10 JAUTO: Automatic injected group conversion\nThis bit is set and cleared by software to enable/disable automatic injected group conversion \nafter regular group conversion.\n0: Automatic injected group conversion disabled\n1: Automatic injected group conversion enabled\nBit 9 AWDSGL: Enable the watchdog on a single channel in scan mode\nThis bit is set and cleared by software to enable/disable the analog watchdog on the channel \nidentified by the AWDCH[4:0] bits.\n0: Analog watchdog enabled on all channels\n1: Analog watchdog enabled on a single channel\nBit 8 SCAN: Scan mode\nThis bit is set and cleared by software to enable/disable the Scan mode. In Scan mode, the \ninputs selected through the ADC_SQRx or ADC_JSQRx registers are converted.\n0: Scan mode disabled\n1: Scan mode enabled\nNote: An EOC interrupt is generated if the EOCIE bit is set:\n–\nAt the end of each regular group sequence if the EOCS bit is cleared to 0\n–\nAt the end of each regular channel conversion if the EOCS bit is set to 1\nNote: A JEOC interrupt is generated only on the end of conversion of the last channel if the \nJEOCIE bit is set.\nBit 7 JEOCIE: Interrupt enable for injected channels\nThis bit is set and cleared by software to enable/disable the end of conversion interrupt for \ninjected channels.\n0: JEOC interrupt disabled\n1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.\nBit 6 AWDIE: Analog watchdog interrupt enable\nThis bit is set and cleared by software to enable/disable the analog watchdog interrupt.\n0: Analog watchdog interrupt disabled\n1: Analog watchdog interrupt enabled\nBit 5 EOCIE: Interrupt enable for EOC\nThis bit is set and cleared by software to enable/disable the end of conversion interrupt.\n0: EOC interrupt disabled\n1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.\nBits 4:0 AWDCH[4:0]: Analog watchdog channel select bits\nThese bits are set and cleared by software. They select the input channel to be guarded by \nthe analog watchdog.\nNote: 00000: ADC analog input Channel0\n00001: ADC analog input Channel1\n...\n01111: ADC analog input Channel15\n10000: ADC analog input Channel16\n10001: ADC analog input Channel17\n10010: ADC analog input Channel18\nOther values reserved\n\n\n<>\n\nRM0090 Rev 21\n421/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.13.3 \nADC control register 2 (ADC_CR2)\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nreserved\nSWST\nART\nEXTEN\nEXTSEL[3:0]\nreserved\nJSWST\nART\nJEXTEN\nJEXTSEL[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nreserved\nALIGN\nEOCS\nDDS\nDMA\nReserved\nCONT\nADON\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBit 30 SWSTART: Start conversion of regular channels\nThis bit is set by software to start conversion and cleared by hardware as soon as the \nconversion starts.\n0: Reset state\n1: Starts conversion of regular channels\nNote: This bit can be set only when ADON = 1 otherwise no conversion is launched.\nBits 29:28 EXTEN: External trigger enable for regular channels\nThese bits are set and cleared by software to select the external trigger polarity and enable \nthe trigger of a regular group.\n00: Trigger detection disabled\n01: Trigger detection on the rising edge\n10: Trigger detection on the falling edge\n11: Trigger detection on both the rising and falling edges\nBits 27:24 EXTSEL[3:0]: External event select for regular group\nThese bits select the external event used to trigger the start of conversion of a regular group:\n0000: Timer 1 CC1 event\n0001: Timer 1 CC2 event\n0010: Timer 1 CC3 event\n0011: Timer 2 CC2 event\n0100: Timer 2 CC3 event\n0101: Timer 2 CC4 event\n0110: Timer 2 TRGO event\n0111: Timer 3 CC1 event\n1000: Timer 3 TRGO event\n1001: Timer 4 CC4 event\n1010: Timer 5 CC1 event\n1011: Timer 5 CC2 event\n1100: Timer 5 CC3 event\n1101: Timer 8 CC1 event\n1110: Timer 8 TRGO event\n1111: EXTI line11\nBit 23 Reserved, must be kept at reset value.\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n422/1757\nRM0090 Rev 21\nBit 22 JSWSTART: Start conversion of injected channels\nThis bit is set by software and cleared by hardware as soon as the conversion starts.\n0: Reset state\n1: Starts conversion of injected channels\nNote: This bit can be set only when ADON = 1 otherwise no conversion is launched.\nBits 21:20 JEXTEN: External trigger enable for injected channels\nThese bits are set and cleared by software to select the external trigger polarity and enable \nthe trigger of an injected group.\n00: Trigger detection disabled\n01: Trigger detection on the rising edge\n10: Trigger detection on the falling edge\n11: Trigger detection on both the rising and falling edges\nBits 19:16 JEXTSEL[3:0]: External event select for injected group\nThese bits select the external event used to trigger the start of conversion of an injected \ngroup.\n0000: Timer 1 CC4 event\n0001: Timer 1 TRGO event\n0010: Timer 2 CC1 event\n0011: Timer 2 TRGO event\n0100: Timer 3 CC2 event\n0101: Timer 3 CC4 event\n0110: Timer 4 CC1 event\n0111: Timer 4 CC2 event\n1000: Timer 4 CC3 event\n1001: Timer 4 TRGO event\n1010: Timer 5 CC4 event\n1011: Timer 5 TRGO event\n1100: Timer 8 CC2 event\n1101: Timer 8 CC3 event\n1110: Timer 8 CC4 event\n1111: EXTI line15\nBits 15:12 Reserved, must be kept at reset value.\nBit 11 ALIGN: Data alignment\nThis bit is set and cleared by software. Refer to Figure 48 and Figure 49.\n0: Right alignment\n1: Left alignment\nBit 10 EOCS: End of conversion selection\nThis bit is set and cleared by software.\n0: The EOC bit is set at the end of each sequence of regular conversions. Overrun detection \nis enabled only if DMA=1.\n1: The EOC bit is set at the end of each regular conversion. Overrun detection is enabled.\nBit 9 DDS: DMA disable selection (for single ADC mode)\nThis bit is set and cleared by software.\n0: No new DMA request is issued after the last transfer (as configured in the DMA controller)\n1: DMA requests are issued as long as data are converted and DMA=1\nBit 8 DMA: Direct memory access mode (for single ADC mode)\nThis bit is set and cleared by software. Refer to the DMA controller chapter for more details.\n0: DMA mode disabled\n1: DMA mode enabled\n\n\n<>\n\nRM0090 Rev 21\n423/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.13.4 \nADC sample time register 1 (ADC_SMPR1)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n \n \n13.13.5 \nADC sample time register 2 (ADC_SMPR2)\nAddress offset: 0x10\nReset value: 0x0000 0000\n \nBits 7:2 Reserved, must be kept at reset value.\nBit 1 CONT: Continuous conversion\nThis bit is set and cleared by software. If it is set, conversion takes place continuously until it \nis cleared.\n0: Single conversion mode\n1: Continuous conversion mode \nBit 0 ADON: A/D Converter ON / OFF\nThis bit is set and cleared by software.\nNote: 0: Disable ADC conversion and go to power down mode\n1: Enable ADC\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nSMP18[2:0]\nSMP17[2:0]\nSMP16[2:0]\nSMP15[2:1]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSMP15_0\nSMP14[2:0]\nSMP13[2:0]\nSMP12[2:0]\nSMP11[2:0]\nSMP10[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31: 27 Reserved, must be kept at reset value.\nBits 26:0 SMPx[2:0]: Channel x sampling time selection\nThese bits are written by software to select the sampling time individually for each channel. \nDuring sampling cycles, the channel selection bits must remain unchanged.\nNote: 000: 3 cycles\n001: 15 cycles\n010: 28 cycles\n011: 56 cycles\n100: 84 cycles\n101: 112 cycles\n110: 144 cycles\n111: 480 cycles\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nSMP9[2:0]\nSMP8[2:0]\nSMP7[2:0]\nSMP6[2:0]\nSMP5[2:1]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSMP\n5_0\nSMP4[2:0]\nSMP3[2:0]\nSMP2[2:0]\nSMP1[2:0]\nSMP0[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n424/1757\nRM0090 Rev 21\n \n13.13.6 \nADC injected channel data offset register x (ADC_JOFRx) (x=1..4)\nAddress offset: 0x14-0x20\nReset value: 0x0000 0000\n \n \n13.13.7 \nADC watchdog higher threshold register (ADC_HTR)\nAddress offset: 0x24\nReset value: 0x0000 0FFF\n \n \nBits 31:30 Reserved, must be kept at reset value.\nBits 29:0 SMPx[2:0]: Channel x sampling time selection\nThese bits are written by software to select the sampling time individually for each channel. \nDuring sample cycles, the channel selection bits must remain unchanged.\nNote: 000: 3 cycles\n001: 15 cycles\n010: 28 cycles\n011: 56 cycles\n100: 84 cycles\n101: 112 cycles\n110: 144 cycles\n111: 480 cycles\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nJOFFSETx[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 JOFFSETx[11:0]: Data offset for injected channel x\nThese bits are written by software to define the offset to be subtracted from the raw \nconverted data when converting injected channels. The conversion result can be read from \nin the ADC_JDRx registers.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nHT[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 HT[11:0]: Analog watchdog higher threshold\nThese bits are written by software to define the higher threshold for the analog watchdog.\n\n\n<>\n\nRM0090 Rev 21\n425/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\nNote:\nThe software can write to these registers when an ADC conversion is ongoing. The \nprogrammed value is effective when the next conversion is complete. Writing to this register \nis performed with a write delay that can create uncertainty on the effective time at which the \nnew value is programmed.\n13.13.8 \nADC watchdog lower threshold register (ADC_LTR)\nAddress offset: 0x28\nReset value: 0x0000 0000\n \n \nNote:\nThe software can write to these registers when an ADC conversion is ongoing. The \nprogrammed value is effective when the next conversion is complete. Writing to this register \nis performed with a write delay that can create uncertainty on the effective time at which the \nnew value is programmed.\n13.13.9 \nADC regular sequence register 1 (ADC_SQR1)\nAddress offset: 0x2C\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLT[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 LT[11:0]: Analog watchdog lower threshold\nThese bits are written by software to define the lower threshold for the analog watchdog.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nL[3:0]\nSQ16[4:1]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSQ16_0\nSQ15[4:0]\nSQ14[4:0]\nSQ13[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value.\nBits 23:20 L[3:0]: Regular channel sequence length\nThese bits are written by software to define the total number of conversions in the regular \nchannel conversion sequence.\n0000: 1 conversion\n0001: 2 conversions\n...\n1111: 16 conversions\nBits 19:15 SQ16[4:0]: 16th conversion in regular sequence\nThese bits are written by software with the channel number (0..18) assigned as the 16th in \nthe conversion sequence.\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n426/1757\nRM0090 Rev 21\n13.13.10 ADC regular sequence register 2 (ADC_SQR2)\nAddress offset: 0x30\nReset value: 0x0000 0000\n \n \n13.13.11 ADC regular sequence register 3 (ADC_SQR3)\nAddress offset: 0x34\nReset value: 0x0000 0000\n \n \nBits 14:10 SQ15[4:0]: 15th conversion in regular sequence\nBits 9:5 SQ14[4:0]: 14th conversion in regular sequence\nBits 4:0 SQ13[4:0]: 13th conversion in regular sequence\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nSQ12[4:0]\nSQ11[4:0]\nSQ10[4:1]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSQ10_0\nSQ9[4:0]\nSQ8[4:0]\nSQ7[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBits 29:26 SQ12[4:0]: 12th conversion in regular sequence\nThese bits are written by software with the channel number (0..18) assigned as the 12th in \nthe sequence to be converted. \nBits 24:20 SQ11[4:0]: 11th conversion in regular sequence\nBits 19:15 SQ10[4:0]: 10th conversion in regular sequence\nBits 14:10 SQ9[4:0]: 9th conversion in regular sequence\nBits 9:5 SQ8[4:0]: 8th conversion in regular sequence\nBits 4:0 SQ7[4:0]: 7th conversion in regular sequence\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nSQ6[4:0]\nSQ5[4:0]\nSQ4[4:1]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSQ4_0\nSQ3[4:0]\nSQ2[4:0]\nSQ1[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBits 29:25 SQ6[4:0]: 6th conversion in regular sequence\nThese bits are written by software with the channel number (0..18) assigned as the 6th in the \nsequence to be converted.\nBits 24:20 SQ5[4:0]: 5th conversion in regular sequence\n\n\n<>\n\nRM0090 Rev 21\n427/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.13.12 ADC injected sequence register (ADC_JSQR)\nAddress offset: 0x38\nReset value: 0x0000 0000\n \n \nNote:\nWhen JL[1:0]=3 (4 injected conversions in the sequencer), the ADC converts the channels \nin the following order: JSQ1[4:0], JSQ2[4:0], JSQ3[4:0], and JSQ4[4:0].\nWhen JL=2 (3 injected conversions in the sequencer), the ADC converts the channels in the \nfollowing order: JSQ2[4:0], JSQ3[4:0], and JSQ4[4:0].\nWhen JL=1 (2 injected conversions in the sequencer), the ADC converts the channels in \nstarting from JSQ3[4:0], and then JSQ4[4:0].\nWhen JL=0 (1 injected conversion in the sequencer), the ADC converts only JSQ4[4:0] \nchannel.\nBits 19:15 SQ4[4:0]: 4th conversion in regular sequence\nBits 14:10 SQ3[4:0]: 3rd conversion in regular sequence\nBits 9:5 SQ2[4:0]: 2nd conversion in regular sequence\nBits 4:0 SQ1[4:0]: 1st conversion in regular sequence\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nJL[1:0]\nJSQ4[4:1]\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nJSQ4[0]\nJSQ3[4:0]\nJSQ2[4:0]\nJSQ1[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:22 Reserved, must be kept at reset value.\nBits 21:20 JL[1:0]: Injected sequence length\nThese bits are written by software to define the total number of conversions in the injected \nchannel conversion sequence.\n00: 1 conversion\n01: 2 conversions\n10: 3 conversions\n11: 4 conversions\nBits 19:15 JSQ4[4:0]: 4th conversion in injected sequence (when JL[1:0]=3, see note below)\nThese bits are written by software with the channel number (0..18) assigned as the 4th in the \nsequence to be converted.\nBits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence (when JL[1:0]=3, see note below)\nBits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence (when JL[1:0]=3, see note below)\nBits 4:0 JSQ1[4:0]: 1st conversion in injected sequence (when JL[1:0]=3, see note below)\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n428/1757\nRM0090 Rev 21\n13.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4)\nAddress offset: 0x3C - 0x48\nReset value: 0x0000 0000\n \n \n13.13.14 ADC regular data register (ADC_DR)\nAddress offset: 0x4C\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nJDATA[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 JDATA[15:0]: Injected data\nThese bits are read-only. They contain the conversion result from injected channel x. The \ndata are left -or right-aligned as shown in Figure 48 and Figure 49.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATA[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 DATA[15:0]: Regular data\nThese bits are read-only. They contain the conversion result from the regular \nchannels. The data are left- or right-aligned as shown in Figure 48 and \nFigure 49.\n\n\n<>\n\nRM0090 Rev 21\n429/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.13.15 ADC Common status register (ADC_CSR)\nAddress offset: 0x00 (this offset address is relative to ADC1 base address + 0x300)\nReset value: 0x0000 0000\nThis register provides an image of the status bits of the different ADCs. Nevertheless it is \nread-only and does not allow to clear the different status bits. Instead each status bit must \nbe cleared by writing it to 0 in the corresponding ADC_SR register.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nOVR3\nSTRT3\nJSTRT3 JEOC 3\nEOC3\nAWD3\nADC3\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOVR2\nSTRT2\nJSTRT\n2\nJEOC2 EOC2\nAWD2\nReserved\nOVR1\nSTRT1\nJSTRT1 JEOC 1\nEOC1\nAWD1\nADC2\nADC1\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:22 Reserved, must be kept at reset value.\nBit 21 OVR3: Overrun flag of ADC3\nThis bit is a copy of the OVR bit in the ADC3_SR register.\nBit 20 STRT3: Regular channel Start flag of ADC3\nThis bit is a copy of the STRT bit in the ADC3_SR register.\nBit 19 JSTRT3: Injected channel Start flag of ADC3\nThis bit is a copy of the JSTRT bit in the ADC3_SR register.\nBit 18 JEOC3: Injected channel end of conversion of ADC3\nThis bit is a copy of the JEOC bit in the ADC3_SR register.\nBit 17 EOC3: End of conversion of ADC3\nThis bit is a copy of the EOC bit in the ADC3_SR register.\nBit 16 AWD3: Analog watchdog flag of ADC3\nThis bit is a copy of the AWD bit in the ADC3_SR register.\nBits 15:14 Reserved, must be kept at reset value.\nBit 13 OVR2: Overrun flag of ADC2\nThis bit is a copy of the OVR bit in the ADC2_SR register.\nBit 12 STRT2: Regular channel Start flag of ADC2\nThis bit is a copy of the STRT bit in the ADC2_SR register.\nBit 11 JSTRT2: Injected channel Start flag of ADC2\nThis bit is a copy of the JSTRT bit in the ADC2_SR register.\nBit 10 JEOC2: Injected channel end of conversion of ADC2\nThis bit is a copy of the JEOC bit in the ADC2_SR register.\nBit 9 EOC2: End of conversion of ADC2\nThis bit is a copy of the EOC bit in the ADC2_SR register.\nBit 8 AWD2: Analog watchdog flag of ADC2\nThis bit is a copy of the AWD bit in the ADC2_SR register.\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n430/1757\nRM0090 Rev 21\n13.13.16 ADC common control register (ADC_CCR)\nAddress offset: 0x04 (this offset address is relative to ADC1 base address + 0x300)\nReset value: 0x0000 0000\n \n \nBits 7:6 Reserved, must be kept at reset value.\nBit 5 OVR1: Overrun flag of ADC1\nThis bit is a copy of the OVR bit in the ADC1_SR register.\nBit 4 STRT1: Regular channel Start flag of ADC1\nThis bit is a copy of the STRT bit in the ADC1_SR register.\nBit 3 JSTRT1: Injected channel Start flag of ADC1\nThis bit is a copy of the JSTRT bit in the ADC1_SR register.\nBit 2 JEOC1: Injected channel end of conversion of ADC1\nThis bit is a copy of the JEOC bit in the ADC1_SR register.\nBit 1 EOC1: End of conversion of ADC1\nThis bit is a copy of the EOC bit in the ADC1_SR register.\nBit 0 AWD1: Analog watchdog flag of ADC1\nThis bit is a copy of the AWD bit in the ADC1_SR register.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTSVREFE VBATE\nReserved\nADCPRE\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDMA[1:0]\nDDS\nRes.\nDELAY[3:0]\nReserved\nMULTI[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value.\nBit 23 TSVREFE: Temperature sensor and VREFINT enable\nThis bit is set and cleared by software to enable/disable the temperature sensor and the \nVREFINT channel.\n0: Temperature sensor and VREFINT channel disabled\n1: Temperature sensor and VREFINT channel enabled\nNote: On STM32F42x and STM32F43x devices, VBATE must be disabled when TSVREFE is \nset. If both bits are set, only the VBAT conversion is performed.\nBit 22 VBATE: VBAT enable\nThis bit is set and cleared by software to enable/disable the VBAT channel.\n0: VBAT channel disabled\n1: VBAT channel enabled\nBits 21:18 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n431/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\nBits 17:16 ADCPRE: ADC prescaler\nSet and cleared by software to select the frequency of the clock to the ADC. The clock is \ncommon for all the ADCs.\nNote: 00: PCLK2 divided by 2\n01: PCLK2 divided by 4\n10: PCLK2 divided by 6\n11: PCLK2 divided by 8\nBits 15:14 DMA: Direct memory access mode for multi ADC mode\nThis bit-field is set and cleared by software. Refer to the DMA controller section for more \ndetails.\n00: DMA mode disabled\n01: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)\n10: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)\n11: DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2)\nBit 13 DDS: DMA disable selection (for multi-ADC mode)\nThis bit is set and cleared by software.\n0: No new DMA request is issued after the last transfer (as configured in the DMA \ncontroller). DMA bits are not cleared by hardware, however they must have been cleared \nand set to the wanted mode by software before new DMA requests can be generated.\n1: DMA requests are issued as long as data are converted and DMA = 01, 10 or 11.\nBit 12 Reserved, must be kept at reset value.\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n432/1757\nRM0090 Rev 21\nBit 11:8 DELAY: Delay between 2 sampling phases\nSet and cleared by software. These bits are used in dual or triple interleaved modes.\n0000: 5 * TADCCLK\n0001: 6 * TADCCLK\n0010: 7 * TADCCLK\n...\n1111: 20 * TADCCLK\nBits 7:5 Reserved, must be kept at reset value.\nBits 4:0 MULTI[4:0]: Multi ADC mode selection\nThese bits are written by software to select the operating mode.\n– All the ADCs independent:\n00000: Independent mode\n– 00001 to 01001: Dual mode, ADC1 and ADC2 working together, ADC3 is independent\n00001: Combined regular simultaneous + injected simultaneous mode\n00010: Combined regular simultaneous + alternate trigger mode\n00011: Reserved\n00101: Injected simultaneous mode only\n00110: Regular simultaneous mode only\n00111: interleaved mode only\n01001: Alternate trigger mode only\n– 10001 to 11001: Triple mode: ADC1, 2 and 3 working together\n10001: Combined regular simultaneous + injected simultaneous mode\n10010: Combined regular simultaneous + alternate trigger mode\n10011: Reserved\n10101: Injected simultaneous mode only\n10110: Regular simultaneous mode only\n10111: interleaved mode only\n11001: Alternate trigger mode only\nAll other combinations are reserved and must not be programmed\nNote: In multi mode, a change of channel configuration generates an abort that can cause a \nloss of synchronization. It is recommended to disable the multi ADC mode before any \nconfiguration change.\n\n\n<>\n\nRM0090 Rev 21\n433/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.13.17 ADC common regular data register for dual and triple modes\n(ADC_CDR)\nAddress offset: 0x08 (this offset address is relative to ADC1 base address + 0x300)\nReset value: 0x0000 0000\n \n \n13.13.18 ADC register map\nThe following table summarizes the ADC registers.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATA2[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATA1[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 DATA2[15:0]: 2nd data item of a pair of regular conversions\n– In dual mode, these bits contain the regular data of ADC2. Refer to Dual ADC mode.\n– In triple mode, these bits contain alternatively the regular data of ADC2, ADC1 and ADC3. \nRefer to Triple ADC mode.\nBits 15:0 DATA1[15:0]: 1st data item of a pair of regular conversions\n– In dual mode, these bits contain the regular data of ADC1. Refer to Dual ADC mode\n– In triple mode, these bits contain alternatively the regular data of ADC1, ADC3 and ADC2. \nRefer to Triple ADC mode.\nTable 72. ADC global register map\nOffset\nRegister\n0x000 - 0x04C\nADC1\n0x050 - 0x0FC\nReserved\n0x100 - 0x14C\nADC2\n0x118 - 0x1FC\nReserved\n0x200 - 0x24C\nADC3\n0x250 - 0x2FC\nReserved\n0x300 - 0x308\nCommon registers\n\n\n<>\n\nAnalog-to-digital converter (ADC)\nRM0090\n434/1757\nRM0090 Rev 21\n \nTable 73. ADC register map and reset values for each ADC\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nADC_SR\nReserved\nOVR\nSTRT\nJSTRT\nJEOC\nEOC\nAWD\nReset value\n0\n0\n0\n0\n0\n0\n0x04\nADC_CR1\nReserved\nOVRIE\nRES[1:0]\nAWDEN\nJAWDEN\nReserved\nDISC \nNUM [2:0]\nJDISCEN\nDISCEN\nJAUTO\nAWD SGL\nSCAN\nJEOCIE\nAWDIE\nEOCIE\nAWDCH[4:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nADC_CR2\nRe\nse\nrv\ned\nSWSTART\nEXTEN[1:0]\nEXTSEL [3:0]\nRe\nse\nrv\ned\nJSWSTART\nJEXTEN[1:0]\nJEXTSEL \n[3:0]\nReserved\nALIGN\nEOCS\nDDS\nDMA\nReserved\nCONT\nADON\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nADC_SMPR1\nSample time bits SMPx_x\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nADC_SMPR2\nSample time bits SMPx_x\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nADC_JOFR1\nReserved\nJOFFSET1[11:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x18\nADC_JOFR2\nReserved\nJOFFSET2[11:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nADC_JOFR3\nReserved\nJOFFSET3[11:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nADC_JOFR4\nReserved\nJOFFSET4[11:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x24\nADC_HTR\nReserved\nHT[11:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x28\nADC_LTR\nReserved\nLT[11:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x2C\nADC_SQR1\nReserved\nL[3:0]\nRegular channel sequence SQx_x bits\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x30\nADC_SQR2\nReserved\nRegular channel sequence SQx_x bits\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x34\nADC_SQR3\nReserved\nRegular channel sequence SQx_x bits\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x38\nADC_JSQR\nReserved\nJL[1:0]\nInjected channel sequence JSQx_x bits\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x3C\nADC_JDR1\nReserved\nJDATA[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x40\nADC_JDR2\nReserved\nJDATA[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x44\nADC_JDR3\nReserved\nJDATA[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x48\nADC_JDR4\nReserved\nJDATA[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x4C\nADC_DR\nReserved\nRegular DATA[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n\n\n<>\n\nRM0090 Rev 21\n435/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n \nRefer to Section 2.3: Memory map for the register boundary addresses.\nTable 74. ADC register map and reset values (common ADC registers)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nADC_CSR\nReserved\nOVR\nSTRT\nJSTRT\nJEOC\nEOC\nAWD\nReserved\nOVR\nSTRT\nJSTRT\nJEOC\nEOC\nAWD\nReserved\nOVR\nSTRT\nJSTRT\nJEOC\nEOC\nAWD\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nADC3\nADC2\nADC1\n0x04\nADC_CCR\nReserved\nTSVREFE\nVBATE\nReserved\nADCPRE[1:0]\nDMA[1:0]\nDDS\nReserved\nDELAY [3:0]\nReserved\nMULTI [4:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nADC_CDR\nRegular DATA2[15:0]\nRegular DATA1[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n\n\n<>\n\nDigital-to-analog converter (DAC)\nRM0090\n436/1757\nRM0090 Rev 21\n14 \nDigital-to-analog converter (DAC)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n14.1 \nDAC introduction\nThe DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be \nconfigured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In \n12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each \nwith its own converter. In dual DAC channel mode, conversions could be done \nindependently or simultaneously when both channels are grouped together for synchronous \nupdate operations. An input reference pin, VREF+ (shared with ADC) is available for better \nresolution.\n14.2 \nDAC main features\n•\nTwo DAC converters: one output channel each\n•\nLeft or right data alignment in 12-bit mode\n•\nSynchronized update capability\n•\nNoise-wave generation\n•\nTriangular-wave generation\n•\nDual DAC channel for independent or simultaneous conversions\n•\nDMA capability for each channel\n•\nDMA underrun error detection\n•\nExternal triggers for conversion\n•\nInput voltage reference, VREF+\nFigure 64 shows the block diagram of a DAC channel and Table 75 gives the pin \ndescription.\n\n\n<>\n\nRM0090 Rev 21\n437/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\nFigure 64. DAC channel block diagram \n \nNote:\nOnce the DAC channelx is enabled, the corresponding GPIO pin (PA4 or PA5) is \nautomatically connected to the analog converter output (DAC_OUTx). In order to avoid \nparasitic consumption, the PA4 or PA5 pin should first be configured to analog (AIN).\nTable 75. DAC pins\nName\nSignal type\nRemarks\nVREF+\nInput, analog reference \npositive\nThe higher/positive reference voltage for the DAC,\n1.8 V ≤ VREF+ ≤ VDDA\nVDDA\nInput, analog supply\nAnalog power supply\nVSSA\nInput, analog supply ground\nGround for analog power supply\nDAC_OUTx\nAnalog output signal\nDAC channelx analog output\nVDDA\nVSSA\nVREF+\nDAC_OUTx\nControl logicx\nDHRx\n12-bit\n12-bit\nLFSRx\ntrianglex\nDM A requestx\nTSELx[2:0] bits\nTIM4_TRGO\nTIM5_TRGO\nTIM6_TRGO\nTIM7_TRGO\nTIM2_TRGO\nTIM8_TRGO\nEXTI_9\nDMAENx\nTENx\nMAMPx[3:0] bits\nWAVENx[1:0] bits\nSWTRIGx\nDORx\nDigital-to-analog\nconverterx\n12-bit\nDAC control register\nai14708b\nTrigger selectorx\n\n\n<>\n\nDigital-to-analog converter (DAC)\nRM0090\n438/1757\nRM0090 Rev 21\n14.3 \nDAC functional description\n14.3.1 \nDAC channel enable\nEach DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR \nregister. The DAC channel is then enabled after a startup time tWAKEUP.\nNote:\nThe ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital \ninterface is enabled even if the ENx bit is reset.\n14.3.2 \nDAC output buffer enable\nThe DAC integrates two output buffers that can be used to reduce the output impedance, \nand to drive external loads directly without having to add an external operational amplifier. \nEach DAC channel output buffer can be enabled and disabled using the corresponding \nBOFFx bit in the DAC_CR register.\n14.3.3 \nDAC data format\nDepending on the selected configuration mode, the data have to be written into the specified \nregister as described below:\n•\nSingle DAC channelx, there are three possibilities:\n–\n8-bit right alignment: the software has to load data into the DAC_DHR8Rx [7:0] \nbits (stored into the DHRx[11:4] bits)\n–\n12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4] \nbits (stored into the DHRx[11:0] bits)\n–\n12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0] \nbits (stored into the DHRx[11:0] bits)\nDepending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and \nstored into the corresponding DHRx (data holding registerx, which are internal non-memory-\nmapped registers). The DHRx register is then loaded into the DORx register either \nautomatically, by software trigger or by an external event trigger.\n\n\n<>\n\nRM0090 Rev 21\n439/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\nFigure 65. Data registers in single DAC channel mode \n•\nDual DAC channels, there are three possibilities:\n–\n8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD \n[7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded \ninto the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits)\n–\n12-bit left alignment: data for DAC channel1 to be loaded into the DAC_DHR12LD \n[15:4] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be \nloaded into the DAC_DHR12LD [31:20] bits (stored into the DHR2[11:0] bits)\n–\n12-bit right alignment: data for DAC channel1 to be loaded into the \nDAC_DHR12RD [11:0] bits (stored into the DHR1[11:0] bits) and data for DAC \nchannel2 to be loaded into the DAC_DHR12LD [27:16] bits (stored into the \nDHR2[11:0] bits)\nDepending on the loaded DAC_DHRyyyD register, the data written by the user is shifted \nand stored into DHR1 and DHR2 (data holding registers, which are internal non-memory-\nmapped registers). The DHR1 and DHR2 registers are then loaded into the DOR1 and \nDOR2 registers, respectively, either automatically, by software trigger or by an external \nevent trigger.\nFigure 66. Data registers in dual DAC channel mode\n14.3.4 \nDAC conversion\nThe DAC_DORx cannot be written directly and any data transfer to the DAC channelx must \nbe performed by loading the DAC_DHRx register (write to DAC_DHR8Rx, DAC_DHR12Lx, \nDAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12LD).\nData stored in the DAC_DHRx register are automatically transferred to the DAC_DORx \nregister after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR \nregister is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR \nregister is set) and a trigger occurs, the transfer is performed three APB1 clock cycles later.\n31\n24\n15\n7\n0\n8-bit right aligned\n12-bit left aligned\n12-bit right aligned\nai14710b\n31\n24\n15\n7\n0\n8-bit right aligned\n12-bit left aligned\n12-bit right aligned\nai14709\n31\n24\n15\n7\n0\n8-bit right aligned\n12-bit left aligned\n12-bit right aligned\nai14709b\n\n\n<>\n\nDigital-to-analog converter (DAC)\nRM0090\n440/1757\nRM0090 Rev 21\nWhen DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage \nbecomes available after a time tSETTLING that depends on the power supply voltage and the \nanalog output load.\nFigure 67. Timing diagram for conversion with trigger disabled TEN = 0\n14.3.5 \nDAC output voltage\nDigital inputs are converted to output voltages on a linear conversion between 0 and VREF+.\nThe analog output voltages on each DAC channel pin are determined by the following \nequation:\n14.3.6 \nDAC trigger selection\nIf the TENx control bit is set, conversion can then be triggered by an external event (timer \ncounter, external interrupt line). The TSELx[2:0] control bits determine which out of eight \npossible events trigger conversion as shown in Table 76.\n \nEach time a DAC interface detects a rising edge on the selected timer TRGO output, or on \nthe selected external interrupt line 9, the last data stored into the DAC_DHRx register are \ntransferred into the DAC_DORx register. The DAC_DORx register is updated three APB1 \ncycles after the trigger occurs.\nAPB1_CLK\n0x1AC\n0x1AC\ntSETTLING\nDHR\nDOR\nOutput voltage\navailable on DAC_OUT pin\nai14711c\nDACoutput \nVREF\nDOR\n4096\n-------------\n×\n=\nTable 76. External triggers\nSource\nType\nTSEL[2:0]\nTimer 6 TRGO event\nInternal signal from on-chip \ntimers\n000\nTimer 8 TRGO event\n001\nTimer 7 TRGO event\n010\nTimer 5 TRGO event\n011\nTimer 2 TRGO event\n100\nTimer 4 TRGO event\n101\nEXTI line9\nExternal pin\n110\nSWTRIG\nSoftware control bit\n111\n\n\n<>\n\nRM0090 Rev 21\n441/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\nIf the software trigger is selected, the conversion starts once the SWTRIG bit is set. \nSWTRIG is reset by hardware once the DAC_DORx register has been loaded with the \nDAC_DHRx register contents.\nNote:\nTSELx[2:0] bit cannot be changed when the ENx bit is set.\nWhen software trigger is selected, the transfer from the DAC_DHRx register to the \nDAC_DORx register takes only one APB1 clock cycle.\n14.3.7 \nDMA request\nEach DAC channel has a DMA capability. Two DMA channels are used to service DAC \nchannel DMA requests.\nA DAC DMA request is generated when an external trigger (but not a software trigger) \noccurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred \ninto the DAC_DORx register.\nIn dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one \nDMA request is needed, the user should set only the corresponding DMAENx bit. In this \nway, the application can manage both DAC channels in dual mode by using one DMA \nrequest and a unique DMA channel.\nDMA underrun\nThe DAC DMA request is not queued so that if a second external trigger arrives before the \nacknowledgement for the first external trigger is received (first request), then no new \nrequest is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register \nis set, reporting the error condition. DMA data transfers are then disabled and no further \nDMA request is treated. The DAC channelx continues to convert old data.\nThe software should clear the DMAUDRx flag by writing “1”, clear the DMAEN bit of the \nused DMA stream and re-initialize both DMA and DAC channelx to restart the transfer \ncorrectly. The software should modify the DAC trigger conversion frequency or lighten the \nDMA workload to avoid a new DMA underrun. Finally, the DAC conversion could be \nresumed by enabling both DMA data transfer and conversion trigger.\nFor each DAC channelx, an interrupt is also generated if its corresponding DMAUDRIEx bit \nin the DAC_CR register is enabled.\n14.3.8 \nNoise generation\nIn order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift \nregister) is available. DAC noise generation is selected by setting WAVEx[1:0] to “01”. The \npreloaded value in LFSR is 0xAAA. This register is updated three APB1 clock cycles after \neach trigger event, following a specific calculation algorithm.\n\n\n<>\n\nDigital-to-analog converter (DAC)\nRM0090\n442/1757\nRM0090 Rev 21\nFigure 68. DAC LFSR register calculation algorithm\nThe LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in \nthe DAC_CR register, is added up to the DAC_DHRx contents without overflow and this \nvalue is then stored into the DAC_DORx register.\nIf LFSR is 0x0000, a ‘1 is injected into it (antilock-up mechanism).\nIt is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.\nFigure 69. DAC conversion (SW trigger enabled) with LFSR wave generation\nNote:\nThe DAC trigger must be enabled for noise generation by setting the TENx bit in the \nDAC_CR register.\n14.3.9 \nTriangle-wave generation\nIt is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. \nDAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is \nconfigured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter \nis incremented three APB1 clock cycles after each trigger event. The value of this counter is \nthen added to the DAC_DHRx register without overflow and the sum is stored into the \nDAC_DORx register. The triangle counter is incremented as long as it is less than the \nmaximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is \nreached, the counter is decremented down to 0, then incremented again and so on.\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n12\nNOR\nX12\nX0\nX\nX4\nX6\nXOR\nai14713c\nAPB1_CLK\n0x00\n0xAAA\nDHR\nDOR\nai14714b\n0xD55\nSWTRIG\n\n\n<>\n\nRM0090 Rev 21\n443/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\nIt is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits.\nFigure 70. DAC triangle wave generation\nFigure 71. DAC conversion (SW trigger enabled) with triangle wave generation\nNote:\nThe DAC trigger must be enabled for noise generation by setting the TENx bit in the \nDAC_CR register.\nThe MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot \nbe changed.\n14.4 \nDual DAC channel conversion\nTo efficiently use the bus bandwidth in applications that require the two DAC channels at the \nsame time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A \nunique register access is then required to drive both DAC channels at the same time.\nEleven possible conversion modes are possible using the two DAC channels and these dual \nregisters. All the conversion modes can nevertheless be obtained using separate DHRx \nregisters if needed.\nAll modes are described in the paragraphs below.\nMAMPx[3:0] max amplitude\n+ DAC_DHRx base value\nDAC_DHRx base value\nIncrementation\nai14715c\nDecrementation\n0\nAPB1_CLK\n0x00\n0xAAA\nDHR\nDOR\nai14714b\n0xD55\nSWTRIG\n\n\n<>\n\nDigital-to-analog converter (DAC)\nRM0090\n444/1757\nRM0090 Rev 21\n14.4.1 \nIndependent trigger without wave generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure different trigger sources by setting different values in the TSEL1[2:0] and \nTSEL2[2:0] bits\n•\nLoad the dual DAC channel data into the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nWhen a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1 \n(three APB1 clock cycles later).\nWhen a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2 \n(three APB1 clock cycles later). \n14.4.2 \nIndependent trigger with single LFSR generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure different trigger sources by setting different values in the TSEL1[2:0] and \nTSEL2[2:0] bits\n•\nConfigure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask \nvalue in the MAMPx[3:0] bits\n•\nLoad the dual DAC channel data into the desired DHR register (DHR12RD, DHR12LD \nor DHR8RD)\nWhen a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to \nthe DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles \nlater). Then the LFSR1 counter is updated.\nWhen a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to \nthe DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles \nlater). Then the LFSR2 counter is updated.\n14.4.3 \nIndependent trigger with different LFSR generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure different trigger sources by setting different values in the TSEL1[2:0] and \nTSEL2[2:0] bits\n•\nConfigure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR masks \nvalues in the MAMP1[3:0] and MAMP2[3:0] bits\n•\nLoad the dual DAC channel data into the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nWhen a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by \nMAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 \n(three APB1 clock cycles later). Then the LFSR1 counter is updated.\nWhen a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by \nMAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 \n(three APB1 clock cycles later). Then the LFSR2 counter is updated.\n\n\n<>\n\nRM0090 Rev 21\n445/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\n14.4.4 \nIndependent trigger with single triangle generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure different trigger sources by setting different values in the TSEL1[2:0] and \nTSEL2[2:0] bits\n•\nConfigure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum \namplitude value in the MAMPx[3:0] bits\n•\nLoad the dual DAC channel data into the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nWhen a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same \ntriangle amplitude, is added to the DHR1 register and the sum is transferred into \nDAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then \nupdated.\nWhen a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same \ntriangle amplitude, is added to the DHR2 register and the sum is transferred into \nDAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then \nupdated.\n14.4.5 \nIndependent trigger with different triangle generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure different trigger sources by setting different values in the TSEL1[2:0] and \nTSEL2[2:0] bits\n•\nConfigure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum \namplitude values in the MAMP1[3:0] and MAMP2[3:0] bits\n•\nLoad the dual DAC channel data into the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nWhen a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with a triangle \namplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is \ntransferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle \ncounter is then updated.\nWhen a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle \namplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is \ntransferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle \ncounter is then updated.\n14.4.6 \nSimultaneous software start\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nLoad the dual DAC channel data to the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nIn this configuration, one APB1 clock cycle later, the DHR1 and DHR2 registers are \ntransferred into DAC_DOR1 and DAC_DOR2, respectively.\n\n\n<>\n\nDigital-to-analog converter (DAC)\nRM0090\n446/1757\nRM0090 Rev 21\n14.4.7 \nSimultaneous trigger without wave generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure the same trigger source for both DAC channels by setting the same value in \nthe TSEL1[2:0] and TSEL2[2:0] bits\n•\nLoad the dual DAC channel data to the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nWhen a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and \nDAC_DOR2, respectively (after three APB1 clock cycles).\n14.4.8 \nSimultaneous trigger with single LFSR generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure the same trigger source for both DAC channels by setting the same value in \nthe TSEL1[2:0] and TSEL2[2:0] bits\n•\nConfigure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask \nvalue in the MAMPx[3:0] bits\n•\nLoad the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or \nDHR8RD)\nWhen a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 \nregister and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The \nLFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask, \nis added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 \nclock cycles later). The LFSR2 counter is then updated.\n14.4.9 \nSimultaneous trigger with different LFSR generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure the same trigger source for both DAC channels by setting the same value in \nthe TSEL1[2:0] and TSEL2[2:0] bits\n•\nConfigure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR mask \nvalues using the MAMP1[3:0] and MAMP2[3:0] bits\n•\nLoad the dual DAC channel data into the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nWhen a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is \nadded to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock \ncycles later). The LFSR1 counter is then updated.\nAt the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to \nthe DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles \nlater). The LFSR2 counter is then updated.\n\n\n<>\n\nRM0090 Rev 21\n447/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\n14.4.10 \nSimultaneous trigger with single triangle generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure the same trigger source for both DAC channels by setting the same value in \nthe TSEL1[2:0] and TSEL2[2:0] bits\n•\nConfigure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum \namplitude value using the MAMPx[3:0] bits\n•\nLoad the dual DAC channel data into the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nWhen a trigger arrives, the DAC channel1 triangle counter, with the same triangle \namplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three \nAPB1 clock cycles later). The DAC channel1 triangle counter is then updated.\nAt the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is \nadded to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock \ncycles later). The DAC channel2 triangle counter is then updated.\n14.4.11 \nSimultaneous trigger with different triangle generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure the same trigger source for both DAC channels by setting the same value in \nthe TSEL1[2:0] and TSEL2[2:0] bits\n•\nConfigure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum \namplitude values in the MAMP1[3:0] and MAMP2[3:0] bits\n•\nLoad the dual DAC channel data into the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nWhen a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude \nconfigured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into \nDAC_DOR1 (three APB1 clock cycles later). Then the DAC channel1 triangle counter is \nupdated.\nAt the same time, the DAC channel2 triangle counter, with a triangle amplitude configured \nby MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 \n(three APB1 clock cycles later). Then the DAC channel2 triangle counter is updated.\n\n\n<>\n\nDigital-to-analog converter (DAC)\nRM0090\n448/1757\nRM0090 Rev 21\n14.5 \nDAC registers\nRefer to Section 1.1: List of abbreviations for registers for registers for a list of abbreviations \nused in register descriptions.\nThe peripheral registers have to be accessed by words (32 bits).\n14.5.1 \nDAC control register (DAC_CR)\nAddress offset: 0x00\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nDMAU\nDRIE2\nDMA \nEN2\nMAMP2[3:0]\nWAVE2[1:0]\nTSEL2[2:0]\nTEN2\nBOFF2\nEN2\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDMAU\nDRIE1\nDMA \nEN1\nMAMP1[3:0]\nWAVE1[1:0]\nTSEL1[2:0]\nTEN1\nBOFF1\nEN1\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBits 29 DMAUDRIE2: DAC channel2 DMA underrun interrupt enable\nThis bit is set and cleared by software.\n0: DAC channel2 DMA underrun interrupt disabled\n1: DAC channel2 DMA underrun interrupt enabled\nBit 28 DMAEN2: DAC channel2 DMA enable\nThis bit is set and cleared by software.\n0: DAC channel2 DMA mode disabled\n1: DAC channel2 DMA mode enabled\nBits 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector\nThese bits are written by software to select mask in wave generation mode or amplitude in \ntriangle generation mode.\n0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1\n0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3\n0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7\n0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15\n0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31\n0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63\n0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127\n0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255\n1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511\n1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023\n1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047\n≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095\nBits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable\nThese bits are set/reset by software.\n00: wave generation disabled \n01: Noise wave generation enabled \n1x: Triangle wave generation enabled\nNote: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)\n\n\n<>\n\nRM0090 Rev 21\n449/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\nBits 21:19 TSEL2[2:0]: DAC channel2 trigger selection\nThese bits select the external event used to trigger DAC channel2\n000: Timer 6 TRGO event\n001: Timer 8 TRGO event\n010: Timer 7 TRGO event\n011: Timer 5 TRGO event\n100: Timer 2 TRGO event\n101: Timer 4 TRGO event\n110: External line9\n111: Software trigger \nNote: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).\nBit 18 TEN2: DAC channel2 trigger enable\nThis bit is set and cleared by software to enable/disable DAC channel2 trigger \n0: DAC channel2 trigger disabled and data written into the DAC_DHRx register are \ntransferred one APB1 clock cycle later to the DAC_DOR2 register\n1: DAC channel2 trigger enabled and data from the DAC_DHRx register are transferred \nthree APB1 clock cycles later to the DAC_DOR2 register\nNote: When software trigger is selected, the transfer from the DAC_DHRx register to the \nDAC_DOR2 register takes only one APB1 clock cycle.\nBit 17 BOFF2: DAC channel2 output buffer disable\nThis bit is set and cleared by software to enable/disable DAC channel2 output buffer.\n0: DAC channel2 output buffer enabled\n1: DAC channel2 output buffer disabled\nBit 16 EN2: DAC channel2 enable\nThis bit is set and cleared by software to enable/disable DAC channel2.\n0: DAC channel2 disabled\n1: DAC channel2 enabled\nBits 15:14 Reserved, must be kept at reset value.\nBit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable\nThis bit is set and cleared by software. \n0: DAC channel1 DMA Underrun Interrupt disabled\n1: DAC channel1 DMA Underrun Interrupt enabled\nBit 12 DMAEN1: DAC channel1 DMA enable\nThis bit is set and cleared by software.\n0: DAC channel1 DMA mode disabled\n1: DAC channel1 DMA mode enabled\n\n\n<>\n\nDigital-to-analog converter (DAC)\nRM0090\n450/1757\nRM0090 Rev 21\nBits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector\nThese bits are written by software to select mask in wave generation mode or amplitude in \ntriangle generation mode.\n0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1\n0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3\n0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7\n0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15\n0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31\n0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63\n0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127\n0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255\n1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511\n1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023\n1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047\n≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095\nBits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable\nThese bits are set and cleared by software.\n00: wave generation disabled\n01: Noise wave generation enabled\n1x: Triangle wave generation enabled\nNote: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).\nBits 5:3 TSEL1[2:0]: DAC channel1 trigger selection\nThese bits select the external event used to trigger DAC channel1.\n000: Timer 6 TRGO event\n001: Timer 8 TRGO event\n010: Timer 7 TRGO event\n011: Timer 5 TRGO event\n100: Timer 2 TRGO event\n101: Timer 4 TRGO event\n110: External line9\n111: Software trigger\nNote: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).\nBit 2 TEN1: DAC channel1 trigger enable\nThis bit is set and cleared by software to enable/disable DAC channel1 trigger.\n0: DAC channel1 trigger disabled and data written into the DAC_DHRx register are \ntransferred one APB1 clock cycle later to the DAC_DOR1 register\n1: DAC channel1 trigger enabled and data from the DAC_DHRx register are transferred \nthree APB1 clock cycles later to the DAC_DOR1 register\nNote: When software trigger is selected, the transfer from the DAC_DHRx register to the \nDAC_DOR1 register takes only one APB1 clock cycle.\nBit 1 BOFF1: DAC channel1 output buffer disable\nThis bit is set and cleared by software to enable/disable DAC channel1 output buffer.\n0: DAC channel1 output buffer enabled\n1: DAC channel1 output buffer disabled\nBit 0 EN1: DAC channel1 enable\nThis bit is set and cleared by software to enable/disable DAC channel1.\n0: DAC channel1 disabled\n1: DAC channel1 enabled\n\n\n<>\n\nRM0090 Rev 21\n451/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\n14.5.2 \nDAC software trigger register (DAC_SWTRIGR)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n14.5.3 \nDAC channel1 12-bit right-aligned data holding register\n(DAC_DHR12R1)\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSWTRIG2 SWTRIG1\nw\nw\nBits 31:2 Reserved, must be kept at reset value.\nBit 1 SWTRIG2: DAC channel2 software trigger\nThis bit is set and cleared by software to enable/disable the software trigger.\n0: Software trigger disabled\n1: Software trigger enabled\nNote: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 \nregister value has been loaded into the DAC_DOR2 register.\nBit 0 SWTRIG1: DAC channel1 software trigger\nThis bit is set and cleared by software to enable/disable the software trigger.\n0: Software trigger disabled\n1: Software trigger enabled\nNote: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 \nregister value has been loaded into the DAC_DOR1 register.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDACC1DHR[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data \nThese bits are written by software which specifies 12-bit data for DAC channel1.\n\n\n<>\n\nDigital-to-analog converter (DAC)\nRM0090\n452/1757\nRM0090 Rev 21\n14.5.4 \nDAC channel1 12-bit left aligned data holding register\n(DAC_DHR12L1)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n \n \n14.5.5 \nDAC channel1 8-bit right aligned data holding register\n(DAC_DHR8R1)\nAddress offset: 0x10\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDACC1DHR[11:0]\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data\nThese bits are written by software which specifies 12-bit data for DAC channel1.\nBits 3:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDACC1DHR[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data\nThese bits are written by software which specifies 8-bit data for DAC channel1.\n\n\n<>\n\nRM0090 Rev 21\n453/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\n14.5.6 \nDAC channel2 12-bit right aligned data holding register\n(DAC_DHR12R2)\nAddress offset: 0x14\nReset value: 0x0000 0000\n \n14.5.7 \nDAC channel2 12-bit left aligned data holding register \n(DAC_DHR12L2)\nAddress offset: 0x18\nReset value: 0x0000 0000\n14.5.8 \nDAC channel2 8-bit right-aligned data holding register\n(DAC_DHR8R2)\nAddress offset: 0x1C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDACC2DHR[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data\nThese bits are written by software which specifies 12-bit data for DAC channel2.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDACC2DHR[11:0]\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data \nThese bits are written by software which specify 12-bit data for DAC channel2.\nBits 3:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDACC2DHR[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data\nThese bits are written by software which specifies 8-bit data for DAC channel2.\n\n\n<>\n\nDigital-to-analog converter (DAC)\nRM0090\n454/1757\nRM0090 Rev 21\n14.5.9 \nDual DAC 12-bit right-aligned data holding register\n(DAC_DHR12RD)\nAddress offset: 0x20\nReset value: 0x0000 0000\n14.5.10 \nDUAL DAC 12-bit left aligned data holding register\n(DAC_DHR12LD)\nAddress offset: 0x24\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nDACC2DHR[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDACC1DHR[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data\nThese bits are written by software which specifies 12-bit data for DAC channel2.\nBits 15:12 Reserved, must be kept at reset value.\nBits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data\nThese bits are written by software which specifies 12-bit data for DAC channel1.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDACC2DHR[11:0]\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDACC1DHR[11:0]\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data\nThese bits are written by software which specifies 12-bit data for DAC channel2.\nBits 19:16 Reserved, must be kept at reset value.\nBits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data\nThese bits are written by software which specifies 12-bit data for DAC channel1.\nBits 3:0 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n455/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\n14.5.11 \nDUAL DAC 8-bit right aligned data holding register\n(DAC_DHR8RD)\nAddress offset: 0x28\nReset value: 0x0000 0000\n \n14.5.12 \nDAC channel1 data output register (DAC_DOR1)\nAddress offset: 0x2C\nReset value: 0x0000 0000\n \n \n14.5.13 \nDAC channel2 data output register (DAC_DOR2)\nAddress offset: 0x30\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDACC2DHR[7:0]\nDACC1DHR[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data\nThese bits are written by software which specifies 8-bit data for DAC channel2.\nBits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data \nThese bits are written by software which specifies 8-bit data for DAC channel1.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDACC1DOR[11:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:12 Reserved, must be kept at reset value.\nBit 11:0 DACC1DOR[11:0]: DAC channel1 data output\nThese bits are read-only, they contain data output for DAC channel1.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDACC2DOR[11:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 DACC2DOR[11:0]: DAC channel2 data output\nThese bits are read-only, they contain data output for DAC channel2.\n\n\n<>\n\nDigital-to-analog converter (DAC)\nRM0090\n456/1757\nRM0090 Rev 21\n14.5.14 \nDAC status register (DAC_SR)\nAddress offset: 0x34\nReset value: 0x0000 0000\n \n \n14.5.15 \nDAC register map\nTable 77 summarizes the DAC registers. \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved \nDMAUDR2\nReserved \nrc_w1\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved \nDMAUDR1\nReserved \nrc_w1\nBits 31:30 Reserved, must be kept at reset value.\nBit 29 DMAUDR2: DAC channel2 DMA underrun flag\nThis bit is set by hardware and cleared by software (by writing it to 1).\n0: No DMA underrun error condition occurred for DAC channel2\n1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is \ndriving DAC channel2 conversion at a frequency higher than the DMA service capability rate)\nBits 28:14 Reserved, must be kept at reset value.\nBit 13 DMAUDR1: DAC channel1 DMA underrun flag\nThis bit is set by hardware and cleared by software (by writing it to 1).\n0: No DMA underrun error condition occurred for DAC channel1\n1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is \ndriving DAC channel1 conversion at a frequency higher than the DMA service capability rate)\nBits 12:0 Reserved, must be kept at reset value.\nTable 77. DAC register map\nOffset Register\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nDAC_CR\nReserved\nDMAUDRIE2\nDMAEN2\nMAMP2[3:0]\nWAVE\n2[2:0]\nTSEL2[2:0]\nTEN2\nBOFF2\nEN2\nReserved\nDMAUDRIE1\nDMAEN1\nMAMP1[3:0]\nWAVE\n1[2:0]\nTSEL1[2\n:0]\nTEN1\nBOFF1\nEN1\n0x04\nDAC_\nSWTRIGR\nReserved\nSWTRIG2\nSWTRIG1\n0x08\nDAC_\nDHR12R1\nReserved\nDACC1DHR[11:0]\n0x0C\nDAC_\nDHR12L1\nReserved\nDACC1DHR[11:0]\nReserved\n0x10\nDAC_\nDHR8R1\nReserved\nDACC1DHR[7:0]\n0x14\nDAC_\nDHR12R2\nReserved\nDACC2DHR[11:0]\n0x18\nDAC_\nDHR12L2\nReserved\nDACC2DHR[11:0]\nReserved\n\n\n<>\n\nRM0090 Rev 21\n457/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x1C\nDAC_\nDHR8R2\nReserved\nDACC2DHR[7:0]\n0x20\nDAC_\nDHR12RD\nReserved\nDACC2DHR[11:0]\nReserved\nDACC1DHR[11:0]\n0x24\nDAC_\nDHR12LD\nDACC2DHR[11:0]\nReserved\nDACC1DHR[11:0]\nReserved\n0x28\nDAC_\nDHR8RD\nReserved\nDACC2DHR[7:0]\nDACC1DHR[7:0]\n0x2C\nDAC_\nDOR1\nReserved\nDACC1DOR[11:0]\n0x30\nDAC_\nDOR2\nReserved\nDACC2DOR[11:0]\n0x34\nDAC_SR\nReserved\nDMAUDR2\nReserved\nDMAUDR1\nReserved\nTable 77. DAC register map (continued)\nOffset Register\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nDigital camera interface (DCMI)\nRM0090\n458/1757\nRM0090 Rev 21\n15 \nDigital camera interface (DCMI)\nThis section applies to all STM32F4xx devices, unless otherwise specified.\n15.1 \nDCMI introduction\nThe digital camera is a synchronous parallel interface able to receive a high-speed data flow \nfrom an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data \nformats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).\nThis interface is for use with black & white cameras, X24 and X5 cameras, and it is \nassumed that all pre-processing like resizing is performed in the camera module.\n15.2 \nDCMI main features\n•\n8-, 10-, 12- or 14-bit parallel interface\n•\nEmbedded/external line and frame synchronization\n•\nContinuous or snapshot mode\n•\nCrop feature\n•\nSupports the following data formats:\n–\n8/10/12/14- bit progressive video: either monochrome or raw bayer\n–\nYCbCr 4:2:2 progressive video\n–\nRGB 565 progressive video\n–\nCompressed data: JPEG\n15.3 \nDCMI pins\nTable 78 shows the DCMI pins.\n \n15.4 \nDCMI clocks\nThe digital camera interface uses two clock domains PIXCLK and HCLK. The signals \ngenerated with PIXCLK are sampled on the rising edge of HCLK once they are stable. An \nenable signal is generated in the HCLK domain, to indicate that data coming from the \ncamera are stable and can be sampled. The minimum PIXCLK period must be higher than \n2.5 HCLK periods.\nTable 78. DCMI pins\nName\nSignal type\nD[0:13]\nData inputs\nHSYNC\nHorizontal synchronization input\nVSYNC\nVertical synchronization input\nPIXCLK\nPixel clock input\n\n\n<>\n\nRM0090 Rev 21\n459/1757\nRM0090\nDigital camera interface (DCMI)\n482\n15.5 \nDCMI functional overview\nThe digital camera interface is a synchronous parallel interface that can receive high-speed \n(up to 54 Mbytes/s) data flows. It consists of up to 14 data lines (D13-D0) and a pixel clock \nline (PIXCLK). The pixel clock has a programmable polarity, so that data can be captured on \neither the rising or the falling edge of the pixel clock.\nThe data are packed into a 32-bit data register (DCMI_DR) and then transferred through a \ngeneral-purpose DMA channel. The image buffer is managed by the DMA, not by the \ncamera interface.\nThe data received from the camera can be organized in lines/frames (raw YUB/RGB/Bayer \nmodes) or can be a sequence of JPEG images. To enable JPEG image reception, the JPEG \nbit (bit 3 of DCMI_CR register) must be set.\nThe data flow is synchronized either by hardware using the optional HSYNC (horizontal \nsynchronization) and VSYNC (vertical synchronization) signals or by synchronization codes \nembedded in the data flow.\nFigure 72 shows the DCMI block diagram.\nFigure 72. DCMI block diagram\nDMA\ninterface\nControl/Status\nregister\nAHB\ninterface\nFIFO/\nData\nformatter\nData\nextraction\nSynchronizer DCMI_PIXCLK\nDCMI_D[0:13], DCMI_HSYNC, DCMI_VSYNC\nai15604b\n\n\n<>\n\nDigital camera interface (DCMI)\nRM0090\n460/1757\nRM0090 Rev 21\nFigure 73. Top-level block diagram\n15.5.1 \nDMA interface\nThe DMA interface is active when the CAPTURE bit in the DCMI_CR register is set. A DMA \nrequest is generated each time the camera interface receives a complete 32-bit data block \nin its register.\n15.5.2 \nDCMI physical interface\nThe interface is composed of 11/13/15/17 inputs. Only the Slave mode is supported.\nThe camera interface can capture 8-bit, 10-bit, 12-bit or 14-bit data depending on the \nEDM[1:0] bits in the DCMI_CR register. If less than 14 bits are used, the unused data pins \nmust not be assigned to DCMI interface through GPIO alternate functions.\n \nThe data are synchronous with PIXCLK and change on the rising/falling edge of the pixel \nclock depending on the polarity.\nThe HSYNC signal indicates the start/end of a line.\nThe VSYNC signal indicates the start/end of a frame\nDCMI\nInterrupt\ncontroller\nDCMI_IT\nExternal\ninterface\nDCMI_D[0:13]\nDCMI_PIXCLK\nDCMI_HSYNC\nDCMI_VSYNC\nDMA_REQ\nHCLK\nai15603b\nTable 79. DCMI signals\nSignal name\nSignal description\n8 bits\n10 bits\n12 bits\n14 bits\nD[0..7]\nD[0..9]\nD[0..11]\nD[0..13]\nData\nPIXCLK\nPixel clock\nHSYNC\nHorizontal synchronization / Data valid\nVSYNC\nVertical synchronization\n\n\n<>\n\nRM0090 Rev 21\n461/1757\nRM0090\nDigital camera interface (DCMI)\n482\nFigure 74. DCMI signal waveforms\n1.\nThe capture edge of DCMI_PIXCLK is the falling edge, the active state of DCMI_HSYNC and \nDCMI_VSYNC is 1.\n1.\nDCMI_HSYNC and DCMI_VSYNC can change states at the same time.\n8-bit data\nWhen EDM[1:0] in DCMI_CR are programmed to “00” the interface captures 8 LSB’s at its \ninput (D[0:7]) and stores them as 8-bit data. The D[13:8] inputs are ignored. In this case, to \ncapture a 32-bit word, the camera interface takes four pixel clock cycles.\nThe first captured data byte is placed in the LSB position in the 32-bit word and the 4th \ncaptured data byte is placed in the MSB position in the 32-bit word. Table 80 gives an \nexample of the positioning of captured data bytes in two 32-bit words.\n \n10-bit data\nWhen EDM[1:0] in DCMI_CR are programmed to “01”, the camera interface captures 10-bit \ndata at its input D[0..9] and stores them as the 10 least significant bits of a 16-bit word. The \nremaining most significant bits in the DCMI_DR register (bits 11 to 15) are cleared to zero. \nSo, in this case, a 32-bit data word is made up every two pixel clock cycles.\nThe first captured data are placed in the LSB position in the 32-bit word and the 2nd \ncaptured data are placed in the MSB position in the 32-bit word as shown in Table 81.\n \nTable 80. Positioning of captured data bytes in 32-bit words (8-bit width)\nByte address\n31:24\n23:16\n15:8\n7:0\n0\nDn+3[7:0]\nDn+2[7:0]\nDn+1[7:0]\nDn[7:0]\n4\nDn+7[7:0]\nDn+6[7:0]\nDn+5[7:0]\nDn+4[7:0]\nTable 81. Positioning of captured data bytes in 32-bit words (10-bit width)\nByte address\n31:26\n25:16\n15:10\n9:0\n0\n0\nDn+1[9:0]\n0\nDn[9:0]\n4\n0\nDn+3[9:0]\n0\nDn+2[9:0]\nDCMI_PIXCLK\nDCMI_DR[0:13]\nDCMI_HSYNC\nDCMI_VSYNC\nai15606b\n\n\n<>\n\nDigital camera interface (DCMI)\nRM0090\n462/1757\nRM0090 Rev 21\n12-bit data\nWhen EDM[1:0] in DCMI_CR are programmed to “10”, the camera interface captures the \n12-bit data at its input D[0..11] and stores them as the 12 least significant bits of a 16-bit \nword. The remaining most significant bits are cleared to zero. So, in this case a 32-bit data \nword is made up every two pixel clock cycles.\nThe first captured data are placed in the LSB position in the 32-bit word and the 2nd \ncaptured data are placed in the MSB position in the 32-bit word as shown in Table 82.\n \n14-bit data\nWhen EDM[1:0] in DCMI_CR are programmed to “11”, the camera interface captures the \n14-bit data at its input D[0..13] and stores them as the 14 least significant bits of a 16-bit \nword. The remaining most significant bits are cleared to zero. So, in this case a 32-bit data \nword is made up every two pixel clock cycles.\nThe first captured data are placed in the LSB position in the 32-bit word and the 2nd \ncaptured data are placed in the MSB position in the 32-bit word as shown in Table 83.\n \n15.5.3 \nSynchronization\nThe digital camera interface supports embedded or hardware (HSYNC & VSYNC) \nsynchronization. When embedded synchronization is used, it is up to the digital camera \nmodule to make sure that the 0x00 and 0xFF values are used ONLY for synchronization \n(not in data). Embedded synchronization codes are supported only for the 8-bit parallel data \ninterface width (that is, in the DCMI_CR register, the EDM[1:0] bits should be cleared to \n“00”).\nFor compressed data, the DCMI supports only the hardware synchronization mode. In this \ncase, VSYNC is used as a start/end of the image, and HSYNC is used as a Data Valid \nsignal. Figure 75 shows the corresponding timing diagram.\nTable 82. Positioning of captured data bytes in 32-bit words (12-bit width)\nByte address\n31:28\n27:16\n15:12\n11:0\n0\n0\nDn+1[11:0]\n0\nDn[11:0]\n4\n0\nDn+3[11:0]\n0\nDn+2[11:0]\nTable 83. Positioning of captured data bytes in 32-bit words (14-bit width)\nByte address\n31:30\n29:16\n15:14\n13:0\n0\n0\nDn+1[13:0]\n0\nDn[13:0]\n4\n0\nDn+3[13:0]\n0\nDn+2[13:0]\n\n\n<>\n\nRM0090 Rev 21\n463/1757\nRM0090\nDigital camera interface (DCMI)\n482\nFigure 75. Timing diagram\nai15944b\nBeginning of JPEG stream\nJPEG data\nDCMI_HSYNC\nJPEG packet data \nDCMI_VSYNC\nPadding data \nat the end of the JPEG stream\nProgrammable\nJPEG packet size\nEnd of JPEG stream\nPacket dispatching depends on the image content.\nThis results in a variable blanking duration.\n\n\n<>\n\nDigital camera interface (DCMI)\nRM0090\n464/1757\nRM0090 Rev 21\nHardware synchronization mode\nIn hardware synchronisation mode, the two synchronization signals (HSYNC/VSYNC) are \nused.\nDepending on the camera module/mode, data may be transmitted during horizontal/vertical \nsynchronisation periods. The HSYNC/VSYNC signals act like blanking signals since all the \ndata received during HSYNC/VSYNC active periods are ignored.\nIn order to correctly transfer images into the DMA/RAM buffer, data transfer is synchronized \nwith the VSYNC signal. When the hardware synchronisation mode is selected, and capture \nis enabled (CAPTURE bit set in DCMI_CR), data transfer is synchronized with the \ndeactivation of the VSYNC signal (next start of frame).\nTransfer can then be continuous, with successive frames transferred by DMA to successive \nbuffers or the same/circular buffer. To allow the DMA management of successive frames, a \nVSIF (Vertical synchronization interrupt flag) is activated at the end of each frame.\nEmbedded data synchronization mode\nIn this synchronisation mode, the data flow is synchronised using 32-bit codes embedded in \nthe data flow. These codes use the 0x00/0xFF values that are not used in data anymore. \nThere are 4 types of codes, all with a 0xFF0000XY format. The embedded synchronization \ncodes are supported only in 8-bit parallel data width capture (in the DCMI_CR register, the \nEDM[1:0] bits should be programmed to “00”). For other data widths, this mode generates \nunpredictable results and must not be used.\nNote:\nCamera modules can have 8 such codes (in interleaved mode). For this reason, the \ninterleaved mode is not supported by the camera interface (otherwise, every other half-\nframe would be discarded).\n•\nMode 2\nFour embedded codes signal the following events\n–\nFrame start (FS)\n–\nFrame end (FE)\n–\nLine start (LS)\n–\nLine end (LE)\nThe XY values in the 0xFF0000XY format of the four codes are programmable (see \nSection 15.8.7: DCMI embedded synchronization code register (DCMI_ESCR)).\nA 0xFF value programmed as a “frame end” means that all the unused codes are \ninterpreted as valid frame end codes. \nIn this mode, once the camera interface has been enabled, the frame capture starts \nafter the first occurrence of the frame end (FE) code followed by a frame start (FS) \ncode.\n•\nMode 1\nAn alternative coding is the camera mode 1. This mode is ITU656 compatible.\nThe codes signal another set of events:\n–\nSAV (active line) - line start \n–\nEAV (active line) - line end\n–\nSAV (blanking) - end of line during interframe blanking period\n–\nEAV (blanking) - end of line during interframe blanking period\n\n\n<>\n\nRM0090 Rev 21\n465/1757\nRM0090\nDigital camera interface (DCMI)\n482\nThis mode can be supported by programming the following codes:\n•\nFS ≤ 0xFF\n•\nFE ≤ 0xFF\n•\nLS ≤ SAV (active)\n•\nLE ≤ EAV (active)\nAn embedded unmask code is also implemented for frame/line start and frame/line end \ncodes. Using it, it is possible to compare only the selected unmasked bits with the \nprogrammed code. You can therefore select a bit to compare in the embedded code and \ndetect a frame/line start or frame/line end. This means that there can be different codes for \nthe frame/line start and frame/line end with the unmasked bit position remaining the same.\nExample\nFS = 0xA5\nUnmask code for FS = 0x10\nIn this case the frame start code is embedded in the bit 4 of the frame start code.\n15.5.4 \nCapture modes\nThis interface supports two types of capture: snapshot (single frame) and continuous grab.\nSnapshot mode (single frame)\nIn this mode, a single frame is captured (CM = ‘1’ in the DCMI_CR register). After the \nCAPTURE bit is set in DCMI_CR, the interface waits for the detection of a start of frame \nbefore sampling the data. The camera interface is automatically disabled (CAPTURE bit \ncleared in DCMI_CR) after receiving the first complete frame. An interrupt is generated \n(IT_FRAME) if it is enabled.\nIn case of an overrun, the frame is lost and the CAPTURE bit is cleared.\nFigure 76. Frame capture waveforms in Snapshot mode\n1.\nHere, the active state of DCMI_HSYNC and DCMI_VSYNC is 1.\n2.\nDCMI_HSYNC and DCMI_VSYNC can change states at the same time.\nDCMI_HSYNC\nDCMI_VSYNC\nFrame 1 captured\nFrame 2\nnot captured\nai15832b\n\n\n<>\n\nDigital camera interface (DCMI)\nRM0090\n466/1757\nRM0090 Rev 21\nContinuous grab mode\nIn this mode (CM bit = ‘0’ in DCMI_CR), once the CAPTURE bit has been set in DCMI_CR, \nthe grabbing process starts on the next VSYNC or embedded frame start depending on the \nmode. The process continues until the CAPTURE bit is cleared in DCMI_CR. Once the \nCAPTURE bit has been cleared, the grabbing process continues until the end of the current \nframe.\nFigure 77. Frame capture waveforms in continuous grab mode\n1.\nHere, the active state of DCMI_HSYNC and DCMI_VSYNC is 1.\n2.\nDCMI_HSYNC and DCMI_VSYNC can change states at the same time.\nIn continuous grab mode, you can configure the FCRC bits in DCMI_CR to grab all pictures, \nevery second picture or one out of four pictures to decrease the frame capture rate.\nNote:\nIn the hardware synchronization mode (ESS = ‘0’ in DCMI_CR), the IT_VSYNC interrupt is \ngenerated (if enabled) even when CAPTURE = ‘0’ in DCMI_CR so, to reduce the frame \ncapture rate even further, the IT_VSYNC interrupt can be used to count the number of \nframes between 2 captures in conjunction with the Snapshot mode. This is not allowed by \nembedded data synchronization mode.\n15.5.5 \nCrop feature\nWith the crop feature, the camera interface can select a rectangular window from the \nreceived image. The start (upper left corner) coordinates and size (horizontal dimension in \nnumber of pixel clocks and vertical dimension in number of lines) are specified using two 32-\nbit registers (DCMI_CWSTRT and DCMI_CWSIZE). The size of the window is specified in \nnumber of pixel clocks (horizontal dimension) and in number of lines (vertical dimension).\nDCMI_HSYNC\nDCMI_VSYNC\nFrame 1 captured\nFrame 2 captured\nai15833b\n\n\n<>\n\nRM0090 Rev 21\n467/1757\nRM0090\nDigital camera interface (DCMI)\n482\nFigure 78. Coordinates and size of the window after cropping\nThese registers specify the coordinates of the starting point of the capture window as a line \nnumber (in the frame, starting from 0) and a number of pixel clocks (on the line, starting from \n0), and the size of the window as a line number and a number of pixel clocks. The CAPCNT \nvalue can only be a multiple of 4 (two least significant bits are forced to 0) to allow the \ncorrect transfer of data through the DMA.\nIf the VSYNC signal goes active before the number of lines is specified in the \nDCMI_CWSIZE register, then the capture stops and an IT_FRAME interrupt is generated \nwhen enabled.\nFigure 79. Data capture waveforms\n1.\nHere, the active state of DCMI_HSYNC and DCMI_VSYNC is 1.\n2.\nDCMI_HSYNC and DCMI_VSYNC can change states at the same time.\nCAPCNT bit in DCMI_CSIZE\nHOFFCNT bit in DCMI_CSTRT\nai15834\nVST bit in DCMI_CSTRT\nVLINE bit in DCMI_CSIZE\nDCMI_HSYNC\nDCMI_VSYNC\nai15835\nCAPCNT\nHOFFCNT\nData not captured in this phase\nData captured in this phase\n\n\n<>\n\nDigital camera interface (DCMI)\nRM0090\n468/1757\nRM0090 Rev 21\n15.5.6 \nJPEG format\nTo allow JPEG image reception, it is necessary to set the JPEG bit in the DCMI_CR register. \nJPEG images are not stored as lines and frames, so the VSYNC signal is used to start the \ncapture while HSYNC serves as a data enable signal. The number of bytes in a line may not \nbe a multiple of 4, you should therefore be careful when handling this case since a DMA \nrequest is generated each time a complete 32-bit word has been constructed from the \ncaptured data. When an end of frame is detected and the 32-bit word to be transferred has \nnot been completely received, the remaining data are padded with ‘0s’ and a DMA request \nis generated.\nThe crop feature and embedded synchronization codes cannot be used in the JPEG format.\n15.5.7 \nFIFO\nA four-word FIFO is implemented to manage data rate transfers on the AHB. The DCMI \nfeatures a simple FIFO controller with a read pointer incremented each time the camera \ninterface reads from the AHB, and a write pointer incremented each time the camera \ninterface writes to the FIFO. There is no overrun protection to prevent the data from being \noverwritten if the AHB interface does not sustain the data transfer rate.\nIn case of overrun or errors in the synchronization signals, the FIFO is reset and the DCMI \ninterface waits for a new start of frame.\n15.6 \nData format description\n15.6.1 \nData formats\nThree types of data are supported:\n•\n8-bit progressive video: either monochrome or raw Bayer format\n•\nYCbCr 4:2:2 progressive video\n•\nRGB565 progressive video. A pixel coded in 16 bits (5 bits for blue, 5 bits for red, 6 bits \nfor green) takes two clock cycles to be transferred.\nCompressed data: JPEG\nFor B&W, YCbCr or RGB data, the maximum input size is 2048 × 2048 pixels. No limit in \nJPEG compressed mode.\nFor monochrome, RGB & YCbCr, the frame buffer is stored in raster mode. 32-bit words are \nused. Only the little endian format is supported.\nFigure 80. Pixel raster scan order\nPixel raster\nscan order\n(increasing\naddresses)\nWord0 Word1 Word2\nPixel row 0\nPixel row n – 1\nai15848\n\n\n<>\n\nRM0090 Rev 21\n469/1757\nRM0090\nDigital camera interface (DCMI)\n482\n15.6.2 \nMonochrome format\nCharacteristics:\n•\nRaster format\n•\n8 bits per pixel\nTable 84 shows how the data are stored.\n \n15.6.3 \nRGB format\nCharacteristics:\n•\nRaster format\n•\nRGB\n•\nInterleaved: one buffer: R, G & B interleaved: BRGBRGBRG, etc.\n•\nOptimized for display output\nThe RGB planar format is compatible with standard OS frame buffer display formats.\nOnly 16 BPP (bits per pixel): RGB565 (2 pixels per 32-bit word) is supported.\nThe 24 BPP (palletized format) and grayscale formats are not supported. Pixels are stored \nin a raster scan order, that is from top to bottom for pixel rows, and from left to right within a \npixel row. Pixel components are R (red), G (green) and B (blue). All components have the \nsame spatial resolution (4:4:4 format). A frame is stored in a single part, with the \ncomponents interleaved on a pixel basis.\nTable 85 shows how the data are stored.\n \n15.6.4 \nYCbCr format\nCharacteristics:\n•\nRaster format\n•\nYCbCr 4:2:2\n•\nInterleaved: one Buffer: Y, Cb & Cr interleaved: CbYCrYCbYCr, etc.\nPixel components are Y (luminance or “luma”), Cb and Cr (chrominance or “chroma” blue \nand red). Each component is encoded in 8 bits. Luma and chroma are stored together \n(interleaved) as shown in Table 86.\nTable 84. Data storage in monochrome progressive video format\nByte address\n31:24\n23:16\n15:8\n7:0\n0\nn + 3\nn + 2\nn + 1\nn\n4\nn + 7\nn + 6\nn + 5\nn + 4\nTable 85. Data storage in RGB progressive video format\nByte address\n31:27\n26:21\n20:16\n15:11\n10:5\n4:0\n0\nRed n + 1\nGreen n + 1\nBlue n + 1\nRed n\nGreen n\nBlue n\n4\nRed n + 4\nGreen n + 3\nBlue n + 3\nRed n + 2\nGreen n + 2\nBlue n + 2\n\n\n<>\n\nDigital camera interface (DCMI)\nRM0090\n470/1757\nRM0090 Rev 21\n \n15.7 \nDCMI interrupts\nFive interrupts are generated. All interrupts are maskable by software. The global interrupt \n(IT_DCMI) is the OR of all the individual interrupts. Table 87 gives the list of all interrupts.\n \n15.8 \nDCMI register description\nAll DCMI registers have to be accessed as 32-bit words, otherwise a bus error occurs.\n15.8.1 \nDCMI control register 1 (DCMI_CR)\nAddress offset: 0x00\nReset value: 0x0000 0x0000\n \n \nTable 86. Data storage in YCbCr progressive video format\nByte address\n31:24\n23:16\n15:8\n7:0\n0\nY n + 1\nCr n\nY n\nCb n\n4\nY n + 3\nCr n + 2\nY n + 2\nCb n + 2\nTable 87. DCMI interrupts\nInterrupt name\nInterrupt event\nIT_LINE\nIndicates the end of line\nIT_FRAME\nIndicates the end of frame capture\nIT_OVR\nindicates the overrun of data reception\nIT_VSYNC\nIndicates the synchronization frame\nIT_ERR\nIndicates the detection of an error in the embedded synchronization frame \ndetection\nIT_DCMI\nLogic OR of the previous interrupts\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nENABLE\nReserved\nEDM\nFCRC\nVSPOL\nHSPOL\nPCKPOL\nESS\nJPEG\nCROP\nCM\nCAPTURE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31:15 Reserved, must be kept at reset value.\nBit 14 ENABLE: DCMI enable\n0: DCMI disabled\n1: DCMI enabled\nNote: The DCMI configuration registers should be programmed correctly before \nenabling this Bit\nBit 13: 12 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n471/1757\nRM0090\nDigital camera interface (DCMI)\n482\nBits 11:10 EDM[1:0]: Extended data mode\n00: Interface captures 8-bit data on every pixel clock\n01: Interface captures 10-bit data on every pixel clock\n10: Interface captures 12-bit data on every pixel clock\n11: Interface captures 14-bit data on every pixel clock\nBits 9:8 FCRC[1:0]: Frame capture rate control\nThese bits define the frequency of frame capture. They are meaningful only in \nContinuous grab mode. They are ignored in snapshot mode.\n00: All frames are captured\n01: Every alternate frame captured (50% bandwidth reduction)\n10: One frame in 4 frames captured (75% bandwidth reduction)\n11: reserved\nBit 7 VSPOL: Vertical synchronization polarity\nThis bit indicates the level on the VSYNC pin when the data are not valid on the \nparallel interface.\n0: VSYNC active low\n1: VSYNC active high\nBit 6 HSPOL: Horizontal synchronization polarity\nThis bit indicates the level on the HSYNC pin when the data are not valid on the \nparallel interface.\n0: HSYNC active low\n1: HSYNC active high\nBit 5 PCKPOL: Pixel clock polarity\nThis bit configures the capture edge of the pixel clock\n0: Falling edge active.\n1: Rising edge active.\nBit 4 ESS: Embedded synchronization select\n0: Hardware synchronization data capture (frame/line start/stop) is synchronized \nwith the HSYNC/VSYNC signals.\n1: Embedded synchronization data capture is synchronized with synchronization \ncodes embedded in the data flow.\nNote: Valid only for 8-bit parallel data. HSPOL/VSPOL are ignored when the ESS \nbit is set.\nThis bit is disabled in JPEG mode.\nBit 3 JPEG: JPEG format\n0: Uncompressed video format\n1: This bit is used for JPEG data transfers. The HSYNC signal is used as data \nenable. The crop and embedded synchronization features (ESS bit) cannot be \nused in this mode.\nBits 2 CROP: Crop feature\n0: The full image is captured. In this case the total number of bytes in an image \nframe should be a multiple of 4\n1: Only the data inside the window specified by the crop register are captured. If \nthe size of the crop window exceeds the picture size, then only the picture size is \ncaptured.\n\n\n<>\n\nDigital camera interface (DCMI)\nRM0090\n472/1757\nRM0090 Rev 21\nBit 1 CM: Capture mode\n0: Continuous grab mode - The received data are transferred into the destination \nmemory through the DMA. The buffer location and mode (linear or circular \nbuffer) is controlled through the system DMA.\n1: Snapshot mode (single frame) - Once activated, the interface waits for the \nstart of frame and then transfers a single frame through the DMA. At the end of \nthe frame, the CAPTURE bit is automatically reset.\nBit 0 CAPTURE: Capture enable\n0: Capture disabled.\n1: Capture enabled.\nThe camera interface waits for the first start of frame, then a DMA request is \ngenerated to transfer the received data into the destination memory.\nIn snapshot mode, the CAPTURE bit is automatically cleared at the end of the \n1st frame received.\nIn continuous grab mode, if the software clears this bit while a capture is \nongoing, the bit is effectively cleared after the frame end.\nNote: The DMA controller and all DCMI configuration registers should be \nprogrammed correctly before enabling this bit.\n\n\n<>\n\nRM0090 Rev 21\n473/1757\nRM0090\nDigital camera interface (DCMI)\n482\n15.8.2 \nDCMI status register (DCMI_SR)\nAddress offset: 0x04\nReset value: 0x0000 0x0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFNE\nVSYNC\nHSYNC\nr\nr\nr\nBits 31:3 Reserved, must be kept at reset value.\nBit 2 FNE: FIFO not empty\nThis bit gives the status of the FIFO\n1: FIFO contains valid data\n0: FIFO empty\nBit 1 VSYNC\nThis bit gives the state of the VSYNC pin with the correct programmed polarity.\nWhen embedded synchronization codes are used, the meaning of this bit is the \nfollowing:\n0: active frame\n1: synchronization between frames\nIn case of embedded synchronization, this bit is meaningful only if the \nCAPTURE bit in DCMI_CR is set.\nBit 0 HSYNC\nThis bit gives the state of the HSYNC pin with the correct programmed polarity.\nWhen embedded synchronization codes are used, the meaning of this bit is the \nfollowing:\n0: active line\n1: synchronization between lines\nIn case of embedded synchronization, this bit is meaningful only if the \nCAPTURE bit in DCMI_CR is set.\n\n\n<>\n\nDigital camera interface (DCMI)\nRM0090\n474/1757\nRM0090 Rev 21\n15.8.3 \nDCMI raw interrupt status register (DCMI_RIS)\nAddress offset: 0x08\nReset value: 0x0000 0x0000\n \nDCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this \nregister returns the status of the corresponding interrupt before masking with the DCMI_IER \nregister value.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLINE_RIS\nVSYNC_RIS\nERR_RIS\nOVR_RIS\nFRAME_RIS\nr\nr\nr\nr\nr\nBits 31:5 Reserved, must be kept at reset value.\nBit 4 LINE_RIS: Line raw interrupt status\nThis bit gets set when the HSYNC signal changes from the inactive state to the \nactive state. It goes high even if the line is not valid.\nIn the case of embedded synchronization, this bit is set only if the CAPTURE bit \nin DCMI_CR is set.\nIt is cleared by writing a ‘1’ to the LINE_ISC bit in DCMI_ICR.\nBit 3 VSYNC_RIS: VSYNC raw interrupt status\nThis bit is set when the VSYNC signal changes from the inactive state to the \nactive state.\nIn the case of embedded synchronization, this bit is set only if the CAPTURE bit \nis set in DCMI_CR.\nIt is cleared by writing a ‘1’ to the VSYNC_ISC bit in DCMI_ICR.\nBit 2 ERR_RIS: Synchronization error raw interrupt status\n0: No synchronization error detected\n1: Embedded synchronization characters are not received in the correct order.\nThis bit is valid only in the embedded synchronization mode. It is cleared by \nwriting a ‘1’ to the ERR_ISC bit in DCMI_ICR.\nNote: This bit is available only in embedded synchronization mode.\nBit 1 OVR_RIS: Overrun raw interrupt status\n0: No data buffer overrun occurred\n1: A data buffer overrun occurred and the data FIFO is corrupted.\nThis bit is cleared by writing a ‘1’ to the OVR_ISC bit in DCMI_ICR.\nBit 0 FRAME_RIS: Capture complete raw interrupt status\n0: No new capture \n1: A frame has been captured.\nThis bit is set when a frame or window has been captured.\nIn case of a cropped window, this bit is set at the end of line of the last line in the \ncrop. It is set even if the captured frame is empty (e.g. window cropped outside \nthe frame).\nThis bit is cleared by writing a ‘1’ to the FRAME_ISC bit in DCMI_ICR.\n\n\n<>\n\nRM0090 Rev 21\n475/1757\nRM0090\nDigital camera interface (DCMI)\n482\n15.8.4 \nDCMI interrupt enable register (DCMI_IER)\nAddress offset: 0x0C\nReset value: 0x0000 0x0000\n \nThe DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set, \nthe corresponding interrupt is enabled. This register is accessible in both read and write.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLINE_IE\nVSYNC_IE\nERR_IE\nOVR_IE\nFRAME_IE\nrw\nrw\nrw\nrw\nrw\nBits 31:5 Reserved, must be kept at reset value.\nBit 4 LINE_IE: Line interrupt enable\n0: No interrupt generation when the line is received\n1: An Interrupt is generated when a line has been completely received\nBit 3 VSYNC_IE: VSYNC interrupt enable\n0: No interrupt generation\n1: An interrupt is generated on each VSYNC transition from the inactive to the \nactive state\nThe active state of the VSYNC signal is defined by the VSPOL bit.\nBit 2 ERR_IE: Synchronization error interrupt enable\n0: No interrupt generation\n1: An interrupt is generated if the embedded synchronization codes are not \nreceived in the correct order.\nNote: This bit is available only in embedded synchronization mode.\nBit 1 OVR_IE: Overrun interrupt enable\n0: No interrupt generation\n1: An interrupt is generated if the DMA was not able to transfer the last data \nbefore new data (32-bit) are received.\nBit 0 FRAME_IE: Capture complete interrupt enable\n0: No interrupt generation\n1: An interrupt is generated at the end of each received frame/crop window (in \ncrop mode).\n\n\n<>\n\nDigital camera interface (DCMI)\nRM0090\n476/1757\nRM0090 Rev 21\n15.8.5 \nDCMI masked interrupt status register (DCMI_MIS)\nThis DCMI_MIS register is a read-only register. When read, it returns the current masked \nstatus value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in \nthis register is set if the corresponding enable bit in DCMI_IER is set and the corresponding \nbit in DCMI_RIS is set.\nAddress offset: 0x10\nReset value: 0x0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLINE_MIS\nVSYNC_MIS\nERR_MIS\nOVR_MIS\nFRAME_MIS\nr\nr\nr\nr\nr\nBits 31:5 Reserved, must be kept at reset value.\nBit 4 LINE_MIS: Line masked interrupt status\nThis bit gives the status of the masked line interrupt\n0: No interrupt generation when the line is received\n1: An Interrupt is generated when a line has been completely received and the \nLINE_IE bit is set in DCMI_IER.\nBit 3 VSYNC_MIS: VSYNC masked interrupt status\nThis bit gives the status of the masked VSYNC interrupt\n0: No interrupt is generated on VSYNC transitions\n1: An interrupt is generated on each VSYNC transition from the inactive to the \nactive state and the VSYNC_IE bit is set in DCMI_IER.\nThe active state of the VSYNC signal is defined by the VSPOL bit.\nBit 2 ERR_MIS: Synchronization error masked interrupt status\nThis bit gives the status of the masked synchronization error interrupt\n0: No interrupt is generated on a synchronization error\n1: An interrupt is generated if the embedded synchronization codes are not \nreceived in the correct order and the ERR_IE bit in DCMI_IER is set.\nNote: This bit is available only in embedded synchronization mode.\nBit 1 OVR_MIS: Overrun masked interrupt status\nThis bit gives the status of the masked overflow interrupt\n0: No interrupt is generated on overrun\n1: An interrupt is generated if the DMA was not able to transfer the last data \nbefore new data (32-bit) are received and the OVR_IE bit is set in DCMI_IER.\nBit 0 FRAME_MIS: Capture complete masked interrupt status\nThis bit gives the status of the masked capture complete interrupt\n0: No interrupt is generated after a complete capture\n1: An interrupt is generated at the end of each received frame/crop window (in \ncrop mode) and the FRAME_IE bit is set in DCMI_IER.\n\n\n<>\n\nRM0090 Rev 21\n477/1757\nRM0090\nDigital camera interface (DCMI)\n482\n15.8.6 \nDCMI interrupt clear register (DCMI_ICR)\nAddress offset: 0x14\nReset value: 0x0000 0x0000\n \nThe DCMI_ICR register is write-only. Writing a ‘1’ into a bit of this register clears the \ncorresponding bit in the DCMI_RIS and DCMI_MIS registers. Writing a ‘0’ has no effect.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLINE_ISC\nVSYNC_ISC\nERR_ISC\nOVR_ISC\nFRAME_ISC\nw\nw\nw\nw\nw\nBits 15:5 Reserved, must be kept at reset value.\nBit 4 LINE_ISC: line interrupt status clear\nWriting a ‘1’ into this bit clears LINE_RIS in the DCMI_RIS register\nBit 3 VSYNC_ISC: Vertical synch interrupt status clear\nWriting a ‘1’ into this bit clears the VSYNC_RIS bit in DCMI_RIS\nBit 2 ERR_ISC: Synchronization error interrupt status clear\nWriting a ‘1’ into this bit clears the ERR_RIS bit in DCMI_RIS\nNote: This bit is available only in embedded synchronization mode.\nBit 1 OVR_ISC: Overrun interrupt status clear\nWriting a ‘1’ into this bit clears the OVR_RIS bit in DCMI_RIS\nBits 0 FRAME_ISC: Capture complete interrupt status clear\nWriting a ‘1’ into this bit clears the FRAME_RIS bit in DCMI_RIS\n\n\n<>\n\nDigital camera interface (DCMI)\nRM0090\n478/1757\nRM0090 Rev 21\n15.8.7 \nDCMI embedded synchronization code register (DCMI_ESCR)\nAddress offset: 0x18\nReset value: 0x0000 0x0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFEC\nLEC\nLSC\nFSC\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 FEC: Frame end delimiter code\nThis byte specifies the code of the frame end delimiter. The code consists of 4 \nbytes in the form of 0xFF, 0x00, 0x00, FEC.\nIf FEC is programmed to 0xFF, all the unused codes (0xFF0000XY) are \ninterpreted as frame end delimiters.\nBits 23:16 LEC: Line end delimiter code\nThis byte specifies the code of the line end delimiter. The code consists of 4 \nbytes in the form of 0xFF, 0x00, 0x00, LEC.\nBits 15:8 LSC: Line start delimiter code\nThis byte specifies the code of the line start delimiter. The code consists of 4 \nbytes in the form of 0xFF, 0x00, 0x00, LSC.\nBits 7:0 FSC: Frame start delimiter code\nThis byte specifies the code of the frame start delimiter. The code consists of 4 \nbytes in the form of 0xFF, 0x00, 0x00, FSC.\nIf FSC is programmed to 0xFF, no frame start delimiter is detected. But, the 1st \noccurrence of LSC after an FEC code is interpreted as a start of frame delimiter.\n\n\n<>\n\nRM0090 Rev 21\n479/1757\nRM0090\nDigital camera interface (DCMI)\n482\n15.8.8 \nDCMI embedded synchronization unmask register (DCMI_ESUR)\nAddress offset: 0x1C\nReset value: 0x0000 0x0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFEU\nLEU\nLSU\nFSU\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 FEU: Frame end delimiter unmask\nThis byte specifies the mask to be applied to the code of the frame end delimiter.\n0: The corresponding bit in the FEC byte in DCMI_ESCR is masked while \ncomparing the frame end delimiter with the received data.\n1: The corresponding bit in the FEC byte in DCMI_ESCR is compared while \ncomparing the frame end delimiter with the received data\nBits 23:16 LEU: Line end delimiter unmask\nThis byte specifies the mask to be applied to the code of the line end delimiter.\n0: The corresponding bit in the LEC byte in DCMI_ESCR is masked while \ncomparing the line end delimiter with the received data\n1: The corresponding bit in the LEC byte in DCMI_ESCR is compared while \ncomparing the line end delimiter with the received data\nBits 15:8 LSU: Line start delimiter unmask\nThis byte specifies the mask to be applied to the code of the line start delimiter.\n0: The corresponding bit in the LSC byte in DCMI_ESCR is masked while \ncomparing the line start delimiter with the received data\n1: The corresponding bit in the LSC byte in DCMI_ESCR is compared while \ncomparing the line start delimiter with the received data\nBits 7:0 FSU: Frame start delimiter unmask\nThis byte specifies the mask to be applied to the code of the frame start \ndelimiter.\n0: The corresponding bit in the FSC byte in DCMI_ESCR is masked while \ncomparing the frame start delimiter with the received data\n1: The corresponding bit in the FSC byte in DCMI_ESCR is compared while \ncomparing the frame start delimiter with the received data\n\n\n<>\n\nDigital camera interface (DCMI)\nRM0090\n480/1757\nRM0090 Rev 21\n15.8.9 \nDCMI crop window start (DCMI_CWSTRT)\nAddress offset: 0x20\nReset value: 0x0000 0x0000\n \n \n15.8.10 \nDCMI crop window size (DCMI_CWSIZE)\nAddress offset: 0x24\nReset value: 0x0000 0x0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nVST[12:0\nReserv\ned\nHOFFCNT[13:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:29 Reserved, must be kept at reset value.\nBits 28:16 VST[12:0]: Vertical start line count\nThe image capture starts with this line number. Previous line data are ignored.\n0x0000 => line 1\n0x0001 => line 2\n0x0002 => line 3\n....\nBits 15:14 Reserved, must be kept at reset value.\nBit 13:0 HOFFCNT[13:0]: Horizontal offset count\nThis value gives the number of pixel clocks to count before starting a capture.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nVLINE13:0]\nReserved\nCAPCNT[13:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBitst 29:16 VLINE[13:0]: Vertical line count\nThis value gives the number of lines to be captured from the starting point.\n0x0000 => 1 line\n0x0001 => 2 lines\n0x0002 => 3 lines\n....\nBits 15:14 Reserved, must be kept at reset value.\nBits 13:0 CAPCNT[13:0]: Capture count\nThis value gives the number of pixel clocks to be captured from the starting \npoint on the same line. It value should corresponds to word-aligned data for \ndifferent widths of parallel interfaces.\n0x0000 => 1 pixel\n0x0001 => 2 pixels\n0x0002 => 3 pixels\n....\n\n\n<>\n\nRM0090 Rev 21\n481/1757\nRM0090\nDigital camera interface (DCMI)\n482\n15.8.11 \nDCMI data register (DCMI_DR)\nAddress offset: 0x28\nReset value: 0x0000 0x0000\n \n \nThe digital camera Interface packages all the received data in 32-bit format before \nrequesting a DMA transfer. A 4-word deep FIFO is available to leave enough time for DMA \ntransfers and avoid DMA overrun conditions.\n15.8.12 \nDCMI register map\nTable 88 summarizes the DCMI registers.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nByte3\nByte2\nByte1\nByte0\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:24 Data byte 3\nBits 23:16 Data byte 2\nBits 15:8 Data byte 1\nBits 7:0 Data byte 0\nTable 88. DCMI register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nDCMI_CR\nReserved\nENABLE\nReserved\nEDM\nFCR\nC\nVSPOL\nHSPOL\nPCKPOL\nESS\nJPEG\nCROP\nCM\nCAPTURE\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nDCMI_SR\nReserved\nFNE\nVSYNC\nHSYNC\nReset value\n0\n0\n0\n0x08\nDCMI_RIS\nReserved\nLINE_RIS\nVSYNC_RIS\nERR_RIS\nOVR_RIS\nFRAME_RIS\nReset value\n0\n0\n0\n0\n0\n0x0C\nDCMI_IER\nReserved\nLINE_IE\nVSYNC_IE\nERR_IE\nOVR_IE\nFRAME_IE\nReset value\n0\n0\n0\n0\n0\n0x10\nDCMI_MIS\nReserved\nLINE_MIS\nVSYNC_MIS\nERR_MIS\nOVR_MIS\nFRAME_MIS\nReset value\n0\n0\n0\n0\n0\n\n\n<>\n\nDigital camera interface (DCMI)\nRM0090\n482/1757\nRM0090 Rev 21\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x14\nDCMI_ICR\nReserved\nLINE_ISC\nVSYNC_ISC\nERR_ISC\nOVR_ISC\nFRAME_ISC\nReset value\n0\n0\n0\n0\n0\n0x18\nDCMI_ESCR\nFEC\nLEC\nLSC\nFSC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nDCMI_ESUR\nFEU\nLEU\nLSU\nFSU\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nDCMI_CWSTR\nT\nReserve\nd\nVST[12:0\nReserved\nHOFFCNT[13:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x24\nDCMI_CWSIZ\nE\nReserved\nVLINE13:0]\nReserved\nCAPCNT[13:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nDCMI_DR\nByte3\nByte2\nByte1\nByte0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 88. DCMI register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n483/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16 \nLCD-TFT controller (LTDC)\nThis section applies only to STM32F429xx/439xx devices.\n16.1 \nIntroduction\nThe LCD-TFT (Liquid Crystal Display - Thin Film Transistor) display controller provides a \nparallel digital RGB (Red, Green, Blue) and signals for horizontal, vertical synchronisation, \nPixel Clock and Data Enable as output to interface directly to a variety of LCD and TFT \npanels.\n16.2 \nLTDC main features\n•\n24-bit RGB Parallel Pixel Output; 8 bits-per-pixel (RGB888)\n•\n2 display layers with dedicated FIFO (64x32-bit)\n•\nColor Look-Up Table (CLUT) up to 256 color (256x24-bit) per layer\n•\nSupports up to XGA (1024x768) resolution\n•\nProgrammable timings for different display panels\n•\nProgrammable Background color\n•\nProgrammable polarity for HSync, VSync and Data Enable\n•\nUp to 8 Input color formats selectable per layer\n–\nARGB8888\n–\nRGB888\n–\nRGB565\n–\nARGB1555\n–\nARGB4444\n–\nL8 (8-bit Luminance or CLUT)\n–\nAL44 (4-bit alpha + 4-bit luminance)\n–\nAL88 (8-bit alpha + 8-bit luminance)\n•\nPseudo-random dithering output for low bits per channel\n–\nDither width 2-bits for Red, Green, Blue\n•\nFlexible blending between two layers using alpha value (per pixel or constant)\n•\nColor Keying (transparency color) \n•\nProgrammable Window position and size \n•\nSupports thin film transistor (TFT) color displays \n•\nAHB master interface with burst of 16 words\n•\nUp to 4 programmable interrupt events\n\n\n<>\n\nLCD-TFT controller (LTDC)\nRM0090\n484/1757\nRM0090 Rev 21\n16.3 \nLTDC functional description\n16.3.1 \nLTDC block diagram \nThe block diagram of the LTDC is shown in Figure 81: LTDC block diagram. \nFigure 81. LTDC block diagram\nLayer FIFO: One FIFO 64x32 bit per layer.\nPFC: Pixel Format Convertor performing the pixel format conversion from the selected input \npixel format of a layer to words.\nAHB interface: For data transfer from memories to the FIFO.\nBlending, Dithering unit and Timings Generator: Refer to Section 16.4.1 and Section 16.4.2.\n16.3.2 \nLTDC reset and clocks\nThe LCD-TFT controller peripheral uses 3 clock domains:\n•\nThe AHB clock domain (HCLK) is used for data transfer from the memories to the \nLayer FIFO and frame buffer configuration register\n•\nThe APB2 clock domain (PCLK2) is used for global configuration register and interrupt \nregisters\n•\nThe Pixel Clock domain (LCD_CLK) is used to generate LCD-TFT interface signals, \npixel data generation and layer configuration. The LCD_CLK output should be \nconfigured following the panel requirements. The LCD_CLK is configured through the \nPLLSAI (refer to RCC section). \nTable 89 summarizes the clock domain for each register. \nMSv19675V1\nLCD-TFT\npanel\nLCD_HSYNC\nLCD_VSYNC\nLCD_DE\nLCD_CLK\nLCD_R[7:0]\nLCD_G[7:0]\nLCD_B[7:0]\nPixel clock domain\nDithering \nunit\nBlending \nunit\nPFC\nPFC\nLayer1 \nFIFO\nLayer1 \nFIFO\nAHB \ninterface\nTiming \ngenerator\nConfiguration \nand status \nregisters\nAHB clock domain\nAPB2 clock domain\nInterrupts\n\n\n<>\n\nRM0090 Rev 21\n485/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n \nCare must be taken when accessing the LTDC registers since the APB2 bus is stalling when \nthe following operations are ongoing:\n•\nRegister write access and update for 6 xPCKL2 period + 5x LCD_CLK period (5x \nHCLK period for register on AHB clock domain)\n•\nRegister read access for 7xPCKL2 period + 5x LCD_CLK period (5x HCLK period for \nregister on AHB clock domain).\nFor registers on PCLK2 clock domain, APB2 bus is stalling during the register write access \nfor 6 xPCKL2 period and 7xPCKL2 period for read access. \nThe LCD controller can be reset by setting the corresponding bit in the RCC_APB2RSTR \nregister. It resets the three clock domains.\nTable 89. LTDC registers versus clock domain\nLTDC registers\nClock domain\nLTDC_LxCR\nHCLK\nLTDC_LxCFBAR\nLTDC_LxCFBLR\nLTDC_LxCFBLNR\nLTDC_SRCR\nPCLK2\nLTDC_IER\nLTDC_ISR\nLTDC_ICR\nLTDC_SSCR\nPixel Clock (LCD_CLK)\nLTDC_BPCR\nLTDC_AWCR\nLTDC_TWCR\nLTDC_GCR\nLTDC_BCCR\nLTDC_LIPCR\nLTDC_CPSR\nLTDC_CDSR\nLTDC_LxWHPCR\nLTDC_LxWVPCR\nLTDC_LxCKCR\nLTDC_LxPFCR\nLTDC_LxCACR\nLTDC_LxDCCR\nLTDC_LxBFCR\nLTDC_LxCLUTWR\n\n\n<>\n\nLCD-TFT controller (LTDC)\nRM0090\n486/1757\nRM0090 Rev 21\n16.3.3 \nLCD-TFT pins and signal interface\nThe Table below summarizes the LTDC signal interface: \n \nThe LCD-TFT controller pins must be configured by the user application. The unused pins \ncan be used for other purposes. \nFor LTDC outputs up to 24-bit (RGB888), if less than 8bpp are used to output for example \nRGB565 or RGB666 to interface on 16b-bit or 18-bit displays, the RGB display data lines \nmust be connected to the MSB of the LCD-TFT controller RGB data lines. As an example, in \nthe case of an LCD-TFT controller interfacing with a RGB565 16-bit display, the LCD display \nR[4:0], G[5:0] and B[4:0] data lines pins must be connected to LCD-TFT controller \nLCD_R[7:3], LCD_G[7:2] and LCD_B[7:3].\n16.4 \nLTDC programmable parameters\nThe LCD-TFT controller provides flexible configurable parameters. It can be enabled or \ndisabled through the LTDC_GCR register.\n16.4.1 \nLTDC Global configuration parameters\nSynchronous Timings:\nFigure 82 presents the configurable timing parameters generated by the Synchronous \nTimings Generator block presented in the block diagram Figure 81. It generates the \nHorizontal and Vertical Synchronization timings panel signals, the Pixel Clock and the Data \nEnable signals.\nTable 90. LCD-TFT pins and signal interface\nLCD-TFT \nsignals \nI/O \nDescription\nLCD_CLK\nO\nClock Output\nLCD_HSYNC\nO\nHorizontal Synchronization\nLCD_VSYNC\nO\nVertical Synchronization\nLCD_DE\nO\nNot Data Enable\nLCD_R[7:0]\nO\nData: 8-bit Red data\nLCD_G[7:0]\nO\nData: 8-bit Green data\nLCD_B[7:0]\nO\nData: 8-bit Blue data\n\n\n<>\n\nRM0090 Rev 21\n487/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\nFigure 82. LCD-TFT Synchronous timings\nNote:\nThe HBP and HFP are respectively the Horizontal back porch and front porch period.\nThe VBP and the VFP are respectively the Vertical back porch and front porch period.\nThe LCD-TFT programmable synchronous timings are: \n–\nHSYNC and VSYNC Width: Horizontal and Vertical Synchronization width \nconfigured by programming a value of HSYNC Width - 1 and VSYNC Width - 1 in \nthe LTDC_SSCR register.\n–\nHBP and VBP: Horizontal and Vertical Synchronization back porch width \nconfigured by programming the accumulated value HSYNC Width + HBP - 1 and \nthe accumulated value VSYNC Width + VBP - 1 in the LTDC_BPCR register.\n–\nActive Width and Active Height: The Active Width and Active Height are \nconfigured by programming the accumulated value HSYNC Width + HBP + \nActive Width - 1 and the accumulated value VSYNC Width + VBP + Active \nHeight - 1 in the LTDC_AWCR register (only up to 1024x768 is supported).\n–\nTotal Width: The Total width is configured by programming the accumulated value \nHSYNC Width + HBP + Active Width + HFP - 1 in the LTDC_TWCR register. The \nHFP is the Horizontal front porch period.\n–\nTotal Height: The Total Height is configured by programming the accumulated \nvalue VSYNC Height + VBP + Active Height + VFP - 1 in the LTDC_TWCR \nregister. The VFP is the Vertical front porch period.\nNote:\nWhen the LTDC is enabled, the timings generated start with X/Y=0/0 position as the first \nhorizontal synchronization pixel in the vertical synchronization area and following the back \nporch, active data display area and the front porch.\nMSv19674V1\nTotal width\nActive width\nHFP\nHBP\nHSYNC\n width\nVSYNC width\nVBP\nVFP\nActive height\nTotal height\nActive display area\nData1, Line1\nData(n), Line(n)\n\n\n<>\n\nLCD-TFT controller (LTDC)\nRM0090\n488/1757\nRM0090 Rev 21\nWhen the LTDC is disabled, the timing generator block is reset to X=Total Width - 1, \nY=Total Height - 1 and held the last pixel before the vertical synchronization phase and the \nFIFO are flushed. Therefore only blanking data is output continuously.\nExample of Synchronous timings configuration\nTFT-LCD timings (should be extracted from Panel datasheet):\n•\nHorizontal and Vertical Synchronization width: 0x8 pixels and 0x4 lines\n•\nHorizontal and Vertical back porch: 0x7 pixels and 0x2 lines\n•\nActive Width and Active Height: 0x280 pixels, 0x1E0 lines (640x480)\n•\nHorizontal front porch: 0x6 pixels\n•\nVertical front porch: 0x2 lines\nThe programmed values in the LTDC timings registers are:\n•\nLTDC_SSCR register: to be programmed to 0x00070003. (HSW[11:0] is 0x7 and \nVSH[10:0] is 0x3)\n•\nLTDC_BPCR register: to be programmed to 0x000E0005. (AHBP[11:0] is 0xE(0x8 + \n0x6) and AVBP[10:0] is 0x5(0x4 + 0x1)) \n•\nLTDC_AWCR register: to be programmed to 0x028E01E5. (AAW[11:0] is 0x28E(0x8 \n+0x7 +0x27F) and AAH[10:0] is 0x1E5(0x4 +0x2 + 0x1DF)\n•\nLTDC_TWCR register: to be programmed to 0x00000294. (TOTALW[11:0] is \n0x294(0x8 +0x7 +0x280 + 0x5)\n•\nLTDC_THCR register: to be programmed to 0x000001E7. (TOTALH[10:0] is \n0x1E7(0x4 +0x2 + 0x1E0 + 1)\nProgrammable polarity\nThe Horizontal and Vertical Synchronization, Data Enable and Pixel Clock output signals \npolarity can be programmed to active high or active low through the LTDC_GCR register.\nBackground Color \nA constant background color (RGB888) can programmed through the LTDC_BCCR \nregister. It is used for blending with the bottom layer.\nDithering\nThe Dithering pseudo-random technique using an LFSR is used to add a small random \nvalue (threshold) to each pixel color channel (R, G or B) value, thus rounding up the MSB in \nsome cases when displaying a 24-bit data on 18-bit display. Thus the Dithering technique is \nused to round data which is different from one frame to the other.\nThe Dither pseudo-random technique is the same as comparing LSBs against a threshold \nvalue and adding a 1 to the MSB part only, if the LSB part is >= the threshold. The LSBs are \ntypically dropped once dithering was applied.\nThe width of the added pseudo-random value is 2 bits for each color channel; 2 bits for Red, \n2 bits for Green and 2 bits for Blue.\nOnce the LCD-TFT controller is enabled, the LFSR starts running with the first active pixel \nand it is kept running even during blanking periods and when dithering is switched off. If the \nLTDC is disabled, the LFSR is reset.\nThe Dithering can be switched On and Off on the fly through the LTDC_GCR register.\n\n\n<>\n\nRM0090 Rev 21\n489/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\nReload Shadow registers\nSome configuration registers are shadowed. The shadow registers values can be reloaded \nimmediately to the active registers when writing to these registers or at the beginning of the \nvertical blanking period following the configuration in the LTDC_SRCR register. If the \nimmediate reload configuration is selected, the reload should be only activated when all new \nregisters have been written.\nThe shadow registers should not be modified again before the reload has been done. \nReading from the shadow registers returns the actual active value. The new written value \ncan only be read after the reload has taken place. \nA register reload interrupt can be generated if enabled in the LTDC_IER register. \nThe shadowed registers are all the Layer 1 and Layer 2 registers except the \nLTDC_LxCLUTWR register.\nInterrupt generation event\nRefer to Section 16.5: LTDC interrupts for interrupt configuration. \n16.4.2 \nLayer programmable parameters\nUp to two layers can be enabled, disabled and configured separately. The layer display \norder is fixed and it is bottom up. If two layers are enabled, the Layer2 is the top displayed \nwindow. \nWindowing\nEvery layer can be positioned and resized and it must be inside the Active Display area.\nThe window position and size are configured through the top-left and bottom-right X/Y \npositions and the Internal timing generator which includes the synchronous, back porch size \nand the active data area. Refer to LTDC_LxWHPCR and LTDC_WVPCR registers.\nThe programmable layer position and size defines the first/last visible pixel of a line and the \nfirst/last visible line in the window. It allows to display either the full image frame or only a \npart of the image frame. Refer to Figure 83\n•\nThe first and the last visible pixel in the layer are set by configuring the WHSTPOS[11:0] \nand WHSPPOS[11:0] in the LTDC_LxWHPCR register.\n•\nThe first and the last visible lines in the layer are set by configuring the WVSTPOS[10:0] \nand WVSPPOS[10:0] in the LTDC_LxWVPCR register.\n\n\n<>\n\nLCD-TFT controller (LTDC)\nRM0090\n490/1757\nRM0090 Rev 21\nFigure 83. Layer window programmable parameters:\nPixel input Format\nThe programmable pixel format is used for the data stored in the frame buffer of a layer.\nUp to 8 input pixel formats can be configured for every layer through the LTDC_LxPFCR \nregister \nThe pixel data is read from the frame buffer and then transformed to the internal 8888 \n(ARGB) format as follows:\n•\nComponents which have a width of less than 8 bits get expanded to 8 bits by bit \nreplication. The selected bit range is concatenated multiple times until it is longer than \n8 bits. Of the resulting vector, the 8 MSB bits are chosen. Example: 5 bits of an \nRGB565 red channel become (bit positions): 43210432 (the 3 LSBs are filled with the 3 \nMSBs of the 5 bits)\nThe figure below describes the pixel data mapping depending on the selected format.\nTable 91. Pixel Data mapping versus Color Format\nARGB8888\n@+3\nAx[7:0]\n@+2\nRx[7:0]\n@+1\nGx[7:0]\n@\nBx[7:0]\n@+7\nAx+1[7:0]\n@+6\nRx+1[7:0]\n@+5\nGx+1[7:0]\n@+4\nBx+1[7:0]\nRGB888\n@+3\nBx+1[7:0]\n@+2\nRx[7:0]\n@+1\nGx[7:0]\n@\nBx[7:0]\n@+7\nGx+2[7:0]\n@+6\nBx+2[7:0]\n@+5\nRx+1[7:0]\n@+4\nGx+1[7:0]\nRGB565\n@+3\nRx+1[4:0] Gx+1[5:3]\n@+2\nGx+1[2:0] Bx+1[4:0]\n@+1\nRx[4:0] Gx[5:3]\n@\nGx[2:0] Bx[4:0]\nMSv19676V3\nActive data area\nWVSPPOS bits in \nLTDC_LxWVPCR\nWindow\nWHSPPOS bits in \nLTDC_LxWHPCR\nWHSTPOS bits in \nLTDC_LxWHPCR\nWVSTPOS bits in \nLTDC_LxWVPCR\n\n\n<>\n\nRM0090 Rev 21\n491/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\nColor Look-Up Table (CLUT)\nThe CLUT can be enabled at run-time for every layer through the LTDC_LxCR register and \nit is only useful in case of indexed color when using the L8, AL44 and AL88 input pixel \nformat. \nFirst, the CLUT has to be loaded with the R, G and B values that replace the original R, G, B \nvalues of that pixel (indexed color). Each color (RGB value) has its own address which is the \nposition within the CLUT.\n@+7\nRx+3[4:0] Gx+3[5:3]\n@+6\nGx+3[2:0] Bx+3[4:0]\n@+5\nRx+2[4:0] Gx+2[5:3]\n@+4\nGx+2[2:0] Bx+2[4:0]\nARGB1555\n@+3\nAx+1[0]Rx+1[4:0]\nGx+1[4:3]\n@+2\nGx+1[2:0] Bx+1[4:0]\n@+1\nAx[0] Rx[4:0] Gx[4:3]\n@\nGx[2:0] Bx[4:0]\n@+7\nAx+3[0]Rx+3[4:0]\nGx+3[4:3]\n@+6\nGx+3[2:0] Bx+3[4:0]\n@+5\nAx+2[0]Rx+2[4:0]Gx+2[4:\n3]\n@+4\nGx+2[2:0] Bx+2[4:0]\nARGB4444\n@+3\nAx+1[3:0]Rx+1[3:0]\n@+2\nGx+1[3:0] Bx+1[3:0]\n@+1\nAx[3:0] Rx[3:0]\n@\nGx[3:0] Bx[3:0]\n@+7\nAx+3[3:0]Rx+3[3:0]\n@+6\nGx+3[3:0] Bx+3[3:0]\n@+5\nAx+2[3:0]Rx+2[3:0]\n@+4\nGx+2[3:0] Bx+2[3:0]\nL8\n@+3\nLx+3[7:0]\n@+2\nLx+2[7:0]\n@+1\nLx+1[7:0]\n@\nLx[7:0]\n@+7\nLx+7[7:0]\n@+6\nLx+6[7:0]\n@+5\nLx+5[7:0]\n@+4\nLx+4[7:0]\nAL44\n@+3\nAx+3[3:0] Lx+3[3:0]\n@+2\nAx+2[3:0] Lx+2[3:0]\n@+1\nAx+1[3:0] Lx+1[3:0]\n@\nAx[3:0] Lx[3:0]\n@+7\nAx+7[3:0] Lx+7[3:0]\n@+6\nAx+6[3:0] Lx+6[3:0]\n@+5\nAx+5[3:0] Lx+5[3:0]\n@+4\nAx+4[3:0] Lx+4[3:0]\nAL88\n@+3\nAx+1[7:0]\n@+2\nLx+1[7:0]\n@+1\nAx[7:0]\n@\nLx[7:0]\n@+7\nAx+3[7:0]\n@+6\nLx+3[7:0]\n@+5\nAx+2[7:0]\n@+4\nLx+2[7:0]\nTable 91. Pixel Data mapping versus Color Format (continued)\nARGB8888\n\n\n<>\n\nLCD-TFT controller (LTDC)\nRM0090\n492/1757\nRM0090 Rev 21\nThe R, G and B values and their own respective address are programmed through the \nLTDC_LxCLUTWR register.\n•\nIn case of L8 and AL88 input pixel format, the CLUT has to be loaded by 256 colors. The \naddress of each color is configured in the CLUTADD bits in the LTDC_LxCLUTWR \nregister.\n•\nIn case of AL44 input pixel format, the CLUT has to be only loaded by 16 colors. The \naddress of each color must be filled by replicating the 4-bit L channel to 8-bit as follows:\n–\nL0 (indexed color 0), at address 0x00\n–\nL1, at address 0x11\n–\nL2, at address 0x22\n–\n.....\n–\nL15, at address 0xFF\nColor Frame Buffer Address\nEvery Layer has a start address for the color frame buffer configured through the \nLTDC_LxCFBAR register.\nWhen a layer is enabled, the data is fetched from the Color Frame Buffer.\nColor Frame Buffer Length\nEvery layer has a total line length setting for the color frame buffer in bytes and a number of \nlines in the frame buffer configurable in the LTDC_LxCFBLR and LTDC_LxCFBLNR \nregister respectively.\nThe line length and the number of lines settings are used to stop the prefetching of data to \nthe layer FIFO at the end of the frame buffer.\n•\nIf it is set to less bytes than required, a FIFO underrun interrupt is generated if it has \nbeen previously enabled.\n•\nIf it is set to more bytes than actually required, the useless data read from the FIFO is \ndiscarded. The useless data is not displayed.\nColor Frame Buffer Pitch\nEvery layer has a configurable pitch for the color frame buffer, which is the distance between \nthe start of one line and the beginning of the next line in bytes. It is configured through the \nLTDC_LxCFBLR register.\nLayer Blending\nThe blending is always active and the two layers can be blended following the blending \nfactors configured through the LTDC_LxBFCR register.\nThe blending order is fixed and it is bottom up. If two layers are enabled, first the Layer1 is \nblended with the Background color, then the Layer2 is blended with the result of blended \ncolor of Layer1 and the background. Refer to Figure 84.\n\n\n<>\n\nRM0090 Rev 21\n493/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\nFigure 84. Blending two layers with background\nDefault color\nEvery layer can have a default color in the format ARGB which is used outside the defined \nlayer window or when a layer is disabled.\nThe default color is configured through the LTDC_LxDCCR register.\nThe blending is always performed between the two layers even when a layer is disabled. To \navoid displaying the default color when a layer is disabled, keep the blending factors of this \nlayer in the LTDC_LxBFCR register to their reset value.\nColor Keying\nA color key (RGB) can be configured to be representative for a transparent pixel.\nIf the Color Keying is enabled, the current pixels (after format conversion and before \nblending) are compared to the color key. If they match for the programmed RGB value, all \nchannels (ARGB) of that pixel are set to 0.\nThe Color Key value can be configured and used at run-time to replace the pixel RGB value.\nThe Color Keying is enabled through the LTDC_LxCKCR register.\n16.5 \nLTDC interrupts\nThe LTDC provides four maskable interrupts logically ORed to two interrupt vectors.\nThe interrupt sources can be enabled or disabled separately through the LTDC_IER \nregister. Setting the appropriate mask bit to 1 enables the corresponding interrupt.\nThe two interrupts are generated on the following events:\n•\nLine interrupt: generated when a programmed line is reached. The line interrupt \nposition is programmed in the LTDC_LIPCR register\n•\nRegister Reload interrupt: generated when the shadow registers reload was performed \nduring the vertical blanking period\n•\nFIFO Underrun interrupt: generated when a pixel is requested from an empty layer \nFIFO\n•\nTransfer Error interrupt: generated when an AHB bus error occurs during data transfer \nThose interrupts events are connected to the NVIC controller as described in the figure \nbelow.\nMS19677V1\nLayer 2\nLayer 1\nBG\nLayer 2\nLayer 1 + BG\nLayer 2 +\nLayer 1 + BG\n\n\n<>\n\nLCD-TFT controller (LTDC)\nRM0090\n494/1757\nRM0090 Rev 21\nFigure 85. Interrupt events\n \nTable 92. LTDC interrupt requests\nInterrupt event\nEvent flag\nEnable Control bit\nLine \nLIF\nLIE\nRegister Reload \nRRIF\nRRIEN\nFIFO Underrun\nFUDERRIF\nFUDERRIE\nTransfer Error \nTERRIF\nTERRIE\nLine\nRegister reload\nLTDC global interrupt\nMS19678V1\nFIFO underrun\nTransfer error\nLTDC global error interrupt\n\n\n<>\n\nRM0090 Rev 21\n495/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.6 \nLTDC programming procedure\n•\nEnable the LTDC clock in the RCC register\n•\nConfigure the required Pixel clock following the panel datasheet\n•\nConfigure the Synchronous timings: VSYNC, HSYNC, Vertical and Horizontal back \nporch, active data area and the front porch timings following the panel datasheet as \ndescribed in the Section 16.4.1: LTDC Global configuration parameters\n•\nConfigure the synchronous signals and clock polarity in the LTDC_GCR register\n•\nIf needed, configure the background color in the LTDC_BCCR register\n•\nConfigure the needed interrupts in the LTDC_IER and LTDC_LIPCR register\n•\nConfigure the Layer1/2 parameters by programming:\n–\nThe Layer window horizontal and vertical position in the LTDC_LxWHPCR and \nLTDC_WVPCR registers. The layer window must be in the active data area.\n–\nThe pixel input format in the LTDC_LxPFCR register\n–\nThe color frame buffer start address in the LTDC_LxCFBAR register\n–\nThe line length and pitch of the color frame buffer in the LTDC_LxCFBLR register\n–\nThe number of lines of the color frame buffer in the LTDC_LxCFBLNR register\n–\nif needed, load the CLUT with the RGB values and its address in the \nLTDC_LxCLUTWR register\n–\nIf needed, configure the default color and the blending factors respectively in the \nLTDC_LxDCCR and LTDC_LxBFCR registers\n•\nEnable Layer1/2 and if needed the CLUT in the LTDC_LxCR register\n•\nIf needed, dithering and color keying can be enabled respectively in the LTDC_GCR \nand LTDC_LxCKCR registers. It can be also enabled on the fly.\n•\nReload the shadow registers to active register through the LTDC_SRCR register.\n•\nEnable the LCD-TFT controller in the LTDC_GCR register.\n•\nAll layer parameters can be modified on the fly except the CLUT. The new configuration \nhas to be either reloaded immediately or during vertical blanking period by configuring \nthe LTDC_SRCR register.\nNote:\nAll layer’s registers are shadowed. Once a register is written, it should not be modified again \nbefore the reload has been done. Thus, a new write to the same register overrides the \nprevious configuration if not yet reloaded.\n\n\n<>\n\nLCD-TFT controller (LTDC)\nRM0090\n496/1757\nRM0090 Rev 21\n16.7 \nLTDC registers\n16.7.1 \nLTDC Synchronization Size Configuration Register (LTDC_SSCR)\nThis register defines the number of Horizontal Synchronization pixels minus 1 and the \nnumber of Vertical Synchronization lines minus 1. Refer to Figure 82 and Section 16.4: \nLTDC programmable parameters for an example of configuration.\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n16.7.2 \nLTDC Back Porch Configuration Register (LTDC_BPCR)\nThis register defines the accumulated number of Horizontal Synchronization and back porch \npixels minus 1 (HSYNC Width + HBP- 1) and the accumulated number of Vertical \nSynchronization and back porch lines minus 1 (VSYNC Height + VBP - 1). Refer to \nFigure 82 and Section 16.4: LTDC programmable parameters for an example of \nconfiguration.\nAddress offset: 0x0C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nHSW[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nVSH[10:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value\nBits 27:16 HSW[11:0]: Horizontal Synchronization Width (in units of pixel clock period)\nThese bits define the number of Horizontal Synchronization pixel minus 1.\nBits 15:11 Reserved, must be kept at reset value\nBits 10:0 VSH[10:0]: Vertical Synchronization Height (in units of horizontal scan line)\nThese bits define the vertical Synchronization height minus 1. It represents the \nnumber\nof horizontal synchronization lines.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nAHBP[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nAVBP[10:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n497/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.7.3 \nLTDC Active Width Configuration Register (LTDC_AWCR)\nThis register defines the accumulated number of Horizontal Synchronization, back porch \nand Active pixels minus 1 (HSYNC width + HBP + Active Width - 1) and the accumulated \nnumber of Vertical Synchronization, back porch lines and Active lines minus 1 (VSYNC \nHeight+ BVBP + Active Height - 1). Refer to Figure 82 and Section 16.4: LTDC \nprogrammable parameters for an example of configuration.\nAddress offset: 0x10\nReset value: 0x0000 0000\nBits 31:28 Reserved, must be kept at reset value\nBits 27:16 AHBP[11:0]: Accumulated Horizontal back porch (in units of pixel clock period)\nThese bits define the Accumulated Horizontal back porch width which includes the \nHorizontal Synchronization and Horizontal back porch pixels minus 1.\nThe Horizontal back porch is the period between Horizontal Synchronization going \ninactive and the start of the active display part of the next scan line.\nBits 15:11 Reserved, must be kept at reset value\nBits 10:0 AVBP[10:0]: Accumulated Vertical back porch (in units of horizontal scan line)\nThese bits define the accumulated Vertical back porch width which includes the Vertical \nSynchronization and Vertical back porch lines minus 1.\nThe Vertical back porch is the number of horizontal scan lines at a start of frame to the \nstart of the first active scan line of the next frame.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nAAW[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nAAH[10:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value\nBits 27:16 AAW[11:0]: Accumulated Active Width (in units of pixel clock period)\nThese bits define the Accumulated Active Width which includes the Horizontal \nSynchronization, Horizontal back porch and Active pixels minus 1.\nThe Active Width is the number of pixels in active display area of the panel scan line. The \nmaximum Active Width supported is 0x400.\nBits 15:11 Reserved, must be kept at reset value\nBits 10:0 AAH[10:0]: Accumulated Active Height (in units of horizontal scan line)\nThese bits define the Accumulated Height which includes the Vertical Synchronization, \nVertical back porch and the Active Height lines minus 1. The Active Height is the number \nof active lines in the panel. The maximum Active Height supported is 0x300.\n\n\n<>\n\nLCD-TFT controller (LTDC)\nRM0090\n498/1757\nRM0090 Rev 21\n16.7.4 \nLTDC Total Width Configuration Register (LTDC_TWCR)\nThis register defines the accumulated number of Horizontal Synchronization, back porch, \nActive and front porch pixels minus 1 (HSYNC Width + HBP + Active Width + HFP - 1) and \nthe accumulated number of Vertical Synchronization, back porch lines, Active and Front \nlines minus 1 (VSYNC Height+ BVBP + Active Height + VFP - 1). Refer to Figure 82 and \nSection 16.4: LTDC programmable parameters for an example of configuration.\nAddress offset: 0x14\nReset value: 0x0000 0000\n16.7.5 \nLTDC Global Control Register (LTDC_GCR)\nThis register defines the global configuration of the LCD-TFT controller. \nAddress offset: 0x18\nReset value: 0x0000 2220\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTOTALW[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n16\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTOTALH[10:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value\nBits 27:16 TOTALW[11:0]: Total Width (in units of pixel clock period)\nThese bits defines the accumulated Total Width which includes the Horizontal \nSynchronization, Horizontal back porch, Active Width and Horizontal front porch pixels \nminus 1.\nBits 15:11 Reserved, must be kept at reset value\nBits 10:0 TOTALH[10:0]: Total Height (in units of horizontal scan line)\nThese bits defines the accumulated Height which includes the Vertical Synchronization, \nVertical back porch, the Active Height and Vertical front porch Height lines minus 1.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nHSPOL\nVSPOL\nDEPOL PCPOL\nReserved\nDEN\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserve\nd\nDRW[2:0]\nReser\nved\nDGW[2:0]\nReser\nved\nDBW[2:0]\nReserved\nLTDCEN\nr\nr\nr\nr\nr\nr\nr\nr\nr\nrw\n\n\n<>\n\nRM0090 Rev 21\n499/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\nBit 31 HSPOL: Horizontal Synchronization Polarity\nThis bit is set and cleared by software.\n0: Horizontal Synchronization polarity is active low\n1: Horizontal Synchronization polarity is active high\nBit 30 VSPOL: Vertical Synchronization Polarity\nThis bit is set and cleared by software.\n0: Vertical Synchronization is active low \n1: Vertical Synchronization is active high\nBit 29 DEPOL: Data Enable Polarity\nThis bit is set and cleared by software.\n0: Data Enable polarity is active low\n1: Data Enable polarity is active high\nBit 28 PCPOL: Pixel Clock Polarity\nThis bit is set and cleared by software.\n0: input pixel clock\n1: inverted input pixel clock\nBits 27:17 Reserved, must be kept at reset value\nBit 16 DEN: Dither Enable \nThis bit is set and cleared by software.\n0: Dither disable\n1: Dither enable\nBit 15 Reserved, must be kept at reset value\nBits 14:12 DRW[2:0]: Dither Red Width \nThese bits return the Dither Red Bits \nBit 11 Reserved, must be kept at reset value\nBits 10:8 DGW[2:0]: Dither Green Width \nThese bits return the Dither Green Bits \nBit 7 Reserved, must be kept at reset value\nBits 6:4 DBW[2:0]: Dither Blue Width \nThese bits return the Dither Blue Bits \nBits 3:1 Reserved, must be kept at reset value\nBit 0 LTDCEN: LCD-TFT controller enable bit \nThis bit is set and cleared by software.\n0: LTDC disable\n1: LTDC enable\n\n\n<>\n\nLCD-TFT controller (LTDC)\nRM0090\n500/1757\nRM0090 Rev 21\n16.7.6 \nLTDC Shadow Reload Configuration Register (LTDC_SRCR)\nThis register allows to reload either immediately or during the vertical blanking period, the \nshadow registers values to the active registers. The shadow registers are all Layer1 and \nLayer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR.\nAddress offset: 0x24\nReset value: 0x0000 0000\nNote:\nThe shadow registers read back the active values. Until the reload has been done, the 'old' \nvalue is read.\n16.7.7 \nLTDC Background Color Configuration Register (LTDC_BCCR)\nThis register defines the background color (RGB888).\nAddress offset: 0x2C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nVBR\nIMR\nrw\nrw\nBits 31:2 Reserved, must be kept at reset value\nBit 1 VBR: Vertical Blanking Reload\nThis bit is set by software and cleared only by hardware after reload. (it cannot be cleared \nthrough register write once it is set) \n0: No effect\n1: The shadow registers are reloaded during the vertical blanking period (at the \nbeginning of the first line after the Active Display Area)\nBit 0 IMR: Immediate Reload\nThis bit is set by software and cleared only by hardware after reload.\n0: No effect\n1: The shadow registers are reloaded immediately\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nBCRED[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nBCGREEN[7:0]\nBCBLUE[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n501/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.7.8 \nLTDC Interrupt Enable Register (LTDC_IER)\nThis register determines which status flags generate an interrupt request by setting the \ncorresponding bit to 1.\nAddress offset: 0x34\nReset value: 0x0000 0000\nBits 31:24 Reserved, must be kept at reset value\nBits 23:16 BCRED[7:0]: Background Color Red value\nThese bits configure the background red value\nBits 15:8 BCGREEN[7:0]: Background Color Green value\nThese bits configure the background green value\nBits 7:0 BCBLUE[7:0]: Background Color Blue value\nThese bits configure the background blue value\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRRIE\nTERRIE\nFUIE\nLIE\nrw\nrw\nrw\nrw\nBits 31:4 Reserved, must be kept at reset value\nBit 3 RRIE: Register Reload interrupt enable\nThis bit is set and cleared by software\n0: Register Reload interrupt disable\n1: Register Reload interrupt enable\nBit 2 TERRIE: Transfer Error Interrupt Enable\nThis bit is set and cleared by software\n0: Transfer Error interrupt disable\n1: Transfer Error interrupt enable\nBit 1 FUIE: FIFO Underrun Interrupt Enable \nThis bit is set and cleared by software\n0: FIFO Underrun interrupt disable\n1: FIFO Underrun Interrupt enable\nBit 0 LIE: Line Interrupt Enable\nThis bit is set and cleared by software\n0: Line interrupt disable\n1: Line Interrupt enable\n\n\n<>\n\nLCD-TFT controller (LTDC)\nRM0090\n502/1757\nRM0090 Rev 21\n16.7.9 \nLTDC Interrupt Status Register (LTDC_ISR)\nThis register returns the interrupt status flag\nAddress offset: 0x38\nReset value: 0x0000 0000\n16.7.10 \nLTDC Interrupt Clear Register (LTDC_ICR)\nAddress offset: 0x3C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRRIF\nTERRIF\nFUIF\nLIF\nr\nr\nr\nr\nBits 31:24 Reserved, must be kept at reset value\nBit 3 RRIF: Register Reload Interrupt Flag\n0: No Register Reload interrupt generated\n1: Register Reload interrupt generated when a vertical blanking reload occurs (and the \nfirst line after the active area is reached)\nBit 2 TERRIF: Transfer Error interrupt flag\n0: No Transfer Error interrupt generated\n1: Transfer Error interrupt generated when a Bus error occurs\nBit 1 FUIF: FIFO Underrun Interrupt flag \n0: NO FIFO Underrun interrupt generated.\n1: A FIFO underrun interrupt is generated, if one of the layer FIFOs is empty and pixel \ndata is read from the FIFO\nBit 0 LIF: Line Interrupt flag\n0: No Line interrupt generated\n1: A Line interrupt is generated, when a programmed line is reached\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCRRIF\nCTERRIF\nCFUIF\nCLIF\nw\nw\nw\nw\n\n\n<>\n\nRM0090 Rev 21\n503/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.7.11 \nLTDC Line Interrupt Position Configuration Register (LTDC_LIPCR)\nThis register defines the position of the line interrupt. The line value to be programmed \ndepends on the timings parameters. Refer to Figure 82.\nAddress offset: 0x40\nReset value: 0x0000 0000\n16.7.12 \nLTDC Current Position Status Register (LTDC_CPSR)\nAddress offset: 0x44\nReset value: 0x0000 0000\nBits 31:24 Reserved, must be kept at reset value\nBit 3 CRRIF: Clears Register Reload Interrupt Flag \n0: No effect\n1: Clears the RRIF flag in the LTDC_ISR register\nBit 2 CTERRIF: Clears the Transfer Error Interrupt Flag \n0: No effect\n1: Clears the TERRIF flag in the LTDC_ISR register.\nBit 1 CFUIF: Clears the FIFO Underrun Interrupt flag \n0: No effect\n1: Clears the FUDERRIF flag in the LTDC_ISR register.\nBit 0 CLIF: Clears the Line Interrupt Flag \n0: No effect\n1: Clears the LIF flag in the LTDC_ISR register.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLIPOS[10:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:11 Reserved, must be kept at reset value\nBits 10:0 LIPOS[10:0]: Line Interrupt Position\nThese bits configure the line interrupt position\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCXPOS[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCYPOS{15;0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n\n\n<>\n\nLCD-TFT controller (LTDC)\nRM0090\n504/1757\nRM0090 Rev 21\n16.7.13 \nLTDC Current Display Status Register (LTDC_CDSR)\nThis register returns the status of the current display phase which is controlled by the \nHSYNC, VSYNC, and Horizontal/Vertical DE signals.\nExample: if the current display phase is the vertical synchronization, the VSYNCS bit is set \n(active high). If the current display phase is the horizontal synchronization, the HSYNCS bit \nis active high.\nAddress offset: 0x48\nReset value: 0x0000 000F\nNote:\nThe returned status does not depend on the configured polarity in the LTDC_GCR register, \ninstead it returns the current active display phase.\nBits 31:16: CXPOS[15:0]: Current X Position \nThese bits return the current X position \nBits 15:0 CYPOS[15:0]: Current Y Position \nThese bits return the current Y position\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nHSYNC\nS\nVSYNC\nS\nHDES\nVDES\nr\nr\nr\nr\nBits 31:24 Reserved, must be kept at reset value\nBit 3 HSYNCS: Horizontal Synchronization display Status\n0: Active low \n1: Active high\nBit 2 VSYNCS: Vertical Synchronization display Status\n0: Active low \n1: Active high\nBit 1 HDES: Horizontal Data Enable display Status\n0: Active low \n1: Active high\nBit 0 VDES: Vertical Data Enable display Status\n0: Active low \n1: Active high\n\n\n<>\n\nRM0090 Rev 21\n505/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.7.14 \nLTDC Layerx Control Register (LTDC_LxCR) (where x=1..2) \nAddress offset: 0x84 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCLUTEN\nReserved\nCOLKEN\nLEN\nrw\nrw\nrw\nBits 31:5 Reserved, must be kept at reset value\nBit 4 CLUTEN: Color Look-Up Table Enable\nThis bit is set and cleared by software.\n0: Color Look-Up Table disable\n1: Color Look-Up Table enable\nThe CLUT is only meaningful for L8, AL44 and AL88 pixel format. Refer to Color Look-Up \nTable (CLUT) on page 491\nBit 3 Reserved, must be kept at reset value\nBit 2 Reserved, must be kept at reset value\nBit 1 COLKEN: Color Keying Enable\nThis bit is set and cleared by software.\n0: Color Keying disable\n1: Color Keying enable\nBit 0 LEN: Layer Enable\nThis bit is set and cleared by software.\n0: Layer disable\n1: Layer enable\n\n\n<>\n\nLCD-TFT controller (LTDC)\nRM0090\n506/1757\nRM0090 Rev 21\n16.7.15 \nLTDC Layerx Window Horizontal Position Configuration Register\n(LTDC_LxWHPCR) (where x=1..2)\nThis register defines the Horizontal Position (first and last pixel) of the layer 1 or 2 window.\nThe first visible pixel of a line is the programmed value of AHBP[10:0] bits + 1 in the \nLTDC_BPCR register.\nThe last visible pixel of a line is the programmed value of AAW[10:0] bits in the \nLTDC_AWCR register. \nAddress offset: 0x88 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\n \nExample: \nThe LTDC_BPCR register is configured to 0x000E0005(AHBP[11:0] is 0xE) and the \nLTDC_AWCR register is configured to 0x028E01E5(AAW[11:0] is 0x28E). To configure the \nhorizontal position of a window size of 630x460, with horizontal start offset of 5 pixels in the \nActive data area.\n1.\nLayer window first pixel: WHSTPOS[11:0] should be programmed to 0x14 (0xE+1+0x5)\n2. \nLayer window last pixel: WHSPPOS[11:0] should be programmed to 0x28A\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nWHSPPOS[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nWHSTPOS[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value\nBits 27:16 WHSPPOS[11:0]: Window Horizontal Stop Position\nThese bits configure the last visible pixel of a line of the layer window.\nThe following condition must be respected: \nWHSPPOS[11:0] ≥ AHBP[10:0] bits + 1 (programmed in LTDC_BPCR register)\nBits 15:12 Reserved, must be kept at reset value\nBits 11:0 WHSTPOS[11:0]: Window Horizontal Start Position\nThese bits configure the first visible pixel of a line of the layer window.\nThe following condition must be respected: \nWHSTPOS[11:0] must be ≤ AAW[10:0] bits (programmed in the LTDC_AWCR \nregister).\n\n\n<>\n\nRM0090 Rev 21\n507/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.7.16 \nLTDC Layerx Window Vertical Position Configuration Register\n(LTDC_LxWVPCR) (where x=1..2)\nThis register defines the vertical position (first and last line) of the layer1 or 2 window. \nThe first visible line of a frame is the programmed value of AVBP[10:0] bits + 1 in the \nregister LTDC_BPCR register. \nThe last visible line of a frame is the programmed value of AAH[10:0] bits in the \nLTDC_AWCR register.\nAddress offset: 0x8C + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\nExample:\nThe LTDC_BPCR register is configured to 0x000E0005 (AVBP[10:0] is 0x5) and the \nLTDC_AWCR register is configured to 0x028E01E5 (AAH[10:0] is 0x1E5). To configure the \nvertical position of a window size of 630x460, with vertical start offset of 8 lines in the Active \ndata area:\n1.\nLayer window first line: WVSTPOS[10:0] should be programmed to 0xE (0x5 + 1 + 0x8)\n2. \nLayer window last line: WVSPPOS[10:0] should be programmed to 0x1DA\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nWVSPPOS[10:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nWVSTPOS[10:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:27 Reserved, must be kept at reset value\nBits 26:16 WVSPPOS[10:0]: Window Vertical Stop Position\nThese bits configures the last visible line of the layer window. \nThe following condition must be respected: \nWHSPPOS[11:0] must be ≥ AVBP[10:0] bits + 1 (programmed in LTDC_BPCR \nregister)\nBits 15:11 Reserved, must be kept at reset value\nBits 10:0 WVSTPOS[10:0]: Window Vertical Start Position\nThese bits configure the first visible line of the layer window.\nThe following condition must be respected: \nWHSTPOS[11:0] must be ≤ AAH[10:0] bits (programmed in the LTDC_AWCR register) \n\n\n<>\n\nLCD-TFT controller (LTDC)\nRM0090\n508/1757\nRM0090 Rev 21\n16.7.17 \nLTDC Layerx Color Keying Configuration Register (LTDC_LxCKCR)\n(where x=1..2)\nThis register defines the color key value (RGB), which is used by the Color Keying.\nAddress offset: 0x90 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\n16.7.18 \nLTDC Layerx Pixel Format Configuration Register (LTDC_LxPFCR)\n(where x=1..2)\nThis register defines the pixel format which is used for the stored data in the frame buffer of \na layer. The pixel data is read from the frame buffer and then transformed to the internal \nformat 8888 (ARGB).\nAddress offset: 0x94 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nCKRED[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCKGREEN[7:0]\nCKBLUE[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value\nBits 23:16 CKRED[7:0]: Color Key Red value\nBits 15:8 CKGREEN[7:0]: Color Key Green value\nBits 7:0 CKBLUE[7:0]: Color Key Blue value \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPF[2:0]\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n509/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.7.19 \nLTDC Layerx Constant Alpha Configuration Register (LTDC_LxCACR)\n(where x=1..2)\nThis register defines the constant alpha value (divided by 255 by Hardware), which is used \nin the alpha blending. Refer to LTDC_LxBFCR register.\nAddress offset: 0x98 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: (Layerx -1) 0x0000 00FF\n16.7.20 \nLTDC Layerx Default Color Configuration Register (LTDC_LxDCCR)\n(where x=1..2)\nThis register defines the default color of a layer in the format ARGB. The default color is \nused outside the defined layer window or when a layer is disabled. The reset value of \n0x00000000 defines a transparent black color.\nAddress offset: 0x9C + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\nBits 31:3 Reserved, must be kept at reset value\nBits 2:0 PF[2:0]: Pixel Format \nThese bits configures the Pixel format\n000: ARGB8888\n001: RGB888\n010: RGB565\n011: ARGB1555\n100: ARGB4444\n101: L8 (8-Bit Luminance)\n110: AL44 (4-Bit Alpha, 4-Bit Luminance)\n111: AL88 (8-Bit Alpha, 8-Bit Luminance)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCONSTA[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value\nBits 7:0 CONSTA[7:0]: Constant Alpha\nThese bits configure the Constant Alpha used for blending. The Constant Alpha is divided \nby 255 by hardware.\nExample: if the programmed Constant Alpha is 0xFF, the Constant Alpha value is \n255/255=1\n\n\n<>\n\nLCD-TFT controller (LTDC)\nRM0090\n510/1757\nRM0090 Rev 21\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDCALPHA[7:0]\nDCRED[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDCGREEN[7:0]\nDCBLUE[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 DCALPHA[7:0]: Default Color Alpha\nThese bits configure the default alpha value\nBits 23:16 DCRED[7:0]: Default Color Red\nThese bits configure the default red value\nBits 15:8 DCGREEN[7:0]: Default Color Green\nThese bits configure the default green value\nBits 7:0 DCBLUE[7:0]: Default Color Blue \nThese bits configure the default blue value\n\n\n<>\n\nRM0090 Rev 21\n511/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.7.21 \nLTDC Layerx Blending Factors Configuration Register (LTDC_LxBFCR)\n(where x=1..2)\nThis register defines the blending factors F1 and F2.\nThe general blending formula is: BC = BF1 x C + BF2 x Cs\n•\nBC = Blended color\n•\nBF1 = Blend Factor 1\n•\nC = Current layer color\n•\nBF2 = Blend Factor 2\n•\nCs = subjacent layers blended color\nAddress offset: 0xA0 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0607\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBF1[2:0]\nReserved\nBF2[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:11 Reserved, must be kept at reset value\nBits 10:8 BF1[2:0]: Blending Factor 1\nThese bits select the blending factor F1\n000: Reserved\n001: Reserved\n010: Reserved\n011: Reserved\n100: Constant Alpha\n101: Reserved\n110: Pixel Alpha x Constant Alpha\n111:Reserved\nBits 7:3 Reserved, must be kept at reset value\nBits 2:0 BF2[2:0]: Blending Factor 2 \nThese bits select the blending factor F2\n000: Reserved\n001: Reserved\n010: Reserved\n011: Reserved\n100: Reserved\n101: 1 - Constant Alpha\n110: Reserved\n111: 1 - (Pixel Alpha x Constant Alpha)\n\n\n<>\n\nLCD-TFT controller (LTDC)\nRM0090\n512/1757\nRM0090 Rev 21\nNote:\nThe Constant Alpha value, is the programmed value in the LxCACR register divided by 255 \nby hardware.\nExample: Only layer1 is enabled, BF1 configured to Constant Alpha\nBF2 configured to 1 - Constant Alpha\nConstant Alpha: The Constant Alpha programmed in the LxCACR register is 240 (0xF0). \nThus, the Constant Alpha value is 240/255 = 0.94\nC: Current Layer Color is 128\nCs: Background color is 48\nLayer1 is blended with the background color. \nBC = Constant Alpha x C + (1 - Constant Alpha) x Cs = 0.94 x 128 + (1- 0.94) x 48 = 123.\n16.7.22 \nLTDC Layerx Color Frame Buffer Address Register (LTDC_LxCFBAR)\n(where x=1..2)\nThis register defines the color frame buffer start address which has to point to the address \nwhere the pixel data of the top left pixel of a layer is stored in the frame buffer.\nAddress offset: 0xAC + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\n16.7.23 \nLTDC Layerx Color Frame Buffer Length Register (LTDC_LxCFBLR)\n(where x=1..2)\nThis register defines the color frame buffer line length and pitch.\nAddress offset: 0xB0 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCFBADD[31:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCFBADD[31:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 CFBADD[31:0]: Color Frame Buffer Start Address\nThese bits defines the color frame buffer start address.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nCFBP[12:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCFBLL[12:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n513/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\nExample:\n•\nA frame buffer having the format RGB565 (2 bytes per pixel) and a width of 256 pixels \n(total number of bytes per line is 256x2=512 bytes), where pitch = line length requires a \nvalue of 0x02000203 to be written into this register.\n•\nA frame buffer having the format RGB888 (3 bytes per pixel) and a width of 320 pixels \n(total number of bytes per line is 320x3=960), where pitch = line length requires a value \nof 0x03C003C3 to be written into this register.\n16.7.24 \nLTDC Layerx ColorFrame Buffer Line Number Register\n(LTDC_LxCFBLNR) (where x=1..2)\nThis register defines the number of lines in the color frame buffer.\nAddress offset: 0xB4 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\nNote:\nThe number of lines and line length settings define how much data is fetched per frame for \nevery layer. If it is configured to less bytes than required, a FIFO underrun interrupt is \ngenerated if enabled.\nThe start address and pitch settings on the other hand define the correct start of every line in \nmemory.\nBits 31:29 Reserved, must be kept at reset valuer\nBits 28:16 CFBP[12:0]: Color Frame Buffer Pitch in bytes \nThese bits define the pitch which is the increment from the start of one line of pixels to the \nstart of the next line in bytes.\nBits 15:13 Reserved, must be kept at reset value\nBits 12:0 CFBLL[12:0]: Color Frame Buffer Line Length\nThese bits define the length of one line of pixels in bytes + 3.\nThe line length is computed as follows: Active high width x number of bytes per pixel + 3.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCFBLNBR[10:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:11 Reserved, must be kept at reset value\nBits 10:0 CFBLNBR[10:0]: Frame Buffer Line Number \nThese bits define the number of lines in the frame buffer which corresponds to the Active \nhigh width.\n\n\n<>\n\nLCD-TFT controller (LTDC)\nRM0090\n514/1757\nRM0090 Rev 21\n16.7.25 \nLTDC Layerx CLUT Write Register (LTDC_LxCLUTWR) \n(where x=1..2)\nThis register defines the CLUT address and the RGB value.\nAddress offset: 0xC4 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\n \nNote:\nThe CLUT write register should only be configured during blanking period or if the layer is \ndisabled. The CLUT can be enabled or disabled in the LTDC_LxCR register.\nThe CLUT is only meaningful for L8, AL44 and AL88 pixel format.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCLUTADD[7:0]\nRED[7:0]\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nGREEN[7:0]\nBLUE[7:0]\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBits 31:24 CLUTADD[7:0]: CLUT Address\nThese bits configure the CLUT address (color position within the CLUT) of each RGB \nvalue\nBits 23:16 RED[7:0]: Red value\nThese bits configure the red value\nBits 15:8 GREEN[7:0]: Green value\nThese bits configure the green value\nBits 7:0 BLUE[7:0]: Blue value\nThese bits configure the blue value\n\n\n<>\n\nRM0090 Rev 21\n515/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.7.26 \nLTDC register map\nThe following table summarizes the LTDC registers. Refer to the register boundary \naddresses table for the LTDC register base address.\n \nTable 93. LTDC register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x0008\nLTDC_SSCR\nReserved\nHSW[9:0]\nReserved\nVSH[10:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x000C\nLTDC_BPCR\nReserved\nAHBP[11:0]\nReserved\nAVBP[10:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0010\nLTDC_AWCR\nReserved\nAAV[11:0]\nReserved\nAAH[10:0]\nReset value\n0\n9\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0014\nLTDC_TWCR\nReserved\nTOTALW[11:0]\nReserved\nTOTALH[10:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0018\nLTDC_GCR\nHSPOL\nVSPOL\nDEPOL\nPCPOL\nReserve\nDEN\nReserved\nDRW[2:0]\nReserved\nDGW[2:0]\nReserved\nDBW[2:0]\nReserved\nLTDCEN\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n1\n0\n0\n1\n0\n0\n0x0024\nLTDC_SRCR\nReserved\nVBR\nIMR\nReset value\n0\n0\n0x002C\nLTDC_BCCR\nReserved\nBC[23:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0034\nLTDC_IER\nReserved\nRRIE\nTERRIE\nFUIE\nLIE\nReset value\n0\n0\n0\n0\n0x0038\nLTDC_ISR\nReserved\nRRIF\nTERRIF\nFUIF\nLIF\nReset value\n0\n0\n0\n0\n0x003C\nLTDC_ICR\nReserved\nCRRIF\nCTERRIF\nCFUIF\nCLIF\nReset value\n0\n0\n0\n0\n0x0040\nLTDC_LIPCR\nReserved\nLIPOS[10:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0044\nLTDC_CPSR\nCXPOS[15:0]\nCYPOS[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0048\nLTDC_CDSR\nReserved\nHSYNCS\nVSYNCS\nHDES\nVDES\nReset value\n1\n1\n1\n1\n0x0084\nLTDC_L1CR\nReserved\nCLUTEN\nReserved\nCOLKEN\nLEN\nReset value\n0\n0\n0\n0x0088\nLTDC_L1WHPCR\nReserved\nWHSPPOS[11:0]\nReserved\nWHSTPOS[11:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n\n\n<>\n\nLCD-TFT controller (LTDC)\nRM0090\n516/1757\nRM0090 Rev 21\n0x008C\nLTDC_L1WVPCR\nReserved\nWVSPPOS[10:0]\nReserved\nWVSTPOS[10:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0090\nLTDC_L1CKCR\nReserved\nCKRED[7:0]\nCKGREEN[7:0]\nCKBLUE[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0094\nLTDC_L1PFCR\nReserved\nPF[2:0]\nReset value\n0\n0\n0\n0x0098\nLTDC_L1CACR\nReserved\nCONSTA[7:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n0x009C\nLTDC_L1DCCR\nDCALPHA[7:0]\nDCRED[7:0]\nDCGREEN[7:0]\nDCBLUE[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00A0\nLTDC_L1BFCR\nReserved\nBF1[2:0]\nReserved\nBF2[2:0]\nReset value\n1\n1\n0\n1\n1\n1\n0x00AC\nLTDC_L1CFBAR\nCFBADD[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00B0\nLTDC_L1CFBLR\nReserved\nCFBP[12:0]\nReserved\nCFBLL[12:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00B4\nLTDC_L1CFBLNR\nReserved\nCFBLNBR[10:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00C4\nLTDC_L1CLUTWR\nCLUTADD[7:0]\nRED[7:0]\nGREEN[7:0]\nBLUE[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0104\nLTDC_L2CR\nReserved\nCLUTEN\nReserved\nCOLKEN\nLEN\nReset value\n0\n0\n0\n0x0108\nLTDC_L2WHPCR\nReserved\nWHSPPOS[11:0]\nReserved\nWHSTPOS[11:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x010C\nLTDC_L2WVPCR\nReserved\nWVSPPOS[10:0]\nReserved\nWVSTPOS[10:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0110\nLTDC_L2CKCR\nReserved\nCKRED[7:0]\nCKGREEN[7:0]\nCKBLUE[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0114\nLTDC_L2PFCR\nReserved\nPF[2:0]\nReset value\n0\n0\n0\n0x0118\nLTDC_L2CACR\nReserved\nCONSTA[7:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n0x011C\nLTDC_L2DCCR\nDCALPHA[7:0]\nDCRED[7:0]\nDCGREEN[7:0]\nDCBLUE[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0120\nLTDC_L2BFCR\nReserved\nBF1[2:0]\nReserved\nBF2[2:0]\nReset value\n1\n1\n0\n1\n1\n1\n0x012C\nLTDC_L2CFBAR\nCFBADD[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0130\nLTDC_L2CFBLR\nReserved\nCFBP[12:0]\nReserved\nCFBLL[12:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 93. LTDC register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n517/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n \n0x0134\nLTDC_L2CFBLNR\nReserved\nCFBLNBR[10:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0144\nLTDC_L2CLUTWR\nCLUTADD[7:0]\nRED[7:0]\nGREEN[7:0]\nBLUE[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 93. LTDC register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n518/1757\nRM0090 Rev 21\n17 \nAdvanced-control timers (TIM1 and TIM8)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n17.1 \nTIM1 and TIM8 introduction\nThe advanced-control timers (TIM1 and TIM8) consist of a 16-bit auto-reload counter driven \nby a programmable prescaler.\nIt may be used for a variety of purposes, including measuring the pulse lengths of input \nsignals (input capture) or generating output waveforms (output compare, PWM, \ncomplementary PWM with dead-time insertion).\nPulse lengths and waveform periods can be modulated from a few microseconds to several \nmilliseconds using the timer prescaler and the RCC clock controller prescalers.\nThe advanced-control (TIM1 and TIM8) and general-purpose (TIMx) timers are completely \nindependent, and do not share any resources. They can be synchronized together as \ndescribed in Section 17.3.20.\n\n\n<>\n\nRM0090 Rev 21\n519/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.2 \nTIM1 and TIM8 main features\nTIM1 and TIM8 timer features include:\n•\n16-bit up, down, up/down auto-reload counter.\n•\n16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock \nfrequency either by any factor between 1 and 65536.\n•\nUp to 4 independent channels for:\n–\nInput capture\n–\nOutput compare\n–\nPWM generation (Edge and Center-aligned mode)\n–\nOne-pulse mode output\n•\nComplementary outputs with programmable dead-time\n•\nSynchronization circuit to control the timer with external signals and to interconnect \nseveral timers together.\n•\nRepetition counter to update the timer registers only after a given number of cycles of \nthe counter.\n•\nBreak input to put the timer’s output signals in reset state or in a known state.\n•\nInterrupt/DMA generation on the following events:\n–\nUpdate: counter overflow/underflow, counter initialization (by software or \ninternal/external trigger)\n–\nTrigger event (counter start, stop, initialization or count by internal/external trigger)\n–\nInput capture\n–\nOutput compare\n–\nBreak input\n•\nSupports incremental (quadrature) encoder and hall-sensor circuitry for positioning \npurposes\n•\nTrigger input for external clock or cycle-by-cycle current management\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n520/1757\nRM0090 Rev 21\nFigure 86. Advanced-control timer block diagram\nMS39906V3\nInterrupt & DMA output\nEvent\nPolarity selection\nInput filter & \nEdge detector\nInput filter & \nEdge detector\nInput filter & \nEdge detector\nInput filter & \nEdge detector\nTRC\nTRC\nTRC\nTRC\nTI4FP4\nTI4FP3\nTI3FP4\nTI3FP3\nPrescaler\nIC3\nIC4\nIC2\nIC1\nPrescaler\nPrescaler\nPrescaler\nTI2FP2\nTI2FP1\nTI1FP1\nTI1FP2\nTI1\nTI2\nTI3\nTI4\nBRK\nClock failure event from clock controller\nCSS (Clock Security System)\nIC1PS\nIC2PS\nIC3PS\nIC4PS\nBI\nCapture/Compare \n4 Register\nU\nCapture/Compare \n3 Register\nU\nU\nCapture/Compare \n2 Register\nCapture/Compare \n1 Register\nU\nCC1I\nCC2I\nCC3I\nCC4I\nCC1I\nCC2I\nCC3I\nCC4I\nOC1REF\nOC2REF\nOC3REF\nOC4REF\nDTG\nDTG\nDTG\nOC4\nOC3N\nOC3\nOC2N\nOC2\nOC1N\nOC1\nDTG[7:0] registers\nCNT\n(counter)\nPSC\n(prescaler)\nCK_CNT\nCK_PSC\nRepetition counter\nREP Register\nUI\nPolarity selection,\nEdge detector and Prescaler\nInput filter\nTrigger \ncontroller\nSlave mode \ncontroller\nEncoder \ninterface\nReset, \nEnable, \nUp/Down, \nCount\nTo other timers\nTo DAC and ADC\nTRGO\nTRGI\nTGI\nInternal clock (CK_INT)\nETRF\nETRP\nETR\nCK_TIM18 from RCC\nTI1FP1\nTI2FP2\nTIMx_ETR\nTIMx_CH1\nTIMx_CH2\nTIMx_CH3\nTIMx_CH4\nTIMx_BKIN\nTIMx_CH1\nTIMx_CH1N\nTIMx_CH3\nTIMx_CH3N\nTIMx_CH2\nTIMx_CH4\nTIMx_CH2N\nU\nU\nOutput \ncontrol\nAutoReload \nRegister\nU\nITR0\nITR1\nITR2\nITR3\nTIF_ED\nOutput \ncontrol\nOutput \ncontrol\nOutput \ncontrol\nTRC\n\n\n<>\n\nRM0090 Rev 21\n521/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.3 \nTIM1 and TIM8 functional description\n17.3.1 \nTime-base unit\nThe main block of the programmable advanced-control timer is a 16-bit counter with its \nrelated auto-reload register. The counter can count up, down or both up and down. The \ncounter clock can be divided by a prescaler. \nThe counter, the auto-reload register and the prescaler register can be written or read by \nsoftware. This is true even when the counter is running.\nThe time-base unit includes:\n•\nCounter register (TIMx_CNT)\n•\nPrescaler register (TIMx_PSC)\n•\nAuto-reload register (TIMx_ARR)\n•\nRepetition counter register (TIMx_RCR)\nThe auto-reload register is preloaded. Writing to or reading from the auto-reload register \naccesses the preload register. The content of the preload register are transferred into the \nshadow register permanently or at each update event (UEV), depending on the auto-reload \npreload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter \nreaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the \nTIMx_CR1 register. It can also be generated by software. The generation of the update \nevent is described in detailed for each configuration.\nThe counter is clocked by the prescaler output CK_CNT, which is enabled only when the \ncounter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller \ndescription to get more details on counter enabling). \nNote that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 \nregister.\nPrescaler description\nThe prescaler can divide the counter clock frequency by any factor between 1 and 65536. It \nis based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). \nIt can be changed on the fly as this control register is buffered. The new prescaler ratio is \ntaken into account at the next update event.\nFigure 87 and Figure 88 give some examples of the counter behavior when the prescaler \nratio is changed on the fly:\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n522/1757\nRM0090 Rev 21\nFigure 87. Counter timing diagram with prescaler division change from 1 to 2\nFigure 88. Counter timing diagram with prescaler division change from 1 to 4\nCK_PSC\n00\nCEN\n \nTimerclock = CK_CNT\n \n \nCounter register\nUpdate event (UEV)\n0\nPrescaler control register\n1\n0\nWrite a new value in TIMx_PSC\nPrescaler buffer\n1\n0\nPrescaler counter\n0\n1\n0\n1\n0\n1\n0\n1\n01\n02\n03\nFA\nFB\nF7\nF8\nF9\nFC\nMS31076V2\n0\n3\n0\n0\n1\n2\n3\n0\n1\n2\n3\nMS31077V2\nCK_PSC\nCEN\n \nTimerclock = CK_CNT\n \n \nCounter register\nUpdate event (UEV)\nPrescaler control register\nWrite a new value in TIMx_PSC\nPrescaler buffer\nPrescaler counter\n00\n01\nFA\nFB\nF7\nF8\nF9\nFC\n3\n0\n\n\n<>\n\nRM0090 Rev 21\n523/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.3.2 \nCounter modes\nUpcounting mode\nIn upcounting mode, the counter counts from 0 to the auto-reload value (content of the \nTIMx_ARR register), then restarts from 0 and generates a counter overflow event.\nIf the repetition counter is used, the update event (UEV) is generated after upcounting is \nrepeated for the number of times programmed in the repetition counter register plus one \n(TIMx_RCR+1). Else the update event is generated at each counter overflow.\nSetting the UG bit in the TIMx_EGR register (by software or by using the slave mode \ncontroller) also generates an update event.\nThe UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 \nregister. This is to avoid updating the shadow registers while writing new values in the \npreload registers. Then no update event occurs until the UDIS bit has been written to 0. \nHowever, the counter restarts from 0, as well as the counter of the prescaler (but the \nprescale rate does not change). In addition, if the URS bit (update request selection) in \nTIMx_CR1 register is set, setting the UG bit generates an update event UEV but without \nsetting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating \nboth update and capture interrupts when clearing the counter on the capture event.\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in \nTIMx_SR register) is set (depending on the URS bit):\n•\nThe repetition counter is reloaded with the content of TIMx_RCR register,\n•\nThe auto-reload shadow register is updated with the preload value (TIMx_ARR),\n•\nThe buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC \nregister).\nThe following figures show some examples of the counter behavior for different clock \nfrequencies when TIMx_ARR=0x36.\nFigure 89. Counter timing diagram, internal clock divided by 1\n00\n02\n03\n04\n05\n06\n07\n33\n34\n35\n36\n31\nMS31078V3\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n01\n32\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n524/1757\nRM0090 Rev 21\nFigure 90. Counter timing diagram, internal clock divided by 2\nFigure 91. Counter timing diagram, internal clock divided by 4\nFigure 92. Counter timing diagram, internal clock divided by N\nMS31079V3\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n0034\n0035\n0036\n0000\n0001\n0002\n0003\nMS31080V3\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n0000\n0001\n0035\n0036\nMS31081V3\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n1F\n20\n\n\n<>\n\nRM0090 Rev 21\n525/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 93. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not \npreloaded)\nFigure 94. Counter timing diagram, update event when ARPE=1 (TIMx_ARR \npreloaded)\nFF\n36\nMS31082V3\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n02\n03\n04\n05\n06\n07\n32\n33\n34\n35\n36\n31\n01\nCEN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\nMS31083V2\nF5\n36\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag\n (UIF)\n00\n02\n03\n04\n05\n06\n07\nF1\nF2\nF3\nF4\nF5\nF0\n01\nCEN\nAuto-reload preload\nregister\nWrite a new value in TIMx_ARR\nAuto-reload shadow\nregister\nF5\n36\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n526/1757\nRM0090 Rev 21\nDowncounting mode\nIn downcounting mode, the counter counts from the auto-reload value (content of the \nTIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a \ncounter underflow event.\nIf the repetition counter is used, the update event (UEV) is generated after downcounting is \nrepeated for the number of times programmed in the repetition counter register plus one \n(TIMx_RCR+1). Else the update event is generated at each counter underflow.\nSetting the UG bit in the TIMx_EGR register (by software or by using the slave mode \ncontroller) also generates an update event.\nThe UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 \nregister. This is to avoid updating the shadow registers while writing new values in the \npreload registers. Then no update event occurs until UDIS bit has been written to 0. \nHowever, the counter restarts from the current auto-reload value, whereas the counter of the \nprescaler restarts from 0 (but the prescale rate doesn’t change). \nIn addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the \nUG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or \nDMA request is sent). This is to avoid generating both update and capture interrupts when \nclearing the counter on the capture event.\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in \nTIMx_SR register) is set (depending on the URS bit):\n•\nThe repetition counter is reloaded with the content of TIMx_RCR register\n•\nThe buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC \nregister)\n•\nThe auto-reload active register is updated with the preload value (content of the \nTIMx_ARR register). Note that the auto-reload is updated before the counter is \nreloaded, so that the next period is the expected one\nThe following figures show some examples of the counter behavior for different clock \nfrequencies when TIMx_ARR=0x36.\n\n\n<>\n\nRM0090 Rev 21\n527/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 95. Counter timing diagram, internal clock divided by 1\nFigure 96. Counter timing diagram, internal clock divided by 2\n36\n34\n33\n32\n31\n30\n2F\n04\n03\n02\n01\n00\n05\nMS31184V1\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow \n(cnt_udf)\nUpdate interrupt flag\n (UIF)\n35\nMS31185V1\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow\nUpdate interrupt flag\n (UIF)\n0002\n0001\n0000\n0036\n0035\n0034\n0033\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n528/1757\nRM0090 Rev 21\nFigure 97. Counter timing diagram, internal clock divided by 4\nFigure 98. Counter timing diagram, internal clock divided by N\nMS40510V1\n0036\n0035\n0001\n0000\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow\nUpdate interrupt flag (UIF)\nCNT_EN\n00\n1F\n20\nMS31187V1\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow\nUpdate interrupt flag\n (UIF)\n36\n\n\n<>\n\nRM0090 Rev 21\n529/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 99. Counter timing diagram, update event when repetition counter is not used\nCenter-aligned mode (up/down counting)\nIn center-aligned mode, the counter counts from 0 to the auto-reload value (content of the \nTIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-\nreload value down to 1 and generates a counter underflow event. Then it restarts counting \nfrom 0.\nCenter-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to \n'00'. The Output compare interrupt flag of channels configured in output is set when: the \ncounter counts down (Center aligned mode 1, CMS = \"01\"), the counter counts up (Center \naligned mode 2, CMS = \"10\") the counter counts up and down (Center aligned mode 3, \nCMS = \"11\").\nIn this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated \nby hardware and gives the current direction of the counter.\nThe update event can be generated at each counter overflow and at each counter underflow \nor by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode \ncontroller) also generates an update event. In this case, the counter restarts counting from \n0, as well as the counter of the prescaler.\nThe UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1 \nregister. This is to avoid updating the shadow registers while writing new values in the \npreload registers. Then no update event occurs until UDIS bit has been written to 0. \nHowever, the counter continues counting up and down, based on the current auto-reload \nvalue. \nIn addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the \nUG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or \nDMA request is sent). This is to avoid generating both update and capture interrupts when \nclearing the counter on the capture event.\nFF\n36\nMS31188V1\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow\nUpdate interrupt flag\n (UIF)\n00\n02\n03\n04\n05\n30\n2F\n32\n33\n34\n35\n36\n31\n01\nCEN\nAuto-reload preload\nregister\nWrite a new value in TIMx_ARR\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n530/1757\nRM0090 Rev 21\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in \nTIMx_SR register) is set (depending on the URS bit):\n•\nThe repetition counter is reloaded with the content of TIMx_RCR register\n•\nThe buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC \nregister)\n•\nThe auto-reload active register is updated with the preload value (content of the \nTIMx_ARR register). Note that if the update source is a counter overflow, the auto-\nreload is updated before the counter is reloaded, so that the next period is the expected \none (the counter is loaded with the new value).\nThe following figures show some examples of the counter behavior for different clock \nfrequencies.\nFigure 100. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6\n1.\nHere, center-aligned mode 1 is used (for more details refer to Section 17.4: TIM1 and TIM8 registers).\nFigure 101. Counter timing diagram, internal clock divided by 2\n \nMS31189V2\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\nCEN\nCounter underflow\n00\n02\n03\n04\n05\n06\n01\n02\n03\n04\n01\n05\n03\n04\nMS31190V2\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nCNT_EN\nCounter underflow\n0003\n0002\n0001\n0000\n0001\n0002\n0003\n\n\n<>\n\nRM0090 Rev 21\n531/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 102. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36\n1.\nCenter-aligned mode 2 or 3 is used with an UIF on overflow.\nFigure 103. Counter timing diagram, internal clock divided by N\n0034\n0035\nMS31191V2\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\nCNT_EN\n0036\n0035\nMS31192V2\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nCounter underflow\n00\n1F\n20\n01\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n532/1757\nRM0090 Rev 21\nFigure 104. Counter timing diagram, update event with ARPE=1 (counter underflow)\nFigure 105. Counter timing diagram, Update event with ARPE=1 (counter overflow)\n17.3.3 \nRepetition counter\nSection 17.3.1: Time-base unit describes how the update event (UEV) is generated with \nrespect to the counter overflows/underflows. It is actually generated only when the repetition \ncounter has reached zero. This can be useful when generating PWM signals.\nThis means that data are transferred from the preload registers to the shadow registers \n(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx \ncapture/compare registers in compare mode) every N+1 counter overflows or underflows, \nwhere N is the value in the TIMx_RCR repetition counter register.\nMS31193V3\nCK_PSC\nTimer clock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\nCEN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\nAuto-reload active register\nFD\n36\n00\n02\n03\n04\n05\n06 07\n01\n06\n05\n04\n03\n02\n01\nFD\n36\nMS31194V2\nFD\n36\nCK_PSC\nTimer clock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n36\n34\n33\n32\n31\n30\n2F\nF8\nF9\nFA\nFB FC\nF7\n35\nCEN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\nAuto-reload active register\nFD\n36\n\n\n<>\n\nRM0090 Rev 21\n533/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nThe repetition counter is decremented:\n•\nAt each counter overflow in upcounting mode,\n•\nAt each counter underflow in downcounting mode,\n•\nAt each counter overflow and at each counter underflow in center-aligned mode. \nAlthough this limits the maximum number of repetition to 128 PWM cycles, it makes it \npossible to update the duty cycle twice per PWM period. When refreshing compare \nregisters only once per PWM period in center-aligned mode, maximum resolution is \n2xTck, due to the symmetry of the pattern.\nThe repetition counter is an auto-reload type; the repetition rate is maintained as defined by \nthe TIMx_RCR register value (refer to Figure 106). When the update event is generated by \nsoftware (by setting the UG bit in TIMx_EGR register) or by hardware through the slave \nmode controller, it occurs immediately whatever the value of the repetition counter is and the \nrepetition counter is reloaded with the content of the TIMx_RCR register.\nIn center-aligned mode, for odd values of RCR, the update event occurs either on the \noverflow or on the underflow depending on when the RCR register was written and when \nthe counter was started. If the RCR was written before starting the counter, the UEV occurs \non the overflow. If the RCR was written after starting the counter, the UEV occurs on the \nunderflow. For example for RCR = 3, the UEV is generated on each 4th overflow or \nunderflow event depending on when RCR was written.\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n534/1757\nRM0090 Rev 21\nFigure 106. Update rate examples depending on mode and TIMx_RCR register \nsettings\nMSv31195V1\nUEV\nUEV\nUEV\nUEV\nUEV\nCounter-aligned mode\nEdge-aligned mode\nUpcounting\nDowncounting\n(by SW)\n(by SW)\n(by SW)\nTIMx_RCR = 3\nand\nre-synchronization\nTIMx_RCR = 3\nTIMx_RCR = 2\nTIMx_RCR = 1\nTIMx_RCR = 0\nCounter\nTIMx_CNT\nUEV\nUpdate event: Preload registers transferred to active registers and update interrupt generated\nUpdate Event if the repetition counter underflow occurs when the counter is equal to the auto-reload value.\n\n\n<>\n\nRM0090 Rev 21\n535/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.3.4 \nClock selection\nThe counter clock can be provided by the following clock sources:\n•\nInternal clock (CK_INT)\n•\nExternal clock mode1: external input pin\n•\nExternal clock mode2: external trigger input ETR\n•\nInternal trigger inputs (ITRx): using one timer as prescaler for another timer, for \nexample, the user can configure Timer 1 to act as a prescaler for Timer 2. Refer to \nUsing one timer as prescaler for another timer for more details.\nInternal clock source (CK_INT)\nIf the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 \nregister) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed \nonly by software (except UG which remains cleared automatically). As soon as the CEN bit \nis written to 1, the prescaler is clocked by the internal clock CK_INT.\nFigure 107 shows the behavior of the control circuit and the upcounter in normal mode, \nwithout prescaler.\nFigure 107. Control circuit in normal mode, internal clock divided by 1\nExternal clock source mode 1\nThis mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at \neach rising or falling edge on a selected input.\nInternal clock\nCounter clock = CK_CNT = CK_PSC\nCounter register\nCEN=CNT_EN\nUG\nCNT_INIT\nMS31085V2\n00\n02\n03\n04\n05\n06\n07\n3 2\n33\n34\n35 36\n31\n01\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n536/1757\nRM0090 Rev 21\nFigure 108. TI2 external clock connection example\nFor example, to configure the upcounter to count in response to a rising edge on the TI2 \ninput, use the following procedure:\n1.\nConfigure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in \nthe TIMx_CCMR1 register.\n2. \nConfigure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 \nregister (if no filter is needed, keep IC2F=0000).\n3. \nSelect rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER \nregister.\n4. \nConfigure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR \nregister. \n5. \nSelect TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register.\n6. \nEnable the counter by writing CEN=1 in the TIMx_CR1 register.\nNote:\nThe capture prescaler is not used for triggering, so the user does not need to configure it. \nWhen a rising edge occurs on TI2, the counter counts once and the TIF flag is set.\nThe delay between the rising edge on TI2 and the actual clock of the counter is due to the \nresynchronization circuit on TI2 input.\nExternal clock\nmode 1 \nInternal clock\nmode\nTRGI\nCK_INT\nCK_PSC\nTIMx_SMCR\nSMS[2:0]\nITRx\nTI1_ED\nTI1FP1\nTI2FP2\nTIMx_SMCR\nTS[2:0]\nTI2\n0\n1\nTIMx_CCER\nCC2P\nFilter\nICF[3:0]\nTIMx_CCMR1\nEdge\ndetector\nTI2F_Rising\nTI2F_Falling\n110\n0xx\n100\n101\nMS31196V1\n(internal clock)\nTI1F\nor\nTI2F\nor\nor\nEncoder\nmode \nETRF\n111\nExternal clock\nmode 2 \nETRF\nECE\n\n\n<>\n\nRM0090 Rev 21\n537/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 109. Control circuit in external clock mode 1\nExternal clock source mode 2 \nThis mode is selected by writing ECE=1 in the TIMx_SMCR register.\nThe counter can count at each rising or falling edge on the external trigger input ETR.\nFigure 110 gives an overview of the external trigger input block.\nFigure 110. External trigger input block\nCounter clock = CK_CNT = CK_PSC\nCounter register\n35\n36\n34\nTI2\nCNT_EN\nTIF\nWrite TIF=0\nMS31087V2\nExternal clock\nmode 1 \nInternal clock\nmode\nTRGI\nCK_INT\nCK_PSC\nTIMx_SMCR\nSMS[2:0]\nMS33116V1\n(internal clock)\nTI1F\nor\nTI2F\nor\nor\nEncoder\nmode \nExternal clock\nmode 2 \nETRF\nECE\n0\n1\nTIMx_SMCR\nETP\nETR pin\nETR\nDivider\n/1, /2, /4, /8\nFilter\ndowncounter\nf\nETRP\nTIMx_SMCR\nETPS[1:0]\nTIMx_SMCR\nETF[3:0]\nDTS\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n538/1757\nRM0090 Rev 21\nFor example, to configure the upcounter to count each 2 rising edges on ETR, use the \nfollowing procedure:\n1.\nAs no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.\n2. \nSet the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register \n3. \nSelect rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR \nregister\n4. \nEnable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.\n5. \nEnable the counter by writing CEN=1 in the TIMx_CR1 register.\nThe counter counts once each 2 ETR rising edges.\nThe delay between the rising edge on ETR and the actual clock of the counter is due to the \nresynchronization circuit on the ETRP signal.\nFigure 111. Control circuit in external clock mode 2\n17.3.5 \nCapture/compare channels\nEach Capture/Compare channel is built around a capture/compare register (including a \nshadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and \nan output stage (with comparator and output control).\nFigure 112 to Figure 115 give an overview of one Capture/Compare channel.\nThe input stage samples the corresponding TIx input to generate a filtered signal TIxF. \nThen, an edge detector with polarity selection generates a signal (TIxFPx) which can be \nused as trigger input by the slave mode controller or as the capture command. It is \nprescaled before the capture register (ICxPS).\nMS33111V2\n34\n35\n36\nfCK_INT\nCNT_EN\nETR\nETRP\nETRF\nCounter clock = \nCK_INT =CK_PSC\nCounter register\n\n\n<>\n\nRM0090 Rev 21\n539/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 112. Capture/compare channel (example: channel 1 input stage)\nThe output stage generates an intermediate waveform that is then used for reference: \nOCxRef (active high). The polarity acts at the end of the chain.\nFigure 113. Capture/compare channel 1 main circuit\n0\n1\nDivider\n/1, /2, /4, /8\nICPS[1:0]\nTI1F_ED\nTo the slave mode controller\nTI1FP1\n11\n01\nCC1S[1:0]\nIC1\nTI2FP1\nTRC\n(from slave mode\ncontroller)\n10\nIC1PS\n0\n1\nMS33115V1\nTI1\nTIMx_CCER\nCC1P/CC1NP\nFilter\ndowncounter\nICF[3:0]\nTIMx_CCMR1\nEdge\ndetector\nTI1F_Rising\nTI1F_Falling\nTIMx_CCMR1\nTIMx_CCER\nTI2F_Rising\n(from channel 2)\nTI2F_Falling\n(from channel 2)\nTI1F\nf\nCC1E\nDTS\nMS31089V3\nCC1E\nCapture/compare shadow register\nComparator\nCapture/compare preload register\nCounter\nIC1PS\nCC1S[0]\nCC1S[1]\nCapture\nInput \nmode\nS\nR\nRead CCR1H\nRead CCR1L\nread_in_progress\ncapture_transfer\nCC1S[0]\nCC1S[1]\nS\nR\nwrite CCR1H\nwrite CCR1L\nwrite_in_progress\nOutput \nmode\nUEV\nOC1PE\n(from time \nbase unit)\ncompare_transfer\nAPB Bus\n8\n8\nhigh\nlow\n(if 16-bit)\nMCU-peripheral interface\nTIMx_CCMR1\nOC1PE\nCNT>CCR1\nCNT=CCR1\nTIMx_EGR\nCC1G\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n540/1757\nRM0090 Rev 21\nFigure 114. Output stage of capture/compare channel (channel 1 to 3)\nFigure 115. Output stage of capture/compare channel (channel 4)\nThe capture/compare block is made of one preload register and one shadow register. Write \nand read always access the preload register. \nIn capture mode, captures are actually done in the shadow register, which is copied into the \npreload register. \nIn compare mode, the content of the preload register is copied into the shadow register \nwhich is compared to the counter.\nMS35909V1\nOutput\nmode\ncontroller\nCNT>CCR1\nCNT=CCR1\nTIM1_CCMR1\nOC1M[3:0]\nOC1REF\nOC1CE\nDead-time\ngenerator\nOC1_DT\nOC1N_DT\nDTG[7:0]\nTIM1_BDTR\n‘0’\n‘0’\nCC1E\nTIM1_CCER\nCC1NE\n0\n1\nCC1P\nTIM1_CCER\n0\n1\nCC1NP\nTIM1_CCER\nOC1\nOutput\nenable\ncircuit\nOC1N\nCC1E TIM1_CCER\nCC1NE\nOSSI\nTIM1_BDTR\nMOE\nOSSR\n0x\n10\n11\n11\n01\nx0\nOutput\nselector\nOCxREF\nOC1REFC\nTo the master mode\ncontroller\nOutput\nenable\ncircuit\nOC5REF\n(1)\nETRF\nMS37370V1\nOutput \nmode \ncontroller\nTIM1_CCMR2\nOC1M[3:0]\nOC4REF\n0\n1\nCC4P\nTIM1_CCER\nOC4\nTo the master \nmode controller\nOutput \nenable \ncircuit\nETR\nCNT>CCR4\nCNT>CCR4\nTIM1_CCER\nTIM1_BDTR\nTIM1_CR2\nOSSI\nMOE\nCC4E\nOIS4\n\n\n<>\n\nRM0090 Rev 21\n541/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.3.6 \nInput capture mode\nIn Input capture mode, the Capture/Compare registers (TIMx_CCRx) are used to latch the \nvalue of the counter after a transition detected by the corresponding ICx signal. When a \ncapture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or \na DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was \nalready high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be \ncleared by software by writing it to ‘0’ or by reading the captured data stored in the \nTIMx_CCRx register. CCxOF is cleared when written to ‘0’.\nThe following example shows how to capture the counter value in TIMx_CCR1 when TI1 \ninput rises. To do this, use the following procedure:\n•\nSelect the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S \nbits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, \nthe channel is configured in input and the TIMx_CCR1 register becomes read-only.\n•\nProgram the needed input filter duration with respect to the signal connected to the \ntimer (by programming ICxF bits in the TIMx_CCMRx register if the input is a TIx input). \nLet’s imagine that, when toggling, the input signal is not stable during at must five \ninternal clock cycles. We must program a filter duration longer than these five clock \ncycles. We can validate a transition on TI1 when 8 consecutive samples with the new \nlevel have been detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in \nthe TIMx_CCMR1 register.\n•\nSelect the edge of the active transition on the TI1 channel by writing CC1P and CC1NP \nbits to 0 in the TIMx_CCER register (rising edge in this case).\n•\nProgram the input prescaler. In our example, we wish the capture to be performed at \neach valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the \nTIMx_CCMR1 register).\n•\nEnable capture from the counter into the capture register by setting the CC1E bit in the \nTIMx_CCER register.\n•\nIf needed, enable the related interrupt request by setting the CC1IE bit in the \nTIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the \nTIMx_DIER register.\nWhen an input capture occurs:\n•\nThe TIMx_CCR1 register gets the value of the counter on the active transition.\n•\nCC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures \noccurred whereas the flag was not cleared.\n•\nAn interrupt is generated depending on the CC1IE bit.\n•\nA DMA request is generated depending on the CC1DE bit.\nIn order to handle the overcapture, it is recommended to read the data before the \novercapture flag. This is to avoid missing an overcapture which could happen after reading \nthe flag and before reading the data.\nNote:\nIC interrupt and/or DMA requests can be generated by software by setting the \ncorresponding CCxG bit in the TIMx_EGR register.\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n542/1757\nRM0090 Rev 21\n17.3.7 \nPWM input mode\nThis mode is a particular case of input capture mode. The procedure is the same except:\n•\nTwo ICx signals are mapped on the same TIx input.\n•\nThese 2 ICx signals are active on edges with opposite polarity.\n•\nOne of the two TIxFP signals is selected as trigger input and the slave mode controller \nis configured in reset mode.\nFor example, user can measure the period (in TIMx_CCR1 register) and the duty cycle (in \nTIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending \non CK_INT frequency and prescaler value):\n•\nSelect the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 \nregister (TI1 selected).\n•\nSelect the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter \nclear): write the CC1P and CC1NP bits to ‘0’ (active on rising edge).\n•\nSelect the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 \nregister (TI1 selected).\n•\nSelect the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P \nbit to '1' and the CC2NP bit to '0' (active on falling edge).\n•\nSelect the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register \n(TI1FP1 selected).\n•\nConfigure the slave mode controller in reset mode: write the SMS bits to 100 in the \nTIMx_SMCR register.\n•\nEnable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.\nFigure 116. PWM input mode timing\n17.3.8 \nForced output mode\nIn output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal \n(OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, \nindependently of any comparison between the output compare register and the counter.\nTo force an output compare signal (OCXREF/OCx) to its active level, the user just needs to \nwrite 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is \n\n\n<>\n\nRM0090 Rev 21\n543/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nforced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity \nbit.\nFor example: CCxP=0 (OCx active high) => OCx is forced to high level.\nThe OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx \nregister.\nAnyway, the comparison between the TIMx_CCRx shadow register and the counter is still \nperformed and allows the flag to be set. Interrupt and DMA requests can be sent \naccordingly. This is described in the output compare mode section below.\n17.3.9 \nOutput compare mode\nThis function is used to control an output waveform or indicating when a period of time has \nelapsed.\nWhen a match is found between the capture/compare register and the counter, the output \ncompare function: \n•\nAssigns the corresponding output pin to a programmable value defined by the output \ncompare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP \nbit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set \nactive (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.\n•\nSets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).\n•\nGenerates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the \nTIMx_DIER register).\n•\nSends a DMA request if the corresponding enable bit is set (CCxDE bit in the \nTIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request \nselection).\nThe TIMx_CCRx registers can be programmed with or without preload registers using the \nOCxPE bit in the TIMx_CCMRx register.\nIn output compare mode, the update event UEV has no effect on OCxREF and OCx output. \nThe timing resolution is one count of the counter. Output compare mode can also be used to \noutput a single pulse (in One Pulse mode).\nProcedure:\n1.\nSelect the counter clock (internal, external, prescaler).\n2. \nWrite the desired data in the TIMx_ARR and TIMx_CCRx registers.\n3. \nSet the CCxIE bit if an interrupt request is to be generated.\n4. \nSelect the output mode. For example:\n–\nWrite OCxM = 011 to toggle OCx output pin when CNT matches CCRx\n–\nWrite OCxPE = 0 to disable preload register\n–\nWrite CCxP = 0 to select active high polarity\n–\nWrite CCxE = 1 to enable the output\n5. \nEnable the counter by setting the CEN bit in the TIMx_CR1 register.\nThe TIMx_CCRx register can be updated at any time by software to control the output \nwaveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx \nshadow register is updated only at the next update event UEV). An example is given in \nFigure 117.\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n544/1757\nRM0090 Rev 21\nFigure 117. Output compare mode, toggle on OC1.\n17.3.10 \nPWM mode\nPulse Width Modulation mode allows generating a signal with a frequency determined by \nthe value of the TIMx_ARR register and a duty cycle determined by the value of the \nTIMx_CCRx register.\nThe PWM mode can be selected independently on each channel (one PWM per OCx \noutput) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the \nTIMx_CCMRx register. The corresponding preload register must be enabled by setting the \nOCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in \nupcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.\nAs the preload registers are transferred to the shadow registers only when an update event \noccurs, before starting the counter, the user must initialize all the registers by setting the UG \nbit in the TIMx_EGR register.\nOCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It \ncan be programmed as active high or active low. OCx output is enabled by a combination of \nthe CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers). \nRefer to the TIMx_CCER register description for more details.\nIn PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine \nwhether TIMx_CCRx ≤TIMx_CNT or TIMx_CNT ≤TIMx_CCRx (depending on the direction \nof the counter). \nThe timer is able to generate PWM in edge-aligned mode or center-aligned mode \ndepending on the CMS bits in the TIMx_CR1 register.\nPWM edge-aligned mode\n•\nUpcounting configuration\nUpcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to \nUpcounting mode.\nIn the following example, we consider PWM mode 1. The reference PWM signal \nOCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the \nMS31092V2\nOC1REF= OC1\nTIM1_CNT\nB200\nB201\n0039\nTIM1_CCR1\n003A\nWrite B201h in the CC1R register\nMatch detected on CCR1\nInterrupt generated if enabled\n003B\nB201\n003A\n\n\n<>\n\nRM0090 Rev 21\n545/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\ncompare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) \nthen OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. \nFigure 118 shows some edge-aligned PWM waveforms in an example where \nTIMx_ARR=8.\nFigure 118. Edge-aligned PWM waveforms (ARR=8)\n•\nDowncounting configuration\nDowncounting is active when DIR bit in TIMx_CR1 register is high. Refer to \nDowncounting mode\nIn PWM mode 1, the reference signal OCxRef is low as long as \nTIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is \ngreater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM \nis not possible in this mode.\nPWM center-aligned mode\nCenter-aligned mode is active when the CMS bits in TIMx_CR1 register are different from \n‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals). \nThe compare flag is set when the counter counts up, when it counts down or both when it \ncounts up and down depending on the CMS bits configuration. The direction bit (DIR) in the \nMS31093V1\nCounter register\n‘1’\n0\n1\n2\n3\n4\n5\n6\n7\n8\n0\n1\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nCCRx=4\nCCRx=8\nCCRx>8\nCCRx=0\n‘0’\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n546/1757\nRM0090 Rev 21\nTIMx_CR1 register is updated by hardware and must not be changed by software. Refer to \nCenter-aligned mode (up/down counting).\nFigure 119 shows some center-aligned PWM waveforms in an example where:\n•\nTIMx_ARR=8,\n•\nPWM mode is the PWM mode 1,\n•\nThe flag is set when the counter counts down corresponding to the center-aligned \nmode 1 selected for CMS=01 in TIMx_CR1 register.\nFigure 119. Center-aligned PWM waveforms (ARR=8)\nHints on using center-aligned mode:\n•\nWhen starting in center-aligned mode, the current up-down configuration is used. It \nmeans that the counter counts up or down depending on the value written in the DIR bit \nCCxIF\n0\n1\n2\n3\n4\n5\n6\n7\n8\n7\n6\n5\n4\n3\n2\n1\n0\n1\nCounter register\nCCRx = 4\nOCxREF\nCMS=01\nCMS=10\nCMS=11\nCCxIF\nCCRx = 7\nOCxREF\nCMS=10 or 11\nCCxIF\nCCRx = 8\nOCxREF\nCMS=01\nCMS=10\nCMS=11\n'1'\nCCxIF\nCCRx > 8\nOCxREF\nCMS=01\nCMS=10\nCMS=11\n'1'\nCCxIF\nCCRx = 0\nOCxREF\nCMS=01\nCMS=10\nCMS=11\n'0'\nai14681b\n\n\n<>\n\nRM0090 Rev 21\n547/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nin the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the \nsame time by the software.\n•\nWriting to the counter while running in center-aligned mode is not recommended as it \ncan lead to unexpected results. In particular:\n–\nThe direction is not updated if the user writes a value in the counter greater than \nthe auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was \ncounting up, it continues to count up.\n–\nThe direction is updated if the user writes 0 or write the TIMx_ARR value in the \ncounter but no Update Event UEV is generated.\n•\nThe safest way to use center-aligned mode is to generate an update by software \n(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to \nwrite the counter while it is running.\n17.3.11 \nComplementary outputs and dead-time insertion\nThe advanced-control timers (TIM1 and TIM8) can output two complementary signals and \nmanage the switching-off and the switching-on instants of the outputs.\nThis time is generally known as dead-time and it has to be adjust it depending on the \ndevices connected to the outputs and their characteristics (intrinsic delays of level-shifters, \ndelays due to power switches...)\nUser can select the polarity of the outputs (main output OCx or complementary OCxN) \nindependently for each output. This is done by writing to the CCxP and CCxNP bits in the \nTIMx_CCER register.\nThe complementary signals OCx and OCxN are activated by a combination of several \ncontrol bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx, \nOISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to Table 96 \nfor more details. In particular, the dead-time is activated when switching to the IDLE state \n(MOE falling down to 0).\nDead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the \nbreak circuit is present. DTG[7:0] bits of the TIMx_BDTR register are used to control the \ndead-time generation for all channels. From a reference waveform OCxREF, it generates 2 \noutputs OCx and OCxN. If OCx and OCxN are active high:\n•\nThe OCx output signal is the same as the reference signal except for the rising edge, \nwhich is delayed relative to the reference rising edge.\n•\nThe OCxN output signal is the opposite of the reference signal except for the rising \nedge, which is delayed relative to the reference falling edge.\nIf the delay is greater than the width of the active output (OCx or OCxN) then the \ncorresponding pulse is not generated.\nThe following figures show the relationships between the output signals of the dead-time \ngenerator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1, \nCCxE=1 and CCxNE=1 in these examples)\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n548/1757\nRM0090 Rev 21\nFigure 120. Complementary output with dead-time insertion.\nFigure 121. Dead-time waveforms with delay greater than the negative pulse.\nFigure 122. Dead-time waveforms with delay greater than the positive pulse.\nThe dead-time delay is the same for each of the channels and is programmable with the \nDTG bits in the TIMx_BDTR register. Refer to Section 17.4.18: TIM1 and TIM8 break and \ndead-time register (TIMx_BDTR) for delay calculation.\nRe-directing OCxREF to OCx or OCxN\nIn output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx \noutput or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER \nregister.\nThis allows the user to send a specific waveform (such as PWM or static active level) on \none output while the complementary remains at its inactive level. Other possibilities are to \ndelay\ndelay\nOCxREF\nOCx\nOCxN\nMS31095V1\nMS31096V1\ndelay\nOCxREF\nOCx\nOCxN\nMS31097V1\ndelay\nOCxREF\nOCx\nOCxN\n\n\n<>\n\nRM0090 Rev 21\n549/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nhave both outputs at inactive level or both outputs active and complementary with \ndead-time.\nNote:\nWhen only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes \nactive as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the \nother hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes \nactive when OCxREF is high whereas OCxN is complemented and becomes active when \nOCxREF is low.\n17.3.12 \nUsing the break function\nWhen using the break function, the output enable signals and inactive levels are modified \naccording to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register, \nOISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs \ncannot be set both to active level at a given time. Refer to Table 96 for more details.\nThe break source can be either the break input pin or a clock failure event, generated by the \nClock Security System (CSS), from the Reset Clock Controller. For further information on \nthe Clock Security System, refer to Section 7.2.7: Clock security system (CSS).\nWhen exiting from reset, the break circuit is disabled and the MOE bit is low. User can \nenable the break function by setting the BKE bit in the TIMx_BDTR register. The break input \npolarity can be selected by configuring the BKP bit in the same register. BKE and BKP can \nbe modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB \nclock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1 \nAPB clock period to correctly read back the bit after the write operation.\nBecause MOE falling edge can be asynchronous, a resynchronization circuit has been \ninserted between the actual signal (acting on the outputs) and the synchronous control bit \n(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous \nand the synchronous signals. In particular, if MOE is written to 1 whereas it was low, a delay \n(dummy instruction) must be inserted before reading it correctly. This is because the user \nwrites an asynchronous signal, but reads a synchronous signal.\nWhen a break occurs (selected level on the break input):\n•\nThe MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state \nor in reset state (selected by the OSSI bit). This feature functions even if the MCU \noscillator is off.\n•\nEach output channel is driven with the level programmed in the OISx bit in the \nTIMx_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable \noutput else the enable output remains high.\n•\nWhen complementary outputs are used: \n–\nThe outputs are first put in reset state inactive state (depending on the polarity). \nThis is done asynchronously so that it works even if no clock is provided to the \ntimer. \n–\nIf the timer clock is still present, then the dead-time generator is reactivated in \norder to drive the outputs with the level programmed in the OISx and OISxN bits \nafter a dead-time. Even in this case, OCx and OCxN cannot be driven to their \n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n550/1757\nRM0090 Rev 21\nactive level together. Note that because of the resynchronization on MOE, the \ndead-time duration is a bit longer than usual (around 2 ck_tim clock cycles).\n–\nIf OSSI=0 then the timer releases the enable outputs else the enable outputs \nremain or become high as soon as one of the CCxE or CCxNE bits is high.\n•\nThe break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be \ngenerated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if \nthe BDE bit in the TIMx_DIER register is set.\n•\nIf the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again \nat the next update event UEV. This can be used to perform a regulation, for instance. \nElse, MOE remains low until it is written to ‘1’ again. In this case, it can be used for \nsecurity and the break input can be connected to an alarm from power drivers, thermal \nsensors or any security components.\nNote:\nThe break inputs is acting on level. Thus, the MOE cannot be set while the break input is \nactive (neither automatically nor by software). In the meantime, the status flag BIF cannot \nbe cleared.\nThe break can be generated by the BRK input which has a programmable polarity and an \nenable bit BKE in the TIMx_BDTR register.\nThere are two solutions to generate a break:\n•\nBy using the BRK input which has a programmable polarity and an enable bit BKE in \nthe TIMx_BDTR register\n•\nBy software through the BG bit of the TIMx_EGR register.\nIn addition to the break input and the output management, a write protection has been \nimplemented inside the break circuit to safeguard the application. It allows freezing the \nconfiguration of several parameters (dead-time duration, OCx/OCxN polarities and state \nwhen disabled, OCxM configurations, break enable and polarity). The user can choose from \nthree levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to \nSection 17.4.18: TIM1 and TIM8 break and dead-time register (TIMx_BDTR). The LOCK \nbits can be written only once after an MCU reset.\n\n\n<>\n\nRM0090 Rev 21\n551/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 123 shows an example of behavior of the outputs in response to a break.\nFigure 123. Output behavior in response to a break.\ndelay\ndelay\ndelay\ndelay\ndelay\ndelay\ndelay\ndelay\nOCxREF\nOCx\n(OCxN not implemented, CCxP=0, OISx=1)\nOCx\n(OCxN not implemented, CCxP=0, OISx=0)\nOCx\n(OCxN not implemented, CCxP=1, OISx=1)\nOCx\n(OCxN not implemented, CCxP=1, OISx=0)\nOCx\nOCxN\n(CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1)\nOCx\nOCxN\n(CCxE=1, CCxP=0, OISx=1, CCxNE=1, CCxNP=1, OISxN=1)\nOCx\nOCxN\n(CCxE=1, CCxP=0, OISx=0, CCxNE=0, CCxNP=0, OISxN=1)\nOCx\nOCxN\n(CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0)\nOCx\nOCxN\n(CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1)\nMS31098V1\nBREAK (MOE ) \n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n552/1757\nRM0090 Rev 21\n17.3.13 \nClearing the OCxREF signal on an external event\nThe OCxREF signal for a given channel can be driven Low by applying a High level to the \nETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The \nOCxREF signal remains Low until the next update event, UEV, occurs. \nThis function can only be used in output compare and PWM modes, and does not work in \nforced mode.\nFor example, the ETR signal can be connected to the output of a comparator to be used for \ncurrent handling. In this case, the ETR must be configured as follow:\n1.\nThe External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR \nregister set to ‘00’.\n2. \nThe external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to \n‘0’.\n3. \nThe External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be \nconfigured according to the user needs.\nFigure 124 shows the behavior of the OCxREF signal when the ETRF Input becomes High, \nfor both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in \nPWM mode.\nFigure 124. Clearing TIMx OCxREF\nNote:\nIn case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at \nthe next counter overflow.\nMSv35889V1\n(CCRx)\nCounter (CNT)\nETRF\nOCxREF (OCxCE = ‘0’)\nOCxREF (OCxCE = ‘1’)\nETRF becomes high\nETRF still high\n\n\n<>\n\nRM0090 Rev 21\n553/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.3.14 \n6-step PWM generation\nWhen complementary outputs are used on a channel, preload bits are available on the \nOCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the \nCOM commutation event. The user can thus program in advance the configuration for the \nnext step and change the configuration of all the channels at the same time. COM can be \ngenerated by software by setting the COM bit in the TIMx_EGR register or by hardware (on \nTRGI rising edge).\nA flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can \ngenerate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request \n(if the COMDE bit is set in the TIMx_DIER register).\nFigure 125 describes the behavior of the OCx and OCxN outputs when a COM event \noccurs, in 3 different examples of programmed configurations.\nFigure 125. 6-step generation, COM example (OSSR=1)\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n554/1757\nRM0090 Rev 21\n17.3.15 \nOne-pulse mode\nOne-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to \nbe started in response to a stimulus and to generate a pulse with a programmable length \nafter a programmable delay.\nStarting the counter can be controlled through the slave mode controller. Generating the \nwaveform can be done in output compare mode or PWM mode. Select One-pulse mode by \nsetting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at \nthe next update event UEV.\nA pulse can be correctly generated only if the compare value is different from the counter \ninitial value. Before starting (when the timer is waiting for the trigger), the configuration must \nbe:\n•\nIn upcounting: CNT < CCRx ≤ARR (in particular, 0 < CCRx)\n•\nIn downcounting: CNT > CCRx\nFigure 126. Example of one pulse mode.\nFor example the user may want to generate a positive pulse on OC1 with a length of tPULSE \nand after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.\nLet’s use TI2FP2 as trigger 1:\n•\nMap TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.\n•\nTI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER \nregister.\n•\nConfigure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in \nthe TIMx_SMCR register.\n•\nTI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register \n(trigger mode).\nMS31099V2\nTI2\nOC1REF\nCounter\nt\n0\nTIM1_ARR\nTIM1_CCR1\nOC1\ntDELAY\ntPULSE\n\n\n<>\n\nRM0090 Rev 21\n555/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nThe OPM waveform is defined by writing the compare registers (taking into account the \nclock frequency and the counter prescaler).\n•\nThe tDELAY is defined by the value written in the TIMx_CCR1 register.\n•\nThe tPULSE is defined by the difference between the auto-reload value and the compare \nvalue (TIMx_ARR - TIMx_CCR1).\n•\nLet us say the user wants to build a waveform with a transition from ‘0’ to ‘1’ when a \ncompare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the \nauto-reload value. To do this, enable PWM mode 2 by writing OC1M=111 in the \nTIMx_CCMR1 register. The user can optionally enable the preload registers by writing \nOC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this \ncase the compare value must be written in the TIMx_CCR1 register, the auto-reload \nvalue in the TIMx_ARR register, generate an update by setting the UG bit and wait for \nexternal trigger event on TI2. CC1P is written to ‘0’ in this example.\nIn our example, the DIR and CMS bits in the TIMx_CR1 register should be low.\nThe user only wants one pulse (Single mode), so '1’ must be written in the OPM bit in the \nTIMx_CR1 register to stop the counter at the next update event (when the counter rolls over \nfrom the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', \nso the Repetitive mode is selected.\nParticular case: OCx fast enable:\nIn One-pulse mode, the edge detection on TIx input set the CEN bit which enables the \ncounter. Then the comparison between the counter and the compare value makes the \noutput toggle. But several clock cycles are needed for these operations and it limits the \nminimum delay tDELAY min we can get.\nIf the user wants to output a waveform with the minimum delay, the OCxFE bit in the \nTIMx_CCMRx register must be set. Then OCxRef (and OCx) are forced in response to the \nstimulus, without taking in account the comparison. Its new level is the same as if a compare \nmatch had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 \nmode.\n17.3.16 \nEncoder interface mode\nTo select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the \ncounter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and \nSMS=’011’ if it is counting on both TI1 and TI2 edges.\nSelect the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER \nregister. When needed, the user can program the input filter as well. CC1NP and CC2NP \nmust be kept low.\nThe two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to \nTable 94. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 \nafter input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted, \nTI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in \nTIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated \nand generates count pulses as well as the direction signal. Depending on the sequence the \ncounter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware \naccordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever \nthe counter is counting on TI1 only, TI2 only or both TI1 and TI2.\nEncoder interface mode acts simply as an external clock with direction selection. This \nmeans that the counter just counts continuously between 0 and the auto-reload value in the \n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n556/1757\nRM0090 Rev 21\nTIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So user must \nconfigure TIMx_ARR before starting. in the same way, the capture, compare, prescaler, \nrepetition counter, trigger output features continue to work as normal. Encoder mode and \nExternal clock mode 2 are not compatible and must not be selected together. \nIn this mode, the counter is modified automatically following the speed and the direction of \nthe incremental encoder and its content, therefore, always represents the encoder’s \nposition. The count direction correspond to the rotation direction of the connected sensor. \nTable 94 summarizes the possible combinations, assuming TI1 and TI2 do not switch at the \nsame time.\n \nAn external incremental encoder can be connected directly to the MCU without external \ninterface logic. However, comparators are normally be used to convert the encoder’s \ndifferential outputs to digital signals. This greatly increases noise immunity. The third \nencoder output which indicate the mechanical zero position, may be connected to an \nexternal interrupt input and trigger a counter reset.\nFigure 127 gives an example of counter operation, showing count signal generation and \ndirection control. It also shows how input jitter is compensated where both edges are \nselected. This might occur if the sensor is positioned near to one of the switching points. For \nthis example we assume that the configuration is the following:\n•\nCC1S=’01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1).\n•\nCC2S=’01’ (TIMx_CCMR1 register, TI1FP2 mapped on TI2).\n•\nCC1P=’0’, CC1NP=’0’, and IC1F = ‘0000’ (TIMx_CCER register, TI1FP1 non-inverted, \nTI1FP1=TI1).\n•\nCC2P=’0’, CC2NP=’0’, and IC2F = ‘0000’ (TIMx_CCER register, TI1FP2 non-inverted, \nTI1FP2= TI2).\n•\nSMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling \nedges).\n•\nCEN=’1’ (TIMx_CR1 register, Counter enabled).\nTable 94. Counting direction versus encoder signals\nActive\nedge\nLevel on opposite signal\n(TI1FP1 for TI2, TI2FP2 for TI1)\nTI1FP1 signal\nTI2FP2 signal\nRising\nFalling\nRising\nFalling\nCounting on \nTI1 only\nHigh\nDown\nUp\nNo Count\nNo Count\nLow\nUp\nDown\nNo Count\nNo Count\nCounting on \nTI2 only\nHigh\nNo Count\nNo Count\nUp\nDown\nLow\nNo Count\nNo Count\nDown\nUp\nCounting on \nTI1 and TI2\nHigh\nDown\nUp\nUp\nDown\nLow\nUp\nDown\nDown\nUp\n\n\n<>\n\nRM0090 Rev 21\n557/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 127. Example of counter operation in encoder interface mode.\nFigure 128 gives an example of counter behavior when TI1FP1 polarity is inverted (same \nconfiguration as above except CC1P=’1’).\nFigure 128. Example of encoder interface mode with TI1FP1 polarity inverted.\nThe timer, when configured in Encoder Interface mode provides information on the sensor’s \ncurrent position.The user can obtain dynamic information (speed, acceleration, \ndeceleration) by measuring the period between two encoder events using a second timer \nconfigured in capture mode. The output of the encoder which indicates the mechanical zero \ncan be used for this purpose. Depending on the time between two events, the counter can \nalso be read at regular times. This can be done by latching the counter value into a third \ninput capture register if available (then the capture signal must be periodic and can be \ngenerated by another timer). when available, it is also possible to read its value through a \nDMA request generated by a real-time clock.\nTI1\nbackward\njitter\njitter\nup\ndown\nup\nTI2\nCounter\nforward\nforward\nMS33107V1\nTI1\nbackward\njitter\njitter\nup\ndown\nTI2\nCounter\nforward\nforward\nMS33108V1\ndown\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n558/1757\nRM0090 Rev 21\n17.3.17 \nTimer input XOR function \nThe TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to \nthe output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and \nTIMx_CH3.\nThe XOR output can be used with all the timer input functions such as trigger or input \ncapture. An example of this feature used to interface Hall sensors is given in \nSection 17.3.18.\n17.3.18 \nInterfacing with Hall sensors\nThis is done using the advanced-control timers (TIM1 or TIM8) to generate PWM signals to \ndrive the motor and another timer TIMx (TIM2, TIM3, TIM4 or TIM5) referred to as \n“interfacing timer” in Figure 129. The “interfacing timer” captures the 3 timer input pins \n(TIMx_CH1, TIMx_CH2, and TIMx_CH3) connected through a XOR to the TI1 input channel \n(selected by setting the TI1S bit in the TIMx_CR2 register).\nThe slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus, \neach time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a \ntime base triggered by any change on the Hall inputs.\nOn the “interfacing timer”, capture/compare channel 1 is configured in capture mode, \ncapture signal is TRC (see Figure 112). The captured value, which corresponds to the time \nelapsed between 2 changes on the inputs, gives information about motor speed.\nThe “interfacing timer” can be used in output mode to generate a pulse which changes the \nconfiguration of the channels of the advanced-control timer (TIM1 or TIM8) (by triggering a \nCOM event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this, \nthe interfacing timer channel must be programmed so that a positive pulse is generated \nafter a programmed delay (in output compare or PWM mode). This pulse is sent to the \nadvanced-control timer (TIM1 or TIM8) through the TRGO output.\nExample: the user wants to change the PWM configuration of the advanced-control timer \nTIM1 after a programmed delay each time a change occurs on the Hall inputs connected to \none of the TIMx timers.\n•\nConfigure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the \nTIMx_CR2 register to ‘1’,\n•\nProgram the time base: write the TIMx_ARR to the max value (the counter must be \ncleared by the TI1 change. Set the prescaler to get a maximum counter period longer \nthan the time between 2 changes on the sensors,\n•\nProgram channel 1 in capture mode (TRC selected): write the CC1S bits in the \nTIMx_CCMR1 register to ‘11’. The user can also program the digital filter if needed,\n•\nProgram channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to ‘111’ \nand the CC2S bits to ‘00’ in the TIMx_CCMR1 register,\n•\nSelect OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 \nregister to ‘101’,\nIn the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the \ntimer is programmed to generate PWM signals, the capture/compare control signals are \npreloaded (CCPC=1 in the TIMx_CR2 register) and the COM event is controlled by the \ntrigger input (CCUS=1 in the TIMx_CR2 register). The PWM control bits (CCxE, OCxM) are \nwritten after a COM event for the next step (this can be done in an interrupt subroutine \ngenerated by the rising edge of OC2REF).\n\n\n<>\n\nRM0090 Rev 21\n559/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 129 describes this example.\nFigure 129. Example of Hall sensor interface\nai17335b\nCounter (CNT)\nTRGO=OC2REF\n(CCR2)\nOC1\nOC1N\nCOM \nWrite CCxE, CCxNE\nTIH1\nTIH2\nTIH3\nCCR1\nOC2\nOC2N\nOC3\nOC3N\nC796\nand OCxM for next step\nInterfacing timer\nAdvanced-control timers \nC7A3\nC7A8\nC794\nC7A5\nC7AB\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n560/1757\nRM0090 Rev 21\n17.3.19 \nTIMx and external trigger synchronization\nThe TIMx timer can be synchronized with an external trigger in several modes: Reset mode, \nGated mode and Trigger mode.\nSlave mode: Reset mode\nThe counter and its prescaler can be reinitialized in response to an event on a trigger input. \nMoreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is \ngenerated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.\nIn the following example, the upcounter is cleared in response to a rising edge on TI1 input:\n•\nConfigure the channel 1 to detect rising edges on TI1. Configure the input filter duration \n(in this example, we don’t need any filter, so we keep IC1F=0000). The capture \nprescaler is not used for triggering, so there’s no need to configure it. The CC1S bits \nselect the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write \nCC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect \nrising edges only).\n•\nConfigure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select \nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\n•\nStart the counter by writing CEN=1 in the TIMx_CR1 register.\nThe counter starts counting on the internal clock, then behaves normally until TI1 rising \nedge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the \ntrigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA \nrequest can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).\nThe following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. \nThe delay between the rising edge on TI1 and the actual reset of the counter is due to the \nresynchronization circuit on TI1 input.\nFigure 130. Control circuit in reset mode\nMS31401V3\nUG\nTI1\n00\nCounter clock = CK_CNT = CK_PSC\nCounter register\n01\n02\n03\n00\n01\n02\n03\n32\n33\n34\n35\n36\n31\n30\nTIF\n\n\n<>\n\nRM0090 Rev 21\n561/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nSlave mode: Gated mode\nThe counter can be enabled depending on the level of a selected input.\nIn the following example, the upcounter counts only when TI1 input is low:\n•\nConfigure the channel 1 to detect low levels on TI1. Configure the input filter duration \n(in this example, we don’t need any filter, so we keep IC1F=0000). The capture \nprescaler is not used for triggering, so the user does not need to configure it. The \nCC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register. \nWrite CC1P=1 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and \ndetect low level only).\n•\nConfigure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select \nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\n•\nEnable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the \ncounter doesn’t start if CEN=0, whatever is the trigger input level).\nThe counter starts counting on the internal clock as long as TI1 is low and stops as soon as \nTI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts \nor stops.\nThe delay between the rising edge on TI1 and the actual stop of the counter is due to the \nresynchronization circuit on TI1 input.\nFigure 131. Control circuit in gated mode\nMS31402V3\nTI1\nCNT_EN\nWrite TIF=0\nCounter clock = ck_cnt = ck_psc\nCounter register\nTIF\n37 38\n32\n33\n34\n35\n36\n31\n30\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n562/1757\nRM0090 Rev 21\nSlave mode: Trigger mode\nThe counter can start in response to an event on a selected input.\nIn the following example, the upcounter starts in response to a rising edge on TI2 input:\n•\nConfigure the channel 2 to detect rising edges on TI2. Configure the input filter duration \n(in this example, we don’t need any filter, so we keep IC2F=0000). The capture \nprescaler is not used for triggering, so there’s no need to configure it. The CC2S bits \nare configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 \nregister. Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity \n(and detect low level only).\n•\nConfigure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select \nTI2 as the input source by writing TS=110 in TIMx_SMCR register.\nWhen a rising edge occurs on TI2, the counter starts counting on the internal clock and the \nTIF flag is set.\nThe delay between the rising edge on TI2 and the actual start of the counter is due to the \nresynchronization circuit on TI2 input.\nFigure 132. Control circuit in trigger mode\nSlave mode: external clock mode 2 + trigger mode\nThe external clock mode 2 can be used in addition to another slave mode (except external \nclock mode 1 and encoder mode). In this case, the ETR signal is used as external clock \ninput, and another input can be selected as trigger input (in reset mode, gated mode or \ntrigger mode). It is recommended not to select ETR as TRGI through the TS bits of \nTIMx_SMCR register.\nIn the following example, the upcounter is incremented at each rising edge of the ETR \nsignal as soon as a rising edge of TI1 occurs:\n1.\nConfigure the external trigger input circuit by programming the TIMx_SMCR register as \nfollows:\n–\nETF = 0000: no filter \n–\nETPS = 00: prescaler disabled\n–\nETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock \nmode 2.\n2. \nConfigure the channel 1 as follows, to detect rising edges on TI: \n–\nIC1F=0000: no filter. \n–\nThe capture prescaler is not used for triggering and does not need to be \nconfigured.\n–\nCC1S=01 in TIMx_CCMR1 register to select only the input capture source\nMS31403V2\nTI2\nCNT_EN\nCounter clock = ck_cnt = ck_psc\nCounter register\nTIF\n37\n38\n34\n35\n36\n\n\n<>\n\nRM0090 Rev 21\n563/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n–\nCC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and \ndetect rising edge only).\n3. \nConfigure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select \nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\nA rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on \nETR rising edges.\nThe delay between the rising edge of the ETR signal and the actual reset of the counter is \ndue to the resynchronization circuit on ETRP input. \nFigure 133. Control circuit in external clock mode 2 + trigger mode\n17.3.20 \nTimer synchronization\nThe TIM timers are linked together internally for timer synchronization or chaining. Refer to \nSection 18.3.15: Timer synchronization for details.\nNote:\nThe clock of the slave timer must be enabled prior to receive events from the master timer, \nand must not be changed on-the-fly while triggers are received from the master timer.\n17.3.21 \nDebug mode\nWhen the microcontroller enters debug mode (Cortex®-M4 with FPU core halted), the TIMx \ncounter either continues to work normally or stops, depending on DBG_TIMx_STOP \nconfiguration bit in DBG module. For more details, refer to Section 38.16.2: Debug support \nfor timers, watchdog, bxCAN and I2C.\nFor safety purposes, when the counter is stopped (DBG_TIMx_STOP = 1 in \nDBGMCU_APBx_FZ register), the outputs are disabled (as if the MOE bit was reset). The \noutputs can either be forced to an inactive state (OSSI bit = 1), or have their control taken \nover by the GPIO controller (OSSI bit = 0) to force them to Hi-Z.\nMS33110V1\n34\n35\n36\nTIF\nCounter register\nCounter clock = CK_CNT = CK_PSC\nETR\nCEN/CNT_EN\nTI1\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n564/1757\nRM0090 Rev 21\n17.4 \nTIM1 and TIM8 registers\nRefer to Section 2.2 for a list of abbreviations used in register descriptions.\nThe peripheral registers must be written by half-words (16 bits) or words (32 bits). Read \naccesses can be done by bytes (8 bits), half-word (16 bits) or words (32 bits).\n17.4.1 \nTIM1 and TIM8 control register 1 (TIMx_CR1)\nAddress offset: 0x00\nReset value: 0x0000\n \n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCKD[1:0]\nARPE\nCMS[1:0]\nDIR\nOPM\nURS\nUDIS\nCEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:10 Reserved, must be kept at reset value.\nBits 9:8 CKD[1:0]: Clock division\nThis bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the \ndead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters \n(ETR, TIx),\n00: tDTS=tCK_INT\n01: tDTS=2*tCK_INT\n10: tDTS=4*tCK_INT\n11: Reserved, do not program this value\nBit 7 ARPE: Auto-reload preload enable\n0: TIMx_ARR register is not buffered\n1: TIMx_ARR register is buffered\nBits 6:5 CMS[1:0]: Center-aligned mode selection\n00: Edge-aligned mode. The counter counts up or down depending on the direction bit \n(DIR).\n01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare \ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set \nonly when the counter is counting down.\n10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare \ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set \nonly when the counter is counting up.\n11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare \ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set \nboth when the counter is counting up or down.\nNote: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as \nthe counter is enabled (CEN=1)\nBit 4 DIR: Direction\n0: Counter used as upcounter\n1: Counter used as downcounter\nNote: This bit is read only when the timer is configured in Center-aligned mode or Encoder \nmode.\nBit 3 OPM: One pulse mode\n0: Counter is not stopped at update event\n1: Counter stops counting at the next update event (clearing the bit CEN)\n\n\n<>\n\nRM0090 Rev 21\n565/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.4.2 \nTIM1 and TIM8 control register 2 (TIMx_CR2)\nAddress offset: 0x04\nReset value: 0x0000\n \n \nBit 2 URS: Update request source\nThis bit is set and cleared by software to select the UEV event sources.\n0: Any of the following events generate an update interrupt or DMA request if enabled. \nThese events can be: \n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\n1: Only counter overflow/underflow generates an update interrupt or DMA request if \nenabled.\nBit 1 UDIS: Update disable\nThis bit is set and cleared by software to enable/disable UEV event generation.\n0: UEV enabled. The Update (UEV) event is generated by one of the following events:\n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\nBuffered registers are then loaded with their preload values.\n1: UEV disabled. The Update event is not generated, shadow registers keep their value \n(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is \nset or if a hardware reset is received from the slave mode controller.\nBit 0 CEN: Counter enable\n0: Counter disabled\n1: Counter enabled\nNote: External clock, gated mode and encoder mode can work only if the CEN bit has been \npreviously set by software. However trigger mode can set the CEN bit automatically by \nhardware.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nOIS4\nOIS3N\nOIS3\nOIS2N\nOIS2\nOIS1N\nOIS1\nTI1S\nMMS[2:0]\nCCDS\nCCUS\nRes.\nCCPC\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 Reserved, must be kept at reset value.\nBit 14 OIS4: Output Idle state 4 (OC4 output)\nrefer to OIS1 bit\nBit 13 OIS3N: Output Idle state 3 (OC3N output)\nrefer to OIS1N bit\nBit 12 OIS3: Output Idle state 3 (OC3 output)\nrefer to OIS1 bit\nBit 11 OIS2N: Output Idle state 2 (OC2N output)\nrefer to OIS1N bit\nBit 10 OIS2: Output Idle state 2 (OC2 output)\nrefer to OIS1 bit\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n566/1757\nRM0090 Rev 21\nBit 9 OIS1N: Output Idle state 1 (OC1N output)\n0: OC1N=0 after a dead-time when MOE=0\n1: OC1N=1 after a dead-time when MOE=0\nNote: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed \n(LOCK bits in TIMx_BDTR register).\nBit 8 OIS1: Output Idle state 1 (OC1 output)\n0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0\n1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0\nNote: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed \n(LOCK bits in TIMx_BDTR register).\nBit 7 TI1S: TI1 selection\n0: The TIMx_CH1 pin is connected to TI1 input\n1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)\nBits 6:4 MMS[2:0]: Master mode selection\nThese bits allow to select the information to be sent in master mode to slave timers for \nsynchronization (TRGO). The combination is as follows:\n000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the \nreset is generated by the trigger input (slave mode controller configured in reset mode) then \nthe signal on TRGO is delayed compared to the actual reset.\n001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is \nuseful to start several timers at the same time or to control a window in which a slave timer is \nenable. The Counter Enable signal is generated by a logic OR between CEN control bit and \nthe trigger input when configured in gated mode. When the Counter Enable signal is \ncontrolled by the trigger input, there is a delay on TRGO, except if the master/slave mode is \nselected (see the MSM bit description in TIMx_SMCR register).\n010: Update - The update event is selected as trigger output (TRGO). For instance a master \ntimer can then be used as a prescaler for a slave timer.\n011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be \nset (even if it was already high), as soon as a capture or a compare match occurred. \n(TRGO).\n100: Compare - OC1REF signal is used as trigger output (TRGO)\n101: Compare - OC2REF signal is used as trigger output (TRGO)\n110: Compare - OC3REF signal is used as trigger output (TRGO)\n111: Compare - OC4REF signal is used as trigger output (TRGO)\nNote: The clock of the slave timer and ADC must be enabled prior to receiving events from \nthe master timer, and must not be changed on-the-fly while triggers are received from \nthe master timer.\nBit 3 CCDS: Capture/compare DMA selection\n0: CCx DMA request sent when CCx event occurs\n1: CCx DMA requests sent when update event occurs\n\n\n<>\n\nRM0090 Rev 21\n567/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nBit 2 CCUS: Capture/compare control update selection\n0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting \nthe COMG bit only\n1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting \nthe COMG bit or when an rising edge occurs on TRGI\nNote: This bit acts only on channels that have a complementary output.\nBit 1 Reserved, must be kept at reset value.\nBit 0 CCPC: Capture/compare preloaded control\n0: CCxE, CCxNE and OCxM bits are not preloaded\n1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated \nonly when a commutation event (COM) occurs (COMG bit set or rising edge detected on \nTRGI, depending on the CCUS bit).\nNote: This bit acts only on channels that have a complementary output.\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n568/1757\nRM0090 Rev 21\n17.4.3 \nTIM1 and TIM8 slave mode control register (TIMx_SMCR)\nAddress offset: 0x08\nReset value: 0x0000\n \n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nETP\nECE\nETPS[1:0]\nETF[3:0]\nMSM\nTS[2:0]\nRes.\nSMS[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nRes.\nrw\nrw\nrw\nBit 15 ETP: External trigger polarity\nThis bit selects whether ETR or ETR is used for trigger operations\n0: ETR is non-inverted, active at high level or rising edge.\n1: ETR is inverted, active at low level or falling edge.\nBit 14 ECE: External clock enable\nThis bit enables External clock mode 2.\n0: External clock mode 2 disabled\n1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF \nsignal.\nNote: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with \nTRGI connected to ETRF (SMS=111 and TS=111).\n2: It is possible to simultaneously use external clock mode 2 with the following slave \nmodes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be \nconnected to ETRF in this case (TS bits must not be 111).\n3: If external clock mode 1 and external clock mode 2 are enabled at the same time, \nthe external clock input is ETRF.\nBits 13:12 ETPS[1:0]: External trigger prescaler\nExternal trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A \nprescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external \nclocks.\n00: Prescaler OFF\n01: ETRP frequency divided by 2\n10: ETRP frequency divided by 4\n11: ETRP frequency divided by 8\n\n\n<>\n\nRM0090 Rev 21\n569/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nBits 11:8 ETF[3:0]: External trigger filter\nThis bit-field then defines the frequency used to sample ETRP signal and the length of the \ndigital filter applied to ETRP. The digital filter is made of an event counter in which N \nconsecutive events are needed to validate a transition on the output:\n0000: No filter, sampling is done at fDTS\n0001: fSAMPLING=fCK_INT, N=2\n0010: fSAMPLING=fCK_INT, N=4\n0011: fSAMPLING=fCK_INT, N=8\n0100: fSAMPLING=fDTS/2, N=6\n0101: fSAMPLING=fDTS/2, N=8\n0110: fSAMPLING=fDTS/4, N=6\n0111: fSAMPLING=fDTS/4, N=8\n1000: fSAMPLING=fDTS/8, N=6\n1001: fSAMPLING=fDTS/8, N=8\n1010: fSAMPLING=fDTS/16, N=5\n1011: fSAMPLING=fDTS/16, N=6\n1100: fSAMPLING=fDTS/16, N=8\n1101: fSAMPLING=fDTS/32, N=5\n1110: fSAMPLING=fDTS/32, N=6\n1111: fSAMPLING=fDTS/32, N=8\nBit 7 MSM: Master/slave mode\n0: No action\n1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect \nsynchronization between the current timer and its slaves (through TRGO). It is useful if we \nwant to synchronize several timers on a single external event.\nBits 6:4 TS[2:0]: Trigger selection\nThis bit-field selects the trigger input to be used to synchronize the counter.\n000: Internal Trigger 0 (ITR0) \n001: Internal Trigger 1 (ITR1)\n010: Internal Trigger 2 (ITR2)\n011: Internal Trigger 3 (ITR3)\n100: TI1 Edge Detector (TI1F_ED)\n101: Filtered Timer Input 1 (TI1FP1)\n110: Filtered Timer Input 2 (TI2FP2)\n111: External Trigger input (ETRF)\nSee Table 95 for more details on ITRx meaning for each Timer.\nNote: These bits must be changed only when they are not used (e.g. when SMS=000) to \navoid wrong edge detections at the transition.\nBit 3 Reserved, must be kept at reset value.\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n570/1757\nRM0090 Rev 21\n \n17.4.4 \nTIM1 and TIM8 DMA/interrupt enable register (TIMx_DIER)\nAddress offset: 0x0C\nReset value: 0x0000\n \nBits 2:0 SMS: Slave mode selection\nWhen external signals are selected the active edge of the trigger signal (TRGI) is linked to \nthe polarity selected on the external input (see Input Control register and Control register \ndescription.\n000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal \nclock.\n001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 \nlevel.\n010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 \nlevel.\n011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges \ndepending on the level of the other input.\n100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter \nand generates an update of the registers.\n101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The \ncounter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of \nthe counter are controlled.\n110: Trigger mode - The counter starts at a rising edge of the trigger TRGI (but it is not \nreset). Only the start of the counter is controlled.\n111: External Clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.\nNote: The gated mode must not be used if TI1F_ED is selected as the trigger input \n(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the \ngated mode checks the level of the trigger signal.\nThe clock of the slave timer must be enabled prior to receiving events from the master \ntimer, and must not be changed on-the-fly while triggers are received from the master \ntimer.\nTable 95. TIMx Internal trigger connection\nSlave TIM\nITR0 (TS = 000)\nITR1 (TS = 001)\nITR2 (TS = 010)\nITR3 (TS = 011)\nTIM1\nTIM5_TRGO\nTIM2_TRGO\nTIM3_TRGO\nTIM4_TRGO\nTIM8\nTIM1_TRGO\nTIM2_TRGO\nTIM4_TRGO\nTIM5_TRGO\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nTDE\nCOMDE CC4DE CC3DE CC2DE CC1DE\nUDE\nBIE\nTIE\nCOMIE\nCC4IE\nCC3IE\nCC2IE\nCC1IE\nUIE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 Reserved, must be kept at reset value.\nBit 14 TDE: Trigger DMA request enable\n0: Trigger DMA request disabled\n1: Trigger DMA request enabled\nBit 13 COMDE: COM DMA request enable\n0: COM DMA request disabled\n1: COM DMA request enabled\n\n\n<>\n\nRM0090 Rev 21\n571/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nBit 12 CC4DE: Capture/Compare 4 DMA request enable\n0: CC4 DMA request disabled\n1: CC4 DMA request enabled\nBit 11 CC3DE: Capture/Compare 3 DMA request enable\n0: CC3 DMA request disabled\n1: CC3 DMA request enabled\nBit 10 CC2DE: Capture/Compare 2 DMA request enable\n0: CC2 DMA request disabled\n1: CC2 DMA request enabled\nBit 9 CC1DE: Capture/Compare 1 DMA request enable\n0: CC1 DMA request disabled\n1: CC1 DMA request enabled\nBit 8 UDE: Update DMA request enable\n0: Update DMA request disabled\n1: Update DMA request enabled\nBit 7 BIE: Break interrupt enable\n0: Break interrupt disabled\n1: Break interrupt enabled\nBit 6 TIE: Trigger interrupt enable\n0: Trigger interrupt disabled\n1: Trigger interrupt enabled\nBit 5 COMIE: COM interrupt enable\n0: COM interrupt disabled\n1: COM interrupt enabled\nBit 4 CC4IE: Capture/Compare 4 interrupt enable\n0: CC4 interrupt disabled\n1: CC4 interrupt enabled\nBit 3 CC3IE: Capture/Compare 3 interrupt enable\n0: CC3 interrupt disabled\n1: CC3 interrupt enabled\nBit 2 CC2IE: Capture/Compare 2 interrupt enable\n0: CC2 interrupt disabled\n1: CC2 interrupt enabled\nBit 1 CC1IE: Capture/Compare 1 interrupt enable\n0: CC1 interrupt disabled\n1: CC1 interrupt enabled\nBit 0 UIE: Update interrupt enable\n0: Update interrupt disabled\n1: Update interrupt enabled\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n572/1757\nRM0090 Rev 21\n17.4.5 \nTIM1 and TIM8 status register (TIMx_SR)\nAddress offset: 0x10\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCC4OF CC3OF CC2OF CC1OF\nRes.\nBIF\nTIF\nCOMIF\nCC4IF\nCC3IF\nCC2IF\nCC1IF\nUIF\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nRes.\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nBits 15:13 Reserved, must be kept at reset value.\nBit 12 CC4OF: Capture/Compare 4 overcapture flag\nrefer to CC1OF description\nBit 11 CC3OF: Capture/Compare 3 overcapture flag\nrefer to CC1OF description\nBit 10 CC2OF: Capture/Compare 2 overcapture flag\nrefer to CC1OF description\nBit 9 CC1OF: Capture/Compare 1 overcapture flag\nThis flag is set by hardware only when the corresponding channel is configured in input \ncapture mode. It is cleared by software by writing it to ‘0’.\n0: No overcapture has been detected.\n1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was \nalready set\nBit 8 Reserved, must be kept at reset value.\nBit 7 BIF: Break interrupt flag\nThis flag is set by hardware as soon as the break input goes active. It can be cleared by \nsoftware if the break input is not active.\n0: No break event occurred.\n1: An active level has been detected on the break input.\nBit 6 TIF: Trigger interrupt flag\nThis flag is set by hardware on trigger event (active edge detected on TRGI input when the \nslave mode controller is enabled in all modes but gated mode. It is set when the counter \nstarts or stops when gated mode is selected. It is cleared by software.\n0: No trigger event occurred.\n1: Trigger interrupt pending.\nBit 5 COMIF: COM interrupt flag\nThis flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, \nCCxNE, OCxM - have been updated). It is cleared by software.\n0: No COM event occurred.\n1: COM interrupt pending.\nBit 4 CC4IF: Capture/Compare 4 interrupt flag\nrefer to CC1IF description\nBit 3 CC3IF: Capture/Compare 3 interrupt flag\nrefer to CC1IF description\n\n\n<>\n\nRM0090 Rev 21\n573/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.4.6 \nTIM1 and TIM8 event generation register (TIMx_EGR)\nAddress offset: 0x14\nReset value: 0x0000\n \nBit 2 CC2IF: Capture/Compare 2 interrupt flag\nrefer to CC1IF description\nBit 1 CC1IF: Capture/Compare 1 interrupt flag\nIf channel CC1 is configured as output:\nThis flag is set by hardware when the counter matches the compare value, with some \nexception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register \ndescription). It is cleared by software.\n0: No match.\n1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. \nWhen the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF \nbit goes high on the counter overflow (in upcounting and up/down-counting modes) or \nunderflow (in downcounting mode)\nIf channel CC1 is configured as input:\nThis bit is set by hardware on a capture. It is cleared by software or by reading the \nTIMx_CCR1 register.\n0: No input capture occurred\n1: The counter value has been captured in TIMx_CCR1 register (An edge has been \ndetected on IC1 which matches the selected polarity)\nBit 0 UIF: Update interrupt flag\nThis bit is set by hardware on an update event. It is cleared by software.\n0: No update occurred.\n1: Update interrupt pending. This bit is set by hardware when the registers are updated:\n– At overflow or underflow regarding the repetition counter value (update if repetition counter \n= 0) and if the UDIS=0 in the TIMx_CR1 register.\n– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and \nUDIS=0 in the TIMx_CR1 register.\n– When CNT is reinitialized by a trigger event (refer to Section 17.4.3: TIM1 and TIM8 slave \nmode control register (TIMx_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBG\nTG\nCOMG\nCC4G\nCC3G\nCC2G\nCC1G\nUG\nw\nw\nw\nw\nw\nw\nw\nw\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 BG: Break generation\nThis bit is set by software in order to generate an event, it is automatically cleared by \nhardware.\n0: No action\n1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or \nDMA transfer can occur if enabled.\nBit 6 TG: Trigger generation\nThis bit is set by software in order to generate an event, it is automatically cleared by \nhardware.\n0: No action\n1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if \nenabled.\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n574/1757\nRM0090 Rev 21\nBit 5 COMG: Capture/Compare control update generation\nThis bit can be set by software, it is automatically cleared by hardware\n0: No action\n1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits\nNote: This bit acts only on channels having a complementary output.\nBit 4 CC4G: Capture/Compare 4 generation\nrefer to CC1G description\nBit 3 CC3G: Capture/Compare 3 generation\nrefer to CC1G description\nBit 2 CC2G: Capture/Compare 2 generation\nrefer to CC1G description\nBit 1 CC1G: Capture/Compare 1 generation\nThis bit is set by software in order to generate an event, it is automatically cleared by \nhardware.\n0: No action\n1: A capture/compare event is generated on channel 1:\nIf channel CC1 is configured as output:\nCC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.\nIf channel CC1 is configured as input:\nThe current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, \nthe corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the \nCC1IF flag was already high.\nBit 0 UG: Update generation\nThis bit can be set by software, it is automatically cleared by hardware.\n0: No action\n1: Reinitialize the counter and generates an update of the registers. Note that the prescaler \ncounter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if \nthe center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload \nvalue (TIMx_ARR) if DIR=1 (downcounting).\n\n\n<>\n\nRM0090 Rev 21\n575/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.4.7 \nTIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1)\nAddress offset: 0x18\nReset value: 0x0000\nThe channels can be used in input (capture mode) or in output (compare mode). The \ndirection of a channel is defined by configuring the corresponding CCxS bits. All the other \nbits of this register have a different function in input and in output mode. For a given bit, \nOCxx describes its function when the channel is configured in output, ICxx describes its \nfunction when the channel is configured in input. So the user must take care that the same \nbit can have a different meaning for the input stage and for the output stage.\n \nOutput compare mode:\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOC2\nCE\nOC2M[2:0]\nOC2\nPE\nOC2\nFE\nCC2S[1:0]\nOC1\nCE\nOC1M[2:0]\nOC1\nPE\nOC1\nFE\nCC1S[1:0]\nIC2F[3:0]\nIC2PSC[1:0]\nIC1F[3:0]\nIC1PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 OC2CE: Output compare 2 clear enable\nBits 14:12 OC2M[2:0]: Output compare 2 mode\nBit 11 OC2PE: Output compare 2 preload enable\nBit 10 OC2FE: Output compare 2 fast enable\nBits 9:8 CC2S[1:0]: Capture/Compare 2 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC2 channel is configured as output\n01: CC2 channel is configured as input, IC2 is mapped on TI2\n10: CC2 channel is configured as input, IC2 is mapped on TI1\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through the TS bit (TIMx_SMCR register)\nNote: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).\nBit 7 OC1CE: Output compare 1 clear enable\nOC1CE: Output compare 1 Clear Enable\n0: OC1Ref is not affected by the ETRF Input\n1: OC1Ref is cleared as soon as a High level is detected on ETRF input\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n576/1757\nRM0090 Rev 21\nBits 6:4 OC1M: Output compare 1 mode\nThese bits define the behavior of the output reference signal OC1REF from which OC1 and \nOC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends \non CC1P and CC1NP bits.\n000: Frozen - The comparison between the output compare register TIMx_CCR1 and the \ncounter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing \nbase).\n001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter \nTIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).\n010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the \ncounter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).\n011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.\n100: Force inactive level - OC1REF is forced low.\n101: Force active level - OC1REF is forced high.\n110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (OC1REF=’1’).\n111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 else \ninactive.\nNote: 1: These bits can not be modified as long as LOCK level 3 has been programmed \n(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in \noutput).\n2: In PWM mode 1 or 2, the OCREF level changes only when the result of the \ncomparison changes or when the output compare mode switches from “frozen” mode \nto “PWM” mode.\n3: On channels having a complementary output, this bit field is preloaded. If the CCPC \nbit is set in the TIMx_CR2 register then the OC1M active bits take the new value from \nthe preloaded bits only when a COM event is generated.\nBit 3 OC1PE: Output compare 1 preload enable\n0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the \nnew value is taken in account immediately.\n1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload \nregister. TIMx_CCR1 preload value is loaded in the active register at each update event.\nNote: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK \nbits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).\nBit 2 OC1FE: Output compare 1 fast enable\nThis bit is used to accelerate the effect of an event on the trigger in input on the CC output.\n0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is \nON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is \n5 clock cycles.\n1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is \nset to the compare level independently from the result of the comparison. Delay to sample \nthe trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if \nthe channel is configured in PWM1 or PWM2 mode.\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: CC1 channel is configured as input, IC1 is mapped on TI2\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).\n\n\n<>\n\nRM0090 Rev 21\n577/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nInput capture mode\n \n17.4.8 \nTIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2)\nAddress offset: 0x1C\nBits 15:12 IC2F: Input capture 2 filter\nBits 11:10 IC2PSC[1:0]: Input capture 2 prescaler\nBits 9:8 CC2S: Capture/Compare 2 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC2 channel is configured as output\n01: CC2 channel is configured as input, IC2 is mapped on TI2\n10: CC2 channel is configured as input, IC2 is mapped on TI1\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an \ninternal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).\nBits 7:4 IC1F[3:0]: Input capture 1 filter\nThis bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied \nto TI1. The digital filter is made of an event counter in which N consecutive events are needed to \nvalidate a transition on the output:\n0000: No filter, sampling is done at fDTS\n0001: fSAMPLING=fCK_INT, N=2\n0010: fSAMPLING=fCK_INT, N=4\n0011: fSAMPLING=fCK_INT, N=8\n0100: fSAMPLING=fDTS/2, N=6\n0101: fSAMPLING=fDTS/2, N=8\n0110: fSAMPLING=fDTS/4, N=6\n0111: fSAMPLING=fDTS/4, N=8\n1000: fSAMPLING=fDTS/8, N=6\n1001: fSAMPLING=fDTS/8, N=8\n1010: fSAMPLING=fDTS/16, N=5\n1011: fSAMPLING=fDTS/16, N=6\n1100: fSAMPLING=fDTS/16, N=8\n1101: fSAMPLING=fDTS/32, N=5\n1110: fSAMPLING=fDTS/32, N=6\n1111: fSAMPLING=fDTS/32, N=8\nBits 3:2 IC1PSC: Input capture 1 prescaler\nThis bit-field defines the ratio of the prescaler acting on CC1 input (IC1).\nThe prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).\n00: no prescaler, capture is done each time an edge is detected on the capture input\n01: capture is done once every 2 events\n10: capture is done once every 4 events\n11: capture is done once every 8 events\nBits 1:0 CC1S: Capture/Compare 1 Selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: CC1 channel is configured as input, IC1 is mapped on TI2\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an \ninternal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n578/1757\nRM0090 Rev 21\nReset value: 0x0000\nRefer to the above CCMR1 register description.\nOutput compare mode\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOC4\nCE\nOC4M[2:0]\nOC4\nPE\nOC4\nFE\nCC4S[1:0]\nOC3\nCE.\nOC3M[2:0]\nOC3\nPE\nOC3\nFE\nCC3S[1:0]\nIC4F[3:0]\nIC4PSC[1:0]\nIC3F[3:0]\nIC3PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 OC4CE: Output compare 4 clear enable\nBits 14:12 OC4M: Output compare 4 mode\nBit 11 OC4PE: Output compare 4 preload enable\nBit 10 OC4FE: Output compare 4 fast enable\nBits 9:8 CC4S: Capture/Compare 4 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC4 channel is configured as output\n01: CC4 channel is configured as input, IC4 is mapped on TI4\n10: CC4 channel is configured as input, IC4 is mapped on TI3\n11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).\nBit 7 OC3CE: Output compare 3 clear enable\nBits 6:4 OC3M: Output compare 3 mode\nBit 3 OC3PE: Output compare 3 preload enable\nBit 2 OC3FE: Output compare 3 fast enable\nBits 1:0 CC3S: Capture/Compare 3 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC3 channel is configured as output\n01: CC3 channel is configured as input, IC3 is mapped on TI3\n10: CC3 channel is configured as input, IC3 is mapped on TI4\n11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).\n\n\n<>\n\nRM0090 Rev 21\n579/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nInput capture mode\n \n17.4.9 \nTIM1 and TIM8 capture/compare enable register (TIMx_CCER)\nAddress offset: 0x20\nReset value: 0x0000\n \nBits 15:12 IC4F: Input capture 4 filter\nBits 11:10 IC4PSC: Input capture 4 prescaler\nBits 9:8 CC4S: Capture/Compare 4 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC4 channel is configured as output\n01: CC4 channel is configured as input, IC4 is mapped on TI4\n10: CC4 channel is configured as input, IC4 is mapped on TI3\n11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).\nBits 7:4 IC3F: Input capture 3 filter\nBits 3:2 IC3PSC: Input capture 3 prescaler\nBits 1:0 CC3S: Capture/compare 3 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC3 channel is configured as output\n01: CC3 channel is configured as input, IC3 is mapped on TI3\n10: CC3 channel is configured as input, IC3 is mapped on TI4\n11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCC4NP\nRes.\nCC4P\nCC4E\nCC3NP CC3NE\nCC3P\nCC3E\nCC2NP CC2NE\nCC2P\nCC2E\nCC1NP CC1NE\nCC1P\nCC1E\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 CC4NP: Capture/Compare 4 complementary output polarity\nrefer to CC1NP description\nBit 14 Reserved, must be kept at reset value.\nBit 13 CC4P: Capture/Compare 4 output polarity\nrefer to CC1P description\nBit 12 CC4E: Capture/Compare 4 output enable\nrefer to CC1E description\nBit 11 CC3NP: Capture/Compare 3 complementary output polarity\nrefer to CC1NP description\nBit 10 CC3NE: Capture/Compare 3 complementary output enable\nrefer to CC1NE description\nBit 9 CC3P: Capture/Compare 3 output polarity\nrefer to CC1P description\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n580/1757\nRM0090 Rev 21\nBit 8 CC3E: Capture/Compare 3 output enable\nrefer to CC1E description\nBit 7 CC2NP: Capture/Compare 2 complementary output polarity\nrefer to CC1NP description\nBit 6 CC2NE: Capture/Compare 2 complementary output enable\nrefer to CC1NE description\nBit 5 CC2P: Capture/Compare 2 output polarity\nrefer to CC1P description\nBit 4 CC2E: Capture/Compare 2 output enable\nrefer to CC1E description\nBit 3 CC1NP: Capture/Compare 1 complementary output polarity\nCC1 channel configured as output:\n0: OC1N active high.\n1: OC1N active low.\nCC1 channel configured as input:\nThis bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer \nto CC1P description.\nNote: On channels having a complementary output, this bit is preloaded. If the CCPC bit is \nset in the TIMx_CR2 register then the CC1NP active bit takes the new value from the \npreloaded bit only when a Commutation event is generated.\nNote: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits \nin TIMx_BDTR register) and CC1S=”00” (the channel is configured in output).\nBit 2 CC1NE: Capture/Compare 1 complementary output enable\n0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N \nand CC1E bits.\n1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, \nOSSR, OIS1, OIS1N and CC1E bits.\nNote: On channels having a complementary output, this bit is preloaded. If the CCPC bit is \nset in the TIMx_CR2 register then the CC1NE active bit takes the new value from the \npreloaded bit only when a Commutation event is generated.\n\n\n<>\n\nRM0090 Rev 21\n581/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nBit 1 CC1P: Capture/Compare 1 output polarity\nCC1 channel configured as output:\n0: OC1 active high\n1: OC1 active low\nCC1 channel configured as input:\nCC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture \noperations.\n00: non-inverted/rising edge\nThe circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external \nclock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder \nmode).\n01: inverted/falling edge\nThe circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external \nclock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder \nmode).\n10: reserved, do not use this configuration.\n11: non-inverted/both edges\nThe circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations \nin reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated \nmode). This configuration must not be used in encoder mode.\nNote: On channels having a complementary output, this bit is preloaded. If the CCPC bit is \nset in the TIMx_CR2 register then the CC1P active bit takes the new value from the \npreloaded bit only when a Commutation event is generated.\nNote: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits \nin TIMx_BDTR register).\nBit 0 CC1E: Capture/Compare 1 output enable\nCC1 channel configured as output:\n0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N \nand CC1NE bits.\n1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, \nOSSR, OIS1, OIS1N and CC1NE bits.\nCC1 channel configured as input:\nThis bit determines if a capture of the counter value can actually be done into the input \ncapture/compare register 1 (TIMx_CCR1) or not.\n0: Capture disabled.\n1: Capture enabled.\nNote: On channels having a complementary output, this bit is preloaded. If the CCPC bit is \nset in the TIMx_CR2 register then the CC1E active bit takes the new value from the \npreloaded bit only when a Commutation event is generated.\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n582/1757\nRM0090 Rev 21\n \nNote:\nThe state of the external I/O pins connected to the complementary OCx and OCxN channels \ndepends on the OCx and OCxN channel state and the GPIO registers.\nTable 96. Output control bits for complementary OCx and OCxN channels with\nbreak feature\nControl bits\nOutput states(1)\nMOE \nbit\nOSSI \nbit\nOSSR \nbit\nCCxE \nbit\nCCxNE \nbit\nOCx output state\nOCxN output state\n1\nX\n0\n0\n0\nOutput Disabled (not driven by \nthe timer), OCx=0, OCx_EN=0\nOutput Disabled (not driven by the \ntimer), OCxN=0, OCxN_EN=0\n0\n0\n1\nOutput Disabled (not driven by \nthe timer), OCx=0, OCx_EN=0\nOCxREF + Polarity OCxN=OCxREF \nxor CCxNP, OCxN_EN=1\n0\n1\n0\nOCxREF + Polarity\nOCx=OCxREF xor CCxP,\nOCx_EN=1\nOutput Disabled (not driven by the \ntimer)\nOCxN=0, OCxN_EN=0\n0\n1\n1\nOCREF + Polarity + dead-time\nOCx_EN=1\nComplementary to OCREF (not \nOCREF) + Polarity + dead-time\nOCxN_EN=1\n1\n0\n0\nOutput Disabled (not driven by \nthe timer)\nOCx=CCxP, OCx_EN=0\nOutput Disabled (not driven by the \ntimer)\nOCxN=CCxNP, OCxN_EN=0\n1\n0\n1\nOff-State (output enabled with \ninactive state)\nOCx=CCxP, OCx_EN=1\nOCxREF + Polarity\nOCxN=OCxREF xor CCxNP, \nOCxN_EN=1\n1\n1\n0\nOCxREF + Polarity\nOCx=OCxREF xor CCxP,\nOCx_EN=1\nOff-State (output enabled with \ninactive state)\nOCxN=CCxNP, OCxN_EN=1\n1\n1\n1\nOCREF + Polarity + dead-time\nOCx_EN=1\nComplementary to OCREF (not \nOCREF) + Polarity + dead-time\nOCxN_EN=1\n0\n0\nX\nX\nX\nOutput disabled (not driven by the timer anymore). The output state is \ndefined by the GPIO controller and can be High, Low or Hi-Z.\n1\n0\n0\n0\n1\nOff-State (output enabled with inactive state)\nAsynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP, \nOCxN_EN=1\nThen if the clock is present: OCx=OISx and OCxN=OISxN after a \ndead-time, assuming that OISx and OISxN do not correspond to OCX \nand OCxN both in active state\n1\n0\n1\n1\n1.\nWhen both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept \ncleared.\n\n\n<>\n\nRM0090 Rev 21\n583/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.4.10 \nTIM1 and TIM8 counter (TIMx_CNT)\nAddress offset: 0x24\nReset value: 0x0000\n \n17.4.11 \nTIM1 and TIM8 prescaler (TIMx_PSC)\nAddress offset: 0x28\nReset value: 0x0000\n \n17.4.12 \nTIM1 and TIM8 auto-reload register (TIMx_ARR)\nAddress offset: 0x2C\nReset value: 0xFFFF\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCNT[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CNT[15:0]: Counter value\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPSC[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 PSC[15:0]: Prescaler value\nThe counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1).\nPSC contains the value to be loaded in the active prescaler register at each update event \n(including when the counter is cleared through UG bit of TIMx_EGR register or through \ntrigger controller when configured in “reset mode”).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nARR[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 ARR[15:0]: Auto-reload value\nARR is the value to be loaded in the actual auto-reload register.\nRefer to Section 17.3.1: Time-base unit for more details about ARR update and behavior.\nThe counter is blocked while the auto-reload value is null.\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n584/1757\nRM0090 Rev 21\n17.4.13 \nTIM1 and TIM8 repetition counter register (TIMx_RCR)\nAddress offset: 0x30\nReset value: 0x0000\n \n17.4.14 \nTIM1 and TIM8 capture/compare register 1 (TIMx_CCR1)\nAddress offset: 0x34\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nREP[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value.\nBits 7:0 REP[7:0]: Repetition counter value\nThese bits allow the user to set-up the update rate of the compare registers (i.e. periodic \ntransfers from preload to active registers) when preload registers are enable, as well as the \nupdate interrupt generation rate, if this interrupt is enable.\nEach time the REP_CNT related downcounter reaches zero, an update event is generated \nand it restarts counting from REP value. As REP_CNT is reloaded with REP value only at \nthe repetition update event U_RC, any write to the TIMx_RCR register is not taken in \naccount until the next repetition update event.\nIt means in PWM mode (REP+1) corresponds to:\n–\nthe number of PWM periods in edge-aligned mode\n–\nthe number of half PWM period in center-aligned mode.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR1[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 15:0 CCR1[15:0]: Capture/Compare 1 value\nIf channel CC1 is configured as output:\nCCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register \n(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when \nan update event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signaled on OC1 output.\nIf channel CC1 is configured as input:\nCCR1 is the counter value transferred by the last input capture 1 event (IC1). The \nTIMx_CCR1 register is read-only and cannot be programmed.\n\n\n<>\n\nRM0090 Rev 21\n585/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.4.15 \nTIM1 and TIM8 capture/compare register 2 (TIMx_CCR2)\nAddress offset: 0x38\nReset value: 0x0000\n \n17.4.16 \nTIM1 and TIM8 capture/compare register 3 (TIMx_CCR3)\nAddress offset: 0x3C\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR2[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 15:0 CCR2[15:0]: Capture/Compare 2 value\nIf channel CC2 is configured as output:\nCCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register \n(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when \nan update event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signalled on OC2 output.\nIf channel CC2 is configured as input:\nCCR2 is the counter value transferred by the last input capture 2 event (IC2). The \nTIMx_CCR2 register is read-only and cannot be programmed.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR3[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 15:0 CCR3[15:0]: Capture/Compare value\nIf channel CC3 is configured as output:\nCCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register \n(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when \nan update event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signalled on OC3 output.\nIf channel CC3 is configured as input:\nCCR3 is the counter value transferred by the last input capture 3 event (IC3). The \nTIMx_CCR3 register is read-only and cannot be programmed.\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n586/1757\nRM0090 Rev 21\n17.4.17 \nTIM1 and TIM8 capture/compare register 4 (TIMx_CCR4)\nAddress offset: 0x40\nReset value: 0x0000\n \n17.4.18 \nTIM1 and TIM8 break and dead-time register (TIMx_BDTR)\nAddress offset: 0x44\nReset value: 0x0000\nNote:\nAs the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on \nthe LOCK configuration, it can be necessary to configure all of them during the first write \naccess to the TIMx_BDTR register.\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR4[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 15:0 CCR4[15:0]: Capture/Compare value\nIf channel CC4 is configured as output:\nCCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register \n(bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when \nan update event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signalled on OC4 output.\nIf channel CC4 is configured as input:\nCCR4 is the counter value transferred by the last input capture 4 event (IC4). The \nTIMx_CCR3 register is read-only and cannot be programmed.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMOE\nAOE\nBKP\nBKE\nOSSR\nOSSI\nLOCK[1:0]\nDTG[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 MOE: Main output enable\nThis bit is cleared asynchronously by hardware as soon as the break input is active. It is set \nby software or automatically depending on the AOE bit. It is acting only on the channels \nwhich are configured in output.\n0: OC and OCN outputs are disabled or forced to idle state.\n1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in \nTIMx_CCER register).\nSee OC/OCN enable description for more details (Section 17.4.9: TIM1 and TIM8 \ncapture/compare enable register (TIMx_CCER)).\nBit 14 AOE: Automatic output enable\n0: MOE can be set only by software\n1: MOE can be set by software or automatically at the next update event (if the break input is \nnot be active)\nNote: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits \nin TIMx_BDTR register).\n\n\n<>\n\nRM0090 Rev 21\n587/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nBit 13 BKP: Break polarity\n0: Break input BRK is active low\n1: Break input BRK is active high\nNote: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits \nin TIMx_BDTR register).\nNote: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.\nBit 12 BKE: Break enable\n0: Break inputs (BRK and CSS clock failure event) disabled\n1; Break inputs (BRK and CSS clock failure event) enabled\nNote: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in \nTIMx_BDTR register).\nNote: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.\nBit 11 OSSR: Off-state selection for Run mode\nThis bit is used when MOE=1 on channels having a complementary output which are \nconfigured as outputs. OSSR is not implemented if no complementary output is implemented \nin the timer.\nSee OC/OCN enable description for more details (Section 17.4.9: TIM1 and TIM8 \ncapture/compare enable register (TIMx_CCER)).\n0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).\n1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 \nor CCxNE=1. Then, OC/OCN enable output signal=1\nNote: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK \nbits in TIMx_BDTR register).\nBit 10 OSSI: Off-state selection for Idle mode\nThis bit is used when MOE=0 on channels configured as outputs.\nSee OC/OCN enable description for more details (Section 17.4.9: TIM1 and TIM8 \ncapture/compare enable register (TIMx_CCER)).\n0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).\n1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or \nCCxNE=1. OC/OCN enable output signal=1)\nNote: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK \nbits in TIMx_BDTR register).\nBits 9:8 LOCK[1:0]: Lock configuration\nThese bits offer a write protection against software errors.\n00: LOCK OFF - No bit is write protected.\n01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 \nregister and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.\n10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER \nregister, as long as the related channel is configured in output through the CCxS bits) as well \nas OSSR and OSSI bits can no longer be written.\n11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in \nTIMx_CCMRx registers, as long as the related channel is configured in output through the \nCCxS bits) can no longer be written.\nNote: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register \nhas been written, their content is frozen until the next reset.\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n588/1757\nRM0090 Rev 21\n17.4.19 \nTIM1 and TIM8 DMA control register (TIMx_DCR)\nAddress offset: 0x48\nReset value: 0x0000\n \nBits 7:0 DTG[7:0]: Dead-time generator setup\nThis bit-field defines the duration of the dead-time inserted between the complementary \noutputs. DT correspond to this duration.\nDTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS.\nDTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS.\nDTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS.\nDTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS.\nExample if TDTS=125ns (8MHz), dead-time possible values are:\n0 to 15875 ns by 125 ns steps,\n16 us to 31750 ns by 250 ns steps,\n32 us to 63us by 1 us steps,\n64 us to 126 us by 2 us steps\nNote: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed \n(LOCK bits in TIMx_BDTR register).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDBL[4:0]\nReserved\nDBA[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:13 Reserved, must be kept at reset value.\nBits 12:8 DBL[4:0]: DMA burst length\nThis 5-bit vector defines the number of DMA transfers (the timer detects a burst transfer \nwhen a read or a write access to the TIMx_DMAR register address is performed). \nthe TIMx_DMAR address)\n00000: 1 transfer\n00001: 2 transfers\n00010: 3 transfers\n...\n10001: 18 transfers\nBits 7:5 Reserved, must be kept at reset value.\nBits 4:0 DBA[4:0]: DMA base address\nThis 5-bits vector defines the base-address for DMA transfers (when read/write access are \ndone through the TIMx_DMAR address). DBA is defined as an offset starting from the \naddress of the TIMx_CR1 register.\nExample:\n00000: TIMx_CR1,\n00001: TIMx_CR2,\n00010: TIMx_SMCR,\n...\nExample: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In \nthis case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.\n\n\n<>\n\nRM0090 Rev 21\n589/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.4.20 \nTIM1 and TIM8 DMA address for full transfer (TIMx_DMAR)\nAddress offset: 0x4C\nReset value: 0x0000 0000\n \nExample of how to use the DMA burst feature\nIn this example the timer DMA burst feature is used to update the contents of the CCRx \nregisters (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers. \nThis is done in the following steps:\n1.\nConfigure the corresponding DMA channel as follows: \n–\nDMA channel peripheral address is the DMAR register address \n–\nDMA channel memory address is the address of the buffer in the RAM containing \nthe data to be transferred by DMA into CCRx registers. \n–\nNumber of data to transfer = 3 (See note below). \n–\nCircular mode disabled. \n2. \nConfigure the DCR register by configuring the DBA and DBL bit fields as follows: \nDBL = 3 transfers, DBA = 0xE. \n3. \nEnable the TIMx update DMA request (set the UDE bit in the DIER register). \n4. \nEnable TIMx \n5. \nEnable the DMA channel\nNote:\nThis example is for the case where every CCRx register to be updated once. If every CCRx \nregister is to be updated twice for example, the number of data to transfer should be 6. Let's \ntake the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and \ndata6. The data is transferred to the CCRx registers as follows: on the first update DMA \nrequest, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to \nCCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is \ntransferred to CCR3 and data6 is transferred to CCR4. \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDMAB[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDMAB[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 DMAB[31:0]: DMA register for burst accesses\nA read or write operation to the DMAR register accesses the register located at the address\n(TIMx_CR1 address) + (DBA + DMA index) x 4 \nwhere TIMx_CR1 address is the address of the control register 1, DBA is the DMA base \naddress configured in TIMx_DCR register, DMA index is automatically controlled by the \nDMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).\n\n\n<>\n\nAdvanced-control timers (TIM1 and TIM8)\nRM0090\n590/1757\nRM0090 Rev 21\n17.4.21 \nTIM1 and TIM8 register map\nTIM1 and TIM8 registers are mapped as 16-bit addressable registers as described in the \ntable below:\n \nTable 97. TIM1 and TIM8 register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nTIMx_CR1\nReserved\nCKD \n[1:0]\nARPE\nCMS\n[1:0]\nDIR\nOPM\nURS\nUDIS\nCEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nTIMx_CR2\nReserved\nOIS4\nOIS3N\nOIS3\nOIS2N\nOIS2\nOIS1N\nOIS1\nTI1S\nMMS[2:0]\nCCDS\nCCUS\nReserved\nCCPC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nTIMx_SMCR\nReserved\nETP\nECE\nETP\nS \n[1:0]\nETF[3:0]\nMSM\nTS[2:0]\nReserved\nSMS[2:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nTIMx_DIER\nReserved\nTDE\nCOMDE\nCC4DE\nCC3DE\nCC2DE\nCC1DE\nUDE\nBIE\nTIE\nCOMIE\nCC4IE\nCC3IE\nCC2IE\nCC1IE\nUIE\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nTIMx_SR\nReserved\nCC4OF\nCC3OF\nCC2OF\nCC1OF\nReserved\nBIF\nTIF\nCOMIF\nCC4IF\nCC3IF\nCC2IF\nCC1IF\nUIF\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nTIMx_EGR\nReserved\nBG\nTG\nCOMG\nCC4G\nCC3G\nCC2G\nCC1G\nUG\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x18\nTIMx_CCMR1\nOutput compare \nmode\nReserved\nOC2CE\nOC2M\n[2:0]\nOC2PE\nOC2FE\nCC2S \n[1:0]\nOC1CE\nOC1M\n[2:0]\nOC1PE\nOC1FE\nCC1\nS \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTIMx_CCMR1\nInput capture \nmode\nReserved\nIC2F[3:0]\nIC2\nPSC\n[1:0]\nCC2S \n[1:0]\nIC1F[3:0]\nIC1\nPSC\n[1:0]\nCC1\nS \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nTIMx_CCMR2\nOutput compare \nmode\nReserved\nOC4CE\nOC4M\n[2:0]\nOC4PE\nOC4FE\nCC4S \n[1:0]\nOC3CE\nOC3M\n[2:0]\nOC3PE\nOC3FE\nCC3\nS \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTIMx_CCMR2\nInput capture \nmode\nReserved\nIC4F[3:0]\nIC4\nPSC\n[1:0]\nCC4S \n[1:0]\nIC3F[3:0]\nIC3\nPSC\n[1:0]\nCC3\nS \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nTIMx_CCER\nReserved\nCC4NP\nReserved\nCC4P\nCC4E\nCC3NP\nCC3NE\nCC3P\nCC3E\nCC2NP\nCC2NE\nCC2P\nCC2E\nCC1NP\nCC1NE\nCC1P\nCC1E\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x24\nTIMx_CNT\nReserved\nCNT[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nTIMx_PSC\nReserved\nPSC[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n\n\n<>\n\nRM0090 Rev 21\n591/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x2C\nTIMx_ARR\nReserved\nARR[15:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x30\nTIMx_RCR\nReserved\nREP[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x34\nTIMx_CCR1\nReserved\nCCR1[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x38\nTIMx_CCR2\nReserved\nCCR2[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x3C\nTIMx_CCR3\nReserved\nCCR3[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x40\nTIMx_CCR4\nReserved\nCCR4[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x44\nTIMx_BDTR\nReserved\nMOE\nAOE\nBKP\nBKE\nOSSR\nOSSI\nLOCK \n[1:0]\nDT[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x48\nTIMx_DCR\nReserved\nDBL[4:0]\nReserved\nDBA[4:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x4C\nTIMx_DMAR\nDMAB[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 97. TIM1 and TIM8 register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n592/1757\nRM0090 Rev 21\n18 \nGeneral-purpose timers (TIM2 to TIM5)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n18.1 \nTIM2 to TIM5 introduction\nThe general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a \nprogrammable prescaler.\nThey may be used for a variety of purposes, including measuring the pulse lengths of input \nsignals (input capture) or generating output waveforms (output compare and PWM).\nPulse lengths and waveform periods can be modulated from a few microseconds to several \nmilliseconds using the timer prescaler and the RCC clock controller prescalers.\nThe timers are completely independent, and do not share any resources. They can be \nsynchronized together as described in Section 18.3.15.\n18.2 \nTIM2 to TIM5 main features\nGeneral-purpose TIMx timer features include:\n•\n16-bit (TIM3 and TIM4) or 32-bit (TIM2 and TIM5) up, down, up/down auto-reload \ncounter.\n•\n16-bit programmable prescaler used to divide (also “on the fly”) the counter clock \nfrequency by any factor between 1 and 65536.\n•\nUp to four independent channels for:\n–\nInput capture\n–\nOutput compare\n–\nPWM generation (Edge- and Center-aligned modes)\n–\nOne-pulse mode output\n•\nSynchronization circuit to control the timer with external signals and to interconnect \nseveral timers.\n•\nInterrupt/DMA generation on the following events:\n–\nUpdate: counter overflow/underflow, counter initialization (by software or \ninternal/external trigger)\n–\nTrigger event (counter start, stop, initialization or count by internal/external trigger)\n–\nInput capture\n–\nOutput compare\n•\nSupports incremental (quadrature) encoder and hall-sensor circuitry for positioning \npurposes\n•\nTrigger input for external clock or cycle-by-cycle current management\n\n\n<>\n\nRM0090 Rev 21\n593/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFigure 134. General-purpose timer block diagram\nU\nU\nU\nCC1I\nCC2I\nTrigger\ncontroller\n+/-\nStop, clear or up/down\nTI1FP1\nTI2FP2\nITR0\nITR1\nITR2\nTRGI\nOutput\ncontrol\nTRGO\nOC1REF\nOC2REF\nU\nUI\nReset, enable, up, count\nCK_PSC\nIC1\nIC2\nIC2PS\nIC1PS\nTI1FP1\nTGI\nTRC\nTRC\nITR\nTRC\nTI1F_ED\nCC1I\nCC2I\nTI1FP2\nTI2FP1\nTI2FP2\nTI1\nTI2\nTIMx_CH1\nTIMx_CH2\nOC1\nOC2\nTIMx_CH2\nTIMx_CH1\nto other timers\nto DAC/ADC\nSlave \ncontroller \nmode\nPSC\nprescaler\nCNT counter\nInternal clock (CK_INT)\nCK_CNT\nTIMxCLK from RCC\nITR3\nMS19673V1\nXOR\nInput filter & \nedge detector\n \nCapture/Compare 1 register\nNotes:\nReg\nPreload registers transferred\nto active registers on U event\naccording to control bit\nEvent\nInterrupt & DMA output\nAuto-reload register\nCapture/Compare 2 register\nPrescaler\nPrescaler\nInput filter & \nedge detector\nOutput\ncontrol\nU\nU\nCC3I\nCC4I\nOutput\ncontrol\nOC3REF\nOC4REF\nIC3\nIC4\nIC4PS\nIC3PS\nTI4FP3\nTI4FP4\nTIMx_CH3\nTIMx_CH4\nOC3\nOC4\nTIMx_CH4\nTIMx_CH3\nInput filter & \nedge detector\n \nCapture/Compare 3 register\nCapture/Compare 4 register\nPrescaler\nPrescaler\nInput filter & \nedge detector\nOutput\ncontrol\nTRC\nTI3FP3\nTI3FP4\nTRC\nCC3I\nCC4I\nTI3\nTI4\nEncoder\ninterface\nTIMx_ETR\nInput filter\nPolarity selection & edge\ndetector & prescaler\nETR\nETRP\nETRF\nETRF\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n594/1757\nRM0090 Rev 21\n18.3 \nTIM2 to TIM5 functional description\n18.3.1 \nTime-base unit\nThe main block of the programmable timer is a 16-bit/32-bit counter with its related auto-\nreload register. The counter can count up. The counter clock can be divided by a prescaler. \nThe counter, the auto-reload register and the prescaler register can be written or read by \nsoftware. This is true even when the counter is running.\nThe time-base unit includes:\n•\nCounter register (TIMx_CNT)\n•\nPrescaler register (TIMx_PSC):\n•\nAuto-Reload register (TIMx_ARR)\nThe auto-reload register is preloaded. Writing to or reading from the auto-reload register \naccesses the preload register. The content of the preload register are transferred into the \nshadow register permanently or at each update event (UEV), depending on the auto-reload \npreload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter \nreaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the \nTIMx_CR1 register. It can also be generated by software. The generation of the update \nevent is described in detail for each configuration.\nThe counter is clocked by the prescaler output CK_CNT, which is enabled only when the \ncounter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller \ndescription to get more details on counter enabling).\nNote that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN. \nPrescaler description\nThe prescaler can divide the counter clock frequency by any factor between 1 and 65536. It \nis based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC \nregister). It can be changed on the fly as this control register is buffered. The new prescaler \nratio is taken into account at the next update event.\nFigure 135 and Figure 136 give some examples of the counter behavior when the prescaler \nratio is changed on the fly:\n\n\n<>\n\nRM0090 Rev 21\n595/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFigure 135. Counter timing diagram with prescaler division change from 1 to 2\nFigure 136. Counter timing diagram with prescaler division change from 1 to 4\n18.3.2 \nCounter modes\nUpcounting mode\nIn upcounting mode, the counter counts from 0 to the auto-reload value (content of the \nTIMx_ARR register), then restarts from 0 and generates a counter overflow event.\nAn Update event can be generated at each counter overflow or by setting the UG bit in the \nTIMx_EGR register (by software or by using the slave mode controller). \nThe UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. \nThis is to avoid updating the shadow registers while writing new values in the preload \nregisters. Then no update event occurs until the UDIS bit has been written to 0. However, \nthe counter restarts from 0, as well as the counter of the prescaler (but the prescale rate \nMS35833V1\nCK_PSC\n00\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\n0\nPrescaler control register\n1\n0\nWrite a new value in TIMx_PSC\nPrescaler buffer\n1\n0\nPrescaler counter\n0\n1\n0\n1\n0\n1\n0\n1\n01\n02\n03\nFA FB\nF7\nF8\nF9\nFC\nMS35834V1\n0\n3\n0\n0\n1\n2\n3\n0\n1\n2\n3\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nPrescaler control register\nWrite a new value in TIMx_PSC\nPrescaler buffer\nPrescaler counter\n00\n01\nFA FB\nF7\nF8\nF9\nFC\n3\n0\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n596/1757\nRM0090 Rev 21\ndoes not change). In addition, if the URS bit (update request selection) in TIMx_CR1 \nregister is set, setting the UG bit generates an update event UEV but without setting the UIF \nflag (thus no interrupt or DMA request is sent). This is to avoid generating both update and \ncapture interrupts when clearing the counter on the capture event.\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in \nTIMx_SR register) is set (depending on the URS bit):\n•\nThe buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC \nregister)\n•\nThe auto-reload shadow register is updated with the preload value (TIMx_ARR)\nThe following figures show some examples of the counter behavior for different clock \nfrequencies when TIMx_ARR=0x36.\nFigure 137. Counter timing diagram, internal clock divided by 1\nFigure 138. Counter timing diagram, internal clock divided by 2\n00\n02\n03\n04\n05\n06\n07\n33\n34\n35\n36\n31\nMS35836V1\nCK_INT\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n01\n32\nMS35835V1\nCK_INT\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n0034\n0035\n0036\n0000\n0001\n0002\n0003\n\n\n<>\n\nRM0090 Rev 21\n597/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFigure 139. Counter timing diagram, internal clock divided by 4\nFigure 140. Counter timing diagram, internal clock divided by N\n0000\n0001\n0035\n0036\nMSv37301V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\nCNT_EN\nMSv37302V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n1F\n20\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n598/1757\nRM0090 Rev 21\nFigure 141. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not \npreloaded)\nFigure 142. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR \npreloaded)\nDowncounting mode\nIn downcounting mode, the counter counts from the auto-reload value (content of the \nTIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a \ncounter underflow event.\nAn Update event can be generate at each counter underflow or by setting the UG bit in the \nTIMx_EGR register (by software or by using the slave mode controller) \nThe UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 \nregister. This is to avoid updating the shadow registers while writing new values in the \nFF\n36\nMSv37303V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n02 03\n04 05 06 07\n32\n33 34 35 36\n31\n01\nCNT_EN\nAuto-reload register\nWrite a new value in TIMx_ARR\nMSv37304V1\nF5\n36\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n02 03 04\n05 06\n07\nF1 F2 F3 F4 F5\nF0\n01\nCNT_EN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\nAuto-reload shadow register\nF5\n36\n\n\n<>\n\nRM0090 Rev 21\n599/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\npreload registers. Then no update event occurs until UDIS bit has been written to 0. \nHowever, the counter restarts from the current auto-reload value, whereas the counter of the \nprescaler restarts from 0 (but the prescale rate does not change). \nIn addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the \nUG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or \nDMA request is sent). This is to avoid generating both update and capture interrupts when \nclearing the counter on the capture event.\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in \nTIMx_SR register) is set (depending on the URS bit):\n•\nThe buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC \nregister).\n•\nThe auto-reload active register is updated with the preload value (content of the \nTIMx_ARR register). Note that the auto-reload is updated before the counter is \nreloaded, so that the next period is the expected one.\nThe following figures show some examples of the counter behavior for different clock \nfrequencies when TIMx_ARR=0x36.\nFigure 143. Counter timing diagram, internal clock divided by 1\n36\n34\n33\n32\n31\n30\n2F\n04\n03 02\n01\n00\n05\nMSv37305V1\nCK_INT\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow (cnt_udf) \nUpdate interrupt flag (UIF)\n35\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n600/1757\nRM0090 Rev 21\nFigure 144. Counter timing diagram, internal clock divided by 2\nFigure 145. Counter timing diagram, internal clock divided by 4\nFigure 146. Counter timing diagram, internal clock divided by N\nMSv37306V1\nCK_INT\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow\nUpdate interrupt flag (UIF)\n0002\n0001\n0000\n0036\n0035\n0034\n0033\nMS40511V1\n0036\n0035\n0001\n0000\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow\nUpdate interrupt flag (UIF)\nCNT_EN\nMS37340V1\n00\n1F\n20\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n36\n\n\n<>\n\nRM0090 Rev 21\n601/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFigure 147. Counter timing diagram, Update event\nCenter-aligned mode (up/down counting)\nIn center-aligned mode, the counter counts from 0 to the auto-reload value (content of the \nTIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-\nreload value down to 1 and generates a counter underflow event. Then it restarts counting \nfrom 0.\nCenter-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to \n'00'. The Output compare interrupt flag of channels configured in output is set when: the \ncounter counts down (Center aligned mode 1, CMS = \"01\"), the counter counts up (Center \naligned mode 2, CMS = \"10\") the counter counts up and down (Center aligned mode 3, \nCMS = \"11\").\nIn this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated \nby hardware and gives the current direction of the counter.\nThe update event can be generated at each counter overflow and at each counter underflow \nor by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode \ncontroller) also generates an update event. In this case, the counter restarts counting from \n0, as well as the counter of the prescaler.\nThe UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 \nregister. This is to avoid updating the shadow registers while writing new values in the \npreload registers. Then no update event occurs until the UDIS bit has been written to 0. \nHowever, the counter continues counting up and down, based on the current auto-reload \nvalue.\nIn addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the \nUG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or \nDMA request is sent). This is to avoid generating both update and capture interrupt when \nclearing the counter on the capture event.\nMS37341V1\nFF\n36\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n01\nCNT_EN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\n00\n36\n05\n04\n03\n02\n35 34\n33\n32\n31 30\n2F\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n602/1757\nRM0090 Rev 21\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in \nTIMx_SR register) is set (depending on the URS bit):\n•\nThe buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC \nregister).\n•\nThe auto-reload active register is updated with the preload value (content of the \nTIMx_ARR register). Note that if the update source is a counter overflow, the auto-\nreload is updated before the counter is reloaded, so that the next period is the expected \none (the counter is loaded with the new value).\nThe following figures show some examples of the counter behavior for different clock \nfrequencies.\nFigure 148. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6\n1.\nHere, center-aligned mode 1 is used, for more details refer to Section 18.4.1: TIMx control register 1 (TIMx_CR1).\nFigure 149. Counter timing diagram, internal clock divided by 2\nMS37342V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\nCNT_EN\nCounter underflow\n00\n02\n03\n04\n05 06\n01\n02 03 04\n01\n05\n03\n04\nMS37343V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nCNT_EN\nCounter underflow\n0003\n0002\n0001\n0000\n0001\n0002\n0003\n\n\n<>\n\nRM0090 Rev 21\n603/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFigure 150. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36\n1.\nCenter-aligned mode 2 or 3 is used with an UIF on overflow.\nFigure 151. Counter timing diagram, internal clock divided by N\nMS37344V1\n0034\n0035\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow (cnt_ovf)\nUpdate interrupt flag (UIF)\nCNT_EN\n0036\n0035\nMS37345V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nCounter underflow\n00\n1F\n20\n01\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n604/1757\nRM0090 Rev 21\nFigure 152. Counter timing diagram, Update event with ARPE=1 (counter underflow)\nFigure 153. Counter timing diagram, Update event with ARPE=1 (counter overflow)\nMS37360V1\nFD\n36\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow\nUpdate interrupt flag (UIF)\n00\n02 03 04 05 06\n07\n01\nCNT_EN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\n06\n05\n04 03 02 01\nFD\n36\nAuto-reload active register\nMS37361V1\nFD\n36\nCK_INT\nTimer clock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n36\n34 33 32\n31 30 2F\nF8\nF9 FA FB FC\nF7\n35\nCNT_EN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\nAuto-reload active register\nFD\n36\n\n\n<>\n\nRM0090 Rev 21\n605/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n18.3.3 \nClock selection\nThe counter clock can be provided by the following clock sources:\n•\nInternal clock (CK_INT)\n•\nExternal clock mode1: external input pin (TIx)\n•\nExternal clock mode2: external trigger input (ETR) available on TIM2, TIM3 and TIM4 \nonly.\n•\nInternal trigger inputs (ITRx): using one timer as prescaler for another timer, for \nexample, Timer3 can be configured to act as a prescaler for Timer 2. Refer to Using \none timer as prescaler for another timer for more details.\nInternal clock source (CK_INT)\nIf the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the \nCEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual \ncontrol bits and can be changed only by software (except UG which remains cleared \nautomatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal \nclock CK_INT.\nFigure 154 shows the behavior of the control circuit and the upcounter in normal mode, \nwithout prescaler.\nFigure 154. Control circuit in normal mode, internal clock divided by 1\nExternal clock source mode 1\nThis mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at \neach rising or falling edge on a selected input.\nInternal clock\nCounter clock = CK_CNT = CK_PSC\nCounter register\nCEN=CNT_EN\nUG\nCNT_INIT\nMS31085V2\n00\n02\n03\n04\n05\n06\n07\n3 2\n33\n34\n35 36\n31\n01\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n606/1757\nRM0090 Rev 21\nFigure 155. TI2 external clock connection example\nFor example, to configure the upcounter to count in response to a rising edge on the TI2 \ninput, use the following procedure:\n1.\nConfigure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the \nTIMx_CCMR1 register.\n2. \nConfigure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 \nregister (if no filter is needed, keep IC2F=0000).\nNote:\nThe capture prescaler is not used for triggering, so there’s no need to configure it.\n3. \nSelect rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER \nregister.\n4. \nConfigure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR \nregister. \n5. \nSelect TI2 as the input source by writing TS=110 in the TIMx_SMCR register.\n6. \nEnable the counter by writing CEN=1 in the TIMx_CR1 register.\nWhen a rising edge occurs on TI2, the counter counts once and the TIF flag is set.\nThe delay between the rising edge on TI2 and the actual clock of the counter is due to the \nresynchronization circuit on TI2 input.\nExternal clock\nmode 1 \nInternal clock\nmode\nTRGI\nCK_INT\nCK_PSC\nTIMx_SMCR\nSMS[2:0]\nITRx\nTI1_ED\nTI1FP1\nTI2FP2\nTIMx_SMCR\nTS[2:0]\nTI2\n0\n1\nTIMx_CCER\nCC2P\nFilter\nICF[3:0]\nTIMx_CCMR1\nEdge\ndetector\nTI2F_Rising\nTI2F_Falling\n110\n0xx\n100\n101\nMS31196V1\n(internal clock)\nTI1F\nor\nTI2F\nor\nor\nEncoder\nmode \nETRF\n111\nExternal clock\nmode 2 \nETRF\nECE\n\n\n<>\n\nRM0090 Rev 21\n607/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFigure 156. Control circuit in external clock mode 1\nExternal clock source mode 2\nThis mode is selected by writing ECE=1 in the TIMx_SMCR register.\nThe counter can count at each rising or falling edge on the external trigger input ETR.\nFigure 157 gives an overview of the external trigger input block.\nFigure 157. External trigger input block\nFor example, to configure the upcounter to count each 2 rising edges on ETR, use the \nfollowing procedure:\n1.\nAs no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.\n2. \nSet the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register \n3. \nSelect rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR \nregister\n4. \nEnable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.\n5. \nEnable the counter by writing CEN=1 in the TIMx_CR1 register.\nThe counter counts once each 2 ETR rising edges.\nCounter clock = CK_CNT = CK_PSC\nCounter register\n35\n36\n34\nTI2\nCNT_EN\nTIF\nWrite TIF=0\nMS31087V2\nMS37365V1\nTRGI\nCK_INT\nTIMx_SMCR\nSMS[2:0]\n(internal clock)\nTI1F\nor\nTI2F\nor\nor\nEncoder\nmode \nETRF\nECE\n0\n1\nTIMx_SMCR\nETP\nETR pin\nETR\nDivider\n/1, /2, /4, /8\nFilter\ndowncounter\nCK_INT\nETRP\nTIMx_SMCR\nETPS[1:0]\nTIMx_SMCR\nETF[3:0]\nExternal clock \nmode 1\nExternal clock \nmode 2\nInternal clock \nmode\nCK_PSC\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n608/1757\nRM0090 Rev 21\nThe delay between the rising edge on ETR and the actual clock of the counter is due to the \nresynchronization circuit on the ETRP signal.\nFigure 158. Control circuit in external clock mode 2\n18.3.4 \nCapture/compare channels\nEach Capture/Compare channel (see Figure 159) is built around a capture/compare register \n(including a shadow register), an input stage for capture (with digital filter, multiplexing and \nprescaler) and an output stage (with comparator and output control).\nThe input stage samples the corresponding TIx input to generate a filtered signal TIxF. \nThen, an edge detector with polarity selection generates a signal (TIxFPx) which can be \nused as trigger input by the slave mode controller or as the capture command. It is \nprescaled before the capture register (ICxPS).\nFigure 159. Capture/compare channel (example: channel 1 input stage)\nThe output stage generates an intermediate waveform which is then used for reference: \nOCxRef (active high). The polarity acts at the end of the chain.\nMS37362V1\n34\n35\n36\nCNT_EN\nETR\nETRP\nETRF\nCounter clock = CK_INT =CK_PSC\nCounter register\nCK_INT\nTI1\nTIMx_CCER\nCC1P/CC1NP\ndivider\n/1, /2, /4, /8\nICPS[1:0]\nTI1F_ED\nfilter\nICF[3:0]\ndowncounter\nTIMx_CCMR1\nEdge\nDetector\nTI1F_Rising\nTI1F_Falling\nto the slave mode controller\nTI1FP1\n11\n01\nTIMx_CCMR1\nCC1S[1:0]\nIC1\nTI2FP1\nTRC\n(from channel 2)\n(from slave mode\ncontroller)\n10\nfDTS\nTIMx_CCER\nCC1E\nIC1PS\nTI1F\nTI2F_rising\nTI2F_falling\n(from channel 2)\n\n\n<>\n\nRM0090 Rev 21\n609/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFigure 160. Capture/compare channel 1 main circuit\nFigure 161. Output stage of capture/compare channel (channel 1)\nThe capture/compare block is made of one preload register and one shadow register. Write \nand read always access the preload register. \nIn capture mode, captures are actually done in the shadow register, which is copied into the \npreload register. \nIn compare mode, the content of the preload register is copied into the shadow register \nwhich is compared to the counter.\nCC1E\nCapture/compare shadow register\nComparator\nCapture/compare preload register\nCounter\nIC1PS\nCC1S[0]\nCC1S[1]\nCapture\nInput \nmode\nS\nR\nRead CCR1H\nRead CCR1L\nread_in_progress\ncapture_transfer\nCC1S[0]\nCC1S[1]\nS\nR\nwrite CCR1H\nwrite CCR1L\nwrite_in_progress\nOutput \nmode\nUEV\nOC1PE\n(from time\nbase unit)\ncompare_transfer\nAPB Bus\n8\n8\nhigh\nlow\n(if 16-bit)\nMCU-peripheral interface\nTIMx_CCMR1\nOC1PE\nCNT>CCR1\nCNT=CCR1\nTIMx_EGR\nCC1G\nMS33144V1\nOutput mode\nTIMx_CNT > TIMx_CCR1\ncontroller\nTIMx_CCMR1\nOC1M[2:0]\noc1ref\n0\n1\nTIMx_CCER\nOutput\nEnable\nCircuit\nOC1\nTIMx_CCER\nTo the master mode\ncontroller\nETRF\nai17187b\nCC1P\nCC1E\nTIMx_CNT = TIMx_CCR1\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n610/1757\nRM0090 Rev 21\n18.3.5 \nInput capture mode\nIn Input capture mode, the Capture/Compare registers (TIMx_CCRx) are used to latch the \nvalue of the counter after a transition detected by the corresponding ICx signal. When a \ncapture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or \na DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was \nalready high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be \ncleared by software by writing it to 0 or by reading the captured data stored in the \nTIMx_CCRx register. CCxOF is cleared when written to 0.\nThe following example shows how to capture the counter value in TIMx_CCR1 when TI1 \ninput rises. To do this, use the following procedure:\n•\nSelect the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S \nbits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, \nthe channel is configured in input and the TIMx_CCR1 register becomes read-only.\n•\nProgram the needed input filter duration with respect to the signal connected to the \ntimer (by programming the ICxF bits in the TIMx_CCMRx register if the input is one of \nthe TIx inputs). Let’s imagine that, when toggling, the input signal is not stable during at \nmust five internal clock cycles. We must program a filter duration longer than these five \nclock cycles. We can validate a transition on TI1 when eight consecutive samples with \nthe new level have been detected (sampled at fDTS frequency). Then write IC1F bits to \n0011 in the TIMx_CCMR1 register.\n•\nSelect the edge of the active transition on the TI1 channel by writing the CC1P and \nCC1NP bits to 00 in the TIMx_CCER register (rising edge in this case).\n•\nProgram the input prescaler. In our example, we wish the capture to be performed at \neach valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the \nTIMx_CCMR1 register).\n•\nEnable capture from the counter into the capture register by setting the CC1E bit in the \nTIMx_CCER register.\n•\nIf needed, enable the related interrupt request by setting the CC1IE bit in the \nTIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the \nTIMx_DIER register.\nWhen an input capture occurs:\n•\nThe TIMx_CCR1 register gets the value of the counter on the active transition.\n•\nCC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures \noccurred whereas the flag was not cleared.\n•\nAn interrupt is generated depending on the CC1IE bit.\n•\nA DMA request is generated depending on the CC1DE bit.\nIn order to handle the overcapture, it is recommended to read the data before the \novercapture flag. This is to avoid missing an overcapture which could happen after reading \nthe flag and before reading the data.\nNote:\nIC interrupt and/or DMA requests can be generated by software by setting the \ncorresponding CCxG bit in the TIMx_EGR register.\n\n\n<>\n\nRM0090 Rev 21\n611/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n18.3.6 \nPWM input mode\nThis mode is a particular case of input capture mode. The procedure is the same except:\n•\nTwo ICx signals are mapped on the same TIx input.\n•\nThese 2 ICx signals are active on edges with opposite polarity.\n•\nOne of the two TIxFP signals is selected as trigger input and the slave mode controller \nis configured in reset mode.\nFor example, the user can measure the period (in TIMx_CCR1 register) and the duty cycle \n(in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure \n(depending on CK_INT frequency and prescaler value):\n•\nSelect the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 \nregister (TI1 selected).\n•\nSelect the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter \nclear): write the CC1P to ‘0’ and the CC1NP bit to ‘0’ (active on rising edge).\n•\nSelect the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 \nregister (TI1 selected).\n•\nSelect the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P \nbit to ‘1’ and the CC2NP bit to ’0’(active on falling edge).\n•\nSelect the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register \n(TI1FP1 selected).\n•\nConfigure the slave mode controller in reset mode: write the SMS bits to 100 in the \nTIMx_SMCR register.\n•\nEnable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register.\nFigure 162. PWM input mode timing\nTI1\nTIMx_CNT\n0000\n0001\n0002\n0003\n0004\n0000\n0004\nTIMx_CCR1\nTIMx_CCR2\n0004\n0002\nIC1 capture\nIC2 capture\nreset counter\nIC2 capture\npu\nl se wid th\n \nIC1 capture\nperiod\nmeasurement\nmeasurement\nai15413\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n612/1757\nRM0090 Rev 21\n18.3.7 \nForced output mode\nIn output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal \n(OCxREF and then OCx) can be forced to active or inactive level directly by software, \nindependently of any comparison between the output compare register and the counter.\nTo force an output compare signal (ocxref/OCx) to its active level, the user just needs to \nwrite 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is \nforced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity \nbit.\ne.g.: CCxP=0 (OCx active high) => OCx is forced to high level.\nocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx \nregister.\nAnyway, the comparison between the TIMx_CCRx shadow register and the counter is still \nperformed and allows the flag to be set. Interrupt and DMA requests can be sent \naccordingly. This is described in the next section.\n18.3.8 \nOutput compare mode\nThis function is used to control an output waveform or indicating when a period of time has \nelapsed.\nWhen a match is found between the capture/compare register and the counter, the output \ncompare function: \n•\nAssigns the corresponding output pin to a programmable value defined by the output \ncompare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP \nbit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set \nactive (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.\n•\nSets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).\n•\nGenerates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the \nTIMx_DIER register).\n•\nSends a DMA request if the corresponding enable bit is set (CCxDE bit in the \nTIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request \nselection).\nThe TIMx_CCRx registers can be programmed with or without preload registers using the \nOCxPE bit in the TIMx_CCMRx register.\nIn output compare mode, the update event UEV has no effect on ocxref and OCx output. \nThe timing resolution is one count of the counter. Output compare mode can also be used to \noutput a single pulse (in One-pulse mode).\nProcedure:\n1.\nSelect the counter clock (internal, external, prescaler).\n2. \nWrite the desired data in the TIMx_ARR and TIMx_CCRx registers.\n3. \nSet the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be \ngenerated.\n4. \nSelect the output mode. For example, the user must write OCxM=011, OCxPE=0, \nCCxP=0 and CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx \npreload is not used, OCx is enabled and active high.\n5. \nEnable the counter by setting the CEN bit in the TIMx_CR1 register.\n\n\n<>\n\nRM0090 Rev 21\n613/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nThe TIMx_CCRx register can be updated at any time by software to control the output \nwaveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx \nshadow register is updated only at the next update event UEV). An example is given in \nFigure 163.\nFigure 163. Output compare mode, toggle on OC1\n18.3.9 \nPWM mode\nPulse width modulation mode allows generating a signal with a frequency determined by the \nvalue of the TIMx_ARR register and a duty cycle determined by the value of the \nTIMx_CCRx register.\nThe PWM mode can be selected independently on each channel (one PWM per OCx \noutput) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the \nTIMx_CCMRx register. The user must enable the corresponding preload register by setting \nthe OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register \nby setting the ARPE bit in the TIMx_CR1 register.\nAs the preload registers are transferred to the shadow registers only when an update event \noccurs, before starting the counter, the user has to initialize all the registers by setting the \nUG bit in the TIMx_EGR register.\nOCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It \ncan be programmed as active high or active low. OCx output is enabled by the CCxE bit in \nthe TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.\nIn PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine \nwhether TIMx_CCRx≤TIMx_CNT or TIMx_CNT≤TIMx_CCRx (depending on the direction of \nthe counter). However, to comply with the ETRF (OCREF can be cleared by an external \nevent through the ETR signal until the next PWM period), the OCREF signal is asserted \nonly:\n•\nWhen the result of the comparison changes, or\n•\nWhen the output compare mode (OCxM bits in TIMx_CCMRx register) switches from \nthe “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes \n(OCxM=‘110 or ‘111).\nThis forces the PWM by software while the timer is running.\nMS37363V1\nOC1REF = OC1\nTIMx_CNT\nB200\nB201\n0039\nTIMx_CCR1\n003A\nWrite B201h in the CC1R register\nMatch detected on CCR1\nInterrupt generated if enabled\n003B\nB201\n003A\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n614/1757\nRM0090 Rev 21\nThe timer is able to generate PWM in edge-aligned mode or center-aligned mode \ndepending on the CMS bits in the TIMx_CR1 register.\nPWM edge-aligned mode\nUpcounting configuration\nUpcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting \nmode.\nIn the following example, we consider PWM mode 1. The reference PWM signal OCxREF is \nhigh as long as TIMx_CNT TIMx_CCRx else \nit becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in \nTIMx_ARR, then ocxref is held at ‘1. 0% PWM is not possible in this mode.\nPWM center-aligned mode\nCenter-aligned mode is active when the CMS bits in TIMx_CR1 register are different from \n‘00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The \ncompare flag is set when the counter counts up, when it counts down or both when it counts \nMS31093V1\nCounter register\n‘1’\n0\n1\n2\n3\n4\n5\n6\n7\n8\n0\n1\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nCCRx=4\nCCRx=8\nCCRx>8\nCCRx=0\n‘0’\n\n\n<>\n\nRM0090 Rev 21\n615/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nup and down depending on the CMS bits configuration. The direction bit (DIR) in the \nTIMx_CR1 register is updated by hardware and must not be changed by software. Refer to \nCenter-aligned mode (up/down counting).\nFigure 165 shows some center-aligned PWM waveforms in an example where:\n•\nTIMx_ARR=8,\n•\nPWM mode is the PWM mode 1,\n•\nThe flag is set when the counter counts down corresponding to the center-aligned \nmode 1 selected for CMS=01 in TIMx_CR1 register.\nFigure 165. Center-aligned PWM waveforms (ARR=8)\nHints on using center-aligned mode:\n•\nWhen starting in center-aligned mode, the current up-down configuration is used. It \nmeans that the counter counts up or down depending on the value written in the DIR bit \nCCxIF\n0\n1\n2\n3\n4\n5\n6\n7\n8\n7\n6\n5\n4\n3\n2\n1\n0\n1\nCounter register\nCCRx = 4\nOCxREF\nCMS=01\nCMS=10\nCMS=11\nCCxIF\nCCRx = 7\nOCxREF\nCMS=10 or 11\nCCxIF\nCCRx = 8\nOCxREF\nCMS=01\nCMS=10\nCMS=11\n'1'\nCCxIF\nCCRx > 8\nOCxREF\nCMS=01\nCMS=10\nCMS=11\n'1'\nCCxIF\nCCRx = 0\nOCxREF\nCMS=01\nCMS=10\nCMS=11\n'0'\nai14681b\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n616/1757\nRM0090 Rev 21\nin the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the \nsame time by the software.\n•\nWriting to the counter while running in center-aligned mode is not recommended as it \ncan lead to unexpected results. In particular:\n–\nThe direction is not updated if the user writes a value in the counter that is greater \nthan the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter \nwas counting up, it continues to count up.\n–\nThe direction is updated if the user writes 0 or write the TIMx_ARR value in the \ncounter but no Update Event UEV is generated.\n•\nThe safest way to use center-aligned mode is to generate an update by software \n(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to \nwrite the counter while it is running.\n18.3.10 \nOne-pulse mode\nOne-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to \nbe started in response to a stimulus and to generate a pulse with a programmable length \nafter a programmable delay.\nStarting the counter can be controlled through the slave mode controller. Generating the \nwaveform can be done in output compare mode or PWM mode. Select One-pulse mode by \nsetting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at \nthe next update event UEV.\nA pulse can be correctly generated only if the compare value is different from the counter \ninitial value. Before starting (when the timer is waiting for the trigger), the configuration must \nbe:\n•\nIn upcounting: CNTCCRx.\nFigure 166. Example of one-pulse mode\nFor example the user may want to generate a positive pulse on OC1 with a length of tPULSE \nand after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.\nMS31099V1\nTI2\nOC1REF\nCounter\nt\n0\nTIM1_ARR\nTIM1_CCR1\nOC1\ntDELAY\ntPULSE\n\n\n<>\n\nRM0090 Rev 21\n617/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nLet’s use TI2FP2 as trigger 1:\n•\nMap TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register.\n•\nTI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER \nregister.\n•\nConfigure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in \nthe TIMx_SMCR register.\n•\nTI2FP2 is used to start the counter by writing SMS to ‘110 in the TIMx_SMCR register \n(trigger mode).\nThe OPM waveform is defined by writing the compare registers (taking into account the \nclock frequency and the counter prescaler).\n•\nThe tDELAY is defined by the value written in the TIMx_CCR1 register.\n•\nThe tPULSE is defined by the difference between the auto-reload value and the compare \nvalue (TIMx_ARR - TIMx_CCR + 1).\n•\nLet us say user wants to build a waveform with a transition from ‘0 to ‘1 when a \ncompare match occurs and a transition from ‘1 to ‘0 when the counter reaches the \nauto-reload value. To do this enable PWM mode 2 by writing OC1M=111 in the \nTIMx_CCMR1 register. The user can optionally enable the preload registers by writing \nOC1PE=1 in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this \ncase write the compare value in the TIMx_CCR1 register, the auto-reload value in the \nTIMx_ARR register, generate an update by setting the UG bit and wait for external \ntrigger event on TI2. CC1P is written to ‘0 in this example.\nIn our example, the DIR and CMS bits in the TIMx_CR1 register should be low.\nUser only wants one pulse (Single mode), so write '1 in the OPM bit in the TIMx_CR1 \nregister to stop the counter at the next update event (when the counter rolls over from the \nauto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the \nRepetitive mode is selected.\nParticular case: OCx fast enable:\nIn One-pulse mode, the edge detection on TIx input set the CEN bit which enables the \ncounter. Then the comparison between the counter and the compare value makes the \noutput toggle. But several clock cycles are needed for these operations and it limits the \nminimum delay tDELAY min we can get.\nTo output a waveform with the minimum delay, the user can set the OCxFE bit in the \nTIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus, \nwithout taking in account the comparison. Its new level is the same as if a compare match \nhad occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.\n18.3.11 \nClearing the OCxREF signal on an external event\nThe OCxREF signal for a given channel can be driven Low by applying a High level to the \nETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to '1'). The \nOCxREF signal remains Low until the next update event, UEV, occurs. \nThis function can only be used in output compare and PWM modes, and does not work in \nforced mode. \nFor example, the ETR signal can be connected to the output of a comparator to be used for \ncurrent handling. In this case, ETR must be configured as follows:\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n618/1757\nRM0090 Rev 21\n1.\nThe external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR \nregister are cleared to 00.\n2. \nThe external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is \ncleared to 0.\n3. \nThe external trigger polarity (ETP) and the external trigger filter (ETF) can be \nconfigured according to the application’s needs.\nFigure 167 shows the behavior of the OCxREF signal when the ETRF input becomes high, \nfor both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in \nPWM mode.\nFigure 167. Clearing TIMx OCxREF\n1.\nIn case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the next counter \noverflow.\n18.3.12 \nEncoder interface mode\nTo select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter \nis counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if \nit is counting on both TI1 and TI2 edges.\nSelect the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER \nregister. When needed, program the input filter as well.\nThe two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to \nTable 98. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 \nafter input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted, \nTI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in \nTIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated \nand generates count pulses as well as the direction signal. Depending on the sequence the \ncounter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware \naccordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever \nthe counter is counting on TI1 only, TI2 only or both TI1 and TI2.\nEncoder interface mode acts simply as an external clock with direction selection. This \nmeans that the counter just counts continuously between 0 and the auto-reload value in the \nTIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So the user \nmust configure TIMx_ARR before starting. In the same way, the capture, compare, \nprescaler, trigger output features continue to work as normal. \nMS37368V1\n(CCRx)\nCounter (CNT)\nETRF\nOCxREF (OCxCE = ‘0’)\nOCxREF (OCxCE = ‘1’)\nETRF becomes high\nETRF still high\n\n\n<>\n\nRM0090 Rev 21\n619/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nIn this mode, the counter is modified automatically following the speed and the direction of \nthe incremental encoder and its content, therefore, always represents the encoder’s \nposition. The count direction correspond to the rotation direction of the connected sensor. \nThe table summarizes the possible combinations, assuming TI1 and TI2 do not switch at the \nsame time.\n \nAn external incremental encoder can be connected directly to the MCU without external \ninterface logic. However, comparators are normally be used to convert the encoder’s \ndifferential outputs to digital signals. This greatly increases noise immunity. The third \nencoder output which indicate the mechanical zero position, may be connected to an \nexternal interrupt input and trigger a counter reset.\nFigure 168 gives an example of counter operation, showing count signal generation and \ndirection control. It also shows how input jitter is compensated where both edges are \nselected. This might occur if the sensor is positioned near to one of the switching points. For \nthis example we assume that the configuration is the following:\n•\nCC1S= ‘01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1)\n•\nCC2S= ‘01’ (TIMx_CCMR1 register, TI2FP2 mapped on TI2)\n•\nCC1P= ‘0’, CC1NP = ‘0’, IC1F =’0000’ (TIMx_CCER register, TI1FP1 noninverted, \nTI1FP1=TI1)\n•\nCC2P= ‘0’, CC2NP = ‘0’, IC2F =’0000’ (TIMx_CCER register, TI2FP2 noninverted, \nTI2FP2=TI2)\n•\nSMS= ‘011’ (TIMx_SMCR register, both inputs are active on both rising and falling \nedges)\n•\nCEN = 1 (TIMx_CR1 register, Counter is enabled)\nTable 98. Counting direction versus encoder signals\nActive edge\nLevel on opposite \nsignal (TI1FP1 for \nTI2, TI2FP2 for TI1)\nTI1FP1 signal\nTI2FP2 signal\nRising\nFalling\nRising\nFalling\nCounting on \nTI1 only\nHigh\nDown\nUp\nNo Count\nNo Count\nLow\nUp\nDown\nNo Count\nNo Count\nCounting on \nTI2 only\nHigh\nNo Count\nNo Count\nUp\nDown\nLow\nNo Count\nNo Count\nDown\nUp\nCounting on \nTI1 and TI2\nHigh\nDown\nUp\nUp\nDown\nLow\nUp\nDown\nDown\nUp\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n620/1757\nRM0090 Rev 21\nFigure 168. Example of counter operation in encoder interface mode \nFigure 169 gives an example of counter behavior when TI1FP1 polarity is inverted (same \nconfiguration as above except CC1P=1).\nFigure 169. Example of encoder interface mode with TI1FP1 polarity inverted \nThe timer, when configured in Encoder Interface mode provides information on the sensor’s \ncurrent position. The user can obtain dynamic information (speed, acceleration, \ndeceleration) by measuring the period between two encoder events using a second timer \nconfigured in capture mode. The output of the encoder which indicates the mechanical zero \ncan be used for this purpose. Depending on the time between two events, the counter can \nalso be read at regular times. The user can do this by latching the counter value into a third \ninput capture register if available (then the capture signal must be periodic and can be \ngenerated by another timer). when available, it is also possible to read its value through a \nDMA request generated by a Real-Time clock.\nTI1\nbackward\njitter\njitter\nup\ndown\nup\nTI2\nCounter\nforward\nforward\nMS33107V1\nTI1\nbackward\njitter\njitter\nup\ndown\nTI2\nCounter\nforward\nforward\nMS33108V1\ndown\n\n\n<>\n\nRM0090 Rev 21\n621/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n18.3.13 \nTimer input XOR function\nThe TI1S bit in the TIM_CR2 register, allows the input filter of channel 1 to be connected to \nthe output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3.\nThe XOR output can be used with all the timer input functions such as trigger or input \ncapture.\n18.3.14 \nTimers and external trigger synchronization\nThe TIMx Timers can be synchronized with an external trigger in several modes: Reset \nmode, Gated mode and Trigger mode.\nSlave mode: Reset mode\nThe counter and its prescaler can be reinitialized in response to an event on a trigger input. \nMoreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is \ngenerated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.\nIn the following example, the upcounter is cleared in response to a rising edge on TI1 input:\n•\nConfigure the channel 1 to detect rising edges on TI1. Configure the input filter duration \n(in this example, no need of any filter, IC1F=0000 kept). The capture prescaler is not \nused for triggering, so the user does not need to configure it. The CC1S bits select the \ninput capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=0 and \nCC1NP=0 in TIMx_CCER register to validate the polarity (and detect rising edges \nonly).\n•\nConfigure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select \nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\n•\nStart the counter by writing CEN=1 in the TIMx_CR1 register.\nThe counter starts counting on the internal clock, then behaves normally until TI1 rising \nedge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the \ntrigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA \nrequest can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).\nFigure 170 shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay \nbetween the rising edge on TI1 and the actual reset of the counter is due to the \nresynchronization circuit on TI1 input.\nFigure 170. Control circuit in reset mode\nMS37384V1\n00\nCounter clock = CK_CNT = CK_PSC\nCounter register\n01 02 03 00\n01 02 03\n32 33 34 35 36\nUG\nTI1\n31\n30\nTIF\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n622/1757\nRM0090 Rev 21\nSlave mode: Gated mode\nThe counter can be enabled depending on the level of a selected input.\nIn the following example, the upcounter counts only when TI1 input is low:\n•\nConfigure the channel 1 to detect low levels on TI1. Configure the input filter duration \n(in this example, no need of any filter, IC1F=0000 kept). The capture prescaler is not \nused for triggering, so the user does not need to configure it. The CC1S bits select the \ninput capture source only, CC1S=01 in TIMx_CCMR1 register. Write CC1P=1 in \nTIMx_CCER register to validate the polarity (and detect low level only).\n•\nConfigure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select \nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\n•\nEnable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the \ncounter does not start if CEN=0, whatever is the trigger input level).\nThe counter starts counting on the internal clock as long as TI1 is low and stops as soon as \nTI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts \nor stops.\nThe delay between the rising edge on TI1 and the actual stop of the counter is due to the \nresynchronization circuit on TI1 input.\nFigure 171. Control circuit in gated mode\n1.\nThe configuration “CCxP=CCxNP=1” (detection of both rising and falling edges) does not have any effect \nin gated mode because gated mode acts on a level and not on an edge.\nSlave mode: Trigger mode\nThe counter can start in response to an event on a selected input.\nIn the following example, the upcounter starts in response to a rising edge on TI2 input:\n•\nConfigure the channel 2 to detect rising edges on TI2. Configure the input filter duration \n(in this example, no need of any filter, IC2F=0000 kept). The capture prescaler is not \nused for triggering, so the user does not need to configure it. CC2S bits are selecting \nthe input capture source only, CC2S=01 in TIMx_CCMR1 register. Write CC2P=1 in \nTIMx_CCER register to validate the polarity (and detect low level only).\n•\nConfigure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select \nTI2 as the input source by writing TS=110 in TIMx_SMCR register.\nMS40512V1\nTI1\nCNT_EN\nWrite TIF=0\n37\nCounter clock = CK_CNT = CK_PSC\nCounter register\n38\n32\n33\n34\n35\n36\n31\n30\nTIF\n\n\n<>\n\nRM0090 Rev 21\n623/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nWhen a rising edge occurs on TI2, the counter starts counting on the internal clock and the \nTIF flag is set.\nThe delay between the rising edge on TI2 and the actual start of the counter is due to the \nresynchronization circuit on TI2 input.\nFigure 172. Control circuit in trigger mode\nSlave mode: External Clock mode 2 + trigger mode\nThe external clock mode 2 can be used in addition to another slave mode (except external \nclock mode 1 and encoder mode). In this case, the ETR signal is used as external clock \ninput, and another input can be selected as trigger input when operating in reset mode, \ngated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS \nbits of TIMx_SMCR register.\nIn the following example, the upcounter is incremented at each rising edge of the ETR \nsignal as soon as a rising edge of TI1 occurs:\n1.\nConfigure the external trigger input circuit by programming the TIMx_SMCR register as \nfollows:\n–\nETF = 0000: no filter \n–\nETPS = 00: prescaler disabled\n–\nETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock \nmode 2.\n2. \nConfigure the channel 1 as follows, to detect rising edges on TI: \n–\nIC1F = 0000: no filter. \n–\nThe capture prescaler is not used for triggering and does not need to be \nconfigured.\n–\nCC1S = 01 in TIMx_CCMR1 register to select only the input capture source\n–\nCC1P = 0 in TIMx_CCER register to validate the polarity (and detect rising edge \nonly).\n3. \nConfigure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select \nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\nA rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on \nETR rising edges.\nThe delay between the rising edge of the ETR signal and the actual reset of the counter is \ndue to the resynchronization circuit on ETRP input. \nMS37386V1\nTI2\nCNT_EN\nCounter register\nTIF\n37 38\n34\n35 36\nCounter clock = CK_CNT = CK_PSC\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n624/1757\nRM0090 Rev 21\nFigure 173. Control circuit in external clock mode 2 + trigger mode\n18.3.15 \nTimer synchronization\nThe TIMx timers are linked together internally for timer synchronization or chaining. When \none Timer is configured in Master mode, it can reset, start, stop or clock the counter of \nanother Timer configured in Slave mode.\nFigure 174 presents an overview of the trigger selection and the master mode selection \nblocks.\nNote:\nThe clock of the slave timer must be enabled prior to receiving events from the master timer, \nand must not be changed on-the-fly while triggers are received from the master timer.\nUsing one timer as prescaler for another timer\nFigure 174. Master/Slave timer example\nMS33110V1\n34\n35\n36\nTIF\nCounter register\nCounter clock = CK_CNT = CK_PSC\nETR\nCEN/CNT_EN\nTI1\nMS37387V1\nCounter\nMaster \nmode \ncontrol \nUEV\nPrescaler\nClock\nCounter\nPrescaler\nCK_PSC\nTRGO1\nMMS\nSMS\nTS\nInput trigger \nselection\nTIM1\nTIM2\nSlave \nmode \ncontrol \nITR0\n\n\n<>\n\nRM0090 Rev 21\n625/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFor example, the user can configure Timer 1 to act as a prescaler for Timer 2 (see \nFigure 174). To do this:\n•\nConfigure Timer 1 in master mode so that it outputs a periodic trigger signal on each \nupdate event UEV. If you write MMS=010 in the TIM1_CR2 register, a rising edge is \noutput on TRGO1 each time an update event is generated.\n•\nTo connect the TRGO1 output of Timer 1 to Timer 2, Timer 2 must be configured in \nslave mode using ITR0 as internal trigger. You select this through the TS bits in the \nTIM2_SMCR register (writing TS=000).\n•\nThen you put the slave mode controller in external clock mode 1 (write SMS=111 in the \nTIM2_SMCR register). This causes Timer 2 to be clocked by the rising edge of the \nperiodic Timer 1 trigger signal (which correspond to the timer 1 counter overflow).\n•\nFinally both timers must be enabled by setting their respective CEN bits (TIMx_CR1 \nregister).\nNote:\nIf OCx is selected on Timer 1 as trigger output (MMS=1xx), its rising edge is used to clock \nthe counter of timer 2.\nUsing one timer to enable another timer\nIn this example, we control the enable of Timer 2 with the output compare 1 of Timer 1. \nRefer to Figure 174 for connections. Timer 2 counts on the divided internal clock only when \nOC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the \nprescaler compared to CK_INT (fCK_CNT = fCK_INT/3).\n•\nConfigure Timer 1 master mode to send its Output compare 1 Reference (OC1REF) \nsignal as trigger output (MMS=100 in the TIM1_CR2 register).\n•\nConfigure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).\n•\nConfigure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR \nregister).\n•\nConfigure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).\n•\nEnable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).\n•\nStart Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).\nNote:\nThe counter 2 clock is not synchronized with counter 1, this mode only affects the Timer 2 \ncounter enable signal.\nFigure 175. Gating timer 2 with OC1REF of timer 1\nIn the example in Figure 175, the Timer 2 counter and prescaler are not initialized before \nbeing started. So they start counting from their current value. It is possible to start from a \ngiven value by resetting both timers before starting Timer 1. You can then write any value \nMS37388V1\nCK_INT\nFC\nFD\nFE\nFF\n00\n01\nTIMER1-OC1REF\nTIMER1-CNT\n3046\n3045\n3047\n3048\nTIMER2-CNT\nTIMER2-TIF\nWrite TIF = 0 \n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n626/1757\nRM0090 Rev 21\nyou want in the timer counters. The timers can easily be reset by software using the UG bit \nin the TIMx_EGR registers.\nIn the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts \nfrom 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both \ntimers. Timer 2 stops when Timer 1 is disabled by writing ‘0 to the CEN bit in the TIM1_CR1 \nregister:\n•\nConfigure Timer 1 master mode to send its Output compare 1 Reference (OC1REF) \nsignal as trigger output (MMS=100 in the TIM1_CR2 register).\n•\nConfigure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).\n•\nConfigure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR \nregister).\n•\nConfigure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).\n•\nReset Timer 1 by writing ‘1 in UG bit (TIM1_EGR register).\n•\nReset Timer 2 by writing ‘1 in UG bit (TIM2_EGR register).\n•\nInitialize Timer 2 to 0xE7 by writing ‘0xE7’ in the timer 2 counter (TIM2_CNTL).\n•\nEnable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).\n•\nStart Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).\n•\nStop Timer 1 by writing ‘0 in the CEN bit (TIM1_CR1 register).\nFigure 176. Gating timer 2 with Enable of timer 1\nMS37389V1\nCK_INT\n75\n00\nE7\nTIMER1-CNT_INIT\nTIMER1-CNT\nAB\nTIMER2-CNT\nTIMER2-CNT_INIT\nWrite TIF = 0 \n01\n02\nE9\nE8\n00\nTIMER1-CEN=CNT_EN\nTIMER2-write CNT\nTIMER2-TIF\n\n\n<>\n\nRM0090 Rev 21\n627/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nUsing one timer to start another timer\nIn this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to \nFigure 174 for connections. Timer 2 starts counting from its current value (which can be \nnonzero) on the divided internal clock as soon as the update event is generated by Timer 1. \nWhen Timer 2 receives the trigger signal its CEN bit is automatically set and the counter \ncounts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock \nfrequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).\n•\nConfigure Timer 1 master mode to send its Update Event (UEV) as trigger output \n(MMS=010 in the TIM1_CR2 register).\n•\nConfigure the Timer 1 period (TIM1_ARR registers).\n•\nConfigure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR \nregister).\n•\nConfigure Timer 2 in trigger mode (SMS=110 in TIM2_SMCR register).\n•\nStart Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).\nFigure 177. Triggering timer 2 with update of timer 1\nAs in the previous example, the user can initialize both counters before starting counting. \nFigure 178 shows the behavior with the same configuration as in Figure 177 but in trigger \nmode instead of gated mode (SMS=110 in the TIM2_SMCR register).\nMS37390V1\nWrite TIF = 0 \nCK_INT\nTIMER2-CNT\nFD\nTIMER1-CNT\nTIMER2-CEN=CNT_EN\nTIMER2-TIF\nFE\nFF\n00\n01\n02\n46\n47\n48\n45\nTIMER1-UEV\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n628/1757\nRM0090 Rev 21\nFigure 178. Triggering timer 2 with Enable of timer 1\nStarting 2 timers synchronously in response to an external trigger\nIn this example, we set the enable of timer 1 when its TI1 input rises, and the enable of \nTimer 2 with the enable of Timer 1. Refer to Figure 174 for connections. To ensure the \ncounters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect \nto TI1, master with respect to Timer 2):\n•\nConfigure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the \nTIM1_CR2 register).\n•\nConfigure Timer 1 slave mode to get the input trigger from TI1 (TS=100 in the \nTIM1_SMCR register).\n•\nConfigure Timer 1 in trigger mode (SMS=110 in the TIM1_SMCR register).\n•\nConfigure the Timer 1 in Master/Slave mode by writing MSM=1 (TIM1_SMCR register).\n•\nConfigure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR \nregister).\n•\nConfigure Timer 2 in trigger mode (SMS=110 in the TIM2_SMCR register).\nWhen a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on \nthe internal clock and both TIF flags are set.\nNote:\nIn this example both timers are initialized before starting (by setting their respective UG \nbits). Both counters starts from 0, but you can easily insert an offset between them by \nwriting any of the counter registers (TIMx_CNT). You can see that the master/slave mode \ninsert a delay between CNT_EN and CK_PSC on timer 1.\nMS37391V1\nWrite TIF = 0 \nCK_INT\nTIMER2-CNT\nTIMER1-CNT_INIT\nTIMER1-CEN=CNT_EN\nTIMER2-TIF\nE7\n02\n00\n01\nE9\n75\nCD\n00\nE8\nEA\nTIMER1-CNT\nTIMER2-CNT_INIT\nTIMER2-write CNT\n\n\n<>\n\nRM0090 Rev 21\n629/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFigure 179. Triggering timer 1 and 2 with timer 1 TI1 input\n18.3.16 \nDebug mode\nWhen the microcontroller enters debug mode (Cortex®-M4 with FPU core - halted), the \nTIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP \nconfiguration bit in DBGMCU module. For more details, refer to Section 38.16.2: Debug \nsupport for timers, watchdog, bxCAN and I2C.\nMS37392V1\nCK_INT\nTIMER2-CNT\nTIMER1-CEN=CNT_EN\nTIMER2-TIF\n01\nTIMER1-CNT\n02 03 04 05 06 07 08 09\n00\nTIMER2-CEN=CNT_EN\nTIMER1-TIF\nTIMER1-CK_PSC\nTIMER1-TI1\nTIMER2-CK_PSC\n01 02 03 04 05 06 07 08 09\n00\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n630/1757\nRM0090 Rev 21\n18.4 \nTIM2 to TIM5 registers\nRefer to Section 2.2 for a list of abbreviations used in register descriptions.\nThe 32-bit peripheral registers have to be written by words (32 bits). All other peripheral \nregisters have to be written by half-words (16 bits) or words (32 bits). Read accesses can be \ndone by bytes (8 bits), half-words (16 bits) or words (32 bits). \n18.4.1 \nTIMx control register 1 (TIMx_CR1)\nAddress offset: 0x00\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCKD[1:0]\nARPE\nCMS\nDIR\nOPM\nURS\nUDIS\nCEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:10 Reserved, must be kept at reset value.\nBits 9:8 CKD: Clock division\nThis bit-field indicates the division ratio between the timer clock (CK_INT) frequency and \nsampling clock used by the digital filters (ETR, TIx),\n00: tDTS = tCK_INT\n01: tDTS = 2 × tCK_INT\n10: tDTS = 4 × tCK_INT\n11: Reserved\nBit 7 ARPE: Auto-reload preload enable\n0: TIMx_ARR register is not buffered\n1: TIMx_ARR register is buffered\nBits 6:5 CMS: Center-aligned mode selection\n00: Edge-aligned mode. The counter counts up or down depending on the direction bit \n(DIR).\n01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare \ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set \nonly when the counter is counting down.\n10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare \ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set \nonly when the counter is counting up.\n11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare \ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set \nboth when the counter is counting up or down.\nNote: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as \nthe counter is enabled (CEN=1)\nBit 4 DIR: Direction\n0: Counter used as upcounter\n1: Counter used as downcounter\nNote: This bit is read only when the timer is configured in Center-aligned mode or Encoder \nmode.\nBit 3 OPM: One-pulse mode\n0: Counter is not stopped at update event\n1: Counter stops counting at the next update event (clearing the bit CEN)\n\n\n<>\n\nRM0090 Rev 21\n631/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nBit 2 URS: Update request source\nThis bit is set and cleared by software to select the UEV event sources.\n0: Any of the following events generate an update interrupt or DMA request if enabled. \nThese events can be: \n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\n1: Only counter overflow/underflow generates an update interrupt or DMA request if \nenabled.\nBit 1 UDIS: Update disable\nThis bit is set and cleared by software to enable/disable UEV event generation.\n0: UEV enabled. The Update (UEV) event is generated by one of the following events:\n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\nBuffered registers are then loaded with their preload values.\n1: UEV disabled. The Update event is not generated, shadow registers keep their value \n(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is \nset or if a hardware reset is received from the slave mode controller.\nBit 0 CEN: Counter enable\n0: Counter disabled\n1: Counter enabled\nNote: External clock, gated mode and encoder mode can work only if the CEN bit has been \npreviously set by software. However trigger mode can set the CEN bit automatically by \nhardware. \nCEN is cleared automatically in one-pulse mode, when an update event occurs.\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n632/1757\nRM0090 Rev 21\n18.4.2 \nTIMx control register 2 (TIMx_CR2)\nAddress offset: 0x04\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTI1S\nMMS[2:0]\nCCDS\nReserved\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 TI1S: TI1 selection\n0: The TIMx_CH1 pin is connected to TI1 input\n1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) \nBits 6:4 MMS[2:0]: Master mode selection\nThese bits can be used to select the information to be sent in master mode to slave timers \nfor synchronization (TRGO). The combination is as follows:\n000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the \nreset is generated by the trigger input (slave mode controller configured in reset mode) then \nthe signal on TRGO is delayed compared to the actual reset.\n001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is \nuseful to start several timers at the same time or to control a window in which a slave timer is \nenabled. The Counter Enable signal is generated by a logic OR between CEN control bit \nand the trigger input when configured in gated mode. \nWhen the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, \nexcept if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR \nregister).\n010: Update - The update event is selected as trigger output (TRGO). For instance a master \ntimer can then be used as a prescaler for a slave timer.\n011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be \nset (even if it was already high), as soon as a capture or a compare match occurred. \n(TRGO)\n100: Compare - OC1REF signal is used as trigger output (TRGO)\n101: Compare - OC2REF signal is used as trigger output (TRGO)\n110: Compare - OC3REF signal is used as trigger output (TRGO)\n111: Compare - OC4REF signal is used as trigger output (TRGO)\nNote: The clock of the slave timer and ADC must be enabled prior to receiving events from \nthe master timer, and must not be changed on-the-fly while triggers are received from \nthe master timer.\nBit 3 CCDS: Capture/compare DMA selection\n0: CCx DMA request sent when CCx event occurs\n1: CCx DMA requests sent when update event occurs\nBits 2:0 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n633/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n18.4.3 \nTIMx slave mode control register (TIMx_SMCR)\nAddress offset: 0x08\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nETP\nECE\nETPS[1:0]\nETF[3:0]\nMSM\nTS[2:0]\nRes.\nSMS[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 ETP: External trigger polarity\nThis bit selects whether ETR or ETR is used for trigger operations\n0: ETR is noninverted, active at high level or rising edge\n1: ETR is inverted, active at low level or falling edge\nBit 14 ECE: External clock enable\nThis bit enables External clock mode 2.\n0: External clock mode 2 disabled\n1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF \nsignal.\n1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI \nconnected to ETRF (SMS=111 and TS=111).\n2: It is possible to simultaneously use external clock mode 2 with the following slave modes: \nreset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to \nETRF in this case (TS bits must not be 111).\n3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the \nexternal clock input is ETRF.\nBits 13:12 ETPS: External trigger prescaler\nExternal trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A \nprescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external \nclocks.\n00: Prescaler OFF\n01: ETRP frequency divided by 2\n10: ETRP frequency divided by 4\n11: ETRP frequency divided by 8\nBits 11:8 ETF[3:0]: External trigger filter\nThis bit-field then defines the frequency used to sample ETRP signal and the length of the \ndigital filter applied to ETRP. The digital filter is made of an event counter in which N \nconsecutive events are needed to validate a transition on the output:\n0000: No filter, sampling is done at fDTS\n0001: fSAMPLING=fCK_INT, N=2\n0010: fSAMPLING=fCK_INT, N=4\n0011: fSAMPLING=fCK_INT, N=8\n0100: fSAMPLING=fDTS/2, N=6\n0101: fSAMPLING=fDTS/2, N=8\n0110: fSAMPLING=fDTS/4, N=6\n0111: fSAMPLING=fDTS/4, N=8\n1000: fSAMPLING=fDTS/8, N=6\n1001: fSAMPLING=fDTS/8, N=8\n1010: fSAMPLING=fDTS/16, N=5\n1011: fSAMPLING=fDTS/16, N=6\n1100: fSAMPLING=fDTS/16, N=8\n1101: fSAMPLING=fDTS/32, N=5\n1110: fSAMPLING=fDTS/32, N=6\n1111: fSAMPLING=fDTS/32, N=8\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n634/1757\nRM0090 Rev 21\n \nBit 7 MSM: Master/Slave mode\n0: No action\n1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect \nsynchronization between the current timer and its slaves (through TRGO). It is useful if we \nwant to synchronize several timers on a single external event.\nBits 6:4 TS: Trigger selection\nThis bit-field selects the trigger input to be used to synchronize the counter.\n000: Internal Trigger 0 (ITR0)\n001: Internal Trigger 1 (ITR1). \n010: Internal Trigger 2 (ITR2). \n011: Internal Trigger 3 (ITR3).\n100: TI1 Edge Detector (TI1F_ED)\n101: Filtered Timer Input 1 (TI1FP1)\n110: Filtered Timer Input 2 (TI2FP2)\n111: External Trigger input (ETRF)\nSee Table 99: TIMx internal trigger connection on page 635 for more details on ITRx \nmeaning for each Timer.\nNote: These bits must be changed only when they are not used (e.g. when SMS=000) to \navoid wrong edge detections at the transition.\nBit 3 Reserved, must be kept at reset value.\nBits 2:0 SMS: Slave mode selection\nWhen external signals are selected the active edge of the trigger signal (TRGI) is linked to \nthe polarity selected on the external input (see Input Control register and Control register \ndescription.\n000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal \nclock.\n001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 \nlevel.\n010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 \nlevel.\n011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges \ndepending on the level of the other input.\n100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter \nand generates an update of the registers.\n101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The \ncounter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of \nthe counter are controlled.\n110: Trigger mode - The counter starts at a rising edge of the trigger TRGI (but it is not \nreset). Only the start of the counter is controlled.\n111: External Clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.\nNote: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100). \nIndeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode \nchecks the level of the trigger signal.\nThe clock of the slave timer must be enabled prior to receiving events from the master \ntimer, and must not be changed on-the-fly while triggers are received from the master \ntimer.\n\n\n<>\n\nRM0090 Rev 21\n635/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n \n18.4.4 \nTIMx DMA/Interrupt enable register (TIMx_DIER)\nAddress offset: 0x0C\nReset value: 0x0000\n \nTable 99. TIMx internal trigger connection\nSlave TIM\nITR0 (TS = 000)\nITR1 (TS = 001)\nITR2 (TS = 010)\nITR3 (TS = 011)\nTIM2\nTIM1_TRGO\nTIM8_TRGO\nTIM3_TRGO\nTIM4_TRGO\nTIM3\nTIM1_TRGO\nTIM2_TRGO\nTIM5_TRGO\nTIM4_TRGO\nTIM4\nTIM1_TRGO\nTIM2_TRGO\nTIM3_TRGO\nTIM8_TRGO\nTIM5\nTIM2_TRGO\nTIM3_TRGO\nTIM4_TRGO\nTIM8_TRGO\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nTDE\nRes\nCC4DE CC3DE CC2DE CC1DE\nUDE\nRes.\nTIE\nRes\nCC4IE\nCC3IE\nCC2IE\nCC1IE\nUIE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15\nReserved, must be kept at reset value.\nBit 14 TDE: Trigger DMA request enable\n0: Trigger DMA request disabled.\n1: Trigger DMA request enabled.\nBit 13\nReserved, always read as 0\nBit 12 CC4DE: Capture/Compare 4 DMA request enable\n0: CC4 DMA request disabled.\n1: CC4 DMA request enabled.\nBit 11 CC3DE: Capture/Compare 3 DMA request enable\n0: CC3 DMA request disabled.\n1: CC3 DMA request enabled.\nBit 10 CC2DE: Capture/Compare 2 DMA request enable\n0: CC2 DMA request disabled.\n1: CC2 DMA request enabled.\nBit 9 CC1DE: Capture/Compare 1 DMA request enable\n0: CC1 DMA request disabled.\n1: CC1 DMA request enabled.\nBit 8 UDE: Update DMA request enable\n0: Update DMA request disabled.\n1: Update DMA request enabled.\nBit 7\nReserved, must be kept at reset value.\nBit 6 TIE: Trigger interrupt enable\n0: Trigger interrupt disabled.\n1: Trigger interrupt enabled.\nBit 5\nReserved, must be kept at reset value.\nBit 4 CC4IE: Capture/Compare 4 interrupt enable\n0: CC4 interrupt disabled.\n1: CC4 interrupt enabled.\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n636/1757\nRM0090 Rev 21\n18.4.5 \nTIMx status register (TIMx_SR)\nAddress offset: 0x10\nReset value: 0x0000\n \nBit 3 CC3IE: Capture/Compare 3 interrupt enable\n0: CC3 interrupt disabled\n1: CC3 interrupt enabled\nBit 2 CC2IE: Capture/Compare 2 interrupt enable\n0: CC2 interrupt disabled\n1: CC2 interrupt enabled\nBit 1 CC1IE: Capture/Compare 1 interrupt enable\n0: CC1 interrupt disabled\n1: CC1 interrupt enabled\nBit 0 UIE: Update interrupt enable\n0: Update interrupt disabled\n1: Update interrupt enabled\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCC4OF CC3OF CC2OF CC1OF\nReserved\nTIF\nRes\nCC4IF\nCC3IF\nCC2IF\nCC1IF\nUIF\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nBits 15:13\nReserved, must be kept at reset value.\nBit 12 CC4OF: Capture/Compare 4 overcapture flag\nrefer to CC1OF description\nBit 11 CC3OF: Capture/Compare 3 overcapture flag\nrefer to CC1OF description\nBit 10 CC2OF: Capture/compare 2 overcapture flag\nrefer to CC1OF description\nBit 9 CC1OF: Capture/Compare 1 overcapture flag\nThis flag is set by hardware only when the corresponding channel is configured in input \ncapture mode. It is cleared by software by writing it to ‘0.\n0: No overcapture has been detected\n1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was \nalready set\nBits 8:7\nReserved, must be kept at reset value.\nBit 6 TIF: Trigger interrupt flag\nThis flag is set by hardware on trigger event (active edge detected on TRGI input when the \nslave mode controller is enabled in all modes but gated mode. It is set when the counter \nstarts or stops when gated mode is selected. It is cleared by software.\n0: No trigger event occurred\n1: Trigger interrupt pending\nBit 5\nReserved, must be kept at reset value.\nBit 4 CC4IF: Capture/Compare 4 interrupt flag\nrefer to CC1IF description\n\n\n<>\n\nRM0090 Rev 21\n637/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nBit 3 CC3IF: Capture/Compare 3 interrupt flag\nrefer to CC1IF description\nBit 2 CC2IF: Capture/Compare 2 interrupt flag\nrefer to CC1IF description\nBit 1 CC1IF: Capture/compare 1 interrupt flag\nIf channel CC1 is configured as output:\nThis flag is set by hardware when the counter matches the compare value, with some \nexception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register \ndescription). It is cleared by software.\n0: No match\n1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. \nWhen the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit \ngoes high on the counter overflow (in upcounting and up/down-counting modes) or underflow \n(in downcounting mode)\nIf channel CC1 is configured as input:\nThis bit is set by hardware on a capture. It is cleared by software or by reading the \nTIMx_CCR1 register.\n0: No input capture occurred\n1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected \non IC1 which matches the selected polarity)\nBit 0 UIF: Update interrupt flag\n″\nThis bit is set by hardware on an update event. It is cleared by software.\n0: No update occurred.\n1: Update interrupt pending. This bit is set by hardware when the registers are updated:\n″\nAt overflow or underflow (for TIM2 to TIM5) and if UDIS=0 in the TIMx_CR1 register.\n″\nWhen CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 \nand UDIS=0 in the TIMx_CR1 register.\nWhen CNT is reinitialized by a trigger event (refer to the synchro control register description), \nif URS=0 and UDIS=0 in the TIMx_CR1 register.\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n638/1757\nRM0090 Rev 21\n18.4.6 \nTIMx event generation register (TIMx_EGR)\nAddress offset: 0x14\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTG\nRes.\nCC4G\nCC3G\nCC2G\nCC1G\nUG\nw\nw\nw\nw\nw\nw\nBits 15:7 Reserved, must be kept at reset value.\nBit 6 TG: Trigger generation\nThis bit is set by software in order to generate an event, it is automatically cleared by \nhardware.\n0: No action\n1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if \nenabled.\nBit 5 Reserved, must be kept at reset value.\nBit 4 CC4G: Capture/compare 4 generation\nrefer to CC1G description\nBit 3 CC3G: Capture/compare 3 generation\nrefer to CC1G description\nBit 2 CC2G: Capture/compare 2 generation\nrefer to CC1G description\nBit 1 CC1G: Capture/compare 1 generation\nThis bit is set by software in order to generate an event, it is automatically cleared by \nhardware.\n0: No action\n1: A capture/compare event is generated on channel 1:\nIf channel CC1 is configured as output:\nCC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.\nIf channel CC1 is configured as input:\nThe current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, \nthe corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the \nCC1IF flag was already high.\nBit 0 UG: Update generation\nThis bit can be set by software, it is automatically cleared by hardware.\n0: No action\n1: Re-initialize the counter and generates an update of the registers. Note that the prescaler \ncounter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if \nthe center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload \nvalue (TIMx_ARR) if DIR=1 (downcounting).\n\n\n<>\n\nRM0090 Rev 21\n639/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n18.4.7 \nTIMx capture/compare mode register 1 (TIMx_CCMR1)\nAddress offset: 0x18\nReset value: 0x0000\nThe channels can be used in input (capture mode) or in output (compare mode). The \ndirection of a channel is defined by configuring the corresponding CCxS bits. All the other \nbits of this register have a different function in input and in output mode. For a given bit, \nOCxx describes its function when the channel is configured in output, ICxx describes its \nfunction when the channel is configured in input. Take care that the same bit can have a \ndifferent meaning for the input stage and for the output stage.\n \nOutput compare mode\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOC2CE\nOC2M[2:0]\nOC2PE OC2FE\nCC2S[1:0]\nOC1CE\nOC1M[2:0]\nOC1PE OC1FE\nCC1S[1:0]\nIC2F[3:0]\nIC2PSC[1:0]\nIC1F[3:0]\nIC1PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 OC2CE: Output compare 2 clear enable\nBits 14:12 OC2M[2:0]: Output compare 2 mode\nBit 11 OC2PE: Output compare 2 preload enable\nBit 10 OC2FE: Output compare 2 fast enable\nBits 9:8 CC2S[1:0]: Capture/Compare 2 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC2 channel is configured as output\n01: CC2 channel is configured as input, IC2 is mapped on TI2\n10: CC2 channel is configured as input, IC2 is mapped on TI1\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through the TS bit (TIMx_SMCR register)\nNote: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).\nBit 7 OC1CE: Output compare 1 clear enable\nOC1CE: Output compare 1 Clear Enable\n0: OC1Ref is not affected by the ETRF input\n1: OC1Ref is cleared as soon as a High level is detected on ETRF input\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n640/1757\nRM0090 Rev 21\nBits 6:4 OC1M: Output compare 1 mode\nThese bits define the behavior of the output reference signal OC1REF from which OC1 and \nOC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends \non CC1P and CC1NP bits.\n000: Frozen - The comparison between the output compare register TIMx_CCR1 and the \ncounter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing \nbase).\n001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter \nTIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).\n010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the \ncounter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).\n011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.\n100: Force inactive level - OC1REF is forced low.\n101: Force active level - OC1REF is forced high.\n110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (OC1REF=1).\n111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 else \ninactive.\nNote: In PWM mode 1 or 2, the OCREF level changes only when the result of the \ncomparison changes or when the output compare mode switches from “frozen” mode \nto “PWM” mode.\nBit 3 OC1PE: Output compare 1 preload enable\n0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the \nnew value is taken in account immediately.\n1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload \nregister. TIMx_CCR1 preload value is loaded in the active register at each update event.\nNote: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK \nbits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output).\nBit 2 OC1FE: Output compare 1 fast enable\nThis bit is used to accelerate the effect of an event on the trigger in input on the CC output.\n0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is \nON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is \n5 clock cycles.\n1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC \nis set to the compare level independently from the result of the comparison. Delay to sample \nthe trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if \nthe channel is configured in PWM1 or PWM2 mode.\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC1 channel is configured as output.\n01: CC1 channel is configured as input, IC1 is mapped on TI1.\n10: CC1 channel is configured as input, IC1 is mapped on TI2.\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\n\n\n<>\n\nRM0090 Rev 21\n641/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nInput capture mode\nBits 15:12 IC2F: Input capture 2 filter\nBits 11:10 IC2PSC[1:0]: Input capture 2 prescaler\nBits 9:8 CC2S: Capture/compare 2 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC2 channel is configured as output.\n01: CC2 channel is configured as input, IC2 is mapped on TI2.\n10: CC2 channel is configured as input, IC2 is mapped on TI1.\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).\nBits 7:4 IC1F: Input capture 1 filter\nThis bit-field defines the frequency used to sample TI1 input and the length of the digital filter \napplied to TI1. The digital filter is made of an event counter in which N consecutive events \nare needed to validate a transition on the output:\n0000: No filter, sampling is done at fDTS\n0001: fSAMPLING=fCK_INT, N=2\n0010: fSAMPLING=fCK_INT, N=4\n0011: fSAMPLING=fCK_INT, N=8\n0100: fSAMPLING=fDTS/2, N=6\n0101: fSAMPLING=fDTS/2, N=8\n0110: fSAMPLING=fDTS/4, N=6\n0111: fSAMPLING=fDTS/4, N=8\n1000: fSAMPLING=fDTS/8, N=6\n1001: fSAMPLING=fDTS/8, N=8\n1010: fSAMPLING=fDTS/16, N=5\n1011: fSAMPLING=fDTS/16, N=6\n1100: fSAMPLING=fDTS/16, N=8\n1101: fSAMPLING=fDTS/32, N=5\n1110: fSAMPLING=fDTS/32, N=6\n1111: fSAMPLING=fDTS/32, N=8\nBits 3:2 IC1PSC: Input capture 1 prescaler\nThis bit-field defines the ratio of the prescaler acting on CC1 input (IC1).\nThe prescaler is reset as soon as CC1E=0 (TIMx_CCER register).\n00: no prescaler, capture is done each time an edge is detected on the capture input\n01: capture is done once every 2 events\n10: capture is done once every 4 events\n11: capture is done once every 8 events\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: CC1 channel is configured as input, IC1 is mapped on TI2\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n642/1757\nRM0090 Rev 21\n18.4.8 \nTIMx capture/compare mode register 2 (TIMx_CCMR2)\nAddress offset: 0x1C\nReset value: 0x0000\nRefer to the above CCMR1 register description.\nOutput compare mode\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOC4CE\nOC4M[2:0]\nOC4PE OC4FE\nCC4S[1:0]\nOC3CE\nOC3M[2:0]\nOC3PE OC3FE\nCC3S[1:0]\nIC4F[3:0]\nIC4PSC[1:0]\nIC3F[3:0]\nIC3PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 OC4CE: Output compare 4 clear enable\nBits 14:12 OC4M: Output compare 4 mode\nBit 11 OC4PE: Output compare 4 preload enable\nBit 10 OC4FE: Output compare 4 fast enable\nBits 9:8 CC4S: Capture/Compare 4 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC4 channel is configured as output\n01: CC4 channel is configured as input, IC4 is mapped on TI4\n10: CC4 channel is configured as input, IC4 is mapped on TI3\n11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).\nBit 7 OC3CE: Output compare 3 clear enable\nBits 6:4 OC3M: Output compare 3 mode\nBit 3 OC3PE: Output compare 3 preload enable\nBit 2 OC3FE: Output compare 3 fast enable\nBits 1:0 CC3S: Capture/Compare 3 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC3 channel is configured as output\n01: CC3 channel is configured as input, IC3 is mapped on TI3\n10: CC3 channel is configured as input, IC3 is mapped on TI4\n11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).\n\n\n<>\n\nRM0090 Rev 21\n643/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nInput capture mode\n18.4.9 \nTIMx capture/compare enable register (TIMx_CCER)\nAddress offset: 0x20\nReset value: 0x0000\n \n \nBits 15:12 IC4F: Input capture 4 filter\nBits 11:10 IC4PSC: Input capture 4 prescaler\nBits 9:8 CC4S: Capture/Compare 4 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC4 channel is configured as output\n01: CC4 channel is configured as input, IC4 is mapped on TI4\n10: CC4 channel is configured as input, IC4 is mapped on TI3\n11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).\nBits 7:4 IC3F: Input capture 3 filter\nBits 3:2 IC3PSC: Input capture 3 prescaler\nBits 1:0 CC3S: Capture/Compare 3 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC3 channel is configured as output\n01: CC3 channel is configured as input, IC3 is mapped on TI3\n10: CC3 channel is configured as input, IC3 is mapped on TI4\n11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCC4NP\nRes.\nCC4P\nCC4E\nCC3NP\nRes.\nCC3P\nCC3E\nCC2NP\nRes.\nCC2P\nCC2E\nCC1NP\nRes.\nCC1P\nCC1E\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 CC4NP: Capture/Compare 4 output Polarity.\nRefer to CC1NP description\nBit 14\nReserved, must be kept at reset value.\nBit 13 CC4P: Capture/Compare 4 output Polarity.\nrefer to CC1P description\nBit 12 CC4E: Capture/Compare 4 output enable.\nrefer to CC1E description\nBit 11 CC3NP: Capture/Compare 3 output Polarity.\nrefer to CC1NP description\nBit 10\nReserved, must be kept at reset value.\nBit 9 CC3P: Capture/Compare 3 output Polarity.\nrefer to CC1P description\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n644/1757\nRM0090 Rev 21\n \nBit 8 CC3E: Capture/Compare 3 output enable.\nrefer to CC1E description\nBit 7 CC2NP: Capture/Compare 2 output Polarity.\nrefer to CC1NP description\nBit 6\nReserved, must be kept at reset value.\nBit 5 CC2P: Capture/Compare 2 output Polarity.\nrefer to CC1P description\nBit 4 CC2E: Capture/Compare 2 output enable.\nrefer to CC1E description\nBit 3 CC1NP: Capture/Compare 1 output Polarity.\nCC1 channel configured as output:\nCC1NP must be kept cleared in this case.\nCC1 channel configured as input:\nThis bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P \ndescription.\nBit 2\nReserved, must be kept at reset value.\nBit 1 CC1P: Capture/Compare 1 output Polarity.\nCC1 channel configured as output:\n0: OC1 active high\n1: OC1 active low\nCC1 channel configured as input:\nCC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.\n00: noninverted/rising edge\nCircuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger \nmode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).\n01: inverted/falling edge\nCircuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger \nmode), TIxFP1 is inverted (trigger in gated mode, encoder mode).\n10: reserved, do not use this configuration.\n11: noninverted/both edges\nCircuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external \nclock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration \nmust not be used for encoder mode.\nBit 0 CC1E: Capture/Compare 1 output enable.\nCC1 channel configured as output:\n0: Off - OC1 is not active\n1: On - OC1 signal is output on the corresponding output pin\nCC1 channel configured as input:\nThis bit determines if a capture of the counter value can actually be done into the input \ncapture/compare register 1 (TIMx_CCR1) or not.\n0: Capture disabled\n1: Capture enabled\nTable 100. Output control bit for standard OCx channels\nCCxE bit\nOCx output state\n0\nOutput Disabled (OCx=0, OCx_EN=0)\n1\nOCx=OCxREF + Polarity, OCx_EN=1\n\n\n<>\n\nRM0090 Rev 21\n645/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nNote:\nThe state of the external IO pins connected to the standard OCx channels depends on the \nOCx channel state and the GPIO registers.\n18.4.10 \nTIMx counter (TIMx_CNT)\nAddress offset: 0x24\nReset value: 0x0000 0000\n \n18.4.11 \nTIMx prescaler (TIMx_PSC)\nAddress offset: 0x28\nReset value: 0x0000\n \n18.4.12 \nTIMx auto-reload register (TIMx_ARR)\nAddress offset: 0x2C\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCNT[31:16] (depending on timers)\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCNT[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 CNT[31:16]: High counter value (on TIM2 and TIM5).\nBits 15:0 CNT[15:0]: Counter value\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPSC[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 PSC[15:0]: Prescaler value\nThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).\nPSC contains the value to be loaded in the active prescaler register at each update event \n(including when the counter is cleared through UG bit of TIMx_EGR register or through \ntrigger controller when configured in “reset mode”).\nReset value: 0xFFFF FFFF\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nARR[31:16] (depending on timers)\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nARR[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n646/1757\nRM0090 Rev 21\n \n18.4.13 \nTIMx capture/compare register 1 (TIMx_CCR1)\nAddress offset: 0x34\nReset value: 0x0000 0000\n \n18.4.14 \nTIMx capture/compare register 2 (TIMx_CCR2)\nAddress offset: 0x38\nReset value: 0x0000 0000\nBits 31:16 ARR[31:16]: High auto-reload value (on TIM2 and TIM5).\nBits 15:0\nARR[15:0]: Auto-reload value\nARR is the value to be loaded in the actual auto-reload register.\nRefer to the Section 18.3.1: Time-base unit for more details about ARR update and \nbehavior.\nThe counter is blocked while the auto-reload value is null.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCCR1[31:16] (depending on timers)\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR1[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 31:16 CCR1[31:16]: High Capture/Compare 1 value (on TIM2 and TIM5).\nBits 15:0 CCR1[15:0]: Low Capture/Compare 1 value\nIf channel CC1 is configured as output:\nCCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register \n(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when \nan update event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signaled on OC1 output.\nIf channel CC1is configured as input:\nCCR1 is the counter value transferred by the last input capture 1 event (IC1). The \nTIMx_CCR1 register is read-only and cannot be programmed.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCCR2[31:16] (depending on timers)\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR2[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\n\n\n<>\n\nRM0090 Rev 21\n647/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n \n18.4.15 \nTIMx capture/compare register 3 (TIMx_CCR3)\nAddress offset: 0x3C\nReset value: 0x0000 0000\n \n18.4.16 \nTIMx capture/compare register 4 (TIMx_CCR4)\nAddress offset: 0x40\nReset value: 0x0000 0000\nBits 31:16 CCR2[31:16]: High Capture/Compare 2 value (on TIM2 and TIM5).\nBits 15:0 CCR2[15:0]: Low Capture/Compare 2 value\nIf channel CC2 is configured as output:\nCCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR register (bit \nOC2PE). Else the preload value is copied in the active capture/compare 2 register when an \nupdate event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signalled on OC2 output.\nIf channel CC2 is configured as input:\nCCR2 is the counter value transferred by the last input capture 2 event (IC2). The \nTIMx_CCR2 register is read-only and cannot be programmed.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCCR3[31:16] (depending on timers)\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR3[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2 and TIM5).\nBits 15:0 CCR3[15:0]: Low Capture/Compare value\nIf channel CC3 is configured as output:\nCCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR register (bit \nOC3PE). Else the preload value is copied in the active capture/compare 3 register when an \nupdate event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signaled on OC3 output.\nIf channel CC3 is configured as input:\nCCR3 is the counter value transferred by the last input capture 3 event (IC3). The \nTIMx_CCR3 register is read-only and cannot be programmed.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCCR4[31:16] (depending on timers)\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR4[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n648/1757\nRM0090 Rev 21\n \n18.4.17 \nTIMx DMA control register (TIMx_DCR)\nAddress offset: 0x48\nReset value: 0x0000\n \nBits 31:16 CCR4[31:16]: High Capture/Compare 4 value (on TIM2 and TIM5).\nBits 15:0 CCR4[15:0]: Low Capture/Compare value\n1.\nif CC4 channel is configured as output (CC4S bits):\nCCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR register \n(bit OC4PE). Else the preload value is copied in the active capture/compare 4 register \nwhen an update event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signalled on OC4 output.\n2. \nif CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register):\nCCR4 is the counter value transferred by the last input capture 4 event (IC4). The \nTIMx_CCR4 register is read-only and cannot be programmed.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDBL[4:0]\nReserved\nDBA[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:13 Reserved, must be kept at reset value.\nBits 12:8 DBL[4:0]: DMA burst length\nThis 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer \nwhen a read or a write access is done to the TIMx_DMAR address).\n00000: 1 transfer,\n00001: 2 transfers,\n00010: 3 transfers,\n...\n10001: 18 transfers.\nBits 7:5 Reserved, must be kept at reset value.\nBits 4:0 DBA[4:0]: DMA base address\nThis 5-bit vector defines the base-address for DMA transfers (when read/write access are \ndone through the TIMx_DMAR address). DBA is defined as an offset starting from the \naddress of the TIMx_CR1 register.\nExample:\n00000: TIMx_CR1,\n00001: TIMx_CR2,\n00010: TIMx_SMCR,\n...\nExample: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this \ncase the transfer is done to/from 7 registers starting from the TIMx_CR1 address.\n\n\n<>\n\nRM0090 Rev 21\n649/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n18.4.18 \nTIMx DMA address for full transfer (TIMx_DMAR)\nAddress offset: 0x4C\nReset value: 0x0000\n \nExample of how to use the DMA burst feature\nIn this example the timer DMA burst feature is used to update the contents of the CCRx \nregisters (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers. \nThis is done in the following steps:\n1.\nConfigure the corresponding DMA channel as follows: \n–\nDMA channel peripheral address is the DMAR register address \n–\nDMA channel memory address is the address of the buffer in the RAM containing \nthe data to be transferred by DMA into CCRx registers. \n–\nNumber of data to transfer = 3 (See note below). \n–\nCircular mode disabled. \n2. \nConfigure the DCR register by configuring the DBA and DBL bit fields as follows: \nDBL = 3 transfers, DBA = 0xE. \n3. \nEnable the TIMx update DMA request (set the UDE bit in the DIER register). \n4. \nEnable TIMx \n5. \nEnable the DMA channel\nNote:\nThis example is for the case where every CCRx register to be updated once. If every CCRx \nregister is to be updated twice for example, the number of data to transfer should be 6. Let's \ntake the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and \ndata6. The data is transferred to the CCRx registers as follows: on the first update DMA \nrequest, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to \nCCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is \ntransferred to CCR3 and data6 is transferred to CCR4. \n18.4.19 \nTIM2 option register (TIM2_OR)\nAddress offset: 0x50\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDMAB[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 DMAB[15:0]: DMA register for burst accesses\nA read or write operation to the DMAR register accesses the register located at the address\n(TIMx_CR1 address) + (DBA + DMA index) x 4 \nwhere TIMx_CR1 address is the address of the control register 1, DBA is the DMA base \naddress configured in TIMx_DCR register, DMA index is automatically controlled by the \nDMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nITR1_RMP\nReserved\nrw\nrw\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n650/1757\nRM0090 Rev 21\n \n18.4.20 \nTIM5 option register (TIM5_OR)\nAddress offset: 0x50\nReset value: 0x0000\n \nBits 15:12 Reserved, must be kept at reset value.\nBits 11:10 ITR1_RMP: Internal trigger 1 remap\nSet and cleared by software.\n00: TIM8_TRGOUT\n01: PTP trigger output is connected to TIM2_ITR1\n10: OTG FS SOF is connected to the TIM2_ITR1 input\n11: OTG HS SOF is connected to the TIM2_ITR1 input\nBits 9:0 Reserved, must be kept at reset value.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTI4_RMP\nReserved\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value.\nBits 7:6 TI4_RMP: Timer Input 4 remap\nSet and cleared by software.\n00: TIM5 Channel4 is connected to the GPIO: Refer to the Alternate function mapping table \nin the datasheets.\n01: the LSI internal clock is connected to the TIM5_CH4 input for calibration purposes\n10: the LSE internal clock is connected to the TIM5_CH4 input for calibration purposes\n11: the RTC wake-up interrupt is connected to TIM5_CH4 input for calibration purposes. \nWake-up interrupt should be enabled. \nBits 5:0 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n651/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n18.4.21 \nTIMx register map\nTIMx registers are mapped as described in the table below: \n \nTable 101. TIM2 to TIM5 register map and reset values \nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nTIMx_CR1\nReserved\nCKD \n[1:0]\nARPE\nCMS\n[1:0]\nDIR\nOPM\nURS\nUDIS\nCEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nTIMx_CR2\nReserved\nTI1S\nMMS[2:0]\nCCDS\nReserved\nReset value\n0\n0\n0\n0\n0\n0x08\nTIMx_SMCR\nReserved\nETP\nECE\nETPS \n[1:0]\nETF[3:0]\nMSM\nTS[2:0]\nReserved\nSMS[2:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nTIMx_DIER\nReserved\nTDE\nCOMDE\nCC4DE\nCC3DE\nCC2DE\nCC1DE\nUDE\nReserved\nTIE\nReserved\nCC4IE\nCC3IE\nCC2IE\nCC1IE\nUIE\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nTIMx_SR\nReserved\nCC4OF\nCC3OF\nCC2OF\nCC1OF\nReserved\nTIF\nReserved\nCC4IF\nCC3IF\nCC2IF\nCC1IF\nUIF\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nTIMx_EGR\nReserved\nTG\nReserved\nCC4G\nCC3G\nCC2G\nCC1G\nUG\nReset value\n0\n0\n0\n0\n0\n0\n0x18\nTIMx_CCMR1\nOutput Compare \nmode\nReserved\nOC2CE\nOC2M\n[2:0]\nOC2PE\nOC2FE\nCC2S \n[1:0]\nOC1CE\nOC1M\n[2:0]\nOC1PE\nOC1FE\nCC1S \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTIMx_CCMR1\nInput Capture \nmode\nReserved\nIC2F[3:0]\nIC2\nPSC\n[1:0]\nCC2S \n[1:0]\nIC1F[3:0]\nIC1\nPSC\n[1:0]\nCC1S \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nTIMx_CCMR2\nOutput Compare \nmode\nReserved\nOC4CE\nOC4M\n[2:0]\nOC4PE\nOC4FE\nCC4S \n[1:0]\nOC3CE\nOC3M\n[2:0]\nOC3PE\nOC3FE\nCC3S \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTIMx_CCMR2\nInput Capture \nmode\nReserved\nIC4F[3:0]\nIC4\nPSC\n[1:0]\nCC4S \n[1:0]\nIC3F[3:0]\nIC3\nPSC\n[1:0]\nCC3S \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nTIMx_CCER\nReserved\nCC4NP\nReserved\nCC4P\nCC4E\nCC3NP\nReserved\nCC3P\nCC3E\nCC2NP\nReserved\nCC2P\nCC2E\nCC1NP\nReserved\nCC1P\nCC1E\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x24\nTIMx_CNT\nCNT[31:16]\n(TIM2 and TIM5 only, reserved on the other timers)\nCNT[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nTIMx_PSC\nReserved\nPSC[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n\n\n<>\n\nGeneral-purpose timers (TIM2 to TIM5)\nRM0090\n652/1757\nRM0090 Rev 21\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x2C\nTIMx_ARR\nARR[31:16]\n(TIM2 and TIM5 only, reserved on the other timers)\nARR[15:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x30\nReserved\n0x34\nTIMx_CCR1\nCCR1[31:16]\n(TIM2 and TIM5 only, reserved on the other timers)\nCCR1[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x38\nTIMx_CCR2\nCCR2[31:16]\n(TIM2 and TIM5 only, reserved on the other timers)\nCCR2[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x3C\nTIMx_CCR3\nCCR3[31:16]\n(TIM2 and TIM5 only, reserved on the other timers)\nCCR3[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x40\nTIMx_CCR4\nCCR4[31:16]\n(TIM2 and TIM5 only, reserved on the other timers)\nCCR4[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x44\nReserved\n0x48\nTIMx_DCR\nReserved\nDBL[4:0]\nReserved\nDBA[4:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x4C\nTIMx_DMAR\nReserved\nDMAB[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x50\nTIM2_OR\nReserved\nReserved\nITR1_\nRMP\nReserved\nReset value\n0\n0\n0x50\nTIM5_OR\nReserved\nReserved\nIT4_\nRMP\nReserved\nReset value\n0\n0\nTable 101. TIM2 to TIM5 register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n653/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19 \nGeneral-purpose timers (TIM9 to TIM14)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n19.1 \nTIM9 to TIM14 introduction\nThe TIM9 to TIM14 general-purpose timers consist of a 16-bit auto-reload counter driven by \na programmable prescaler.\nThey may be used for a variety of purposes, including measuring the pulse lengths of input \nsignals (input capture) or generating output waveforms (output compare, PWM).\nPulse lengths and waveform periods can be modulated from a few microseconds to several \nmilliseconds using the timer prescaler and the RCC clock controller prescalers.\nThe TIM9 to TIM14 timers are completely independent, and do not share any resources. \nThey can be synchronized together as described in Section 19.3.12.\n19.2 \nTIM9 to TIM14 main features\n19.2.1 \nTIM9/TIM12 main features\nThe features of the TIM9 to TIM14 general-purpose timers include:\n•\n16-bit auto-reload upcounter\n•\n16-bit programmable prescaler used to divide the counter clock frequency by any factor \nbetween 1 and 65536 (can be changed “on the fly”)\n•\nUp to 2 independent channels for:\n–\nInput capture\n–\nOutput compare\n–\nPWM generation (edge-aligned mode)\n–\nOne-pulse mode output\n•\nSynchronization circuit to control the timer with external signals and to interconnect \nseveral timers together\n•\nInterrupt generation on the following events:\n–\nUpdate: counter overflow, counter initialization (by software or internal trigger)\n–\nTrigger event (counter start, stop, initialization or count by internal trigger)\n–\nInput capture\n–\nOutput compare\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n654/1757\nRM0090 Rev 21\nFigure 180. General-purpose timer block diagram (TIM9 and TIM12) \n19.2.2 \nTIM10/TIM11 and TIM13/TIM14 main features\nThe features of general-purpose timers TIM10/TIM11 and TIM13/TIM14 include:\n•\n16-bit auto-reload upcounter\n•\n16-bit programmable prescaler used to divide the counter clock frequency by any factor \nbetween 1 and 65536 (can be changed “on the fly”)\n•\nindependent channel for:\n–\nInput capture\n–\nOutput compare\n–\nPWM generation (edge-aligned mode)\n–\nOne-pulse mode output\n•\nInterrupt generation on the following events:\n–\nUpdate: counter overflow, counter initialization (by software)\n–\nInput capture\n–\nOutput compare\nU\nU\nU\nCC1I\nCC2I\nTrigger\ncontroller\n+/-\nStop, Clear\nTI1FP1\nTI2FP2\nITR0\nITR1\nITR2\nTRGI\nOutput\ncontrol\nOC1REF\nOC2REF\nU\nUI\nReset, enable, up, count\nCK_PSC\nIC1\nIC2\nIC2PS\nIC1PS\nTI1FP1\nTGI\nTRC\nTRC\nITR\nTRC\nTI1F_ED\nCC1I\nCC2I\nTI1FP2\nTI2FP1\nTI2FP2\nTI1\nTI2\nTIMx_CH1\nTIMx_CH2\nOC1\nOC2\nTIMx_CH1\nTIMx_CH2\nSlave \ncontroller \nmode\nPSC\nprescaler\nCNT counter\nInternal clock (CK_INT)\nCK_CNT\nITR3\nai17190b\nInput filter & \nedge detector\nCapture/Compare 1 register\nNotes:\nReg\nPreload registers transferred\nto active registers on U event\naccording to control bit\nEvent\nInterrupt\nAuto-reload register\nCapture/Compare 2 register\nPrescaler\nPrescaler\nInput filter & \nedge detector\nOutput\ncontrol\n\n\n<>\n\nRM0090 Rev 21\n655/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\nFigure 181. General-purpose timer block diagram (TIM10/11/13/14)\nAutoreload register\nCapture/Compare 1 register\nU\nU\nCC1I\nStop, Clear \noutput\ncontrol\nOC1\nOC1REF\nU\nUI\nIC1\nPrescaler\nInput filter &\nedge detector\nIC1PS\nTI1FP1\nReg\nevent\nNotes: \nPreload registers transferred\nto active registers on U event \naccording to control bit\ninterrupt & DMA output\nCC1I\nTI1\nTIMx_CH1\nprescaler\ncounter\n+/-\nCK_PSC\nPSC\nCNT\nCK_CNT\nInternal clock (CK_INT)\nai17725c\nTrigger\nController\nEnable\ncounter\nTIMx_CH1\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n656/1757\nRM0090 Rev 21\n19.3 \nTIM9 to TIM14 functional description\n19.3.1 \nTime-base unit\nThe main block of the timer is a 16-bit counter with its related auto-reload register. The \ncounters counts up. \nThe counter clock can be divided by a prescaler.\nThe counter, the auto-reload register and the prescaler register can be written or read by \nsoftware. This is true even when the counter is running.\nThe time-base unit includes:\n•\nCounter register (TIMx_CNT)\n•\nPrescaler register (TIMx_PSC)\n•\nAuto-reload register (TIMx_ARR)\nThe auto-reload register is preloaded. Writing to or reading from the auto-reload register \naccesses the preload register. The content of the preload register are transferred into the \nshadow register permanently or at each update event (UEV), depending on the auto-reload \npreload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter \nreaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be \ngenerated by software. The generation of the update event is described in details for each \nconfiguration.\nThe counter is clocked by the prescaler output CK_CNT, which is enabled only when the \ncounter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller \ndescription to get more details on counter enabling). \nNote that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 \nregister.\nPrescaler description\nThe prescaler can divide the counter clock frequency by any factor between 1 and 65536. It \nis based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). \nIt can be changed on the fly as this control register is buffered. The new prescaler ratio is \ntaken into account at the next update event.\nFigure 182 and Figure 183 give some examples of the counter behavior when the prescaler \nratio is changed on the fly.\n\n\n<>\n\nRM0090 Rev 21\n657/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\nFigure 182. Counter timing diagram with prescaler division change from 1 to 2\nFigure 183. Counter timing diagram with prescaler division change from 1 to 4\nCK_PSC\n00\nCEN\n \nTimerclock = CK_CNT\n \n \nCounter register\nUpdate event (UEV)\n0\nPrescaler control register\n1\n0\nWrite a new value in TIMx_PSC\nPrescaler buffer\n1\n0\nPrescaler counter\n0\n1\n0\n1\n0\n1\n0\n1\n01\n02\n03\nFA\nFB\nF7\nF8\nF9\nFC\nMS31076V2\n0\n3\n0\n0\n1\n2\n3\n0\n1\n2\n3\nMS31077V2\nCK_PSC\nCEN\n \nTimerclock = CK_CNT\n \n \nCounter register\nUpdate event (UEV)\nPrescaler control register\nWrite a new value in TIMx_PSC\nPrescaler buffer\nPrescaler counter\n00\n01\nFA\nFB\nF7\nF8\nF9\nFC\n3\n0\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n658/1757\nRM0090 Rev 21\n19.3.2 \nCounter modes\nUpcounting mode\nIn upcounting mode, the counter counts from 0 to the auto-reload value (content of the \nTIMx_ARR register), then restarts from 0 and generates a counter overflow event.\nSetting the UG bit in the TIMx_EGR register (by software or by using the slave mode \ncontroller on TIM9 and TIM12) also generates an update event.\nThe UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 \nregister. This is to avoid updating the shadow registers while writing new values in the \npreload registers. Then no update event occurs until the UDIS bit has been written to 0. \nHowever, the counter restarts from 0, as well as the counter of the prescaler (but the \nprescale rate does not change). In addition, if the URS bit (update request selection) in \nTIMx_CR1 register is set, setting the UG bit generates an update event UEV but without \nsetting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and \ncapture interrupts when clearing the counter on the capture event.\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in \nTIMx_SR register) is set (depending on the URS bit):\n•\nThe auto-reload shadow register is updated with the preload value (TIMx_ARR),\n•\nThe buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC \nregister).\nThe following figures show some examples of the counter behavior for different clock \nfrequencies when TIMx_ARR=0x36.\nFigure 184. Counter timing diagram, internal clock divided by 1\n00\n02\n03\n04\n05\n06\n07\n33\n34\n35\n36\n31\nMS31078V3\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n01\n32\n\n\n<>\n\nRM0090 Rev 21\n659/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\nFigure 185. Counter timing diagram, internal clock divided by 2\nFigure 186. Counter timing diagram, internal clock divided by 4\nFigure 187. Counter timing diagram, internal clock divided by N\nMS31079V3\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n0034\n0035\n0036\n0000\n0001\n0002\n0003\nMS31080V3\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n0000\n0001\n0035\n0036\nMS31081V3\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n1F\n20\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n660/1757\nRM0090 Rev 21\nFigure 188. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not \npreloaded)\nFigure 189. Counter timing diagram, update event when ARPE=1 (TIMx_ARR \npreloaded)\nFF\n36\nMS31082V3\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n02\n03\n04\n05\n06\n07\n32\n33\n34\n35\n36\n31\n01\nCEN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\nMS31083V2\nF5\n36\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag\n (UIF)\n00\n02\n03\n04\n05\n06\n07\nF1\nF2\nF3\nF4\nF5\nF0\n01\nCEN\nAuto-reload preload\nregister\nWrite a new value in TIMx_ARR\nAuto-reload shadow\nregister\nF5\n36\n\n\n<>\n\nRM0090 Rev 21\n661/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.3.3 \nClock selection\nThe counter clock can be provided by the following clock sources:\n•\nInternal clock (CK_INT)\n•\nExternal clock mode1 (for TIM9 and TIM12): external input pin (TIx) \n•\nInternal trigger inputs (ITRx) (for TIM9 and TIM12): connecting the trigger output from \nanother timer. Refer to Using one timer as prescaler for another timer for more details.\nInternal clock source (CK_INT)\nThe internal clock source is the default clock source for TIM10/TIM11 and TIM13/TIM14. \nFor TIM9 and TIM12, the internal clock source is selected when the slave mode controller is \ndisabled (SMS=’000’). The CEN bit in the TIMx_CR1 register and the UG bit in the \nTIMx_EGR register are then used as control bits and can be changed only by software \n(except for UG which remains cleared). As soon as the CEN bit is programmed to 1, the \nprescaler is clocked by the internal clock CK_INT. \nFigure 190 shows the behavior of the control circuit and of the upcounter in normal mode, \nwithout prescaler.\nFigure 190. Control circuit in normal mode, internal clock divided by 1\nExternal clock source mode 1(TIM9 and TIM12)\nThis mode is selected when SMS=’111’ in the TIMx_SMCR register. The counter can count \nat each rising or falling edge on a selected input.\nInternal clock\nCounter clock = CK_CNT = CK_PSC\nCounter register\nCEN=CNT_EN\nUG\nCNT_INIT\nMS31085V2\n00\n02\n03\n04\n05\n06\n07\n3 2\n33\n34\n35 36\n31\n01\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n662/1757\nRM0090 Rev 21\nFigure 191. TI2 external clock connection example\nFor example, to configure the upcounter to count in response to a rising edge on the TI2 \ninput, use the following procedure:\n1.\nConfigure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in \nthe TIMx_CCMR1 register.\n2. \nConfigure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 \nregister (if no filter is needed, keep IC2F=’0000’).\n3. \nSelect the rising edge polarity by writing CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER \nregister.\n4. \nConfigure the timer in external clock mode 1 by writing SMS=’111’ in the TIMx_SMCR \nregister. \n5. \nSelect TI2 as the trigger input source by writing TS=’110’ in the TIMx_SMCR register.\n6. \nEnable the counter by writing CEN=’1’ in the TIMx_CR1 register.\nNote:\nThe capture prescaler is not used for triggering, so no need to configure it.\nWhen a rising edge occurs on TI2, the counter counts once and the TIF flag is set.\nThe delay between the rising edge on TI2 and the actual clock of the counter is due to the \nresynchronization circuit on TI2 input.\nFigure 192. Control circuit in external clock mode 1\nExternal clock \nmode 1\nInternal clock\nmode\nTRGI\nCK_INT\nCK_PSC\nTIMx_SMCR\nSMS[2:0]\nITRx\nTI1_ED\nTI1FP1\nTI2FP2\nTIMx_SMCR\nTS[2:0]\nTI2\n0\n1\nTIMx_CCER\nCC2P\nFilter\nICF[3:0]\nTIMx_CCMR1\nEdge\ndetector\nTI2F_Rising\nTI2F_Falling\n110\n0xx\n100\n101\nMS37337V1\n(internal clock)\nTI1F\nor\nTI2F\nor\nor\nCounter clock = CK_CNT = CK_PSC\nCounter register\n35\n36\n34\nTI2\nCNT_EN\nTIF\nWrite TIF = 0\nMS31087V3\n\n\n<>\n\nRM0090 Rev 21\n663/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.3.4 \nCapture/compare channels\nEach Capture/Compare channel is built around a capture/compare register (including a \nshadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and \nan output stage (with comparator and output control).\nFigure 193 to Figure 195 give an overview of a capture/compare channel.\nThe input stage samples the corresponding TIx input to generate a filtered signal TIxF. \nThen, an edge detector with polarity selection generates a signal (TIxFPx) which can be \nused as trigger input by the slave mode controller or as the capture command. It is \nprescaled before the capture register (ICxPS).\nFigure 193. Capture/compare channel (example: channel 1 input stage)\nThe output stage generates an intermediate waveform which is then used for reference: \nOCxRef (active high). The polarity acts at the end of the chain.\n0\n1\nDivider\n/1, /2, /4, /8\nICPS[1:0]\nTI1F_ED\nTo the slave mode controller\nTI1FP1\n11\n01\nCC1S[1:0]\nIC1\nTI2FP1\nTRC\n(from slave mode\ncontroller)\n10\nIC1PS\n0\n1\nMS33115V1\nTI1\nTIMx_CCER\nCC1P/CC1NP\nFilter\ndowncounter\nICF[3:0]\nTIMx_CCMR1\nEdge\ndetector\nTI1F_Rising\nTI1F_Falling\nTIMx_CCMR1\nTIMx_CCER\nTI2F_Rising\n(from channel 2)\nTI2F_Falling\n(from channel 2)\nTI1F\nf\nCC1E\nDTS\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n664/1757\nRM0090 Rev 21\nFigure 194. Capture/compare channel 1 main circuit\nFigure 195. Output stage of capture/compare channel (channel 1)\nThe capture/compare block is made of one preload register and one shadow register. Write \nand read always access the preload register. \nIn capture mode, captures are actually done in the shadow register, which is copied into the \npreload register. \nIn compare mode, the content of the preload register is copied into the shadow register \nwhich is compared to the counter.\n19.3.5 \nInput capture mode\nIn Input capture mode, the Capture/Compare registers (TIMx_CCRx) are used to latch the \nvalue of the counter after a transition detected by the corresponding ICx signal. When a \ncapture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or \na DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was \nalready high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be \nMS31089V3\nCC1E\nCapture/compare shadow register\nComparator\nCapture/compare preload register\nCounter\nIC1PS\nCC1S[0]\nCC1S[1]\nCapture\nInput \nmode\nS\nR\nRead CCR1H\nRead CCR1L\nread_in_progress\ncapture_transfer\nCC1S[0]\nCC1S[1]\nS\nR\nwrite CCR1H\nwrite CCR1L\nwrite_in_progress\nOutput \nmode\nUEV\nOC1PE\n(from time \nbase unit)\ncompare_transfer\nAPB Bus\n8\n8\nhigh\nlow\n(if 16-bit)\nMCU-peripheral interface\nTIMx_CCMR1\nOC1PE\nCNT>CCR1\nCNT=CCR1\nTIMx_EGR\nCC1G\nai17720\nOutput \nmode\ncontroller\nCNT > CCR2\nCNT = CCR2\nTIMx_CCMR1\nOC2M[2:0]\n0\n1\nCC1P\nTIMx_CCER\nOutput\nenable\ncircuit\nOC1\nCC1E TIMx_CCER\nTo the master \nmode controller\nOC1_REF\n\n\n<>\n\nRM0090 Rev 21\n665/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\ncleared by software by writing it to ‘0’ or by reading the captured data stored in the \nTIMx_CCRx register. CCxOF is cleared when the user writes it to ‘0’.\nThe following example shows how to capture the counter value in TIMx_CCR1 when TI1 \ninput rises. To do this, use the following procedure:\n1.\nSelect the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S \nbits to ‘01’ in the TIMx_CCMR1 register. As soon as CC1S becomes different from ‘00’, \nthe channel is configured in input mode and the TIMx_CCR1 register becomes read-\nonly.\n2. \nProgram the needed input filter duration with respect to the signal connected to the \ntimer (by programming the ICxF bits in the TIMx_CCMRx register if the input is one of \nthe TIx inputs). Let us imagine that, when toggling, the input signal is not stable during \nat least five internal clock cycles. We must program a filter duration longer than these 5 \nclock cycles. We can validate a transition on TI1 when eight consecutive samples with \nthe new level have been detected (sampled at fDTS frequency). Then write IC1F bits to \n‘0011’ in the TIMx_CCMR1 register.\n3. \nSelect the edge of the active transition on the TI1 channel by programming CC1P and \nCC1NP bits to ‘00’ in the TIMx_CCER register (rising edge in this case).\n4. \nProgram the input prescaler. In our example, we wish the capture to be performed at \neach valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the \nTIMx_CCMR1 register).\n5. \nEnable capture from the counter into the capture register by setting the CC1E bit in the \nTIMx_CCER register.\n6. \nIf needed, enable the related interrupt request by setting the CC1IE bit in the \nTIMx_DIER register.\nWhen an input capture occurs:\n•\nThe TIMx_CCR1 register gets the value of the counter on the active transition.\n•\nCC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures \noccurred whereas the flag was not cleared.\n•\nAn interrupt is generated depending on the CC1IE bit.\nIn order to handle the overcapture, it is recommended to read the data before the \novercapture flag. This is to avoid missing an overcapture which could happen after reading \nthe flag and before reading the data.\nNote:\nIC interrupt requests can be generated by software by setting the corresponding CCxG bit in \nthe TIMx_EGR register.\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n666/1757\nRM0090 Rev 21\n19.3.6 \nPWM input mode (only for TIM9/12)\nThis mode is a particular case of input capture mode. The procedure is the same except:\n•\nTwo ICx signals are mapped on the same TIx input.\n•\nThese 2 ICx signals are active on edges with opposite polarity.\n•\nOne of the two TIxFP signals is selected as trigger input and the slave mode controller \nis configured in reset mode.\nFor example, the user can measure the period (in TIMx_CCR1 register) and the duty cycle \n(in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure \n(depending on CK_INT frequency and prescaler value):\n1.\nSelect the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1 \nregister (TI1 selected).\n2. \nSelect the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter \nclear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge).\n3. \nSelect the active input for TIMx_CCR2: write the CC2S bits to ‘10’ in the TIMx_CCMR1 \nregister (TI1 selected).\n4. \nSelect the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P \nbit to '1' and the CC2NP bit to '0' (active on falling edge).\n5. \nSelect the valid trigger input: write the TS bits to ‘101’ in the TIMx_SMCR register \n(TI1FP1 selected).\n6. \nConfigure the slave mode controller in reset mode: write the SMS bits to ‘100’ in the \nTIMx_SMCR register.\n7. \nEnable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.\nFigure 196. PWM input mode timing\n1.\nThe PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only \nTI1FP1 and TI2FP2 are connected to the slave mode controller.\nTI1\nTIMx_CNT\n0000\n0001\n0002\n0003\n0004\n0000\n0004\nTIMx_CCR1\nTIMx_CCR2\n0004\n0002\nIC1 capture\nIC2 capture\nreset counter\nIC2 capture\npu\nl se wid th\n \nIC1 capture\nperiod\nmeasurement\nmeasurement\nai15413\n\n\n<>\n\nRM0090 Rev 21\n667/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.3.7 \nForced output mode\nIn output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal \n(OCxREF and then OCx) can be forced to active or inactive level directly by software, \nindependently of any comparison between the output compare register and the counter.\nTo force an output compare signal (OCXREF/OCx) to its active level, the user just needs to \nwrite ‘101’ in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is \nforced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity \nbit.\nFor example: CCxP=’0’ (OCx active high) => OCx is forced to high level.\nThe OCxREF signal can be forced low by writing the OCxM bits to ‘100’ in the \nTIMx_CCMRx register.\nAnyway, the comparison between the TIMx_CCRx shadow register and the counter is still \nperformed and allows the flag to be set. Interrupt requests can be sent accordingly. This is \ndescribed in the output compare mode section below.\n19.3.8 \nOutput compare mode\nThis function is used to control an output waveform or indicating when a period of time has \nelapsed.\nWhen a match is found between the capture/compare register and the counter, the output \ncompare function: \n1.\nAssigns the corresponding output pin to a programmable value defined by the output \ncompare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP \nbit in the TIMx_CCER register). The output pin can keep its level (OCXM=’000’), be set \nactive (OCxM=’001’), be set inactive (OCxM=’010’) or can toggle (OCxM=’011’) on \nmatch.\n2. \nSets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).\n3. \nGenerates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the \nTIMx_DIER register).\nThe TIMx_CCRx registers can be programmed with or without preload registers using the \nOCxPE bit in the TIMx_CCMRx register.\nIn output compare mode, the update event UEV has no effect on OCxREF and OCx output. \nThe timing resolution is one count of the counter. Output compare mode can also be used to \noutput a single pulse (in One-pulse mode).\nProcedure:\n1.\nSelect the counter clock (internal, external, prescaler).\n2. \nWrite the desired data in the TIMx_ARR and TIMx_CCRx registers.\n3. \nSet the CCxIE bit if an interrupt request is to be generated.\n4. \nSelect the output mode. For example:\n–\nWrite OCxM = ‘011’ to toggle OCx output pin when CNT matches CCRx\n–\nWrite OCxPE = ‘0’ to disable preload register\n–\nWrite CCxP = ‘0’ to select active high polarity\n–\nWrite CCxE = ‘1’ to enable the output\n5. \nEnable the counter by setting the CEN bit in the TIMx_CR1 register.\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n668/1757\nRM0090 Rev 21\nThe TIMx_CCRx register can be updated at any time by software to control the output \nwaveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx \nshadow register is updated only at the next update event UEV). An example is given in \nFigure 197.\nFigure 197. Output compare mode, toggle on OC1.\n19.3.9 \nPWM mode\nPulse Width Modulation mode allows the user to generate a signal with a frequency \ndetermined by the value of the TIMx_ARR register and a duty cycle determined by the value \nof the TIMx_CCRx register.\nThe PWM mode can be selected independently on each channel (one PWM per OCx \noutput) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the \nTIMx_CCMRx register. Enable the corresponding preload register by setting the OCxPE bit \nin the TIMx_CCMRx register, and eventually the auto-reload preload register by setting the \nARPE bit in the TIMx_CR1 register.\nAs the preload registers are transferred to the shadow registers only when an update event \noccurs, before starting the counter, the user has to initialize all the registers by setting the \nUG bit in the TIMx_EGR register.\nThe OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. \nIt can be programmed as active high or active low. The OCx output is enabled by the CCxE \nbit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more \ndetails.\nIn PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine \nwhether TIMx_CNT ≤TIMx_CCRx.\nThe timer is able to generate PWM in edge-aligned mode only since the counter is \nupcounting.\nPWM edge-aligned mode\nIn the following example, we consider PWM mode 1. The reference PWM signal OCxREF is \nhigh as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in \nMS31092V2\nOC1REF= OC1\nTIM1_CNT\nB200\nB201\n0039\nTIM1_CCR1\n003A\nWrite B201h in the CC1R register\nMatch detected on CCR1\nInterrupt generated if enabled\n003B\nB201\n003A\n\n\n<>\n\nRM0090 Rev 21\n669/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\nTIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at \n‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 198 shows some edge-\naligned PWM waveforms in an example where TIMx_ARR=8.\nFigure 198. Edge-aligned PWM waveforms (ARR=8)\n19.3.10 \nOne-pulse mode\nOne-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to \nbe started in response to a stimulus and to generate a pulse with a programmable length \nafter a programmable delay.\nStarting the counter can be controlled through the slave mode controller. Generating the \nwaveform can be done in output compare mode or PWM mode. Select One-pulse mode by \nsetting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at \nthe next update event UEV.\nA pulse can be correctly generated only if the compare value is different from the counter \ninitial value. Before starting (when the timer is waiting for the trigger), the configuration must \nbe as follows:\nCNT < CCRx≤ARR (in particular, 0 < CCRx)\nMS31093V1\nCounter register\n‘1’\n0\n1\n2\n3\n4\n5\n6\n7\n8\n0\n1\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nCCRx=4\nCCRx=8\nCCRx>8\nCCRx=0\n‘0’\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n670/1757\nRM0090 Rev 21\nFigure 199. Example of one pulse mode.\nFor example the user may want to generate a positive pulse on OC1 with a length of tPULSE \nand after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.\nUse TI2FP2 as trigger 1:\n1.\nMap TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.\n2. \nTI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP = ‘0’ in the TIMx_CCER \nregister.\n3. \nConfigure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in \nthe TIMx_SMCR register.\n4. \nTI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register \n(trigger mode).\nThe OPM waveform is defined by writing the compare registers (taking into account the \nclock frequency and the counter prescaler).\n•\nThe tDELAY is defined by the value written in the TIMx_CCR1 register.\n•\nThe tPULSE is defined by the difference between the auto-reload value and the compare \nvalue (TIMx_ARR - TIMx_CCR1).\n•\nLet us say the user wants to build a waveform with a transition from ‘0’ to ‘1’ when a \ncompare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the \nauto-reload value. To do this enable PWM mode 2 by writing OC1M=’111’ in the \nTIMx_CCMR1 register. The user can optionally enable the preload registers by writing \nOC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this \ncase the user has to write the compare value in the TIMx_CCR1 register, the auto-\nreload value in the TIMx_ARR register, generate an update by setting the UG bit and \nwait for external trigger event on TI2. CC1P is written to ‘0’ in this example.\nThe user only wants one pulse (Single mode), so write '1 in the OPM bit in the TIMx_CR1 \nregister to stop the counter at the next update event (when the counter rolls over from the \nauto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the \nRepetitive mode is selected.\nMS31099V1\nTI2\nOC1REF\nCounter\nt\n0\nTIM1_ARR\nTIM1_CCR1\nOC1\ntDELAY\ntPULSE\n\n\n<>\n\nRM0090 Rev 21\n671/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\nParticular case: OCx fast enable\nIn One-pulse mode, the edge detection on TIx input set the CEN bit which enables the \ncounter. Then the comparison between the counter and the compare value makes the \noutput toggle. But several clock cycles are needed for these operations and it limits the \nminimum delay tDELAY min we can get.\nIf the user wants to output a waveform with the minimum delay, set the OCxFE bit in the \nTIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, \nwithout taking in account the comparison. Its new level is the same as if a compare match \nhad occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.\n19.3.11 \nTIM9/12 external trigger synchronization\nThe TIM9/12 timers can be synchronized with an external trigger in several modes: Reset \nmode, Gated mode and Trigger mode.\nSlave mode: Reset mode\nThe counter and its prescaler can be reinitialized in response to an event on a trigger input. \nMoreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is \ngenerated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.\nIn the following example, the upcounter is cleared in response to a rising edge on TI1 input:\n1.\nConfigure the channel 1 to detect rising edges on TI1. Configure the input filter duration \n(in this example, no need of any filter, IC1F = 0000 kept). The capture prescaler is not \nused for triggering, so there’s no need to configure it. The CC1S bits select the input \ncapture source only, CC1S = ‘01’ in the TIMx_CCMR1 register. Program CC1P and \nCC1NP to ‘00’ in TIMx_CCER register to validate the polarity (and detect rising edges \nonly).\n2. \nConfigure the timer in reset mode by writing SMS=’100’ in TIMx_SMCR register. Select \nTI1 as the input source by writing TS=’101’ in TIMx_SMCR register.\n3. \nStart the counter by writing CEN=’1’ in the TIMx_CR1 register.\nThe counter starts counting on the internal clock, then behaves normally until TI1 rising \nedge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the \ntrigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request can be sent if \nenabled (depending on the TIE bit in TIMx_DIER register).\nThe following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. \nThe delay between the rising edge on TI1 and the actual reset of the counter is due to the \nresynchronization circuit on TI1 input.\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n672/1757\nRM0090 Rev 21\nFigure 200. Control circuit in reset mode\nSlave mode: Gated mode\nThe counter can be enabled depending on the level of a selected input.\nIn the following example, the upcounter counts only when TI1 input is low:\n1.\nConfigure the channel 1 to detect low levels on TI1. Configure the input filter duration \n(in this example, no need of any filter, IC1F=’0000’ kept). The capture prescaler is not \nused for triggering, so there’s no need to configure it. The CC1S bits select the input \ncapture source only, CC1S=’01’ in TIMx_CCMR1 register. Program CC1P=’1’ and \nCC1NP= ‘0’ in TIMx_CCER register to validate the polarity (and detect low level only).\n2. \nConfigure the timer in gated mode by writing SMS=’101’ in TIMx_SMCR register. \nSelect TI1 as the input source by writing TS=’101’ in TIMx_SMCR register.\n3. \nEnable the counter by writing CEN=’1’ in the TIMx_CR1 register (in gated mode, the \ncounter does not start if CEN=’0’, whatever is the trigger input level).\nThe counter starts counting on the internal clock as long as TI1 is low and stops as soon as \nTI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts \nor stops.\nThe delay between the rising edge on TI1 and the actual stop of the counter is due to the \nresynchronization circuit on TI1 input.\nMS31401V2\n00\nCounter clock = ck_cnt = ck_psc\nCounter register\n01 02 03\n00\n01 02 03\n32\n33\n34\n35\n36\nUG\nTI1\n31\n30\nTIF\n\n\n<>\n\nRM0090 Rev 21\n673/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\nFigure 201. Control circuit in gated mode\nSlave mode: Trigger mode\nThe counter can start in response to an event on a selected input.\nIn the following example, the upcounter starts in response to a rising edge on TI2 input:\n1.\nConfigure the channel 2 to detect rising edges on TI2. Configure the input filter duration \n(in this example, no need of any filter, IC2F=’0000’ kept). The capture prescaler is not \nused for triggering, so there’s no need to configure it. The CC2S bits are configured to \nselect the input capture source only, CC2S=’01’ in TIMx_CCMR1 register. Program \nCC2P=’1’ and CC2NP=’0’ in TIMx_CCER register to validate the polarity (and detect \nlow level only).\n2. \nConfigure the timer in trigger mode by writing SMS=’110’ in TIMx_SMCR register. \nSelect TI2 as the input source by writing TS=’110’ in TIMx_SMCR register.\nWhen a rising edge occurs on TI2, the counter starts counting on the internal clock and the \nTIF flag is set.\nThe delay between the rising edge on TI2 and the actual start of the counter is due to the \nresynchronization circuit on TI2 input.\nFigure 202. Control circuit in trigger mode\nMS31402V1\nTI1\ncnt_en\nWrite TIF=0\n37\nCounter clock = ck_cnt = ck_psc\nCounter register\n38\n32\n33\n34\n35\n36\n31\n30\nTIF\nMS31403V1\nTI2\ncnt_en\n37\nCounter clock = ck_cnt = ck_psc\nCounter register\n38\n34\n35\n36\nTIF\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n674/1757\nRM0090 Rev 21\n19.3.12 \nTimer synchronization (TIM9/12)\nThe TIM timers are linked together internally for timer synchronization or chaining. Refer to \nSection 18.3.15: Timer synchronization for details.\nNote:\nThe clock of the slave timer must be enabled prior to receive events from the master timer, \nand must not be changed on-the-fly while triggers are received from the master timer.\n19.3.13 \nDebug mode\nWhen the microcontroller enters debug mode (Cortex®-M4 with FPU core halted), the TIMx \ncounter either continues to work normally or stops, depending on DBG_TIMx_STOP \nconfiguration bit in DBG module. For more details, refer to Section 38.16.2: Debug support \nfor timers, watchdog, bxCAN and I2C.\n\n\n<>\n\nRM0090 Rev 21\n675/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.4 \nTIM9 and TIM12 registers\nRefer to Section 2.2 for a list of abbreviations used in register descriptions.\nThe peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read \naccesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). \n19.4.1 \nTIM9/12 control register 1 (TIMx_CR1)\nAddress offset: 0x00\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCKD[1:0]\nARPE\nReserved\nOPM\nURS\nUDIS\nCEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:10 Reserved, must be kept at reset value.\nBits 9:8 CKD: Clock division\nThis bit-field indicates the division ratio between the timer clock (CK_INT) frequency and \nsampling clock used by the digital filters (TIx),\n00: tDTS = tCK_INT\n01: tDTS = 2 × tCK_INT\n10: tDTS = 4 × tCK_INT\n11: Reserved\nBit 7 ARPE: Auto-reload preload enable\n0: TIMx_ARR register is not buffered.\n1: TIMx_ARR register is buffered.\nBits 6:4 Reserved, must be kept at reset value.\nBit 3 OPM: One-pulse mode\n0: Counter is not stopped on the update event\n1: Counter stops counting on the next update event (clearing the CEN bit).\nBit 2 URS: Update request source\nThis bit is set and cleared by software to select the UEV event sources.\n0: Any of the following events generates an update interrupt if enabled:\n–\nCounter overflow\n–\nSetting the UG bit\n1: Only counter overflow generates an update interrupt if enabled.\nBit 1 UDIS: Update disable\nThis bit is set and cleared by software to enable/disable update event (UEV) generation.\n0: UEV enabled. An UEV is generated by one of the following events:\n–\nCounter overflow\n–\nSetting the UG bit\nBuffered registers are then loaded with their preload values.\n1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, \nCCRx). The counter and the prescaler are reinitialized if the UG bit is set.\nBit 0 CEN: Counter enable\n0: Counter disabled\n1: Counter enabled\nCEN is cleared automatically in one-pulse mode, when an update event occurs.\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n676/1757\nRM0090 Rev 21\n19.4.2 \nTIM9/12 slave mode control register (TIMx_SMCR)\nAddress offset: 0x08\nReset value: 0x0000\n \n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMSM\nTS[2:0]\nRes.\nSMS[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 MSM: Master/Slave mode\n0: No action\n1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect \nsynchronization between the current timer and its slaves (through TRGO). It is useful in \norder to synchronize several timers on a single external event.\nBits 6:4 TS: Trigger selection\nThis bit field selects the trigger input to be used to synchronize the counter.\n000: Internal Trigger 0 (ITR0)\n001: Internal Trigger 1 (ITR1)\n010: Internal Trigger 2 (ITR2)\n011: Internal Trigger 3 (ITR3)\n100: TI1 Edge Detector (TI1F_ED)\n101: Filtered Timer Input 1 (TI1FP1)\n110: Filtered Timer Input 2 (TI2FP2)\n111: Reserved.\nSee Table 102 for more details on the meaning of ITRx for each timer.\nNote: These bits must be changed only when they are not used (e.g. when SMS=’000’) to \navoid wrong edge detections at the transition.\n\n\n<>\n\nRM0090 Rev 21\n677/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n \n19.4.3 \nTIM9/12 Interrupt enable register (TIMx_DIER)\nAddress offset: 0x0C\nReset value: 0x0000\n \nBit 3 Reserved, must be kept at reset value.\nBits 2:0 SMS: Slave mode selection\nWhen external signals are selected, the active edge of the trigger signal (TRGI) is linked to \nthe polarity selected on the external input (see Input control register and Control register \ndescriptions.\n000: Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal \nclock\n001: Reserved\n010: Reserved\n011: Reserved\n100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter \nand generates an update of the registers\n101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The \ncounter stops (but is not reset) as soon as the trigger becomes low. Counter starts and stops \nare both controlled\n110: Trigger mode - The counter starts on a rising edge of the trigger TRGI (but it is not \nreset). Only the start of the counter is controlled\n111: External clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter\nNote: The Gated mode must not be used if TI1F_ED is selected as the trigger input \n(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the \nGated mode checks the level of the trigger signal.\nNote: The clock of the slave timer must be enabled prior to receive events from the master \ntimer, and must not be changed on-the-fly while triggers are received from the master \ntimer.\nTable 102. TIMx internal trigger connection\nSlave TIM\nITR0 (TS = 000)\nITR1 (TS = 001)\nITR2 (TS = 010)\nITR3 (TS = 011)\nTIM9\nTIM2_TRGO\nTIM3_TRGO\nTIM10_OC\nTIM11_OC\nTIM12\nTIM4_TRGO\nTIM5_TRGO\nTIM13_OC\nTIM14_OC\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTIE\nRes\nCC2IE\nCC1IE\nUIE\nrw\nrw\nrw\nrw\nBits 15:7\nReserved, must be kept at reset value.\nBit 6 TIE: Trigger interrupt enable\n0: Trigger interrupt disabled.\n1: Trigger interrupt enabled.\nBit 5:3\nReserved, must be kept at reset value.\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n678/1757\nRM0090 Rev 21\nBit 2 CC2IE: Capture/Compare 2 interrupt enable\n0: CC2 interrupt disabled.\n1: CC2 interrupt enabled.\nBit 1 CC1IE: Capture/Compare 1 interrupt enable\n0: CC1 interrupt disabled.\n1: CC1 interrupt enabled.\nBit 0 UIE: Update interrupt enable\n0: Update interrupt disabled.\n1: Update interrupt enabled.\n\n\n<>\n\nRM0090 Rev 21\n679/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.4.4 \nTIM9/12 status register (TIMx_SR)\nAddress offset: 0x10\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCC2OF CC1OF\nReserved\nTIF\nReserved\nCC2IF\nCC1IF\nUIF\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nBits 15:11\nReserved, must be kept at reset value.\nBit 10 CC2OF: Capture/compare 2 overcapture flag\nrefer to CC1OF description\nBit 9 CC1OF: Capture/Compare 1 overcapture flag\nThis flag is set by hardware only when the corresponding channel is configured in input \ncapture mode. It is cleared by software by writing it to ‘0’.\n0: No overcapture has been detected.\n1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was \nalready set\nBits 8:7\nReserved, must be kept at reset value.\nBit 6 TIF: Trigger interrupt flag\nThis flag is set by hardware on trigger event (active edge detected on TRGI input when the \nslave mode controller is enabled in all modes but gated mode. It is set when the counter \nstarts or stops when gated mode is selected. It is cleared by software.\n0: No trigger event occurred.\n1: Trigger interrupt pending.\nBits 5:3\nReserved, must be kept at reset value.\nBit 2 CC2IF: Capture/Compare 2 interrupt flag\nrefer to CC1IF description\nBit 1 CC1IF: Capture/compare 1 interrupt flag\nIf channel CC1 is configured as output:\nThis flag is set by hardware when the counter matches the compare value. It is cleared by \nsoftware.\n0: No match.\n1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. \nWhen the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF \nbit goes high on the counter overflow.\nIf channel CC1 is configured as input:\nThis bit is set by hardware on a capture. It is cleared by software or by reading the \nTIMx_CCR1 register.\n0: No input capture occurred.\n1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected \non IC1 which matches the selected polarity).\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n680/1757\nRM0090 Rev 21\n19.4.5 \nTIM9/12 event generation register (TIMx_EGR)\nAddress offset: 0x14\nReset value: 0x0000\n \nBit 0 UIF: Update interrupt flag\nThis bit is set by hardware on an update event. It is cleared by software.\n0: No update occurred.\n1: Update interrupt pending. This bit is set by hardware when the registers are updated:\n– At overflow and if UDIS=’0’ in the TIMx_CR1 register.\n– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and \nUDIS=’0’ in the TIMx_CR1 register.\n– When CNT is reinitialized by a trigger event (refer to the synchro control register \ndescription), if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTG\nReserved\nCC2G\nCC1G\nUG\nw\nw\nw\nw\nBits 15:7 Reserved, must be kept at reset value.\nBit 6 TG: Trigger generation\nThis bit is set by software in order to generate an event, it is automatically cleared by \nhardware.\n0: No action\n1: The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled\nBits 5:3 Reserved, must be kept at reset value.\nBit 2 CC2G: Capture/compare 2 generation\nrefer to CC1G description\nBit 1 CC1G: Capture/compare 1 generation\nThis bit is set by software to generate an event, it is automatically cleared by hardware.\n0: No action\n1: A capture/compare event is generated on channel 1:\nIf channel CC1 is configured as output:\nthe CC1IF flag is set, the corresponding interrupt is sent if enabled.\nIf channel CC1 is configured as input:\nThe current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the \ncorresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was \nalready high.\nBit 0 UG: Update generation\nThis bit can be set by software, it is automatically cleared by hardware.\n0: No action\n1: Re-initializes the counter and generates an update of the registers. The prescaler counter \nis also cleared and the prescaler ratio is not affected. The counter is cleared.\n\n\n<>\n\nRM0090 Rev 21\n681/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.4.6 \nTIM9/12 capture/compare mode register 1 (TIMx_CCMR1)\nAddress offset: 0x18\nReset value: 0x0000\nThe channels can be used in input (capture mode) or in output (compare mode). The \ndirection of a channel is defined by configuring the corresponding CCxS bits. All the other \nbits in this register have different functions in input and output modes. For a given bit, OCxx \ndescribes its function when the channel is configured in output mode, ICxx describes its \nfunction when the channel is configured in input mode. Take care that the same bit can have \ndifferent meanings for the input stage and the output stage.\nOutput compare mode\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nOC2M[2:0]\nOC2PE OC2FE\nCC2S[1:0]\nRes.\nOC1M[2:0]\nOC1PE OC1FE\nCC1S[1:0]\nIC2F[3:0]\nIC2PSC[1:0]\nIC1F[3:0]\nIC1PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15\nReserved, must be kept at reset value.\nBits 14:12 OC2M[2:0]: Output compare 2 mode\nBit 11 OC2PE: Output compare 2 preload enable\nBit 10 OC2FE: Output compare 2 fast enable\nBits 9:8 CC2S[1:0]: Capture/Compare 2 selection\nThis bitfield defines the direction of the channel (input/output) as well as the used input. \n00: CC2 channel is configured as output\n01: CC2 channel is configured as input, IC2 is mapped on TI2\n10: CC2 channel is configured as input, IC2 is mapped on TI1\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an \ninternal trigger input is selected through the TS bit (TIMx_SMCR register\nNote: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).\nBit 7\nReserved, must be kept at reset value.\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n682/1757\nRM0090 Rev 21\nBits 6:4 OC1M: Output compare 1 mode\nThese bits define the behavior of the output reference signal OC1REF from which OC1 and \nOC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N \ndepend on the CC1P and CC1NP bits, respectively.\n000: Frozen - The comparison between the output compare register TIMx_CCR1 and the \ncounter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing \nbase).\n001: Set channel 1 to active level on match. The OC1REF signal is forced high when the \nTIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1).\n010: Set channel 1 to inactive level on match. The OC1REF signal is forced low when the \nTIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1).\n011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1\n100: Force inactive level - OC1REF is forced low\n101: Force active level - OC1REF is forced high\n110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1, else it is active (OC1REF=’1’)\n111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 \nelse it is inactive.\nNote: In PWM mode 1 or 2, the OCREF level changes only when the result of the \ncomparison changes or when the output compare mode switches from “frozen” mode \nto “PWM” mode.\nBit 3 OC1PE: Output compare 1 preload enable\n0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the \nnew value is taken into account immediately\n1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload \nregister. TIMx_CCR1 preload value is loaded into the active register at each update event\nBit 2 OC1FE: Output compare 1 fast enable\nThis bit is used to accelerate the effect of an event on the trigger in input on the CC output.\n0: CC1 behaves normally depending on the counter and CCR1 values even when the \ntrigger is ON. The minimum delay to activate the CC1 output when an edge occurs on the \ntrigger input is 5 clock cycles\n1: An active edge on the trigger input acts like a compare match on the CC1 output. Then, \nOC is set to the compare level independently of the result of the comparison. Delay to \nsample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE \nacts only if the channel is configured in PWM1 or PWM2 mode.\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bitfield defines the direction of the channel (input/output) as well as the used input. \n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: CC1 channel is configured as input, IC1 is mapped on TI2\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode works only if an \ninternal trigger input is selected through the TS bit (TIMx_SMCR register)\nNote: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\n\n\n<>\n\nRM0090 Rev 21\n683/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\nInput capture mode\nBits 15:12 IC2F: Input capture 2 filter\nBits 11:10 IC2PSC[1:0]: Input capture 2 prescaler\nBits 9:8 CC2S: Capture/compare 2 selection\nThis bitfield defines the direction of the channel (input/output) as well as the used input. \n00: CC2 channel is configured as output\n01: CC2 channel is configured as input, IC2 is mapped on TI2\n10: CC2 channel is configured as input, IC2 is mapped on TI1\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an \ninternal trigger input is selected through the TS bit (TIMx_SMCR register)\nNote: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).\nBits 7:4 IC1F: Input capture 1 filter\nThis bitfield defines the frequency used to sample the TI1 input and the length of the digital \nfilter applied to TI1. The digital filter is made of an event counter in which N consecutive \nevents are needed to validate a transition on the output:\n0000: No filter, sampling is done at fDTS\n0001: fSAMPLING=fCK_INT, N=2\n0010: fSAMPLING=fCK_INT, N=4\n0011: fSAMPLING=fCK_INT, N=8 \n0100: fSAMPLING=fDTS/2, N=6\n0101: fSAMPLING=fDTS/2, N=8\n0110: fSAMPLING=fDTS/4, N=6\n0111: fSAMPLING=fDTS/4, N=8\n1000: fSAMPLING=fDTS/8, N=6\n1001: fSAMPLING=fDTS/8, N=8\n1010: fSAMPLING=fDTS/16, N=5\n1011: fSAMPLING=fDTS/16, N=6\n1100: fSAMPLING=fDTS/16, N=8\n1101: fSAMPLING=fDTS/32, N=5\n1110: fSAMPLING=fDTS/32, N=6\n1111: fSAMPLING=fDTS/32, N=8\nBits 3:2 IC1PSC: Input capture 1 prescaler\nThis bitfield defines the ratio of the prescaler acting on the CC1 input (IC1).\nThe prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).\n00: no prescaler, capture is done each time an edge is detected on the capture input\n01: capture is done once every 2 events\n10: capture is done once every 4 events\n11: capture is done once every 8 events\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bitfield defines the direction of the channel (input/output) as well as the used input. \n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: CC1 channel is configured as input, IC1 is mapped on TI2\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n684/1757\nRM0090 Rev 21\n19.4.7 \nTIM9/12 capture/compare enable register (TIMx_CCER)\nAddress offset: 0x20\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCC2NP\nRes.\nCC2P\nCC2E\nCC1NP\nRes.\nCC1P\nCC1E\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 CC2NP: Capture/Compare 2 output Polarity\nrefer to CC1NP description \nBits 6 Reserved, must be kept at reset value.\nBit 5 CC2P: Capture/Compare 2 output Polarity\nrefer to CC1P description\nBit 4 CC2E: Capture/Compare 2 output enable\nrefer to CC1E description\nBit 3 CC1NP: Capture/Compare 1 complementary output Polarity\nCC1 channel configured as output: CC1NP must be kept cleared\nCC1 channel configured as input: CC1NP is used in conjunction with CC1P to define \nTI1FP1/TI2FP1 polarity (refer to CC1P description).\nBit 2 Reserved, must be kept at reset value.\nBit 1 CC1P: Capture/Compare 1 output Polarity.\nCC1 channel configured as output:\n0: OC1 active high.\n1: OC1 active low.\nCC1 channel configured as input:\nCC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.\n00: noninverted/rising edge\nCircuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger \nmode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).\n01: inverted/falling edge\nCircuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger \nmode), TIxFP1 is inverted (trigger in gated mode, encoder mode).\n10: reserved, do not use this configuration.\nNote: 11: noninverted/both edges\nCircuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, \nexternal clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This \nconfiguration must not be used for encoder mode.\nBit 0 CC1E: Capture/Compare 1 output enable.\nCC1 channel configured as output:\n0: Off - OC1 is not active. \n1: On - OC1 signal is output on the corresponding output pin. \nCC1 channel configured as input:\nThis bit determines if a capture of the counter value can actually be done into the input \ncapture/compare register 1 (TIMx_CCR1) or not.\n0: Capture disabled.\n1: Capture enabled.\n\n\n<>\n\nRM0090 Rev 21\n685/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n \nNote:\nThe states of the external I/O pins connected to the standard OCx channels depend on the \nstate of the OCx channel and on the GPIO registers.\n19.4.8 \nTIM9/12 counter (TIMx_CNT)\nAddress offset: 0x24\nReset value: 0x0000 \n \n19.4.9 \nTIM9/12 prescaler (TIMx_PSC)\nAddress offset: 0x28\nReset value: 0x0000\n \n19.4.10 \nTIM9/12 auto-reload register (TIMx_ARR)\nAddress offset: 0x2C\nReset value: 0xFFFF\n \nTable 103. Output control bit for standard OCx channels\nCCxE bit\nOCx output state\n0\nOutput disabled (OCx=’0’, OCx_EN=’0’)\n1\nOCx=OCxREF + Polarity, OCx_EN=’1’\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCNT[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CNT[15:0]: Counter value\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPSC[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 PSC[15:0]: Prescaler value\nThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).\nPSC contains the value to be loaded in the active prescaler register at each update event \n(including when the counter is cleared through UG bit of TIMx_EGR register or through \ntrigger controller when configured in “reset mode”).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nARR[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 ARR[15:0]: Auto-reload value\nARR is the value to be loaded into the actual auto-reload register.\nRefer to the Section 19.3.1: Time-base unit for more details about ARR update and \nbehavior.\nThe counter is blocked while the auto-reload value is null.\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n686/1757\nRM0090 Rev 21\n19.4.11 \nTIM9/12 capture/compare register 1 (TIMx_CCR1)\nAddress offset: 0x34\nReset value: 0x0000\n \n19.4.12 \nTIM9/12 capture/compare register 2 (TIMx_CCR2)\nAddress offset: 0x38\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR1[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 15:0 CCR1[15:0]: Capture/Compare 1 value\nIf channel CC1 is configured as output:\nCCR1 is the value to be loaded into the actual capture/compare 1 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register \n(OC1PE bit). Else the preload value is copied into the active capture/compare 1 register \nwhen an update event occurs.\nThe active capture/compare register contains the value to be compared to the TIMx_CNT \ncounter and signaled on the OC1 output.\nIf channel CC1is configured as input:\nCCR1 is the counter value transferred by the last input capture 1 event (IC1). The \nTIMx_CCR1 register is read-only and cannot be programmed.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR2[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 15:0 CCR2[15:0]: Capture/Compare 2 value\nIf channel CC2 is configured as output:\nCCR2 is the value to be loaded into the actual capture/compare 2 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register \n(OC2PE bit). Else the preload value is copied into the active capture/compare 2 register \nwhen an update event occurs.\nThe active capture/compare register contains the value to be compared to the TIMx_CNT \ncounter and signalled on the OC2 output.\nIf channel CC2 is configured as input:\nCCR2 is the counter value transferred by the last input capture 2 event (IC2). The \nTIMx_CCR2 register is read-only and cannot be programmed.\n\n\n<>\n\nRM0090 Rev 21\n687/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.4.13 \nTIM9/12 register map\nTIM9/12 registers are mapped as 16-bit addressable registers as described below. The \nreserved memory areas are highlighted in gray in the table.\n \nTable 104. TIM9/12 register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nTIMx_CR1\nReserved\nCKD \n[1:0]\nARPE\nReserved\nOPM\nURS\nUDIS\nCEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0x08\nTIMx_SMCR\nReserved\nMSM\nTS[2:0]\nReserved\nSMS[2:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0x0C\nTIMx_DIER\nReserved\nTIE\nReserved\nCC2IE\nCC1IE\nUIE\nReset value\n0\n0\n0\n0\n0x10\nTIMx_SR\nReserved\nCC2OF\nCC1OF\nReserved\nTIF\nReserved\nCC2IF\nCC1IF\nUIF\nReset value\n0\n0\n0\n0\n0\n0\n0x14\nTIMx_EGR\nReserved\nTG\nReserved\nCC2G\nCC1G\nUG\nReset value\n0\n0\n0\n0\n0x18\nTIMx_CCMR1\nOutput compare \nmode\nReserved\nOC2M\n[2:0]\nOC2PE\nOC2FE\nCC2S \n[1:0]\nReserved\nOC1M\n[2:0]\nOC1PE\nOC1FE\nCC1\nS \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTIMx_CCMR1\nInput capture \nmode\nReserved\nIC2F[3:0]\nIC2\nPSC\n[1:0]\nCC2S \n[1:0]\nIC1F[3:0]\nIC1\nPSC\n[1:0]\nCC1\nS \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nReserved\n0x20\nTIMx_CCER\nReserved\nCC2NP\nReserved\nCC2P\nCC2E\nCC1NP\nReserved\nCC1P\nCC1E\nReset value\n0\n0\n0\n0\n0\n0\n0x24\nTIMx_CNT\nReserved\nCNT[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nTIMx_PSC\nReserved\nPSC[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x2C\nTIMx_ARR\nReserved\nARR[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x30\nReserved\n0x34\nTIMx_CCR1\nReserved\nCCR1[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n688/1757\nRM0090 Rev 21\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x38\nTIMx_CCR2\nReserved\nCCR2[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x3C to\n0x4C\nReserved\nTable 104. TIM9/12 register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n689/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.5 \nTIM10/11/13/14 registers\nThe peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read \naccesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). \n19.5.1 \nTIM10/11/13/14 control register 1 (TIMx_CR1)\nAddress offset: 0x00\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCKD[1:0]\nARPE\nReserved\nOPM\nURS\nUDIS\nCEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:10 Reserved, must be kept at reset value.\nBits 9:8 CKD: Clock division\nThis bit-field indicates the division ratio between the timer clock (CK_INT) frequency and \nsampling clock used by the digital filters (TIx),\n00: tDTS = tCK_INT\n01: tDTS = 2 × tCK_INT\n10: tDTS = 4 × tCK_INT\n11: Reserved\nBit 7 ARPE: Auto-reload preload enable\n0: TIMx_ARR register is not buffered\n1: TIMx_ARR register is buffered\nBits 6:4 Reserved, must be kept at reset value.\nBit 3 OPM: One-pulse mode\n0: Counter is not stopped on the update event\n1: Counter stops counting on the next update event (clearing the CEN bit).\nBit 2 URS: Update request source\nThis bit is set and cleared by software to select the update interrupt (UEV) sources.\n0: Any of the following events generate an UEV if enabled: \n–\nCounter overflow\n–\nSetting the UG bit\n1: Only counter overflow generates an UEV if enabled.\nBit 1 UDIS: Update disable\nThis bit is set and cleared by software to enable/disable update interrupt (UEV) event \ngeneration.\n0: UEV enabled. An UEV is generated by one of the following events:\n–\nCounter overflow\n–\nSetting the UG bit. \nBuffered registers are then loaded with their preload values.\n1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, \nCCRx). The counter and the prescaler are reinitialized if the UG bit is set.\nBit 0 CEN: Counter enable\n0: Counter disabled\n1: Counter enabled\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n690/1757\nRM0090 Rev 21\n19.5.2 \nTIM10/11/13/14 Interrupt enable register (TIMx_DIER)\nAddress offset: 0x0C\nReset value: 0x0000\n \n19.5.3 \nTIM10/11/13/14 status register (TIMx_SR)\nAddress offset: 0x10\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCC1IE\nUIE\nrw\nrw\nBits 15:2\nReserved, must be kept at reset value.\nBit 1 CC1IE: Capture/Compare 1 interrupt enable\n0: CC1 interrupt disabled\n1: CC1 interrupt enabled\nBit 0 UIE: Update interrupt enable\n0: Update interrupt disabled\n1: Update interrupt enabled\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCC1OF\nReserved\nCC1IF\nUIF\nrc_w0\nrc_w0\nrc_w0\nBits 15:10\nReserved, must be kept at reset value.\nBit 9 CC1OF: Capture/Compare 1 overcapture flag\nThis flag is set by hardware only when the corresponding channel is configured in input \ncapture mode. It is cleared by software by writing it to ‘0’.\n0: No overcapture has been detected.\n1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was \nalready set\nBits 8:2\nReserved, must be kept at reset value.\nBit 1 CC1IF: Capture/compare 1 interrupt flag\nIf channel CC1 is configured as output:\nThis flag is set by hardware when the counter matches the compare value. It is cleared by \nsoftware.\n0: No match.\n1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. \nWhen the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit \ngoes high on the counter overflow.\nIf channel CC1 is configured as input:\nThis bit is set by hardware on a capture. It is cleared by software or by reading the \nTIMx_CCR1 register.\n0: No input capture occurred.\n1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected \non IC1 which matches the selected polarity).\n\n\n<>\n\nRM0090 Rev 21\n691/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.5.4 \nTIM10/11/13/14 event generation register (TIMx_EGR)\nAddress offset: 0x14\nReset value: 0x0000\n \n19.5.5 \nTIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1)\nAddress offset: 0x18\nReset value: 0x0000\nThe channels can be used in input (capture mode) or in output (compare mode). The \ndirection of a channel is defined by configuring the corresponding CCxS bits. All the other \nbits of this register have a different function in input and in output mode. For a given bit, \nOCxx describes its function when the channel is configured in output, ICxx describes its \nfunction when the channel is configured in input. So take care that the same bit can have a \ndifferent meaning for the input stage and for the output stage.\nBit 0 UIF: Update interrupt flag\nThis bit is set by hardware on an update event. It is cleared by software.\n0: No update occurred.\n1: Update interrupt pending. This bit is set by hardware when the registers are updated:\n–\nAt overflow and if UDIS=’0’ in the TIMx_CR1 register.\n–\nWhen CNT is reinitialized by software using the UG bit in TIMx_EGR register, if \nURS=’0’ and UDIS=’0’ in the TIMx_CR1 register.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCC1G\nUG\nw\nw\nBits 15:2 Reserved, must be kept at reset value.\nBit 1 CC1G: Capture/compare 1 generation\nThis bit is set by software in order to generate an event, it is automatically cleared by \nhardware.\n0: No action\n1: A capture/compare event is generated on channel 1:\nIf channel CC1 is configured as output:\nCC1IF flag is set, Corresponding interrupt or is sent if enabled.\nIf channel CC1 is configured as input:\nThe current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, \nthe corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was \nalready high.\nBit 0 UG: Update generation\nThis bit can be set by software, it is automatically cleared by hardware.\n0: No action\n1: Re-initialize the counter and generates an update of the registers. Note that the prescaler \ncounter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared. \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOC1M[2:0]\nOC1PE OC1FE\nCC1S[1:0]\nReserved\nIC1F[3:0]\nIC1PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n692/1757\nRM0090 Rev 21\nOutput compare mode\nBits 15:7\nReserved, must be kept at reset value.\nBits 6:4 OC1M: Output compare 1 mode\nThese bits define the behavior of the output reference signal OC1REF from which OC1 is \nderived. OC1REF is active high whereas OC1 active level depends on CC1P bit. \n000: Frozen. The comparison between the output compare register TIMx_CCR1 and the \ncounter TIMx_CNT has no effect on the outputs. \n001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter \nTIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). \n010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the \ncounter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). \n011: Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1. \n100: Force inactive level - OC1REF is forced low. \n101: Force active level - OC1REF is forced high.\n110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive.\n111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active.\nNote: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison \nchanges or when the output compare mode switches from frozen to PWM mode. \nBit 3 OC1PE: Output compare 1 preload enable\n0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the \nnew value is taken in account immediately. \n1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload \nregister. TIMx_CCR1 preload value is loaded in the active register at each update event.\nBit 2 OC1FE: Output compare 1 fast enable\nThis bit is used to accelerate the effect of an event on the trigger in input on the CC output.\n0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is \nON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is \n5 clock cycles.\n1: An active edge on the trigger input acts like a compare match on CC1 output. OC is then \nset to the compare level independently of the result of the comparison. Delay to sample the \ntrigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the \nchannel is configured in PWM1 or PWM2 mode.\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC1 channel is configured as output.\n01: CC1 channel is configured as input, IC1 is mapped on TI1.\n10: \n11: \nNote: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\n\n\n<>\n\nRM0090 Rev 21\n693/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\nInput capture mode\n \nBits 15:8\nReserved, must be kept at reset value.\nBits 7:4 IC1F: Input capture 1 filter\nThis bit-field defines the frequency used to sample TI1 input and the length of the digital filter \napplied to TI1. The digital filter is made of an event counter in which N consecutive events \nare needed to validate a transition on the output:\n0000: No filter, sampling is done at fDTS\n0001: fSAMPLING=fCK_INT, N=2\n0010: fSAMPLING=fCK_INT, N=4\n0011: fSAMPLING=fCK_INT, N=8\n0100: fSAMPLING=fDTS/2, N=6\n0101: fSAMPLING=fDTS/2, N=8\n0110: fSAMPLING=fDTS/4, N=6\n0111: fSAMPLING=fDTS/4, N=8\n1000: fSAMPLING=fDTS/8, N=6\n1001: fSAMPLING=fDTS/8, N=8\n1010: fSAMPLING=fDTS/16, N=5\n1011: fSAMPLING=fDTS/16, N=6\n1100: fSAMPLING=fDTS/16, N=8\n1101: fSAMPLING=fDTS/32, N=5\n1110: fSAMPLING=fDTS/32, N=6\n1111: fSAMPLING=fDTS/32, N=8\nBits 3:2 IC1PSC: Input capture 1 prescaler\nThis bit-field defines the ratio of the prescaler acting on CC1 input (IC1).\nThe prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).\n00: no prescaler, capture is done each time an edge is detected on the capture input\n01: capture is done once every 2 events\n10: capture is done once every 4 events\n11: capture is done once every 8 events\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: Reserved\n11: Reserved\nNote: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n694/1757\nRM0090 Rev 21\n19.5.6 \nTIM10/11/13/14 capture/compare enable register (TIMx_CCER)\nAddress offset: 0x20\nReset value: 0x0000\n \n \nNote:\nThe state of the external I/O pins connected to the standard OCx channels depends on the \nOCx channel state and the GPIO registers.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCC1NP\nRes.\nCC1P\nCC1E\nrw\nrw\nrw\nBits 15:4 Reserved, must be kept at reset value.\nBit 3 CC1NP: Capture/Compare 1 complementary output Polarity. \nCC1 channel configured as output: CC1NP must be kept cleared. \nCC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define \nTI1FP1 polarity (refer to CC1P description).\nBit 2 Reserved, must be kept at reset value. \nBit 1 CC1P: Capture/Compare 1 output Polarity.\nCC1 channel configured as output:\n0: OC1 active high\n1: OC1 active low\nCC1 channel configured as input:\nThe CC1P bit selects TI1FP1 and TI2FP1 polarity for trigger or capture operations.\n00: noninverted/rising edge\nCircuit is sensitive to TI1FP1 rising edge (capture mode), TI1FP1 is not inverted. \n01: inverted/falling edge\nCircuit is sensitive to TI1FP1 falling edge (capture mode), TI1FP1 is inverted.\n10: reserved, do not use this configuration. \n11: noninverted/both edges\nCircuit is sensitive to both TI1FP1 rising and falling edges (capture mode), TI1FP1 is not \ninverted. \nBit 0 CC1E: Capture/Compare 1 output enable.\nCC1 channel configured as output:\n0: Off - OC1 is not active\n1: On - OC1 signal is output on the corresponding output pin\nCC1 channel configured as input:\nThis bit determines if a capture of the counter value can actually be done into the input \ncapture/compare register 1 (TIMx_CCR1) or not.\n0: Capture disabled\n1: Capture enabled\nTable 105. Output control bit for standard OCx channels\nCCxE bit\nOCx output state\n0\nOutput Disabled (OCx=’0’, OCx_EN=’0’)\n1\nOCx=OCxREF + Polarity, OCx_EN=’1’\n\n\n<>\n\nRM0090 Rev 21\n695/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.5.7 \nTIM10/11/13/14 counter (TIMx_CNT)\nAddress offset: 0x24\nReset value: 0x0000\n \n19.5.8 \nTIM10/11/13/14 prescaler (TIMx_PSC)\nAddress offset: 0x28\nReset value: 0x0000\n \n19.5.9 \nTIM10/11/13/14 auto-reload register (TIMx_ARR)\nAddress offset: 0x2C\nReset value: 0xFFFF\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCNT[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CNT[15:0]: Counter value\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPSC[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 PSC[15:0]: Prescaler value\nThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).\nPSC contains the value to be loaded in the active prescaler register at each update event \n(including when the counter is cleared through UG bit of TIMx_EGR register or through \ntrigger controller when configured in “reset mode”).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nARR[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 ARR[15:0]: Auto-reload value\nARR is the value to be loaded in the actual auto-reload register.\nRefer to Section 19.3.1: Time-base unit for more details about ARR update and behavior.\nThe counter is blocked while the auto-reload value is null.\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n696/1757\nRM0090 Rev 21\n19.5.10 \nTIM10/11/13/14 capture/compare register 1 (TIMx_CCR1)\nAddress offset: 0x34\nReset value: 0x0000\n \n \n19.5.11 \nTIM11 option register 1 (TIM11_OR)\nAddress offset: 0x50\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR1[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 15:0 CCR1[15:0]: Capture/Compare 1 value\nIf channel CC1 is configured as output:\nCCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit \nOC1PE). Else the preload value is copied in the active capture/compare 1 register when an \nupdate event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signaled on OC1 output.\nIf channel CC1is configured as input:\nCCR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 \nregister is read-only and cannot be programmed.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTI1_RMP[1:0]\nrw\nBits 15:2\nReserved, must be kept at reset value.\nBits 1:0\nTI1_RMP[1:0]: TIM11 Input 1 remapping capability\nSet and cleared by software.\n00,01,11: TIM11 Channel1 is connected to the GPIO (refer to the Alternate function mapping \ntable in the datasheets).\n10: HSE_RTC clock (HSE divided by programmable prescaler) is connected to the \nTIM11_CH1 input for measurement purposes\n\n\n<>\n\nRM0090 Rev 21\n697/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.5.12 \nTIM10/11/13/14 register map\nTIMx registers are mapped as 16-bit addressable registers as described in the table below. \nTable 106. TIM10/11/13/14 register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nTIMx_CR1\nReserved\nCKD \n[1:0]\nARPE\nReserve\nd\nOPM\nURS\nUDIS\nCEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0x08\nTIMx_SMCR\nReserved\nReset value\n0x0C\nTIMx_DIER\nReserved\nCC1IE\nUIE\nReset value\n0\n0\n0x10\nTIMx_SR\nReserved\nCC1OF\nReserved\nCC1IF\nUIF\nReset value\n0\n0\n0\n0x14\nTIMx_EGR\nReserved\nCC1G\nUG\nReset value\n0\n0\n0x18\nTIMx_CCMR1\nOutput compare \nmode\nReserved\nOC1M\n[2:0]\nOC1PE\nOC1FE\nCC1S \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\nTIMx_CCMR1\nInput capture \nmode\nReserved\nIC1F[3:0]\nIC1\nPSC\n[1:0]\nCC1S \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nReserved\n0x20\nTIMx_CCER\nReserved\nCC1NP\nReserved\nCC1P\nCC1E\nReset value\n0\n0\n0\n0x24\nTIMx_CNT\nReserved\nCNT[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nTIMx_PSC\nReserved\nPSC[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x2C\nTIMx_ARR\nReserved\nARR[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x30\nReserved\n0x34\nTIMx_CCR1\nReserved\nCCR1[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x38 to\n0x4C\nReserved\n\n\n<>\n\nGeneral-purpose timers (TIM9 to TIM14)\nRM0090\n698/1757\nRM0090 Rev 21\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x50\nTIMx_OR\nReserved\nTI1_RMP\nReset value\n0\n0\nTable 106. TIM10/11/13/14 register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n699/1757\nRM0090\nBasic timers (TIM6 and TIM7)\n710\n20 \nBasic timers (TIM6 and TIM7)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n20.1 \nTIM6 and TIM7 introduction\nThe basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a \nprogrammable prescaler.\nThey may be used as generic timers for time-base generation but they are also specifically \nused to drive the digital-to-analog converter (DAC). In fact, the timers are internally \nconnected to the DAC and are able to drive it through their trigger outputs.\nThe timers are completely independent, and do not share any resources. \n20.2 \nTIM6 and TIM7 main features\nBasic timer (TIM6 and TIM7) features include:\n•\n16-bit auto-reload upcounter\n•\n16-bit programmable prescaler used to divide (also “on the fly”) the counter clock \nfrequency by any factor between 1 and 65536\n•\nSynchronization circuit to trigger the DAC\n•\nInterrupt/DMA generation on the update event: counter overflow\nFigure 203. Basic timer block diagram\nU\nTrigger\ncontroller\nStop, Clear or up\nTRGO\nU\nUI\nReset, Enable, Count,\nevent\nPreload registers transferred \nto active registers on U event according to control bit\ninterrupt & DMA output\nto DAC \nCOUNTER\nCK_PSC\nCNT\nCK_CNT\nController\nInternal clock (CK_INT)\nTIMxCLK from RCC\n±\nPrescaler\nPSC\nAuto-reload Register\nFlag\nai14749b\n\n\n<>\n\nBasic timers (TIM6 and TIM7)\nRM0090\n700/1757\nRM0090 Rev 21\n20.3 \nTIM6 and TIM7 functional description\n20.3.1 \nTime-base unit\nThe main block of the programmable timer is a 16-bit upcounter with its related auto-reload \nregister. The counter clock can be divided by a prescaler. \nThe counter, the auto-reload register and the prescaler register can be written or read by \nsoftware. This is true even when the counter is running.\nThe time-base unit includes:\n•\nCounter register (TIMx_CNT)\n•\nPrescaler register (TIMx_PSC)\n•\nAuto-Reload register (TIMx_ARR)\nThe auto-reload register is preloaded. The preload register is accessed each time an \nattempt is made to write or read the auto-reload register. The contents of the preload \nregister are transferred into the shadow register permanently or at each update event UEV, \ndepending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The \nupdate event is sent when the counter reaches the overflow value and if the UDIS bit equals \n0 in the TIMx_CR1 register. It can also be generated by software. The generation of the \nupdate event is described in detail for each configuration.\nThe counter is clocked by the prescaler output CK_CNT, which is enabled only when the \ncounter enable bit (CEN) in the TIMx_CR1 register is set. \nNote that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN. \nPrescaler description\nThe prescaler can divide the counter clock frequency by any factor between 1 and 65536. It \nis based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). \nIt can be changed on the fly as the TIMx_PSC control register is buffered. The new \nprescaler ratio is taken into account at the next update event.\nFigure 204 and Figure 205 give some examples of the counter behavior when the prescaler \nratio is changed on the fly.\n\n\n<>\n\nRM0090 Rev 21\n701/1757\nRM0090\nBasic timers (TIM6 and TIM7)\n710\nFigure 204. Counter timing diagram with prescaler division change from 1 to 2\nFigure 205. Counter timing diagram with prescaler division change from 1 to 4\nCK_PSC\n00\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\n0\nPrescaler control register\n1\n0\nWrite a new value in TIMx_PSC\nPrescaler buffer\n1\n0\nPrescaler counter\n0\n1\n0\n1\n0\n1\n0\n1\n01\n02\n03\nFA\nFB\nF7\nF8\nF9\nFC\nMS31076V3\n0\n3\n0\n0\n1\n2\n3\n0\n1\n2\n3\nMS31077V3\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nPrescaler control register\nWrite a new value in TIMx_PSC\nPrescaler buffer\nPrescaler counter\n00\n01\nFA FB\nF7\nF8\nF9\nFC\n3\n0\n\n\n<>\n\nBasic timers (TIM6 and TIM7)\nRM0090\n702/1757\nRM0090 Rev 21\n20.3.2 \nCounting mode\nThe counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), \nthen restarts from 0 and generates a counter overflow event.\nAn update event can be generate at each counter overflow or by setting the UG bit in the \nTIMx_EGR register (by software or by using the slave mode controller). \nThe UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 \nregister. This avoids updating the shadow registers while writing new values into the preload \nregisters. In this way, no update event occurs until the UDIS bit has been written to 0, \nhowever, the counter and the prescaler counter both restart from 0 (but the prescale rate \ndoes not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 \nregister is set, setting the UG bit generates an update event UEV, but the UIF flag is not set \n(so no interrupt or DMA request is sent). \nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in \nthe TIMx_SR register) is set (depending on the URS bit):\n•\nThe buffer of the prescaler is reloaded with the preload value (contents of the \nTIMx_PSC register)\n•\nThe auto-reload shadow register is updated with the preload value (TIMx_ARR)\nThe following figures show some examples of the counter behavior for different clock \nfrequencies when TIMx_ARR = 0x36.\nFigure 206. Counter timing diagram, internal clock divided by 1\nMS37364V1\n00\n02\n03\n04\n05\n06\n07\n33\n34\n35\n36\n31\nCK_INT\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n01\n32\n\n\n<>\n\nRM0090 Rev 21\n703/1757\nRM0090\nBasic timers (TIM6 and TIM7)\n710\nFigure 207. Counter timing diagram, internal clock divided by 2\nFigure 208. Counter timing diagram, internal clock divided by 4\nFigure 209. Counter timing diagram, internal clock divided by N\nMS35835V1\nCK_INT\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n0034\n0035\n0036\n0000\n0001\n0002\n0003\n0000\n0001\n0035\n0036\nMSv37301V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\nCNT_EN\nMSv37302V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n1F\n20\n\n\n<>\n\nBasic timers (TIM6 and TIM7)\nRM0090\n704/1757\nRM0090 Rev 21\nFigure 210. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not\npreloaded)\nFigure 211. Counter timing diagram, update event when ARPE=1 (TIMx_ARR\npreloaded)\n20.3.3 \nClock source\nThe counter clock is provided by the Internal clock (CK_INT) source.\nThe CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual \ncontrol bits and can be changed only by software (except for UG that remains cleared \nautomatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal \nclock CK_INT.\nFigure 212 shows the behavior of the control circuit and the upcounter in normal mode, \nwithout prescaler.\nFF\n36\nMSv37303V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n02 03\n04 05 06 07\n32\n33 34 35 36\n31\n01\nCNT_EN\nAuto-reload register\nWrite a new value in TIMx_ARR\nMSv37304V1\nF5\n36\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n02 03 04\n05 06\n07\nF1 F2 F3 F4 F5\nF0\n01\nCNT_EN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\nAuto-reload shadow register\nF5\n36\n\n\n<>\n\nRM0090 Rev 21\n705/1757\nRM0090\nBasic timers (TIM6 and TIM7)\n710\nFigure 212. Control circuit in normal mode, internal clock divided by 1\n20.3.4 \nDebug mode\nWhen the microcontroller enters the debug mode (Cortex®-M4 with FPU core - halted), the \nTIMx counter either continues to work normally or stops, depending on the \nDBG_TIMx_STOP configuration bit in the DBG module. For more details, refer to \nSection 38.16.2: Debug support for timers, watchdog, bxCAN and I2C.\n20.4 \nTIM6 and TIM7 registers\nRefer to Section 2.2 for a list of abbreviations used in register descriptions.\nThe peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read \naccesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). \n20.4.1 \nTIM6 and TIM7 control register 1 (TIMx_CR1)\nAddress offset: 0x00\nReset value: 0x0000\n \nInternal clock\nCounter clock = CK_CNT = CK_PSC\nCounter register\nCEN=CNT_EN\nUG\nCNT_INIT\nMS31085V2\n00\n02\n03\n04\n05\n06\n07\n3 2\n33\n34\n35 36\n31\n01\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nARPE\nReserved\nOPM\nURS\nUDIS\nCEN\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 ARPE: Auto-reload preload enable\n0: TIMx_ARR register is not buffered.\n1: TIMx_ARR register is buffered.\nBits 6:4 Reserved, must be kept at reset value.\nBit 3 OPM: One-pulse mode\n0: Counter is not stopped at update event\n1: Counter stops counting at the next update event (clearing the CEN bit).\n\n\n<>\n\nBasic timers (TIM6 and TIM7)\nRM0090\n706/1757\nRM0090 Rev 21\nBit 2 URS: Update request source\nThis bit is set and cleared by software to select the UEV event sources.\n0: Any of the following events generates an update interrupt or DMA request if enabled. \nThese events can be: \n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\n1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.\nBit 1 UDIS: Update disable\nThis bit is set and cleared by software to enable/disable UEV event generation.\n0: UEV enabled. The Update (UEV) event is generated by one of the following events:\n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\nBuffered registers are then loaded with their preload values.\n1: UEV disabled. The Update event is not generated, shadow registers keep their value \n(ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if \na hardware reset is received from the slave mode controller.\nBit 0 CEN: Counter enable\n0: Counter disabled\n1: Counter enabled\nNote: Gated mode can work only if the CEN bit has been previously set by software. However \ntrigger mode can set the CEN bit automatically by hardware. \nCEN is cleared automatically in one-pulse mode, when an update event occurs.\n\n\n<>\n\nRM0090 Rev 21\n707/1757\nRM0090\nBasic timers (TIM6 and TIM7)\n710\n20.4.2 \nTIM6 and TIM7 control register 2 (TIMx_CR2)\nAddress offset: 0x04\nReset value: 0x0000\n \n20.4.3 \nTIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER)\nAddress offset: 0x0C\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMMS[2:0]\nReserved\nrw\nrw\nrw\nBits 15:7 Reserved, must be kept at reset value.\nBits 6:4 MMS[2:0]: Master mode selection\nThese bits are used to select the information to be sent in master mode to slave timers for \nsynchronization (TRGO). The combination is as follows:\n000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If \nreset is generated by the trigger input (slave mode controller configured in reset mode) then \nthe signal on TRGO is delayed compared to the actual reset.\n001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is \nuseful to start several timers at the same time or to control a window in which a slave timer \nis enabled. The Counter Enable signal is generated by a logic OR between CEN control bit \nand the trigger input when configured in gated mode. \nWhen the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, \nexcept if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR \nregister).\n010: Update - The update event is selected as a trigger output (TRGO). For instance a \nmaster timer can then be used as a prescaler for a slave timer.\nNote: The clock of the slave timer and ADC must be enabled prior to receiving events from \nthe master timer, and must not be changed on-the-fly while triggers are received from \nthe master timer.\nBits 3:0 Reserved, must be kept at reset value.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nUDE\nReserved\nUIE\nrw\nrw\nBits 15:9 Reserved, must be kept at reset value.\nBit 8 UDE: Update DMA request enable\n0: Update DMA request disabled.\n1: Update DMA request enabled.\nBits 7:1 Reserved, must be kept at reset value.\nBit 0 UIE: Update interrupt enable\n0: Update interrupt disabled.\n1: Update interrupt enabled.\n\n\n<>\n\nBasic timers (TIM6 and TIM7)\nRM0090\n708/1757\nRM0090 Rev 21\n20.4.4 \nTIM6 and TIM7 status register (TIMx_SR)\nAddress offset: 0x10\nReset value: 0x0000\n \n20.4.5 \nTIM6 and TIM7 event generation register (TIMx_EGR)\nAddress offset: 0x14\nReset value: 0x0000\n \n20.4.6 \nTIM6 and TIM7 counter (TIMx_CNT)\nAddress offset: 0x24\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nUIF\nrc_w0\nBits 15:1 Reserved, must be kept at reset value.\nBit 0 UIF: Update interrupt flag\nThis bit is set by hardware on an update event. It is cleared by software.\n0: No update occurred.\n1: Update interrupt pending. This bit is set by hardware when the registers are updated:\n– At overflow or underflow and if UDIS = 0 in the TIMx_CR1 register.\n– When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 \nand UDIS = 0 in the TIMx_CR1 register.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nUG\nw\nBits 15:1 Reserved, must be kept at reset value.\nBit 0 UG: Update generation\nThis bit can be set by software, it is automatically cleared by hardware.\n0: No action.\n1: Re-initializes the timer counter and generates an update of the registers. Note that the \nprescaler counter is cleared too (but the prescaler ratio is not affected).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCNT[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0\nCNT[15:0]: Counter value\n\n\n<>\n\nRM0090 Rev 21\n709/1757\nRM0090\nBasic timers (TIM6 and TIM7)\n710\n20.4.7 \nTIM6 and TIM7 prescaler (TIMx_PSC)\nAddress offset: 0x28\nReset value: 0x0000\n \n20.4.8 \nTIM6 and TIM7 auto-reload register (TIMx_ARR)\nAddress offset: 0x2C\nReset value: 0xFFFF\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPSC[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 PSC[15:0]: Prescaler value\nThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).\nPSC contains the value to be loaded in the active prescaler register at each update event \n(including when the counter is cleared through UG bit of TIMx_EGR register or through \ntrigger controller when configured in “reset mode”).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nARR[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 ARR[15:0]: Auto-reload value\nARR is the value to be loaded into the actual auto-reload register.\nRefer to Section 20.3.1: Time-base unit for more details about ARR update and behavior.\nThe counter is blocked while the auto-reload value is null.\n\n\n<>\n\nBasic timers (TIM6 and TIM7)\nRM0090\n710/1757\nRM0090 Rev 21\n20.4.9 \nTIM6 and TIM7 register map\nTIMx registers are mapped as 16-bit addressable registers as described in the table below. \n \nRefer to Section 2.3: Memory map for the register boundary addresses. \nTable 107. TIM6 and TIM7 register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nTIMx_CR1\nReserved\nARPE\nReserved\nOPM\nURS\nUDIS\nCEN\nReset value\n0\n0\n0\n0\n0\n0x04\nTIMx_CR2\nReserved\nMMS[2:0]\nReserved\nReset value\n0\n0\n0\n0x08\nReserved\n0x0C\nTIMx_DIER\nReserved\nUDE\nReserved\nUIE\nReset value\n0\n0\n0x10\nTIMx_SR\nReserved\nUIF\nReset value\n0\n0x14\nTIMx_EGR\nReserved\nUG\nReset value\n0\n0x18\nReserved\n0x1C\nReserved\n0x20\nReserved\n0x24\nTIMx_CNT\nReserved\nCNT[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nTIMx_PSC\nReserved\nPSC[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x2C\nTIMx_ARR\nReserved\nARR[15:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n\n\n<>\n\nRM0090 Rev 21\n711/1757\nRM0090\nIndependent watchdog (IWDG)\n715\n21 \nIndependent watchdog (IWDG)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n21.1 \nIWDG introduction\nThe devices have two embedded watchdog peripherals which offer a combination of high \nsafety level, timing accuracy and flexibility of use. Both watchdog peripherals (Independent \nand Window) serve to detect and resolve malfunctions due to software failure, and to trigger \nsystem reset or an interrupt (window watchdog only) when the counter reaches a given \ntimeout value.\nThe independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI) \nand thus stays active even if the main clock fails. The window watchdog (WWDG) clock is \nprescaled from the APB1 clock and has a configurable time-window that can be \nprogrammed to detect abnormally late or early application behavior.\nThe IWDG is best suited to applications which require the watchdog to run as a totally \nindependent process outside the main application, but have lower timing accuracy \nconstraints. The WWDG is best suited to applications which require the watchdog to react \nwithin an accurate timing window. For further information on the window watchdog, refer to \nSection 22 on page 716.\n21.2 \nIWDG main features\n•\nFree-running downcounter\n•\nclocked from an independent RC oscillator (can operate in Standby and Stop modes)\n•\nReset (if watchdog activated) when the downcounter value of 0x000 is reached\n21.3 \nIWDG functional description\nFigure 213 shows the functional blocks of the independent watchdog module. \nWhen the independent watchdog is started by writing the value 0xCCCC in the Key register \n(IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it \nreaches the end of count value (0x000) a reset signal is generated (IWDG reset).\nWhenever the key value 0xAAAA is written in the IWDG_KR register, the IWDG_RLR value \nis reloaded in the counter and the watchdog reset is prevented.\n21.3.1 \nHardware watchdog\nIf the “Hardware watchdog” feature is enabled through the device option bits, the watchdog \nis automatically enabled at power-on, and generates a reset unless the Key register is \nwritten by the software before the counter reaches end of count.\n21.3.2 \nRegister access protection\nWrite access to the IWDG_PR and IWDG_RLR registers is protected. To modify them, first \nwrite the code 0x5555 in the IWDG_KR register. A write access to this register with a \n\n\n<>\n\nIndependent watchdog (IWDG)\nRM0090\n712/1757\nRM0090 Rev 21\ndifferent value breaks the sequence and register access is protected again. This implies that \nit is the case of the reload operation (writing 0xAAAA).\nA status register is available to indicate that an update of the prescaler or the down-counter \nreload value is on going.\n21.3.3 \nDebug mode\nWhen the microcontroller enters debug mode (Cortex®-M4 with FPU core halted), the IWDG \ncounter either continues to work normally or stops, depending on DBG_IWDG_STOP \nconfiguration bit in DBG module. For more details, refer to Section 38.16.2: Debug support \nfor timers, watchdog, bxCAN and I2C.\nFigure 213. Independent watchdog block diagram\nNote:\nThe watchdog function is implemented in the VDD voltage domain, still functional in Stop and \nStandby modes.\n \nIWDG reset\nprescaler\nIWDG_PR\nPrescaler register\nIWDG_RLR\nReload register\n8-bit\nLSI\n(40 kHz) \nIWDG_KR\nKey register\n \nCORE\n VDD voltage domain\nIWDG_SR\nStatus register\n \nMS19944V2\n12-bit reload value\n12-bit downcounter\n \nTable 108. Min/max IWDG timeout period (in ms) at 32 kHz (LSI)(1)\n1.\nThese timings are given for a 32 kHz clock but the microcontroller internal RC frequency can vary. Refer to \nthe LSI oscillator characteristics table in the device datasheet for maximum and minimum values.\nPrescaler divider\nPR[2:0] bits\nMin timeout RL[11:0]= 0x000\nMax timeout RL[11:0]= 0xFFF\n/4\n0\n0.125\n512\n/8\n1\n0.25\n1024\n/16\n2\n0.5\n2048\n/32\n3\n1\n4096\n/64\n4\n2\n8192\n/128\n5\n4\n16384\n/256\n6\n8\n32768\n\n\n<>\n\nRM0090 Rev 21\n713/1757\nRM0090\nIndependent watchdog (IWDG)\n715\n21.4 \nIWDG registers\nRefer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.\nThe peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).\n21.4.1 \nKey register (IWDG_KR)\nAddress offset: 0x00\nReset value: 0x0000 0000 (reset by Standby mode)\n \n21.4.2 \nPrescaler register (IWDG_PR)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nKEY[15:0]\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 KEY[15:0]: Key value (write only, read 0000h)\nThese bits must be written by software at regular intervals with the key value AAAAh, \notherwise the watchdog generates a reset when the counter reaches 0. \nWriting the key value 5555h to enable access to the IWDG_PR and IWDG_RLR registers \n(see Section 21.3.2)\nWriting the key value CCCCh starts the watchdog (except if the hardware watchdog option is \nselected)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPR[2:0]\nrw\nrw\nrw\nBits 31:3 Reserved, must be kept at reset value.\nBits 2:0 PR[2:0]: Prescaler divider \nThese bits are write access protected seeSection 21.3.2. They are written by software to \nselect the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in \norder to be able to change the prescaler divider.\n000: divider /4\n001: divider /8\n010: divider /16\n011: divider /32\n100: divider /64\n101: divider /128\n110: divider /256\n111: divider /256\nNote: Reading this register returns the prescaler value from the VDD voltage domain. This \nvalue may not be up to date/valid if a write operation to this register is ongoing. For this \nreason the value read from this register is valid only when the PVU bit in the IWDG_SR \nregister is reset.\n\n\n<>\n\nIndependent watchdog (IWDG)\nRM0090\n714/1757\nRM0090 Rev 21\n21.4.3 \nReload register (IWDG_RLR)\nAddress offset: 0x08\nReset value: 0x0000 0FFF (reset by Standby mode)\n \n21.4.4 \nStatus register (IWDG_SR)\nAddress offset: 0x0C\nReset value: 0x0000 0000 (not reset by Standby mode)\n \n \nNote:\nIf several reload values or prescaler values are used by application, it is mandatory to wait \nuntil RVU bit is reset before changing the reload value and to wait until PVU bit is reset \nbefore changing the prescaler value. However, after updating the prescaler and/or the \nreload value it is not necessary to wait until RVU or PVU is reset before continuing code \nexecution (even in case of low-power mode entry, the write operation is taken into account \nand completes)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRL[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits11:0 RL[11:0]: Watchdog counter reload value \nThese bits are write access protected see Section 21.3.2. They are written by software to \ndefine the value to be loaded in the watchdog counter each time the value AAAAh is written \nin the IWDG_KR register. The watchdog counter counts down from this value. The timeout \nperiod is a function of this value and the clock prescaler. Refer to Table 108. \nThe RVU bit in the IWDG_SR register must be reset in order to be able to change the reload \nvalue.\nNote: Reading this register returns the reload value from the VDD voltage domain. This value \nmay not be up to date/valid if a write operation to this register is ongoing on this \nregister. For this reason the value read from this register is valid only when the RVU bit \nin the IWDG_SR register is reset.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRVU PVU\nr\nr\nBits 31:2 Reserved, must be kept at reset value.\nBit 1 RVU: Watchdog counter reload value update \nThis bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset \nby hardware when the reload value update operation is completed in the VDD voltage domain \n(takes up to 5 RC 40 kHz cycles).\nReload value can be updated only when RVU bit is reset.\nBit 0 PVU: Watchdog prescaler value update\nThis bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is \nreset by hardware when the prescaler update operation is completed in the VDD voltage \ndomain (takes up to 5 RC 40 kHz cycles).\nPrescaler value can be updated only when PVU bit is reset.\n\n\n<>\n\nRM0090 Rev 21\n715/1757\nRM0090\nIndependent watchdog (IWDG)\n715\n21.4.5 \nIWDG register map\nThe following table gives the IWDG register map and reset values. \n \nRefer to Section 2.3: Memory map for the register boundary addresses.\nTable 109. IWDG register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nIWDG_KR\nReserved\nKEY[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nIWDG_PR\nReserved\nPR[2:0]\nReset value\n0\n0\n0\n0x08\nIWDG_RLR\nReserved\nRL[11:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x0C\nIWDG_SR\nReserved\nRVU\nPVU\nReset value\n0\n0\n\n\n<>\n\nWindow watchdog (WWDG)\nRM0090\n716/1757\nRM0090 Rev 21\n22 \nWindow watchdog (WWDG)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n22.1 \nWWDG introduction\nThe window watchdog is used to detect the occurrence of a software fault, usually \ngenerated by external interference or by unforeseen logical conditions, which causes the \napplication program to abandon its normal sequence. The watchdog circuit generates an \nMCU reset on expiry of a programmed time period, unless the program refreshes the \ncontents of the downcounter before the T6 bit becomes cleared. An MCU reset is also \ngenerated if the 7-bit downcounter value (in the control register) is refreshed before the \ndowncounter has reached the window register value. This implies that the counter must be \nrefreshed in a limited window.\n22.2 \nWWDG main features\n•\nProgrammable free-running downcounter \n•\nConditional reset\n–\nReset (if watchdog activated) when the downcounter value becomes less than \n0x40\n–\nReset (if watchdog activated) if the downcounter is reloaded outside the window \n(see Figure 215)\n•\nEarly wake-up interrupt (EWI): triggered (if enabled and the watchdog activated) when \nthe downcounter is equal to 0x40. \n22.3 \nWWDG functional description\nIf the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the \n7-bit downcounter (T[6:0] bits) rolls over from 0x40 to 0x3F (T6 becomes cleared), it initiates \na reset. If the software reloads the counter while the counter is greater than the value stored \nin the window register, then a reset is generated.\n\n\n<>\n\nRM0090 Rev 21\n717/1757\nRM0090\nWindow watchdog (WWDG)\n722\nFigure 214. Watchdog block diagram\nThe application program must write in the WWDG_CR register at regular intervals during \nnormal operation to prevent an MCU reset. This operation must occur only when the counter \nvalue is lower than the window register value. The value to be stored in the WWDG_CR \nregister must be between 0xFF and 0xC0.\nEnabling the watchdog\nThe watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the \nWWDG_CR register, then it cannot be disabled again except by a reset.\nControlling the downcounter\nThis downcounter is free-running, counting down even if the watchdog is disabled. When \nthe watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset. \nThe T[5:0] bits contain the number of increments which represents the time delay before the \nwatchdog produces a reset. The timing varies between a minimum and a maximum value \ndue to the unknown status of the prescaler when writing to the WWDG_CR register (see \nFigure 215). The Configuration register (WWDG_CFR) contains the high limit of the window: \nTo prevent a reset, the downcounter must be reloaded when its value is lower than the \nwindow register value and greater than 0x3F. Figure 215 describes the window watchdog \nprocess.\nNote:\nThe T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is \ncleared).\nAdvanced watchdog interrupt feature \nThe Early Wake-up Interrupt (EWI) can be used if specific safety operations or data logging \nmust be performed before the actual reset is generated. The EWI interrupt is enabled by \nsetting the EWI bit in the WWDG_CFR register. When the downcounter reaches the value \n0x40, an EWI interrupt is generated and the corresponding interrupt service routine (ISR) \ncan be used to trigger specific actions (such as communications or data logging), before \nresetting the device. \n06Y\u0016\u001a\u0015\u0015\u00199\u0015\n5(6(7\n\u001a\u0010ELW\u0003GRZQFRXQWHU\u0003\u000b&17\f\n:DWFKGRJ\u0003FRQILJXUDWLRQ\u0003UHJLVWHU\u0003\u000b::'*B&)5\f\nFRPSDUDWRU\n7\u0019\u001d\u0013\u0003!\u0003:\u0019\u001d\u0013\n \u0014\u0003ZKHQ\n:ULWH\u0003::'*B&5\n3&/.\u0014\n\u000bIURP\u00035&&\u0003FORFN\u0003FRQWUROOHU\f\n:'*\u0003SUHVFDOHU\n\u000b:'*7%\f\n\u0010\n:\u0019\n:\u0014\n:\u0015\n:\u0016\n:\u0017\n:\u0018\n:\u0013\n\u0012\u0017\u0013\u001c\u0019\n:'*$\n7\u0019\n:DWFKGRJ\u0003FRQWURO\u0003UHJLVWHU\u0003\u000b::'*B&5\f\n7\u0014\n7\u0015\n7\u0016\n7\u0017\n7\u0018\n7\u0013\n\n\n<>\n\nWindow watchdog (WWDG)\nRM0090\n718/1757\nRM0090 Rev 21\nIn some applications, the EWI interrupt can be used to manage a software system check \nand/or system recovery/graceful degradation, without generating a WWDG reset. In this \ncase, the corresponding interrupt service routine (ISR) should reload the WWDG counter to \navoid the WWDG reset, then trigger the required actions. \nThe EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register. \nNote:\nWhen the EWI interrupt cannot be served (due to a system lock in a higher priority task), the \nWWDG reset is eventually generated. \n22.4 \nHow to program the watchdog timeout\nWarning:\nWhen writing to the WWDG_CR register, always write 1 in the \nT6 bit to avoid generating an immediate reset. \nFigure 215. Window watchdog timing diagram\nThe formula to calculate the WWDG timeout value is given by:\nwhere:\ntWWDG: WWDG timeout\ntPCLK1: APB1 clock period measured in ms\n4096: value corresponding to internal divider\nai17101c\nW[6:0]\nT[6:0] CNT downcounter\nRefresh not allowed\n0x3F\nRefresh allowed\nTime\nT6 bit\nRESET\ntWWDG\ntPCLK1\n4096\n×\n2WDGTB[1:0]\n×\nT[5:0]\n1\n+\n(\n)\n×\n=\nms\n(\n)\n\n\n<>\n\nRM0090 Rev 21\n719/1757\nRM0090\nWindow watchdog (WWDG)\n722\nAs an example, let us assume APB1 frequency is equal to 24 MHz, WDGTB[1:0] is set to 3 \nand T[5:0] is set to 63: \nRefer to Table 110 for the minimum and maximum values of the tWWDG.\n \n22.5 \nDebug mode\nWhen the microcontroller enters debug mode (Cortex®-M4 with FPU core halted), the \nWWDG counter either continues to work normally or stops, depending on \nDBG_WWDG_STOP configuration bit in DBG module. For more details, refer to \nSection 38.16.2: Debug support for timers, watchdog, bxCAN and I2C.\nTable 110. Minimum and maximum timeout values at 30 MHz (fPCLK1)\nPrescaler\nWDGTB\nMin timeout (µs)\nT[5:0] = 0x00\nMax timeout (ms)\nT[5:0] = 0x3F\n1\n0\n136.53\n8.74\n2\n1\n273.07\n17.48\n4\n2\n546.13\n34.95\n8\n3\n1092.27\n69.91\ntWWDG\n1\n24000\n⁄\n4096\n×\n23\n×\n63\n1\n+\n(\n)\n×\n21.85ms\n=\n=\n\n\n<>\n\nWindow watchdog (WWDG)\nRM0090\n720/1757\nRM0090 Rev 21\n22.6 \nWWDG registers\nRefer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.\nThe peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).\n22.6.1 \nControl register (WWDG_CR)\nAddress offset: 0x00\nReset value: 0x0000 007F\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nWDGA\nT[6:0]\nrs\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBit 7 WDGA: Activation bit \nThis bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the \nwatchdog can generate a reset.\n0: Watchdog disabled\n1: Watchdog enabled\nBits 6:0 T[6:0]: 7-bit counter (MSB to LSB)\nThese bits contain the value of the watchdog counter. It is decremented every (4096 x \n2WDGTB[1:0]) PCLK1 cycles. A reset is produced when it rolls over from 0x40 to 0x3F (T6 \nbecomes cleared).\n\n\n<>\n\nRM0090 Rev 21\n721/1757\nRM0090\nWindow watchdog (WWDG)\n722\n22.6.2 \nConfiguration register (WWDG_CFR)\nAddress offset: 0x04\nReset value: 0x0000 007F\n \n \n22.6.3 \nStatus register (WWDG_SR)\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nEWI\nWDGTB[1:0]\nW[6:0]\nrs\nrw\nrw\nBit 31:10 Reserved, must be kept at reset value.\nBit 9 EWI: Early wake-up interrupt\nWhen set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is \nonly cleared by hardware after a reset. \nBits 8:7 WDGTB[1:0]: Timer base\nThe time base of the prescaler can be modified as follows:\n00: CK Counter Clock (PCLK1 div 4096) div 1\n01: CK Counter Clock (PCLK1 div 4096) div 2\n10: CK Counter Clock (PCLK1 div 4096) div 4\n11: CK Counter Clock (PCLK1 div 4096) div 8\nBits 6:0 W[6:0]: 7-bit window value\nThese bits contain the window value to be compared to the downcounter.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nEWIF\nrc_w0\nBits 31:1 Reserved, must be kept at reset value.\nBit 0 EWIF: Early wake-up interrupt flag\nThis bit is set by hardware when the counter has reached the value 0x40. It must be cleared \nby software by writing ‘0’. A write of ‘1’ has no effect. This bit is also set if the interrupt is not \nenabled. \n\n\n<>\n\nWindow watchdog (WWDG)\nRM0090\n722/1757\nRM0090 Rev 21\n22.6.4 \nWWDG register map\nThe following table gives the WWDG register map and reset values. \n \nRefer to Section 2.3: Memory map for the register boundary addresses.\nTable 111. WWDG register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nWWDG_CR\nReserved\nWDGA\nT[6:0]\nReset value\n0\n1\n1\n1\n1\n1\n1\n1\n0x04\nWWDG_CFR\nReserved\nEWI\nWDGTB1\nWDGTB0\nW[6:0]\nReset value\n0\n0\n0\n1\n1\n1\n1\n1\n1\n1\n0x08\nWWDG_SR\nReserved\nEWIF\nReset value\n0\n\n\n<>\n\nRM0090 Rev 21\n723/1757\nRM0090\nCryptographic processor (CRYP)\n769\n23 \nCryptographic processor (CRYP)\nThis section applies to STM32F415/417xx and STM32F43xxx devices.\n23.1 \nCRYP introduction\nThe cryptographic processor can be used to both encipher and decipher data using the \nDES, Triple-DES or AES (128, 192, or 256) algorithms. It is a fully compliant implementation \nof the following standards:\n•\nThe data encryption standard (DES) and Triple-DES (TDES) as defined by Federal \nInformation Processing Standards Publication (FIPS PUB 46-3, 1999 October 25). It \nfollows the American National Standards Institute (ANSI) X9.52 standard.\n•\nThe advanced encryption standard (AES) as defined by Federal Information \nProcessing Standards Publication (FIPS PUB 197, 2001 November 26)\nThe CRYP processor performs data encryption and decryption using DES and TDES \nalgorithms in Electronic codebook (ECB) or Cipher block chaining (CBC) mode.\nThe CRYP peripheral is a 32-bit AHB2 peripheral. It supports DMA transfer for incoming and \nprocessed data, and has input and output FIFOs (each 8 words deep).\n23.2 \nCRYP main features\n•\nSuitable for AES, DES and TDES enciphering and deciphering operations\n•\nAES\n–\nSupports the ECB, CBC, CTR, CCM and GCM chaining algorithms (CCM and \nGCM are available on STM32F42xxx and STM32F43xxx only)\n–\nSupports 128-, 192- and 256-bit keys\n–\n4 × 32-bit initialization vectors (IV) used in the CBC, CTR, CCM and GCM modes\n \n \nTable 112. Number of cycles required to process each 128-bit block\n(STM32F415/417xx)\nAlgorithm / Key size\nECB\nCBC\nCTR\n128b\n14\n14\n14\n192b\n16\n16\n16\n256b\n18\n18\n18\nTable 113. Number of cycles required to process each 128-bit block\n(STM32F43xxx)\nAlgorithm / \nKey size\nECB\nCBC\nCTR\nGCM\nCCM\nInit\nHeader\nPayload\nTag\nInit\nHeader\nPayload\nTag\n128b\n14\n14\n14\n24\n10\n14\n14\n12\n14\n25\n14\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n724/1757\nRM0090 Rev 21\n•\nDES/TDES\n–\nDirect implementation of simple DES algorithms (a single key, K1, is used)\n–\nSupports the ECB and CBC chaining algorithms\n–\nSupports 64-, 128- and 192-bit keys (including parity)\n–\n2 × 32-bit initialization vectors (IV) used in the CBC mode\n–\n16 HCLK cycles to process one 64-bit block in DES\n–\n48 HCLK cycles to process one 64-bit block in TDES\n•\nCommon to DES/TDES and AES\n–\nIN and OUT FIFO (each with an 8-word depth, a 32-bit width, corresponding to 4 \nDES blocks or 2 AES blocks)\n–\nAutomatic data flow control with support of direct memory access (DMA) (using 2 \nchannels, one for incoming data the other for processed data)\n–\nData swapping logic to support 1-, 8-, 16- or 32-bit data\n192b\n16\n16\n16\n28\n10\n16\n16\n14\n16\n29\n16\n256b\n18\n18\n18\n32\n10\n18\n18\n16\n18\n33\n18\nTable 113. Number of cycles required to process each 128-bit block\n(STM32F43xxx)\n\n\n<>\n\nRM0090 Rev 21\n725/1757\nRM0090\nCryptographic processor (CRYP)\n769\n23.3 \nCRYP functional description\nThe cryptographic processor implements a Triple-DES (TDES, that also supports DES) core \nand an AES cryptographic core. Section 23.3.1 and Section 23.3.2 provide details on these \ncores.\nSince the TDES and the AES algorithms use block ciphers, incomplete input data blocks \nhave to be padded prior to encryption (extra bits should be appended to the trailing end of \nthe data string). After decryption, the padding has to be discarded. The hardware does not \nmanage the padding operation, the software has to handle it.\nFigure 216 shows the block diagram of the cryptographic processor.\nFigure 216. Block diagram (STM32F415/417xx)\n32-bit AHB2 bus\n \nProcessor core\nDES/TDES/AES\nCRYP_DIN\nswappi ng\nswappin g\n8 × 32-bit\nIN FIFO\n8 × 32-bit\nOUT FIFO\nCRYP_CR\nCRYP_K0...K3\nCRYP_IV0...IV1\nIV0...IV127\nk255...k0\nCRYP_IMSCR\nCRYP_RIS\nCRYP_MISR\nCRYP_DMACR\nCRYP_SR\nStatus\nDMA control register\nInterrupt registers\nControl register\nInitialization vectors\nKey\nai16068b\nCRYP_DOUT\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n726/1757\nRM0090 Rev 21\nFigure 217. Block diagram (STM32F43xxx)\n23.3.1 \nDES/TDES cryptographic core\nThe DES/Triple-DES cryptographic core consists of three components:\n•\nThe DES algorithm (DEA)\n•\nMultiple keys (1 for the DES algorithm, 1 to 3 for the TDES algorithm)\n•\nThe initialization vector (used in the CBC mode)\nThe basic processing involved in the TDES is as follows: an input block is read in the DEA \nand encrypted using the first key, K1 (K0 is not used in TDES mode). The output is then \ndecrypted using the second key, K2, and encrypted using the third key, K3. The key \ndepends on the algorithm which is used: \n•\nDES mode: Key = [K1]\n•\nTDES mode: Key = [K3 K2 K1]\nwhere Kx=[KxR KxL], R = right, L = left\nAccording to the mode implemented, the resultant output block is used to calculate the \nciphertext.\nNote that the outputs of the intermediate DEA stages is never revealed outside the \ncryptographic boundary.\n32-bit AHB2 bus\nProcessor core\nDES/TDES/AES\nCRYP_DIN\nCRYP_DOUT\nswappi ng\nswappin g\n8 × 32-bit\nIN FIFO\n8 × 32-bit\nOUT FIFO\nCRYP_CR\nCRYP_K0...K3\nCRYP_IV0...IV1\nIV0...IV127\nk255...k0\nCRYP_IMSCR\nCRYP_RIS\nCRYP_MISR\nCRYP_DMACR\nCRYP_SR\nStatus\nDMA control register\nInterrupt registers\nControl register\nInitialization vectors\nKey\nMS30441V1\nCRYP_CSGCMCCM0..7\nContext swapping\nCRYP_CSGCM0..7\n\n\n<>\n\nRM0090 Rev 21\n727/1757\nRM0090\nCryptographic processor (CRYP)\n769\nThe TDES allows three different keying options:\n•\nThree independent keys\nThe first option specifies that all the keys are independent, that is, K1, K2 and K3 are \nindependent. FIPS PUB 46-3 – 1999 (and ANSI X9.52 – 1998) refers to this option as \nthe Keying Option 1 and, to the TDES as 3-key TDES.\n•\nTwo independent keys\nThe second option specifies that K1 and K2 are independent and K3 is equal to K1, \nthat is, K1 and K2 are independent, K3 = K1. FIPS PUB 46-3 – 1999 (and ANSI X9.52 \n– 1998) refers to this second option as the Keying Option 2 and, to the TDES as 2-key \nTDES.\n•\nThree equal keys\nThe third option specifies that K1, K2 and K3 are equal, that is, K1 = K2 = K3. FIPS \nPUB 46-3 – 1999 (and ANSI X9.52 – 1998) refers to the third option as the Keying \nOption 3. This “1-key” TDES is equivalent to single DES.\nFIPS PUB 46-3 – 1999 (and ANSI X9.52-1998) provides a thorough explanation of the \nprocessing involved in the four operation modes supplied by the TDEA (TDES algorithm): \nTDES-ECB encryption, TDES-ECB decryption, TDES-CBC encryption and TDES-CBC \ndecryption.\nThis reference manual only gives a brief explanation of each mode.\nDES and TDES Electronic codebook (DES/TDES-ECB) mode\n•\nDES/TDES-ECB mode encryption\nFigure 218 illustrates the encryption in DES and TDES Electronic codebook \n(DES/TDES-ECB) mode. A 64-bit plaintext data block (P) is used after bit/byte/half-\nword swapping (refer to Section 23.3.3: Data type on page 742) as the input block (I). \nThe input block is processed through the DEA in the encrypt state using K1. The output \nof this process is fed back directly to the input of the DEA where the DES is performed \nin the decrypt state using K2. The output of this process is fed back directly to the input \nof the DEA where the DES is performed in the encrypt state using K3. The resultant 64-\nbit output block (O) is used, after bit/byte/half-word swapping, as ciphertext (C) and it is \npushed into the OUT FIFO.\n•\nDES/TDES-ECB mode decryption\nFigure 219 illustrates the DES/TDES-ECB decryption. A 64-bit ciphertext block (C) is \nused, after bit/byte/half-word swapping, as the input block (I). The keying sequence is \nreversed compared to that used in the encryption process. The input block is \nprocessed through the DEA in the decrypt state using K3. The output of this process is \nfed back directly to the input of the DEA where the DES is performed in the encrypt \nstate using K2. The new result is directly fed to the input of the DEA where the DES is \nperformed in the decrypt state using K1. The resultant 64-bit output block (O), after \nbit/byte/half-word swapping, produces the plaintext (P).\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n728/1757\nRM0090 Rev 21\nFigure 218. DES/TDES-ECB mode encryption\n1.\nK: key; C: cipher text; I: input block; O: output block; P: plain text.\nFigure 219. DES/TDES-ECB mode decryption\n1.\nK: key; C: cipher text; I: input block; O: output block; P: plain text.\nIN FIFO\nDEA, encrypt\nK1\nP, 64 bits\nDEA, decrypt\nK2\nDEA, encrypt\nK3\nOUT FIFO\nplaintext P\nciphertext C\n64\n64\n64\nswapping\nO, 64 bits\nC, 64 bits\nswapping\nDATATYPE\nDATATYPE\nai16069b\nIN FIFO\nC, 64 bits\nOUT FIFO\nciphertext C\nplaintext P\nDEA, decrypt\nK3\nDEA, encrypt\nK2\nDEA, decrypt\nK1\n64\n64\n64\nI, 64 bits\nswapping\nO, 64 bits\nDATATYPE\nDATATYPE\nP, 64 bits\nswapping\nMS19021V1\n\n\n<>\n\nRM0090 Rev 21\n729/1757\nRM0090\nCryptographic processor (CRYP)\n769\nDES and TDES Cipher block chaining (DES/TDES-CBC) mode\n•\nDES/TDES-CBC mode encryption\nFigure 220 illustrates the DES and Triple-DES Cipher block chaining (DES/TDES-\nCBC) mode encryption. This mode begins by dividing a plaintext message into 64-bit \ndata blocks. In TCBC encryption, the first input block (I1), obtained after bit/byte/half-\nword swapping (refer to Section 23.3.3: Data type on page 742), is formed by \nexclusive-ORing the first plaintext data block (P1) with a 64-bit initialization vector IV (I1 \n= IV ⊕ P1). The input block is processed through the DEA in the encrypt state using K1. \nThe output of this process is fed back directly to the input of the DEA, which performs \nthe DES in the decrypt state using K2. The output of this process is fed directly to the \ninput of the DEA, which performs the DES in the encrypt state using K3. The resultant \n64-bit output block (O1) is used directly as the ciphertext (C1), that is, C1 = O1. This first \nciphertext block is then exclusive-ORed with the second plaintext data block to produce \nthe second input block, (I2) = (C1 ⊕ P2). Note that I2 and P2 now refer to the second \nblock. The second input block is processed through the TDEA to produce the second \nciphertext block. This encryption process continues to “chain” successive cipher and \nplaintext blocks together until the last plaintext block in the message is encrypted. If the \nmessage does not consist of an integral number of data blocks, then the final partial \ndata block should be encrypted in a manner specified for the application.\n•\nDES/TDES-CBC mode decryption\nIn DES/TDES-CBC decryption (see Figure 221), the first ciphertext block (C1) is used \ndirectly as the input block (I1). The keying sequence is reversed compared to that used \nfor the encrypt process. The input block is processed through the DEA in the decrypt \nstate using K3. The output of this process is fed directly to the input of the DEA where \nthe DES is processed in the encrypt state using K2. This resulting value is directly fed \nto the input of the DEA where the DES is processed in the decrypt state using K1. The \nresulting output block is exclusive-ORed with the IV (which must be the same as that \nused during encryption) to produce the first plaintext block (P1 = O1 ⊕ IV). The second \nciphertext block is then used as the next input block and is processed through the \nTDEA. The resulting output block is exclusive-ORed with the first ciphertext block to \nproduce the second plaintext data block (P2 = O2 ⊕ C1). (Note that P2 and O2 refer to \nthe second block of data.) The TCBC decryption process continues in this manner until \nthe last complete ciphertext block has been decrypted. Ciphertext representing a \npartial data block must be decrypted in a manner specified for the application.\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n730/1757\nRM0090 Rev 21\nFigure 220. DES/TDES-CBC mode encryption\n1.\nK: key; C: cipher text; I: input block; O: output block; Ps: plain text before swapping (when decoding) or \nafter swapping (when encoding); P: plain text; IV: initialization vectors.\nIN FIFO\nDEA, encrypt\nK1\nP, 64 bits\nDEA, decrypt\nK2\nDEA, encrypt\nK3\nOUT FIFO\nO, 64 bits\nplaintext P\nciphertext C\n64\n64\n64\nPs, 64 bits\nswapping\n+\nIV0(L/R)\n64\nI, 64 bits\n(before CRYP\nis enabled)\nO is written back\ninto IV at the\nsame time as it\nis pushed into\nthe OUT FIFO\nswapping\nC, 64 bits\nDATATYPE\nDATATYPE\nAHB2 data write\nai16070b\n\n\n<>\n\nRM0090 Rev 21\n731/1757\nRM0090\nCryptographic processor (CRYP)\n769\nFigure 221. DES/TDES-CBC mode decryption\n1.\nK: key; C: cipher text; I: input block; O: output block; Ps: plain text before swapping (when decoding) or \nafter swapping (when encoding); P: plain text; IV: initialization vectors.\n23.3.2 \nAES cryptographic core\nThe AES cryptographic core consists of three components:\n•\nThe AES algorithm (AEA: advanced encryption algorithm)\n•\nMultiple keys\n•\nInitialization vector(s) or Nonce\nThe AES utilizes keys of 3 possible lengths: 128, 192 or 256 bits and, depending on the \noperation mode used, zero or one 128-bit initialization vector (IV).\nThe basic processing involved in the AES is as follows: an input block of 128 bits is read \nfrom the input FIFO and sent to the AEA to be encrypted using the key (K0...3). The key \nformat depends on the key size: \n•\nIf Key size = 128: Key = [K3 K2]\n•\nIf Key size = 192: Key = [K3 K2 K1]\n•\nIf Key size = 256: Key = [K3 K2 K1 K0]\nwhere Kx=[KxR KxL],R=right, L=left\nAccording to the mode implemented, the resultant output block is used to calculate the \nciphertext.\nFIPS PUB 197 (November 26, 2001) provides a thorough explanation of the processing \ninvolved in the four operation modes supplied by the AES core: AES-ECB encryption, AES-\nIN FIFO\nI, 64 bits\nOUT FIFO\nPs, 64 bits\nciphertext C\nplaintext P\nP, 64 bits\nswapping\nDEA, decrypt\nK3\nDEA, encrypt\nK2\nDEA, decrypt\nK1\n64\n64\n64\n+\nIV0(L/R)\n64\nAHB2 data write\n(before CRYP\nis enabled)\nO, 64 bits\nI is written back\ninto IV at the\nsame time as P\nis pushed into\n the OUT FIFO\nC, 64 bits\nswapping\nDATATYPE\nDATATYPE\nMS19022V1\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n732/1757\nRM0090 Rev 21\nECB decryption, AES-CBC encryption and AES-CBC decryption.This reference manual \nonly gives a brief explanation of each mode.\nAES Electronic codebook (AES-ECB) mode\n•\nAES-ECB mode encryption\nFigure 222 illustrates the AES Electronic codebook (AES-ECB) mode encryption.\nIn AES-ECB encryption, a 128- bit plaintext data block (P) is used after bit/byte/half-\nword swapping (refer to Section 23.3.3: Data type on page 742) as the input block (I). \nThe input block is processed through the AEA in the encrypt state using the 128, 192 or \n256-bit key. The resultant 128-bit output block (O) is used after bit/byte/half-word \nswapping as ciphertext (C). It is then pushed into the OUT FIFO.\n•\nAES-ECB mode decryption\nFigure 223 illustrates the AES Electronic codebook (AES-ECB) mode encryption.\nTo perform an AES decryption in the ECB mode, the secret key has to be prepared (it is \nnecessary to execute the complete key schedule for encryption) by collecting the last \nround key, and using it as the first round key for the decryption of the ciphertext. This \npreparation function is computed by the AES core. Refer to Section 23.3.6: Procedure \nto perform an encryption or a decryption for more details on how to prepare the key.\nIn AES-ECB decryption, a 128-bit ciphertext block (C) is used after bit/byte/half-word \nswapping as the input block (I). The keying sequence is reversed compared to that of \nthe encryption process. The resultant 128-bit output block (O), after bit/byte or half-\nword swapping, produces the plaintext (P).\nFigure 222. AES-ECB mode encryption\n1.\nK: key; C: cipher text; I: input block; O: output block; P: plain text.\n2.\nIf Key size = 128: Key = [K3 K2]. \nIf Key size = 192: Key = [K3 K2 K1]\nIf Key size = 256: Key = [K3 K2 K1 K0].\nIN FIFO\nAEA, encrypt\nK0...3(1)\nP, 128 bits\nOUT FIFO\nplaintext P\nciphertext C\n128/192\nI, 128 bits\nswapping\nC, 128 bits\nswapping\nDATATYPE\nDATATYPE\nor 256\nai16071b\n\n\n<>\n\nRM0090 Rev 21\n733/1757\nRM0090\nCryptographic processor (CRYP)\n769\nFigure 223. AES-ECB mode decryption\n1.\nK: key; C: cipher text; I: input block; O: output block; P: plain text.\n2.\nIf Key size = 128 => Key = [K3 K2]. \nIf Key size = 192 => Key = [K3 K2 K1]\nIf Key size = 256 => Key = [K3 K2 K1 K0].\nAES Cipher block chaining (AES-CBC) mode\n•\nAES-CBC mode encryption\nThe AES Cipher block chaining (AES-CBC) mode decryption is shown on Figure 224.\nIn AES-CBC encryption, the first input block (I1) obtained after bit/byte/half-word \nswapping (refer to Section 23.3.3: Data type on page 742) is formed by exclusive-\nORing the first plaintext data block (P1) with a 128-bit initialization vector IV (I1 = IV ⊕ \nP1). The input block is processed through the AEA in the encrypt state using the 128-, \n192- or 256-bit key (K0...K3). The resultant 128-bit output block (O1) is used directly as \nciphertext (C1), that is, C1 = O1. This first ciphertext block is then exclusive-ORed with \nthe second plaintext data block to produce the second input block, (I2) = (C1 ⊕ P2). \nNote that I2 and P2 now refer to the second block. The second input block is processed \nthrough the AEA to produce the second ciphertext block. This encryption process \ncontinues to “chain” successive cipher and plaintext blocks together until the last \nplaintext block in the message is encrypted. If the message does not consist of an \nintegral number of data blocks, then the final partial data block should be encrypted in a \nmanner specified for the application.\nIn the CBC mode, like in the ECB mode, the secret key must be prepared to perform an \nAES decryption. Refer to Section 23.3.6: Procedure to perform an encryption or a \ndecryption on page 747 for more details on how to prepare the key.\n•\nAES-CBC mode decryption\nIn AES-CBC decryption (see Figure 225), the first 128-bit ciphertext block (C1) is used \ndirectly as the input block (I1). The input block is processed through the AEA in the \ndecrypt state using the 128-, 192- or 256-bit key. The resulting output block is \nexclusive-ORed with the 128-bit initialization vector IV (which must be the same as that \nused during encryption) to produce the first plaintext block (P1 = O1 ⊕ IV). The second \nciphertext block is then used as the next input block and is processed through the AEA. \nThe resulting output block is exclusive-ORed with the first ciphertext block to produce \nthe second plaintext data block (P2 = O2 ⊕ C1). (Note that P2 and O2 refer to the second \nIN FIFO\nC, 128 bits\nOUT FIFO\nciphertext C\nplaintext P\nAEA, decrypt\nI, 128 bits\nswapping\nO, 128 bits\nDATATYPE\nDATATYPE\nP, 128 bits\nswapping\nK0...3(1)\n128/192\nor 256\nMS19023V1\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n734/1757\nRM0090 Rev 21\nblock of data.) The AES-CBC decryption process continues in this manner until the last \ncomplete ciphertext block has been decrypted. Ciphertext representing a partial data \nblock must be decrypted in a manner specified for the application.\nFigure 224. AES-CBC mode encryption\n1.\nK: key; C: cipher text; I: input block; O: output block; Ps: plain text before swapping (when decoding) or \nafter swapping (when encoding); P: plain text; IV: Initialization vectors.\n2.\nIVx=[IVxR IVxL], R=right, L=left.\n3.\nIf Key size = 128 => Key = [K3 K2]. \nIf Key size = 192 => Key = [K3 K2 K1]\nIf Key size = 256 => Key = [K3 K2 K1 K0].\nIN FIFO\nAEA, encrypt\nP, 128 bits\nOUT FIFO\nO, 128 bits\nplaintext P\nciphertext C\nswapping\n+\nIV=[IV1 IV0](2)\n128\nI, 128 bits\nAHB2 data write\n(before CRYP\nis enabled)\nO is written\nback into IV\nat the same time\nas it is pushed\ninto the OUT FIFO\nswapping\nC, 128 bits\nDATATYPE\nDATATYPE\nK0...3(3)\n128, 192\nor 256\nPs, 128 bits\nai16072b\n\n\n<>\n\nRM0090 Rev 21\n735/1757\nRM0090\nCryptographic processor (CRYP)\n769\nFigure 225. AES-CBC mode decryption\n1.\nK: key; C: cipher text; I: input block; O: output block; Ps: plain text before swapping (when decoding) or \nafter swapping (when encoding); P: plain text; IV: Initialization vectors.\n2.\nIVx=[IVxR IVxL], R=right, L=left.\n3.\nIf Key size = 128 => Key = [K3 K2]. \nIf Key size = 192 => Key = [K3 K2 K1]\nIf Key size = 256 => Key = [K3 K2 K1 K0].\nAES counter mode (AES-CTR) mode\nThe AES counter mode uses the AES block as a key stream generator. The generated keys \nare then XORed with the plaintext to obtain the cipher. For this reason, it makes no sense to \nspeak of different CTR encryption/decryption, since the two operations are exactly the \nsame.\nIn fact, given:\n•\nPlaintext: P[0], P[1], ..., P[n] (128 bits each)\n•\nA key K to be used (the size does not matter)\n•\nAn initial counter block (call it ICB but it has the same functionality as the IV of CBC)\nThe cipher is computed as follows:\nC[i] = enck(iv[i]) xor P[i], where:\niv[0] = ICB and iv[i+1] = func(iv[i]), where func is an update function \napplied to the previous iv block; func is basically an increment of one of the fields \ncomposing the iv block.\nGiven that the ICB for decryption is the same as the one for encryption, the key stream \ngenerated during decryption is the same as the one generated during encryption. Then, the \nciphertext is XORed with the key stream in order to retrieve the original plaintext. The \ndecryption operation therefore acts exactly in the same way as the encryption operation.\nIN FIFO\nI, 128 bits\nOUT FIFO\nciphertext C\nplaintext P\nP, 128 bits\nswapping\nAEA, decrypt\nK0...3(3)\n128, 192\n+\n128\nAHB2 data write\n(before CRYP\nis enabled)\nO, 128 bits\nI is written\nback into IV\nat the same time\nas P is pushed\ninto the OUT FIFO\nC, 128 bits\nswapping\nDATATYPE\nDATATYPE\nor 256\nPs, 128 bits\nMS19024V1\nIV=[IV1 IV0](2)\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n736/1757\nRM0090 Rev 21\nFigure 226 and Figure 227 illustrate AES-CTR encryption and decryption, respectively. \nFigure 226. AES-CTR mode encryption\n1.\nK: key; C: cipher text; I: input Block; o: output block; Ps: plain text before swapping (when decoding) or \nafter swapping (when encoding); Cs: cipher text after swapping (when decoding) or before swapping (when \nencoding); P: plain text; IV: Initialization vectors.\nIN FIFO\nAEA, encrypt\nP, 128 bits\nOUT FIFO\nCs, 128 bit\nplaintext P\nciphertext C\nswapping\n+\nIV0...1(L/R)\nO, 128 bits\nI, 128 bits\nAHB2 data write\n(before CRYP\nis enabled)\n(I + 1) is written\nback into IV\nat same time\nthan C is pushed\nin OUT FIFO\nswapping\nC, 128 bits\nDATATYPE\nDATATYPE\nK0...3\n128, 192\nor 256\nPs, 128 bits\n+1\nai16073b\n\n\n<>\n\nRM0090 Rev 21\n737/1757\nRM0090\nCryptographic processor (CRYP)\n769\nFigure 227. AES-CTR mode decryption\n1.\nK: key; C: cipher text; I: input Block; o: output block; Ps: plain text before swapping (when decoding) or \nafter swapping (when encoding); Cs: cipher text after swapping (when decoding) or before swapping (when \nencoding); P: plain text; IV: Initialization vectors.\nFigure 228 shows the structure of the IV block as defined by the standard [2]. It is composed \nof three distinct fields.\nFigure 228. Initial counter block structure for the Counter mode\n•\nNonce is a 32-bit, single-use value. A new nonce should be assigned to each different \ncommunication.\n•\nThe initialization vector (IV) is a 64-bit value and the standard specifies that the \nencryptor must choose IV so as to ensure that a given value is used only once for a \ngiven key\n•\nThe counter is a 32-bit big-endian integer that is incremented each time a block has \nbeen encrypted. The initial value of the counter should be set to ‘1’.\nThe block increments the least significant 32 bits, while it leaves the other (most significant) \n96 bits unchanged.\nIN FIFO\nAEA, encrypt\nC, 128 bits\nOUT FIFO\nPs, 128 bits\nciphertext P\nplaintext C\nswapping\n+\nIV0...1(L/R)\nI, 128 bits\nAHB2 data write\n(before CRYP\nis enabled)\n(I + 1) is written\nback into IV\nat same time\nthan P is pushed\nin OUT FIFO\nswapping\nP, 128 bits\nDATATYPE\nDATATYPE\nK0...3\n128, 192\nor 256\nCs, 128 bits\n+1\nO, 128 bits\nMS19025V1\nNonce\n32 bits\nInitialization vector (IV)\n64 bits\nCounter\n32 bits\nai16074\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n738/1757\nRM0090 Rev 21\nAES Galois/counter mode (GCM)\nThe AES Galois/counter mode (GCM) allows encrypting and authenticating the plaintext, \nand generating the correspondent ciphertext and tag (also known as message \nauthentication code or message integrity check). This algorithm is based on AES counter \nmode to ensure confidentiality. It uses a multiplier over a fixed finite field to generate the tag. \nAn initialization vector is required at the beginning of the algorithm.\nThe message to be processed is split into 2 parts: \n•\nThe header (also knows as additional authentication data): data which is authenticated \nbut no protected (such as information for routing the packet)\n•\nThe payload (also knows as plaintext or ciphertext): the message itself which is \nauthenticated and encrypted.\nNote:\nThe header must precede the payload and the two parts cannot be mixed together.\nThe GCM standard requires to pass, at the end of the message, a specific 128-bit block \ncomposed of the size of the header (64 bits) and the size of the payload (64 bits). During the \ncomputation, the header blocks must be distinguished from the payload blocks. \nIn GCM mode, four steps are required to perform an encryption/decryption: \n\n\n<>\n\nRM0090 Rev 21\n739/1757\nRM0090\nCryptographic processor (CRYP)\n769\n1.\nGCM init phase\nDuring this first step, the HASH key is calculated and saved internally to be used for \nprocessing all the blocks. It is recommended to follow the sequence below:\na) \nMake sure that the cryptographic processor is disabled by clearing the CRYPEN \nbit in the CRYP_CR register.\nb) \nSelect the GCM chaining mode by programming ALGOMODE bits to ‘01000’ in \nCRYP_CR.\nc) \nConfigure GCM_CCMPH bits to ‘00’ in CRYP_CR to start the GCM Init phase.\nd) \nInitialize the key registers (128,192 and 256 bits) in CRYP_KEYRx as well as the \ninitialization vector (IV).\ne) \nSet CRYPEN bit to ‘1’ to start the calculation of the HASH key.\nf) \nWait for the CRYPEN bit to be cleared to ‘0’ before moving on to the next phase.\ng) \nSet the CRYPEN bit to ‘1’.\n2. \nGCM header phase\nThis step must be performed after the GCM Init phase:\nh) \nSet the GCM_CCMPH bits to ‘01’ in CRYP_CR to indicate that the header phase \nhas started.\ni) \nWrite the header data. Three methods can be used:\n–\nProgram the data by blocks of 32 bits into the CRYP_DIN register, and use the \nIFNF flag to determine if the input FIFO can receive data. The size of the header \nmust be a multiple of 128 bits (4 words). \n–\nProgram the data into the CRYP_DIN register by blocks of 8 words, and use the \nIFEM flag to determine if the input FIFO can receive data (IFEM=’1’). The size of \nthe header must be a multiple of 128 bits (4 words). \n–\nUse the DMA.\nj) \nOnce all header data have been supplied, wait until the BUSY bit is cleared in the \nCRYP_SR register. \n3. \nGCM payload phase (encryption/decryption)\nThis step must be performed after the GCM header phase:\nk) \nConfigure GCM_CCMPH to ‘10’ in the CRYP_CR register.\nl) \nSelect the algorithm direction (encryption or decryption) by using the ALGODIR bit \nin CRYP_CR.\nm) Program the payload message into the CRYP_DIN register, and use the IFNF flag \nto determine if the input FIFO can receive data. Alternatively, the data could be \nprogrammed into the CRYP_DIN register by blocks of 8 words and the IFEM flag \nused to determine if the input FIFO can receive data (IFEM=’1’). In parallel, the \n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n740/1757\nRM0090 Rev 21\nOFNE/OFFU flag of the CRYP_DOUT register can be monitored to check if the \noutput FIFO is not empty.\nn) \nRepeat the previous step until all payload blocks have been encrypted or \ndecrypted. Alternatively, DMA could be used.\n4. \nGCM final phase\nThis step generates the authentication tag:\no) \nConfigure GCM_CCMPH[1:0] to ‘11’ in CRYP_CR.\np) \nWrite the input into the CRYP_DIN register 4 times. The input must contain the \nnumber of bits in the header (64 bits) concatenated with the number of bits in the \npayload (64 bits).\nq) \nWait till the OFNE flag (FIFO output not empty) is set to ‘1’ in the CRYP_SR \nregister.\nr) \nRead the CRYP_DOUT register 4 times: the output corresponds to the \nauthentication tag. \ns) \nDisable the cryptographic processor (CRYPEN bit in CRYP_CR = ‘0’)\nNote:\nWhen a decryption is performed, it is not required to compute the key at the beginning. At \nthe end of the decryption, the generated tag should be compared with the expected tag \npassed with the message. In addition, the ALGODIR bit (algorithm direction) must be set to ‘1’.\nNo need to disable/enable CRYP processor when moving from header phase to tag phase. \nAES Galois message authentication code (GMAC)\nThe cryptographic processor also supports GMAC to authenticate the plaintext. It uses the \nGCM algorithm and a multiplier over a fixed finite field to generate the corresponding tag.\nAn initialization vector is required at the beginning of the algorithm.\nActually, the GMAC algorithm corresponds to the GCM algorithm applied on a message \ncomposed of the header only. As a consequence, the payload phase is not required.\nAES combined cipher machine (CCM)\nThe CCM algorithm allows encrypting and authenticating the plaintext, as well as generating \nthe corresponding ciphertext and tag (also known as message authentication code or \nmessage integrity check). This algorithm is based on AES counter mode to ensure \nconfidentiality. It uses the AES CBC mode to generate a 128-bit tag.\nThe CCM standard (RFC 3610 Counter with CBC-MAC (CCM) dated September 2003) \ndefines particular encoding rules for the first authentication block (called B0 in the standard). \nIn particular, the first block includes flags, a nonce and the payload length expressed in \nbytes. The CCM standard specifies another format, called A or counter, for \nencryption/decryption. The counter is incremented during the payload phase and its 32 LSB \nbits are initialized to ‘1’ during the tag generation (called A0 packet in the CCM standard).\nNote:\nThe hardware does not perform the formatting operation of the B0 packet. It should be \nhandled by the software.\nAs for the GCM algorithm, the message to be processed is split into 2 parts: \n•\nThe header (also knows as additional authentication data): data which is authenticated \nbut no protected (such as information for routing the packet)\n•\nThe payload (also knows as plaintext or ciphertext): the message itself which is \nauthenticated and encrypted. \n\n\n<>\n\nRM0090 Rev 21\n741/1757\nRM0090\nCryptographic processor (CRYP)\n769\nNote:\nThe header part must precede the payload and the two parts cannot be mixed together.\nIn CCM mode, 4 steps are required to perform and encryption or decryption: \n1.\nCCM init phase\nIn this first step, the B0 packet of the CCM message (1st packet) is programmed into \nthe CRYP_DIN register. During this phase, the CRYP_DOUT register does not contain \nany output data.\nThe following sequence must be followed: \na) \nMake sure that the cryptographic processor is disabled by clearing the CRYPEN \nbit in the CRYP_CR register.\nb) \nSelect the CCM chaining mode by programming the ALGOMODE bits to ‘01001’ \nin the CRYP_CR register.\nc) \nConfigure the GCM_CCMPH bits to ‘00’ in CRYP_CR to start the CCM Init phase.\nd) \nInitialize the key registers (128,192 and 256 bits) in CRYP_KEYRx as well as the \ninitialization vector (IV).\ne) \nSet the CRYPEN bit to ‘1’ in CRYP_CR. \nf) \nProgram the B0 packet into the input data register.\ng) \nWait for the CRYPEN bit to be cleared before moving on to the next phase.\nh) \nSet CRYPEN to ‘1’.\n2. \nCCM header phase\nThis step must be performed after the CCM Init phase. The sequence is identical for \nencryption and decryption. \nDuring this phase, the CRYP_DOUT register does not contain any output data. \nThis phase can be skipped if there is no additional authenticated data.\nThe following sequence must be followed: \ni) \nSet the GCM_CCMPH bit to ’01’ in CRYP_CR to indicate that the header phase \nhas started.\nj) \nThree methods can be used:\n–\nProgram the header data by blocks of 32 bits into the CRYP_DIN register, and use \nthe IFNF flag to determine if the input FIFO can receive data. The size of the \nheader must be a multiple of 128 bits (4 words). \n–\nProgram the header data into the CRYP_DIN register by blocks of 8 words, and \nuse the IFEM flag to determine if the input FIFO can receive data (IFEM=’1’). The \nsize of the header must be a multiple of 128 bits (4 words). \n–\nUse the DMA.\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n742/1757\nRM0090 Rev 21\nNote:\nThe first block B1 must be formatted with the header length. This task should be handled by \nsoftware.\nk) \nOnce all header data have been supplied, wait until the BUSY flag is cleared.\n3. \nCCM payload phase (encryption/decryption)\nThis step must be performed after the CCM header phase. During this phase, the \nencrypted/decrypted payload is stored in the CRYP_DOUT register.\nThe following sequence must be followed: \nl) \nConfigure GCM_CCMPH bits to ‘10’ in CRYP_CR.\nm) Select the algorithm direction (encryption or decryption) by using the ALGODIR bit \nin CRYP_CR.\nn) \nProgram the payload message into the CRYP_DIN register, and use the IFNF flag \nto determine if the input FIFO can receive data. Alternatively, the data could be \nprogrammed into the CRYP_DIN register by blocks of 8 words and the IFEM flag \nused to determine if the input FIFO can receive data (IFEM=’1’). In parallel, the \nOFNE/OFFU flag of the CRYP_DOUT register can be monitored to check if the \noutput FIFO is not empty.\no) \nRepeat the previous step until all payload blocks have been encrypted or \ndecrypted. Alternatively, DMA could be used.\n4. \nCCM final phase\nThis step generates the authentication tag. During this phase, the authentication tag of \nthe message is generated and stored in the CRYP_DOUT register.\np) \nConfigure GCM_CCMPH[1:0] bits to ‘11’ in CRYP_CR.\nq) \nLoad the A0 initialized counter, and program the 128-bit A0 value by writing 4 \ntimes 32 bits into the CRYP_DIN register.\nr) \nWait till the OFNE flag (FIFO output not empty) is set to ‘1’ in the CRYP_SR \nregister.\ns) \nRead the CRYP_DOUT register 4 times: the output corresponds to the encrypted \nauthentication tag. \nt) \nDisable the cryptographic processor (CRYPEN bit in CRYP_CR = ‘0’)\nNote:\nThe hardware does not perform the formatting of the original B0 and B1 packets and the tag \ncomparison between encryption and decryption. They have to be handled by software.\nThe cryptographic processor does not need to be disabled/enabled when moving from the \nheader phase to the tag phase.\nAES cipher message authentication code (CMAC)\nThe CMAC algorithm allows authenticating the plaintext, and generating the corresponding \ntag. The CMAC sequence is identical to the CCM one, except that the payload phase is \nskipped. \n23.3.3 \nData type\nData enter the CRYP processor 32 bits (word) at a time as they are written into the \nCRYP_DIN register. The principle of the DES is that streams of data are processed 64 bits \nby 64 bits and, for each 64-bit block, the bits are numbered from M1 to M64, with M1 the left-\nmost bit and M64 the right-most bit of the block. The same principle is used for the AES, but \nwith a 128-bit block size.\n\n\n<>\n\nRM0090 Rev 21\n743/1757\nRM0090\nCryptographic processor (CRYP)\n769\nThe system memory organization is little-endian: whatever the data type (bit, byte, 16-bit \nhalf-word, 32-bit word) used, the least-significant data occupy the lowest address locations. \nA bit, byte, or half-word swapping operation (depending on the kind of data to be encrypted) \ntherefore has to be performed on the data read from the IN FIFO before they enter the \nCRYP processor. The same swapping operation should be performed on the CRYP data \nbefore they are written into the OUT FIFO. For example, the operation would be byte \nswapping for an ASCII text stream.\nThe kind of data to be processed is configured with the DATATYPE bitfield in the CRYP \ncontrol register (CRYP_CR).\n \nFigure 229 shows how the 64-bit data block M1...64 is constructed from two consecutive 32-\nbit words popped off the IN FIFO by the CRYP processor, according to the DATATYPE \nvalue. The same schematic can easily be extended to form the 128-bit block for the AES \nTable 114. Data types\nDATATYPE in \nCRYP_CR\nSwapping performed\nSystem memory data\n(plaintext or cypher)\n00b\nNo swapping\nExample: TDES block value 0xABCD77206973FE01 is \nrepresented in system memory as:\n01b\nHalf-word (16-bit) \nswapping\nExample: TDES block value 0xABCD77206973FE01 is \nrepresented in system memory as:\n10b\nByte (8-bit) swapping\nExample: TDES block value 0xABCD77206973FE01 is \nrepresented in system memory as:\n11b\nBit swapping\nTDES block value 0x4E6F772069732074 is represented in system \nmemory as:\n \n0xABCD7720 6973FE01 \nTDES block size = 64bit = 2x 32 bit \n0xABCD7720 \n0x6973FE01 \n@ \n@+4 \nsystem memory \n0xABCD 7720 6973 FE01 \nTDES block size = 64bit = 2x 32 bit \n0x7720 ABCD \n0xFE01 6973 \n@ \n@+4 \nsystem memory \n \n0xAB CD 77 20 69 73 FE 01 \nTDES block size = 64bit = 2x 32 bit \n0x 20 77 CD AB \n0x 01 FE 73 69 \n@ \n@+4 \nsystem memory \n \n0x4E 6F 77 20 69 73 20 74 \n0x04 EE F6 72 \n0x2E 04 CE 96 \n@ \n@+4 \n0000 0100 1110 1110 1111 0110 0111 0010 \n0100 1110 0110 1111 \n0111 0111 0010 0000 \n0110 1001 0111 0011 \n0010 0000 0111 0100 \n0010 1110 0000 0100 1100 1110 1001 0110 \n@ \n@+4 \nsystem memory\n \nTDES Bloc size = 64bit = 2x 32 bit \n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n744/1757\nRM0090 Rev 21\ncryptographic algorithm (for the AES, the block length is four 32-bit words, but swapping \nonly takes place at word level, so it is identical to the one described here for the TDES).\nNote:\nThe same swapping is performed between the IN FIFO and the CRYP data block, and \nbetween the CRYP data block and the OUT FIFO.\nFigure 229. 64-bit block construction according to DATATYPE\nByte 0,3\nByte 0,2\nByte 0,1\nByte 0,0\nM25...32\nM17...24\nM9...16\nM1...8\nIN FIFO\nbit string\nM1\nM2\nM30\nM31 M32\nbit swapping operation\nIN FIFO\nbit string\nbyte swapping operation\nByte 0,0\nByte 0,1\nByte 0,2\nByte 0,3\nbits 7...0\nbits 7...0\nbits 7...0\nbits 7...0\nIN FIFO\nbit string\nhald-word swapping operation\nHalf-word 0,0\nbits 15...0\nDATATYPE = 11b\nDATATYPE = 10b\nDATATYPE = 01b\nHalf-word 0,1\nbits 15...0\nHalf-word 0,0\nM1...16\nHalf-word 0,1\nM17...32\nM33\nM34 M62\nM63\nM64\nbit 0\nbit 1\nbit 2\nbit 30\nbit 31\nbit 0\nbit 1\nbit 2\nbit 30\nbit 31\nfirst word written into the CRYP_DIN register\nsecond word written into the CRYP_DIN register\nByte 1,0\nByte 1,1\nByte 1,2\nByte 1,3\nbits 7...0\nbits 7...0\nbits 7...0\nbits 7...0\nfirst word written into the CRYP_DIN register\nsecond word written into the CRYP_DIN register\nByte 1,3\nByte 1,2\nByte 1,1\nByte 1,0\nM57...64\nM49...56\nM41...48\nM33...40\n(bit ordering within byte is unchanged)\nHalf-word 1,0\nbits 15...0\nHalf-word 1,1\nbits 15...0\nfirst word written into the CRYP_DIN register\nsecond word written into the CRYP_DIN register\nHalf-word 1,0\nM33...48\nHalf-word 1,1\nM49...64\nIN FIFO\nbit string\nNo swapping operation\nDATATYPE = 00b\nWord 0\nbits 31...0\nWord 0\nM1...32\nWord 1\nbits 31...0\nfirst word written into the CRYP_DIN register\nsecond word written into the CRYP_DIN register\nWord 1\nM33...64\nai16075\n\n\n<>\n\nRM0090 Rev 21\n745/1757\nRM0090\nCryptographic processor (CRYP)\n769\n23.3.4 \nInitialization vectors - CRYP_IV0...1(L/R)\nInitialization vectors are considered as two 64-bit data items. They therefore do not have the \nsame data format and representation in system memory as plaintext or cypher data, and \nthey are not affected by the DATATYPE value.\nInitialization vectors are defined by two consecutive 32-bit words, CRYP_IVL (left part, \nnoted as bits IV1...32) and CRYP_IVR (right part, noted as bits IV33...64). \nDuring the DES or TDES CBC encryption, the CRYP_IV0(L/R) bits are XORed with the 64-\nbit data block popped off the IN FIFO after swapping (according to the DATATYPE value), \nthat is, with the M1...64 bits of the data block. When the output of the DEA3 block is \navailable, it is copied back into the CRYP_IV0(L/R) vector, and this new content is XORed \nwith the next 64-bit data block popped off the IN FIFO, and so on.\nDuring the DES or TDES CBC decryption, the CRYP_IV0(L/R) bits are XORed with the 64-\nbit data block (that is, with the M1...64 bits) delivered by the TDEA1 block before swapping \n(according to the DATATYPE value), and pushed into the OUT FIFO. When the XORed \nresult is swapped and pushed into the OUT FIFO, the CRYP_IV0(L/R) value is replaced by \nthe output of the IN FIFO, then the IN FIFO is popped, and a new 64-bit data block can be \nprocessed.\nDuring the AES CBC encryption, the CRYP_IV0...1(L/R) bits are XORed with the 128-bit \ndata block popped off the IN FIFO after swapping (according to the DATATYPE value). \nWhen the output of the AES core is available, it is copied back into the CRYP_IV0...1(L/R) \nvector, and this new content is XORed with the next 128-bit data block popped off the IN \nFIFO, and so on.\nDuring the AES CBC decryption, the CRYP_IV0...1(L/R) bits are XORed with the 128-bit \ndata block delivered by the AES core before swapping (according to the DATATYPE value) \nand pushed into the OUT FIFO. When the XORed result is swapped and pushed into the \nOUT FIFO, the CRYP_IV0...1(L/R) value is replaced by the output of the IN FIFO, then the \nIN FIFO is popped, and a new 128-bit data block can be processed.\nDuring the AES CTR encryption or decryption, the CRYP_IV0...1(L/R) bits are encrypted by \nthe AES core. Then the result of the encryption is XORed with the 128-bit data block popped \noff the IN FIFO after swapping (according to the DATATYPE value). When the XORed result \nis swapped and pushed into the OUT FIFO, the counter part of the CRYP_IV0...1(L/R) value \n(32 LSB) is incremented.\nAny write operation to the CRYP_IV0...1(L/R) registers when bit BUSY = 1b in the \nCRYP_SR register is disregarded (CRYP_IV0...1(L/R) register content not modified). Thus, \nyou must check that bit BUSY = 0b before modifying initialization vectors.\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n746/1757\nRM0090 Rev 21\nFigure 230. Initialization vectors use in the TDES-CBC encryption\n23.3.5 \nCRYP busy state\nWhen there is enough data in the input FIFO (at least 2 words for the DES or TDES \nalgorithm mode, 4 words for the AES algorithm mode) and enough free-space in the output \nFIFO (at least 2 (DES/TDES) or 4 (AES) word locations), and when the bit CRYPEN = 1 in \nthe CRYP_CR register, then the cryptographic processor automatically starts an encryption \nor decryption process (according to the value of the ALGODIR bit in the CRYP_CR \nregister).\nThis process takes 48 AHB2 clock cycles for the Triple-DES algorithm, 16 AHB2 clock \ncycles for the simple DES algorithm, and 14, 16 or 18 AHB2 clock cycles for the AES with \nkey lengths of 128, 192 or 256 bits, respectively. During the whole process, the BUSY bit in \nthe CRYP_SR register is set to ‘1’. At the end of the process, two (DES/TDES) or four (AES) \nwords are written by the CRYP Core into the output FIFO, and the BUSY bit is cleared. In \nCRYP_IVL\nbit string\nM1 M2 M30 M31 M32\nTDES-CBC encryption example, DATATYPE = 11b\nM33 M34 M62 M63 M64\nbit 0\nbit 1\nbit 2\nbit 30\nbit 31\nbit 0\nbit 1\nbit 2\nbit 30\nbit 31\nfirst word written into the CRYP_DIN register\nsecond word written into the CRYP_DIN register\nIV1\nCRYP_IVR\n0\n1\n2\n30\n31\n0\n1\n2\n30\n31\nDEA Encrypt, \nK1\nDEA Decrypt, \nK2\nDEA Encrypt, \nK3\nCRYP_IVL\nCRYP_IVR\n0\n1\n2\n30\n31\n0\n1\n2\n30\n31\nCRYP result is copied\nback to the CRYP_IVL/R\nregisters after cyphering\nOUT FIFO\nFirst word from the OUT FIFO contains the left part of the cyphertext block (O1...32)\nSecond word from OUT FIFO contains the right part of cyphertext block (O33...64)\nIV2\nIV30 IV31 IV32 IV33 IV34\nIV62 IV63 IV64\nI1\nI2\nI30\nI33\nI34\nI62\nI63\nI64\nI31\nI32\nIV1\nIV2\nIV30 IV31 IV32 IV33 IV34\nIV62 IV63 IV64\nai16076\n\n\n<>\n\nRM0090 Rev 21\n747/1757\nRM0090\nCryptographic processor (CRYP)\n769\nthe CBC, CTR mode, the initialization vectors CRYP_IVx(L/R)R (x = 0..3) are updated as \nwell.\nA write operation to the key registers (CRYP_Kx(L/R)R, x = 0..3), the initialization registers \n(CRYP_IVx(L/R)R, x = 0..3), or to bits [9:2] in the CRYP_CR register are ignored when the \ncryptographic processor is busy (bit BUSY = 1b in the CRYP_SR register), and the registers \nare not modified. It is thus not possible to modify the configuration of the cryptographic \nprocessor while it is processing a block of data. It is however possible to clear the CRYPEN \nbit while BUSY = 1, in which case the ongoing DES, TDES or AES processing is completed \nand the two/four word results are written into the output FIFO, and then, only then, the \nBUSY bit is cleared.\nNote:\nWhen a block is being processed in the DES or TDES mode, if the output FIFO becomes full \nand if the input FIFO contains at least one new block, then the new block is popped off the \ninput FIFO and the BUSY bit remains high until there is enough space to store this new \nblock into the output FIFO.\n23.3.6 \nProcedure to perform an encryption or a decryption\nInitialization\n1.\nInitialize the peripheral (the order of operations is not important except for the key \npreparation for AES-ECB or AES-CBC decryption. The key size and the key value \nmust be entered before preparing the key and the algorithm must be configured once \nthe key has been prepared):\na) \nConfigure the key size (128-, 192- or 256-bit, in the AES only) with the KEYSIZE \nbits in the CRYP_CR register\nb) \nWrite the symmetric key into the CRYP_KxL/R registers (2 to 8 registers to be \nwritten depending on the algorithm)\nc) \nConfigure the data type (1-, 8-, 16- or 32-bit), with the DATATYPE bits in the \nCRYP_CR register\nd) \nIn case of decryption in AES-ECB or AES-CBC, you must prepare the key: \nconfigure the key preparation mode by setting the ALGOMODE bits to ‘111’ in the \nCRYP_CR register. Then write the CRYPEN bit to ‘1’: the BUSY bit is set. Wait \nuntil BUSY returns to 0 (CRYPEN is automatically cleared as well): the key is \nprepared for decryption\ne) \nConfigure the algorithm and chaining (the DES/TDES in ECB/CBC, the AES in \nECB/CBC/CTR/GCM/CCM) with the ALGOMODE bits in the CRYP_CR register\nf) \nConfigure the direction (encryption/decryption), with the ALGODIR bit in the \nCRYP_CR register\ng) \nWrite the initialization vectors into the CRYP_IVxL/R register (in CBC or CTR \nmodes only)\n2. \nFlush the IN and OUT FIFOs by writing the FFLUSH bit to 1 in the CRYP_CR register\nProcessing when the DMA is used to transfer the data from/to the memory\n1.\nConfigure the DMA controller to transfer the input data from the memory. The transfer \nlength is the length of the message. As message padding is not managed by the \nperipheral, the message length must be an entire number of blocks. The data are \ntransferred in burst mode. The burst length is 4 words in the AES and 2 or 4 words in \n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n748/1757\nRM0090 Rev 21\nthe DES/TDES. The DMA should be configured to set an interrupt on transfer \ncompletion of the output data to indicate that the processing is finished.\n2. \nEnable the cryptographic processor by writing the CRYPEN bit to 1. Enable the DMA \nrequests by setting the DIEN and DOEN bits in the CRYP_DMACR register.\n3. \nAll the transfers and processing are managed by the DMA and the cryptographic \nprocessor. The DMA interrupt indicates that the processing is complete. Both FIFOs \nare normally empty and BUSY = 0.\nProcessing when the data are transferred by the CPU during interrupts\n1.\nEnable the interrupts by setting the INIM and OUTIM bits in the CRYP_IMSCR register.\n2. \nEnable the cryptographic processor by setting the CRYPEN bit in the CRYP_CR \nregister.\n3. \nIn the interrupt managing the input data: load the input message into the IN FIFO. You \ncan load 2 or 4 words at a time, or load data until the FIFO is full. When the last word of \nthe message has been entered into the FIFO, disable the interrupt by clearing the INIM \nbit.\n4. \nIn the interrupt managing the output data: read the output message from the OUT \nFIFO. You can read 1 block (2 or 4 words) at a time or read data until the FIFO is \nempty. When the last word has been read, INIM=0, BUSY=0 and both FIFOs are empty \n(IFEM=1 and OFNE=0). You can disable the interrupt by clearing the OUTIM bit and, \nthe peripheral by clearing the CRYPEN bit.\nProcessing without using the DMA nor interrupts\n1.\nEnable the cryptographic processor by setting the CRYPEN bit in the CRYP_CR \nregister.\n2. \nWrite the first blocks in the input FIFO (2 to 8 words).\n3. \nRepeat the following sequence until the complete message has been processed:\na) \nWait for OFNE=1, then read the OUT-FIFO (1 block or until the FIFO is empty)\nb) \nWait for IFNF=1, then write the IN FIFO (1 block or until the FIFO is full)\n4. \nAt the end of the processing, BUSY=0 and both FIFOs are empty (IFEM=1 and \nOFNE=0). You can disable the peripheral by clearing the CRYPEN bit.\n23.3.7 \nContext swapping\nIf a context switching is needed because a new task launched by the OS requires this \nresource, the following tasks have to be performed for full context restoration (example \nwhen the DMA is used):\n\n\n<>\n\nRM0090 Rev 21\n749/1757\nRM0090\nCryptographic processor (CRYP)\n769\nCase of the AES and DES\n1.\nContext saving\na) \nStop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR \nregister.\nb) \nWait until both the IN and OUT FIFOs are empty (IFEM=1 and OFNE=0 in the \nCRYP_SR register) and the BUSY bit is cleared.\nc) \nStop DMA transfers on the OUT FIFO by writing the DOEN bit to 0 in the \nCRYP_DMACR register and clear the CRYPEN bit.\nd) \nSave the current configuration (bits [9:2] and bits 19 in the CRYP_CR register) \nand, if not in ECB mode, the initialization vectors. The key value must already be \navailable in the memory. When needed, save the DMA status (pointers for IN and \nOUT messages, number of remaining bytes, etc.). \nAdditional bits should be saved when GCM/GMAC or CCM/CMAC algorithms are \nused:\n–\nbits [17:16] in the CRYP_CR register\n–\ncontext swap registers:\nCRYP_CSGCMCCM0..7 for GCM/GMAC or CCM/CMAC algorithm\nCRYP_CSGCM0..7 for GCM/GMAC algorithm.\n2. \nConfigure and execute the other processing.\n3. \nContext restoration\na) \nConfigure the processor as in Section 23.3.6: Procedure to perform an encryption \nor a decryption on page 747, Initialization with the saved configuration. For the \nAES-ECB or AES-CBC decryption, the key must be prepared again.\nb) \nIf needed, reconfigure the DMA controller to transfer the rest of the message.\nc) \nEnable the processor by setting the CRYPEN bit and, the DMA requests by setting \nthe DIEN and DOEN bits.\nCase of the TDES\nContext swapping can be done in the TDES in the same way as in the AES. But as the input \nFIFO can contain up to 4 unprocessed blocks and as the processing duration per block is \nhigher, it can be faster in certain cases to interrupt the processing without waiting for the IN \nFIFO to be empty.\n1.\nContext saving\na) \nStop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR \nregister.\nb) \nDisable the processor by clearing the CRYPEN bit (the processing stops at the \nend of the current block).\nc) \nWait until the OUT FIFO is empty (OFNE=0 in the CRYP_SR register) and the \nBUSY bit is cleared.\nd) \nStop DMA transfers on the OUT FIFO by writing the DOEN bit to 0 in the \nCRYP_DMACR register.\ne) \nSave the current configuration (bits [9:2] and bits 19 in the CRYP_CR register) \nand, if not in ECB mode, the initialization vectors. The key value must already be \navailable in the memory. When needed, save the DMA status (pointers for IN and \nOUT messages, number of remaining bytes, etc.). Read back the data loaded in \n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n750/1757\nRM0090 Rev 21\nthe IN FIFO that have not been processed and save them in the memory until the \nFIFO is empty.\nNote:\nIn GCM/GMAC or CCM/CMAC mode, bits [17:16] of the CRYP_CR register should also be \nsaved.\n2. \nConfigure and execute the other processing.\n3. \nContext restoration\na) \nConfigure the processor as in Section 23.3.6: Procedure to perform an encryption \nor a decryption on page 747, Initialization with the saved configuration. For the \nAES-ECB or AES-CBC decryption, the key must be prepared again.\nb) \nWrite the data that were saved during context saving into the IN FIFO.\nc) \nIf needed, reconfigure the DMA controller to transfer the rest of the message.\nd) \nEnable the processor by setting the CRYPEN bit and, the DMA requests by setting \nthe DIEN and DOEN bits.\n23.4 \nCRYP interrupts\nThere are two individual maskable interrupt sources generated by the CRYP. These two \nsources are combined into a single interrupt signal, which is the only interrupt signal from \nthe CRYP that drives the NVIC (nested vectored interrupt controller). This combined \ninterrupt, which is an OR function of the individual masked sources, is asserted if any of the \nindividual interrupts listed below is asserted and enabled.\nYou can enable or disable the interrupt sources individually by changing the mask bits in the \nCRYP_IMSCR register. Setting the appropriate mask bit to ‘1’ enables the interrupt.\nThe status of the individual interrupt sources can be read either from the CRYP_RISR \nregister, for raw interrupt status, or from the CRYP_MISR register, for the masked interrupt \nstatus.\nOutput FIFO service interrupt - OUTMIS\nThe output FIFO service interrupt is asserted when there is one or more (32-bit word) data \nitems in the output FIFO. This interrupt is cleared by reading data from the output FIFO until \nthere is no valid (32-bit) word left (that is, the interrupt follows the state of the OFNE (output \nFIFO not empty) flag).\nThe output FIFO service interrupt OUTMIS is NOT enabled with the CRYP enable bit. \nConsequently, disabling the CRYP does not force the OUTMIS signal low if the output FIFO \nis not empty.\nInput FIFO service interrupt - INMIS\nThe input FIFO service interrupt is asserted when there are less than four words in the input \nFIFO. It is cleared by performing write operations to the input FIFO until it holds four or more \nwords.\nThe input FIFO service interrupt INMIS is enabled with the CRYP enable bit. Consequently, \nwhen CRYP is disabled, the INMIS signal is low even if the input FIFO is empty.\n\n\n<>\n\nRM0090 Rev 21\n751/1757\nRM0090\nCryptographic processor (CRYP)\n769\nFigure 231. CRYP interrupt mapping diagram\n23.5 \nCRYP DMA interface\nThe cryptographic processor provides an interface to connect to the DMA controller. The \nDMA operation is controlled through the CRYP DMA control register, CRYP_DMACR.\nThe burst and single transfer request signals are not mutually exclusive. They can both be \nasserted at the same time. For example, when there are 6 words available in the OUT FIFO, \nthe burst transfer request and the single transfer request are asserted. After a burst transfer \nof 4 words, the single transfer request only is asserted to transfer the last 2 available words. \nThis is useful for situations where the number of words left to be received in the stream is \nless than a burst.\nEach request signal remains asserted until the relevant DMA clear signal is asserted. After \nthe request clear signal is deasserted, a request signal can become active again, depending \non the above described conditions. All request signals are deasserted if the CRYP \nperipheral is disabled or the DMA enable bit is cleared (DIEN bit for the IN FIFO and DOEN \nbit for the OUT FIFO in the CRYP_DMACR register).\nNote:\nThe DMA controller must be configured to perform burst of 4 words or less. Otherwise some \ndata could be lost.\nIn order to let the DMA controller empty the OUT FIFO before filling up the IN FIFO, the \nOUTDMA channel should have a higher priority than the INDMA channel.\n23.6 \nCRYP registers\nThe cryptographic core is associated with several control and status registers, eight key \nregisters and four initialization vectors registers.\n23.6.1 \nCRYP control register (CRYP_CR) for STM32F415/417xx\nAddress offset: 0x00\nReset value: 0x0000 0000\n \nINRIS\nINIM\nCRYPEN\nINMIS\nIN FIFO Interrupt - INMIS\nOUTRIS\nOUTIM\nOUTMIS\nOUT FIFO Interrupt - OUTMIS\nGlobal Interrupt\nai16077\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCRYPEN FFLUSH\nReserved\nKEYSIZE\nDATATYPE\nALGOMODE[2:0]\nALGODIR\nRes.\nRes.\nrw\nw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n752/1757\nRM0090 Rev 21\n \nBits 31:18 Reserved, must be kept at reset value\nBits 17:16 Reserved, must be kept at reset value\nBit 15 CRYPEN: Cryptographic processor enable\n0: CRYP processor is disabled\n1: CRYP processor is enabled\nNote: The CRYPEN bit is automatically cleared by hardware when the key \npreparation process ends (ALGOMODE=111b) or GCM_CCM init Phase\nBit 14 FFLUSH: FIFO flush\nWhen CRYPEN = 0, writing this bit to 1 flushes the IN and OUT FIFOs (that is \nread and write pointers of the FIFOs are reset. Writing this bit to 0 has no effect.\nWhen CRYPEN = 1, writing this bit to 0 or 1 has no effect.\nReading this bit always returns 0.\nBits 13:10 Reserved, must be kept at reset value\nBits 9:8 KEYSIZE[1:0]: Key size selection (AES mode only)\nThis bitfield defines the bit-length of the key used for the AES cryptographic core. \nThis bitfield is ‘don’t care’ in the DES or TDES modes.\n00: 128 bit key length\n01: 192 bit key length\n10: 256 bit key length\n11: Reserved, do not use this value\nBits 7:6 DATATYPE[1:0]: Data type selection\nThis bitfield defines the format of data entered in the CRYP_DIN register (refer to \nSection 23.3.3: Data type).\n00: 32-bit data. No swapping of each word. First word pushed into the IN FIFO \n(or popped off the OUT FIFO) forms bits 1...32 of the data block, the second \nword forms bits 33...64.\n01: 16-bit data, or half-word. Each word pushed into the IN FIFO (or popped off \nthe OUT FIFO) is considered as 2 half-words, which are swapped with each \nother.\n10: 8-bit data, or bytes. Each word pushed into the IN FIFO (or popped off the \nOUT FIFO) is considered as 4 bytes, which are swapped with each other.\n11: bit data, or bit-string. Each word pushed into the IN FIFO (or popped off the \nOUT FIFO) is considered as 32 bits (1st bit of the string at position 0), which are \nswapped with each other.\n\n\n<>\n\nRM0090 Rev 21\n753/1757\nRM0090\nCryptographic processor (CRYP)\n769\nNote:\nWriting to the KEYSIZE, DATATYPE, ALGOMODE and ALGODIR bits while BUSY=1 has \nno effect. These bits can only be configured when BUSY=0.\nThe FFLUSH bit has to be set only when BUSY=0. If not, the FIFO is flushed, but the block \nbeing processed may be pushed into the output FIFO just after the flush operation, resulting \nin a nonempty FIFO condition.\n23.6.2 \nCRYP control register (CRYP_CR) for STM32F415/417xx\nAddress offset: 0x00\nReset value: 0x0000 0000\n Bits 5:3 ALGOMODE[2:0]: Algorithm mode\n000: TDES-ECB (triple-DES Electronic codebook): no feedback between blocks \nof data. Initialization vectors (CRYP_IV0(L/R)) are not used, three key vectors \n(K1, K2, and K3) are used (K0 is not used).\n001: TDES-CBC (triple-DES Cipher block chaining): output block is XORed with \nthe subsequent input block before its entry into the algorithm. Initialization \nvectors (CRYP_IV0L/R) must be initialized, three key vectors (K1, K2, and K3) \nare used (K0 is not used).\n010: DES-ECB (simple DES Electronic codebook): no feedback between blocks \nof data. Initialization vectors (CRYP_IV0L/R) are not used, only one key vector \n(K1) is used (K0, K2, K3 are not used).\n011: DES-CBC (simple DES Cipher block chaining): output block is XORed with \nthe subsequent input block before its entry into the algorithm. Initialization \nvectors (CRYP_IV0L/R) must be initialized. Only one key vector (K1) is used \n(K0, K2, K3 are not used).\n100: AES-ECB (AES Electronic codebook): no feedback between blocks of data. \nInitialization vectors (CRYP_IV0L/R...1L/R) are not used. All four key vectors \n(K0...K3) are used.\n101: AES-CBC (AES Cipher block chaining): output block is XORed with the \nsubsequent input block before its entry into the algorithm. Initialization vectors \n(CRYP_IV0L/R...1L/R) must be initialized. All four key vectors (K0...K3) are \nused.\n110: AES-CTR (AES counter mode): output block is XORed with the subsequent \ninput block before its entry into the algorithm. Initialization vectors \n(CRYP_IV0L/R...1L/R) must be initialized. All four key vectors (K0...K3) are \nused. CTR decryption does not differ from CTR encryption, since the core \nalways encrypts the current counter block to produce the key stream that is \nXORed with the plaintext or cipher in input. Thus, ALGODIR is don’t care when \nALGOMODE = 110b, and the key must NOT be unrolled (prepared) for \ndecryption.\n111: AES key preparation for decryption mode. Writing this value when CRYPEN \n= 1 immediately starts an AES round for key preparation. The secret key must \nhave previously been loaded into the K0...K3 registers. The BUSY bit in the \nCRYP_SR register is set during the key preparation. After key processing, the \nresulting key is copied back into the K0...K3 registers, and the BUSY bit is \ncleared.\nBit 2 ALGODIR: Algorithm direction\n0: Encrypt\n1: Decrypt\nBits 1:0 Reserved, must be kept at reset value\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n754/1757\nRM0090 Rev 21\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nALGO\nMODE\n[3]\nRes.\nGCM_CCMPH\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCRYPEN FFLUSH\nReserved\nKEYSIZE\nDATATYPE\nALGOMODE[2:0]\nALGODIR\nReserved\nrw\nw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:20 Reserved, forced by hardware to 0.\nBit 18 Reserved, forced by hardware to 0.\nBits 17:16 GCM_CCMPH[1:0]: no effect if “GCM or CCM algorithm” is not set\n00: GCM_CCM init Phase\n01: GCM_CCM header phase\n10: GCM_CCM payload phase\n11: GCM_CCM final phase\nBit 15 CRYPEN: Cryptographic processor enable\n0: CRYP processor is disabled\n1: CRYP processor is enabled\nNote: The CRYPEN bit is automatically cleared by hardware when the key \npreparation process ends (ALGOMODE=111b) or GCM_CCM init Phase\nBit 14 FFLUSH: FIFO flush\nWhen CRYPEN = 0, writing this bit to 1 flushes the IN and OUT FIFOs (that is \nread and write pointers of the FIFOs are reset. Writing this bit to 0 has no effect.\nWhen CRYPEN = 1, writing this bit to 0 or 1 has no effect.\nReading this bit always returns 0.\nBits 13:10 Reserved, forced by hardware to 0.\nBits 9:8 KEYSIZE[1:0]: Key size selection (AES mode only)\nThis bitfield defines the bit-length of the key used for the AES cryptographic core. \nThis bitfield is ‘don’t care’ in the DES or TDES modes.\n00: 128 bit key length\n01: 192 bit key length\n10: 256 bit key length\n11: Reserved, do not use this value\nBits 7:6 DATATYPE[1:0]: Data type selection\nThis bitfield defines the format of data entered in the CRYP_DIN register (refer to \nSection 23.3.3: Data type).\n00: 32-bit data. No swapping of each word. First word pushed into the IN FIFO \n(or popped off the OUT FIFO) forms bits 1...32 of the data block, the second \nword forms bits 33...64.\n01: 16-bit data, or half-word. Each word pushed into the IN FIFO (or popped off \nthe OUT FIFO) is considered as 2 half-words, which are swapped with each \nother.\n10: 8-bit data, or bytes. Each word pushed into the IN FIFO (or popped off the \nOUT FIFO) is considered as 4 bytes, which are swapped with each other.\n11: bit data, or bit-string. Each word pushed into the IN FIFO (or popped off the \nOUT FIFO) is considered as 32 bits (1st bit of the string at position 0), which are \nswapped with each other.\n\n\n<>\n\nRM0090 Rev 21\n755/1757\nRM0090\nCryptographic processor (CRYP)\n769\nNote:\nWriting to the KEYSIZE, DATATYPE, ALGOMODE and ALGODIR bits while BUSY=1 has \nno effect. These bits can only be configured when BUSY=0.\nThe FFLUSH bit has to be set only when BUSY=0. If not, the FIFO is flushed, but the block \nbeing processed may be pushed into the output FIFO just after the flush operation, resulting \nin a nonempty FIFO condition.\nBits 19 and 5:3 ALGOMODE[3:0]: Algorithm mode\n0000: TDES-ECB (triple-DES Electronic codebook): no feedback between \nblocks of data. Initialization vectors (CRYP_IV0(L/R)) are not used, three key \nvectors (K1, K2, and K3) are used (K0 is not used).\n0001: TDES-CBC (triple-DES Cipher block chaining): output block is XORed \nwith the subsequent input block before its entry into the algorithm. Initialization \nvectors (CRYP_IV0L/R) must be initialized, three key vectors (K1, K2, and K3) \nare used (K0 is not used).\n0010: DES-ECB (simple DES Electronic codebook): no feedback between \nblocks of data. Initialization vectors (CRYP_IV0L/R) are not used, only one key \nvector (K1) is used (K0, K2, K3 are not used).\n0011: DES-CBC (simple DES Cipher block chaining): output block is XORed with \nthe subsequent input block before its entry into the algorithm. Initialization \nvectors (CRYP_IV0L/R) must be initialized. Only one key vector (K1) is used \n(K0, K2, K3 are not used).\n0100: AES-ECB (AES Electronic codebook): no feedback between blocks of \ndata. Initialization vectors (CRYP_IV0L/R...1L/R) are not used. All four key \nvectors (K0...K3) are used.\n0101: AES-CBC (AES Cipher block chaining): output block is XORed with the \nsubsequent input block before its entry into the algorithm. Initialization vectors \n(CRYP_IV0L/R...1L/R) must be initialized. All four key vectors (K0...K3) are \nused.\n0110: AES-CTR (AES Counter mode): output block is XORed with the \nsubsequent input block before its entry into the algorithm. Initialization vectors \n(CRYP_IV0L/R...1L/R) must be initialized. All four key vectors (K0...K3) are \nused. CTR decryption does not differ from CTR encryption, since the core \nalways encrypts the current counter block to produce the key stream that is \nXORed with the plaintext or cipher in input. Thus, ALGODIR is don’t care when \nALGOMODE = 110b, and the key must NOT be unrolled (prepared) for \ndecryption.\n0111: AES key preparation for decryption mode. Writing this value when \nCRYPEN = 1 immediately starts an AES round for key preparation. The secret \nkey must have previously been loaded into the K0...K3 registers. The BUSY bit \nin the CRYP_SR register is set during the key preparation. After key processing, \nthe resulting key is copied back into the K0...K3 registers, and the BUSY bit is \ncleared.\n1000: Galois Counter Mode (GCM). This algorithm mode is also used for the \nGMAC algorithm.\n1001: Counter with CBC-MAC (CCM). This algorithm mode is also used for the \nCMAC algorithm.\nBit 2 ALGODIR: Algorithm direction\n0: Encrypt\n1: Decrypt\nBits 1:0 Reserved, must be kept to 0.\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n756/1757\nRM0090 Rev 21\n23.6.3 \nCRYP status register (CRYP_SR)\nAddress offset: 0x04\nReset value: 0x0000 0003\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBUSY\nOFFU\nOFNE\nIFNF\nIFEM\nr\nr\nr\nr\nr\nBits 31:5 Reserved, must be kept at reset value\nBit 4 BUSY: Busy bit\n0: The CRYP Core is not processing any data. The reason is either that:\n–\nthe CRYP core is disabled (CRYPEN=0 in the CRYP_CR register) and \nthe last processing has completed, or\n–\nThe CRYP core is waiting for enough data in the input FIFO or enough \nfree space in the output FIFO (that is in each case at least 2 words in \nthe DES, 4 words in the AES).\n1: The CRYP core is currently processing a block of data or a key preparation \n(for AES decryption).\nBit 3 OFFU: Output FIFO full\n0: Output FIFO is not full\n1: Output FIFO is full\nBit 2 OFNE: Output FIFO not empty\n0: Output FIFO is empty\n1: Output FIFO is not empty\nBit 1 IFNF: Input FIFO not full\n0: Input FIFO is full\n1: Input FIFO is not full\nBit 0 IFEM: Input FIFO empty\n0: Input FIFO is not empty\n1: Input FIFO is empty\n\n\n<>\n\nRM0090 Rev 21\n757/1757\nRM0090\nCryptographic processor (CRYP)\n769\n23.6.4 \nCRYP data input register (CRYP_DIN)\nAddress offset: 0x08\nReset value: 0x0000 0000\nThe CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter up to \nfour 64-bit (TDES) or two 128-bit (AES) plaintext (when encrypting) or ciphertext (when \ndecrypting) blocks into the input FIFO, one 32-bit word at a time.\nThe first word written into the FIFO is the MSB of the input block. The LSB of the input block \nis written at the end. Disregarding the data swapping, this gives:\n•\nIn the DES/TDES modes: a block is a sequence of bits numbered from bit 1 (leftmost \nbit) to bit 64 (rightmost bit). Bit 1 corresponds to the MSB (bit 31) of the first word \nentered into the FIFO, bit 64 corresponds to the LSB (bit 0) of the second word entered \ninto the FIFO.\n•\nIn the AES mode: a block is a sequence of bits numbered from 0 (leftmost bit) to 127 \n(rightmost bit). Bit 0 corresponds to the MSB (bit 31) of the first word written into the \nFIFO, bit 127 corresponds to the LSB (bit 0) of the 4th word written into the FIFO.\nTo fit different data sizes, the data written in the CRYP_DIN register can be swapped before \nbeing processed by configuring the DATATYPE bits in the CRYP_CR register. Refer to \nSection 23.3.3: Data type on page 742 for more details.\nWhen CRYP_DIN register is written to, the data are pushed into the input FIFO. When at \nleast two 32-bit words in the DES/TDES mode (or four 32-bit words in the AES mode) have \nbeen pushed into the input FIFO, and when at least 2 words are free in the output FIFO, the \nCRYP engine starts an encrypting or decrypting process. This process takes two 32-bit \nwords in the DES/TDES mode (or four 32-bit words in the AES mode) from the input FIFO \nand delivers two 32-bit words (or 4, respectively) to the output FIFO per process round.\nWhen CRYP_DIN register is read:\n•\nIf CRYPEN = 0, the FIFO is popped, and then the data present in the Input FIFO are \nreturned, from the oldest one (first reading) to the newest one (last reading). The IFEM \nflag must be checked before each read operation to make sure that the FIFO is not \nempty.\n•\nif CRYPEN = 1, an undefined value is returned.\nAfter the CRYP_DIN register has been read once or several times, the FIFO must be \nflushed by setting the FFLUSH bit prior to processing new data.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATAIN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATAIN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 DATAIN: Data input\nRead = returns Input FIFO content if CRYPEN = 0, else returns an undefined \nvalue.\nWrite = Input FIFO is written.\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n758/1757\nRM0090 Rev 21\n23.6.5 \nCRYP data output register (CRYP_DOUT)\nAddress offset: 0x0C\nReset value: 0x0000 0000\nThe CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is \nused to retrieve up to four 64-bit (TDES mode) or two 128-bit (AES mode) ciphertext (when \nencrypting) or plaintext (when decrypting) blocks from the output FIFO, one 32-bit word at a \ntime.\nLike for the input data, the MSB of the output block is the first word read from the output \nFIFO. The LSB of the output block is read at the end. Disregarding data swapping, this \ngives:\n•\nIn the DES/TDES modes: Bit 1 (leftmost bit) corresponds to the MSB (bit 31) of the first \nword read from the FIFO, bit 64 (rightmost bit) corresponds to the LSB (bit 0) of the \nsecond word read from the FIFO.\n•\nIn the AES mode: Bit 0 (leftmost bit) corresponds to the MSB (bit 31) of the first word \nread from the FIFO, bit 127 (rightmost bit) corresponds to the LSB (bit 0) of the 4th \nword read from the FIFO.\nTo fit different data sizes, the data can be swapped after processing by configuring the \nDATATYPE bits in the CRYP_CR register. Refer to Section 23.3.3: Data type on page 742 \nfor more details.\nWhen CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to \nby the read pointer) is returned.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATAOUT\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATAOUT\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 DATAOUT: Data output\nRead = returns output FIFO content.\nWrite = No effect.\n\n\n<>\n\nRM0090 Rev 21\n759/1757\nRM0090\nCryptographic processor (CRYP)\n769\n23.6.6 \nCRYP DMA control register (CRYP_DMACR)\nAddress offset: 0x10\nReset value: 0x0000 0000\n \n \n23.6.7 \nCRYP interrupt mask set/clear register (CRYP_IMSCR)\nAddress offset: 0x14\nReset value: 0x0000 0000\nThe CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write \nregister. On a read operation, this register gives the current value of the mask on the \nrelevant interrupt. Writing 1 to the particular bit sets the mask, enabling the interrupt to be \nread. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when \nthe peripheral is reset.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDOEN\nDIEN\nrw\nrw\nBits 31:2 Reserved, must be kept at reset value\nBit 1 DOEN: DMA output enable\n0: DMA for outgoing data transfer is disabled\n1: DMA for outgoing data transfer is enabled\nBit 0 DIEN: DMA input enable\n0: DMA for incoming data transfer is disabled\n1: DMA for incoming data transfer is enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOUTIM\nINIM\nrw\nrw\nBits 31:2 Reserved, must be kept at reset value\nBit 1 OUTIM: Output FIFO service interrupt mask\n0: Output FIFO service interrupt is masked\n1: Output FIFO service interrupt is not masked\nBit 0 INIM: Input FIFO service interrupt mask\n0: Input FIFO service interrupt is masked\n1: Input FIFO service interrupt is not masked\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n760/1757\nRM0090 Rev 21\n23.6.8 \nCRYP raw interrupt status register (CRYP_RISR)\nAddress offset: 0x18\nReset value: 0x0000 0001\nThe CRYP_RISR register is the raw interrupt status register. It is a read-only register. On a \nread, this register gives the current raw status of the corresponding interrupt prior to \nmasking. A write has no effect.\n \n \n23.6.9 \nCRYP masked interrupt status register (CRYP_MISR)\nAddress offset: 0x1C\nReset value: 0x0000 0000\nThe CRYP_MISR register is the masked interrupt status register. It is a read-only register. \nOn a read, this register gives the current masked status of the corresponding interrupt prior \nto masking. A write has no effect.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOUTRIS\nINRIS\nr\nr\nBits 31:2 Reserved, must be kept at reset value\nBit 1 OUTRIS: Output FIFO service raw interrupt status\nGives the raw interrupt state prior to masking of the output FIFO service \ninterrupt.\n0: Raw interrupt not pending\n1: Raw interrupt pending\nBit 0 INRIS: Input FIFO service raw interrupt status\nGives the raw interrupt state prior to masking of the Input FIFO service interrupt.\n0: Raw interrupt not pending\n1: Raw interrupt pending\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOUTMIS\nINMIS\nr\nr\n\n\n<>\n\nRM0090 Rev 21\n761/1757\nRM0090\nCryptographic processor (CRYP)\n769\n \n23.6.10 \nCRYP key registers (CRYP_K0...3(L/R)R)\nAddress offset: 0x20 to 0x3C\nReset value: 0x0000 0000\nThese registers contain the cryptographic keys.\nIn the TDES mode, keys are 64-bit binary values (number from left to right, that is the \nleftmost bit is bit 1), named K1, K2 and K3 (K0 is not used), each key consists of 56 \ninformation bits and 8 parity bits. The parity bits are reserved for error detection purposes \nand are not used by the current block. Thus, bits 8, 16, 24, 32, 40, 48, 56 and 64 of each 64-\nbit key value Kx[1:64] are not used.\nIn the AES mode, the key is considered as a single 128-, 192- or 256-bit long bit sequence, \nk0k1k2...k127/191/255 (k0 being the leftmost bit). The AES key is entered into the registers as \nfollows:\n•\nfor AES-128: k0..k127 corresponds to b127..b0 (b255..b128 are not used),\n•\nfor AES-192: k0..k191 corresponds to b191..b0 (b255..b192 are not used),\n•\nfor AES-256: k0..k255 corresponds to b255..b0.\nIn any case b0 is the rightmost bit.\nCRYP_K0LR (address offset: 0x20)\nCRYP_K0RR (address offset: 0x24)\nBits 31:2 Reserved, must be kept at reset value\nBit 1 OUTMIS: Output FIFO service masked interrupt status\nGives the interrupt state after masking of the output FIFO service interrupt.\n0: Interrupt not pending\n1: Interrupt pending\nBit 0 INMIS: Input FIFO service masked interrupt status\nGives the interrupt state after masking of the input FIFO service interrupt.\n0: Interrupt not pending\n1: Interrupt pending when CRYPEN = 1\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nb255\nb254\nb253\nb252\nb251\nb250\nb249\nb248\nb247\nb246\nb245\nb244\nb243\nb242\nb241\nb240\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nb239\nb238\nb237\nb236\nb235\nb234\nb233\nb232\nb231\nb230\nb229\nb228\nb227\nb226\nb225\nb224\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nb223\nb222\nb221\nb220\nb219\nb218\nb217\nb216\nb215\nb214\nb213\nb212\nb211\nb210\nb209\nb208\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nb207\nb206\nb205\nb204\nb203\nb202\nb201\nb200\nb199\nb198\nb197\nb196\nb195\nb194\nb193\nb192\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n762/1757\nRM0090 Rev 21\nCRYP_K1LR (address offset: 0x28)\nCRYP_K1RR (address offset: 0x2C)\nCRYP_K2LR (address offset: 0x30)\nCRYP_K2RR (address offset: 0x34)\nCRYP_K3LR (address offset: 0x38)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nk1.1\nb191\nk1.2\nb190\nk1.3\nb189\nk1.4\nb188\nk1.5\nb187\nk1.6\nb186\nk1.7\nb185\nk1.8\nb184\nk1.9\nb183\nk1.10\nb182\nk1.11\nb181\nk1.12\nb180\nk1.13\nb179\nk1.14\nb178\nk1.15\nb177\nk1.16\nb176\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nk1.17\nb175\nk1.18\nb174\nk1.19\nb173\nk1.20\nb172\nk1.21\nb171\nk1.22\nb170\nk1.23\nb169\nk1.24\nb168\nk1.25\nb167\nk1.26\nb166\nk1.27\nb165\nk1.28\nb164\nk1.29\nb163\nk1.30\nb162\nk1.31\nb161\nk1.32\nb160\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nk1.33\nb159\nk1.34\nb158\nk1.35\nb157\nk1.36\nb156\nk1.37\nb155\nk1.38\nb154\nk1.39\nb153\nk1.40\nb152\nk1.41\nb151\nk1.42\nb150\nk1.43\nb149\nk1.44\nb148\nk1.45\nb147\nk1.46\nb146\nk1.47\nb145\nk1.48\nb144\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nk1.49\nb143\nk1.50\nb142\nk1.51\nb141\nk1.52\nb140\nk1.53\nb139\nk1.54\nb138\nk1.55\nb137\nk1.56\nb136\nk1.57\nb135\nk1.58\nb134\nk1.59\nb133\nk1.60\nb132\nk1.61\nb131\nk1.62\nb130\nk1.63\nb129\nk1.64\nb128\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nk2.1\nb127\nk2.2\nb126\nk2.3\nb125\nk2.4\nb124\nk2.5\nb123\nk2.6\nb122\nk2.7\nb121\nk2.8\nb120\nk2.9\nb119\nk2.10\nb118\nk2.11\nb117\nk2.12\nb116\nk2.13\nb115\nk2.14\nb114\nk2.15\nb113\nk2.16\nb112\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nk2.17\nb111\nk2.18\nb110\nk2.19\nb109\nk2.20\nb108\nk2.21\nb107\nk2.22\nb106\nk2.23\nb105\nk2.24\nb104\nk2.25\nb103\nk2.26\nb102\nk2.27\nb101\nk2.28\nb100\nk2.29\nb99\nk2.30\nb98\nk2.31\nb97\nk2.32\nb96\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nk2.33\nb95\nk2.34\nb94\nk2.35\nb93\nk2.36\nb92\nk2.37\nb91\nk2.38\nb90\nk2.39\nb89\nk2.40\nb88\nk2.41\nb87\nk2.42\nb86\nk2.43\nb85\nk2.44\nb84\nk2.45\nb83\nk2.46\nb82\nk2.47\nb81\nk2.48\nb80\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nk2.49\nb79\nk2.50\nb78\nk2.51\nb77\nk2.52\nb76\nk2.53\nb75\nk2.54\nb74\nk2.55\nb73\nk2.56\nb72\nk2.57\nb71\nk2.58\nb70\nk2.59\nb69\nk2.60\nb68\nk2.61\nb67\nk2.62\nb66\nk2.63\nb65\nk2.64\nb64\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nk3.1\nb63\nk3.2\nb62\nk3.3\nb61\nk3.4\nb60\nk3.5\nb59\nk3.6\nb58\nk3.7\nb57\nk3.8\nb56\nk3.9\nb55\nk3.10\nb54\nk3.11\nb53\nk3.12\nb52\nk3.13\nb51\nk3.14\nb50\nk3.15\nb49\nk3.16\nb48\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nk3.17\nb47\nk3.18\nb46\nk3.19\nb45\nk3.20\nb44\nk3.21\nb43\nk3.22\nb42\nk3.23\nb41\nk3.24\nb40\nk3.25\nb39\nk3.26\nb38\nk3.27\nb37\nk3.28\nb36\nk3.29\nb35\nk3.30\nb34\nk3.31\nb33\nk3.32\nb32\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n\n\n<>\n\nRM0090 Rev 21\n763/1757\nRM0090\nCryptographic processor (CRYP)\n769\nCRYP_K3RR (address offset: 0x3C)\nNote:\nWrite accesses to these registers are disregarded when the cryptographic processor is busy \n(bit BUSY = 1 in the CRYP_SR register).\n23.6.11 \nCRYP initialization vector registers (CRYP_IV0...1(L/R)R)\nAddress offset: 0x40 to 0x4C\nReset value: 0x0000 0000\nThe CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization \nvector (64 bits for DES/TDES and 128 bits for AES) and are used in the CBC (Cipher block \nchaining) and Counter (CTR) modes. After each computation round of the TDES or AES \nCore, the CRYP_IV0...1(L/R)R registers are updated as described in Section : DES and \nTDES Cipher block chaining (DES/TDES-CBC) mode on page 729, Section : AES Cipher \nblock chaining (AES-CBC) mode on page 733 and Section : AES counter mode (AES-CTR) \nmode on page 735.\nIV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of \nthe initialization vector. IV1(L/R)R is used only in the AES.\nCRYP_IV0LR (address offset: 0x40)\nCRYP_IV0RR (address offset: 0x44)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nk3.33\nb31\nk3.34\nb30\nk3.35\nb29\nk3.36\nb28\nk3.37\nb27\nk3.38\nb26\nk3.39\nb25\nk3.40\nb24\nk3.41\nb23\nk3.42\nb22\nk3.43\nb21\nk3.44\nb20\nk3.45\nb19\nk3.46\nb18\nk3.47\nb17\nk3.48\nb16\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nk3.49\nb15\nk3.50\nb14\nk3.51\nb13\nk3.52\nb12\nk3.53\nb11\nk3.54\nb10\nk3.55\nb9\nk3.56\nb8\nk3.57\nb7\nk3.58\nb6\nk3.59\nb5\nk3.60\nb4\nk3.61\nb3\nk3.62\nb2\nk3.63\nb1\nk3.64\nb0\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nIV0\nIV1\nIV2\nIV3\nIV4\nIV5\nIV6\nIV7\nIV8\nIV9\nIV10\nIV11\nIV12\nIV13\nIV14\nIV15\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nIV16\nIV17\nIV18\nIV19\nIV20\nIV21\nIV22\nIV23\nIV24\nIV25\nIV26\nIV27\nIV28\nIV29\nIV30\nIV31\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nIV32\nIV33\nIV34\nIV35\nIV36\nIV37\nIV38\nIV39\nIV40\nIV41\nIV42\nIV43\nIV44\nIV45\nIV46\nIV47\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nIV48\nIV49\nIV50\nIV51\nIV52\nIV53\nIV54\nIV55\nIV56\nIV57\nIV58\nIV59\nIV60\nIV61\nIV62\nIV63\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n764/1757\nRM0090 Rev 21\nCRYP_IV1LR (address offset: 0x48)\nCRYP_IV1RR (address offset: 0x4C)\nNote:\nIn DES/3DES modes, only CRYP_IV0(L/R) is used.\nWrite access to these registers are disregarded when the cryptographic processor is busy \n(bit BUSY = 1 in the CRYP_SR register).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nIV64\nIV65\nIV66\nIV67\nIV68\nIV69\nIV70\nIV71\nIV72\nIV73\nIV74\nIV75\nIV76\nIV77\nIV78\nIV79\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nIV80\nIV81\nIV82\nIV83\nIV84\nIV85\nIV86\nIV87\nIV88\nIV89\nIV90\nIV91\nIV92\nIV93\nIV94\nIV95\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nIV96\nIV97\nIV98\nIV99\nIV100\nIV101\nIV102\nIV103\nIV104\nIV105\nIV106\nIV107\nIV108\nIV109\nIV110\nIV111\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nIV112\nIV113\nIV114\nIV115\nIV116\nIV117\nIV118\nIV119\nIV120\nIV121\nIV122\nIV123\nIV124\nIV125\nIV126\nIV127\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n765/1757\nRM0090\nCryptographic processor (CRYP)\n769\n23.6.12 \nCRYP context swap registers (CRYP_CSGCMCCM0..7R and\nCRYP_CSGCM0..7R) for STM32F42xxx and STM32F43xxx\nAddress offset: \n•\nCRYP_CSGCMCCM0..7: 0x050 to 0x06C: used for GCM/GMAC or CCM/CMAC \nalogrithm only\n•\nCRYP_CSGCM0..7: 0x070 to 0x08C: used for GCM/GMAC algorithm only\nReset value: 0x0000 0000\nThese registers contain the complete internal register states of the CRYP processor when \nthe GCM/GMAC or CCM/CMAC algorithm is selected. They are useful when a context swap \nhas to be performed because a high-priority task needs the cryptographic processor while it \nis already in use by another task. \nWhen such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in \nGCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM/CMAC mode) registers have to \nbe read and the values retrieved have to be saved in the system memory space. The \ncryptographic processor can then be used by the preemptive task, and when the \ncryptographic computation is complete, the saved context can be read from memory and \nwritten back into the corresponding context swap registers.\nNote:\nThese registers are used only when GCM/GMAC or CCM/CMAC algorithm mode is \nselected.\nCRYP_CSGCMCCMxR: where x=[7:0]\nCRYP_CSGCMxR: where x=[7:0]\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCRYP_CSGCMCCMxR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCRYP_CSGCMCCMxR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCRYP_CSGCMxR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCRYP_CSGCMxR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n766/1757\nRM0090 Rev 21\n23.6.13 \nCRYP register map\n Table 115. CRYP register map and reset values for STM32F415/417xx\nOffset\nRegister \nname and \nreset value\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\n0x00\nCRYP_CR\nReserved\nCRYPEN\nFFLUSH\nReserved\nKEYSIZE\nDATATYPE\nALOMODE[2:0]\nALGODIR\nRes.\nReset value\n0 0\n0 0 0 0 0 0 0 0\n0x04\nCRYP_SR\nReserved\nBUSY\nOFFU\nOFNE\nIFNF\nIFEM\nReset value\n0 0 0 1 1\n0x08\nCRYP_DIN\nDATAIN\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0\n0x0C\nCRYP_DOUT\nDATAOUT\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0\n0x10\nCRYP_DMAC\nR\nReserved\nDOEN\nDIEN\nReset value\n0 0\n0x14\nCRYP_IMSC\nR\nReserved\nOUTIM\nINIM\nReset value\n0 0\n0x18\nCRYP_RISR\nReserved\nOUTRIS\nINRIS\nReset value\n0 1\n0x1C\nCRYP_MISR\nReserved\nOUTMIS\nIN%IS\nReset value\n0 0\n0x20\nCRYP_K0LR\nCRYP_K0LR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x24\nCRYP_K0RR\nCRYP_K0RR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n...\n0x38\nCRYP_K3LR\nCRYP_K3LR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x3C\nCRYP_K3RR\nCRYP_K3RR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x40\nCRYP_IV0LR\nCRYP_IV0LR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n\n\n<>\n\nRM0090 Rev 21\n767/1757\nRM0090\nCryptographic processor (CRYP)\n769\n \n0x44\nCRYP_IV0RR\nCRYP_IV0RR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x48\nCRYP_IV1LR\nCRYP_IV1LR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x4C\nCRYP_IV1RR\nCRYP_IV1RR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nTable 115. CRYP register map and reset values for STM32F415/417xx (continued)\nOffset\nRegister \nname and \nreset value\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTable 116. CRYP register map and reset values for STM32F43xxx\nOffset\nRegister \nname\nreset value\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\n0x00\nCRYP_CR\nReserved\nALGOMODE[3]\nRes.\nGCM_CCMPH\nCRYPEN\nFFLUSH\nReserved\nKEYSIZE\nDATATYPE\nALOMODE[2:0]\nALGODIR\nRes..\nReset value\n0 0 0 0\n0 0 0 0 0 0 0 0\n0x04\nCRYP_SR\nReserved\nBUSY\nOFFU\nOFNE\nIFNF\nIFEM\nReset value\n0 0 0 1 1\n0x08\nCRYP_DIN\nDATAIN\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0\n0x0C\nCRYP_DOUT\nDATAOUT\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0\n0x10\nCRYP_DMAC\nR\nReserved\nDOEN\nDIEN\nReset value\n0 0\n0x14\nCRYP_IMSC\nR\nReserved\nOUTIM\nINIM\nReset value\n0 0\n0x18\nCRYP_RISR\nReserved\nOUTRIS\nINRIS\nReset value\n0 1\n\n\n<>\n\nCryptographic processor (CRYP)\nRM0090\n768/1757\nRM0090 Rev 21\n0x1C\nCRYP_MISR\nReserved\nOUTMIS\nIN%IS\nReset value\n0 0\n0x20\nCRYP_K0LR\nCRYP_K0LR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x24\nCRYP_K0RR\nCRYP_K0RR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n...\n...\n0x38\nCRYP_K3LR\nCRYP_K3LR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x3C\nCRYP_K3RR\nCRYP_K3RR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x40\nCRYP_IV0LR\nCRYP_IV0LR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x44\nCRYP_IV0RR\nCRYP_IV0RR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x48\nCRYP_IV1LR\nCRYP_IV1LR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x4C\nCRYP_IV1RR\nCRYP_IV1RR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x50\nCRYP_\nCSGCMCCM\nR\nCRYP_CSGCMCCM0R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x54\nCRYP_\nCSGCMCCM\n1R\nCRYP_CSGCMCCM1R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x58\nCRYP_\nCSGCMCCM\n2R\nCRYP_CSGCMCCM2R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x5C\nCRYP_\nCSGCMCCM\n3R\nCRYP_CSGCMCCM3R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nTable 116. CRYP register map and reset values for STM32F43xxx (continued)\nOffset\nRegister \nname\nreset value\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n769/1757\nRM0090\nCryptographic processor (CRYP)\n769\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x60\nCRYP_\nCSGCMCCM\n4R\nCRYP_CSGCMCCM4R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x64\nCRYP_\nCSGCMCCM\n5R\nCRYP_CSGCMCCM5R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x68\nCRYP_\nCSGCMCCM\n6R\nCRYP_CSGCMCCM6R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x6C\nCRYP_\nCSGCMCCM\n7R\nCRYP_CSGCMCCM7R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x70\nCRYP_CSGC\nM0R\nCRYP_CSGCM0R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x74\nCRYP_CSGC\nM1R\nCRYP_CSGCM1R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x78\nCRYP_CSGC\nM2R\nCRYP_CSGCM2R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x7C\nCRYP_CSGC\nM3R\nCRYP_CSGCM3R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x80\nCRYP_CSGC\nM4R\nCRYP_CSGCM4R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x84\nCRYP_CSGC\nM5R\nCRYP_CSGCM5R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x88\nCRYP_CSGC\nM6R\nCRYP_CSGCM6R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x8C\nCRYP_CSGC\nM7R\nCRYP_CSGCM7R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nTable 116. CRYP register map and reset values for STM32F43xxx (continued)\nOffset\nRegister \nname\nreset value\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRandom number generator (RNG)\nRM0090\n770/1757\nRM0090 Rev 21\n24 \nRandom number generator (RNG)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n24.1 \nRNG introduction\nThe RNG processor is a random number generator, based on a continuous analog noise, \nthat provides a random 32-bit value to the host when read. \nThe RNG passed the FIPS PUB 140-2 (2001 October 10) tests with a success ratio of 99%.\n24.2 \nRNG main features\n•\nIt delivers 32-bit random numbers, produced by an analog generator\n•\n40 periods of the RNG_CLK clock signal between two consecutive random numbers\n•\nMonitoring of the RNG entropy to flag abnormal behavior (generation of stable values, \nor of a stable sequence of values)\n•\nIt can be disabled to reduce power consumption\n24.3 \nRNG functional description\nFigure 232 shows the RNG block diagram.\nFigure 232. Block diagram\n1.\nFor more details about RNG Clock (RNG_CLK) source, please refer to Section 6: Reset and clock control \nfor STM32F42xxx and STM32F43xxx (RCC) and Section 7: Reset and clock control for \nSTM32F405xx/07xx and STM32F415xx/17xx(RCC).\nThe random number generator implements an analog circuit. This circuit generates seeds \nthat feed a linear feedback shift register (RNG_LFSR) in order to produce 32-bit random \nnumbers.\n32-bit AHB bus\nRNG_DR\nRNG _CR\nRNG _SR\nStatus register\nControl register\nfault detector\nLFSR\nAnalog seed\nRNG_CLK\nClock checker &\ndata register\n Shift Register\nfeed a Linear Feedback\nai16080\n\n\n<>\n\nRM0090 Rev 21\n771/1757\nRM0090\nRandom number generator (RNG)\n774\nThe analog circuit is made of several ring oscillators whose outputs are XORed to generate \nthe seeds. The RNG_LFSR is clocked by a dedicated clock (RNG_CLK) at a constant \nfrequency, so that the quality of the random number is independent of the HCLK frequency. \nThe contents of the RNG_LFSR are transferred into the data register (RNG_DR) when a \nsignificant number of seeds have been introduced into the RNG_LFSR.\nIn parallel, the analog seed and the dedicated RNG_CLK clock are monitored. Status bits (in \nthe RNG_SR register) indicate when an abnormal sequence occurs on the seed or when \nthe frequency of the RNG_CLK clock is too low. An interrupt can be generated when an \nerror is detected.\n24.3.1 \nOperation\nTo run the RNG, follow the steps below:\n1.\nEnable the interrupt if needed (to do so, set the IE bit in the RNG_CR register). An \ninterrupt is generated when a random number is ready or when an error occurs.\n2. \nEnable the random number generation by setting the RNGEN bit in the RNG_CR \nregister. This activates the analog part, the RNG_LFSR and the error detector.\n3. \nAt each interrupt, check that no error occurred (the SEIS and CEIS bits should be ‘0’ in \nthe RNG_SR register) and that a random number is ready (the DRDY bit is ‘1’ in the \nRNG_SR register). The contents of the RNG_DR register can then be read.\nAs required by the FIPS PUB (Federal Information Processing Standard Publication) 140-2, \nthe first random number generated after setting the RNGEN bit should not be used, but \nsaved for comparison with the next generated random number. Each subsequent generated \nrandom number has to be compared with the previously generated number. The test fails if \nany two compared numbers are equal (continuous random number generator test).\n24.3.2 \nError management\nIf the CEIS bit is read as ‘1’ (clock error)\nIn the case of a clock, the RNG is no more able to generate random numbers because the \nRNG_CLK clock is not correct. Check that the clock controller is correctly configured to \nprovide the RNG clock and clear the CEIS bit. The RNG can work when the CECS bit is ‘0’. \nThe clock error has no impact on the previously generated random numbers, and the \nRNG_DR register contents can be used.\nIf the SEIS bit is read as ‘1’ (seed error)\nIn the case of a seed error, the generation of random numbers is interrupted for as long as \nthe SECS bit is ‘1’. If a number is available in the RNG_DR register, it must not be used \nbecause it may not have enough entropy.\nWhat you should do is clear the SEIS bit, then clear and set the RNGEN bit to reinitialize \nand restart the RNG.\n24.4 \nRNG registers\nThe RNG is associated with a control register, a data register and a status register. They \nhave to be accessed by words (32 bits).\n\n\n<>\n\nRandom number generator (RNG)\nRM0090\n772/1757\nRM0090 Rev 21\n24.4.1 \nRNG control register (RNG_CR)\nAddress offset: 0x00\nReset value: 0x0000 0000\n \n \n24.4.2 \nRNG status register (RNG_SR)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nIE\nRNGEN\nReserved\nrw\nrw\nBits 31:4 Reserved, must be kept at reset value\nBit 3 IE: Interrupt enable\n0: RNG Interrupt is disabled\n1: RNG Interrupt is enabled. An interrupt is pending as soon as DRDY=1 or SEIS=1 or \nCEIS=1 in the RNG_SR register.\nBit 2 RNGEN: Random number generator enable\n0: Random number generator is disabled\n1: random Number Generator is enabled.\nBits 1:0 Reserved, must be kept at reset value\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSEIS\nCEIS\nReserved\nSECS\nCECS\nDRDY\nrc_w0\nrc_w0\nr\nr\nr\nBits 31:3 Reserved, must be kept at reset value\nBit 6 SEIS: Seed error interrupt status\nThis bit is set at the same time as SECS, it is cleared by writing it to 0.\n0: No faulty sequence detected\n1: One of the following faulty sequences has been detected:\n–\nMore than 64 consecutive bits at the same value (0 or 1)\n–\nMore than 32 consecutive alternances of 0 and 1 (0101010101...01)\nAn interrupt is pending if IE = 1 in the RNG_CR register.\nBit 5 CEIS: Clock error interrupt status\nThis bit is set at the same time as CECS, it is cleared by writing it to 0.\n0: The RNG_CLK clock was correctly detected\n1: The RNG_CLK was not correctly detected (fRNG_CLK< fHCLK/16)\nAn interrupt is pending if IE = 1 in the RNG_CR register.\nBits 4:3 Reserved, must be kept at reset value\n\n\n<>\n\nRM0090 Rev 21\n773/1757\nRM0090\nRandom number generator (RNG)\n774\n24.4.3 \nRNG data register (RNG_DR)\nAddress offset: 0x08\nReset value: 0x0000 0000\nThe RNG_DR register is a read-only register that delivers a 32-bit random value when read. \nAfter being read, this register delivers a new random value after a maximum time of 40 \nperiods of the RNG_CLK clock. The software must check that the DRDY bit is set before \nreading the RNDATA value.\n \n \nBit 2 SECS: Seed error current status\n0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a \nfaulty sequence was detected and the situation has been recovered.\n1: One of the following faulty sequences has been detected:\n–\nMore than 64 consecutive bits at the same value (0 or 1)\n–\nMore than 32 consecutive alternances of 0 and 1 (0101010101...01)\nBit 1 CECS: Clock error current status\n0: The RNG_CLK clock has been correctly detected. If the CEIS bit is set, this means that a \nclock error was detected and the situation has been recovered\n1: The RNG_CLK was not correctly detected (fRNG_CLK< fHCLK/16).\nBit 0 DRDY: Data ready\n0: The RNG_DR register is not yet valid, no random data is available\n1: The RNG_DR register contains valid random data\nNote: An interrupt is pending if IE = 1 in the RNG_CR register.\nOnce the RNG_DR register has been read, this bit returns to 0 until a new valid value is \ncomputed.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nRNDATA\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRNDATA\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 RNDATA: Random data\n32-bit random data.\n\n\n<>\n\nRandom number generator (RNG)\nRM0090\n774/1757\nRM0090 Rev 21\n24.4.4 \nRNG register map\nTable 117 gives the RNG register map and reset values.\n \nTable 117. RNG register map and reset map\nOffset\nRegister \nname\nreset value\nRegister size\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nRNG_CR\n0x0000000\nReserved\nIE\nRNGEN\nReserved\n0x04\nRNG_SR\n0x0000000\nReserved\nSEIS\nCEIS\nReserved\nSECS\nCECS\nDRDY\n0x08\nRNG_DR\n0x0000000\nRNDATA[31:0]\n\n\n<>\n\nRM0090 Rev 21\n775/1757\nRM0090\nHash processor (HASH)\n800\n25 \nHash processor (HASH)\nThis section applies to STM32F415/417xx and STM32F43xxx devices.\n25.1 \nHASH introduction\nThe hash processor is a fully compliant implementation of the secure hash algorithm \n(SHA-1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and \nthe HMAC (keyed-hash message authentication code) algorithm suitable for a variety of \napplications. It computes a message digest (160 bits for the SHA-1 algorithm, 256 bits for \nthe SHA-256 algorithm and 224 bits for the SHA-224 algorithm,128 bits for the MD5 \nalgorithm) for messages of up to (264 – 1) bits, while HMAC algorithms provide a way of \nauthenticating messages by means of hash functions. HMAC algorithms consist in calling \nthe SHA-1, SHA-224, SHA-256 or MD5 hash function twice.\n25.2 \nHASH main features\n•\nSuitable for data authentication applications, compliant with:\n–\nFIPS PUB 180-2 (Federal Information Processing Standards Publication 180-2)\n–\nSecure Hash Standard specifications (SHA-1, SHA-224 and SHA-256) \n–\nIETF RFC 1321 (Internet Engineering Task Force Request For Comments number \n1321) specifications (MD5)\n•\nFast computation of SHA-1, SHA-224 and SHA-256, and MD5 (SHA-224 and SHA-256 \nare available on STM32F43xxx only)\n•\nAHB slave peripheral\n•\n32-bit data words for input data, supporting word, half-word, byte and bit bit-string \nrepresentations, with little-endian data representation only.\n•\nAutomatic swapping to comply with the big-endian SHA1, SHA-224 and SHA-256 \ncomputation standard with little-endian input bit-string representation\n•\nAutomatic padding to complete the input bit string to fit modulo 512 (16 × 32 bits) \nmessage digest computing\n•\n5× 32-bit words (H0 to H5) on STM32F415/417xx and 8 × 32-bit words (H0 to H7) on \nSTM32F43xxx for output message digest, reload able to continue interrupted message \ndigest computation.\n•\nCorresponding 32-bit words of the digest from consecutive message blocks are added \nto each other to form the digest of the whole message\n•\nAutomatic data flow control with support for direct memory access (DMA)\nNote:\nPadding, as defined in the SHA-1, SHA-224 and SHA-256 algorithm, consists in adding a bit \nat bx1 followed by N bits at bx0 to get a total length congruent to 448 modulo 512. After this, \nthe message is completed with a 64-bit integer which is the binary representation of the \noriginal message length.\nFor this hash processor, the quanta for entering the message is a 32-bit word, so an \nadditional information must be provided at the end of the message entry, which is the \nnumber of valid bits in the last 32-bit word entered.\n\n\n<>\n\nHash processor (HASH)\nRM0090\n776/1757\nRM0090 Rev 21\n25.3 \nHASH functional description\nFigure 1 shows the block diagram of the hash processor.\nFigure 233. Block diagram for STM32F415/417xx\n32-bit AHB2 bus\nHash / HMAC\nSHA-1 / MD5\nHASH_DIN\nswa ppin g\n16 × 32-bit\nIN FIFO\nHASH_CR\nHASH_H0...H4\nHASH_CSR0..50\ncontext\ndigest\nHASH_IMR\nHASH_SR\nInterrupt registers\nControl register\nContext swapping\nMessage digest\nprocessor core\nHASH_ST R\nStart register\nIN FIFO full\nwrite into HASH_DIN\nControl and status\nregisters\nData\nregister\nor write DCAL bit to 1\nor 1 complete block\nor DCAL written to 1\nIN buffer\ntransferred by the DMA\nai16081\n\n\n<>\n\nRM0090 Rev 21\n777/1757\nRM0090\nHash processor (HASH)\n800\nFigure 234. Block diagram for STM32F43xxx\nThe FIPS PUB 180-2 standard and the IETF RFC 1321 publication specify the SHA-1, SHA-\n224 and SHA-256 and MD5 secure hash algorithms, respectively, for computing a \ncondensed representation of a message or data file. When a message of any length below \n264 bits is provided on input, the SHA-1, SHA-224 and SHA-256 and MD5 produce \nrespective a 160-bit, 224 bit, 256 bit and 128-bit output string, respectively, called a \nmessage digest. The message digest can then be processed with a digital signature \nalgorithm in order to generate or verify the signature for the message. Signing the message \ndigest rather than the message often improves the efficiency of the process because the \nmessage digest is usually much smaller in size than the message. The verifier of a digital \nsignature has to use the same hash algorithm as the one used by the creator of the digital \nsignature.\nThe SHA-1, SHA-224 and SHA-256 and MD5 are qualified as “secure” because it is \ncomputationally infeasible to find a message that corresponds to a given message digest, or \nto find two different messages that produce the same message digest. Any change to a \nmessage in transit, with very high probability, results in a different message digest, and the \nsignature fails to verify. For more detail on the SHA-1 or SHA-224 and SHA-256 algorithm, \nplease refer to the FIPS PUB 180-2 (Federal Information Processing Standards Publication \n180-2), 2002 august 1.\nThe current implementation of this standard works with little-endian input data convention. \nFor example, the C string “abc” must be represented in memory as the 24-bit hexadecimal \nvalue 0x434241.\nA message or data file to be processed by the hash processor should be considered a bit \nstring. The length of the message is the number of bits in the message (the empty message \n32-bit AHB2 bus\nHash / HMAC\nSHA-1, SHA-224, SHA-256 and MD5\nHASH_DIN\nswa ppin g\n16 × 32-bit\nIN FIFO\nHASH_CR\nHASH_H0...H7\nHASH_CSR0..53\ncontext\ndigest\nHASH_IMR\nHASH_SR\nInterrupt registers\nControl register\nContext swapping\nMessage digest\nprocessor core\nHASH_ST R\nStart register\nIN FIFO full\nwrite into HASH_DIN\nControl and status\nregisters\nData\nregister\nor write DCAL bit to 1\nor 1 complete block\nor DCAL written to 1\nIN buffer\ntransferred by the DMA\nMS30442V1\n\n\n<>\n\nHash processor (HASH)\nRM0090\n778/1757\nRM0090 Rev 21\nhas length 0). You can consider that 32 bits of this bit string forms a 32-bit word. Note that \nthe FIPS PUB 180-1 standard uses the convention that bit strings grow from left to right, and \nbits can be grouped as bytes (8 bits) or words (32 bits) (but some implementations also use \nhalf-words (16 bits), and implicitly, uses the big-endian byte (half-word) ordering. This \nconvention is mainly important for padding (see Section 1.3.4: Message padding on \npage 12).\n25.3.1 \nDuration of the processing\nThe computation of an intermediate block of a message takes:\n•\n66 HCLK clock cycles in SHA-1\n•\n50 HCLK clock cycles in SHA-224\n•\n50 HCLK clock cycles in SHA-256\n•\n50 HCLK clock cycles in MD5\nto which you must add the time needed to load the 16 words of the block into the processor \n(at least 16 clock cycles for a 512-bit block).\nThe time needed to process the last block of a message (or of a key in HMAC) can be \nlonger. This time depends on the length of the last block and the size of the key (in HMAC \nmode). Compared to the processing of an intermediate block, it can be increased by a factor \nof:\n•\n1 to 2.5 for a hash message\n•\naround 2.5 for an HMAC input-key\n•\n1 to 2.5 for an HMAC message\n•\naround 2.5 for an HMAC output key in case of a short key\n•\n3.5 to 5 for an HMAC output key in case of a long key\n25.3.2 \nData type\nData are entered into the hash processor 32 bits (word) at a time, by writing them into the \nHASH_DIN register. But the original bit-string can be organized in bytes, half-words or \nwords, or even be represented as bits. As the system memory organization is little-endian \nand SHA1, SHA-224 and SHA-256 computation is big-endian, depending on the way the \noriginal bit string is grouped, a bit, byte, or half-word swapping operation is performed \nautomatically by the hash processor.\nThe kind of data to be processed is configured with the DATATYPE bitfield in the HASH \ncontrol register (HASH_CR).\n\n\n<>\n\nRM0090 Rev 21\n779/1757\nRM0090\nHash processor (HASH)\n800\nFigure 235. Bit, byte and half-word swapping\nB y t e 3\nB y t e 2\nB y t e 1\nB y t e 0\nbi t s 7 . . . 0\nb i t s 7 .. . 0\nb i t s 7 .. . 0\nbi t s 7 . . . 0\nH A S H_D I N\nbit string organization in\nbi t 0 bi t 1\n bi t 2 9 b i t 3 0 b i t 3 1\nBit s w a p pi n g ope r a t i o n\nb i t- s tr i n g g r o ws\ni n t hi s di rect io n\nas d e f i n e d b y\nFIPS PUB 1 80 - 2 s t d .\nbi t 0\nbi t 1\nbi t 2\nbi t 3 0\nb i t 3 1\nH A S H_D I N\nB y t e s w a p ping ope r a t i o n\nb i t- s tr i n g g r o ws\ni n t hi s di rect io n\nas d e f i n e d b y\nFIPS PUB 1 80 - 2 s t d .\nB y t e 0\nB y t e 1\nB y t e 2\nB y t e 3\nbi t s 7 . . . 0\nb i t s 7 .. . 0\nb i t s 7 .. . 0\nbi t s 7 . . . 0\nHA S H_ D I N\nH a l f - w o r d s w a pping o p er a t io n\nb i t-str in g g r o ws\ni n t h is d i rect i o n\na s d e fi n e d b y\nF I PS PUB 18 0 - 2 s t d .\nHalf-wo r d 0\nbi t s 15 . . . 0\nD A T A TYPE = bx 1 1\nD A T A T YPE = bx 10\nD A T A T YPE = bx 01\nHalf-wo r d 1\nbi t s 15 . . . 0\nHalf-wor d 0\nbi t s 15 .. . 0\nHalf-wor d 1\nbi t s 15 .. . 0\n“1” “0s”\np ad d ing is perfo r m ed\non this side of the\nbit s t ri n g.\nai16082b\nHash processor: Big-Endian\nBits entred with little-Endian format\nA-In case of binary data hash, all bits should be swapped as below \nB-In case of byte data hash, all bytes should be swapped as below \nC-In case of half-word hash, all half-word should be swapped as below \nBytes entred with little-Endian format\nBit string organization in\nHash processor: Big-Endian\nhalf word entred with little-Endian format\nBit string organization in\nHash processor: Big-Endian\n\n\n<>\n\nHash processor (HASH)\nRM0090\n780/1757\nRM0090 Rev 21\nThe least significant bit of the message has to be at position 0 (right) in the first word \nentered into the hash processor, the 32nd bit of the bit string has to be at position 0 in the \nsecond word entered into the hash processor and so on.\n25.3.3 \nMessage digest computing\nThe HASH sequentially processes blocks of 512 bits when computing the message digest. \nThus, each time 16 × 32-bit words (= 512 bits) have been written by the DMA or the CPU, \ninto the hash processor, the HASH automatically starts computing the message digest. This \noperation is known as a partial digest computation.\nThe message to be processed is entered into the peripheral by 32-bit words written into the \nHASH_DIN register. The current contents of the HASH_DIN register are transferred to the \ninput FIFO (IN FIFO) each time the register is written with new data. HASH_DIN and the \ninput FIFO form a FIFO of a 17-word length (named the IN buffer).\nThe processing of a block can start only once the last value of the block has entered the IN \nFIFO. The peripheral must get the information as to whether the HASH_DIN register \ncontains the last bits of the message or not. Two cases may occur:\n•\nWhen the DMA is not used:\n–\nIn case of a partial digest computation, this is done by writing an additional word \ninto the HASH_DIN register (actually the first word of the next block). Then the \nsoftware must wait until the processor is ready again (when DINIS=1) before \nwriting new data into HASH_DIN.\n–\nIn case of a final digest computation (last block entered), this is done by writing the \nDCAL bit to 1.\n•\nWhen the DMA is used:\nThe contents of the HASH_DIN register are interpreted automatically with the \ninformation sent by the DMA controller.\n–\nIn case of a single DMA transfer: Multiple DMA transfer (MDMAT) bit should be \ncleared on STM32F43xxx. When the last block has been transferred to the \nHASH_DIN register via DMA channel, DCAL bit is set to automatically to 1 in the \nHASH_STR register in order to launch the final digest calculation.\n–\nIn case of a multiple DMA transfer (available only on STM32F43xxx): Multiple \nDMA transfer (MDMAT) bit should be set to 1 by software so DCAL bit does not \nget set automatically by HW, in this case the final digest calculation for hash and \nfor each phases for HMAC (for more details about HMAC phases please refer to \nHMAC operation section) is not launched a the end of the DMA transfer request, \nallowing the processor to receive a new DMA transfer. During the last DMA \ntransfer, Multiple DMA transfer (MDMAT) bit should be cleared by software in \norder to set automatically DCAL bit at the end of the last bloc and lunch the final \ndigest.\n–\nThe contents of the HASH_DIN register are interpreted automatically with the \ninformation sent by the DMA controller.\nThis process —data entering + partial digest computation— continues until the last bits of \nthe original message are written to the HASH_DIN register. As the length (number of bits) of \na message can be any integer value, the last word written into the HASH processor may \nhave a valid number of bits between 1 and 32. This number of valid bits in the last word, \nNBLW, has to be written into the HASH_STR register, so that message padding is correctly \nperformed before the final message digest computation.\n\n\n<>\n\nRM0090 Rev 21\n781/1757\nRM0090\nHash processor (HASH)\n800\nOnce this is done, writing into HASH_STR with bit DCAL = 1 starts the processing of the last \nentered block of message by the hash processor. This processing consists in:\n•\nAutomatically performing the message padding operation: the purpose of this operation \nis to make the total length of a padded message a multiple of 512. The HASH \nsequentially processes blocks of 512 bits when computing the message digest\n•\nComputing the final message digest\nWhen the DMA is enabled, it provides the information to the hash processor when it is \ntransferring the last data word. Then the padding and digest computation are performed \nautomatically as if DCAL had been written to 1.\n25.3.4 \nMessage padding\nMessage padding consists in appending a “1” followed by m “0”s followed by a 64-bit integer \nto the end of the original message to produce a padded message block of length 512. The \n“1” is added to the last word written into the HASH_DIN register at the bit position defined by \nthe NBLW bitfield, and the remaining upper bits are cleared (“0”s).\nExample: let us assume that the original message is the ASCII binary-coded form of “abc”, \nof length L = 24:\nbyte 0\nbyte 1\nbyte 2\nbyte 3\n01100001 01100010 01100011 UUUUUUUU\n<-- 1st word written to HASH_DIN --> \nNBLW has to be loaded with the value 24: a “1” is appended at bit location 24 in the bit string \n(starting counting from left to right in the above bit string), which corresponds to bit 31 in the \nHASH_DIN register (little-endian convention):\n01100001 01100010 01100011 1UUUUUUU\nSince L = 24, the number of bits in the above bit string is 25, and 423 “0”s are appended, \nmaking now 448. This gives (in hexadecimal, big-endian format):\n61626380 00000000 00000000 00000000\n00000000 00000000 00000000 00000000\n00000000 00000000 00000000 00000000\n00000000 00000000\nThe L value, in two-word representation (that is 00000000 00000018) is appended. Hence \nthe final padded message in hexadecimal:\n61626380 00000000 00000000 00000000\n00000000 00000000 00000000 00000000\n00000000 00000000 00000000 00000000\n00000000 00000000 00000000 00000028\nIf the HASH is programmed to use the little-endian byte input format, the above message \nhas to be entered by doing the following steps:\n1.\n0xUU636261 is written into the HASH_DIN register (where ‘U’ means don’t care)\n2. \n0x18 is written into the HASH_STR register (the number of valid bits in the last word \nwritten into the HASH_DIN register is 24, as the original message length is 24 bits)\n3. \n0x10 is written into the HASH_STR register to start the message padding and digest \ncomputation. When NBLW ≠ 0x00, the message padding puts a “1” into the HASH_DIN \nregister at the bit position defined by the NBLW value, and inserts “0”s at bit locations \n[31:(NBLW+1)]. When NBLW == 0x00, the message padding inserts one new word with \n\n\n<>\n\nHash processor (HASH)\nRM0090\n782/1757\nRM0090 Rev 21\nvalue 0x0000 0001. Then an all zero word (0x0000 0000) is added and the message \nlength in a two-word representation, to get a block of 16 x 32-bit words.\n4. \nThe HASH computing is performed, and the message digest is then available in the \nHASH_Hx registers (x = 0...4) for the SHA-1 algorithm. For example:\nH0 = 0xA9993E36\nH1 = 0x4706816A\nH2 = 0xBA3E2571\nH3 = 0x7850C26C\nH4 = 0x9CD0D89D\n25.3.5 \nHash operation\nThe hash function (SHA-1, SHA-224, SHA-256 and MD5) is selected when the INIT bit is \nwritten to ‘1’ in the HASH_CR register while the MODE bit is at ‘0’ in HASH_CR. The \nalgorithm (SHA-1, SHA-224,SHA-256 or MD5) is selected at the same time (that is when the \nINIT bit is set) using the ALGO bits.\nThe message can then be sent by writing it word by word into the HASH_DIN register. When \na block of 512 bits —that is 16 words— has been written, a partial digest computation starts \nupon writing the first data of the next block. The hash processor remains busy for 66 cycles \nfor the SHA-1 algorithm, or 50 cycles for the MD5 algorithm, SHA-224 algorithm and SHA-\n256 algorithm.\nThe process can then be repeated until the last word of the message. If DMA transfers are \nused, refer to the Procedure where the data are loaded by DMA section. Otherwise, if the \nmessage length is not an exact multiple of 512 bits, then the HASH_STR register has to be \nwritten to launch the computation of the final digest.\nOnce computed, the digest can be read from the HASH_H0...HASH_H4 registers (for the \nMD5 algorithm, HASH_H4 is not relevant) on STM32F415/417xx, and from the \nHASH_H0...HASH_H7 registers on STM32F43xxx where:\nHASH_H4..HASH_H7 are not relevant when the MD5 algorithm is selected,\nHASH_H5.. HASH_H7 are not relevant when the SHA-1algorithm is selected,\nHASH_H7 is not relevant when the SHA-224 algorithm is selected.\n25.3.6 \nHMAC operation\nThe HMAC algorithm is used for message authentication, by irreversibly binding the \nmessage being processed to a key chosen by the user. For HMAC specifications, refer to \n“HMAC: keyed-hashing for message authentication, H. Krawczyk, M. Bellare, R. Canetti, \nFebruary 1997.\nBasically, the algorithm consists of two nested hash operations:\nHMAC(message) = Hash[((key | pad) XOR 0x5C) \n| Hash(((key | pad) XOR 0x36) | message)]\nwhere:\n•\npad is a sequence of zeroes needed to extend the key to the length of the underlying \nhash function data block (that is 512 bits for both the SHA-1, SHA224, SHA-256 and \nMD5 hash algorithms)\n•\n| represents the concatenation operator\nTo compute the HMAC, four different phases are required:\n\n\n<>\n\nRM0090 Rev 21\n783/1757\nRM0090\nHash processor (HASH)\n800\n1.\nThe block is initialized by writing the INIT bit to ‘1’ with the MODE bit at ‘1’ and the \nALGO bits set to the value corresponding to the desired algorithm. The LKEY bit must \nalso be set during this phase if the key being used is longer than 64 bytes (in this case, \nthe HMAC specifications specify that the hash of the key should be used in place of the \nreal key).\n2. \nThe key (to be used for the inner hash function) is then given to the core. This \noperation follows the same mechanism as the one used to send the message in the \nhash operation (that is, by writing into HASH_DIN and, finally, into HASH_STR).\n3. \nOnce the last word has been entered and computation has started, the hash processor \nelaborates the key. It is then ready to accept the message text using the same \nmechanism as the one used to send the message in the hash operation.\n4. \nAfter the first hash round, the hash processor returns “ready” to indicate that it is ready \nto receive the key to be used for the outer hash function (normally, this key is the same \nas the one used for the inner hash function). When the last word of the key is entered \nand computation starts, the HMAC result is made available in the \nHASH_H0...HASH_H4 registers on STM32F415/417xx and on HASH_H0...HASH_H7 \nregisters on STM32F43xxx. \nNote:\n1\nThe computation latency of the HMAC primitive depends on the lengths of the keys and \nmessage. You could the HMAC as two nested underlying hash functions with the same key \nlength (long or short).\n25.3.7 \nContext swapping\nIt is possible to interrupt a hash/HMAC process to perform another processing with a higher \npriority, and to complete the interrupted process later on, when the higher-priority task is \ncomplete. To do so, the context of the interrupted task must be saved from the hash \nregisters to memory, and then be restored from memory to the hash registers.\nThe procedures where the data flow is controlled by software or by DMA are described \nbelow.\n\n\n<>\n\nHash processor (HASH)\nRM0090\n784/1757\nRM0090 Rev 21\nProcedure where the data are loaded by software\nThe context can be saved only when no block is currently being processed. That is, you \nmust wait for DINIS = 1 (the last block has been processed and the input FIFO is empty) or \nNBW ≠0 (the FIFO is not full and no processing is ongoing).\n•\nContext saving:\nStore the contents of the following registers into memory:\n–\nHASH_IMR\n–\nHASH_STR\n–\nHASH_CR\n–\nHASH_CSR0 to HASH_CSR50 on STM32F415/417xx, and HASH_CSR0 to \nHASH_CSR53 on STM32F43xxx.\n•\nContext restoring:\nThe context can be restored when the high-priority task is complete. Please follow the \norder of the sequence below.\na) \nWrite the following registers with the values saved in memory: HASH_IMR, \nHASH_STR and HASH_CR\nb) \nInitialize the hash processor by setting the INIT bit in the HASH_CR register\nc) \nWrite the HASH_CSR0 to HASH_CSR50 (STM32F415/417xx), and HASH_CSR0 \nto HASH_CSR53 (STM32F43xxx) registers with the values saved in memory\nYou can now restart the processing from the point where it has been interrupted.\nProcedure where the data are loaded by DMA\nIn this case it is not possible to predict if a DMA transfer is in progress or if the process is \nongoing. Thus, you must stop the DMA transfers, then wait until the HASH is ready in order \nto interrupt the processing of a message.\n•\nInterrupting a processing:\n–\nClear the DMAE bit to disable the DMA interface\n–\nWait until the current DMA transfer is complete (wait for DMAES = 0 in the \nHASH_SR register). Note that the block may or not have been totally transferred \nto the HASH.\n–\nDisable the corresponding channel in the DMA controller\n–\nWait until the hash processor is ready (no block is being processed), that is wait \nfor DINIS = 1\n•\nThe context saving and context restoring phases are the same as above (see \nProcedure where the data are loaded by software).\nReconfigure the DMA controller so that it transfers the end of the message. You can now \nrestart the processing from the point where it was interrupted by setting the DMAE bit.\nNote:\nIf context swapping does not involve HMAC operations, the HASH_CSR38 to \nHASH_CSR50 (STM32F415/417xx) and HASH_CSR38 to HASH_CSR53 (STM32F43xxx) \nregisters do not have to be saved and restored.\nIf context swapping occurs between two blocks (the last block was completely processed \nand the next block has not yet been pushed into the IN FIFO, NBW = 000 in the HASH_CR \nregister), the HASH_CSR22 to HASH_CSR37 registers do not have to be saved and \nrestored.\n\n\n<>\n\nRM0090 Rev 21\n785/1757\nRM0090\nHash processor (HASH)\n800\n25.3.8 \nHASH interrupt\nThere are two individual maskable interrupt sources generated by the HASH processor. \nThey are connected to the same interrupt vector.\nYou can enable or disable the interrupt sources individually by changing the mask bits in the \nHASH_IMR register. Setting the appropriate mask bit to 1 enables the interrupt.\nThe status of the individual interrupt sources can be read from the HASH_SR register.\nFigure 236. HASH interrupt mapping diagram\n25.4 \nHASH registers\nThe HASH core is associated with several control and status registers and five message \ndigest registers.\nAll these registers are accessible through word accesses only, else an AHB error is \ngenerated.\n25.4.1 \nHASH control register (HASH_CR) for STM32F415/417xx\nAddress offset: 0x00\nReset value: 0x0000 0000\n \n \nDCIS\nDCIM\nDINIS\nDINIM\nHASH interrupt to NVIC\nai16086\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nLKEY\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDINNE\nNBW\nALGO[0]\nMODE\nDATATYPE\nDMAE\nINIT\nReserved\nr\nr\nr\nr\nr\nrw\nrw\nrw\nrw\nrw\nw\nBits 31:17 Reserved, forced by hardware to 0.\nBit 16 LKEY: Long key selection\nThis bit selects between short key (≤ 64 bytes) or long key (> 64 bytes) in HMAC \nmode\n0: Short key (≤ 64 bytes)\n1: Long key (> 64 bytes)\nNote: This selection is only taken into account when the INIT bit is set and MODE \n= 1. Changing this bit during a computation has no effect.\nBits 15:13 Reserved, forced by hardware to 0.\n\n\n<>\n\nHash processor (HASH)\nRM0090\n786/1757\nRM0090 Rev 21\nBit 12 DINNE: DIN not empty\nThis bit is set when the HASH_DIN register holds valid data (that is after being \nwritten at least once). It is cleared when either the INIT bit (initialization) or the \nDCAL bit (completion of the previous message processing) is written to 1.\n0: No data are present in the data input buffer\n1: The input buffer contains at least one word of data\nBits 11:8 NBW: Number of words already pushed\nThis bitfield reflects the number of words in the message that have already been \npushed into the IN FIFO.\nNBW increments (+1) when a write access is performed to the HASH_DIN \nregister while DINNE = 1.\nIt goes to 0000 when the INIT bit is written to 1 or when a digest calculation \nstarts (DCAL written to 1 or DMA end of transfer).\n″\nIf the DMA is not used:\n0000 and DINNE=0: no word has been pushed into the DIN buffer (the buffer is \nempty, both the HASH_DIN register and the IN FIFO are empty)\n0000 and DINNE=1: 1 word has been pushed into the DIN buffer (The \nHASH_DIN register contains 1 word, the IN FIFO is empty)\n0001: 2 words have been pushed into the DIN buffer (the HASH_DIN register \nand the IN FIFO contain 1 word each)\n...\n1111: 16 words have been pushed into the DIN buffer\n″\nIf the DMA is used, NBW is the exact number of words that have been \npushed into the IN FIFO.\nBit 7 ALGO[1:0]: Algorithm selection\nThese bits selects the SHA-1 or the MD5 algorithm:\n0: SHA-1 algorithm selected\n1: MD5 algorithm selected\nNote: This selection is only taken into account when the INIT bit is set. Changing \nthis bit during a computation has no effect.\nBit 6 MODE: Mode selection\nThis bit selects the HASH or HMAC mode for the selected algorithm:\n0: Hash mode selected\n1: HMAC mode selected. LKEY must be set if the key being used is longer than \n64 bytes.\nNote: This selection is only taken into account when the INIT bit is set. Changing \nthis bit during a computation has no effect.\nBits 5:4 DATATYPE: Data type selection\nDefines the format of the data entered into the HASH_DIN register:\n00: 32-bit data. The data written into HASH_DIN are directly used by the HASH \nprocessing, without reordering.\n01: 16-bit data, or half-word. The data written into HASH_DIN are considered as \n2 half-words, and are swapped before being used by the HASH processing.\n10: 8-bit data, or bytes. The data written into HASH_DIN are considered as 4 \nbytes, and are swapped before being used by the HASH processing.\n11: bit data, or bit-string. The data written into HASH_DIN are considered as 32 \nbits (1st bit of the sting at position 0), and are swapped before being used by the \nHASH processing (1st bit of the string at position 31).\n\n\n<>\n\nRM0090 Rev 21\n787/1757\nRM0090\nHash processor (HASH)\n800\nBit 3 DMAE: DMA enable\n0: DMA transfers disabled\n1: DMA transfers enabled. A DMA request is sent as soon as the HASH core is \nready to receive data.\nNote: 1: This bit is cleared by hardware when the DMA asserts the DMA terminal \ncount signal (while transferring the last data of the message). This bit is not \ncleared when the INIT bit is written to 1.\n2: If this bit is written to 0 while a DMA transfer has already been requested \nto the DMA, DMAE is cleared but the current transfer is not aborted. \nInstead, the DMA interface remains internally enabled until the transfer is \ncomplete or INIT is written to 1.\nBit 2 INIT: Initialize message digest calculation\nWriting this bit to 1 resets the hash processor core, so that the HASH is ready to \ncompute the message digest of a new message.\nWriting this bit to 0 has no effect.\nReading this bit always return 0.\nBits 1:0 Reserved, must be kept cleared.\n\n\n<>\n\nHash processor (HASH)\nRM0090\n788/1757\nRM0090 Rev 21\n25.4.2 \nHASH control register (HASH_CR) for STM32F43xxx\nAddress offset: 0x00\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nALGO[1]\nReserved\nLKEY\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMDMAT\nDINNE\nNBW\nALGO[0]\nMODE\nDATATYPE\nDMAE\nINIT\nReserved\nrw\nr\nr\nr\nr\nr\nrw\nrw\nrw\nrw\nrw\nw\nBits 31:19 Reserved, forced by hardware to 0.\nBit 17 Reserved, forced by hardware to 0.\nBit 16 LKEY: Long key selection\nThis bit selects between short key (≤ 64 bytes) or long key (> 64 bytes) in HMAC \nmode\n0: Short key (≤ 64 bytes)\n1: Long key (> 64 bytes)\nNote: This selection is only taken into account when the INIT bit is set and MODE \n= 1. Changing this bit during a computation has no effect.\nBits 15:14 Reserved, forced by hardware to 0.\nBit 13 MDMAT: Multiple DMA Transfers \nThis bit is set when hashing large files when multiple DMA transfers are needed. \n0: DCAL is automatically set at the end of a DMA transfer.\n1: DCAL is not automatically set at the end of a DMA transfer.\nBit 12 DINNE: DIN not empty\nThis bit is set when the HASH_DIN register holds valid data (that is after being \nwritten at least once). It is cleared when either the INIT bit (initialization) or the \nDCAL bit (completion of the previous message processing) is written to 1.\n0: No data are present in the data input buffer\n1: The input buffer contains at least one word of data\n\n\n<>\n\nRM0090 Rev 21\n789/1757\nRM0090\nHash processor (HASH)\n800\nBits 11:8 NBW: Number of words already pushed\nThis bitfield reflects the number of words in the message that have already been \npushed into the IN FIFO.\nNBW increments (+1) when a write access is performed to the HASH_DIN \nregister while DINNE = 1.\nIt goes to 0000 when the INIT bit is written to 1 or when a digest calculation \nstarts (DCAL written to 1 or DMA end of transfer).\n″\nIf the DMA is not used:\n0000 and DINNE=0: no word has been pushed into the DIN buffer (the buffer is \nempty, both the HASH_DIN register and the IN FIFO are empty)\n0000 and DINNE=1: 1 word has been pushed into the DIN buffer (The \nHASH_DIN register contains 1 word, the IN FIFO is empty)\n0001: 2 words have been pushed into the DIN buffer (the HASH_DIN register \nand the IN FIFO contain 1 word each)\n...\n1111: 16 words have been pushed into the DIN buffer\n″\nIf the DMA is used, NBW is the exact number of words that have been \npushed into the IN FIFO.\nBit 18 and bit 7 ALGO[1:0]: Algorithm selection\nThese bits selects the SHA-1, SHA-224, SHA256 or the MD5 algorithm:\n00: SHA-1 algorithm selected\n01: MD5 algorithm selected\n10: SHA224 algorithm selected\n11: SHA256 algorithm selected\nNote: This selection is only taken into account when the INIT bit is set. Changing \nthis bit during a computation has no effect.\nBit 6 MODE: Mode selection\nThis bit selects the HASH or HMAC mode for the selected algorithm:\n0: Hash mode selected\n1: HMAC mode selected. LKEY must be set if the key being used is longer than \n64 bytes.\nNote: This selection is only taken into account when the INIT bit is set. Changing \nthis bit during a computation has no effect.\nBits 5:4 DATATYPE: Data type selection\nDefines the format of the data entered into the HASH_DIN register:\n00: 32-bit data. The data written into HASH_DIN are directly used by the HASH \nprocessing, without reordering.\n01: 16-bit data, or half-word. The data written into HASH_DIN are considered as \n2 half-words, and are swapped before being used by the HASH processing.\n10: 8-bit data, or bytes. The data written into HASH_DIN are considered as 4 \nbytes, and are swapped before being used by the HASH processing.\n11: bit data, or bit-string. The data written into HASH_DIN are considered as 32 \nbits (1st bit of the sting at position 0), and are swapped before being used by the \nHASH processing (1st bit of the string at position 31).\n\n\n<>\n\nHash processor (HASH)\nRM0090\n790/1757\nRM0090 Rev 21\nBit 3 DMAE: DMA enable\n0: DMA transfers disabled\n1: DMA transfers enabled. A DMA request is sent as soon as the HASH core is \nready to receive data.\nNote: 1: This bit is cleared by hardware when the DMA asserts the DMA terminal \ncount signal (while transferring the last data of the message). This bit is not \ncleared when the INIT bit is written to 1.\n2: If this bit is written to 0 while a DMA transfer has already been requested \nto the DMA, DMAE is cleared but the current transfer is not aborted. \nInstead, the DMA interface remains internally enabled until the transfer is \ncomplete or INIT is written to 1.\nBit 2 INIT: Initialize message digest calculation\nWriting this bit to 1 resets the hash processor core, so that the HASH is ready to \ncompute the message digest of a new message.\nWriting this bit to 0 has no effect.\nReading this bit always return 0.\nBits 1:0 Reserved, must be kept cleared.\n\n\n<>\n\nRM0090 Rev 21\n791/1757\nRM0090\nHash processor (HASH)\n800\n25.4.3 \nHASH data input register (HASH_DIN)\nAddress offset: 0x04\nReset value: 0x0000 0000\nHASH_DIN is the data input register. It is 32-bit wide. It is used to enter the message by \nblocks of 512 bits. When the HASH_DIN register is written to, the value presented on the \nAHB databus is ‘pushed’ into the HASH core and the register takes the new value presented \non the AHB databus. The DATATYPE bits must previously have been configured in the \nHASH_CR register to get a correct message representation.\nWhen a block of 16 words has been written to the HASH_DIN register, an intermediate \ndigest calculation is launched:\n•\nby writing new data into the HASH_DIN register (the first word of the next block) if the \nDMA is not used (intermediate digest calculation)\n•\nautomatically if the DMA is used\nWhen the last block has been written to the HASH_DIN register, the final digest calculation \n(including padding) is launched:\n•\nby writing the DCAL bit to 1 in the HASH_STR register (final digest calculation)\n•\nautomatically if the DMA is used and MDMAT bit is set to ‘0’.\nWhen a digest calculation (intermediate or final) is in progress, any new write access to the \nHASH_DIN register is extended (by wait-state insertion on the AHB bus) until the HASH \ncalculation completes.\nWhen the HASH_DIN register is read, the last word written in this location is accessed (zero \nafter reset).\n .\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATAIN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATAIN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 DATAIN: Data input\nRead = returns the current register content.\nWrite = the current register content is pushed into the IN FIFO, and the register \ntakes the new value presented on the AHB databus.\n\n\n<>\n\nHash processor (HASH)\nRM0090\n792/1757\nRM0090 Rev 21\n25.4.4 \nHASH start register (HASH_STR)\nAddress offset: 0x08\nReset value: 0x0000 0000\nThe HASH_STR register has two functions:\n•\nIt is used to define the number of valid bits in the last word of the message entered in \nthe hash processor (that is the number of valid least significant bits in the last data \nwritten into the HASH_DIN register)\n•\nIt is used to start the processing of the last block in the message by writing the DCAL \nbit to 1\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDCAL\nReserved\nNBLW\nw\nrw\nrw\nrw\nrw\nrw\nBits 31:9 Reserved, forced by hardware to 0.\nBit 8 DCAL: Digest calculation\nWriting this bit to 1 starts the message padding, using the previously written \nvalue of NBLW, and starts the calculation of the final message digest with all data \nwords written to the IN FIFO since the INIT bit was last written to 1.\nReading this bit returns 0.\nNote \nBits 7:5 Reserved, forced by hardware to 0.\nBits 4:0 NBLW: Number of valid bits in the last word of the message in the bit string \norganization of hash processor \nWhen these bits are written and DCAL is at ‘0’, they take the value on the AHB \ndatabus:\n0x00: All 32 bits of the last data written in the bit string organization of hash \nprocessor (after data swapping) are valid.\n0x01: Only bit [31] of the last data written in the bit string organization of hash \nprocessor (after data swapping) are valid\n0x02: Only bits [31:30] of the last data written in the bit string organization of \nhash processor (after data swapping) are valid\n0x03: Only bits [31:29] of the last data written in the bit string organization of \nhash processor (after data swapping) are valid\n...\n0x1F: Only bits [0] of the last data written in the bit string organization of hash \nprocessor (after data swapping) are valid\nWhen these bits are written and DCAL is at ‘1’, the bitfield is not changed.\nReading them returns the last value written to NBLW.\nNote: These bits must be configured before setting the DCAL bit, else they are not \ntaken into account. Especially, it is not possible to configure NBLW and set \nDCAL at the same time.\n\n\n<>\n\nRM0090 Rev 21\n793/1757\nRM0090\nHash processor (HASH)\n800\n25.4.5 \nHASH digest registers (HASH_HR0..4/5/6/7)\nAddress offset: 0x0C to 0x1C (STM32F415/417xx), plus 0x310 to 0x32C (STM32F43xxx)\nReset value: 0x0000 0000\nThese registers contain the message digest result named as:\n1.\nH0, H1, H2, H3 and H4, respectively, in the SHA1 algorithm description\nNote that in this case, the HASH_H5 to HASH_H7 register is not used, and is read as \nzero.\n2. \nA, B, C and D, respectively, in the MD5 algorithm description\nNote that in this case, the HASH_H4 to HASH_H7 register is not used, and is read as \nzero.\n3. \nH0 to H6, respectively, in the SHA224 algorithm description,\nNote that in this case, the HASH_H7 register is not used, and is read as zero.\n4. \nH0 to H7, respectively, in the SHA256 algorithm description,\nIf a read access to one of these registers occurs while the HASH core is calculating an \nintermediate digest or a final message digest (that is when the DCAL bit has been written to \n1), then the read is stalled until the completion of the HASH calculation.\nNote:\nH0, H1, H2, H3 and H4 mapping are duplicated in two region.\nHASH_HR0\nAddress offset: 0x0C and 0x310\n \nHASH_HR1\nAddress offset: 0x10 and 0x314\n \nHASH_HR2\nAddress offset: 0x14 and 0x318\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nH0\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nH0\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nH1\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nH1\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nH2\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n\n\n<>\n\nHash processor (HASH)\nRM0090\n794/1757\nRM0090 Rev 21\nHASH_HR3\nAddress offset: 0x18 and 0x31C\n \nHASH_HR4\nAddress offset: 0x1C and 0x320\n \nHASH_HR5\nAddress offset: 0x324\n \nHASH_HR6\nAddress offset: 0x328\n \nHASH_HR7\nAddress offset: 0x32C\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nH2\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nH3\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nH3\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nH4\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nH4\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nH5\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nH5\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nH6\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nH6\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n\n\n<>\n\nRM0090 Rev 21\n795/1757\nRM0090\nHash processor (HASH)\n800\n \nNote:\nWhen starting a digest computation for a new bit stream (by writing the INIT bit to 1), these \nregisters assume their reset values.\n25.4.6 \nHASH interrupt enable register (HASH_IMR)\nAddress offset: 0x20\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nH7\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nH7\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDCIE\nDINIE\nrw\nrw\nBits 31:2 Reserved, forced by hardware to 0.\nBit 1 DCIE: Digest calculation completion interrupt enable\n0: Digest calculation completion interrupt disabled\n1: Digest calculation completion interrupt enabled.\nBit 0 DINIE: Data input interrupt enable\n0: Data input interrupt disabled\n1: Data input interrupt enabled\n\n\n<>\n\nHash processor (HASH)\nRM0090\n796/1757\nRM0090 Rev 21\n25.4.7 \nHASH status register (HASH_SR)\nAddress offset: 0x24\nReset value: 0x0000 0001\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBUSY\nDMAS\nDCIS\nDINIS\nr\nr\nrc_w0\nrc_w0\nBits 31:4 Reserved, forced by hardware to 0.\nBit 3 BUSY: Busy bit\n0: No block is currently being processed\n1: The hash core is processing a block of data\nBit 2 DMAS: DMA Status\nThis bit provides information on the DMA interface activity. It is set with DMAE \nand cleared when DMAE=0 and no DMA transfer is ongoing. No interrupt is \nassociated with this bit.\n0: DMA interface is disabled (DMAE=0) and no transfer is ongoing\n1: DMA interface is enabled (DMAE=1) or a transfer is ongoing\nBit 1 DCIS: Digest calculation completion interrupt status\nThis bit is set by hardware when a digest becomes ready (the whole message \nhas been processed). It is cleared by writing it to 0 or by writing the INIT bit to 1 \nin the HASH_CR register.\n0: No digest available in the HASH_Hx registers\n1: Digest calculation complete, a digest is available in the HASH_Hx registers. \nAn interrupt is generated if the DCIE bit is set in the HASH_IMR register.\nBit 0 DINIS: Data input interrupt status\nThis bit is set by hardware when the input buffer is ready to get a new block (16 \nlocations are free). It is cleared by writing it to 0 or by writing the HASH_DIN \nregister.\n0: Less than 16 locations are free in the input buffer\n1: A new block can be entered into the input buffer. An interrupt is generated if \nthe DINIE bit is set in the HASH_IMR register.\n\n\n<>\n\nRM0090 Rev 21\n797/1757\nRM0090\nHash processor (HASH)\n800\n25.4.8 \nHASH context swap registers (HASH_CSRx)\nAddress offset: 0x0F8 to 0x1C0\n•\nFor HASH_CSR0 register: Reset value is 0x0000 0002.\n•\nFor others registers: Reset value is 0x0000 0000 , except for STM32F43xxx devices \nwhere the HASH_CSR2 register reset value is 0x2000 0000\nAdditional registers are available from 0x1C1 to 0x1CC on STM32F43xxx:\n•\nReset value: 0x0000 0000.\nThese registers contain the complete internal register states of the hash processor, and are \nuseful when a context swap has to be done because a high-priority task has to use the hash \nprocessor while it is already in use by another task.\nWhen such an event occurs, the HASH_CSRx registers have to be read and the read \nvalues have to be saved somewhere in the system memory space. Then the hash \nprocessor can be used by the preemptive task, and when hash computation is finished, the \nsaved context can be read from memory and written back into these HASH_CSRx registers.\nHASH_CSRx\nAddress offset: 0x0F8 to 0x1C0 on STM32F415/417xx \nAddress offset: 0x0F8 to 0x1CC on STM32F43xxx\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCSx\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCSx\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nHash processor (HASH)\nRM0090\n798/1757\nRM0090 Rev 21\n25.4.9 \nHASH register map\nTable 9 gives the summary HASH register map and reset values.\n \nTable 118. HASH register map and reset values on STM32F415/417xx\nOffset\nRegister name\nreset value\nRegister size\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nHASH_CR\nReserved\nLKEY\nReserved\nDINNE\nNBW\nALGO[0]\nMODE\nDATATYPE\nDMAE\nINIT\nReserved\nReset value\n0\n0 0 0 0 0 0 0 0 0 0 0\n0x04\nHASH_DIN\nDATAIN\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x08\nHASH_STR\nReserved\nDCAL\nReserved\nNBLW\nReset value\n0\n0 0 0 0 0\n0x0C \nHASH_HR0\nH0\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x10 \nHASH_HR1\nH1\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x14 \nHASH_HR2\nH2\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x18\nHASH_HR3\nH3\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x1C\nHASH_HR4\nH4\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x20\nHASH_IMR\nReserved\nDCIE\nDINIE\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x24\nHASH_SR\nReserved\nBUSY\nDMAS\nDCIS\nDINIS\nReset value\n0 0 0 1\n0xF8\nHASH_CSR0\nCSR0\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0\n...\n...\n0x1C0 HASH_CSR50\nCSR50\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nReserved\n0x310\nHASH_HR0\nH0\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x314\nHASH_HR1\nH1\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n\n\n<>\n\nRM0090 Rev 21\n799/1757\nRM0090\nHash processor (HASH)\n800\n0x318\nHASH_HR2\nH2\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x31C\nHASH_HR3\nH3\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x320\nHASH_HR4\nH4\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nTable 119. HASH register map and reset values on STM32F43xxx\nOffset\nRegister name\nreset value\nRegister size\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nHASH_CR\nReserved\nALGO[1]\nReserved\nLKEY\nReserved\nMDMAT\nDINNE\nNBW\nALGO[0]\nMODE\nDATATYPE\nDMAE\nINIT\nReserved\nReset value\n0\n0\n0 0 0 0 0 0 0 0 0 0 0 0\n0x04\nHASH_DIN\nDATAIN\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x08\nHASH_STR\nReserved\nDCAL\nReserved\nNBLW\nReset value\n0\n0 0 0 0 0\n0x0C \nHASH_HR0\nH0\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x10 \nHASH_HR1\nH1\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x14 \nHASH_HR2\nH2\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x18\nHASH_HR3\nH3\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x1C\nHASH_HR4\nH4\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x20\nHASH_IMR\nReserved\nDCIE\nDINIE\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x24\nHASH_SR\nReserved\nBUSY\nDMAS\nDCIS\nDINIS\nReset value\n0 0 0 1\nTable 118. HASH register map and reset values on STM32F415/417xx (continued)\nOffset\nRegister name\nreset value\nRegister size\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nHash processor (HASH)\nRM0090\n800/1757\nRM0090 Rev 21\n0xF8\nHASH_CSR0\nCSR0\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0\n...\n...\n0x1CC\nHASH_CSR53\nCSR53\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nReserved\n0x310\nHASH_HR0\nH0\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x314\nHASH_HR1\nH1\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x318\nHASH_HR2\nH2\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x31C\nHASH_HR3\nH3\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x320\nHASH_HR4\nH4\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x324\nHASH_HR5\nH5\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x328\nHASH_HR6\nH6\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x32C\nHASH_HR7\nH7\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nTable 119. HASH register map and reset values on STM32F43xxx (continued)\nOffset\nRegister name\nreset value\nRegister size\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n801/1757\nRM0090\nReal-time clock (RTC)\n841\n26 \nReal-time clock (RTC)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n26.1 \nIntroduction\nThe real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-\nof-day clock/calendar, two programmable alarm interrupts, and a periodic programmable \nwake-up flag with interrupt capability. The RTC also includes an automatic wake-up unit to \nmanage low-power modes.\nTwo 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day \nof week), date (day of month), month, and year, expressed in binary coded decimal format \n(BCD). The sub-seconds value is also available in binary format.\nCompensations for 28-, 29- (leap year), 30-, and 31-day months are performed \nautomatically. Daylight saving time compensation can also be performed. \nAdditional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, \nhours, day, and date.\nA digital calibration feature is available to compensate for any deviation in crystal oscillator \naccuracy.\nAfter backup domain reset, all RTC registers are protected against possible parasitic write \naccesses.\nAs long as the supply voltage remains in the operating range, the RTC never stops, \nregardless of the device status (Run mode, low-power mode or under reset).\n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n802/1757\nRM0090 Rev 21\n26.2 \nRTC main features\nThe RTC unit main features are the following (see Figure 237: RTC block diagram):\n•\nCalendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of \nweek), date (day of month), month, and year.\n•\nDaylight saving compensation programmable by software.\n•\nTwo programmable alarms with interrupt function. The alarms can be triggered by any \ncombination of the calendar fields.\n•\nAutomatic wake-up unit generating a periodic flag that triggers an automatic wake-up \ninterrupt.\n•\nReference clock detection: a more precise second source clock (50 or 60 Hz) can be \nused to enhance the calendar precision.\n•\nAccurate synchronization with an external clock using the subsecond shift feature.\n•\nMaskable interrupts/events:\n–\nAlarm A\n–\nAlarm B\n–\nWake-up interrupt\n–\nTimestamp\n–\nTamper detection\n•\nDigital calibration circuit (periodic counter correction) \n–\n5 ppm accuracy \n–\n0.95 ppm accuracy, obtained in a calibration window of several seconds\n•\nTimestamp function for event saving (1 event)\n•\nTamper detection:\n–\n2 tamper events with configurable filter and internal pull-up.\n•\n20 backup registers (80 bytes). The backup registers are reset when a tamper \ndetection event occurs.\n•\nAlternate function output (RTC_OUT) which selects one of the following two outputs: \n–\nRTC_CALIB: 512 Hz or 1 Hz clock output (with an LSE frequency of 32.768 kHz).\nThis output is enabled by setting the COE bit in the RTC_CR register. It is routed \nto the device RTC_AF1 function. \n–\nRTC_ALARM (Alarm A, Alarm B or wake-up). \nThis output is selected by configuring the OSEL[1:0] bits in the RTC_CR register. \nIt is routed to the device RTC_AF1 function.\n•\nRTC alternate function inputs:\n–\nRTC_TS: timestamp event detection. It is routed to the device RTC_AF1 and \nRTC_AF2 functions. \n–\nRTC_TAMP1: TAMPER1 event detection. It is routed to the device RTC_AF1 and \nRTC_AF2 functions. \n–\nRTC_TAMP2: TAMPER2 event detection. \n–\nRTC_REFIN: reference clock input (usually the mains, 50 or 60 Hz).\nRefer to Section 8.3.15: Selection of RTC_AF1 and RTC_AF2 alternate functions. \n\n\n<>\n\nRM0090 Rev 21\n803/1757\nRM0090\nReal-time clock (RTC)\n841\nFigure 237. RTC block diagram \n1.\nOn STM32F4xx devices, the RTC_AF1 and RTC_AF2 alternate functions are connected to PC13 and PI8, \nrespectively.\nMS30216V7\nCalendar\nRTC_ALARM\nRTCCLK\nDivided HSE\nLSE (32.768 Hz)\nLSI\nSynchronous \n15-bit prescaler \n(default = 256)\nALRAF\nRTC_PRER\nBackup registers \nand RTC tamper \ncontrol register\nTAMPxF\nTime stamp \nregisters\nTSF\nOutput \ncontrol\nRTC_OUT\ncalibration\nRTC_TAMP2\n=\nSmooth\nck_spre\n(default 1 Hz)\nRTC_REFIN\nRTC_TAMP1\nRTC_TS\nAsynchronous \n7-bit prescaler \n(default = 128)\nRTC_PRER\nRTC_CALR\nShadow registers \nRTC_TR,\nRTC_DR\nAlarm A\nRTC_ALRMAR\nRTC_ALRMASSR \nck_apre\n(default 256 Hz\nRTC_CALIB\nShadow register \nRTC_SSR\nAlarm B\n=\nALRBF\nWUCKSEL[1:0]\nPrescaler\n1, 2, 4, 8, 16\n16-bit wakeup\nauto reload timer\nRTC_WUTR\nRTC_TAMP3\nWUTF\nOSEL[1:0]\nRTC_ALRMBR\nRTC_ALRMBSSR \n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n804/1757\nRM0090 Rev 21\n26.3 \nRTC functional description\n26.3.1 \nClock and prescalers\nThe RTC clock source (RTCCLK) is selected through the clock controller among the LSE \nclock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock \nsource configuration, refer to Section 7: Reset and clock control for STM32F405xx/07xx \nand STM32F415xx/17xx(RCC) and Section 6: Reset and clock control for STM32F42xxx \nand STM32F43xxx (RCC).\nA programmable prescaler stage generates a 1 Hz clock which is used to update the \ncalendar. To minimize power consumption, the prescaler is split into 2 programmable \nprescalers (see Figure 237: RTC block diagram):\n•\nA 7-bit asynchronous prescaler configured through the PREDIV_A bits of the \nRTC_PRER register. \n•\n A 15-bit synchronous prescaler configured through the PREDIV_S bits of the \nRTC_PRER register. \nNote:\nWhen both prescalers are used, it is recommended to configure the asynchronous prescaler \nto a high value to minimize consumption.\nThe asynchronous prescaler division factor is set to 128, and the synchronous division \nfactor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency \nof 32.768 kHz. \nThe minimum division factor is 1 and the maximum division factor is 222. \nThis corresponds to a maximum input frequency of around 4 MHz. \nfck_apre is given by the following formula:\nThe ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it \nreaches 0, RTC_SSR is reloaded with the content of PREDIV_S. \nfck_spre is given by the following formula:\nThe ck_spre clock can be used either to update the calendar or as timebase for the 16-bit \nwake-up auto-reload timer. To obtain short timeout periods, the 16-bit wake-up auto-reload \ntimer can also run with the RTCCLK divided by the programmable 4-bit asynchronous \nprescaler (see Section 26.3.4: Periodic auto-wakeup for details).\nfCK_APRE\nfRTCCLK\nPREDIV_A\n1\n+\n--------------------------------------\n=\nfCK_SPRE\nfRTCCLK\nPREDIV_S\n1\n+\n(\n)\nPREDIV_A\n1\n+\n(\n)\n×\n-----------------------------------------------------------------------------------------------\n=\n\n\n<>\n\nRM0090 Rev 21\n805/1757\nRM0090\nReal-time clock (RTC)\n841\n26.3.2 \nReal-time clock and calendar\nThe RTC calendar time and date registers are accessed through shadow registers which \nare synchronized with PCLK1 (APB1 clock). They can also be accessed directly in order to \navoid waiting for the synchronization duration.\n•\nRTC_SSR for the subseconds \n•\nRTC_TR for the time\n•\nRTC_DR for the date\nEvery two RTCCLK periods, the current calendar value is copied into the shadow registers, \nand the RSF bit of RTC_ISR register is set (see Section 26.6.4). The copy is not performed \nin Stop and Standby mode. When exiting these modes, the shadow registers are updated \nafter up to 2 RTCCLK periods.\nWhen the application reads the calendar registers, it accesses the content of the shadow \nregisters.t is possible to make a direct access to the calendar registers by setting the \nBYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user \naccesses the shadow registers.\nWhen reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD=0 mode, the \nfrequency of the APB clock (fAPB) must be at least 7 times the frequency of the RTC clock \n(fRTCCLK).\nThe shadow registers are reset by system reset. \n26.3.3 \nProgrammable alarms\nThe RTC unit provides two programmable alarms, Alarm A and Alarm B.\nThe programmable alarm functions are enabled through the ALRAIE and ALRBIE bits in the \nRTC_CR register. The ALRAF and ALRBF flags are set to 1 if the calendar subseconds, \nseconds, minutes, hours, date or day match the values programmed in the alarm registers \nRTC_ALRMASSR/RTC_ALRMAR and RTC_ALRMBSSR/RTC_ALRMBR, respectively. \nEach calendar field can be independently selected through the MSKx bits of the \nRTC_ALRMAR and RTC_ALRMBR registers, and through the MASKSSx bits of the \nRTC_ALRMASSR and RTC_ALRMBSSR registers. The alarm interrupts are enabled \nthrough the ALRAIE and ALRBIE bits in the RTC_CR register.\nAlarm A and Alarm B (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the \nRTC_ALARM output. RTC_ALARM polarity can be configured through bit POL in the \nRTC_CR register.\nCaution:\nIf the seconds field is selected (MSK0 bit reset in RTC_ALRMAR or RTC_ALRMBR), the \nsynchronous prescaler division factor set in the RTC_PRER register must be at least 3 to \nensure correct behavior.\n26.3.4 \nPeriodic auto-wakeup \nThe periodic wake-up flag is generated by a 16-bit programmable auto-reload down-\ncounter. The wake-up timer range can be extended to 17 bits.\nThe wake-up function is enabled through the WUTE bit in the RTC_CR register.\n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n806/1757\nRM0090 Rev 21\nThe wake-up timer clock input can be:\n•\nRTC clock (RTCCLK) divided by 2, 4, 8, or 16.\nWhen RTCCLK is LSE(32.768kHz), this allows configuring the wake-up interrupt period \nfrom 122 µs to 32 s, with a resolution down to 61µs.\n•\nck_spre (usually 1 Hz internal clock)\nWhen ck_spre frequency is 1Hz, this allows achieving a wake-up time from 1 s to \naround 36 hours with one-second resolution. This large programmable time range is \ndivided in 2 parts:\n–\nfrom 1s to 18 hours when WUCKSEL [2:1] = 10\n–\nand from around 18h to 36h when WUCKSEL[2:1] = 11. In this last case 216 is \nadded to the 16-bit counter current value.When the initialization sequence is \ncomplete (see Programming the wake-up timer on page 808), the timer starts \ncounting down.When the wake-up function is enabled, the down-counting remains \nactive in low-power modes. In addition, when it reaches 0, the WUTF flag is set in \nthe RTC_ISR register, and the wake-up counter is automatically reloaded with its \nreload value (RTC_WUTR register value).\nThe WUTF flag must then be cleared by software.\nWhen the periodic wake-up interrupt is enabled by setting the WUTIE bit in the RTC_CR2 \nregister, it can exit the device from low-power modes.\nThe periodic wake-up flag can be routed to the RTC_ALARM output provided it has been \nenabled through bits OSEL[1:0] of RTC_CR register. RTC_ALARM polarity can be \nconfigured through the POL bit in the RTC_CR register.\nSystem reset, as well as low-power modes (Sleep, Stop and Standby) have no influence on \nthe wake-up timer.\n26.3.5 \nRTC initialization and configuration\nRTC register access\nThe RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC \nregister accesses except on read accesses to calendar shadow registers when \nBYPSHAD=0.\nRTC register write protection\nAfter system reset, the RTC registers are protected against parasitic write access with the \nDBP bit of the PWR power control register (PWR_CR). The DBP bit must be set to enable \nRTC registers write access.\nAfter backup domain reset, all the RTC registers are write-protected. Writing to the RTC \nregisters is enabled by writing a key into the Write Protection register, RTC_WPR.\nThe following steps are required to unlock the write protection on all the RTC registers \nexcept for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR.\n1.\nWrite ‘0xCA’ into the RTC_WPR register.\n2. \nWrite ‘0x53’ into the RTC_WPR register.\nWriting a wrong key reactivates the write protection.\nThe protection mechanism is not affected by system reset.\n\n\n<>\n\nRM0090 Rev 21\n807/1757\nRM0090\nReal-time clock (RTC)\n841\nCalendar initialization and configuration\nTo program the initial time and date calendar values, including the time format and the \nprescaler configuration, the following sequence is required:\n1.\nSet INIT bit to 1 in the RTC_ISR register to enter initialization mode. In this mode, the \ncalendar counter is stopped and its value can be updated.\n2. \nPoll INITF bit of in the RTC_ISR register. The initialization phase mode is entered when \nINITF is set to 1. It takes from 1 to 2 RTCCLK clock cycles (due to clock \nsynchronization). \n3. \nTo generate a 1 Hz clock for the calendar counter, program first the synchronous \nprescaler factor in RTC_PRER register, and then program the asynchronous prescaler \nfactor. Even if only one of the two fields needs to be changed, 2 separate write \naccesses must be performed to the RTC_PRER register.\n4. \nLoad the initial time and date values in the shadow registers (RTC_TR and RTC_DR), \nand configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR \nregister.\n5. \nExit the initialization mode by clearing the INIT bit. The actual calendar counter value is \nthen automatically loaded and the counting restarts after 4 RTCCLK clock cycles.\nWhen the initialization sequence is complete, the calendar starts counting.\nNote:\nAfter a system reset, the application can read the INITS flag in the RTC_ISR register to \ncheck if the calendar has been initialized or not. If this flag equals 0, the calendar has not \nbeen initialized since the year field is set at its backup domain reset default value (0x00).\nTo read the calendar after initialization, the software must first check that the RSF flag is set \nin the RTC_ISR register.\nDaylight saving time\nThe daylight saving time management is performed through bits SUB1H, ADD1H, and BKP \nof the RTC_CR register.\nUsing SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one \nsingle operation without going through the initialization procedure.\nIn addition, the software can use the BKP bit to memorize this operation.\nProgramming the alarm\nA similar procedure must be followed to program or update the programmable alarm (Alarm \nA or Alarm B):\n1.\nClear ALRAE or ALRBIE in RTC_CR to disable Alarm A or Alarm B.\n2. \nPoll ALRAWF or ALRBWF in RTC_ISR until it is set to make sure the access to alarm \nregisters is allowed. This takes 1 to 2 RTCCLK clock cycles (due to clock \nsynchronization). \n3. \nProgram the Alarm A or Alarm B registers (RTC_ALRMASSR/RTC_ALRMAR or \nRTC_ALRMBSSR/RTC_ALRMBR).\n4. \nSet ALRAE or ALRBIE in the RTC_CR register to enable Alarm A or Alarm B again.\nNote:\nEach change of the RTC_CR register is taken into account after 1 to 2 RTCCLK clock cycles \ndue to clock synchronization.\n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n808/1757\nRM0090 Rev 21\nProgramming the wake-up timer\nThe following sequence is required to configure or change the wake-up timer auto-reload \nvalue (WUT[15:0] in RTC_WUTR):\n1.\nClear WUTE in RTC_CR to disable the wake-up timer.\n2. \nPoll WUTWF until it is set in RTC_ISR to make sure the access to wake-up auto-reload \ncounter and to WUCKSEL[2:0] bits is allowed. It takes 1 to 2 RTCCLK clock cycles \n(due to clock synchronization).\n3. \nProgram the wake-up auto-reload value WUT[15:0], and the wake-up clock selection \n(WUCKSEL[2:0] bits in RTC_CR).Set WUTE in RTC_CR to enable the timer again. \nThe wake-up timer restarts down-counting. The WUTWF bit is cleared up to 2 RTCCLK \nclocks cycles after WUTE is cleared, due to clock synchronization.\n26.3.6 \nReading the calendar\nWhen BYPSHAD control bit is cleared in the RTC_CR register\nTo read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB1 \nclock frequency (fPCLK1) must be equal to or greater than seven times the fRTCCLK RTC \nclock frequency. This ensures a secure behavior of the synchronization mechanism.\nIf the APB1 clock frequency is less than seven times the RTC clock frequency, the software \nmust read the calendar time and date registers twice. If the second read of the RTC_TR \ngives the same result as the first read, this ensures that the data is correct. Otherwise a third \nread access must be done. In any case the APB1 clock frequency must never be lower than \nthe RTC clock frequency.\nThe RSF bit is set in RTC_ISR register each time the calendar registers are copied into the \nRTC_SSR, RTC_TR and RTC_DR shadow registers. The copy is performed every two \nRTCCLK cycles. To ensure consistency between the 3 values, reading either RTC_SSR or \nRTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is \nread. In case the software makes read accesses to the calendar in a time interval smaller \nthan 1 RTCCLK periods: RSF must be cleared by software after the first calendar read, and \nthen the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR \nand RTC_DR registers.\nAfter waking up from low-power mode (Stop or Standby), RSF must be cleared by software. \nThe software must then wait until it is set again before reading the RTC_SSR, RTC_TR and \nRTC_DR registers.\nThe RSF bit must be cleared after wake-up and not before entering low-power mode.\nNote:\nAfter a system reset, the software must wait until RSF is set before reading the RTC_SSR, \nRTC_TR and RTC_DR registers. Indeed, a system reset resets the shadow registers to \ntheir default values. \nAfter an initialization (refer to Calendar initialization and configuration on page 807): the \nsoftware must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR \nregisters.\nAfter synchronization (refer to Section 26.3.8: RTC synchronization): the software must wait \nuntil RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers.\n\n\n<>\n\nRM0090 Rev 21\n809/1757\nRM0090\nReal-time clock (RTC)\n841\nWhen the BYPSHAD control bit is set in the RTC_CR register (bypass shadow \nregisters)\nReading the calendar registers gives the values from the calendar counters directly, thus \neliminating the need to wait for the RSF bit to be set. This is especially useful after exiting \nfrom low-power modes (STOP or Standby), since the shadow registers are not updated \nduring these modes.\nWhen the BYPSHAD bit is set to 1, the results of the different registers might not be \ncoherent with each other if an RTCCLK edge occurs between two read accesses to the \nregisters. Additionally, the value of one of the registers may be incorrect if an RTCCLK edge \noccurs during the read operation. The software must read all the registers twice, and then \ncompare the results to confirm that the data is coherent and correct. Alternatively, the \nsoftware can just compare the two results of the least-significant calendar register.\nNote:\nWhile BYPSHAD=1, instructions which read the calendar registers require one extra APB \ncycle to complete.\n26.3.7 \nResetting the RTC\nThe calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the \nRTC status register (RTC_ISR) are reset to their default values by all available system reset \nsources.\nOn the contrary, the following registers are resetted to their default values by a backup \ndomain reset and are not affected by a system reset: the RTC current calendar registers, \nthe RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC \ncalibration registers (RTC_CALIBR or RTC_CALR), the RTC shift register (RTC_SHIFTR), \nthe RTC timestamp registers (RTC_TSSSR, RTC_TSTR and RTC_TSDR), the RTC tamper \nand alternate function configuration register (RTC_TAFCR), the RTC backup registers \n(RTC_BKPxR), the wake-up timer register (RTC_WUTR), the Alarm A and Alarm B \nregisters (RTC_ALRMASSR/RTC_ALRMAR and RTC_ALRMBSSR/RTC_ALRMBR). \nIn addition, when the RTC is clocked by the LSE, it goes on running under system reset if \nthe reset source is different from a backup domain reset one. Refer to section RTC clock of \nthe Reset and clock controller for details about the list of the RTC clock sources that are not \naffected by system reset.\nWhen a backup domain reset occurs, the RTC is stopped and all the RTC registers are set \nto their reset values.\n26.3.8 \nRTC synchronization \nThe RTC can be synchronized to a remote clock with a high degree of precision. After \nreading the sub-second field (RTC_SSR or RTC_TSSSR), a calculation can be made of the \nprecise offset between the times being maintained by the remote clock and the RTC. The \nRTC can then be adjusted to eliminate this offset by “shifting” its clock by a fraction of a \nsecond using RTC_SHIFTR.\nRTC_SSR contains the value of the synchronous prescaler counter. This allows one to \ncalculate the exact time being maintained by the RTC down to a resolution of \n1 / (PREDIV_S + 1) seconds. As a consequence, the resolution can be improved by \nincreasing the synchronous prescaler value (PREDIV_S[14:0]. The maximum resolution \nallowed (30.52 μs with a 32768 Hz clock) is obtained with PREDIV_S set to 0x7FFF.\n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n810/1757\nRM0090 Rev 21\nHowever, increasing PREDIV_S means that PREDIV_A must be decreased in order to \nmaintain the synchronous prescaler output at 1 Hz. In this way, the frequency of the \nasynchronous prescaler output increases, which may increase the RTC dynamic \nconsumption.\nThe RTC can be finely adjusted using the RTC shift control register (RTC_SHIFTR). Writing \nto RTC_SHIFTR can shift (either delay or advance) the clock by up to a second with a \nresolution of 1 / (PREDIV_S + 1) seconds. The shift operation consists of adding the \nSUBFS[14:0] value to the synchronous prescaler counter SS[15:0]: this delays the clock. If \nat the same time the ADD1S bit is set, this results in adding one second and at the same \ntime subtracting a fraction of second, so this advances the clock.\nCaution:\nBefore initiating a shift operation, the user must check that SS[15] = 0 in order to ensure that \nno overflow occurs.\nAs soon as a shift operation is initiated by a write to the RTC_SHIFTR register, the SHPF \nflag is set by hardware to indicate that a shift operation is pending. This bit is cleared by \nhardware as soon as the shift operation has completed. \nCaution:\nThis synchronization feature is not compatible with the reference clock detection feature: \nfirmware must not write to RTC_SHIFTR when REFCKON=1.\n26.3.9 \nRTC reference clock detection\nThe RTC calendar update can be synchronized to a reference clock RTC_REFIN, usually \nthe mains (50 or 60 Hz). The RTC_REFIN reference clock should have a higher precision \nthan the 32.768 kHz LSE clock. When the RTC_REFIN detection is enabled (REFCKON bit \nof RTC_CR set to 1), the calendar is still clocked by the LSE, and RTC_REFIN is used to \ncompensate for the imprecision of the calendar update frequency (1 Hz). \nEach 1 Hz clock edge is compared to the nearest reference clock edge (if one is found \nwithin a given time window). In most cases, the two clock edges are properly aligned. When \nthe 1 Hz clock becomes misaligned due to the imprecision of the LSE clock, the RTC shifts \nthe 1 Hz clock a bit so that future 1 Hz clock edges are aligned. Thanks to this mechanism, \nthe calendar becomes as precise as the reference clock. \nThe RTC detects if the reference clock source is present by using the 256 Hz clock \n(ck_apre) generated from the 32.768 kHz quartz. The detection is performed during a time \nwindow around each of the calendar updates (every 1 s). The window equals 7 ck_apre \nperiods when detecting the first reference clock edge. A smaller window of 3 ck_apre \nperiods is used for subsequent calendar updates. \nEach time the reference clock is detected in the window, the synchronous prescaler which \noutputs the ck_spre clock is forced to reload. This has no effect when the reference clock \nand the 1 Hz clock are aligned because the prescaler is being reloaded at the same \nmoment. When the clocks are not aligned, the reload shifts future 1 Hz clock edges a little \nfor them to be aligned with the reference clock. \nIf the reference clock halts (no reference clock edge occurred during the 3 ck_apre window), \nthe calendar is updated continuously based solely on the LSE clock. The RTC then waits for \nthe reference clock using a large 7 ck_apre period detection window centered on the \nck_spre edge.\n\n\n<>\n\nRM0090 Rev 21\n811/1757\nRM0090\nReal-time clock (RTC)\n841\nWhen the reference clock detection is enabled, PREDIV_A and PREDIV_S must be set to \ntheir default values:\n•\nPREDIV_A = 0x007F\n•\nPREDIV_S = 0x00FF\nNote:\nThe reference clock detection is not available in Standby mode.\nCaution:\nThe reference clock detection feature cannot be used in conjunction with the coarse digital \ncalibration: RTC_CALIBR must be kept at 0x0000 0000 when REFCKON=1.\n26.3.10 \nRTC coarse digital calibration\nTwo digital calibration methods are available: coarse and smooth calibration. To perform \ncoarse calibration refer to Section 26.6.7: RTC calibration register (RTC_CALIBR).\n The two calibration methods are not intended to be used together, the application must \nselect one of the two methods. Coarse calibration is provided for compatibly reasons. To \nperform smooth calibration refer to Section 26.3.11: RTC smooth digital calibration and the \nSection 26.6.16: RTC calibration register (RTC_CALR)\nThe coarse digital calibration can be used to compensate crystal inaccuracy by adding \n(positive calibration) or masking (negative calibration) clock cycles at the output of the \nasynchronous prescaler (ck_apre).\nPositive and negative calibration are selected by setting the DCS bit in RTC_CALIBR \nregister to ‘0’ and ‘1’, respectively.\nWhen positive calibration is enabled (DCS = ‘0’), 2 ck_apre cycles are added every minute \n(around 15360 ck_apre cycles) for 2xDC minutes. This causes the calendar to be updated \nsooner, thereby adjusting the effective RTC frequency to be a bit higher.\nWhen negative calibration is enabled (DCS = ‘1’), 1 ck_apre cycle is removed every minute \n(around 15360 ck_apre cycles) for 2xDC minutes. This causes the calendar to be updated \nlater, thereby adjusting the effective RTC frequency to be a bit lower.\nDC is configured through bits DC[4:0] of RTC_CALIBR register. This number ranges from 0 \nto 31 corresponding to a time interval (2xDC) ranging from 0 to 62.\nThe coarse digital calibration can be configured only in initialization mode, and starts when \nthe INIT bit is cleared. The full calibration cycle lasts 64 minutes. The first 2xDC minutes of \nthe 64 -minute cycle are modified as just described.\nNegative calibration can be performed with a resolution of about 2 ppm while positive \ncalibration can be performed with a resolution of about 4 ppm. The maximum calibration \nranges from -63 ppm to 126 ppm.\nThe calibration can be performed either on the LSE or on the HSE clock.\nCaution:\nDigital calibration may not work correctly if PREDIV_A < 6.\nCase of RTCCLK=32.768 kHz and PREDIV_A+1=128\nThe following description assumes that ck_apre frequency is 256 Hz obtained with an LSE \nclock nominal frequency of 32.768 kHz, and PREDIV_A set to 127 (default value). \nThe ck_spre clock frequency is only modified during the first 2xDC minutes of the 64-minute \ncycle. For example, when DC equals 1, only the first 2 minutes are modified. This means \nthat the first 2xDC minutes of each 64-minute cycle have, once per minute, one second \n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n812/1757\nRM0090 Rev 21\neither shortened by 256 or lengthened by 128 RTCCLK cycles, given that each ck_apre \ncycle represents 128 RTCCLK cycles (with PREDIV_A+1=128).\nTherefore each calibration step has the effect of adding 512 or subtracting 256 oscillator \ncycles for every 125829120 RTCCLK cycles (64min x 60 s/min x 32768 cycles/s). This is \nequivalent to +4.069 ppm or -2.035 ppm per calibration step. As a result, the calibration \nresolution is +10.5 or -5.27 seconds per month, and the total calibration ranges from +5.45 \nto -2.72 minutes per month.\nIn order to measure the clock deviation, a 512 Hz clock is output for calibration.Refer to \nSection 26.3.14: Calibration clock output.\n26.3.11 \nRTC smooth digital calibration \n RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a range \nfrom -487.1 ppm to +488.5 ppm. The correction of the frequency is performed using series \nof small adjustments (adding and/or subtracting individual RTCCLK pulses). These \nadjustments are fairly well distributed so that the RTC is well calibrated even when observed \nover short durations of time.\nThe smooth digital calibration is performed during a cycle of about 220 RTCCLK pulses, or \n32 seconds when the input frequency is 32768 Hz. This cycle is maintained by a 20-bit \ncounter, cal_cnt[19:0], clocked by RTCCLK.\nThe smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles \nto be masked during the 32-second cycle:\n•\nSetting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32-\nsecond cycle.\n•\nSetting CALM[1] to 1 causes two additional cycles to be masked\n•\nSetting CALM[2] to 1 causes four additional cycles to be masked\n•\nand so on up to CALM[8] set to 1 which causes 256 clocks to be masked.\nNote:\nCALM[8:0] (RTC_CALRx) specifies the number of RTCCLK pulses to be masked during the \n32-second cycle. Setting the bit CALM[0] to ‘1’ causes exactly one pulse to be masked \nduring the 32-second cycle at the moment when cal_cnt[19:0] is 0x80000; CALM[1]=1 \ncauses two other cycles to be masked (when cal_cnt is 0x40000 and 0xC0000); CALM[2]=1 \ncauses four other cycles to be masked (cal_cnt = 0x20000/0x60000/0xA0000/ 0xE0000); \nand so on up to CALM[8]=1 which causes 256 clocks to be masked (cal_cnt = 0xXX800).\nWhile CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine \nresolution, the bit CALP can be used to increase the frequency by 488.5 ppm. Setting CALP \nto ‘1’ effectively inserts an extra RTCCLK pulse every 211 RTCCLK cycles, which means \nthat 512 clocks are added during every 32-second cycle.\nUsing CALM together with CALP, an offset ranging from -511 to +512 RTCCLK cycles can \nbe added during the 32-second cycle, which translates to a calibration range of -487.1 ppm \nto +488.5 ppm with a resolution of about 0.954 ppm.\nThe formula to calculate the effective calibrated frequency (FCAL) given the input frequency \n(FRTCCLK) is as follows:\nFCAL = FRTCCLK x [1 + (CALP x 512 - CALM) / (220 + CALM - CALP x 512)]\nCalibration when PREDIV_A<3\nThe CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in \nRTC_PRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are \n\n\n<>\n\nRM0090 Rev 21\n813/1757\nRM0090\nReal-time clock (RTC)\n841\nset to a value less than 3, CALP is ignored and the calibration operates as if CALP was \nequal to 0.\nTo perform a calibration with PREDIV_A less than 3, the synchronous prescaler value \n(PREDIV_S) should be reduced so that each second is accelerated by 8 RTCCLK clock \ncycles, which is equivalent to adding 256 clock cycles every 32 seconds. As a result, \nbetween 255 and 256 clock pulses (corresponding to a calibration range from 243.3 to \n244.1 ppm) can effectively be added during each 32-second cycle using only the CALM bits.\nWith a nominal RTCCLK frequency of 32768 Hz, when PREDIV_A equals 1 (division factor \nof 2), PREDIV_S should be set to 16379 rather than 16383 (4 less). The only other \ninteresting case is when PREDIV_A equals 0, PREDIV_S should be set to 32759 rather \nthan 32767 (8 less).\nIf PREDIV_S is reduced in this way, the formula given the effective frequency of the\ncalibrated input clock is as follows:\nFCAL = FRTCCLK x [1 + (256 - CALM) / (220 + CALM - 256)]\nIn this case, CALM[7:0] equals 0x100 (the midpoint of the CALM range) is the correct \nsetting if RTCCLK is exactly 32768.00 Hz.\nVerifying the RTC calibration\nRTC precision is performed by measuring the precise frequency of RTCCLK and calculating \nthe correct CALM value and CALP values. An optional 1 Hz output is provided to allow \napplications to measure and verify the RTC precision.\nMeasuring the precise frequency of the RTC over a limited interval can result in a \nmeasurement error of up to 2 RTCCLK clock cycles over the measurement period, \ndepending on how the digital calibration cycle is aligned with the measurement period.\nHowever, this measurement error can be eliminated if the measurement period is the same \nlength as the calibration cycle period. In this case, the only error observed is the error due to \nthe resolution of the digital calibration.\n•\nBy default, the calibration cycle period is 32 seconds. \nUsing this mode and measuring the accuracy of the 1 Hz output over exactly 32 \nseconds guarantees that the measure is within 0.477 ppm (0.5 RTCCLK cycles over 32 \nseconds, due to the limitation of the calibration resolution). \n•\nCALW16 bit of the RTC_CALR register can be set to 1 to force a 16- second calibration \ncycle period.\nIn this case, the RTC precision can be measured during 16 seconds with a maximum \nerror of 0.954 ppm (0.5 RTCCLK cycles over 16 seconds). However, since the \ncalibration resolution is reduced, the long term RTC precision is also reduced to 0.954 \nppm: CALM[0] bit is stuck at 0 when CALW16 is set to 1.\n•\nCALW8 bit of the RTC_CALR register can be set to 1 to force a 8- second calibration \ncycle period.\nIn this case, the RTC precision can be measured during 8 seconds with a maximum \nerror of 1.907 ppm (0.5 RTCCLK cycles over 8s). The long term RTC precision is also \nreduced to 1.907 ppm: CALM[1:0] bits are stuck at 00 when CALW8 is set to 1.\nRe-calibration on-the-fly\nThe calibration register (RTC_CALR) can be updated on-the-fly while RTC_ISR/INITF=0, by \nusing the follow process:\n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n814/1757\nRM0090 Rev 21\n1.\nPoll the RTC_ISR/RECALPF (re-calibration pending flag).\n2. \nIf it is set to 0, write a new value to RTC_CALR, if necessary. RECALPF is then \nautomatically set to 1\n3. \nWithin three ck_apre cycles after the write operation to RTC_CALR, the new calibration \nsettings take effect.\n26.3.12 \nTimestamp function\nTimestamp is enabled by setting the TSE bit of RTC_CR register to 1.\nThe calendar is saved in the timestamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) \nwhen a timestamp event is detected on the pin to which the TIMESTAMP alternate function \nis mapped. When a timestamp event occurs, the timestamp flag bit (TSF) in RTC_ISR \nregister is set. \nBy setting the TSIE bit in the RTC_CR register, an interrupt is generated when a timestamp \nevent occurs. \nIf a new timestamp event is detected while the timestamp flag (TSF) is already set, the \ntimestamp overflow flag (TSOVF) flag is set and the timestamp registers (RTC_TSTR and \nRTC_TSDR) maintain the results of the previous event.\nNote:\nTSF is set 2 ck_apre cycles after the timestamp event occurs due to synchronization \nprocess.\nThere is no delay in the setting of TSOVF. This means that if two timestamp events are \nclose together, TSOVF can be seen as '1' while TSF is still '0'. As a consequence, it is \nrecommended to poll TSOVF only after TSF has been set.\nCaution:\nIf a timestamp event occurs immediately after the TSF bit is supposed to be cleared, then \nboth TSF and TSOVF bits are set. To avoid masking a timestamp event occurring at the \nsame moment, the application must not write ‘0’ into TSF bit unless it has already read it to \n‘1’.\nOptionally, a tamper event can cause a timestamp to be recorded. See the description of the \nTAMPTS control bit in Section 26.6.17: RTC tamper and alternate function configuration \nregister (RTC_TAFCR). If the timestamp event is on the same pin as a tamper event \nconfigured in filtered mode (TAMPFLT set to a non-zero value), the timestamp on tamper \ndetection event mode must be selected by setting TAMPTS='1' in RTC_TAFCR register.\nTIMESTAMP alternate function\nThe TIMESTAMP alternate function (RTC_TS) can be mapped either to RTC_AF1 or to \nRTC_AF2 depending on the value of the TSINSEL bit in the RTC_TAFCR register (see \nSection 26.6.17: RTC tamper and alternate function configuration register (RTC_TAFCR)). \nMapping the timestamp event on RTC_AF2 is not allowed if RTC_AF1 is used as TAMPER \nin filtered mode (TAMPFLT set to a non-zero value).\n26.3.13 \nTamper detection\nTwo tamper detection inputs are available. They can be configured either for edge detection, \nor for level detection with filtering.\nRTC backup registers\nThe backup registers (RTC_BKPxR) are twenty 32-bit registers for storing 80 bytes of user \napplication data. They are implemented in the backup domain that remains powered-on by \n\n\n<>\n\nRM0090 Rev 21\n815/1757\nRM0090\nReal-time clock (RTC)\n841\nVBAT when the VDD power is switched off. They are not reset by system reset or when the \ndevice wakes up from Standby mode. They are reset by a backup domain reset\nThe backup registers are reset when a tamper detection event occurs (see Section 26.6.20: \nRTC backup registers (RTC_BKPxR) and Tamper detection initialization on page 815. \nTamper detection initialization\nEach tamper detection input is associated with the TAMP1F/TAMP2F flags in the RTC_ISR2 \nregister. Each input can be enabled by setting the corresponding TAMP1E/TAMP2E bits to 1 \nin the RTC_TAFCR register.\nA tamper detection event resets all backup registers (RTC_BKPxR).\nBy setting the TAMPIE bit in the RTC_TAFCR register, an interrupt is generated when a \ntamper detection event occurs. \nTimestamp on tamper event\nWith TAMPTS set to ‘1 , any tamper event causes a timestamp to occur. In this case, either \nthe TSF bit or the TSOVF bit are set in RTC_ISR, in the same manner as if a normal \ntimestamp event occurs. The affected tamper flag register (TAMP1F, TAMP2F) is set at the \nsame time that TSF or TSOVF is set.\nEdge detection on tamper inputs\nIf the TAMPFLT bits are “00”, the TAMPER pins generate tamper detection events \n(RTC_TAMP[2:1]) when either a rising edge is observed or an falling edge is observed \ndepending on the corresponding TAMPxTRG bit. The internal pull-up resistors on the \nTAMPER inputs are deactivated when edge detection is selected.\nCaution:\nTo avoid losing tamper detection events, the signal used for edge detection is logically \nANDed with TAMPxE in order to detect a tamper detection event in case it occurs before the \nTAMPERx pin is enabled.\n•\nWhen TAMPxTRG = 0: if the TAMPERx alternate function is already high before \ntamper detection is enabled (TAMPxE bit set to 1), a tamper event is detected as soon \nas TAMPERx is enabled, even if there was no rising edge on TAMPERx after TAMPxE \nwas set.\n•\nWhen TAMPxTRG = 1: if the TAMPERx alternate function is already low before tamper \ndetection is enabled, a tamper event is detected as soon as TAMPERx is enabled \n(even if there was no falling edge on TAMPERx after TAMPxE was set.\nAfter a tamper event has been detected and cleared, the TAMPERx alternate function \nshould be disabled and then re-enabled (TAMPxE set to 1) before re-programming the \nbackup registers (RTC_BKPxR). This prevents the application from writing to the backup \nregisters while the TAMPERx value still indicates a tamper detection. This is equivalent to a \nlevel detection on the TAMPERx alternate function.\nNote:\nTamper detection is still active when VDD power is switched off. To avoid unwanted resetting \nof the backup registers, the pin to which the TAMPER alternate function is mapped should \nbe externally tied to the correct level.\nLevel detection with filtering on tamper inputs \nLevel detection with filtering is performed by setting TAMPFLT to a non-zero value. A tamper \ndetection event is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive \n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n816/1757\nRM0090 Rev 21\nsamples are observed at the level designated by the TAMPxTRG bits \n(TAMP1TRG/TAMP2TRG).\nThe TAMPER inputs are pre-charged through the I/O internal pull-up resistance before its \nstate is sampled, unless disabled by setting TAMPPUDIS to 1,The duration of the precharge \nis determined by the TAMPPRCH bits, allowing for larger capacitances on the tamper \ninputs.\nThe trade-off between tamper detection latency and power consumption through the pull-up \ncan be optimized by using TAMPFREQ to determine the frequency of the sampling for level \ndetection. \nNote:\nRefer to the datasheets for the electrical characteristics of the pull-up resistors.\nTAMPER alternate function detection\nThe TAMPER1 alternate function (RTC_TAMP1) can be mapped either to RTC_AF1(PC13) \nor RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in RTC_TAFCR register (see \nSection 26.6.17: RTC tamper and alternate function configuration register (RTC_TAFCR)). \nTAMPE bit must be cleared when TAMP1INSEL is modified to avoid unwanted setting of \nTAMPF. \nThe TAMPER 2 alternate function corresponds to RTC_TAMP2 pin.\n26.3.14 \nCalibration clock output\nWhen the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the \nRTC_CALIB device output. If the COSEL bit in the RTC_CR register is reset and \nPREDIV_A = 0x7F, the RTC_CALIB frequency is fRTCCLK/64. This corresponds to a \ncalibration output at 512 Hz for an RTCCLK frequency at 32.768 kHz. \nThe RTC_CALIB output is not impacted by the calibration value programmed in \nRTC_CALIBR register. The RTC_CALIB duty cycle is irregular: there is a light jitter on falling \nedges. It is therefore recommended to use rising edges.\nIf COSEL is set and (PREDIV_S+1) is a non-zero multiple of 256 (i.e: PREDIV_S[7:0] = \n0xFF), the RTC_CALIB frequency is fRTCCLK/(256 * (PREDIV_A+1)). This corresponds to a \ncalibration output at 1 Hz for prescaler default values (PREDIV_A = 0x7F, PREDIV_S = \n0xFF), with an RTCCLK frequency at 32.768 kHz. The 1 Hz output is affected when a shift \noperation is on going and may toggle during the shift operation (SHPF=1). \nCalibration alternate function output\nWhen the COE bit in the RTC_CR register is set to 1, the calibration alternate function \n(RTC_CALIB) is enabled on RTC_AF1.\nNote:\nWhen RTC_CALIB or RTC_ALARM is selected, RTC_AF1 is automatically configured in \noutput alternate function.\n26.3.15 \nAlarm output\nThree functions can be selected on Alarm output: ALRAF, ALRBF and WUTF. These \nfunctions reflect the contents of the corresponding flags in the RTC_ISR register. \nThe OSEL[1:0] control bits in the RTC_CR register are used to activate the alarm alternate \nfunction output (RTC_ALARM) in RTC_AF1, and to select the function which is output on \nRTC_ALARM.\n\n\n<>\n\nRM0090 Rev 21\n817/1757\nRM0090\nReal-time clock (RTC)\n841\nThe polarity of the output is determined by the POL control bit in RTC_CR so that the \nopposite of the selected flag bit is output when POL is set to 1.\nAlarm alternate function output\nRTC_ALARM can be configured in output open drain or output push-pull using the control \nbit ALARMOUTTYPE in the RTC_TAFCR register.\nNote:\nOnce RTC_ALARM is enabled, it has priority over RTC_CALIB (COE bit is don't care on \nRTC_AF1).\nWhen RTC_CALIB or RTC_ALARM is selected, RTC_AF1 is automatically configured in \noutput alternate function.\n26.4 \nRTC and low-power modes\n \n26.5 \nRTC interrupts\nAll RTC interrupts are connected to the EXTI controller.\nTo enable the RTC Alarm interrupt, the following sequence is required:\n1.\nConfigure and enable the EXTI Line 17 in interrupt mode and select the rising edge \nsensitivity.\n2. \nConfigure and enable the RTC_Alarm IRQ channel in the NVIC.\n3. \nConfigure the RTC to generate RTC alarms (Alarm A or Alarm B).\nTo enable the RTC Wake-up interrupt, the following sequence is required:\n1.\nConfigure and enable the EXTI Line 22 in interrupt mode and select the rising edge \nsensitivity.\n2. \nConfigure and enable the RTC_WKUP IRQ channel in the NVIC.\n3. \nConfigure the RTC to generate the RTC wake-up timer event.\nTo enable the RTC Tamper interrupt, the following sequence is required:\n1.\nConfigure and enable the EXTI Line 21 in interrupt mode and select the rising edge \nsensitivity.\n2. \nConfigure and Enable the TAMP_STAMP IRQ channel in the NVIC.\n3. \nConfigure the RTC to detect the RTC tamper event.\nTo enable the RTC TimeStamp interrupt, the following sequence is required:\nTable 120. Effect of low-power modes on RTC\nMode \nDescription \nSleep\nNo effect \nRTC interrupts cause the device to exit the Sleep mode.\nStop\nThe RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC \ntamper event, RTC time stamp event, and RTC Wake-up cause the device to exit the Stop \nmode.\nStandby\nThe RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC \ntamper event, RTC time stamp event, and RTC Wake-up cause the device to exit the \nStandby mode.\n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n818/1757\nRM0090 Rev 21\n1.\nConfigure and enable the EXTI Line 21 in interrupt mode and select the rising edge \nsensitivity.\n2. \nConfigure and Enable the TAMP_STAMP IRQ channel in the NVIC.\n3. \nConfigure the RTC to detect the RTC timestamp event.\n \nTable 121. Interrupt control bits\nInterrupt event\nEvent flag\nEnable \ncontrol \nbit\nExit the \nSleep \nmode\nExit the \nStop \nmode\nExit the \nStandby \nmode\nAlarm A\nALRAF\nALRAIE\nyes\nyes(1)\n1.\nWake-up from STOP and Standby modes is possible only when the RTC clock source is LSE or LSI.\nyes(1)\nAlarm B\nALRBF\nALRBIE\nyes\nyes(1)\nyes(1)\nWake-up\nWUTF\nWUTIE\nyes\nyes(1)\nyes(1)\nTimeStamp\nTSF\nTSIE\nyes\nyes(1)\nyes(1)\nTamper1 detection\nTAMP1F\nTAMPIE\nyes\nyes(1)\nyes(1)\nTamper2 detection(2)\n2.\nIf RTC_TAMPER2 pin is present. Refer to device datasheet pinout.\nTAMP2F\nTAMPIE\nyes\nyes(1)\nyes(1)\n\n\n<>\n\nRM0090 Rev 21\n819/1757\nRM0090\nReal-time clock (RTC)\n841\n26.6 \nRTC registers\nRefer to Section 1.1: List of abbreviations for registers for registers for a list of abbreviations \nused in register descriptions.\nThe peripheral registers have to be accessed by words (32 bits).\n26.6.1 \nRTC time register (RTC_TR)\nThe RTC_TR is the calendar time shadow register. This register must be written in \ninitialization mode only. Refer to Calendar initialization and configuration on page 807 and \nReading the calendar on page 808.\nAddress offset: 0x00\nBackup domain reset value: 0x0000 0000\nSystem reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.\n \n \nNote:\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPM\nHT[1:0]\nHU[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nMNT[2:0]\nMNU[3:0]\nRes.\nST[2:0]\nSU[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31-24 Reserved\nBit 23 Reserved, must be kept at reset value.\nBit 22 PM: AM/PM notation\n0: AM or 24-hour format\n1: PM\nBits 21:20 HT[1:0]: Hour tens in BCD format\nBits 19:16 HU[3:0]: Hour units in BCD format\nBit 15 Reserved, must be kept at reset value.\nBits 14:12 MNT[2:0]: Minute tens in BCD format\nBit 11:8 MNU[3:0]: Minute units in BCD format\nBit 7 Reserved, must be kept at reset value.\nBits 6:4 ST[2:0]: Second tens in BCD format\nBits 3:0 SU[3:0]: Second units in BCD format\n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n820/1757\nRM0090 Rev 21\n26.6.2 \nRTC date register (RTC_DR)\nThe RTC_DR is the calendar date shadow register. This register must be written in \ninitialization mode only. Refer to Calendar initialization and configuration on page 807 and \nReading the calendar on page 808.\nAddress offset: 0x04\nBackup domain reset value: 0x0000 2101\nSystem reset: 0x0000 2101 when BYPSHAD = 0. Not affected when BYPSHAD = 1.\n \n \nNote:\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nYT[3:0]\nYU[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nWDU[2:0]\nMT\nMU[3:0]\nReserved\nDT[1:0]\nDU[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31-24 Reserved\nBits 23:20 YT[3:0]: Year tens in BCD format\nBits 19:16 YU[3:0]: Year units in BCD format\nBits 15:13 WDU[2:0]: Week day units\n000: forbidden\n001: Monday\n...\n111: Sunday\nBit 12 MT: Month tens in BCD format\nBits 11:8 MU: Month units in BCD format\nBits 7:6 Reserved, must be kept at reset value.\nBits 5:4 DT[1:0]: Date tens in BCD format\nBits 3:0 DU[3:0]: Date units in BCD format\n\n\n<>\n\nRM0090 Rev 21\n821/1757\nRM0090\nReal-time clock (RTC)\n841\n26.6.3 \nRTC control register (RTC_CR)\nAddress offset: 0x08\nBackup domain reset value: 0x0000 0000 \nSystem reset: not affected\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nCOE\nOSEL[1:0]\nPOL\nCOSEL\nBKP\nSUB1H ADD1H\nrw\nrw\nrw\nrw\nrw\nrw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTSIE\nWUTIE\nALRBIE ALRAIE\nTSE\nWUTE\nALRBE\nALRAE\nDCE\nFMT\nBYPS\nHAD\nREFCKON TSEDGE\nWUCKSEL[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value.\nBit 23 COE: Calibration output enable\nThis bit enables the RTC_CALIB output\n0: Calibration output disabled\n1: Calibration output enabled\nBits 22:21 OSEL[1:0]: Output selection\nThese bits are used to select the flag to be routed to RTC_ALARM output\n00: Output disabled\n01: Alarm A output enabled\n10:Alarm B output enabled\n11: Wake-up output enabled\nBit 20 POL: Output polarity\nThis bit is used to configure the polarity of RTC_ALARM output\n0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])\n1: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]).\nBit 19 COSEL: Calibration output selection\nWhen COE=1, this bit selects which signal is output on RTC_CALIB.\n0: Calibration output is 512 Hz\n1: Calibration output is 1 Hz\nThese frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default \nvalues (PREDIV_A=127 and PREDIV_S=255). Refer to Section 26.3.14: Calibration clock \noutput\nBit 18 BKP: Backup\nThis bit can be written by the user to memorize whether the daylight saving time change has \nbeen performed or not.\nBit 17 SUB1H: Subtract 1 hour (winter time change)\nWhen this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the \ncurrent hour is not 0. This bit is always read as 0.\nSetting this bit has no effect when current hour is 0.\n0: No effect\n1: Subtracts 1 hour to the current time. This can be used for winter time change.\n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n822/1757\nRM0090 Rev 21\nBit 16 ADD1H: Add 1 hour (summer time change)\nWhen this bit is set, 1 hour is added to the calendar time. This bit is always read as 0.\n0: No effect\n1: Adds 1 hour to the current time. This can be used for summer time change outside \ninitialization mode.\nBit 15 TSIE: Timestamp interrupt enable\n0: Timestamp Interrupt disable\n1: Timestamp Interrupt enable\nBit 14 WUTIE: Wake-up timer interrupt enable\n0: Wake-up timer interrupt disabled\n1: Wake-up timer interrupt enabled\nBit 13 ALRBIE: Alarm B interrupt enable\n0: Alarm B Interrupt disable\n1: Alarm B Interrupt enable\nBit 12 ALRAIE: Alarm A interrupt enable\n0: Alarm A interrupt disabled\n1: Alarm A interrupt enabled\nBit 11 TSE: Time stamp enable\n0: Time stamp disable\n1: Time stamp enable\nBit 10 WUTE: Wake-up timer enable\n0: Wake-up timer disabled\n1: Wake-up timer enabled\nNote: When the wake-up timer is disabled, wait for WUTWF=1 before enabling it again.\nBit 9 ALRBE: Alarm B enable\n0: Alarm B disabled\n1: Alarm B enabled\nBit 8 ALRAE: Alarm A enable\n0: Alarm A disabled\n1: Alarm A enabled\nBit 7 DCE: Coarse digital calibration enable\n0: Digital calibration disabled\n1: Digital calibration enabled\nPREDIV_A must be 6 or greater\nBit 6 FMT: Hour format\n0: 24 hour/day format\n1: AM/PM hour format\nBit 5 BYPSHAD: Bypass the shadow registers\n0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from \nthe shadow registers, which are updated once every two RTCCLK cycles.\n1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken \ndirectly from the calendar counters.\nNote: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, \nBYPSHAD must be set to ‘1’.\n\n\n<>\n\nRM0090 Rev 21\n823/1757\nRM0090\nReal-time clock (RTC)\n841\nNote:\nWUT = Wake-up unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when \nWUCKSEL[2:1 = 11]. \nBits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1).\nBits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR \nWUTWF bit = 1.\nIt is recommended not to change the hour during the calendar hour increment as it could \nmask the incrementation of the calendar hour.\nADD1H and SUB1H changes are effective in the next second.\nTo avoid spuriously setting of TSF, TSE must be reset when TSEDGE is changed. \nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806.\n26.6.4 \nRTC initialization and status register (RTC_ISR)\nAddress offset: 0x0C\nBackup domain reset value: 0x0000 0007\nSystem reset value: Not affected except INIT, INITF and RSF which are cleared to 0.\n \nBit 4 REFCKON: Reference clock detection enable (50 or 60 Hz)\n0: Reference clock detection disabled\n1: Reference clock detection enabled\nNote: PREDIV_S must be 0x00FF.\nBit 3 TSEDGE: Timestamp event active edge\n0: TIMESTAMP rising edge generates a timestamp event\n1: TIMESTAMP falling edge generates a timestamp event\nTSE must be reset when TSEDGE is changed to avoid unwanted TSF setting\nBits 2:0 WUCKSEL[2:0]: Wake-up clock selection\n000: RTC/16 clock is selected\n001: RTC/8 clock is selected\n010: RTC/4 clock is selected\n011: RTC/2 clock is selected\n10x: ck_spre (usually 1 Hz) clock is selected\n11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value \n(see note below)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nRECAL \nPF\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nTAMP \n2F\nTAMP \n1F\nTSOVF\nTSF\nWUTF\nALRBF\nALRAF\nINIT\nINITF\nRSF\nINITS\nSHPF\nWUT \nWF\nALRB \nWF\nALRA \nWF\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrw\nr\nrc_w0\nr\nr\nr\nr\nr\n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n824/1757\nRM0090 Rev 21\nBits 31:17 Reserved \nBit 16 RECALPF: Recalibration pending Flag\nThe RECALPF status flag is automatically set to ‘1’ when software writes to the RTC_CALR \nregister, indicating that the RTC_CALR register is blocked. When the new calibration \nsettings are taken into account, this bit returns to ‘0’. Refer to Section : Re-calibration on-the-\nfly.\nBit 15 Reserved, must be kept at reset value.\nBit 14 TAMP2F: TAMPER2 detection flag\nThis flag is set by hardware when a tamper detection event is detected on tamper input 2.\nIt is cleared by software writing 0.\nBit 13 TAMP1F: Tamper detection flag\nThis flag is set by hardware when a tamper detection event is detected.\nIt is cleared by software writing 0.\nBit 12 TSOVF: Timestamp overflow flag\nThis flag is set by hardware when a timestamp event occurs while TSF is already set.\nThis flag is cleared by software by writing 0. It is recommended to check and then clear \nTSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a \ntimestamp event occurs immediately before the TSF bit is cleared.\nBit 11 TSF: Timestamp flag\nThis flag is set by hardware when a timestamp event occurs.\nThis flag is cleared by software by writing 0.\nBit 10 WUTF: Wake-up timer flag\nThis flag is set by hardware when the wake-up auto-reload counter reaches 0.\nThis flag is cleared by software by writing 0.\nThis flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 \nagain.\nBit 9 ALRBF: Alarm B flag\nThis flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the \nAlarm B register (RTC_ALRMBR).\nThis flag is cleared by software by writing 0.\nBit 8 ALRAF: Alarm A flag\nThis flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the \nAlarm A register (RTC_ALRMAR).\nThis flag is cleared by software by writing 0.\nBit 7 INIT: Initialization mode\n0: Free running mode\n1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and \nprescaler register (RTC_PRER). Counters are stopped and start counting from the new \nvalue when INIT is reset.\nBit 6 INITF: Initialization flag\nWhen this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler \nregisters can be updated.\n0: Calendar registers update is not allowed\n1: Calendar registers update is allowed.\n\n\n<>\n\nRM0090 Rev 21\n825/1757\nRM0090\nReal-time clock (RTC)\n841\nNote:\nThe ALRAF, ALRBF, WUTF and TSF bits are cleared 2 APB clock cycles after programming \nthem to 0.\nThis register is write protected (except for RTC_ISR[13:8] bits). The write access procedure \nis described in RTC register write protection on page 806.\nBit 5 RSF: Registers synchronization flag\nThis bit is set by hardware each time the calendar registers are copied into the shadow \nregisters (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in \ninitialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow \nregister mode (BYPSHAD=1). This bit can also be cleared by software.\n0: Calendar shadow registers not yet synchronized\n1: Calendar shadow registers synchronized\nBit 4 INITS: Initialization status flag\nThis bit is set by hardware when the calendar year field is different from 0 (backup domain \nreset value state).\n0: Calendar has not been initialized\n1: Calendar has been initialized\nBit 3 SHPF: Shift operation pending \n0: No shift operation is pending\n1: A shift operation is pending\nThis flag is set by hardware as soon as a shift operation is initiated by a write to the \nRTC_SHIFTR. It is cleared by hardware when the corresponding shift operation has been \nexecuted. Writing to SHPF has no effect.\nBit 2 WUTWF: Wake-up timer write flag\nThis bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in \nRTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The \nwake-up timer values can be changed when WUTE bit is cleared and WUTWF is set.\n0: Wake-up timer configuration update not allowed\n1: Wake-up timer configuration update allowed\nBit 1 ALRBWF: Alarm B write flag\nThis bit is set by hardware when Alarm B values can be changed, after the ALRBIE bit has \nbeen set to 0 in RTC_CR.\nIt is cleared by hardware in initialization mode.\n0: Alarm B update not allowed\n1: Alarm B update allowed.\nBit 0 ALRAWF: Alarm A write flag\nThis bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has \nbeen set to 0 in RTC_CR.\nIt is cleared by hardware in initialization mode.\n0: Alarm A update not allowed\n1: Alarm A update allowed\n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n826/1757\nRM0090 Rev 21\n26.6.5 \nRTC prescaler register (RTC_PRER)\nAddress offset: 0x10\nBackup domain reset value: 0x007F 00FF\nSystem reset: not affected\n \n \nNote:\nThis register must be written in initialization mode only. The initialization must be performed \nin two separate write accesses. Refer to Calendar initialization and configuration on \npage 807\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806.\n26.6.6 \nRTC wake-up timer register (RTC_WUTR)\nAddress offset: 0x14\nBackup domain reset value: 0x0000 FFFF\nSystem reset: not affected\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPREDIV_A[6:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nPREDIV_S[14:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved\nBit 23 Reserved, must be kept at reset value.\nBits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor\nThis is the asynchronous division factor: \nck_apre frequency = RTCCLK frequency/(PREDIV_A+1)\nBit 15 Reserved, must be kept at reset value.\nBits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor\nThis is the synchronous division factor: \nck_spre frequency = ck_apre frequency/(PREDIV_S+1)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nWUT[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n827/1757\nRM0090\nReal-time clock (RTC)\n841\n \nNote:\nThis register can be written only when WUTWF is set to 1 in RTC_ISR.\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806.\n26.6.7 \nRTC calibration register (RTC_CALIBR)\nAddress offset: 0x18\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected\n \n \nBits 31:16 Reserved\nBits 15:0 WUT[15:0]: Wake-up auto-reload value bits\nWhen the wake-up timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] \n+ 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the \nRTC_CR register\nWhen WUCKSEL[2] = 1, the wake-up timer becomes 17-bits and WUCKSEL[1] effectively \nbecomes WUT[16] the most-significant bit to be reloaded into the timer.\nNote: The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting \nWUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden. \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDCS\nReserved\nDC[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved\nBit 7 DCS: Digital calibration sign\n0: Positive calibration: calendar update frequency is increased\n1: Negative calibration: calendar update frequency is decreased\nBits 6:5 Reserved, must be kept at reset value.\nBits 4:0 DC[4:0]: Digital calibration\nDCS = 0 (positive calibration)\n00000: + 0 ppm\n00001: + 4 ppm (rounded value)\n00010: + 8 ppm (rounded value)\n..\n11111: + 126 ppm (rounded value)\nDCS = 1 (negative calibration)\n00000: − 0 ppm\n00001: − 2 ppm (rounded value)\n00010: − 4 ppm (rounded value)\n..\n11111: − 63 ppm (rounded value)\nRefer to Case of RTCCLK=32.768 kHz and PREDIV_A+1=128 on page 811 for the exact \nstep value.\n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n828/1757\nRM0090 Rev 21\nNote:\nThis register can be written in initialization mode only (RTC_ISR/INITF = ‘1’).\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806.\n26.6.8 \nRTC alarm A register (RTC_ALRMAR)\nAddress offset: 0x1C\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMSK4\nWDSEL\nDT[1:0]\nDU[3:0]\nMSK3\n PM\nHT[1:0]\nHU[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMSK2\n MNT[2:0]\nMNU[3:0]\nMSK1\n ST[2:0]\nSU[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 MSK4: Alarm A date mask\n0: Alarm A set if the date/day match\n1: Date/day don’t care in Alarm A comparison\nBit 30 WDSEL: Week day selection\n0: DU[3:0] represents the date units\n1: DU[3:0] represents the week day. DT[1:0] is don’t care.\nBits 29:28 DT[1:0]: Date tens in BCD format.\nBits 27:24 DU[3:0]: Date units or day in BCD format.\nBit 23 MSK3: Alarm A hours mask\n0: Alarm A set if the hours match\n1: Hours don’t care in Alarm A comparison\nBit 22 PM: AM/PM notation\n0: AM or 24-hour format\n1: PM\nBits 21:20 HT[1:0]: Hour tens in BCD format.\nBits 19:16 HU[3:0]: Hour units in BCD format.\nBit 15 MSK2: Alarm A minutes mask\n0: Alarm A set if the minutes match\n1: Minutes don’t care in Alarm A comparison\nBits 14:12 MNT[2:0]: Minute tens in BCD format.\nBits 11:8 MNU[3:0]: Minute units in BCD format.\nBit 7 MSK1: Alarm A seconds mask\n0: Alarm A set if the seconds match\n1: Seconds don’t care in Alarm A comparison\nBits 6:4 ST[2:0]: Second tens in BCD format.\nBits 3:0 SU[3:0]: Second units in BCD format.\n\n\n<>\n\nRM0090 Rev 21\n829/1757\nRM0090\nReal-time clock (RTC)\n841\nNote:\nThis register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization \nmode.\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806.\n26.6.9 \nRTC alarm B register (RTC_ALRMBR)\nAddress offset: 0x20\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMSK4\nWDSEL\nDT[1:0]\nDU[3:0]\nMSK3\n PM\nHT[1:0]\nHU[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMSK2\n MNT[2:0]\nMNU[3:0]\nMSK1\n ST[2:0]\nSU[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 MSK4: Alarm B date mask\n0: Alarm B set if the date and day match\n1: Date and day don’t care in Alarm B comparison\nBit 30 WDSEL: Week day selection\n0: DU[3:0] represents the date units\n1: DU[3:0] represents the week day. DT[1:0] is don’t care.\nBits 29:28 DT[1:0]: Date tens in BCD format\nBits 27:24 DU[3:0]: Date units or day in BCD format\nBit 23 MSK3: Alarm B hours mask\n0: Alarm B set if the hours match\n1: Hours don’t care in Alarm B comparison\nBit 22 PM: AM/PM notation\n0: AM or 24-hour format\n1: PM\nBits 21:20 HT[1:0]: Hour tens in BCD format\nBits 19:16 HU[3:0]: Hour units in BCD format\nBit 15 MSK2: Alarm B minutes mask\n0: Alarm B set if the minutes match\n1: Minutes don’t care in Alarm B comparison\nBits 14:12 MNT[2:0]: Minute tens in BCD format\nBits 11:8 MNU[3:0]: Minute units in BCD format\nBit 7 MSK1: Alarm B seconds mask\n0: Alarm B set if the seconds match\n1: Seconds don’t care in Alarm B comparison\nBits 6:4 ST[2:0]: Second tens in BCD format\nBits 3:0 SU[3:0]: Second units in BCD format\n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n830/1757\nRM0090 Rev 21\nNote:\nThis register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization \nmode.\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806.\n26.6.10 \nRTC write protection register (RTC_WPR)\nAddress offset: 0x24\nBackup domain reset value: 0x0000 0000\n \n \n26.6.11 \nRTC sub second register (RTC_SSR)\nAddress offset: 0x28\nBackup domain reset value: 0x0000 0000\nSystem reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nKEY\nw\nw\nw\nw\nw\nw\nw\nw\nBits 31:8 Reserved, must be kept at reset value.\nBits 7:0 KEY: Write protection key\nThis byte is written by software.\nReading this byte always returns 0x00.\nRefer to RTC register write protection for a description of how to unlock RTC register write \nprotection.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSS[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 Reserved\nBits 15:0 SS: Sub second value\nSS[15:0] is the value in the synchronous prescaler’s counter. The fraction of a second is \ngiven by the formula below:\nSecond fraction = ( PREDIV_S - SS ) / ( PREDIV_S + 1 )\nNote: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct \ntime/date is one second less than as indicated by RTC_TR/RTC_DR.\n\n\n<>\n\nRM0090 Rev 21\n831/1757\nRM0090\nReal-time clock (RTC)\n841\n26.6.12 \nRTC shift control register (RTC_SHIFTR)\nAddress offset: 0x2C\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected\n \n \nNote:\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806\n26.6.13 \nRTC time stamp time register (RTC_TSTR)\nAddress offset: 0x30\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nADD1S\nReserved\nw\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nSUBFS[14:0]\nr\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBit 31 ADD1S: Add one second\n0: No effect\n1: Add one second to the clock/calendar\nThis bit is write only and is always read as zero. Writing to this bit has no effect when a shift \noperation is pending (when SHPF=1, in RTC_ISR).\nThis function is intended to be used with SUBFS (see description below) in order to \neffectively add a fraction of a second to the clock in an atomic operation.\nBits 30:15 Reserved\nBits 14:0 SUBFS: Subtract a fraction of a second\nThese bits are write only and is always read as zero. Writing to this bit has no effect when a \nshift operation is pending (when SHPF=1, in RTC_ISR).\nThe value which is written to SUBFS is added to the synchronous prescaler’s counter. Since \nthis counter counts down, this operation effectively subtracts from (delays) the clock by:\nDelay (seconds) = SUBFS / ( PREDIV_S + 1 )\nA fraction of a second can effectively be added to the clock (advancing the clock) when the \nADD1S function is used in conjunction with SUBFS, effectively advancing the clock by:\nAdvance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) .\nNote: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be \nsure that the shadow registers have been updated with the shifted time.\nRefer to Section 26.3.8: RTC synchronization.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n PM\nHT[1:0]\nHU[3:0]\nr\nr\nr\nr\nr\nr\nr\n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n832/1757\nRM0090 Rev 21\n \nNote:\nThe content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when \nTSF bit is reset.\n26.6.14 \nRTC time stamp date register (RTC_TSDR)\nAddress offset: 0x34\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected\n \n \nNote:\nThe content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when \nTSF bit is reset.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nMNT[2:0]\nMNU[3:0]\nRes.\nST[2:0]\nSU[3:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:23 Reserved, must be kept at reset value.\nBit 22 PM: AM/PM notation\n0: AM or 24-hour format\n1: PM\nBits 21:20 HT[1:0]: Hour tens in BCD format.\nBits 19:16 HU[3:0]: Hour units in BCD format.\nBit 15\nReserved, must be kept at reset value.\nBits 14:12 MNT[2:0]: Minute tens in BCD format.\nBits 11:8 MNU[3:0]: Minute units in BCD format.\nBit 7 Reserved, must be kept at reset value.\nBits 6:4 ST[2:0]: Second tens in BCD format.\nBits 3:0 SU[3:0]: Second units in BCD format.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nWDU[1:0]\nMT\nMU[3:0]\nReserved\nDT[1:0]\nDU[3:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:13 WDU[1:0]: Week day units\nBit 12 MT: Month tens in BCD format\nBits 11:8 MU[3:0]: Month units in BCD format\nBits 7:6 Reserved, must be kept at reset value.\nBits 5:4 DT[1:0]: Date tens in BCD format\nBit 3:0 DU[3:0]: Date units in BCD format\n\n\n<>\n\nRM0090 Rev 21\n833/1757\nRM0090\nReal-time clock (RTC)\n841\n26.6.15 \nRTC timestamp sub second register (RTC_TSSSR)\nAddress offset: 0x38\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected\n \n \nNote:\nThe content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the \nRTC_ISR/TSF bit is reset.\n26.6.16 \nRTC calibration register (RTC_CALR)\nAddress offset: 0x3C\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSS[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 Reserved\nBits 15:0 SS: Sub second value\nSS[15:0] is the value of the synchronous prescaler’s counter when the timestamp event \noccurred. \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCALP\nCALW8 CALW16\nReserved\nCALM[8:0]\nrw\nrw\nrw\nr\nr\nr\nr\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n834/1757\nRM0090 Rev 21\n \nNote:\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806\nBits 31:16 Reserved\nBit 15 CALP: Increase frequency of RTC by 488.5 ppm\n0: No RTCCLK pulses are added.\n1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency increased by \n488.5 ppm). \nThis feature is intended to be used in conjunction with CALM, which lowers the frequency of \nthe calendar with a fine resolution. if the input frequency is 32768 Hz, the number of \nRTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - \nCALM.\nRefer to Section 26.3.11: RTC smooth digital calibration.\nBit 14 CALW8: Use an 8-second calibration cycle period\nWhen CALW8 is set to ‘1’, the 8-second calibration cycle period is selected. \nCALM[1:0] are stuck at “00” when CALW8=’1’.\nRefer to Section 26.3.11: RTC smooth digital calibration.\nBit 13 CALW16: Use a 16-second calibration cycle period\nWhen CALW16 is set to ‘1’, the 16-second calibration cycle period is selected. This bit must \nnot be set to ‘1’ if CALW8=1.\nNote: CALM[0] is stuck at ‘0’ when CALW16=’1’.\nRefer to Section 26.3.11: RTC smooth digital calibration.\nBits 12:9 Reserved\nBits 8:0 CALM[8:0]: Calibration minus\nThe frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 \nseconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar \nwith a resolution of 0.9537 ppm.\nTo increase the frequency of the calendar, this feature should be used in conjunction with \nCALP.\nSee Section 26.3.11: RTC smooth digital calibration on page 812.\n\n\n<>\n\nRM0090 Rev 21\n835/1757\nRM0090\nReal-time clock (RTC)\n841\n26.6.17 \nRTC tamper and alternate function configuration register\n(RTC_TAFCR)\nAddress offset: 0x40\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nALARMOUT\nTYPE\nTSIN\nSEL\nTAMP1\nINSEL\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTAMP-\nPUDIS\nTAMP-\nPRCH[1:0]\nTAMPFLT[1:0]\nTAMPFREQ[2:0]\nTAMPT\nS\nReserved\nTAMP2\n-TRG\nTAMP2\nE\nTAMPIE\nTAMP1\nTRG\nTAMP1\nE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:19 Reserved. Always read as 0.\nBit 18 ALARMOUTTYPE: RTC_ALARM output type\n0: RTC_ALARM is an open-drain output\n1: RTC_ALARM is a push-pull output\nBit 17 TSINSEL: TIMESTAMP mapping\n0: RTC_AF1 used as TIMESTAMP\n1: RTC_AF2 used as TIMESTAMP\nBit 16 TAMP1INSEL: TAMPER1 mapping\n0: RTC_AF1 used as TAMPER1\n1: RTC_AF2 used as TAMPER1\nNote: TAMP1E must be reset when TAMP1INSEL is changed to avoid unwanted setting of \nTAMP1F.\nBit 15 TAMPPUDIS: TAMPER pull-up disable\nThis bit determines if each of the tamper pins are pre-charged before each sample.\n0: Precharge tamper pins before sampling (enable internal pull-up)\n1: Disable precharge of tamper pins\nNote:\nBits 14:13 TAMPPRCH[1:0]: Tamper precharge duration\nThese bit determines the duration of time during which the pull-up/is activated before each \nsample. TAMPPRCH is valid for each of the tamper inputs.\n0x0: 1 RTCCLK cycle\n0x1: 2 RTCCLK cycles\n0x2: 4 RTCCLK cycles\n0x3: 8 RTCCLK cycles\n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n836/1757\nRM0090 Rev 21\nBits 12:11 TAMPFLT[1:0]: Tamper filter count\nThese bits determines the number of consecutive samples at the specified level \n(TAMP*TRG) necessary to activate a Tamper event. TAMPFLT is valid for each of the tamper \ninputs.\n0x0: Tamper is activated on edge of tamper input transitions to the active level (no internal \npull-up on tamper input).\n0x1: Tamper is activated after 2 consecutive samples at the active level.\n0x2: Tamper is activated after 4 consecutive samples at the active level.\n0x3: Tamper is activated after 8 consecutive samples at the active level.\nBits 10:8 TAMPFREQ[2:0]: Tamper sampling frequency\nDetermines the frequency at which each of the tamper inputs are sampled.\n0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)\n0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)\n0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)\n0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)\n0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)\n0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)\n0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)\n0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)\nBit 7 TAMPTS: Activate timestamp on tamper detection event\n0: Tamper detection event does not cause a timestamp to be saved\n1: Save timestamp on tamper detection event\nTAMPTS is valid even if TSE=0 in the RTC_CR register. \nBits 6:5 Reserved. Always read as 0.\nBit 4 TAMP2TRG: Active level for tamper 2\nif TAMPFLT != 00 \n0: TAMPER2 staying low triggers a tamper detection event.\n1: TAMPER2 staying high triggers a tamper detection event.\nif TAMPFLT = 00:\n0: TAMPER2 rising edge triggers a tamper detection event.\n1: TAMPER2 falling edge triggers a tamper detection event.\nBit 3 TAMP2E: Tamper 2 detection enable\n0: Tamper 2 detection disabled\n1: Tamper 2 detection enabled\nBit 2 TAMPIE: Tamper interrupt enable\n0: Tamper interrupt disabled\n1: Tamper interrupt enabled\n\n\n<>\n\nRM0090 Rev 21\n837/1757\nRM0090\nReal-time clock (RTC)\n841\n26.6.18 \nRTC alarm A sub second register (RTC_ALRMASSR)\nAddress offset: 0x44\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected \n \n \nBit 1 TAMP1TRG: Active level for tamper 1\nif TAMPFLT != 00 \n0: TAMPER1 staying low triggers a tamper detection event.\n1: TAMPER1 staying high triggers a tamper detection event.\nif TAMPFLT = 00:\n0: TAMPER1 rising edge triggers a tamper detection event.\n1: TAMPER1 falling edge triggers a tamper detection event.\nCaution: When TAMPFLT = 0, TAMPxE must be reset when TAMPxTRG is changed to avoid \nspuriously setting TAMPxF.\nBit 0 TAMP1E: Tamper 1 detection enable\n0: Tamper 1 detection disabled\n1: Tamper 1 detection enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nMASKSS[3:0]\nReserved\nr\nr\nr\nr\nrw\nrw\nrw\nrw\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSS[14:0]\nr\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nw\nrw\nrw\nBits 31:28 Reserved\nBits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit\n0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is \nincremented (assuming that the rest of the fields match).\n1: SS[14:1] are don’t care in Alarm A comparison. Only SS[0] is compared.\n2: SS[14:2] are don’t care in Alarm A comparison. Only SS[1:0] are compared.\n3: SS[14:3] are don’t care in Alarm A comparison. Only SS[2:0] are compared.\n...\n12: SS[14:12] are don’t care in Alarm A comparison. SS[11:0] are compared.\n13: SS[14:13] are don’t care in Alarm A comparison. SS[12:0] are compared.\n14: SS[14] is don’t care in Alarm A comparison. SS[13:0] are compared.\n15: All 15 SS bits are compared and must match to activate alarm.\nThe overflow bits of the synchronous counter (bits 15) is never compared. This bit can be \ndifferent from 0 only after a shift operation.\nBits 23:15 Reserved\nBits 14:0 SS[14:0]: Sub seconds value\nThis value is compared with the contents of the synchronous prescaler’s counter to \ndetermine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.\n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n838/1757\nRM0090 Rev 21\nNote:\nThis register can be written only when ALRAE is reset in RTC_CR register, or in initialization \nmode.\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806\n26.6.19 \nRTC alarm B sub second register (RTC_ALRMBSSR)\nAddress offset: 0x48\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected \n \n \nNote:\nThis register can be written only when ALRBIE is reset in RTC_CR register, or in \ninitialization mode.\nThis register is write protected.The write access procedure is described in Section : RTC \nregister write protection\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nMASKSS[3:0]\nReserved\nr\nr\nr\nr\nrw\nrw\nrw\nrw\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSS[14:0]\nr\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nw\nrw\nrw\nBits 31:28 Reserved\nBits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit\n0x0: No comparison on sub seconds for Alarm B. The alarm is set when the seconds unit is \nincremented (assuming that the rest of the fields match).\n0x1: SS[14:1] are don’t care in Alarm B comparison. Only SS[0] is compared.\n0x2: SS[14:2] are don’t care in Alarm B comparison. Only SS[1:0] are compared.\n0x3: SS[14:3] are don’t care in Alarm B comparison. Only SS[2:0] are compared.\n...\n0xC: SS[14:12] are don’t care in Alarm B comparison. SS[11:0] are compared.\n0xD: SS[14:13] are don’t care in Alarm B comparison. SS[12:0] are compared.\n0xE: SS[14] is don’t care in Alarm B comparison. SS[13:0] are compared.\n0xF: All 15 SS bits are compared and must match to activate alarm.\nThe overflow bits of the synchronous counter (bits 15) is never compared. This bit can be \ndifferent from 0 only after a shift operation.\nBits 23:15 Reserved\nBits 14:0 SS[14:0]: Sub seconds value\nThis value is compared with the contents of the synchronous prescaler’s counter to \ndetermine if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared.\n\n\n<>\n\nRM0090 Rev 21\n839/1757\nRM0090\nReal-time clock (RTC)\n841\n26.6.20 \nRTC backup registers (RTC_BKPxR)\nAddress offset: 0x50 to 0x9C\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected \n \n \n26.6.21 \nRTC register map\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nBKP[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nBKP[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nw\nrw\nrw\nBits 31:0 BKP[31:0]\nThe application can write or read data to and from these registers. \nThey are powered-on by VBAT when VDD is switched off, so that they are not reset by \nSystem reset, and their contents remain valid when the device operates in low-power mode. \nThis register is reset on a tamper detection event, as long as TAMPxF=1.\nTable 122. RTC register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nRTC_TR\nReserved\nPM\nHT\n[1:0]\nHU[3:0]\nReserved\nMNT[2:0]\nMNU[3:0]\nReserved\nST[2:0]\nSU[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nRTC_DR\nReserved\nYT[3:0]\nYU[3:0]\nWDU[2:0]\nMT\nMU[3:0]\nReserved\nDT\n[1:0]\nDU[3:0]\nReset value\n0\n0\n1\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n1\n0x08\nRTC_CR\nReserved\nCOE\nOSEL\n[1:0]\nPOL\nCOSEL\nBKP\nSUB1H\nADD1H\nTSIE\nWUTIE\nALRBIE\nALRAIE\nTSE\nWUTE\nALRBE\nALRAE\nDCE\nFMT\nBYPSHAD\nREFCKON\nTSEDGE\nWCKSEL\n[2:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nRTC_ISR\nReserved\nTAMP2F\nTAMP1F\nTSOVF\nTSF\nWUTF\nALRBF\nALRAF\nINIT\nINITF\nRSF\nINITS\nSHPF\nWUTWF\nALRBWF\nALRAWF\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n1\n0x10\nRTC_PRER\nReserved\nPREDIV_A[6:0]\nReserved\nPREDIV_S[14:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n1\n1\n1\n1\n1\n0x14\nRTC_WUTR\nReserved\nWUT[15:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x18\nRTC_CALIBR\nReserved\nDCS\nReserved\nDC[4:0]\nReset value\n0\n0\n0\n0\n0\n0\n\n\n<>\n\nReal-time clock (RTC)\nRM0090\n840/1757\nRM0090 Rev 21\n0x1C\nRTC_ALRMAR\nMSK4\nWDSEL\nDT\n[1:0]\nDU[3:0]\nMSK3\nPM\nHT\n[1:0]\nHU[3:0]\nMSK2\nMNT[2:0]\nMNU[3:0]\nMSK1\nST[2:0]\nSU[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nRTC_ALRMBR\nMSK4\nWDSEL\nDT\n[1:0]\nDU[3:0]\nMSK3\nPM\nHT\n[1:0]\nHU[3:0]\nMSK2\nMNT[2:0]\nMNU[3:0]\nMSK2\nST[2:0]\nSU[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x24\nRTC_WPR\nReserved\nKEY[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nRTC_SSR\nReserved\nSS[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x2C\nRTC_SHIFTR\nADD1S\nReserved\nSUBFS[14:0]\nReset value\n0\n0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x30\nRTC_TSTR\nReserved\nPM\nHT[1:0]\nHU[3:0]\nReserved\nMNT[2:0]\nMNU[3:0]\nReserved\nST[2:0]\nSU[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x38\nRTC_TSSSR\nReserved\nSS[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x3C\nRTC_ CALR\nReserved\nCALP\nCALW8\nCALW16\nReserved\nCALM[8:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x40\nRTC_TAFCR\nReserved\nALARMOUTTYPE\nTSINSEL\nTAMP1INSEL\nTAMPPUDIS\nTAMPPRCH[1:0]\nTAMPFLT[1:0]\nTAMPFREQ[2:0]\nTAMPTS\nReserved\nTAMP2TRG\nTAMP2E\nTAMPIE\nTAMP1ETRG\nTAMP1E\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x44\nRTC_ \nALRMASSR\nReserved\nMASKSS[3:0]\nReserved\nSS[14:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x48\nRTC_ \nALRMBSSR\nReserved\nMASKSS[3:0]\nReserved\nSS[14:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x50\nto 0x9C\nRTC_BKP0R\nBKP[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nto \nRTC_BKP19R\nBKP[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 122. RTC register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n841/1757\nRM0090\nReal-time clock (RTC)\n841\nRefer to Section 2.3: Memory map for the register boundary addresses.\nCaution:\nIn Table 122, the reset value is the value after a backup domain reset. The majority of the \nregisters are not affected by a system reset. For more information, please refer to \nSection 26.3.7: Resetting the RTC.\n\n\n<>\n\nInter-integrated circuit (I2C) interface\nRM0090\n842/1757\nRM0090 Rev 21\n27 \nInter-integrated circuit (I2C) interface\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n27.1 \nI2C introduction\nI2C (inter-integrated circuit) bus Interface serves as an interface between the microcontroller \nand the serial I2C bus. It provides multimaster capability, and controls all I2C bus-specific \nsequencing, protocol, arbitration and timing. It supports the standard mode (Sm, up to \n100 kHz) and Fm mode (Fm, up to 400 kHz). \nIt may be used for a variety of purposes, including CRC generation and verification, SMBus \n(system management bus) and PMBus (power management bus).\nDepending on specific device implementation DMA capability can be available for reduced \nCPU overload.\n27.2 \nI2C main features\n•\nParallel-bus/I2C protocol converter\n•\nMultimaster capability: the same interface can act as Master or Slave\n•\nI2C Master features:\n–\nClock generation\n–\nStart and Stop generation\n•\nI2C Slave features:\n–\nProgrammable I2C Address detection\n–\nDual Addressing Capability to acknowledge 2 slave addresses\n–\nStop bit detection\n•\nGeneration and detection of 7-bit/10-bit addressing and General Call\n•\nSupports different communication speeds: \n–\nStandard Speed (up to 100 kHz)\n–\nFast Speed (up to 400 kHz)\n•\nAnalog noise filter \n•\nProgrammable digital noise filter for STM32F42xxx and STM32F43xxx\n•\nStatus flags:\n–\nTransmitter/Receiver mode flag\n–\nEnd-of-Byte transmission flag\n–\nI2C busy flag\n•\nError flags:\n–\nArbitration lost condition for master mode\n–\nAcknowledgment failure after address/ data transmission\n–\nDetection of misplaced start or stop condition\n–\nOverrun/Underrun if clock stretching is disabled\n•\n2 Interrupt vectors: \n\n\n<>\n\nRM0090 Rev 21\n843/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\n–\n1 Interrupt for successful address/ data communication\n–\n1 Interrupt for error condition\n•\nOptional clock stretching\n•\n1-byte buffer with DMA capability\n•\nConfigurable PEC (packet error checking) generation or verification:\n–\nPEC value can be transmitted as last byte in Tx mode\n–\nPEC error checking for last received byte\n•\nSMBus 2.0 Compatibility:\n–\n25 ms clock low timeout delay\n–\n10 ms master cumulative clock low extend time\n–\n25 ms slave cumulative clock low extend time\n–\nHardware PEC generation/verification with ACK control\n–\nAddress Resolution Protocol (ARP) supported\n•\nPMBus Compatibility\nNote:\nSome of the above features may not be available in certain products. The user should refer \nto the product data sheet, to identify the specific features supported by the I2C interface \nimplementation.\n27.3 \nI2C functional description\nIn addition to receiving and transmitting data, this interface converts it from serial to parallel \nformat and vice versa. The interrupts are enabled or disabled by software. The interface is \nconnected to the I2C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected \nwith a standard (up to 100 kHz) or fast (up to 400 kHz) I2C bus. \n27.3.1 \nMode selection\nThe interface can operate in one of the four following modes:\n•\nSlave transmitter\n•\nSlave receiver\n•\nMaster transmitter\n•\nMaster receiver\nBy default, it operates in slave mode. The interface automatically switches from slave to \nmaster, after it generates a START condition and from master to slave, if an arbitration loss \nor a Stop generation occurs, allowing multimaster capability.\nCommunication flow\nIn Master mode, the I2C interface initiates a data transfer and generates the clock signal. A \nserial data transfer always begins with a start condition and ends with a stop condition. Both \nstart and stop conditions are generated in master mode by software.\nIn Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and \nthe General Call address. The General Call address detection may be enabled or disabled \nby software. \n\n\n<>\n\nInter-integrated circuit (I2C) interface\nRM0090\n844/1757\nRM0090 Rev 21\nData and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the \nstart condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is \nalways transmitted in Master mode. \nA 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must \nsend an acknowledge bit to the transmitter. Refer to Figure 238.\nFigure 238. I2C bus protocol\nAcknowledge may be enabled or disabled by software. The I2C interface addresses (dual \naddressing 7-bit/ 10-bit and/or general call address) can be selected by software. \nThe block diagram of the I2C interface is shown in Figure 239. \nMS19854V1\nSDA\nSCL\nStart\ncondition\nStop\ncondition\nMSB\nACK\n1\n2\n8\n9\n\n\n<>\n\nRM0090 Rev 21\n845/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nFigure 239. I2C block diagram for STM32F40x/41x \nData shift register\nComparator\nOwn address register\nClock control \nStatus registers \nControl registers \nControl \nClock\ncontrol\nData\ncontrol\nSCL\nlogic\nDual address register\nData register\nPEC register\nInterrupts\nPEC calculation\nSMBA\nSDA\nRegister (CCR)\n(SR1&SR2)\n(CR1&CR2)\nDMA requests & ACK\nMS30035V1\nNoise\nfilter\nNoise\nfilter\n\n\n<>\n\nInter-integrated circuit (I2C) interface\nRM0090\n846/1757\nRM0090 Rev 21\nFigure 240. I2C block diagram for STM32F42x/43x\n1.\nSMBA is an optional signal in SMBus mode. This signal is not applicable if SMBus is disabled.\n27.3.2 \nI2C slave mode\nBy default the I2C interface operates in Slave mode. To switch from default Slave mode to \nMaster mode a Start condition generation is needed.\nThe peripheral input clock must be programmed in the I2C_CR2 register in order to \ngenerate correct timings. The peripheral input clock frequency must be at least:\n•\n2 MHz in Sm mode\n•\n4 MHz in Fm mode \nAs soon as a start condition is detected, the address is received from the SDA line and sent \nto the shift register. Then it is compared with the address of the interface (OAR1) and with \nOAR2 (if ENDUAL=1) or the General Call address (if ENGC = 1). \nNote:\nIn 10-bit addressing mode, the comparison includes the header sequence (11110xx0), \nwhere xx denotes the two most significant bits of the address.\nData shift register\nComparator\nOwn address register\nClock control \nStatus registers \nControl registers \nControl \nClock\ncontrol\nData\ncontrol\nSCL\nlogic\nDual address register\nData register\nPEC register\nInterrupts\nPEC calculation\nSMBA\nSDA\nRegister (CCR)\n(SR1&SR2)\n(CR1&CR2)\nDMA requests & ACK\nMS30035V1\nNoise\nfilter\nNoise\nfilter\n\n\n<>\n\nRM0090 Rev 21\n847/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nHeader or address not matched: the interface ignores it and waits for another Start \ncondition.\nHeader matched (10-bit mode only): the interface generates an acknowledge pulse if the \nACK bit is set and waits for the 8-bit slave address.\nAddress matched: the interface generates in sequence:\n•\nAn acknowledge pulse if the ACK bit is set\n•\nThe ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit is \nset. \n•\nIf ENDUAL=1, the software has to read the DUALF bit to check which slave address \nhas been acknowledged.\nIn 10-bit mode, after receiving the address sequence the slave is always in Receiver mode. \nIt enters Transmitter mode on receiving a repeated Start condition followed by the header \nsequence with matching address bits and the least significant bit set (11110xx1).\nThe TRA bit indicates whether the slave is in Receiver or Transmitter mode.\nSlave transmitter\nFollowing the address reception and after clearing ADDR, the slave sends bytes from the \nDR register to the SDA line via the internal shift register.\nThe slave stretches SCL low until ADDR is cleared and DR filled with the data to be sent \n(see Figure 241 Transfer sequencing EV1 EV3).\nWhen the acknowledge pulse is received: \n•\nThe TxE bit is set by hardware with an interrupt if the ITEVFEN and the ITBUFEN bits \nare set.\nIf TxE is set and some data were not written in the I2C_DR register before the end of the \nnext data transmission, the BTF bit is set and the interface waits until BTF is cleared by a \nread to I2C_SR1 followed by a write to the I2C_DR register, stretching SCL low.\n\n\n<>\n\nInter-integrated circuit (I2C) interface\nRM0090\n848/1757\nRM0090 Rev 21\nFigure 241. Transfer sequence diagram for slave transmitter\n1.\nThe EV1 and EV3_1 events stretch SCL low until the end of the corresponding software sequence.\n2.\nThe EV3 event stretches SCL low if the software sequence is not completed before the end of the next byte \ntransmission.\nSlave receiver\nFollowing the address reception and after clearing ADDR, the slave receives bytes from the \nSDA line into the DR register via the internal shift register. After each byte the interface \ngenerates in sequence:\n•\nAn acknowledge pulse if the ACK bit is set\n•\nThe RxNE bit is set by hardware and an interrupt is generated if the ITEVFEN and \nITBUFEN bit is set.\nIf RxNE is set and the data in the DR register is not read before the end of the next data \nreception, the BTF bit is set and the interface waits until BTF is cleared by a read from the \nI2C_DR register, stretching SCL low (see Figure 242 Transfer sequencing).\n7-bit slave transmitter\n10-bit slave transmitter\nLegend: S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge,\nEVx= Event (with interrupt if ITEVFEN=1)\nEV1: ADDR=1, cleared by reading SR1 followed by reading SR2\nEV3-1: TxE=1, shift register empty, data register empty, write Data1 in DR.\nEV3: TxE=1, shift register not empty, data register empty, cleared by writing DR\n \nEV3-2: AF=1; AF is cleared by writing ‘0’ in AF bit of SR1 register.\nS\nAddress\nA\nData1\nA\nData2\nA\n.....\nDataN\nNA\nP\nEV1\nEV3-1 EV3\nEV3\nEV3\nEV3-2\nS\nHeader\nA\nAddress\nA\nEV1\nSr\nHeader\nA\nData1\nA\n.... DataN\nNA\nP\nEV1\nEV3_1\nEV3\nEV3\nEV3-2\nai18209\n\n\n<>\n\nRM0090 Rev 21\n849/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nFigure 242. Transfer sequence diagram for slave receiver\n1.\nThe EV1 event stretches SCL low until the end of the corresponding software sequence.\n2.\nThe EV2 event stretches SCL low if the software sequence is not completed before the end of the next byte \nreception.\n3.\nAfter checking the SR1 register content, the user should perform the complete clearing sequence for each \nflag found set.\nThus, for ADDR and STOPF flags, the following sequence is required inside the I2C interrupt routine:\nREAD SR1\nif (ADDR == 1) {READ SR1; READ SR2}\nif (STOPF == 1) {READ SR1; WRITE CR1}\nThe purpose is to make sure that both ADDR and STOPF flags are cleared if both are found set.\nClosing slave communication\nAfter the last data byte is transferred a Stop Condition is generated by the master. The \ninterface detects this condition and sets:\n•\nThe STOPF bit and generates an interrupt if the ITEVFEN bit is set.\nThe STOPF bit is cleared by a read of the SR1 register followed by a write to the CR1 \nregister (see EV4 in Figure 242).\n27.3.3 \nI2C master mode\nIn Master mode, the I2C interface initiates a data transfer and generates the clock signal. A \nserial data transfer always begins with a Start condition and ends with a Stop condition. \nMaster mode is selected as soon as the Start condition is generated on the bus with a \nSTART bit.\nThe following is the required sequence in master mode.\n•\nProgram the peripheral input clock in I2C_CR2 register in order to generate correct \ntimings\n•\nConfigure the clock control registers\n•\nConfigure the rise time register\n•\nProgram the I2C_CR1 register to enable the peripheral\n•\nSet the START bit in the I2C_CR1 register to generate a Start condition\nThe peripheral input clock frequency must be at least:\n•\n2 MHz in Sm mode \n•\n4 MHz in Fm mode\n7-bit slave receiver\n10-bit slave receiver\nLegend: S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge, \nEVx= Event (with interrupt if ITEVFEN=1)\nEV1: ADDR=1, cleared by reading SR1 followed by reading SR2\nEV2: RxNE=1 cleared by reading DR register.\nEV4: STOPF=1, cleared by reading SR1 register followed by writing to the CR1 register\nS\nAddress\nA\nData1\nA\nData2\nA\n.....\nDataN\nA\nP\nEV1\nEV2\nEV2\nEV2\nEV4\nS\nHeader\nA\nAddress\nA\nData1\nA\n.....\nDataN\nA\nP\nEV1\nEV2\nEV2\nEV4\nai18208\n\n\n<>\n\nInter-integrated circuit (I2C) interface\nRM0090\n850/1757\nRM0090 Rev 21\nSCL master clock generation\nThe CCR bits are used to generate the high and low level of the SCL clock, starting from the \ngeneration of the rising and falling edge (respectively). As a slave may stretch the SCL line, \nthe peripheral checks the SCL input from the bus at the end of the time programmed in \nTRISE bits after rising edge generation. \n•\nIf the SCL line is low, it means that a slave is stretching the bus, and the high level \ncounter stops until the SCL line is detected high. This allows to guarantee the minimum \nHIGH period of the SCL clock parameter. \n•\nIf the SCL line is high, the high level counter keeps on counting.\nIndeed, the feedback loop from the SCL rising edge generation by the peripheral to the SCL \nrising edge detection by the peripheral takes time even if no slave stretches the clock. This \nloopback duration is linked to the SCL rising time (impacting SCL VIH input detection), plus \ndelay due to the noise filter present on the SCL input path, plus delay due to internal SCL \ninput synchronization with APB clock. The maximum time used by the feedback loop is \nprogrammed in the TRISE bits, so that the SCL frequency remains stable whatever the SCL \nrising time.\nStart condition\nSetting the START bit causes the interface to generate a Start condition and to switch to \nMaster mode (MSL bit set) when the BUSY bit is cleared.\nNote:\nIn master mode, setting the START bit causes the interface to generate a ReStart condition \nat the end of the current byte transfer.\nOnce the Start condition is sent:\n•\nThe SB bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.\nThen the master waits for a read of the SR1 register followed by a write in the DR register \nwith the Slave address (see Figure 243 and Figure 244 Transfer sequencing EV5).\nSlave address transmission\nThen the slave address is sent to the SDA line via the internal shift register.\n•\nIn 10-bit addressing mode, sending the header sequence causes the following event:\n–\nThe ADD10 bit is set by hardware and an interrupt is generated if the ITEVFEN bit \nis set. \nThen the master waits for a read of the SR1 register followed by a write in the DR \nregister with the second address byte (see Figure 243 and Figure 244 Transfer \nsequencing). \n–\nThe ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit \nis set. \nThen the master waits for a read of the SR1 register followed by a read of the SR2 \nregister (see Figure 243 and Figure 244 Transfer sequencing).\n•\nIn 7-bit addressing mode, one address byte is sent.\nAs soon as the address byte is sent,\n–\nThe ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit \nis set. \nThen the master waits for a read of the SR1 register followed by a read of the SR2 \nregister (see Figure 243 and Figure 244 Transfer sequencing). \n\n\n<>\n\nRM0090 Rev 21\n851/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nThe master can decide to enter Transmitter or Receiver mode depending on the LSB of the \nslave address sent.\n•\nIn 7-bit addressing mode,\n–\nTo enter Transmitter mode, a master sends the slave address with LSB reset.\n–\nTo enter Receiver mode, a master sends the slave address with LSB set.\n•\nIn 10-bit addressing mode,\n–\nTo enter Transmitter mode, a master sends the header (11110xx0) and then the \nslave address, (where xx denotes the two most significant bits of the address).\n–\nTo enter Receiver mode, a master sends the header (11110xx0) and then the \nslave address. Then it should send a repeated Start condition followed by the \nheader (11110xx1), (where xx denotes the two most significant bits of the \naddress).\nThe TRA bit indicates whether the master is in Receiver or Transmitter mode.\nMaster transmitter\nFollowing the address transmission and after clearing ADDR, the master sends bytes from \nthe DR register to the SDA line via the internal shift register.\nThe master waits until the first data byte is written into I2C_DR (see Figure 243 Transfer \nsequencing EV8_1).\nWhen the acknowledge pulse is received, the TxE bit is set by hardware and an interrupt is \ngenerated if the ITEVFEN and ITBUFEN bits are set.\nIf TxE is set and a data byte was not written in the DR register before the end of the last data \ntransmission, BTF is set and the interface waits until BTF is cleared by a write to I2C_DR, \nstretching SCL low.\nClosing the communication\nAfter the last byte is written to the DR register, the STOP bit is set by software to generate a \nStop condition (see Figure 243 Transfer sequencing EV8_2). The interface automatically \ngoes back to slave mode (MSL bit cleared).\nNote:\nStop condition should be programmed during EV8_2 event, when either TxE or BTF is set.\n\n\n<>\n\nInter-integrated circuit (I2C) interface\nRM0090\n852/1757\nRM0090 Rev 21\nFigure 243. Transfer sequence diagram for master transmitter\n1.\nThe EV5, EV6, EV9, EV8_1 and EV8_2 events stretch SCL low until the end of the corresponding software sequence.\n2.\nThe EV8 event stretches SCL low if the software sequence is not complete before the end of the next byte transmission.\nMaster receiver\nFollowing the address transmission and after clearing ADDR, the I2C interface enters \nMaster Receiver mode. In this mode the interface receives bytes from the SDA line into the \nDR register via the internal shift register. After each byte the interface generates in \nsequence:\n1.\nAn acknowledge pulse if the ACK bit is set\n2. \nThe RxNE bit is set and an interrupt is generated if the ITEVFEN and ITBUFEN bits are \nset (see Figure 244 Transfer sequencing EV7).\nIf the RxNE bit is set and the data in the DR register is not read before the end of the last \ndata reception, the BTF bit is set by hardware and the interface waits until BTF is cleared by \na read in the DR register, stretching SCL low. \nClosing the communication\nThe master sends a NACK for the last byte received from the slave. After receiving this \nNACK, the slave releases the control of the SCL and SDA lines. Then the master can send \na Stop/Restart condition.\n1.\nTo generate the nonacknowledge pulse after the last received data byte, the ACK bit \nmust be cleared just after reading the second last data byte (after second last RxNE \nevent).\n2. \nIn order to generate the Stop/Restart condition, software must set the STOP/START bit \nafter reading the second last data byte (after the second last RxNE event). \n3. \nIn case a single byte has to be received, the Acknowledge disable is made during EV6 \n(before ADDR flag is cleared) and the STOP condition generation is made after EV6.\nAfter the Stop condition generation, the interface goes automatically back to slave mode \n(MSL bit cleared).\n7-bit master transmitter\n10-bit master transmitter\nLegend: S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge, \nEVx= Event (with interrupt if ITEVFEN = 1)\nEV5: SB=1, cleared by reading SR1 register followed by writing DR register with Address.\nEV6: ADDR=1, cleared by reading SR1 register followed by reading SR2.\nEV8_1: TxE=1, shift register empty, data register empty, write Data1 in DR.\nEV8: TxE=1, shift register not empty, data register empty, cleared by writing DR register\n.\nEV8_2: TxE=1, BTF = 1, Program Stop request. TxE and BTF are cleared by hardware by the Stop condition\nEV9: ADD10=1, cleared by reading SR1 register followed by writing DR register.\nS\nAddress\nA\nData1\nA\nData2\nA\n.....\nDataN\nA\nP\nEV5\nEV6\nEV8_1\nEV8\nEV8\nEV8\nEV8_2\nS\nHeader\nA\nAddress\nA\nData1\nA\n.....\nDataN\nA\nP\nEV5\nEV9\nEV6\nEV8_1\nEV8\nEV8\nEV8_2\nai18210\n\n\n<>\n\nRM0090 Rev 21\n853/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nFigure 244. Transfer sequence diagram for master receiver \n1.\nIf a single byte is received, it is NA.\n2.\nThe EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence.\n3.\nThe EV7 event stretches SCL low if the software sequence is not completed before the end of the next byte \nreception.\n4.\nThe EV7_1 software sequence must be completed before the ACK pulse of the current byte transfer.\n The procedures described below are recommended if the EV7-1 software sequence is not \ncompleted before the ACK pulse of the current byte transfer.\nThese procedures must be followed to make sure:\n•\nThe ACK bit is set low on time before the end of the last data reception\n•\nThe STOP bit is set high after the last data reception without reception of \nsupplementary data.\nFor 2-byte reception:\n•\nWait until ADDR = 1 (SCL stretched low until the ADDR flag is cleared)\n•\nSet ACK low, set POS high\n•\nClear ADDR flag\n•\nWait until BTF = 1 (Data 1 in DR, Data2 in shift register, SCL stretched low until a data \n1 is read)\n•\nSet STOP high\n•\nRead data 1 and 2\n7-bit master receiver\n10-bit master receiver\nLegend: S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge,\nEVx= Event (with interrupt if ITEVFEN=1)\nEV5: SB=1, cleared by reading SR1 register followed by writing DR register.\nEV6: ADDR=1, cleared by reading SR1 register followed by reading SR2. In 10-bit master receiver mode, this se-\nquence should be followed by writing CR2 with START = 1.\nEV7: RxNE=1 cleared by reading DR register.\nEV7_1: RxNE=1 cleared by reading DR register, program ACK=0 and STOP request\nEV9: ADD10=1, cleared by reading SR1 register followed by writing DR register.\nS\nAddress\nA\nData1\nA(1)\nData2\nA\n.....\nDataN\nNA\nP\nEV5\nEV6\nEV7\nEV7\nEV7_1\nEV7\nS\nHeader\nA\nAddress\nA\nEV5\nEV9\nEV6\nSr\nHeader\nA\nData1\nA(1)\n.....\nEV5\nEV6\nEV7\nData2\nA\nEV7\nDataN\nNA\nP\nEV7_1\nEV7\nai17540d\nIn case of the reception of 1 byte, the Acknowledge disable must be performed during EV6 event, i.e. before clearing ADDR flag.\n\n\n<>\n\nInter-integrated circuit (I2C) interface\nRM0090\n854/1757\nRM0090 Rev 21\nFor N >2 -byte reception, from N-2 data reception\n•\nWait until BTF = 1 (data N-2 in DR, data N-1 in shift register, SCL stretched low until \ndata N-2 is read)\n•\nSet ACK low\n•\nRead data N-2\n•\nWait until BTF = 1 (data N-1 in DR, data N in shift register, SCL stretched low until a \ndata N-1 is read)\n•\nSet STOP high\n•\nRead data N-1 and N\n27.3.4 \nError conditions\nThe following are the error conditions which may cause communication to fail.\nBus error (BERR)\nThis error occurs when the I2C interface detects an external Stop or Start condition during \nan address or a data transfer. In this case:\n•\nthe BERR bit is set and an interrupt is generated if the ITERREN bit is set\n•\nin Slave mode: data are discarded and the lines are released by hardware:\n–\nin case of a misplaced Start, the slave considers it is a restart and waits for an \naddress, or a Stop condition\n–\nin case of a misplaced Stop, the slave behaves like for a Stop condition and the \nlines are released by hardware\n•\nIn Master mode: the lines are not released and the state of the current transmission is \nnot affected. It is up to the software to abort or not the current transmission\nAcknowledge failure (AF)\nThis error occurs when the interface detects a nonacknowledge bit. In this case:\n•\nthe AF bit is set and an interrupt is generated if the ITERREN bit is set\n•\na transmitter which receives a NACK must reset the communication:\n–\nIf Slave: lines are released by hardware\n–\nIf Master: a Stop or repeated Start condition must be generated by software\nArbitration lost (ARLO)\nThis error occurs when the I2C interface detects an arbitration lost condition. In this case\n•\nthe ARLO bit is set by hardware (and an interrupt is generated if the ITERREN bit is \nset)\n•\nthe I2C Interface goes automatically back to slave mode (the MSL bit is cleared). When \nthe I2C loses the arbitration, it is not able to acknowledge its slave address in the same \ntransfer, but it can acknowledge it after a repeated Start from the winning master.\n•\nlines are released by hardware\n\n\n<>\n\nRM0090 Rev 21\n855/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nOverrun/underrun error (OVR)\nAn overrun error can occur in slave mode when clock stretching is disabled and the I2C \ninterface is receiving data. The interface has received a byte (RxNE=1) and the data in DR \nhas not been read, before the next byte is received by the interface. In this case,\n•\nThe last received byte is lost. \n•\nIn case of Overrun error, software should clear the RxNE bit and the transmitter should \nre-transmit the last received byte.\nUnderrun error can occur in slave mode when clock stretching is disabled and the I2C \ninterface is transmitting data. The interface has not updated the DR with the next byte \n(TxE=1), before the clock comes for the next byte. In this case,\n•\nThe same byte in the DR register is sent again.\n•\nThe user should make sure that data received on the receiver side during an underrun \nerror are discarded and that the next bytes are written within the clock low time \nspecified in the I2C bus standard.\nFor the first byte to be transmitted, the DR must be written after ADDR is cleared and before \nthe first SCL rising edge. If not possible, the receiver must discard the first data.\n27.3.5 \nProgrammable noise filter\nThe programmable noise filter is available on STM32F42xxx and STM32F43xxx devices \nonly.\nIn Fm mode, the I2C standard requires that spikes are suppressed to a length of 50 ns on \nSDA and SCL lines.\nAn analog noise filter is implemented in the SDA and SCL I/Os. This filter is enabled by \ndefault and can be disabled by setting the ANOFF bit in the I2C_FLTR register.\nA digital noise filter can be enabled by configuring the DNF[3:0] bits to a non-zero value. \nThis suppresses the spikes on SDA and SCL inputs with a length of up to DNF[3:0] * \nTPCLK1. \nEnabling the digital noise filter increases the SDA hold time by (DNF[3:0] +1)* TPCLK.\nTo be compliant with the maximum hold time of the I2C-bus specification version 2.1 \n(Thd:dat), the DNF bits must be programmed using the constraints shown in Table 123, and \nassuming that the analog filter is disabled.\nNote:\nDNF[3:0] must only be configured when the I2C is disabled (PE = 0). If the analog filter is \nalso enabled, the digital filter is added to the analog filter.\n \nTable 123. Maximum DNF[3:0] value to be compliant with Thd:dat(max)\nPCLK1 frequency\nMaximum DNF value\nSm mode\nFm mode\n2 <= FPCLK1 <= 5\n2\n0\n5 < FPCLK1 <= 10\n12\n0\n10 < FPCLK1 <= 20\n15\n1\n20 < FPCLK1 <= 30\n15\n7\n\n\n<>\n\nInter-integrated circuit (I2C) interface\nRM0090\n856/1757\nRM0090 Rev 21\nNote:\nFor each frequency range, the constraint is given based on the worst case which is the \nminimum frequency of the range. Greater DNF values can be used if the system can \nsupport maximum hold time violation.\n27.3.6 \nSDA/SCL line control\n•\nIf clock stretching is enabled:\n–\nTransmitter mode: If TxE=1 and BTF=1: the interface holds the clock line low \nbefore transmission to wait for the microcontroller to write the byte in the Data \nregister (both buffer and shift register are empty).\n–\nReceiver mode: If RxNE=1 and BTF=1: the interface holds the clock line low after \nreception to wait for the microcontroller to read the byte in the Data register (both \nbuffer and shift register are full).\n•\nIf clock stretching is disabled in Slave mode:\n–\nOverrun Error in case of RxNE=1 and no read of DR has been done before the \nnext byte is received. The last received byte is lost.\n–\nUnderrun Error in case TxE=1 and no write into DR has been done before the next \nbyte must be transmitted. The same byte is sent again.\n–\nWrite Collision not managed.\n27.3.7 \nSMBus\nIntroduction\nThe System Management Bus (SMBus) is a two-wire interface through which various \ndevices can communicate with each other and with the rest of the system. It is based on I2C \nprinciples of operation. SMBus provides a control bus for system and power management \nrelated tasks. A system may use SMBus to pass messages to and from devices instead of \ntoggling individual control lines. \nThe System Management Bus Specification refers to three types of devices. A slave is a \ndevice that is receiving or responding to a command. A master is a device that issues \ncommands, generates the clocks, and terminates the transfer. A host is a specialized \nmaster that provides the main interface to the system's CPU. A host must be a master-slave \nand must support the SMBus host notify protocol. Only one host is allowed in a system.\nSimilarities between SMBus and I2C\n•\n2-wire bus protocol (1 Clk, 1 Data) + SMBus Alert line optional\n•\nMaster-slave communication, Master provides clock\n•\nMulti master capability\n•\nSMBus data format similar to I2C 7-bit addressing format (Figure 238).\n30 < FPCLK1 <= 40\n15\n13\n40 < FPCLK1 <= 50\n15\n15\nTable 123. Maximum DNF[3:0] value to be compliant with Thd:dat(max) (continued)\nPCLK1 frequency\nMaximum DNF value\nSm mode\nFm mode\n\n\n<>\n\nRM0090 Rev 21\n857/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nDifferences between SMBus and I2C\nThe following table describes the differences between SMBus and I2C.\n \nSMBus application usage\nWith System Management Bus, a device can provide manufacturer information, tell the \nsystem what its model/part number is, save its state for a suspend event, report different \ntypes of errors, accept control parameters, and return its status. SMBus provides a control \nbus for system and power management related tasks. \nDevice identification\nAny device that exists on the System Management Bus as a slave has a unique address \ncalled the Slave Address. For the list of reserved slave addresses, refer to the SMBus \nspecification version. 2.0 (http://smbus.org/).\nBus protocols\nThe SMBus specification supports up to nine bus protocols. For more details of these \nprotocols and SMBus address types, refer to SMBus specification version. 2.0. These \nprotocols should be implemented by the user software.\nAddress resolution protocol (ARP)\nSMBus slave address conflicts can be resolved by dynamically assigning a new unique \naddress to each slave device. The Address Resolution Protocol (ARP) has the following \nattributes:\n•\nAddress assignment uses the standard SMBus physical layer arbitration mechanism\n•\nAssigned addresses remain constant while device power is applied; address retention \nthrough device power loss is also allowed\n•\nNo additional SMBus packet overhead is incurred after address assignment. (i.e. \nsubsequent accesses to assigned slave addresses have the same overhead as \naccesses to fixed address devices.)\n•\nAny SMBus master can enumerate the bus\nUnique device identifier (UDID)\nIn order to provide a mechanism to isolate each device for the purpose of address \nassignment, each device must implement a unique device identifier (UDID). \nTable 124. SMBus vs. I2C\nSMBus\nI2C\nMax. speed 100 kHz\nMax. speed 400 kHz\nMin. clock speed 10 kHz\nNo minimum clock speed\n35 ms clock low timeout\nNo timeout\nLogic levels are fixed\nLogic levels are VDD dependent\nDifferent address types (reserved, dynamic etc.)\n7-bit, 10-bit and general call slave address types\nDifferent bus protocols (quick command, process \ncall etc.)\nNo bus protocols\n\n\n<>\n\nInter-integrated circuit (I2C) interface\nRM0090\n858/1757\nRM0090 Rev 21\nFor the details on 128-bit UDID and more information on ARP, refer to SMBus specification \nversion 2.0.\nSMBus alert mode\nSMBus Alert is an optional signal with an interrupt line for devices that want to trade their \nability to master for a pin. SMBA is a wired-AND signal just as the SCL and SDA signals are. \nSMBA is used in conjunction with the SMBus General Call Address. Messages invoked with \nthe SMBus are two bytes long. \nA slave-only device can signal the host through SMBA that it wants to talk by setting ALERT \nbit in I2C_CR1 register. The host processes the interrupt and simultaneously accesses all \nSMBA devices through the Alert Response Address (known as ARA having a value 0001 \n100X). Only the device(s) which pulled SMBA low acknowledge the Alert Response \nAddress. This status is identified using SMBALERT Status flag in I2C_SR1 register. The \nhost performs a modified Receive Byte operation. The 7 bit device address provided by the \nslave transmit device is placed in the 7 most significant bits of the byte. The eighth bit can \nbe a zero or one.\nIf more than one device pulls SMBA low, the highest priority (lowest address) device wins \ncommunication rights via standard arbitration during the slave address transfer. After \nacknowledging the slave address the device must disengage its SMBA pull-down. If the \nhost still sees SMBA low when the message transfer is complete, it knows to read the ARA \nagain.\nA host which does not implement the SMBA signal may periodically access the ARA.\nFor more details on SMBus Alert mode, refer to SMBus specification version 2.0.\nTimeout error\nThere are differences in the timing specifications between I2C and SMBus.\nSMBus defines a clock low timeout, TIMEOUT of 35 ms. Also SMBus specifies TLOW: \nSEXT as the cumulative clock low extend time for a slave device. SMBus specifies TLOW: \nMEXT as the cumulative clock low extend time for a master device. For more details on \nthese timeouts, refer to SMBus specification version 2.0.\nThe status flag Timeout or Tlow Error in I2C_SR1 shows the status of this feature.\nHow to use the interface in SMBus mode\nTo switch from I2C mode to SMBus mode, the following sequence should be performed.\n•\nSet the SMBus bit in the I2C_CR1 register\n•\nConfigure the SMBTYPE and ENARP bits in the I2C_CR1 register as required for the \napplication \nIf you want to configure the device as a master, follow the Start condition generation \nprocedure in Section 27.3.3. Otherwise, follow the sequence in Section 27.3.2. \nThe application has to control the various SMBus protocols by software.\n•\nSMB Device Default Address acknowledged if ENARP=1 and SMBTYPE=0\n•\nSMB Host Header acknowledged if ENARP=1 and SMBTYPE=1\n•\nSMB Alert Response Address acknowledged if SMBALERT=1\n\n\n<>\n\nRM0090 Rev 21\n859/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\n27.3.8 \nDMA requests\nDMA requests (when enabled) are generated only for data transfer. DMA requests are \ngenerated by Data register becoming empty in transmission and Data register becoming full \nin reception. The DMA must be initialized and enabled before the I2C data transfer. The \nDMAEN bit must be set in the I2C_CR2 register before the ADDR event. In master mode or \nin slave mode when clock stretching is enabled, the DMAEN bit can also be set during the \nADDR event, before clearing the ADDR flag. The DMA request must be served before the \nend of the current byte transfer. When the number of data transfers which has been \nprogrammed for the corresponding DMA stream is reached, the DMA controller sends an \nEnd of Transfer EOT signal to the I2C interface and generates a Transfer Complete interrupt \nif enabled: \n•\nMaster transmitter: In the interrupt routine after the EOT interrupt, disable DMA \nrequests then wait for a BTF event before programming the Stop condition.\n•\nMaster receiver\n–\nWhen the number of bytes to be received is equal to or greater than two, the DMA \ncontroller sends a hardware signal, EOT_1, corresponding to the last but one data \nbyte (number_of_bytes – 1). If, in the I2C_CR2 register, the LAST bit is set, I2C \nautomatically sends a NACK after the next byte following EOT_1. The user can \ngenerate a Stop condition in the DMA Transfer Complete interrupt routine if \nenabled.\n–\nWhen a single byte must be received: the NACK must be programmed during EV6 \nevent, i.e. program ACK=0 when ADDR=1, before clearing ADDR flag. Then the \nuser can program the STOP condition either after clearing ADDR flag, or in the \nDMA Transfer Complete interrupt routine.\nTransmission using DMA\nDMA mode can be enabled for transmission by setting the DMAEN bit in the I2C_CR2 \nregister. Data are loaded from a Memory area configured using the DMA peripheral (refer to \nthe DMA specification) to the I2C_DR register whenever the TxE bit is set. To map a DMA \nstream x for I2C transmission (where x is the stream number), perform the following \nsequence:\n1.\nSet the I2C_DR register address in the DMA_SxPAR register. The data are moved to \nthis address from the memory after each TxE event.\n2. \nSet the memory address in the DMA_SxMA0R register (and in DMA_SxMA1R register \nin the case of a bouble buffer mode). The data are loaded into I2C_DR from this \nmemory after each TxE event.\n3. \nConfigure the total number of bytes to be transferred in the DMA_SxNDTR register. \nAfter each TxE event, this value is decremented.\n4. \nConfigure the DMA stream priority using the PL[0:1] bits in the DMA_SxCR register\n5. \nSet the DIR bit in the DMA_SxCR register and configure interrupts after half transfer or \nfull transfer depending on application requirements.\n6. \nActivate the stream by setting the EN bit in the DMA_SxCR register.\nWhen the number of data transfers which has been programmed in the DMA Controller \nregisters is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the \nI2C interface and the DMA generates an interrupt, if enabled, on the DMA stream interrupt \nvector.\nNote:\nDo not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for transmission.\n\n\n<>\n\nInter-integrated circuit (I2C) interface\nRM0090\n860/1757\nRM0090 Rev 21\nReception using DMA\nDMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register. \nData are loaded from the I2C_DR register to a Memory area configured using the DMA \nperipheral (refer to the DMA specification) whenever a data byte is received. To map a DMA \nstream x for I2C reception (where x is the stream number), perform the following sequence:\n1.\nSet the I2C_DR register address in DMA_SxPAR register. The data are moved from \nthis address to the memory after each RxNE event.\n2. \nSet the memory address in the DMA_SxMA0R register (and in DMA_SxMA1R register \nin the case of a bouble buffer mode). The data are loaded from the I2C_DR register to \nthis memory area after each RxNE event.\n3. \nConfigure the total number of bytes to be transferred in the DMA_SxNDTR register. \nAfter each RxNE event, this value is decremented.\n4. \nConfigure the stream priority using the PL[0:1] bits in the DMA_SxCR register\n5. \nReset the DIR bit and configure interrupts in the DMA_SxCR register after half transfer \nor full transfer depending on application requirements.\n6. \nActivate the stream by setting the EN bit in the DMA_SxCR register.\nWhen the number of data transfers which has been programmed in the DMA Controller \nregisters is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the \nI2C interface and DMA generates an interrupt, if enabled, on the DMA stream interrupt \nvector. \nNote:\nDo not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for reception.\n27.3.9 \nPacket error checking\nA PEC calculator has been implemented to improve the reliability of communication. The \nPEC is calculated by using the C(x) = x8 + x2 + x + 1 CRC-8 polynomial serially on each bit.\n•\nPEC calculation is enabled by setting the ENPEC bit in the I2C_CR1 register. PEC is a \nCRC-8 calculated on all message bytes including addresses and R/W bits.\n–\nIn transmission: set the PEC transfer bit in the I2C_CR1 register after the TxE \nevent corresponding to the last byte. The PEC is transferred after the last \ntransmitted byte.\n–\nIn reception: set the PEC bit in the I2C_CR1 register after the RxNE event \ncorresponding to the last byte so that the receiver sends a NACK if the next \nreceived byte is not equal to the internally calculated PEC. In case of Master-\nReceiver, a NACK must follow the PEC whatever the check result. The PEC must \n\n\n<>\n\nRM0090 Rev 21\n861/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nbe set before the ACK of the CRC reception in slave mode. It must be set when \nthe ACK is set low in master mode.\n•\nA PECERR error flag/interrupt is also available in the I2C_SR1 register.\n•\nIf DMA and PEC calculation are both enabled:-\n–\nIn transmission: when the I2C interface receives an EOT signal from the DMA \ncontroller, it automatically sends a PEC after the last byte.\n–\nIn reception: when the I2C interface receives an EOT_1 signal from the DMA \ncontroller, it automatically considers the next byte as a PEC and checks it. A DMA \nrequest is generated after PEC reception.\n•\nTo allow intermediate PEC transfers, a control bit is available in the I2C_CR2 register \n(LAST bit) to determine if it is really the last DMA transfer or not. If it is the last DMA \nrequest for a master receiver, a NACK is automatically sent after the last received byte.\n•\nPEC calculation is corrupted by an arbitration loss.\n27.4 \nI2C interrupts\nThe table below gives the list of I2C interrupt requests.\n \nNote:\nSB, ADDR, ADD10, STOPF, BTF, RxNE and TxE are logically OR-ed on the same interrupt \nchannel.\nBERR, ARLO, AF, OVR, PECERR, TIMEOUT and SMBALERT are logically OR-ed on the \nsame interrupt channel.\nTable 125. I2C Interrupt requests\nInterrupt event\nEvent flag\nEnable control bit\nStart bit sent (Master)\nSB\nITEVFEN\nAddress sent (Master) or Address matched (Slave)\nADDR\n10-bit header sent (Master)\nADD10\nStop received (Slave)\nSTOPF\nData byte transfer finished\nBTF\nReceive buffer not empty\nRxNE\nITEVFEN and ITBUFEN\nTransmit buffer empty\nTxE\nBus error\nBERR\nITERREN\nArbitration loss (Master)\nARLO\nAcknowledge failure\nAF\nOverrun/Underrun\nOVR\nPEC error\nPECERR\nTimeout/Tlow error\nTIMEOUT\nSMBus Alert\nSMBALERT\n\n\n<>\n\nInter-integrated circuit (I2C) interface\nRM0090\n862/1757\nRM0090 Rev 21\nFigure 245. I2C interrupt mapping diagram \nADDR\nSB\nADD10\nRxNE\nTxE\nBTF\nit_event\nARLO\nBERR\nAF\nOVR\nPECERR\nTIMEOUT\nSMBALERT\nITERREN\nit_error\nITEVFEN\nITBUFEN\nSTOPF\nMS42082V1\n\n\n<>\n\nRM0090 Rev 21\n863/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\n27.5 \nI2C debug mode\nWhen the microcontroller enters the debug mode (Cortex®-M4 with FPU core halted), the \nSMBUS timeout either continues to work normally or stops, depending on the \nDBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details, \nrefer to Section 38.16.2: Debug support for timers, watchdog, bxCAN and I2C.\n27.6 \nI2C registers\nRefer to Section 1.1 for a list of abbreviations used in register descriptions.\nThe peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).\n27.6.1 \nI2C Control register 1 (I2C_CR1)\nAddress offset: 0x00\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSWRST\nRes.\nALERT\nPEC\nPOS\nACK\nSTOP\nSTART\nNO\nSTRETCH\nENGC\nENPEC ENARP\nSMB\nTYPE\nRes.\nSMBU\nS\nPE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 SWRST: Software reset\nWhen set, the I2C is under reset state. Before resetting this bit, make sure the I2C lines are \nreleased and the bus is free.\n0: I2C Peripheral not under reset\n1: I2C Peripheral under reset state\nNote: This bit can be used to reinitialize the peripheral after an error or a locked state. As an \nexample, if the BUSY bit is set and remains locked due to a glitch on the bus, the \nSWRST bit can be used to exit from this state.\nBit 14 Reserved, must be kept at reset value\nBit 13 ALERT: SMBus alert\nThis bit is set and cleared by software, and cleared by hardware when PE=0.\n0: Releases SMBA pin high. Alert Response Address Header followed by NACK.\n1: Drives SMBA pin low. Alert Response Address Header followed by ACK.\nBit 12 PEC: Packet error checking\nThis bit is set and cleared by software, and cleared by hardware when PEC is transferred or \nby a START or Stop condition or when PE=0.\n0: No PEC transfer\n1: PEC transfer (in Tx or Rx mode)\nNote: PEC calculation is corrupted by an arbitration loss.\nBit 11 POS: Acknowledge/PEC Position (for data reception)\nThis bit is set and cleared by software and cleared by hardware when PE=0.\n0: ACK bit controls the (N)ACK of the current byte being received in the shift register. The \nPEC bit indicates that current byte in shift register is a PEC.\n1: ACK bit controls the (N)ACK of the next byte which is received in the shift register. The \nPEC bit indicates that the next byte in the shift register is a PEC\nNote: The POS bit must be used only in 2-byte reception configuration in master mode. It \nmust be configured before data reception starts, as described in the 2-byte reception \nprocedure recommended in Section : Master receiver on page 852.\n\n\n<>\n\nInter-integrated circuit (I2C) interface\nRM0090\n864/1757\nRM0090 Rev 21\nBit 10 ACK: Acknowledge enable\nThis bit is set and cleared by software and cleared by hardware when PE=0.\n0: No acknowledge returned\n1: Acknowledge returned after a byte is received (matched address or data)\nBit 9 STOP: Stop generation\nThe bit is set and cleared by software, cleared by hardware when a Stop condition is \ndetected, set by hardware when a timeout error is detected.\nIn Master mode:\n0: No Stop generation.\n1: Stop generation after the current byte transfer or after the current Start condition is sent.\nIn Slave mode:\n0: No Stop generation.\n1: Release the SCL and SDA lines after the current byte transfer. \nBit 8 START: Start generation\nThis bit is set and cleared by software and cleared by hardware when start is sent or PE=0.\nIn Master mode:\n0: No Start generation\n1: Repeated start generation\nIn Slave mode:\n0: No Start generation\n1: Start generation when the bus is free\nBit 7 NOSTRETCH: Clock stretching disable (Slave mode)\nThis bit is used to disable clock stretching in slave mode when ADDR or BTF flag is set, until \nit is reset by software.\n0: Clock stretching enabled\n1: Clock stretching disabled\nBit 6 ENGC: General call enable\n0: General call disabled. Address 00h is NACKed.\n1: General call enabled. Address 00h is ACKed.\nBit 5 ENPEC: PEC enable\n0: PEC calculation disabled\n1: PEC calculation enabled\nBit 4 ENARP: ARP enable\n0: ARP disable\n1: ARP enable\nSMBus Device default address recognized if SMBTYPE=0\nSMBus Host address recognized if SMBTYPE=1\nBit 3 SMBTYPE: SMBus type\n0: SMBus Device\n1: SMBus Host\n\n\n<>\n\nRM0090 Rev 21\n865/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nNote:\nWhen the STOP, START or PEC bit is set, the software must not perform any write access \nto I2C_CR1 before this bit is cleared by hardware. Otherwise there is a risk of setting a \nsecond STOP, START or PEC request.\n27.6.2 \nI2C Control register 2 (I2C_CR2)\nAddress offset: 0x04\nReset value: 0x0000\n \nBit 2 Reserved, must be kept at reset value\nBit 1 SMBUS: SMBus mode\n0: I2C mode\n1: SMBus mode\nBit 0 PE: Peripheral enable\n0: Peripheral disable\n1: Peripheral enable\nNote: If this bit is reset while a communication is on going, the peripheral is disabled at the \nend of the current communication, when back to IDLE state. \nAll bit resets due to PE=0 occur at the end of the communication.\nIn master mode, this bit must not be reset before the end of the communication.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLAST\nDMAEN ITBUFEN ITEVTEN ITERREN\nReserved\nFREQ[5:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:13 Reserved, must be kept at reset value\nBit 12 LAST: DMA last transfer\n0: Next DMA EOT is not the last transfer\n1: Next DMA EOT is the last transfer\nNote: This bit is used in master receiver mode to permit the generation of a NACK on the last \nreceived data.\nBit 11 DMAEN: DMA requests enable\n0: DMA requests disabled\n1: DMA request enabled when TxE=1 or RxNE =1\nBit 10 ITBUFEN: Buffer interrupt enable\n0: TxE = 1 or RxNE = 1 does not generate any interrupt.\n1: TxE = 1 or RxNE = 1 generates Event Interrupt (whatever the state of DMAEN)\n\n\n<>\n\nInter-integrated circuit (I2C) interface\nRM0090\n866/1757\nRM0090 Rev 21\nBit 9 ITEVTEN: Event interrupt enable\n0: Event interrupt disabled\n1: Event interrupt enabled\nThis interrupt is generated when:\n–\nSB = 1 (Master)\n–\nADDR = 1 (Master/Slave)\n–\nADD10= 1 (Master)\n–\nSTOPF = 1 (Slave)\n–\nBTF = 1 with no TxE or RxNE event\n–\nTxE event to 1 if ITBUFEN = 1\n–\nRxNE event to 1if ITBUFEN = 1\nBit 8 ITERREN: Error interrupt enable\n0: Error interrupt disabled\n1: Error interrupt enabled\nThis interrupt is generated when:\n–\nBERR = 1\n–\nARLO = 1\n–\nAF = 1\n–\nOVR = 1\n–\nPECERR = 1\n–\nTIMEOUT = 1\n–\nSMBALERT = 1\nBits 7:6 Reserved, must be kept at reset value\nBits 5:0 FREQ[5:0]: Peripheral clock frequency\nThe FREQ bits must be configured with the APB clock frequency value (I2C peripheral \nconnected to APB). The FREQ field is used by the peripheral to generate data setup and \nhold times compliant with the I2C specifications. The minimum allowed frequency is 2 MHz, \nthe maximum frequency is limited by the maximum APB frequency and cannot exceed \n50 MHz (peripheral intrinsic maximum limit).\n0b000000: Not allowed\n0b000001: Not allowed\n0b000010: 2 MHz\n...\n0b110010: 50 MHz\nHigher than 0b101010: Not allowed\n\n\n<>\n\nRM0090 Rev 21\n867/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\n27.6.3 \nI2C Own address register 1 (I2C_OAR1)\nAddress offset: 0x08\nReset value: 0x0000\n \n27.6.4 \nI2C Own address register 2 (I2C_OAR2)\nAddress offset: 0x0C\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nADD\nMODE\nReserved\nADD[9:8]\nADD[7:1]\nADD0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 ADDMODE Addressing mode (slave mode)\n0: 7-bit slave address (10-bit address not acknowledged)\n1: 10-bit slave address (7-bit address not acknowledged)\nBit 14\nShould always be kept at 1 by software.\nBits 13:10\nReserved, must be kept at reset value\nBits 9:8 ADD[9:8]: Interface address\n7-bit addressing mode: don’t care\n10-bit addressing mode: bits9:8 of address\nBits 7:1 ADD[7:1]: Interface address\nbits 7:1 of address\nBit 0 ADD0: Interface address\n7-bit addressing mode: don’t care\n10-bit addressing mode: bit 0 of address\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nADD2[7:1]\nENDUAL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value\nBits 7:1 ADD2[7:1]: Interface address\nbits 7:1 of address in dual addressing mode\nBit 0 ENDUAL: Dual addressing mode enable\n0: Only OAR1 is recognized in 7-bit addressing mode\n1: Both OAR1 and OAR2 are recognized in 7-bit addressing mode\n\n\n<>\n\nInter-integrated circuit (I2C) interface\nRM0090\n868/1757\nRM0090 Rev 21\n27.6.5 \nI2C Data register (I2C_DR)\nAddress offset: 0x10\nReset value: 0x0000\n \n27.6.6 \nI2C Status register 1 (I2C_SR1)\nAddress offset: 0x14\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDR[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value\nBits 7:0 DR[7:0] 8-bit data register\nByte received or to be transmitted to the bus.\n– Transmitter mode: Byte transmission starts automatically when a byte is written in the DR \nregister. A continuous transmit stream can be maintained if the next data to be transmitted is \nput in DR once the transmission is started (TxE=1)\n– Receiver mode: Received byte is copied into DR (RxNE=1). A continuous transmit stream \ncan be maintained if DR is read before the next data byte is received (RxNE=1).\nNote: In slave mode, the address is not copied into DR.\nWrite collision is not managed (DR can be written if TxE=0).\nIf an ARLO event occurs on ACK pulse, the received byte is not copied into DR and so \ncannot be read.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSMB\nALERT\nTIME\nOUT\nRes.\nPEC\nERR\nOVR\nAF\nARLO\nBERR\nTxE\nRxNE\nRes.\nSTOPF\nADD10\nBTF\nADDR\nSB\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nr\nr\nr\nr\nr\nr\nr\nBit 15 SMBALERT: SMBus alert \nIn SMBus host mode:\n0: no SMBALERT\n1: SMBALERT event occurred on pin\nIn SMBus slave mode:\n0: no SMBALERT response address header\n1: SMBALERT response address header to SMBALERT LOW received\n– Cleared by software writing 0, or by hardware when PE=0.\n\n\n<>\n\nRM0090 Rev 21\n869/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nBit 14 TIMEOUT: Timeout or Tlow error \n0: No timeout error\n1: SCL remained LOW for 25 ms (Timeout)\nor\nMaster cumulative clock low extend time more than 10 ms (Tlow:mext)\nor\nSlave cumulative clock low extend time more than 25 ms (Tlow:sext)\n– When set in slave mode: slave resets the communication and lines are released by \nhardware\n– When set in master mode: Stop condition sent by hardware\n– Cleared by software writing 0, or by hardware when PE=0.\nNote: This functionality is available only in SMBus mode.\nBit 13 Reserved, must be kept at reset value\nBit 12 PECERR: PEC Error in reception\n0: no PEC error: receiver returns ACK after PEC reception (if ACK=1)\n1: PEC error: receiver returns NACK after PEC reception (whatever ACK)\n– Cleared by software writing 0, or by hardware when PE=0.\nNote: When the received CRC is wrong, PECERR is not set in slave mode if the PEC control \nbit is not set before the end of the CRC reception. Nevertheless, reading the PEC value \ndetermines whether the received CRC is right or wrong.\nBit 11 OVR: Overrun/Underrun\n0: No overrun/underrun\n1: Overrun or underrun\n– Set by hardware in slave mode when NOSTRETCH=1 and:\n– In reception when a new byte is received (including ACK pulse) and the DR register has not \nbeen read yet. New received byte is lost.\n– In transmission when a new byte should be sent and the DR register has not been written \nyet. The same byte is sent twice.\n– Cleared by software writing 0, or by hardware when PE=0.\nNote: If the DR write occurs very close to SCL rising edge, the sent data is unspecified and a \nhold timing error occurs\nBit 10 AF: Acknowledge failure\n0: No acknowledge failure\n1: Acknowledge failure\n– Set by hardware when no acknowledge is returned. \n– Cleared by software writing 0, or by hardware when PE=0.\nBit 9 ARLO: Arbitration lost (master mode) \n0: No Arbitration Lost detected\n1: Arbitration Lost detected\nSet by hardware when the interface loses the arbitration of the bus to another master\n– Cleared by software writing 0, or by hardware when PE=0.\nAfter an ARLO event the interface switches back automatically to Slave mode (MSL=0). \nNote: In SMBUS, the arbitration on the data in slave mode occurs only during the data phase, \nor the acknowledge transmission (not on the address acknowledge).\n\n\n<>\n\nInter-integrated circuit (I2C) interface\nRM0090\n870/1757\nRM0090 Rev 21\nBit 8 BERR: Bus error \n0: No misplaced Start or Stop condition\n1: Misplaced Start or Stop condition\n– Set by hardware when the interface detects an SDA rising or falling edge while SCL is high, \noccurring in a non-valid position during a byte transfer.\n– Cleared by software writing 0, or by hardware when PE=0.\nBit 7 TxE: Data register empty (transmitters) \n0: Data register not empty\n1: Data register empty\n– Set when DR is empty in transmission. TxE is not set during address phase.\n– Cleared by software writing to the DR register or by hardware after a start or a stop condition \nor when PE=0.\nTxE is not set if either a NACK is received, or if next byte to be transmitted is PEC (PEC=1)\nNote: TxE is not cleared by writing the first data being transmitted, or by writing data when \nBTF is set, as in both cases the data register is still empty.\nBit 6 RxNE: Data register not empty (receivers)\n0: Data register empty\n1: Data register not empty\n– Set when data register is not empty in receiver mode. RxNE is not set during address phase.\n– Cleared by software reading or writing the DR register or by hardware when PE=0.\nRxNE is not set in case of ARLO event.\nNote: RxNE is not cleared by reading data when BTF is set, as the data register is still full.\nBit 5 Reserved, must be kept at reset value\nBit 4 STOPF: Stop detection (slave mode) \n0: No Stop condition detected\n1: Stop condition detected\n– Set by hardware when a Stop condition is detected on the bus by the slave after an \nacknowledge (if ACK=1). \n– Cleared by software reading the SR1 register followed by a write in the CR1 register, or by \nhardware when PE=0\nNote: The STOPF bit is not set after a NACK reception.\nIt is recommended to perform the complete clearing sequence (READ SR1 then \nWRITE CR1) after the STOPF is set. Refer to Figure 242.\nBit 3 ADD10: 10-bit header sent (Master mode) \n0: No ADD10 event occurred.\n1: Master has sent first address byte (header).\n– Set by hardware when the master has sent the first byte in 10-bit address mode. \n– Cleared by software reading the SR1 register followed by a write in the DR register of the \nsecond address byte, or by hardware when PE=0.\nNote: ADD10 bit is not set after a NACK reception\n\n\n<>\n\nRM0090 Rev 21\n871/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\n27.6.7 \nI2C Status register 2 (I2C_SR2)\nAddress offset: 0x18\nReset value: 0x0000\nNote:\nReading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was \nset after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found \nset in I2C_SR1 or when the STOPF bit is cleared.\n \nBit 2 BTF: Byte transfer finished\n0: Data byte transfer not done\n1: Data byte transfer succeeded\n– Set by hardware when NOSTRETCH=0 and: \n– In reception when a new byte is received (including ACK pulse) and DR has not been read \nyet (RxNE=1).\n– In transmission when a new byte should be sent and DR has not been written yet (TxE=1). \n– Cleared by software by either a read or write in the DR register or by hardware after a start or \na stop condition in transmission or when PE=0.\nNote: The BTF bit is not set after a NACK reception\nThe BTF bit is not set if next byte to be transmitted is the PEC (TRA=1 in I2C_SR2 \nregister and PEC=1 in I2C_CR1 register)\nBit 1 ADDR: Address sent (master mode)/matched (slave mode)\nThis bit is cleared by software reading SR1 register followed reading SR2, or by hardware \nwhen PE=0.\nAddress matched (Slave)\n0: Address mismatched or not received.\n1: Received address matched.\n– Set by hardware as soon as the received slave address matched with the OAR registers \ncontent or a general call or a SMBus Device Default Address or SMBus Host or SMBus Alert \nis recognized. (when enabled depending on configuration).\nNote: In slave mode, it is recommended to perform the complete clearing sequence (READ \nSR1 then READ SR2) after ADDR is set. Refer to Figure 242.\nAddress sent (Master)\n0: No end of address transmission\n1: End of address transmission\n– For 10-bit addressing, the bit is set after the ACK of the 2nd byte.\n– For 7-bit addressing, the bit is set after the ACK of the byte.\nNote: ADDR is not set after a NACK reception\nBit 0 SB: Start bit (Master mode)\n0: No Start condition\n1: Start condition generated.\n– Set when a Start condition generated.\n– Cleared by software by reading the SR1 register followed by writing the DR register, or by \nhardware when PE=0\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPEC[7:0]\nDUALF\nSMB\nHOST\nSMBDE\nFAULT\nGEN\nCALL\nRes.\nTRA\nBUSY\nMSL\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n\n\n<>\n\nInter-integrated circuit (I2C) interface\nRM0090\n872/1757\nRM0090 Rev 21\n \nNote:\nReading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was \nset after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found \nset in I2C_SR1 or when the STOPF bit is cleared.\nBits 15:8 PEC[7:0] Packet error checking register\nThis register contains the internal PEC when ENPEC=1. \nBit 7 DUALF: Dual flag (Slave mode)\n0: Received address matched with OAR1\n1: Received address matched with OAR2\n– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.\nBit 6 SMBHOST: SMBus host header (Slave mode)\n0: No SMBus Host address\n1: SMBus Host address received when SMBTYPE=1 and ENARP=1.\n– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.\nBit 5 SMBDEFAULT: SMBus device default address (Slave mode) \n0: No SMBus Device Default address\n1: SMBus Device Default address received when ENARP=1\n– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.\nBit 4 GENCALL: General call address (Slave mode) \n0: No General Call\n1: General Call Address received when ENGC=1\n– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.\nBit 3 Reserved, must be kept at reset value\nBit 2 TRA: Transmitter/receiver\n0: Data bytes received\n1: Data bytes transmitted\nThis bit is set depending on the R/W bit of the address byte, at the end of total address \nphase.\nIt is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start \ncondition, loss of bus arbitration (ARLO=1), or when PE=0.\nBit 1 BUSY: Bus busy\n0: No communication on the bus\n1: Communication ongoing on the bus\n– Set by hardware on detection of SDA or SCL low \n– cleared by hardware on detection of a Stop condition. \nIt indicates a communication in progress on the bus. This information is still updated when \nthe interface is disabled (PE=0).\nBit 0 MSL: Master/slave\n0: Slave mode\n1: Master mode\n– Set by hardware as soon as the interface is in Master mode (SB=1). \n– Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration \n(ARLO=1), or by hardware when PE=0. \n\n\n<>\n\nRM0090 Rev 21\n873/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\n27.6.8 \nI2C Clock control register (I2C_CCR)\nAddress offset: 0x1C\nReset value: 0x0000\nNote:\nfPCLK1 must be at least 2 MHz to achieve Sm mode I²C frequencies. It must be at least 4 \nMHz to achieve Fm mode I²C frequencies. It must be a multiple of 10MHz to reach the \n400 kHz maximum I²C Fm mode clock.\nThe CCR register must be configured only when the I2C is disabled (PE = 0).\n \n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nF/S\nDUTY\nReserved\nCCR[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 F/S: I2C master mode selection\n0: Sm mode I2C\n1: Fm mode I2C\nBit 14 DUTY: Fm mode duty cycle \n0: Fm mode tlow/thigh = 2\n1: Fm mode tlow/thigh = 16/9 (see CCR)\nBits 13:12 Reserved, must be kept at reset value\nBits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode) \nControls the SCL clock in master mode.\nSm mode or SMBus:\nThigh = CCR * TPCLK1\nTlow = CCR * TPCLK1\nFm mode:\nIf DUTY = 0:\nThigh = CCR * TPCLK1\nTlow = 2 * CCR * TPCLK1\nIf DUTY = 1: \nThigh = 9 * CCR * TPCLK1\nTlow = 16 * CCR * TPCLK1\nFor instance: in Sm mode, to generate a 100 kHz SCL frequency: \nIf FREQ = 08, TPCLK1 = 125 ns so CCR must be programmed with 0x28\n(0x28 <=> 40d x 125 ns = 5000 ns.)\nNote: The minimum allowed value is 0x04, except in FAST DUTY mode where the minimum \nallowed value is 0x01\nthigh = tr(SCL) + tw(SCLH).\ntlow = tf(SCL) + tw(SCLL).\nWhere the I2C parameters below are part of the I2C standard specification.\n- tr(SCL) = SCL clock rise time from 30% to 70%.\n- tf(SCL) = SCL clock fall time from 70% to 30%.\n- tw(SCLH) = SCL clock high time measure at 70%.\n- tw(SCLL) = SCL clock low time measure at 30%.\nI2C communication speed, fSCL ~ 1/(thigh + tlow). The real frequency may differ due to \nthe analog noise filter input delay.\nThe CCR register must be configured only when the I2C is disabled (PE = 0).\n\n\n<>\n\nInter-integrated circuit (I2C) interface\nRM0090\n874/1757\nRM0090 Rev 21\n27.6.9 \nI2C TRISE register (I2C_TRISE)\nAddress offset: 0x20\nReset value: 0x0002 \n \n27.6.10 \nI2C FLTR register (I2C_FLTR)\nAddress offset: 0x24\nReset value: 0x0000\nThe I2C_FLTR is available on STM32F42xxx and STM32F43xxx only.\n \n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTRISE[5:0]\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:6 Reserved, must be kept at reset value\nBits 5:0 TRISE[5:0]: Maximum rise time in Fm/Sm mode (Master mode)\nThese bits should provide the maximum duration of the SCL feedback loop in master mode. \nThe purpose is to keep a stable SCL frequency whatever the SCL rising edge duration.\nThese bits must be programmed with the maximum SCL rise time given in the I2C bus \nspecification, incremented by 1.\nFor instance: in Sm mode, the maximum allowed SCL rise time is 1000 ns.\nIf, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 0x08 and TPCLK1 = 125 ns \ntherefore the TRISE[5:0] bits must be programmed with 09h.\n(1000 ns / 125 ns = 8 + 1)\nThe filter value can also be added to TRISE[5:0].\nIf the result is not an integer, TRISE[5:0] must be programmed with the integer part, in order \nto respect the tHIGH parameter.\nNote: TRISE[5:0] must be configured only when the I2C is disabled (PE = 0).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nANOFF\nDNF[3:0]\nrw\nrw\nrw\nrw\nrw\nBits 15:5 Reserved, must be kept at reset value\nBit 4 ANOFF: Analog noise filter OFF\n0: Analog noise filter enable\n1: Analog noise filter disable\nNote: ANOFF must be configured only when the I2C is disabled (PE = 0).\nBits 3:0 DNF[3:0]: Digital noise filter\nThese bits are used to configure the digital noise filter on SDA and SCL inputs. The digital filter \nsuppresses the spikes with a length of up to DNF[3:0] * TPCLK1.\n0000: Digital noise filter disable\n0001: Digital noise filter enabled and filtering capability up to 1* TPCLK1.\n...\n1111: Digital noise filter enabled and filtering capability up to 15* TPCLK1.\nNote: DNF[3:0] must be configured only when the I2C is disabled (PE = 0). If the analog filter \nis also enabled, the digital filter is added to the analog filter.\n\n\n<>\n\nRM0090 Rev 21\n875/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\n27.6.11 \nI2C register map\nThe table below provides the I2C register map and reset values. \n \nRefer to Section 2.3: Memory map for the register boundary addresses table.\nTable 126. I2C register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nI2C_CR1\nReserved\nSWRST\nReserved\nALERT\nPEC\nPOS\nACK\nSTOP\nSTART\nNOSTRETCH\nENGC\nENPEC\nENARP\nSMBTYPE\nReserved\nSMBUS\nPE\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nI2C_CR2\nReserved\nLAST\nDMAEN\nITBUFEN\nITEVTEN\nITERREN\nReserved\nFREQ[5:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nI2C_OAR1\nReserved\nADDMODE\nReserved\nADD[9:8]\nADD[7:1]\nADD0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nI2C_OAR2\nReserved\nADD2[7:1]\nENDUAL\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nI2C_DR\nReserved\nDR[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nI2C_SR1\nReserved\nSMBALERT\nTIMEOUT\nReserved\nPECERR\nOVR\nAF\nARLO\nBERR\nTxE\nRxNE\nReserved\nSTOPF\nADD10\nBTF\nADDR\nSB\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x18\nI2C_SR2\nReserved\nPEC[7:0]\nDUALF\nSMBHOST\nSMBDEFAUL\nGENCALL\nReserved\nTRA\nBUSY\nMSL\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nI2C_CCR\nReserved\nF/S\nDUTY\nReserved\nCCR[11:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nI2C_TRISE\nReserved\nTRISE[5:0]\nReset value\n0\n0\n0\n0\n1\n0\n0x24\nI2C_FLTR\nReserved\nANOFF\nDNF[3:0]\nReset value\n0\n0\n0\n0\n0\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n876/1757\nRM0090 Rev 21\n28 \nSerial peripheral interface (SPI)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n28.1 \nSPI introduction\nThe SPI interface provides two main functions, supporting the SPI or the I2S audio protocol. \nBy default, the SPI function is selected. It is possible to switch the interface from SPI to I2S \nby software. \nThe serial peripheral interface (SPI) allows half/ full-duplex, synchronous, serial \ncommunication with external devices. The interface can be configured as the master and in \nthis case it provides the communication clock (SCK) to the external slave device. The \ninterface is also capable of operating in multimaster configuration.\nIt may be used for a variety of purposes, including simplex synchronous transfers on two \nlines with a possible bidirectional data line or reliable communication using CRC checking.\nThe I2S is also a synchronous serial communication interface. It can address four different \naudio standards including the I2S Philips standard, the MSB- and LSB-justified standards, \nand the PCM standard. It can operate as a slave or a master device in full-duplex mode \n(using 4 pins) or in half-duplex mode (using 3 pins). Master clock can be provided by the \ninterface to an external slave component when the I2S is configured as the communication \nmaster.\nWarning:\nSince some SPI1 and SPI3/I2S3 pins may be mapped onto \nsome pins used by the JTAG interface (SPI1_NSS onto JTDI, \nSPI3_NSS/I2S3_WS onto JTDI and SPI3_SCK/I2S3_CK onto \nJTDO), you may either:\n– map SPI/I2S onto other pins\n– disable the JTAG and use the SWD interface prior to \nconfiguring the pins listed as SPI I/Os (when debugging the \napplication) or\n– disable both JTAG/SWD interfaces (for standalone \napplications).\nFor more information on the configuration of the JTAG/SWD \ninterface pins, please refer to Section 8.3.2: I/O pin \nmultiplexer and mapping.\n\n\n<>\n\nRM0090 Rev 21\n877/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.2 \nSPI and I2S main features\n28.2.1 \nSPI features\n•\nFull-duplex synchronous transfers on three lines\n•\nSimplex synchronous transfers on two lines with or without a bidirectional data line\n•\n8- or 16-bit transfer frame format selection\n•\nMaster or slave operation\n•\nMultimaster mode capability\n•\n8 master mode baud rate prescalers (fPCLK/2 max.)\n•\nSlave mode frequency (fPCLK/2 max)\n•\nFaster communication for both master and slave\n•\nNSS management by hardware or software for both master and slave: dynamic change \nof master/slave operations\n•\nProgrammable clock polarity and phase\n•\nProgrammable data order with MSB-first or LSB-first shifting\n•\nDedicated transmission and reception flags with interrupt capability\n•\nSPI bus busy status flag\n•\nSPI TI mode \n•\nHardware CRC feature for reliable communication:\n–\nCRC value can be transmitted as last byte in Tx mode\n–\nAutomatic CRC error checking for last received byte\n•\nMaster mode fault, overrun and CRC error flags with interrupt capability\n•\n1-byte transmission and reception buffer with DMA capability: Tx and Rx requests\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n878/1757\nRM0090 Rev 21\n28.2.2 \nI2S features\n•\nFull duplex communication\n•\nHalf-duplex communication (only transmitter or receiver)\n•\nMaster or slave operations\n•\n8-bit programmable linear prescaler to reach accurate audio sample frequencies (from \n8 kHz to 192 kHz)\n•\nData format may be 16-bit, 24-bit or 32-bit\n•\nPacket frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, 32-bit data \nframe) by audio channel\n•\nProgrammable clock polarity (steady state)\n•\nUnderrun flag in slave transmission mode, overrun flag in reception mode (master and \nslave), and Frame Error flag in reception and transmission mode (slave only)\n•\n16-bit register for transmission and reception with one data register for both channel \nsides\n•\nSupported I2S protocols:\n–\nI2S Phillps standard\n–\nMSB-justified standard (left-justified)\n–\nLSB-justified standard (right-justified)\n–\nPCM standard (with short and long frame synchronization on 16-bit channel frame \nor 16-bit data frame extended to 32-bit channel frame)\n•\nData direction is always MSB first\n•\nDMA capability for transmission and reception (16-bit wide)\n•\nMaster clock may be output to drive an external audio component. Ratio is fixed at \n256 × FS (where FS is the audio sampling frequency)\n•\nBoth I2S (I2S2 and I2S3) have a dedicated PLL (PLLI2S) to generate an even more \naccurate clock.\n•\nI2S (I2S2 and I2S3) clock can be derived from an external clock mapped on the \nI2S_CKIN pin.\n\n\n<>\n\nRM0090 Rev 21\n879/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.3 \nSPI functional description\n28.3.1 \nGeneral description\nThe block diagram of the SPI is shown in Figure 246. \nFigure 246. SPI block diagram\nUsually, the SPI is connected to external devices through four pins:\n•\nMISO: Master In / Slave Out data. This pin can be used to transmit data in slave mode \nand receive data in master mode.\n•\nMOSI: Master Out / Slave In data. This pin can be used to transmit data in master \nmode and receive data in slave mode.\n•\nSCK: Serial Clock output for SPI masters and input for SPI slaves.\n•\nNSS: Slave select. This is an optional pin to select a slave device. This pin acts as a \n‘chip select’ to let the SPI master communicate with slaves individually and to avoid \ncontention on the data lines. Slave NSS inputs can be driven by standard IO ports on \nthe master device. The NSS pin may also be used as an output if enabled (SSOE bit) \nand driven low if the SPI is in master configuration. In this manner, all NSS pins from \ndevices connected to the Master NSS pin see a low level and become slaves when \nthey are configured in NSS hardware mode. When configured in master mode with \nNSS configured as an input (MSTR=1 and SSOE=0) and if NSS is pulled low, the SPI \nenters the master mode fault state: the MSTR bit is automatically cleared and the \ndevice is configured in slave mode (refer to Section 28.3.10). \nA basic example of interconnections between a single master and a single slave is \nillustrated in Figure 247.\nMS51604V1\nMOSI\nMISO\nBaud rate generator\nSCK\nMaster control logic\nCommunication control\nSPE\nBR2\nBR1\nBR0\nMSTR\nCPOL\nCPHA\nBR[2:0]\nRXNE\nIE\nLSB\nFIRST\nBIDI\nMODE\nBIDI\nOE\nBSY\nOVR\nMOD\nF\nRXNE\nTXE\nERR\nIE\nTXE\nIE\n0\n0\nDFF\n0\nSSOE\nCRCEN\n0\nRX\nONLY\nCRC\nNext\nCRC\nERR\n0\n1\nNSS\nSPI_CR1\nSPI_CR2\nSPI_SR\nTXDM\nAEN\nRXDM\nAEN\nAddress and data bus\nRead\nRx buffer\nShift register\nLSB first\nTx buffer\nWrite\nSSM\nSSI\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n880/1757\nRM0090 Rev 21\nFigure 247. Single master/ single slave application\n1.\nHere, the NSS pin is configured as an input.\nThe MOSI pins are connected together and the MISO pins are connected together. In this \nway data is transferred serially between master and slave (most significant bit first).\nThe communication is always initiated by the master. When the master device transmits \ndata to a slave device via the MOSI pin, the slave device responds via the MISO pin. This \nimplies full-duplex communication with both data out and data in synchronized with the \nsame clock signal (which is provided by the master device via the SCK pin).\nSlave select (NSS) pin management\nHardware or software slave select management can be set using the SSM bit in the \nSPI_CR1 register.\n•\nSoftware NSS management (SSM = 1)\nThe slave select information is driven internally by the value of the SSI bit in the \nSPI_CR1 register. The external NSS pin remains free for other application uses.\n•\nHardware NSS management (SSM = 0)\nTwo configurations are possible depending on the NSS output configuration (SSOE bit \nin register SPI_CR2).\n–\nNSS output enabled (SSM = 0, SSOE = 1)\nThis configuration is used only when the device operates in master mode. The \nNSS signal is driven low when the master starts the communication and is kept \nlow until the SPI is disabled. \n–\nNSS output disabled (SSM = 0, SSOE = 0)\nThis configuration allows multimaster capability for devices operating in master \nmode. For devices set as slave, the NSS pin acts as a classical NSS input: the \nslave is selected when NSS is low and deselected when NSS high.\n8-bit shift register\nSPI clock\ngenerator\n8-bit shift register\nMISO\nMOSI\nMOSI\nMISO\nSCK\nSCK\nSlave\nMaster\nNSS(1)\nNSS(1)\nVDD\nMSBit\nLSBit\nMSBit\nLSBit\nNot used if NSS is managed\n by software\nai14745\n\n\n<>\n\nRM0090 Rev 21\n881/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nClock phase and clock polarity\nFour possible timing relationships may be chosen by software, using the CPOL and CPHA \nbits in the SPI_CR1 register. The CPOL (clock polarity) bit controls the steady state value of \nthe clock when no data is being transferred. This bit affects both master and slave modes. If \nCPOL is reset, the SCK pin has a low-level idle state. If CPOL is set, the SCK pin has a \nhigh-level idle state.\nIf the CPHA (clock phase) bit is set, the second edge on the SCK pin (falling edge if the \nCPOL bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data are \nlatched on the occurrence of the second clock transition. If the CPHA bit is reset, the first \nedge on the SCK pin (falling edge if CPOL bit is set, rising edge if CPOL bit is reset) is the \nMSBit capture strobe. Data are latched on the occurrence of the first clock transition.\nThe combination of the CPOL (clock polarity) and CPHA (clock phase) bits selects the data \ncapture clock edge.\nFigure 248, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. \nThe diagram may be interpreted as a master or slave timing diagram where the SCK pin, \nthe MISO pin, the MOSI pin are directly connected between the master and the slave \ndevice.\nNote:\nPrior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit.\nMaster and slave must be programmed with the same timing mode.\nThe idle state of SCK must correspond to the polarity selected in the SPI_CR1 register (by \npulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).\nThe Data Frame Format (8- or 16-bit) is selected through the DFF bit in SPI_CR1 register, \nand determines the data length during transmission/reception.\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n882/1757\nRM0090 Rev 21\nFigure 248. Data clock timing diagram\n1.\nThese timings are shown with the LSBFIRST bit reset in the SPI_CR1 register.\nData frame format\nData can be shifted out either MSB-first or LSB-first depending on the value of the \nLSBFIRST bit in the SPI_CR1 register.\nEach data frame is 8 or 16 bits long depending on the size of the data programmed using \nthe DFF bit in the SPI_CR1 register. The selected data frame format is applicable for \ntransmission and/or reception. \nCPOL = 1\nCPOL = 0\nMSBit\nLSBit\nMSBit\nLSBit\nMISO\nMOSI\nNSS\n(to slave)\nCapture strobe\nCPHA =1\nCPOL = 1\nCPOL = 0\nMSBit\nLSBit\nMSBit\nLSBit\nMISO\nMOSI\nNSS\n(to slave)\nCapture strobe\nCPHA =0\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \nai17154d\n\n\n<>\n\nRM0090 Rev 21\n883/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.3.2 \nConfiguring the SPI in slave mode\nIn the slave configuration, the serial clock is received on the SCK pin from the master \ndevice. The value set in the BR[2:0] bits in the SPI_CR1 register, does not affect the data \ntransfer rate.\nNote:\nIt is recommended to enable the SPI slave before the master sends the clock. If not, \nundesired data transmission might occur. The data register of the slave needs to be ready \nbefore the first edge of the communication clock or before the end of the ongoing \ncommunication. It is mandatory to have the polarity of the communication clock set to the \nsteady state value before the slave and the master are enabled.\nFollow the procedure below to configure the SPI in slave mode:\nProcedure\n1.\nSet the DFF bit to define 8- or 16-bit data frame format\n2. \nSelect the CPOL and CPHA bits to define one of the four relationships between the \ndata transfer and the serial clock (see Figure 248). For correct data transfer, the CPOL \nand CPHA bits must be configured in the same way in the slave device and the master \ndevice. This step is not required when the TI mode is selected through the FRF bit in \nthe SPI_CR2 register. \n3. \nThe frame format (MSB-first or LSB-first depending on the value of the LSBFIRST bit in \nthe SPI_CR1 register) must be the same as the master device. This step is not \nrequired when TI mode is selected.\n4. \nIn Hardware mode (refer to Slave select (NSS) pin management), the NSS pin must be \nconnected to a low level signal during the complete byte transmit sequence. In NSS \nsoftware mode, set the SSM bit and clear the SSI bit in the SPI_CR1 register. This step \nis not required when TI mode is selected.\n5. \nSet the FRF bit in the SPI_CR2 register to select the TI mode protocol for serial \ncommunications.\n6. \nClear the MSTR bit and set the SPE bit (both in the SPI_CR1 register) to assign the \npins to alternate functions.\nIn this configuration the MOSI pin is a data input and the MISO pin is a data output.\nTransmit sequence\nThe data byte is parallel-loaded into the Tx buffer during a write cycle.\nThe transmit sequence begins when the slave device receives the clock signal and the most \nsignificant bit of the data on its MOSI pin. The remaining bits (the 7 bits in 8-bit data frame \nformat, and the 15 bits in 16-bit data frame format) are loaded into the shift-register. The \nTXE flag in the SPI_SR register is set on the transfer of data from the Tx Buffer to the shift \nregister and an interrupt is generated if the TXEIE bit in the SPI_CR2 register is set.\nReceive sequence\nFor the receiver, when data transfer is complete:\n•\nThe Data in shift register is transferred to Rx Buffer and the RXNE flag (SPI_SR \nregister) is set\n•\nAn Interrupt is generated if the RXNEIE bit is set in the SPI_CR2 register.\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n884/1757\nRM0090 Rev 21\nAfter the last sampling clock edge the RXNE bit is set, a copy of the data byte received in \nthe shift register is moved to the Rx buffer. When the SPI_DR register is read, the SPI \nperipheral returns this buffered value.\nClearing of the RXNE bit is performed by reading the SPI_DR register.\nSPI TI protocol in slave mode\nIn slave mode, the SPI interface is compatible with the TI protocol. The FRF bit of the \nSPI_CR2 register can be used to configure the slave SPI serial communications to be \ncompliant with this protocol.\nThe clock polarity and phase are forced to conform to the TI protocol requirements whatever \nthe values set in the SPI_CR1 register. NSS management is also specific to the TI protocol \nwhich makes the configuration of NSS management through the SPI_CR1 and SPI_CR2 \nregisters (such as SSM, SSI, SSOE) transparent for the user.\nIn Slave mode (Figure 249: TI mode - Slave mode, single transfer and Figure 250: TI mode \n- Slave mode, continuous transfer), the SPI baud rate prescaler is used to control the \nmoment when the MISO pin state changes to HI-Z. Any baud rate can be used thus allowing \nto determine this moment with optimal flexibility. However, the baud rate is generally set to \nthe external master clock baud rate. The time for the MISO signal to become HI-Z (trelease) \ndepends on internal resynchronizations and on the baud rate value set in through BR[2:0] of \nSPI_CR1 register. It is given by the formula:\nNote:\nThis feature is not available for Motorola SPI communications (FRF bit set to 0).\nTo detect TI frame errors in Slave transmitter only mode by using the Error interrupt (ERRIE \n= 1), the SPI must be configured in 2-line unidirectional mode by setting BIDIMODE and \nBIDIOE to 1 in the SPI_CR1 register. When BIDIMODE is set to 0, OVR is set to 1 because \nthe data register is never read and error interrupt are always generated, while when \nBIDIMODE is set to 1, data are not received and OVR is never set.\nFigure 249. TI mode - Slave mode, single transfer\ntbaud_rate\n2\n----------------------------\n4\ntpclk\n×\n+\ntrelease\ntbaud_rate\n2\n----------------------------\n6\ntpclk\n×\n+\n<\n<\nai18434\nMSBIN\nMOSI\ninput\nNSS\ninput\nSCK\ninput\ntrigger\nedge\nsampling\nedge\ntrigger\nedge\nsampling\nedge\ntrigger\nedge\nsampling\nedge\nDONTCARE\nLSBIN\nDONTCARE\nMISO\noutput\n1 or 0\nMSBOUT\nLSBOUT\ntRelease\n\n\n<>\n\nRM0090 Rev 21\n885/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nFigure 250. TI mode - Slave mode, continuous transfer\n28.3.3 \nConfiguring the SPI in master mode\nIn the master configuration, the serial clock is generated on the SCK pin.\nProcedure\n1.\nSelect the BR[2:0] bits to define the serial clock baud rate (see SPI_CR1 register).\n2. \nSelect the CPOL and CPHA bits to define one of the four relationships between the \ndata transfer and the serial clock (see Figure 248). This step is not required when the \nTI mode is selected.\n3. \nSet the DFF bit to define 8- or 16-bit data frame format\n4. \nConfigure the LSBFIRST bit in the SPI_CR1 register to define the frame format. This \nstep is not required when the TI mode is selected.\n5. \nIf the NSS pin is required in input mode, in hardware mode, connect the NSS pin to a \nhigh-level signal during the complete byte transmit sequence. In NSS software mode, \nset the SSM and SSI bits in the SPI_CR1 register. If the NSS pin is required in output \nmode, the SSOE bit only should be set. This step is not required when the TI mode is \nselected.\n6. \nSet the FRF bit in SPI_CR2 to select the TI protocol for serial communications.\n7. \nThe MSTR and SPE bits must be set (they remain set only if the NSS pin is connected \nto a high-level signal).\nIn this configuration the MOSI pin is a data output and the MISO pin is a data input.\nTransmit sequence\nThe transmit sequence begins when a byte is written in the Tx Buffer.\nThe data byte is parallel-loaded into the shift register (from the internal bus) during the first \nbit transmission and then shifted out serially to the MOSI pin MSB first or LSB first \ndepending on the LSBFIRST bit in the SPI_CR1 register. The TXE flag is set on the transfer \nof data from the Tx Buffer to the shift register and an interrupt is generated if the TXEIE bit in \nthe SPI_CR2 register is set.\nai18435\nMSBIN\nMOSI\ninput\nNSS\ninput\nSCK\ninput\ntrigger\nsampling trigger\nsampling trigger\nsampling\nDONTCARE\nLSBIN\nDONTCARE\nMISO\noutput\n1 or 0\nMSBOUT\nLSBOUT\nMSBIN\nLSBIN\nMSBOUT\nLSBOUT\nFRAME 1\nFRAME 2\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n886/1757\nRM0090 Rev 21\nReceive sequence\nFor the receiver, when data transfer is complete:\n•\nThe data in the shift register is transferred to the RX Buffer and the RXNE flag is set\n•\nAn interrupt is generated if the RXNEIE bit is set in the SPI_CR2 register\nAt the last sampling clock edge the RXNE bit is set, a copy of the data byte received in the \nshift register is moved to the Rx buffer. When the SPI_DR register is read, the SPI \nperipheral returns this buffered value.\nClearing the RXNE bit is performed by reading the SPI_DR register.\nA continuous transmit stream can be maintained if the next data to be transmitted is put in \nthe Tx buffer once the transmission is started. Note that TXE flag should be ‘1 before any \nattempt to write the Tx buffer is made.\nNote:\nWhen a master is communicating with SPI slaves which need to be de-selected between \ntransmissions, the NSS pin must be configured as GPIO or another GPIO must be used and \ntoggled by software. \nSPI TI protocol in master mode\nIn master mode, the SPI interface is compatible with the TI protocol. The FRF bit of the \nSPI_CR2 register can be used to configure the master SPI serial communications to be \ncompliant with this protocol.\nThe clock polarity and phase are forced to conform to the TI protocol requirements whatever \nthe values set in the SPI_CR1 register. NSS management is also specific to the TI protocol \nwhich makes the configuration of NSS management through the SPI_CR1 and SPI_CR2 \nregisters (SSM, SSI, SSOE) transparent for the user.\nFigure 251: TI mode - master mode, single transfer and Figure 252: TI mode - master mode, \ncontinuous transfer) show the SPI master communication waveforms when the TI mode is \nselected in master mode.\nFigure 251. TI mode - master mode, single transfer\nai18436\nMSBIN\nMOSI\ninput\nNSS\noutput\nSCK\noutput\ntrigger\nedge\nsampling\nedge\ntrigger\nedge\nsampling\nedge\ntrigger\nedge\nsampling\nedge\nDONTCARE\nLSBIN\nDONTCARE\nMISO\noutput\n1 or 0\nMSBOUT\nLSBOUT\n\n\n<>\n\nRM0090 Rev 21\n887/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nFigure 252. TI mode - master mode, continuous transfer\n28.3.4 \nConfiguring the SPI for half-duplex communication\nThe SPI is capable of operating in half-duplex mode in 2 configurations.\n•\n1 clock and 1 bidirectional data wire\n•\n1 clock and 1 data wire (receive-only or transmit-only)\n1 clock and 1 bidirectional data wire (BIDIMODE = 1)\nThis mode is enabled by setting the BIDIMODE bit in the SPI_CR1 register. In this mode \nSCK is used for the clock and MOSI in master or MISO in slave mode is used for data \ncommunication. The transfer direction (Input/Output) is selected by the BIDIOE bit in the \nSPI_CR1 register. When this bit is 1, the data line is output otherwise it is input.\n1 clock and 1 unidirectional data wire (BIDIMODE = 0)\nIn this mode, the application can use the SPI either in transmit-only mode or in receive-only \nmode.\n•\nTransmit-only mode is similar to full-duplex mode (BIDIMODE=0, RXONLY=0): the \ndata are transmitted on the transmit pin (MOSI in master mode or MISO in slave mode) \nand the receive pin (MISO in master mode or MOSI in slave mode) can be used as a \ngeneral-purpose IO. In this case, the application just needs to ignore the Rx buffer (if \nthe data register is read, it does not contain the received value).\n•\nIn receive-only mode, the application can disable the SPI output function by setting the \nRXONLY bit in the SPI_CR1 register. In this case, it frees the transmit IO pin (MOSI in \nmaster mode or MISO in slave mode), so it can be used for other purposes.\nTo start the communication in receive-only mode, configure and enable the SPI:\n•\nIn master mode, the communication starts immediately and stops when the SPE bit is \ncleared and the current reception stops. There is no need to read the BSY flag in this \nmode. It is always set when an SPI communication is ongoing.\n•\nIn slave mode, the SPI continues to receive as long as the NSS is pulled down (or the \nSSI bit is cleared in NSS software mode) and the SCK is running.\nai18437\nMSBOUT\nMOSI\noutput\nNSS\noutput\nSCK\noutput\ntrigger\nsampling trigger\nsampling trigger\nsampling\nDONTCARE\nLSBOUT\nDONTCARE\nMISO\nintput\n1 or 0\nMSBIN\nLSBIN\nMSBOUT\nLSBOUT\nMSBIN\nLSBIN\nFRAME 1\nFRAME 2\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n888/1757\nRM0090 Rev 21\n28.3.5 \nData transmission and reception procedures\nRx and Tx buffers\nIn reception, data are received and then stored into an internal Rx buffer while In \ntransmission, data are first stored into an internal Tx buffer before being transmitted.\nA read access of the SPI_DR register returns the Rx buffered value whereas a write access \nto the SPI_DR stores the written data into the Tx buffer.\nStart sequence in master mode\n•\nIn full-duplex (BIDIMODE=0 and RXONLY=0)\n–\nThe sequence begins when data are written into the SPI_DR register (Tx buffer).\n–\nThe data are then parallel loaded from the Tx buffer into the 8-bit shift register \nduring the first bit transmission and then shifted out serially to the MOSI pin.\n–\nAt the same time, the received data on the MISO pin is shifted in serially to the 8-\nbit shift register and then parallel loaded into the SPI_DR register (Rx buffer).\n•\nIn unidirectional receive-only mode (BIDIMODE=0 and RXONLY=1)\n–\nThe sequence begins as soon as SPE=1\n–\nOnly the receiver is activated and the received data on the MISO pin are shifted in \nserially to the 8-bit shift register and then parallel loaded into the SPI_DR register \n(Rx buffer).\n•\nIn bidirectional mode, when transmitting (BIDIMODE=1 and BIDIOE=1)\n–\nThe sequence begins when data are written into the SPI_DR register (Tx buffer).\n–\nThe data are then parallel loaded from the Tx buffer into the 8-bit shift register \nduring the first bit transmission and then shifted out serially to the MOSI pin.\n–\nNo data are received.\n•\nIn bidirectional mode, when receiving (BIDIMODE=1 and BIDIOE=0)\n–\nThe sequence begins as soon as SPE=1 and BIDIOE=0.\n–\nThe received data on the MOSI pin are shifted in serially to the 8-bit shift register \nand then parallel loaded into the SPI_DR register (Rx buffer).\n–\nThe transmitter is not activated and no data are shifted out serially to the MOSI \npin.\nStart sequence in slave mode\n•\nIn full-duplex mode (BIDIMODE=0 and RXONLY=0)\n–\nThe sequence begins when the slave device receives the clock signal and the first \nbit of the data on its MOSI pin. The 7 remaining bits are loaded into the shift \nregister.\n–\nAt the same time, the data are parallel loaded from the Tx buffer into the 8-bit shift \nregister during the first bit transmission, and then shifted out serially to the MISO \n\n\n<>\n\nRM0090 Rev 21\n889/1757\nRM0090\nSerial peripheral interface (SPI)\n928\npin. The software must have written the data to be sent before the SPI master \ndevice initiates the transfer.\n•\nIn unidirectional receive-only mode (BIDIMODE=0 and RXONLY=1)\n–\nThe sequence begins when the slave device receives the clock signal and the first \nbit of the data on its MOSI pin. The 7 remaining bits are loaded into the shift \nregister.\n–\nThe transmitter is not activated and no data are shifted out serially to the MISO \npin.\n•\nIn bidirectional mode, when transmitting (BIDIMODE=1 and BIDIOE=1)\n–\nThe sequence begins when the slave device receives the clock signal and the first \nbit in the Tx buffer is transmitted on the MISO pin.\n–\nThe data are then parallel loaded from the Tx buffer into the 8-bit shift register \nduring the first bit transmission and then shifted out serially to the MISO pin. The \nsoftware must have written the data to be sent before the SPI master device \ninitiates the transfer.\n–\nNo data are received.\n•\nIn bidirectional mode, when receiving (BIDIMODE=1 and BIDIOE=0)\n–\nThe sequence begins when the slave device receives the clock signal and the first \nbit of the data on its MISO pin.\n–\nThe received data on the MISO pin are shifted in serially to the 8-bit shift register \nand then parallel loaded into the SPI_DR register (Rx buffer).\n–\nThe transmitter is not activated and no data are shifted out serially to the MISO \npin.\nHandling data transmission and reception\nThe TXE flag (Tx buffer empty) is set when the data are transferred from the Tx buffer to the \nshift register. It indicates that the internal Tx buffer is ready to be loaded with the next data. \nAn interrupt can be generated if the TXEIE bit in the SPI_CR2 register is set. Clearing the \nTXE bit is performed by writing to the SPI_DR register.\nNote:\nThe software must ensure that the TXE flag is set to 1 before attempting to write to the Tx \nbuffer. Otherwise, it overwrites the data previously written to the Tx buffer.\nThe RXNE flag (Rx buffer not empty) is set on the last sampling clock edge, when the data \nare transferred from the shift register to the Rx buffer. It indicates that data are ready to be \nread from the SPI_DR register. An interrupt can be generated if the RXNEIE bit in the \nSPI_CR2 register is set. Clearing the RXNE bit is performed by reading the SPI_DR \nregister.\nFor some configurations, the BSY flag can be used during the last data transfer to wait until \nthe completion of the transfer.\nFull-duplex transmit and receive procedure in master or slave mode (BIDIMODE=0 and \nRXONLY=0)\nThe software has to follow this procedure to transmit and receive data (see Figure 253 and \nFigure 254):\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n890/1757\nRM0090 Rev 21\n1.\nEnable the SPI by setting the SPE bit to 1.\n2. \nWrite the first data item to be transmitted into the SPI_DR register (this clears the TXE \nflag).\n3. \nWait until TXE=1 and write the second data item to be transmitted. Then wait until \nRXNE=1 and read the SPI_DR to get the first received data item (this clears the RXNE \nbit). Repeat this operation for each data item to be transmitted/received until the n–1 \nreceived data.\n4. \nWait until RXNE=1 and read the last received data.\n5. \nWait until TXE=1 and then wait until BSY=0 before disabling the SPI.\nThis procedure can also be implemented using dedicated interrupt subroutines launched at \neach rising edges of the RXNE or TXE flag.\nFigure 253. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and\nRXONLY=0) in case of continuous transfers\nMISO/MOSI (in)\nTx buffer\nDATA1 = 0xA1\n TXE flag\n0xF2\nBSY flag\n0xF3\nsoftware \nwrites 0xF1 \ninto SPI_DR\nsoftware waits \nuntil TXE=1 and \nwrites 0xF2 into \nSPI_DR\nsoftware waits \nuntil RXNE=1 \nand reads 0xA1 \nfrom SPI_DR\nset by hardware\ncleared by software\nset by hardware\ncleared by software\nset by hardware\nset by hardware\nSCK\nDATA 2 = 0xA2\nDATA 3 = 0xA3\nreset by hardware\nExample in Master mode with CPOL=1, CPHA=1\n0xF1\n RXNE flag\n(write SPI_DR)\nRx buffer\nset by hardware\nMISO/MOSI (out)\nDATA1 = 0xF1\nDATA2 = 0xF2\nDATA3 = 0xF3\n(read SPI_DR)\n0xA1\n0xA2\n0xA3\nsoftware waits \nuntil TXE=1 and \nwrites 0xF3 into \nSPI_DR\nsoftware waits \nuntil RXNE=1 \nand reads 0xA2 \nfrom SPI_ DR\nsoftware waits \nuntil RXNE=1 \nand reads 0xA3 \nfrom SPI_DR\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7\ncleared by software\nai17343\n\n\n<>\n\nRM0090 Rev 21\n891/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nFigure 254. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0,\nRXONLY=0) in case of continuous transfers\nTransmit-only procedure (BIDIMODE=0 RXONLY=0)\nIn this mode, the procedure can be reduced as described below and the BSY bit can be \nused to wait until the completion of the transmission (see Figure 255 and Figure 256).\n1.\nEnable the SPI by setting the SPE bit to 1.\n2. \nWrite the first data item to send into the SPI_DR register (this clears the TXE bit).\n3. \nWait until TXE=1 and write the next data item to be transmitted. Repeat this step for \neach data item to be transmitted.\n4. \nAfter writing the last data item into the SPI_DR register, wait until TXE=1, then wait until \nBSY=0, this indicates that the transmission of the last data is complete.\nThis procedure can be also implemented using dedicated interrupt subroutines launched at \neach rising edge of the TXE flag.\nNote:\nDuring discontinuous communications, there is a 2 APB clock period delay between the \nwrite operation to SPI_DR and the BSY bit setting. As a consequence, in transmit-only \nmode, it is mandatory to wait first until TXE is set and then until BSY is cleared after writing \nthe last data.\nAfter transmitting two data items in transmit-only mode, the OVR flag is set in the SPI_SR \nregister since the received data are never read.\n0xF1\nset by cleared by software\nMISO/MOSI (in)\nTx buffer\nDATA 1 = 0xA1\n TXE flag\n0xF2\nBSY flag\n0xF3\nsoftware \nwrites 0xF1 \ninto SPI_DR\nsoftware waits \nuntil TXE=1 and \nwrites 0xF2 into \nSPI_DR\nsoftware waits \nuntil RXNE=1 \nand reads 0xA1 \nfrom SPI_DR\nset by hardware\ncleared by software\nset by hardware\ncleared by software\nset by hardware\nSCK\nDATA 2 = 0xA2\nDATA 3 = 0xA3\nreset by hardware\nExample in Slave mode with CPOL=1, CPHA=1\n RXNE flag\n(write to SPI_DR)\nRx buffer\nset by hardware\nMISO/MOSI (out)\nDATA 1 = 0xF1\nDATA 2 = 0xF2\nDATA 3 = 0xF3\n(read from SPI_DR)\n0xA1\n0xA2\n0xA3\nsoftware waits \nuntil TXE=1 and \nwrites 0xF3 into \nSPI_DR\nsoftware waits \nuntil RXNE=1 \nand reads 0xA2 \nfrom SPI_ DR\nsoftware waits \nuntil RXNE=1 \nand reads 0xA3 \nfrom SPI_DR\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7\ncleared by software\nai17344\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n892/1757\nRM0090 Rev 21\nFigure 255. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0)\nin case of continuous transfers\nFigure 256. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of \ncontinuous transfers\nBidirectional transmit procedure (BIDIMODE=1 and BIDIOE=1)\nIn this mode, the procedure is similar to the procedure in Transmit-only mode except that \nthe BIDIMODE and BIDIOE bits both have to be set in the SPI_CR2 register before enabling \nthe SPI.\nUnidirectional receive-only procedure (BIDIMODE=0 and RXONLY=1)\nIn this mode, the procedure can be reduced as described below (see Figure 257):\n0xF1\nTx buffer\nTXE flag\n0xF2\nBSY flag\n0xF3\nsoftware writes \n0xF1 into \nSPI_DR\nsoftware waits \nuntil TXE=1 and \nwrites 0xF2 into \nSPI_DR\nset by hardware\ncleared by software\nset by hardware\ncleared by software\nset by hardware\nset by hardware\nSCK\nreset by hardware\nExample in Master mode with CPOL=1, CPHA=1\n(write to SPI_DR)\nMISO/MOSI (out)\nDATA 1 = 0xF1\nDATA 2 = 0xF2\nDATA 3 = 0xF3\nsoftware waits \nuntil TXE=1 and \nwrites 0xF3 into \nSPI_DR\nsoftware waits until BSY=0\nsoftware waits until TXE=1 \nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7\nai17345\n0xF1\nTx buffer\nTXE flag\n0xF2\nBSY flag\n0xF3\nsoftware writes \n0xF1 into \nSPI_DR\nsoftware waits \nuntil TXE=1 and \nwrites 0xF2 into \nSPI_DR\nset by hardware\ncleared by software\nset by hardware\ncleared by software\nset by hardware\nset by hardware\nSCK\nreset by hardware\nExample in slave mode with CPOL=1, CPHA=1\n(write to SPI_DR)\nMISO/MOSI (out)\nDATA 1 = 0xF1\nDATA 2 = 0xF2\nDATA 3 = 0xF3\nsoftware waits \nuntil TXE=1 and \nwrites 0xF3 into \nSPI_DR\nsoftware waits until BSY=0\nsoftware waits until TXE=1 \nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3 b4 b5\nb6\nb7 b0 b1\nb2\nb3 b4 b5\nb6\nb7\nai17346\n\n\n<>\n\nRM0090 Rev 21\n893/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n1.\nSet the RXONLY bit in the SPI_CR1 register.\n2. \nEnable the SPI by setting the SPE bit to 1:\na) \nIn master mode, this immediately activates the generation of the SCK clock, and \ndata are serially received until the SPI is disabled (SPE=0).\nb) \nIn slave mode, data are received when the SPI master device drives NSS low and \ngenerates the SCK clock.\n3. \nWait until RXNE=1 and read the SPI_DR register to get the received data (this clears \nthe RXNE bit). Repeat this operation for each data item to be received.\nThis procedure can also be implemented using dedicated interrupt subroutines launched at \neach rising edge of the RXNE flag.\nNote:\nIf it is required to disable the SPI after the last transfer, follow the recommendation \ndescribed in Section 28.3.8.\nFigure 257. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1)\nin case of continuous transfers\nBidirectional receive procedure (BIDIMODE=1 and BIDIOE=0)\nIn this mode, the procedure is similar to the Receive-only mode procedure except that the \nBIDIMODE bit has to be set and the BIDIOE bit cleared in the SPI_CR2 register before \nenabling the SPI.\nContinuous and discontinuous transfers\nWhen transmitting data in master mode, if the software is fast enough to detect each rising \nedge of TXE (or TXE interrupt) and to immediately write to the SPI_DR register before the \nongoing data transfer is complete, the communication is said to be continuous. In this case, \nthere is no discontinuity in the generation of the SPI clock between each data item and the \nBSY bit is never cleared between each data transfer.\nOn the contrary, if the software is not fast enough, this can lead to some discontinuities in \nthe communication. In this case, the BSY bit is cleared between each data transmission \n(see Figure 258).\nIn Master receive-only mode (RXONLY=1), the communication is always continuous and \nthe BSY flag is always read at 1.\nMISO/MOSI (in)\nDATA 1 = 0xA1\nsoftware waits until RXNE=1 \nand reads 0xA1 from SPI_DR\nSCK\nDATA 2 = 0xA2\nDATA 3 = 0xA3\nExample with CPOL=1, CPHA=1, RXONLY=1\n RXNE flag\nRx buffer\nset by hardware\n(read from SPI_DR)\n0xA1\n0xA2\n0xA3\nsoftware waits until RXNE=1 \nand reads 0xA2 from SPI_DR\nsoftware waits until RXNE=1 \nand reads 0xA3 from SPI_DR\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7\ncleared by software\nai17347\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n894/1757\nRM0090 Rev 21\nIn slave mode, the continuity of the communication is decided by the SPI master device. In \nany case, even if the communication is continuous, the BSY flag goes low between each \ntransfer for a minimum duration of one SPI clock cycle (see Figure 256).\nFigure 258. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) \nin case of discontinuous transfers\n28.3.6 \nCRC calculation\nA CRC calculator has been implemented for communication reliability. Separate CRC \ncalculators are implemented for transmitted data and received data. The CRC is calculated \nusing a programmable polynomial serially on each bit. It is calculated on the sampling clock \nedge defined by the CPHA and CPOL bits in the SPI_CR1 register.\nNote:\nThis SPI offers two kinds of CRC calculation standard which depend directly on the data \nframe format selected for the transmission and/or reception: 8-bit data (CR8) and 16-bit data \n(CRC16).\nCRC calculation is enabled by setting the CRCEN bit in the SPI_CR1 register. This action \nresets the CRC registers (SPI_RXCRCR and SPI_TXCRCR). In full duplex or transmitter \nonly mode, when the transfers are managed by the software (CPU mode), it is necessary to \nwrite the bit CRCNEXT immediately after the last data to be transferred is written to the \nSPI_DR. At the end of this last data transfer, the SPI_TXCRCR value is transmitted.\nIn receive only mode and when the transfers are managed by software (CPU mode), it is \nnecessary to write the CRCNEXT bit after the second last data has been received. The CRC \nis received just after the last data reception and the CRC check is then performed.\nAt the end of data and CRC transfers, the CRCERR flag in the SPI_SR register is set if \ncorruption occurs during the transfer.\nIf data are present in the TX buffer, the CRC value is transmitted only after the transmission \nof the data byte. During CRC transmission, the CRC calculator is switched off and the \nregister value remains unchanged.\nSPI communication using the CRC is possible through the following procedure:\nMOSI (out)\nTx buffer\nDATA 1 = 0xF1\nTXE flag\n0xF1\nBSY flag\n0xF2\nsoftware writes 0xF1 \ninto SPI_DR\nsoftware waits until TXE=1 but is \nlate to write 0xF2 into SPI_DR\nsoftware waits until TXE=1 but \nis late to write 0xF3 into \nSPI_DR\nSCK\n3\nF\nx\n0\n \n=\n \n3\n \nA\nT\nA\nD\n2\nF\nx\n0\n \n=\n \n2\n \nA\nT\nA\nD\nExample with CPOL=1, CPHA=1\n0xF3\nsoftware waits \nuntil TXE=1\nsoftware waits until BSY=0\n(write to SPI_DR)\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7\nai17348\n\n\n<>\n\nRM0090 Rev 21\n895/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n1.\nProgram the CPOL, CPHA, LSBFirst, BR, SSM, SSI and MSTR values.\n2. \nProgram the polynomial in the SPI_CRCPR register.\n3. \nEnable the CRC calculation by setting the CRCEN bit in the SPI_CR1 register. This \nalso clears the SPI_RXCRCR and SPI_TXCRCR registers.\n4. \nEnable the SPI by setting the SPE bit in the SPI_CR1 register.\n5. \nStart the communication and sustain the communication until all but one byte or half-\nword have been transmitted or received.\n–\nIn full duplex or transmitter-only mode, when the transfers are managed by \nsoftware, when writing the last byte or half word to the Tx buffer, set the \nCRCNEXT bit in the SPI_CR1 register to indicate that the CRC is transmitted after \nthe transmission of the last byte.\n–\nIn receiver only mode, set the bit CRCNEXT just after the reception of the second \nto last data to prepare the SPI to enter in CRC Phase at the end of the reception of \nthe last data. CRC calculation is frozen during the CRC transfer. \n6. \nAfter the transfer of the last byte or half word, the SPI enters the CRC transfer and \ncheck phase. In full duplex mode or receiver-only mode, the received CRC is \ncompared to the SPI_RXCRCR value. If the value does not match, the CRCERR flag in \nSPI_SR is set and an interrupt can be generated when the ERRIE bit in the SPI_CR2 \nregister is set.\nNote:\nWhen the SPI is in slave mode, be careful to enable CRC calculation only when the clock is \nstable, that is, when the clock is in the steady state. If not, a wrong CRC calculation may be \ndone. In fact, the CRC is sensitive to the SCK slave input clock as soon as CRCEN is set, \nand this, whatever the value of the SPE bit.\nWith high bitrate frequencies, be careful when transmitting the CRC. As the number of used \nCPU cycles has to be as low as possible in the CRC transfer phase, it is forbidden to call \nsoftware functions in the CRC transmission sequence to avoid errors in the last data and \nCRC reception. In fact, CRCNEXT bit has to be written before the end of the \ntransmission/reception of the last data.\nFor high bit rate frequencies, it is advised to use the DMA mode to avoid the degradation of \nthe SPI speed performance due to CPU accesses impacting the SPI bandwidth.\nWhen the devices are configured as slaves and the NSS hardware mode is used, the NSS \npin needs to be kept low between the data phase and the CRC phase.\nWhen the SPI is configured in slave mode with the CRC feature enabled, CRC calculation \ntakes place even if a high level is applied on the NSS pin. This may happen for example in \ncase of a multislave environment where the communication master addresses slaves \nalternately.\nBetween a slave deselection (high level on NSS) and a new slave selection (low level on \nNSS), the CRC value should be cleared on both master and slave sides in order to \nresynchronize the master and slave for their respective CRC calculation.\nTo clear the CRC, follow the procedure below:\n1.\nDisable SPI (SPE = 0)\n2. \nClear the CRCEN bit\n3. \nSet the CRCEN bit\n4. \nEnable the SPI (SPE = 1)\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n896/1757\nRM0090 Rev 21\n28.3.7 \nStatus flags\nFour status flags are provided for the application to completely monitor the state of the SPI \nbus.\nTx buffer empty flag (TXE)\nWhen it is set, this flag indicates that the Tx buffer is empty and the next data to be \ntransmitted can be loaded into the buffer. The TXE flag is cleared when writing to the \nSPI_DR register.\nRx buffer not empty (RXNE)\nWhen set, this flag indicates that there are valid received data in the Rx buffer. It is cleared \nwhen SPI_DR is read.\nBUSY flag\nThis BSY flag is set and cleared by hardware (writing to this flag has no effect). The BSY \nflag indicates the state of the communication layer of the SPI.\nWhen BSY is set, it indicates that the SPI is busy communicating. There is one exception in \nmaster mode / bidirectional receive mode (MSTR=1 and BDM=1 and BDOE=0) where the \nBSY flag is kept low during reception.\nThe BSY flag is useful to detect the end of a transfer if the software wants to disable the SPI \nand enter Halt mode (or disable the peripheral clock). This avoids corrupting the last \ntransfer. For this, the procedure described below must be strictly respected.\nThe BSY flag is also useful to avoid write collisions in a multimaster system.\nThe BSY flag is set when a transfer starts, with the exception of master mode / bidirectional \nreceive mode (MSTR=1 and BDM=1 and BDOE=0).\nIt is cleared:\n•\nwhen a transfer is finished (except in master mode if the communication is continuous)\n•\nwhen the SPI is disabled\n•\nwhen a master mode fault occurs (MODF=1)\nWhen communication is not continuous, the BSY flag is low between each communication.\nWhen communication is continuous:\n•\nin master mode, the BSY flag is kept high during all the transfers\n•\nin slave mode, the BSY flag goes low for one SPI clock cycle between each transfer\nNote:\nDo not use the BSY flag to handle each data transmission or reception. It is better to use the \nTXE and RXNE flags instead.\n\n\n<>\n\nRM0090 Rev 21\n897/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.3.8 \nDisabling the SPI\nWhen a transfer is terminated, the application can stop the communication by disabling the \nSPI peripheral. This is done by clearing the SPE bit.\nFor some configurations, disabling the SPI and entering the Halt mode while a transfer is \nongoing can cause the current transfer to be corrupted and/or the BSY flag might become \nunreliable.\nTo avoid any of those effects, it is recommended to respect the following procedure when \ndisabling the SPI:\nIn master or slave full-duplex mode (BIDIMODE=0, RXONLY=0)\n1.\nWait until RXNE=1 to receive the last data\n2. \nWait until TXE=1\n3. \nThen wait until BSY=0\n4. \nDisable the SPI (SPE=0) and, eventually, enter the Halt mode (or disable the peripheral \nclock)\nIn master or slave unidirectional transmit-only mode (BIDIMODE=0, \nRXONLY=0) or bidirectional transmit mode (BIDIMODE=1, BIDIOE=1)\nAfter the last data is written into the SPI_DR register:\n1.\nWait until TXE=1\n2. \nThen wait until BSY=0\n3. \nDisable the SPI (SPE=0) and, eventually, enter the Halt mode (or disable the peripheral \nclock)\nIn master unidirectional receive-only mode (MSTR=1, BIDIMODE=0, \nRXONLY=1) or bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0)\nThis case must be managed in a particular way to ensure that the SPI does not initiate a \nnew transfer. The sequence below is valid only for SPI Motorola configuration (FRF bit set to \n0):\n1.\nWait for the second to last occurrence of RXNE=1 (n–1)\n2. \nThen wait for one SPI clock cycle (using a software loop) before disabling the SPI \n(SPE=0)\n3. \nThen wait for the last RXNE=1 before entering the Halt mode (or disabling the \nperipheral clock)\nWhen the SPI is configured in TI mode (Bit FRF set to 1), the following procedure has to be \nrespected to avoid generating an undesired pulse on NSS when the SPI is disabled:\n1.\nWait for the second to last occurrence of RXNE = 1 (n-1).\n2. \nDisable the SPI (SPE = 0) in the following window frame using a software loop:\n–\nAfter at least one SPI clock cycle,\n–\nBefore the beginning of the LSB data transfer.\nNote:\nIn master bidirectional receive mode (MSTR=1 and BDM=1 and BDOE=0), the BSY flag is \nkept low during transfers.\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n898/1757\nRM0090 Rev 21\nIn slave receive-only mode (MSTR=0, BIDIMODE=0, RXONLY=1) or \nbidirectional receive mode (MSTR=0, BIDIMODE=1, BIDOE=0)\n1.\nYou can disable the SPI (write SPE=1) at any time: the current transfer completes \nbefore the SPI is effectively disabled\n2. \nThen, if you want to enter the Halt mode, you must first wait until BSY = 0 before \nentering the Halt mode (or disabling the peripheral clock).\n28.3.9 \nSPI communication using DMA (direct memory addressing)\nTo operate at its maximum speed, the SPI needs to be fed with the data for transmission \nand the data received on the Rx buffer should be read to avoid overrun. To facilitate the \ntransfers, the SPI features a DMA capability implementing a simple request/acknowledge \nprotocol.\nA DMA access is requested when the enable bit in the SPI_CR2 register is enabled. \nSeparate requests must be issued to the Tx and Rx buffers (see Figure 259 and \nFigure 260):\n•\nIn transmission, a DMA request is issued each time TXE is set to 1. The DMA then \nwrites to the SPI_DR register (this clears the TXE flag).\n•\nIn reception, a DMA request is issued each time RXNE is set to 1. The DMA then reads \nthe SPI_DR register (this clears the RXNE flag).\nWhen the SPI is used only to transmit data, it is possible to enable only the SPI Tx DMA \nchannel. In this case, the OVR flag is set because the data received are not read.\nWhen the SPI is used only to receive data, it is possible to enable only the SPI Rx DMA \nchannel.\nIn transmission mode, when the DMA has written all the data to be transmitted (flag TCIF is \nset in the DMA_ISR register), the BSY flag can be monitored to ensure that the SPI \ncommunication is complete. This is required to avoid corrupting the last transmission before \ndisabling the SPI or entering the Stop mode. The software must first wait until TXE=1 and \nthen until BSY=0.\nNote:\nDuring discontinuous communications, there is a 2 APB clock period delay between the \nwrite operation to SPI_DR and the BSY bit setting. As a consequence, it is mandatory to \nwait first until TXE=1 and then until BSY=0 after writing the last data.\n\n\n<>\n\nRM0090 Rev 21\n899/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nFigure 259. Transmission using DMA\nFigure 260. Reception using DMA\n0xF1\nTx buffer\nTXE flag\n0xF2\nBSY flag\n0xF3\nset by hardware\nclear by DMA write\nset by hardware\ncleared by DMA write\nset by hardware\nset by hardware\nSCK\nreset\nExample with CPOL=1, CPHA=1\n(write to SPI_DR)\nMISO/MOSI (out)\nDATA 1 = 0xF1\nDATA 2 = 0xF2\nDATA 3 = 0xF3\nsoftware configures the \nDMA SPI Tx channel\nto send 3 data items\nand enables the SPI\nDMA writes to SPI_DR\nDMA request\nignored by the DMA because\nDMA TCIF flag\nset by hardware\nclear by software\nDMA writes \nDATA1 into \nSPI_DR\nby hardware\nDMA writes \nDATA2 into \nSPI_DR\nDMA writes \nDATA3 into \nSPI_DR\nsoftware waits until BSY=0\n(DMA transfer complete)\nDMA transfer is \ncomplete (TCIF=1 in \nDMA_ISR)\nsoftware waits \nuntil TXE=1\nDMA transfer is complete\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7\nai17349\nMISO/MOSI (in)\nDATA 1 = 0xA1\nsoftware configures the \nDMA SPI Rx channel\nto receive 3 data items\nand enables the SPI\nSCK\nDATA 2 = 0xA2\nDATA 3 = 0xA3\nExample with CPOL=1, CPHA=1\nRXNE flag\nRx buffer\nset by hardware\n(read from SPI_DR)\n0xA1\n0xA2\n0xA3\nDMA request\nDMA reads \nDATA3 from \nSPI_DR\nflag DMA TCIF\nset by hardware\nclear \nby software\nDMA read from SPI_DR\nThe DMA transfer is \ncomplete (TCIF=1 in \nDMA_ISR)\nDMA reads \nDATA2 from \nSPI_DR\nDMA reads \nDATA1 from \nSPI_DR\n(DMA transfer complete)\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3 b4 b5\nb6\nb7 b0 b1\nb2\nb3 b4 b5\nb6\nb7\nclear by DMA read\nai17350\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n900/1757\nRM0090 Rev 21\nDMA capability with CRC\nWhen SPI communication is enabled with CRC communication and DMA mode, the \ntransmission and reception of the CRC at the end of communication are automatic that is \nwithout using the bit CRCNEXT. After the CRC reception, the CRC must be read in the \nSPI_DR register to clear the RXNE flag.\nAt the end of data and CRC transfers, the CRCERR flag in SPI_SR is set if corruption \noccurs during the transfer.\n28.3.10 \nError flags\nMaster mode fault (MODF)\nMaster mode fault occurs when the master device has its NSS pin pulled low (in NSS \nhardware mode) or SSI bit low (in NSS software mode), this automatically sets the MODF \nbit. Master mode fault affects the SPI peripheral in the following ways:\n•\nThe MODF bit is set and an SPI interrupt is generated if the ERRIE bit is set.\n•\nThe SPE bit is cleared. This blocks all output from the device and disables the SPI \ninterface.\n•\nThe MSTR bit is cleared, thus forcing the device into slave mode.\nUse the following software sequence to clear the MODF bit:\n1.\nMake a read or write access to the SPI_SR register while the MODF bit is set.\n2. \nThen write to the SPI_CR1 register.\nTo avoid any multiple slave conflicts in a system comprising several MCUs, the NSS pin \nmust be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits can \nbe restored to their original state after this clearing sequence.\nAs a security, hardware does not allow the setting of the SPE and MSTR bits while the \nMODF bit is set.\nIn a slave device the MODF bit cannot be set. However, in a multimaster configuration, the \ndevice can be in slave mode with this MODF bit set. In this case, the MODF bit indicates \nthat there might have been a multimaster conflict for system control. An interrupt routine can \nbe used to recover cleanly from this state by performing a reset or returning to a default \nstate.\nOverrun condition\nAn overrun condition occurs when the master device has sent data bytes and the slave \ndevice has not cleared the RXNE bit resulting from the previous data byte transmitted. \nWhen an overrun condition occurs:\n•\nthe OVR bit is set and an interrupt is generated if the ERRIE bit is set.\nIn this case, the receiver buffer contents are not updated with the newly received data from \nthe master device. A read from the SPI_DR register returns this byte. All other subsequently \ntransmitted bytes are lost.\nClearing the OVR bit is done by a read from the SPI_DR register followed by a read access \nto the SPI_SR register.\n\n\n<>\n\nRM0090 Rev 21\n901/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nCRC error\nThis flag is used to verify the validity of the value received when the CRCEN bit in the \nSPI_CR1 register is set. The CRCERR flag in the SPI_SR register is set if the value \nreceived in the shift register does not match the receiver SPI_RXCRCR value.\nTI mode frame format error\nA TI mode frame format error is detected when an NSS pulse occurs during an ongoing \ncommunication when the SPI is acting in slave mode and configured to conform to the TI \nmode protocol. When this error occurs, the FRE flag is set in the SPI_SR register. The SPI \nis not disabled when an error occurs, the NSS pulse is ignored, and the SPI waits for the \nnext NSS pulse before starting a new transfer. The data may be corrupted since the error \ndetection may result in the lost of two data bytes.\nThe FRE flag is cleared when SPI_SR register is read. If the bit ERRIE is set, an interrupt is \ngenerated on the NSS error detection. In this case, the SPI should be disabled because \ndata consistency is no more guaranteed and communications should be reinitiated by the \nmaster when the slave SPI is re-enabled.\nFigure 261. TI mode frame format error detection\n28.3.11 \nSPI interrupts\n \nai18438\nMSBIN\nMOSI\ninput\nNSS\noutput\nSCK\noutput\ntrigger\nsampling trigger\nsampling trigger\nsampling\nDONTCARE\nMISO\noutput\n1 or 0\nMSBOUT\nLSBOUT\nMSBIN\nLSBIN\nMSBOUT\nLSBOUT\ntrigger\nsampling trigger samplingtrigger\nsampling trigger\nsampling\nLSBIN\nDONTCARE\nTIFRFE\nTable 127. SPI interrupt requests\nInterrupt event\nEvent flag\nEnable Control bit\nTransmit buffer empty flag\nTXE\nTXEIE\nReceive buffer not empty flag\nRXNE\nRXNEIE\nMaster mode fault event\nMODF\nERRIE\nOverrun error\nOVR\nCRC error flag\nCRCERR\nTI frame format error\nFRE\nERRIE\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n902/1757\nRM0090 Rev 21\n28.4 \nI2S functional description\n28.4.1 \nI2S general description\nThe block diagram of the I2S is shown in Figure 262.\nFigure 262. I2S block diagram \n1.\nI2S2ext_SD and I2S3ext_SD are the extended SD pins that control the I2S full duplex mode.\nThe SPI could function as an audio I2S interface when the I2S capability is enabled (by \nsetting the I2SMOD bit in the SPI_I2SCFGR register). This interface uses almost the same \npins, flags and interrupts as the SPI.\nTx buffer \nShift register\n16-bit\nCommunication\nRx buffer\n16-bit\nMOSI/ SD\nMaster control logic \nMISO/\nI2S2ext_SD/\nI2S3ext_SD(1)\nSPI \nbaud rate generator\nCK\nI2SMOD\nLSB first\nLSB\nFirst\nSPE BR2\nBR1\nBR0\nMSTR CPOL CPHA\nBidi\nmode\nBidi\nOE\nCRC\nEN\nCRC\nNext DFF\nRx\nonly SSM\nSSI\nAddress and data bus\ncontrol\nNSS/WS\nBSY OVR MODF CRC\nERR\nCH\nSIDE TxE RxNE\nI2S clock generator\nMCK\nI2S_CK\nI2S\nMODI2SE\nCH\nDATLEN\nLEN\nCK \nPOL\nI2SCFG\nI2SSTD\nMCKOEODD\nI2SDIV[7:0]\n[1:0]\n[1:0]\n[1:0]\nUDR\nI2SxCLK \nMS19909V1\nFRE\n\n\n<>\n\nRM0090 Rev 21\n903/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nThe I2S shares three common pins with the SPI:\n•\nSD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time-\nmultiplexed data channels (in half-duplex mode only).\n•\nWS: Word Select (mapped on the NSS pin) is the data control signal output in master \nmode and input in slave mode.\n•\nCK: Serial Clock (mapped on the SCK pin) is the serial clock output in master mode \nand serial clock input in slave mode.\n•\nI2S2ext_SD and I2S3ext_SD: additional pins (mapped on the MISO pin) to control the \nI2S full duplex mode.\nAn additional pin could be used when a master clock output is needed for some external \naudio devices:\n•\nMCK: Master Clock (mapped separately) is used, when the I2S is configured in master \nmode (and when the MCKOE bit in the SPI_I2SPR register is set), to output this \nadditional clock generated at a preconfigured frequency rate equal to 256 × FS, where \nFS is the audio sampling frequency.\nThe I2S uses its own clock generator to produce the communication clock when it is set in \nmaster mode. This clock generator is also the source of the master clock output. Two \nadditional registers are available in I2S mode. One is linked to the clock generator \nconfiguration SPI_I2SPR and the other one is a generic I2S configuration register \nSPI_I2SCFGR (audio standard, slave/master mode, data format, packet frame, clock \npolarity, etc.).\nThe SPI_CR1 register and all CRC registers are not used in the I2S mode. Likewise, the \nSSOE bit in the SPI_CR2 register and the MODF and CRCERR bits in the SPI_SR are not \nused.\nThe I2S uses the same SPI register for data transfer (SPI_DR) in 16-bit wide mode.\n28.4.2 \nI2S full duplex\nTo support I2S full duplex mode, two extra I2S instances called extended I2Ss (I2S2_ext, \nI2S3_ext) are available in addition to I2S2 and I2S3 (see Figure 263). The first I2S full-\nduplex interface is consequently based on I2S2 and I2S2_ext, and the second one on I2S3 \nand I2S3_ext.\nNote:\nI2S2_ext an I2S3_ext are used only in full-duplex mode.\nFigure 263. I2S full duplex block diagram \n1.\nWhere x can be 2 or 3.\nMS19910V1\nSPI/I2Sx \nI2Sx_ext \nSPIx_MOSI/I2Sx_SD(in/out)\nI2S_ WS \nI2Sx_SCK \nI2Sx_extSD(in/out)\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n904/1757\nRM0090 Rev 21\nI2Sx can operate in master mode. As a result:\n•\n Only I2Sx can output SCK and WS in half duplex mode\n•\n Only I2Sx can deliver SCK and WS to I2S2_ext and I2S3_ext in full duplex mode.\nThe extended I2Ss (I2Sx_ext) can be used only in full duplex mode. The I2Sx_ext operate \nalways in slave mode.\nBoth I2Sx and I2Sx_ext can be configured as transmitters or receivers.\n28.4.3 \nSupported audio protocols\nThe four-line bus has to handle only audio data generally time-multiplexed on two channels: \nthe right channel and the left channel. However there is only one 16-bit register for the \ntransmission and the reception. So, it is up to the software to write into the data register the \nadequate value corresponding to the considered channel side, or to read the data from the \ndata register and to identify the corresponding channel by checking the CHSIDE bit in the \nSPI_SR register. Channel Left is always sent first followed by the channel right (CHSIDE \nhas no meaning for the PCM protocol).\nFour data and packet frames are available. Data may be sent with a format of:\n•\n16-bit data packed in 16-bit frame\n•\n16-bit data packed in 32-bit frame\n•\n24-bit data packed in 32-bit frame\n•\n32-bit data packed in 32-bit frame\nWhen using 16-bit data extended on 32-bit packet, the first 16 bits (MSB) are the significant \nbits, the 16-bit LSB is forced to 0 without any need for software action or DMA request (only \none read/write operation).\nThe 24-bit and 32-bit data frames need two CPU read or write operations to/from the \nSPI_DR or two DMA operations if the DMA is preferred for the application. For 24-bit data \nframe specifically, the 8 nonsignificant bits are extended to 32 bits with 0-bits (by hardware).\nFor all data formats and communication standards, the most significant bit is always sent \nfirst (MSB first). \nThe I2S interface supports four audio standards, configurable using the I2SSTD[1:0] and \nPCMSYNC bits in the SPI_I2SCFGR register.\nI2S Philips standard\nFor this standard, the WS signal is used to indicate which channel is being transmitted. It is \nactivated one CK clock cycle before the first bit (MSB) is available.\n\n\n<>\n\nRM0090 Rev 21\n905/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nFigure 264. I2S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0)\nData are latched on the falling edge of CK (for the transmitter) and are read on the rising \nedge (for the receiver). The WS signal is also latched on the falling edge of CK.\nFigure 265. I2S Philips standard waveforms (24-bit frame with CPOL = 0)\nThis mode needs two write or read operations to/from the SPI_DR.\n•\nIn transmission mode:\nif 0x8EAA33 has to be sent (24-bit):\nFigure 266. Transmitting 0x8EAA33\n•\nIn reception mode:\nif data 0x8EAA33 is received:\nMS19591V1\nCK\nWS\nSD\nCan be 16-bit or 32-bit\nMSB\nMSB\nLSB\nChannel left\nChannel \nright\ntransmission\nreception\nMS19592V1\nCK\nWS\nSD\nTransmission\nReception\n24-bit data\nMSB\nLSB\nChannel left 32-bit\nChannel right\n8-bit remaining 0 forced\nMS19593V1\n0x8EAA\n0x33XX\nFirst write to Data register\nSecond write to Data register\nOnly the 8 MSB are sent \nto compare the 24 bits\n8 LSBs have no meaning \nand can be anything\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n906/1757\nRM0090 Rev 21\nFigure 267. Receiving 0x8EAA33\nFigure 268. I2S Philips standard (16-bit extended to 32-bit packet frame with \nCPOL = 0)\nWhen 16-bit data frame extended to 32-bit channel frame is selected during the I2S \nconfiguration phase, only one access to SPI_DR is required. The 16 remaining bits are \nforced by hardware to 0x0000 to extend the data to 32-bit format.\nIf the data to transmit or the received data are 0x76A3 (0x76A30000 extended to 32-bit), the \noperation shown in Figure 269 is required.\nFigure 269. Example\nFor transmission, each time an MSB is written to SPI_DR, the TXE flag is set and its \ninterrupt, if allowed, is generated to load SPI_DR with the new value to send. This takes \nplace even if 0x0000 have not yet been sent because it is done by hardware.\nFor reception, the RXNE flag is set and its interrupt, if allowed, is generated when the first \n16 MSB half-word is received.\nIn this way, more time is provided between two write or read operations, which prevents \nunderrun or overrun conditions (depending on the direction of the data transfer).\nMSB justified standard\nFor this standard, the WS signal is generated at the same time as the first data bit, which is \nthe MSBit.\nMS19594V1\n0x8EAA\n0x33XX\nFirst read to Data register\nSecond read to Data register\nOnly the 8 MSB are sent \nto compare the 24 bits\n8 LSBs have no meaning \nand can be anything\nMS19599V1\nCK\nWS\nSD\nTransmission\nReception\n16-bit data\nMSB\nLSB\nChannel left 32-bit\nChannel right\n16-bit remaining 0 forced\nMS19595V1\n0x76A3\nOnly one access to SPIx_DR\n\n\n<>\n\nRM0090 Rev 21\n907/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nFigure 270. MSB justified 16-bit or 32-bit full-accuracy length with CPOL = 0\nData are latched on the falling edge of CK (for transmitter) and are read on the rising edge \n(for the receiver).\nFigure 271. MSB justified 24-bit frame length with CPOL = 0\nFigure 272. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0\nLSB justified standard\nThis standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit \nfull-accuracy frame formats).\nMS30100 V1\nCK\nWS\nSD\nTransmission\nReception\n16- or 32 bit data\nMSB\nLSB\nChannel left\nChannel right\nMSB\nMS30101V1\nCK\nWS\nSD\nTransmission\nReception\n24 bit data\nMSB\nLSB\nChannel left 32-bit\nChannel right\n8-bit remaining\n0 forced\nMS30102V1\nCK\nWS\nSD\nTransmission\nReception\n16-bit data\nMSB\nLSB\nChannel left 32-bit\nChannel right\n16-bit remaining\n0 forced\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n908/1757\nRM0090 Rev 21\nFigure 273. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0\nFigure 274. LSB justified 24-bit frame length with CPOL = 0\n•\nIn transmission mode:\nIf data 0x3478AE have to be transmitted, two write operations to the SPI_DR register \nare required from software or by DMA. The operations are shown below.\nFigure 275. Operations required to transmit 0x3478AE\n•\nIn reception mode:\nIf data 0x3478AE are received, two successive read operations from SPI_DR are \nrequired on each RXNE event.\nMS30103V1\nCK\nWS\nSD\nTransmission\nReception\n16- or 32-bit data\nMSB\nLSB\nChannel left\nChannel right\nMSB\nMS30104V1\nCK\nWS\nSD\nTransmission\nReception\n8-bit data\n0 forced\nMSB\nLSB\nChannel left 32-bit\nChannel right\n24-bit remaining\n0xXX34\n0x78AE\nFirst write to Data register \nconditioned by TXE=1\nSecond write to Data register \nconditioned by TXE=1\nOnly the 8 LSB of the \nhalf-word are significant. \nA field of 0x00 is forced \ninstead of the 8 MSBs.\nMS19596V1\n\n\n<>\n\nRM0090 Rev 21\n909/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nFigure 276. Operations required to receive 0x3478AE\nFigure 277. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0\nWhen 16-bit data frame extended to 32-bit channel frame is selected during the I2S \nconfiguration phase, Only one access to SPI_DR is required. The 16 remaining bits are \nforced by hardware to 0x0000 to extend the data to 32-bit format. In this case it corresponds \nto the half-word MSB.\nIf the data to transmit or the received data are 0x76A3 (0x0000 76A3 extended to 32-bit), \nthe operation shown in Figure 278 is required.\nFigure 278. Example of LSB justified 16-bit extended to 32-bit packet frame\nIn transmission mode, when TXE is asserted, the application has to write the data to be \ntransmitted (in this case 0x76A3). The 0x000 field is transmitted first (extension on 32-bit). \nTXE is asserted again as soon as the effective data (0x76A3) is sent on SD.\nIn reception mode, RXNE is asserted as soon as the significant half-word is received (and \nnot the 0x0000 field).\nIn this way, more time is provided between two write or read operations to prevent underrun \nor overrun conditions.\n0xXX34\n0x78AE\nFirst read from Data register \nconditioned by RXNE=1\nSecond read from Data register \nconditioned by RXNE=1\nOnly the 8 LSB of the \nhalf-word are significant. \nA field of 0x00 is forced \ninstead of the 8 MSBs.\nMS19597V1\nMS30105V1\nCK\nWS\nSD\nTransmission\nReception\n16-bit data\n0 forced\nMSB\nLSB\nChannel left 32-bit\nChannel right\n16-bit remaining\n0x76A3\nOnly one access to the SPIx-DR register\nMS19598V1\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n910/1757\nRM0090 Rev 21\nPCM standard\nFor the PCM standard, there is no need to use channel-side information. The two PCM \nmodes (short and long frame) are available and configurable using the PCMSYNC bit in \nSPI_I2SCFGR.\nFigure 279. PCM standard waveforms (16-bit)\nFor long frame synchronization, the WS signal assertion time is fixed 13 bits in master \nmode.\nFor short frame synchronization, the WS synchronization signal is only one cycle long.\nFigure 280. PCM standard waveforms (16-bit extended to 32-bit packet frame)\nNote:\nFor both modes (master and slave) and for both synchronizations (short and long), the \nnumber of bits between two consecutive pieces of data (and so two synchronization signals) \nneeds to be specified (DATLEN and CHLEN bits in the SPI_I2SCFGR register) even in \nslave mode.\n28.4.4 \nClock generator\nThe I2S bitrate determines the dataflow on the I2S data line and the I2S clock signal \nfrequency.\nI2S bitrate = number of bits per channel × number of channels × sampling audio frequency\nFor a 16-bit audio, left and right channel, the I2S bitrate is calculated as follows:\nI2S bitrate = 16 × 2 × FS\nIt is I2S bitrate = 32 x 2 x FS if the packet length is 32-bit wide.\nMS30106V1\nCK\nWS\nshort frame\nSD\nWS\nlong frame\n13-bits\nMSB\nLSB MSB\nMS30107V1\nCK\nWS\nshort frame\nSD\nWS\nlong frame\nUp to 13-bits\nMSB\nLSB\n16 bits\n\n\n<>\n\nRM0090 Rev 21\n911/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nFigure 281. Audio sampling frequency definition\nWhen the master mode is configured, a specific action needs to be taken to properly \nprogram the linear divider in order to communicate with the desired audio frequency.\nFigure 282. I2S clock generator architecture\n1.\nWhere x could be 2 or 3.\nFigure 281 presents the communication clock architecture. To achieve high-quality audio \nperformance, the I2SxCLK clock source can be either the PLLI2S output (through R division \nfactor) or an external clock (mapped to I2S_CKIN pin).\nThe audio sampling frequency can be 192 kHz, 96 kHz, or 48 kHz. In order to reach the \ndesired frequency, the linear divider needs to be programmed according to the formulas \nbelow:\nWhen the master clock is generated (MCKOE in the SPI_I2SPR register is set):\nFS = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide\nFS = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide\nWhen the master clock is disabled (MCKOE bit cleared):\nFS = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide\nFS = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide\nTable 128 provides example precision values for different clock configurations.\nNote:\nOther configurations are possible that allow optimum clock precision.\nMS30108V1\n16-or 32-bit left \nchannel\n16-or 32-bit \nright channel\n32- or 64-bits\nsampling point\nsampling point\nFS\nFS : audio sampling frequency\nMS30109V1\nMCKOE ODD\n8-bit linear divider \n+ reshaping stage\nDivider by 4\nDiv2\nI²SDIV[7:0]\nI²SMOD\nCHLEN\n0\n1\n0\n1\nMCKOE\nCK\nMCK\nI²SxCLK\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n912/1757\nRM0090 Rev 21\n \n \n28.4.5 \nI2S master mode\nThe I2S can be configured as follows: \n•\nIn master mode for transmission or reception (half-duplex mode using I2Sx)\n•\nIn master mode transmission and reception (full duplex mode using I2Sx and \nI2Sx_ext).\nThis means that the serial clock is generated on the CK pin as well as the Word Select \nsignal WS. Master clock (MCK) may be output or not, thanks to the MCKOE bit in the \nSPI_I2SPR register.\nTable 128. Audio frequency precision (for PLLM VCO = 1 MHz or 2 MHz)(1)\nMaster \nclock\nTarget fS \n(Hz)\nData \nformat\nPLLI2SN\nPLLI2SR\nI2SDIV\nI2SODD\nReal fS (Hz)\nError\nDisabled\n8000\n16-bit\n192\n2\n187\n1\n8000\n0.0000%\n32-bit\n192\n3\n62\n1\n8000\n0.0000%\n16000\n16-bit\n192\n3\n62\n1\n16000\n0.0000%\n32-bit\n256\n2\n62\n1\n16000\n0.0000%\n32000\n16-bit\n256\n2\n62\n1\n32000\n0.0000%\n32-bit\n256\n5\n12\n1\n32000\n0.0000%\n48000\n16-bit\n192\n5\n12\n1\n48000\n0.0000%\n32-bit\n384\n5\n12\n1\n48000\n0.0000%\n96000\n16-bit\n384\n5\n12\n1\n96000\n0.0000%\n32-bit\n424\n3\n11\n1\n96014.49219\n0.0151%\n22050\n16-bit\n290\n3\n68\n1\n22049.87695\n0.0006%\n32-bit\n302\n2\n53\n1\n22050.23438\n0.0011%\n44100\n16-bit\n302\n2\n53\n1\n44100.46875\n0.0011%\n32-bit\n429\n4\n19\n0\n44099.50781\n0.0011%\n192000\n16-bit\n424\n3\n11\n1\n192028.9844\n0.0151%\n32-bit\n258\n3\n3\n1\n191964.2813\n0.0186%\nEnabled\n8000\ndon't care\n256\n5\n12\n1\n8000\n0.0000%\n16000\ndon't care\n213\n2\n13\n0\n16000.60059\n0.0038%\n32000\ndon't care\n213\n2\n6\n1\n32001.20117\n0.0038%\n48000\ndon't care\n258\n3\n3\n1\n47991.07031\n0.0186%\n96000\ndon't care\n344\n2\n3\n1\n95982.14063\n0.0186%\n22050\ndon't care\n429\n4\n9\n1\n22049.75391\n0.0011%\n44100\ndon't care\n271\n2\n6\n0\n44108.07422\n0.0183%\n1.\nThis table gives only example values for different clock configurations. Other configurations allowing optimum clock \nprecision are possible.\n\n\n<>\n\nRM0090 Rev 21\n913/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nProcedure\n1.\nSelect the I2SDIV[7:0] bits in the SPI_I2SPR register to define the serial clock baud \nrate to reach the proper audio sample frequency. The ODD bit in the SPI_I2SPR \nregister also has to be defined.\n2. \nSelect the CKPOL bit to define the steady level for the communication clock. Set the \nMCKOE bit in the SPI_I2SPR register if the master clock MCK needs to be provided to \nthe external DAC/ADC audio component (the I2SDIV and ODD values should be \ncomputed depending on the state of the MCK output, for more details refer to \nSection 28.4.4: Clock generator).\n3. \nSet the I2SMOD bit in SPI_I2SCFGR to activate the I2S functionalities and choose the \nI2S standard through the I2SSTD[1:0] and PCMSYNC bits, the data length through the \nDATLEN[1:0] bits and the number of bits per channel by configuring the CHLEN bit. \nSelect also the I2S master mode and direction (Transmitter or Receiver) through the \nI2SCFG[1:0] bits in the SPI_I2SCFGR register.\n4. \nIf needed, select all the potential interruption sources and the DMA capabilities by \nwriting the SPI_CR2 register.\n5. \nThe I2SE bit in SPI_I2SCFGR register must be set.\nWS and CK are configured in output mode. MCK is also an output, if the MCKOE bit in \nSPI_I2SPR is set.\nTransmission sequence\nThe transmission sequence begins when a half-word is written into the Tx buffer.\nAssumedly, the first data written into the Tx buffer correspond to the channel Left data. \nWhen data are transferred from the Tx buffer to the shift register, TXE is set and data \ncorresponding to the channel Right have to be written into the Tx buffer. The CHSIDE flag \nindicates which channel is to be transmitted. It has a meaning when the TXE flag is set \nbecause the CHSIDE flag is updated when TXE goes high.\nA full frame has to be considered as a Left channel data transmission followed by a Right \nchannel data transmission. It is not possible to have a partial frame where only the left \nchannel is sent.\nThe data half-word is parallel loaded into the 16-bit shift register during the first bit \ntransmission, and then shifted out, serially, to the MOSI/SD pin, MSB first. The TXE flag is \nset after each transfer from the Tx buffer to the shift register and an interrupt is generated if \nthe TXEIE bit in the SPI_CR2 register is set.\nFor more details about the write operations depending on the I2S standard mode selected, \nrefer to Section 28.4.3: Supported audio protocols).\nTo ensure a continuous audio data transmission, it is mandatory to write the SPI_DR with \nthe next data to transmit before the end of the current transmission.\nTo switch off the I2S, by clearing I2SE, it is mandatory to wait for TXE = 1 and BSY = 0.\nReception sequence\nThe operating mode is the same as for the transmission mode except for the point 3 (refer to \nthe procedure described in Section 28.4.5: I2S master mode), where the configuration \nshould set the master reception mode through the I2SCFG[1:0] bits.\nWhatever the data or channel length, the audio data are received by 16-bit packets. This \nmeans that each time the Rx buffer is full, the RXNE flag is set and an interrupt is generated \n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n914/1757\nRM0090 Rev 21\nif the RXNEIE bit is set in SPI_CR2 register. Depending on the data and channel length \nconfiguration, the audio value received for a right or left channel may result from one or two \nreceptions into the Rx buffer.\nClearing the RXNE bit is performed by reading the SPI_DR register.\nCHSIDE is updated after each reception. It is sensitive to the WS signal generated by the \nI2S cell.\nFor more details about the read operations depending on the I2S standard mode selected, \nrefer to Section 28.4.3: Supported audio protocols.\nIf data are received while the previously received data have not been read yet, an overrun is \ngenerated and the OVR flag is set. If the ERRIE bit is set in the SPI_CR2 register, an \ninterrupt is generated to indicate the error.\nTo switch off the I2S, specific actions are required to ensure that the I2S completes the \ntransfer cycle properly without initiating a new data transfer. The sequence depends on the \nconfiguration of the data and channel lengths, and on the audio protocol mode selected. In \nthe case of:\n•\n16-bit data length extended on 32-bit channel length (DATLEN = 00 and CHLEN = 1) \nusing the LSB justified mode (I2SSTD = 10)\na) \nWait for the second to last RXNE = 1 (n – 1)\nb) \nThen wait 17 I2S clock cycles (using a software loop)\nc) \nDisable the I2S (I2SE = 0)\n•\n16-bit data length extended on 32-bit channel length (DATLEN = 00 and CHLEN = 1) in \nMSB justified, I2S or PCM modes (I2SSTD = 00, I2SSTD = 01 or I2SSTD = 11, \nrespectively)\na) \nWait for the last RXNE\nb) \nThen wait 1 I2S clock cycle (using a software loop)\nc) \nDisable the I2S (I2SE = 0)\n•\nFor all other combinations of DATLEN and CHLEN, whatever the audio mode selected \nthrough the I2SSTD bits, carry out the following sequence to switch off the I2S:\na) \nWait for the second to last RXNE = 1 (n – 1)\nb) \nThen wait one I2S clock cycle (using a software loop)\nc) \nDisable the I2S (I2SE = 0)\nNote:\nThe BSY flag is kept low during transfers.\n28.4.6 \nI2S slave mode\nThe I2S can be configured as follows: \n•\nIn slave mode for transmission or reception (half-duplex mode using I2Sx)\n•\nIn slave mode transmission and reception (full duplex mode using I2Sx and I2Sx_ext).\nThe operating mode is following mainly the same rules as described for the I2S master \nconfiguration. In slave mode, there is no clock to be generated by the I2S interface. The \nclock and WS signals are input from the external master connected to the I2S interface. \nThere is then no need, for the user, to configure the clock.\nThe configuration steps to follow are listed below:\n\n\n<>\n\nRM0090 Rev 21\n915/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n1.\nSet the I2SMOD bit in the SPI_I2SCFGR register to reach the I2S functionalities and \nchoose the I2S standard through the I2SSTD[1:0] bits, the data length through the \nDATLEN[1:0] bits and the number of bits per channel for the frame configuring the \nCHLEN bit. Select also the mode (transmission or reception) for the slave through the \nI2SCFG[1:0] bits in SPI_I2SCFGR register.\n2. \nIf needed, select all the potential interrupt sources and the DMA capabilities by writing \nthe SPI_CR2 register.\n3. \nThe I2SE bit in SPI_I2SCFGR register must be set.\nTransmission sequence\nThe transmission sequence begins when the external master device sends the clock and \nwhen the NSS_WS signal requests the transfer of data. The slave has to be enabled before \nthe external master starts the communication. The I2S data register has to be loaded before \nthe master initiates the communication.\nFor the I2S, MSB justified and LSB justified modes, the first data item to be written into the \ndata register corresponds to the data for the left channel. When the communication starts, \nthe data are transferred from the Tx buffer to the shift register. The TXE flag is then set in \norder to request the right channel data to be written into the I2S data register.\nThe CHSIDE flag indicates which channel is to be transmitted. Compared to the master \ntransmission mode, in slave mode, CHSIDE is sensitive to the WS signal coming from the \nexternal master. This means that the slave needs to be ready to transmit the first data \nbefore the clock is generated by the master. WS assertion corresponds to left channel \ntransmitted first.\nNote:\nThe I2SE has to be written at least two PCLK cycles before the first clock of the master \ncomes on the CK line.\nThe data half-word is parallel-loaded into the 16-bit shift register (from the internal bus) \nduring the first bit transmission, and then shifted out serially to the MOSI/SD pin MSB first. \nThe TXE flag is set after each transfer from the Tx buffer to the shift register and an interrupt \nis generated if the TXEIE bit in the SPI_CR2 register is set.\nNote that the TXE flag should be checked to be at 1 before attempting to write the Tx buffer.\nFor more details about the write operations depending on the I2S standard mode selected, \nrefer to Section 28.4.3: Supported audio protocols.\nTo secure a continuous audio data transmission, it is mandatory to write the SPI_DR \nregister with the next data to transmit before the end of the current transmission. An \nunderrun flag is set and an interrupt may be generated if the data are not written into the \nSPI_DR register before the first clock edge of the next data communication. This indicates \nto the software that the transferred data are wrong. If the ERRIE bit is set into the SPI_CR2 \nregister, an interrupt is generated when the UDR flag in the SPI_SR register goes high. In \nthis case, it is mandatory to switch off the I2S and to restart a data transfer starting from the \nleft channel.\nTo switch off the I2S, by clearing the I2SE bit, it is mandatory to wait for TXE = 1 and \nBSY = 0.\nReception sequence\nThe operating mode is the same as for the transmission mode except for the point 1 (refer to \nthe procedure described in Section 28.4.6: I2S slave mode), where the configuration should \nset the master reception mode using the I2SCFG[1:0] bits in the SPI_I2SCFGR register.\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n916/1757\nRM0090 Rev 21\nWhatever the data length or the channel length, the audio data are received by 16-bit \npackets. This means that each time the RX buffer is full, the RXNE flag in the SPI_SR \nregister is set and an interrupt is generated if the RXNEIE bit is set in the SPI_CR2 register. \nDepending on the data length and channel length configuration, the audio value received for \na right or left channel may result from one or two receptions into the RX buffer.\nThe CHSIDE flag is updated each time data are received to be read from SPI_DR. It is \nsensitive to the external WS line managed by the external master component.\nClearing the RXNE bit is performed by reading the SPI_DR register.\nFor more details about the read operations depending the I2S standard mode selected, refer \nto Section 28.4.3: Supported audio protocols.\nIf data are received while the precedent received data have not yet been read, an overrun is \ngenerated and the OVR flag is set. If the bit ERRIE is set in the SPI_CR2 register, an \ninterrupt is generated to indicate the error.\nTo switch off the I2S in reception mode, I2SE has to be cleared immediately after receiving \nthe last RXNE = 1.\nNote:\nThe external master components should have the capability of sending/receiving data in 16-\nbit or 32-bit packets via an audio channel.\n28.4.7 \nStatus flags\nThree status flags are provided for the application to fully monitor the state of the I2S bus.\nBusy flag (BSY)\nThe BSY flag is set and cleared by hardware (writing to this flag has no effect). It indicates \nthe state of the communication layer of the I2S.\nWhen BSY is set, it indicates that the I2S is busy communicating. There is one exception in \nmaster receive mode (I2SCFG = 11) where the BSY flag is kept low during reception.\nThe BSY flag is useful to detect the end of a transfer if the software needs to disable the I2S. \nThis avoids corrupting the last transfer. For this, the procedure described below must be \nstrictly respected.\nThe BSY flag is set when a transfer starts, except when the I2S is in master receiver mode.\nThe BSY flag is cleared:\n•\nwhen a transfer completes (except in master transmit mode, in which the \ncommunication is supposed to be continuous)\n•\nwhen the I2S is disabled\nWhen communication is continuous:\n•\nIn master transmit mode, the BSY flag is kept high during all the transfers\n•\nIn slave mode, the BSY flag goes low for one I2S clock cycle between each transfer\nNote:\nDo not use the BSY flag to handle each data transmission or reception. It is better to use the \nTXE and RXNE flags instead.\n\n\n<>\n\nRM0090 Rev 21\n917/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nTx buffer empty flag (TXE)\nWhen set, this flag indicates that the Tx buffer is empty and the next data to be transmitted \ncan then be loaded into it. The TXE flag is reset when the Tx buffer already contains data to \nbe transmitted. It is also reset when the I2S is disabled (I2SE bit is reset).\nRX buffer not empty (RXNE)\nWhen set, this flag indicates that there are valid received data in the RX Buffer. It is reset \nwhen SPI_DR register is read.\nChannel Side flag (CHSIDE)\nIn transmission mode, this flag is refreshed when TXE goes high. It indicates the channel \nside to which the data to transfer on SD has to belong. In case of an underrun error event in \nslave transmission mode, this flag is not reliable and I2S needs to be switched off and \nswitched on before resuming the communication.\nIn reception mode, this flag is refreshed when data are received into SPI_DR. It indicates \nfrom which channel side data have been received. Note that in case of error (like OVR) this \nflag becomes meaningless and the I2S should be reset by disabling and then enabling it \n(with configuration if it needs changing).\nThis flag has no meaning in the PCM standard (for both Short and Long frame modes).\nWhen the OVR or UDR flag in the SPI_SR is set and the ERRIE bit in SPI_CR2 is also set, \nan interrupt is generated. This interrupt can be cleared by reading the SPI_SR status \nregister (once the interrupt source has been cleared).\n28.4.8 \nError flags\nThere are three error flags for the I2S cell.\nUnderrun flag (UDR)\nIn slave transmission mode this flag is set when the first clock for data transmission appears \nwhile the software has not yet loaded any value into SPI_DR. It is available when the \nI2SMOD bit in SPI_I2SCFGR is set. An interrupt may be generated if the ERRIE bit in \nSPI_CR2 is set.\nThe UDR bit is cleared by a read operation on the SPI_SR register.\nOverrun flag (OVR)\nThis flag is set when data are received and the previous data have not yet been read from \nSPI_DR. As a result, the incoming data are lost. An interrupt may be generated if the ERRIE \nbit is set in SPI_CR2.\nIn this case, the receive buffer contents are not updated with the newly received data from \nthe transmitter device. A read operation to the SPI_DR register returns the previous \ncorrectly received data. All other subsequently transmitted half-words are lost.\nClearing the OVR bit is done by a read operation on the SPI_DR register followed by a read \naccess to the SPI_SR register.\nFrame error flag (FRE)\nThis flag can be set by hardware only if the I2S is configured in Slave mode. It is set if the \nexternal master is changing the WS line at a moment when the slave is not expected this \n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n918/1757\nRM0090 Rev 21\nchange. If the synchronization is lost, to recover from this state and resynchronize the \nexternal master device with the I2S slave device, follow the steps below:\n1.\nDisable the I2S\n2. \nRe-enable it when the correct level is detected on the WS line (WS line is high in I2S \nmode, or low for MSB- or LSB-justified or PCM modes). \nDesynchronization between the master and slave device may be due to noisy environment \non the SCK communication clock or on the WS frame synchronization line. An error interrupt \ncan be generated if the ERRIE bit is set. The desynchronization flag (FRE) is cleared by \nsoftware when the status register is read.\n28.4.9 \nI2S interrupts\nTable 129 provides the list of I2S interrupts.\n \n28.4.10 \nDMA features\nDMA is working in exactly the same way as for the SPI mode. There is no difference on the \nI2S. Only the CRC feature is not available in I2S mode since there is no data transfer \nprotection system.\nTable 129. I2S interrupt requests\nInterrupt event\nEvent flag\nEnable Control bit\nTransmit buffer empty flag\nTXE\nTXEIE\nReceive buffer not empty flag\nRXNE\nRXNEIE\nOverrun error\nOVR\nERRIE\nUnderrun error\nUDR\nFrame error flag\nFRE\nERRIE\n\n\n<>\n\nRM0090 Rev 21\n919/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.5 \nSPI and I2S registers\nThe peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).\n28.5.1 \nSPI control register 1 (SPI_CR1) (not used in I2S mode)\nAddress offset: 0x00\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nBIDI\nMODE\nBIDI\nOE\nCRC\nEN\nCRC\nNEXT\nDFF\nRX\nONLY\nSSM\nSSI\nLSB\nFIRST\nSPE\nBR [2:0]\nMSTR\nCPOL\nCPHA\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 BIDIMODE: Bidirectional data mode enable\n0: 2-line unidirectional data mode selected\n1: 1-line bidirectional data mode selected\nNote: This bit is not used in I2S mode\nBit 14 BIDIOE: Output enable in bidirectional mode\nThis bit combined with the BIDImode bit selects the direction of transfer in bidirectional mode\n0: Output disabled (receive-only mode) \n1: Output enabled (transmit-only mode)\nNote: This bit is not used in I2S mode.\nIn master mode, the MOSI pin is used while the MISO pin is used in slave mode.\nBit 13 CRCEN: Hardware CRC calculation enable\n0: CRC calculation disabled\n1: CRC calculation enabled\nNote: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation. \nIt is not used in I2S mode.\nBit 12 CRCNEXT: CRC transfer next\n0: Data phase (no CRC phase) \n1: Next transfer is CRC (CRC phase)\nNote: When the SPI is configured in full duplex or transmitter only modes, CRCNEXT must be \nwritten as soon as the last data is written to the SPI_DR register. \nWhen the SPI is configured in receiver only mode, CRCNEXT must be set after the \nsecond last data reception. \nThis bit should be kept cleared when the transfers are managed by DMA.\nIt is not used in I2S mode.\nBit 11 DFF: Data frame format\n0: 8-bit data frame format is selected for transmission/reception\n1: 16-bit data frame format is selected for transmission/reception\nNote: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation.\nIt is not used in I2S mode.\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n920/1757\nRM0090 Rev 21\nBit 10 RXONLY: Receive only\nThis bit combined with the BIDImode bit selects the direction of transfer in 2-line \nunidirectional mode. This bit is also useful in a multislave system in which this particular \nslave is not accessed, the output from the accessed slave is not corrupted.\n0: Full duplex (Transmit and receive)\n1: Output disabled (Receive-only mode)\nNote: This bit is not used in I2S mode\nBit 9 SSM: Software slave management\nWhen the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit.\n0: Software slave management disabled\n1: Software slave management enabled\nNote: This bit is not used in I2S mode and SPI TI mode\nBit 8 SSI: Internal slave select\nThis bit has an effect only when the SSM bit is set. The value of this bit is forced onto the \nNSS pin and the IO value of the NSS pin is ignored.\nNote: This bit is not used in I2S mode and SPI TI mode\nBit 7 LSBFIRST: Frame format\n0: MSB transmitted first\n1: LSB transmitted first\nNote: This bit should not be changed when communication is ongoing.\nIt is not used in I2S mode and SPI TI mode\nBit 6 SPE: SPI enable\n0: Peripheral disabled\n1: Peripheral enabled\nNote: This bit is not used in I2S mode.\nWhen disabling the SPI, follow the procedure described in Section 28.3.8.\nBits 5:3 BR[2:0]: Baud rate control\n000: fPCLK/2\n001: fPCLK/4\n010: fPCLK/8\n011: fPCLK/16\n100: fPCLK/32\n101: fPCLK/64\n110: fPCLK/128\n111: fPCLK/256\nNote: These bits should not be changed when communication is ongoing.\nThey are not used in I2S mode.\nBit 2 MSTR: Master selection \n0: Slave configuration\n1: Master configuration\nNote: This bit should not be changed when communication is ongoing.\nIt is not used in I2S mode.\n\n\n<>\n\nRM0090 Rev 21\n921/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.5.2 \nSPI control register 2 (SPI_CR2)\nAddress offset: 0x04\nReset value: 0x0000\n \nBit1 CPOL: Clock polarity \n0: CK to 0 when idle\n1: CK to 1 when idle\nNote: This bit should not be changed when communication is ongoing.\nIt is not used in I2S mode and SPI TI mode.\nBit 0 CPHA: Clock phase \n0: The first clock transition is the first data capture edge\n1: The second clock transition is the first data capture edge\nNote: This bit should not be changed when communication is ongoing.\nIt is not used in I2S mode and SPI TI mode.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTXEIE\nRXNEIE\nERRIE\nFRF\nRes.\nSSOE\nTXDMAEN RXDMAEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 TXEIE: Tx buffer empty interrupt enable\n0: TXE interrupt masked \n1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set.\nBit 6 RXNEIE: RX buffer not empty interrupt enable\n0: RXNE interrupt masked \n1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is \nset.\nBit 5 ERRIE: Error interrupt enable\nThis bit controls the generation of an interrupt when an error condition occurs )(CRCERR, \nOVR, MODF in SPI mode, FRE in TI mode and UDR, OVR, and FRE in I2S mode).\n0: Error interrupt is masked\n1: Error interrupt is enabled\nBit 4 FRF: Frame format\n0: SPI Motorola mode\n1 SPI TI mode \nNote: This bit is not used in I2S mode.\nBit 3 Reserved. Forced to 0 by hardware.\nBit 2 SSOE: SS output enable\n0: SS output is disabled in master mode and the cell can work in multimaster configuration\n1: SS output is enabled in master mode and when the cell is enabled. The cell cannot work \nin a multimaster environment.\nNote: This bit is not used in I2S mode and SPI TI mode.\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n922/1757\nRM0090 Rev 21\n28.5.3 \nSPI status register (SPI_SR)\nAddress offset: 0x08\nReset value: 0x0002\n \nBit 1 TXDMAEN: Tx buffer DMA enable\nWhen this bit is set, the DMA request is made whenever the TXE flag is set.\n0: Tx buffer DMA disabled\n1: Tx buffer DMA enabled\nBit 0 RXDMAEN: Rx buffer DMA enable\nWhen this bit is set, the DMA request is made whenever the RXNE flag is set.\n0: Rx buffer DMA disabled\n1: Rx buffer DMA enabled\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFRE\nBSY\nOVR\nMODF\nCRC\nERR\nUDR\nCHSIDE\nTXE\nRXNE\nr\nr\nr\nr\nrc_w0\nr\nr\nr\nr\nBits 15:9 Reserved. Forced to 0 by hardware.\nBit 8 FRE: Frame format error\n0: No frame format error\n1: A frame format error occurred\nThis flag is set by hardware and cleared by software when the SPIx_SR register is read.\nNote: This flag is used when the SPI operates in TI slave mode or I2S slave mode (refer to \nSection 28.3.10).\nBit 7 BSY: Busy flag\n0: SPI (or I2S) not busy\n1: SPI (or I2S) is busy in communication or Tx buffer is not empty\nThis flag is set and cleared by hardware.\nNote: BSY flag must be used with caution: refer to Section 28.3.7 and Section 28.3.8.\nBit 6 OVR: Overrun flag\n0: No overrun occurred\n1: Overrun occurred\nThis flag is set by hardware and reset by a software sequence (see Section 28.3.10).\nBit 5 MODF: Mode fault\n0: No mode fault occurred\n1: Mode fault occurred\nThis flag is set by hardware and reset by a software sequence (see Section 28.3.10).\nNote: This bit is not used in I2S mode\nBit 4 CRCERR: CRC error flag\n0: CRC value received matches the SPI_RXCRCR value\n1: CRC value received does not match the SPI_RXCRCR value\nThis flag is set by hardware and cleared by software writing 0.\nNote: This bit is not used in I2S mode.\n\n\n<>\n\nRM0090 Rev 21\n923/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.5.4 \nSPI data register (SPI_DR)\nAddress offset: 0x0C\nReset value: 0x0000\n \n \nBit 3 UDR: Underrun flag\n0: No underrun occurred\n1: Underrun occurred\nThis flag is set by hardware and reset by a software sequence. Refer to Section 28.4.8: \nError flags for the software sequence.\nNote: This bit is not used in SPI mode.\nBit 2 CHSIDE: Channel side\n0: Channel Left has to be transmitted or has been received\n1: Channel Right has to be transmitted or has been received\nNote: This bit is not used for SPI mode and is meaningless in PCM mode.\nBit 1 TXE: Transmit buffer empty\n0: Tx buffer not empty\n1: Tx buffer empty\nBit 0 RXNE: Receive buffer not empty\n0: Rx buffer empty\n1: Rx buffer not empty\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDR[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 DR[15:0]: Data register\nData received or to be transmitted.\nThe data register is split into 2 buffers - one for writing (Transmit Buffer) and another one for \nreading (Receive buffer). A write to the data register writes into the Tx buffer and a read \nfrom the data register returns the value held in the Rx buffer.\nNote: These notes apply to SPI mode:\nDepending on the data frame format selection bit (DFF in SPI_CR1 register), the data \nsent or received is either 8-bit or 16-bit. This selection has to be made before enabling \nthe SPI to ensure correct operation. \nFor an 8-bit data frame, the buffers are 8-bit and only the LSB of the register \n(SPI_DR[7:0]) is used for transmission/reception. When in reception mode, the MSB of \nthe register (SPI_DR[15:8]) is forced to 0.\nFor a 16-bit data frame, the buffers are 16-bit and the entire register, SPI_DR[15:0] is \nused for transmission/reception.\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n924/1757\nRM0090 Rev 21\n28.5.5 \nSPI CRC polynomial register (SPI_CRCPR) (not used in I2S\nmode)\nAddress offset: 0x10\nReset value: 0x0007\n \n28.5.6 \nSPI RX CRC register (SPI_RXCRCR) (not used in I2S mode)\nAddress offset: 0x14\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCRCPOLY[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CRCPOLY[15:0]: CRC polynomial register\nThis register contains the polynomial for the CRC calculation.\nThe CRC polynomial (0007h) is the reset value of this register. Another polynomial can be \nconfigured as required.\nNote: These bits are not used for the I2S mode.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRXCRC[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 15:0 RXCRC[15:0]: Rx CRC register\nWhen CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of \nthe subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1 \nregister is written to 1. The CRC is calculated serially using the polynomial programmed in \nthe SPI_CRCPR register. \nOnly the 8 LSB bits are considered when the data frame format is set to be 8-bit data (DFF \nbit of SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard.\nThe entire 16-bits of this register are considered when a 16-bit data frame format is selected \n(DFF bit of the SPI_CR1 register is set). CRC calculation is done based on any CRC16 \nstandard.\nNote: A read to this register when the BSY Flag is set could return an incorrect value.\nThese bits are not used for I2S mode.\n\n\n<>\n\nRM0090 Rev 21\n925/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.5.7 \nSPI TX CRC register (SPI_TXCRCR) (not used in I2S mode)\nAddress offset: 0x18\nReset value: 0x0000\n \n28.5.8 \nSPI_I2S configuration register (SPI_I2SCFGR)\nAddress offset: 0x1C\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTXCRC[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 15:0 TXCRC[15:0]: Tx CRC register\nWhen CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of \nthe subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 \nis written to 1. The CRC is calculated serially using the polynomial programmed in the \nSPI_CRCPR register.\nOnly the 8 LSB bits are considered when the data frame format is set to be 8-bit data (DFF \nbit of SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard.\nThe entire 16-bits of this register are considered when a 16-bit data frame format is selected \n(DFF bit of the SPI_CR1 register is set). CRC calculation is done based on any CRC16 \nstandard.\nNote: A read to this register when the BSY flag is set could return an incorrect value.\nThese bits are not used for I2S mode.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nI2SMOD\nI2SE\nI2SCFG\nPCMSY\nNC\nRes.\nI2SSTD\nCKPOL\nDATLEN\nCHLEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:12 Reserved, must be kept at reset value.\nBit 11 I2SMOD: I2S mode selection\n0: SPI mode is selected\n1: I2S mode is selected\nNote: This bit should be configured when the SPI or I2S is disabled\nBit 10 I2SE: I2S Enable\n0: I2S peripheral is disabled\n1: I2S peripheral is enabled\nNote: This bit is not used in SPI mode.\nBits 9:8 I2SCFG: I2S configuration mode\n00: Slave - transmit\n01: Slave - receive\n10: Master - transmit\n11: Master - receive\nNote: This bit should be configured when the I2S is disabled.\nIt is not used in SPI mode.\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n926/1757\nRM0090 Rev 21\nBit 7 PCMSYNC: PCM frame synchronization\n0: Short frame synchronization\n1: Long frame synchronization\nNote: This bit has a meaning only if I2SSTD = 11 (PCM standard is used)\nIt is not used in SPI mode.\nBit 6 Reserved: forced at 0 by hardware\nBits 5:4 I2SSTD: I2S standard selection\n00: I2S Philips standard.\n01: MSB justified standard (left justified)\n10: LSB justified standard (right justified)\n11: PCM standard\nFor more details on I2S standards, refer to Section 28.4.3: Supported audio protocols. Not used \nin SPI mode.\nNote: For correct operation, these bits should be configured when the I2S is disabled.\nBit 3 CKPOL: Steady state clock polarity\n0: I2S clock steady state is low level\n1: I2S clock steady state is high level\nNote: For correct operation, this bit should be configured when the I2S is disabled.\nThis bit is not used in SPI mode\nBits 2:1 DATLEN: Data length to be transferred\n00: 16-bit data length\n01: 24-bit data length\n10: 32-bit data length\n11: Not allowed\nNote: For correct operation, these bits should be configured when the I2S is disabled.\nThis bit is not used in SPI mode.\nBit 0 CHLEN: Channel length (number of bits per audio channel)\n0: 16-bit wide\n1: 32-bit wide\nThe bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to \n32-bit by hardware whatever the value filled in. Not used in SPI mode.\nNote: For correct operation, this bit should be configured when the I2S is disabled.\n\n\n<>\n\nRM0090 Rev 21\n927/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.5.9 \nSPI_I2S prescaler register (SPI_I2SPR)\nAddress offset: 0x20\nReset value: 0000 0010 (0x0002)\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMCKOE\nODD\nI2SDIV\nrw\nrw\nrw\nBits 15:10 Reserved, must be kept at reset value.\nBit 9 MCKOE: Master clock output enable\n0: Master clock output is disabled\n1: Master clock output is enabled\nNote: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master \nmode.\nThis bit is not used in SPI mode.\nBit 8 ODD: Odd factor for the prescaler\n0: real divider value is = I2SDIV *2\n1: real divider value is = (I2SDIV * 2)+1\nRefer to Section 28.4.4: Clock generator. Not used in SPI mode.\nNote: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master \nmode.\nBits 7:0 I2SDIV: I2S Linear prescaler\nI2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.\nRefer to Section 28.4.4: Clock generator. Not used in SPI mode.\nNote: These bits should be configured when the I2S is disabled. It is used only when the I2S is in \nmaster mode.\n\n\n<>\n\nSerial peripheral interface (SPI)\nRM0090\n928/1757\nRM0090 Rev 21\n28.5.10 \nSPI register map\nThe table provides shows the SPI register map and reset values. \n \nRefer to Section 2.3: Memory map for the register boundary addresses.\nTable 130. SPI register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nSPI_CR1\nReserved\nBIDIMODE\nBIDIOE\nCRCEN\nCRCNEXT\nDFF\nRXONLY\nSSM\nSSI\nLSBFIRST\nSPE\nBR [2:0]\nMSTR\nCPOL\nCPHA\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nSPI_CR2\nReserved\nTXEIE\nRXNEIE\nERRIE\nFRF\nReserved\nSSOE\nTXDMAEN\nRXDMAEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0x08\nSPI_SR\nReserved\nFRE\nBSY\nOVR\nMODF\nCRCERR\nUDR\nCHSIDE\nTXE\nRXNE\nReset value\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0x0C\nSPI_DR\nReserved\nDR[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nSPI_CRCPR\nReserved\nCRCPOLY[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n0x14\nSPI_RXCRCR\nReserved\nRxCRC[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x18\nSPI_TXCRCR\nReserved\nTxCRC[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nSPI_I2SCFGR\nReserved\nI2SMOD\nI2SE\nI2SCFG\nPCMSYNC\nReserved\nI2SSTD\nCKPOL\nDATLEN\nCHLEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nSPI_I2SPR\nReserved\nMCKOE\nODD\nI2SDIV\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n929/1757\nRM0090\nSerial audio interface (SAI)\n967\n29 \nSerial audio interface (SAI)\nThis section applies to the STM32F42xxx and STM32F43xxx family.\n29.1 \nIntroduction\nThe SAI interface (serial audio interface) offers a wide set of audio protocols due to its \nflexibility and wide range of configurations. Many stereo or mono audio applications may be \ntargeted. I2S standards, LSB or MSB-justified, PCM/DSP, free protocol, and AC’97 \nprotocols may be addressed for example. \nTo bring this level of flexibility and configurability, the SAI contains two audio sub-blocks that \nare fully independent of each other. Each audio sub-block is connected to up to 4 pins (SD, \nSCK, FS, MCLK). Some of these pins can be shared if the two sub-blocks are declared as \nsynchronous to leave some free to be used as general purpose I/Os. The MCLK pin can be \noutput, or not, depending on the application, the decoder requirement and whether the \naudio block is configured as the master.\nThe SAI can work in master or slave configuration. The audio sub-blocks can be either \nreceiver or transmitter and can work synchronously or not (with respect to the other one).\n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n930/1757\nRM0090 Rev 21\n29.2 \nMain features\n•\nTwo independent audio sub-blocks which can be transmitters or receivers with their \nrespective FIFO.\n•\n8-word integrated FIFOs for each audio sub-block.\n•\nSynchronous or asynchronous mode between the audio sub-blocks.\n•\nMaster or slave configuration independent for both audio sub-blocks. \n•\nClock generator for each audio block to target independent audio frequency sampling \nwhen both audio sub-blocks are configured in master mode.\n•\nData size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.\n•\nPeripheral with large configurability and flexibility allowing to target as example the \nfollowing audio protocol: I2S, LSB or MSB-justified, PCM/DSP, free protocol mode, \nAC’97\n•\nUp to 16 slots available with configurable size and with the possibility to select which \nones are active in the audio frame.\n•\nNumber of bits by frame may be configurable.\n•\nFrame synchronization active level configurable (offset, bit length, level).\n•\nFirst active bit position in the slot is configurable.\n•\nLSB first or MSB first for data transfer.\n•\nMute mode.\n•\nStereo/Mono audio frame capability.\n•\nCommunication clock strobing edge configurable (SCK).\n•\nError flags with associated interrupts if enabled respectively.\n–\nOverrun and underrun detection,\n–\nAnticipated frame synchronization signal detection in slave mode,\n–\nLate frame synchronization signal detection in slave mode,\n–\nCodec not ready for the AC’97 mode in reception.\n•\nInterruption sources when enabled:\n–\nErrors,\n–\nFIFO requests.\n•\nDMA interface with 2 dedicated channels to handle access to the dedicated integrated \nFIFO of each SAI audio sub-block.\n\n\n<>\n\nRM0090 Rev 21\n931/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.3 \nFunctional block diagram\nThe block diagram of the SAI is shown in Figure 283. \nFigure 283. Functional block diagram\nThe SAI is mainly composed of two audio sub-blocks with their own clock generator. Each \naudio block integrates a 32-bit shift register controlled by their own functional state machine. \nData are stored or read from the dedicated FIFO. FIFO may be accessed by the CPU, or by \nDMA in order to leave the CPU free during the communication. Each audio block is \nindependent. They can be synchronous with each other.\nAn I/O line controller manages each dedicated pins for a given audio block in the SAI. If the \ntwo blocks are synchronized, this controller reduces the number of I/Os used, freeing up an \nFS pin, an SCK pin and eventually an MCLK pin, making them general purpose I/Os\nThe functional state machine can be configured to address a wide range of audio protocols. \nSome registers are present to set-up the desired protocols (audio frame waveform \ngenerator). \nThe audio block can be a transmitter or receiver, in master or slave mode. The master mode \nmeans the bit clock SCK and the frame synchronization signal are generated from the SAI, \nwhereas in slave mode, they come from another external or internal master. There is a \nparticular case for which the FS signal direction is not directly linked to the master or slave \nMS30032V1\nFIFO\nFIFO\nAudio block A\n32-bit shift register\nAPB interface\nAPB interface\nSerial Audio Interface\nFIFO ctrl\nFSM\nConfiguration \nregisters and\nStatus register\nAPB\nAPB\nSAI_CK_A\nsynchro\nctrl out\n \nint_sck\nint_FS\nFS_A\nSCK_A\nSD_A\nMCLK_A\nSAI_XCR1\nClock generator\nAudio block A\nFSM\n(SAI)\nAudio block B\nFIFO ctrl\nConfiguration \nregisters and\nStatus register\nClock generator\nAudio block B\nSAI_XCR1\nSAI_CK_B\nI/O line Management\nFS_B\nSCK_B\nSD_B\nMCLK_B\n32-bit shift register\n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n932/1757\nRM0090 Rev 21\nmode definition. In AC’97 protocol, it is an SAI output even if the SAI (link controller) is set-\nup to consume the SCK clock (and so to be in Slave mode). \n29.4 \nMain SAI modes\nEach audio sub-block of the SAI can be configured to be master or slave via bit MODE[0] in \nthe SAI_xCR1 register of the selected audio block. \nIn master mode:\n•\nThe bit clock is generated by the SAI using the clock generator on pin SCK_A or \nSCK_B (depending which audio block is declared as a master in the SAI). \n•\nThe dedicated pin SCK_x is considered as an output.\nIn slave mode:\n•\nThe slave must be enabled before the master is enabled.\n•\nThe slave audio block’s SCK clock I/O pin is considered input if it is configured in \nasynchronous mode.\n•\nIf the audio block is declared synchronous with the second audio block in the SAI, its \nSCK I/O pin is released to leave it free to be used as a general purpose I/O and is \nconnected internally to the SCK pin of the device with which it is synchronized.\nEach audio sub-block can be independently defined as a transmitter or receiver by bit \nMODE[1] in the SAI_xCR1 register of the relevant audio block. The I/O pin SD is defined \nrespectively as an output or an input.\nIt is possible to declare two master audio blocks in the same SAI with two different MCLK \nand SCK clock frequencies (they have to be declared asynchronous). \nEach of the audio blocks in the SAI are enabled by bit SAIxEN in the SAI_xCR1 register. As \nsoon as this bit is active, the transmitter or the receiver is sensitive to the activity on the \nclock line, data line and synchronization line in slave mode. \nIn master TX mode, enabling the audio block immediately generates the bit clock for the \nexternal slaves even if there is no data in the FIFO, However FS signal generation is \nconditioned by the presence of data in the FIFO. After the FIFO receives the first data to \ntransmit, this data is output to external slaves. If there is no data to transmit in the FIFO, 0 \nvalues are then sent in the audio frame with an underrun flag generation.\nIn slave mode, the audio frame starts when the audio block is enabled and when a start of \nframe is detected.\nIn Slave TX mode, no underrun event is possible on the first frame after the audio block is \nenabled, because the mandatory operating sequence in this case is:\n1.\nWrite into the SAI_xDR (by software or by DMA).\n2. \nWait until the FIFO threshold (FLH) flag is different from 000b (FIFO empty).\n3. \nEnable the audio block in slave transmitter mode.\n\n\n<>\n\nRM0090 Rev 21\n933/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.5 \nSAI synchronization mode\nInternal synchronization\nAn audio block can be declared synchronous with the second audio block. In this case, the \nbit clock and the frame synchronization signals are shared to reduce the number of external \npins used for the communication. The audio block declared as synchronous with the other \none sees its own SCK_x, FS_x, and MCLK_x pins released to bring them back as GPIOs. \nThe one declared asynchronous is the one for which the I/O pins FS_x and SCK_x ad \nMCLK_x (if the audio block is considered as master) are considered.\nTypically, the audio block synchronous mode may be used to configure the SAI in full duplex \nmode. One of the two audio blocks can be configured as master and the other as slave, or \nboth can be slaves; with one block declared as asynchronous (respective bit SYNCEN[1:0] \n= 00 in SAI_xCR1) and the other one declared as synchronous with the other audio block \n(respective bit SYNCEN[1:0] = 01 in the SAI_xCR1).\nNote:\nAPB frequency PCLK must be greater or equal to twice the bit rate clock frequency (due to \ninternal resynchronization stages).\n29.6 \nAudio data size\nThe audio frame can target different data sizes by configuring bit DS[2:0] in the SAI_xCR1 \nregister. The data sizes may be 8-, 10-, 16-, 20-, 24- or 32-bit. During the transfer, either the \nMSB or the LSB of the data are sent first, depending on the configuration of bit LSBFIRST in \nthe SAI_xCR1 register.\n29.7 \nFrame synchronization\nThe FS signal acts as the Frame synchronization signal in the audio frame (start of frame). \nThe shape of this signal is completely configurable in order to target the different audio \nprotocols with their own specificities concerning this Frame synchronization behavior. This \nconfigurability is done using register SAI_xFRCR. Figure 284 gives a view of this flexibility.\nFigure 284. Audio frame\nSlot 0\nFs\nsck\nsd\nFs offset\nFs length = < 256 bits\nFs active length = < 128 bits\nMS30037V1\nSlot 1\nSlot 2\nSlot 3\nSlot n\n…\n…\n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n934/1757\nRM0090 Rev 21\nIn AC’97 mode (bit PRTCFG[1:0] = 10 in the SAI_xCR1 register), the frame synchronization \nshape is forced to be configured to target these protocols. The SAI_xFRCR register value is \nignored.\nEach audio block is independent and so each requires a specific configuration.\n29.7.1 \nFrame length\n•\nMaster mode: The audio frame length can be configured up to 256 bit clock, setting bit \nFRL[7:0] in the SAI_xFRCR register. If the frame length is greater than the number of \ndeclared slots for the frame, the remaining bits to transmit are extended to 0 or the SD \nline is released to HI-z depending the state of bit TRIS in the SAI_xCR2 register (refer \nto Section 29.12.4). In reception mode, the remaining bit is ignored.\n•\nSlave mode: The audio frame length is mainly used in order to specify to the slave the \nnumber of bit clocks per audio frame sent by the external master. It is used mainly to \ndetect from the master, any anticipated or late occurrence of the Frame \nsynchronization signal during an on-going audio frame. An error is generated in such \ncase. For more details please refer to the Section 29.13.\nThe number of bits in the frame is equal to FRL[7:0] + 1. \nThe minimum number of bits to transfer in an audio frame is 8. This is the case when the \ndata size is 8-bit and only one slot is defined in NBSLOT[3:0] in the SAI_xSLOTR register \n(NBSLOT[3:0] = 0000 for slot 0).\nIn master mode:\n•\nIf bit NODIV in the SAI_xCR1 register is cleared, the frame length should be aligned to \na number equal to a power of 2, from 8 to 256. This is to ensure that an audio frame \ncontains an integer number of MCLK pulses per bit clock, which ensures correct \noperation of the external DAC/ADC inside the decoders. If the value set in FRL[7:0] \ndoes not respect this rule, flag WCKCFG is set when the audio block is enabled and an \ninterrupt is generated if bit WCKCFGIE is set in the SAI_xIM register. The SAI is \nautomatically disabled.\n•\nIf bit NODIV in the SAI_xCR1 register is set, the FRL[7:0] bit can take any of the values \nwithout constraint since the input clock of the audio block should be equal to the bit \nclock. There is no MCLK_x clock which can be output. MCLK_x output pad is \nautomatically disabled.\nIn slave mode, there are no constraints for the FRL[7:0] bit configuration in the SAI_xFRCR \nregister.\n29.7.2 \nFrame synchronization polarity\nBit FSPOL in the SAI_xFRCR register sets the active polarity of the FS pin from which a \nframe is started. The start of frame is edge sensitive.\nIn slave mode, the audio block waits for a valid frame to start to transmit or to receive. Start \nof frame is synchronized to this signal. It is effective only if the start of frame is not detected \nduring an on-going communication and assimilated to an anticipated start of frame (refer to \nSection 29.13).\nIn master mode, the frame synchronization is sent continuously each time an audio frame is \ncomplete until the SAIxEN bit in the SAI_xCR1 register is cleared. If no data is present in the \nFIFO at the end of the previous audio frame, an underrun condition is managed as \ndescribed in Section 29.13), but there is no interruption in the audio communication flow.\n\n\n<>\n\nRM0090 Rev 21\n935/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.7.3 \nFrame synchronization active level length\nBit FSALL[6:0] in the SAI_xFRCR register configures the length of the active level of the \nFrame synchronization signal. The length can be set from 1 to 128 bit clock SCK. \nThe active length may be half of the frame length in I2S, LSB or MSB-justified modes for \ninstance, or one-bit wide for PCM/DSP or free protocol mode, or even 16-bit length in \nAC’97. \n29.7.4 \nFrame synchronization offset\nDepending on the audio protocol targeted in the application, the Frame synchronization \nsignal can be asserted when transmitting the last bit or the first bit of the audio frame (as for \ninstance, respectively, in I2S standard protocol and in MSB-justified protocol). Bit FSOFF in \nthe SAI_xFRCR register makes the choice.\n29.7.5 \nFS signal role\nThe FS signal may have a different meaning depending on the FS function. Bit FSDEF in \nthe SAI_xFRCR register selects which meaning it has. It may be either:\n•\n0: a start of frame, like for instance the PCM/DSP, free protocol, AC’97, audio \nprotocols, \n•\n1: a start of frame and a channel side identification within the audio frame like for the \nI2S, the MSB or LSB-justified protocols. \nWhen the FS signal is considered as a start of frame and channel side identification within \nthe frame, the number of declared slots must be considered to be half of the number for the \nleft channel and half of the number for the right channel. If the number of bit clock on half \naudio frame is greater than the number of slots dedicated to a channel side, if TRIS = 0, 0 is \nsent for transmission for the remaining bit clock in the SAI_xCR2 register, otherwise if TRIS \n= 1, the SD line is released to HI-Z. In reception, the remaining bit clock are not considered \nuntil the channel side changes.\nFigure 285. FS role is start of frame + channel side identification (FSDEF = TRIS = 1)\n1.\nThe frame length should be even.\nsck\nslot\nAudio frame\nFS\nHalf of frame\nAudio frame\nFS\nHalf of frame\nNumber of slots not aligned with the audio frame\nNumber of slots aligned with the audio frame\nMS30038V1\nSlot 0 \nsck\nslot\nSlot 1\nSlot 2\nSlot 3\nSlot 5\nSlot 4\nSlot 0 ON\nSlot 1 OFF\nSlot 2 ON\nSlot 3 ON\nSlot 4 OFF\nSlot 5 ON\n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n936/1757\nRM0090 Rev 21\nIf bit FSDEF in SAI_xFRCR is kept clear, so FS signal is equivalent to a start of frame, and \nif the number of slots defined in bit NBSLOT[3:0] in SAI_xSLOTR multiplied by \nthe number of bits by slot configured in bit SLOTSZ[1:0] in SAI_xSLOTR is less than the \nframe size (bit FRL[7:0] in the SAI_xFRCR register), then, \n•\nif TRIS = 0 in the SAI_xCR2 register, the remaining bit after the last slot is forced to 0 \nuntil the end of frame in case of transmission,\n•\nif TRIS = 1, the line is released to HI-Z during the transfer of these remaining bits. In \nreception mode, these bits are discarded.\nFigure 286. FS role is start of frame (FSDEF = 0)\n29.8 \nSlot configuration\nThe slot is the basic element in the audio frame. The number of slots in the audio frame is \nequal to the configured setting of bit NBSLOT[3:0] in the SAI_xSLOTR register +1. \nThe maximum number of slots per audio frame is fixed at 16. \nFor AC’97 protocol (when bit PRTCFG[1:0] = 10), the number of slots is automatically set to \ntarget the protocol specification, and the value of NBSLOT[3:0] is ignored. \nEach slot can be defined as a valid slot, or not, by setting bit SLOTEN[15:0] in the \nSAI_xSLOTR register. In an audio frame, during the transfer of a non-valid slot, 0 value is \nforced on the data line or the SD data line is released to HI-z (refer to Section 29.12.4) if the \naudio block is transmitter, or the received value from the end of this slot is ignored. \nConsequently, there is no FIFO access and so no request to read or write the FIFO linked to \nthis inactive slot status.\nThe slot size is also configurable as shown in the Figure 287. The size of the slots is \nselected by setting bit SLOTSZ[1:0] in the SAI_xSLOTR register. The size is applied \nidentically for each slot in an audio frame. \nAudio frame\nData = 0 after slot n if TRIS = 0\nSD output released (HI-Z) after slot n if TRIS = 1\nMS30039V1\nsck\nslot\nSlot 0 \nSlot 1 \nSlot 2 \nSlot n\n...\n\n\n<>\n\nRM0090 Rev 21\n937/1757\nRM0090\nSerial audio interface (SAI)\n967\nFigure 287. Slot size configuration with FBOFF = 0 in SAI_xSLOTR\nIt is possible to choose the position of the first data bit to transfer within the slots, this offset \nis configured by bit FBOFF[5:0] in the SAI_xSLOTR register. 0 values are injected in \ntransmitter mode from the beginning of the slot until this offset position is reached. In \nreception, the bit in the offset phase is ignored. This feature targets the LSB justified \nprotocol (if the offset is equal to the slot size minus the data size).\nFigure 288. First bit offset\nIt is mandatory to respect the following conditions in order to avoid bad SAI behavior:\nFBOFF ≤ (SLOTSZ - DS),\nDS ≤ SLOTSZ,\nNBSLOT x SLOTSZ ≤ FRL (frame length),\nThe number of slots should be even when bit FSDEF in the SAI_xFRCR register is set.\nIn AC’97 (bit PRTCFG[1:0] = 10), the slot size is automatically set as defined in \nSection 29.11. \nMS30033V1\n00..00\n00..00\nX..X\nXX..XX\nX: don’t care\nAudio block is transmitter\nSlot size = data size\ndata size\ndata size\ndata size\ndata size\nslotx\nslotx\nslotx\n16-bit\n32-bit\nAudio block is receiver\nSlot size = data size\ndata size\ndata size\ndata size\nslotx\nslotx\nslotx\n16-bit\n32-bit\ndata size\nMS30034V1\nXX .. XX\n00\n00..00\nX: don’t care\nAudio block is transmitter\nSlot size = data size\ndata size\ndata size\ndata size\ndata size\nslotx\nslotx\nslotx\n16-bit\n32-bit\nAudio block is receiver\n00\nFBOFF\nFBOFF = SLOT SZ -DS\nXX\nSlot size = data size\ndata size\ndata size\ndata size\ndata size\nslotx\nslotx\nslotx\n16-bit\n32-bit\nXX\nFBOFF\nFBOFF = SLOT SZ -DS\n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n938/1757\nRM0090 Rev 21\n29.9 \nSAI clock generator\nEach audio block has its own clock generator to make these two blocks completely \nindependent. There is no difference in terms of functionality between these two clock \ngenerators. They are exactly the same.\nWhen the audio block is defined as Master, the clock generator generates the \ncommunication clock (the bit clock) and the master clock for external decoders. \nWhen the audio block is defined as slave, the clock generator is OFF.\nFigure 289 illustrates the architecture of the audio block clock generator.\nFigure 289. Audio block clock generator overview\nNote:\nIf NoDiv is set to 1, the MCLK_x signal is set at 0 level if this pin is configured as the SAI pin \nin GPIO peripherals.\nThe clock source for the clock generator comes from the product clock controller. The \nSAI_CK_x clock is equivalent to the master clock which may be divided for the external \ndecoders using bit MCKDIV[3:0]: \nMCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2), if MCKDIV[3:0] is not equal to 0000. \nMCLK_x = SAI_CK_x, if MCKDIV[3:0] is equal to 0000.\nMCLK_x signal is used only in free protocol mode.\nThe division must be even in order to keep 50% on the Duty cycle on the MCLK output and \non the SCK_x clock. If bit MCKDIV[3:0] = 0000, division by one is applied to have MCLK_x \n= SAI_CK_x.\nIn the SAI, the single ratio MCLK/FS = 256 is considered. Mostly, three frequency ranges \nare encountered as illustrated in the Table 131.\nMaster clock\ndivider\nBit clock divider \nMCKDIV[3:0]\nSCK_x\nMCLK_x\nNODIV\n0\n1\n0\n1\nNODIV\n0\n1\n0\nNODIV\nSAI_CK_x\nMS30040V1\nFRL[7:0]\n\n\n<>\n\nRM0090 Rev 21\n939/1757\nRM0090\nSerial audio interface (SAI)\n967\n \nThe master clock may be generated externally on an I/O pad for external decoders if the \ncorresponding audio block is declared as master with bit NODIV = 0 in the SAI_xCR1 \nregister. In slave, the value set in this last bit is ignored since the clock generator is OFF, \nand the MCLK_x I/O pin is released for use as a general purpose I/O.\nThe bit clock is derived from the master clock. The bit clock divider sets the divider factor \nbetween the bit clock SCK_x and the master clock MCLK_x following the formula:\nSCK_x = MCLK x (FRL[7:0] +1) / 256\nwhere:\n256 is the fixed ratio between MCLK and the audio frequency sampling.\nFRL[7:0] is the number of bit clock - 1 in the audio frame, configured in the SAI_xFRCR \nregister.\nIt is mandatory in master mode that (FRL[7:0] +1) should be equal to a number with a power \nof 2 (refer to Section 29.7) in order to have an even integer number of MCLK_x pulses by bit \nclock. The 50% duty cycle is guaranteed on the bit clock SCK_x.\nThe SAI_CK_x clock can be also equal to the bit clock frequency. In this case, bit NODIV in \nthe SAI_xCR1 register should be set and the value inside the MCKDIV divider and the bit \nclock divider is ignored. In this case, the number of bits per frame is fully configurable \nwithout the need to be equal to a power of two.\nThe bit clock strobing edge on SCK can be configured by bit CKSTR in the SAI_xCR1 \nregister.\n29.10 \nInternal FIFOs\nEach audio block in the SAI has its own FIFO. Depending if the block is defined to be a \ntransmitter or a receiver, the FIFO is written or read, respectively. There is therefore only \none FIFO request linked to FREQ bit in the SAI_xSR register. \nTable 131. Example of possible audio frequency sampling range\nInput SAI_CK_x clock \nfrequency\nMost usual audio frequency \nsampling achievable\nMCKDIV[3:0]\n192 kHz x 256\n192 kHz\n MCKDIV[3:0] = 0000\n96 kHz\n MCKDIV[3:0] = 0001\n48 kHz\n MCKDIV[3:0] = 0010\n16 kHz\n MCKDIV[3:0] = 0100\n8 kHz\n MCKDIV[3:0] = 1000\n44.1 kHz x 256\n44.1 kHz\n MCKDIV[3:0] = 0000\n22.05 kHz\n MCKDIV[3:0] = 0001\n11.025 kHz\n MCKDIV[3:0] = 0010\nSAI_CK_x = MCLK(1)\n1.\nThis may happen when the product clock controller selects an external clock source, instead of PLL clock.\nMCLK\n MCKDIV[3:0] = 0000\n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n940/1757\nRM0090 Rev 21\nAn interrupt is generated if FREQIE bit is enabled in the SAI_xIM register. This depends on: \n•\nFIFO threshold setting (FLTH bits in SAI_CR2) \n•\nCommunication direction transmitter or receiver (see Section : Interrupt generation in \ntransmitter mode and Section : Interrupt generation in reception mode)\nInterrupt generation in transmitter mode\nThe interrupt generation depends on the FIFO configuration in transmitter mode: \n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO empty \n(FTH[2:0] set to 000b), an interrupt is generated (FREQ bit set by hardware to 1 in \nSAI_XSR register) if no data are available in SAI_xDR register (FLTH[2:0] bits in SAI_xSR \nis less than 001b). This Interrupt (FREQ bit in SAI_XSR register) is cleared by hardware \nwhen the FIFO became not empty (FLTH[2:0] bits in SAI_xSR are different from 000b) i.e \none or more data are stored in the FIFO.\n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO quarter full \n(FTH[2:0] set to 001b), an interrupt is generated (FREQ bit set by hardware to 1 in \nSAI_XSR register) if less than a quarter of the FIFO contains data (FLTH[2:0] bits in \nSAI_xSR are less than 010b). This Interrupt (FREQ bit in SAI_XSR register) is cleared by \nhardware when at least a quarter of the FIFO contains data (FLTH[2:0] bits in SAI_xSR \nare higher or equal to 010b).\n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO half full \n(FTH[2:0] set to 010b), an interrupt is generated (FREQ bit set by hardware to 1 in \nSAI_XSR register) if less than half of the FIFO contains data (FLTH[2:0] bits in SAI_xSR \nare less than 011b). This Interrupt (FREQ bit in SAI_XSR register) is cleared by hardware \nwhen at least half of the FIFO contains data (FLTH[2:0] bits in SAI_xSR are higher or \nequal to 011b).\n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO three quarter \n(FTH[2:0] set to 011b), an interrupt is generated (FREQ bit is set by hardware to 1 in \nSAI_XSR register) if less than three quarters of the FIFO contain data (FLTH[2:0] bits in \nSAI_xSR are less than 100b). This Interrupt (FREQ bit in SAI_XSR register) is cleared by \nhardware when at least three quarters of the FIFO contain data (FLTH[2:0] bits in \nSAI_xSR are higher or equal to 100b).\n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO full (FTH[2:0] \nset to 100b), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_XSR \nregister) if the FIFO is not full (FLTH[2:0] bits in SAI_xSR is less than 101b). This Interrupt \n(FREQ bit in SAI_XSR register) is cleared by hardware when the FIFO is full (FLTH[2:0] \nbits in SAI_xSR is equal to 101b value).\nInterrupt generation in reception mode\nThe interrupt generation depends on the FIFO configuration in reception mode: \n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO empty \n(FTH[2:0] set to 000b), an interrupt is generated (FREQ bit is set by hardware to 1 in \nSAI_XSR register) if at least one data is available in SAI_xDR register(FLTH[2:0] bits in \nSAI_xSR is higher or equal to 001b). This Interrupt (FREQ bit in SAI_XSR register) is \ncleared by hardware when the FIFO became empty (FLTH[2:0] bits in SAI_xSR is equal \nto 000b) i.e no data is stored in FIFO.\n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO quarter fully \n(FTH[2:0] set to 001b), an interrupt is generated (FREQ bit is set by hardware to 1 in \nSAI_XSR register) if at less one quarter of the FIFO data locations are available \n\n\n<>\n\nRM0090 Rev 21\n941/1757\nRM0090\nSerial audio interface (SAI)\n967\n(FLTH[2:0] bits in SAI_xSR is higher or equal to 010b). This Interrupt (FREQ bit in \nSAI_XSR register) is cleared by hardware when less than a quarter of the FIFO data \nlocations become available (FLTH[2:0] bits in SAI_xSR is less than 010b).\n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO half fully \n(FTH[2:0] set to 010b value), an interrupt is generated (FREQ bit is set by hardware to 1 \nin SAI_XSR register) if at least half of the FIFO data locations are available (FLTH[2:0] \nbits in SAI_xSR is higher or equal to 011b). This Interrupt (FREQ bit in SAI_XSR register) \nis cleared by hardware when less than half of the FIFO data locations become available \n(FLTH[2:0] bits in SAI_xSR is less than 011b).\n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO three quarter \nfull(FTH[2:0] set to 011b value), an interrupt is generated (FREQ bit is set by hardware to \n1 in SAI_XSR register) if at least three quarters of the FIFO data locations are available \n(FLTH[2:0] bits in SAI_xSR is higher or equal to 100b). This Interrupt (FREQ bit in \nSAI_XSR register) is cleared by hardware when the FIFO has less than three quarters of \nthe FIFO data locations avalable(FLTH[2:0] bits in SAI_xSR is less than 100b).\n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO full(FTH[2:0] \nset to 100b), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_XSR \nregister) if the FIFO is full (FLTH[2:0] bits in SAI_xSR is equal to 101b). This Interrupt \n(FREQ bit in SAI_XSR register) is cleared by hardware when the FIFO is not full \n(FLTH[2:0] bits in SAI_xSR is less than 101b). \nLike interrupt generation, the SAI can use the DMA if DMAEN bit in the SAI_xCR1 register is \nset. The FREQ bit assertion mechanism is the same as the interruption generation \nmechanism described above for FREQIE.\nEach FIFO is an 8-word FIFO. Each read or write operation from/to the FIFO targets one \nword FIFO allocation whatever the access size. Each FIFO word contains one audio frame. \nFIFO pointers are incremented by one word after each access to the SAI_xDR register.\nData should be right aligned when it is written in the SAI_xDR. \nData received are right aligned in the SAI_xDR.\nThe FIFO pointers can be reinitialized when the SAI is disabled by setting bit FFLUSH in the \nSAI_xCR2 register. If FFLUSH is set when the SAI is enabled, the data present in the FIFO \nare lost automatically.\n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n942/1757\nRM0090 Rev 21\n29.11 \nAC’97 link controller\nThe SAI is able to work as an AC’97 link controller. In this protocol:\n•\nThe slot number and the slot size are fixed. \n•\nThe frame synchronization signal is perfectly defined and has a fixed shape. \nTo select this protocol, set bit PRTCFG[1:0] in the SAI_xCR1 register to 10. When AC’97 \nmode is selected the data sizes that can be used are 16-bit or 20-bit only, else SAI behavior \nis not guaranteed.\n•\nBits NBSLOT[3:0] and SLOTSZ[1:0] are consequently ignored. \n•\nThe number of slots is fixed at 13 slots. The first one is 16 bits wide and all the others \nare 20 bits wide (data slots).\n•\nBit FBOFF[5:0] in the SAI_xSLOTR register is ignored\n•\nThe SAI_xFRCR register is ignored. \nThe FS signal from the block defined as asynchronous is configured automatically as an \noutput, since the AC’97 controller link drives the FS signal whatever the master or slave \nconfiguration.\nFigure 290 presents an AC’97 audio frame structure.\nFigure 290. AC’97 audio frame\nNote:\nIn AC’97 protocol, bit 2 of the tag is reserved (always 0), so whatever the value written in the \nSAI FIFO, bit 2 of the TAG is forced to 0 level.\nFor more details about TAG representation, please refer to the AC’97 protocol standard.\nOne SAI can be used to target an AC’97 point-to-point communication.\nIn receiver mode, the SAI acting as an AC’97 link controller does not require any FIFO \nrequest and so no data storage in the FIFO when the codec ready bit in the slot 0 is \ndecoded low. If bit CNRDYIE is enabled in the SAI_xIM register, flag CNRDY is set in the \nSAI_xSR register and an interrupt is generated. This flag is dedicated to the AC’97 protocol.\nMS192343V1\nFS\n1\n2\n3\n4\n5\n6\n7\n8\n9\n10\n11\n12\nSDI\nSDO\nTag\nCMD\nADDR\nCMD\nDATA\nLINE1\nDAC\nPCM\nLFRONT\nPCM\nRFRONT\nPCM\nCENTER\nPCM\nLSURR\nPCM\nRSURR\nPCM\nLFE\nLINE2\nDAC\nHSET\nDAC\nIO\nCTRL\nTag\nSTATUS\nADDR\nSTATUS\nDATA\nLINE1\nADC\nPCM\nLEFT\nPCM\nRIGHT\nPCM\nMIC\nRSR\nVD\nRSR\nLVD\nLINE2\nADC\nHSET\nIO\nSTATUS\nRSR\nVD\n\n\n<>\n\nRM0090 Rev 21\n943/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.12 \nSpecific features\nThe SAI has some specific functions which can be useful depending on the audio protocol \nselected. These functions are accessible through specific bits in the SAI_xCR2 register.\n29.12.1 \nMute mode \nMute mode may be used when the audio block is a transmitter or receiver.\nTransmitter\nIn transmitter mode, Mute mode can be selected at anytime. Mute mode is active for entire \naudio frames. The bit MUTE in the SAI_xCR2 register requests Mute mode when it is set \nduring an on-going frame.\nThe mute mode bit is strobed only at the end of the frame. If set at this time, the mute mode \nis active at the beginning of the new audio frame, for a complete frame, until the next end of \nframe, it then strobes the bit to determine if the next frame is still a mute frame.\nIf the number of slots set in bit NBSLOT[3:0] in the SAI_xSLOTR register is lower than or \nequal to two, it is possible to specify if the value sent during the Mute mode is 0 or if it is the \nlast value of each slot. The selection is done via bit MUTEVAL in the SAI_xCR2 register.\nIf the number of slots set in bit NBSLOT[3:0] in the SAI_xSLOTR register is greater than \ntwo, MUTEVAL bit in the SAI_xCR2 has no meaning as 0 values are sent on each bit on \neach slot. \nDuring Mute mode, the FIFO pointers are still incremented, meaning that data which was \npresent in the FIFO and for which the Mute mode is requested is discarded.\nReceiver\nIn receiver mode, it is possible to detect a Mute mode sent from the external transmitter \nwhen all the declared and valid slots of the audio frame receive 0 for a given consecutive \nnumber of audio frames (bit MUTECNT[5:0] in the SAI_xCR2 register). \nWhen the number of MUTE frames is detected, flag MUTEDET in the SAI_xSR register is \nset and an interrupt can be generated if bit MUTEDETIE is set in the SAI_xCR2. \nThe mute frame counter is cleared when the audio block is disabled or when a valid slot \nreceives at least one data in an audio frame. The interrupt is generated just once, when the \ncounter reaches the specified value in bit MUTECNT[5:0]. Then the interrupt event is re-\narmed when the counter is cleared.\n29.12.2 \nMONO/STEREO function\nIn transmission mode, it is possible to address the Mono mode without any data pre-\nprocessing in memory when the number of slot is equal to 2 (NBSLOT[3:0] = 0001 in the \nSAI_xSLOTR). In such a case, the access to and from the FIFO is reduced by two since in \ntransmission, the data for slot 0 is duplicated into data slot 1. \nTo select the Mono feature, set bit MONO in the SAI_xCR1 register.\nIn reception mode, bit MONO can be set and has a meaning only if the number of slots is \nequal to 2 like for the transmission mode. When it is set, only the data of slot 0 are stored in \nthe FIFO. The data belonging to slot 1 are discarded since in this case, it is supposed to be \nthe same as the previous slot. If the data flux in reception is a real stereo audio flow with a \n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n944/1757\nRM0090 Rev 21\ndistinct and different left and right data, bit MONO has no meaning. The conversion from the \noutput stereo file to the equivalent mono file is done by software.\nNote:\nTo enable Mono mode, NBSLOT and SLOTEN must equal two and MONO bit set to 1.\n29.12.3 \nCompanding mode\nTelecommunication applications may require to process the data to transmit or to receive \nwith a data companding algorithm.\nDepending on the COMP[1:0] bit in the SAI_xCR2 register (used only when free protocol \nmode is selected), the software may choose to process or not the data before sending it on \nSD serial output line (compression) or to expand the data after the reception on SD serial \ninput line (expansion) as illustrated in Figure 291. The two companding modes supported \nare the µ-Law and the A-Law log which are a part of the CCITT G.711 recommendation. \nThe companding standard employed in the United States and Japan is the µ-Law and allows \n14 bits of dynamic range (COMP[1:0] = 10 in the SAI_xCR2 register). \nThe European companding standard is A-Law and allows 13 bits of dynamic range \n(COMP[1:0] = 11 in the SAI_xCR2 register).\nCompanding standard (µ-Law or A-Law) can be computed based on 1’s complement or 2’s \ncomplement representation depending on the CPL bit setting in the SAI_xCR2 register.\nThe µ-Law and A-Law formats encode data into 8-bit code elements with MSB alignment. \nCompanded data is always 8 bits wide. For this reason, bit DS[2:0] in the SAI_xCR1 register \nis forced to 010 when the SAI audio block is enabled (bit SAIxEN = 1 in the SAI_xCR1 \nregister) and when the COMP[1:0] bit selects one of these two companding modes.\nIf no companding processing is required, COMP[1:0] bit in the SAI_xCR2 register should be \nkept cleared.\nFigure 291. Data companding hardware in an audio block in the SAI\nNote:\nNot applicable when AC’97 selected.\nexpand\nFIFO \nCOMP[1]\nCOMP[1]\n32-bit shift register\nSD\nReceiver mode (bit MODE[0] = 1 in SAI_xCR1)\nTransmitter mode (bit MODE[0] = 0 in SAI_xCR1)\nMS19244V1\n1\n0\n1\n0\n32-bit shift register\nSD\ncompress\nFIFO \n\n\n<>\n\nRM0090 Rev 21\n945/1757\nRM0090\nSerial audio interface (SAI)\n967\nExpansion or compression mode is automatically selected by the SAI configuration. \n•\nIf the SAI audio block is configured to be a transmitter, and if the COMP[1] bit is set in \nthe SAI_xCR2 register, the compression mode is applied. \n•\nIf the SAI audio block is declared as a receiver, the expansion algorithm is applied.\n29.12.4 \nOutput data line management on an inactive slot \nIn transmitter mode, it is possible to choose the behavior of the SD line in output when an \ninactive slot is sent on the data line (via bit TRIS in the SAI_xCR2 register when the SAI is \ndisabled).\n•\nEither the SAI forces 0 on the SD output line when an inactive slot is transmitted, or \n•\nThe line is released in HI-z state at the end of the last bit of data transferred, to release \nthe line for other transmitters connected to this node. \nIt is important to note that the two transmitters do not attempt to drive the same SD output \npin simultaneously, which could result in a short circuit. In order to ensure a gap between \ntransmissions, if the data is lower than 32-bit, the data can be extended to 32-bit by setting \nbit SLOTSZ[1:0] = 10 in the SAI_xSLOTR register. Then, the SD output pin is tristated at the \nend of the LSB of the active slot (during the padding to 0 phase to extend the data to 32-bit) \nif the following slot is declared inactive. \nIn addition, if the number of slots multiplied by the slot size is lower than the frame length, \nthe SD output line is tristated when the padding to 0 is done to complete the audio frame. \nFigure 292 illustrates these behaviors.\n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n946/1757\nRM0090 Rev 21\nFigure 292. Tristate strategy on SD output line on an inactive slot\nWhen the selected audio protocol uses the FS signal as a start of frame and a channel side \nidentification (bit FSDEF = 1 in the SAI_xFRCR register), the tristate mode is managed \naccording to Figure 293 (where bit TRIS in the SAI_xCR1 register = 1, and FSDEF=1, and \nhalf frame length > number of slots/2, and NBSLOT=6).\nslot\nAudio frame\nBit TRIS = 1 in the SAI_xCR1 and frame length = number of slots\nMS192345V1\nSlot size = data size\nSlot size > data size\nBit TRIS = 1 in the SAI_xCR1 and frame length > number of slots\nSD (output)\nsck\nSlot 0 ON\nSlot 1 OFF\nSlot 2 OFF\nSlot 3 ON\n.. ON\n.. ON\nSlot n ON\nData 0\nData 1\n..\n..\nData m\nSlot 0 ON\nSlot 1 OFF\nSlot 2 OFF\nSlot 3 ON\n.. ON\n.. ON\nSlot n ON\nData 0\nData 1\n..\n..\nData m\nSlot 0 ON\nSlot 1 OFF\nSlot 2 OFF\nSlot 3 ON\n.. ON\n.. ON\nSlot n ON\nData 0\n..\n..\nData m\nslot\nSD (output)\nslot\nSD (output)\nslot\nAudio frame\nSlot size = data size\nSD (output)\nsck\nSlot 0 ON\nSlot 1 OFF\nSlot 2 OFF\n.. ON\nSlot n ON\nData 0\n..\nData m\nslot\nSlot size > data size\nSD (output)\nSlot 0 ON\nSlot 1 OFF\nSlot 2 OFF\n.. ON\nSlot n ON\n..\nData m\nData 0\nslot\nSD (output)\nSlot 0 ON\nSlot 1 OFF\nSlot 2 OFF\n.. ON\n..\nData m\n.. ON\n\n\n<>\n\nRM0090 Rev 21\n947/1757\nRM0090\nSerial audio interface (SAI)\n967\nFigure 293. Tristate on output data line in a protocol like I2S\nIf the TRIS bit in the SAI_xCR2 register is cleared, all the High impedance states on the SD \noutput line on Figure 292 and Figure 293 are replaced by a drive with a value of 0.\n29.13 \nError flags\nThe SAI embeds some error flags:\n–\nFIFO overrun/underrun,\n–\nAnticipated frame synchronization detection,\n–\nLate frame synchronization detection,\n–\nCodec not ready (AC’97 exclusively),\n–\nWrong clock configuration in master mode.\n29.13.1 \nFIFO overrun/underrun (OVRUDR)\nThe FIFO Overrun/Underrun bit is called OVRUDR in the SAI_xSR register.\nThe overrun or underrun errors occupy the same bit since an audio block can be either \nreceiver or transmitter and each audio block in an SAI has its own SAI_xSR register.\nOverrun\nWhen the audio block is configured as receiver, an overrun condition may appear if data is \nreceived in an audio frame when the FIFO is full and is not able to store the received data. \nIn this case, the received data is lost, the flag OVRUDR in the SAI_xSR register is set and \nan interrupt is generated if bit OVRUDRIE is set in the SAI_xIM register. The slot number \nfrom which the overrun occurs, is stored internally. No more data are stored into the FIFO \nuntil it becomes free to store new data. When the FIFO has at least one data free, the SAI \naudio block receiver stores new data (from new audio frame) from the slot number which \nslot\nMS192346V1\nSlot size = data size\nSlot size > data size\nSD (output)\nsck\nSlot 0 ON\nSlot 1 OFF\nSlot 2 ON\nSlot 3 ON\nSlot 4 OFF\nSlot 5 ON\nData 0\nData 1\nSlot 0 ON\nSlot 1 OFF\nSlot 2 ON\nData 0\nslot\nSD (output)\nData 2\nData 3\nSlot 3 ON\nSlot 4 OFF\nSlot 5 ON\nData 1\nData 2\nData 3\nSlot 0 ON\nSlot 1 OFF\nSlot 2 ON\nData 0\nslot\nSD (output)\nSlot 3 ON\nSlot 4 OFF\nSlot 5 ON\nData 1\nData m\n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n948/1757\nRM0090 Rev 21\nwas stored internally when the overrun condition was detected, and this, to avoid data slot \nde-alignment in the destination memory (refer to Figure 294).\nThe OVRUDR flag is cleared when bit COVRUDR is set in the SAI_xCLRFR register. \nFigure 294. Overrun detection error\nUnderrun\nAn underrun may occur when the audio block in the SAI is a transmitter and the FIFO is \nempty when data needs to be transmitted (the audio block configuration (Master or Slave) is \nnot relevant). If an underrun is detected, the software must resynchronize data and slot. \nProceed as follows:\n1.\nDisable the SAI peripheral by resetting the SAIEN bit of the SAI_xCR1 register. Check \nthat the SAI has been disabled by reading back the SAIEN bit (SAIEN should be equal \nto 0).\n2. \nFlush the Tx FIFO through the FFLUS bit of the SAI_xCR2 register.\n3. \nRe-assigned to the correct data to be transferred on the first active slot of the new \nframe.\n4. \nRe-enabling the SAI peripheral (SAIEN bit set to 1).\nThe underrun event sets the OVRUDR flag in the SAI_xSR register and an interrupt is \ngenerated if the OVRUDRIE bit is set in the SAI_xIM register. To clear this flag, set the \nCOVRUDR bit in the SAI_xCLRFR register.\nMS192348V2\nsck\ndata\nSlot 0 ON\nExample: FIFO overrun on Slot 1\nAudio frame\nAudio frame\nSlot n ON\n... ON\nFIFO full\nOVRUDR\nSlot 1 ON\nSlot 1 ON\nSlot 0 ON\nSlot 1 ON\nReceived data discarded\nData stored again in FIFO\nCOVRUDR = 1\n\n\n<>\n\nRM0090 Rev 21\n949/1757\nRM0090\nSerial audio interface (SAI)\n967\nFigure 295. FIFO underrun event\n29.13.2 \nAnticipated frame synchronisation detection (AFSDET)\nThis flag AFSDET is used only in Slave mode. In master mode, it is never asserted. It \ninforms about the detection of a frame synchronisation (FS) earlier than expected since the \nframe length, the frame polarity, the frame offset are defined and known. \nEarly detection sets flag AFSDET in the SAI_xSR register. \nThis detection has no effect on the current audio frame which is not sensitive to the \nanticipated FS. This means that “parasitic” events on signal FS are flagged without any \nperturbation of the current audio frame.\nIf bit AFSDETIE is set in the SAI_xIM register, an interrupt is generated. To clear the flag \nAFSDET, bit CAFSDET in the SAI_xCLRFR register has to be set.\nTo resynchronize with the master after Anticipated frame detection error, four steps should \nbe respected:\n1.\nSAI block should be disabled by resetting SAIEN bit in SAI_xCR1 register, to be sure \nthat the SAI is disabled SAIEN bit is should be equal to 0 (reading back this bit).\n2. \nFIFO should be flushed via FFLUS bit in SAI_xCR2 register.\n3. \nRe-enabling the SAI peripheral (SAIEN bit set to 1) then the SAI.\n4. \nSAI block waits for the assertion on FS to restart the synchronization with master.\nNote:\nThis flag is not asserted in AC’97 since the SAI audio block acts as a link controller and \ngenerates the FS signal even when declared as slave.\n29.13.3 \nLate frame synchronization detection\nFlag LFSDET in the SAI_xSR register can be set only when the SAI audio block is defined \nas slave. The frame length, the frame polarity and the frame offset configuration are known \nin register SAI_xFRCR. \nIf the external master does not send the FS signal at the expecting time (generating the \nsignal too late), the flag LFSDET in the SAI_xSR register is set and an interrupt is generated \nif bit LFSDETIE in the SAI_xIM register is set. \nThe flag is cleared when bit CLFSDET is set in the SAI_xCLRFR register. \nMS192347V2\nsck\ndata\nSlot 0 ON\nMUTE\nSlot size = data size\nSD (output)\nExample: FIFO underrun on Slot 1\nAudio frame\nAudio frame\nMUTE\nSlot 1 ON\n... ON\nSlot 0 ON\nOVRUND=1\nMUTE\nFIFO empty\nOVRUND\n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n950/1757\nRM0090 Rev 21\nThe late frame synchronisation detection flag is set when the error is detected, SAI needs to \nbe resynchronized with the master (the four steps described above should be respected).\nThis detection and flag assertion can detect glitches on the SCK clock in a noisy \nenvironment, detected by the state machine of the audio block. It could incorrectly shift the \nSAI audio block state machine from one state in the current audio frame, thus corrupting the \nframe.\nThere is no corruption if the external master is not managing the audio data frame transfer in \na continuous mode, which should not be the case for most application purposes. In this \ncase, flag LFSDET is set.\nNote:\nThis flag is not asserted in AC’97 mode since the SAI audio block acts as a link controller \nand generates the FS signal even when declared as slave.\n29.13.4 \nCodec not ready (CNRDY AC’97)\nThe flag CNRDY in the SAI_xSR register is relevant only if the SAI audio block is configured \nto work in AC’97 mode (bit PRTCFG[1:0] = 10 in the SAI_xCR1 register). If bit CNRDYIE is \nset in the SAI_xIM register, an interrupt is generated when the flag CNRDY is set. \nIt is asserted when the codec is not ready to communicate during the reception of the TAG 0 \n(slot0) of the AC’97 audio frame. In this case, no data are automatically stored into the FIFO \nsince the codec is not ready, until the TAG 0 indicates that the codec is ready. All the active \nslots defined in the SAI_xSLOTR register are captured when the codec is ready.\nTo clear the flag, bit CCNRDY in the SAI_xCLRFR register has to be set.\n29.13.5 \nWrong clock configuration in master mode (with NODIV = 0)\nWhen the audio block is master (MODE[1] = 0 in the SAI_xCR1 register) and if bit NODIV in \nthe SAI_xCR1 is clear, the flag WCKCFG is set if bit FRL[7:0] in the SAI_xFRCR is not set \nwith a proper value when the SAIxEN bit in the SAI_xCR1 register is set, in order to respect \nthis following rule:\nwhere n is in the range from 3 to 8.\nIf bit WCKCFGIE is set, an interrupt is generated when flag WCKCFG is set in the SAI_xSR \nregister. To clear the flag, set bit CWCKCFG bit in the SAI_xCLRFR register. \nWhen bit WCKCFG is set, the audio block is automatically disabled, clearing bit SAIxEN in \nthe SAI_xCR1 register via hardware. \nThe above formula is intended to guarantee that the number of MCLK pulses by bit clock is \nan even integer in the audio frame with a 50% duty cycle bit clock generation to guarantee \nthe good quality of the audio sounds or acquisitions. \nFRL[7,0]\n(\n)\n1\n+\n2n\n=\n\n\n<>\n\nRM0090 Rev 21\n951/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.14 \nInterrupt sources\nThe SAI has 7 possible interrupt sources as illustrated by Table 132.\n \nBelow are the SAI configuration steps to follow when an interrupt occurs:\n1.\nDisable SAI interrupt.\n2. \nConfigure SAI.\n3. \nConfigure SAI interrupt source.\n4. \nEnable SAI.\n29.15 \nDisabling the SAI\nThe audio block in the SAI can be disabled at any moment by clearing bit SAIxEN in the \nSAI_xCR1 register. All the frames that have already started are automatically completed \nbefore the total extinction of the SAI. Bit SAIxEN in the SAI_xCR1 register stays high until \nthe SAI is completely switched-off at the end of the current audio frame transfer.\nTable 132. Interrupt sources\nInterrupt\nsource\nInterru\npt\ngroup\nAudio block mode\nInterrupt enable\nInterrupt clear\nFREQ\nFREQ\nMaster or Slave\nReceiver or transmitter\nFREQIE in \nSAI_xIM register\nDepend on:\n- FIFO threshold setting \n(FLTH bits in SAI_CR2) \n- Communication direction \ntransmitter or receiver\nfor more details please refer \nto Internal FIFOs section\nOVRUDR ERROR Master or Slave\nReceiver or transmitter\nOVRUDRIE in \nSAI_xIM register\nCOVRUDR = 1 in \nSAI_xCLRFR register\nAFSDET\nERROR\nSlave\n(Not used in AC’97 \nmode)\nAFSDETIE in \nSAI_xIM register\nCAFSDET = 1 in \nSAI_xCLRFR register\nLFSDET\nERROR\nSlave\n(Not used in AC’97 \nmode)\nLFSDETIE in \nSAI_xIM register\nCLFSDET = 1 in \nSAI_xCLRFR register\nCNRDY\nERROR Slave\n(Only in AC’97 mode)\nCNRDYIE in \nSAI_xIM register\nCCNRDY = 1 in \nSAI_xCLRFR register\nMUTEDE\nT\nMUTE\nMaster or slave\nReceiver mode only\nMUTEDETIE in \nSAI_xIM register\nCMUTEDET = 1 in \nSAI_xCLRFR register\nWCKCFG ERROR\nMaster with NODIV = 0 \nin the SAI_xCR1 \nregister\nWCKCFGIE in \nSAI_xIM register\nCWCKCFG = 1 in \nSAI_xCLRFR register\n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n952/1757\nRM0090 Rev 21\nIf there is an audio block in the SAI synchronous with the other one, the one which is the \nmaster must be disabled first.\n29.16 \nSAI DMA interface\nIn order to free the CPU and to optimize the bus bandwidth, each SAI audio block has an \nindependent DMA interface in order to read or to write into the SAI_xDR register (to hit the \ninternal FIFO). There is one DMA channel per audio block following basic DMA \nrequest/acknowledge protocol.\nTo configure the audio block to transfer through the DMA interface, set bit DMAEN in the \nSAI_xCR1 register. The DMA request is managed directly by the FIFO controller depend of \nFIFO threshold level (for more details please refer to Internal FIFOs section). DMA direction \nis linked to the SAI audio block configuration:\n•\nIf the audio block is a transmitter, the audio block’s FIFO controller outputs a DMA \nrequest to load the FIFO with data written in the SAI_xDR register.\n•\nIf the audio block is a receiver, the DMA request concerns read operations from the \nSAI_xDR register.\nBelow are the SAI configuration steps followed when DMA is used:\n1.\nConfigure SAI and FIFO Threshold level (in order to specify when the DMA request to \nbe launched)\n2. \nConfigure SAI DMA channel\n3. \nEnable DMA\n4. \nEnable SAI\nNote:\nBefore configuring the SAI block, the SAI DMA channel must be disabled. \n\n\n<>\n\nRM0090 Rev 21\n953/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.17 \nSAI registers\n29.17.1 \nSAI x configuration register 1 (SAI_xCR1) where x is A or B\nAddress offset: Block A: 0x004\nAddress offset: Block B: 0x024\nReset value: 0x0000 0040\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nMCKDIV[3:0]\nNODIV\nRes.\nDMAEN SAIxEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOutDri\nv\nMONO\nSYNCEN[1:0]\nCKSTR\nLSBFIR\nST\nDS[2:0]\nRes.\nPRTCFG[1:0]\nMODE[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, always read as 0.\nBit 23:20 MCKDIV[3:0]: Master clock divider. These bits are set and cleared by software.\n0000: Divides by 1 the master clock input.\nOtherwise, The Master clock frequency is calculated accordingly to the following formula:\nMCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2)\nThese bits have no meaning when the audio block is slave.\nThey have to be configured when the audio block is disabled.\nBit 19 NODIV: No divider. This bit is set and cleared by software.\n0: Master Clock divider is enabled\n1: No divider used in the clock generator (in this case Master Clock Divider bit has no effect)\nBit 18 Reserved, always read as 0.\nBit 17 DMAEN: DMA enable. This bit is set and cleared by software.\n0: DMA is disabled\n1: DMA is enabled\nNote: In receiver mode, the bits MODE must be configured before setting bit DMAEN to avoid a DMA \nrequest since the audio block is transmitter after reset (default setting)\nBit 16 SAIxEN: Audio block enable where x is A or B. This bit is set by software. It is cleared by hardware, \nafter disabling it by software (writing the bit low), the audio is completely disabled (waiting for the end \nof the current frame).\n0: Audio block is disabled\n1: Audio block is enabled: this bit can be set only if it is at 0 during the write operation (means the \nSAI is completely disabled before being re-enabled).\nThis bit allows to control the state of the audio block. If it is disabled somewhere in an audio frame, \nthe ongoing transfer is complete and the cell is totally disabled at the end of this audio frame \ntransfer.\nNote: When SAIx block is configured as master mode, clock must be present on the input of the SAI \nbefore setting SAIxEN bit.\nBits 15:14 Reserved, always read as 0.\nBit 13 OUTDRIV: Output drive. This bit is set and cleared by software. \n0: Audio block output driven when SAIEN is set\n1: Audio block output driven immediately after the setting of this bit.\nNote: This bit has to be set before enabling the audio block but after the audio block configuration. \n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n954/1757\nRM0090 Rev 21\nBit 12 MONO: Mono mode. This bit is set and cleared by software. \n0: Stereo mode\n1: Mono mode.\nThis bit has a meaning only when the number of slots is equal to 2.\nWhen the Mono mode is selected, the data of the slot 0 data is duplicated on the slot 1 when the \naudio block is a transmitter. In reception mode, the slot1 is discarded and only the data received \nfrom the slot 0 are stored.\nRefer to Section 29.12.2 for more details.\nBits 11:10 SYNCEN[1:0]: Synchronization enable. This bit is set and cleared by software. \n00: audio block is asynchronous.\n01: audio block is synchronous with the other internal audio block. In this case audio block should be \nconfigured in Slave mode\n10: Reserved.\n11: Not used\nThese bits have to be configured when the audio block is disabled.\nBit 9 CKSTR: Clock strobing edge. This bit is set and cleared by software. \n0: data strobing edge is falling edge of SCK\n1: data strobing edge is rising edge of SCK\nThis bit has to be configured when the audio block is disabled.\nBit 8 LSBFIRST: Least significant bit first. This bit is set and cleared by software. \n0: data is transferred with the MSB of the data first\n1: data is transferred with the LSB of the data first\nThis bit has to be configured when the audio block is disabled.\nThis bit has no meaning in AC’97 audio protocol since in AC’97 data is transferred with the MSB of \nthe data first.\nBits 7:5 DS[2:0]: Data size. These bits are set and cleared by software. \n000: Not used\n001: Not used\n010: 8-bit\n011: 10-bit\n100: 16-bit\n101: 20-bit\n110: 24-bit\n111: 32-bit\nWhen the companding mode is selected (bit COMP[1:0]), these DS[1:0] are ignored since the data \nsize is fixed to 8-bit mode by the algorithm itself.\nThese bits must be configured when the audio block is disabled.\nNote: When AC’97 mode is selected the data sizes that can be used are: 16-bit or 20-bit only, else \nSAI behavior is not guaranteed.\n\n\n<>\n\nRM0090 Rev 21\n955/1757\nRM0090\nSerial audio interface (SAI)\n967\nBit 4 Reserved, always read as 0.\nBits 3:2 PRTCFG[1:0]: Protocol configuration. These bits are set and cleared by software. \n00: Free protocol\n01: Not used\n10: AC’97 protocol\n11: Not used\nFree protocol selection allows to use the powerful configuration of the audio block to address a \nspecific audio protocol (such as I2S, LSB/MSB justified, free protocol, PCM/DSP) setting most of the \nconfiguration register bits as well as frame configuration register.\nThese bits have to be configured when the audio block is disabled.\nBits 1:0 MODE[1:0]: Audio block mode. These bits are set and cleared by software. \n00: Master transmitter\n01: Master receiver\n10: Slave transmitter\n11: Slave receiver\nThese bits have to be configured when the audio block is disabled.\nNote: In Master transmitter mode the audio block starts to generate the FS and clocks\n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n956/1757\nRM0090 Rev 21\n29.17.2 \nSAI x configuration register 2 (SAI_xCR2) where x is A or B\nAddress offset: Block A: 0x008\nAddress offset: Block B: 0x028\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCOMP[1:0]\nCPL\nMUTECNT[5:0]\nMUTE\nVAL\nMute\nTRIS\nFFLUS\nFTH\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, always read as 0\nBits 15:14 COMP[1:0]: Companding mode. These bits are set and cleared by software.\n00: No companding algorithm\n01: Reserved.\n10: µ-Law algorithm\n11: A-Law algorithm\nThe µ-Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of \ncomplement that is used depends on ComPLement bit.\nThe data expansion or data compression are determined by the state of bit MODE[0]. \nThe data compression is applied if the audio block is configured as a transmitter.\nThe data expansion is automatically applied when the audio block is configured as a receiver.\nRefer to Section 29.12.3 for more details.\nNote: Companding mode is applicable only when free protocol mode is selected.\nBit 13 CPL: Complement bit. This bit is set and cleared by software. \nIt defines the type of complement to be used for companding mode \n0: 1’s complement representation.\n1: 2’s complement representation.\nNote: This bit has effect only when the companding mode is µ-Law algorithm or A-Law algorithm.\nBits 12:7 MUTECNT[5:0]: Mute counter. These bits are set and cleared by software. \nThese bits are used only in reception mode. \nThe value set in these bits is compared to the number of consecutive mute frames detected in \nreception. When the number of mute frames is equal to this value, the flag MUTEDET is set and an \ninterrupt is generated if bit MUTEDETIE is set.\nRefer to Section 29.12.1 for more details.\n\n\n<>\n\nRM0090 Rev 21\n957/1757\nRM0090\nSerial audio interface (SAI)\n967\nBit 6 MUTEVAL: Mute value. This bit is set and cleared by software.This bit has to be written before \nenabling the audio block: SAIxEN.\n0: Bit value 0 is sent during the MUTE mode. \n1: Last values are sent during the MUTE mode.\nThis bit has a meaning only when the audio block is a transmitter and when the number of slots is \nlower or equal to 2 and if the MUTE bit is set.\nIf more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, \nwhatever the value of this MUTEVAL bit.\nif the number of slot is lower or equal to 2 and MUTEVAL = 1, the mute value transmitted for each \nslot is the one sent during the previous frame.\nRefer to Section 29.12.1 for more details.\nBit 5 MUTE: Mute. This bit is set and cleared by software.\n0: No Mute mode. \n1: Mute mode enabled.\nThis bit has a meaning only when the audio block is a transmitter. The MUTE value is linked to the \nMUTEVAL value if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2.\nRefer to Section 29.12.1 for more details.\nBit 4 TRIS: Tristate management on data line. This bit is set and cleared by software. \n0: SD output line is still driven by the SAI when a slot is inactive.\n1: SD output line is released (HI-Z) at the end of the last data bit of the last active slot if the next one \nis inactive.\nThis bit has a meaning only if the audio block is configured to be a transmitter.\nThis bit should be configured when SAI is disabled.\nRefer to Section 29.12.4 for more details.\nBit 3 FFLUSH: FIFO flush. This bit is set by software. It is always read low. \n0: No FIFO flush. \n1: FIFO flush.\nWriting 1 to the bit triggers the FIFO Flush. All the internal FIFO pointers (read and write) are \ncleared.\nData still present in the FIFO are lost in such case (no more transmission or received data lost).\nThis bit should be configured when SAI is disabled.\nBefore flushing SAI, DMA stream/interruption must be disabled\nBits 2:0 FTH: FIFO threshold. This bit is set and cleared by software. \n000: FIFO empty \n001: ¼ FIFO\n010: ½ FIFO\n011: ¾ FIFO\n100: FIFO full\n101: Reserved\n110: Reserved\n111: Reserved\n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n958/1757\nRM0090 Rev 21\n29.17.3 \nSAI x frame configuration register (SAI_XFRCR) where x is A or B\nAddress offset: Block A: 0x00C\nAddress offset: Block B: 0x02C\nReset value: 0x0000 0007\nNote:\nThis register has no meaning in AC’97 audio protocol\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nFSOFF\nFSPOL\nFSDEF\nrw \nrw\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nFSALL[6:0]\nFRL[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:19 Reserved, always read as 0.\nBit 18 FSOFF: Frame synchronization offset. This bit is set and cleared by software.\n0: FS is asserted on the first bit of the slot 0.\n1: FS is asserted one bit before the first bit of the slot 0.\nThis bit has no meaning and is not used in AC’97 audio block configuration.\nThis bit must be configured when the audio block is disabled.\nBit 17 FSPOL: Frame synchronization polarity. This bit is set and cleared by software\n0: FS is active low (falling edge)\n1: FS is active high (rising edge)\nThis bit is used to configure the level of the start of frame on the FS signal.\nThis bit has no meaning and is not used in AC’97 audio block configuration.\nThis bit must be configured when the audio block is disabled.\nBit 16 FSDEF: Frame synchronization definition. This bit is set and cleared by software.\n0: FS signal is a start frame signal\n1: FS signal is a start of frame signal + channel side identification\nWhen the bit is set, the number of slots defined in the SAI_ASLOTR register has to be even. It \nmeans that there is half of this number of slots dedicated for the left channel and the other slots for \nthe right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...)\nThis bit has no meaning and is not used in AC’97 audio block configuration.\nThis bit must be configured when the audio block is disabled.\n\n\n<>\n\nRM0090 Rev 21\n959/1757\nRM0090\nSerial audio interface (SAI)\n967\nBit 15 Reserved, always read as 0.\nBits 14:8 FSALL[6:0]: Frame synchronization active level length. These bits are set and cleared by software\nThe value set in these bits specifies the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of \nthe active level of the FS signal in the audio frame \nThese bits have no meaning and are not used in AC’97 audio block configuration.\nThese bits must be configured when the audio block is disabled.\nBits 7:0 FRL[7:0]: Frame length. These bits are set and cleared by software.\nThey define the length of the audio frame. More precisely, these bits define the number of SCK \nclocks for each audio frame. \nThe number of bits in the frame is equal to FRL[7:0] + 1. \nThe minimum number of bits to transfer in an audio frame has to be equal to 8 or else the audio \nblock has unexpected behavior. This is the case when the data size is 8-bit and only one slot 0 is \ndefined in NBSLOT[4:0] in the SAI_ASLOTR register (NBSLOT[3:0] = 0000).\nIn master mode, if the master clock MCLK_x pin is declared as an output, the frame length should \nbe aligned to a number equal to a power of 2, from 8 to 256 in order to keep in an audio frame, an \ninteger number of MCLK pulses by bit clock for correct operation for external DAC/ADC inside the \ndecoders.\nThe Frame length should be even.\nThese bits have no meaning and are not used in AC’97 audio block configuration.\nNote: The FRL[7:0] bitfield must be configured when the audio block is disabled. \n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n960/1757\nRM0090 Rev 21\n29.17.4 \nSAI x slot register (SAI_xSLOTR) where x is A or B\nAddress offset: Block A: 0x010\nAddress offset: Block B: 0x030\nReset value: 0x0000 0000\nNote:\nThis register has no meaning in AC’97 audio protocol\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nSLOTEN[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNBSLOT[3:0]\nSLOTSZ[1:0]\nRes\nFBOFF[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 SLOTEN[15:0]: Slot enable. These bits are set and cleared by software.\nEach bit of the SLOTEN bits identify a slot position from 0 to 15 (maximum 16 slots)\n0: Inactive slot.\n1: Active slot.\nThese bits must be set when the audio block is disabled.\nThey are ignored in AC’97 mode.\nBits 15:12 Reserved, always read as 0.\nBits 11:8 NBSLOT[3:0]: Number of slots in an audio frame. These bits are set and cleared by software.\nThe value set in these bits register represents the number of slots + 1 in the audio frame (including \nthe number of inactive slots). The maximum number of slots is 16.\nThe number of slots should be even if bit FSDEF in the SAI_AFRCR register is set.\nIf the size is greater than the data size, the remaining bits are forced to 0 if bit TRIS in the SAI_xCR1 \nregister is clear, otherwise they are forced to 0 if the next slot is active or the SD line is forced to HI-\nZ if the next slot is inactive and bit TRIS = 1.\nThese bits must be set when the audio block is disabled.\nThey are ignored in AC’97 omode.\nBits 7:6 SLOTSZ[1:0]: Slot size\nThis bits is set and cleared by software.\n00: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_ACR1 register).\n01: 16-bit\n10: 32-bit\n11: Reserved\nThe slot size must be greater or equal to the data size. If this condition is not respected, the behavior \nof the SAI is undetermined.\nThese bits must be set when the audio block is disabled.\nThey are ignored in AC’97 mode.\nBit 1 Reserved, always read as 0.\nBits 4:0 FBOFF[4:0]: First bit offset \nThese bits are set and cleared by software.\nThe value set in these bits represents the position of the first data transfer bit in the slot. It represents \nan offset value. During this offset phase 0 value are sent on the data line for transmission mode. For \nreception mode, the received bit are discarded during the offset phase.\nThese bits must be set when the audio block is disabled.\nThey are ignored in AC’97 mode.\n\n\n<>\n\nRM0090 Rev 21\n961/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.17.5 \nSAI x interrupt mask register (SAI_xIM) where x is A or B\nAddress offset: block A: 0x014\nAddress offset: block B: 0x034\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLFSDETI\nE\nAFSDET\nIE\nCNRDY\nIE\nFREQI\nE\nWCKC\nFGIE\nMUT\nEDET\nIE\nOVRU\nDRIE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:7 Reserved, always read as 0.\nBit 6 LFSDETIE: Late frame synchronization detection interrupt enable. This bit is set and cleared by \nsoftware.\n0: Interrupt is disabled\n1: Interrupt is enabled\nWhen this bit is set, an interrupt is generated if the LFSDET bit is set in the SAI_ASR register.\nThis bit has no meaning in AC’97 mode. It has no meaning also if the audio block is master.\nBit 5 AFSDETIE: Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by \nsoftware.\n0: Interrupt is disabled\n1: Interrupt is enabled\nWhen this bit is set, an interrupt is generated if the AFSDET bit in the SAI_ASR register is set.\nThis bit has no meaning in AC’97 mode. It has no meaning also if the audio block is master.\nBit 4 CNRDYIE: Codec not ready interrupt enable (ac’97). This bit is set and cleared by software.\n0: Interrupt is disabled\n1: Interrupt is enabled\nWhen the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC’97 frame if the \ncodec connected on this line is ready or not. If not, the flag CNRDY in the SAI_ASR register is set \nand an interruption is generated.\nThis bit has a meaning only if the AC97 mode is selected (bit PRTCFG[1:0]) and the audio block is a \nreceiver.\nBit 3 FREQIE: FIFO request interrupt enable. This bit is set and cleared by software.\n0: Interrupt is disabled\n1: Interrupt is enabled\nWhen this bit is set, an interrupt is generated if the FREQ bit in the SAI_ASR register is set.\nIn receiver mode, the bit MODE must be configured before setting bit FREQIE to avoid a parasitic \ninterruption since the audio block is a transmitter (default setting).\n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n962/1757\nRM0090 Rev 21\nBit 2 WCKCFGIE: Wrong clock configuration interrupt enable. This bit is set and cleared by software.\n0: Interrupt is disabled\n1: Interrupt is enabled\nThis bit is considered only if the audio block is configured as master (MODE[1] = 0 in the SAI_ACR1 \nregister) and bit NODIV = 0 in the SAI_xCR1 register.\nIt generates an interrupt if the flag WCKCFG in the SAI_ASR register is set.\nNote: This bit is used only in free protocol mode and has no meaning for other modes.\nBit 1 MUTEDETIE: Mute detection interrupt enable. This bit is set and cleared by software.\n0: Interrupt is disabled\n1: Interrupt is enabled\nWhen this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_ASR register is set.\nThis bit has a meaning only if the audio block is configured in receiver mode.\nBit 0 OVRUDRIE: Overrun/underrun interrupt enable. This bit is set and cleared by software.\n0: Interrupt is disabled\n1: Interrupt is enabled\nWhen this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_ASR register is set.\n\n\n<>\n\nRM0090 Rev 21\n963/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.17.6 \nSAI x status register (SAI_xSR) where x is A or B\nAddress offset: block A: 0x018\nAddress offset: block B: 0x038\nReset value: 0x0000 0008\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nFLTH\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLFSDET AFSDET\nCNRDY\nFREQ\nWCKCFG\nMUTED\nET\nOVRUDR\nr\nr\nr\nr\nr\nr\nr\nBits 31:19 Reserved, always read as 0.\nBits 18:16 FLTH: FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by \nhardware and its setting depends on SAI block configuration (transmitter or receiver mode). \nIf SAI block is configured as transmitter:\n000: FIFO_empty\n001: FIFO <= ¼ but not empty\n010: ¼ < FIFO <= ½\n011: ½ < FIFO <= ¾\n100: ¾ < FIFO but not full\n101: FIFO full\nIf SAI block is configured as receiver:\n000: FIFO_empty\n001: FIFO < ¼ but not empty\n010: ¼ <= FIFO < ½\n011: ½ =< FIFO < ¾\n100: ¾ =< FIFO but not full\n101: FIFO full\nBits 15:7 Reserved, always read as 0.\nBit 6 LFSDET: Late frame synchronization detection. This bit is read only.\n0: No error.\n1: Frame synchronization signal is not present at the right time. \nThis flag can be set only if the audio block is configured in Slave mode.\nIt is not used in AC’97 mode.\nIt may generate an interrupt if bit LFSDETIE in the SAI_xIM register is set.\nThis flag is cleared when the software sets bit CLFSDET in the SAI_xCLRFR register\nBit 5 AFSDET: Anticipated frame synchronization detection. This bit is read only.\n0: No error.\n1: Frame synchronization signal is detected earlier than expected. \nThis flag can be set only if the audio block is configured in Slave mode.\nIt is not used in AC’97.\nIt may generate an interrupt if bit AFSDETIE in the SAI_xIM register is set.\nThis flag is cleared when the software sets bit CAFSDET in the SAI_xCLRFR register\n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n964/1757\nRM0090 Rev 21\n \nBit 4 CNRDY: Codec not ready. This bit is read only. \n0: The external AC’97 codec is ready \n1: The external AC’97 codec is not ready\nThis bit is used only when the AC’97 audio protocol is selected in the SAI_xCR1 register and is \nconfigured in receiver mode.\nIt may generate an interrupt if bit CNRDYIE in the SAI_xIM register is set.\nThis flag is cleared when the software sets bit CCNRDY in the SAI_xCLRFR register\nBit 3 FREQ: FIFO request. This bit is read only.\n0: No FIFO request.\n1: FIFO request to read or to write the SAI_xDR.\nThe request depends on the audio block configuration. \nIf configured in transmission, the FIFO request concerns a write request operation in the SAI_xDR. \nIf configured in reception, the FIFO request concerns a read request operation from the SAI_xDR.\nThis flag can generate an interrupt if bit FREQIE in the SAI_xIM register is set.\nBit 2 WCKCFG: Wrong clock configuration flag. This bit is read only. \n0: The clock configuration is correct\n1: The clock configuration does not respect the rule concerning the frame length specification \ndefined in Section 29.7 (configuration of FRL[7:0] bit in the SAI_x FRCR register)\nThis bit is used only when the audio block is master (MODE[1] = 0 in the SAI_xCR1 register) and \nwhen NODIV = 0 in the SAI_xCR1 register. \nIt may generate an interrupt if bit WCKCFGIE in the SAI_xIM register is set.\nThis flag is cleared when the software sets bit CWCKCFG in the SAI_xCLRFR register\nBit 1 MUTEDET: Mute detection. This bit is read only.\n0: No MUTE detection on the SD input line\n1: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio \nframe\nThis flag is set if consecutive 0 values are received in each slot of an audio frame and for a \nconsecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register).\nIt may generate an interrupt if bit MUTEDETIE in the SAI_xIM register is set.\nThis flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register.\nBit 0 OVRUDR: Overrun / underrun. This bit is read only.\n0: No overrun/underrun error.\n1: Overrun/underrun error detection.\nThe overrun condition can occur only when the audio block is configured in reception.\nThe underrun condition can occur only when the audio block is configured in transmission.\nIt may generate an interrupt if bit OVRUDRIE in the SAI_xIM register is set.\nThis flag is cleared when the software set bit COVRUDR bit in the SAI_xCLRFR register.\n\n\n<>\n\nRM0090 Rev 21\n965/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.17.7 \nSAI x clear flag register (SAI_xCLRFR) where X is A or B\nAddress offset: block A: 0x01C\nAddress offset: block B: 0x03C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCLFSDET\nCAFSDE\nT\nCCNRDY\nReserved\nCWCKCFG CMUTE\nDET\nCOVRUD\nR\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:7 Reserved, always read as 0.\nBit 6 CLFSDET: Clear late frame synchronization detection flag. This bit is write only.\nWriting 1 in this bit clears the flag LFSDET in the SAI_xSR register.\nIt is not used in AC’97.\nReading this bit always returns the value 0. \nBit 5 .CAFSDET: Clear anticipated frame synchronization detection flag. This bit is write only.\nWriting 1 in this bit clears the flag AFSDET in the SAI_xSR register.\nIt is not used in AC’97.\nReading this bit always returns the value 0. \nBit 4 CCNRDY: Clear codec not ready flag. This bit is write only.\nWriting 1 in this bit clears the flag CNRDY in the SAI_xSR register.\nThis bit is used only when the AC’97 audio protocol is selected in the SAI_xCR1 register.\nReading this bit always returns the value 0. \nBit 3 Reserved, always read as 0.\nBit 2 CWCKCFG: Clear wrong clock configuration flag. This bit is write only.\nWriting 1 in this bit clears the flag WCKCFG in the SAI_xSR register.\nThis bit is used only when the audio block is set as master (MODE[1] = 0 in the SAI_ACR1 register) \nand bit NODIV = 0 in the SAI_xCR1 register.\nReading this bit always returns the value 0. \nBit 1 CMUTEDET: Mute detection flag. This bit is write only.\nWriting 1 in this bit clears the flag MUTEDET in the SAI_xSR register.\nReading this bit always returns the value 0. \nBit 0 COVRUDR: Clear overrun / underrun. This bit is write only.\nWriting 1 in this bit clears the flag OVRUDR in the SAI_xSR register.\nReading this bit always returns the value 0.\n\n\n<>\n\nSerial audio interface (SAI)\nRM0090\n966/1757\nRM0090 Rev 21\n29.17.8 \nSAI x data register (SAI_xDR) where x is A or B\nAddress offset: block A: 0x020\nAddress offset: block B: 0x040\nReset value: 0x0000 0000\n \n \n29.17.9 \nSAI register map\nThe following table summarizes the SAI registers.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATA[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATA[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 DATA[31:0]: Data \nA write into this register has the effect of loading the FIFO if the FIFO is not full.\nA read from this register has to effect of draining-up the FIFO if the FIFO is not empty.\nTable 133. SAI register map and reset values\nOffset\nRegister \nand reset \nvalue\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x0004\nor\n0x0024\nSAI_xCR1\nReserved\nMCKDIV[3:0]\nNODIV\nRes.\nDMAEN\nSAIxEN\nReserved.\nOutDri\nMONO\nSYNCE\nN[1:0]\nCKSTR\nLSBFIRST\nDS[2:0]\nRes.\nPRTCF\nG[1:0]\nMODE[\n1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0x0008\nor 0x0028\nSAI_xCR2\nReserved\nCOMP[\n1:0]\nCPL\nMUTECN[5:0]\nMUTE VAL\nMUTE\nTRIS\nFFLUS\nFTH\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x000Cor \n0x002C\nSAI_xFRCR\nReserved\nFSOFF\nFSPOL\nFSDEF\nReserved\nFSALL[6:0]\nFRL[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n0x0010 or\n0x0030\nSAI_xSLOTR\nSLOTEN[15:0]\nReserved\nNBSLOT[3:0] SLOTS\nZ[1:0}\nReserved\nFBOFF[4:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0014\nor 0x0034\nSAI_xIM\nReserved\nLFSDET\nAFSDETIE\nCNRDYIE\nFREQIE\nWCKCFG\nMUTEDET\nOVRUDRIE\nReset value\n0\n0\n0\n0\n0\n0\n0\n0x0018\nor \n0x0038\nSAI_xSR\nReserved\nFLVL[2:0]\nReserved\nLFSDET\nAFSDET\nCNRDY\nFREQ\nWCKCFG\nMUTEDET\nOVRUDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n\n\n<>\n\nRM0090 Rev 21\n967/1757\nRM0090\nSerial audio interface (SAI)\n967\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x001C\nor 0x003C\nSAI_xCLRFR\nReserved\nLFSDET\nCAFSDET\nCNRDY\nRes.\nWCKCFG\nMUTEDET\nOVRUDR\nReset value\n0\n0\n0\n0\n0\n0\n0x0020\nor 0x0040\nSAI_xDR\nDATA[31:0] \nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 133. SAI register map and reset values (continued)\nOffset\nRegister \nand reset \nvalue\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n968/1757\nRM0090 Rev 21\n30 \nUniversal synchronous asynchronous receiver\ntransmitter (USART)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n30.1 \nUSART introduction\nThe universal synchronous asynchronous receiver transmitter (USART) offers a flexible \nmeans of full-duplex data exchange with external equipment requiring an industry standard \nNRZ asynchronous serial data format. The USART offers a very wide range of baud rates \nusing a fractional baud rate generator.\nIt supports synchronous one-way communication and half-duplex single wire \ncommunication. It also supports the LIN (local interconnection network), Smartcard Protocol \nand IrDA (infrared data association) SIR ENDEC specifications, and modem operations \n(CTS/RTS). It allows multiprocessor communication.\nHigh speed data communication is possible by using the DMA for multibuffer configuration.\n30.2 \nUSART main features\n•\nFull duplex, asynchronous communications\n•\nNRZ standard format (Mark/Space)\n•\nConfigurable oversampling method by 16 or by 8 to give flexibility between speed and \nclock tolerance\n•\nFractional baud rate generator systems\n–\nCommon programmable transmit and receive baud rate (refer to the datasheets \nfor the value of the baud rate at the maximum APB frequency.\n•\nProgrammable data word length (8 or 9 bits)\n•\nConfigurable stop bits - support for 1 or 2 stop bits\n•\nLIN Master Synchronous Break send capability and LIN slave break detection \ncapability\n–\n13-bit break generation and 10/11 bit break detection when USART is hardware \nconfigured for LIN\n•\nTransmitter clock output for synchronous transmission\n•\nIrDA SIR encoder decoder\n–\nSupport for 3/16 bit duration for normal mode\n•\nSmartcard emulation capability\n–\nThe Smartcard interface supports the asynchronous protocol Smartcards as \ndefined in the ISO 7816-3 standards\n–\n0.5, 1.5 stop bits for Smartcard operation\n•\nSingle-wire half-duplex communication\n•\nConfigurable multibuffer communication using DMA (direct memory access)\n–\nBuffering of received/transmitted bytes in reserved SRAM using centralized DMA\n•\nSeparate enable bits for transmitter and receiver\n\n\n<>\n\nRM0090 Rev 21\n969/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n•\nTransfer detection flags:\n–\nReceive buffer full\n–\nTransmit buffer empty\n–\nEnd of transmission flags\n•\nParity control:\n–\nTransmits parity bit\n–\nChecks parity of received data byte\n•\nFour error detection flags:\n–\nOverrun error\n–\nNoise detection\n–\nFrame error\n–\nParity error\n•\nTen interrupt sources with flags:\n–\nCTS changes\n–\nLIN break detection\n–\nTransmit data register empty\n–\nTransmission complete\n–\nReceive data register full\n–\nIdle line received\n–\nOverrun error\n–\nFraming error \n–\nNoise error\n–\nParity error\n•\nMultiprocessor communication - enter into mute mode if address match does not occur\n•\nWake up from mute mode (by idle line detection or address mark detection)\n•\nTwo receiver wake-up modes: Address bit (MSB, 9th bit), Idle line\n30.3 \nUSART functional description\nThe interface is externally connected to another device by three pins (see Figure 296). Any \nUSART bidirectional communication requires a minimum of two pins: Receive Data In (RX) \nand Transmit Data Out (TX):\nRX: Receive Data Input is the serial data input. Oversampling techniques are used for data \nrecovery by discriminating between valid incoming data and noise.\nTX: Transmit Data Output. When the transmitter is disabled, the output pin returns to its I/O \nport configuration. When the transmitter is enabled and nothing is to be transmitted, the TX \npin is at high level. In single-wire and smartcard modes, this I/O is used to transmit and \nreceive the data (at USART level, data are then received on SW_RX).\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n970/1757\nRM0090 Rev 21\nThrough these pins, serial data is transmitted and received in normal USART mode as \nframes comprising: \n•\nAn Idle Line prior to transmission or reception\n•\nA start bit\n•\nA data word (8 or 9 bits) least significant bit first\n•\n0.5,1, 1.5, 2 Stop bits indicating that the frame is complete\n•\nThis interface uses a fractional baud rate generator - with a 12-bit mantissa and 4-bit \nfraction\n•\nA status register (USART_SR)\n•\nData Register (USART_DR)\n•\nA baud rate register (USART_BRR) - 12-bit mantissa and 4-bit fraction.\n•\nA Guardtime Register (USART_GTPR) in case of Smartcard mode.\nRefer to Section 30.6: USART registers on page 1010 for the definitions of each bit. \nThe following pin is required to interface in synchronous mode:\n•\nCK: Transmitter clock output. This pin outputs the transmitter data clock for \nsynchronous transmission corresponding to SPI master mode (no clock pulses on start \nbit and stop bit, and a software option to send a clock pulse on the last data bit). In \nparallel data can be received synchronously on RX. This can be used to control \nperipherals that have shift registers (e.g. LCD drivers). The clock phase and polarity \nare software programmable. In smartcard mode, CK can provide the clock to the \nsmartcard. \nThe following pins are required in Hardware flow control mode:\n•\nCTS: Clear To Send blocks the data transmission at the end of the current transfer \nwhen high\n•\nRTS: Request to send indicates that the USART is ready to receive a data (when low).\n\n\n<>\n\nRM0090 Rev 21\n971/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nFigure 296. USART block diagram\nWakeup\nunit\nReceiver\ncontrol\nSR\nTransmit\ncontrol\nTXE TC RXNE IDLE ORE NF\nFE\nUSART\ncontrol\ninterrupt\nCR1\nM\nWAKE\nReceive data register (RDR)\nReceive Shift Register\nRead\nTransmit data register (TDR)\nTransmit Shift Register\nWrite\nSW_RX\nTX\n(Data register) DR\nTransmitter\n clock\nReceiver \nclock\nReceiver rate\nTransmitter rate\n \nfPCLKx(x=1,2)\n control\ncontrol\n/ [8 x (2 - OVER8)]\nConventional baud rate generator\nSBK\nRWU\nRE\nTE\nIDLE\nRXNE\nTCIE\nTXEIE\nCR1\nUE\nPCE\nPS\nPEIE\nPE\nPWDATA\nIRLP\nSCEN\nIREN\nDMAR\nDMAT\nUSART Address\nCR2\nCR3\nIrDA\nSIR\nENDEC\nblock\nLINE\nCKEN\nCPOL CPHA LBCL\nSCLK control\nCK\nCR2\nGT\nSTOP[1:0]\nNACK\nDIV_Mantissa\n15\n0\nRE\nUSART_BRR\n/USARTDIV\nTE\nHD\n(CPU or DMA)\n(CPU or DMA)\nPRDATA\nHardware\nflow\ncontroller\nCTS LBD\nRX\nIRDA_OUT\nIRDA_IN\nRTS\nCTS\nGTPR\nPSC\nIE\nIE\nDIV_Fraction\n4\nUSARTDIV = DIV_Mantissa + (DIV_Fraction / 8 × (2 – OVER8))\nSAMPLING\nCR1\nOVER8\nDIVIDER\nai16099b\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n972/1757\nRM0090 Rev 21\n30.3.1 \nUSART character description\nWord length may be selected as being either 8 or 9 bits by programming the M bit in the \nUSART_CR1 register (see Figure 297).\nThe TX pin is in low state during the start bit. It is in high state during the stop bit. \nAn Idle character is interpreted as an entire frame of “1”s followed by the start bit of the \nnext frame which contains data (The number of “1” ‘s includes the number of stop bits).\nA Break character is interpreted on receiving “0”s for a frame period. At the end of the \nbreak frame the transmitter inserts either 1 or 2 stop bits (logic “1” bit) to acknowledge the \nstart bit.\nTransmission and reception are driven by a common baud rate generator, the clock for each \nis generated when the enable bit is set respectively for the transmitter and receiver.\nThe details of each block is given below.\nFigure 297. Word length programming\nMS19822V2\nBit0\nBit1\nBit2\nBit3\nBit4\nBit5\nBit6\nBit7\nBit8\nStart\nbit\nStop\nbit\nNext\nStart \nbit\nIdle frame\n9-bit word length (M bit is set), 1 Stop bit\nPossible\nParity\nbit\nBreak frame\nData frame\nNext data frame\nClock\n** LBCL bit controls last data clock pulse\n**\nStart\nbit\nStart\nbit\nStop\nbit\nBit0\nBit1\nBit2\nBit3\nBit4\nBit5\nBit6\nBit7\nStart\nbit\nStop\nbit\nNext\nStart \nbit\nIdle frame\n8-bit word length (M bit is reset), 1 Stop bit\nPossible\nParity\nbit\nBreak frame\nData frame\nNext data frame\nClock\n** LBCL bit controls last data clock pulse\n**\nStart\nbit\nStart\nbit\nStop\nbit\n\n\n<>\n\nRM0090 Rev 21\n973/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n30.3.2 \nTransmitter\nThe transmitter can send data words of either 8 or 9 bits depending on the M bit status. \nWhen the transmit enable bit (TE) is set, the data in the transmit shift register is output on \nthe TX pin and the corresponding clock pulses are output on the CK pin.\nCharacter transmission\nDuring an USART transmission, data shifts out least significant bit first on the TX pin. In this \nmode, the USART_DR register consists of a buffer (TDR) between the internal bus and the \ntransmit shift register (see Figure 296).\nEvery character is preceded by a start bit which is a logic level low for one bit period. The \ncharacter is terminated by a configurable number of stop bits.\nThe following stop bits are supported by USART: 0.5, 1, 1.5 and 2 stop bits.\nNote:\nThe TE bit should not be reset during transmission of data. Resetting the TE bit during the \ntransmission corrupts the data on the TX pin as the baud rate counters get frozen. The \ncurrent data being transmitted are lost. \nAn idle frame is sent after the TE bit is enabled.\nConfigurable stop bits\nThe number of stop bits to be transmitted with every character can be programmed in \nControl register 2, bits 13,12.\n•\n1 stop bit: This is the default value of number of stop bits.\n•\n2 Stop bits: This is supported by normal USART, single-wire and modem modes.\n•\n0.5 stop bit: To be used when receiving data in Smartcard mode.\n•\n1.5 stop bits: To be used when transmitting and receiving data in Smartcard mode.\nAn idle frame transmission includes the stop bits.\nA break transmission is 10 low bits followed by the configured number of stop bits (when m \n= 0) and 11 low bits followed by the configured number of stop bits (when m = 1). It is not \npossible to transmit long breaks (break of length greater than 10/11 low bits).\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n974/1757\nRM0090 Rev 21\nFigure 298. Configurable stop bits \nProcedure:\n1.\nEnable the USART by writing the UE bit in USART_CR1 register to 1.\n2. \nProgram the M bit in USART_CR1 to define the word length.\n3. \nProgram the number of stop bits in USART_CR2.\n4. \nSelect DMA enable (DMAT) in USART_CR3 if Multi buffer Communication is to take \nplace. Configure the DMA register as explained in multibuffer communication.\n5. \nSelect the desired baud rate using the USART_BRR register.\n6. \nSet the TE bit in USART_CR1 to send an idle frame as first transmission.\n7. \nWrite the data to send in the USART_DR register (this clears the TXE bit). Repeat this \nfor each data to be transmitted in case of single buffer.\n8. \nAfter writing the last data into the USART_DR register, wait until TC=1. This indicates \nthat the transmission of the last frame is complete. This is required for instance when \nthe USART is disabled or enters the Halt mode to avoid corrupting the last \ntransmission.\nSingle byte communication\nClearing the TXE bit is always performed by a write to the data register.\nThe TXE bit is set by hardware and it indicates:\n•\nThe data has been moved from TDR to the shift register and the data transmission has \nstarted. \n•\nThe TDR register is empty.\n•\nThe next data can be written in the USART_DR register without overwriting the \nprevious data.\nThis flag generates an interrupt if the TXEIE bit is set.\nMSv42088V1\nBit0\nBit1\nBit2\nBit3\nBit4\nBit5\nBit6\nBit7\nStart\nBit\nStop\nbit\nNext\nstart \n8-bit Word length (M bit is reset)\nPossible\nparity \nbit\nData frame\nNext data frame\n****\n** LBCL bit controls last data clock pulse\nCLOCK\n**\nBit0\nBit1\nBit2\nBit3\nBit4\nBit5\nBit6\nBit7\nStart\nBit\n2 Stop Bits \nNext\nStart \nBit\nPossible\nparity \nbit\nData frame\nNext data frame\nNext data frame\nBit0\nBit1\nBit2\nBit3\nBit4\nBit5\nBit6\nBit7\nStart\nBit\nNext\nstart \nbit\nPossible\nParity \nBit\nData frame\nNext data frame\n1 1/2 stop bits \na) 1 Stop Bit\nb) 1 1/2 stop Bits\nc) 2 Stop Bits\nBit0\nBit1\nBit2\nBit3\nBit4\nBit5\nBit6\nBit7\nStart\nBit\n1/2 Stop Bit \nNext\nStart \nBit\nPossible\nparity \nbit\nData frame\nd) 1/2 Stop Bit\n\n\n<>\n\nRM0090 Rev 21\n975/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nWhen a transmission is taking place, a write instruction to the USART_DR register stores \nthe data in the TDR register and which is copied in the shift register at the end of the current \ntransmission.\nWhen no transmission is taking place, a write instruction to the USART_DR register places \nthe data directly in the shift register, the data transmission starts, and the TXE bit is \nimmediately set.\nIf a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An \ninterrupt is generated if the TCIE bit is set in the USART_CR1 register.\nAfter writing the last data into the USART_DR register, it is mandatory to wait for TC=1 \nbefore disabling the USART or causing the microcontroller to enter the low-power mode \n(see Figure 299: TC/TXE behavior when transmitting).\nThe TC bit is cleared by the following software sequence:\n1.\nA read from the USART_SR register\n2. \nA write to the USART_DR register\nNote:\nThe TC bit can also be cleared by writing a ‘0 to it. This clearing sequence is recommended \nonly for Multibuffer communication.\nFigure 299. TC/TXE behavior when transmitting\nBreak characters\nSetting the SBK bit transmits a break character. The break frame length depends on the M \nbit (see Figure 297).\nIf the SBK bit is set to ‘1 a break character is sent on the TX line after completing the current \ncharacter transmission. This bit is reset by hardware when the break character is completed \n(during the stop bit of the break character). The USART inserts a logic 1 bit at the end of the \nlast break frame to guarantee the recognition of the start bit of the next frame.\nNote:\nIf the software resets the SBK bit before the commencement of break transmission, the \nbreak character is not transmitted. For two consecutive breaks, the SBK bit should be set \nafter the stop bit of the previous break.\nSoftware wait until TC=1\nSoftware \nenables the \nUSART\nSoftware waits until TXE=1 \nand writes F2 into DR\nIdle preamble\nFrame 1\nFrame 2\nFrame 3\nSet by hardware\nset by hardware\ncleared by software\nset by hardware\ncleared by software\nSoftware waits until TXE=1 \nand writes F1 into DR\nSoftware waits until TXE=1 \nand writes F1 into DR\nTC is not set \nbecause TXE=0\nTC is not set \nbecause TXE=1\nUSART_DR\nTC flag\nTXE flag\nTX line\nset\nby hardware\nTC is not set \nbecause TXE=0\nF1\nF2\nF3\nMS48961V1\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n976/1757\nRM0090 Rev 21\nIdle characters\nSetting the TE bit drives the USART to send an idle frame before the first data frame.\n30.3.3 \nReceiver\nThe USART can receive data words of either 8 or 9 bits depending on the M bit in the \nUSART_CR1 register. \nStart bit detection\nThe start bit detection sequence is the same when oversampling by 16 or by 8.\nIn the USART, the start bit is detected when a specific sequence of samples is recognized. \nThis sequence is: 1 1 1 0 X 0 X 0 X 0 0 0 0.\nFigure 300. Start bit detection when oversampling by 16 or 8\nNote:\nIf the sequence is not complete, the start bit detection aborts and the receiver returns to the \nidle state (no flag is set), where it waits for a falling edge.\nThe start bit is confirmed (RXNE flag set, interrupt generated if RXNEIE=1) if the three \nsampled bits are at 0 (first sampling on the third, fifth and seventh bit finds the three bits at 0 \nand second sampling on the eighth, ninth and tenth bit also finds the three bits at 0).\nThe start bit is validated (RXNE flag set, interrupt generated if RXNEIE=1) but the NE noise \nflag is set if, for both samplings, at least two out of the three sampled bits are at 0 (sampling \non the third, fifth and seventh bit and sampling on the eighth, ninth and tenth bit). If this \n0\n1\n0\nX\n0\nX\n0\n0\n0\n0\nX\nX\nX\nX\nX\nX\nFalling edge\ndetection\n1\n1\n1\n2\n3\n4\n5\n6\n7\n8\n9\n10\n11\n12\n13\n14\n15\n16\nX\nX\nX\nX\nX\nX\nX\nX\n9\n1\n0\n1 1\n1 2\n1 3\n1 4\n1 5 1 6\n6/16\n7/16\n7/16\nX\nAt least 2 bits\nout of 3 at 0\nAt least 2 bits\nout of 3 at 0\nOne-bit time\nConditions\nto validate\nthe start bit\nReal\nsample\nclock\nIdeal\nsample\nclock\nRX line\nRX state\nIdle\nStart bit\nSampled values\nai15471b\n\n\n<>\n\nRM0090 Rev 21\n977/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\ncondition is not met, the start detection aborts and the receiver returns to the idle state (no \nflag is set).\nIf, for one of the samplings (on the third, fifth and seventh bit, or on the eighth, ninth and \ntenth bit), two out of the three bits are found at 0, the start bit is validated but the NE noise \nflag bit is set.\nCharacter reception\nDuring an USART reception, data shifts in least significant bit first through the RX pin. In this \nmode, the USART_DR register consists of a buffer (RDR) between the internal bus and the \nreceived shift register.\nProcedure:\n1.\nEnable the USART by writing the UE bit in USART_CR1 register to 1.\n2. \nProgram the M bit in USART_CR1 to define the word length.\n3. \nProgram the number of stop bits in USART_CR2.\n4. \nSelect DMA enable (DMAR) in USART_CR3 if multibuffer communication is to take \nplace. Configure the DMA register as explained in multibuffer communication. STEP 3\n5. \nSelect the desired baud rate using the baud rate register USART_BRR \n6. \nSet the RE bit USART_CR1. This enables the receiver which begins searching for a \nstart bit.\nWhen a character is received\n•\nThe RXNE bit is set. It indicates that the content of the shift register is transferred to the \nRDR. In other words, data has been received and can be read (as well as its \nassociated error flags).\n•\nAn interrupt is generated if the RXNEIE bit is set.\n•\nThe error flags can be set if a frame error, noise or an overrun error has been detected \nduring reception.\n•\nIn multibuffer, RXNE is set after every byte received and is cleared by the DMA read to \nthe Data Register.\n•\nIn single buffer mode, clearing the RXNE bit is performed by a software read to the \nUSART_DR register. The RXNE flag can also be cleared by writing a zero to it. The \nRXNE bit must be cleared before the end of the reception of the next character to avoid \nan overrun error.\nNote:\nThe RE bit should not be reset while receiving data. If the RE bit is disabled during \nreception, the reception of the current byte is aborted.\nBreak character\nWhen a break character is received, the USART handles it as a framing error.\nIdle character\nWhen an idle frame is detected, there is the same procedure as a data received character \nplus an interrupt if the IDLEIE bit is set.\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n978/1757\nRM0090 Rev 21\nOverrun error\nAn overrun error occurs when a character is received when RXNE has not been reset. Data \ncan not be transferred from the shift register to the RDR register until the RXNE bit is \ncleared.\nThe RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set \nwhen the next data is received or the previous DMA request has not been serviced. When \nan overrun error occurs: \n•\nThe ORE bit is set. \n•\nThe RDR content is not lost. The previous data is available when a read to USART_DR \nis performed. \n•\nThe shift register is overwritten. After that point, any data received during overrun is \nlost.\n•\nAn interrupt is generated if either the RXNEIE bit is set or both the EIE and DMAR bits \nare set.\n•\nThe ORE bit is reset by a read to the USART_SR register followed by a USART_DR \nregister read operation.\nNote:\nThe ORE bit, when set, indicates that at least 1 data has been lost. There are two \npossibilities:\n•\nif RXNE=1, then the last valid data is stored in the receive register RDR and can be \nread,\n•\nif RXNE=0, then it means that the last valid data has already been read and thus there \nis nothing to be read in the RDR. This case can occur when the last valid data is read in \nthe RDR at the same time as the new (and lost) data is received. It may also occur \nwhen the new data is received during the reading sequence (between the USART_SR \nregister read access and the USART_DR read access).\nSelecting the proper oversampling method\nThe receiver implements different user-configurable oversampling techniques (except in \nsynchronous mode) for data recovery by discriminating between valid incoming data and \nnoise.\nThe oversampling method can be selected by programming the OVER8 bit in the \nUSART_CR1 register and can be either 16 or 8 times the baud rate clock (Figure 301 and \nFigure 302).\nDepending on the application:\n•\nselect oversampling by 8 (OVER8=1) to achieve higher speed (up to fPCLK/8). In this \ncase the maximum receiver tolerance to clock deviation is reduced (refer to \nSection 30.3.5: USART receiver tolerance to clock deviation on page 991)\n•\nselect oversampling by 16 (OVER8=0) to increase the tolerance of the receiver to clock \ndeviations. In this case, the maximum speed is limited to maximum fPCLK/16\n\n\n<>\n\nRM0090 Rev 21\n979/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nProgramming the ONEBIT bit in the USART_CR3 register selects the method used to \nevaluate the logic level. There are two options:\n•\nthe majority vote of the three samples in the center of the received bit. In this case, \nwhen the 3 samples used for the majority vote are not equal, the NF bit is set\n•\na single sample in the center of the received bit\nDepending on the application:\n–\nselect the three samples’ majority vote method (ONEBIT=0) when operating in a \nnoisy environment and reject the data when a noise is detected (refer to \nFigure 134) because this indicates that a glitch occurred during the sampling.\n–\nselect the single sample method (ONEBIT=1) when the line is noise-free to \nincrease the receiver’s tolerance to clock deviations (see Section 30.3.5: USART \nreceiver tolerance to clock deviation on page 991). In this case the NF bit is never \nset.\nWhen noise is detected in a frame:\n•\nThe NF bit is set at the rising edge of the RXNE bit.\n•\nThe invalid data is transferred from the Shift register to the USART_DR register.\n•\nNo interrupt is generated in case of single byte communication. However this bit rises \nat the same time as the RXNE bit which itself generates an interrupt. In case of \nmultibuffer communication an interrupt is issued if the EIE bit is set in the USART_CR3 \nregister.\nThe NF bit is reset by a USART_SR register read operation followed by a USART_DR \nregister read operation.\nNote:\nOversampling by 8 is not available in the Smartcard, IrDA and LIN modes. In those modes, \nthe OVER8 bit is forced to ‘0 by hardware.\nFigure 301. Data sampling when oversampling by 16\nMSv31152V1\n1\n2\n3\n4\n5\n6\n7\n8\n9\n10\n11\n12\n13\n14\n15\n16\nsampled values\n6/16\n7/16\n7/16\nOne bit time\nSample clock\nRX line\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n980/1757\nRM0090 Rev 21\nFigure 302. Data sampling when oversampling by 8\n \nFraming error\nA framing error is detected when:\nThe stop bit is not recognized on reception at the expected time, following either a de-\nsynchronization or excessive noise. \nWhen the framing error is detected:\n•\nThe FE bit is set by hardware\n•\nThe invalid data is transferred from the Shift register to the USART_DR register.\n•\nNo interrupt is generated in case of single byte communication. However this bit rises \nat the same time as the RXNE bit which itself generates an interrupt. In case of \nmultibuffer communication an interrupt isissued if the EIE bit is set in the USART_CR3 \nregister.\nThe FE bit is reset by a USART_SR register read operation followed by a USART_DR \nregister read operation.\nTable 134. Noise detection from sampled data\nSampled value\nNE status\nReceived bit value\n000\n0\n0\n001\n1\n0\n010\n1\n0\n011\n1\n1\n100\n1\n0\n101\n1\n1\n110\n1\n1\n111\n0\n1\nMSv31153V1\n1\n2\n3\n4\n5\n6\n7\nsampled values\n2/8\n3/8\n3/8\nOne bit time\nSample \nclock (x8)\nRX line\n8\n\n\n<>\n\nRM0090 Rev 21\n981/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nConfigurable stop bits during reception\nThe number of stop bits to be received can be configured through the control bits of Control \nRegister 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 in Smartcard mode.\n1.\n0.5 stop bit (reception in Smartcard mode): No sampling is done for 0.5 stop bit. As \na consequence, no framing error and no break frame can be detected when 0.5 stop bit \nis selected.\n2. \n1 stop bit: Sampling for 1 stop Bit is done on the 8th, 9th and 10th samples.\n3. \n1.5 stop bits (Smartcard mode): When transmitting in smartcard mode, the device \nmust check that the data is correctly sent. Thus the receiver block must be enabled (RE \n=1 in the USART_CR1 register) and the stop bit is checked to test if the smartcard has \ndetected a parity error. In the event of a parity error, the smartcard forces the data \nsignal low during the sampling - NACK signal-, which is flagged as a framing error. \nThen, the FE flag is set with the RXNE at the end of the 1.5 stop bit. Sampling for 1.5 \nstop bits is done on the 16th, 17th and 18th samples (1 baud clock period after the \nbeginning of the stop bit). The 1.5 stop bit can be decomposed into 2 parts: one 0.5 \nbaud clock period during which nothing happens, followed by 1 normal stop bit period \nduring which sampling occurs halfway through. Refer to Section 30.3.11: Smartcard on \npage 1000 for more details.\n4. \n2 stop bits: Sampling for 2 stop bits is done on the 8th, 9th and 10th samples of the \nfirst stop bit. If a framing error is detected during the first stop bit the framing error flag \nis set. The second stop bit is not checked for framing error. The RXNE flag is set at the \nend of the first stop bit.\n30.3.4 \nFractional baud rate generation\nThe baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as \nprogrammed in the Mantissa and Fraction values of USARTDIV.\nEquation 1: Baud rate for standard USART (SPI mode included)\nEquation 2: Baud rate in Smartcard, LIN and IrDA modes\nUSARTDIV is an unsigned fixed point number that is coded on the USART_BRR register.\n•\nWhen OVER8=0, the fractional part is coded on 4 bits and programmed by the \nDIV_fraction[3:0] bits in the USART_BRR register\n•\nWhen OVER8=1, the fractional part is coded on 3 bits and programmed by the \nDIV_fraction[2:0] bits in the USART_BRR register, and bit DIV_fraction[3] must be kept \ncleared.\nNote:\nThe baud counters are updated to the new value in the baud registers after a write operation \nto USART_BRR. Hence the baud rate register value should not be changed during \ncommunication.\nTx/Rx baud\nfCK\n8\n2\nOVER8\n–\n(\n)\nUSARTDIV\n×\n×\n------------------------------------------------------------------------------------\n=\nTx/Rx baud\nfCK\n16\nUSARTDIV\n×\n----------------------------------------------\n=\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n982/1757\nRM0090 Rev 21\nHow to derive USARTDIV from USART_BRR register values when OVER8=0\nExample 1:\nIf DIV_Mantissa = 0d27 and DIV_Fraction = 0d12 (USART_BRR = 0x1BC), then\nMantissa (USARTDIV) = 0d27\nFraction (USARTDIV) = 12/16 = 0d0.75\nTherefore USARTDIV = 0d27.75\nExample 2:\nTo program USARTDIV = 0d25.62\nThis leads to:\nDIV_Fraction = 16*0d0.62 = 0d9.92\nThe nearest real number is 0d10 = 0xA\nDIV_Mantissa = mantissa (0d25.620) = 0d25 = 0x19\nThen, USART_BRR = 0x19A hence USARTDIV = 0d25.625\nExample 3: \nTo program USARTDIV = 0d50.99\nThis leads to:\nDIV_Fraction = 16*0d0.99 = 0d15.84\nThe nearest real number is 0d16 = 0x10 => overflow of DIV_frac[3:0] => carry must be \nadded up to the mantissa\nDIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33\nThen, USART_BRR = 0x330 hence USARTDIV = 0d51.000\nHow to derive USARTDIV from USART_BRR register values when OVER8=1\nExample 1:\nIf DIV_Mantissa = 0x27 and DIV_Fraction[2:0]= 0d6 (USART_BRR = 0x1B6), then\nMantissa (USARTDIV) = 0d27\nFraction (USARTDIV) = 6/8 = 0d0.75\nTherefore USARTDIV = 0d27.75\nExample 2: \nTo program USARTDIV = 0d25.62\nThis leads to:\nDIV_Fraction = 8*0d0.62 = 0d4.96\nThe nearest real number is 0d5 = 0x5\nDIV_Mantissa = mantissa (0d25.620) = 0d25 = 0x19\n\n\n<>\n\nRM0090 Rev 21\n983/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nThen, USART_BRR = 0x195 => USARTDIV = 0d25.625\nExample 3: \nTo program USARTDIV = 0d50.99\nThis leads to:\nDIV_Fraction = 8*0d0.99 = 0d7.92\nThe nearest real number is 0d8 = 0x8 => overflow of the DIV_frac[2:0] => carry must be \nadded up to the mantissa\nDIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33\nThen, USART_BRR = 0x0330 => USARTDIV = 0d51.000\n \nTable 135. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 12 MHz,\noversampling by 16(1)\nOversampling by 16 (OVER8=0)\nBaud rate7\nfPCLK = 8 MHz\nfPCLK = 12 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired) B.rate / \nDesired B.rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error\n1\n1.2 KBps\n1.2 KBps\n416.6875\n0\n1.2 KBps\n625\n0\n2\n2.4 KBps\n2.4 KBps\n208.3125\n0.01\n2.4 KBps\n312.5\n0\n3\n9.6 KBps\n9.604 KBps\n52.0625\n0.04\n9.6 KBps\n78.125\n0\n4\n19.2 KBps\n19.185 KBps\n26.0625\n0.08\n19.2 KBps\n39.0625\n0\n5\n38.4 KBps\n38.462 KBps\n13\n0.16\n38.339 KBps\n19.5625\n0.16\n6\n57.6 KBps\n57.554 KBps\n8.6875\n0.08\n57.692 KBps\n13\n0.16\n7\n115.2 KBps\n115.942 KBps\n4.3125\n0.64\n115.385 KBps\n6.5\n0.16\n8\n230.4 KBps\n228.571 KBps\n2.1875\n0.79\n230.769 KBps\n3.25\n0.16\n9\n460.8 KBps\n470.588 KBps\n1.0625\n2.12\n461.538 KBps\n1.625\n0.16\n10\n921.6 KBps\nNA\nNA\nNA\nNA\nNA\nNA\n11\n2 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n12\n3 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n984/1757\nRM0090 Rev 21\n \n \nTable 136. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK =12 MHz,\noversampling by 8(1)\nOversampling by 8 (OVER8 = 1)\nBaud rate\nfPCLK = 8 MHz\nfPCLK = 12 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired) \nB.rate / \nDesired \nB.rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error\n1\n1.2 KBps\n1.2 KBps\n833.375\n0\n1.2 KBps\n1250\n0\n2\n2.4 KBps\n2.4 KBps\n416.625\n0.01\n2.4 KBps\n625\n0\n3\n9.6 KBps\n9.604 KBps\n104.125\n0.04\n9.6 KBps\n156.25\n0\n4\n19.2 KBps\n19.185 KBps\n52.125\n0.08\n19.2 KBps\n78.125\n0\n5\n38.4 KBps\n38.462 KBps\n26\n0.16\n38.339 KBps\n39.125\n0.16\n6\n57.6 KBps\n57.554 KBps\n17.375\n0.08\n57.692 KBps\n26\n0.16\n7\n115.2 KBps\n115.942 KBps\n8.625\n0.64\n115.385 KBps\n13\n0.16\n8\n230.4 KBps\n228.571 KBps\n4.375\n0.79\n230.769 KBps\n6.5\n0.16\n9\n460.8 KBps\n470.588 KBps\n2.125\n2.12\n461.538 KBps\n3.25\n0.16\n10\n921.6 KBps\n888.889 KBps\n1.125\n3.55\n923.077 KBps\n1.625\n0.16\n11\n2 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n12\n3 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\nTable 137. Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz,\noversampling by 16(1)\nOversampling by 16 (OVER8 = 0)\nBaud rate\nfPCLK = 16 MHz\nfPCLK = 24 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired) B.rate / \nDesired B.rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error\n1\n1.2 KBps\n1.2 KBps\n833.3125\n0\n1.2\n1250\n0\n2\n2.4 KBps\n2.4 KBps\n416.6875\n0\n2.4\n625\n0\n3\n9.6 KBps\n9.598 KBps\n104.1875\n0.02\n9.6\n156.25\n0\n4\n19.2 KBps\n19.208 KBps\n52.0625\n0.04\n19.2\n78.125\n0\n5\n38.4 KBps\n38.369 KBps\n26.0625\n0.08\n38.4\n39.0625\n0\n6\n57.6 KBps\n57.554 KBps\n17.375\n0.08\n57.554\n26.0625\n0.08\n\n\n<>\n\nRM0090 Rev 21\n985/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n \n7\n115.2 KBps\n115.108 KBps\n8.6875\n0.08\n115.385\n13\n0.16\n8\n230.4 KBps\n231.884 KBps\n4.3125\n0.64\n230.769\n6.5\n0.16\n9\n460.8 KBps\n457.143 KBps\n2.1875\n0.79\n461.538\n3.25\n0.16\n10\n921.6 KBps\n941.176 KBps\n1.0625\n2.12\n923.077\n1.625\n0.16\n11\n2 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n12\n3 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\nTable 137. Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz,\noversampling by 16(1) (continued)\nOversampling by 16 (OVER8 = 0)\nBaud rate\nfPCLK = 16 MHz\nfPCLK = 24 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired) B.rate / \nDesired B.rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error\nTable 138. Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz,\noversampling by 8(1)\nOversampling by 8 (OVER8=1)\nBaud rate\nfPCLK = 16 MHz\nfPCLK = 24 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired) B.rate / \nDesired B.rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error\n1\n1.2 KBps\n1.2 KBps\n1666.625\n0\n1.2 KBps\n2500\n0\n2\n2.4 KBps\n2.4 KBps\n833.375\n0\n2.4 KBps\n1250\n0\n3\n9.6 KBps\n9.598 KBps\n208.375\n0.02\n9.6 KBps\n312.5\n0\n4\n19.2 KBps\n19.208 KBps\n104.125\n0.04\n19.2 KBps\n156.25\n0\n5\n38.4 KBps\n38.369 KBps\n52.125\n0.08\n38.4 KBps\n78.125\n0\n6\n57.6 KBps\n57.554 KBps\n34.75\n0.08\n57.554 KBps\n52.125\n0.08\n7\n115.2 KBps\n115.108 KBps\n17.375\n0.08\n115.385 KBps\n26\n0.16\n8\n230.4 KBps\n231.884 KBps\n8.625\n0.64\n230.769 KBps\n13\n0.16\n9\n460.8 KBps\n457.143 KBps\n4.375\n0.79\n461.538 KBps\n6.5\n0.16\n10\n921.6 KBps\n941.176 KBps\n2.125\n2.12\n923.077 KBps\n3.25\n0.16\n11\n2 MBps\n2000 KBps\n1\n0\n2000 KBps\n1.5\n0\n12\n3 MBps\nNA\nNA\nNA\n3000 KBps\n1\n0\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n986/1757\nRM0090 Rev 21\n \nTable 139. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,\noversampling by 16(1)\nOversampling by 16 (OVER8=0)\nBaud rate\nfPCLK = 8 MHz\nfPCLK = 16 MHz\nS.No\nDesired\nActual\nValue \nprogramme\nd in the \nbaud rate \nregister\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error\n1.\n2.4 KBps\n2.400 KBps\n208.3125\n0.00%\n2.400 KBps\n416.6875\n0.00%\n2.\n9.6 KBps\n9.604 KBps\n52.0625\n0.04%\n9.598 KBps\n104.1875\n0.02%\n3.\n19.2 KBps\n19.185 KBps\n26.0625\n0.08%\n19.208 KBps\n52.0625\n0.04%\n4.\n57.6 KBps\n57.554 KBps\n8.6875\n0.08%\n57.554 KBps\n17.3750\n0.08%\n5.\n115.2 KBps\n115.942 KBps 4.3125\n0.64%\n115.108 KBps\n8.6875\n0.08%\n6.\n230.4 KBps\n228.571 \nKBps\n2.1875\n0.79%\n231.884 KBps\n4.3125\n0.64%\n7.\n460.8 KBps\n470.588 \nKBps\n1.0625\n2.12%\n457.143 KBps\n2.1875\n0.79%\n8.\n896 KBps\nNA\nNA\nNA\n888.889 KBps\n1.1250\n0.79%\n9.\n921.6 KBps\nNA\nNA\nNA\n941.176 KBps\n1.0625\n2.12%\n10.\n1.792 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n11.\n1.8432 MBps NA\nNA\nNA\nNA\nNA\nNA\n12.\n3.584 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n13.\n3.6864 MBps NA\nNA\nNA\nNA\nNA\nNA\n14.\n7.168 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n15.\n7.3728 MBps NA\nNA\nNA\nNA\nNA\nNA\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\nTable 140. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,\noversampling by 8(1)\nOversampling by 8 (OVER8=1)\nBaud rate\nfPCLK = 8 MHz\nfPCLK = 16 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\n1.\n2.4 KBps\n2.400 KBps\n416.625\n0.01%\n2.400 KBps\n833.375\n0.00%\n2.\n9.6 KBps\n9.604 KBps\n104.125\n0.04%\n9.598 KBps\n208.375\n0.02%\n3.\n19.2 KBps\n19.185 KBps\n52.125\n0.08%\n19.208 KBps\n104.125\n0.04%\n\n\n<>\n\nRM0090 Rev 21\n987/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n \n4.\n57.6 KBps\n57.557 KBps\n17.375\n0.08%\n57.554 KBps\n34.750\n0.08%\n5.\n115.2 KBps\n115.942 KBps\n8.625\n0.64%\n115.108 KBps\n17.375\n0.08%\n6.\n230.4 KBps\n228.571 KBps\n4.375\n0.79%\n231.884 KBps\n8.625\n0.64%\n7.\n460.8 KBps\n470.588 KBps\n2.125\n2.12%\n457.143 KBps\n4.375\n0.79%\n8.\n896 KBps\n888.889 KBps\n1.125\n0.79%\n888.889 KBps\n2.250\n0.79%\n9.\n921.6 KBps\n888.889 KBps\n1.125\n3.55%\n941.176 KBps\n2.125\n2.12%\n10.\n1.792 MBps\nNA\nNA\nNA\n1.7777 MBps\n1.125\n0.79%\n11.\n1.8432 MBps\nNA\nNA\nNA\n1.7777 MBps\n1.125\n3.55%\n12.\n3.584 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n13.\n3.6864 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n14.\n7.168 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n15.\n7.3728 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\nTable 140. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,\noversampling by 8(1) (continued)\nOversampling by 8 (OVER8=1)\nBaud rate\nfPCLK = 8 MHz\nfPCLK = 16 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\nTable 141. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,\noversampling by 16(1)(2)\nOversampling by 16 (OVER8=0)\nBaud rate\nfPCLK = 30 MHz\nfPCLK = 60 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\n1.\n2.4 KBps\n2.400 KBps\n781.2500\n0.00%\n2.400 KBps\n1562.5000\n0.00%\n2.\n9.6 KBps\n9.600 KBps\n195.3125\n0.00%\n9.600 KBps\n390.6250\n0.00%\n3.\n19.2 KBps\n19.194 KBps\n97.6875\n0.03%\n19.200 KBps\n195.3125\n0.00%\n4.\n57.6 KBps\n57.582KBps\n32.5625\n0.03%\n57.582 KBps\n65.1250\n0.03%\n5.\n115.2 KBps\n115.385 KBps\n16.2500\n0.16%\n115.163 KBps\n32.5625\n0.03%\n6.\n230.4 KBps\n230.769 KBps\n8.1250\n0.16%\n230.769KBps\n16.2500\n0.16%\n7.\n460.8 KBps\n461.538 KBps\n4.0625\n0.16%\n461.538 KBps 8.1250\n0.16%\n8.\n896 KBps\n909.091 KBps\n2.0625\n1.46%\n895.522 KBps 4.1875\n0.05%\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n988/1757\nRM0090 Rev 21\n \n9.\n921.6 KBps\n909.091 KBps\n2.0625\n1.36%\n923.077 KBps 4.0625\n0.16%\n10.\n1.792 MBps\n1.1764 MBps\n1.0625\n1.52%\n1.8182 MBps\n2.0625\n1.36%\n11.\n1.8432 \nMBps\n1.8750 MBps\n1.0000\n1.73%\n1.8182 MBps\n2.0625\n1.52%\n12.\n3.584 MBps\nNA\nNA\nNA\n3.2594 MBps\n1.0625\n1.52%\n13.\n3.6864 \nMBps\nNA\nNA\nNA\n3.7500 MBps\n1.0000\n1.73%\n14.\n7.168 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n15.\n7.3728 \nMBps\nNA\nNA\nNA\nNA\nNA\nNA\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\n2.\nOnly USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device \ndatasheets for the maximum values for PCLK1 and PCLK2.\nTable 141. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,\noversampling by 16(1)(2) (continued)\nOversampling by 16 (OVER8=0)\nBaud rate\nfPCLK = 30 MHz\nfPCLK = 60 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\nTable 142. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,\noversampling by 8(1) (2)\nOversampling by 8 (OVER8=1)\nBaud rate\nfPCLK = 30 MHz\nfPCLK =60 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\n1.\n2.4 KBps\n2.400 KBps\n1562.5000\n0.00%\n2.400 KBps\n3125.0000\n0.00%\n2.\n9.6 KBps\n9.600 KBps\n390.6250\n0.00%\n9.600 KBps\n781.2500\n0.00%\n3.\n19.2 KBps\n19.194 KBps\n195.3750\n0.03%\n19.200 KBps\n390.6250\n0.00%\n4.\n57.6 KBps\n57.582 KBps\n65.1250\n0.16%\n57.582 KBps\n130.2500\n0.03%\n5.\n115.2 KBps\n115.385 KBps\n32.5000\n0.16%\n115.163 KBps\n65.1250\n0.03%\n6.\n230.4 KBps\n230.769 KBps\n16.2500\n0.16%\n230.769 KBps\n32.5000\n0.16%\n7.\n460.8 KBps\n461.538 KBps\n8.1250\n0.16%\n461.538 KBps\n16.2500\n0.16%\n8.\n896 KBps\n909.091 KBps\n4.1250\n1.46%\n895.522 KBps\n8.3750\n0.05%\n9.\n921.6 KBps\n909.091 KBps\n4.1250\n1.36%\n923.077 KBps\n8.1250\n0.16%\n10.\n1.792 MBps\n1.7647 MBps\n2.1250\n1.52%\n1.8182 MBps\n4.1250\n1.46%\n\n\n<>\n\nRM0090 Rev 21\n989/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n \n11.\n1.8432 MBps\n1.8750 MBps\n2.0000\n1.73%\n1.8182 MBps\n4.1250\n1.36%\n12.\n3.584 MBps\n3.7500 MBps\n1.0000\n4.63%\n3.5294 MBps\n2.1250\n1.52%\n13.\n3.6864 MBps\n3.7500 MBps\n1.0000\n1.73%\n3.7500 MBps\n2.0000\n1.73%\n14.\n7.168 MBps\nNA\nNA\nNA\n7.5000 MBps\n1.0000\n4.63%\n15.\n7.3728 MBps\nNA\nNA\nNA\n7.5000 MBps\n1.0000\n1.73%\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\n2.\nOnly USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device \ndatasheets for the maximum values for PCLK1 and PCLK2.\nTable 142. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,\noversampling by 8(1) (2) (continued)\nOversampling by 8 (OVER8=1)\nBaud rate\nfPCLK = 30 MHz\nfPCLK =60 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\nTable 143. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 Hz,\noversampling by 16(1)(2)\nOversampling by 16 (OVER8=0)\nBaud rate\nfPCLK = 42 MHz\nfPCLK = 84 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\n1.\n1.2 KBps\n1.2 KBps\n2187.5\n0\n1.2 KBps\nNA\n0\n2.\n2.4 KBps\n2.4 KBps\n1093.75\n0\n2.4 KBps\n2187.5\n0\n3.\n9.6 KBps\n9.6 KBps\n273.4375\n0\n9.6 KBps\n546.875\n0\n4.\n19.2 KBps\n19.195 KBps\n136.75\n0.02\n19.2 KBps\n273.4375\n0\n5.\n38.4 KBps\n38.391 KBps\n68.375\n0.02\n38.391 KBps\n136.75\n0.02\n6.\n57.6 KBps\n57.613 KBps\n45.5625\n0.02\n57.613 KBps\n91.125\n0.02\n7.\n115.2 KBps\n115.068 KBps\n22.8125\n0.11\n115.226 KBps\n45.5625\n0.02\n8.\n230.4 KBps\n230.769 KBps\n11.375\n0.16\n230.137 KBps 22.8125\n0.11\n9.\n460.8 KBps\n461.538 KBps\n5.6875\n0.16\n461.538 KBps 11.375\n0.16\n10.\n921.6 KBps\n913.043 KBps\n2.875\n0.93\n923.076 KBps 5.6875\n0.93\n11.\n1.792 MBps\n1.826 MBps\n1.4375\n1.9\n1.787 MBps\n2.9375\n0.27\n12.\n1.8432 MBps 1.826 MBps\n1.4375\n0.93\n1.826 MBps\n2.875\n0.93\n13.\n3.584 MBps\nN.A\nN.A\nN.A\n3.652 MBps\n1.4375\n1.9\n14.\n3.6864 MBps N.A\nN.A\nN.A\n3.652 MBps\n1.4375\n0.93\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n990/1757\nRM0090 Rev 21\n \n15.\n7.168 MBps\nN.A\nN.A\nN.A\nN.A\nN.A\nN.A\n16.\n7.3728 MBps N.A\nN.A\nN.A\nN.A\nN.A\nN.A\n17.\n9 MBps\nN.A\nN.A\nN.A\nN.A\nN.A\nN.A\n18.\n10.5 MBps\nN.A\nN.A\nN.A\nN.A\nN.A\nN.A\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can be \nfixed with these data.\n2.\nOnly USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device \ndatasheets for the maximum values for PCLK1 and PCLK2.\nTable 143. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 Hz,\noversampling by 16(1)(2) (continued)\nOversampling by 16 (OVER8=0)\nBaud rate\nfPCLK = 42 MHz\nfPCLK = 84 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\nTable 144. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 MHz,\noversampling by 8(1)(2)\nOversampling by 8 (OVER8=1)\nBaud rate\nfPCLK = 42 MHz\nfPCLK = 84 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\nValue \nprogrammed \nin the baud \nrate register\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\n1.\n2.4 KBps\n2.4 KBps\n2187.5\n0\n2.4 KBps\nNA\n0\n2.\n9.6 KBps\n9.6 KBps\n546.875\n0\n9.6 KBps\n1093.75\n0\n3.\n19.2 KBps\n19.195 KBps\n273.5\n0.02\n19.2 KBps\n546.875\n0\n4.\n38.4 KBps\n38.391 KBps\n136.75\n0.02\n38.391 KBps\n273.5\n0.02\n5.\n57.6 KBps\n57.613 KBps\n91.125\n0.02\n57.613 KBps\n182.25\n0.02\n6.\n115.2 KBps\n115.068 KBps\n45.625\n0.11\n115.226 KBps\n91.125\n0.02\n7.\n230.4 KBps\n230.769 KBps\n22.75\n0.11\n230.137 KBps\n45.625\n0.11\n8.\n460.8 KBps\n461.538 KBps\n11.375\n0.16\n461.538 KBps\n22.75\n0.16\n9.\n921.6 KBps\n913.043 KBps\n5.75\n0.93\n923.076 KBps\n11.375\n0.93\n10.\n1.792 MBps\n1.826 MBps\n2.875\n1.9\n1.787Mbps\n5.875\n0.27\n11.\n1.8432 MBps\n1.826 MBps\n2.875\n0.93\n1.826 MBps\n5.75\n0.93\n12.\n3.584 MBps\n3.5 MBps\n1.5\n2.34\n3.652 MBps\n2.875\n1.9\n13.\n3.6864 MBps\n3.82 MBps\n1.375\n3.57\n3.652 MBps\n2.875\n0.93\n14.\n7.168 MBps\nN.A\nN.A\nN.A\n7 MBps\n1.5\n2.34\n15.\n7.3728 MBps\nN.A\nN.A\nN.A\n7.636 MBps\n1.375\n3.57\n\n\n<>\n\nRM0090 Rev 21\n991/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n30.3.5 \nUSART receiver tolerance to clock deviation\nThe USART asynchronous receiver works correctly only if the total clock system deviation is \nsmaller than the USART receiver’s tolerance. The causes which contribute to the total \ndeviation are:\n•\nDTRA: Deviation due to the transmitter error (which also includes the deviation of the \ntransmitter’s local oscillator)\n•\nDQUANT: Error due to the baud rate quantization of the receiver\n•\nDREC: Deviation of the receiver’s local oscillator\n•\nDTCL: Deviation due to the transmission line (generally due to the transceivers which \ncan introduce an asymmetry between the low-to-high transition timing and the high-to-\nlow transition timing)\nDTRA + DQUANT + DREC + DTCL < USART receiver’s tolerance\nThe USART receiver’s tolerance to properly receive data is equal to the maximum tolerated \ndeviation and depends on the following choices:\n•\n10- or 11-bit character length defined by the M bit in the USART_CR1 register\n•\noversampling by 8 or 16 defined by the OVER8 bit in the USART_CR1 register\n•\nuse of fractional baud rate or not\n•\nuse of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in \nthe USART_CR3 register\n \n16.\n9 MBps\nN.A\nN.A\nN.A\n9.333 MBps\n1.125\n3.7\n17.\n10.5 MBps\nN.A\nN.A\nN.A\n10.5 MBps\n1\n0\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\n2.\nOnly USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device \ndatasheets for the maximum values for PCLK1 and PCLK2.\nTable 144. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 MHz,\noversampling by 8(1)(2) (continued)\nOversampling by 8 (OVER8=1)\nBaud rate\nfPCLK = 42 MHz\nfPCLK = 84 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\nValue \nprogrammed \nin the baud \nrate register\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\nTable 145. USART receiver’s tolerance when DIV fraction is 0\nM bit\nOVER8 bit = 0\nOVER8 bit = 1\nONEBIT=0\nONEBIT=1\nONEBIT=0\nONEBIT=1\n0\n3.75%\n4.375%\n2.50%\n3.75%\n1\n3.41%\n3.97%\n2.27%\n3.41%\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n992/1757\nRM0090 Rev 21\n \nNote:\nThe figures specified in Table 145 and Table 146 may slightly differ in the special case when \nthe received frames contain some Idle frames of exactly 10-bit times when M=0 (11-bit times \nwhen M=1).\n30.3.6 \nMultiprocessor communication\nThere is a possibility of performing multiprocessor communication with the USART (several \nUSARTs connected in a network). For instance one of the USARTs can be the master, its TX \noutput is connected to the RX input of the other USART. The others are slaves, their \nrespective TX outputs are logically ANDed together and connected to the RX input of the \nmaster.\nIn multiprocessor configurations it is often desirable that only the intended message \nrecipient should actively receive the full message contents, thus reducing redundant USART \nservice overhead for all non addressed receivers.\nThe non addressed devices may be placed in mute mode by means of the muting function. \nIn mute mode:\n•\nNone of the reception status bits can be set.\n•\nAll the receive interrupts are inhibited.\n•\nThe RWU bit in USART_CR1 register is set to 1. RWU can be controlled automatically \nby hardware or written by the software under certain conditions.\nThe USART can enter or exit from mute mode using one of two methods, depending on the \nWAKE bit in the USART_CR1 register:\n•\nIdle Line detection if the WAKE bit is reset,\n•\nAddress Mark detection if the WAKE bit is set.\nIdle line detection (WAKE=0)\nThe USART enters mute mode when the RWU bit is written to 1.\nIt wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but \nthe IDLE bit is not set in the USART_SR register. RWU can also be written to 0 by software.\nAn example of mute mode behavior using Idle line detection is given in Figure 303.\nTable 146. USART receiver tolerance when DIV_Fraction is different from 0\nM bit\nOVER8 bit = 0\nOVER8 bit = 1\nONEBIT=0\nONEBIT=1\nONEBIT=0\nONEBIT=1\n0\n3.33%\n3.88%\n2%\n3%\n1\n3.03%\n3.53%\n1.82%\n2.73%\n\n\n<>\n\nRM0090 Rev 21\n993/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nFigure 303. Mute mode using Idle line detection\nAddress mark detection (WAKE=1)\nIn this mode, bytes are recognized as addresses if their MSB is a ‘1 else they are \nconsidered as data. In an address byte, the address of the targeted receiver is put on the 4 \nLSB. This 4-bit word is compared by the receiver with its own address which is programmed \nin the ADD bits in the USART_CR2 register.\nThe USART enters mute mode when an address character is received which does not \nmatch its programmed address. In this case, the RWU bit is set by hardware. The RXNE \nflag is not set for this address byte and no interrupt nor DMA request is issued as the \nUSART would have entered mute mode.\nIt exits from mute mode when an address character is received which matches the \nprogrammed address. Then the RWU bit is cleared and subsequent bytes are received \nnormally. The RXNE bit is set for the address character since the RWU bit has been \ncleared.\nThe RWU bit can be written to as 0 or 1 when the receiver buffer contains no data (RXNE=0 \nin the USART_SR register). Otherwise the write attempt is ignored.\nAn example of mute mode behavior using address mark detection is given in Figure 304.\nFigure 304. Mute mode using address mark detection\nMSv40881V1\nData 1 Data 2\nIDLE\nData 3 Data 4\nData 6\nIdle frame detected\nRWU written to 1\nRWU\nRX\nMute mode\nNormal mode\nRXNE\nRXNE\nData 5\nMSv40882V1\nIDLE\nAddr=0 Data 1 Data 2\nIDLE\nAddr=1 Data 3 Data 4 Addr=2 Data 5\nIn this example, the current address of the receiver is 1 \n(programmed in the USART_CR2 register)\nRXNE\nNon-matching address\nMatching address\nNon-matching address\nRWU written to 1\n(RXNE was cleared)\nRWU\nRX\nMute mode\nMute mode\nNormal mode\nRXNE\nRXNE\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n994/1757\nRM0090 Rev 21\n30.3.7 \nParity control\nParity control (generation of parity bit in transmission and parity checking in reception) can \nbe enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame \nlength defined by the M bit, the possible USART frame formats are as listed in Table 147.\n \nEven parity\nThe parity bit is calculated to obtain an even number of “1s” inside the frame made of the 7 \nor 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.\nE.g.: data=00110101; 4 bits set => parity bit is 0 if even parity is selected (PS bit in \nUSART_CR1 = 0).\nOdd parity\nThe parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or \n8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.\nE.g.: data=00110101; 4 bits set => parity bit is 1 if odd parity is selected (PS bit in \nUSART_CR1 = 1).\nParity checking in reception\nIf the parity check fails, the PE flag is set in the USART_SR register and an interrupt is \ngenerated if PEIE is set in the USART_CR1 register. The PE flag is cleared by a software \nsequence (a read from the status register followed by a read or write access to the \nUSART_DR data register).\nNote:\nIn case of wake-up by an address mark: the MSB bit of the data is taken into account to \nidentify an address but not the parity bit. And the receiver does not check the parity of the \naddress data (PE is not set in case of a parity error).\nParity generation in transmission\nIf the PCE bit is set in USART_CR1, then the MSB bit of the data written in the data register \nis transmitted but is changed by the parity bit (even number of “1s” if even parity is selected \n(PS=0) or an odd number of “1s” if odd parity is selected (PS=1)).\nNote:\nThe software routine that manages the transmission can activate the software sequence \nwhich clears the PE flag (a read from the status register followed by a read or write access \nto the data register). When operating in half-duplex mode, depending on the software, this \ncan cause the PE flag to be unexpectedly cleared.\nTable 147. Frame formats\nM bit\nPCE bit \nUSART frame(1)\n1.\nLegends: SB: start bit, STB: stop bit, PB: parity bit.\n0\n0\n| SB | 8 bit data | STB |\n0\n1\n| SB | 7-bit data | PB | STB |\n1\n0\n| SB | 9-bit data | STB |\n1\n1\n| SB | 8-bit data PB | STB |\n\n\n<>\n\nRM0090 Rev 21\n995/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n30.3.8 \nLIN (local interconnection network) mode\nThe LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN \nmode, the following bits must be kept cleared:\n•\nSTOP[1:0] and CLKEN in the USART_CR2 register\n•\nSCEN, HDSEL and IREN in the USART_CR3 register.\nLIN transmission\nThe same procedure explained in Section 30.3.2 has to be applied for LIN Master \ntransmission than for normal USART transmission with the following differences:\n•\nClear the M bit to configure 8-bit word length.\n•\nSet the LINEN bit to enter LIN mode. In this case, setting the SBK bit sends 13 ‘0 bits \nas a break character. Then a bit of value ‘1 is sent to allow the next start detection.\nLIN reception\nA break detection circuit is implemented on the USART interface. The detection is totally \nindependent from the normal USART receiver. A break can be detected whenever it occurs, \nduring Idle state or during a frame.\nWhen the receiver is enabled (RE=1 in USART_CR1), the circuit looks at the RX input for a \nstart signal. The method for detecting start bits is the same when searching break \ncharacters or data. After a start bit has been detected, the circuit samples the next bits \nexactly like for the data (on the 8th, 9th and 10th samples). If 10 (when the LBDL = 0 in \nUSART_CR2) or 11 (when LBDL=1 in USART_CR2) consecutive bits are detected as ‘0, \nand are followed by a delimiter character, the LBD flag is set in USART_SR. If the LBDIE \nbit=1, an interrupt is generated. Before validating the break, the delimiter is checked for as it \nsignifies that the RX line has returned to a high level.\nIf a ‘1 is sampled before the 10 or 11 have occurred, the break detection circuit cancels the \ncurrent detection and searches for a start bit again. \nIf the LIN mode is disabled (LINEN=0), the receiver continues working as normal USART, \nwithout taking into account the break detection.\nIf the LIN mode is enabled (LINEN=1), as soon as a framing error occurs (stop bit detected \nat ‘0, which is the case for any break frame), the receiver stops until the break detection \ncircuit receives either a ‘1, if the break word was not complete, or a delimiter character if a \nbreak has been detected.\nThe behavior of the break detector state machine and the break flag is shown on the \nFigure 305: Break detection in LIN mode (11-bit break length - LBDL bit is set) on page 996.\nExamples of break frames are given on Figure 306: Break detection in LIN mode vs. \nFraming error detection on page 997.\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n996/1757\nRM0090 Rev 21\nFigure 305. Break detection in LIN mode (11-bit break length - LBDL bit is set)\nMSv40883V1\nIdle\nBit0\nBit1\nBit2 Bit3\nBit4\nBit5 Bit6\nBit7\nBit8\nBit9 Bit10\nIdle\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\nCase 1: break signal not long enough => break discarded, LBD is not set\nRX line\nCapture strobe\nBreak state \nmachine\nRead samples\nIdle\nBit0\nBit1\nBit2 Bit3\nBit4\nBit5 Bit6\nBit7\nBit8\nBit9 B10\nIdle\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nCase 2: break signal just long enough => break detected, LBD is set\nRX line\nCapture strobe\nBreak state \nmachine\nRead samples\nBreak frame\nBreak frame\nDelimiter is immediate\nLBD\nIdle\nBit0\nBit1\nBit2 Bit3\nBit4\nBit5 Bit6\nBit7\nBit8\nBit9 Bit10\nIdle\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nCase 3: break signal long enough => break detected, LBD is set\nRX line\nCapture strobe\nBreak state \nmachine\nRead samples\nBreak frame\nLBD\nwait delimiter\n\n\n<>\n\nRM0090 Rev 21\n997/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nFigure 306. Break detection in LIN mode vs. Framing error detection\n30.3.9 \nUSART synchronous mode\nThe synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to \n1. In synchronous mode, the following bits must be kept cleared:\n•\nLINEN bit in the USART_CR2 register,\n•\nSCEN, HDSEL and IREN bits in the USART_CR3 register.\nThe USART allows the user to control a bidirectional synchronous serial communications in \nmaster mode. The CK pin is the output of the USART transmitter clock. No clock pulses are \nsent to the CK pin during start bit and stop bit. Depending on the state of the LBCL bit in the \nUSART_CR2 register clock pulses are generated or not during the last valid data bit \n(address mark). The CPOL bit in the USART_CR2 register allows the user to select the \nclock polarity, and the CPHA bit in the USART_CR2 register allows the user to select the \nphase of the external clock (see Figure 307, Figure 308 & Figure 309).\nDuring the Idle state, preamble and send break, the external CK clock is not activated.\nIn synchronous mode the USART transmitter works exactly like in asynchronous mode. But \nas CK is synchronized with TX (according to CPOL and CPHA), the data on TX is \nsynchronous.\nIn this mode the USART receiver works in a different manner compared to the \nasynchronous mode. If RE=1, the data is sampled on CK (rising or falling edge, depending \non CPOL and CPHA), without any oversampling. A setup and a hold time must be \nrespected (which depends on the baud rate: 1/16 bit time).\nNote:\nThe CK pin works in conjunction with the TX pin. Thus, the clock is provided only if the \ntransmitter is enabled (TE=1) and a data is being transmitted (the data register USART_DR \nMSv31157V1\ndata 1\nIDLE\nBREAK\ndata 2 (0x55)\ndata 3 (header)\n1 data time\n1 data time\nRX line\nRXNE /FE\nLBDF\nCase 1: break occurring after an Idle\ndata 1\ndata2\nBREAK\ndata 2 (0x55)\ndata 3 (header)\n1 data time\n1 data time\nRX line\nRXNE /FE\nLBDF\nCase 2: break occurring while data is being received\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n998/1757\nRM0090 Rev 21\nhas been written). This means that it is not possible to receive a synchronous data without \ntransmitting data.\nThe LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the \nreceiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. These \nbits should not be changed while the transmitter or the receiver is enabled.\nIt is advised that TE and RE are set in the same instruction in order to minimize the setup \nand the hold time of the receiver.\nThe USART supports master mode only: it cannot receive or send data related to an input \nclock (CK is always an output).\nFigure 307. USART example of synchronous transmission\nFigure 308. USART data clock timing diagram (M=0)\nMSv31158V2\nUSART\nSynchronous device\n(slave SPI)\nRX\nTX\nData out\nData in \nClock\nCK\nMSv31159V2\n0\n1\n2\n3\n4\n5\n6\n7\n0\n1\n2\n3\n4\n5\n6\n7\n*\n*\n*\n*\nMSB\nMSB\nLSB\nLSB\nStart\nStart\nStop\nIdle or preceding \ntransmission\nIdle or next \ntransmission\n*\n*LBCL bit controls last data pulse\nCapture strobe\nData on RX \n(from slave)\nData on TX \n(from master)\nClock (CPOL=1, \nCPHA=1\nClock (CPOL=1, \nCPHA=0\nClock (CPOL=0, \nCPHA=1\nClock (CPOL=0, \nCPHA=0\nStop\nM=0 (8 data bits)\n\n\n<>\n\nRM0090 Rev 21\n999/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nFigure 309. USART data clock timing diagram (M=1)\nFigure 310. RX data setup/hold time\nNote:\nThe function of CK is different in Smartcard mode. Refer to the Smartcard mode chapter for \nmore details.\n30.3.10 \nSingle-wire half-duplex communication \nThe single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3 \nregister. In this mode, the following bits must be kept cleared:\n•\nLINEN and CLKEN bits in the USART_CR2 register,\n•\nSCEN and IREN bits in the USART_CR3 register.\nThe USART can be configured to follow a single-wire half-duplex protocol where the TX and \nRX lines are internally connected. The selection between half- and full-duplex \ncommunication is made with a control bit ‘HALF DUPLEX SEL’ (HDSEL in USART_CR3).\nMSv31160V1\n0\n1\n2\n3\n4\n5\n6\n8\n0\n1\n2\n3\n4\n5\n6\n8\n*\n*\n*\n*\nMSB\nMSB\nLSB\nLSB\nStart\nStart\nStop\nIdle or \npreceding \ntransmission\nIdle or next \ntransmission\n*\n*LBCL bit controls last data pulse\nCapture \nstrobe\nData on RX \n(from slave)\nData on TX \n(from master)\nClock (CPOL=1, \nCPHA=1\nClock (CPOL=1, \nCPHA=0\nClock (CPOL=0, \nCPHA=1\nClock (CPOL=0, \nCPHA=0\nStop\nM=1 (9 data bits)\n7\n7\nMSv31161V2\nData on RX (from slave)\nCK\n(capture strobe on CK rising \nedge in this example)\nValid DATA bit\ntSETUP\ntHOLD\ntSETUP=tHOLD 1/16 bit time\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1000/1757\nRM0090 Rev 21\nAs soon as HDSEL is written to 1:\n•\nthe TX and RX lines are internally connected\n•\nthe RX pin is no longer used\n•\nthe TX pin is always released when no data is transmitted. Thus, it acts as a standard \nI/O in idle or in reception. It means that the I/O must be configured so that TX is \nconfigured as floating input (or output high open-drain) when not driven by the USART.\nApart from this, the communications are similar to what is done in normal USART mode. \nThe conflicts on the line must be managed by the software (by the use of a centralized \narbiter, for instance). In particular, the transmission is never blocked by hardware and \ncontinue to occur as soon as a data is written in the data register while the TE bit is set.\n30.3.11 \nSmartcard\nThe Smartcard mode is selected by setting the SCEN bit in the USART_CR3 register. In \nsmartcard mode, the following bits must be kept cleared:\n•\nLINEN bit in the USART_CR2 register,\n•\nHDSEL and IREN bits in the USART_CR3 register.\nMoreover, the CLKEN bit may be set in order to provide a clock to the smartcard.\nThe Smartcard interface is designed to support asynchronous protocol Smartcards as \ndefined in the ISO 7816-3 standard. The USART should be configured as:\n•\n8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register\n•\n1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 \nregister. \nNote:\nIt is also possible to choose 0.5 stop bit for receiving but it is recommended to use 1.5 stop \nbits for both transmitting and receiving to avoid switching between the two configurations.\nFigure 311 shows examples of what can be seen on the data line with and without parity \nerror. \nFigure 311. ISO 7816-3 asynchronous protocol\nWhen connected to a Smartcard, the TX output of the USART drives a bidirectional line that \nis also driven by the Smartcard. The TX pin must be configured as open-drain.\nSmartcard is a single wire half duplex communication protocol.\n•\nTransmission of data from the transmit shift register is guaranteed to be delayed by a \nminimum of 1/2 baud clock. In normal operation a full transmit shift register starts \nMSv31162V1\nWithout Parity error\np\n7\n6\n5\n4\n3\n2\n1\n0\nS\nGuard time\nWithParity error\np\n7\n6\n5\n4\n3\n2\n1\n0\nS\nGuard time\nStart bit\nStart bit\nLine pulled low by receiver \nduring stop in case of parity error\n\n\n<>\n\nRM0090 Rev 21\n1001/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nshifting on the next baud clock edge. In Smartcard mode this transmission is further \ndelayed by a guaranteed 1/2 baud clock.\n•\nIf a parity error is detected during reception of a frame programmed with a 0.5 or 1.5 \nstop bit period, the transmit line is pulled low for a baud clock period after the \ncompletion of the receive frame. This is to indicate to the Smartcard that the data \ntransmitted to USART has not been correctly received. This NACK signal (pulling \ntransmit line low for 1 baud clock) causes a framing error on the transmitter side \n(configured with 1.5 stop bits). The application can handle re-sending of data according \nto the protocol. A parity error is ‘NACK’ed by the receiver if the NACK control bit is set, \notherwise a NACK is not transmitted.\n•\nThe assertion of the TC flag can be delayed by programming the Guard Time register. \nIn normal operation, TC is asserted when the transmit shift register is empty and no \nfurther transmit requests are outstanding. In Smartcard mode an empty transmit shift \nregister triggers the guard time counter to count up to the programmed value in the \nGuard Time register. TC is forced low during this time. When the guard time counter \nreaches the programmed value TC is asserted high.\n•\nThe de-assertion of TC flag is unaffected by Smartcard mode.\n•\nIf a framing error is detected on the transmitter end (due to a NACK from the receiver), \nthe NACK is not detected as a start bit by the receive block of the transmitter. \nAccording to the ISO protocol, the duration of the received NACK can be 1 or 2 baud \nclock periods.\n•\nOn the receiver side, if a parity error is detected and a NACK is transmitted the receiver \ndoes not detect the NACK as a start bit.\nNote:\nA break character is not significant in Smartcard mode. A 0x00 data with a framing error is \ntreated as data and not as a break. \nNo Idle frame is transmitted when toggling the TE bit. The Idle frame (as defined for the \nother configurations) is not defined by the ISO protocol.\nFigure 312 details how the NACK signal is sampled by the USART. In this example the \nUSART is transmitting a data and is configured with 1.5 stop bits. The receiver part of the \nUSART is enabled in order to check the integrity of the data and the NACK signal.\nFigure 312. Parity error detection using the 1.5 stop bits\nThe USART can provide a clock to the smartcard through the CK output. In smartcard \nmode, CK is not associated to the communication but is simply derived from the internal \nperipheral input clock through a 5-bit prescaler. The division ratio is configured in the \nMSv31163V1\nBit 7\nParity bit\n1.5 Stop bit\n1 bit time\n1.5 bit time\n0.5 bit time\nSampling at \n8th, 9th, 10th\nSampling at \n8th, 9th, 10th\nSampling at \n8th, 9th, 10th\nSampling at \n8th, 9th, 10th\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1002/1757\nRM0090 Rev 21\nprescaler register USART_GTPR. CK frequency can be programmed from fCK/2 to fCK/62, \nwhere fCK is the peripheral input clock.\n30.3.12 \nIrDA SIR ENDEC block \nThe IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA \nmode, the following bits must be kept cleared:\n•\nLINEN, STOP and CLKEN bits in the USART_CR2 register,\n•\nSCEN and HDSEL bits in the USART_CR3 register.\nThe IrDA SIR physical layer specifies use of a Return to Zero, Inverted (RZI) modulation \nscheme that represents logic 0 as an infrared light pulse (see Figure 313).\nThe SIR Transmit encoder modulates the Non Return to Zero (NRZ) transmit bit stream \noutput from USART. The output pulse stream is transmitted to an external output driver and \ninfrared LED. USART supports only bit rates up to 115.2Kbps for the SIR ENDEC. In normal \nmode the transmitted pulse width is specified as 3/16 of a bit period.\nThe SIR receive decoder demodulates the return-to-zero bit stream from the infrared \ndetector and outputs the received NRZ serial bit stream to USART. The decoder input is \nnormally HIGH (marking state) in the Idle state. The transmit encoder output has the \nopposite polarity to the decoder input. A start bit is detected when the decoder input is low.\n•\nIrDA is a half duplex communication protocol. If the Transmitter is busy (i.e. the USART \nis sending data to the IrDA encoder), any data on the IrDA receive line is ignored by the \nIrDA decoder and if the Receiver is busy (USART is receiving decoded data from the \nUSART), data on the TX from the USART to IrDA is not encoded by IrDA. While \nreceiving data, transmission should be avoided as the data to be transmitted could be \ncorrupted.\n•\nA ‘0 is transmitted as a high pulse and a ‘1 is transmitted as a ‘0. The width of the pulse \nis specified as 3/16th of the selected bit period in normal mode (see Figure 314).\n•\nThe SIR decoder converts the IrDA compliant receive signal into a bit stream for \nUSART.\n•\nThe SIR receive logic interprets a high state as a logic one and low pulses as logic \nzeros.\n•\nThe transmit encoder output has the opposite polarity to the decoder input. The SIR \noutput is in low state when Idle.\n•\nThe IrDA specification requires the acceptance of pulses greater than 1.41 us. The \nacceptable pulse width is programmable. Glitch detection logic on the receiver end \nfilters out pulses of width less than 2 PSC periods (PSC is the prescaler value \nprogrammed in the IrDA low-power Baud Register, USART_GTPR). Pulses of width \nless than 1 PSC period are always rejected, but those of width greater than one and \nless than two periods may be accepted or rejected, those greater than 2 periods are \naccepted as a pulse. The IrDA encoder/decoder does not work when PSC = 0.\n•\nThe receiver can communicate with a low-power transmitter.\n•\nIn IrDA mode, the STOP bits in the USART_CR2 register must be configured to “1 stop \nbit”.\n\n\n<>\n\nRM0090 Rev 21\n1003/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nIrDA low-power mode \nTransmitter:\nIn low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the \nwidth of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz. \nGenerally this value is 1.8432 MHz (1.42 MHz < PSC< 2.12 MHz). A low-power mode \nprogrammable divisor divides the system clock to achieve this value.\nReceiver:\nReceiving in low-power mode is similar to receiving in normal mode. For glitch detection the \nUSART should discard pulses of duration shorter than 1/PSC. A valid low is accepted only if \nits duration is greater than 2 periods of the IrDA low-power Baud clock (PSC value in \nUSART_GTPR).\nNote:\nA pulse of width less than two and greater than one PSC period(s) may or may not be \nrejected.\nThe receiver set up time should be managed by software. The IrDA physical layer \nspecification specifies a minimum of 10 ms delay between transmission and reception (IrDA \nis a half duplex protocol).\nFigure 313. IrDA SIR ENDEC- block diagram\nFigure 314. IrDA data modulation (3/16) -Normal mode\nMSv31164V\nUSART\nIrDA\nUSART\nSIR\nTransmit\nEncoder\nSIR\nReceive\nDEcoder\nTX\nSIREN\nRX\nUSART_RX\nUSART_TX\nMSv31165V1\nTX\nStart \nbit\n0\n1\n0\n1\n0\n0\n1\n1\n0\n1\nStop \nbit\nBit period\nIrDA_OUT\nIrDA_IN\nRX\n3/16\n0\n1\n0\n1\n0\n0\n1\n1\n0\n1\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1004/1757\nRM0090 Rev 21\n30.3.13 \nContinuous communication using DMA\nThe USART is capable of continuous communication using the DMA. The DMA requests for \nRx buffer and Tx buffer are generated independently.\nTransmission using DMA\nDMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 \nregister. Data is loaded from a SRAM area configured using the DMA peripheral (refer to the \nDMA specification) to the USART_DR register whenever the TXE bit is set. To map a DMA \nchannel for USART transmission, use the following procedure (x denotes the channel \nnumber):\n1.\nWrite the USART_DR register address in the DMA control register to configure it as the \ndestination of the transfer. The data are moved to this address from memory after each \nTXE event.\n2. \nWrite the memory address in the DMA control register to configure it as the source of \nthe transfer. The data are loaded into the USART_DR register from this memory area \nafter each TXE event.\n3. \nConfigure the total number of bytes to be transferred to the DMA control register.\n4. \nConfigure the channel priority in the DMA register\n5. \nConfigure DMA interrupt generation after half/ full transfer as required by the \napplication.\n6. \nClear the TC bit in the SR register by writing 0 to it.\n7. \nActivate the channel in the DMA register.\nWhen the number of data transfers programmed in the DMA Controller is reached, the DMA \ncontroller generates an interrupt on the DMA channel interrupt vector.\nIn transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag \nis set in the DMA_ISR register), the TC flag can be monitored to make sure that the USART \ncommunication is complete. This is required to avoid corrupting the last transmission before \ndisabling the USART or entering the Stop mode. The software must wait until TC=1. The TC \nflag remains cleared during all data transfers and it is set by hardware at the last frame’s \nend of transmission.\n\n\n<>\n\nRM0090 Rev 21\n1005/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nFigure 315. Transmission using DMA\nReception using DMA\nDMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register. \nData is loaded from the USART_DR register to a SRAM area configured using the DMA \nperipheral (refer to the DMA specification) whenever a data byte is received. To map a DMA \nchannel for USART reception, use the following procedure:\n1.\nWrite the USART_DR register address in the DMA control register to configure it as the \nsource of the transfer. The data are moved from this address to the memory after each \nRXNE event.\n2. \nWrite the memory address in the DMA control register to configure it as the destination \nof the transfer. The data are loaded from USART_DR to this memory area after each \nRXNE event.\n3. \nConfigure the total number of bytes to be transferred in the DMA control register.\n4. \nConfigure the channel priority in the DMA control register\n5. \nConfigure interrupt generation after half/ full transfer as required by the application.\n6. \nActivate the channel in the DMA control register.\nWhen the number of data transfers programmed in the DMA Controller is reached, the DMA \ncontroller generates an interrupt on the DMA channel interrupt vector. The DMAR bit should \nbe cleared by software in the USART_CR3 register during the interrupt subroutine.\nTX line\nUSART_DR\nFrame 1\nTXE flag\nF2\nTC flag\nF3\nFrame 2\nsoftware waits until TC=1\nFrame 3\nset by hardware\ncleared by DMA read\nset by hardware\ncleared by DMA read\nset by hardware\nset \nIdle preamble\nby hardware\nF1\nsoftware configures \nthe DMA to send 3 \ndata and enables the \nUSART\nDMA request\nignored by the DMA \nDMA writes\nflag DMA TCIF \nset by hardware\nclear \nby software\n USART_DR\nbecause DMA transfer is complete\nDMA writes F1 \ninto \nUSART_DR\nDMA writes F2 \ninto \nUSART_DR\nDMA writes F3 \ninto \nUSART_DR.\nThe DMA transfer \nis complete \n(TCIF=1 in \nDMA_ISR)\n(Transfer complete)\nai17192b\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1006/1757\nRM0090 Rev 21\nFigure 316. Reception using DMA\nError flagging and interrupt generation in multibuffer communication \nIn case of multibuffer communication if any error occurs during the transaction the error flag \nis asserted after the current byte. An interrupt is generated if the interrupt enable flag is set. \nFor framing error, overrun error and noise flag which are asserted with RXNE in case of \nsingle byte reception, there is a separate error flag interrupt enable bit (EIE bit in the \nUSART_CR3 register), which if set, issues an interrupt after the current byte with either of \nthese errors.\n30.3.14 \nHardware flow control\nIt is possible to control the serial data flow between 2 devices by using the CTS input and \nthe RTS output. The Figure 317 shows how to connect 2 devices in this mode:\nFigure 317. Hardware flow control between 2 USARTs\nRTS and CTS flow control can be enabled independently by writing respectively RTSE and \nCTSE bits to 1 (in the USART_CR3 register).\nTX line\nUSART_DR\nFrame 1\nRXNE flag\nF2\nF3\nFrame 2\nFrame 3\nset by hardware\ncleared by DMA read\nF1\nsoftware configures the \nDMA to receive 3 data \nblocks and enables\nthe USART\nDMA request\nDMA reads USART_DR\nDMA TCIF flag\nset by hardware\ncleared \nby software\nDMA reads F1 \nfrom \nUSART_DR\n(Transfer complete)\nDMA reads F2 \nfrom \nUSART_DR\nDMA reads F3 \nfrom \nUSART_DR\nThe DMA transfer \nis complete \n(TCIF=1 in \nDMA_ISR)\nai17193b\nMSv31169V2\nTX circuit\nUSART 1\nTX \nRX circuit\nRX circuit\nUSART 2\nTX circuit\nTX \nCTS\nCTS\nRTS\nRX \nRTS\nRX \n\n\n<>\n\nRM0090 Rev 21\n1007/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nRTS flow control\nIf the RTS flow control is enabled (RTSE=1), then RTS is asserted (tied low) as long as the \nUSART receiver is ready to receive a new data. When the receive register is full, RTS is \ndeasserted, indicating that the transmission is expected to stop at the end of the current \nframe. Figure 318 shows an example of communication with RTS flow control enabled.\nFigure 318. RTS flow control\nCTS flow control\nIf the CTS flow control is enabled (CTSE=1), then the transmitter checks the CTS input \nbefore transmitting the next frame. If CTS is asserted (tied low), then the next data is \ntransmitted (assuming that a data is to be transmitted, in other words, if TXE=0), else the \ntransmission does not occur. When CTS is deasserted during a transmission, the current \ntransmission is completed before the transmitter stops.\nWhen CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the CTS \ninput toggles. It indicates when the receiver becomes ready or not ready for communication. \nAn interrupt is generated if the CTSIE bit in the USART_CR3 register is set. The figure \nbelow shows an example of communication with CTS flow control enabled.\nMSv68794V1\nStart\nbit\nStart\nbit\nStop\nbit Idle\nStop\nbit\nRX\nRTS\nData 1 read \nData 2 can now be transmitted\nRXNE\nRXNE\nData 1\nData 2\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1008/1757\nRM0090 Rev 21\nFigure 319. CTS flow control\nNote:\nSpecial behavior of break frames: when the CTS flow is enabled, the transmitter does not \ncheck the CTS input state to send a break.\nMSv68793V1\nStart\nbit\nStop\nbit\nTX\nTDR\nCTS\nData 1\nData 2\nStop\nbit Idle Start\nbit\nData 2\nData 3\nData 3\nempty\nempty\nCTS\nCTS\nTransmit data register\nWriting data 3 in TDR\nTransmission of Data 3 is \ndelayed until CTS = 0 \n\n\n<>\n\nRM0090 Rev 21\n1009/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n30.4 \nUSART interrupts\n \nThe USART interrupt events are connected to the same interrupt vector (see Figure 320).\n•\nDuring transmission: Transmission Complete, Clear to Send or Transmit Data Register \nempty interrupt.\n•\nWhile receiving: Idle Line detection, Overrun error, Receive Data register not empty, \nParity error, LIN break detection, Noise Flag (only in multi buffer communication) and \nFraming Error (only in multi buffer communication).\nThese events generate an interrupt if the corresponding Enable Control Bit is set.\nFigure 320. USART interrupt mapping diagram \nTable 148. USART interrupt requests\nInterrupt event\nEvent flag\nEnable control \nbit\nTransmit Data Register Empty\nTXE\nTXEIE\nCTS flag\nCTS\nCTSIE\nTransmission Complete\nTC\nTCIE\nReceived Data Ready to be Read\nRXNE\nRXNEIE\nOverrun Error Detected\nORE\nIdle Line Detected\nIDLE\nIDLEIE\nParity Error\nPE\nPEIE\nBreak Flag\nLBD\nLBDIE\nNoise Flag, Overrun error and Framing Error in multibuffer \ncommunication\nNF or ORE or FE EIE\nMSv42089V1\nTC\nTCIE\nTXE\nTXEIE\nCTSIF\nCTSIE\nIDLE\nIDLEIE\nRXNEIE\nORE\nRXNEIE\nRXNE\nPE\nPEIE\nLBD\nLBDIE\nFE\nNE\nORE\nEIE\nUSART \ninterrupt\nDMAR\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1010/1757\nRM0090 Rev 21\n30.5 \nUSART mode configuration\n \n30.6 \nUSART registers\nRefer to Section 1.1: List of abbreviations for registers for registers for a list of abbreviations \nused in register descriptions.\nThe peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).\n30.6.1 \nStatus register (USART_SR)\nAddress offset: 0x00\nReset value: 0x000C0 00C0\nTable 149. USART mode configuration(1)\n1.\nX = supported; NA = not applicable.\nUSART modes\nUSART\n1\nUSART\n2\nUSART\n3\nUART4\nUART5\nUSART\n6\nAsynchronous mode\nX\nX\nX\nX\nX\nX\nHardware flow control\nX\nX\nX\nNA\nNA\nX\nMultibuffer communication (DMA)\nX\nX\nX\nX\nX\nX\nMultiprocessor communication\nX\nX\nX\nX\nX\nX\nSynchronous\nX\nX\nX\nNA\nNA\nX\nSmartcard\nX\nX\nX\nNA\nNA\nX\nHalf-duplex (single-wire mode)\nX\nX\nX\nX\nX\nX\nIrDA\nX\nX\nX\nX\nX\nX\nLIN\nX\nX\nX\nX\nX\nX\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCTS\nLBD\nTXE\nTC\nRXNE\nIDLE\nORE\nNF\nFE\nPE\nrc_w0\nrc_w0\nr\nrc_w0\nrc_w0\nr\nr\nr\nr\nr\n\n\n<>\n\nRM0090 Rev 21\n1011/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n \nBits 31:10 Reserved, must be kept at reset value\nBit 9 CTS: CTS flag\nThis bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by \nsoftware (by writing it to 0). An interrupt is generated if CTSIE=1 in the USART_CR3 \nregister.\n0: No change occurred on the CTS status line\n1: A change occurred on the CTS status line\nNote: This bit is not available for UART4 & UART5.\nBit 8 LBD: LIN break detection flag\nThis bit is set by hardware when the LIN break is detected. It is cleared by software (by \nwriting it to 0). An interrupt is generated if LBDIE = 1 in the USART_CR2 register.\n0: LIN Break not detected\n1: LIN break detected\nNote: An interrupt is generated when LBD=1 if LBDIE=1\nBit 7 TXE: Transmit data register empty\nThis bit is set by hardware when the content of the TDR register has been transferred into \nthe shift register. An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register. It \nis cleared by a write to the USART_DR register.\n0: Data is not transferred to the shift register\n1: Data is transferred to the shift register)\nNote: This bit is used during single buffer transmission.\nBit 6 TC: Transmission complete\nThis bit is set by hardware if the transmission of a frame containing data is complete and if \nTXE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by \na software sequence (a read from the USART_SR register followed by a write to the \nUSART_DR register). The TC bit can also be cleared by writing a '0' to it. This clearing \nsequence is recommended only for multibuffer communication.\n0: Transmission is not complete\n1: Transmission is complete\nBit 5 RXNE: Read data register not empty\nThis bit is set by hardware when the content of the RDR shift register has been transferred \nto the USART_DR register. An interrupt is generated if RXNEIE=1 in the USART_CR1 \nregister. It is cleared by a read to the USART_DR register. The RXNE flag can also be \ncleared by writing a zero to it. This clearing sequence is recommended only for multibuffer \ncommunication.\n0: Data is not received\n1: Received data is ready to be read.\nBit 4 IDLE: IDLE line detected\nThis bit is set by hardware when an Idle Line is detected. An interrupt is generated if the \nIDLEIE=1 in the USART_CR1 register. It is cleared by a software sequence (an read to the \nUSART_SR register followed by a read to the USART_DR register). \n0: No Idle Line is detected\n1: Idle Line is detected\nNote: The IDLE bit is not set again until the RXNE bit has been set itself (a new idle line \noccurs).\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1012/1757\nRM0090 Rev 21\nBit 3 ORE: Overrun error\nThis bit is set by hardware when the word currently being received in the shift register is \nready to be transferred into the RDR register while RXNE=1. An interrupt is generated if \nRXNEIE=1 in the USART_CR1 register. It is cleared by a software sequence (an read to the \nUSART_SR register followed by a read to the USART_DR register).\n0: No Overrun error\n1: Overrun error is detected\nNote: When this bit is set, the RDR register content is not lost but the shift register is \noverwritten. An interrupt is generated on ORE flag in case of Multi Buffer \ncommunication if the EIE bit is set.\nBit 2 NF: Noise detected flag\nThis bit is set by hardware when noise is detected on a received frame. It is cleared by a \nsoftware sequence (an read to the USART_SR register followed by a read to the \nUSART_DR register).\n0: No noise is detected\n1: Noise is detected\nNote: This bit does not generate interrupt as it appears at the same time as the RXNE bit \nwhich itself generates an interrupting interrupt is generated on NF flag in case of Multi \nBuffer communication if the EIE bit is set.\nNote: When the line is noise-free, the NF flag can be disabled by programming the ONEBIT \nbit to 1 to increase the USART tolerance to deviations (Refer to Section 30.3.5: USART \nreceiver tolerance to clock deviation on page 991).\nBit 1 FE: Framing error\nThis bit is set by hardware when a de-synchronization, excessive noise or a break character \nis detected. It is cleared by a software sequence (an read to the USART_SR register \nfollowed by a read to the USART_DR register).\n0: No Framing error is detected\n1: Framing error or break character is detected\nNote: This bit does not generate interrupt as it appears at the same time as the RXNE bit \nwhich itself generates an interrupt. If the word currently being transferred causes both \nframe error and overrun error, it is transferred and only the ORE bit is set.\nAn interrupt is generated on FE flag in case of Multi Buffer communication if the EIE bit \nis set.\nBit 0 PE: Parity error\nThis bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a \nsoftware sequence (a read from the status register followed by a read or write access to the \nUSART_DR data register). The software must wait for the RXNE flag to be set before \nclearing the PE bit.\nAn interrupt is generated if PEIE = 1 in the USART_CR1 register.\n0: No parity error\n1: Parity error\n\n\n<>\n\nRM0090 Rev 21\n1013/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n30.6.2 \nData register (USART_DR)\nAddress offset: 0x04\nReset value: 0xXXXX XXXX \n30.6.3 \nBaud rate register (USART_BRR)\nNote:\nThe baud counters stop counting if the TE or RE bits are disabled respectively.\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n30.6.4 \nControl register 1 (USART_CR1)\nAddress offset: 0x0C\nReset value: 0x0000 0000\nBits 31:9 Reserved, must be kept at reset value\nBits 8:0 DR[8:0]: Data value\nContains the Received or Transmitted data character, depending on whether it is read from \nor written to.\nThe Data register performs a double function (read and write) since it is composed of two \nregisters, one for transmission (TDR) and one for reception (RDR)\nThe TDR register provides the parallel interface between the internal bus and the output shift \nregister (see Figure 296: USART block diagram).\nThe RDR register provides the parallel interface between the input shift register and the \ninternal bus.\nWhen transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the \nvalue written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because \nit is replaced by the parity.\nWhen receiving with the parity enabled, the value read in the MSB bit is the received parity \nbit.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDIV_Mantissa[11:0]\nDIV_Fraction[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value\nBits 15:4 DIV_Mantissa[11:0]: mantissa of USARTDIV\nThese 12 bits define the mantissa of the USART Divider (USARTDIV)\nBits 3:0 DIV_Fraction[3:0]: fraction of USARTDIV\nThese 4 bits define the fraction of the USART Divider (USARTDIV). When OVER8=1, the \nDIV_Fraction3 bit is not considered and must be kept cleared.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOVER8\nReserved\nUE\nM\nWAKE\nPCE\nPS\nPEIE\nTXEIE\nTCIE\nRXNEIE\nIDLEIE\nTE\nRE\nRWU\nSBK\nrw\nRes.\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1014/1757\nRM0090 Rev 21\n \nBits 31:16 Reserved, must be kept at reset value\nBit 15 OVER8: Oversampling mode\n0: oversampling by 16\n1: oversampling by 8\nNote: Oversampling by 8 is not available in the Smartcard, IrDA and LIN modes: when \nSCEN=1,IREN=1 or LINEN=1 then OVER8 is forced to ‘0 by hardware.\nBit 14 Reserved, must be kept at reset value\nBit 13 UE: USART enable\nWhen this bit is cleared, the USART prescalers and outputs are stopped and the end of the \ncurrent byte transfer in order to reduce power consumption. This bit is set and cleared by \nsoftware.\n0: USART prescaler and outputs disabled\n1: USART enabled\nBit 12 M: Word length\nThis bit determines the word length. It is set or cleared by software.\n0: 1 Start bit, 8 Data bits, n Stop bit\n1: 1 Start bit, 9 Data bits, n Stop bit\nNote: The M bit must not be modified during a data transfer (both transmission and reception)\nBit 11 WAKE: Wake-up method\nThis bit determines the USART wake-up method, it is set or cleared by software.\n0: Idle Line\n1: Address Mark\nBit 10 PCE: Parity control enable\nThis bit selects the hardware parity control (generation and detection). When the parity \ncontrol is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit \nif M=0) and parity is checked on the received data. This bit is set and cleared by software. \nOnce it is set, PCE is active after the current byte (in reception and in transmission).\n0: Parity control disabled\n1: Parity control enabled\nBit 9 PS: Parity selection\nThis bit selects the odd or even parity when the parity generation/detection is enabled (PCE \nbit set). It is set and cleared by software. The parity is selected after the current byte.\n0: Even parity\n1: Odd parity\nBit 8 PEIE: PE interrupt enable\nThis bit is set and cleared by software.\n0: Interrupt is inhibited\n1: An USART interrupt is generated whenever PE=1 in the USART_SR register\nBit 7 TXEIE: TXE interrupt enable\nThis bit is set and cleared by software.\n0: Interrupt is inhibited\n1: An USART interrupt is generated whenever TXE=1 in the USART_SR register\nBit 6 TCIE: Transmission complete interrupt enable\nThis bit is set and cleared by software.\n0: Interrupt is inhibited\n1: An USART interrupt is generated whenever TC=1 in the USART_SR register\n\n\n<>\n\nRM0090 Rev 21\n1015/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nBit 5 RXNEIE: RXNE interrupt enable\nThis bit is set and cleared by software.\n0: Interrupt is inhibited\n1: An USART interrupt is generated whenever ORE=1 or RXNE=1 in the USART_SR \nregister\nBit 4 IDLEIE: IDLE interrupt enable\nThis bit is set and cleared by software.\n0: Interrupt is inhibited\n1: An USART interrupt is generated whenever IDLE=1 in the USART_SR register\nBit 3 TE: Transmitter enable\nThis bit enables the transmitter. It is set and cleared by software. \n0: Transmitter is disabled\n1: Transmitter is enabled\nNote: During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble \n(idle line) after the current word, except in smartcard mode.\nWhen TE is set, there is a 1 bit-time delay before the transmission starts.\nBit 2 RE: Receiver enable\nThis bit enables the receiver. It is set and cleared by software. \n0: Receiver is disabled\n1: Receiver is enabled and begins searching for a start bit\nBit 1 RWU: Receiver wake-up\nThis bit determines if the USART is in mute mode or not. It is set and cleared by software \nand can be cleared by hardware when a wake-up sequence is recognized. \n0: Receiver in active mode\n1: Receiver in mute mode\nNote: Before selecting Mute mode (by setting the RWU bit) the USART must first receive a \ndata byte, otherwise it cannot function in Mute mode with wake-up by Idle line \ndetection.\nIn Address Mark Detection wake-up configuration (WAKE bit=1) the RWU bit cannot be \nmodified by software while the RXNE bit is set.\nBit 0 SBK: Send break\nThis bit set is used to send break characters. It can be set and cleared by software. It should \nbe set by software, and is reset by hardware during the stop bit of break.\n0: No break character is transmitted.\n1: Break character is transmitted.\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1016/1757\nRM0090 Rev 21\n30.6.5 \nControl register 2 (USART_CR2)\nAddress offset: 0x10\nReset value: 0x0000 0000 \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nLINEN\nSTOP[1:0]\nCLKEN\nCPOL\nCPHA\nLBCL\nRes.\nLBDIE\nLBDL\nRes.\nADD[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:15 Reserved, must be kept at reset value\nBit 14 LINEN: LIN mode enable\nThis bit is set and cleared by software.\n0: LIN mode disabled\n1: LIN mode enabled\nThe LIN mode enables the capability to send LIN Synch Breaks (13 low bits) using the SBK bit in \nthe USART_CR1 register, and to detect LIN Sync breaks.\nBits 13:12 STOP: STOP bits\nThese bits are used for programming the stop bits.\n00: 1 Stop bit\n01: 0.5 Stop bit\n10: 2 Stop bits\n11: 1.5 Stop bit\nNote: The 0.5 Stop bit and 1.5 Stop bit are not available for UART4 & UART5.\nBit 11 CLKEN: Clock enable\nThis bit allows the user to enable the CK pin.\n0: CK pin disabled\n1: CK pin enabled\nThis bit is not available for UART4 & UART5.\nBit 10 CPOL: Clock polarity\nThis bit allows the user to select the polarity of the clock output on the CK pin in synchronous mode. \nIt works in conjunction with the CPHA bit to produce the desired clock/data relationship \n0: Steady low value on CK pin outside transmission window.\n1: Steady high value on CK pin outside transmission window.\nThis bit is not available for UART4 & UART5.\nBit 9 CPHA: Clock phase\nThis bit allows the user to select the phase of the clock output on the CK pin in synchronous mode. \nIt works in conjunction with the CPOL bit to produce the desired clock/data relationship (see figures \n308 to 309)\n0: The first clock transition is the first data capture edge\n1: The second clock transition is the first data capture edge\nNote: This bit is not available for UART4 & UART5.\n\n\n<>\n\nRM0090 Rev 21\n1017/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nNote:\nThese 3 bits (CPOL, CPHA, LBCL) should not be written while the transmitter is enabled.\n30.6.6 \nControl register 3 (USART_CR3)\nAddress offset: 0x14\nReset value: 0x0000 0000\n \nBit 8 LBCL: Last bit clock pulse\nThis bit allows the user to select whether the clock pulse associated with the last data bit \ntransmitted (MSB) has to be output on the CK pin in synchronous mode. \n0: The clock pulse of the last data bit is not output to the CK pin\n1: The clock pulse of the last data bit is output to the CK pin\nNote: 1: The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected \nby the M bit in the USART_CR1 register.\n2: This bit is not available for UART4 & UART5.\nBit 7 Reserved, must be kept at reset value\nBit 6 LBDIE: LIN break detection interrupt enable\nBreak interrupt mask (break detection using break delimiter).\n0: Interrupt is inhibited\n1: An interrupt is generated whenever LBD=1 in the USART_SR register\nBit 5 LBDL: lin break detection length\nThis bit is for selection between 11 bit or 10 bit break detection.\n0: 10-bit break detection\n1: 11-bit break detection\nBit 4 Reserved, must be kept at reset value\nBits 3:0 ADD[3:0]: Address of the USART node\nThis bit-field gives the address of the USART node.\nThis is used in multiprocessor communication during mute mode, for wake up with address mark \ndetection.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nONEBIT\nCTSIE\nCTSE\nRTSE\nDMAT\nDMAR\nSCEN\nNACK\nHDSEL\nIRLP\nIREN\nEIE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value\nBit 11 ONEBIT: One sample bit method enable\nThis bit allows the user to select the sample method. When the one sample bit method is \nselected the noise detection flag (NF) is disabled.\n0: Three sample bit method\n1: One sample bit method\nNote: The ONEBIT feature applies only to data bits. It does not apply to START bit.\nBit 10 CTSIE: CTS interrupt enable\n0: Interrupt is inhibited\n1: An interrupt is generated whenever CTS=1 in the USART_SR register\nNote: This bit is not available for UART4 & UART5.\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1018/1757\nRM0090 Rev 21\nBit 9 CTSE: CTS enable\n0: CTS hardware flow control disabled\n1: CTS mode enabled, data is only transmitted when the CTS input is asserted (tied to 0). If \nthe CTS input is deasserted while a data is being transmitted, then the transmission is \ncompleted before stopping. If a data is written into the data register while CTS is \ndeasserted, the transmission is postponed until CTS is asserted.\nNote: This bit is not available for UART4 & UART5.\nBit 8 RTSE: RTS enable\n0: RTS hardware flow control disabled\n1: RTS interrupt enabled, data is only requested when there is space in the receive buffer. \nThe transmission of data is expected to cease after the current character has been \ntransmitted. The RTS output is asserted (tied to 0) when a data can be received.\nNote: This bit is not available for UART4 & UART5.\nBit 7 DMAT: DMA enable transmitter\nThis bit is set/reset by software\n1: DMA mode is enabled for transmission.\n0: DMA mode is disabled for transmission.\nBit 6 DMAR: DMA enable receiver\nThis bit is set/reset by software\n1: DMA mode is enabled for reception\n0: DMA mode is disabled for reception\nBit 5 SCEN: Smartcard mode enable\nThis bit is used for enabling Smartcard mode.\n0: Smartcard Mode disabled\n1: Smartcard Mode enabled\nNote: This bit is not available for UART4 & UART5.\nBit 4 NACK: Smartcard NACK enable\n0: NACK transmission in case of parity error is disabled\n1: NACK transmission during parity error is enabled\nNote: This bit is not available for UART4 & UART5.\nBit 3 HDSEL: Half-duplex selection\nSelection of Single-wire Half-duplex mode \n0: Half duplex mode is not selected\n1: Half duplex mode is selected \n\n\n<>\n\nRM0090 Rev 21\n1019/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nBit 2 IRLP: IrDA low-power\nThis bit is used for selecting between normal and low-power IrDA modes\n0: Normal mode\n1: Low-power mode\nBit 1 IREN: IrDA mode enable\nThis bit is set and cleared by software.\n0: IrDA disabled\n1: IrDA enabled\nBit 0 EIE: Error interrupt enable\nError Interrupt Enable Bit is required to enable interrupt generation in case of a framing \nerror, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USART_SR register) in \ncase of Multi Buffer Communication (DMAR=1 in the USART_CR3 register).\n0: Interrupt is inhibited\n1: An interrupt is generated whenever DMAR=1 in the USART_CR3 register and FE=1 or \nORE=1 or NF=1 in the USART_SR register.\n\n\n<>\n\nUniversal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1020/1757\nRM0090 Rev 21\n30.6.7 \nGuard time and prescaler register (USART_GTPR)\nAddress offset: 0x18\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nGT[7:0]\nPSC[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value\nBits 15:8 GT[7:0]: Guard time value\nThis bit-field gives the Guard time value in terms of number of baud clocks.\nThis is used in Smartcard mode. The Transmission Complete flag is set after this guard time \nvalue.\nNote: This bit is not available for UART4 & UART5.\nBits 7:0 PSC[7:0]: Prescaler value\n– In IrDA Low-power mode: \nPSC[7:0] = IrDA Low-Power Baud Rate\nUsed for programming the prescaler for dividing the system clock to achieve the low-power \nfrequency:\nThe source clock is divided by the value given in the register (8 significant bits):\n00000000: Reserved - do not program this value\n00000001: divides the source clock by 1\n00000010: divides the source clock by 2\n... \n– In normal IrDA mode: PSC must be set to 00000001.\n– In smartcard mode:\nPSC[4:0]: Prescaler value\nUsed for programming the prescaler for dividing the system clock to provide the smartcard \nclock.\nThe value given in the register (5 significant bits) is multiplied by 2 to give the division factor \nof the source clock frequency:\n00000: Reserved - do not program this value\n00001: divides the source clock by 2\n00010: divides the source clock by 4\n00011: divides the source clock by 6\n... \nNote: 1: Bits [7:5] have no effect if Smartcard mode is used.\n2: This bit is not available for UART4 & UART5.\n\n\n<>\n\nRM0090 Rev 21\n1021/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n30.6.8 \nUSART register map\nThe table below gives the USART register map and reset values. \n \nRefer to Section 2.3: Memory map for the register boundary addresses.\nTable 150. USART register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nUSART_SR\nReserved\nCTS\nLBD\nTXE\nTC\nRXNE\nIDLE\nORE\nNF\nFE\nPE\nReset value\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\n0x04\nUSART_DR\nReserved\nDR[8:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nUSART_BRR\nReserved\nDIV_Mantissa[15:4]\nDIV_Fraction\n[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nUSART_CR1\nReserved\nOVER8\nReserved\nUE\nM\nWAKE\nPCE\nPS\nPEIE\nTXEIE\nTCIE\nRXNEIE\nIDLEIE\nTE\nRE\nRWU\nSBK\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nUSART_CR2\nReserved\nLINEN\nSTOP\n[1:0]\nCLKEN\nCPOL\nCPHA\nLBCL\nReserved\nLBDIE\nLBDL\nReserved\nADD[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nUSART_CR3\nReserved\nONEBIT\nCTSIE\nCTSE\nRTSE\nDMAT\nDMAR\nSCEN\nNACK\nHDSEL\nIRLP\nIREN\nEIE\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x18\nUSART_GTPR\nReserved\nGT[7:0]\nPSC[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1022/1757\nRM0090 Rev 21\n31 \nSecure digital input/output interface (SDIO)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n31.1 \nSDIO main features\nThe SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2 \nperipheral bus and MultiMediaCards (MMCs), SD memory cards, SDIO cards and CE-ATA \ndevices.\nThe MultiMediaCard system specifications are available through the MultiMediaCard \nAssociation website at http://www.jedec.org/, published by the MMCA technical committee.\nSD memory card and SD I/O card system specifications are available through the SD card \nAssociation website at http://www.sdcard.org. \nCE-ATA system specifications are available through the CE-ATA workgroup website.\nThe SDIO features include the following:\n•\nFull compliance with MultiMediaCard System Specification Version 4.2. Card support \nfor three different databus modes: 1-bit (default), 4-bit and 8-bit\n•\nFull compatibility with previous versions of MultiMediaCards (forward compatibility)\n•\nFull compliance with SD Memory Card Specifications Version 2.0\n•\nFull compliance with SD I/O Card Specification Version 2.0: card support for two \ndifferent databus modes: 1-bit (default) and 4-bit\n•\nFull support of the CE-ATA features (full compliance with CE-ATA digital protocol \nRev1.1)\n•\nData transfer up to 50 MHz for the 8 bit mode\n•\nData and command output enable signals to control external bidirectional drivers.\nNote:\nThe SDIO does not have an SPI-compatible communication mode.\nThe SD memory card protocol is a superset of the MultiMediaCard protocol as defined in the \nMultiMediaCard system specification V2.11. Several commands required for SD memory \ndevices are not supported by either SD I/O-only cards or the I/O portion of combo cards. \nSome of these commands have no use in SD I/O devices, such as erase commands, and \nthus are not supported in the SDIO. In addition, several commands are different between \nSD memory cards and SD I/O cards and thus are not supported in the SDIO. For details \nrefer to SD I/O card Specification Version 1.0. CE-ATA is supported over the MMC electrical \ninterface using a protocol that utilizes the existing MMC access primitives. The interface \nelectrical and signaling definition is as defined in the MMC reference.\nThe MultiMediaCard/SD bus connects cards to the controller.\nThe current version of the SDIO supports only one SD/SDIO/MMC4.2 card at any one time \nand a stack of MMC4.1 or previous.\n\n\n<>\n\nRM0090 Rev 21\n1023/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.2 \nSDIO bus topology\nCommunication over the bus is based on command and data transfers.\nThe basic transaction on the MultiMediaCard/SD/SD I/O bus is the command/response \ntransaction. These types of bus transaction transfer their information directly within the \ncommand or response structure. In addition, some operations have a data token.\nData transfers to/from SD/SDIO memory cards are done in data blocks. Data transfers \nto/from MMC are done data blocks or streams. Data transfers to/from the CE-ATA Devices \nare done in data blocks.\nFigure 321. SDIO “no response” and “no data” operations\nFigure 322. SDIO (multiple) block read operation\nai14734b\nOperation (no response)\nOperation (no data)\nSDMMC_CMD\nSDMMC_D\nFrom host to card(s)\nFrom host to card\nFrom card to host\nResponse\nCommand\nCommand\nai14735b\nCommand\nResponse\nData block crc\nData block crc\nData block crc\nBlock read operation\nMultiple block read operation\nData stop operation\nFrom host to card From card to host\ndata from card to host\nStop command\nstops data transfer\nCommand\nResponse\nSDMMC_CMD\nSDMMC_D\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1024/1757\nRM0090 Rev 21\nFigure 323. SDIO (multiple) block write operation\nNote:\nThe SDIO does not send any data as long as the Busy signal is asserted (SDIO_D0 \npulled low).\nFigure 324. SDIO sequential read operation\nFigure 325. SDIO sequential write operation\nai14737b\nCommand\nResponse\nData block crc\nData block crc\nData stop operation\nFrom host to card From card to host\ndata from host to card\nStop command\nstops data transfer\nCommand\nResponse\nSDMMC_CMD\nSDMMC_D\nBusy\nBlock write operation\nBusy\nMultiple block write operation\nai14738b\nData stop operation\nFrom card to host\nStop command\nstops data transfer\nCommand\nResponse\nCommand\nResponse\nData stream\nData transfer operation\nFrom host to\ncard(s)\nData from card to host\nSDMMC_CMD\nSDMMC_D\nai14739b\nData stop operation\nFrom card to host\nStop command\nstops data transfer\nResponse\nCommand\nResponse\nCommand\nData stream\nData transfer operation\nFrom host to\ncard(s)\nData from host to card\nSDMMC_CMD\nSDMMC_D\n\n\n<>\n\nRM0090 Rev 21\n1025/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.3 \nSDIO functional description\nThe SDIO consists of two parts:\n•\nThe SDIO adapter block provides all functions specific to the MMC/SD/SD I/O card \nsuch as the clock generation unit, command and data transfer.\n•\nThe APB2 interface accesses the SDIO adapter registers, and generates interrupt and \nDMA request signals.\nFigure 326. SDIO block diagram\nBy default SDIO_D0 is used for data transfer. After initialization, the host can change the \ndatabus width.\nIf a MultiMediaCard is connected to the bus, SDIO_D0, SDIO_D[3:0] or SDIO_D[7:0] can be \nused for data transfer. MMC V3.31 or previous, supports only 1 bit of data so only SDIO_D0 \ncan be used.\nIf an SD or SD I/O card is connected to the bus, data transfer can be configured by the host \nto use SDIO_D0 or SDIO_D[3:0]. All data lines are operating in push-pull mode.\nSDIO_CMD has two operational modes:\n•\nOpen-drain for initialization (only for MMCV3.31 or previous)\n•\nPush-pull for command transfer (SD/SD I/O card MMC4.2 use push-pull drivers also for \ninitialization)\nSDIO_CK is the clock to the card: one bit is transferred on both command and data lines \nwith each clock cycle. \nThe SDIO uses two clock signals:\n•\nSDIO adapter clock SDIOCLK up to 50 MHz (48 MHz when in use with USB)\n•\nAPB2 bus clock (PCLK2)\nPCLK2 and SDIO_CK clock frequencies must respect the following condition:\nThe signals shown in Table 151 are used on the MultiMediaCard/SD/SD I/O card bus.\nai15898b\nAPB2 bus\nAPB2\nInterrupts and\nPCLK2\nSDMMC_CK\ninterface\nDMA request\nSDMMCCLK\nSDMMC_D[7:0]\nSDMMC_CMD\nSDMMC\nSDMMC \nadapter\nFrequenc PCLK2\n(\n)\n3\n8\n⁄\nFrequency SDIO_CK\n(\n)\n×\n≥\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1026/1757\nRM0090 Rev 21\n \n31.3.1 \nSDIO adapter\nFigure 327 shows a simplified block diagram of an SDIO adapter.\nFigure 327. SDIO adapter\nThe SDIO adapter is a multimedia/secure digital memory card bus master that provides an \ninterface to a multimedia card stack or to a secure digital memory card. It consists of five \nsubunits:\n•\nAdapter register block\n•\nControl unit\n•\nCommand path\n•\nData path\n•\nData FIFO\nNote:\nThe adapter registers and FIFO use the APB2 bus clock domain (PCLK2). The control unit, \ncommand path and data path use the SDIO adapter clock domain (SDIOCLK).\nAdapter register block\nThe adapter register block contains all system registers. This block also generates the \nsignals that clear the static flags in the multimedia card. The clear signals are generated \nwhen 1 is written into the corresponding bit location in the SDIO Clear register.\nTable 151. SDIO I/O definitions\nPin\nDirection\nDescription\nSDIO_CK\nOutput\nMultiMediaCard/SD/SDIO card clock. This pin is the clock from \nhost to card.\nSDIO_CMD\nBidirectional\nMultiMediaCard/SD/SDIO card command. This pin is the \nbidirectional command/response signal.\nSDIO_D[7:0]\nBidirectional\nMultiMediaCard/SD/SDIO card data. These pins are the \nbidirectional databus. \nai15899b\nTo APB2 \ninterface\nControl unit\nCommand \npath\nData path\nAdapter \nregisters\nSDMMC_CK\nSDMMC_CMD\nSDMMC_D[7:0]\nSDMMC adapter\nPCLK2\nSDMMCCLK\nFIFO\nCard bus\n\n\n<>\n\nRM0090 Rev 21\n1027/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nControl unit\nThe control unit contains the power management functions and the clock divider for the \nmemory card clock.\nThere are three power phases:\n•\npower-off\n•\npower-up\n•\npower-on\nFigure 328. Control unit\nThe control unit is illustrated in Figure 328. It consists of a power management subunit and \na clock management subunit.\nThe power management subunit disables the card bus output signals during the power-off \nand power-up phases.\nThe clock management subunit generates and controls the SDIO_CK signal. The SDIO_CK \noutput can use either the clock divide or the clock bypass mode. The clock output is \ninactive:\n•\nafter reset\n•\nduring the power-off or power-up phases\n•\nif the power saving mode is enabled and the card bus is in the Idle state (eight clock \nperiods after both the command and data path subunits enter the Idle phase)\nai14804b\nControl unit\nPower management\nClock management\nAdapter \nregisters\nSDMMC_CK\nTo command and data path\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1028/1757\nRM0090 Rev 21\nCommand path\nThe command path unit sends commands to and receives responses from the cards.\nFigure 329. SDIO adapter command path\n•\nCommand path state machine (CPSM)\n–\nWhen the command register is written to and the enable bit is set, command \ntransfer starts. When the command has been sent, the command path state \nmachine (CPSM) sets the status flags and enters the Idle state if a response is not \nrequired. If a response is required, it waits for the response (see Figure 330 on \npage 1029). When the response is received, the received CRC code and the \ninternally generated code are compared, and the appropriate status flags are set.\nai15900b\nAdapter registers\nCMD\nStatus\nflag\nCRC\nShift\nregister\nCMD\nTo control unit\nSDMMC_CMDin\nSDMMC_CMDout\nTo APB2 interface\nControl\nlogic\nCommand \ntimer\nArgument\nResponse\nregisters\n\n\n<>\n\nRM0090 Rev 21\n1029/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nFigure 330. Command path state machine (CPSM)\nWhen the Wait state is entered, the command timer starts running. If the timeout is reached \nbefore the CPSM moves to the Receive state, the timeout flag is set and the Idle state is \nentered.\nNote:\nThe command timeout has a fixed value of 64 SDIO_CK clock periods.\nIf the interrupt bit is set in the command register, the timer is disabled and the CPSM waits \nfor an interrupt request from one of the cards. If a pending bit is set in the command register, \nthe CPSM enters the Pend state, and waits for a CmdPend signal from the data path \nsubunit. When CmdPend is detected, the CPSM moves to the Send state. This enables the \ndata counter to trigger the stop command transmission.\nNote:\nThe CPSM remains in the Idle state for at least eight SDIO_CK periods to meet the NCC and \nNRC timing constraints. NCC is the minimum delay between two host commands, and NRC is \nthe minimum delay between the host command and the card response.\nIdle\nPend\nSend\nWait\nReceive\nLast Data\nCPSM\ndisabled\nEnabled and\ncommand start\nCPSM disabled or \nno response\nWait for response\nResponse\nstarted\nResponse received or\ndisabled or command \nCRC failed\nCPSM Disabled or\ncommand timeout\nCPSM Enabled and\npending command\nai14806b\nWait_CPL\nResponse Received in CE-ATA\nmode and no interrupt and\nwait for CE-ATA Command\nCompletion signal enabled\nResponse Received in CE-ATA mode and\nno interrupt and wait for CE-ATA\nCommand Completion signal disabled\nCE-ATA Command\nCompletion signal\nreceived or\nCPSM disabled or\nCommand CRC failed\nOn reset\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1030/1757\nRM0090 Rev 21\nFigure 331. SDIO command transfer\n•\nCommand format\n–\nCommand: a command is a token that starts an operation. Command are sent \nfrom the host either to a single card (addressed command) or to all connected \ncards (broadcast command are available for MMC V3.31 or previous). Commands \nare transferred serially on the CMD line. All commands have a fixed length of 48 \nbits. The general format for a command token for MultiMediaCards, SD-Memory \ncards and SDIO-Cards is shown in Table 152. CE-ATA commands are an \nextension of MMC commands V4.2, and so have the same format.\nThe command path operates in a half-duplex mode, so that commands and \nresponses can either be sent or received. If the CPSM is not in the Send state, the \nSDIO_CMD output is in the Hi-Z state, as shown in Figure 331 on page 1030. \nData on SDIO_CMD are synchronous with the rising edge of SDIO_CK. Table 152 \nshows the command format.\n \n–\nResponse: a response is a token that is sent from an addressed card (or \nsynchronously from all connected cards for MMC V3.31 or previous), to the host \nas an answer to a previously received command. Responses are transferred \nserially on the CMD line.\nThe SDIO supports two response types. Both use CRC error checking:\n•\n48 bit short response\n•\n136 bit long response\nNote:\nIf the response does not contain a CRC (CMD1 response), the device driver must ignore the \nCRC failed status.\nTable 152. Command format\nBit position\nWidth\nValue\nDescription\n47\n1\n0\nStart bit\n46\n1\n1\nTransmission bit\n[45:40]\n6\n-\nCommand index\n[39:8]\n32\n-\nArgument\n[7:1]\n7\n-\nCRC7\n0\n1\n1\nEnd bit\nai14807b\nSDMMC_CK\nSDMMC_CMD\nCommand\nResponse\nCommand\nState\nIdle\nSend\nWait\nReceive\nIdle\nSend\nHi-Z\nController drives\nHi-Z\nCard drives\nHi-Z\nController drives\nat least 8 SDMMC_CK \ncycles\n\n\n<>\n\nRM0090 Rev 21\n1031/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n \n \nThe command register contains the command index (six bits sent to a card) and the \ncommand type. These determine whether the command requires a response, and whether \nthe response is 48 or 136 bits long (see Section 31.9.4 on page 1065). The command path \nimplements the status flags shown in Table 155:\n \nThe CRC generator calculates the CRC checksum for all bits before the CRC code. This \nincludes the start bit, transmitter bit, command index, and command argument (or card \nstatus). The CRC checksum is calculated for the first 120 bits of CID or CSD for the long \nresponse format. Note that the start bit, transmitter bit and the six reserved bits are not used \nin the CRC calculation.\nThe CRC checksum is a 7-bit value:\n CRC[6:0] = Remainder [(M(x) * x7) / G(x)]\nG(x) = x7 + x3 + 1\nM(x) = (start bit) * x39 + ... + (last bit before CRC) * x0, or\nM(x) = (start bit) * x119 + ... + (last bit before CRC) * x0\nTable 153. Short response format\nBit position\nWidth\nValue\nDescription\n47\n1\n0\nStart bit\n46\n1\n0\nTransmission bit\n[45:40]\n6\n-\nCommand index\n[39:8]\n32\n-\nArgument\n[7:1]\n7\n-\nCRC7(or 1111111)\n0\n1\n1\nEnd bit\nTable 154. Long response format\nBit position\nWidth\nValue\nDescription\n135\n1\n0\nStart bit\n134\n1\n0\nTransmission bit\n[133:128]\n6\n111111\nReserved\n[127:1]\n127\n-\nCID or CSD (including internal CRC7)\n0\n1\n1\nEnd bit\nTable 155. Command path status flags\nFlag\nDescription\nCMDREND\nSet if response CRC is OK.\nCCRCFAIL\nSet if response CRC fails.\nCMDSENT\nSet when command (that does not require response) is sent\nCTIMEOUT\nResponse timeout.\nCMDACT\nCommand transfer in progress.\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1032/1757\nRM0090 Rev 21\nData path\nThe data path subunit transfers data to and from cards. Figure 332 shows a block diagram \nof the data path.\nFigure 332. Data path\nThe card databus width can be programmed using the clock control register. If the 4-bit wide \nbus mode is enabled, data is transferred at four bits per clock cycle over all four data signals \n(SDIO_D[3:0]). If the 8-bit wide bus mode is enabled, data is transferred at eight bits per \nclock cycle over all eight data signals (SDIO_D[7:0]). If the wide bus mode is not enabled, \nonly one bit per clock cycle is transferred over SDIO_D0.\nDepending on the transfer direction (send or receive), the data path state machine (DPSM) \nmoves to the Wait_S or Wait_R state when it is enabled:\n•\nSend: the DPSM moves to the Wait_S state. If there is data in the transmit FIFO, the \nDPSM moves to the Send state, and the data path subunit starts sending data to a \ncard.\n•\nReceive: the DPSM moves to the Wait_R state and waits for a start bit. When it \nreceives a start bit, the DPSM moves to the Receive state, and the data path subunit \nstarts receiving data from a card.\nData path state machine (DPSM)\nThe DPSM operates at SDIO_CK frequency. Data on the card bus signals is synchronous to \nthe rising edge of SDIO_CK. The DPSM has six states, as shown in Figure 333: Data path \nstate machine (DPSM).\nai14808b\nData path\nData FIFO\nTransmit\nStatus\nflag\nCRC\nShift\nregister\nTo control unit\nSDMMC_Din[7:0]\nSDMMC_Dout[7:0]\nReceive\nControl\nlogic\nData\ntimer\n\n\n<>\n\nRM0090 Rev 21\n1033/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nFigure 333. Data path state machine (DPSM)\n•\nIdle: the data path is inactive, and the SDIO_D[7:0] outputs are in Hi-Z. When the data \ncontrol register is written and the enable bit is set, the DPSM loads the data counter \nwith a new value and, depending on the data direction bit, moves to either the Wait_S \nor the Wait_R state.\n•\nWait_R: if the data counter equals zero, the DPSM moves to the Idle state when the \nreceive FIFO is empty. If the data counter is not zero, the DPSM waits for a start bit on \nSDIO_D. The DPSM moves to the Receive state if it receives a start bit before a \ntimeout, and loads the data block counter. If it reaches a timeout before it detects a \nstart bit, or a start bit error occurs, it moves to the Idle state and sets the timeout status \nflag.\n•\nReceive: serial data received from a card is packed in bytes and written to the data \nFIFO. Depending on the transfer mode bit in the data control register, the data transfer \nmode can be either block or stream:\n–\nIn block mode, when the data block counter reaches zero, the DPSM waits until it \nreceives the CRC code. If the received code matches the internally generated \nIdle\nBusy\nSend\nWait_R\nReceive\nEnd of packet\nDisabled or CRC fail\nor timeout\nNot busy\nDisabled or\nend of data\nData ready\nEnd of packet or\nend of data or\nFIFO overrun\nEnable and not send\nDisabled or\nRx FIFO empty or timeout or\nstart bit error\nDisabled or FIFO underrun or\nend of data or CRC fail\nai14809b\nWait_S\nStart bit\nOn reset\nDisabled or CRC fail\nEnable and send\nDPSM disabled\nRead Wait\nDPSM enabled and\nRead Wait Started\nand SD I/O mode enabled\nReadWait Stop\nData received and\nRead Wait Started and\nSD I/O mode enabled\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1034/1757\nRM0090 Rev 21\nCRC code, the DPSM moves to the Wait_R state. If not, the CRC fail status flag is \nset and the DPSM moves to the Idle state.\n–\nIn stream mode, the DPSM receives data while the data counter is not zero. When \nthe counter is zero, the remaining data in the shift register is written to the data \nFIFO, and the DPSM moves to the Wait_R state.\nIf a FIFO overrun error occurs, the DPSM sets the FIFO error flag and moves to the \nIdle state:\n•\nWait_S: the DPSM moves to the Idle state if the data counter is zero. If not, it waits until \nthe data FIFO empty flag is deasserted, and moves to the Send state.\nNote:\nThe DPSM remains in the Wait_S state for at least two clock periods to meet the NWR timing \nrequirements, where NWR is the number of clock cycles between the reception of the card \nresponse and the start of the data transfer from the host.\n•\nSend: the DPSM starts sending data to a card. Depending on the transfer mode bit in \nthe data control register, the data transfer mode can be either block or stream:\n–\nIn block mode, when the data block counter reaches zero, the DPSM sends an \ninternally generated CRC code and end bit, and moves to the Busy state.\n–\nIn stream mode, the DPSM sends data to a card while the enable bit is high and \nthe data counter is not zero. It then moves to the Idle state.\nIf a FIFO underrun error occurs, the DPSM sets the FIFO error flag and moves to the \nIdle state.\n•\nBusy: the DPSM waits for the CRC status flag:\n–\nIf it does not receive a positive CRC status, it moves to the Idle state and sets the \nCRC fail status flag.\n–\nIf it receives a positive CRC status, it moves to the Wait_S state if SDIO_D0 is not \nlow (the card is not busy).\nIf a timeout occurs while the DPSM is in the Busy state, it sets the data timeout flag and \nmoves to the Idle state.\nThe data timer is enabled when the DPSM is in the Wait_R or Busy state, and \ngenerates the data timeout error:\n–\nWhen transmitting data, the timeout occurs if the DPSM stays in the Busy state for \nlonger than the programmed timeout period\n–\nWhen receiving data, the timeout occurs if the end of the data is not true, and if the \nDPSM stays in the Wait_R state for longer than the programmed timeout period.\n•\nData: data can be transferred from the card to the host or vice versa. Data is \ntransferred via the data lines. They are stored in a FIFO of 32 words, each word is 32 \nbits wide.\n \nTable 156. Data token format\nDescription\nStart bit\nData\nCRC16\nEnd bit\nBlock Data\n0\n-\nyes\n1\nStream Data\n0\n-\nno\n1\n\n\n<>\n\nRM0090 Rev 21\n1035/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nData FIFO\nThe data FIFO (first-in-first-out) subunit is a data buffer with a transmit and receive unit.\nThe FIFO contains a 32-bit wide, 32-word deep data buffer, and transmit and receive logic. \nBecause the data FIFO operates in the APB2 clock domain (PCLK2), all signals from the \nsubunits in the SDIO clock domain (SDIOCLK) are resynchronized.\nDepending on the TXACT and RXACT flags, the FIFO can be disabled, transmit enabled, or \nreceive enabled. TXACT and RXACT are driven by the data path subunit and are mutually \nexclusive:\n–\nThe transmit FIFO refers to the transmit logic and data buffer when TXACT is \nasserted\n–\nThe receive FIFO refers to the receive logic and data buffer when RXACT is \nasserted\n•\nTransmit FIFO:\nData can be written to the transmit FIFO through the APB2 interface when the SDIO is \nenabled for transmission.\nThe transmit FIFO is accessible via 32 sequential addresses. The transmit FIFO \ncontains a data output register that holds the data word pointed to by the read pointer. \nWhen the data path subunit has loaded its shift register, it increments the read pointer \nand drives new data out.\nIf the transmit FIFO is disabled, all status flags are deasserted. The data path subunit \nasserts TXACT when it transmits data.\n \n•\nReceive FIFO\nWhen the data path subunit receives a word of data, it drives the data on the write \ndatabus. The write pointer is incremented after the write operation completes. On the \nread side, the contents of the FIFO word pointed to by the current value of the read \npointer is driven onto the read databus. If the receive FIFO is disabled, all status flags \nare deasserted, and the read and write pointers are reset. The data path subunit \nasserts RXACT when it receives data. Table 158 lists the receive FIFO status flags. \nThe receive FIFO is accessible via 32 sequential addresses.\nTable 157. Transmit FIFO status flags\nFlag\nDescription\nTXFIFOF\nSet to high when all 32 transmit FIFO words contain valid data.\nTXFIFOE\nSet to high when the transmit FIFO does not contain valid data.\nTXFIFOHE\nSet to high when 8 or more transmit FIFO words are empty. This flag can be used \nas a DMA request.\nTXDAVL\nSet to high when the transmit FIFO contains valid data. This flag is the inverse of \nthe TXFIFOE flag.\nTXUNDERR\nSet to high when an underrun error occurs. This flag is cleared by writing to the \nSDIO Clear register.\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1036/1757\nRM0090 Rev 21\n \n31.3.2 \nSDIO APB2 interface\nThe APB2 interface generates the interrupt and DMA requests, and accesses the SDIO \nadapter registers and the data FIFO. It consists of a data path, register decoder, and \ninterrupt/DMA logic.\nSDIO interrupts\nThe interrupt logic generates an interrupt request signal that is asserted when at least one \nof the selected status flags is high. A mask register is provided to allow selection of the \nconditions that generate an interrupt. A status flag generates the interrupt request if a \ncorresponding mask flag is set.\nSDIO/DMA interface - procedure for data transfers between the SDIO and \nmemory\nIn the example shown, the transfer is from the SDIO host controller to an MMC (512 bytes \nusing CMD24 (WRITE_BLOCK). The SDIO FIFO is filled by data stored in a memory using \nthe DMA controller.\n1.\nDo the card identification process\n2. \nIncrease the SDIO_CK frequency\n3. \nSelect the card by sending CMD7\n4. \nConfigure the DMA2 as follows:\na) \nEnable DMA2 controller and clear any pending interrupts.\nb) \nProgram the DMA2_Stream3 or DMA2_Stream6 Channel4 source address \nregister with the memory location’s base address and DMA2_Stream3 or \nTable 158. Receive FIFO status flags\nFlag\nDescription\nRXFIFOF\nSet to high when all 32 receive FIFO words contain valid data\nRXFIFOE\nSet to high when the receive FIFO does not contain valid data. \nRXFIFOHF\n Set to high when 8 or more receive FIFO words contain valid data. This flag can be \nused as a DMA request.\nRXDAVL\nSet to high when the receive FIFO is not empty. This flag is the inverse of the \nRXFIFOE flag.\nRXOVERR\nSet to high when an overrun error occurs. This flag is cleared by writing to the SDIO \nClear register.\n\n\n<>\n\nRM0090 Rev 21\n1037/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nDMA2_Stream6 Channel4 destination address register with the SDIO_FIFO \nregister address.\nc) \nProgram DMA2_Stream3 or DMA2_Stream6 Channel4 control register (memory \nincrement, not peripheral increment, peripheral and source width is word size).\nd) \nProgram DMA2_Stream3 or DMA2_Stream6 Channel4 to select the peripheral as \nflow controller (set PFCTRL bit in DMA_S3CR or DMA_S6CR configuration \nregister).\ne) \nConfigure the incremental burst transfer to 4 beats (at least from peripheral side) \nin DMA2_Stream3 or DMA2_Stream6 Channel4.\nf) \nEnable DMA2_Stream3 or DMA2_Stream6 Channel4\n5. \nSend CMD24 (WRITE_BLOCK) as follows:\na) \nProgram the SDIO data length register (SDIO data timer register should be \nalready programmed before the card identification process).\nb) \nProgram the SDIO argument register with the address location of the card where \ndata is to be transferred.\nc) \nProgram the SDIO command register: CmdIndex with 24 (WRITE_BLOCK); \nWaitResp with ‘1’ (SDIO card host waits for a response); CPSMEN with ‘1’ (SDIO \ncard host enabled to send a command). Other fields are at their reset value.\nd) \nWait for SDIO_STA[6] = CMDREND interrupt, then program the SDIO data control \nregister: DTEN with ‘1’ (SDIO card host enabled to send data); DTDIR with ‘0’ \n(from controller to card); DTMODE with ‘0’ (block data transfer); DMAEN with ‘1’ \n(DMA enabled); DBLOCKSIZE with 0x9 (512 bytes). Other fields are don’t care.\ne) \nWait for SDIO_STA[10] = DBCKEND.\n6. \nCheck that no channels are still enabled by polling the DMA Enabled Channel Status \nregister.\n31.4 \nCard functional description\n31.4.1 \nCard identification mode\nWhile in card identification mode the host resets all cards, validates the operation voltage \nrange, identifies cards and sets a relative card address (RCA) for each card on the bus. All \ndata communications in the card identification mode use the command line (CMD) only.\n31.4.2 \nCard reset\nThe GO_IDLE_STATE command (CMD0) is the software reset command and it puts the \nMultiMediaCard and SD memory in the Idle state. The IO_RW_DIRECT command (CMD52) \nresets the SD I/O card. After power-up or CMD0, all cards output bus drivers are in the high-\nimpedance state and the cards are initialized with a default relative card address \n(RCA=0x0001) and with a default driver stage register setting (lowest speed, highest driving \ncurrent capability).\n31.4.3 \nOperating voltage range validation\nAll cards can communicate with the SDIO card host using any operating voltage within the \nspecification range. The supported minimum and maximum VDD values are defined in the \noperation conditions register (OCR) on the card.\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1038/1757\nRM0090 Rev 21\nCards that store the card identification number (CID) and card specific data (CSD) in the \npayload memory are able to communicate this information only under data-transfer VDD \nconditions. When the SDIO card host module and the card have incompatible VDD ranges, \nthe card is not able to complete the identification cycle and cannot send CSD data. For this \npurpose, the special commands, SEND_OP_COND (CMD1), SD_APP_OP_COND (ACMD41 \nfor SD Memory), and IO_SEND_OP_COND (CMD5 for SD I/O), are designed to provide a \nmechanism to identify and reject cards that do not match the VDD range desired by the \nSDIO card host. The SDIO card host sends the required VDD voltage window as the \noperand of these commands. Cards that cannot perform data transfer in the specified range \ndisconnect from the bus and go to the inactive state.\nBy using these commands without including the voltage range as the operand, the SDIO \ncard host can query each card and determine the common voltage range before placing out-\nof-range cards in the inactive state. This query is used when the SDIO card host is able to \nselect a common voltage range or when the user requires notification that cards are not \nusable.\n31.4.4 \nCard identification process\nThe card identification process differs for MultiMediaCards and SD cards. For \nMultiMediaCard cards, the identification process starts at clock rate Fod. The SDIO_CMD \nline output drivers are open-drain and allow parallel card operation during this process. The \nregistration process is accomplished as follows:\n1.\nThe bus is activated.\n2. \nThe SDIO card host broadcasts SEND_OP_COND (CMD1) to receive operation \nconditions.\n3. \nThe response is the wired AND operation of the operation condition registers from all \ncards.\n4. \nIncompatible cards are placed in the inactive state.\n5. \nThe SDIO card host broadcasts ALL_SEND_CID (CMD2) to all active cards.\n6. \nThe active cards simultaneously send their CID numbers serially. Cards with outgoing \nCID bits that do not match the bits on the command line stop transmitting and must wait \nfor the next identification cycle. One card successfully transmits a full CID to the SDIO \ncard host and enters the Identification state.\n7. \nThe SDIO card host issues SET_RELATIVE_ADDR (CMD3) to that card. This new \naddress is called the relative card address (RCA); it is shorter than the CID and \naddresses the card. The assigned card changes to the Standby state, it does not react \nto further identification cycles, and its output switches from open-drain to push-pull.\n8. \nThe SDIO card host repeats steps 5 through 7 until it receives a timeout condition.\nFor the SD card, the identification process starts at clock rate Fod, and the SDIO_CMD line \noutput drives are push-pull drivers instead of open-drain. The registration process is \naccomplished as follows:\n\n\n<>\n\nRM0090 Rev 21\n1039/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n1.\nThe bus is activated.\n2. \nThe SDIO card host broadcasts SD_APP_OP_COND (ACMD41).\n3. \nThe cards respond with the contents of their operation condition registers.\n4. \nThe incompatible cards are placed in the inactive state.\n5. \nThe SDIO card host broadcasts ALL_SEND_CID (CMD2) to all active cards.\n6. \nThe cards send back their unique card identification numbers (CIDs) and enter the \nIdentification state.\n7. \nThe SDIO card host issues SET_RELATIVE_ADDR (CMD3) to an active card with an \naddress. This new address is called the relative card address (RCA); it is shorter than \nthe CID and addresses the card. The assigned card changes to the Standby state. The \nSDIO card host can reissue this command to change the RCA. The RCA of the card is \nthe last assigned value.\n8. \nThe SDIO card host repeats steps 5 through 7 with all active cards.\nFor the SD I/O card, the registration process is accomplished as follows:\n1.\nThe bus is activated.\n2. \nThe SDIO card host sends IO_SEND_OP_COND (CMD5).\n3. \nThe cards respond with the contents of their operation condition registers.\n4. \nThe incompatible cards are set to the inactive state.\n5. \nThe SDIO card host issues SET_RELATIVE_ADDR (CMD3) to an active card with an \naddress. This new address is called the relative card address (RCA); it is shorter than \nthe CID and addresses the card. The assigned card changes to the Standby state. The \nSDIO card host can reissue this command to change the RCA. The RCA of the card is \nthe last assigned value.\n31.4.5 \nBlock write\nDuring block write (CMD24 - 27) one or more blocks of data are transferred from the host to \nthe card with a CRC appended to the end of each block by the host. A card supporting block \nwrite is always able to accept a block of data defined by WRITE_BL_LEN. If the CRC fails, \nthe card indicates the failure on the SDIO_D line and the transferred data are discarded and \nnot written, and all further transmitted blocks (in multiple block write mode) are ignored.\nIf the host uses partial blocks whose accumulated length is not block aligned and, block \nmisalignment is not allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card \ndetects the block misalignment error before the beginning of the first misaligned block. \n(ADDRESS_ERROR error bit is set in the status register). The write operation is also \naborted if the host tries to write over a write-protected area. In this case, however, the card \nsets the WP_VIOLATION bit.\nProgramming of the CID and CSD registers does not require a previous block length setting. \nThe transferred data is also CRC protected. If a part of the CSD or CID register is stored in \nROM, then this unchangeable part must match the corresponding part of the receive buffer. \nIf this match fails, then the card reports an error and does not change any register contents. \nSome cards may require long and unpredictable times to write a block of data. After \nreceiving a block of data and completing the CRC check, the card begins writing and holds \nthe SDIO_D line low if its write buffer is full and unable to accept new data from a new \nWRITE_BLOCK command. The host may poll the status of the card with a SEND_STATUS \ncommand (CMD13) at any time, and the card responds with its status. The \nREADY_FOR_DATA status bit indicates whether the card can accept new data or whether \nthe write process is still in progress. The host may deselect the card by issuing CMD7 (to \n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1040/1757\nRM0090 Rev 21\nselect a different card), which places the card in the Disconnect state and release the \nSDIO_D line(s) without interrupting the write operation. When selecting the card again, it \nreactivates busy indication by pulling SDIO_D to low if programming is still in progress and \nthe write buffer is unavailable.\n31.4.6 \nBlock read\nIn Block read mode the basic unit of data transfer is a block whose maximum size is defined \nin the CSD (READ_BL_LEN). If READ_BL_PARTIAL is set, smaller blocks whose start and \nend addresses are entirely contained within one physical block (as defined by \nREAD_BL_LEN) may also be transmitted. A CRC is appended to the end of each block, \nensuring data transfer integrity. CMD17 (READ_SINGLE_BLOCK) initiates a block read and \nafter completing the transfer, the card returns to the Transfer state.\nCMD18 (READ_MULTIPLE_BLOCK) starts a transfer of several consecutive blocks.\nThe host can abort reading at any time, within a multiple block operation, regardless of its \ntype. Transaction abort is done by sending the stop transmission command.\nIf the card detects an error (for example, out of range, address misalignment or internal \nerror) during a multiple block read operation (both types) it stops the data transmission and \nremains in the data state. The host must than abort the operation by sending the stop \ntransmission command. The read error is reported in the response to the stop transmission \ncommand.\nIf the host sends a stop transmission command after the card transmits the last block of a \nmultiple block operation with a predefined number of blocks, it is responded to as an illegal \ncommand, since the card is no longer in the data state. If the host uses partial blocks whose \naccumulated length is not block-aligned and block misalignment is not allowed, the card \ndetects a block misalignment error condition at the beginning of the first misaligned block \n(ADDRESS_ERROR error bit is set in the status register).\n31.4.7 \nStream access, stream write and stream read \n(MultiMediaCard only)\nIn stream mode, data is transferred in bytes and no CRC is appended at the end of each \nblock.\nStream write (MultiMediaCard only)\nWRITE_DAT_UNTIL_STOP (CMD20) starts the data transfer from the SDIO card host to the \ncard, beginning at the specified address and continuing until the SDIO card host issues a \nstop command. When partial blocks are allowed (CSD parameter WRITE_BL_PARTIAL is \nset), the data stream can start and stop at any address within the card address space, \notherwise it can only start and stop at block boundaries. Because the amount of data to be \ntransferred is not determined in advance, a CRC cannot be used. When the end of the \nmemory range is reached while sending data and no stop command is sent by the SD card \nhost, any additional transferred data are discarded.\n\n\n<>\n\nRM0090 Rev 21\n1041/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nThe maximum clock frequency for a stream write operation is given by the following \nequation fields of the card-specific data register:\n•\nMaximumspeed = maximum write frequency\n•\nTRANSPEED = maximum data transfer rate\n•\nwritebllen = maximum write data block length\n•\nNSAC = data read access time 2 in CLK cycles\n•\nTAAC = data read access time 1\n•\nR2WFACTOR = write speed factor\nIf the host attempts to use a higher frequency, the card may not be able to process the data \nand stop programming, set the OVERRUN error bit in the status register, and while ignoring \nall further data transfer, wait (in the receive data state) for a stop command. The write \noperation is also aborted if the host tries to write over a write-protected area. In this case, \nhowever, the card sets the WP_VIOLATION bit.\nStream read (MultiMediaCard only)\nREAD_DAT_UNTIL_STOP (CMD11) controls a stream-oriented data transfer.\nThis command instructs the card to send its data, starting at a specified address, until the \nSDIO card host sends STOP_TRANSMISSION (CMD12). The stop command has an \nexecution delay due to the serial command transmission and the data transfer stops after \nthe end bit of the stop command. When the end of the memory range is reached while \nsending data and no stop command is sent by the SDIO card host, any subsequent data \nsent are considered undefined.\nThe maximum clock frequency for a stream read operation is given by the following \nequation and uses fields of the card specific data register.\n•\nMaximumspeed = maximum read frequency\n•\nTRANSPEED = maximum data transfer rate\n•\nreadbllen = maximum read data block length\n•\nwritebllen = maximum write data block length\n•\nNSAC = data read access time 2 in CLK cycles\n•\nTAAC = data read access time 1\n•\nR2WFACTOR = write speed factor\nIf the host attempts to use a higher frequency, the card is not able to sustain data transfer. If \nthis happens, the card sets the UNDERRUN error bit in the status register, aborts the \ntransmission and waits in the data state for a stop command.\nMaximumspeed\nMIN TRANSPEED 8\n2writebllen\n×\n(\n)\nNSAC\n–\n(\n)\nTAAC\nR2WFACTOR\n×\n-------------------------------------------------------------------------\n(\n,\n)\n=\nMaximumspeed\nMIN TRANSPEED 8\n2readbllen\n×\n(\n)\nNSAC\n–\n(\n)\nTAAC\nR2WFACTOR\n×\n------------------------------------------------------------------------\n(\n,\n)\n=\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1042/1757\nRM0090 Rev 21\n31.4.8 \nErase: group erase and sector erase\nThe erasable unit of the MultiMediaCard is the erase group. The erase group is measured in \nwrite blocks, which are the basic writable units of the card. The size of the erase group is a \ncard-specific parameter and defined in the CSD.\nThe host can erase a contiguous range of Erase Groups. Starting the erase process is a \nthree-step sequence.\nFirst the host defines the start address of the range using the ERASE_GROUP_START \n(CMD35) command, next it defines the last address of the range using the \nERASE_GROUP_END (CMD36) command and, finally, it starts the erase process by issuing \nthe ERASE (CMD38) command. The address field in the erase commands is an Erase \nGroup address in byte units. The card ignores all LSBs below the Erase Group size, \neffectively rounding the address down to the Erase Group boundary.\nIf an erase command is received out of sequence, the card sets the ERASE_SEQ_ERROR \nbit in the status register and resets the whole sequence.\nIf an out-of-sequence (neither of the erase commands, except SEND_STATUS) command \nreceived, the card sets the ERASE_RESET status bit in the status register, resets the erase \nsequence and executes the last command.\nIf the erase range includes write protected blocks, they are left intact and only unprotected \nblocks are erased. The WP_ERASE_SKIP status bit in the status register is set.\nThe card indicates that an erase is in progress by holding SDIO_D low. The actual erase \ntime may be quite long, and the host may issue CMD7 to deselect the card.\n31.4.9 \nWide bus selection or deselection\nWide bus (4-bit bus width) operation mode is selected or deselected using \nSET_BUS_WIDTH (ACMD6). The default bus width after power-up or GO_IDLE_STATE \n(CMD0) is 1 bit. SET_BUS_WIDTH (ACMD6) is only valid in a transfer state, which means \nthat the bus width can be changed only after a card is selected by \nSELECT/DESELECT_CARD (CMD7).\n31.4.10 \nProtection management\nThree write protection methods for the cards are supported in the SDIO card host module:\n1.\ninternal card write protection (card responsibility)\n2. \nmechanical write protection switch (SDIO card host module responsibility only)\n3. \npassword-protected card lock operation\nInternal card write protection\nCard data can be protected against write and erase. By setting the permanent or temporary \nwrite-protect bits in the CSD, the entire card can be permanently write-protected by the \nmanufacturer or content provider. For cards that support write protection of groups of \nsectors by setting the WP_GRP_ENABLE bit in the CSD, portions of the data can be \nprotected, and the write protection can be changed by the application. The write protection \nis in units of WP_GRP_SIZE sectors as specified in the CSD. The SET_WRITE_PROT and \nCLR_WRITE_PROT commands control the protection of the addressed group. The \nSEND_WRITE_PROT command is similar to a single block read command. The card sends \na data block containing 32 write protection bits (representing 32 write protect groups starting \n\n\n<>\n\nRM0090 Rev 21\n1043/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nat the specified address) followed by 16 CRC bits. The address field in the write protect \ncommands is a group address in byte units.\nThe card ignores all LSBs below the group size.\nMechanical write protect switch\nA mechanical sliding tab on the side of the card allows the user to set or clear the write \nprotection on a card. When the sliding tab is positioned with the window open, the card is \nwrite-protected, and when the window is closed, the card contents can be changed. A \nmatched switch on the socket side indicates to the SDIO card host module that the card is \nwrite-protected. The SDIO card host module is responsible for protecting the card. The \nposition of the write protect switch is unknown to the internal circuitry of the card.\nPassword protect\nThe password protection feature enables the SDIO card host module to lock and unlock a \ncard with a password. The password is stored in the 128-bit PWD register and its size is set \nin the 8-bit PWD_LEN register. These registers are nonvolatile so that a power cycle does \nnot erase them. Locked cards respond to and execute certain commands. This means that \nthe SDIO card host module is allowed to reset, initialize, select, and query for status, \nhowever it is not allowed to access data on the card. When the password is set (as indicated \nby a nonzero value of PWD_LEN), the card is locked automatically after power-up. As with \nthe CSD and CID register write commands, the lock/unlock commands are available in the \ntransfer state only. In this state, the command does not include an address argument and \nthe card must be selected before using it. The card lock/unlock commands have the \nstructure and bus transaction types of a regular single-block write command. The \ntransferred data block includes all of the required information for the command (the \npassword setting mode, the PWD itself, and card lock/unlock). The command data block \nsize is defined by the SDIO card host module before it sends the card lock/unlock \ncommand, and has the structure shown in Table 172.\nThe bit settings are as follows:\n•\nERASE: setting it forces an erase operation. All other bits must be zero, and only the \ncommand byte is sent\n•\nLOCK_UNLOCK: setting it locks the card. LOCK_UNLOCK can be set simultaneously \nwith SET_PWD, however not with CLR_PWD\n•\nCLR_PWD: setting it clears the password data\n•\nSET_PWD: setting it saves the password data to memory\n•\nPWD_LEN: it defines the length of the password in bytes\n•\nPWD: the password (new or currently used, depending on the command)\nThe following sections list the command sequences to set/reset a password, lock/unlock the \ncard, and force an erase.\nSetting the password\n1.\nSelect a card (SELECT/DESELECT_CARD, CMD7), if none is already selected.\n2. \nDefine the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card \nlock/unlock mode, the 8-bit PWD_LEN, and the number of bytes of the new password. \n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1044/1757\nRM0090 Rev 21\nWhen a password replacement is done, the block size must take into account that both \nthe old and the new passwords are sent with the command.\n3. \nSend LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line \nincluding the 16-bit CRC. The data block indicates the mode (SET_PWD = 1), the \nlength (PWD_LEN), and the password (PWD) itself. When a password replacement is \ndone, the length value (PWD_LEN) includes the length of both passwords, the old and \nthe new one, and the PWD field includes the old password (currently used) followed by \nthe new password.\n4. \nWhen the password is matched, the new password and its size are saved into the PWD \nand PWD_LEN fields, respectively. When the old password sent does not correspond \n(in size and/or content) to the expected password, the LOCK_UNLOCK_FAILED error \nbit is set in the card status register, and the password is not changed.\nThe password length field (PWD_LEN) indicates whether a password is currently set. When \nthis field is nonzero, there is a password set and the card locks itself after power-up. It is \npossible to lock the card immediately in the current power session by setting the \nLOCK_UNLOCK bit (while setting the password) or sending an additional command for card \nlocking.\nResetting the password\n1.\nSelect a card (SELECT/DESELECT_CARD, CMD7), if none is already selected.\n2. \nDefine the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card \nlock/unlock mode, the 8-bit PWD_LEN, and the number of bytes in the currently used \npassword.\n3. \nSend LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line \nincluding the 16-bit CRC. The data block indicates the mode (CLR_PWD = 1), the \nlength (PWD_LEN) and the password (PWD) itself. The LOCK_UNLOCK bit is ignored.\n4. \nWhen the password is matched, the PWD field is cleared and PWD_LEN is set to 0. \nWhen the password sent does not correspond (in size and/or content) to the expected \npassword, the LOCK_UNLOCK_FAILED error bit is set in the card status register, and \nthe password is not changed.\nLocking a card\n1.\nSelect a card (SELECT/DESELECT_CARD, CMD7), if none is already selected.\n2. \nDefine the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card \nlock/unlock mode (byte 0 in Table 172), the 8-bit PWD_LEN, and the number of bytes \nof the current password.\n3. \nSend LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line \nincluding the 16-bit CRC. The data block indicates the mode (LOCK_UNLOCK = 1), the \nlength (PWD_LEN), and the password (PWD) itself.\n4. \nWhen the password is matched, the card is locked and the CARD_IS_LOCKED status \nbit is set in the card status register. When the password sent does not correspond (in \nsize and/or content) to the expected password, the LOCK_UNLOCK_FAILED error bit \nis set in the card status register, and the lock fails.\nIt is possible to set the password and to lock the card in the same sequence. In this case, \nthe SDIO card host module performs all the required steps for setting the password (see \nSetting the password on page 1043), however it is necessary to set the LOCK_UNLOCK bit \nin Step 3 when the new password command is sent.\n\n\n<>\n\nRM0090 Rev 21\n1045/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nWhen the password is previously set (PWD_LEN is not 0), the card is locked automatically \nafter power-on reset. An attempt to lock a locked card or to lock a card that does not have a \npassword fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register.\nUnlocking the card\n1.\nSelect a card (SELECT/DESELECT_CARD, CMD7), if none is already selected.\n2. \nDefine the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit \ncardlock/unlock mode (byte 0 in Table 172), the 8-bit PWD_LEN, and the number of \nbytes of the current password.\n3. \nSend LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line \nincluding the 16-bit CRC. The data block indicates the mode (LOCK_UNLOCK = 0), the \nlength (PWD_LEN), and the password (PWD) itself.\n4. \nWhen the password is matched, the card is unlocked and the CARD_IS_LOCKED \nstatus bit is cleared in the card status register. When the password sent is not correct in \nsize and/or content and does not correspond to the expected password, the \nLOCK_UNLOCK_FAILED error bit is set in the card status register, and the card \nremains locked.\nThe unlocking function is only valid for the current power session. When the PWD field is not \nclear, the card is locked automatically on the next power-up.\nAn attempt to unlock an unlocked card fails and the LOCK_UNLOCK_FAILED error bit is set \nin the card status register.\nForcing erase\nIf the user has forgotten the password (PWD content), it is possible to access the card after \nclearing all the data on the card. This forced erase operation erases all card data and all \npassword data.\n1.\nSelect a card (SELECT/DESELECT_CARD, CMD7), if none is already selected.\n2. \nSet the block length (SET_BLOCKLEN, CMD16) to 1 byte. Only the 8-bit card \nlock/unlock byte (byte 0 in Table 172) is sent.\n3. \nSend LOCK/UNLOCK (CMD42) with the appropriate data byte on the data line including \nthe 16-bit CRC. The data block indicates the mode (ERASE = 1). All other bits must be \nzero.\n4. \nWhen the ERASE bit is the only bit set in the data field, all card contents are erased, \nincluding the PWD and PWD_LEN fields, and the card is no longer locked. When any \nother bits are set, the LOCK_UNLOCK_FAILED error bit is set in the card status \nregister and the card retains all of its data, and remains locked.\nAn attempt to use a force erase on an unlocked card fails and the LOCK_UNLOCK_FAILED \nerror bit is set in the card status register.\n31.4.11 \nCard status register\nThe response format R1 contains a 32-bit field named card status. This field is intended to \ntransmit the card status information (which may be stored in a local status register) to the \nhost. If not specified otherwise, the status entries are always related to the previously issued \ncommand.\nTable 159 defines the different entries of the status. The type and clear condition fields in \nthe table are abbreviated as follows:\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1046/1757\nRM0090 Rev 21\nType:\n•\nE: error bit\n•\nS: status bit\n•\nR: detected and set for the actual command response\n•\nX: detected and set during command execution. The SDIO card host must poll the card \nby issuing the status command to read these bits.\nClear condition:\n•\nA: according to the card current state\n•\nB: always related to the previous command. Reception of a valid command clears it \n(with a delay of one command)\n•\nC: clear by read\n \nTable 159. Card status\nBits\nIdentifier\nType \nValue\nDescription \nClear \ncondition\n31\nADDRESS_ \nOUT_OF_RANGE \nE R X ’0’= no error \n’1’= error \nThe command address argument was out \nof the allowed range for this card.\nA multiple block or stream read/write \noperation is (although started in a valid \naddress) attempting to read or write \nbeyond the card capacity.\nC\n30\nADDRESS_MISALIGN \n-\n’0’= no error \n’1’= error \nThe commands address argument (in \naccordance with the currently set block \nlength) positions the first data block \nmisaligned to the card physical blocks.\nA multiple block read/write operation \n(although started with a valid \naddress/block-length combination) is \nattempting to read or write a data block \nwhich is not aligned with the physical \nblocks of the card. \nC\n29\nBLOCK_LEN_ERROR \n-\n’0’= no error \n’1’= error \nEither the argument of a \nSET_BLOCKLEN command exceeds the \nmaximum value allowed for the card, or \nthe previously defined block length is \nillegal for the current command (e.g. the \nhost issues a write command, the current \nblock length is smaller than the maximum \nallowed value for the card and it is not \nallowed to write partial blocks) \nC\n28\nERASE_SEQ_ERROR \n-\n’0’= no error\n’1’= error \nAn error in the sequence of erase \ncommands occurred. \nC\n27\nERASE_PARAM \nE X\n’0’= no error \n’1’= error \nAn invalid selection of erase groups for \nerase occurred. \nC\n26\nWP_VIOLATION \nE X\n’0’= no error \n’1’= error \nAttempt to program a write-protected \nblock. \nC\n\n\n<>\n\nRM0090 Rev 21\n1047/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n25\nCARD_IS_LOCKED \nS R \n‘0’ = card \nunlocked\n‘1’ = card locked \nWhen set, signals that the card is locked \nby the host \nA\n24\nLOCK_UNLOCK_ \nFAILED \nE X\n’0’= no error \n’1’= error \nSet when a sequence or password error \nhas been detected in lock/unlock card \ncommand \nC\n23\nCOM_CRC_ERROR \nE R\n’0’= no error \n’1’= error \nThe CRC check of the previous command \nfailed. \nB\n22\nILLEGAL_COMMAND \nE R\n’0’= no error \n’1’= error \nCommand not legal for the card state \nB\n21\nCARD_ECC_FAILED \nE X\n’0’= success\n’1’= failure \nCard internal ECC was applied but failed \nto correct the data. \nC\n20\nCC_ERROR \nE R\n’0’= no error\n’1’= error \n(Undefined by the standard) A card error \noccurred, which is not related to the host \ncommand. \nC\n19\nERROR \nE X\n’0’= no error \n’1’= error \n(Undefined by the standard) A generic \ncard error related to the (and detected \nduring) execution of the last host \ncommand (e.g. read or write failures). \nC\n18\nReserved\n17\nReserved\n16\nCID/CSD_OVERWRITE \nE X\n’0’= no error ‘1’= \nerror \nCan be either of the following errors:\n– The CID register has already been \nwritten and cannot be overwritten\n– The read-only section of the CSD does \nnot match the card contents\n– An attempt to reverse the copy (set as \noriginal) or permanent WP \n(unprotected) bits was made\nC\n15\nWP_ERASE_SKIP \nE X\n’0’= not protected\n’1’= protected \nSet when only partial address space \nwas erased due to existing write\nC\n14\nCARD_ECC_DISABLED\nS X\n’0’= enabled\n’1’= disabled\nThe command has been executed without \nusing the internal ECC.\nA\n13\nERASE_RESET \n-\n’0’= cleared \n’1’= set \nAn erase sequence was cleared before \nexecuting because an out of erase \nsequence command was received \n(commands other than CMD35, CMD36, \nCMD38 or CMD13) \nC\nTable 159. Card status (continued)\nBits\nIdentifier\nType \nValue\nDescription \nClear \ncondition\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1048/1757\nRM0090 Rev 21\n31.4.12 \nSD status register\nThe SD status contains status bits that are related to the SD memory card proprietary \nfeatures and may be used for future application-specific usage. The size of the SD Status is \none data block of 512 bits. The contents of this register are transmitted to the SDIO card \nhost if ACMD13 is sent (CMD55 followed with CMD13). ACMD13 can be sent to a card in \ntransfer state only (card is selected).\nTable 160 defines the different entries of the SD status register. The type and clear condition \nfields in the table are abbreviated as follows:\nType:\n•\nE: error bit\n•\nS: status bit\n•\nR: detected and set for the actual command response\n•\nX: detected and set during command execution. The SDIO card Host must poll the card \nby issuing the status command to read these bits\n12:9\nCURRENT_STATE \nS R\n0 = Idle\n1 = Ready \n2 = Ident \n3 = Stby \n4 = Tran \n5 = Data \n6 = Rcv \n7 = Prg \n8 = Dis \n9 = Btst \n10-15 = reserved \nThe state of the card when receiving the \ncommand. If the command execution \ncauses a state change, it is visible to the \nhost in the response on the next \ncommand. The four bits are interpreted as \na binary number between 0 and 15. \nB\n8\nREADY_FOR_DATA \nS R\n’0’= not ready ‘1’ \n= ready \nCorresponds to buffer empty signalling on \nthe bus \n-\n7\nSWITCH_ERROR \nE X\n’0’= no error\n’1’= switch error \nIf set, the card did not switch to the \nexpected mode as requested by the \nSWITCH command \nB\n6\nReserved\n5\nAPP_CMD \nS R\n‘0’ = Disabled \n‘1’ = Enabled \nThe card expects ACMD, or an indication \nthat the command has been interpreted \nas ACMD\nC\n4\nReserved for SD I/O Card\n3\nAKE_SEQ_ERROR\nE R\n’0’= no error \n’1’= error \nError in the sequence of the \nauthentication process\nC\n2\nReserved for application specific commands \n1\nReserved for manufacturer test mode \n0\nTable 159. Card status (continued)\nBits\nIdentifier\nType \nValue\nDescription \nClear \ncondition\n\n\n<>\n\nRM0090 Rev 21\n1049/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nClear condition:\n•\nA: according to the card current state\n•\nB: always related to the previous command. Reception of a valid command clears it \n(with a delay of one command)\n•\nC: clear by read\n \nTable 160. SD status\nBits\nIdentifier\nType\nValue\nDescription \nClear \ncondition\n511: 510\nDAT_BUS_WIDTH S R\n’00’= 1 (default)\n‘01’= reserved\n‘10’= 4 bit width\n‘11’= reserved\nShows the currently defined \ndatabus width that was \ndefined by \nSET_BUS_WIDTH \ncommand\nA\n509\nSECURED_MODE S R\n’0’= Not in the mode\n’1’= In Secured Mode\nCard is in Secured Mode of \noperation (refer to the “SD \nSecurity Specification”).\nA\n508: 496 Reserved\n495: 480 SD_CARD_TYPE\nS R\n’00xxh’= SD Memory Cards as \ndefined in Physical Spec Ver1.01-\n2.00 (’x’= don’t care). The \nfollowing cards are currently \ndefined:\n’0000’= Regular SD RD/WR Card.\n’0001’= SD ROM Card\nIn the future, the 8 LSBs are \nused to define different \nvariations of an SD memory \ncard (each bit defines \ndifferent SD types). The 8 \nMSBs are used to define SD \nCards that do not comply \nwith current SD physical \nlayer specification.\nA\n479: 448 SIZE_OF_PROTE\nCT ED_AREA\nS R\nSize of protected area (See \nbelow)\n(See below)\nA\n447: 440 SPEED_CLASS\nS R\nSpeed Class of the card (See \nbelow)\n(See below)\nA\n439: 432 PERFORMANCE_\nMOVE\nS R\nPerformance of move indicated by \n1 [MB/s] step.\n(See below)\n(See below)\nA\n431:428\nAU_SIZE\nS R\nSize of AU\n(See below)\n(See below)\nA\n427:424\nReserved\n423:408\nERASE_SIZE\nS R\nNumber of AUs to be erased at a \ntime\n(See below)\nA\n407:402\nERASE_TIMEOUT S R\nTimeout value for erasing areas \nspecified by \nUNIT_OF_ERASE_AU\n(See below)\nA\n401:400\nERASE_OFFSET\nS R\nFixed offset value added to erase \ntime.\n(See below)\nA\n399:312\nReserved\n311:0\nReserved for Manufacturer\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1050/1757\nRM0090 Rev 21\nSIZE_OF_PROTECTED_AREA\nSetting this field differs between standard- and high-capacity cards. In the case of a \nstandard-capacity card, the capacity of protected area is calculated as follows:\nProtected area = SIZE_OF_PROTECTED_AREA_* MULT * BLOCK_LEN.\nSIZE_OF_PROTECTED_AREA is specified by the unit in MULT*BLOCK_LEN.\nIn the case of a high-capacity card, the capacity of protected area is specified in this field:\nProtected area = SIZE_OF_PROTECTED_AREA\nSIZE_OF_PROTECTED_AREA is specified by the unit in bytes.\nSPEED_CLASS\nThis 8-bit field indicates the speed class and the value can be calculated by PW/2 (where \nPW is the write performance).\n \nPERFORMANCE_MOVE\nThis 8-bit field indicates Pm (performance move) and the value can be set by 1 [MB/sec] \nsteps. If the card does not move used RUs (recording units), Pm should be considered as \ninfinity. Setting the field to FFh means infinity.\n \nTable 161. Speed class code field\nSPEED_CLASS\nValue definition\n00h\nClass 0\n01h\nClass 2\n02h\nClass 4\n03h\nClass 6\n04h – FFh\nReserved\nTable 162. Performance move field\nPERFORMANCE_MOVE\nValue definition\n00h\nNot defined\n01h\n1 [MB/sec]\n02h\n02h 2 [MB/sec]\n---------\n---------\nFEh\n254 [MB/sec]\nFFh\n Infinity\n\n\n<>\n\nRM0090 Rev 21\n1051/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nAU_SIZE\nThis 4-bit field indicates the AU size and the value can be selected in the power of 2 base \nfrom 16 KB.\n \nThe maximum AU size, which depends on the card capacity, is defined in Table 164. The \ncard can be set to any AU size between RU size and maximum AU size.\n \nERASE_SIZE\nThis 16-bit field indicates NERASE. When NERASE numbers of AUs are erased, the \ntimeout value is specified by ERASE_TIMEOUT (Refer to ERASE_TIMEOUT). The host \nshould determine the proper number of AUs to be erased in one operation so that the host \ncan show the progress of the erase operation. If this field is set to 0, the erase timeout \ncalculation is not supported.\n \nTable 163. AU_SIZE field\nAU_SIZE\nValue definition\n00h\nNot defined\n01h\n16 KB\n02h\n32 KB\n03h\n64 KB\n04h\n128 KB\n05h\n256 KB\n06h\n512 KB\n07h\n1 MB\n08h\n2 MB\n09h\n4 MB\nAh – Fh\nReserved\nTable 164. Maximum AU size\nCapacity\n16 MB-64 MB\n128 MB-256 MB\n512 MB\n1 GB-32 GB\nMaximum AU Size\n512 KB\n1 MB\n2 MB\n4 MB\nTable 165. Erase size field\nERASE_SIZE\nValue definition\n0000h \nErase timeout calculation is not supported.\n0001h \n1 AU\n0002h\n2 AU\n0003h\n3 AU\n---------\n---------\nFFFFh\n65535 AU\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1052/1757\nRM0090 Rev 21\nERASE_TIMEOUT\nThis 6-bit field indicates TERASE and the value indicates the erase timeout from offset \nwhen multiple AUs are being erased as specified by ERASE_SIZE. The range of \nERASE_TIMEOUT can be defined as up to 63 seconds and the card manufacturer can \nchoose any combination of ERASE_SIZE and ERASE_TIMEOUT depending on the \nimplementation. Determining ERASE_TIMEOUT determines the ERASE_SIZE.\n \nERASE_OFFSET\nThis 2-bit field indicates TOFFSET and one of four values can be selected. This field is \nmeaningless if the ERASE_SIZE and ERASE_TIMEOUT fields are set to 0.\n \n31.4.13 \nSD I/O mode\nSD I/O interrupts\nTo allow the SD I/O card to interrupt the MultiMediaCard/SD module, an interrupt function is \navailable on a pin on the SD interface. Pin 8, used as SDIO_D1 when operating in the 4-bit \nSD mode, signals the cards interrupt to the MultiMediaCard/SD module. The use of the \ninterrupt is optional for each card or function within a card. The SD I/O interrupt is level-\nsensitive, which means that the interrupt line must be held active (low) until it is either \nrecognized and acted upon by the MultiMediaCard/SD module or deasserted due to the end \nof the interrupt period. After the MultiMediaCard/SD module has serviced the interrupt, the \ninterrupt status bit is cleared via an I/O write to the appropriate bit in the SD I/O card’s \ninternal registers. The interrupt output of all SD I/O cards is active low and the application \nmust provide external pull-up resistors on all data lines (SDIO_D[3:0]). The \nMultiMediaCard/SD module samples the level of pin 8 (SDIO_D/IRQ) into the interrupt \ndetector only during the interrupt period. At all other times, the MultiMediaCard/SD module \nignores this value.\nTable 166. Erase timeout field\nERASE_TIMEOUT\nValue definition\n00 \nErase timeout calculation is not supported.\n01 \n1 [sec]\n02\n2 [sec]\n03\n3 [sec]\n---------\n---------\n63\n63 [sec]\nTable 167. Erase offset field\nERASE_OFFSET\nValue definition\n0h \n0 [sec]\n1h \n1 [sec]\n2h\n2 [sec]\n3h\n3 [sec]\n\n\n<>\n\nRM0090 Rev 21\n1053/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nThe interrupt period is applicable for both memory and I/O operations. The definition of the \ninterrupt period for operations with single blocks is different from the definition for multiple-\nblock data transfers.\nSD I/O suspend and resume\nWithin a multifunction SD I/O or a card with both I/O and memory functions, there are \nmultiple devices (I/O and memory) that share access to the MMC/SD bus. To share access \nto the MMC/SD module among multiple devices, SD I/O and combo cards optionally \nimplement the concept of suspend/resume. When a card supports suspend/resume, the \nMMC/SD module can temporarily halt a data transfer operation to one function or memory \n(suspend) to free the bus for a higher-priority transfer to a different function or memory. After \nthis higher-priority transfer is complete, the original transfer is resumed (restarted) where it \nleft off. Support of suspend/resume is optional on a per-card basis. To perform the \nsuspend/resume operation on the MMC/SD bus, the MMC/SD module performs the \nfollowing steps:\n1.\nDetermines the function currently using the SDIO_D [3:0] line(s)\n2. \nRequests the lower-priority or slower transaction to suspend\n3. \nWaits for the transaction suspension to complete\n4. \nBegins the higher-priority transaction\n5. \nWaits for the completion of the higher priority transaction\n6. \nRestores the suspended transaction\nSD I/O ReadWait\nThe optional ReadWait (RW) operation is defined only for the SD 1-bit and 4-bit modes. The \nReadWait operation allows the MMC/SD module to signal a card that it is reading multiple \nregisters (IO_RW_EXTENDED, CMD53) to temporarily stall the data transfer while allowing \nthe MMC/SD module to send commands to any function within the SD I/O device. To \ndetermine when a card supports the ReadWait protocol, the MMC/SD module must test \ncapability bits in the internal card registers. The timing for ReadWait is based on the \ninterrupt period.\n31.4.14 \nCommands and responses\nApplication-specific and general commands\nThe SD card host module system is designed to provide a standard interface for a variety of \napplications types. In this environment, there is a need for specific customer/application \nfeatures. To implement these features, two types of generic commands are defined in the \nstandard: application-specific commands (ACMD) and general commands (GEN_CMD).\nWhen the card receives the APP_CMD (CMD55) command, the card expects the next \ncommand to be an application-specific command. ACMDs have the same structure as \nregular MultiMediaCard commands and can have the same CMD number. The card \nrecognizes it as ACMD because it appears after APP_CMD (CMD55). When the command \nimmediately following the APP_CMD (CMD55) is not a defined application-specific \ncommand, the standard command is used. For example, when the card has a definition for \nSD_STATUS (ACMD13), and receives CMD13 immediately following APP_CMD (CMD55), \nthis is interpreted as SD_STATUS (ACMD13). However, when the card receives CMD7 \nimmediately following APP_CMD (CMD55) and the card does not have a definition for \nACMD7, this is interpreted as the standard (SELECT/DESELECT_CARD) CMD7.\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1054/1757\nRM0090 Rev 21\nTo use one of the manufacturer-specific ACMDs the SD card Host must perform the \nfollowing steps:\n1.\nSend APP_CMD (CMD55)\nThe card responds to the MultiMediaCard/SD module, indicating that the APP_CMD bit \nis set and an ACMD is now expected.\n2. \nSend the required ACMD\nThe card responds to the MultiMediaCard/SD module, indicating that the APP_CMD bit \nis set and that the accepted command is interpreted as an ACMD. When a nonACMD \nis sent, it is handled by the card as a normal MultiMediaCard command and the \nAPP_CMD bit in the card status register stays clear.\nWhen an invalid command is sent (neither ACMD nor CMD) it is handled as a standard \nMultiMediaCard illegal command error.\nThe bus transaction for a GEN_CMD is the same as the single-block read or write \ncommands (WRITE_BLOCK, CMD24 or READ_SINGLE_BLOCK,CMD17). In this case, the \nargument denotes the direction of the data transfer rather than the address, and the data \nblock has vendor-specific format and meaning.\nThe card must be selected (in transfer state) before sending GEN_CMD (CMD56). The data \nblock size is defined by SET_BLOCKLEN (CMD16). The response to GEN_CMD (CMD56) \nis in R1b format.\nCommand types\nBoth application-specific and general commands are divided into the four following types:\n•\nbroadcast command (BC): sent to all cards; no responses returned.\n•\nbroadcast command with response (BCR): sent to all cards; responses received \nfrom all cards simultaneously.\n•\naddressed (point-to-point) command (AC): sent to the card that is selected; does \nnot include a data transfer on the SDIO_D line(s).\n•\naddressed (point-to-point) data transfer command (ADTC): sent to the card that is \nselected; includes a data transfer on the SDIO_D line(s).\nCommand formats\nSee Table 152 on page 1030 for command formats.\nCommands for the MultiMediaCard/SD module\n \nTable 168. Block-oriented write commands\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nCMD23\nac\n[31:16] set to 0 \n[15:0] number \nof blocks\nR1\nSET_BLOCK_COUNT\nDefines the number of blocks which \nare going to be transferred in the \nmultiple-block read or write command \nthat follows.\nCMD24\nadtc\n[31:0] data \naddress\nR1\nWRITE_BLOCK\nWrites a block of the size selected by \nthe SET_BLOCKLEN command.\n\n\n<>\n\nRM0090 Rev 21\n1055/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n \n \nCMD25\nadtc\n[31:0] data \naddress\nR1\nWRITE_MULTIPLE_BLOCK\nContinuously writes blocks of data \nuntil a STOP_TRANSMISSION \nfollows or the requested number of \nblocks has been received.\nCMD26\nadtc\n[31:0] stuff bits R1\nPROGRAM_CID\nProgramming of the card identification \nregister. This command must be \nissued only once per card. The card \ncontains hardware to prevent this \noperation after the first programming. \nNormally this command is reserved \nfor manufacturer.\nCMD27\nadtc\n[31:0] stuff bits R1\nPROGRAM_CSD\nProgramming of the programmable \nbits of the CSD.\nTable 168. Block-oriented write commands (continued)\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nTable 169. Block-oriented write protection commands\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nCMD28\nac\n[31:0] data \naddress\nR1b\nSET_WRITE_PROT\nIf the card has write protection features, \nthis command sets the write protection bit \nof the addressed group. The properties of \nwrite protection are coded in the card-\nspecific data (WP_GRP_SIZE).\nCMD29\nac\n[31:0] data \naddress\nR1b\nCLR_WRITE_PROT\nIf the card provides write protection \nfeatures, this command clears the write \nprotection bit of the addressed group.\nCMD30\nadtc\n[31:0] write \nprotect data \naddress\nR1\nSEND_WRITE_PROT\nIf the card provides write protection \nfeatures, this command asks the card to \nsend the status of the write protection \nbits. \nCMD31\nReserved\nTable 170. Erase commands\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nCMD32\n...\nCMD34\nReserved. These command indexes cannot be used in order to maintain backward compatibility with older \nversions of the MultiMediaCard.\nCMD35 ac\n[31:0] data address R1\nERASE_GROUP_START\nSets the address of the first erase \ngroup within a range to be selected \nfor erase.\nCMD36 ac\n[31:0] data address R1\nERASE_GROUP_END\nSets the address of the last erase \ngroup within a continuous range to be \nselected for erase.\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1056/1757\nRM0090 Rev 21\n \n \n \nCMD37 Reserved. This command index cannot be used in order to maintain backward compatibility with older \nversions of the MultiMediaCards\nCMD38 ac\n[31:0] stuff bits\nR1\nERASE\nErases all previously selected write \nblocks.\nTable 170. Erase commands (continued)\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nTable 171. I/O mode commands\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nCMD39\nac\n[31:16] RCA \n[15:15] register \nwrite flag \n[14:8] register \naddress \n[7:0] register data\nR4\nFAST_IO\nUsed to write and read 8-bit (register) data \nfields. The command addresses a card and a \nregister and provides the data for writing if \nthe write flag is set. The R4 response \ncontains data read from the addressed \nregister. This command accesses \napplication-dependent registers that are not \ndefined in the MultiMediaCard standard.\nCMD40\nbcr\n[31:0] stuff bits\nR5\nGO_IRQ_STATE Places the system in the interrupt mode.\nCMD41\nReserved\nTable 172. Lock card\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nCMD42\nadtc\n[31:0] stuff bits\nR1b\nLOCK_UNLOCK\nSets/resets the password or locks/unlocks \nthe card. The size of the data block is set \nby the SET_BLOCK_LEN command.\nCMD43 \n... \nCMD54\nReserved\nTable 173. Application-specific commands\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nCMD55\nac\n[31:16] RCA\n[15:0] stuff bits\nR1\nAPP_CMD\nIndicates to the card that the next command \nbits is an application specific command rather \nthan a standard command\nCMD56\nadtc\n[31:1] stuff bits\n[0]: RD/WR\n-\n-\nUsed either to transfer a data block to the card \nor to get a data block from the card for general \npurpose/application-specific commands. The \nsize of the data block is set by the \nSET_BLOCK_LEN command.\n\n\n<>\n\nRM0090 Rev 21\n1057/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.5 \nResponse formats\nAll responses are sent via the MCCMD command line SDIO_CMD. The response \ntransmission always starts with the left bit of the bit string corresponding to the response \ncode word. The code length depends on the response type.\nA response always starts with a start bit (always 0), followed by the bit indicating the \ndirection of transmission (card = 0). A value denoted by x in the tables below indicates a \nvariable entry. All responses, except for the R3 response type, are protected by a CRC. \nEvery command code word is terminated by the end bit (always 1).\nThere are five types of responses. Their formats are defined as follows:\n31.5.1 \nR1 (normal response command)\nCode length = 48 bits. The 45:40 bits indicate the index of the command to be responded to, \nthis value being interpreted as a binary-coded number (between 0 and 63). The status of the \ncard is coded in 32 bits.\n \n31.5.2 \nR1b\nIt is identical to R1 with an optional busy signal transmitted on the data line. The card may \nbecome busy after receiving these commands based on its state prior to the command \nreception.\n31.5.3 \nR2 (CID, CSD register)\nCode length = 136 bits. The contents of the CID register are sent as a response to the \nCMD2 and CMD10 commands. The contents of the CSD register are sent as a response to \nCMD57 \n... \nCMD59\nReserved.\nCMD60 \n... \nCMD63\nReserved for manufacturer.\nTable 173. Application-specific commands (continued)\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nTable 174. R1 response\nBit position\nWidth (bits\nValue\nDescription\n47\n1\n0\nStart bit\n46\n1\n0\nTransmission bit\n[45:40]\n6\nX\nCommand index\n[39:8]\n32\nX\nCard status\n[7:1]\n7\nX\nCRC7\n0\n1\n1\nEnd bit\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1058/1757\nRM0090 Rev 21\nCMD9. Only the bits [127...1] of the CID and CSD are transferred, the reserved bit [0] of \nthese registers is replaced by the end bit of the response. The card indicates that an erase \nis in progress by holding MCDAT low. The actual erase time may be quite long, and the host \nmay issue CMD7 to deselect the card.\n \n31.5.4 \nR3 (OCR register)\nCode length: 48 bits. The contents of the OCR register are sent as a response to CMD1. \nThe level coding is as follows: restricted voltage windows = low, card busy = low.\n \n31.5.5 \nR4 (Fast I/O)\nCode length: 48 bits. The argument field contains the RCA of the addressed card, the \nregister address to be read from or written to, and its content.\n \nTable 175. R2 response\nBit position\nWidth (bits\nValue\nDescription\n135\n1\n0\nStart bit\n134\n1\n0\nTransmission bit\n[133:128]\n6\n‘111111’\nCommand index\n[127:1]\n127\nX\nCard status\n0\n1\n1\nEnd bit\nTable 176. R3 response\nBit position\nWidth (bits\nValue\nDescription\n47\n1\n0\nStart bit\n46\n1\n0\nTransmission bit\n[45:40]\n6\n‘111111’\nReserved\n[39:8]\n32\nX\nOCR register\n[7:1]\n7\n‘1111111’\nReserved\n0\n1\n1\nEnd bit\nTable 177. R4 response\nBit position\nWidth (bits\nValue\nDescription\n47\n1\n0\nStart bit\n46\n1\n0\nTransmission bit\n[45:40]\n6\n‘100111’\nCMD39\n[39:8] Argument field\n[31:16]\n16\nX\nRCA\n[15:8]\n8\nX\nregister address\n[7:0]\n8\nX\nread register contents\n\n\n<>\n\nRM0090 Rev 21\n1059/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.5.6 \nR4b\nFor SD I/O only: an SDIO card receiving the CMD5 responds with a unique SDIO response \nR4. The format is:\n \nOnce an SD I/O card has received a CMD5, the I/O portion of that card is enabled to \nrespond normally to all further commands. This I/O enable of the function within the I/O card \nremains set until a reset, power cycle or CMD52 with write to I/O reset is received by the \ncard. Note that an SD memory-only card may respond to a CMD5. The proper response for \na memory-only card would be Present memory = 1 and Number of I/O functions = 0. A \nmemory-only card built to meet the SD Memory Card specification version 1.0 would detect \nthe CMD5 as an illegal command and not respond. The I/O aware host sends CMD5. If the \ncard responds with response R4, the host determines the card’s configuration based on the \ndata contained within the R4 response.\n31.5.7 \nR5 (interrupt request)\nOnly for MultiMediaCard. Code length: 48 bits. If the response is generated by the host, the \nRCA field in the argument is 0x0.\n \n[7:1]\n7\nX\nCRC7\n0\n1\n1\nEnd bit\nTable 177. R4 response (continued)\nBit position\nWidth (bits\nValue\nDescription\nTable 178. R4b response\nBit position\nWidth (bits\nValue\nDescription\n47\n1\n0\nStart bit\n46\n1\n0\nTransmission bit\n[45:40]\n6\nx\nReserved\n[39:8] Argument field\n39\n16\nX\nCard is ready\n[38:36]\n3\nX\nNumber of I/O functions\n35\n1\nX\nPresent memory\n[34:32]\n3\nX\nStuff bits\n[31:8]\n24\nX\nI/O ORC\n[7:1]\n7\nX\nReserved\n0\n1\n1\nEnd bit\nTable 179. R5 response\nBit position\nWidth (bits\nValue\nDescription\n47\n1\n0\nStart bit\n46\n1\n0\nTransmission bit\n[45:40]\n6\n‘101000’\nCMD40\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1060/1757\nRM0090 Rev 21\n31.5.8 \nR6\nOnly for SD I/O. The normal response to CMD3 by a memory device. It is shown in \nTable 180.\n \nThe card [23:8] status bits are changed when CMD3 is sent to an I/O-only card. In this case, \nthe 16 bits of response are the SD I/O-only values:\n•\nBit [15] COM_CRC_ERROR\n•\nBit [14] ILLEGAL_COMMAND\n•\nBit [13] ERROR\n•\nBits [12:0] Reserved\n31.6 \nSDIO I/O card-specific operations\nThe following features are SD I/O-specific operations:\n•\nSDIO read wait operation by SDIO_D2 signalling\n•\nSDIO read wait operation by stopping the clock\n•\nSDIO suspend/resume operation (write and read suspend)\n•\nSDIO interrupts\nThe SDIO supports these operations only if the SDIO_DCTRL[11] bit is set, except for read \nsuspend that does not need specific hardware implementation.\n[39:8] Argument field\n[31:16]\n16\nX\nRCA [31:16] of winning \ncard or of the host\n[15:0]\n16\nX\nNot defined. May be used \nfor IRQ data\n[7:1]\n7\nX\nCRC7\n0\n1\n1\nEnd bit\nTable 179. R5 response (continued)\nBit position\nWidth (bits\nValue\nDescription\nTable 180. R6 response\nBit position\nWidth (bits)\nValue\nDescription\n47\n1\n0\nStart bit\n46\n1\n0\nTransmission bit\n[45:40]\n6\n‘101000’\nCMD40\n[39:8] Argument \nfield\n[31:16]\n16\nX\nRCA [31:16] of winning card or of the host\n[15:0]\n16\nX\nNot defined. May be used for IRQ data\n[7:1]\n7\nX\nCRC7\n0\n1\n1\nEnd bit\n\n\n<>\n\nRM0090 Rev 21\n1061/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.6.1 \nSDIO I/O read wait operation by SDIO_D2 signaling\nIt is possible to start the readwait interval before the first block is received: when the data \npath is enabled (SDIO_DCTRL[0] bit set), the SDIO-specific operation is enabled \n(SDIO_DCTRL[11] bit set), read wait starts (SDI0_DCTRL[10] =0 and SDI_DCTRL[8] =1) \nand data direction is from card to SDIO (SDIO_DCTRL[1] = 1), the DPSM directly moves \nfrom Idle to Readwait. In Readwait the DPSM drives SDIO_D2 to 0 after 2 SDIO_CK clock \ncycles. In this state, when you set the RWSTOP bit (SDIO_DCTRL[9]), the DPSM remains \nin Wait for two more SDIO_CK clock cycles to drive SDIO_D2 to 1 for one clock cycle (in \naccordance with SDIO specification). The DPSM then starts waiting again until it receives \ndata from the card. The DPSM does not start a readwait interval while receiving a block \neven if read wait start is set: the readwait interval starts after the CRC is received. The \nRWSTOP bit has to be cleared to start a new read wait operation. During the readwait \ninterval, the SDIO can detect SDIO interrupts on SDIO_D1.\n31.6.2 \nSDIO read wait operation by stopping SDIO_CK\nIf the SDIO card does not support the previous read wait method, the SDIO can perform a \nread wait by stopping SDIO_CK (SDIO_DCTRL is set just like in the method presented in \nSection 31.6.1, but SDIO_DCTRL[10] =1): DSPM stops the clock two SDIO_CK cycles after \nthe end bit of the current received block and starts the clock again after the read wait start bit \nis set.\nAs SDIO_CK is stopped, any command can be issued to the card. During a read/wait \ninterval, the SDIO can detect SDIO interrupts on SDIO_D1.\n31.6.3 \nSDIO suspend/resume operation\nWhile sending data to the card, the SDIO can suspend the write operation. the \nSDIO_CMD[11] bit is set and indicates to the CPSM that the current command is a suspend \ncommand. The CPSM analyzes the response and when the ACK is received from the card \n(suspend accepted), it acknowledges the DPSM that goes Idle after receiving the CRC \ntoken of the current block.\nThe hardware does not save the number of the remaining block to be sent to complete the \nsuspended operation (resume).\nThe write operation can be suspended by software, just by disabling the DPSM \n(SDIO_DCTRL[0] =0) when the ACK of the suspend command is received from the card. \nThe DPSM enters then the Idle state.\nTo suspend a read: the DPSM waits in the Wait_r state as the function to be suspended \nsends a complete packet just before stopping the data transaction. The application \ncontinues reading RxFIFO until the FIF0 is empty, and the DPSM goes Idle automatically.\n31.6.4 \nSDIO interrupts\nSDIO interrupts are detected on the SDIO_D1 line once the SDIO_DCTRL[11] bit is set.\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1062/1757\nRM0090 Rev 21\n31.7 \nCE-ATA specific operations\nThe following features are CE-ATA specific operations:\n•\nsending the command completion signal disable to the CE-ATA device\n•\nreceiving the command completion signal from the CE-ATA device\n•\nsignaling the completion of the CE-ATA command to the CPU, using the status bit \nand/or interrupt.\nThe SDIO supports these operations only for the CE-ATA CMD61 command, that is, if \nSDIO_CMD[14] is set.\n31.7.1 \nCommand completion signal disable\nCommand completion signal disable is sent 8 bit cycles after the reception of a short \nresponse if the ‘enable CMD completion’ bit, SDIO_CMD[12], is not set and the ‘not interrupt \nEnable’ bit, SDIO_CMD[13], is set.\nThe CPSM enters the Pend state, loading the command shift register with the disable \nsequence “00001” and, the command counter with 43. Eight cycles after, a trigger moves \nthe CPSM to the Send state. When the command counter reaches 48, the CPSM becomes \nIdle as no response is awaited.\n31.7.2 \nCommand completion signal enable\nIf the ‘enable CMD completion’ bit SDIO_CMD[12] is set and the ‘not interrupt Enable’ bit \nSDIO_CMD[13] is set, the CPSM waits for the command completion signal in the Waitcpl \nstate.\nWhen ‘0’ is received on the CMD line, the CPSM enters the Idle state. No new command \ncan be sent for 7 bit cycles. Then, for the last 5 cycles (out of the 7) the CMD line is driven to \n‘1’ in push-pull mode.\n31.7.3 \nCE-ATA interrupt\nThe command completion is signaled to the CPU by the status bit SDIO_STA[23]. This static \nbit can be cleared with the clear bit SDIO_ICR[23].\nThe SDIO_STA[23] status bit can generate an interrupt on each interrupt line, depending on \nthe mask bit SDIO_MASKx[23].\n31.7.4 \nAborting CMD61\nIf the command completion disable signal has not been sent and CMD61 needs to be \naborted, the command state machine must be disabled. It then becomes Idle, and the \nCMD12 command can be sent. No command completion disable signal is sent during the \noperation.\n\n\n<>\n\nRM0090 Rev 21\n1063/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.8 \nHW flow control\nThe HW flow control functionality is used to avoid FIFO underrun (TX mode) and overrun \n(RX mode) errors.\nThe behavior is to stop SDIO_CK and freeze SDIO state machines. The data transfer is \nstalled while the FIFO is unable to transmit or receive data. Only state machines clocked by \nSDIOCLK are frozen, the APB2 interface is still alive. The FIFO can thus be filled or emptied \neven if flow control is activated.\nTo enable HW flow control, the SDIO_CLKCR[14] register bit must be set to 1. After reset \nFlow Control is disabled.\n31.9 \nSDIO registers\nThe device communicates to the system via 32-bit-wide control registers accessible via \nAPB2.\nThe peripheral registers have to be accessed by words (32 bits).\n31.9.1 \nSDIO power control register (SDIO_POWER)\nAddress offset: 0x00\nReset value: 0x0000 0000\n \nNote:\nAt least seven HCLK clock periods are needed between two write accesses to this register.\nAfter a data write, data cannot be written to this register for three SDIOCLK clock periods \nplus two PCLK2 clock periods.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPWRC\nTRL\nrw\nrw\nBits 31:2 Reserved, must be kept at reset value\nBits 1:0 PWRCTRL: Power supply control bits.\nThese bits are used to define the current functional state of the card clock:\n00: Power-off: the clock to card is stopped.\n01: Reserved\n10: Reserved power-up\n11: Power-on: the card is clocked.\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1064/1757\nRM0090 Rev 21\n31.9.2 \nSDI clock control register (SDIO_CLKCR)\nAddress offset: 0x04\nReset value: 0x0000 0000\nThe SDIO_CLKCR register controls the SDIO_CK output clock.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nHWFC_EN\nNEGEDGE\nWID\nBUS\nBYPASS\nPWRSAV\nCLKEN\nCLKDIV\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:15 Reserved, must be kept at reset value\nBit 14 HWFC_EN: HW Flow Control enable\n0b: HW Flow Control is disabled\n1b: HW Flow Control is enabled\nWhen HW Flow Control is enabled, the meaning of the TXFIFOE and RXFIFOF interrupt \nsignals, see SDIO Status register definition in Section 31.9.11.\nBit 13 NEGEDGE:SDIO_CK dephasing selection bit\n0b: SDIO_CK generated on the rising edge of the master clock SDIOCLK\n1b: SDIO_CK generated on the falling edge of the master clock SDIOCLK\nBits 12:11 WIDBUS: Wide bus mode enable bit\n00: Default bus mode: SDIO_D0 used\n01: 4-wide bus mode: SDIO_D[3:0] used\n10: 8-wide bus mode: SDIO_D[7:0] used\nBit 10 BYPASS: Clock divider bypass enable bit\n0: Disable bypass: SDIOCLK is divided according to the CLKDIV value before driving the \nSDIO_CK output signal.\n1: Enable bypass: SDIOCLK directly drives the SDIO_CK output signal.\nBit 9 PWRSAV: Power saving configuration bit\nFor power saving, the SDIO_CK clock output can be disabled when the bus is idle by setting \nPWRSAV:\n0: SDIO_CK clock is always enabled\n1: SDIO_CK is only enabled when the bus is active\nBit 8 CLKEN: Clock enable bit\n0: SDIO_CK is disabled\n1: SDIO_CK is enabled\nBits 7:0 CLKDIV: Clock divide factor\nThis field defines the divide factor between the input clock (SDIOCLK) and the output clock \n(SDIO_CK): SDIO_CK frequency = SDIOCLK / [CLKDIV + 2].\nNote: In order to have a duty cycle of 50% it is recommended to select even values of \nCLKDIV.\n\n\n<>\n\nRM0090 Rev 21\n1065/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nNote:\nWhile the SD/SDIO card or MultiMediaCard is in identification mode, the SDIO_CK \nfrequency must be less than 400 kHz.\nThe clock frequency can be changed to the maximum card bus frequency when relative \ncard addresses are assigned to all cards.\nAfter a data write, data cannot be written to this register for three SDIOCLK clock periods \nplus two PCLK2 clock periods. SDIO_CK can also be stopped during the read wait interval \nfor SD I/O cards: in this case the SDIO_CLKCR register does not control SDIO_CK.\n31.9.3 \nSDIO argument register (SDIO_ARG)\nAddress offset: 0x08\nReset value: 0x0000 0000\nThe SDIO_ARG register contains a 32-bit command argument, which is sent to a card as \npart of a command message.\n \n \n31.9.4 \nSDIO command register (SDIO_CMD)\nAddress offset: 0x0C\nReset value: 0x0000 0000\nThe SDIO_CMD register contains the command index and command type bits. The \ncommand index is sent to a card as part of a command message. The command type bits \ncontrol the command path state machine (CPSM).\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCMDARG\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 CMDARG: Command argument\nCommand argument sent to a card as part of a command message. If a command contains \nan argument, it must be loaded into this register before writing a command to the command \nregister.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCE-ATACMD\nnIEN\nENCMDcompl\nSDIOSuspend\nCPSMEN\nWAITPEND\nWAITINT\nWAITRESP\nCMDINDEX\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:15 Reserved, must be kept at reset value\nBit 14 ATACMD: CE-ATA command\nIf ATACMD is set, the CPSM transfers CMD61.\nBit 13 nIEN: not Interrupt Enable\nif this bit is 0, interrupts in the CE-ATA device are enabled.\nBit 12 ENCMDcompl: Enable CMD completion\nIf this bit is set, the command completion signal is enabled.\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1066/1757\nRM0090 Rev 21\nNote:\nAfter a data write, data cannot be written to this register for three SDIOCLK clock periods \nplus two PCLK2 clock periods.\nMultiMediaCards can send two kinds of response: short responses, 48 bits long, or long \nresponses,136 bits long. SD card and SD I/O card can send only short responses, the \nargument can vary according to the type of response: the software distinguishes the type of \nresponse according to the sent command. CE-ATA devices send only short responses.\n31.9.5 \nSDIO command response register (SDIO_RESPCMD)\nAddress offset: 0x10\nReset value: 0x0000 0000\nThe SDIO_RESPCMD register contains the command index field of the last command \nresponse received. If the command response transmission does not contain the command \nindex field (long or OCR response), the RESPCMD field is unknown, although it must \ncontain 111111b (the value of the reserved field from the response).\n \n \nBit 11 SDIOSuspend: SD I/O suspend command\nIf this bit is set, the command to be sent is a suspend command (to be used only with SDIO \ncard).\nBit 10 CPSMEN: Command path state machine (CPSM) Enable bit\nIf this bit is set, the CPSM is enabled.\nBit 9 WAITPEND: CPSM Waits for ends of data transfer (CmdPend internal signal).\nIf this bit is set, the CPSM waits for the end of data transfer before it starts sending a \ncommand.\nBit 8 WAITINT: CPSM waits for interrupt request\nIf this bit is set, the CPSM disables command timeout and waits for an interrupt request.\nBits 7:6 WAITRESP: Wait for response bits\nThey are used to configure whether the CPSM is to wait for a response, and if yes, which \nkind of response.\n00: No response, expect CMDSENT flag\n01: Short response, expect CMDREND or CCRCFAIL flag\n10: No response, expect CMDSENT flag\n11: Long response, expect CMDREND or CCRCFAIL flag\nBits 5:0 CMDINDEX: Command index\nThe command index is sent to the card as part of a command message.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRESPCMD\nr\nr\nr\nr\nr\nr\nBits 31:6 Reserved, must be kept at reset value\nBits 5:0 RESPCMD: Response command index\nRead-only bit field. Contains the command index of the last command response received.\n\n\n<>\n\nRM0090 Rev 21\n1067/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.9.6 \nSDIO response 1..4 register (SDIO_RESPx)\nAddress offset: (0x10 + (4 × x)); x = 1..4\nReset value: 0x0000 0000\nThe SDIO_RESP1/2/3/4 registers contain the status of a card, which is part of the received \nresponse.\n \n \nThe Card Status size is 32 or 127 bits, depending on the response type.\n \nThe most significant bit of the card status is received first. The SDIO_RESP3 register LSB is \nalways 0b.\n31.9.7 \nSDIO data timer register (SDIO_DTIMER)\nAddress offset: 0x24\nReset value: 0x0000 0000\nThe SDIO_DTIMER register contains the data timeout period, in card bus clock periods. \nA counter loads the value from the SDIO_DTIMER register, and starts decrementing when \nthe data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 \nwhile the DPSM is in either of these states, the timeout status flag is set.\n \n \nNote:\nA data transfer must be written to the data timer register and the data length register before \nbeing written to the data control register.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCARDSTATUSx\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 CARDSTATUSx: see Table 181.\nTable 181. Response type and SDIO_RESPx registers\nRegister\nShort response\nLong response\nSDIO_RESP1\nCard Status[31:0]\nCard Status [127:96]\nSDIO_RESP2\nUnused\nCard Status [95:64]\nSDIO_RESP3\nUnused\nCard Status [63:32]\nSDIO_RESP4\nUnused\nCard Status [31:1]0b\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATATIME\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 DATATIME: Data timeout period\nData timeout period expressed in card bus clock periods.\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1068/1757\nRM0090 Rev 21\n31.9.8 \nSDIO data length register (SDIO_DLEN)\nAddress offset: 0x28\nReset value: 0x0000 0000\nThe SDIO_DLEN register contains the number of data bytes to be transferred. The value is \nloaded into the data counter when data transfer starts.\n \n \nNote:\nFor a block data transfer, the value in the data length register must be a multiple of the block \nsize (see SDIO_DCTRL). A data transfer must be written to the data timer register and the \ndata length register before being written to the data control register.\nFor an SDIO multibyte transfer the value in the data length register must be between 1 and \n512.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDATALENGTH\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:25 Reserved, must be kept at reset value\nBits 24:0 DATALENGTH: Data length value\nNumber of data bytes to be transferred.\n\n\n<>\n\nRM0090 Rev 21\n1069/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.9.9 \nSDIO data control register (SDIO_DCTRL)\nAddress offset: 0x2C\nReset value: 0x0000 0000\nThe SDIO_DCTRL register control the data path state machine (DPSM).\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSDIOEN\nRWMOD\nRWSTOP\nRWSTART\nDBLOCKSIZE\nDMAEN\nDTMODE\nDTDIR\nDTEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value\nBit 11 SDIOEN: SD I/O enable functions\nIf this bit is set, the DPSM performs an SD I/O-card-specific operation.\nBit 10 RWMOD: Read wait mode\n0: Read Wait control stopping SDIO_D2\n1: Read Wait control using SDIO_CK\nBit 9 RWSTOP: Read wait stop\n0: Read wait in progress if RWSTART bit is set\n1: Enable for read wait stop if RWSTART bit is set\nBit 8 RWSTART: Read wait start\nIf this bit is set, read wait operation starts.\nBits 7:4 DBLOCKSIZE: Data block size\nDefine the data block length when the block data transfer mode is selected:\n0000: (0 decimal) lock length = 20 = 1 byte\n0001: (1 decimal) lock length = 21 = 2 bytes\n0010: (2 decimal) lock length = 22 = 4 bytes\n0011: (3 decimal) lock length = 23 = 8 bytes\n0100: (4 decimal) lock length = 24 = 16 bytes\n0101: (5 decimal) lock length = 25 = 32 bytes\n0110: (6 decimal) lock length = 26 = 64 bytes\n0111: (7 decimal) lock length = 27 = 128 bytes\n1000: (8 decimal) lock length = 28 = 256 bytes\n1001: (9 decimal) lock length = 29 = 512 bytes\n1010: (10 decimal) lock length = 210 = 1024 bytes\n1011: (11 decimal) lock length = 211 = 2048 bytes\n1100: (12 decimal) lock length = 212 = 4096 bytes\n1101: (13 decimal) lock length = 213 = 8192 bytes\n1110: (14 decimal) lock length = 214 = 16384 bytes\n1111: (15 decimal) reserved\nBit 3 DMAEN: DMA enable bit\n0: DMA disabled.\n1: DMA enabled.\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1070/1757\nRM0090 Rev 21\nNote:\nAfter a data write, data cannot be written to this register for three SDIOCLK clock periods \nplus two PCLK2 clock periods.\nThe meaning of the DTMODE bit changes according to the value of the SDIOEN bit. When \nSDIOEN=0 and DTMODE=1, the MultiMediaCard stream mode is enabled, and when \nSDIOEN=1 and DTMODE=1, the peripheral enables an SDIO multibyte transfer.\n31.9.10 \nSDIO data counter register (SDIO_DCOUNT)\nAddress offset: 0x30\nReset value: 0x0000 0000\nThe SDIO_DCOUNT register loads the value from the data length register (see \nSDIO_DLEN) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As \ndata is transferred, the counter decrements the value until it reaches 0. The DPSM then \nmoves to the Idle state and the data status end flag, DATAEND, is set.\n \n \nNote:\nThis register should be read only when the data transfer is complete.\nBit 2 DTMODE: Data transfer mode selection 1: Stream or SDIO multibyte data transfer.\n0: Block data transfer\n1: Stream or SDIO multibyte data transfer\nBit 1 DTDIR: Data transfer direction selection\n0: From controller to card.\n1: From card to controller.\nBit 0 DTEN: Data transfer enabled bit\nData transfer starts if 1b is written to the DTEN bit. Depending on the direction bit, DTDIR, \nthe DPSM moves to the Wait_S, Wait_R state or Readwait if RW Start is set immediately at \nthe beginning of the transfer. It is not necessary to clear the enable bit after the end of a data \ntransfer but the SDIO_DCTRL must be updated to enable a new data transfer\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDATACOUNT\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:25 Reserved, must be kept at reset value\nBits 24:0 DATACOUNT: Data count value\nWhen this bit is read, the number of remaining data bytes to be transferred is returned. Write \nhas no effect.\n\n\n<>\n\nRM0090 Rev 21\n1071/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.9.11 \nSDIO status register (SDIO_STA)\nAddress offset: 0x34\nReset value: 0x0000 0000\nThe SDIO_STA register is a read-only register. It contains two types of flag:\n•\nStatic flags (bits [23:22,10:0]): these bits remain asserted until they are cleared by \nwriting to the SDIO Interrupt Clear register (see SDIO_ICR)\n•\nDynamic flags (bits [21:11]): these bits change state depending on the state of the \nunderlying logic (for example, FIFO full and empty flags are asserted and deasserted \nas data while written to the FIFO)\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCEATAEND\nSDIOIT\nRXDAVL\nTXDAVL\nRXFIFOE\nTXFIFOE\nRXFIFOF\nTXFIFOF\nRXFIFOHF\nTXFIFOHE\nRXACT\nTXACT\nCMDACT\nDBCKEND\nSTBITERR\nDATAEND\nCMDSENT\nCMDREND\nRXOVERR\nTXUNDERR\nDTIMEOUT\nCTIMEOUT\nDCRCFAIL\nCCRCFAIL\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:24 Reserved, must be kept at reset value\nBit 23 CEATAEND: CE-ATA command completion signal received for CMD61\nBit 22 SDIOIT: SDIO interrupt received\nBit 21 RXDAVL: Data available in receive FIFO\nBit 20 TXDAVL: Data available in transmit FIFO\nBit 19 RXFIFOE: Receive FIFO empty\nBit 18 TXFIFOE: Transmit FIFO empty\nWhen HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO \ncontains 2 words.\nBit 17 RXFIFOF: Receive FIFO full\nWhen HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the \nFIFO is full.\nBit 16 TXFIFOF: Transmit FIFO full\nBit 15 RXFIFOHF: Receive FIFO half full: there are at least 8 words in the FIFO\nBit 14 TXFIFOHE: Transmit FIFO half empty: at least 8 words can be written into the FIFO\nBit 13 RXACT: Data receive in progress\nBit 12 TXACT: Data transmit in progress\nBit 11 CMDACT: Command transfer in progress\nBit 10 DBCKEND: Data block sent/received (CRC check passed)\nBit 9 STBITERR: Start bit not detected on all data signals in wide bus mode\nBit 8 DATAEND: Data end (data counter, SDIDCOUNT, is zero)\nBit 7 CMDSENT: Command sent (no response required)\nBit 6 CMDREND: Command response received (CRC check passed)\nBit 5 RXOVERR: Received FIFO overrun error\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1072/1757\nRM0090 Rev 21\n31.9.12 \nSDIO interrupt clear register (SDIO_ICR)\nAddress offset: 0x38\nReset value: 0x0000 0000\nThe SDIO_ICR register is a write-only register. Writing a bit with 1b clears the corresponding \nbit in the SDIO_STA Status register.\n \n \nBit 4 TXUNDERR: Transmit FIFO underrun error\nBit 3 DTIMEOUT: Data timeout\nBit 2 CTIMEOUT: Command response timeout\nThe Command TimeOut period has a fixed value of 64 SDIO_CK clock periods.\nBit 1 DCRCFAIL: Data block sent/received (CRC check failed)\nBit 0 CCRCFAIL: Command response received (CRC check failed)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCEATAENDC\nSDIOITC\nReserved\nDBCKENDC\nSTBITERRC\nDATAENDC\nCMDSENTC\nCMDRENDC\nRXOVERRC\nTXUNDERRC\nDTIMEOUTC\nCTIMEOUTC\nDCRCFAILC\nCCRCFAILC\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value\nBit 23 CEATAENDC: CEATAEND flag clear bit\nSet by software to clear the CEATAEND flag.\n0: CEATAEND not cleared\n1: CEATAEND cleared\nBit 22 SDIOITC: SDIOIT flag clear bit\nSet by software to clear the SDIOIT flag.\n0: SDIOIT not cleared\n1: SDIOIT cleared\nBits 21:11 Reserved, must be kept at reset value\nBit 10 DBCKENDC: DBCKEND flag clear bit\nSet by software to clear the DBCKEND flag.\n0: DBCKEND not cleared\n1: DBCKEND cleared\nBit 9 STBITERRC: STBITERR flag clear bit\nSet by software to clear the STBITERR flag.\n0: STBITERR not cleared\n1: STBITERR cleared\nBit 8 DATAENDC: DATAEND flag clear bit\nSet by software to clear the DATAEND flag.\n0: DATAEND not cleared\n1: DATAEND cleared\n\n\n<>\n\nRM0090 Rev 21\n1073/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nBit 7 CMDSENTC: CMDSENT flag clear bit\nSet by software to clear the CMDSENT flag.\n0: CMDSENT not cleared\n1: CMDSENT cleared\nBit 6 CMDRENDC: CMDREND flag clear bit\nSet by software to clear the CMDREND flag.\n0: CMDREND not cleared\n1: CMDREND cleared\nBit 5 RXOVERRC: RXOVERR flag clear bit\nSet by software to clear the RXOVERR flag.\n0: RXOVERR not cleared\n1: RXOVERR cleared\nBit 4 TXUNDERRC: TXUNDERR flag clear bit\nSet by software to clear TXUNDERR flag.\n0: TXUNDERR not cleared\n1: TXUNDERR cleared\nBit 3 DTIMEOUTC: DTIMEOUT flag clear bit\nSet by software to clear the DTIMEOUT flag.\n0: DTIMEOUT not cleared\n1: DTIMEOUT cleared\nBit 2 CTIMEOUTC: CTIMEOUT flag clear bit\nSet by software to clear the CTIMEOUT flag.\n0: CTIMEOUT not cleared\n1: CTIMEOUT cleared\nBit 1 DCRCFAILC: DCRCFAIL flag clear bit\nSet by software to clear the DCRCFAIL flag.\n0: DCRCFAIL not cleared\n1: DCRCFAIL cleared\nBit 0 CCRCFAILC: CCRCFAIL flag clear bit\nSet by software to clear the CCRCFAIL flag.\n0: CCRCFAIL not cleared\n1: CCRCFAIL cleared\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1074/1757\nRM0090 Rev 21\n31.9.13 \nSDIO mask register (SDIO_MASK)\nAddress offset: 0x3C\nReset value: 0x0000 0000\nThe interrupt mask register determines which status flags generate an interrupt request by \nsetting the corresponding bit to 1b.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCEATAENDIE\nSDIOITIE\nRXDAVLIE\nTXDAVLIE\nRXFIFOEIE\nTXFIFOEIE\nRXFIFOFIE\nTXFIFOFIE\nRXFIFOHFIE\nTXFIFOHEIE\nRXACTIE\nTXACTIE\nCMDACTIE\nDBCKENDIE\nSTBITERRIE\nDATAENDIE\nCMDSENTIE\nCMDRENDIE\nRXOVERRIE\nTXUNDERRIE\nDTIMEOUTIE\nCTIMEOUTIE\nDCRCFAILIE\nCCRCFAILIE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value\nBit 23 CEATAENDIE: CE-ATA command completion signal received interrupt enable\nSet and cleared by software to enable/disable the interrupt generated when receiving the \nCE-ATA command completion signal.\n0: CE-ATA command completion signal received interrupt disabled\n1: CE-ATA command completion signal received interrupt enabled\nBit 22 SDIOITIE: SDIO mode interrupt received interrupt enable\nSet and cleared by software to enable/disable the interrupt generated when receiving the \nSDIO mode interrupt.\n0: SDIO Mode Interrupt Received interrupt disabled\n1: SDIO Mode Interrupt Received interrupt enabled\nBit 21 RXDAVLIE: Data available in Rx FIFO interrupt enable\nSet and cleared by software to enable/disable the interrupt generated by the presence of \ndata available in Rx FIFO.\n0: Data available in Rx FIFO interrupt disabled\n1: Data available in Rx FIFO interrupt enabled\nBit 20 TXDAVLIE: Data available in Tx FIFO interrupt enable\nSet and cleared by software to enable/disable the interrupt generated by the presence of \ndata available in Tx FIFO.\n0: Data available in Tx FIFO interrupt disabled\n1: Data available in Tx FIFO interrupt enabled\nBit 19 RXFIFOEIE: Rx FIFO empty interrupt enable\nSet and cleared by software to enable/disable interrupt caused by Rx FIFO empty.\n0: Rx FIFO empty interrupt disabled\n1: Rx FIFO empty interrupt enabled\nBit 18 TXFIFOEIE: Tx FIFO empty interrupt enable\nSet and cleared by software to enable/disable interrupt caused by Tx FIFO empty.\n0: Tx FIFO empty interrupt disabled\n1: Tx FIFO empty interrupt enabled\nBit 17 RXFIFOFIE: Rx FIFO full interrupt enable\nSet and cleared by software to enable/disable interrupt caused by Rx FIFO full.\n0: Rx FIFO full interrupt disabled\n1: Rx FIFO full interrupt enabled\n\n\n<>\n\nRM0090 Rev 21\n1075/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nBit 16 TXFIFOFIE: Tx FIFO full interrupt enable\nSet and cleared by software to enable/disable interrupt caused by Tx FIFO full.\n0: Tx FIFO full interrupt disabled\n1: Tx FIFO full interrupt enabled\nBit 15 RXFIFOHFIE: Rx FIFO half full interrupt enable\nSet and cleared by software to enable/disable interrupt caused by Rx FIFO half full.\n0: Rx FIFO half full interrupt disabled\n1: Rx FIFO half full interrupt enabled\nBit 14 TXFIFOHEIE: Tx FIFO half empty interrupt enable\nSet and cleared by software to enable/disable interrupt caused by Tx FIFO half empty.\n0: Tx FIFO half empty interrupt disabled\n1: Tx FIFO half empty interrupt enabled\nBit 13 RXACTIE: Data receive acting interrupt enable\nSet and cleared by software to enable/disable interrupt caused by data being received (data \nreceive acting).\n0: Data receive acting interrupt disabled\n1: Data receive acting interrupt enabled\nBit 12 TXACTIE: Data transmit acting interrupt enable\nSet and cleared by software to enable/disable interrupt caused by data being transferred \n(data transmit acting).\n0: Data transmit acting interrupt disabled\n1: Data transmit acting interrupt enabled\nBit 11 CMDACTIE: Command acting interrupt enable\nSet and cleared by software to enable/disable interrupt caused by a command being \ntransferred (command acting).\n0: Command acting interrupt disabled\n1: Command acting interrupt enabled\nBit 10 DBCKENDIE: Data block end interrupt enable\nSet and cleared by software to enable/disable interrupt caused by data block end.\n0: Data block end interrupt disabled\n1: Data block end interrupt enabled\nBit 9 STBITERRIE: Start bit error interrupt enable\nSet and cleared by software to enable/disable interrupt caused by start bit error.\n0: Start bit error interrupt disabled\n1: Start bit error interrupt enabled\nBit 8 DATAENDIE: Data end interrupt enable\nSet and cleared by software to enable/disable interrupt caused by data end.\n0: Data end interrupt disabled\n1: Data end interrupt enabled\nBit 7 CMDSENTIE: Command sent interrupt enable\nSet and cleared by software to enable/disable interrupt caused by sending command.\n0: Command sent interrupt disabled\n1: Command sent interrupt enabled\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1076/1757\nRM0090 Rev 21\n31.9.14 \nSDIO FIFO counter register (SDIO_FIFOCNT)\nAddress offset: 0x48\nReset value: 0x0000 0000\nThe SDIO_FIFOCNT register contains the remaining number of words to be written to or \nread from the FIFO. The FIFO counter loads the value from the data length register (see \nSDIO_DLEN) when the data transfer enable bit, DTEN, is set in the data control register \n(SDIO_DCTRL register) and the DPSM is at the Idle state. If the data length is not word-\naligned (multiple of 4), the remaining 1 to 3 bytes are regarded as a word.\n \n \nBit 6 CMDRENDIE: Command response received interrupt enable\nSet and cleared by software to enable/disable interrupt caused by receiving command \nresponse.\n0: Command response received interrupt disabled\n1: command Response Received interrupt enabled\nBit 5 RXOVERRIE: Rx FIFO overrun error interrupt enable\nSet and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error.\n0: Rx FIFO overrun error interrupt disabled\n1: Rx FIFO overrun error interrupt enabled\nBit 4 TXUNDERRIE: Tx FIFO underrun error interrupt enable\nSet and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error.\n0: Tx FIFO underrun error interrupt disabled\n1: Tx FIFO underrun error interrupt enabled\nBit 3 DTIMEOUTIE: Data timeout interrupt enable\nSet and cleared by software to enable/disable interrupt caused by data timeout.\n0: Data timeout interrupt disabled\n1: Data timeout interrupt enabled\nBit 2 CTIMEOUTIE: Command timeout interrupt enable\nSet and cleared by software to enable/disable interrupt caused by command timeout.\n0: Command timeout interrupt disabled\n1: Command timeout interrupt enabled\nBit 1 DCRCFAILIE: Data CRC fail interrupt enable\nSet and cleared by software to enable/disable interrupt caused by data CRC failure.\n0: Data CRC fail interrupt disabled\n1: Data CRC fail interrupt enabled\nBit 0 CCRCFAILIE: Command CRC fail interrupt enable\nSet and cleared by software to enable/disable interrupt caused by command CRC failure.\n0: Command CRC fail interrupt disabled\n1: Command CRC fail interrupt enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFIFOCOUNT\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:24 Reserved, must be kept at reset value\nBits 23:0\nFIFOCOUNT: Remaining number of words to be written to or read from the FIFO.\n\n\n<>\n\nRM0090 Rev 21\n1077/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.9.15 \nSDIO data FIFO register (SDIO_FIFO)\nAddress offset: 0x80\nReset value: 0x0000 0000\nThe receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs \ncontain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store \nmultiple operands to read from/write to the FIFO.\n \n \n31.9.16 \nSDIO register map\nThe following table summarizes the SDIO registers. \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFIF0Data\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nbits 31:0 FIFOData: Receive and transmit FIFO data\nThe FIFO data occupies 32 entries of 32-bit words, from address:\nSDIO base + 0x080 to SDIO base + 0xFC.\nTable 182. SDIO register map\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nSDIO_POWER\nReserved\nPWRCTRL\n0x04\nSDIO_CLKCR\nReserved\nHWFC_EN\nNEGEDGE\nWIDBUS\nBYPASS\nPWRSAV\nCLKEN\nCLKDIV\n0x08\nSDIO_ARG\nCMDARG\n0x0C\nSDIO_CMD\nReserved\nCE-ATACMD\nnIEN\nENCMDcompl\nSDIOSuspend\nCPSMEN\nWAITPEND\nWAITINT\nWAITRESP\nCMDINDEX\n0x10\nSDIO_RESPCMD\nReserved\nRESPCMD\n0x14\nSDIO_RESP1\nCARDSTATUS1\n0x18\nSDIO_RESP2\nCARDSTATUS2\n0x1C\nSDIO_RESP3\nCARDSTATUS3\n0x20\nSDIO_RESP4\nCARDSTATUS4\n0x24\nSDIO_DTIMER\nDATATIME\n0x28\nSDIO_DLEN\nReserved\nDATALENGTH\n0x2C\nSDIO_DCTRL\nReserved\nSDIOEN\nRWMOD\nRWSTOP\nRWSTART\nDBLOCKSIZE\nDMAEN\nDTMODE\nDTDIR\nDTEN\n0x30\nSDIO_DCOUNT\nReserved\nDATACOUNT\n\n\n<>\n\nSecure digital input/output interface (SDIO)\nRM0090\n1078/1757\nRM0090 Rev 21\n0x34\nSDIO_STA\nReserved\nCEATAEND\nSDIOIT\nRXDAVL\nTXDAVL\nRXFIFOE\nTXFIFOE\nRXFIFOF\nTXFIFOF\nRXFIFOHF\nTXFIFOHE\nRXACT\nTXACT\nCMDACT\nDBCKEND\nSTBITERR\nDATAEND\nCMDSENT\nCMDREND\nRXOVERR\nTXUNDERR\nDTIMEOUT\nCTIMEOUT\nDCRCFAIL\nCCRCFAIL\n0x38\nSDIO_ICR\nReserved\nCEATAENDC\nSDIOITC\nReserved\nDBCKENDC\nSTBITERRC\nDATAENDC\nCMDSENTC\nCMDRENDC\nRXOVERRC\nTXUNDERRC\nDTIMEOUTC\nCTIMEOUTC\nDCRCFAILC\nCCRCFAILC\n0x3C\nSDIO_MASK\nReserved\nCEATAENDIE\nSDIOITIE\nRXDAVLIE\nTXDAVLIE\nRXFIFOEIE\nTXFIFOEIE\nRXFIFOFIE\nTXFIFOFIE\nRXFIFOHFIE\nTXFIFOHEIE\nRXACTIE\nTXACTIE\nCMDACTIE\nDBCKENDIE\nSTBITERRIE\nDATAENDIE\nCMDSENTIE\nCMDRENDIE\nRXOVERRIE\nTXUNDERRIE\nDTIMEOUTIE\nCTIMEOUTIE\nDCRCFAILIE\nCCRCFAILIE\n0x48\nSDIO_FIFOCNT\nReserved\nFIFOCOUNT\n0x80\nSDIO_FIFO\nFIF0Data\nTable 182. SDIO register map (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1079/1757\nRM0090\nController area network (bxCAN)\n1124\n32 \nController area network (bxCAN)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n32.1 \nbxCAN introduction\nThe Basic Extended CAN peripheral, named bxCAN, interfaces the CAN network. It \nsupports the CAN protocols version 2.0A and B. It has been designed to manage a high \nnumber of incoming messages efficiently with a minimum CPU load. It also meets the \npriority requirements for transmit messages. \nFor safety-critical applications, the CAN controller provides all hardware functions for \nsupporting the CAN Time Triggered Communication option.\n32.2 \nbxCAN main features\n•\nSupports CAN protocol version 2.0 A, B Active\n•\nBit rates up to 1 Mbit/s\n•\nSupports the Time Triggered Communication option\nTransmission\n•\nThree transmit mailboxes\n•\nConfigurable transmit priority\n•\nTime Stamp on SOF transmission\nReception\n•\nTwo receive FIFOs with three stages\n•\nScalable filter banks:\n–\n28 filter banks shared between CAN1 and CAN2\n•\nIdentifier list feature\n•\nConfigurable FIFO overrun\n•\nTime Stamp on SOF reception\nTime-triggered communication option\n•\nDisable automatic retransmission mode\n•\n16-bit free running timer\n•\nTime Stamp sent in last two data bytes\nManagement\n•\nMaskable interrupts\n•\nSoftware-efficient mailbox mapping at a unique address space\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1080/1757\nRM0090 Rev 21\nDual CAN\n•\nCAN1: Master bxCAN for managing the communication between a Slave bxCAN and \nthe 512-byte SRAM memory\n•\nCAN2: Slave bxCAN, with no direct access to the SRAM memory. \n•\nThe two bxCAN cells share the 512-byte SRAM memory (see Figure 335)\n32.3 \nbxCAN general description\nIn today’s CAN applications, the number of nodes in a network is increasing and often \nseveral networks are linked together via gateways. Typically the number of messages in the \nsystem (and thus to be handled by each node) has significantly increased. In addition to the \napplication messages, Network Management and Diagnostic messages have been \nintroduced. \n•\nAn enhanced filtering mechanism is required to handle each type of message.\nFurthermore, application tasks require more CPU time, therefore real-time constraints \ncaused by message reception have to be reduced.\n•\nA receive FIFO scheme allows the CPU to be dedicated to application tasks for a long \ntime period without losing messages.\nThe standard HLP (Higher Layer Protocol) based on standard CAN drivers requires an \nefficient interface to the CAN controller.\nFigure 334. CAN network topology\n32.3.1 \nCAN 2.0B active core\nThe bxCAN module handles the transmission and the reception of CAN messages fully \nautonomously. Standard identifiers (11-bit) and extended identifiers (29-bit) are fully \nsupported by hardware.\nCAN node 1\nCAN node 2\nCAN node n\nCAN\nCAN\nHigh\nLow\nCAN\nCAN\nRx\nTx\nCAN\nTransceiver\nCAN\nController\nMCU\nCAN Bus\nApplication\n\n\n<>\n\nRM0090 Rev 21\n1081/1757\nRM0090\nController area network (bxCAN)\n1124\n32.3.2 \nControl, status and configuration registers\nThe application uses these registers to:\n•\nConfigure CAN parameters, e.g. baud rate\n•\nRequest transmissions\n•\nHandle receptions\n•\nManage interrupts\n•\nGet diagnostic information\n32.3.3 \nTx mailboxes\nThree transmit mailboxes are provided to the software for setting up messages. The \ntransmission Scheduler decides which mailbox has to be transmitted first.\n32.3.4 \nAcceptance filters\nThe bxCAN provides 28 scalable/configurable identifier filter banks for selecting the \nincoming messages the software needs and discarding the others. \nReceive FIFO\nTwo receive FIFOs are used by hardware to store the incoming messages. Three complete \nmessages can be stored in each FIFO. The FIFOs are managed completely by hardware. \n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1082/1757\nRM0090 Rev 21\nFigure 335. Dual CAN block diagram\n32.4 \nbxCAN operating modes\nbxCAN has three main operating modes: initialization, normal and Sleep. After a \nhardware reset, bxCAN is in Sleep mode to reduce power consumption and an internal pull-\nup is active on CANTX. The software requests bxCAN to enter initialization or Sleep mode \nby setting the INRQ or SLEEP bits in the CAN_MCR register. Once the mode has been \nentered, bxCAN confirms it by setting the INAK or SLAK bits in the CAN_MSR register and \nthe internal pull-up is disabled. When neither INAK nor SLAK are set, bxCAN is in normal \n26\n..\nAcceptance Filters\n..\n3\n2\n1\nFilter \n0\n27\nTransmission\nScheduler\nMailbox 0\n1\n2\nReceive FIFO 1\nMailbox 0\n1\n2\nReceive FIFO 0\nMailbox 0\n1\n2\nTx Mailboxes\nTransmission\nScheduler\nMailbox 0\n1\n2\nReceive FIFO 1\nMailbox 0\n1\n2\nReceive FIFO 0\nMailbox 0\n1\n2\nTx Mailboxes\nMemory \nAccess \nController\nMaster Control\nMaster Status\nRx FIFO 0 Status\nRx FIFO 1 Status\nError Status\nBit Timing\nInterrupt Enable\nControl/Status/Configuration\nTx Status\nMaster Control\nMaster Status\nRx FIFO 0 Status\nRx FIFO 1 Status\nError Status\nBit Timing\nFilter Mode\nFilter Scale\nInterrupt Enable\nControl/Status/Configuration\nTx Status\nFilter FIFO Assign\nFilter Master\nFilter Activation\nCAN 2.0B Active Core\nCAN2 (Slave)\nCAN 2.0B Active Core\nCAN1 (Master) with 512 bytes SRAM\nMaster\nr\ne\nts\na\nM\nr\ne\nts\na\nM\nMaster Filters\nSlave\nSlave\nSlave\nSlave Filters\n(0 to 27)\n(0 to 27)\nNote: CAN 2 start filter bank number n is confi gurable by writing to\nthe CAN2SB[5:0] bits in the CAN_ FMR register.\nai16094b\n\n\n<>\n\nRM0090 Rev 21\n1083/1757\nRM0090\nController area network (bxCAN)\n1124\nmode. Before entering normal mode bxCAN always has to synchronize on the CAN bus. \nTo synchronize, bxCAN waits until the CAN bus is idle, this means 11 consecutive recessive \nbits have been monitored on CANRX.\n32.4.1 \nInitialization mode\nThe software initialization can be done while the hardware is in Initialization mode. To enter \nthis mode the software sets the INRQ bit in the CAN_MCR register and waits until the \nhardware has confirmed the request by setting the INAK bit in the CAN_MSR register.\nTo leave Initialization mode, the software clears the INRQ bit. bxCAN has left Initialization \nmode once the INAK bit has been cleared by hardware.\nWhile in Initialization Mode, all message transfers to and from the CAN bus are stopped and \nthe status of the CAN bus output CANTX is recessive (high). \nEntering Initialization Mode does not change any of the configuration registers.\nTo initialize the CAN Controller, software has to set up the Bit Timing (CAN_BTR) and CAN \noptions (CAN_MCR) registers. \nTo initialize the registers associated with the CAN filter banks (mode, scale, FIFO \nassignment, activation and filter values), software has to set the FINIT bit (CAN_FMR). Filter \ninitialization also can be done outside the initialization mode. \nNote:\nWhen FINIT=1, CAN reception is deactivated.\nThe filter values also can be modified by deactivating the associated filter activation bits (in \nthe CAN_FA1R register). \nIf a filter bank is not used, it is recommended to leave it non active (leave the corresponding \nFACT bit cleared).\n32.4.2 \nNormal mode\nOnce the initialization is complete, the software must request the hardware to enter Normal \nmode to be able to synchronize on the CAN bus and start reception and transmission.\nThe request to enter Normal mode is issued by clearing the INRQ bit in the CAN_MCR \nregister. The bxCAN enters Normal mode and is ready to take part in bus activities when it \nhas synchronized with the data transfer on the CAN bus. This is done by waiting for the \noccurrence of a sequence of 11 consecutive recessive bits (Bus Idle state). The switch to \nNormal mode is confirmed by the hardware by clearing the INAK bit in the CAN_MSR \nregister.\nThe initialization of the filter values is independent from Initialization Mode but must be done \nwhile the filter is not active (corresponding FACTx bit cleared). The filter scale and mode \nconfiguration must be configured before entering Normal Mode.\n32.4.3 \nSleep mode (low-power)\nTo reduce power consumption, bxCAN has a low-power mode called Sleep mode. This \nmode is entered on software request by setting the SLEEP bit in the CAN_MCR register. In \nthis mode, the bxCAN clock is stopped, however software can still access the bxCAN \nmailboxes. \nIf software requests entry to initialization mode by setting the INRQ bit while bxCAN is in \nSleep mode, it must also clear the SLEEP bit.\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1084/1757\nRM0090 Rev 21\nbxCAN can be woken up (exit Sleep mode) either by software clearing the SLEEP bit or on \ndetection of CAN bus activity.\nOn CAN bus activity detection, hardware automatically performs the wake-up sequence by \nclearing the SLEEP bit if the AWUM bit in the CAN_MCR register is set. If the AWUM bit is \ncleared, software has to clear the SLEEP bit when a wake-up interrupt occurs, in order to \nexit from Sleep mode.\nNote:\nIf the wake-up interrupt is enabled (WKUIE bit set in CAN_IER register) a wake-up interrupt \nis generated on detection of CAN bus activity, even if the bxCAN automatically performs the \nwake-up sequence.\nAfter the SLEEP bit has been cleared, Sleep mode is exited once bxCAN has synchronized \nwith the CAN bus, refer to Figure 336. The Sleep mode is exited once the SLAK bit has \nbeen cleared by hardware.\nFigure 336. bxCAN operating modes\n1.\nACK = The wait state during which hardware confirms a request by setting the INAK or SLAK bits in the \nCAN_MSR register\n2.\nSYNC = The state during which bxCAN waits until the CAN bus is idle, meaning 11 consecutive recessive \nbits have been monitored on CANRX\n32.5 \nTest mode\nTest mode can be selected by the SILM and LBKM bits in the CAN_BTR register. These bits \nmust be configured while bxCAN is in Initialization mode. Once test mode has been \nselected, the INRQ bit in the CAN_MCR register must be reset to enter Normal mode.\n32.5.1 \nSilent mode\nThe bxCAN can be put in Silent mode by setting the SILM bit in the CAN_BTR register.\nIn Silent mode, the bxCAN is able to receive valid data frames and valid remote frames, but \nit sends only recessive bits on the CAN bus and it cannot start a transmission. If the bxCAN \nhas to send a dominant bit (ACK bit, overload flag, active error flag), the bit is rerouted \ninternally so that the CAN Core monitors this dominant bit, although the CAN bus may \nSleep\nInitialization\nNormal\nReset\nSLAK= 1\nINAK = 0\nSLAK= 0\nINAK = 1\nSLAK= 0\nINAK = 0\nSLEEP . INRQ . ACK\nSLEEP . INRQ . ACK\nINRQ . ACK\nINRQ . SYNC . SLEEP\nSLEEP . ACK\nSLEEP . SYNC . INRQ \nai15902\n\n\n<>\n\nRM0090 Rev 21\n1085/1757\nRM0090\nController area network (bxCAN)\n1124\nremain in recessive state. Silent mode can be used to analyze the traffic on a CAN bus \nwithout affecting it by the transmission of dominant bits (Acknowledge Bits, Error Frames).\nFigure 337. bxCAN in silent mode\n32.5.2 \nLoop back mode\nThe bxCAN can be set in Loop Back Mode by setting the LBKM bit in the CAN_BTR \nregister. In Loop Back Mode, the bxCAN treats its own transmitted messages as received \nmessages and stores them (if they pass acceptance filtering) in a Receive mailbox. \nFigure 338. bxCAN in loop back mode\nThis mode is provided for self-test functions. To be independent of external events, the CAN \nCore ignores acknowledge errors (no dominant bit sampled in the acknowledge slot of a \ndata / remote frame) in Loop Back Mode. In this mode, the bxCAN performs an internal \nfeedback from its Tx output to its Rx input. The actual value of the CANRX input pin is \ndisregarded by the bxCAN. The transmitted messages can be monitored on the CANTX pin.\n32.5.3 \nLoop back combined with silent mode\nIt is also possible to combine Loop Back mode and Silent mode by setting the LBKM and \nSILM bits in the CAN_BTR register. This mode can be used for a “Hot Selftest”, meaning the \nbxCAN can be tested like in Loop Back mode but without affecting a running CAN system \nconnected to the CANTX and CANRX pins. In this mode, the CANRX pin is disconnected \nfrom the bxCAN and the CANTX pin is held recessive. \nbxCAN\nCANTX CANRX\nTx\nRx\n=1\nbxCAN\nCANTX CANRX\nTx\nRx\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1086/1757\nRM0090 Rev 21\nFigure 339. bxCAN in combined mode\n32.6 \nDebug mode\nWhen the microcontroller enters the debug mode (Cortex®-M4 with FPU core halted), the \nbxCAN continues to work normally or stops, depending on:\n•\nthe DBG_CAN1_STOP bit for CAN1 or the DBG_CAN2_STOP bit for CAN2 in the \nDBG module. For more details, refer to Section 38.16.2: Debug support for timers, \nwatchdog, bxCAN and I2C.\n•\nthe DBF bit in CAN_MCR. For more details, refer to Section 32.9.2.\n32.7 \nbxCAN functional description\n32.7.1 \nTransmission handling\nIn order to transmit a message, the application must select one empty transmit mailbox, set \nup the identifier, the data length code (DLC) and the data before requesting the transmission \nby setting the corresponding TXRQ bit in the CAN_TIxR register. Once the mailbox has left \nempty state, the software no longer has write access to the mailbox registers. Immediately \nafter the TXRQ bit has been set, the mailbox enters pending state and waits to become the \nhighest priority mailbox, see Transmit Priority. As soon as the mailbox has the highest \npriority it is scheduled for transmission. The transmission of the message of the scheduled \nmailbox starts (enters transmit state) when the CAN bus becomes idle. Once the mailbox \nhas been successfully transmitted, it becomes empty again. The hardware indicates a \nsuccessful transmission by setting the RQCP and TXOK bits in the CAN_TSR register. \nIf the transmission fails, the cause is indicated by the ALST bit in the CAN_TSR register in \ncase of an Arbitration Lost, and/or the TERR bit, in case of transmission error detection.\nbxCAN\nCANTX CANRX\nTx\nRx\n=1\n\n\n<>\n\nRM0090 Rev 21\n1087/1757\nRM0090\nController area network (bxCAN)\n1124\nTransmit priority\n \nAbort\nA transmission request can be aborted by the user setting the ABRQ bit in the CAN_TSR \nregister. In pending or scheduled state, the mailbox is aborted immediately. An abort \nrequest while the mailbox is in transmit state can have two results. If the mailbox is \ntransmitted successfully the mailbox becomes empty with the TXOK bit set in the \nCAN_TSR register. If the transmission fails, the mailbox becomes scheduled, the \ntransmission is aborted and becomes empty with TXOK cleared. In all cases the mailbox \nbecomes empty again at least at the end of the current transmission.\nNonautomatic retransmission mode\nThis mode has been implemented in order to fulfil the requirement of the Time Triggered \nCommunication option of the CAN standard. To configure the hardware in this mode the \nNART bit in the CAN_MCR register must be set.\nIn this mode, each transmission is started only once. If the first attempt fails, due to an \narbitration loss or an error, the hardware does not automatically restart the message \ntransmission.\nAt the end of the first transmission attempt, the hardware considers the request as \ncompleted and sets the RQCP bit in the CAN_TSR register. The result of the transmission is \nindicated in the CAN_TSR register by the TXOK, ALST and TERR bits.\nBy identifier\nWhen more than one transmit mailbox is pending, the \ntransmission order is given by the identifier of the message \nstored in the mailbox. The message with the lowest identifier \nvalue has the highest priority according to the arbitration of the \nCAN protocol. If the identifier values are equal, the lower mailbox \nnumber is scheduled first.\nBy transmit request order The transmit mailboxes can be configured as a transmit FIFO by \nsetting the TXFP bit in the CAN_MCR register. In this mode the \npriority order is given by the transmit request order. This mode is \nvery useful for segmented transmission.\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1088/1757\nRM0090 Rev 21\nFigure 340. Transmit mailbox states\n32.7.2 \nTime triggered communication mode\nIn this mode, the internal counter of the CAN hardware is activated and used to generate the \nTime Stamp value stored in the CAN_RDTxR/CAN_TDTxR registers, respectively (for Rx \nand Tx mailboxes). The internal counter is incremented each CAN bit time (refer to \nSection 32.7.7). The internal counter is captured on the sample point of the Start Of Frame \nbit in both reception and transmission. \n32.7.3 \nReception handling\nFor the reception of CAN messages, three mailboxes organized as a FIFO are provided. In \norder to save CPU load, simplify the software and guarantee data consistency, the FIFO is \nmanaged completely by hardware. The application accesses the messages stored in the \nFIFO through the FIFO output mailbox.\nValid message\nA received message is considered as valid when it has been received correctly according to \nthe CAN protocol (no error until the last but one bit of the EOF field) and It passed through \nthe identifier filtering successfully, see Section 32.7.4.\nEMPTY\nTXRQ=1\nRQCP=X\nTXOK=X\nPENDING\nRQCP=0\nTXOK=0\nSCHEDULED\nRQCP=0\nTXOK=0\nMailbox has\nTRANSMIT\nRQCP=0\nTXOK=0\nCAN Bus = IDLE\nTransmit failed * NART\nTransmit succeeded\nMailbox does not\nEMPTY\nRQCP=1\nTXOK=0\nhighest priority\nhave highest priority\nEMPTY\nRQCP=1\nTXOK=1\nABRQ=1\nABRQ=1\nTransmit failed * NART\nTME = 1\nTME = 0\nTME = 0\nTME = 0\nTME = 1\nTME = 1\n\n\n<>\n\nRM0090 Rev 21\n1089/1757\nRM0090\nController area network (bxCAN)\n1124\nFigure 341. Receive FIFO states\nFIFO management\nStarting from the empty state, the first valid message received is stored in the FIFO which \nbecomes pending_1. The hardware signals the event setting the FMP[1:0] bits in the \nCAN_RFR register to the value 01b. The message is available in the FIFO output mailbox. \nThe software reads out the mailbox content and releases it by setting the RFOM bit in the \nCAN_RFR register. The FIFO becomes empty again. If a new valid message has been \nreceived in the meantime, the FIFO stays in pending_1 state and the new message is \navailable in the output mailbox. \nIf the application does not release the mailbox, the next valid message is stored in the FIFO \nwhich enters pending_2 state (FMP[1:0] = 10b). The storage process is repeated for the \nnext valid message putting the FIFO into pending_3 state (FMP[1:0] = 11b). At this point, \nthe software must release the output mailbox by setting the RFOM bit, so that a mailbox is \nfree to store the next valid message. Otherwise the next valid message received causes a \nloss of message.\nRefer also to Section 32.7.5\nOverrun\nOnce the FIFO is in pending_3 state (i.e. the three mailboxes are full) the next valid \nmessage reception leads to an overrun and a message is lost. The hardware signals the \nEMPTY\nValid Message\nFMP=0x00\nFOVR=0\nPENDING_1\nFMP=0x01\nFOVR=0\nReceived\nPENDING_2\nFMP=0x10\nFOVR=0\nPENDING_3\nFMP=0x11\nFOVR=0\nValid Message\nReceived\nRelease\nOVERRUN\nFMP=0x11\nFOVR=1\nMailbox\nRelease\nMailbox\nValid Message\nReceived\nValid Message\nReceived\nRelease\nMailbox\nRelease\nMailbox\nValid Message\nReceived\nRFOM=1 \nRFOM=1\nRFOM=1\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1090/1757\nRM0090 Rev 21\noverrun condition by setting the FOVR bit in the CAN_RFR register. Which message is lost \ndepends on the configuration of the FIFO:\n•\nIf the FIFO lock function is disabled (RFLM bit in the CAN_MCR register cleared) the \nlast message stored in the FIFO is overwritten by the new incoming message. In this \ncase the latest messages are always available to the application.\n•\nIf the FIFO lock function is enabled (RFLM bit in the CAN_MCR register set) the most \nrecent message is discarded and the software has the three oldest messages in the \nFIFO available.\nReception related interrupts\nOnce a message has been stored in the FIFO, the FMP[1:0] bits are updated and an \ninterrupt request is generated if the FMPIE bit in the CAN_IER register is set.\nWhen the FIFO becomes full (i.e. a third message is stored) the FULL bit in the CAN_RFR \nregister is set and an interrupt is generated if the FFIE bit in the CAN_IER register is set.\nOn overrun condition, the FOVR bit is set and an interrupt is generated if the FOVIE bit in \nthe CAN_IER register is set.\n32.7.4 \nIdentifier filtering\nIn the CAN protocol the identifier of a message is not associated with the address of a node \nbut related to the content of the message. Consequently a transmitter broadcasts its \nmessage to all receivers. On message reception a receiver node decides - depending on \nthe identifier value - whether the software needs the message or not. If the message is \nneeded, it is copied into the SRAM. If not, the message must be discarded without \nintervention by the software.\nTo fulfill this requirement, the bxCAN Controller provides 28 configurable and scalable filter \nbanks (27-0) to the application. This hardware filtering saves CPU resources which would \nbe otherwise needed to perform filtering by software. Each filter bank x consists of two 32-bit \nregisters, CAN_FxR0 and CAN_FxR1. \nScalable width\nTo optimize and adapt the filters to the application needs, each filter bank can be scaled \nindependently. Depending on the filter scale a filter bank provides:\n•\nOne 32-bit filter for the STDID[10:0], EXTID[17:0], IDE and RTR bits.\n•\nTwo 16-bit filters for the STDID[10:0], RTR, IDE and EXTID[17:15] bits.\nRefer to Figure 342.\nFurthermore, the filters can be configured in mask mode or in identifier list mode. \nMask mode \nIn mask mode the identifier registers are associated with mask registers specifying which \nbits of the identifier are handled as “must match” or as “don’t care”. \nIdentifier list mode\nIn identifier list mode, the mask registers are used as identifier registers. Thus instead of \ndefining an identifier and a mask, two identifiers are specified, doubling the number of single \nidentifiers. All bits of the incoming identifier must match the bits specified in the filter \nregisters.\n\n\n<>\n\nRM0090 Rev 21\n1091/1757\nRM0090\nController area network (bxCAN)\n1124\nFilter bank scale and mode configuration\nThe filter banks are configured by means of the corresponding CAN_FMR register. To \nconfigure a filter bank it must be deactivated by clearing the FACT bit in the CAN_FAR \nregister. The filter scale is configured by means of the corresponding FSCx bit in the \nCAN_FS1R register, refer to Figure 342. The identifier list or identifier mask mode for the \ncorresponding Mask/Identifier registers is configured by means of the FBMx bits in the \nCAN_FMR register.\nTo filter a group of identifiers, configure the Mask/Identifier registers in mask mode. \nTo select single identifiers, configure the Mask/Identifier registers in identifier list mode.\nFilters not used by the application should be left deactivated.\nEach filter within a filter bank is numbered (called the Filter Number) from 0 to a maximum \ndependent on the mode and the scale of each of the filter banks.\nConcerning the filter configuration, refer to Figure 342.\nFigure 342. Filter bank scale configuration - register organization\nFilter match index\nOnce a message has been received in the FIFO it is available to the application. Typically, \napplication data is copied into SRAM locations. To copy the data to the right location the \nOne 32-Bit Filter - Identifier Mask\nTwo 16-Bit Filters - Identifier Mask\nCAN_FxR1[31:24]\nCAN_FxR2[31:24]\nCAN_FxR1[15:8]\nCAN_FxR1[31:24]\nCAN_FxR1[7:0]\nCAN_FxR1[23:16]\nx = filter bank number\nFSCx = 1\nFSCx = 0\n1 These bits are located in the CAN_FS1R register\nFilter Bank Scale \nID\nMask\nID\nMask\nSTID[10:3]\nSTID[2:0] \nEXID[12:5]\nMapping\nSTID[10:3]\n \nID\nMask\nMapping\nRTR\nTwo 32-Bit Filters - Identifier List\nID\nID\nSTID[10:3]\nSTID[2:0]\nEXID[12:5]\nMapping\nFour 16-Bit Filters - Identifier List\nID\nID\nSTID[10:3]\nID\nID\nMapping\nn\nn+1\nn+2\nn+3\nn+1\nFilter Bank Mode2\nn\nn\nn+1\nEXID[4:0]\nIDE\nEXID[17:13]\nEXID[17:13]\nSTID[2:0] RTR IDE EXID[17:15]\nFBMx = 0\nFBMx = 1\nFilter \n2 These bits are located in the CAN_FM1R register\nn\nNum.\nFBMx = 0\nFBMx = 1\nConfig. Bits1\n STID[2:0] RTR IDE EXID[17:15]\n0\nRTR\nEXID[4:0]\nIDE\n0\nCAN_FxR1[23:16]\nCAN_FxR1[15:8]\nCAN_FxR1[7:0]\nCAN_FxR2[7:0]\nCAN_FxR2[15:8]\nCAN_FxR2[23:16]\nCAN_FxR1[31:24]\nCAN_FxR2[31:24]\nCAN_FxR1[23:16]\nCAN_FxR1[15:8]\nCAN_FxR1[7:0]\nCAN_FxR2[7:0]\nCAN_FxR2[15:8]\nCAN_FxR2[23:16]\nCAN_FxR2[15:8]\nCAN_FxR2[31:24]\nCAN_FxR2[7:0]\nCAN_FxR2[23:16]\nCAN_FxR1[15:8]\nCAN_FxR1[31:24]\nCAN_FxR1[7:0]\nCAN_FxR1[23:16]\nCAN_FxR2[15:8]\nCAN_FxR2[31:24]\nCAN_FxR2[7:0]\nCAN_FxR2[23:16]\nID=Identifier\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1092/1757\nRM0090 Rev 21\napplication has to identify the data by means of the identifier. To avoid this, and to ease the \naccess to the SRAM locations, the CAN controller provides a Filter Match Index.\nThis index is stored in the mailbox together with the message according to the filter priority \nrules. Thus each received message has its associated filter match index.\nThe Filter Match index can be used in two ways:\n•\nCompare the Filter Match index with a list of expected values.\n•\nUse the Filter Match Index as an index on an array to access the data destination \nlocation.\nFor nonmasked filters, the software no longer has to compare the identifier. \nIf the filter is masked the software reduces the comparison to the masked bits only.\nThe index value of the filter number does not take into account the activation state of the \nfilter banks. In addition, two independent numbering schemes are used, one for each FIFO. \nRefer to Figure 343 for an example.\nFigure 343. Example of filter numbering\n9\n8\nID List (32-bit)\nID Mask (32-bit)\nID List (16-bit)\nID List (32-bit)\nDeactivated\nID Mask (16-bit)\nID List (32-bit)\nFilter \n0\n1\n3\n5\n6\n9\nID Mask (32-bit)\n13\nFIFO0\nFilter \n0\n1\n2\n3\n4\n5\n6\n7\n10\n11\n12\n13\nID Mask (16-bit)\nID List (32-bit)\nID Mask (16-bit)\nID List (16-bit)\nDeactivated\nID Mask (16-bit)\nID List (32-bit)\nFilter \n2\n4\n7\n8\n10\n11\nID Mask (32-bit)\n12\nFIFO1\nFilter \n0\n1\n2\n4\n5\n6\n7\n8\n11\n12\n13\n14\n3\nDeactivated\n9\n10\nNum.\nNum.\nBank\nBank\nID = Identifier\n\n\n<>\n\nRM0090 Rev 21\n1093/1757\nRM0090\nController area network (bxCAN)\n1124\nFilter priority rules\nDepending on the filter combination it may occur that an identifier passes successfully \nthrough several filters. In this case the filter match value stored in the receive mailbox is \nchosen according to the following priority rules:\n•\nA 32-bit filter takes priority over a 16-bit filter.\n•\nFor filters of equal scale, priority is given to the Identifier List mode over the Identifier \nMask mode\n•\nFor filters of equal scale and mode, priority is given by the filter number (the lower the \nnumber, the higher the priority).\nFigure 344. Filtering mechanism - Example\nThe example above shows the filtering principle of the bxCAN. On reception of a message, \nthe identifier is compared first with the filters configured in identifier list mode. If there is a \nmatch, the message is stored in the associated FIFO and the index of the matching filter is \nstored in the Filter Match Index. As shown in the example, the identifier matches with \nIdentifier #2 thus the message content and FMI 2 is stored in the FIFO. \nIf there is no match, the incoming identifier is then compared with the filters configured in \nmask mode. \nIf the identifier does not match any of the identifiers configured in the filters, the message is \ndiscarded by hardware without disturbing the software.\nIdentifier List\nMessage Discarded\nIdentifier & Mask\nIdentifier \n0\nIdentifier \n1\nIdentifier \n4\nIdentifier \n5\nIdentifier \n2\nMask\nIdentifier \n3\nMask\nIdentifier\nMessage Received\nCtrl\nData\nIdentifier #4 Match\nMessage\nStored\nReceive FIFO\nNo Match\nFound\nFilter number stored in the \nFilter Match Index field \nwithin the CAN_RDTxR \nregister\nFMI\nFilter bank \n0\n2\n3\n1\n4\nNum\nThree filter banks in 32-bit Unidentified List mode,\nthe remaining in 32-bit Identifier Mask mode\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1094/1757\nRM0090 Rev 21\n32.7.5 \nMessage storage\nThe interface between the software and the hardware for the CAN messages is \nimplemented by means of mailboxes. A mailbox contains all information related to a \nmessage; identifier, data, control, status and time stamp information.\nTransmit mailbox\nThe software sets up the message to be transmitted in an empty transmit mailbox. The \nstatus of the transmission is indicated by hardware in the CAN_TSR register.\n \nReceive mailbox\nWhen a message has been received, it is available to the software in the FIFO output \nmailbox. Once the software has handled the message (e.g. read it) the software must \nrelease the FIFO output mailbox by means of the RFOM bit in the CAN_RFR register to \nmake the next incoming message available. The filter match index is stored in the MFMI \nfield of the CAN_RDTxR register. The 16-bit time stamp value is stored in the TIME[15:0] \nfield of CAN_RDTxR.\n \nTable 183. Transmit mailbox mapping\nOffset to transmit mailbox base address (bytes)\nRegister name\n0\nCAN_TIxR\n4\nCAN_TDTxR \n8\nCAN_TDLxR\n12\nCAN_TDHxR\nTable 184. Receive mailbox mapping\nOffset to receive mailbox base address (bytes)\nRegister name\n0\nCAN_RIxR\n4\nCAN_RDTxR\n8\nCAN_RDLxR\n12\nCAN_RDHxR\n\n\n<>\n\nRM0090 Rev 21\n1095/1757\nRM0090\nController area network (bxCAN)\n1124\nFigure 345. CAN error state diagram\nERROR PASSIVE\nWhen TEC or REC > 127\nWhen TEC and REC < 128,\nERROR ACTIVE\nBUS OFF\n When TEC > 255\nWhen 128 * 11 recessive bits occur:\nai15903\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1096/1757\nRM0090 Rev 21\n32.7.6 \nError management\nThe error management as described in the CAN protocol is handled entirely by hardware \nusing a Transmit Error Counter (TEC value, in CAN_ESR register) and a Receive Error \nCounter (REC value, in the CAN_ESR register), which get incremented or decremented \naccording to the error condition. For detailed information about TEC and REC management, \nrefer to the CAN standard. \nBoth of them may be read by software to determine the stability of the network. \nFurthermore, the CAN hardware provides detailed information on the current error status in \nCAN_ESR register. By means of the CAN_IER register (ERRIE bit, etc.), the software can \nconfigure the interrupt generation on error detection in a very flexible way.\nBus-Off recovery\nThe Bus-Off state is reached when TEC is greater than 255, this state is indicated by BOFF \nbit in CAN_ESR register. In Bus-Off state, the bxCAN is no longer able to transmit and \nreceive messages. \nDepending on the ABOM bit in the CAN_MCR register bxCAN recovers from Bus-Off \n(become error active again) either automatically or on software request. But in both cases \nthe bxCAN has to wait at least for the recovery sequence specified in the CAN standard \n(128 occurrences of 11 consecutive recessive bits monitored on CANRX).\nIf ABOM is set, the bxCAN starts the recovering sequence automatically after it has entered \nBus-Off state.\nIf ABOM is cleared, the software must initiate the recovering sequence by requesting \nbxCAN to enter and to leave initialization mode.\nNote:\nIn initialization mode, bxCAN does not monitor the CANRX signal, therefore it cannot \ncomplete the recovery sequence. To recover, bxCAN must be in normal mode.\n32.7.7 \nBit timing\nThe bit timing logic monitors the serial bus-line and performs sampling and adjustment of \nthe sample point by synchronizing on the start-bit edge and resynchronizing on the following \nedges. \nIts operation may be explained simply by splitting nominal bit time into three segments as \nfollows:\n•\nSynchronization segment (SYNC_SEG): a bit change is expected to occur within this \ntime segment. It has a fixed length of one time quantum (1 x tq).\n•\nBit segment 1 (BS1): defines the location of the sample point. It includes the \nPROP_SEG and PHASE_SEG1 of the CAN standard. Its duration is programmable \nbetween 1 and 16 time quanta but may be automatically lengthened to compensate for \npositive phase drifts due to differences in the frequency of the various nodes of the \nnetwork.\n•\nBit segment 2 (BS2): defines the location of the transmit point. It represents the \nPHASE_SEG2 of the CAN standard. Its duration is programmable between 1 and 8 \ntime quanta but may also be automatically shortened to compensate for negative \nphase drifts.\nThe resynchronization Jump Width (SJW) defines an upper bound to the amount of \nlengthening or shortening of the bit segments. It is programmable between 1 and 4 time \nquanta.\n\n\n<>\n\nRM0090 Rev 21\n1097/1757\nRM0090\nController area network (bxCAN)\n1124\nA valid edge is defined as the first transition in a bit time from dominant to recessive bus \nlevel provided the controller itself does not send a recessive bit.\nIf a valid edge is detected in BS1 instead of SYNC_SEG, BS1 is extended by up to SJW so \nthat the sample point is delayed.\nConversely, if a valid edge is detected in BS2 instead of SYNC_SEG, BS2 is shortened by \nup to SJW so that the transmit point is moved earlier.\nAs a safeguard against programming errors, the configuration of the Bit Timing register \n(CAN_BTR) is only possible while the device is in Standby mode.\nNote:\nFor a detailed description of the CAN bit timing and resynchronization mechanism, refer to \nthe ISO 11898 standard.\nFigure 346. Bit timing\nSYNC_SEG\nBIT SEGMENT 1 (BS1)\nBIT SEGMENT 2 (BS2)\nNOMINAL BIT TIME\n1 x tq\ntBS1\ntBS2\nSAMPLE POINT\nTRANSMIT POINT\nNominalBitTime\n1\ntq\n×\ntBS1\ntBS2\n+\n+\n=\nwith:\ntBS1 = tq x (TS1[3:0] + 1),\ntBS2 = tq x (TS2[2:0] + 1),\ntq = (BRP[9:0] + 1) x tPCLK\ntPCLK = time period of the APB clock,\nBRP[9:0], TS1[3:0] and TS2[2:0] are defined in the CAN_BTR register.\nBaudRate\n1\nNominalBitTime\n----------------------------------------------\n=\nwhere tq refers to the Time quantum\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1098/1757\nRM0090 Rev 21\nFigure 347. CAN frames\n32.8 \nbxCAN interrupts\nFour interrupt vectors are dedicated to bxCAN. Each interrupt source can be independently \nenabled or disabled by means of the CAN Interrupt Enable register (CAN_IER).\nData Frame or\nRemote Frame\nData Field\n8 * N\nCtrl Field\n6\nArbitration Field\n32\nCRC Field\n16\nAck Field\n7\nSOF\nID\nDLC\nCRC\nData Frame (Standard identifier)\n44 + 8 * N\nArbitration Field\n32\nRTR\nIDE\nr0\nSOF\nID\nDLC\nRemote Frame\n44\nCRC Field\n16\n7\nCRC\nCtrl Field\n6\nOverload \nOverload Frame\n Error \n6\nError Delimiter\n8\nError Frame\nFlag Echo\n 6\nBus Idle\nInter-Frame Space\nSuspend\n8\nIntermission\n3\nTransmission\nACK\nACK\n2\n2\nInter-Frame Space\nor Overload Frame\nInter-Frame Space\nInter-Frame Space\nor Overload Frame\nInter-Frame Space\nInter-Frame Space\nor Overload Frame\nNotes:\n 0 <= N <= 8\n SOF = Start Of Frame\n ID = Identifier\n RTR = Remote Transmission Request\n IDE = Identifier Extension Bit\n r0 = Reserved Bit\n DLC = Data Length Code\n CRC = Cyclic Redundancy Code\n Error flag: 6 dominant bits if node is error \nactive else 6 recessive bits.\n Suspend transmission: applies to error \npassive nodes only.\n EOF = End of Frame\n ACK = Acknowledge bit\n Ctrl = Control\nData Frame or\nRemote Frame\nAny Frame\nInter-Frame Space\nor Error Frame\nEnd Of Frame or\nError Delimiter or\nOverload Delimiter\nAck Field\nEOF\nRTR\nIDE\nr0\nEOF\nData Field\n8 * N\nCtrl Field\n6\n32\nCRC Field\n16\nAck Field\n7\nSOF\nID\nDLC\nCRC\nData Frame (Extended Identifier)\n64 + 8 * N\nACK\n2\nInter-Frame Space\nor Overload Frame\nInter-Frame Space\nSRR\nIDE\nEOF\nRTR\nr1\nr0\n32\n6\nOverload \n8\n 6\nOverload \nFlag\nEcho\nDelimiter\nFlag\nai15154\nArbitration Field\nArbitration Field\n\n\n<>\n\nRM0090 Rev 21\n1099/1757\nRM0090\nController area network (bxCAN)\n1124\nFigure 348. Event flags and interrupt generation\n•\nThe transmit interrupt can be generated by the following events:\n–\nTransmit mailbox 0 becomes empty, RQCP0 bit in the CAN_TSR register set.\n–\nTransmit mailbox 1 becomes empty, RQCP1 bit in the CAN_TSR register set.\n–\nTransmit mailbox 2 becomes empty, RQCP2 bit in the CAN_TSR register set.\n•\nThe FIFO 0 interrupt can be generated by the following events:\n–\nReception of a new message, FMP0 bits in the CAN_RF0R register are not ‘00’.\n–\nFIFO0 full condition, FULL0 bit in the CAN_RF0R register set.\n–\nFIFO0 overrun condition, FOVR0 bit in the CAN_RF0R register set.\n•\nThe FIFO 1 interrupt can be generated by the following events:\n–\nReception of a new message, FMP1 bits in the CAN_RF1R register are not ‘00’.\n–\nFIFO1 full condition, FULL1 bit in the CAN_RF1R register set.\n–\nFIFO1 overrun condition, FOVR1 bit in the CAN_RF1R register set.\n•\nThe error and status change interrupt can be generated by the following events:\n–\nError condition, for more details on error conditions refer to the CAN Error Status \nregister (CAN_ESR).\nRQCP0 \nRQCP1 \nFMP1\nCAN_TSR\n+\nTMEIE\nCAN_IER\nTRANSMIT\n&\nFMPIE1\nFULL1\n&\nFFIE1\nFOVR1\n&\nFOVIE1\n&\n+\nCAN_RF1R\nFIFO 1\nEWGF\nEWGIE\nEPVF\nEPVIE\nBOFF\nBOFIE\n1≤LEC≤6\nLECIE\n&\n&\n&\n&\nCAN_ESR\n+\n&\nERRIE\nINTERRUPT\nINTERRUPT\nFMP0\n&\nFMPIE0\nFULL0\n&\nFFIE0\nFOVR0\n&\nFOVIE0\n+\nCAN_RF0R\nFIFO 0\nINTERRUPT\nRQCP2 \nWKUI\n&\nWKUIE\nCAN_MSR\n+\nINTERRUPT\nERROR\nSTATUS CHANGE\nERRI\nSLAKI\nSLKIE\n&\nCAN_MSR\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1100/1757\nRM0090 Rev 21\n–\nWake-up condition, SOF monitored on the CAN Rx signal.\n–\nEntry into Sleep mode.\n32.9 \nCAN registers\nThe peripheral registers have to be accessed by words (32 bits).\n32.9.1 \nRegister access protection\nErroneous access to certain configuration registers can cause the hardware to temporarily \ndisturb the whole CAN network. Therefore the CAN_BTR register can be modified by \nsoftware only while the CAN hardware is in initialization mode.\nAlthough the transmission of incorrect data does not cause problems at the CAN network \nlevel, it can severely disturb the application. A transmit mailbox can be only modified by \nsoftware while it is in empty state, refer to Figure 340.\nThe filter values can be modified either deactivating the associated filter banks or by setting \nthe FINIT bit. Moreover, the modification of the filter configuration (scale, mode and FIFO \nassignment) in CAN_FMxR, CAN_FSxR and CAN_FFAR registers can only be done when \nthe filter initialization mode is set (FINIT=1) in the CAN_FMR register.\n32.9.2 \nCAN control and status registers\nRefer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.\nCAN master control register (CAN_MCR)\nAddress offset: 0x00\nReset value: 0x0001 0002\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nDBF\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRESET\nReserved\nTTCM\nABOM\nAWUM\nNART\nRFLM\nTXFP\nSLEEP\nINRQ\nrs\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:17 Reserved, must be kept at reset value.\nBit 16 DBF: Debug freeze\n0: CAN working during debug\n1: CAN reception/transmission frozen during debug. Reception FIFOs can still be \naccessed/controlled normally.\nBit 15 RESET: bxCAN software master reset\n0: Normal operation.\n1: Force a master reset of the bxCAN -> Sleep mode activated after reset (FMP bits and \nCAN_MCR register are initialized to the reset values). This bit is automatically reset to 0.\nBits 14:8 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n1101/1757\nRM0090\nController area network (bxCAN)\n1124\nBit 7 TTCM: Time triggered communication mode\n0: Time Triggered Communication mode disabled.\n1: Time Triggered Communication mode enabled\nNote: For more information on Time Triggered Communication mode refer to Section 32.7.2.\nBit 6 ABOM: Automatic bus-off management\nThis bit controls the behavior of the CAN hardware on leaving the Bus-Off state. \n0: The Bus-Off state is left on software request, once 128 occurrences of 11 recessive bits \nhave been monitored and the software has first set and cleared the INRQ bit of the \nCAN_MCR register. \n1: The Bus-Off state is left automatically by hardware once 128 occurrences of 11 recessive \nbits have been monitored.\nFor detailed information on the Bus-Off state refer to Section 32.7.6.\nBit 5 AWUM: Automatic wake-up mode\nThis bit controls the behavior of the CAN hardware on message reception during Sleep \nmode. \n0: The Sleep mode is left on software request by clearing the SLEEP bit of the CAN_MCR \nregister.\n1: The Sleep mode is left automatically by hardware on CAN message detection.\nThe SLEEP bit of the CAN_MCR register and the SLAK bit of the CAN_MSR register are \ncleared by hardware.\nBit 4 NART: No automatic retransmission\n0: The CAN hardware automatically retransmits the message until it has been successfully \ntransmitted according to the CAN standard.\n1: A message is transmitted only once, independently of the transmission result (successful, \nerror or arbitration lost).\nBit 3 RFLM: Receive FIFO locked mode\n0: Receive FIFO not locked on overrun. Once a receive FIFO is full the next incoming \nmessage overwrites the previous one.\n1: Receive FIFO locked against overrun. Once a receive FIFO is full the next incoming \nmessage is discarded.\nBit 2 TXFP: Transmit FIFO priority\nThis bit controls the transmission order when several mailboxes are pending at the same \ntime.\n0: Priority driven by the identifier of the message\n1: Priority driven by the request order (chronologically)\nBit 1 SLEEP: Sleep mode request\nThis bit is set by software to request the CAN hardware to enter the Sleep mode. Sleep \nmode is entered as soon as the current CAN activity (transmission or reception of a CAN \nframe) has been completed.\nThis bit is cleared by software to exit Sleep mode.\nThis bit is cleared by hardware when the AWUM bit is set and a SOF bit is detected on the \nCAN Rx signal.\nThis bit is set after reset - CAN starts in Sleep mode.\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1102/1757\nRM0090 Rev 21\nCAN master status register (CAN_MSR)\nAddress offset: 0x04\nReset value: 0x0000 0C02\n \n \nBit 0 INRQ: Initialization request\nThe software clears this bit to switch the hardware into normal mode. Once 11 consecutive \nrecessive bits have been monitored on the Rx signal the CAN hardware is synchronized and \nready for transmission and reception. Hardware signals this event by clearing the INAK bit in \nthe CAN_MSR register.\nSoftware sets this bit to request the CAN hardware to enter initialization mode. Once \nsoftware has set the INRQ bit, the CAN hardware waits until the current CAN activity \n(transmission or reception) is completed before entering the initialization mode. Hardware \nsignals this event by setting the INAK bit in the CAN_MSR register.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved.\nRX\nSAMP\nRXM\nTXM\nReserved\nSLAKI\nWKUI\nERRI\nSLAK\nINAK\nr\nr\nr\nr\nrc_w1\nrc_w1\nrc_w1\nr\nr\nBits 31:12 Reserved, must be kept at reset value.\nBit 11 RX: CAN Rx signal\nMonitors the actual value of the CAN_RX Pin.\nBit 10 SAMP: Last sample point \nThe value of RX on the last sample point (current received bit value).\nBit 9 RXM: Receive mode\nThe CAN hardware is currently receiver. \nBit 8 TXM: Transmit mode\nThe CAN hardware is currently transmitter.\nBits 7:5 Reserved, must be kept at reset value.\nBit 4 SLAKI: Sleep acknowledge interrupt\nWhen SLKIE=1, this bit is set by hardware to signal that the bxCAN has entered Sleep \nMode. When set, this bit generates a status change interrupt if the SLKIE bit in the \nCAN_IER register is set.\nThis bit is cleared by software or by hardware, when SLAK is cleared.\nNote: When SLKIE=0, no polling on SLAKI is possible. In this case the SLAK bit can be \npolled.\nBit 3 WKUI: Wake-up interrupt\nThis bit is set by hardware to signal that a SOF bit has been detected while the CAN \nhardware was in Sleep mode. Setting this bit generates a status change interrupt if the \nWKUIE bit in the CAN_IER register is set.\nThis bit is cleared by software.\n\n\n<>\n\nRM0090 Rev 21\n1103/1757\nRM0090\nController area network (bxCAN)\n1124\nCAN transmit status register (CAN_TSR)\nAddress offset: 0x08\nReset value: 0x1C00 0000\n \n \nBit 2 ERRI: Error interrupt\nThis bit is set by hardware when a bit of the CAN_ESR has been set on error detection and \nthe corresponding interrupt in the CAN_IER is enabled. Setting this bit generates a status \nchange interrupt if the ERRIE bit in the CAN_IER register is set.\nThis bit is cleared by software.\nBit 1 SLAK: Sleep acknowledge\nThis bit is set by hardware and indicates to the software that the CAN hardware is now in \nSleep mode. This bit acknowledges the Sleep mode request from the software (set SLEEP \nbit in CAN_MCR register).\nThis bit is cleared by hardware when the CAN hardware has left Sleep mode (to be \nsynchronized on the CAN bus). To be synchronized the hardware has to monitor a \nsequence of 11 consecutive recessive bits on the CAN RX signal.\nNote: The process of leaving Sleep mode is triggered when the SLEEP bit in the CAN_MCR \nregister is cleared. Refer to the AWUM bit of the CAN_MCR register description for \ndetailed information for clearing SLEEP bit\nBit 0 INAK: Initialization acknowledge\nThis bit is set by hardware and indicates to the software that the CAN hardware is now in \ninitialization mode. This bit acknowledges the initialization request from the software (set \nINRQ bit in CAN_MCR register).\nThis bit is cleared by hardware when the CAN hardware has left the initialization mode (to \nbe synchronized on the CAN bus). To be synchronized the hardware has to monitor a \nsequence of 11 consecutive recessive bits on the CAN RX signal.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nLOW2\nLOW1\nLOW0\nTME2\nTME1\nTME0\nCODE[1:0]\nABRQ2\nReserved\nTERR2\nALST2\nTXOK2 RQCP2\nr\nr\nr\nr\nr\nr\nr\nr\nrs\nrc_w1\nrc_w1\nrc_w1\nrc_w1\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nABRQ1\nReserved\nRes.\nTERR1\nALST1\nTXOK1 RQCP1 ABRQ0\nReserved\nTERR0\nALST0\nTXOK0 RQCP0\nrs\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrs\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nBit 31 LOW2: Lowest priority flag for mailbox 2\nThis bit is set by hardware when more than one mailbox are pending for transmission and \nmailbox 2 has the lowest priority.\nBit 30 LOW1: Lowest priority flag for mailbox 1 \nThis bit is set by hardware when more than one mailbox are pending for transmission and \nmailbox 1 has the lowest priority.\nBit 29 LOW0: Lowest priority flag for mailbox 0\nThis bit is set by hardware when more than one mailbox are pending for transmission and \nmailbox 0 has the lowest priority.\nNote: The LOW[2:0] bits are set to zero when only one mailbox is pending.\nBit 28 TME2: Transmit mailbox 2 empty \nThis bit is set by hardware when no transmit request is pending for mailbox 2.\nBit 27 TME1: Transmit mailbox 1 empty \nThis bit is set by hardware when no transmit request is pending for mailbox 1.\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1104/1757\nRM0090 Rev 21\nBit 26 TME0: Transmit mailbox 0 empty\nThis bit is set by hardware when no transmit request is pending for mailbox 0.\nBits 25:24 CODE[1:0]: Mailbox code\nIn case at least one transmit mailbox is free, the code value is equal to the number of the \nnext transmit mailbox free.\nIn case all transmit mailboxes are pending, the code value is equal to the number of the \ntransmit mailbox with the lowest priority.\nBit 23 ABRQ2: Abort request for mailbox 2\nSet by software to abort the transmission request for the corresponding mailbox. \nCleared by hardware when the mailbox becomes empty.\nSetting this bit has no effect when the mailbox is not pending for transmission.\nBits 22:20 Reserved, must be kept at reset value.\nBit 19 TERR2: Transmission error of mailbox 2\nThis bit is set when the previous TX failed due to an error. \nBit 18 ALST2: Arbitration lost for mailbox 2\nThis bit is set when the previous TX failed due to an arbitration lost. \nBit 17 TXOK2: Transmission OK of mailbox 2\nThe hardware updates this bit after each transmission attempt.\n0: The previous transmission failed\n1: The previous transmission was successful\nThis bit is set by hardware when the transmission request on mailbox 2 has been completed \nsuccessfully. Refer to Figure 340.\nBit 16 RQCP2: Request completed mailbox2\nSet by hardware when the last request (transmit or abort) has been performed.\nCleared by software writing a “1” or by hardware on transmission request (TXRQ2 set in \nCAN_TMID2R register).\nClearing this bit clears all the status bits (TXOK2, ALST2 and TERR2) for Mailbox 2.\nBit 15 ABRQ1: Abort request for mailbox 1\nSet by software to abort the transmission request for the corresponding mailbox. \nCleared by hardware when the mailbox becomes empty.\nSetting this bit has no effect when the mailbox is not pending for transmission.\nBits 14:12 Reserved, must be kept at reset value.\nBit 11 TERR1: Transmission error of mailbox1\nThis bit is set when the previous TX failed due to an error. \nBit 10 ALST1: Arbitration lost for mailbox1\nThis bit is set when the previous TX failed due to an arbitration lost. \nBit 9 TXOK1: Transmission OK of mailbox1\nThe hardware updates this bit after each transmission attempt.\n0: The previous transmission failed\n1: The previous transmission was successful\nThis bit is set by hardware when the transmission request on mailbox 1 has been completed \nsuccessfully. Refer to Figure 340\nBit 8 RQCP1: Request completed mailbox1\nSet by hardware when the last request (transmit or abort) has been performed.\nCleared by software writing a “1” or by hardware on transmission request (TXRQ1 set in \nCAN_TI1R register).\nClearing this bit clears all the status bits (TXOK1, ALST1 and TERR1) for Mailbox 1.\n\n\n<>\n\nRM0090 Rev 21\n1105/1757\nRM0090\nController area network (bxCAN)\n1124\nCAN receive FIFO 0 register (CAN_RF0R)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n \n \nBit 7 ABRQ0: Abort request for mailbox0\nSet by software to abort the transmission request for the corresponding mailbox. \nCleared by hardware when the mailbox becomes empty.\nSetting this bit has no effect when the mailbox is not pending for transmission.\nBits 6:4 Reserved, must be kept at reset value.\nBit 3 TERR0: Transmission error of mailbox0\nThis bit is set when the previous TX failed due to an error. \nBit 2 ALST0: Arbitration lost for mailbox0\nThis bit is set when the previous TX failed due to an arbitration lost.\nBit 1 TXOK0: Transmission OK of mailbox0\nThe hardware updates this bit after each transmission attempt.\n0: The previous transmission failed\n1: The previous transmission was successful\nThis bit is set by hardware when the transmission request on mailbox 1 has been completed \nsuccessfully. Refer to Figure 340\nBit 0 RQCP0: Request completed mailbox0\nSet by hardware when the last request (transmit or abort) has been performed.\nCleared by software writing a “1” or by hardware on transmission request (TXRQ0 set in \nCAN_TI0R register).\nClearing this bit clears all the status bits (TXOK0, ALST0 and TERR0) for Mailbox 0.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRFOM0\nFOVR0\nFULL0\nRes.\nFMP0[1:0]\nrs\nrc_w1\nrc_w1\nr\nr\nBits 31:6 Reserved, must be kept at reset value.\nBit 5 RFOM0: Release FIFO 0 output mailbox\nSet by software to release the output mailbox of the FIFO. The output mailbox can only be \nreleased when at least one message is pending in the FIFO. Setting this bit when the FIFO \nis empty has no effect. If at least two messages are pending in the FIFO, the software has to \nrelease the output mailbox to access the next message.\nCleared by hardware when the output mailbox has been released.\nBit 4 FOVR0: FIFO 0 overrun \nThis bit is set by hardware when a new message has been received and passed the filter \nwhile the FIFO was full. \nThis bit is cleared by software. \nBit 3 FULL0: FIFO 0 full\nSet by hardware when three messages are stored in the FIFO. \nThis bit is cleared by software.\nBit 2 Reserved, must be kept at reset value.\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1106/1757\nRM0090 Rev 21\nCAN receive FIFO 1 register (CAN_RF1R)\nAddress offset: 0x10\nReset value: 0x0000 0000\n \n \nCAN interrupt enable register (CAN_IER)\nAddress offset: 0x14\nReset value: 0x0000 0000\n \nBits 1:0 FMP0[1:0]: FIFO 0 message pending\nThese bits indicate how many messages are pending in the receive FIFO. \nFMP is increased each time the hardware stores a new message in to the FIFO. FMP is \ndecreased each time the software releases the output mailbox by setting the RFOM0 bit.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRFOM1\nFOVR1\nFULL1\nRes.\nFMP1[1:0]\nrs\nrc_w1\nrc_w1\nr\nr\nBits 31:6 Reserved, must be kept at reset value.\nBit 5 RFOM1: Release FIFO 1 output mailbox\nSet by software to release the output mailbox of the FIFO. The output mailbox can only be \nreleased when at least one message is pending in the FIFO. Setting this bit when the FIFO \nis empty has no effect. If at least two messages are pending in the FIFO, the software has to \nrelease the output mailbox to access the next message.\nCleared by hardware when the output mailbox has been released.\nBit 4 FOVR1: FIFO 1 overrun \nThis bit is set by hardware when a new message has been received and passed the filter \nwhile the FIFO was full. \nThis bit is cleared by software. \nBit 3 FULL1: FIFO 1 full\nSet by hardware when three messages are stored in the FIFO.\nThis bit is cleared by software.\nBit 2 Reserved, must be kept at reset value.\nBits 1:0 FMP1[1:0]: FIFO 1 message pending\nThese bits indicate how many messages are pending in the receive FIFO1. \nFMP1 is increased each time the hardware stores a new message in to the FIFO1. FMP is \ndecreased each time the software releases the output mailbox by setting the RFOM1 bit.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nSLKIE\nWKUIE\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nERRIE\nReserved\nLEC\nIE\nBOF\nIE\nEPV\nIE\nEWG\nIE\nRes.\nFOV\nIE1\nFF\nIE1\nFMP\nIE1\nFOV\nIE0\nFF\nIE0\nFMP\nIE0\nTME\nIE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n1107/1757\nRM0090\nController area network (bxCAN)\n1124\n \nBits 31:18 Reserved, must be kept at reset value.\nBit 17 SLKIE: Sleep interrupt enable\n0: No interrupt when SLAKI bit is set.\n1: Interrupt generated when SLAKI bit is set.\nBit 16 WKUIE: Wake-up interrupt enable\n0: No interrupt when WKUI is set.\n1: Interrupt generated when WKUI bit is set.\nBit 15 ERRIE: Error interrupt enable\n0: No interrupt is generated when an error condition is pending in the CAN_ESR.\n1: An interrupt is generation when an error condition is pending in the CAN_ESR.\nBits 14:12 Reserved, must be kept at reset value.\nBit 11 LECIE: Last error code interrupt enable\n0: ERRI bit is not set when the error code in LEC[2:0] is set by hardware on error detection.\n1: ERRI bit is set when the error code in LEC[2:0] is set by hardware on error detection.\nBit 10 BOFIE: Bus-off interrupt enable\n0: ERRI bit is not set when BOFF is set.\n1: ERRI bit is set when BOFF is set.\nBit 9 EPVIE: Error passive interrupt enable\n0: ERRI bit is not set when EPVF is set.\n1: ERRI bit is set when EPVF is set.\nBit 8 EWGIE: Error warning interrupt enable\n0: ERRI bit is not set when EWGF is set.\n1: ERRI bit is set when EWGF is set.\nBit 7 Reserved, must be kept at reset value.\nBit 6 FOVIE1: FIFO overrun interrupt enable\n0: No interrupt when FOVR is set.\n1: Interrupt generation when FOVR is set.\nBit 5 FFIE1: FIFO full interrupt enable\n0: No interrupt when FULL bit is set.\n1: Interrupt generated when FULL bit is set.\nBit 4 FMPIE1: FIFO message pending interrupt enable\n0: No interrupt generated when state of FMP[1:0] bits are not 00b.\n1: Interrupt generated when state of FMP[1:0] bits are not 00b.\nBit 3 FOVIE0: FIFO overrun interrupt enable\n0: No interrupt when FOVR bit is set.\n1: Interrupt generated when FOVR bit is set.\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1108/1757\nRM0090 Rev 21\nCAN error status register (CAN_ESR)\nAddress offset: 0x18\nReset value: 0x0000 0000\n \n \nBit 2 FFIE0: FIFO full interrupt enable\n0: No interrupt when FULL bit is set.\n1: Interrupt generated when FULL bit is set.\nBit 1 FMPIE0: FIFO message pending interrupt enable\n0: No interrupt generated when state of FMP[1:0] bits are not 00b.\n1: Interrupt generated when state of FMP[1:0] bits are not 00b.\nBit 0 TMEIE: Transmit mailbox empty interrupt enable\n0: No interrupt when RQCPx bit is set.\n1: Interrupt generated when RQCPx bit is set.\nNote: Refer to Section 32.8: bxCAN interrupts.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nREC[7:0]\nTEC[7:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLEC[2:0]\nRes.\nBOFF\nEPVF\nEWGF\nrw\nrw\nrw\nr\nr\nr\nBits 31:24 REC[7:0]: Receive error counter \nThe implementing part of the fault confinement mechanism of the CAN protocol. In case of \nan error during reception, this counter is incremented by 1 or by 8 depending on the error \ncondition as defined by the CAN standard. After every successful reception the counter is \ndecremented by 1 or reset to 120 if its value was higher than 128. When the counter value \nexceeds 127, the CAN controller enters the error passive state.\nBits 23:16 TEC[7:0]: Least significant byte of the 9-bit transmit error counter\nThe implementing part of the fault confinement mechanism of the CAN protocol.\nBits 15:7 Reserved, must be kept at reset value.\nBits 6:4 LEC[2:0]: Last error code\nThis field is set by hardware and holds a code which indicates the error condition of the last \nerror detected on the CAN bus. If a message has been transferred (reception or \ntransmission) without error, this field is cleared to ‘0’. \nThe LEC[2:0] bits can be set to value 0b111 by software. They are updated by hardware to \nindicate the current communication status.\n000: No Error\n001: Stuff Error\n010: Form Error\n011: Acknowledgment Error\n100: Bit recessive Error\n101: Bit dominant Error\n110: CRC Error\n111: Set by software\nBit 3 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n1109/1757\nRM0090\nController area network (bxCAN)\n1124\nCAN bit timing register (CAN_BTR)\nAddress offset: 0x1C\nReset value: 0x0123 0000\nThis register can only be accessed by the software when the CAN hardware is in \ninitialization mode.\n \n \nBit 2 BOFF: Bus-off flag\nThis bit is set by hardware when it enters the bus-off state. The bus-off state is entered on \nTEC overflow, greater than 255, refer to Section 32.7.6.\nBit 1 EPVF: Error passive flag\nThis bit is set by hardware when the Error Passive limit has been reached (Receive Error \nCounter or Transmit Error Counter>127).\nBit 0 EWGF: Error warning flag\nThis bit is set by hardware when the warning limit has been reached \n(Receive Error Counter or Transmit Error Counter≥96).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nSILM\nLBKM\nReserved\nSJW[1:0]\nRes.\nTS2[2:0]\nTS1[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBRP[9:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 SILM: Silent mode (debug)\n0: Normal operation\n1: Silent Mode\nBit 30 LBKM: Loop back mode (debug)\n0: Loop Back Mode disabled\n1: Loop Back Mode enabled\nBits 29:26 Reserved, must be kept at reset value.\nBits 25:24 SJW[1:0]: Resynchronization jump width\nThese bits define the maximum number of time quanta the CAN hardware is allowed to \nlengthen or shorten a bit to perform the resynchronization.\ntRJW = tq x (SJW[1:0] + 1)\nBit 23 Reserved, must be kept at reset value.\nBits 22:20 TS2[2:0]: Time segment 2\nThese bits define the number of time quanta in Time Segment 2.\ntBS2 = tq x (TS2[2:0] + 1)\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1110/1757\nRM0090 Rev 21\n32.9.3 \nCAN mailbox registers\nThis chapter describes the registers of the transmit and receive mailboxes. Refer to \nSection 32.7.5: Message storage for detailed register mapping.\nTransmit and receive mailboxes have the same registers except:\n•\nThe FMI field in the CAN_RDTxR register.\n•\nA receive mailbox is always write protected.\n•\nA transmit mailbox is write-enabled only while empty, corresponding TME bit in the \nCAN_TSR register set.\nThere are three TX Mailboxes and two RX Mailboxes , as shown in Figure 349. Each RX \nMailbox allows access to a 3-level depth FIFO, the access being offered only to the oldest \nreceived message in the FIFO. Each mailbox consist of four registers.\nFigure 349. RX and TX mailboxes\nBits 19:16 TS1[3:0]: Time segment 1\nThese bits define the number of time quanta in Time Segment 1\ntBS1 = tq x (TS1[3:0] + 1)\nFor more information on bit timing refer to Section 32.7.7.\nBits 15:10 Reserved, must be kept at reset value.\nBits 9:0 BRP[9:0]: Baud rate prescaler\nThese bits define the length of a time quanta.\ntq = (BRP[9:0]+1) x tPCLK\nCAN_RI0R\nCAN_RDT0R\nCAN_RL0R\nCAN_RH0R\nCAN_TI0R\nCAN_TDT0R\nCAN_TDL0R\nCAN_TDH0R\nFIFO0\nThree Tx Mailboxes\nCAN_RI1R\nCAN_RDT1R\nCAN_RL1R\nCAN_RH1R\nFIFO1\nCAN_TI1R\nCAN_TDT1R\nCAN_TDL1R\nCAN_TDH1R\nCAN_TI2R\nCAN_TDT2R\nCAN_TDL2R\nCAN_TDH2R\n\n\n<>\n\nRM0090 Rev 21\n1111/1757\nRM0090\nController area network (bxCAN)\n1124\nCAN TX mailbox identifier register (CAN_TIxR) (x=0..2)\nAddress offsets: 0x180, 0x190, 0x1A0\nReset value: 0xXXXX XXXX (except bit 0, TXRQ = 0)\nAll TX registers are write protected when the mailbox is pending transmission (TMEx reset). \nThis register also implements the TX request control (bit 0) - reset value 0.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nSTID[10:0]/EXID[28:18]\nEXID[17:13]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXID[12:0]\nIDE\nRTR\nTXRQ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:21 STID[10:0]/EXID[28:18]: Standard identifier or extended identifier\nThe standard identifier or the MSBs of the extended identifier (depending on the IDE bit \nvalue).\nBits 20:3 EXID[17:0]: Extended identifier\nThe LSBs of the extended identifier.\nBit 2 IDE: Identifier extension\nThis bit defines the identifier type of message in the mailbox.\n0: Standard identifier.\n1: Extended identifier.\nBit 1 RTR: Remote transmission request\n0: Data frame\n1: Remote frame\nBit 0 TXRQ: Transmit mailbox request\nSet by software to request the transmission for the corresponding mailbox.\nCleared by hardware when the mailbox becomes empty.\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1112/1757\nRM0090 Rev 21\nCAN mailbox data length control and time stamp register (CAN_TDTxR) \n(x=0..2)\nAll bits of this register are write protected when the mailbox is not in empty state.\nAddress offsets: 0x184, 0x194, 0x1A4\nReset value: 0xXXXX XXXX\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nTIME[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTGT\nReserved\nDLC[3:0]\nrw\nrw\nrw\nrw\nrw\nBits 31:16 TIME[15:0]: Message time stamp\nThis field contains the 16-bit timer value captured at the SOF transmission.\nBits 15:9 Reserved, must be kept at reset value.\nBit 8 TGT: Transmit global time \nThis bit is active only when the hardware is in the Time Trigger Communication mode, \nTTCM bit of the CAN_MCR register is set.\n0: Time stamp TIME[15:0] is not sent. \n1: Time stamp TIME[15:0] value is sent in the last two data bytes of the 8-byte message: \nTIME[7:0] in data byte 7 and TIME[15:8] in data byte 6, replacing the data written in \nCAN_TDHxR[31:16] register (DATA6[7:0] and DATA7[7:0]). DLC must be programmed as 8 \nin order these two bytes to be sent over the CAN bus. \nBits 7:4 Reserved, must be kept at reset value.\nBits 3:0 DLC[3:0]: Data length code\nThis field defines the number of data bytes a data frame contains or a remote frame request.\nA message can contain from 0 to 8 data bytes, depending on the value in the DLC field.\n\n\n<>\n\nRM0090 Rev 21\n1113/1757\nRM0090\nController area network (bxCAN)\n1124\nCAN mailbox data low register (CAN_TDLxR) (x=0..2)\nAll bits of this register are write protected when the mailbox is not in empty state.\nAddress offsets: 0x188, 0x198, 0x1A8\nReset value: 0xXXXX XXXX\n \n \nCAN mailbox data high register (CAN_TDHxR) (x=0..2)\nAll bits of this register are write protected when the mailbox is not in empty state.\nAddress offsets: 0x18C, 0x19C, 0x1AC\nReset value: 0xXXXX XXXX\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATA3[7:0]\nDATA2[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATA1[7:0]\nDATA0[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 DATA3[7:0]: Data byte 3 \nData byte 3 of the message.\nBits 23:16 DATA2[7:0]: Data byte 2 \nData byte 2 of the message. \nBits 15:8 DATA1[7:0]: Data byte 1 \nData byte 1 of the message. \nBits 7:0 DATA0[7:0]: Data byte 0\nData byte 0 of the message.\nA message can contain from 0 to 8 data bytes and starts with byte 0.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATA7[7:0]\nDATA6[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATA5[7:0]\nDATA4[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 DATA7[7:0]: Data byte 7 \nData byte 7 of the message.\nNote: If TGT of this message and TTCM are active, DATA7 and DATA6 are replaced by the \nTIME stamp value.\nBits 23:16 DATA6[7:0]: Data byte 6 \nData byte 6 of the message. \nBits 15:8 DATA5[7:0]: Data byte 5 \nData byte 5 of the message. \nBits 7:0 DATA4[7:0]: Data byte 4\nData byte 4 of the message.\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1114/1757\nRM0090 Rev 21\nCAN receive FIFO mailbox identifier register (CAN_RIxR) (x=0..1)\nAddress offsets: 0x1B0, 0x1C0\nReset value: 0xXXXX XXXX\nAll RX registers are write protected.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nSTID[10:0]/EXID[28:18]\nEXID[17:13]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXID[12:0]\nIDE\nRTR\nRes.\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:21 STID[10:0]/EXID[28:18]: Standard identifier or extended identifier\nThe standard identifier or the MSBs of the extended identifier (depending on the IDE bit \nvalue).\nBits 20:3 EXID[17:0]: Extended identifier\nThe LSBs of the extended identifier. \nBit 2 IDE: Identifier extension\nThis bit defines the identifier type of message in the mailbox.\n0: Standard identifier.\n1: Extended identifier.\nBit 1 RTR: Remote transmission request\n0: Data frame\n1: Remote frame\nBit 0 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n1115/1757\nRM0090\nController area network (bxCAN)\n1124\nCAN receive FIFO mailbox data length control and time stamp register \n(CAN_RDTxR) (x=0..1)\nAddress offsets: 0x1B4, 0x1C4\nReset value: 0xXXXX XXXX\nAll RX registers are write protected.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nTIME[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFMI[7:0]\nReserved\nDLC[3:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 TIME[15:0]: Message time stamp\nThis field contains the 16-bit timer value captured at the SOF detection.\nBits 15:8 FMI[7:0]: Filter match index\nThis register contains the index of the filter the message stored in the mailbox passed \nthrough. For more details on identifier filtering refer to Section 32.7.4 \nBits 7:4 Reserved, must be kept at reset value.\nBits 3:0 DLC[3:0]: Data length code\nThis field defines the number of data bytes a data frame contains (0 to 8). It is 0 in the case \nof a remote frame request.\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1116/1757\nRM0090 Rev 21\nCAN receive FIFO mailbox data low register (CAN_RDLxR) (x=0..1)\nAll bits of this register are write protected when the mailbox is not in empty state.\nAddress offsets: 0x1B8, 0x1C8\nReset value: 0xXXXX XXXX\nAll RX registers are write protected.\n \n \nCAN receive FIFO mailbox data high register (CAN_RDHxR) (x=0..1)\nAddress offsets: 0x1BC, 0x1CC\nReset value: 0xXXXX XXXX\nAll RX registers are write protected.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATA3[7:0]\nDATA2[7:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATA1[7:0]\nDATA0[7:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:24 DATA3[7:0]: Data Byte 3 \nData byte 3 of the message.\nBits 23:16 DATA2[7:0]: Data Byte 2 \nData byte 2 of the message. \nBits 15:8 DATA1[7:0]: Data Byte 1 \nData byte 1 of the message. \nBits 7:0 DATA0[7:0]: Data Byte 0 \nData byte 0 of the message.\nA message can contain from 0 to 8 data bytes and starts with byte 0.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATA7[7:0]\nDATA6[7:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATA5[7:0]\nDATA4[7:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:24 DATA7[7:0]: Data Byte 7 \nData byte 3 of the message.\nBits 23:16 DATA6[7:0]: Data Byte 6 \nData byte 2 of the message. \nBits 15:8 DATA5[7:0]: Data Byte 5 \nData byte 1 of the message. \nBits 7:0 DATA4[7:0]: Data Byte 4 \nData byte 0 of the message.\n\n\n<>\n\nRM0090 Rev 21\n1117/1757\nRM0090\nController area network (bxCAN)\n1124\n32.9.4 \nCAN filter registers\nCAN filter master register (CAN_FMR)\nAddress offset: 0x200\nReset value: 0x2A1C 0E01\nAll bits of this register are set and cleared by software.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCAN2SB[5:0]\nReserved\nFINIT\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:14 Reserved, must be kept at reset value.\nBits 13:8 CAN2SB[5:0]: CAN2 start bank\nThese bits are set and cleared by software. They define the start bank for the CAN2 \ninterface (Slave) in the range 0 to 27.\nNote: When CAN2SB[5:0] = 28d, all the filters to CAN1 can be used.\nWhen CAN2SB[5:0] is set to 0, no filters are assigned to CAN1. \nBits 7:1 Reserved, must be kept at reset value.\nBit 0 FINIT: Filter init mode \nInitialization mode for filter banks\n0: Active filters mode.\n1: Initialization mode for the filters.\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1118/1757\nRM0090 Rev 21\nCAN filter mode register (CAN_FM1R)\nAddress offset: 0x204\nReset value: 0x0000 0000\nThis register can be written only when the filter initialization mode is set (FINIT=1) in the \nCAN_FMR register.\n \nNote:\nRefer to Figure 342.\n \nCAN filter scale register (CAN_FS1R)\nAddress offset: 0x20C\nReset value: 0x0000 0000\nThis register can be written only when the filter initialization mode is set (FINIT=1) in the \nCAN_FMR register.\n \n \nNote:\nRefer to Figure 342.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nFBM27\nFBM26\nFBM25\nFBM24\nFBM23\nFBM22\nFBM21\nFBM20\nFBM19\nFBM18\nFBM17\nFBM16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFBM15\nFBM14\nFBM13\nFBM12\nFBM11\nFBM10\nFBM9\nFBM8\nFBM7\nFBM6\nFBM5\nFBM4\nFBM3\nFBM2\nFBM1\nFBM0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28\nReserved, must be kept at reset value.\nBits 27:0 FBMx: Filter mode\nMode of the registers of Filter x. \n0: Two 32-bit registers of filter bank x are in Identifier Mask mode.\n1: Two 32-bit registers of filter bank x are in Identifier List mode.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nFSC27\nFSC26\nFSC25\nFSC24\nFSC23\nFSC22\nFSC21\nFSC20\nFSC19\nFSC18\nFSC17\nFSC16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFSC15\nFSC14\nFSC13\nFSC12\nFSC11\nFSC10\nFSC9\nFSC8\nFSC7\nFSC6\nFSC5\nFSC4\nFSC3\nFSC2\nFSC1\nFSC0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBits 27:0 FSCx: Filter scale configuration\nThese bits define the scale configuration of Filters 13-0.\n0: Dual 16-bit scale configuration\n1: Single 32-bit scale configuration\n\n\n<>\n\nRM0090 Rev 21\n1119/1757\nRM0090\nController area network (bxCAN)\n1124\nCAN filter FIFO assignment register (CAN_FFA1R)\nAddress offset: 0x214\nReset value: 0x0000 0000\nThis register can be written only when the filter initialization mode is set (FINIT=1) in the \nCAN_FMR register.\n \n \nCAN filter activation register (CAN_FA1R)\nAddress offset: 0x21C\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nFFA27\nFFA26\nFFA25\nFFA24\nFFA23\nFFA22\nFFA21\nFFA20\nFFA19\nFFA18\nFFA17\nFFA16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFFA15\nFFA14\nFFA13\nFFA12\nFFA11\nFFA10\nFFA9\nFFA8\nFFA7\nFFA6\nFFA5\nFFA4\nFFA3\nFFA2\nFFA1\nFFA0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBits 27:0 FFAx: Filter FIFO assignment for filter x\nThe message passing through this filter is stored in the specified FIFO.\n0: Filter assigned to FIFO 0\n1: Filter assigned to FIFO 1\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nFACT27 FACT26 FACT25 FACT24 FACT23 FACT22 FACT21 FACT20 FACT19 FACT18 FACT17 FACT16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFACT15 FACT14 FACT13 FACT12 FACT11 FACT10 FACT9\nFACT8\nFACT7\nFACT6\nFACT5\nFACT4\nFACT3\nFACT2\nFACT1\nFACT0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBits 27:0 FACTx: Filter active\nThe software sets this bit to activate Filter x. To modify the Filter x registers (CAN_FxR[0:7]), \nthe FACTx bit must be cleared or the FINIT bit of the CAN_FMR register must be set.\n0: Filter x is not active\n1: Filter x is active\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1120/1757\nRM0090 Rev 21\nFilter bank i register x (CAN_FiRx) (i=0..27, x=1, 2)\nAddress offsets: 0x240..0x31C\nReset value: 0xXXXX XXXX\nThere are 28 filter banks, i=0 .. 27. Each filter bank i is composed of two 32-bit registers, \nCAN_FiR[2:1].\nThis register can only be modified when the FACTx bit of the CAN_FAxR register is cleared \nor when the FINIT bit of the CAN_FMR register is set.\n \nIn all configurations:\n \nNote:\nDepending on the scale and mode configuration of the filter the function of each register can \ndiffer. For the filter mapping, functions description and mask registers association, refer to \nSection 32.7.4.\nA Mask/Identifier register in mask mode has the same bit mapping as in identifier list \nmode. \nFor the register mapping/addresses of the filter banks refer to Table 185.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nFB31\nFB30\nFB29\nFB28\nFB27\nFB26\nFB25\nFB24\nFB23\nFB22\nFB21\nFB20\nFB19\nFB18\nFB17\nFB16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFB15\nFB14\nFB13\nFB12\nFB11\nFB10\nFB9\nFB8\nFB7\nFB6\nFB5\nFB4\nFB3\nFB2\nFB1\nFB0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 FB[31:0]: Filter bits \nIdentifier\nEach bit of the register specifies the level of the corresponding bit of the expected identifier.\n0: Dominant bit is expected\n1: Recessive bit is expected\nMask\nEach bit of the register specifies whether the bit of the associated identifier register must \nmatch with the corresponding bit of the expected identifier or not.\n0: Don’t care, the bit is not used for the comparison\n1: Must match, the bit of the incoming identifier must have the same level has specified in \nthe corresponding identifier register of the filter.\n\n\n<>\n\nRM0090 Rev 21\n1121/1757\nRM0090\nController area network (bxCAN)\n1124\n32.9.5 \nbxCAN register map\nRefer to Section 2.3: Memory map for the register boundary addresses. The registers from \noffset 0x200 to 31C are present only in CAN1.\n \nTable 185. bxCAN register map and reset values \nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x000\nCAN_MCR\nReserved\nDBF\nRESET\nReserved\nTTCM\nABOM\nAWUM\nNART\nRFLM\nTXFP\nSLEEP\nINRQ\nReset value\n1\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0x004\nCAN_MSR\nReserved\nRX\nSAMP\nRXM\nTXM\nRes.\nSLAKI\nWKUI\nERRI\nSLAK\nINAK\nReset value\n1\n1\n0\n0\n0\n0\n0\n1\n0\n0x008\nCAN_TSR\nLOW[2:0]\nTME[2:0]\nCODE[1:0]\nABRQ2\nRes.\nTERR2\nALST2\nTXOK2\nRQCP2\nABRQ1\nRes.\nTERR1\nALST1\nTXOK1\nRQCP1\nABRQ0\nRes..\nTERR0\nALST0\nTXOK0\nRQCP0\nReset value\n0\n0\n0\n1\n1\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00C\nCAN_RF0R\nReserved\nRFOM0\nFOVR0\nFULL0\nReserved\nFMP0[1:0]\nReset value\n0\n0\n0\n0\n0\n0x010\nCAN_RF1R\nReserved\nRFOM1\nFOVR1\nFULL1\nReserved\nFMP1[1:0]\nReset value\n0\n0\n0\n0\n0\n0x014\nCAN_IER\nReserved\nSLKIE\nWKUIE\nERRIE\nRes.\nLECIE\nBOFIE\nEPVIE\nEWGIE\nReserved\nFOVIE1\nFFIE1\nFMPIE1\nFOVIE0\nFFIE0\nFMPIE0\nTMEIE\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x018\nCAN_ESR\nREC[7:0]\nTEC[7:0]\nReserved\nLEC[2:0]\nReserved\nBOFF\nEPVF\nEWGF\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x01C\nCAN_BTR\nSILM\nLBKM\nReserved\nSJW[1:0]\nReserved\nTS2[2:0]\nTS1[3:0]\nReserved\nBRP[9:0]\nReset value\n0\n0\n0\n0\n0\n1\n0\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x020-\n0x17F\nReserved\n0x180\nCAN_TI0R\nSTID[10:0]/EXID[28:18]\nEXID[17:0]\nIDE\nRTR\nTXRQ\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0\n0x184\nCAN_TDT0R\nTIME[15:0]\nReserved\nTGT\nReserved\nDLC[3:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x188\nCAN_TDL0R\nDATA3[7:0]\nDATA2[7:0]\nDATA1[7:0]\nDATA0[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1122/1757\nRM0090 Rev 21\n0x18C\nCAN_TDH0R\nDATA7[7:0]\nDATA6[7:0]\nDATA5[7:0]\nDATA4[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x190\nCAN_TI1R\nSTID[10:0]/EXID[28:18]\nEXID[17:0]\nIDE\nRTR\nTXRQ\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0\n0x194\nCAN_TDT1R\nTIME[15:0]\nReserved\nTGT\nReserved\nDLC[3:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x198\nCAN_TDL1R\nDATA3[7:0]\nDATA2[7:0]\nDATA1[7:0]\nDATA0[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x19C\nCAN_TDH1R\nDATA7[7:0]\nDATA6[7:0]\nDATA5[7:0]\nDATA4[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1A0\nCAN_TI2R\nSTID[10:0]/EXID[28:18]\nEXID[17:0]\nIDE\nRTR\nTXRQ\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0\n0x1A4\nCAN_TDT2R\nTIME[15:0]\nReserved\nTGT\nReserved\nDLC[3:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1A8\nCAN_TDL2R\nDATA3[7:0]\nDATA2[7:0]\nDATA1[7:0]\nDATA0[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1AC\nCAN_TDH2R\nDATA7[7:0]\nDATA6[7:0]\nDATA5[7:0]\nDATA4[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1B0\nCAN_RI0R\nSTID[10:0]/EXID[28:18]\nEXID[17:0]\nIDE\nRTR\nReserved\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1B4\nCAN_RDT0R\nTIME[15:0]\nFMI[7:0]\nReserved\nDLC[3:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1B8\nCAN_RDL0R\nDATA3[7:0]\nDATA2[7:0]\nDATA1[7:0]\nDATA0[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1BC\nCAN_RDH0R\nDATA7[7:0]\nDATA6[7:0]\nDATA5[7:0]\nDATA4[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1C0\nCAN_RI1R\nSTID[10:0]/EXID[28:18]\nEXID[17:0]\nIDE\nRTR\nReserved\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nTable 185. bxCAN register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1123/1757\nRM0090\nController area network (bxCAN)\n1124\n0x1C4\nCAN_RDT1R\nTIME[15:0]\nFMI[7:0]\nReserved\nDLC[3:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1C8\nCAN_RDL1R\nDATA3[7:0]\nDATA2[7:0]\nDATA1[7:0]\nDATA0[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1CC\nCAN_RDH1R\nDATA7[7:0]\nDATA6[7:0]\nDATA5[7:0]\nDATA4[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1D0-\n0x1FF\nReserved\n0x200\nCAN_FMR\nReserved\nCAN2SB[5:0]\nReserved\nFINIT\nReset value\n0\n0\n1\n1\n1\n0\n1\n0x204\nCAN_FM1R\nReserved\nFBM[27:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x208\nReserved\n0x20C\nCAN_FS1R\nReserved\nFSC[27:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x210\nReserved\n0x214\nCAN_FFA1R\nReserved\nFFA[27:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x218\nReserved\n0x21C\nCAN_FA1R\nReserved\nFACT[27:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x220\nReserved\n0x224-\n0x23F\nReserved\n0x240\nCAN_F0R1\nFB[31:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x244\nCAN_F0R2\nFB[31:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x248\nCAN_F1R1\nFB[31:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nTable 185. bxCAN register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nController area network (bxCAN)\nRM0090\n1124/1757\nRM0090 Rev 21\n0x24C\nCAN_F1R2\nFB[31:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n.\n.\n.\n.\n.\n.\n.\n.\n.\n.\n.\n.\n0x318\nCAN_F27R1\nFB[31:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x31C\nCAN_F27R2\nFB[31:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nTable 185. bxCAN register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1125/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n33 \nEthernet (ETH): media access control (MAC) with\nDMA controller\nThis section applies only to STM32F42xx/F43xx and STM32F407x/F417x devices.\n33.1 \nEthernet introduction\nPortions Copyright (c) 2004, 2005 Synopsys, Inc. All rights reserved. Used with permission.\nThe Ethernet peripheral enables the STM32F4xx to transmit and receive data over Ethernet \nin compliance with the IEEE 802.3-2002 standard.\nThe Ethernet provides a configurable, flexible peripheral to meet the needs of various \napplications and customers. It supports two industry standard interfaces to the external \nphysical layer (PHY): the default media independent interface (MII) defined in the IEEE \n802.3 specifications and the reduced media independent interface (RMII). It can be used in \nnumber of applications such as switches, network interface cards, etc.\nThe Ethernet is compliant with the following standards:\n•\nIEEE 802.3-2002 for Ethernet MAC\n•\nIEEE 1588-2008 standard for precision networked clock synchronization\n•\nAMBA 2.0 for AHB Master/Slave ports\n•\nRMII specification from RMII consortium\n33.2 \nEthernet main features\nThe Ethernet (ETH) peripheral includes the following features, listed by category:\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1126/1757\nRM0090 Rev 21\n33.2.1 \nMAC core features\n•\nSupports 10/100 Mbit/s data transfer rates with external PHY interfaces\n•\nIEEE 802.3-compliant MII interface to communicate with an external Fast Ethernet \nPHY\n•\nSupports both full-duplex and half-duplex operations\n–\nSupports CSMA/CD Protocol for half-duplex operation\n–\nSupports IEEE 802.3x flow control for full-duplex operation\n–\nOptional forwarding of received pause control frames to the user application in full-\nduplex operation\n–\nBack-pressure support for half-duplex operation\n–\nAutomatic transmission of zero-quanta pause frame on deassertion of flow control \ninput in full-duplex operation\n•\nPreamble and start-of-frame data (SFD) insertion in Transmit, and deletion in Receive \npaths\n•\nAutomatic CRC and pad generation controllable on a per-frame basis\n•\nOptions for automatic pad/CRC stripping on receive frames\n•\nProgrammable frame length to support Standard frames with sizes up to 16 KB\n•\nProgrammable interframe gap (40-96 bit times in steps of 8)\n•\nSupports a variety of flexible address filtering modes:\n–\nUp to four 48-bit perfect (DA) address filters with masks for each byte\n–\nUp to three 48-bit SA address comparison check with masks for each byte\n–\n64-bit Hash filter (optional) for multicast and unicast (DA) addresses\n–\nOption to pass all multicast addressed frames\n–\nPromiscuous mode support to pass all frames without any filtering for network \nmonitoring\n–\nPasses all incoming packets (as per filter) with a status report\n•\nSeparate 32-bit status returned for transmission and reception packets\n•\nSupports IEEE 802.1Q VLAN tag detection for reception frames\n•\nSeparate transmission, reception, and control interfaces to the Application\n•\nSupports mandatory network statistics with RMON/MIB counters (RFC2819/RFC2665)\n•\nMDIO interface for PHY device configuration and management\n•\nDetection of LAN wake-up frames and AMD Magic Packet™ frames\n•\nReceive feature for checksum off-load for received IPv4 and TCP packets \nencapsulated by the Ethernet frame\n•\nEnhanced receive feature for checking IPv4 header checksum and TCP, UDP, or ICMP \nchecksum encapsulated in IPv4 or IPv6 datagrams\n•\nSupport Ethernet frame time stamping as described in IEEE 1588-2008. Sixty-four-bit \ntime stamps are given in each frame’s transmit or receive status\n•\nTwo sets of FIFOs: a 2-KB Transmit FIFO with programmable threshold capability, and \na 2-KB Receive FIFO with a configurable threshold (default of 64 bytes)\n•\nReceive Status vectors inserted into the Receive FIFO after the EOF transfer enables \nmultiple-frame storage in the Receive FIFO without requiring another FIFO to store \nthose frames’ Receive Status\n•\nOption to filter all error frames on reception and not forward them to the application in \n\n\n<>\n\nRM0090 Rev 21\n1127/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nStore-and-Forward mode\n•\nOption to forward under-sized good frames\n•\nSupports statistics by generating pulses for frames dropped or corrupted (due to \noverflow) in the Receive FIFO\n•\nSupports Store and Forward mechanism for transmission to the MAC core\n•\nAutomatic generation of PAUSE frame control or back pressure signal to the MAC core \nbased on Receive FIFO-fill (threshold configurable) level\n•\nHandles automatic retransmission of Collision frames for transmission\n•\nDiscards frames on late collision, excessive collisions, excessive deferral and underrun \nconditions\n•\nSoftware control to flush Tx FIFO\n•\nCalculates and inserts IPv4 header checksum and TCP, UDP, or ICMP checksum in \nframes transmitted in Store-and-Forward mode\n•\nSupports internal loopback on the MII for debugging\n33.2.2 \nDMA features\n•\nSupports all AHB burst types in the AHB Slave Interface\n•\nSoftware can select the type of AHB burst (fixed or indefinite burst) in the AHB Master \ninterface.\n•\nOption to select address-aligned bursts from AHB master port\n•\nOptimization for packet-oriented DMA transfers with frame delimiters\n•\nByte-aligned addressing for data buffer support\n•\nDual-buffer (ring) or linked-list (chained) descriptor chaining\n•\nDescriptor architecture, allowing large blocks of data transfer with minimum CPU \nintervention;\n•\neach descriptor can transfer up to 8 KB of data\n•\nComprehensive status reporting for normal operation and transfers with errors\n•\nIndividual programmable burst size for Transmit and Receive DMA Engines for optimal \nhost bus utilization\n•\nProgrammable interrupt options for different operational conditions\n•\nPer-frame Transmit/Receive complete interrupt control\n•\nRound-robin or fixed-priority arbitration between Receive and Transmit engines\n•\nStart/Stop modes\n•\nCurrent Tx/Rx buffer pointer as status registers\n•\nCurrent Tx/Rx descriptor pointer as status registers\n33.2.3 \nPTP features\n•\nReceived and transmitted frames time stamping\n•\nCoarse and fine correction methods\n•\nTrigger interrupt when system time becomes greater than target time\n•\nPulse per second output (product alternate function output)\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1128/1757\nRM0090 Rev 21\n33.3 \nEthernet pins\nTable 186 shows the MAC signals and the corresponding MII/RMII signal mapping. All MAC \nsignals are mapped onto AF11, some signals are mapped onto different I/O pins, and \nshould be configured in Alternate function mode (for more details, refer to Section 8.3.2: I/O \npin multiplexer and mapping).\n \nTable 186. Alternate function mapping\nPort\nAF11\nETH\nPA0-WKUP\nETH_MII_CRS\nPA1\nETH_MII _RX_CLK / ETH_RMII _REF_CLK\nPA2\nETH _MDIO\nPA3\nETH _MII_COL\nPA7\nETH_MII _RX_DV / ETH_RMII _CRS_DV\nPB0\nETH _MII_RXD2\nPB1\nETH _MII_RXD3\nPB5\nETH _PPS_OUT\nPB8\nETH _MII_TXD3\nPB10\nETH_ MII_RX_ER\nPB11\nETH _MII_TX_EN / ETH _RMII_TX_EN\nPB12\nETH _MII_TXD0 / ETH _RMII_TXD0\nPB13\nETH _MII_TXD1 / ETH _RMII_TXD1\nPC1\nETH _MDC\nPC2\nETH _MII_TXD2\nPC3\nETH _MII_TX_CLK\nPC4\nETH_MII_RXD0 / ETH_RMII_RXD0\nPC5\nETH _MII_RXD1/ ETH _RMII_RXD1\nPE2\nETH_MII_TXD3\nPG8\nETH_PPS_OUT\nPG11\nETH _MII_TX_EN / ETH _RMII_TX_EN\nPG13\nETH _MII_TXD0 / ETH _RMII_TXD0\nPG14\nETH _MII_TXD1 / ETH _RMII_TXD1\nPH2\nETH _MII_CRS\nPH3\nETH _MII_COL\nPH6\nETH _MII_RXD2\nPH7\nETH _MII_RXD3\nPI10\nETH _MII_RX_ER\n\n\n<>\n\nRM0090 Rev 21\n1129/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n33.4 \nEthernet functional description: SMI, MII and RMII\nThe Ethernet peripheral consists of a MAC 802.3 (media access control) with a dedicated \nDMA controller. It supports both default media-independent interface (MII) and reduced \nmedia-independent interface (RMII) through one selection bit (refer to SYSCFG_PMC \nregister).\nThe DMA controller interfaces with the Core and memories through the AHB Master and \nSlave interfaces. The AHB Master Interface controls data transfers while the AHB Slave \ninterface accesses Control and Status registers (CSR) space.\nThe Transmit FIFO (Tx FIFO) buffers data read from system memory by the DMA before \ntransmission by the MAC Core. Similarly, the Receive FIFO (Rx FIFO) stores the Ethernet \nframes received from the line until they are transferred to system memory by the DMA. \nThe Ethernet peripheral also includes an SMI to communicate with external PHY. A set of \nconfiguration registers permit the user to select the desired mode and features for the MAC \nand the DMA controller.\nNote:\nThe AHB clock frequency must be at least 25 MHz when the Ethernet is used.\nFigure 350. ETH block diagram\n1.\nFor AHB connections refer to Figure 1: System architecture for STM32F405xx/07xx and \nSTM32F415xx/17xx devices and Figure 2: System architecture for STM32F42xxx and STM32F43xxx \ndevices.\n33.4.1 \nStation management interface: SMI\nThe station management interface (SMI) allows the application to access any PHY registers \nthrough a 2-wire clock and data lines. The interface supports accessing up to 32 PHYs.\nThe application can select one of the 32 PHYs and one of the 32 registers within any PHY \nand send control data or receive status information. Only one register in one PHY can be \naddressed at any given time.\nBoth the MDC clock line and the MDIO data line are implemented as alternate function I/O \nin the microcontroller:\n•\nMDC: a periodic clock that provides the timing reference for the data transfer at the \nmaximum frequency of 2.5 MHz. The minimum high and low times for MDC must be \n2 Kbyte\nRX FIFO\n \nEthernet\nDMA \nMedia access\ncontrol\nMAC 802.3 \nMAC\ncontrol\nregisters\nDMA\ncontrol &\nstatus\nregisters\nOperation\nmode\nregister\n \nInterface\nSelect \nMII \nMDC \nMDIO\nAHB Slave interface\nRMII \nai15620c\nBus matrix\nExternal PHY\nChecksum\noffload\nPTP\nIEEE1588\nPMT\nMMC\n2 Kbyte\nTX FIFO\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1130/1757\nRM0090 Rev 21\n160 ns each, and the minimum period for MDC must be 400 ns. In idle state the SMI \nmanagement interface drives the MDC clock signal low.\n•\nMDIO: data input/output bitstream to transfer status information to/from the PHY device \nsynchronously with the MDC clock signal\nFigure 351. SMI interface signals\nSMI frame format\nThe frame structure related to a read or write operation is shown in Table 187, the order of \nbit transmission must be from left to right.\n \nThe management frame consists of eight fields:\n•\nPreamble: each transaction (read or write) can be initiated with the preamble field that \ncorresponds to 32 contiguous logic one bits on the MDIO line with 32 corresponding \ncycles on MDC. This field is used to establish synchronization with the PHY device.\n•\nStart: the start of frame is defined by a <01> pattern to verify transitions on the line \nfrom the default logic one state to zero and back to one.\n•\nOperation: defines the type of transaction (read or write) in progress.\n•\nPADDR: the PHY address is 5 bits, allowing 32 unique PHY addresses. The MSB bit of \nthe address is the first transmitted and received.\n•\nRADDR: the register address is 5 bits, allowing 32 individual registers to be addressed \nwithin the selected PHY device. The MSB bit of the address is the first transmitted and \nreceived.\n•\nTA: the turn-around field defines a 2-bit pattern between the RADDR and DATA fields \nto avoid contention during a read transaction. For a read transaction the MAC controller \ndrives high-impedance on the MDIO line for the 2 bits of TA. The PHY device must \ndrive a high-impedance state on the first bit of TA, a zero bit on the second one.\nTable 187. Management frame format\nManagement frame fields\nPreamble \n(32 bits)\nStart\nOperation\nPADDR\nRADDR\nTA\nData (16 bits)\nIdle\nRead\n1... 1\n 01\n 10\nppppp\nrrrrr\nZ0\nddddddddddddddd\nZ\nWrite\n1... 1\n 01\n 01\nppppp\nrrrrr\n10\nddddddddddddddd\nZ\nSTM32 MCU \nMDIO\n \nMDC\nExternal \nPHY \nai15621b\n802.3 MAC\n\n\n<>\n\nRM0090 Rev 21\n1131/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nFor a write transaction, the MAC controller drives a <10> pattern during the TA field. \nThe PHY device must drive a high-impedance state for the 2 bits of TA.\n•\nData: the data field is 16-bit. The first bit transmitted and received must be bit 15 of the \nETH_MIID register.\n•\nIdle: the MDIO line is driven in high-impedance state. All three-state drivers must be \ndisabled and the PHY’s pull-up resistor keeps the line at logic one.\nSMI write operation\nWhen the application sets the MII Write and Busy bits (in Ethernet MAC MII address register \n(ETH_MACMIIAR)), the SMI initiates a write operation into the PHY registers by transferring \nthe PHY address, the register address in PHY, and the write data (in Ethernet MAC MII data \nregister (ETH_MACMIIDR). The application should not change the MII Address register \ncontents or the MII Data register while the transaction is ongoing. Write operations to the MII \nAddress register or the MII Data register during this period are ignored (the Busy bit is high), \nand the transaction is completed without any error. After the Write operation has completed, \nthe SMI indicates this by resetting the Busy bit.\nFigure 352 shows the frame format for the write operation.\nFigure 352. MDIO timing and frame structure - Write cycle\nSMI read operation\nWhen the user sets the MII Busy bit in the Ethernet MAC MII address register \n(ETH_MACMIIAR) with the MII Write bit at 0, the SMI initiates a read operation in the PHY \nregisters by transferring the PHY address and the register address in PHY. The application \nshould not change the MII Address register contents or the MII Data register while the \ntransaction is ongoing. Write operations to the MII Address register or MII Data register \nduring this period are ignored (the Busy bit is high) and the transaction is completed without \nany error. After the read operation has completed, the SMI resets the Busy bit and then \nupdates the MII Data register with the data read from the PHY. \nFigure 353 shows the frame format for the read operation.\nMDC\nMDIO\n32 1's\n0\n1\n0 1\nA4\nA3\nA2\nA1 A0\nR4\nR3\nR2\nR1\nR0\nD15 D14\nD1\nD0\nPreamble\nStart\nof\nframe\nOP\ncode\nPHY address\nRegister address\nTurn\naround\ndata\nData to PHY\nai15626\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1132/1757\nRM0090 Rev 21\nFigure 353. MDIO timing and frame structure - Read cycle\nSMI clock selection\nThe MAC initiates the Management Write/Read operation. The SMI clock is a divided clock \nwhose source is the application clock (AHB clock). The divide factor depends on the clock \nrange setting in the MII Address register.\nTable 188 shows how to set the clock ranges.\n \n33.4.2 \nMedia-independent interface: MII\nThe media-independent interface (MII) defines the interconnection between the MAC \nsublayer and the PHY for data transfer at 10 Mbit/s and 100 Mbit/s.\nFigure 354. Media independent interface signals\nTable 188. Clock range\nSelection\nHCLK clock\nMDC clock\n000\n60-100 MHz\nAHB clock / 42\n001\n100-150 MHz\nAHB clock / 62\n010\n20-35 MHz\nAHB clock / 16\n011\n35-60 MHz\nAHB clock / 26\n100\n150-180 MHz\nAHB clock / 102\n 101, 110, 111\nReserved\n-\nMDC\nMDIO\n32 1's\n0\n1\n1\n0\nA4\nA3\nA2\nA1 A0\nR4\nR3\nR2\nR1\nR0\nD15 D14\nD1\nD0\nPreamble\nStart\nof\nframe\nOP\ncode\nPHY address\nRegister address\nTurn\naround\ndata\nData to PHY\nai15627\nData from PHY\nMDC \nMDIO \nRX_DV \nCRS \nCOL \nTX_EN \nRX_CLK \nRXD[3:0] \nRX_ER \nTX _CLK \nTXD[3:0]\n \nExternal\n PHY\nai15622c\n802.3 MAC\nSTM32 MCU \n\n\n<>\n\nRM0090 Rev 21\n1133/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n•\nMII_TX_CLK: continuous clock that provides the timing reference for the TX data \ntransfer. The nominal frequency is: 2.5 MHz at 10 Mbit/s speed; 25 MHz at 100 Mbit/s \nspeed.\n•\nMII_RX_CLK: continuous clock that provides the timing reference for the RX data \ntransfer. The nominal frequency is: 2.5 MHz at 10 Mbit/s speed; 25 MHz at 100 Mbit/s \nspeed.\n•\nMII_TX_EN: transmission enable indicates that the MAC is presenting nibbles on the \nMII for transmission. It must be asserted synchronously (MII_TX_CLK) with the first \nnibble of the preamble and must remain asserted while all nibbles to be transmitted are \npresented to the MII.\n•\nMII_TXD[3:0]: transmit data is a bundle of 4 data signals driven synchronously by the \nMAC sublayer and qualified (valid data) on the assertion of the MII_TX_EN signal. \nMII_TXD[0] is the least significant bit, MII_TXD[3] is the most significant bit. While \nMII_TX_EN is deasserted the transmit data must have no effect upon the PHY.\n•\nMII_CRS: carrier sense is asserted by the PHY when either the transmit or receive \nmedium is non idle. It shall be deasserted by the PHY when both the transmit and \nreceive media are idle. The PHY must ensure that the MII_CS signal remains asserted \nthroughout the duration of a collision condition. This signal is not required to transition \nsynchronously with respect to the TX and RX clocks. In full duplex mode the state of \nthis signal is don’t care for the MAC sublayer.\n•\nMII_COL: collision detection must be asserted by the PHY upon detection of a collision \non the medium and must remain asserted while the collision condition persists. This \nsignal is not required to transition synchronously with respect to the TX and RX clocks. \nIn full duplex mode the state of this signal is don’t care for the MAC sublayer.\n•\nMII_RXD[3:0]: reception data is a bundle of 4 data signals driven synchronously by the \nPHY and qualified (valid data) on the assertion of the MII_RX_DV signal. MII_RXD[0] is \nthe least significant bit, MII_RXD[3] is the most significant bit. While MII_RX_EN is \ndeasserted and MII_RX_ER is asserted, a specific MII_RXD[3:0] value is used to \ntransfer specific information from the PHY (see Table 190).\n•\nMII_RX_DV: receive data valid indicates that the PHY is presenting recovered and \ndecoded nibbles on the MII for reception. It must be asserted synchronously \n(MII_RX_CLK) with the first recovered nibble of the frame and must remain asserted \nthrough the final recovered nibble. It must be deasserted prior to the first clock cycle \nthat follows the final nibble. In order to receive the frame correctly, the MII_RX_DV \nsignal must encompass the frame, starting no later than the SFD field.\n•\nMII_RX_ER: receive error must be asserted for one or more clock periods \n(MII_RX_CLK) to indicate to the MAC sublayer that an error was detected somewhere \nin the frame. This error condition must be qualified by MII_RX_DV assertion as \ndescribed in Table 190.\n \nTable 189. TX interface signal encoding\nMII_TX_EN\nMII_TXD[3:0]\nDescription\n0\n0000 through 1111\nNormal inter-frame\n1\n0000 through 1111\nNormal data transmission\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1134/1757\nRM0090 Rev 21\n \nMII clock sources\nTo generate both TX_CLK and RX_CLK clock signals, the external PHY must be clocked \nwith an external 25 MHz as shown in Figure 355. Instead of using an external 25 MHz \nquartz to provide this clock, the STM32F4xxmicrocontroller can output this signal on its \nMCO pin. In this case, the PLL multiplier has to be configured so as to get the desired \nfrequency on the MCO pin, from the 25 MHz external quartz.\nFigure 355. MII clock sources\n33.4.3 \nReduced media-independent interface: RMII\nThe reduced media-independent interface (RMII) specification reduces the pin count \nbetween the microcontroller Ethernet peripheral and the external Ethernet in 10/100 Mbit/s. \nAccording to the IEEE 802.3u standard, an MII contains 16 pins for data and control. The \nRMII specification is dedicated to reduce the pin count to 7 pins (a 62.5% decrease in pin \ncount).\nTable 190. RX interface signal encoding\nMII_RX_DV\nMII_RX_ERR\nMII_RXD[3:0]\nDescription\n0\n0\n0000 through 1111\nNormal inter-frame\n0\n1\n0000 \nNormal inter-frame\n0\n1\n0001 through 1101\nReserved\n0\n1\n1110\nFalse carrier indication\n0\n1\n1111\nReserved\n1\n0\n0000 through 1111\nNormal data reception\n1\n1\n0000 through 1111\nData reception with errors\nSTM32 \nMCU \n \nMCO \n25 MHz \n25 MHz \nTX _CLK \nFor 10/100 Mbit/s\nRX _CLK\nHSE\n802.3 MAC\nai15623b\nExternal\n PHY\n\n\n<>\n\nRM0090 Rev 21\n1135/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nThe RMII is instantiated between the MAC and the PHY. This helps translation of the MAC’s \nMII into the RMII. The RMII block has the following characteristics:\n•\nIt supports 10-Mbit/s and 100-Mbit/s operating rates\n•\nThe clock reference must be doubled to 50 MHz\n•\nThe same clock reference must be sourced externally to both MAC and external \nEthernet PHY\n•\nIt provides independent 2-bit wide (dibit) transmit and receive data paths\nFigure 356. Reduced media-independent interface signals\nRMII clock sources\nEither clock the PHY from an external 50 MHz clock or use a PHY with an embedded PLL to \ngenerate the 50 MHz frequency. \nFigure 357. RMII clock sources\n33.4.4 \nMII/RMII selection\nThe mode, MII or RMII, is selected using the configuration bit 23, MII_RMII_SEL, in the \nSYSCFG_PMC register. The application has to set the MII/RMII mode while the Ethernet \ncontroller is under reset or before enabling the clocks.\nSTM32 \nMCU \nTXD[1:0] \nTX_EN \nRXD[1:0] \nCRS_DV \nMDC \nMDIO \nREF_ CLK\nClock source\n802.3 MAC\nExternal\n PHY\nai15624b\nMS19930V1\nSTM32 \nMCU \nREF_CLK\n50 MHz \n25 MHz\n \nPLL \nFor 10/100 Mbit/s\nExternal\n PHY\n802.3 MAC\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1136/1757\nRM0090 Rev 21\nMII/RMII internal clock scheme\nThe clock scheme required to support both the MII and RMII, as well as 10 and 100 Mbit/s \noperations is described in Figure 358.\nFigure 358. Clock scheme\n1.\nThe MII/RMII selection is controlled through bit 23, MII_RMII_SEL, in the SYSCFG_PMC register.\nTo save a pin, the two input clock signals, RMII_REF_CK and MII_RX_CLK, are multiplexed \non the same GPIO pin.\n33.5 \nEthernet functional description: MAC 802.3\nThe IEEE 802.3 International Standard for local area networks (LANs) employs the \nCSMA/CD (carrier sense multiple access with collision detection) as the access method.\nThe Ethernet peripheral consists of a MAC 802.3 (media access control) controller with \nmedia independent interface (MII) and a dedicated DMA controller.\nThe MAC block implements the LAN CSMA/CD sublayer for the following families of \nsystems: 10 Mbit/s and 100 Mbit/s of data rates for baseband and broadband systems. Half- \nand full-duplex operation modes are supported. The collision detection access method is \napplied only to the half-duplex operation mode. The MAC control frame sublayer is \nsupported.\nThe MAC sublayer performs the following functions associated with a data link control \nprocedure:\n•\nData encapsulation (transmit and receive)\n–\nFraming (frame boundary delimitation, frame synchronization)\n–\nAddressing (handling of source and destination addresses)\n–\nError detection\n•\nMedia access management\n–\nMedium allocation (collision avoidance)\n–\nContention resolution (collision handling)\nGPIO and AF\ncontroller\nGPIO and AF\ncontroller\nMII_TX_CLK as AF\n(25 MHz or 2.5 MHz)\nMII_RX_CLK as AF\n(25 MHz or 2.5 MHz)\nSync. divider\n/2 for 100 Mb/s\n/20 for 10 Mb/s\n50 MHz\n0\n1\n0\n1\n25 MHz or 2.5 MHz\n25 MHz or 2.5 MHz\n0 MII\n1 RMII(1)\n25 MHz\nor 2.5 MHz\n25 MHz\nor 2.5 MHz\nMACTXCLK\nMACRXCLK\nTX\nRX\nAHB\nHCLK\nHCLK\nMAC\nmust be greater\nthan 25 MHz\nai15650\nRMII\nRMII_REF_CK as AF\n(50 MHz)\n\n\n<>\n\nRM0090 Rev 21\n1137/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nBasically there are two operating modes of the MAC sublayer:\n•\nHalf-duplex mode: the stations contend for the use of the physical medium, using the \nCSMA/CD algorithms.\n•\nFull duplex mode: simultaneous transmission and reception without contention \nresolution (CSMA/CD algorithm are unnecessary) when all the following conditions are \nmet:\n–\nphysical medium capability to support simultaneous transmission and reception\n–\nexactly 2 stations connected to the LAN\n–\nboth stations configured for full-duplex operation\n33.5.1 \nMAC 802.3 frame format\nThe MAC block implements the MAC sublayer and the optional MAC control sublayer \n(10/100 Mbit/s) as specified by the IEEE 802.3-2002 standard.\nTwo frame formats are specified for data communication systems using the CSMA/CD \nMAC:\n•\nBasic MAC frame format\n•\nTagged MAC frame format (extension of the basic MAC frame format)\nFigure 360 and Figure 361 describe the frame structure (untagged and tagged) that \nincludes the following fields:\n•\nPreamble: 7-byte field used for synchronization purposes (PLS circuitry)\nHexadecimal value: 55-55-55-55-55-55-55\nBit pattern: 01010101 01010101 01010101 01010101 01010101 01010101 01010101 \n(right-to-left bit transmission)\n•\nStart frame delimiter (SFD): 1-byte field used to indicate the start of a frame. \nHexadecimal value: D5\nBit pattern: 11010101 (right-to-left bit transmission)\n•\nDestination and Source Address fields: 6-byte fields to indicate the destination and \nsource station addresses as follows (see Figure 359):\n–\nEach address is 48 bits in length\n–\nThe first LSB bit (I/G) in the destination address field is used to indicate an \nindividual (I/G = 0) or a group address (I/G = 1). A group address could identify \nnone, one or more, or all the stations connected to the LAN. In the source address \nthe first bit is reserved and reset to 0.\n–\nThe second bit (U/L) distinguishes between locally (U/L = 1) or globally (U/L = 0) \nadministered addresses. For broadcast addresses this bit is also 1.\n–\nEach byte of each address field must be transmitted least significant bit first.\nThe address designation is based on the following types:\n•\nIndividual address: this is the physical address associated with a particular station on \nthe network.\n•\nGroup address. A multidestination address associated with one or more stations on a \ngiven network. There are two kinds of multicast address:\n–\nMulticast-group address: an address associated with a group of logically related \nstations.\n–\nBroadcast address: a distinguished, predefined multicast address (all 1’s in the \ndestination address field) that always denotes all the stations on a given LAN.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1138/1757\nRM0090 Rev 21\nFigure 359. Address field format\n•\nQTag Prefix: 4-byte field inserted between the Source address field and the MAC Client \nLength/Type field. This field is an extension of the basic frame (untagged) to obtain the \ntagged MAC frame. The untagged MAC frames do not include this field. The \nextensions for tagging are as follows:\n–\n2-byte constant Length/Type field value consistent with the Type interpretation \n(greater than 0x0600) equal to the value of the 802.1Q Tag Protocol Type (0x8100 \nhexadecimal). This constant field is used to distinguish tagged and untagged MAC \nframes.\n–\n2-byte field containing the Tag control information field subdivided as follows: a 3-\nbit user priority, a canonical format indicator (CFI) bit and a 12-bit VLAN Identifier. \nThe length of the tagged MAC frame is extended by 4 bytes by the QTag Prefix.\n•\nMAC client length/type: 2-byte field with different meaning (mutually exclusive), \ndepending on its value:\n–\nIf the value is less than or equal to maxValidFrame (0d1500) then this field \nindicates the number of MAC client data bytes contained in the subsequent data \nfield of the 802.3 frame (length interpretation).\n–\nIf the value is greater than or equal to MinTypeValue (0d1536 decimal, 0x0600) \nthen this field indicates the nature of the MAC client protocol (Type interpretation) \nrelated to the Ethernet frame.\nRegardless of the interpretation of the length/type field, if the length of the data field is \nless than the minimum required for proper operation of the protocol, a PAD field is \nadded after the data field but prior to the FCS (frame check sequence) field. The \nlength/type field is transmitted and received with the higher-order byte first.\nFor length/type field values in the range between maxValidLength and minTypeValue \n(boundaries excluded), the behavior of the MAC sublayer is not specified: they may or \nmay not be passed by the MAC sublayer.\n•\nData and PAD fields: n-byte data field. Full data transparency is provided, it means that \nany arbitrary sequence of byte values may appear in the data field. The size of the \nPAD, if any, is determined by the size of the data field. Max and min length of the data \nand PAD field are:\n–\nMaximum length = 1500 bytes\n–\nMinimum length for untagged MAC frames = 46 bytes\n–\nMinimum length for tagged MAC frames = 42 bytes\nWhen the data field length is less than the minimum required, the PAD field is added to \nmatch the minimum length (42 bytes for tagged frames, 46 bytes for untagged frames).\n•\nFrame check sequence: 4-byte field that contains the cyclic redundancy check (CRC) \nvalue. The CRC computation is based on the following fields: source address, \ndestination address, QTag prefix, length/type, LLC data and PAD (that is, all fields \nexcept the preamble, SFD). The generating polynomial is the following:\nMSB\nLSB\nBit transmission order (right to left)\nU/L I/G\n46-bit address\nI/G = 0 Individual address\nI/G = 1 Group address\nU/L = 0 Globally administered address\nU/L = 1 Locally administered address \nai15628\nG x\n( )\nx32\nx26\nx23\nx22\nx16\nx12\nx11\nx10\nx8\nx7\nx5\nx4\nx2\nx\n1\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n=\n\n\n<>\n\nRM0090 Rev 21\n1139/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nThe CRC value of a frame is computed as follows:\n•\nThe first 2 bits of the frame are complemented\n•\nThe n-bits of the frame are the coefficients of a polynomial M(x) of degree (n – 1). The \nfirst bit of the destination address corresponds to the xn – 1 term and the last bit of the \ndata field corresponds to the x0 term\n•\nM(x) is multiplied by x32 and divided by G(x), producing a remainder R(x) of degree \n≤31\n•\nThe coefficients of R(x) are considered as a 32-bit sequence\n•\nThe bit sequence is complemented and the result is the CRC\n•\nThe 32-bits of the CRC value are placed in the frame check sequence. The x32 term is \nthe first transmitted, the x0 term is the last one\nFigure 360. MAC frame format\nPreamble\nSFD\nDestination address\nSource address\nMAC client length/type\nMAC client data\nPAD\nFrame check sequence\n7 bytes\n1 byte\n6 bytes\n6 bytes\n2 bytes\n46-1500 bytes\n4 bytes\nMSB\nLSB\nBit transmission order (right to left)\nBytes within\n frame transmitted\ntop to bottom\nai15629\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1140/1757\nRM0090 Rev 21\nFigure 361. Tagged MAC frame format\nEach byte of the MAC frame, except the FCS field, is transmitted low-order bit first.\nAn invalid MAC frame is defined by one of the following conditions:\n•\nThe frame length is inconsistent with the expected value as specified by the length/type \nfield. If the length/type field contains a type value, then the frame length is assumed to \nbe consistent with this field (no invalid frame)\n•\nThe frame length is not an integer number of bytes (extra bits)\n•\nThe CRC value computed on the incoming frame does not match the included FCS\n33.5.2 \nMAC frame transmission\nThe DMA controls all transactions for the transmit path. Ethernet frames read from the \nsystem memory are pushed into the FIFO by the DMA. The frames are then popped out and \ntransferred to the MAC core. When the end-of-frame is transferred, the status of the \ntransmission is taken from the MAC core and transferred back to the DMA. The Transmit \nFIFO has a depth of 2 Kbyte. FIFO-fill level is indicated to the DMA so that it can initiate a \ndata fetch in required bursts from the system memory, using the AHB interface. The data \nfrom the AHB Master interface is pushed into the FIFO.\nWhen the SOF is detected, the MAC accepts the data and begins transmitting to the MII. \nThe time required to transmit the frame data to the MII after the application initiates \ntransmission is variable, depending on delay factors like IFG delay, time to transmit \npreamble/SFD, and any back-off delays for Half-duplex mode. After the EOF is transferred \nto the MAC core, the core completes normal transmission and then gives the status of \ntransmission back to the DMA. If a normal collision (in Half-duplex mode) occurs during \ntransmission, the MAC core makes the transmit status valid, then accepts and drops all \nfurther data until the next SOF is received. The same frame should be retransmitted from \nSOF on observing a Retry request (in the Status) from the MAC. The MAC issues an \nunderflow status if the data are not provided continuously during the transmission. During \nthe normal transfer of a frame, if the MAC receives an SOF without getting an EOF for the \nprevious frame, then the SOF is ignored and the new frame is considered as the \ncontinuation of the previous frame.\nPreamble\nSFD\n Destination address\nSource address\nLength/type = 802.1QTagType\n Tag control information\nMAC client length/type\nMAC client data\n7 bytes\n1 byte\n6 bytes\n6 bytes\nQTag Prefix\n42-1500 bytes\n2 bytes\nMSB\nLSB\nBit transmission order (right to left)\nbytes within\n frame transmitted\ntop to bottom\nFrame check sequence\nPad\n4 bytes\n4 bytes\n1 0 0 0 0 0 0 0 1\nVLAN identifier (VID, 12 bits)\nCFI\nUser priority\nMSB\nLSB\n0 0 0 0 0 0 0 0 0\nai15630\n\n\n<>\n\nRM0090 Rev 21\n1141/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nThere are two modes of operation for popping data towards the MAC core:\n•\nIn Threshold mode, as soon as the number of bytes in the FIFO crosses the configured \nthreshold level (or when the end-of-frame is written before the threshold is crossed), \nthe data is ready to be popped out and forwarded to the MAC core. The threshold level \nis configured using the TTC bits of ETH_DMABMR.\n•\nIn Store-and-forward mode, only after a complete frame is stored in the FIFO, the frame \nis popped towards the MAC core. If the Tx FIFO size is smaller than the Ethernet frame \nto be transmitted, then the frame is popped towards the MAC core when the Tx FIFO \nbecomes almost full.\nThe application can flush the Transmit FIFO of all contents by setting the FTF \n(ETH_DMAOMR register [20]) bit. This bit is self-clearing and initializes the FIFO pointers to \nthe default state. If the FTF bit is set during a frame transfer to the MAC core, then transfer \nis stopped as the FIFO is considered to be empty. Hence an underflow event occurs at the \nMAC transmitter and the corresponding Status word is forwarded to the DMA.\nAutomatic CRC and pad generation\nWhen the number of bytes received from the application falls below 60 (DA+SA+LT+Data), \nzeros are appended to the transmitting frame to make the data length exactly 46 bytes to \nmeet the minimum data field requirement of IEEE 802.3. The MAC can be programmed not \nto append any padding. The cyclic redundancy check (CRC) for the frame check sequence \n(FCS) field is calculated and appended to the data being transmitted. When the MAC is \nprogrammed to not append the CRC value to the end of Ethernet frames, the computed \nCRC is not transmitted. An exception to this rule is that when the MAC is programmed to \nappend pads for frames (DA+SA+LT+Data) less than 60 bytes, CRC is appended at the end \nof the padded frames.\nThe CRC generator calculates the 32-bit CRC for the FCS field of the Ethernet frame. The \nencoding is defined by the following polynomial.\nTransmit protocol\nThe MAC controls the operation of Ethernet frame transmission. It performs the following \nfunctions to meet the IEEE 802.3/802.3z specifications. It:\n•\ngenerates the preamble and SFD\n•\ngenerates the jam pattern in Half-duplex mode\n•\ncontrols the Jabber timeout\n•\ncontrols the flow for Half-duplex mode (back pressure)\n•\ngenerates the transmit frame status\n•\ncontains time stamp snapshot logic in accordance with IEEE 1588\nWhen a new frame transmission is requested, the MAC sends out the preamble and SFD, \nfollowed by the data. The preamble is defined as 7 bytes of 0b10101010 pattern, and the \nSFD is defined as 1 byte of 0b10101011 pattern. The collision window is defined as 1 slot \ntime (512 bit times for 10/100 Mbit/s Ethernet). The jam pattern generation is applicable only \nto Half-duplex mode, not to Full-duplex mode.\nIn MII mode, if a collision occurs at any time from the beginning of the frame to the end of \nthe CRC field, the MAC sends a 32-bit jam pattern of 0x5555 5555 on the MII to inform all \nG x\n( )\nx32\nx26\nx23\nx22\nx16\nx12\nx11\nx10\nx8\nx7\nx5\nx4\nx2\nx\n1\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n=\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1142/1757\nRM0090 Rev 21\nother stations that a collision has occurred. If the collision is seen during the preamble \ntransmission phase, the MAC completes the transmission of the preamble and SFD and \nthen sends the jam pattern.\nA jabber timer is maintained to cut off the transmission of Ethernet frames if more than 2048 \n(default) bytes have to be transferred. The MAC uses the deferral mechanism for flow \ncontrol (back pressure) in Half-duplex mode. When the application requests to stop \nreceiving frames, the MAC sends a JAM pattern of 32 bytes whenever it senses the \nreception of a frame, provided that transmit flow control is enabled. This results in a collision \nand the remote station backs off. The application requests flow control by setting the BPA bit \n(bit 0) in the ETH_MACFCR register. If the application requests a frame to be transmitted, \nthen it is scheduled and transmitted even when back pressure is activated. Note that if back \npressure is kept activated for a long time (and more than 16 consecutive collision events \noccur) then the remote stations abort their transmissions due to excessive collisions. If IEEE \n1588 time stamping is enabled for the transmit frame, this block takes a snapshot of the \nsystem time when the SFD is put onto the transmit MII bus.\nTransmit scheduler\nThe MAC is responsible for scheduling the frame transmission on the MII. It maintains the \ninterframe gap between two transmitted frames and follows the truncated binary exponential \nbackoff algorithm for Half-duplex mode. The MAC enables transmission after satisfying the \nIFG and backoff delays. It maintains an idle period of the configured interframe gap (IFG bits \nin the ETH_MACCR register) between any two transmitted frames. If frames to be \ntransmitted arrive sooner than the configured IFG time, the MII waits for the enable signal \nfrom the MAC before starting the transmission on it. The MAC starts its IFG counter as soon \nas the carrier signal of the MII goes inactive. At the end of the programmed IFG value, the \nMAC enables transmission in Full-duplex mode. In Half-duplex mode and when IFG is \nconfigured for 96 bit times, the MAC follows the rule of deference specified in Section \n4.2.3.2.1 of the IEEE 802.3 specification. The MAC resets its IFG counter if a carrier is \ndetected during the first two-thirds (64-bit times for all IFG values) of the IFG interval. If the \ncarrier is detected during the final one third of the IFG interval, the MAC continues the IFG \ncount and enables the transmitter after the IFG interval. The MAC implements the truncated \nbinary exponential backoff algorithm when it operates in Half-duplex mode.\nTransmit flow control\nWhen the Transmit Flow Control Enable bit (TFE bit in ETH_MACFCR) is set, the MAC \ngenerates Pause frames and transmits them as necessary, in Full-duplex mode. The Pause \nframe is appended with the calculated CRC, and is sent. Pause frame generation can be \ninitiated in two ways.\nA pause frame is sent either when the application sets the FCB bit in the ETH_MACFCR \nregister or when the receive FIFO is full (packet buffer).\n•\nIf the application has requested flow control by setting the FCB bit in ETH_MACFCR, \nthe MAC generates and transmits a single Pause frame. The value of the pause time in \nthe generated frame contains the programmed pause time value in ETH_MACFCR. To \nextend the pause or end the pause prior to the time specified in the previously \ntransmitted Pause frame, the application must request another Pause frame \ntransmission after programming the Pause Time value (PT in ETH_MACFCR register) \nwith the appropriate value.\n•\nIf the application has requested flow control when the receive FIFO is full, the MAC \ngenerates and transmits a Pause frame. The value of the pause time in the generated \nframe is the programmed pause time value in ETH_MACFCR. If the receive FIFO \n\n\n<>\n\nRM0090 Rev 21\n1143/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nremains full at a configurable number of slot-times (PLT bits in ETH_MACFCR) before \nthis Pause time runs out, a second Pause frame is transmitted. The process is \nrepeated as long as the receive FIFO remains full. If this condition is no more satisfied \nprior to the sampling time, the MAC transmits a Pause frame with zero pause time to \nindicate to the remote end that the receive buffer is ready to receive new data frames.\nSingle-packet transmit operation\nThe general sequence of events for a transmit operation is as follows:\n1.\nIf the system has data to be transferred, the DMA controller fetches them from the \nmemory through the AHB Master interface and starts forwarding them to the FIFO. It \ncontinues to receive the data until the end of frame is transferred.\n2. \nWhen the threshold level is crossed or a full packet of data is received into the FIFO, \nthe frame data are popped and driven to the MAC core. The DMA continues to transfer \ndata from the FIFO until a complete packet has been transferred to the MAC. Upon \ncompletion of the frame, the DMA controller is notified by the status coming from the \nMAC.\nTransmit operation—Two packets in the buffer\n1.\nBecause the DMA must update the descriptor status before releasing it to the Host, \nthere can be at the most two frames inside a transmit FIFO. The second frame is \nfetched by the DMA and put into the FIFO only if the OSF (operate on second frame) \nbit is set. If this bit is not set, the next frame is fetched from the memory only after the \nMAC has completely processed the frame and the DMA has released the descriptors.\n2. \nIf the OSF bit is set, the DMA starts fetching the second frame immediately after \ncompleting the transfer of the first frame to the FIFO. It does not wait for the status to \nbe updated. In the meantime, the second frame is received into the FIFO while the first \nframe is being transmitted. As soon as the first frame has been transferred and the \nstatus is received from the MAC, it is pushed to the DMA. If the DMA has already \ncompleted sending the second packet to the FIFO, the second transmission must wait \nfor the status of the first packet before proceeding to the next frame.\nRetransmission during collision\nWhile a frame is being transferred to the MAC, a collision event may occur on the MAC line \ninterface in Half-duplex mode. The MAC would then indicate a retry attempt by giving the \nstatus even before the end of frame is received. Then the retransmission is enabled and the \nframe is popped out again from the FIFO. After more than 96 bytes have been popped \ntowards the MAC core, the FIFO controller frees up that space and makes it available to the \nDMA to push in more data. This means that the retransmission is not possible after this \nthreshold is crossed or when the MAC core indicates a late collision event.\nTransmit FIFO flush operation\nThe MAC provides a control to the software to flush the Transmit FIFO through the use of Bit \n20 in the Operation mode register. The Flush operation is immediate and the Tx FIFO and \nthe corresponding pointers are cleared to the initial state even if the Tx FIFO is in the middle \nof transferring a frame to the MAC Core. This results in an underflow event in the MAC \ntransmitter, and the frame transmission is aborted. The status of such a frame is marked \nwith both underflow and frame flush events (TDES0 bits 13 and 1). No data are coming to \nthe FIFO from the application (DMA) during the Flush operation. Transfer transmit status \nwords are transferred to the application for the number of frames that is flushed (including \npartial frames). Frames that are completely flushed have the Frame flush status bit (TDES0 \n13) set. The Flush operation is completed when the application (DMA) has accepted all of \n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1144/1757\nRM0090 Rev 21\nthe Status words for the frames that were flushed. The Transmit FIFO Flush control register \nbit is then cleared. At this point, new frames from the application (DMA) are accepted. All \ndata presented for transmission after a Flush operation are discarded unless they start with \nan SOF marker.\nTransmit status word\nAt the end of the Ethernet frame transfer to the MAC core and after the core has completed \nthe transmission of the frame, the transmit status is given to the application. The detailed \ndescription of the Transmit Status is the same as for bits [23:0] in TDES0. If IEEE 1588 time \nstamping is enabled, a specific frames’ 64-bit time stamp is returned, along with the transmit \nstatus.\nTransmit checksum offload\nCommunication protocols such as TCP and UDP implement checksum fields, which helps \ndetermine the integrity of data transmitted over a network. Because the most widespread \nuse of Ethernet is to encapsulate TCP and UDP over IP datagrams, the Ethernet controller \nhas a transmit checksum offload feature that supports checksum calculation and insertion in \nthe transmit path, and error detection in the receive path. This section explains the operation \nof the checksum offload feature for transmitted frames.\nNote:\nThe checksum for TCP, UDP or ICMP is calculated over a complete frame, then inserted \ninto its corresponding header field. Due to this requirement, this function is enabled only \nwhen the Transmit FIFO is configured for Store-and-forward mode (that is, when the TSF bit \nis set in the ETH_ETH_DMAOMR register). If the core is configured for Threshold (cut-\nthrough) mode, the Transmit checksum offload is bypassed.\nYou must make sure the Transmit FIFO is deep enough to store a complete frame before \nthat frame is transferred to the MAC Core transmitter. If the FIFO depth is less than the input \nEthernet frame size, the payload (TCP/UDP/ICMP) checksum insertion function is bypassed \nand only the frame’s IPv4 Header checksum is modified, even in Store-and-forward mode.\nThe transmit checksum offload supports two types of checksum calculation and insertion. \nThis checksum can be controlled for each frame by setting the CIC bits (Bits 27:23 in \nTDES0, described in TDES0: Transmit descriptor Word0).\nSee IETF specifications RFC 791, RFC 793, RFC 768, RFC 792, RFC 2460 and RFC 4443 \nfor IPv4, TCP, UDP, ICMP, IPv6 and ICMPv6 packet header specifications, respectively.\n•\nIP header checksum\nIn IPv4 datagrams, the integrity of the header fields is indicated by the 16-bit header \nchecksum field (the eleventh and twelfth bytes of the IPv4 datagram). The checksum \noffload detects an IPv4 datagram when the Ethernet frame’s Type field has the value \n0x0800 and the IP datagram’s Version field has the value 0x4. The input frame’s \nchecksum field is ignored during calculation and replaced by the calculated value. IPv6 \nheaders do not have a checksum field; thus, the checksum offload does not modify \nIPv6 header fields. The result of this IP header checksum calculation is indicated by the \nIP Header Error status bit in the Transmit status (Bit 16). This status bit is set whenever \nthe values of the Ethernet Type field and the IP header’s Version field are not \nconsistent, or when the Ethernet frame does not have enough data, as indicated by the \n\n\n<>\n\nRM0090 Rev 21\n1145/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nIP header Length field. In other words, this bit is set when an IP header error is \nasserted under the following circumstances:\na) \nFor IPv4 datagrams:\n–\nThe received Ethernet type is 0x0800, but the IP header’s Version field does not \nequal 0x4\n–\nThe IPv4 Header Length field indicates a value less than 0x5 (20 bytes)\n–\nThe total frame length is less than the value given in the IPv4 Header Length field\nb) \nFor IPv6 datagrams:\n–\nThe Ethernet type is 0x86DD but the IP header Version field does not equal 0x6 \n–\nThe frame ends before the IPv6 header (40 bytes) or extension header (as given \nin the corresponding Header Length field in an extension header) has been \ncompletely received. Even when the checksum offload detects such an IP header \nerror, it inserts an IPv4 header checksum if the Ethernet Type field indicates an \nIPv4 payload.\n•\nTCP/UDP/ICMP checksum\nThe TCP/UDP/ICMP checksum processes the IPv4 or IPv6 header (including \nextension headers) and determines whether the encapsulated payload is TCP, UDP or \nICMP.\nNote that:\na) \nFor non-TCP, -UDP, or -ICMP/ICMPv6 payloads, this checksum is bypassed and \nnothing further is modified in the frame.\nb) \nFragmented IP frames (IPv4 or IPv6), IP frames with security features (such as an \nauthentication header or encapsulated security payload), and IPv6 frames with \nrouting headers are bypassed and not processed by the checksum.\nThe checksum is calculated for the TCP, UDP, or ICMP payload and inserted into its \ncorresponding field in the header. It can work in the following two modes:\n–\nIn the first mode, the TCP, UDP, or ICMPv6 pseudo-header is not included in the \nchecksum calculation and is assumed to be present in the input frame’s checksum \nfield. The checksum field is included in the checksum calculation, and then \nreplaced by the final calculated checksum.\n–\nIn the second mode, the checksum field is ignored, the TCP, UDP, or ICMPv6 \npseudo-header data are included into the checksum calculation, and the \nchecksum field is overwritten with the final calculated value.\nNote that: for ICMP-over-IPv4 packets, the checksum field in the ICMP packet must \nalways be 0x0000 in both modes, because pseudo-headers are not defined for such \npackets. If it does not equal 0x0000, an incorrect checksum may be inserted into the \npacket.\nThe result of this operation is indicated by the payload checksum error status bit in the \nTransmit Status vector (bit 12). The payload checksum error status bit is set when \neither of the following is detected:\n–\nthe frame has been forwarded to the MAC transmitter in Store-and-forward mode \nwithout the end of frame being written to the FIFO\n–\nthe packet ends before the number of bytes indicated by the payload length field in \nthe IP header is received.\nWhen the packet is longer than the indicated payload length, the bytes are ignored as \nstuff bytes, and no error is reported. When the first type of error is detected, the TCP, \n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1146/1757\nRM0090 Rev 21\nUDP or ICMP header is not modified. For the second error type, still, the calculated \nchecksum is inserted into the corresponding header field.\nMII/RMII transmit bit order\nEach nibble from the MII is transmitted on the RMII a dibit at a time with the order of dibit \ntransmission shown in Figure 362. Lower order bits (D1 and D0) are transmitted first \nfollowed by higher order bits (D2 and D3).\nFigure 362. Transmission bit order\nMII/RMII transmit timing diagrams\nFigure 363. Transmission with no collision\nD0\nD1\nD2\nD3\nLSB\nMII_TXD[3:0]\nMSB\nD0\nD1\nLSB\nMSB\nRMII_TXD[1:0]\nBibit stream\nNibble stream\nai15632\nMII_TX_CLK\nMII_TX_EN\nMII_TXD[3:0]\nPR\nEA\nMB\nLE\nMII_CS\nMII_COL\nai15631\nLow\n\n\n<>\n\nRM0090 Rev 21\n1147/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nFigure 364. Transmission with collision\nFigure 365 shows a frame transmission in MII and RMII.\nFigure 365. Frame transmission in MMI and RMII modes\n33.5.3 \nMAC frame reception\nThe MAC received frames are pushes into the Rx FIFO. The status (fill level) of this FIFO is \nindicated to the DMA once it crosses the configured receive threshold (RTC in the \nETH_DMAOMR register) so that the DMA can initiate pre-configured burst transfers \ntowards the AHB interface.\nIn the default Cut-through mode, when 64 bytes (configured with the RTC bits in the \nETH_DMAOMR register) or a full packet of data are received into the FIFO, the data are \npopped out and the DMA is notified of its availability. Once the DMA has initiated the \ntransfer to the AHB interface, the data transfer continues from the FIFO until a complete \nMII_TX_CLK\nMII_TX_EN\nMII_TXD[3:0]\nPR\nEAM\nBLE\nSFD\nMII_CS\nMII_COL\nai15651\nDA\nDA\nJAM\nJAM\nJAM\nJAM\nMII_RX_CLK\nMII_TX_EN\nMII_TXD[3:0]\nRMII_REF_CLK\nRMII_TXD[1:0]\nRMII_TX_EN\nai15652\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1148/1757\nRM0090 Rev 21\npacket has been transferred. Upon completion of the EOF frame transfer, the status word is \npopped out and sent to the DMA controller.\nIn Rx FIFO Store-and-forward mode (configured by the RSF bit in the ETH_DMAOMR \nregister), a frame is read only after being written completely into the Receive FIFO. In this \nmode, all error frames are dropped (if the core is configured to do so) such that only valid \nframes are read and forwarded to the application. In Cut-through mode, some error frames \nare not dropped, because the error status is received at the end of the frame, by which time \nthe start of that frame has already been read of the FIFO.\nA receive operation is initiated when the MAC detects an SFD on the MII. The core strips the \npreamble and SFD before proceeding to process the frame. The header fields are checked \nfor the filtering and the FCS field used to verify the CRC for the frame. The frame is dropped \nin the core if it fails the address filter.\nReceive protocol\nThe received frame preamble and SFD are stripped. Once the SFD has been detected, the \nMAC starts sending the Ethernet frame data to the receive FIFO, beginning with the first \nbyte following the SFD (destination address). If IEEE 1588 time stamping is enabled, a \nsnapshot of the system time is taken when any frame's SFD is detected on the MII. Unless \nthe MAC filters out and drops the frame, this time stamp is passed on to the application.\nIf the received frame length/type field is less than 0x600 and if the MAC is programmed for \nthe auto CRC/pad stripping option, the MAC sends the data of the frame to RxFIFO up to \nthe count specified in the length/type field, then starts dropping bytes (including the FCS \nfield). If the Length/Type field is greater than or equal to 0x600, the MAC sends all received \nEthernet frame data to Rx FIFO, regardless of the value on the programmed auto-CRC strip \noption. The MAC watchdog timer is enabled by default, that is, frames above 2048 bytes \n(DA + SA + LT + Data + pad + FCS) are cut off. This feature can be disabled by \nprogramming the watchdog disable (WD) bit in the MAC configuration register. However, \neven if the watchdog timer is disabled, frames greater than 16 KB in size are cut off and a \nwatchdog timeout status is given.\nReceive CRC: automatic CRC and pad stripping\nThe MAC checks for any CRC error in the receiving frame. It calculates the 32-bit CRC for \nthe received frame that includes the Destination address field through the FCS field. The \nencoding is defined by the following polynomial.\nRegardless of the auto-pad/CRC strip, the MAC receives the entire frame to compute the \nCRC check for the received frame.\nReceive checksum offload\nBoth IPv4 and IPv6 frames in the received Ethernet frames are detected and processed for \ndata integrity. You can enable the receive checksum offload by setting the IPCO bit in the \nETH_MACCR register. The MAC receiver identifies IPv4 or IPv6 frames by checking for \nvalue 0x0800 or 0x86DD, respectively, in the received Ethernet frame Type field. This \nidentification applies to VLAN-tagged frames as well. The receive checksum offload \ncalculates IPv4 header checksums and checks that they match the received IPv4 header \nchecksums. The IP Header Error bit is set for any mismatch between the indicated payload \nG x\n( )\nx32\nx26\nx23\nx22\nx16\nx12\nx11\nx10\nx8\nx7\nx5\nx4\nx2\nx\n1\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n=\n\n\n<>\n\nRM0090 Rev 21\n1149/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\ntype (Ethernet Type field) and the IP header version, or when the received frame does not \nhave enough bytes, as indicated by the IPv4 header’s Length field (or when fewer than 20 \nbytes are available in an IPv4 or IPv6 header). The receive checksum offload also identifies \na TCP, UDP or ICMP payload in the received IP datagrams (IPv4 or IPv6) and calculates the \nchecksum of such payloads properly, as defined in the TCP, UDP or ICMP specifications. It \nincludes the TCP/UDP/ICMPv6 pseudo-header bytes for checksum calculation and checks \nwhether the received checksum field matches the calculated value. The result of this \noperation is given as a Payload Checksum Error bit in the receive status word. This status \nbit is also set if the length of the TCP, UDP or ICMP payload does not match the expected \npayload length given in the IP header. As mentioned in TCP/UDP/ICMP checksum, the \nreceive checksum offload bypasses the payload of fragmented IP datagrams, IP datagrams \nwith security features, IPv6 routing headers, and payloads other than TCP, UDP or ICMP. \nThis information (whether the checksum is bypassed or not) is given in the receive status, \nas described in the RDES0: Receive descriptor Word0 section. In this configuration, the \ncore does not append any payload checksum bytes to the received Ethernet frames.\nAs mentioned in RDES0: Receive descriptor Word0, the meaning of certain register bits \nchanges as shown in Table 191.\n \nReceive frame controller\nIf the RA bit is reset in the MAC CSR frame filter register, the MAC performs frame filtering \nbased on the destination/source address (the application still needs to perform another level \nof filtering if it decides not to receive any bad frames like runt, CRC error frames, etc.). On \ndetecting a filter-fail, the frame is dropped and not transferred to the application. When the \nfiltering parameters are changed dynamically, and in case of (DA-SA) filter-fail, the rest of \nthe frame is dropped and the Rx Status Word is immediately updated (with zero frame \nTable 191. Frame statuses\nBit 18: \nEthernet frame\nBit 27: Header \nchecksum error\n Bit 28: Payload \nchecksum error\nFrame status\n0\n0\n0\nThe frame is an IEEE 802.3 frame (Length \nfield value is less than 0x0600).\n1\n0\n0\nIPv4/IPv6 Type frame in which no checksum \nerror is detected.\n1\n0\n1\nIPv4/IPv6 Type frame in which a payload \nchecksum error (as described for PCE) is \ndetected\n1\n1\n0\nIPv4/IPv6 Type frame in which IP header \nchecksum error (as described for IPCO HCE) \nis detected.\n1\n1\n1\nIPv4/IPv6 Type frame in which both PCE and \nIPCO HCE are detected.\n0\n0\n1\nIPv4/IPv6 Type frame in which there is no IP \nHCE and the payload check is bypassed due \nto unsupported payload.\n0\n1\n1\nType frame which is neither IPv4 or IPv6 \n(checksum offload bypasses the checksum \ncheck completely)\n0\n1\n0\nReserved\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1150/1757\nRM0090 Rev 21\nlength, CRC error and Runt Error bits set), indicating the filter fail. In Ethernet power down \nmode, all received frames are dropped, and are not forwarded to the application.\nReceive flow control\nThe MAC detects the receiving Pause frame and pauses the frame transmission for the \ndelay specified within the received Pause frame (only in Full-duplex mode). The Pause \nframe detection function can be enabled or disabled with the RFCE bit in ETH_MACFCR. \nOnce receive flow control has been enabled, the received frame destination address begins \nto be monitored for any match with the multicast address of the control frame \n(0x0180 C200 0001). If a match is detected (the destination address of the received frame \nmatches the reserved control frame destination address), the MAC then decides whether or \nnot to transfer the received control frame to the application, based on the level of the PCF \nbit in ETH_MACFFR.\nThe MAC also decodes the type, opcode, and Pause Timer fields of the receiving control \nframe. If the byte count of the status indicates 64 bytes, and if there is no CRC error, the \nMAC transmitter pauses the transmission of any data frame for the duration of the decoded \nPause time value, multiplied by the slot time (64 byte times for both 10/100 Mbit/s modes). \nMeanwhile, if another Pause frame is detected with a zero Pause time value, the MAC \nresets the Pause time and manages this new pause request.\nIf the received control frame matches neither the type field (0x8808), the opcode (0x00001), \nnor the byte length (64 bytes), or if there is a CRC error, the MAC does not generate a \nPause.\nIn the case of a pause frame with a multicast destination address, the MAC filters the frame \nbased on the address match.\nFor a pause frame with a unicast destination address, the MAC filtering depends on whether \nthe DA matched the contents of the MAC address 0 register and whether the UPDF bit in \nETH_MACFCR is set (detecting a pause frame even with a unicast destination address). \nThe PCF register bits (bits [7:6] in ETH_MACFFR) control filtering for control frames in \naddition to address filtering.\nReceive operation multiframe handling\nSince the status is available immediately following the data, the FIFO is capable of storing \nany number of frames into it, as long as it is not full.\nError handling\nIf the Rx FIFO is full before it receives the EOF data from the MAC, an overflow is declared \nand the whole frame is dropped, and the overflow counter in the (ETH_DMAMFBOCR \nregister) is incremented. The status indicates a partial frame due to overflow. The Rx FIFO \ncan filter error and undersized frames, if enabled (using the FEF and FUGF bits in \nETH_DMAOMR).\nIf the Receive FIFO is configured to operate in Store-and-forward mode, all error frames can \nbe filtered and dropped.\nIn Cut-through mode, if a frame's status and length are available when that frame's SOF is \nread from the Rx FIFO, then the complete erroneous frame can be dropped. The DMA can \nflush the error frame being read from the FIFO, by enabling the receive frame flash bit. The \ndata transfer to the application (DMA) is then stopped and the rest of the frame is internally \nread and dropped. The next frame transfer can then be started, if available.\n\n\n<>\n\nRM0090 Rev 21\n1151/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nReceive status word\nAt the end of the Ethernet frame reception, the MAC outputs the receive status to the \napplication (DMA). The detailed description of the receive status is the same as for \nbits[31:0] in RDES0, given in RDES0: Receive descriptor Word0.\nFrame length interface\nIn case of switch applications, data transmission and reception between the application and \nMAC happen as complete frame transfers. The application layer should be aware of the \nlength of the frames received from the ingress port in order to transfer the frame to the \negress port. The MAC core provides the frame length of each received frame inside the \nstatus at the end of each frame reception.\nNote:\nA frame length value of 0 is given for partial frames written into the Rx FIFO due to overflow.\nMII/RMII receive bit order\nEach nibble is transmitted to the MII from the dibit received from the RMII in the nibble \ntransmission order shown in Figure 366. The lower-order bits (D0 and D1) are received first, \nfollowed by the higher-order bits (D2 and D3).\nFigure 366. Receive bit order\nD0\nD1\nD2\nD3\nLSB\nMII_RXD[3:0]\nMSB\nD0\nD1\nLSB\nMSB\nRMII_RXD[1:0]\nDi-bit stream\nNibble stream\nai15633\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1152/1757\nRM0090 Rev 21\nFigure 367. Reception with no error\nFigure 368. Reception with errors\nFigure 369. Reception with false carrier indication\n33.5.4 \nMAC interrupts\nInterrupts can be generated from the MAC core as a result of various events.\nThe ETH_MACSR register describes the events that can cause an interrupt from the MAC \ncore. You can prevent each event from asserting the interrupt by setting the corresponding \nmask bits in the Interrupt Mask register.\nMII_RX_CLK\nMII_RX_DV\nMII_RXD[3:0]\nPREAMBLE\nSFD\nMII_RX_ERR\nai15634\nFCS\nMII_RX_CLK\nMII_RX_DV\nMII_RXD[3:0]\nPREAMBLE\nSFD\nMII_RX_ERR\nai15635\nDA\nDA\nXX\nXX\nXX\nMII_RX_CLK\nMII_RX_DV\nMII_RXD[3:0]\nXX\nMII_RX_ERR\nai15636\n0E\nXX\nXX\nXX\nXX\nXX\nXX\nXX\n\n\n<>\n\nRM0090 Rev 21\n1153/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nThe interrupt register bits only indicate the block from which the event is reported. You have \nto read the corresponding status registers and other registers to clear the interrupt. For \nexample, bit 3 of the Interrupt register, set high, indicates that the Magic packet or Wake-on-\nLAN frame is received in Power-down mode. You must read the ETH_MACPMTCSR \nregister to clear this interrupt event.\nFigure 370. MAC core interrupt masking scheme\n33.5.5 \nMAC filtering\nAddress filtering\nAddress filtering checks the destination and source addresses on all received frames and \nthe address filtering status is reported accordingly. Address checking is based on different \nparameters (Frame filter register) chosen by the application. The filtered frame can also be \nidentified: multicast or broadcast frame.\nAddress filtering uses the station's physical (MAC) address and the Multicast Hash table for \naddress checking purposes.\nUnicast destination address filter\nThe MAC supports up to 4 MAC addresses for unicast perfect filtering. If perfect filtering is \nselected (HU bit in the Frame filter register is reset), the MAC compares all 48 bits of the \nreceived unicast address with the programmed MAC address for any match. Default \nMacAddr0 is always enabled, other addresses MacAddr1–MacAddr3 are selected with an \nindividual enable bit. Each byte of these other addresses (MacAddr1–MacAddr3) can be \nmasked during comparison with the corresponding received DA byte by setting the \ncorresponding Mask Byte Control bit in the register. This helps group address filtering for the \nDA. In Hash filtering mode (when HU bit is set), the MAC performs imperfect filtering for \nunicast addresses using a 64-bit Hash table. For hash filtering, the MAC uses the 6 upper \nCRC (see note 1 below) bits of the received destination address to index the content of the \nHash table. A value of 000000 selects bit 0 in the selected register, and a value of 111111 \nselects bit 63 in the Hash Table register. If the corresponding bit (indicated by the 6-bit CRC) \nis set to 1, the unicast frame is said to have passed the Hash filter; otherwise, the frame has \nfailed the Hash filter.\nNote:\nThis CRC is a 32-bit value coded by the following polynomial (for more details refer to \nSection 33.5.3):\nAND\nAND\nOR\nTSTI\nPMTI\nInterrupt\nTSTS\nPMTS\nPMTIM\nai15637\nTSTIM\nG x\n( )\nx32\nx26\nx23\nx22\nx16\nx12\nx11\nx10\nx8\nx7\nx5\nx4\nx2\nx\n1\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n=\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1154/1757\nRM0090 Rev 21\nMulticast destination address filter\nThe MAC can be programmed to pass all multicast frames by setting the PAM bit in the \nFrame filter register. If the PAM bit is reset, the MAC performs the filtering for multicast \naddresses based on the HM bit in the Frame filter register. In Perfect filtering mode, the \nmulticast address is compared with the programmed MAC destination address registers \n(1–3). Group address filtering is also supported. In Hash filtering mode, the MAC performs \nimperfect filtering using a 64-bit Hash table. For hash filtering, the MAC uses the 6 upper \nCRC (see note 1 below) bits of the received multicast address to index the content of the \nHash table. A value of 000000 selects bit 0 in the selected register and a value of 111111 \nselects bit 63 in the Hash Table register. If the corresponding bit is set to 1, then the \nmulticast frame is said to have passed the Hash filter; otherwise, the frame has failed the \nHash filter.\nNote:\nThis CRC is a 32-bit value coded by the following polynomial (for more details refer to \nSection 33.5.3):\nHash or perfect address filter\nThe DA filter can be configured to pass a frame when its DA matches either the Hash filter \nor the Perfect filter by setting the HPF bit in the Frame filter register and setting the \ncorresponding HU or HM bits. This configuration applies to both unicast and multicast \nframes. If the HPF bit is reset, only one of the filters (Hash or Perfect) is applied to the \nreceived frame.\nBroadcast address filter\nThe MAC does not filter any broadcast frames in the default mode. However, if the MAC is \nprogrammed to reject all broadcast frames by setting the BFD bit in the Frame filter register, \nany broadcast frames are dropped.\nUnicast source address filter\nThe MAC can also perform perfect filtering based on the source address field of the \nreceived frames. By default, the MAC compares the SA field with the values programmed in \nthe SA registers. The MAC address registers [1:3] can be configured to contain SA instead \nof DA for comparison, by setting bit 30 in the corresponding register. Group filtering with SA \nis also supported. The frames that fail the SA filter are dropped by the MAC if the SAF bit in \nthe Frame filter register is set. Otherwise, the result of the SA filter is given as a status bit in \nthe Receive Status word (see RDES0: Receive descriptor Word0).\nWhen the SAF bit is set, the result of the SA and DA filters is AND’ed to decide whether the \nframe needs to be forwarded. This means that either of the filter fail result drops the frame. \nBoth filters have to pass the frame for the frame to be forwarded to the application.\nInverse filtering operation\nFor both destination and source address filtering, there is an option to invert the filter-match \nresult at the final output. These are controlled by the DAIF and SAIF bits in the Frame filter \nregister, respectively. The DAIF bit is applicable for both Unicast and Multicast DA frames. \nThe result of the unicast/multicast destination address filter is inverted in this mode. \nSimilarly, when the SAIF bit is set, the result of the unicast SA filter is inverted. Table 192 \nG x\n( )\nx32\nx26\nx23\nx22\nx16\nx12\nx11\nx10\nx8\nx7\nx5\nx4\nx2\nx\n1\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n=\n\n\n<>\n\nRM0090 Rev 21\n1155/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nand Table 193 summarize destination and source address filtering based on the type of \nframe received.\n \nTable 192. Destination address filtering\nFrame \ntype\nPM\nHPF\nHU\nDAIF\nHM\nPAM\nDB\nDA filter operation\nBroadcast\n1\nX\nX\nX\nX\nX\nX\nPass\n0\nX\nX\nX\nX\nX\n0\nPass\n0\nX\nX\nX\nX\nX\n1\nFail\nUnicast\n1\nX\nX\nX\nX\nX\nX\nPass all frames\n0\nX\n0\n0\nX\nX\nX\nPass on perfect/group filter match\n0\nX\n0\n1\nX\nX\nX\nFail on perfect/Group filter match\n0\n0\n1\n0\nX\nX\nX\nPass on hash filter match\n0\n0\n1\n1\nX\nX\nX\nFail on hash filter match\n0\n1\n1\n0\nX\nX\nX\nPass on hash or perfect/Group filter \nmatch\n0\n1\n1\n1\nX\nX\nX\nFail on hash or perfect/Group filter match\nMulticast\n1\nX\nX\nX\nX\nX\nX\nPass all frames\nX\nX\nX\nX\nX\n1\nX\nPass all frames\n0\nX\nX\n0\n0\n0\nX\nPass on Perfect/Group filter match and \ndrop PAUSE control frames if PCF = 0x\n0\n0\nX\n0\n1\n0\nX\nPass on hash filter match and drop \nPAUSE control frames if PCF = 0x\n0\n1\nX\n0\n1\n0\nX\nPass on hash or perfect/Group filter \nmatch and drop PAUSE control frames if \nPCF = 0x\n0\nX\nX\n1\n0\n0\nX\nFail on perfect/Group filter match and \ndrop PAUSE control frames if PCF = 0x\n0\n0\nX\n1\n1\n0\nX\nFail on hash filter match and drop PAUSE \ncontrol frames if PCF = 0x\n0\n1\nX\n1\n1\n0\nX\nFail on hash or perfect/Group filter match \nand drop PAUSE control frames if PCF = \n0x\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1156/1757\nRM0090 Rev 21\n \n33.5.6 \nMAC loopback mode\nThe MAC supports loopback of transmitted frames onto its receiver. By default, the MAC \nloopback function is disabled, but this feature can be enabled by programming the \nLoopback bit in the MAC ETH_MACCR register.\n33.5.7 \nMAC management counters: MMC\nThe MAC management counters (MMC) maintain a set of registers for gathering statistics \non the received and transmitted frames. These include a control register for controlling the \nbehavior of the registers, two 32-bit registers containing generated interrupts (receive and \ntransmit), and two 32-bit registers containing masks for the Interrupt register (receive and \ntransmit). These registers are accessible from the application. Each register is 32 bits wide.\nSection 33.8 describes the various counters and lists the addresses of each of the statistics \ncounters. This address is used for read/write accesses to the desired transmit/receive \ncounter.\nThe Receive MMC counters are updated for frames that pass address filtering. Dropped \nframes statistics are not updated unless the dropped frames are runt frames of less than 6 \nbytes (DA bytes are not received fully).\nGood transmitted and received frames\nTransmitted frames are considered “good” if transmitted successfully. In other words, a \ntransmitted frame is good if the frame transmission is not aborted due to any of the following \nerrors:\n+ Jabber Timeout\n+ No Carrier/Loss of Carrier \n+ Late Collision\n+ Frame Underflow\n+ Excessive Deferral\n+ Excessive Collision\nTable 193. Source address filtering\nFrame type\nPM\nSAIF\nSAF\nSA filter operation\nUnicast\n1\nX\nX\nPass all frames\n0\n0\n0\nPass status on perfect/Group filter match but do not drop \nframes that fail\n0\n1\n0\nFail status on perfect/group filter match but do not drop frame\n0\n0\n1\nPass on perfect/group filter match and drop frames that fail\n0\n1\n1\nFail on perfect/group filter match and drop frames that fail\n\n\n<>\n\nRM0090 Rev 21\n1157/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nReceived frames are considered “good” if none of the following errors exists:\n+ CRC error\n+ Runt Frame (shorter than 64 bytes)\n+ Alignment error (in 10/ 100 Mbit/s only)\n+ Length error (non-Type frames only)\n+ Out of Range (non-Type frames only, longer than maximum size)\n+ MII_RXER Input error\nThe maximum frame size depends on the frame type, as follows:\n+ Untagged frame maxsize = 1518 \n+ VLAN Frame maxsize = 1522\n33.5.8 \nPower management: PMT\nThis section describes the power management (PMT) mechanisms supported by the MAC. \nPMT supports the reception of network (remote) wake-up frames and Magic Packet frames. \nPMT generates interrupts for wake-up frames and Magic Packets received by the MAC. The \nPMT block is enabled with remote wake-up frame enable and Magic Packet enable. These \nenable bits (WFE and MPE) are in the ETH_MACPMTCSR register and are programmed by \nthe application. When the power down mode is enabled in the PMT, then all received frames \nare dropped by the MAC and they are not forwarded to the application. The MAC comes out \nof the power down mode only when either a Magic Packet or a Remote wake-up frame is \nreceived and the corresponding detection is enabled.\nRemote wake-up frame filter register\nThere are eight wake-up frame filter registers. To write on each of them, load the wake-up \nframe filter register value by value. The wanted values of the wake-up frame filter are loaded \nby sequentially loading eight times the wake-up frame filter register. The read operation is \nidentical to the write operation. To read the eight values, you have to read eight times the \nwake-up frame filter register to reach the last register. Each read/write points the wake-up \nframe filter register to the next filter register.\nFigure 371. Wake-up frame filter register\nFilter 0 Byte Mask\nFilter 1 Byte Mask\nFilter 2 Byte Mask\nFilter 3 Byte Mask\nRSVD\nFilter 3\nCommand\nRSVD\nFilter 2\nCommand\nRSVD\nFilter 1\nCommand\nRSVD\nFilter 0\nCommand\nFilter 3 Offset\nFilter 2 Offset\nFilter 1 Offset\nFilter 0 Offset\nFilter 1 CRC - 16\nFilter 0 CRC - 16\nFilter 3 CRC - 16\nFilter 2 CRC - 16\nWakeup frame filter reg0\nWakeup frame filter reg1\nWakeup frame filter reg2\nWakeup frame filter reg3\nWakeup frame filter reg4\nWakeup frame filter reg5\nWakeup frame filter reg6\nWakeup frame filter reg7\nai15647\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1158/1757\nRM0090 Rev 21\n•\nFilter i Byte Mask\nThis register defines which bytes of the frame are examined by filter i (0, 1, 2, and 3) in \norder to determine whether or not the frame is a wake-up frame. The MSB (thirty-first \nbit) must be zero. Bit j [30:0] is the Byte Mask. If bit j (byte number) of the Byte Mask is \nset, then Filter i Offset + j of the incoming frame is processed by the CRC block; \notherwise Filter i Offset + j is ignored.\n•\nFilter i Command\nThis 4-bit command controls the filter i operation. Bit 3 specifies the address type, \ndefining the pattern’s destination address type. When the bit is set, the pattern applies \nto only multicast frames. When the bit is reset, the pattern applies only to unicast \nframes. Bit 2 and bit 1 are reserved. Bit 0 is the enable bit for filter i; if bit 0 is not set, \nfilter i is disabled.\n•\nFilter i Offset\nThis register defines the offset (within the frame) from which the frames are examined \nby filter i. This 8-bit pattern offset is the offset for the filter i first byte to be examined. \nThe minimum allowed is 12, which refers to the 13th byte of the frame (offset value 0 \nrefers to the first byte of the frame).\n•\nFilter i CRC-16\nThis register contains the CRC_16 value calculated from the pattern, as well as the \nbyte mask programmed to the wake-up filter register block.\nRemote wake-up frame detection\nWhen the MAC is in sleep mode and the remote wake-up bit is enabled in the \nETH_MACPMTCSR register, normal operation is resumed after receiving a remote wake-up \nframe. The application writes all eight wake-up filter registers, by performing a sequential \nwrite to the wake-up frame filter register address. The application enables remote wake-up \nby writing a 1 to bit 2 in the ETH_MACPMTCSR register. PMT supports four programmable \nfilters that provide different receive frame patterns. If the incoming frame passes the \naddress filtering of Filter Command, and if Filter CRC-16 matches the incoming examined \npattern, then the wake-up frame is received. Filter_offset (minimum value 12, which refers to \nthe 13th byte of the frame) determines the offset from which the frame is to be examined. \nFilter Byte Mask determines which bytes of the frame must be examined. The thirty-first bit \nof Byte Mask must be set to zero. The wake-up frame is checked only for length error, FCS \nerror, dribble bit error, MII error, collision, and to ensure that it is not a runt frame. Even if the \nwake-up frame is more than 512 bytes long, if the frame has a valid CRC value, it is \nconsidered valid. Wake-up frame detection is updated in the ETH_MACPMTCSR register \nfor every remote wake-up frame received. If enabled, a PMT interrupt is generated to \nindicate the reception of a remote wake-up frame.\nMagic packet detection\nThe Magic Packet frame is based on a method that uses Advanced Micro Device’s Magic \nPacket technology to power up the sleeping device on the network. The MAC receives a \nspecific packet of information, called a Magic Packet, addressed to the node on the network. \nOnly Magic Packets that are addressed to the device or a broadcast address are checked to \ndetermine whether they meet the wake-up requirements. Magic Packets that pass address \nfiltering (unicast or broadcast) are checked to determine whether they meet the remote \nWake-on-LAN data format of 6 bytes of all ones followed by a MAC address appearing 16 \ntimes. The application enables Magic Packet wake-up by writing a 1 to bit 1 in the \nETH_MACPMTCSR register. The PMT block constantly monitors each frame addressed to \n\n\n<>\n\nRM0090 Rev 21\n1159/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nthe node for a specific Magic Packet pattern. Each received frame is checked for a \n0xFFFF FFFF FFFF pattern following the destination and source address field. The PMT \nblock then checks the frame for 16 repetitions of the MAC address without any breaks or \ninterruptions. In case of a break in the 16 repetitions of the address, the 0xFFFF FFFF FFFF \npattern is scanned for again in the incoming frame. The 16 repetitions can be anywhere in \nthe frame, but must be preceded by the synchronization stream (0xFFFF FFFF FFFF). The \ndevice also accepts a multicast frame, as long as the 16 duplications of the MAC address \nare detected. If the MAC address of a node is 0x0011 2233 4455, then the MAC scans for \nthe data sequence:\nDestination address source address ……………….. FFFF FFFF FFFF\n0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455\n0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455\n0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455\n0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455\n …CRC\nMagic Packet detection is updated in the ETH_MACPMTCSR register for received Magic \nPacket. If enabled, a PMT interrupt is generated to indicate the reception of a Magic Packet.\nSystem consideration during power-down\nThe Ethernet PMT block is able to detect frames while the system is in the Stop mode, \nprovided that the EXTI line 19 is enabled.\nThe MAC receiver state machine should remain enabled during the power-down mode. This \nmeans that the RE bit has to remain set in the ETH_MACCR register because it is involved \nin magic packet/ wake-on-LAN frame detection. The transmit state machine should however \nbe turned off during the power-down mode by clearing the TE bit in the ETH_MACCR \nregister. Moreover, the Ethernet DMA should be disabled during the power-down mode, \nbecause it is not necessary to copy the magic packet/wake-on-LAN frame into the SRAM. \nTo disable the Ethernet DMA, clear the ST bit and the SR bit (for the transmit DMA and the \nreceive DMA, respectively) in the ETH_DMAOMR register.\nThe recommended power-down and wake-up sequences are as follows:\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1160/1757\nRM0090 Rev 21\n1.\nDisable the transmit DMA and wait for any previous frame transmissions to complete. \nThese transmissions can be detected when the transmit interrupt ETH_DMASR \nregister[0] is received.\n2. \nDisable the MAC transmitter and MAC receiver by clearing the RE and TE bits in the \nETH_MACCR configuration register.\n3. \nWait for the receive DMA to have emptied all the frames in the Rx FIFO.\n4. \nDisable the receive DMA.\n5. \nConfigure and enable the EXTI line 19 to generate either an event or an interrupt.\n6. \nIf you configure the EXTI line 19 to generate an interrupt, you also have to correctly \nconfigure the ETH_WKUP_IRQ Handler function, which should clear the pending bit of \nthe EXTI line 19.\n7. \nEnable Magic packet/Wake-on-LAN frame detection by setting the MFE/ WFE bit in the \nETH_MACPMTCSR register.\n8. \nEnable the MAC power-down mode, by setting the PD bit in the ETH_MACPMTCSR \nregister.\n9. \nEnable the MAC Receiver by setting the RE bit in the ETH_MACCR register.\n10. Enter the system’s Stop mode (for more details refer to Section 4.3.4: Stop mode):\n11. On receiving a valid wake-up frame, the Ethernet peripheral exits the power-down \nmode.\n12. Read the ETH_MACPMTCSR to clear the power management event flag, enable the \nMAC transmitter state machine, and the receive and transmit DMA.\n13. Configure the system clock: enable the HSE and set the clocks.\n33.5.9 \nPrecision time protocol (IEEE1588 PTP)\nThe IEEE 1588 standard defines a protocol that allows precise clock synchronization in \nmeasurement and control systems implemented with technologies such as network \ncommunication, local computing and distributed objects. The protocol applies to systems \nthat communicate by local area networks supporting multicast messaging, including (but not \nlimited to) Ethernet. This protocol is used to synchronize heterogeneous systems that \ninclude clocks of varying inherent precision, resolution and stability. The protocol supports \nsystem-wide synchronization accuracy in the submicrosecond range with minimum network \nand local clock computing resources. The message-based protocol, known as the precision \ntime protocol (PTP), is transported over UDP/IP. The system or network is classified into \nMaster and Slave nodes for distributing the timing/clock information. The protocol’s \ntechnique for synchronizing a slave node to a master node by exchanging PTP messages is \ndescribed in Figure 372.\n\n\n<>\n\nRM0090 Rev 21\n1161/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nFigure 372. Networked time synchronization\n1.\nThe master broadcasts PTP Sync messages to all its nodes. The Sync message \ncontains the master’s reference time information. The time at which this message \nleaves the master’s system is t1. For Ethernet ports, this time has to be captured at the \nMII.\n2. \nA slave receives the Sync message and also captures the exact time, t2, using its \ntiming reference.\n3. \nThe master then sends the slave a Follow_up message, which contains the t1 \ninformation for later use.\n4. \nThe slave sends the master a Delay_Req message, noting the exact time, t3, at which \nthis frame leaves the MII.\n5. \nThe master receives this message and captures the exact time, t4, at which it enters its \nsystem.\n6. \nThe master sends the t4 information to the slave in the Delay_Resp message.\n7. \nThe slave uses the four values of t1, t2, t3, and t4 to synchronize its local timing \nreference to the master’s timing reference.\nMost of the protocol implementation occurs in the software, above the UDP layer. As \ndescribed above, however, hardware support is required to capture the exact time when \nspecific PTP packets enter or leave the Ethernet port at the MII. This timing information has \nto be captured and returned to the software for a proper, high-accuracy implementation of \nPTP.\nReference timing source\nTo get a snapshot of the time, the core requires a reference time in 64-bit format (split into \ntwo 32-bit channels, with the upper 32 bits providing time in seconds, and the lower 32 bits \nindicating time in nanoseconds) as defined in the IEEE 1588 specification.\nThe PTP reference clock input is used to internally generate the reference time (also called \nthe System Time) and to capture time stamps. The frequency of this reference clock must \nMaster clock time\nSlave clock time\nData at\nslave clock\nSync message\nFollow_up message\ncontaining value of t1\nDelay_Req message\nDelay_Resp message\ncontaining value of t4\ntime\nt1\nt2m\nt3m\nt4\nt1, t2, t3, t4\nt2\nt1, t2\nt3\nt2\nt1, t2, t3\nai15669\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1162/1757\nRM0090 Rev 21\nbe greater than or equal to the resolution of time stamp counter. The synchronization \naccuracy target between the master node and the slaves is around 100 ns.\nThe generation, update and modification of the System Time are described in System Time \ncorrection methods.\nThe accuracy depends on the PTP reference clock input period, the characteristics of the \noscillator (drift) and the frequency of the synchronization procedure.\nDue to the synchronization from the Tx and Rx clock input domain to the PTP reference \nclock domain, the uncertainty on the time stamp latched value is 1 reference clock period. If \nwe add the uncertainty due to resolution, we add half the period for time stamping.\nTransmission of frames with the PTP feature\nWhen a frame’s SFD is output on the MII, a time stamp is captured. Frames for which time \nstamp capture is required are controllable on a per-frame basis. In other words, each \ntransmitted frame can be marked to indicate whether a time stamp must be captured or not \nfor that frame. The transmitted frames are not processed to identify PTP frames. Frame \ncontrol is exercised through the control bits in the transmit descriptor. Captured time stamps \nare returned to the application in the same way as the status is provided for frames. The \ntime stamp is sent back along with the Transmit status of the frame, inside the \ncorresponding transmit descriptor, thus connecting the time stamp automatically to the \nspecific PTP frame. The 64-bit time stamp information is written back to the TDES2 and \nTDES3 fields, with TDES2 holding the time stamp’s 32 least significant bits.\nReception of frames with the PTP feature\nWhen the IEEE 1588 time stamping feature is enabled, the Ethernet MAC captures the time \nstamp of all frames received on the MII. The MAC provides the time stamp as soon as the \nframe reception is complete. Captured time stamps are returned to the application in the \nsame way as the frame status is provided. The time stamp is sent back along with the \nReceive status of the frame, inside the corresponding receive descriptor. The 64-bit time \nstamp information is written back to the RDES2 and RDES3 fields, with RDES2 holding the \ntime stamp’s 32 least significant bits.\nSystem Time correction methods\nThe 64-bit PTP time is updated using the PTP input reference clock, HCLK. This PTP time \nis used as a source to take snapshots (time stamps) of the Ethernet frames being \ntransmitted or received at the MII. The System Time counter can be initialized or corrected \nusing either the Coarse or the Fine correction method.\nIn the Coarse correction method, the initial value or the offset value is written to the Time \nstamp update register (refer to Section 33.8.3). For initialization, the System Time counter is \nwritten with the value in the Time stamp update registers, whereas for system time \ncorrection, the offset value (Time stamp update register) is added to or subtracted from the \nsystem time.\nIn the Fine correction method, the slave clock (reference clock) frequency drift with respect \nto the master clock (as defined in IEEE 1588) is corrected over a period of time, unlike in the \nCoarse correction method where it is corrected in a single clock cycle. The longer correction \ntime helps maintain linear time and does not introduce drastic changes (or a large jitter) in \nthe reference time between PTP Sync message intervals. In this method, an accumulator \nsums up the contents of the Addend register as shown in Figure 373. The arithmetic carry \nthat the accumulator generates is used as a pulse to increment the system time counter. \n\n\n<>\n\nRM0090 Rev 21\n1163/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nThe accumulator and the addend are 32-bit registers. Here, the accumulator acts as a high-\nprecision frequency multiplier or divider. Figure 373 shows this algorithm.\nFigure 373. System time update using the Fine correction method\nThe system time update logic requires a 50 MHz clock frequency to achieve 20 ns accuracy. \nThe frequency division is the ratio of the reference clock frequency to the required clock \nfrequency. Hence, if the reference clock (HCLK) is, let us say, 66 MHz, the ratio is calculated \nas 66 MHz/50 MHz = 1.32. Hence, the default addend value to be set in the register is \n232/1.32, which is equal to 0xC1F0 7C1F.\nIf the reference clock drifts lower, to 65 MHz for example, the ratio is 65/50 or 1.3 and the \nvalue to set in the addend register is 232/1.30 equal to 0xC4EC 4EC4. If the clock drifts \nhigher, to 67 MHz for example, the addend register must be set to 0xBF0 B7672. When the \nclock drift is zero, the default addend value of 0xC1F0 7C1F (232/1.32) should be \nprogrammed.\nIn Figure 373, the constant value used to increment the subsecond register is 0d43. This \nmakes an accuracy of 20 ns in the system time (in other words, it is incremented by 20 ns \nsteps).\nThe software has to calculate the drift in frequency based on the Sync messages, and to \nupdate the Addend register accordingly. Initially, the slave clock is set with \nFreqCompensationValue0 in the Addend register. This value is as follows:\nFreqCompensationValue0 = 232 / FreqDivisionRatio\nIf MasterToSlaveDelay is initially assumed to be the same for consecutive Sync messages, \nthe algorithm described below must be applied. After a few Sync cycles, frequency lock \noccurs. The slave clock can then determine a precise MasterToSlaveDelay value and re-\nsynchronize with the master using the new value.\nAddend register\n+\nAccumulator register\nSubsecond register\n+\nConstant value\nSecond register\nIncrement Second register\nAddend update\nai15670\nIncrement Subsecond\nregister\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1164/1757\nRM0090 Rev 21\nThe algorithm is as follows:\n•\nAt time MasterSyncTime (n) the master sends the slave clock a Sync message. The \nslave receives this message when its local clock is SlaveClockTime (n) and computes \nMasterClockTime (n) as:\nMasterClockTime (n) = MasterSyncTime (n) + MasterToSlaveDelay (n)\n•\nThe master clock count for current Sync cycle, MasterClockCount (n) is given by:\nMasterClockCount (n) = MasterClockTime (n) – MasterClockTime (n – 1) (assuming \nthat MasterToSlaveDelay is the same for Sync cycles n and n – 1)\n•\nThe slave clock count for current Sync cycle, SlaveClockCount (n) is given by:\nSlaveClockCount (n) = SlaveClockTime (n) – SlaveClockTime (n – 1)\n•\nThe difference between master and slave clock counts for current Sync cycle, \nClockDiffCount (n) is given by:\nClockDiffCount (n) = MasterClockCount (n) – SlaveClockCount (n)\n•\nThe frequency-scaling factor for slave clock, FreqScaleFactor (n) is given by:\nFreqScaleFactor (n) = (MasterClockCount (n) + ClockDiffCount (n)) / \nSlaveClockCount (n)\n•\nThe frequency compensation value for Addend register, FreqCompensationValue (n) is \ngiven by:\nFreqCompensationValue (n) = FreqScaleFactor (n) × FreqCompensationValue (n – 1)\nIn theory, this algorithm achieves lock in one Sync cycle; however, it may take several \ncycles, due to changing network propagation delays and operating conditions.\nThis algorithm is self-correcting: if for any reason the slave clock is initially set to a value \nfrom the master that is incorrect, the algorithm corrects it at the cost of more Sync cycles.\nProgramming steps for system time generation initialization\nThe time stamping feature can be enabled by setting bit 0 in the Time stamp control register \n(ETH__PTPTSCR). However, it is essential to initialize the time stamp counter after this bit \nis set to start time stamp operation. The proper sequence is the following:\n1.\nMask the Time stamp trigger interrupt by setting bit 9 in the MACIMR register.\n2. \nProgram Time stamp register bit 0 to enable time stamping.\n3. \nProgram the Subsecond increment register based on the PTP clock frequency.\n4. \nIf you are using the Fine correction method, program the Time stamp addend register \nand set Time stamp control register bit 5 (addend register update).\n5. \nPoll the Time stamp control register until bit 5 is cleared.\n6. \nTo select the Fine correction method (if required), program Time stamp control register \nbit 1.\n7. \nProgram the Time stamp high update and Time stamp low update registers with the \nappropriate time value.\n8. \nSet Time stamp control register bit 2 (Time stamp init).\n9. \nThe Time stamp counter starts operation as soon as it is initialized with the value \nwritten in the Time stamp update register.\n10. Enable the MAC receiver and transmitter for proper time stamping.\nNote:\nIf time stamp operation is disabled by clearing bit 0 in the ETH_PTPTSCR register, the \nabove steps must be repeated to restart the time stamp operation.\n\n\n<>\n\nRM0090 Rev 21\n1165/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nProgramming steps for system time update in the Coarse correction method\nTo synchronize or update the system time in one process (coarse correction method), \nperform the following steps: \n1.\nWrite the offset (positive or negative) in the Time stamp update high and low registers. \n2. \nSet bit 3 (TSSTU) in the Time stamp control register.\n3. \nThe value in the Time stamp update registers is added to or subtracted from the system \ntime when the TSSTU bit is cleared.\nProgramming steps for system time update in the Fine correction method\nTo synchronize or update the system time to reduce system-time jitter (fine correction \nmethod), perform the following steps:\n1.\nWith the help of the algorithm explained in System Time correction methods, calculate \nthe rate by which you want to speed up or slow down the system time increments.\n2. \nUpdate the time stamp.\n3. \nWait the time you want the new value of the Addend register to be active. You can do \nthis by activating the Time stamp trigger interrupt after the system time reaches the \ntarget value.\n4. \nProgram the required target time in the Target time high and low registers. Unmask the \nTime stamp interrupt by clearing bit 9 in the ETH_MACIMR register.\n5. \nSet Time stamp control register bit 4 (TSARU).\n6. \nWhen this trigger causes an interrupt, read the ETH_MACSR register.\n7. \nReprogram the Time stamp addend register with the old value and set ETH_TPTSCR \nbit 5 again.\nPTP trigger internal connection with TIM2\nThe MAC provides a trigger interrupt when the system time becomes greater than the target \ntime. Using an interrupt introduces a known latency plus an uncertainty in the command \nexecution time.\nIn order to avoid this uncertainty, a PTP trigger output signal is set high when the system \ntime is greater than the target time. It is internally connected to the TIM2 input trigger. With \nthis signal, the input capture feature, the output compare feature and the waveforms of the \ntimer can be used, triggered by the synchronized PTP system time. No uncertainty is \nintroduced since the clock of the timer (PCLK1: TIM2 APB1 clock) and PTP reference clock \n(HCLK) are synchronous.\nThis PTP trigger signal is connected to the TIM2 ITR1 input selectable by software. The \nconnection is enabled through bits 11 and 10 in the TIM2 option register (TIM2_OR). \nFigure 374 shows the connection.\nFigure 374. PTP trigger output to TIM2 ITR1 connection\nEthernet MAC\nai15671\nTIM2\nITR1\nPTP trigger\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1166/1757\nRM0090 Rev 21\nPTP pulse-per-second output signal\nThis PTP pulse output is used to check the synchronization between all nodes in the \nnetwork. To be able to test the difference between the local slave clock and the master \nreference clock, both clocks were given a pulse-per-second (PPS) output signal that may be \nconnected to an oscilloscope if necessary. The deviation between the two signals can \ntherefore be measured. The pulse width of the PPS output is 125 ms.\nThe PPS output is enabled through a GPIO alternate function. (GPIO_AFR register).\nThe default frequency of the PPS output is 1 Hz. PPSFREQ[3:0] (in ETH_PTPPPSCR) can \nbe used to set the frequency of the PPS output to 2PPSFREQ Hz.\nWhen set to 1 Hz, the PPS pulse width is 125 ms with binary rollover (TSSSR=0, bit 9 in \nETH_PTPTSCR) and 100 ms with digital rollover (TSSSR=1). When set to 2 Hz and higher, \nthe duty cycle of the PPS output is 50% with binary rollover.\nWith digital rollover (TSSSR=1), it is recommended not to use the PPS output with a \nfrequency other than 1 Hz as it would have irregular waveforms (though its average \nfrequency would always be correct during any one-second window).\nFigure 375. PPS output\n33.6 \nEthernet functional description: DMA controller operation\nThe DMA has independent transmit and receive engines, and a CSR space. The transmit \nengine transfers data from system memory into the Tx FIFO while the receive engine \ntransfers data from the Rx FIFO into system memory. The controller utilizes descriptors to \nefficiently move data from source to destination with minimum CPU intervention. The DMA \nis designed for packet-oriented data transfers such as frames in Ethernet. The controller can \nbe programmed to interrupt the CPU in cases such as frame transmit and receive transfer \ncompletion, and other normal/error conditions. The DMA and the STM32F4xx communicate \nthrough two data structures:\n•\nControl and status registers (CSR)\n•\nDescriptor lists and data buffers.\nControl and status registers are described in detail in Section 33.8. Descriptors are \ndescribed in detail in Normal Tx DMA descriptors.\nThe DMA transfers the received data frames to the receive buffer in the STM32F4xx \nmemory, and transmits data frames from the transmit buffer in the STM32F4xx memory. \nDescriptors that reside in the STM32F4xx memory act as pointers to these buffers. There \nare two descriptor lists: one for reception, and one for transmission. The base address of \neach list is written into DMA registers 3 and 4, respectively. A descriptor list is forward-linked \n(either implicitly or explicitly). The last descriptor may point back to the first entry to create a \nring structure. Explicit chaining of descriptors is accomplished by configuring the second \naddress chained in both the receive and transmit descriptors (RDES1[14] and TDES0[20]). \nThe descriptor lists reside in the Host’s physical memory space. Each descriptor can point to \na maximum of two buffers. This enables the use of two physically addressed buffers, \nEthernet MAC\nai15672\nPPS output\n\n\n<>\n\nRM0090 Rev 21\n1167/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\ninstead of two contiguous buffers in memory. A data buffer resides in the Host’s physical \nmemory space, and consists of an entire frame or part of a frame, but cannot exceed a \nsingle frame. Buffers contain only data. The buffer status is maintained in the descriptor. \nData chaining refers to frames that span multiple data buffers. However, a single descriptor \ncannot span multiple frames. The DMA skips to the next frame buffer when the end of frame \nis detected. Data chaining can be enabled or disabled. The descriptor ring and chain \nstructure is shown in Figure 376.\nFigure 376. Descriptor ring and chain structure\n33.6.1 \nInitialization of a transfer using DMA\nInitialization for the MAC is as follows:\n1.\nWrite to ETH_DMABMR to set STM32F4xx bus access parameters.\n2. \nWrite to the ETH_DMAIER register to mask unnecessary interrupt causes.\n3. \nThe software driver creates the transmit and receive descriptor lists. Then it writes to \nboth the ETH_DMARDLAR and ETH_DMATDLAR registers, providing the DMA with \nthe start address of each list.\n4. \nWrite to MAC registers 1, 2, and 3 to choose the desired filtering options.\n5. \nWrite to the MAC ETH_MACCR register to configure and enable the transmit and \nreceive operating modes. The PS and DM bits are set based on the auto-negotiation \nresult (read from the PHY).\n6. \nWrite to the ETH_DMAOMR register to set bits 13 and 1 and start transmission and \nreception.\n7. \nThe transmit and receive engines enter the running state and attempt to acquire \ndescriptors from the respective descriptor lists. The receive and transmit engines then \nbegin processing receive and transmit operations. The transmit and receive processes \nare independent of each other and can be started or stopped separately.\n33.6.2 \nHost bus burst access\nThe DMA attempts to execute fixed-length burst transfers on the AHB master interface if \nconfigured to do so (FB bit in ETH_DMABMR). The maximum burst length is indicated and \nlimited by the PBL field (ETH_DMABMR [13:8]). The receive and transmit descriptors are \nDescriptor 0\nai15638\nDescriptor 1\nDescriptor 2\nDescriptor n\nBuffer 1\nBuffer 2\nBuffer 1\nBuffer 2\nBuffer 1\nBuffer 2\nBuffer 1\nBuffer 2\nRing structure\nChain structure\nDescriptor 0\nDescriptor 1\nDescriptor 2\nBuffer 1\nBuffer 1\nBuffer 1\nNext descriptor\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1168/1757\nRM0090 Rev 21\nalways accessed in the maximum possible burst size (limited by PBL) for the 16 bytes to be \nread.\nThe Transmit DMA initiates a data transfer only when there is sufficient space in the \nTransmit FIFO to accommodate the configured burst or the number of bytes until the end of \nframe (when it is less than the configured burst length). The DMA indicates the start address \nand the number of transfers required to the AHB Master Interface. When the AHB Interface \nis configured for fixed-length burst, then it transfers data using the best combination of \nINCR4, INCR8, INCR16 and SINGLE transactions. Otherwise (no fixed-length burst), it \ntransfers data using INCR (undefined length) and SINGLE transactions.\nThe Receive DMA initiates a data transfer only when sufficient data for the configured burst \nis available in Receive FIFO or when the end of frame (when it is less than the configured \nburst length) is detected in the Receive FIFO. The DMA indicates the start address and the \nnumber of transfers required to the AHB master interface. When the AHB interface is \nconfigured for fixed-length burst, then it transfers data using the best combination of INCR4, \nINCR8, INCR16 and SINGLE transactions. If the end of frame is reached before the fixed-\nburst ends on the AHB interface, then dummy transfers are performed in order to complete \nthe fixed-length burst. Otherwise (FB bit in ETH_DMABMR is reset), it transfers data using \nINCR (undefined length) and SINGLE transactions.\nWhen the AHB interface is configured for address-aligned beats, both DMA engines ensure \nthat the first burst transfer the AHB initiates is less than or equal to the size of the configured \nPBL. Thus, all subsequent beats start at an address that is aligned to the configured PBL. \nThe DMA can only align the address for beats up to size 16 (for PBL > 16), because the \nAHB interface does not support more than INCR16.\n33.6.3 \nHost data buffer alignment\nThe transmit and receive data buffers do not have any restrictions on start address \nalignment. In our system with 32-bit memory, the start address for the buffers can be aligned \nto any of the four bytes. However, the DMA always initiates transfers with address aligned to \nthe bus width with dummy data for the byte lanes not required. This typically happens during \nthe transfer of the beginning or end of an Ethernet frame.\n•\nExample of buffer read:\nIf the Transmit buffer address is 0x0000 0FF2, and 15 bytes need to be transferred, \nthen the DMA reads five full words from address 0x0000 0FF0, but when transferring \ndata to the Transmit FIFO, the extra bytes (the first two bytes) are dropped or ignored. \nSimilarly, the last 3 bytes of the last transfer are also ignored. The DMA always ensures \nit transfers a full 32-bit data items to the Transmit FIFO, unless it is the end of frame.\n•\nExample of buffer write:\nIf the Receive buffer address is 0x0000 0FF2, and 16 bytes of a received frame need to \nbe transferred, then the DMA writes five full 32-bit data items from address \n0x0000 0FF0. But the first 2 bytes of the first transfer and the last 2 bytes of the third \ntransfer have dummy data.\n33.6.4 \nBuffer size calculations\nThe DMA does not update the size fields in the transmit and receive descriptors. The DMA \nupdates only the status fields (xDES0) of the descriptors. The driver has to calculate the \nsizes. The transmit DMA transfers the exact number of bytes (indicated by buffer size field in \nTDES1) towards the MAC core. If a descriptor is marked as first (FS bit in TDES0 is set), \nthen the DMA marks the first transfer from the buffer as the start of frame. If a descriptor is \n\n\n<>\n\nRM0090 Rev 21\n1169/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nmarked as last (LS bit in TDES0), then the DMA marks the last transfer from that data buffer \nas the end of frame. The receive DMA transfers data to a buffer until the buffer is full or the \nend of frame is received. If a descriptor is not marked as last (LS bit in RDES0), then the \nbuffer(s) that correspond to the descriptor are full and the amount of valid data in a buffer is \naccurately indicated by the buffer size field minus the data buffer pointer offset when the \ndescriptor’s FS bit is set. The offset is zero when the data buffer pointer is aligned to the \ndatabus width. If a descriptor is marked as last, then the buffer may not be full (as indicated \nby the buffer size in RDES1). To compute the amount of valid data in this final buffer, the \ndriver must read the frame length (FL bits in RDES0[29:16]) and subtract the sum of the \nbuffer sizes of the preceding buffers in this frame. The receive DMA always transfers the \nstart of next frame with a new descriptor.\nNote:\nEven when the start address of a receive buffer is not aligned to the system databus width \nthe system should allocate a receive buffer of a size aligned to the system bus width. For \nexample, if the system allocates a 1024 byte (1 KB) receive buffer starting from address \n0x1000, the software can program the buffer start address in the receive descriptor to have \na 0x1002 offset. The receive DMA writes the frame to this buffer with dummy data in the first \ntwo locations (0x1000 and 0x1001). The actual frame is written from location 0x1002. Thus, \nthe actual useful space in this buffer is 1022 bytes, even though the buffer size is \nprogrammed as 1024 bytes, due to the start address offset.\n33.6.5 \nDMA arbiter\nThe arbiter inside the DMA takes care of the arbitration between transmit and receive \nchannel accesses to the AHB master interface. Two types of arbitrations are possible: \nround-robin, and fixed-priority. When round-robin arbitration is selected (DA bit in \nETH_DMABMR is reset), the arbiter allocates the databus in the ratio set by the PM bits in \nETH_DMABMR, when both transmit and receive DMAs request access simultaneously. \nWhen the DA bit is set, the receive DMA always gets priority over the transmit DMA for data \naccess.\n33.6.6 \nError response to DMA\nFor any data transfer initiated by a DMA channel, if the slave replies with an error response, \nthat DMA stops all operations and updates the error bits and the fatal bus error bit in the \nStatus register (ETH_DMASR register). That DMA controller can resume operation only \nafter soft- or hard-resetting the peripheral and re-initializing the DMA.\n33.6.7 \nTx DMA configuration\nTxDMA operation: default (non-OSF) mode\nThe transmit DMA engine in default mode proceeds as follows:\n1.\nThe user sets up the transmit descriptor (TDES0-TDES3) and sets the OWN bit \n(TDES0[31]) after setting up the corresponding data buffer(s) with Ethernet frame data.\n2. \nOnce the ST bit (ETH_DMAOMR register[13]) is set, the DMA enters the Run state.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1170/1757\nRM0090 Rev 21\n3. \nWhile in the Run state, the DMA polls the transmit descriptor list for frames requiring \ntransmission. After polling starts, it continues in either sequential descriptor ring order \nor chained order. If the DMA detects a descriptor flagged as owned by the CPU, or if an \nerror condition occurs, transmission is suspended and both the Transmit buffer \nUnavailable (ETH_DMASR register[2]) and Normal Interrupt Summary (ETH_DMASR \nregister[16]) bits are set. The transmit engine proceeds to Step 9.\n4. \nIf the acquired descriptor is flagged as owned by DMA (TDES0[31] is set), the DMA \ndecodes the transmit data buffer address from the acquired descriptor.\n5. \nThe DMA fetches the transmit data from the STM32F4xx memory and transfers the \ndata.\n6. \nIf an Ethernet frame is stored over data buffers in multiple descriptors, the DMA closes \nthe intermediate descriptor and fetches the next descriptor. Steps 3, 4, and 5 are \nrepeated until the end of Ethernet frame data is transferred.\n7. \nWhen frame transmission is complete, if IEEE 1588 time stamping was enabled for the \nframe (as indicated in the transmit status) the time stamp value is written to the transmit \ndescriptor (TDES2 and TDES3) that contains the end-of-frame buffer. The status \ninformation is then written to this transmit descriptor (TDES0). Because the OWN bit is \ncleared during this step, the CPU now owns this descriptor. If time stamping was not \nenabled for this frame, the DMA does not alter the contents of TDES2 and TDES3.\n8. \nTransmit Interrupt (ETH_DMASR register [0]) is set after completing the transmission \nof a frame that has Interrupt on Completion (TDES1[31]) set in its last descriptor. The \nDMA engine then returns to Step 3.\n9. \nIn the Suspend state, the DMA tries to re-acquire the descriptor (and thereby returns to \nStep 3) when it receives a transmit poll demand, and the Underflow Interrupt Status bit \nis cleared.\nFigure 377 shows the TxDMA transmission flow in default mode.\n\n\n<>\n\nRM0090 Rev 21\n1171/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nFigure 377. TxDMA operation in Default mode\nTxDMA operation: OSF mode\nWhile in the Run state, the transmit process can simultaneously acquire two frames without \nclosing the Status descriptor of the first (if the OSF bit is set in ETH_DMAOMR register[2]). \nAs the transmit process finishes transferring the first frame, it immediately polls the transmit \ndescriptor list for the second frame. If the second frame is valid, the transmit process \ntransfers this frame before writing the first frame’s status information. In OSF mode, the \nRun-state transmit DMA operates according to the following sequence:\nStart TxDMA\n(Re-)fetch next \ndescriptor\nWrite status word\nto TDES0\nWait for Tx status\nTransfer data from \nbuffer(s)\n(AHB)\nerror?\nOwn\nbit set?\n(AHB)\nerror?\nFrame xfer \ncomplete?\nTime stamp \npresent?\n(AHB)\nerror?\nWrite time stamp to \nTDES2 and TDES3\n(AHB)\nerror?\nStop TxDMA\nTxDMA suspended\nNo\nYes\nNo\nYes\nNo\nNo\nStart\nYes\nYes\nYes\nClose intermediate \ndescriptor\nNo\nYes\nNo\nYes\nNo\nPoll demand\nai15639\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1172/1757\nRM0090 Rev 21\n1.\nThe DMA operates as described in steps 1–6 of the TxDMA (default mode).\n2. \nWithout closing the previous frame’s last descriptor, the DMA fetches the next \ndescriptor.\n3. \nIf the DMA owns the acquired descriptor, the DMA decodes the transmit buffer address \nin this descriptor. If the DMA does not own the descriptor, the DMA goes into Suspend \nmode and skips to Step 7.\n4. \nThe DMA fetches the Transmit frame from the STM32F4xx memory and transfers the \nframe until the end of frame data are transferred, closing the intermediate descriptors if \nthis frame is split across multiple descriptors.\n5. \nThe DMA waits for the transmission status and time stamp of the previous frame. When \nthe status is available, the DMA writes the time stamp to TDES2 and TDES3, if such \ntime stamp was captured (as indicated by a status bit). The DMA then writes the status, \nwith a cleared OWN bit, to the corresponding TDES0, thus closing the descriptor. If \ntime stamping was not enabled for the previous frame, the DMA does not alter the \ncontents of TDES2 and TDES3.\n6. \nIf enabled, the Transmit interrupt is set, the DMA fetches the next descriptor, then \nproceeds to Step 3 (when Status is normal). If the previous transmission status shows \nan underflow error, the DMA goes into Suspend mode (Step 7). \n7. \nIn Suspend mode, if a pending status and time stamp are received by the DMA, it \nwrites the time stamp (if enabled for the current frame) to TDES2 and TDES3, then \nwrites the status to the corresponding TDES0. It then sets relevant interrupts and \nreturns to Suspend mode. \n8. \nThe DMA can exit Suspend mode and enter the Run state (go to Step 1 or Step 2 \ndepending on pending status) only after receiving a Transmit Poll demand \n(ETH_DMATPDR register).\nFigure 378 shows the basic flowchart in OSF mode.\n\n\n<>\n\nRM0090 Rev 21\n1173/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nFigure 378. TxDMA operation in OSF mode\nTransmit frame processing\nThe transmit DMA expects that the data buffers contain complete Ethernet frames, \nexcluding preamble, pad bytes, and FCS fields. The DA, SA, and Type/Len fields contain \nvalid data. If the transmit descriptor indicates that the MAC core must disable CRC or pad \ninsertion, the buffer must have complete Ethernet frames (excluding preamble), including \nthe CRC bytes. Frames can be data-chained and span over several buffers. Frames have to \nbe delimited by the first descriptor (TDES0[28]) and the last descriptor (TDES0[29]). As the \ntransmission starts, TDES0[28] has to be set in the first descriptor. When this occurs, the \nframe data are transferred from the memory buffer to the Transmit FIFO. Concurrently, if the \nlast descriptor (TDES0[29]) of the current frame is cleared, the transmit process attempts to \nacquire the next descriptor. The transmit process expects TDES0[28] to be cleared in this \ndescriptor. If TDES0[29] is cleared, it indicates an intermediary buffer. If TDES0[29] is set, it \nPrevious frame \nstatus available\nStart TxDMA\n(Re-)fetch next \ndescriptor\nWrite status word to \nprev. frame’s TDES0\nTransfer data from \nbuffer(s)\n(AHB)\nerror?\nOwn\nbit set?\n(AHB)\nerror?\nFrame xfer \ncomplete?\nTime stamp \npresent?\n(AHB)\nerror?\nWrite time stamp to \nTDES2 & TDES3 \nfor previous frame\n(AHB)\nerror?\nStop TxDMA\nNo\nYes\nNo\nYes\nNo\nStart\nYes\nClose intermediate \ndescriptor\nNo\nNo\nWait for previous \nframe’s Tx status\nSecond\nframe?\nYes\nYes\nNo\nYes\nYes\nWrite time stamp to \nTDES2 & TDES3 \nfor previous frame\n(AHB)\nerror?\n(AHB)\nerror?\nYes\nTime stamp \npresent?\nYes\nWrite status word to \nprev. frame’s TDES0\nTxDMA suspended\nYes\nNo\nYes\nNo\nNo\nPoll \ndemand\nNo\nNo\nai15640\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1174/1757\nRM0090 Rev 21\nindicates the last buffer of the frame. After the last buffer of the frame has been transmitted, \nthe DMA writes back the final status information to the transmit descriptor 0 (TDES0) word \nof the descriptor that has the last segment set in transmit descriptor 0 (TDES0[29]). At this \ntime, if Interrupt on Completion (TDES0[30]) is set, Transmit Interrupt (in ETH_DMASR \nregister [0]) is set, the next descriptor is fetched, and the process repeats. Actual frame \ntransmission begins after the Transmit FIFO has reached either a programmable transmit \nthreshold (ETH_DMAOMR register[16:14]), or a full frame is contained in the FIFO. There is \nalso an option for the Store and forward mode (ETH_DMAOMR register[21]). Descriptors \nare released (OWN bit TDES0[31] is cleared) when the DMA finishes transferring the frame.\nTransmit polling suspended\nTransmit polling can be suspended by either of the following conditions:\n•\nThe DMA detects a descriptor owned by the CPU (TDES0[31]=0) and the Transmit \nbuffer unavailable flag is set (ETH_DMASR register[2]). To resume, the driver must \ngive descriptor ownership to the DMA and then issue a Poll Demand command.\n•\nA frame transmission is aborted when a transmit error due to underflow is detected. \nThe appropriate Transmit Descriptor 0 (TDES0) bit is set. If the second condition \noccurs, both the Abnormal Interrupt Summary (in ETH_DMASR register [15]) and \nTransmit Underflow bits (in ETH_DMASR register[5]) are set, and the information is \nwritten to Transmit Descriptor 0, causing the suspension. If the DMA goes into \nSuspend state due to the first condition, then both the Normal Interrupt Summary \n(ETH_DMASR register [16]) and Transmit Buffer Unavailable (ETH_DMASR \nregister[2]) bits are set. In both cases, the position in the transmit list is retained. The \nretained position is that of the descriptor following the last descriptor closed by the \nDMA. The driver must explicitly issue a Transmit Poll Demand command after rectifying \nthe suspension cause.\nNormal Tx DMA descriptors\nThe normal transmit descriptor structure consists of four 32-bit words as shown in \nFigure 379. The bit descriptions of TDES0, TDES1, TDES2 and TDES3 are given below.\nNote that enhanced descriptors must be used if time stamping is activated (ETH_PTPTSCR \nbit 0, TSE=1) or if IPv4 checksum offload is activated (ETH_MACCR bit 10, IPCO=1).\nFigure 379. Normal transmit descriptor\nTDES 3\nO\nW\nN\nCtrl\n[30:26]\nRes.\n24\nCtrl\n[23:20]\nReserved\n[19:18]\nStatus [16:0]\nReserved\n[31:29]\nBuffer 2 byte count\n[28:16]\nReserved\n[15:13]\nBuffer 1 byte count\n[12:0]\nBuffer 1 address [31:0] / Time stamp low [31:0]\nBuffer 2 address [31:0] or Next descriptor address [31:0] / Time stamp high [31:0]\nTDES 0\nTDES 1\nTDES 2\n31\n0\nai15642b\nT\nT\nS\nE\nT\nT\nS\nS\n\n\n<>\n\nRM0090 Rev 21\n1175/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n•\nTDES0: Transmit descriptor Word0\nThe application software has to program the control bits [30:26]+[23:20] plus the OWN \nbit [31] during descriptor initialization. When the DMA updates the descriptor (or writes \nit back), it resets all the control bits plus the OWN bit, and reports only the status bits.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nOWN\nIC\nLS\nFS\nDC\nDP\nTTSE\nRes\nCIC\nTER\nTCH\nRes.\nTTSS\nIHE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nES\nJT\nFF\nIPE\nLCA\nNC\nLCO\nEC\nVF\nCC\nED\nUF\nDB\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 OWN: Own bit\nWhen set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset, it \nindicates that the descriptor is owned by the CPU. The DMA clears this bit either when it \ncompletes the frame transmission or when the buffers allocated in the descriptor are read \ncompletely. The ownership bit of the frame’s first descriptor must be set after all subsequent \ndescriptors belonging to the same frame have been set.\nBit 30 IC: Interrupt on completion\nWhen set, this bit sets the Transmit Interrupt (ETH_DMASR[0]) after the present frame has \nbeen transmitted.\nBit 29 LS: Last segment\nWhen set, this bit indicates that the buffer contains the last segment of the frame.\nBit 28 FS: First segment\nWhen set, this bit indicates that the buffer contains the first segment of a frame.\nBit 27 DC: Disable CRC\nWhen this bit is set, the MAC does not append a cyclic redundancy check (CRC) to the end \nof the transmitted frame. This is valid only when the first segment (TDES0[28]) is set.\nBit 26 DP: Disable pad\nWhen set, the MAC does not automatically add padding to a frame shorter than 64 bytes. \nWhen this bit is reset, the DMA automatically adds padding and CRC to a frame shorter than \n64 bytes, and the CRC field is added despite the state of the DC (TDES0[27]) bit. This is \nvalid only when the first segment (TDES0[28]) is set.\nBit 25 TTSE: Transmit time stamp enable\n When TTSE is set and when TSE is set (ETH_PTPTSCR bit 0), IEEE1588 hardware time \nstamping is activated for the transmit frame described by the descriptor. This field is only valid \nwhen the First segment control bit (TDES0[28]) is set.\nBit 24 Reserved, must be kept at reset value.\nBits 23:22 CIC: Checksum insertion control\nThese bits control the checksum calculation and insertion. Bit encoding is as shown below:\n00: Checksum Insertion disabled\n01: Only IP header checksum calculation and insertion are enabled\n10: IP header checksum and payload checksum calculation and insertion are enabled, but \npseudo-header checksum is not calculated in hardware\n11: IP Header checksum and payload checksum calculation and insertion are enabled, and \npseudo-header checksum is calculated in hardware.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1176/1757\nRM0090 Rev 21\nBit 21 TER: Transmit end of ring\nWhen set, this bit indicates that the descriptor list reached its final descriptor. The DMA \nreturns to the base address of the list, creating a descriptor ring.\nBit 20 TCH: Second address chained\nWhen set, this bit indicates that the second address in the descriptor is the next descriptor \naddress rather than the second buffer address. When TDES0[20] is set, TBS2 \n(TDES1[28:16]) is a “don’t care” value. TDES0[21] takes precedence over TDES0[20].\nBits 19:18 Reserved, must be kept at reset value.\nBit 17 TTSS: Transmit time stamp status\nThis field is used as a status bit to indicate that a time stamp was captured for the described \ntransmit frame. When this bit is set, TDES2 and TDES3 have a time stamp value captured for the \ntransmit frame. This field is only valid when the descriptor’s Last segment control bit (TDES0[29]) \nis set.\nNote that when enhanced descriptors are enabled (EDFE=1 in ETH_DMABMR), TTSS=1 \nindicates that TDES6 and TDES7 have the time stamp value.\nBit 16 IHE: IP header error\nWhen set, this bit indicates that the MAC transmitter detected an error in the IP datagram \nheader. The transmitter checks the header length in the IPv4 packet against the number of \nheader bytes received from the application and indicates an error status if there is a \nmismatch. For IPv6 frames, a header error is reported if the main header length is not 40 \nbytes. Furthermore, the Ethernet length/type field value for an IPv4 or IPv6 frame must \nmatch the IP header version received with the packet. For IPv4 frames, an error status is \nalso indicated if the Header Length field has a value less than 0x5.\nBit 15 ES: Error summary\nIndicates the logical OR of the following bits:\nTDES0[14]: Jabber timeout \nTDES0[13]: Frame flush \nTDES0[11]: Loss of carrier \nTDES0[10]: No carrier \nTDES0[9]: Late collision \nTDES0[8]: Excessive collision \nTDES0[2]:Excessive deferral \nTDES0[1]: Underflow error \nTDES0[16]: IP header error \nTDES0[12]: IP payload error\nBit 14 JT: Jabber timeout\nWhen set, this bit indicates the MAC transmitter has experienced a jabber timeout. This bit is \nonly set when the MAC configuration register’s JD bit is not set.\nBit 13 FF: Frame flushed\nWhen set, this bit indicates that the DMA/MTL flushed the frame due to a software Flush \ncommand given by the CPU.\nBit 12 IPE: IP payload error\nWhen set, this bit indicates that MAC transmitter detected an error in the TCP, UDP, or ICMP \nIP datagram payload. The transmitter checks the payload length received in the IPv4 or IPv6 \nheader against the actual number of TCP, UDP or ICMP packet bytes received from the \napplication and issues an error status in case of a mismatch.\n\n\n<>\n\nRM0090 Rev 21\n1177/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n•\nTDES1: Transmit descriptor Word1\n \n \nBit 11 LCA: Loss of carrier\nWhen set, this bit indicates that a loss of carrier occurred during frame transmission (that is, \nthe MII_CRS signal was inactive for one or more transmit clock periods during frame \ntransmission). This is valid only for the frames transmitted without collision when the MAC \noperates in Half-duplex mode.\nBit 10 NC: No carrier\nWhen set, this bit indicates that the Carrier Sense signal form the PHY was not asserted \nduring transmission.\nBit 9 LCO: Late collision\nWhen set, this bit indicates that frame transmission was aborted due to a collision occurring \nafter the collision window (64 byte times, including preamble, in MII mode). This bit is not \nvalid if the Underflow Error bit is set.\nBit 8 EC: Excessive collision\nWhen set, this bit indicates that the transmission was aborted after 16 successive collisions \nwhile attempting to transmit the current frame. If the RD (Disable retry) bit in the MAC \nConfiguration register is set, this bit is set after the first collision, and the transmission of the \nframe is aborted.\nBit 7 VF: VLAN frame\nWhen set, this bit indicates that the transmitted frame was a VLAN-type frame.\nBits 6:3 CC: Collision count\nThis 4-bit counter value indicates the number of collisions occurring before the frame was \ntransmitted. The count is not valid when the Excessive collisions bit (TDES0[8]) is set.\nBit 2 ED: Excessive deferral\nWhen set, this bit indicates that the transmission has ended because of excessive deferral \nof over 24 288 bit times if the Deferral check (DC) bit in the MAC Control register is set high.\nBit 1 UF: Underflow error\nWhen set, this bit indicates that the MAC aborted the frame because data arrived late from \nthe RAM memory. Underflow error indicates that the DMA encountered an empty transmit \nbuffer while transmitting the frame. The transmission process enters the Suspended state \nand sets both Transmit underflow (ETH_DMASR[5]) and Transmit interrupt \n(ETH_DMASR[0]).\nBit 0 DB: Deferred bit\nWhen set, this bit indicates that the MAC defers before transmission because of the \npresence of the carrier. This bit is valid only in Half-duplex mode.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTBS2\nReserved\nTBS1\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw rw rw rw\nrw\nrw\nrw\n31:29 Reserved, must be kept at reset value.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1178/1757\nRM0090 Rev 21\n•\nTDES2: Transmit descriptor Word2\nTDES2 contains the address pointer to the first buffer of the descriptor or it contains \ntime stamp data.\n \n \n•\nTDES3: Transmit descriptor Word3\nTDES3 contains the address pointer either to the second buffer of the descriptor or the \nnext descriptor, or it contains time stamp data.\n \n28:16 TBS2: Transmit buffer 2 size\nThese bits indicate the second data buffer size in bytes. This field is not valid if TDES0[20] is \nset.\n15:13 Reserved, must be kept at reset value.\n12:0 TBS1: Transmit buffer 1 size\nThese bits indicate the first data buffer byte size, in bytes. If this field is 0, the DMA ignores \nthis buffer and uses Buffer 2 or the next descriptor, depending on the value of TCH \n(TDES0[20]).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTBAP1/TBAP/TTSL\nrw\nBits 31:0 TBAP1: Transmit buffer 1 address pointer / Transmit frame time stamp low\nThese bits have two different functions: they indicate to the DMA the location of data in \nmemory, and after all data are transferred, the DMA can then use these bits to pass back time \nstamp data.\nTBAP: When the software makes this descriptor available to the DMA (at the moment that the \nOWN bit is set to 1 in TDES0), these bits indicate the physical address of Buffer 1. There is no \nlimitation on the buffer address alignment. See Host data buffer alignment for further details on \nbuffer address alignment.\nTTSL: Before it clears the OWN bit in TDES0, the DMA updates this field with the 32 least \nsignificant bits of the time stamp captured for the corresponding transmit frame (overwriting \nthe value for TBAP1). This field has the time stamp only if time stamping is activated for this \nframe (see TTSE, TDES0 bit 25) and if the Last segment control bit (LS) in the descriptor is \nset.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTBAP2/TBAP2/TTSH\nrw\n\n\n<>\n\nRM0090 Rev 21\n1179/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n \nEnhanced Tx DMA descriptors\nEnhanced descriptors (enabled with EDFE=1, ETHDMABMR bit 7), must be used if time \nstamping is activated (TSE=1, ETH_PTPTSCR bit 0) or if IPv4 checksum offload is \nactivated (IPCO=1, ETH_MACCR bit 10).\nEnhanced descriptors comprise eight 32-bit words, twice the size of normal descriptors. \nTDES0, TDES1, TDES2 and TDES3 have the same definitions as for normal transmit \ndescriptors (refer to Normal Tx DMA descriptors). TDES6 and TDES7 hold the time stamp. \nTDES4, TDES5, TDES6 and TDES7 are defined below.\nWhen the Enhanced descriptor mode is selected, the software needs to allocate 32-bytes (8 \nwords) of memory for every descriptor. When time stamping or IPv4 checksum offload are \nnot being used, the enhanced descriptor format may be disabled and the software can use \nnormal descriptors with the default size of 16 bytes.\nBits 31:0 TBAP2: Transmit buffer 2 address pointer (Next descriptor address) / Transmit frame time \nstamp high\nThese bits have two different functions: they indicate to the DMA the location of data in \nmemory, and after all data are transferred, the DMA can then use these bits to pass back \ntime stamp data.\nTBAP2: When the software makes this descriptor available to the DMA (at the moment when \nthe OWN bit is set to 1 in TDES0), these bits indicate the physical address of Buffer 2 when a \ndescriptor ring structure is used. If the Second address chained (TDES1 [20]) bit is set, this \naddress contains the pointer to the physical memory where the next descriptor is present. The \nbuffer address pointer must be aligned to the bus width only when TDES1 [20] is set. (LSBs are \nignored internally.)\nTTSH: Before it clears the OWN bit in TDES0, the DMA updates this field with the 32 most \nsignificant bits of the time stamp captured for the corresponding transmit frame (overwriting \nthe value for TBAP2). This field has the time stamp only if time stamping is activated for this \nframe (see TDES0 bit 25, TTSE) and if the Last segment control bit (LS) in the descriptor is \nset.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1180/1757\nRM0090 Rev 21\nFigure 380. Enhanced transmit descriptor\n•\nTDES4: Transmit descriptor Word4\nReserved\n•\nTDES5: Transmit descriptor Word5\nReserved\n•\nTDES6: Transmit descriptor Word6\n \n \nTDES 3\nO\nW\nN\nCtrl\n[30:26]\nRes.\n24\nCtrl\n[23:20]\nReserved \n[19:18]\nStatus [16:0]\nReserved\n[31:29]\nBuffer 2 byte count\n[28:16]\nReserved\n[15:13]\nBuffer 1 byte count\n[12:0]\nBuffer 1 address [31:0] \nBuffer 2 address [31:0] or Next descriptor address [31:0] \nTDES 0\nTDES 1\nTDES 2\n31\n0\nai17105b\nT\nT\nS\nE\nT\nT\nS\nS\nTDES 7\nTDES 4\nTDES 5\nTDES 6\nReserved\nReserved\nTime stamp low [31:0]\nTime stamp high [31:0]\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTTSL\nrw\nBits 31:0 TTSL: Transmit frame time stamp low\nThis field is updated by DMA with the 32 least significant bits of the time stamp captured \nfor the corresponding transmit frame. This field has the time stamp only if the Last segment \ncontrol bit (LS) in the descriptor is set.\n\n\n<>\n\nRM0090 Rev 21\n1181/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n•\nTDES7: Transmit descriptor Word7\n \n \n33.6.8 \nRx DMA configuration\nThe Receive DMA engine’s reception sequence is illustrated in Figure 381 and described \nbelow:\n1.\nThe CPU sets up Receive descriptors (RDES0-RDES3) and sets the OWN bit \n(RDES0[31]). \n2. \nOnce the SR (ETH_DMAOMR register[1]) bit is set, the DMA enters the Run state. \nWhile in the Run state, the DMA polls the receive descriptor list, attempting to acquire \nfree descriptors. If the fetched descriptor is not free (is owned by the CPU), the DMA \nenters the Suspend state and jumps to Step 9.\n3. \nThe DMA decodes the receive data buffer address from the acquired descriptors.\n4. \nIncoming frames are processed and placed in the acquired descriptor’s data buffers.\n5. \nWhen the buffer is full or the frame transfer is complete, the Receive engine fetches the \nnext descriptor.\n6. \nIf the current frame transfer is complete, the DMA proceeds to step 7. If the DMA does \nnot own the next fetched descriptor and the frame transfer is not complete (EOF is not \nyet transferred), the DMA sets the Descriptor error bit in RDES0 (unless flushing is \ndisabled). The DMA closes the current descriptor (clears the OWN bit) and marks it as \nintermediate by clearing the Last segment (LS) bit in the RDES1 value (marks it as last \ndescriptor if flushing is not disabled), then proceeds to step 8. If the DMA owns the next \ndescriptor but the current frame transfer is not complete, the DMA closes the current \ndescriptor as intermediate and returns to step 4.\n7. \nIf IEEE 1588 time stamping is enabled, the DMA writes the time stamp (if available) to \nthe current descriptor’s RDES2 and RDES3. It then takes the received frame’s status \nand writes the status word to the current descriptor’s RDES0, with the OWN bit cleared \nand the Last segment bit set.\n8. \nThe Receive engine checks the latest descriptor’s OWN bit. If the CPU owns the \ndescriptor (OWN bit is at 0) the Receive buffer unavailable bit (in ETH_DMASR \nregister[7]) is set and the DMA Receive engine enters the Suspended state (step 9). If \nthe DMA owns the descriptor, the engine returns to step 4 and awaits the next frame.\n9. \nBefore the Receive engine enters the Suspend state, partial frames are flushed from \nthe Receive FIFO (you can control flushing using bit 24 in the ETH_DMAOMR \nregister).\n10. The Receive DMA exits the Suspend state when a Receive Poll demand is given or the \nstart of next frame is available from the Receive FIFO. The engine proceeds to step 2 \nand re-fetches the next descriptor.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTTSH\nrw\nBits 31:0 TTSH: Transmit frame time stamp high\nThis field is updated by DMA with the 32 most significant bits of the time stamp captured for \nthe corresponding transmit frame. This field has the time stamp only if the Last segment control \nbit (LS) in the descriptor is set.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1182/1757\nRM0090 Rev 21\nThe DMA does not acknowledge accepting the status until it has completed the time stamp \nwrite-back and is ready to perform status write-back to the descriptor. If software has \nenabled time stamping through CSR, when a valid time stamp value is not available for the \nframe (for example, because the receive FIFO was full before the time stamp could be \nwritten to it), the DMA writes all ones to RDES2 and RDES3. Otherwise (that is, if time \nstamping is not enabled), RDES2 and RDES3 remain unchanged.\nFigure 381. Receive DMA operation\n(Re-)Fetch next \ndescriptor\n(AHB)\nerror?\nNo\nOwn bit set?\nYes\nYes\nStop RxDMA\nStart RxDMA\nStart\n(AHB)\nerror?\nNo\nRxDMA suspended\nYes\nFrame data \navailable?\nWait for frame data\nWrite data to buffer(s)\nYes\nYes\nFetch next descriptor\nYes\nNo\nFrame transfer \ncomplete?\nNo\nSet descriptor error\nYes\nTime stamp \npresent?\nNo\nClose RDES0 as last \ndescriptor\nWrite time stamp to \nRDES2 & RDES3\nNo\n(AHB)\nerror?\nYes\nClose RDES0 as \nintermediate descriptor\nFrame transfer \ncomplete?\nNo\nFlush disabled?\nNo\nFlush the\nremaining frame\nYes\nYes\nNo\nNo\nNo\nYes\nYes\nPoll demand/\nnew frame available\nNo\nYes\n(AHB)\nerror?\n(AHB)\nerror?\nNo\nOwn bit set\nfor next desc?\nFlush \ndisabled?\nai15643\n\n\n<>\n\nRM0090 Rev 21\n1183/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nReceive descriptor acquisition\nThe receive engine always attempts to acquire an extra descriptor in anticipation of an \nincoming frame. Descriptor acquisition is attempted if any of the following conditions is/are \nsatisfied:\n•\nThe receive Start/Stop bit (ETH_DMAOMR register[1]) has been set immediately after \nthe DMA has been placed in the Run state.\n•\nThe data buffer of the current descriptor is full before the end of the frame currently \nbeing transferred\n•\nThe controller has completed frame reception, but the current receive descriptor has \nnot yet been closed.\n•\nThe receive process has been suspended because of a CPU-owned buffer \n(RDES0[31] = 0) and a new frame is received.\n•\nA Receive poll demand has been issued.\nReceive frame processing\nThe MAC transfers the received frames to the STM32F4xx memory only when the frame \npasses the address filter and the frame size is greater than or equal to the configurable \nthreshold bytes set for the Receive FIFO, or when the complete frame is written to the FIFO \nin Store-and-forward mode. If the frame fails the address filtering, it is dropped in the MAC \nblock itself (unless Receive All ETH_MACFFR [31] bit is set). Frames that are shorter than \n64 bytes, because of collision or premature termination, can be purged from the Receive \nFIFO. After 64 (configurable threshold) bytes have been received, the DMA block begins \ntransferring the frame data to the receive buffer pointed to by the current descriptor. The \nDMA sets the first descriptor (RDES0[9]) after the DMA AHB Interface becomes ready to \nreceive a data transfer (if DMA is not fetching transmit data from the memory), to delimit the \nframe. The descriptors are released when the OWN (RDES0[31]) bit is reset to 0, either as \nthe data buffer fills up or as the last segment of the frame is transferred to the receive buffer. \nIf the frame is contained in a single descriptor, both the last descriptor (RDES0[8]) and first \ndescriptor (RDES0[9]) bits are set. The DMA fetches the next descriptor, sets the last \ndescriptor (RDES0[8]) bit, and releases the RDES0 status bits in the previous frame \ndescriptor. Then the DMA sets the receive interrupt bit (ETH_DMASR register [6]). The \nsame process repeats unless the DMA encounters a descriptor flagged as being owned by \nthe CPU. If this occurs, the receive process sets the receive buffer unavailable bit \n(ETH_DMASR register[7]) and then enters the Suspend state. The position in the receive \nlist is retained.\nReceive process suspended\nIf a new receive frame arrives while the receive process is in Suspend state, the DMA re-\nfetches the current descriptor in the STM32F4xx memory. If the descriptor is now owned by \nthe DMA, the receive process re-enters the Run state and starts frame reception. If the \ndescriptor is still owned by the host, by default, the DMA discards the current frame at the \ntop of the Rx FIFO and increments the missed frame counter. If more than one frame is \nstored in the Rx FIFO, the process repeats. The discarding or flushing of the frame at the \ntop of the Rx FIFO can be avoided by setting the DMA Operation mode register bit 24 \n(DFRF). In such conditions, the receive process sets the receive buffer unavailable status \nbit and returns to the Suspend state.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1184/1757\nRM0090 Rev 21\nNormal Rx DMA descriptors\nThe normal receive descriptor structure consists of four 32-bit words (16 bytes). These are \nshown in Figure 382. The bit descriptions of RDES0, RDES1, RDES2 and RDES3 are given \nbelow.\nNote that enhanced descriptors must be used if time stamping is activated (TSE=1, \nETH_PTPTSCR bit 0) or if IPv4 checksum offload is activated (IPCO=1, ETH_MACCR bit \n10).\nFigure 382. Normal Rx DMA descriptor structure\n•\nRDES0: Receive descriptor Word0\nRDES0 contains the received frame status, the frame length and the descriptor \nownership information.\n \n \nRDES 3\nO\nW\nN\nStatus [30:0]\nReserved\n[30:29]\nBuffer 2 byte count\n[28:16]\nCTRL\n[15:14]\nBuffer 1 byte count\n[12:0]\nBuffer 1 address [31:0]\nBuffer 2 address [31:0] or Next descriptor address [31:0]\nRDES 0\nRDES 1\nRDES 2\n31\n0\nai15644\nRes.\nCT\nRL\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOWN\nAFM\nFL\nES\nDE\nSAF\nLE\nOE\nVLAN\nFS\nLS\nIPHCE/TSV\nLCO\nFT\nRWT\nRE\nDE\nCE\nPCE/ESA\nrw\nBit 31 OWN: Own bit\nWhen set, this bit indicates that the descriptor is owned by the DMA of the MAC Subsystem. \nWhen this bit is reset, it indicates that the descriptor is owned by the Host. The DMA clears this bit \neither when it completes the frame reception or when the buffers that are associated with this \ndescriptor are full.\nBit 30 AFM: Destination address filter fail\nWhen set, this bit indicates a frame that failed the DA filter in the MAC Core.\nBits 29:16 FL: Frame length\nThese bits indicate the byte length of the received frame that was transferred to host memory \n(including CRC). This field is valid only when last descriptor (RDES0[8]) is set and descriptor error \n(RDES0[14]) is reset.\nThis field is valid when last descriptor (RDES0[8]) is set. When the last descriptor and error \nsummary bits are not set, this field indicates the accumulated number of bytes that have been \ntransferred for the current frame.\n\n\n<>\n\nRM0090 Rev 21\n1185/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nBit 15 ES: Error summary\nIndicates the logical OR of the following bits:\nRDES0[1]: CRC error\nRDES0[3]: Receive error\nRDES0[4]: Watchdog timeout\nRDES0[6]: Late collision\nRDES0[7]: Giant frame (This is not applicable when RDES0[7] indicates an IPV4 header \nchecksum error.)\n RDES0[11]: Overflow error\n RDES0[14]: Descriptor error.\nThis field is valid only when the last descriptor (RDES0[8]) is set.\nBit 14 DE: Descriptor error\nWhen set, this bit indicates a frame truncation caused by a frame that does not fit within the current \ndescriptor buffers, and that the DMA does not own the next descriptor. The frame is truncated. \nThis field is valid only when the last descriptor (RDES0[8]) is set.\nBit 13 SAF: Source address filter fail\nWhen set, this bit indicates that the SA field of frame failed the SA filter in the MAC Core.\nBit 12 LE: Length error\nWhen set, this bit indicates that the actual length of the received frame does not match the value in \nthe Length/ Type field. This bit is valid only when the Frame type (RDES0[5]) bit is reset.\nBit 11 OE: Overflow error\nWhen set, this bit indicates that the received frame was damaged due to buffer overflow.\nBit 10 VLAN: VLAN tag\nWhen set, this bit indicates that the frame pointed to by this descriptor is a VLAN frame tagged \nby the MAC core.\nBit 9 FS: First descriptor\nWhen set, this bit indicates that this descriptor contains the first buffer of the frame. If the size of the \nfirst buffer is 0, the second buffer contains the beginning of the frame. If the size of the second buffer \nis also 0, the next descriptor contains the beginning of the frame.\nBit 8 LS: Last descriptor\nWhen set, this bit indicates that the buffers pointed to by this descriptor are the last buffers of \nthe frame.\nBit 7 IPHCE/TSV: IPv header checksum error / time stamp valid\nIf IPHCE is set, it indicates an error in the IPv4 or IPv6 header. This error can be due to inconsistent \nEthernet Type field and IP header Version field values, a header checksum mismatch in IPv4, or an \nEthernet frame lacking the expected number of IP header bytes. This bit can take on special \nmeaning as specified in Table 194.\nIf enhanced descriptor format is enabled (EDFE=1, bit 7 of ETH_DMABMR), this bit takes on \nthe TSV function (otherwise it is IPHCE). When TSV is set, it indicates that a snapshot of the \ntimestamp is written in descriptor words 6 (RDES6) and 7 (RDES7). TSV is valid only when \nthe Last descriptor bit (RDES0[8]) is set.\nBit 6 LCO: Late collision\nWhen set, this bit indicates that a late collision has occurred while receiving the frame in Half-\nduplex mode.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1186/1757\nRM0090 Rev 21\nBits 5, 7, and 0 reflect the conditions discussed in Table 194.\nBit 5 FT: Frame type\nWhen set, this bit indicates that the Receive frame is an Ethernet-type frame (the LT field is greater \nthan or equal to 0x0600). When this bit is reset, it indicates that the received frame is an \nIEEE802.3 frame. This bit is not valid for Runt frames less than 14 bytes. When the normal \ndescriptor format is used (ETH_DMABMR EDFE=0), FT can take on special meaning as \nspecified in Table 194.\nBit 4 RWT: Receive watchdog timeout\nWhen set, this bit indicates that the Receive watchdog timer has expired while receiving the \ncurrent frame and the current frame is truncated after the watchdog timeout.\nBit 3 RE: Receive error\nWhen set, this bit indicates that the RX_ERR signal is asserted while RX_DV is asserted \nduring frame reception.\nBit 2 DE: Dribble bit error\nWhen set, this bit indicates that the received frame has a non-integer multiple of bytes (odd \nnibbles). This bit is valid only in MII mode.\nBit 1 CE: CRC error\nWhen set, this bit indicates that a cyclic redundancy check (CRC) error occurred on the \nreceived frame. This field is valid only when the last descriptor (RDES0[8]) is set.\nBit 0 PCE/ESA: Payload checksum error / extended status available\nWhen set, it indicates that the TCP, UDP or ICMP checksum the core calculated does not \nmatch the received encapsulated TCP, UDP or ICMP segment’s Checksum field. This bit is \nalso set when the received number of payload bytes does not match the value indicated in \nthe Length field of the encapsulated IPv4 or IPv6 datagram in the received Ethernet frame. \nThis bit can take on special meaning as specified in Table 194.\nIf the enhanced descriptor format is enabled (EDFE=1, bit 7 in ETH_DMABMR), this bit takes \non the ESA function (otherwise it is PCE). When ESA is set, it indicates that the extended \nstatus is available in descriptor word 4 (RDES4). ESA is valid only when the last descriptor bit \n(RDES0[8]) is set.\n\n\n<>\n\nRM0090 Rev 21\n1187/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n \n•\nRDES1: Receive descriptor Word1\n \n \nTable 194. Receive descriptor 0 - encoding for bits 7, 5 and 0 (normal descriptor\nformat only, EDFE=0)\nBit 5: \nframe \ntype\nBit 7: IPC \nchecksum \nerror\nBit 0: payload \nchecksum \nerror\nFrame status\n0\n0\n0\nIEEE 802.3 Type frame (Length field value is less than \n0x0600.)\n1\n0\n0\nIPv4/IPv6 Type frame, no checksum error detected\n1\n0\n1\nIPv4/IPv6 Type frame with a payload checksum error (as described \nfor PCE) detected\n1\n1\n0\nIPv4/IPv6 Type frame with an IP header checksum error (as \ndescribed for IPC CE) detected\n1\n1\n1\nIPv4/IPv6 Type frame with both IP header and payload checksum \nerrors detected\n0\n0\n1\nIPv4/IPv6 Type frame with no IP header checksum error and the \npayload check bypassed, due to an unsupported payload\n0\n1\n1\nA Type frame that is neither IPv4 or IPv6 (the checksum offload \nengine bypasses checksum completely.)\n0\n1\n0\nReserved\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDIC\nRBS2\nRBS2\nRER\nRCH\nReserved\nRBS\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw rw rw rw\nrw\nrw\nrw\nBit 31 DIC: Disable interrupt on completion\nWhen set, this bit prevents setting the Status register’s RS bit (CSR5[6]) for the received frame \nending in the buffer indicated by this descriptor. This, in turn, disables the assertion of the interrupt to \nHost due to RS for that frame.\nBits 30:29 Reserved, must be kept at reset value.\nBits 28:16 RBS2: Receive buffer 2 size\nThese bits indicate the second data buffer size, in bytes. The buffer size must be a multiple of 4, \n8, or 16, depending on the bus widths (32, 64 or 128, respectively), even if the value of RDES3 \n(buffer2 address pointer) is not aligned to bus width. If the buffer size is not an appropriate multiple \nof 4, 8 or 16, the resulting behavior is undefined. This field is not valid if RDES1 [14] is set.\nBit 15 RER: Receive end of ring\nWhen set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to the \nbase address of the list, creating a descriptor ring.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1188/1757\nRM0090 Rev 21\n•\nRDES2: Receive descriptor Word2\nRDES2 contains the address pointer to the first data buffer in the descriptor, or it \ncontains time stamp data.\n \n \nBit 14 RCH: Second address chained\nWhen set, this bit indicates that the second address in the descriptor is the next descriptor address \nrather than the second buffer address. When this bit is set, RBS2 (RDES1[28:16]) is a “don’t \ncare” value. RDES1[15] takes precedence over RDES1[14].\nBit 13 Reserved, must be kept at reset value.\nBits 12:0 RBS1: Receive buffer 1 size\nIndicates the first data buffer size in bytes. The buffer size must be a multiple of 4, 8 or 16, \ndepending upon the bus widths (32, 64 or 128), even if the value of RDES2 (buffer1 address \npointer) is not aligned. When the buffer size is not a multiple of 4, 8 or 16, the resulting behavior is \nundefined. If this field is 0, the DMA ignores this buffer and uses Buffer 2 or next descriptor \ndepending on the value of RCH (bit 14).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRBP1 / RTSL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw rw rw rw\nrw\nrw\nrw\nBits 31:0 RBAP1 / RTSL: Receive buffer 1 address pointer / Receive frame time stamp low\nThese bits take on two different functions: the application uses them to indicate to the DMA \nwhere to store the data in memory, and then after transferring all the data the DMA may use \nthese bits to pass back time stamp data.\nRBAP1: When the software makes this descriptor available to the DMA (at the moment that \nthe OWN bit is set to 1 in RDES0), these bits indicate the physical address of Buffer 1. There are \nno limitations on the buffer address alignment except for the following condition: the DMA uses the \nconfigured value for its address generation when the RDES2 value is used to store the start of \nframe. Note that the DMA performs a write operation with the RDES2[3/2/1:0] bits as 0 during the \ntransfer of the start of frame but the frame data is shifted as per the actual buffer address pointer. The \nDMA ignores RDES2[3/2/1:0] (corresponding to bus width of 128/64/32) if the address pointer is to \na buffer where the middle or last part of the frame is stored.\nRTSL: Before it clears the OWN bit in RDES0, the DMA updates this field with the 32 least \nsignificant bits of the time stamp captured for the corresponding receive frame (overwriting \nthe value for RBAP1). This field has the time stamp only if time stamping is activated for this \nframe and if the Last segment control bit (LS) in the descriptor is set.\n\n\n<>\n\nRM0090 Rev 21\n1189/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n•\nRDES3: Receive descriptor Word3\nRDES3 contains the address pointer either to the second data buffer in the descriptor \nor to the next descriptor, or it contains time stamp data.\n \n \nEnhanced Rx DMA descriptors format with IEEE1588 time stamp\nEnhanced descriptors (enabled with EDFE=1, ETHDMABMR bit 7), must be used if time \nstamping is activated (TSE=1, ETH_PTPTSCR bit 0) or if IPv4 checksum offload is \nactivated (IPCO=1, ETH_MACCR bit 10).\nEnhanced descriptors comprise eight 32-bit words, twice the size of normal descriptors. \nRDES0, RDES1, RDES2 and RDES3 have the same definitions as for normal receive \ndescriptors (refer to Normal Rx DMA descriptors). RDES4 contains extended status while \nRDES6 and RDES7 hold the time stamp. RDES4, RDES5, RDES6 and RDES7 are defined \nbelow.\nWhen the Enhanced descriptor mode is selected, the software needs to allocate 32 bytes (8 \nwords) of memory for every descriptor. When time stamping or IPv4 checksum offload are \nnot being used, the enhanced descriptor format may be disabled and the software can use \nnormal descriptors with the default size of 16 bytes.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRBP2 / RTSH\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw rw rw rw\nrw\nrw\nrw\nBits 31:0 RBAP2 / RTSH: Receive buffer 2 address pointer (next descriptor address) / Receive frame \ntime stamp high\nThese bits take on two different functions: the application uses them to indicate to the DMA \nthe location of where to store the data in memory, and then after transferring all the data the \nDMA may use these bits to pass back time stamp data.\nRBAP1: When the software makes this descriptor available to the DMA (at the moment that \nthe OWN bit is set to 1 in RDES0), these bits indicate the physical address of buffer 2 when a \ndescriptor ring structure is used. If the second address chained (RDES1 [24]) bit is set, this address \ncontains the pointer to the physical memory where the next descriptor is present. If RDES1 [24] is \nset, the buffer (next descriptor) address pointer must be bus width-aligned (RDES3[3, 2, or \n1:0] = 0, corresponding to a bus width of 128, 64 or 32. LSBs are ignored internally.) \nHowever, when RDES1 [24] is reset, there are no limitations on the RDES3 value, except for the \nfollowing condition: the DMA uses the configured value for its buffer address generation when the \nRDES3 value is used to store the start of frame. The DMA ignores RDES3[3, 2, or 1:0] \n(corresponding to a bus width of 128, 64 or 32) if the address pointer is to a buffer where the \nmiddle or last part of the frame is stored.\nRTSH: Before it clears the OWN bit in RDES0, the DMA updates this field with the 32 most \nsignificant bits of the time stamp captured for the corresponding receive frame (overwriting \nthe value for RBAP2). This field has the time stamp only if time stamping is activated and if \nthe Last segment control bit (LS) in the descriptor is set.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1190/1757\nRM0090 Rev 21\nFigure 383. Enhanced receive descriptor field format with IEEE1588 time stamp \nenabled\n•\nRDES4: Receive descriptor Word4\nThe extended status, shown below, is valid only when there is status related to IPv4 \nchecksum or time stamp available as indicated by bit 0 in RDES0.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPV\nPFT\nPMT\nIPV6PR\nIPV4PR\nIPCB\nIPPE\nIPHE\nIPPT\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw rw rw rw\nrw\nrw\nrw\nBits 31:14 Reserved, must be kept at reset value.\nBit 13 PV: PTP version\nWhen set, indicates that the received PTP message uses the IEEE 1588 version 2 format. \nWhen cleared, it uses version 1 format. This is valid only if the message type is non-zero.\nBit 12 PFT: PTP frame type\nWhen set, this bit indicates that the PTP message is sent directly over Ethernet. When this bit \nis cleared and the message type is non-zero, it indicates that the PTP message is sent over \nUDP-IPv4 or UDP-IPv6. The information on IPv4 or IPv6 can be obtained from bits 6 and 7.\n\n\n<>\n\nRM0090 Rev 21\n1191/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n•\nRDES5: Receive descriptor Word5\nReserved.\n•\nRDES6: Receive descriptor Word6\nThe table below describes the fields that have different meaning for RDES6 when the \nreceive descriptor is closed and time stamping is enabled.\nBits 11:8 PMT: PTP message type\nThese bits are encoded to give the type of the message received.\n– 0000: No PTP message received\n– 0001: SYNC (all clock types)\n– 0010: Follow_Up (all clock types)\n– 0011: Delay_Req (all clock types)\n– 0100: Delay_Resp (all clock types)\n– 0101: Pdelay_Req (in peer-to-peer transparent clock) or Announce (in ordinary or boundary \nclock)\n– 0110: Pdelay_Resp (in peer-to-peer transparent clock) or Management (in ordinary or \nboundary clock)\n– 0111: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock) or Signaling (for ordinary \nor boundary clock)\n– 1xxx - Reserved\nBit 7 IPV6PR: IPv6 packet received\nWhen set, this bit indicates that the received packet is an IPv6 packet.\nBit 6 IPV4PR: IPv4 packet received\nWhen set, this bit indicates that the received packet is an IPv4 packet.\nBit 5 IPCB: IP checksum bypassed\nWhen set, this bit indicates that the checksum offload engine is bypassed.\nBit 4 IPPE: IP payload error\nWhen set, this bit indicates that the 16-bit IP payload checksum (that is, the TCP, UDP, or \nICMP checksum) that the core calculated does not match the corresponding checksum field \nin the received segment. It is also set when the TCP, UDP, or ICMP segment length does not \nmatch the payload length value in the IP Header field.\nBit 3 IPHE: IP header error\nWhen set, this bit indicates either that the 16-bit IPv4 header checksum calculated by the \ncore does not match the received checksum bytes, or that the IP datagram version is not \nconsistent with the Ethernet Type value.\nBits 2:0 IPPT: IP payload type\nif IPv4 checksum offload is activated (IPCO=1, ETH_MACCR bit 10), these bits \nindicate the type of payload encapsulated in the IP datagram. These bits are ‘00’ if there is an IP \nheader error or fragmented IP.\n– 000: Unknown or did not process IP payload\n– 001: UDP\n– 010: TCP\n– 011: ICMP\n– 1xx: Reserved\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1192/1757\nRM0090 Rev 21\n \n .\n•\nRDES7: Receive descriptor Word7\nThe table below describes the fields that have a different meaning for RDES7 when the \nreceive descriptor is closed and time stamping is enabled.\n \n .\n33.6.9 \nDMA interrupts\nInterrupts can be generated as a result of various events. The ETH_DMASR register \ncontains all the bits that might cause an interrupt. The ETH_DMAIER register contains an \nenable bit for each of the events that can cause an interrupt.\nThere are two groups of interrupts, Normal and Abnormal, as described in the ETH_DMASR \nregister. Interrupts are cleared by writing a 1 to the corresponding bit position. When all the \nenabled interrupts within a group are cleared, the corresponding summary bit is cleared. If \nthe MAC core is the cause for assertion of the interrupt, then any of the TSTS or PMTS bits \nin the ETH_DMASR register is set high.\nInterrupts are not queued and if the interrupt event occurs before the driver has responded \nto it, no additional interrupts are generated. For example, the Receive Interrupt bit \n(ETH_DMASR register [6]) indicates that one or more frames were transferred to the \nSTM32F4xx buffer. The driver must scan all descriptors, from the last recorded position to \nthe first one owned by the DMA.\nAn interrupt is generated only once for simultaneous, multiple events. The driver must scan \nthe ETH_DMASR register for the cause of the interrupt. The interrupt is not generated again \nunless a new interrupting event occurs, after the driver has cleared the appropriate bit in the \nETH_DMASR register. For example, the controller generates a Receive interrupt \n(ETH_DMASR register[6]) and the driver begins reading the ETH_DMASR register. Next, \nreceive buffer unavailable (ETH_DMASR register[7]) occurs. The driver clears the Receive \ninterrupt. Even then, a new interrupt is generated, due to the active or pending Receive \nbuffer unavailable interrupt.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRTSL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw rw rw rw\nrw\nrw\nrw\nBits 31:0 RTSL: Receive frame time stamp low\nThe DMA updates this field with the 32 least significant bits of the time stamp captured for the \ncorresponding receive frame. The DMA updates this field only for the last descriptor of the receive \nframe indicated by last descriptor status bit (RDES0[8]). When this field and the RTSH field in \nRDES7 show all ones, the time stamp must be treated as corrupt.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRTSH\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw rw rw rw\nrw\nrw\nrw\nBits 31:0 RTSH: Receive frame time stamp high\nThe DMA updates this field with the 32 most significant bits of the time stamp captured for the \ncorresponding receive frame. The DMA updates this field only for the last descriptor of the receive \nframe indicated by last descriptor status bit (RDES0[8]).\nWhen this field and RDES7’s RTSL field show all ones, the time stamp must be treated as \ncorrupt.\n\n\n<>\n\nRM0090 Rev 21\n1193/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nFigure 384. Interrupt scheme\n33.7 \nEthernet interrupts\nThe Ethernet controller has two interrupt vectors: one dedicated to normal Ethernet \noperations and the other, used only for the Ethernet wake-up event (with wake-up frame or \nMagic Packet detection) when it is mapped on EXTI lIne19.\nThe first Ethernet vector is reserved for interrupts generated by the MAC and the DMA as \nlisted in the MAC interrupts and DMA interrupts sections.\nThe second vector is reserved for interrupts generated by the PMT on wake-up events. The \nmapping of a wake-up event on EXTI line19 causes the STM32F4xx to exit the low-power \nmode, and generates an interrupt.\nWhen an Ethernet wake-up event mapped on EXTI Line19 occurs and the MAC PMT \ninterrupt is enabled and the EXTI Line19 interrupt, with detection on rising edge, is also \nenabled, both interrupts are generated.\nA watchdog timer (see ETH_DMARSWTR register) is given for flexible control of the RS bit \n(ETH_DMASR register). When this watchdog timer is programmed with a non-zero value, it \ngets activated as soon as the RxDMA completes a transfer of a received frame to system \nmemory without asserting the Receive Status because it is not enabled in the corresponding \nReceive descriptor (RDES1[31]). When this timer runs out as per the programmed value, \nthe RS bit is set and the interrupt is asserted if the corresponding RIE is enabled in the \nETH_DMAIER register. This timer is disabled before it runs out, when a frame is transferred \nto memory and the RS is set because it is enabled for that descriptor.\nAND\nAND\nOR\nOR\nAND\nNIS\nNISE\nAND\nAIS\nAISE\nOR\nInterrupt\nTS\nTIE\nFBES\nFBEIE\nAI15646\nPMTI\nTSTI\nMMCI\nAND\nTBUS\nTBUIE\nAND\nRS\nRIE\nAND\nERS\nERIE\nAND\nTPSS\nTPSSIE\nAND\nTJTS\nTJTIE\nAND\nROS\nROIE\nAND\nTUS\nTUIE\nAND\nRBU\nRBUIE\nAND\nRPSS\nRPSSIE\nAND\nRWTS\nRWTIE\nAND\nETS\nETIE\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1194/1757\nRM0090 Rev 21\nNote:\nReading the PMT control and status register automatically clears the Wake-up Frame \nReceived and Magic Packet Received PMT interrupt flags. However, since the registers for \nthese flags are in the CLK_RX domain, there may be a significant delay before this update \nis visible by the firmware. The delay is especially long when the RX clock is slow (in 10 Mbit \nmode) and when the AHB bus is high-frequency.\nSince interrupt requests from the PMT to the CPU are based on the same registers in the \nCLK_RX domain, the CPU may spuriously call the interrupt routine a second time even after \nreading PMT_CSR. Thus, it may be necessary that the firmware polls the Wake-up Frame \nReceived and Magic Packet Received bits and exits the interrupt service routine only when \nthey are found to be at ‘0’.\n33.8 \nEthernet register descriptions\nThe peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32-\nbits).\n33.8.1 \nMAC register description\nEthernet MAC configuration register (ETH_MACCR)\nAddress offset: 0x0000\nReset value: 0x0000 8000\nThe MAC configuration register is the operation mode register of the MAC. It establishes \nreceive and transmit operating modes.\n \n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCSTF\nReserved\nWD\nJD\nReserved\nIFG\nCSD\nReserved\nFES\nROD\nLM\nDM\nIPCO\nRD\nReserved\nAPCS\nBL\nDC\nTE\nRE\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:26 Reserved, must be kept at reset value.\nBit 25\nCSTF: CRC stripping for Type frames\nWhen set, the last 4 bytes (FCS) of all frames of Ether type (type field greater than 0x0600) \nare stripped and dropped before forwarding the frame to the application. \nBit 24Reserved, must be kept at reset value.\nBit 23 WD: Watchdog disable\nWhen this bit is set, the MAC disables the watchdog timer on the receiver, and can receive \nframes of up to 16 384 bytes.\nWhen this bit is reset, the MAC allows no more than 2 048 bytes of the frame being received \nand cuts off any bytes received after that.\nBit 22 JD: Jabber disable\nWhen this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer \nframes of up to 16 384 bytes.\nWhen this bit is reset, the MAC cuts off the transmitter if the application sends out more than \n2 048 bytes of data during transmission.\nBits 21:20 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n1195/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nBits 19:17 IFG: Interframe gap\nThese bits control the minimum interframe gap between frames during transmission.\n000: 96 bit times\n001: 88 bit times\n010: 80 bit times\n….\n111: 40 bit times\nNote: In Half-duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) \nonly. Lower values are not considered.\nBit 16 CSD: Carrier sense disable\nWhen set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame \ntransmission in Half-duplex mode. No error is generated due to Loss of Carrier or No Carrier \nduring such transmission.\nWhen this bit is low, the MAC transmitter generates such errors due to Carrier Sense and \neven aborts the transmissions.\nBit 15 Reserved, must be kept at reset value.\nBit 14 FES: Fast Ethernet speed\nIndicates the speed in Fast Ethernet (MII) mode:\n0: 10 Mbit/s\n1: 100 Mbit/s \nBit 13 ROD: Receive own disable\nWhen this bit is set, the MAC disables the reception of frames in Half-duplex mode.\nWhen this bit is reset, the MAC receives all packets that are given by the PHY while \ntransmitting.\nThis bit is not applicable if the MAC is operating in Full-duplex mode.\nBit 12 LM: Loopback mode\nWhen this bit is set, the MAC operates in loopback mode at the MII. The MII receive clock \ninput (RX_CLK) is required for the loopback to work properly, as the transmit clock is not \nlooped-back internally.\nBit 11 DM: Duplex mode\nWhen this bit is set, the MAC operates in a Full-duplex mode where it can transmit and \nreceive simultaneously.\nBit 10 IPCO: IPv4 checksum offload\nWhen set, this bit enables IPv4 checksum checking for received frame payloads' \nTCP/UDP/ICMP headers. When this bit is reset, the checksum offload function in the \nreceiver is disabled and the corresponding PCE and IP HCE status bits (see Table 191) are \nalways cleared.\nBit 9 RD: Retry disable\nWhen this bit is set, the MAC attempts only 1 transmission. When a collision occurs on the \nMII, the MAC ignores the current frame transmission and reports a Frame Abort with \nexcessive collision error in the transmit frame status.\nWhen this bit is reset, the MAC attempts retries based on the settings of BL.\nNote: This bit is applicable only in the Half-duplex mode.\nBit 8 Reserved, must be kept at reset value.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1196/1757\nRM0090 Rev 21\nBit 7 APCS: Automatic pad/CRC stripping\nWhen this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the \nlength’s field value is less than or equal to 1 500 bytes. All received frames with length field \ngreater than or equal to 1 501 bytes are passed on to the application without stripping the \nPad/FCS field.\nWhen this bit is reset, the MAC passes all incoming frames unmodified.\nBits 6:5 BL: Back-off limit\nThe Back-off limit determines the random integer number (r) of slot time delays (4 096 bit \ntimes for 1000 Mbit/s and 512 bit times for 10/100 Mbit/s) the MAC waits before \nrescheduling a transmission attempt during retries after a collision.\nNote: This bit is applicable only to Half-duplex mode.\n00: k = min (n, 10)\n01: k = min (n, 8)\n10: k = min (n, 4)\n11: k = min (n, 1),\nwhere n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < \n2k\nBit 4 DC: Deferral check\nWhen this bit is set, the deferral check function is enabled in the MAC. The MAC issues a \nFrame Abort status, along with the excessive deferral error bit set in the transmit frame \nstatus when the transmit state machine is deferred for more than 24 288 bit times in 10/100-\nMbit/s mode. Deferral begins when the transmitter is ready to transmit, but is prevented \nbecause of an active CRS (carrier sense) signal on the MII. Defer time is not cumulative. If \nthe transmitter defers for 10 000 bit times, then transmits, collides, backs off, and then has \nto defer again after completion of back-off, the deferral timer resets to 0 and restarts.\nWhen this bit is reset, the deferral check function is disabled and the MAC defers until the \nCRS signal goes inactive. This bit is applicable only in Half-duplex mode.\nBit 3 TE: Transmitter enable\nWhen this bit is set, the transmit state machine of the MAC is enabled for transmission on \nthe MII. When this bit is reset, the MAC transmit state machine is disabled after the \ncompletion of the transmission of the current frame, and does not transmit any further \nframes.\nBit 2 RE: Receiver enable\nWhen this bit is set, the receiver state machine of the MAC is enabled for receiving frames \nfrom the MII. When this bit is reset, the MAC receive state machine is disabled after the \ncompletion of the reception of the current frame, and does not receive any further frames \nfrom the MII.\nBits 1:0 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n1197/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet MAC frame filter register (ETH_MACFFR)\nAddress offset: 0x0004\nReset value: 0x0000 0000\nThe MAC frame filter register contains the filter controls for receiving frames. Some of the \ncontrols from this register go to the address check block of the MAC, which performs the \nfirst level of address filtering. The second level of filtering is performed on the incoming \nframe, based on other controls such as pass bad frames and pass control frames.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRA\nReserved\nHPF\nSAF\nSAIF\nPCF\nBFD\nPAM\nDAIF\nHM\nHU\nPM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 RA: Receive all\nWhen this bit is set, the MAC receiver passes all received frames on to the application, \nirrespective of whether they have passed the address filter. The result of the SA/DA filtering \nis updated (pass or fail) in the corresponding bits in the receive status word. When this bit is \nreset, the MAC receiver passes on to the application only those frames that have passed the \nSA/DA address filter.\nBits 30:11 Reserved, must be kept at reset value.\nBit 10 HPF: Hash or perfect filter\nWhen this bit is set and if the HM or HU bit is set, the address filter passes frames that \nmatch either the perfect filtering or the hash filtering.\nWhen this bit is cleared and if the HU or HM bit is set, only frames that match the Hash filter \nare passed.\nBit 9 SAF: Source address filter\nThe MAC core compares the SA field of the received frames with the values programmed in \nthe enabled SA registers. If the comparison matches, then the SAMatch bit in the RxStatus \nword is set high. When this bit is set high and the SA filter fails, the MAC drops the frame.\nWhen this bit is reset, the MAC core forwards the received frame to the application. It also \nforwards the updated SA Match bit in RxStatus depending on the SA address comparison.\nBit 8 SAIF: Source address inverse filtering\nWhen this bit is set, the address check block operates in inverse filtering mode for the SA \naddress comparison. The frames whose SA matches the SA registers are marked as failing \nthe SA address filter.\nWhen this bit is reset, frames whose SA does not match the SA registers are marked as \nfailing the SA address filter.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1198/1757\nRM0090 Rev 21\nEthernet MAC hash table high register (ETH_MACHTHR)\nAddress offset: 0x0008\nReset value: 0x0000 0000\nThe 64-bit Hash table is used for group address filtering. For hash filtering, the contents of \nthe destination address in the incoming frame are passed through the CRC logic, and the \nupper 6 bits in the CRC register are used to index the contents of the Hash table. This CRC \nis a 32-bit value coded by the following polynomial (for more details refer to Section 33.5.3):\nBits 7:6 PCF: Pass control frames\nThese bits control the forwarding of all control frames (including unicast and multicast \nPAUSE frames). Note that the processing of PAUSE control frames depends only on RFCE \nin Flow Control Register[2].\n00: MAC prevents all control frames from reaching the application\n01: MAC forwards all control frames to application except Pause control frames \n10: MAC forwards all control frames to application even if they fail the address filter\n11: MAC forwards control frames that pass the address filter.\nThese bits control the forwarding of all control frames (including unicast and multicast \nPAUSE frames). Note that the processing of PAUSE control frames depends only on RFCE \nin Flow Control register[2].\n00 or 01: MAC prevents all control frames from reaching the application\n10: MAC forwards all control frames to application even if they fail the address filter\n11: MAC forwards control frames that pass the address filter.\nBit 5 BFD: Broadcast frames disable\nWhen this bit is set, the address filters filter all incoming broadcast frames.\nWhen this bit is reset, the address filters pass all received broadcast frames.\nBit 4 PAM: Pass all multicast\nWhen set, this bit indicates that all received frames with a multicast destination address (first \nbit in the destination address field is '1') are passed.\nWhen reset, filtering of multicast frame depends on the HM bit.\nBit 3 DAIF: Destination address inverse filtering\nWhen this bit is set, the address check block operates in inverse filtering mode for the DA \naddress comparison for both unicast and multicast frames.\nWhen reset, normal filtering of frames is performed.\nBit 2 HM: Hash multicast\nWhen set, MAC performs destination address filtering of received multicast frames \naccording to the hash table.\nWhen reset, the MAC performs a perfect destination address filtering for multicast frames, \nthat is, it compares the DA field with the values programmed in DA registers.\nBit 1 HU: Hash unicast\nWhen set, MAC performs destination address filtering of unicast frames according to the \nhash table.\nWhen reset, the MAC performs a perfect destination address filtering for unicast frames, that \nis, it compares the DA field with the values programmed in DA registers.\nBit 0 PM: Promiscuous mode\nWhen this bit is set, the address filters pass all incoming frames regardless of their \ndestination or source address. The SA/DA filter fails status bits in the receive status word \nare always cleared when PM is set.\nG x\n( )\nx32\nx26\nx23\nx22\nx16\nx12\nx11\nx10\nx8\nx7\nx5\nx4\nx2\nx\n1\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n=\n\n\n<>\n\nRM0090 Rev 21\n1199/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nThe most significant bit determines the register to be used (hash table high/hash table low), \nand the other 5 bits determine which bit within the register. A hash value of 0b0 0000 selects \nbit 0 in the selected register, and a value of 0b1 1111 selects bit 31 in the selected register.\nFor example, if the DA of the incoming frame is received as 0x1F52 419C B6AF (0x1F is the \nfirst byte received on the MII interface), then the internally calculated 6-bit Hash value is \n0x2C and the HTH register bit[12] is checked for filtering. If the DA of the incoming frame is \nreceived as 0xA00A 9800 0045, then the calculated 6-bit Hash value is 0x07 and the HTL \nregister bit[7] is checked for filtering.\nIf the corresponding bit value in the register is 1, the frame is accepted. Otherwise, it is \nrejected. If the PAM (pass all multicast) bit is set in the ETH_MACFFR register, then all \nmulticast frames are accepted regardless of the multicast hash values.\nThe Hash table high register contains the higher 32 bits of the multicast Hash table.\n \nEthernet MAC hash table low register (ETH_MACHTLR)\nAddress offset: 0x000C\nReset value: 0x0000 0000\nThe Hash table low register contains the lower 32 bits of the multi-cast Hash table.\n \n \nEthernet MAC MII address register (ETH_MACMIIAR)\nAddress offset: 0x0010\nReset value: 0x0000 0000\nThe MII address register controls the management cycles to the external PHY through the \nmanagement interface.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nHTH\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 HTH: Hash table high\nThis field contains the upper 32 bits of Hash table.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nHTL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 HTL: Hash table low\nThis field contains the lower 32 bits of the Hash table.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPA\nMR\nReserved\nCR\nMW MB\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrc_\nw1\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1200/1757\nRM0090 Rev 21\n \nEthernet MAC MII data register (ETH_MACMIIDR)\nAddress offset: 0x0014\nReset value: 0x0000 0000\nThe MAC MII Data register stores write data to be written to the PHY register located at the \naddress specified in ETH_MACMIIAR. ETH_MACMIIDR also stores read data from the PHY \nregister located at the address specified by ETH_MACMIIAR.\n \n \nBits 31:16 Reserved, must be kept at reset value.\nBits 15:11 PA: PHY address\nThis field tells which of the 32 possible PHY devices are being accessed.\nBits 10:6 MR: MII register\nThese bits select the desired MII register in the selected PHY device.\nBit 5 Reserved, must be kept at reset value.\nBits 4:2 CR: Clock range\nThe CR clock range selection determines the HCLK frequency and is used to decide the \nfrequency of the MDC clock:\nSelection HCLK MDC clock\n000 60-100 MHz HCLK/42\n001 100-150 MHzHCLK/62\n010 20-35 MHz HCLK/16\n011 35-60 MHz HCLK/26\n100 150-180 MHz HCLK/102\n101, 110, 111 Reserved -\nBit 1 MW: MII write\nWhen set, this bit tells the PHY that this is a Write operation using the MII Data register. If this \nbit is not set, this is a Read operation, placing the data in the MII Data register.\nBit 0 MB: MII busy\nThis bit should read a logic 0 before writing to ETH_MACMIIAR and ETH_MACMIIDR. This \nbit must also be reset to 0 during a Write to ETH_MACMIIAR. During a PHY register access, \nthis bit is set to 0b1 by the application to indicate that a read or write access is in progress. \nETH_MACMIIDR (MII Data) should be kept valid until this bit is cleared by the MAC during a \nPHY Write operation. The ETH_MACMIIDR is invalid until this bit is cleared by the MAC \nduring a PHY Read operation. The ETH_MACMIIAR (MII Address) should not be written to \nuntil this bit is cleared.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMD\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 MD: MII data\nThis contains the 16-bit data value read from the PHY after a Management Read operation, \nor the 16-bit data value to be written to the PHY before a Management Write operation.\n\n\n<>\n\nRM0090 Rev 21\n1201/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet MAC flow control register (ETH_MACFCR)\nAddress offset: 0x0018\nReset value: 0x0000 0000\nThe Flow control register controls the generation and reception of the control (Pause \nCommand) frames by the MAC. A write to a register with the Busy bit set to '1' causes the \nMAC to generate a pause control frame. The fields of the control frame are selected as \nspecified in the 802.3x specification, and the Pause Time value from this register is used in \nthe Pause Time field of the control frame. The Busy bit remains set until the control frame is \ntransferred onto the cable. The Host must make sure that the Busy bit is cleared before \nwriting to the register.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPT\nReserved\nZQPD\nReserved\nPLT\nUPFD\nRFCE\nTFCE\nFCB/\nBPA\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrc_w1\n/rw\nBits 31:16 PT: Pause time\nThis field holds the value to be used in the Pause Time field in the transmit control frame. If \nthe Pause Time bits is configured to be double-synchronized to the MII clock domain, then \nconsecutive write operations to this register should be performed only after at least 4 clock \ncycles in the destination clock domain.\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 ZQPD: Zero-quanta pause disable\nWhen set, this bit disables the automatic generation of Zero-quanta pause control frames on \nthe deassertion of the flow-control signal from the FIFO layer.\nWhen this bit is reset, normal operation with automatic Zero-quanta pause control frame \ngeneration is enabled.\nBit 6 Reserved, must be kept at reset value.\nBits 5:4 PLT: Pause low threshold\nThis field configures the threshold of the Pause timer at which the Pause frame is \nautomatically retransmitted. The threshold values should always be less than the Pause \nTime configured in bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, \nthen a second PAUSE frame is automatically transmitted if initiated at 228 (256 – 28) slot-\ntimes after the first PAUSE frame is transmitted. \nSelection Threshold\n00 Pause time minus 4 slot times\n01 Pause time minus 28 slot times\n10 Pause time minus 144 slot times\n11 Pause time minus 256 slot times\nSlot time is defined as time taken to transmit 512 bits (64 bytes) on the MII interface.\nBit 3 UPFD: Unicast pause frame detect\nWhen this bit is set, the MAC detects the Pause frames with the station’s unicast address \nspecified in the ETH_MACA0HR and ETH_MACA0LR registers, in addition to detecting \nPause frames with the unique multicast address.\nWhen this bit is reset, the MAC detects only a Pause frame with the unique multicast \naddress specified in the 802.3x standard.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1202/1757\nRM0090 Rev 21\nEthernet MAC VLAN tag register (ETH_MACVLANTR)\nAddress offset: 0x001C\nReset value: 0x0000 0000\nThe VLAN tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN frames. \nThe MAC compares the 13th and 14th bytes of the receiving frame (Length/Type) with \n0x8100, and the following 2 bytes are compared with the VLAN tag; if a match occurs, the \nreceived VLAN bit in the receive frame status is set. The legal length of the frame is \nincreased from 1518 bytes to 1522 bytes.\n \nBit 2 RFCE: Receive flow control enable\nWhen this bit is set, the MAC decodes the received Pause frame and disables its transmitter \nfor a specified (Pause Time) time.\nWhen this bit is reset, the decode function of the Pause frame is disabled.\nBit 1 TFCE: Transmit flow control enable\nIn Full-duplex mode, when this bit is set, the MAC enables the flow control operation to \ntransmit Pause frames. When this bit is reset, the flow control operation in the MAC is \ndisabled, and the MAC does not transmit any Pause frames.\nIn Half-duplex mode, when this bit is set, the MAC enables the back-pressure operation. \nWhen this bit is reset, the back pressure feature is disabled.\nBit 0 FCB/BPA: Flow control busy/back pressure activate\nThis bit initiates a Pause Control frame in Full-duplex mode and activates the back pressure \nfunction in Half-duplex mode if TFCE bit is set.\nIn Full-duplex mode, this bit should be read as 0 before writing to the Flow control register. \nTo initiate a Pause control frame, the Application must set this bit to 1. During a transfer of \nthe Control frame, this bit continues to be set to signify that a frame transmission is in \nprogress. After completion of the Pause control frame transmission, the MAC resets this bit \nto 0. The Flow control register should not be written to until this bit is cleared.\nIn Half-duplex mode, when this bit is set (and TFCE is set), back pressure is asserted by the \nMAC core. During back pressure, when the MAC receives a new frame, the transmitter \nstarts sending a JAM pattern resulting in a collision. When the MAC is configured to Full-\nduplex mode, the BPA is automatically disabled.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nVLANTC\nVLANTI\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n1203/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n \nEthernet MAC remote wake-up frame filter register (ETH_MACRWUFFR)\nAddress offset: 0x0028\nReset value: 0x0000 0000\nThis is the address through which the remote wake-up frame filter registers are written/read \nby the application. The Wake-up frame filter register is actually a pointer to eight (not \ntransparent) such wake-up frame filter registers. Eight sequential write operations to this \naddress with the offset (0x0028) write all wake-up frame filter registers. Eight sequential \nread operations from this address with the offset (0x0028) read all wake-up frame filter \nregisters. This register contains the higher 16 bits of the 7th MAC address. Refer to Remote \nwake-up frame filter register section for additional information.\nFigure 385. Ethernet MAC remote wake-up frame filter register (ETH_MACRWUFFR)\nBits 31:17 Reserved, must be kept at reset value.\nBit 16 VLANTC: 12-bit VLAN tag comparison\nWhen this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is \nused for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the \ncorresponding field in the received VLAN-tagged frame.\nWhen this bit is reset, all 16 bits of the received VLAN frame’s fifteenth and sixteenth bytes \nare used for comparison.\nBits 15:0 VLANTI: VLAN tag identifier (for receive frames)\nThis contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth \nand sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the user \npriority, Bit[12] is the canonical format indicator (CFI) and bits[11:0] are the VLAN tag’s VLAN \nidentifier (VID) field. When the VLANTC bit is set, only the VID (bits[11:0]) is used for \ncomparison.\nIf VLANTI (VLANTI[11:0] if VLANTC is set) is all zeros, the MAC does not check the fifteenth \nand sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field value \nof 0x8100 as VLAN frames.\nFilter 0 Byte Mask\nFilter 1 Byte Mask\nFilter 2 Byte Mask\nFilter 3 Byte Mask\nRSVD\nFilter 3\nCommand\nRSVD\nFilter 2\nCommand\nRSVD\nFilter 1\nCommand\nRSVD\nFilter 0\nCommand\nFilter 3 Offset\nFilter 2 Offset\nFilter 1 Offset\nFilter 0 Offset\nFilter 1 CRC - 16\nFilter 0 CRC - 16\nFilter 3 CRC - 16\nFilter 2 CRC - 16\nWakeup frame filter reg0\nWakeup frame filter reg1\nWakeup frame filter reg2\nWakeup frame filter reg3\nWakeup frame filter reg4\nWakeup frame filter reg5\nWakeup frame filter reg6\nWakeup frame filter reg7\nai15648\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1204/1757\nRM0090 Rev 21\nEthernet MAC PMT control and status register (ETH_MACPMTCSR)\nAddress offset: 0x002C\nReset value: 0x0000 0000\nThe ETH_MACPMTCSR programs the request wake-up events and monitors the wake-up \nevents.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nWFFRPR\nReserved\nGU\nReserved\nWFR\nMPR\nReserved\nWFE\nMPE\nPD\nrs\nRes.\nrw\nrc_r rc_r\nrw\nrw\nrs\nBit 31 WFFRPR: Wake-up frame filter register pointer reset\nWhen set, it resets the Remote wake-up frame filter register pointer to 0b000. It is \nautomatically cleared after 1 clock cycle.\nBits 30:10 Reserved, must be kept at reset value.\nBit 9 GU: Global unicast\nWhen set, it enables any unicast packet filtered by the MAC (DAF) address recognition to be \na wake-up frame.\nBits 8:7 Reserved, must be kept at reset value.\nBit 6 WFR: Wake-up frame received\nWhen set, this bit indicates the power management event was generated due to reception of \na wake-up frame. This bit is cleared by a read into this register.\nBit 5 MPR: Magic packet received\nWhen set, this bit indicates the power management event was generated by the reception of \na Magic Packet. This bit is cleared by a read into this register.\nBits 4:3 Reserved, must be kept at reset value.\nBit 2 WFE: Wake-up frame enable\nWhen set, this bit enables the generation of a power management event due to wake-up \nframe reception.\nBit 1 MPE: Magic Packet enable\nWhen set, this bit enables the generation of a power management event due to Magic \nPacket reception.\nBit 0 PD: Power down\nWhen this bit is set, all received frames are dropped. This bit is cleared automatically when \na magic packet or wake-up frame is received, and Power-down mode is disabled. Frames \nreceived after this bit is cleared are forwarded to the application. This bit must only be set \nwhen either the Magic Packet Enable or Wake-up Frame Enable bit is set high.\n\n\n<>\n\nRM0090 Rev 21\n1205/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet MAC debug register (ETH_MACDBGR)\nAddress offset: 0x0034\nReset value: 0x0000 0000\nThis debug register gives the status of all the main modules of the transmit and receive data \npaths and the FIFOs. An all-zero status indicates that the MAC core is in Idle state (and \nFIFOs are empty) and no activity is going on in the data paths.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTFF\nTFNE\nReserved\nTFWA\nTFRS\nMTP\nMTFCS\nMMTEA\nReserved\nRFFL\nReserved\nRFRCS\nRFWRA\nReserved\nMSFRWCS\nMMRPEA\nro\nro\nro\nro\nro\nro\nro\nro\nro\nro\nro\nro\nro\nro\nro\nro\nro\nBits 31:26 Reserved, must be kept at reset value.\nBit 25 TFF: Tx FIFO full\nWhen high, it indicates that the Tx FIFO is full and hence no more frames are accepted for \ntransmission.\nBit 24 TFNE: Tx FIFO not empty\nWhen high, it indicates that the TxFIFO is not empty and has some data left for \ntransmission.\nBit 23 Reserved, must be kept at reset value.\nBit 22 TFWA: Tx FIFO write active\nWhen high, it indicates that the TxFIFO write controller is active and transferring data to the \nTxFIFO.\nBits 21:20 TFRS: Tx FIFO read status\nThis indicates the state of the TxFIFO read controller:\n00: Idle state\n01: Read state (transferring data to the MAC transmitter)\n10: Waiting for TxStatus from MAC transmitter\n11: Writing the received TxStatus or flushing the TxFIFO\nBit 19 MTP: MAC transmitter in pause\nWhen high, it indicates that the MAC transmitter is in Pause condition (in full-duplex mode \nonly) and hence does not schedule any frame for transmission\nBits 18:17 MTFCS: MAC transmit frame controller status\nThis indicates the state of the MAC transmit frame controller:\n00: Idle\n01: Waiting for Status of previous frame or IFG/backoff period to be over\n10: Generating and transmitting a Pause control frame (in full duplex mode)\n11: Transferring input frame for transmission\nBit 16 MMTEA: MAC MII transmit engine active\nWhen high, it indicates that the MAC MII transmit engine is actively transmitting data and \nthat it is not in the Idle state.\nBits 15:10 Reserved, must be kept at reset value.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1206/1757\nRM0090 Rev 21\nBits 9:8 RFFL: Rx FIFO fill level\nThis gives the status of the Rx FIFO fill-level:\n00: RxFIFO empty\n01: RxFIFO fill-level below flow-control de-activate threshold\n10: RxFIFO fill-level above flow-control activate threshold\n11: RxFIFO full\nBit 7 Reserved, must be kept at reset value.\nBits 6:5 RFRCS: Rx FIFO read controller status\nIt gives the state of the Rx FIFO read controller:\n00: IDLE state\n01: Reading frame data\n10: Reading frame status (or time-stamp)\n11: Flushing the frame data and status\nBit 4 RFWRA: Rx FIFO write controller active\nWhen high, it indicates that the Rx FIFO write controller is active and transferring a received \nframe to the FIFO.\nBit 3 Reserved, must be kept at reset value.\nBits 2:1 MSFRWCS: MAC small FIFO read / write controllers status\nWhen high, these bits indicate the respective active state of the small FIFO read and write \ncontrollers of the MAC receive frame controller module.\nBit 0 MMRPEA: MAC MII receive protocol engine active\nWhen high, it indicates that the MAC MII receive protocol engine is actively receiving data \nand is not in the Idle state.\n\n\n<>\n\nRM0090 Rev 21\n1207/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet MAC interrupt status register (ETH_MACSR)\nAddress offset: 0x0038\nReset value: 0x0000 0000\nThe ETH_MACSR register contents identify the events in the MAC that can generate an \ninterrupt.\n \n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTSTS\nReserved\nMMCTS\nMMCRS\nMMCS\nPMTS\nReserved\nrc_r\nr\nr\nr\nr\nBits 15:10 Reserved, must be kept at reset value.\nBit 9 TSTS: Time stamp trigger status \nThis bit is set high when the system time value equals or exceeds the value specified in the \nTarget time high and low registers. This bit is cleared by reading the ETH_PTPTSSR \nregister.\nBits 8:7 Reserved, must be kept at reset value.\nBit 6 MMCTS: MMC transmit status \nThis bit is set high whenever an interrupt is generated in the Ethernet MMC transmit interrupt \nregister (ETH_MMCTIR). This bit is cleared when all the bits in this interrupt register \n(ETH_MMCTIR) are cleared.\nBit 5 MMCRS: MMC receive status \nThis bit is set high whenever an interrupt is generated in the ETH_MMCRIR register. This bit \nis cleared when all the bits in this interrupt register (ETH_MMCRIR) are cleared.\nBit 4 MMCS: MMC status \nThis bit is set high whenever any of bits 6:5 is set high. It is cleared only when both bits are \nlow.\nBit 3 PMTS: PMT status \nThis bit is set whenever a Magic packet or Wake-on-LAN frame is received in Power-down \nmode (see bits 5 and 6 in the ETH_MACPMTCSR register Ethernet MAC PMT control and \nstatus register (ETH_MACPMTCSR)). This bit is cleared when both bits[6:5], of this last \nregister, are cleared due to a read operation to the ETH_MACPMTCSR register.\nBits 2:0 Reserved, must be kept at reset value.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1208/1757\nRM0090 Rev 21\nEthernet MAC interrupt mask register (ETH_MACIMR)\nAddress offset: 0x003C\nReset value: 0x0000 0000\nThe ETH_MACIMR register bits make it possible to mask the interrupt signal due to the \ncorresponding event in the ETH_MACSR register.\n \n \nEthernet MAC address 0 high register (ETH_MACA0HR)\nAddress offset: 0x0040\nReset value: 0x8000 FFFF\nThe MAC address 0 high register holds the upper 16 bits of the 6-byte first MAC address of \nthe station. Note that the first DA byte that is received on the MII interface corresponds to \nthe LS Byte (bits [7:0]) of the MAC address low register. For example, if 0x1122 3344 5566 \nis received (0x11 is the first byte) on the MII as the destination address, then the MAC \naddress 0 register [47:0] is compared with 0x6655 4433 2211.\n \n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTSTIM\nReserved\nPMTIM\nReserved\nrw\nrw\nBits 15:10 Reserved, must be kept at reset value.\nBit 9 TSTIM: Time stamp trigger interrupt mask \nWhen set, this bit disables the time stamp interrupt generation.\nBits 8:4 Reserved, must be kept at reset value.\nBit 3 PMTIM: PMT interrupt mask \nWhen set, this bit disables the assertion of the interrupt signal due to the setting of the PMT \nStatus bit in ETH_MACSR.\nBits 2:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMO\nReserved\nMACA0H\n1\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 MO: Always 1.\nBits 30:16 Reserved, must be kept at reset value.\nBits 15:0 MACA0H: MAC address0 high [47:32]\nThis field contains the upper 16 bits (47:32) of the 6-byte MAC address0. This is used by the \nMAC for filtering for received frames and for inserting the MAC address in the transmit flow \ncontrol (Pause) frames.\n\n\n<>\n\nRM0090 Rev 21\n1209/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet MAC address 0 low register (ETH_MACA0LR)\nAddress offset: 0x0044\nReset value: 0xFFFF FFFF\nThe MAC address 0 low register holds the lower 32 bits of the 6-byte first MAC address of \nthe station.\n \n \nEthernet MAC address 1 high register (ETH_MACA1HR)\nAddress offset: 0x0048\nReset value: 0x0000 FFFF\nThe MAC address 1 high register holds the upper 16 bits of the 6-byte second MAC address \nof the station.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMACA0L\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 MACA0L: MAC address0 low [31:0]\nThis field contains the lower 32 bits of the 6-byte MAC address0. This is used by the MAC \nfor filtering for received frames and for inserting the MAC address in the transmit flow control \n(Pause) frames.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nAE SA\nMBC\nReserved\nMACA1H\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 AE: Address enable\nWhen this bit is set, the address filters use the MAC address1 for perfect filtering. When this \nbit is cleared, the address filters ignore the address for filtering.\nBit 30 SA: Source address\nWhen this bit is set, the MAC address1[47:0] is used for comparison with the SA fields of the \nreceived frame.\nWhen this bit is cleared, the MAC address1[47:0] is used for comparison with the DA fields \nof the received frame.\nBits 29:24 MBC: Mask byte control\nThese bits are mask control bits for comparison of each of the MAC address1 bytes. When \nthey are set high, the MAC core does not compare the corresponding byte of received \nDA/SA with the contents of the MAC address1 registers. Each bit controls the masking of the \nbytes as follows:\n– Bit 29: ETH_MACA1HR [15:8]\n– Bit 28: ETH_MACA1HR [7:0]\n– Bit 27: ETH_MACA1LR [31:24]\n…\n– Bit 24: ETH_MACA1LR [7:0]\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1210/1757\nRM0090 Rev 21\nEthernet MAC address1 low register (ETH_MACA1LR)\nAddress offset: 0x004C\nReset value: 0xFFFF FFFF\nThe MAC address 1 low register holds the lower 32 bits of the 6-byte second MAC address \nof the station.\n \n \nEthernet MAC address 2 high register (ETH_MACA2HR)\nAddress offset: 0x0050\nReset value: 0x0000 FFFF\nThe MAC address 2 high register holds the upper 16 bits of the 6-byte second MAC address \nof the station.\n \nBits 23:16 Reserved, must be kept at reset value.\nBits 15:0 MACA1H: MAC address1 high [47:32]\nThis field contains the upper 16 bits (47:32) of the 6-byte second MAC address.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMACA1L\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 MACA1L: MAC address1 low [31:0]\nThis field contains the lower 32 bits of the 6-byte MAC address1. The content of this field is \nundefined until loaded by the application after the initialization process.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nAE SA\nMBC\nReserved\nMACA2H\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n1211/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n \nEthernet MAC address 2 low register (ETH_MACA2LR)\nAddress offset: 0x0054\nReset value: 0xFFFF FFFF\nThe MAC address 2 low register holds the lower 32 bits of the 6-byte second MAC address \nof the station.\n \n \nBit 31 AE: Address enable\nWhen this bit is set, the address filters use the MAC address2 for perfect filtering. When \nreset, the address filters ignore the address for filtering.\nBit 30 SA: Source address\nWhen this bit is set, the MAC address 2 [47:0] is used for comparison with the SA fields of \nthe received frame.\nWhen this bit is reset, the MAC address 2 [47:0] is used for comparison with the DA fields of \nthe received frame.\nBits 29:24 MBC: Mask byte control\nThese bits are mask control bits for comparison of each of the MAC address2 bytes. When \nset high, the MAC core does not compare the corresponding byte of received DA/SA with the \ncontents of the MAC address 2 registers. Each bit controls the masking of the bytes as \nfollows:\n– Bit 29: ETH_MACA2HR [15:8]\n– Bit 28: ETH_MACA2HR [7:0]\n– Bit 27: ETH_MACA2LR [31:24]\n…\n– Bit 24: ETH_MACA2LR [7:0]\nBits 23:16 Reserved, must be kept at reset value.\nBits 15:0 MACA2H: MAC address2 high [47:32]\nThis field contains the upper 16 bits (47:32) of the 6-byte MAC address2.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMACA2L\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 MACA2L: MAC address2 low [31:0]\nThis field contains the lower 32 bits of the 6-byte second MAC address2. The content of this \nfield is undefined until loaded by the application after the initialization process.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1212/1757\nRM0090 Rev 21\nEthernet MAC address 3 high register (ETH_MACA3HR)\nAddress offset: 0x0058\nReset value: 0x0000 FFFF\nThe MAC address 3 high register holds the upper 16 bits of the 6-byte second MAC address \nof the station.\n \n \nEthernet MAC address 3 low register (ETH_MACA3LR)\nAddress offset: 0x005C\nReset value: 0xFFFF FFFF\nThe MAC address 3 low register holds the lower 32 bits of the 6-byte second MAC address \nof the station.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nAE SA\nMBC\nReserved\nMACA3H\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 AE: Address enable\nWhen this bit is set, the address filters use the MAC address3 for perfect filtering. When this \nbit is cleared, the address filters ignore the address for filtering.\nBit 30 SA: Source address\nWhen this bit is set, the MAC address 3 [47:0] is used for comparison with the SA fields of the \nreceived frame.\nWhen this bit is cleared, the MAC address 3[47:0] is used for comparison with the DA fields \nof the received frame.\nBits 29:24 MBC: Mask byte control\nThese bits are mask control bits for comparison of each of the MAC address3 bytes. When \nthese bits are set high, the MAC core does not compare the corresponding byte of received \nDA/SA with the contents of the MAC address 3 registers. Each bit controls the masking of the \nbytes as follows:\n– Bit 29: ETH_MACA3HR [15:8]\n– Bit 28: ETH_MACA3HR [7:0]\n– Bit 27: ETH_MACA3LR [31:24]\n…\n– Bit 24: ETH_MACA3LR [7:0]\nBits 23:16 Reserved, must be kept at reset value.\nBits 15:0 MACA3H: MAC address3 high [47:32]\nThis field contains the upper 16 bits (47:32) of the 6-byte MAC address3.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMACA3L\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 MACA3L: MAC address3 low [31:0]\nThis field contains the lower 32 bits of the 6-byte second MAC address3. The content of this \nfield is undefined until loaded by the application after the initialization process.\n\n\n<>\n\nRM0090 Rev 21\n1213/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n33.8.2 \nMMC register description\nEthernet MMC control register (ETH_MMCCR)\nAddress offset: 0x0100\nReset value: 0x0000 0000\nThe Ethernet MMC Control register establishes the operating mode of the management \ncounters.\n \n \nEthernet MMC receive interrupt register (ETH_MMCRIR)\nAddress offset: 0x0104\nReset value: 0x0000 0000\nThe Ethernet MMC receive interrupt register maintains the interrupts generated when \nreceive statistic counters reach half their maximum values. (MSB of the counter is set.) It is \na 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMCFHP\nMCP\nMCF\nROR\nCSR\nCR\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:6 Reserved, must be kept at reset value.\nBit 5\nMCFHP: MMC counter Full-Half preset\nWhen MCFHP is low and bit4 is set, all MMC counters get preset to almost-half value. All \nframe-counters get preset to 0x7FFF_FFF0 (half - 16)\nWhen MCFHP is high and bit4 is set, all MMC counters get preset to almost-full value. All \nframe-counters get preset to 0xFFFF_FFF0 (full - 16)\nBit 4\nMCP: MMC counter preset\nWhen set, all counters are initialized or preset to almost full or almost half as per\nBit5 above. This bit is cleared automatically after 1 clock cycle. This bit along\nwith bit5 is useful for debugging and testing the assertion of interrupts due to MMC\ncounter becoming half-full or full.\nBit 3 MCF: MMC counter freeze\nWhen set, this bit freezes all the MMC counters to their current value. (None of the MMC \ncounters are updated due to any transmitted or received frame until this bit is cleared to 0. If \nany MMC counter is read with the Reset on Read bit set, then that counter is also cleared in \nthis mode.)\nBit 2 ROR: Reset on read\nWhen this bit is set, the MMC counters is reset to zero after read (self-clearing after reset). \nThe counters are cleared when the least significant byte lane (bits [7:0]) is read.\nBit 1 CSR: Counter stop rollover\nWhen this bit is set, the counter does not roll over to zero after it reaches the maximum \nvalue.\nBit 0 CR: Counter reset\nWhen it is set, all counters are reset. This bit is cleared automatically after 1 clock cycle.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1214/1757\nRM0090 Rev 21\ncaused the interrupt is read. The least significant byte lane (bits [7:0]) of the respective \ncounter must be read in order to clear the interrupt bit.\n \n \nEthernet MMC transmit interrupt register (ETH_MMCTIR)\nAddress offset: 0x0108\nReset value: 0x0000 0000\nThe Ethernet MMC transmit Interrupt register maintains the interrupts generated when \ntransmit statistic counters reach half their maximum values. (MSB of the counter is set.) It is \na 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that \ncaused the interrupt is read. The least significant byte lane (bits [7:0]) of the respective \ncounter must be read in order to clear the interrupt bit.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRGUFS\nReserved\nRFAES\nRFCES\nReserved\nrc_r\nrc_r rc_r\nBits 31:18 Reserved, must be kept at reset value.\nBit 17 RGUFS: Received Good Unicast Frames Status\nThis bit is set when the received, good unicast frames, counter reaches half the maximum \nvalue.\nBits 16:7 Reserved, must be kept at reset value.\nBit 6 RFAES: Received frames alignment error status\nThis bit is set when the received frames, with alignment error, counter reaches half the \nmaximum value.\nBit 5 RFCES: Received frames CRC error status\nThis bit is set when the received frames, with CRC error, counter reaches half the maximum \nvalue.\nBits 4:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTGFS\nReserved\nTGFMSCS\nTGFSCS\nReserved\nrc_r\nrc_r rc_r\nBits 31:22 Reserved, must be kept at reset value.\nBit 21 TGFS: Transmitted good frames status\nThis bit is set when the transmitted, good frames, counter reaches half the maximum value.\nBits 20:16 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n1215/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet MMC receive interrupt mask register (ETH_MMCRIMR)\nAddress offset: 0x010C\nReset value: 0x0000 0000\nThe Ethernet MMC receive interrupt mask register maintains the masks for interrupts \ngenerated when the receive statistic counters reach half their maximum value. (MSB of the \ncounter is set.) It is a 32-bit wide register.\n \n \nBit 15 TGFMSCS: Transmitted good frames more single collision status\nThis bit is set when the transmitted, good frames after more than a single collision, counter \nreaches half the maximum value.\nBit 14 TGFSCS: Transmitted good frames single collision status\nThis bit is set when the transmitted, good frames after a single collision, counter reaches half \nthe maximum value.\nBits 13:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRGUFM\nReserved\nRFAEM\nRFCEM\nReserved\nrw\nrw\nrw\nBits 31:18 Reserved, must be kept at reset value.\nBit 17 RGUFM: Received good unicast frames mask\nSetting this bit masks the interrupt when the received, good unicast frames, counter \nreaches half the maximum value.\nBits 16:7 Reserved, must be kept at reset value.\nBit 6 RFAEM: Received frames alignment error mask\nSetting this bit masks the interrupt when the received frames, with alignment error, counter \nreaches half the maximum value.\nBit 5 RFCEM: Received frame CRC error mask\nSetting this bit masks the interrupt when the received frames, with CRC error, counter \nreaches half the maximum value.\nBits 4:0 Reserved, must be kept at reset value.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1216/1757\nRM0090 Rev 21\nEthernet MMC transmit interrupt mask register (ETH_MMCTIMR)\nAddress offset: 0x0110\nReset value: 0x0000 0000\nThe Ethernet MMC transmit interrupt mask register maintains the masks for interrupts \ngenerated when the transmit statistic counters reach half their maximum value. (MSB of the \ncounter is set). It is a 32-bit wide register.\n \n \nEthernet MMC transmitted good frames after a single collision counter\nregister (ETH_MMCTGFSCCR)\nAddress offset: 0x014C\nReset value: 0x0000 0000\nThis register contains the number of successfully transmitted frames after a single collision \nin Half-duplex mode.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTGFM\nReserved\nTGFMSCM\nTGFSCM\nReserved\nrw\nrw\nrw\nBits 31:22 Reserved, must be kept at reset value.\nBit 21 TGFM: Transmitted good frames mask\nSetting this bit masks the interrupt when the transmitted, good frames, counter reaches half \nthe maximum value.\nBits 20:16 Reserved, must be kept at reset value.\nBit 15 TGFMSCM: Transmitted good frames more single collision mask\nSetting this bit masks the interrupt when the transmitted good frames after more than a \nsingle collision counter reaches half the maximum value.\nBit 14 TGFSCM: Transmitted good frames single collision mask\nSetting this bit masks the interrupt when the transmitted good frames after a single collision \ncounter reaches half the maximum value.\nBits 13:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTGFSCC\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 TGFSCC: Transmitted good frames single collision counter\nTransmitted good frames after a single collision counter.\n\n\n<>\n\nRM0090 Rev 21\n1217/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet MMC transmitted good frames after more than a single collision \ncounter register (ETH_MMCTGFMSCCR)\nAddress offset: 0x0150\nReset value: 0x0000 0000\nThis register contains the number of successfully transmitted frames after more than a \nsingle collision in Half-duplex mode.\n \n \nEthernet MMC transmitted good frames counter register (ETH_MMCTGFCR)\nAddress offset: 0x0168\nReset value: 0x0000 0000\nThis register contains the number of good frames transmitted.\n \n \nEthernet MMC received frames with CRC error counter register \n(ETH_MMCRFCECR)\nAddress offset: 0x0194\nReset value: 0x0000 0000\nThis register contains the number of frames received with CRC error.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTGFMSCC\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 TGFMSCC: Transmitted good frames more single collision counter\nTransmitted good frames after more than a single collision counter\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTGFC\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 TGFC: Transmitted good frames counter\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRFCEC\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 RFCEC: Received frames CRC error counter\nReceived frames with CRC error counter\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1218/1757\nRM0090 Rev 21\nEthernet MMC received frames with alignment error counter register \n(ETH_MMCRFAECR)\nAddress offset: 0x0198\nReset value: 0x0000 0000\nThis register contains the number of frames received with alignment (dribble) error.\n \n \nMMC received good unicast frames counter register (ETH_MMCRGUFCR)\nAddress offset: 0x01C4\nReset value: 0x0000 0000\nThis register contains the number of good unicast frames received.\n \n \n33.8.3 \nIEEE 1588 time stamp registers\nThis section describes the registers required to support precision network clock \nsynchronization functions under the IEEE 1588 standard.\nEthernet PTP time stamp control register (ETH_PTPTSCR)\nAddress offset: 0x0700\nReset value: 0x0000 00002000\nThis register controls the time stamp generation and update logic.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRFAEC\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 RFAEC: Received frames alignment error counter\nReceived frames with alignment error counter\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRGUFC\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 RGUFC: Received good unicast frames counter\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTSPFFMAE\nTSCNT\nTSSMRME\nTSSEME\nTSSIPV4FE\nTSSIPV6FE\nTSSPTPOEFE\nTSPTPPSV2E\nTSSSR\nTSSARFE\nReserved\nTTSARU\nTSITE\nTSSTU\nTSSTI\nTSFCU\nTSE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n1219/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n \nBits 31:19 Reserved, must be kept at reset value.\nBit 18 TSPFFMAE: Time stamp PTP frame filtering MAC address enable\nWhen set, this bit uses the MAC address (except for MAC address 0) to filter the PTP frames \nwhen PTP is sent directly over Ethernet.\nBits 17:16 TSCNT: Time stamp clock node type\nThe following are the available types of clock node:\n00: Ordinary clock\n01: Boundary clock\n10: End-to-end transparent clock\n11: Peer-to-peer transparent clock\nBit 15 TSSMRME: Time stamp snapshot for message relevant to master enable\nWhen this bit is set, the snapshot is taken for messages relevant to the master node only. \nWhen this bit is cleared the snapshot is taken for messages relevant to the slave node only. \nThis is valid only for the ordinary clock and boundary clock nodes.\nBit 14 TSSEME: Time stamp snapshot for event message enable\nWhen this bit is set, the time stamp snapshot is taken for event messages only (SYNC, \nDelay_Req, Pdelay_Req or Pdelay_Resp). When this bit is cleared the snapshot is taken for \nall other messages except for Announce, Management and Signaling.\nBit 13 TSSIPV4FE: Time stamp snapshot for IPv4 frames enable\nWhen this bit is set, the time stamp snapshot is taken for IPv4 frames.\nBit 12 TSSIPV6FE: Time stamp snapshot for IPv6 frames enable\nWhen this bit is set, the time stamp snapshot is taken for IPv6 frames.\nBit 11 TSSPTPOEFE: Time stamp snapshot for PTP over ethernet frames enable\nWhen this bit is set, the time stamp snapshot is taken for frames which have PTP messages \nin Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP-\nIPEthernet PTP packets.\nBit 10 TSPTPPSV2E: Time stamp PTP packet snooping for version2 format enable\nWhen this bit is set, the PTP packets are snooped using the version 2 format. When the bit is \ncleared, the PTP packets are snooped using the version 1 format.\nNote: IEEE 1588 Version 1 and Version 2 formats as indicated in IEEE standard 1588-2008 \n(Revision of IEEE STD. 1588-2002).\nBit 9 TSSSR: Time stamp subsecond rollover: digital or binary rollover control\nWhen this bit is set, the Time stamp low register rolls over when the subsecond counter \nreaches the value 0x3B9A C9FF (999 999 999 in decimal), and increments the Time Stamp \n(high) seconds.\nWhen this bit is cleared, the rollover value of the subsecond register reaches 0x7FFF FFFF. \nThe subsecond increment has to be programmed correctly depending on the PTP’s \nreference clock frequency and this bit value.\nBit 8 TSSARFE: Time stamp snapshot for all received frames enable\nWhen this bit is set, the time stamp snapshot is enabled for all frames received by the core.\nBits 7:6 Reserved, must be kept at reset value.\nBit 5 TSARU: Time stamp addend register update\nWhen this bit is set, the Time stamp addend register’s contents are updated to the PTP block \nfor fine correction. This bit is cleared when the update is complete. This register bit must be \nread as zero before you can set it.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1220/1757\nRM0090 Rev 21\nThe table below indicates the messages for which a snapshot is taken depending on the \nclock, enable master and enable snapshot for event message register settings.\n \nBit 4 TSITE: Time stamp interrupt trigger enable\nWhen this bit is set, a time stamp interrupt is generated when the system time becomes \ngreater than the value written in the Target time register. When the Time stamp trigger \ninterrupt is generated, this bit is cleared.\nBit 3 TSSTU: Time stamp system time update\nWhen this bit is set, the system time is updated (added to or subtracted from) with the value \nspecified in the Time stamp high update and Time stamp low update registers. Both the \nTSSTU and TSSTI bits must be read as zero before you can set this bit. Once the update is \ncompleted in hardware, this bit is cleared.\nBit 2 TSSTI: Time stamp system time initialize\nWhen this bit is set, the system time is initialized (overwritten) with the value specified in the \nTime stamp high update and Time stamp low update registers. This bit must be read as zero \nbefore you can set it. When initialization is complete, this bit is cleared.\nBit 1 TSFCU: Time stamp fine or coarse update\nWhen set, this bit indicates that the system time stamp is to be updated using the Fine \nUpdate method. When cleared, it indicates the system time stamp is to be updated using the \nCoarse method.\nBit 0 TSE: Time stamp enable\nWhen this bit is set, time stamping is enabled for transmit and receive frames. When this bit \nis cleared, the time stamp function is suspended and time stamps are not added for transmit \nand receive frames. Because the maintained system time is suspended, you must always \ninitialize the time stamp feature (system time) after setting this bit high.\nTable 195. Time stamp snapshot dependency on registers bits\nTSCNT\n(bits 17:16)\nTSSMRME\n(bit 15)(1)\n1.\nN/A = not applicable.\nTSSEME\n(bit 14)\nMessages for which snapshots are taken\n00 or 01\nX(2)\n2.\nX = don’t care.\n0\nSYNC, Follow_Up, Delay_Req, Delay_Resp \n00 or 01\n1\n1\nDelay_Req \n00 or 01\n0\n1\nSYNC \n10\nN/A\n0\nSYNC, Follow_Up, Delay_Req, Delay_Resp \n10\nN/A\n1\nSYNC, Follow_Up \n11\nN/A\n0\nSYNC, Follow_Up, Delay_Req, Delay_Resp, \nPdelay_Req, Pdelay_Resp \n11\nN/A\n1\nSYNC, Pdelay_Req, Pdelay_Resp \n\n\n<>\n\nRM0090 Rev 21\n1221/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet PTP subsecond increment register (ETH_PTPSSIR)\nAddress offset: 0x0704\nReset value: 0x0000 0000\nThis register contains the 8-bit value by which the subsecond register is incremented. In \nCoarse update mode (TSFCU bit in ETH_PTPTSCR), the value in this register is added to \nthe system time every clock cycle of HCLK. In Fine update mode, the value in this register is \nadded to the system time whenever the accumulator gets an overflow.\n \n \nEthernet PTP time stamp high register (ETH_PTPTSHR)\nAddress offset: 0x0708\nReset value: 0x0000 0000\nThis register contains the most significant (higher) 32 time bits. This read-only register \ncontains the seconds system time value. The Time stamp high register, along with Time \nstamp low register, indicates the current value of the system time maintained by the MAC. \nThough it is updated on a continuous basis.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSTSSI\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBits 7:0 STSSI: System time subsecond increment\nThe value programmed in this register is added to the contents of the subsecond value of the \nsystem time in every update.\nFor example, to achieve 20 ns accuracy, the value is: 20 / 0.467 = ~ 43 (or 0x2A).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSTS\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 STS: System time second\nThe value in this field indicates the current value in seconds of the System Time maintained \nby the core.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1222/1757\nRM0090 Rev 21\nEthernet PTP time stamp low register (ETH_PTPTSLR)\nAddress offset: 0x070C\nReset value: 0x0000 0000\nThis register contains the least significant (lower) 32 time bits. This read-only register \ncontains the subsecond system time value.\n \n \nEthernet PTP time stamp high update register (ETH_PTPTSHUR)\nAddress offset: 0x0710\nReset value: 0x0000 0000\nThis register contains the most significant (higher) 32 bits of the time to be written to, added \nto, or subtracted from the System Time value. The Time stamp high update register, along \nwith the Time stamp update low register, initializes or updates the system time maintained \nby the MAC. You have to write both of these registers before setting the TSSTI or TSSTU \nbits in the Time stamp control register.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSTPNS\nSTSS\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBit 31 STPNS: System time positive or negative sign\nThis bit indicates a positive or negative time value. When set, the bit indicates that time \nrepresentation is negative. When cleared, it indicates that time representation is positive. \nBecause the system time should always be positive, this bit is normally zero.\nBits 30:0 STSS: System time subseconds \nThe value in this field has the subsecond time representation, with 0.46 ns accuracy.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTSUS\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 TSUS: Time stamp update second\nThe value in this field indicates the time, in seconds, to be initialized or added to the system \ntime.\n\n\n<>\n\nRM0090 Rev 21\n1223/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet PTP time stamp low update register (ETH_PTPTSLUR)\nAddress offset: 0x0714\nReset value: 0x0000 0000\nThis register contains the least significant (lower) 32 bits of the time to be written to, added \nto, or subtracted from the System Time value.\n \n \nEthernet PTP time stamp addend register (ETH_PTPTSAR)\nAddress offset: 0x0718\nReset value: 0x0000 0000\nThis register is used by the software to readjust the clock frequency linearly to match the \nmaster clock frequency. This register value is used only when the system time is configured \nfor Fine update mode (TSFCU bit in ETH_PTPTSCR). This register content is added to a \n32-bit accumulator in every clock cycle and the system time is updated whenever the \naccumulator overflows.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTSUPNS\nTSUSS\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 TSUPNS: Time stamp update positive or negative sign\nThis bit indicates positive or negative time value. When set, the bit indicates that time \nrepresentation is negative. When cleared, it indicates that time representation is positive. \nWhen TSSTI is set (system time initialization) this bit should be zero. If this bit is set when \nTSSTU is set, the value in the Time stamp update registers is subtracted from the system \ntime. Otherwise it is added to the system time.\nBits 30:0 TSUSS: Time stamp update subseconds\nThe value in this field indicates the subsecond time to be initialized or added to the system \ntime. This value has an accuracy of 0.46 ns (in other words, a value of 0x0000_0001 is \n0.46 ns).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTSA\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 TSA: Time stamp addend\nThis register indicates the 32-bit time value to be added to the Accumulator register to \nachieve time synchronization.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1224/1757\nRM0090 Rev 21\nEthernet PTP target time high register (ETH_PTPTTHR)\nAddress offset: 0x071C\nReset value: 0x0000 0000\nThis register contains the higher 32 bits of time to be compared with the system time for \ninterrupt event generation. The Target time high register, along with Target time low register, \nis used to schedule an interrupt event (TSARU bit in ETH_PTPTSCR) when the system time \nexceeds the value programmed in these registers.\n \n \nEthernet PTP target time low register (ETH_PTPTTLR)\nAddress offset: 0x0720\nReset value: 0x0000 0000\nThis register contains the lower 32 bits of time to be compared with the system time for \ninterrupt event generation.\n \n \nEthernet PTP time stamp status register (ETH_PTPTSSR)\nAddress offset: 0x0728\nReset value: 0x0000 0000\nThis register contains the time stamp status register.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTTSH\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 TTSH: Target time stamp high\nThis register stores the time in seconds. When the time stamp value matches or exceeds \nboth Target time stamp registers, the MAC, if enabled, generates an interrupt.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTTSL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 TTSL: Target time stamp low\nThis register stores the time in (signed) nanoseconds. When the value of the time stamp \nmatches or exceeds both Target time stamp registers, the MAC, if enabled, generates an \ninterrupt.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTSTTR\nTSSO\nro\nro\n\n\n<>\n\nRM0090 Rev 21\n1225/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet PTP PPS control register (ETH_PTPPPSCR)\nAddress offset: 0x072C\nReset value: 0x0000 0000\nThis register controls the frequency of the PPS output.\n \n \nBits 31:2 Reserved, must be kept at reset value.\nBit 1 TSTTR: Time stamp target time reached\nWhen set, this bit indicates that the value of the system time is greater than or equal to the \nvalue specified in the Target time high and low registers. This bit is cleared when the \nETH_PTPTSSR register is read.\nBit 0 TSSO: Time stamp second overflow\nWhen set, this bit indicates that the second value of the time stamp has overflowed beyond \n0xFFFF FFFF.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPPSFREQ\nro\nro\nro\nro\nBits 31:4 Reserved, must be kept at reset value.\nBits 3:0 PPSFREQ: PPS frequency selection\nThe PPS output frequency is set to 2PPSFREQ Hz.\n0000: 1 Hz with a pulse width of 125 ms for binary rollover and, of 100 ms for digital rollover\n0001: 2 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)\n0010: 4 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)\n0011: 8 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)\n0100: 16 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)\n...\n1111: 32768 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)\nNote: If digital rollover is used (TSSSR=1, bit 9 in ETH_PTPTSCR), it is recommended not to \nuse the PPS output with a frequency other than 1 Hz. Otherwise, with digital rollover, \nthe PPS output has irregular waveforms at higher frequencies (though its average \nfrequency is always correct during any one-second window).\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1226/1757\nRM0090 Rev 21\n33.8.4 \nDMA register description\nThis section defines the bits for each DMA register. Non-32 bit accesses are allowed as long \nas the address is word-aligned.\nEthernet DMA bus mode register (ETH_DMABMR)\nAddress offset: 0x1000\nReset value: 0x0002 0101\nThe bus mode register establishes the bus operating modes for the DMA.\n \n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMB\nAAB\nFPM\nUSP\nRDP\nFB\nPM\nPBL\nEDFE\nDSL\nDA\nSR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrs\nBits 31:27 Reserved, must be kept at reset value.\nBit 26 MB: Mixed burst\nWhen this bit is set high and the FB bit is low, the AHB master interface starts all bursts of a \nlength greater than 16 with INCR (undefined burst). When this bit is cleared, it reverts to \nfixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below.\nBit 25 AAB: Address-aligned beats\nWhen this bit is set high and the FB bit equals 1, the AHB interface generates all bursts \naligned to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data \nbuffer’s start address) is not aligned, but subsequent bursts are aligned to the address.\nBit 24 FPM: 4xPBL mode\nWhen set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) \nfour times. Thus the DMA transfers data in a maximum of 4, 8, 16, 32, 64 and 128 beats \ndepending on the PBL value.\nBit 23 USP: Use separate PBL\nWhen set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL \nwhile the PBL value in bits [13:8] is applicable to TxDMA operations only. When this bit is \ncleared, the PBL value in bits [13:8] is applicable for both DMA engines.\nBits 22:17 RDP: Rx DMA PBL\nThese bits indicate the maximum number of beats to be transferred in one RxDMA \ntransaction. This is the maximum value that is used in a single block read/write operation. \nThe RxDMA always attempts to burst as specified in RDP each time it starts a burst transfer \non the host bus. RDP can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. \nAny other value results in undefined behavior.\nThese bits are valid and applicable only when USP is set high.\nBit 16 FB: Fixed burst\nThis bit controls whether the AHB Master interface performs fixed burst transfers or not. \nWhen set, the AHB uses only SINGLE, INCR4, INCR8 or INCR16 during start of normal \nburst transfers. When reset, the AHB uses SINGLE and INCR burst transfer operations.\n\n\n<>\n\nRM0090 Rev 21\n1227/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet DMA transmit poll demand register (ETH_DMATPDR)\nAddress offset: 0x1004\nReset value: 0x0000 0000\nThis register is used by the application to instruct the DMA to poll the transmit descriptor list. \nThe transmit poll demand register enables the Transmit DMA to check whether or not the \ncurrent descriptor is owned by DMA. The Transmit Poll Demand command is given to wake \nup the TxDMA if it is in Suspend mode. The TxDMA can go into Suspend mode due to an \nunderflow error in a transmitted frame or due to the unavailability of descriptors owned by \nBits 15:14 PM: Rx Tx priority ratio\nRxDMA requests are given priority over TxDMA requests in the following ratio:\n00: 1:1\n01: 2:1\n10: 3:1\n11: 4:1\nThis is valid only when the DA bit is cleared.\nBits 13:8 PBL: Programmable burst length\nThese bits indicate the maximum number of beats to be transferred in one DMA transaction. \nThis is the maximum value that is used in a single block read/write operation. The DMA \nalways attempts to burst as specified in PBL each time it starts a burst transfer on the host \nbus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other \nvalue results in undefined behavior. When USP is set, this PBL value is applicable for \nTxDMA transactions only.\nThe PBL values have the following limitations:\n– The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx \nFIFO.\n– The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO.\n– If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx \nFIFO depths must be considered.\n– Do not program out-of-range PBL values, because the system may not behave properly.\nBit 7 EDFE: Enhanced descriptor format enable\nWhen this bit is set, the enhanced descriptor format is enabled and the descriptor size is \nincreased to 32 bytes (8 words). This is required when time stamping is activated (TSE=1, \nETH_PTPTSCR bit 0) or if IPv4 checksum offload is activated (IPCO=1, ETH_MACCR bit \n10).\nBits 6:2 DSL: Descriptor skip length\nThis bit specifies the number of words to skip between two unchained descriptors. The \naddress skipping starts from the end of current descriptor to the start of next descriptor. \nWhen DSL value equals zero, the descriptor table is taken as contiguous by the DMA, in \nRing mode.\nBit 1 DA: DMA Arbitration\n0: Round-robin with Rx:Tx priority given in bits [15:14]\n1: Rx has priority over Tx\nBit 0 SR: Software reset\nWhen this bit is set, the MAC DMA controller resets all MAC Subsystem internal registers \nand logic. It is cleared automatically after the reset operation has completed in all of the core \nclock domains. Read a 0 value in this bit before re-programming any register of the core.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1228/1757\nRM0090 Rev 21\ntransmit DMA. You can issue this command anytime and the TxDMA resets it once it starts \nre-fetching the current descriptor from host memory.\n \n \nEHERNET DMA receive poll demand register (ETH_DMARPDR)\nAddress offset: 0x1008\nReset value: 0x0000 0000\nThis register is used by the application to instruct the DMA to poll the receive descriptor list. \nThe Receive poll demand register enables the receive DMA to check for new descriptors. \nThis command is given to wake up the RxDMA from Suspend state. The RxDMA can go into \nSuspend state only due to the unavailability of descriptors owned by it.\n \n \nEthernet DMA receive descriptor list address register (ETH_DMARDLAR)\nAddress offset: 0x100C\nReset value: 0x0000 0000\nThe Receive descriptor list address register points to the start of the receive descriptor list. \nThe descriptor lists reside in the STM32F4xx's physical memory space and must be word-\naligned. The DMA internally converts it to bus-width aligned address by making the \ncorresponding LS bits low. Writing to the ETH_DMARDLAR register is permitted only when \nreception is stopped. When stopped, the ETH_DMARDLAR register must be written to \nbefore the receive Start command is given.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTPD\nrw\nBits 31:0 TPD: Transmit poll demand\nWhen these bits are written with any value, the DMA reads the current descriptor pointed to \nby the ETH_DMACHTDR register. If that descriptor is not available (owned by Host), \ntransmission returns to the Suspend state and ETH_DMASR register bit 2 is asserted. If the \ndescriptor is available, transmission resumes.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRPD\nrw_wt\nBits 31:0 RPD: Receive poll demand\nWhen these bits are written with any value, the DMA reads the current descriptor pointed to \nby the ETH_DMACHRDR register. If that descriptor is not available (owned by Host), \nreception returns to the Suspended state and ETH_DMASR register bit 7 is not asserted. If \nthe descriptor is available, the Receive DMA returns to active state.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSRL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n1229/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n \nEthernet DMA transmit descriptor list address register (ETH_DMATDLAR)\nAddress offset: 0x1010\nReset value: 0x0000 0000\nThe Transmit descriptor list address register points to the start of the transmit descriptor list. \nThe descriptor lists reside in the STM32F4xx's physical memory space and must be word-\naligned. The DMA internally converts it to bus-width-aligned address by taking the \ncorresponding LSB to low. Writing to the ETH_DMATDLAR register is permitted only when \ntransmission has stopped. Once transmission has stopped, the ETH_DMATDLAR register \ncan be written before the transmission Start command is given.\n \n \nEthernet DMA status register (ETH_DMASR)\nAddress offset: 0x1014\nReset value: 0x0000 0000\nThe Status register contains all the status bits that the DMA reports to the application. The \nETH_DMASR register is usually read by the software driver during an interrupt service \nroutine or polling. Most of the fields in this register cause the host to be interrupted. The \nETH_DMASR register bits are not cleared when read. Writing 1 to (unreserved) bits in \nETH_DMASR register[16:0] clears them and writing 0 has no effect. Each field (bits [16:0]) \ncan be masked by masking the appropriate bit in the ETH_DMAIER register.\n \nBits 31:0 SRL: Start of receive list\nThis field contains the base address of the first descriptor in the receive descriptor list. The \nLSB bits [1/2/3:0] for 32/64/128-bit bus width) are internally ignored and taken as all-zero by \nthe DMA. Hence these LSB bits are read only.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSTL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 STL: Start of transmit list\nThis field contains the base address of the first descriptor in the transmit descriptor list. The \nLSB bits [1/2/3:0] for 32/64/128-bit bus width) are internally ignored and taken as all-zero \nby the DMA. Hence these LSB bits are read-only.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTSTS\nPMTS\nMMCS\nReserved\nEBS\nTPS\nRPS\nNIS\nAIS\nERS\nFBES\nReserved\nETS\nRWTS\nRPSS\nRBUS\nRS\nTUS\nROS\nTJTS\nTBUS\nTPSS\nTS\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1230/1757\nRM0090 Rev 21\n \nBits 31:30 Reserved, must be kept at reset value.\nBit 29 TSTS: Time stamp trigger status\nThis bit indicates an interrupt event in the MAC core's Time stamp generator block. The \nsoftware must read the MAC core’s status register, clearing its source (bit 9), to reset this bit \nto 0. When this bit is high an interrupt is generated if enabled.\nBit 28 PMTS: PMT status\nThis bit indicates an event in the MAC core’s PMT. The software must read the \ncorresponding registers in the MAC core to get the exact cause of interrupt and clear its \nsource to reset this bit to 0. The interrupt is generated when this bit is high if enabled.\nBit 27 MMCS: MMC status\nThis bit reflects an event in the MMC of the MAC core. The software must read the \ncorresponding registers in the MAC core to get the exact cause of interrupt and clear the \nsource of interrupt to make this bit as 0. The interrupt is generated when this bit is high if \nenabled.\nBit 26 Reserved, must be kept at reset value.\nBits 25:23 EBS: Error bits status\nThese bits indicate the type of error that caused a bus error (error response on the AHB \ninterface). Valid only with the fatal bus error bit (ETH_DMASR register [13]) set. This field \ndoes not generate an interrupt.\nBit 231 Error during data transfer by TxDMA \n0 Error during data transfer by RxDMA\nBit 24 1 Error during read transfer\n0 Error during write transfer\nBit 25 1 Error during descriptor access\n0 Error during data buffer access\nBits 22:20 TPS: Transmit process state\nThese bits indicate the Transmit DMA FSM state. This field does not generate an interrupt.\n000: Stopped; Reset or Stop Transmit Command issued\n001: Running; Fetching transmit transfer descriptor\n010: Running; Waiting for status\n011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx \nFIFO)\n100, 101: Reserved for future use\n110: Suspended; Transmit descriptor unavailable or transmit buffer underflow\n111: Running; Closing transmit descriptor\nBits 19:17 RPS: Receive process state \nThese bits indicate the Receive DMA FSM state. This field does not generate an interrupt.\n000: Stopped: Reset or Stop Receive Command issued\n001: Running: Fetching receive transfer descriptor\n010: Reserved for future use\n011: Running: Waiting for receive packet\n100: Suspended: Receive descriptor unavailable\n101: Running: Closing receive descriptor\n110: Reserved for future use\n111: Running: Transferring the receive packet data from receive buffer to host memory\n\n\n<>\n\nRM0090 Rev 21\n1231/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nBit 16 NIS: Normal interrupt summary\nThe normal interrupt summary bit value is the logical OR of the following when the \ncorresponding interrupt bits are enabled in the ETH_DMAIER register:\n– ETH_DMASR [0]: Transmit interrupt\n– ETH_DMASR [2]: Transmit buffer unavailable\n– ETH_DMASR [6]: Receive interrupt\n– ETH_DMASR [14]: Early receive interrupt\nOnly unmasked bits affect the normal interrupt summary bit.\nThis is a sticky bit and it must be cleared (by writing a 1 to this bit) each time a corresponding \nbit that causes NIS to be set is cleared.\nBit 15 AIS: Abnormal interrupt summary\nThe abnormal interrupt summary bit value is the logical OR of the following when the \ncorresponding interrupt bits are enabled in the ETH_DMAIER register:\n– ETH_DMASR [1]:Transmit process stopped\n– ETH_DMASR [3]:Transmit jabber timeout\n– ETH_DMASR [4]: Receive FIFO overflow\n– ETH_DMASR [5]: Transmit underflow\n– ETH_DMASR [7]: Receive buffer unavailable\n– ETH_DMASR [8]: Receive process stopped\n– ETH_DMASR [9]: Receive watchdog timeout\n– ETH_DMASR [10]: Early transmit interrupt\n– ETH_DMASR [13]: Fatal bus error\nOnly unmasked bits affect the abnormal interrupt summary bit.\nThis is a sticky bit and it must be cleared each time a corresponding bit that causes AIS to be \nset is cleared.\nBit 14 ERS: Early receive status\nThis bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt \nETH_DMASR [6] automatically clears this bit.\nBit 13 FBES: Fatal bus error status\nThis bit indicates that a bus error occurred, as detailed in [25:23]. When this bit is set, the \ncorresponding DMA engine disables all its bus accesses.\nBits 12:11 Reserved, must be kept at reset value.\nBit 10 ETS: Early transmit status\nThis bit indicates that the frame to be transmitted was fully transferred to the Transmit FIFO.\nBit 9\nRWTS: Receive watchdog timeout status\nThis bit is asserted when a frame with a length greater than 2 048 bytes is received.\nBit 8 RPSS: Receive process stopped status\nThis bit is asserted when the receive process enters the Stopped state.\nBit 7 RBUS: Receive buffer unavailable status\nThis bit indicates that the next descriptor in the receive list is owned by the host and cannot \nbe acquired by the DMA. Receive process is suspended. To resume processing receive \ndescriptors, the host should change the ownership of the descriptor and issue a Receive Poll \nDemand command. If no Receive Poll Demand is issued, receive process resumes when the \nnext recognized incoming frame is received. ETH_DMASR [7] is set only when the previous \nreceive descriptor was owned by the DMA.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1232/1757\nRM0090 Rev 21\nEthernet DMA operation mode register (ETH_DMAOMR)\nAddress offset: 0x1018\nReset value: 0x0000 0000\nThe operation mode register establishes the Transmit and Receive operating modes and \ncommands. The ETH_DMAOMR register should be the last CSR to be written as part of \nDMA initialization.\n \n \nBit 6 RS: Receive status\nThis bit indicates the completion of the frame reception. Specific frame status information \nhas been posted in the descriptor. Reception remains in the Running state.\nBit 5 TUS: Transmit underflow status\nThis bit indicates that the transmit buffer had an underflow during frame transmission. \nTransmission is suspended and an underflow error TDES0[1] is set.\nBit 4 ROS: Receive overflow status\nThis bit indicates that the receive buffer had an overflow during frame reception. If the partial \nframe is transferred to the application, the overflow status is set in RDES0[11].\nBit 3 TJTS: Transmit jabber timeout status\nThis bit indicates that the transmit jabber timer expired, meaning that the transmitter had \nbeen excessively active. The transmission process is aborted and placed in the Stopped \nstate. This causes the transmit jabber timeout TDES0[14] flag to be asserted.\nBit 2 TBUS: Transmit buffer unavailable status\nThis bit indicates that the next descriptor in the transmit list is owned by the host and cannot \nbe acquired by the DMA. Transmission is suspended. Bits [22:20] explain the transmit \nprocess state transitions. To resume processing transmit descriptors, the host should change \nthe ownership of the bit of the descriptor and then issue a Transmit Poll Demand command.\nBit 1 TPSS: Transmit process stopped status\nThis bit is set when the transmission is stopped.\nBit 0 TS: Transmit status\nThis bit indicates that frame transmission is finished and TDES1[31] is set in the first \ndescriptor.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDTCEFD\nRSF\nDFRF\nReserved\nTSF\nFTF\nReserved\nTTC\nST\nReserved\nFEF\nFUGF\nReserved\nRTC\nOSF\nSR\nReserved\nrw\nrw\nrw\nrw\nrs\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:27 Reserved, must be kept at reset value.\nBit 26 DTCEFD: Dropping of TCP/IP checksum error frames disable\nWhen this bit is set, the core does not drop frames that only have errors detected by the \nreceive checksum offload engine. Such frames do not have any errors (including FCS error) \nin the Ethernet frame received by the MAC but have errors in the encapsulated payload only. \nWhen this bit is cleared, all error frames are dropped if the FEF bit is reset.\n\n\n<>\n\nRM0090 Rev 21\n1233/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nBit 25 RSF: Receive store and forward\nWhen this bit is set, a frame is read from the Rx FIFO after the complete frame has been \nwritten to it, ignoring RTC bits. When this bit is cleared, the Rx FIFO operates in Cut-through \nmode, subject to the threshold specified by the RTC bits.\nBit 24 DFRF: Disable flushing of received frames\nWhen this bit is set, the RxDMA does not flush any frames due to the unavailability of \nreceive descriptors/buffers as it does normally when this bit is cleared (see Receive process \nsuspended).\nBits 23:22 Reserved, must be kept at reset value.\nBit 21 TSF: Transmit store and forward\nWhen this bit is set, transmission starts when a full frame resides in the Transmit FIFO. \nWhen this bit is set, the TTC values specified by the ETH_DMAOMR register bits [16:14] are \nignored.\nWhen this bit is cleared, the TTC values specified by the ETH_DMAOMR register bits \n[16:14] are taken into account.\nThis bit should be changed only when transmission is stopped.\nBit 20 FTF: Flush transmit FIFO\nWhen this bit is set, the transmit FIFO controller logic is reset to its default values and thus \nall data in the Tx FIFO are lost/flushed. This bit is cleared internally when the flushing \noperation is complete. The Operation mode register should not be written to until this bit is \ncleared.\nBits 19:17 Reserved, must be kept at reset value.\nBits 16:14 TTC: Transmit threshold control\nThese three bits control the threshold level of the Transmit FIFO. Transmission starts when \nthe frame size within the Transmit FIFO is larger than the threshold. In addition, full frames \nwith a length less than the threshold are also transmitted. These bits are used only when the \nTSF bit (Bit 21) is cleared.\n000: 64\n001: 128\n010: 192\n011: 256\n100: 40\n101: 32\n110: 24\n111: 16\nBit 13 ST: Start/stop transmission \nWhen this bit is set, transmission is placed in the Running state, and the DMA checks the \ntransmit list at the current position for a frame to be transmitted. Descriptor acquisition is \nattempted either from the current position in the list, which is the transmit list base address \nset by the ETH_DMATDLAR register, or from the position retained when transmission was \nstopped previously. If the current descriptor is not owned by the DMA, transmission enters \nthe Suspended state and the transmit buffer unavailable bit (ETH_DMASR [2]) is set. The \nStart Transmission command is effective only when transmission is stopped. If the command \nis issued before setting the DMA ETH_DMATDLAR register, the DMA behavior is \nunpredictable.\nWhen this bit is cleared, the transmission process is placed in the Stopped state after \ncompleting the transmission of the current frame. The next descriptor position in the transmit \nlist is saved, and becomes the current position when transmission is restarted. The Stop \nTransmission command is effective only when the transmission of the current frame is \ncomplete or when the transmission is in the Suspended state.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1234/1757\nRM0090 Rev 21\nBits 12:8 Reserved, must be kept at reset value.\nBit 7 FEF: Forward error frames\nWhen this bit is set, all frames except runt error frames are forwarded to the DMA.\nWhen this bit is cleared, the Rx FIFO drops frames with error status (CRC error, collision \nerror, giant frame, watchdog timeout, overflow). However, if the frame’s start byte (write) \npointer is already transferred to the read controller side (in Threshold mode), then the \nframes are not dropped. The Rx FIFO drops the error frames if that frame's start byte is not \ntransferred (output) on the ARI bus.\nBit 6 FUGF: Forward undersized good frames\nWhen this bit is set, the Rx FIFO forwards undersized frames (frames with no error and \nlength less than 64 bytes) including pad-bytes and CRC).\nWhen this bit is cleared, the Rx FIFO drops all frames of less than 64 bytes, unless such a \nframe has already been transferred due to lower value of receive threshold (e.g., RTC = 01).\nBit 5 Reserved, must be kept at reset value.\nBits 4:3 RTC: Receive threshold control\nThese two bits control the threshold level of the Receive FIFO. Transfer (request) to DMA \nstarts when the frame size within the Receive FIFO is larger than the threshold. In addition, \nfull frames with a length less than the threshold are transferred automatically.\nNote: Note that value of 11 is not applicable if the configured Receive FIFO size is 128 bytes.\nNote: These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is \nset to 1.\n00: 64\n01: 32\n10: 96\n11: 128\nBit 2 OSF: Operate on second frame\nWhen this bit is set, this bit instructs the DMA to process a second frame of Transmit data \neven before status for first frame is obtained.\nBit 1 SR: Start/stop receive\nWhen this bit is set, the receive process is placed in the Running state. The DMA attempts to \nacquire the descriptor from the receive list and processes incoming frames. Descriptor \nacquisition is attempted from the current position in the list, which is the address set by the \nDMA ETH_DMARDLAR register or the position retained when the receive process was \npreviously stopped. If no descriptor is owned by the DMA, reception is suspended and the \nreceive buffer unavailable bit (ETH_DMASR [7]) is set. The Start Receive command is \neffective only when reception has stopped. If the command was issued before setting the \nDMA ETH_DMARDLAR register, the DMA behavior is unpredictable.\nWhen this bit is cleared, RxDMA operation is stopped after the transfer of the current frame. \nThe next descriptor position in the receive list is saved and becomes the current position \nwhen the receive process is restarted. The Stop Receive command is effective only when \nthe Receive process is in either the Running (waiting for receive packet) or the Suspended \nstate.\nBit 0 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n1235/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet DMA interrupt enable register (ETH_DMAIER)\nAddress offset: 0x101C\nReset value: 0x0000 0000\nThe Interrupt enable register enables the interrupts reported by ETH_DMASR. Setting a bit \nto 1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are \ndisabled.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNISE\nAISE\nERIE\nFBEIE\nReserved\nETIE\nRWTIE\nRPSIE\nRBUIE\nRIE\nTUIE\nROIE\nTJTIE\nTBUIE\nTPSIE\nTIE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:17 Reserved, must be kept at reset value.\nBit 16 NISE: Normal interrupt summary enable\nWhen this bit is set, a normal interrupt is enabled. When this bit is cleared, a normal \ninterrupt is disabled. This bit enables the following bits:\n– ETH_DMASR [0]: Transmit Interrupt\n– ETH_DMASR [2]: Transmit buffer unavailable\n– ETH_DMASR [6]: Receive interrupt\n– ETH_DMASR [14]: Early receive interrupt\nBit 15 AISE: Abnormal interrupt summary enable\nWhen this bit is set, an abnormal interrupt is enabled. When this bit is cleared, an abnormal \ninterrupt is disabled. This bit enables the following bits:\n– ETH_DMASR [1]: Transmit process stopped\n– ETH_DMASR [3]: Transmit jabber timeout\n– ETH_DMASR [4]: Receive overflow\n– ETH_DMASR [5]: Transmit underflow\n– ETH_DMASR [7]: Receive buffer unavailable\n– ETH_DMASR [8]: Receive process stopped\n– ETH_DMASR [9]: Receive watchdog timeout\n– ETH_DMASR [10]: Early transmit interrupt\n– ETH_DMASR [13]: Fatal bus error\nBit 14 ERIE: Early receive interrupt enable\nWhen this bit is set with the normal interrupt summary enable bit (ETH_DMAIER \nregister[16]), the early receive interrupt is enabled.\nWhen this bit is cleared, the early receive interrupt is disabled.\nBit 13 FBEIE: Fatal bus error interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER \nregister[15]), the fatal bus error interrupt is enabled.\nWhen this bit is cleared, the fatal bus error enable interrupt is disabled.\nBits 12:11 Reserved, must be kept at reset value.\nBit 10 ETIE: Early transmit interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER register \n[15]), the early transmit interrupt is enabled.\nWhen this bit is cleared, the early transmit interrupt is disabled.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1236/1757\nRM0090 Rev 21\nThe Ethernet interrupt is generated only when the TSTS or PMTS bits of the DMA Status \nregister is asserted with their corresponding interrupt are unmasked, or when the NIS/AIS \nStatus bit is asserted and the corresponding Interrupt Enable bits (NISE/AISE) are enabled.\nBit 9 RWTIE: receive watchdog timeout interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER \nregister[15]), the receive watchdog timeout interrupt is enabled.\nWhen this bit is cleared, the receive watchdog timeout interrupt is disabled.\nBit 8 RPSIE: Receive process stopped interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER \nregister[15]), the receive stopped interrupt is enabled. When this bit is cleared, the receive \nstopped interrupt is disabled.\nBit 7 RBUIE: Receive buffer unavailable interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER \nregister[15]), the receive buffer unavailable interrupt is enabled.\nWhen this bit is cleared, the receive buffer unavailable interrupt is disabled.\nBit 6 RIE: Receive interrupt enable\nWhen this bit is set with the normal interrupt summary enable bit (ETH_DMAIER \nregister[16]), the receive interrupt is enabled.\nWhen this bit is cleared, the receive interrupt is disabled.\nBit 5 TUIE: Underflow interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER \nregister[15]), the transmit underflow interrupt is enabled.\nWhen this bit is cleared, the underflow interrupt is disabled.\nBit 4\nROIE: Overflow interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER \nregister[15]), the receive overflow interrupt is enabled.\nWhen this bit is cleared, the overflow interrupt is disabled.\nBit 3 TJTIE: Transmit jabber timeout interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER \nregister[15]), the transmit jabber timeout interrupt is enabled.\nWhen this bit is cleared, the transmit jabber timeout interrupt is disabled.\nBit 2 TBUIE: Transmit buffer unavailable interrupt enable\nWhen this bit is set with the normal interrupt summary enable bit (ETH_DMAIER \nregister[16]), the transmit buffer unavailable interrupt is enabled.\nWhen this bit is cleared, the transmit buffer unavailable interrupt is disabled.\nBit 1 TPSIE: Transmit process stopped interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER \nregister[15]), the transmission stopped interrupt is enabled.\nWhen this bit is cleared, the transmission stopped interrupt is disabled.\nBit 0 TIE: Transmit interrupt enable\nWhen this bit is set with the normal interrupt summary enable bit (ETH_DMAIER \nregister[16]), the transmit interrupt is enabled.\nWhen this bit is cleared, the transmit interrupt is disabled.\n\n\n<>\n\nRM0090 Rev 21\n1237/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet DMA missed frame and buffer overflow counter register \n(ETH_DMAMFBOCR)\nAddress offset: 0x1020\nReset value: 0x0000 0000\nThe DMA maintains two counters to track the number of missed frames during reception. \nThis register reports the current value of the counter. The counter is used for diagnostic \npurposes. Bits [15:0] indicate missed frames due to the STM32F4xx buffer being \nunavailable (no receive descriptor was available). Bits [27:17] indicate missed frames due to \nRx FIFO overflow conditions and runt frames (good frames of less than 64 bytes).\n \n \nEthernet DMA receive status watchdog timer register (ETH_DMARSWTR)\nAddress offset: 0x1024\nReset value: 0x0000 0000\nThis register, when written with a non-zero value, enables the watchdog timer for the receive \nstatus (RS, ETH_DMASR[6]).\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOFOC\nMFA\nOMFC\nMFC\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nBits 31:29 Reserved, must be kept at reset value.\nBit 28 OFOC: Overflow bit for FIFO overflow counter\nBits 27:17 MFA: Missed frames by the application\nIndicates the number of frames missed by the application\nBit 16 OMFC: Overflow bit for missed frame counter\nBits 15:0 MFC: Missed frames by the controller\nIndicates the number of frames missed by the Controller due to the host receive buffer being \nunavailable. This counter is incremented each time the DMA discards an incoming frame.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRSWTC\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBits 7:0 RSWTC: Receive status (RS) watchdog timer count\nIndicates the number of HCLK clock cycles multiplied by 256 for which the watchdog timer \nis set. The watchdog timer gets triggered with the programmed value after the RxDMA \ncompletes the transfer of a frame for which the RS status bit is not set due to the setting of \nRDES1[31] in the corresponding descriptor. When the watchdog timer runs out, the RS bit \nis set and the timer is stopped. The watchdog timer is reset when the RS bit is set high due \nto automatic setting of RS as per RDES1[31] of any received frame.\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1238/1757\nRM0090 Rev 21\nEthernet DMA current host transmit descriptor register (ETH_DMACHTDR)\nAddress offset: 0x1048\nReset value: 0x0000 0000\nThe Current host transmit descriptor register points to the start address of the current \ntransmit descriptor read by the DMA.\n \n \nEthernet DMA current host receive descriptor register (ETH_DMACHRDR)\nAddress offset: 0x104C\nReset value: 0x0000 0000\nThe Current host receive descriptor register points to the start address of the current receive \ndescriptor read by the DMA.\n \n \nEthernet DMA current host transmit buffer address register\n(ETH_DMACHTBAR)\nAddress offset: 0x1050\nReset value: 0x0000 0000\nThe Current host transmit buffer address register points to the current transmit buffer \naddress being read by the DMA.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nHTDAP\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 HTDAP: Host transmit descriptor address pointer\nCleared . Pointer updated by DMA during operation.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nHRDAP\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 HRDAP: Host receive descriptor address pointer\nCleared On Reset. Pointer updated by DMA during operation.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nHTBAP\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 HTBAP: Host transmit buffer address pointer\nCleared On Reset. Pointer updated by DMA during operation.\n\n\n<>\n\nRM0090 Rev 21\n1239/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet DMA current host receive buffer address register \n(ETH_DMACHRBAR)\nAddress offset: 0x1054\nReset value: 0x0000 0000\nThe current host receive buffer address register points to the current receive buffer address \nbeing read by the DMA.\n \n \n33.8.5 \nEthernet register maps\nTable 196 gives the ETH register map and reset values.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nHRBAP\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 HRBAP: Host receive buffer address pointer\nCleared On Reset. Pointer updated by DMA during operation.\nTable 196. Ethernet register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nETH_MACCR\nReserved\nCSTF\neserved\nWD\nJD\nReserved\nIFG\nCSD\nReserved\nFES\nROD\nLM\nDM\nIPCO\nRD\nReserved\nAPCS\nBL\nDC\nTE\nRE\nReserved\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nETH_MACFFR\nRA\nReserved\nHPF\nSAF\nSAIF\nPCF\nBFD\nPAM\nDAIF\nHM\nHU\nPM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nETH_MACHTHR\nHTH[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nETH_MACHTLR\nHTL[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nETH_MACMIIAR\nReserved\nPA\nMR\nCR\nM\nW\nM\nB\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nETH_MACMIIDR\nReserved\nMD\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x18\nETH_MACFCR\nPT\nReserved\nZQPD\nReserved\nPLT\nUPFD\nRFCE\nTFCE\nFCB/BPA\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nETH_\nMACVLANTR\nReserved\nVLANTC\nVLANTI\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nETH_\nMACRWUFFR\nFrame filter reg0\\Frame filter reg1\\Frame filter reg2\\Frame filter reg3\\Frame filter reg4\\...\\Frame filter reg7\nReset value\n0\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1240/1757\nRM0090 Rev 21\n0x2C\nETH_\nMACPMTCSR\nWFFRPR\nReserved\nGU\nReserved\nWFR\nMPR\nReserved\nWFE\nMPE\nPD\nReset value\n0\n0\n0\n0\n0\n0\n0\n0x34\nETH_\nMACDBGR\nReserved\nTFF\nTFNEGU\nReserved\nTFWA\nTFRS\nMTP\nMTFCS\nMMTEA\nReserved\nRFFL\nReserved\nRFRCS\nRFWRA\nReserved\nMSFRWCS\nMMRPEA\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x38\nETH_MACSR\nNot applicable\nReserved\nTSTS\nReserved\nMMCTS\nMMCRS\nMMCS\nPMTS\nReserve\nd\nReset value\n0\n0\n0\n0\n0\n0x3C\nETH_MACIMR\nNot applicable\nReserved\nTSTIM\nReserved\nPMTIM\nReserve\nd\nReset value\n0\n0\n0x40\nETH_MACA0HR\nMO\nReserved\nMACA0H\nReset value\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x44\nETH_MACA0LR\nMACA0L\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x48\nETH_MACA1HR\nAE\nSA\nMBC[6:0]\nReserved\nMACA1H\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x4C\nETH_MACA1LR\nMACA1L\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x50\nETH_MACA2HR\nAE\nSA\nMBC\nReserved\nMACA2H\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x54\nETH_MACA2LR\nMACA2L\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x58\nETH_MACA3HR\nAE\nSA\nMBC\nReserved\nMACA3H\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x5C\nETH_MACA3LR\nMACA3L\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x100\nETH_MMCCR\nReserved\nMCFHP\nMCP\nMCF\nROR\nCSR\nCR\nReset value\n0\n0\n0\n0\n0\n0\n0x104\nETH_MMCRIR\nReserved\nRGUFS\nReserved\nRFAES\nRFCES\nReserved\nReset value\n0\n0\n0\n0x108\nETH_MMCTIR\nReserved\nTGFS\nReserved\nTGFMSCS\nTGFSCS\nReserved\nReset value\n0\n0\n0\n0x10C\nETH_MMCRIMR\nReserved\nRGUFM\nReserved\nRFAEM\nRFCEM\nReserved\nReset value\n0\n0\n0\nTable 196. Ethernet register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1241/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n0x110\nETH_MMCTIMR\nReserved\nTGFM\nReserved\nTGFMSCM\nTGFSCM\nReserved\nReset value\n0\n0\n0\n0x14C\nETH_MMCTGFS\nCCR\nTGFSCC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x150\nETH_MMCTGF\nMSCCR\nTGFMSCC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x168\nETH_MMCTGF\nCR\nTGFC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x194\nETH_MMCRFC\nECR\nRFCEC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x198\nETH_MMCRFAE\nCR\nRFAEC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C4\nETH_MMCRGU\nFCR\nRGUFC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x700\nETH_PTPTSCR\nReserved\nTSPFFMAE\nTSCNT\nTSSMRME\nTSSEME\nTSSIPV4FE\nTSSIPV6FE\nTSSPTPOEFE\nTSPTPPSV2E\nTSSSR\nTSSARFE\nReserved\nTTSARU\nTSITE\nTSSTU\nTSSTI\nTSFCU\nTSE\nReset value\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x704\nETH_PTPSSIR\nReserved\nSTSSI\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x708\nETH_PTPTSHR\nSTS[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x70C\nETH_PTPTSLR\nSTPNS\nSTSS\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x710\nETH_PTPTSHU\nR\nTSUS\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x714\nETH_PTPTSLU\nR\nTSUPNS\nTSUSS\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x718\nETH_PTPTSAR\nTSA\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x71C\nETH_PTPTTHR\nTTSH\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x720\nETH_PTPTTLR\nTTSL\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 196. Ethernet register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nEthernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1242/1757\nRM0090 Rev 21\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x728\nETH_PTPTSSR\nReserved\nTSTTR\nTSSO\nReset value\n0\n0\n0x72C\nETH_PTPPPSC\nR\nReserved\nPPS\nFREQ\nReset value\n0\n0\n0\n0x1000\nETH_DMABMR\nReserved\nMB\nAAB\nFPM\nUSP\nRDP\nFB\nPM\nPBL\nEDFE\nDSL\nDA\nSR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n1\n0x1004\nETH_DMATPDR\nTPD\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1008\nETH_DMARPDR\nRPD\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x100C\nETH_DMARDLA\nR\nSRL\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1010\nETH_DMATDLA\nR\nSTL\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1014\nETH_DMASR\nReserved\nTSTS\nPMTS\nMMCS\nReserved\nEBS\nTPS\nRPS\nNIS\nAIS\nERS\nFBES\nReserved\nETS\nRWTS\nRPSS\nRBUS\nRS\nTUS\nROS\nTJTS\nTBUS\nTPSS\nTS\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1018\nETH_DMAOMR\nReserved\nDTCEFD\nRSF\nDFRF\nReserved\nTSF\nFTF\nReserved\nTTC\nST\nReserved\nFEF\nFUGF\nReserved\nRTC\nOSF\nSR\nReserved\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x101C\nETH_DMAIER\nReserved\nNISE\nAISE\nERIE\nFBEIE\nReserved\nETIE\nRWTIE\nRPSIE\nRBUIE\nRIE\nTUIE\nROIE\nTJTIE\nTBUIE\nTPSIE\nTIE\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1020\nETH_DMAMFB\nOCR\nReserved\nOFOC\nMFA\nOMFC\nMFC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1024\nETH_\nDMARSWTR\nReserved\nRSWTC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x1048\nETH_\nDMACHTDR\nHTDAP\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x104C\nETH_\nDMACHRDR\nHRDAP\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1050\nETH_\nDMACHTBAR\nHTBAP\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1054\nETH_\nDMACHRBAR\nHRBAP\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 196. Ethernet register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1243/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34 \nUSB on-the-go full-speed (OTG_FS)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n34.1 \nOTG_FS introduction\nPortions Copyright (c) 2004, 2005 Synopsys, Inc. All rights reserved. Used with permission.\nThis section presents the architecture and the programming model of the OTG_FS \ncontroller.\nThe following acronyms are used throughout this section:\nReferences are made to the following documents:\n•\nUSB On-The-Go Supplement, Revision 1.3\n•\nUniversal Serial Bus Revision 2.0 Specification\nThe OTG_FS is a dual-role device (DRD) controller that supports both device and host \nfunctions and is fully compliant with the On-The-Go Supplement to the USB 2.0 \nSpecification. It can also be configured as a host-only or device-only controller, fully \ncompliant with the USB 2.0 Specification. In host mode, the OTG_FS supports full-speed \n(FS, 12 Mbits/s) and low-speed (LS, 1.5 Mbits/s) transfers whereas in device mode, it only \nsupports full-speed (FS, 12 Mbits/s) transfers. The OTG_FS supports both HNP and SRP. \nThe only external device required is a charge pump for VBUS in host mode.\nFS\nFull-speed\nLS\nLow-speed\nMAC\nMedia access controller\nOTG\nOn-the-go\nPFC\nPacket FIFO controller\nPHY\nPhysical layer\nUSB\nUniversal serial bus\nUTMI\nUSB 2.0 transceiver macrocell interface (UTMI)\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1244/1757\nRM0090 Rev 21\n34.2 \nOTG_FS main features\nThe main features can be divided into three categories: general, host-mode and device-\nmode features.\n34.2.1 \nGeneral features\nThe OTG_FS interface general features are the following:\n•\nIt is USB-IF certified to the Universal Serial Bus Specification Rev 2.0\n•\nIt includes full support (PHY) for the optional On-The-Go (OTG) protocol detailed in the \nOn-The-Go Supplement Rev 1.3 specification\n–\nIntegrated support for A-B Device Identification (ID line)\n–\nIntegrated support for host Negotiation Protocol (HNP) and Session Request \nProtocol (SRP)\n–\nIt allows host to turn VBUS off to conserve battery power in OTG applications\n–\nIt supports OTG monitoring of VBUS levels with internal comparators\n–\nIt supports dynamic host-peripheral switch of role\n•\nIt is software-configurable to operate as:\n–\nSRP capable USB FS Peripheral (B-device)\n–\nSRP capable USB FS/LS host (A-device)\n–\nUSB On-The-Go Full-Speed Dual Role device\n•\nIt supports FS SOF and LS Keep-alives with\n–\nSOF pulse PAD connectivity (OTG_FS_SOF)\n–\nSOF pulse internal connection to timer2 (TIM2)\n–\nConfigurable framing period\n–\nConfigurable end of frame interrupt\n•\nIt includes power saving features such as system stop during USB Suspend, switch-off \nof clock domains internal to the digital core, PHY and DFIFO power management\n•\nIt features a dedicated RAM of 1.25 Kbytes with advanced FIFO control:\n–\nConfigurable partitioning of RAM space into different FIFOs for flexible and \nefficient use of RAM\n–\nEach FIFO can hold multiple packets\n–\nDynamic memory allocation\n–\nConfigurable FIFO sizes that are not powers of 2 to allow the use of contiguous \nmemory locations\n•\nIt guarantees max USB bandwidth for up to one frame (1ms) without system \nintervention\n\n\n<>\n\nRM0090 Rev 21\n1245/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34.2.2 \nHost-mode features\nThe OTG_FS interface main features and requirements in host-mode are the following:\n•\nExternal charge pump for VBUS voltage generation.\n•\nUp to 8 host channels (pipes): each channel is dynamically reconfigurable to allocate \nany type of USB transfer. \n•\nBuilt-in hardware scheduler holding:\n–\nUp to 8 interrupt plus isochronous transfer requests in the periodic hardware \nqueue\n–\nUp to 8 control plus bulk transfer requests in the non-periodic hardware queue\n•\nManagement of a shared RX FIFO, a periodic TX FIFO and a nonperiodic TX FIFO for \nefficient usage of the USB data RAM.\n34.2.3 \nPeripheral-mode features\nThe OTG_FS interface main features in peripheral-mode are the following:\n•\n1 bidirectional control endpoint0\n•\n3 IN endpoints (EPs) configurable to support Bulk, Interrupt or Isochronous transfers\n•\n3 OUT endpoints configurable to support Bulk, Interrupt or Isochronous transfers\n•\nManagement of a shared Rx FIFO and a Tx-OUT FIFO for efficient usage of the USB \ndata RAM\n•\nManagement of up to 4 dedicated Tx-IN FIFOs (one for each active IN EP) to put less \nload on the application\n•\nSupport for the soft disconnect feature.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1246/1757\nRM0090 Rev 21\n34.3 \nOTG_FS functional description\nFigure 386. OTG full-speed block diagram\n34.3.1 \nOTG pins\n \n34.3.2 \nOTG full-speed core\nThe USB OTG FS receives the 48 MHz ±0.25% clock from the reset and clock controller \n(RCC), via an external quartz. The USB clock is used for driving the 48 MHz domain at full-\nspeed (12 Mbit/s) and must be enabled prior to configuring the OTG FS core.\nThe CPU reads and writes from/to the OTG FS core registers through the AHB peripheral \nbus. It is informed of USB events through the single USB OTG interrupt line described in \nSection 34.15: OTG_FS interrupts.\nMS19928V4\nUSB2.0\nOTG FS\ncore\nSystem clock domain\nUSB clock \ndomain\nOTG\nFS\nPHY\nOTG_FS_DP\nOTG_FS_DM\nOTG_FS_ID\nOTG_FS_VBUS\nUniversal serial bus\nPower\nand\nclock\ncontroller\nCortex® core\nUTMIFS\nRAM bus\n1.25 Kbyte\nUSB data\nFIFOs\nUSB clock at 48 MHz\nUSB suspend\nOTG_FS_SOF\nTable 197. OTG_FS input/output pins\nSignal name\nSignal type\nDescription\nOTG_FS_DP\nDigital input/output\nUSB OTG D+ line\nOTG_FS_DM\nDigital input/output\nUSB OTG D- line\nOTG_FS_ID\nDigital input\nUSB OTG ID\nOTG_FS_VBUS\nAnalog input\nUSB OTG VBUS\nOTG_FS_SOF\nDigital output\nUSB OTG Start Of Frame (visibility)\n\n\n<>\n\nRM0090 Rev 21\n1247/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nThe CPU submits data over the USB by writing 32-bit words to dedicated OTG_FS locations \n(push registers). The data are then automatically stored into Tx-data FIFOs configured \nwithin the USB data RAM. There is one Tx-FIFO push register for each in-endpoint \n(peripheral mode) or out-channel (host mode).\nThe CPU receives the data from the USB by reading 32-bit words from dedicated OTG_FS \naddresses (pop registers). The data are then automatically retrieved from a shared Rx-FIFO \nconfigured within the 1.25 KB USB data RAM. There is one Rx-FIFO pop register for each \nout-endpoint or in-channel.\nThe USB protocol layer is driven by the serial interface engine (SIE) and serialized over the \nUSB by the full-/low-speed transceiver module within the on-chip physical layer (PHY).\n34.3.3 \nFull-speed OTG PHY\nThe embedded full-speed OTG PHY is controlled by the OTG FS core and conveys USB \ncontrol & data signals through the full-speed subset of the UTMI+ Bus (UTMIFS). It provides \nthe physical support to USB connectivity.\nThe full-speed OTG PHY includes the following components:\n•\nFS/LS transceiver module used by both host and device. It directly drives transmission \nand reception on the single-ended USB lines.\n•\nintegrated ID pull-up resistor used to sample the ID line for A/B device identification.\n•\nDP/DM integrated pull-up and pull-down resistors controlled by the OTG_FS core \ndepending on the current role of the device. As a peripheral, it enables the DP pull-up \nresistor to signal full-speed peripheral connections as soon as VBUS is sensed to be at \na valid level (B-session valid). In host mode, pull-down resistors are enabled on both \nDP/DM. Pull-up and pull-down resistors are dynamically switched when the device’s \nrole is changed via the host negotiation protocol (HNP).\n•\nPull-up/pull-down resistor ECN circuit. The DP pull-up consists of 2 resistors controlled \nseparately from the OTG_FS as per the resistor Engineering Change Notice applied to \nUSB Rev2.0. The dynamic trimming of the DP pull-up strength allows for better noise \nrejection and Tx/Rx signal quality.\n•\nVBUS sensing comparators with hysteresis used to detect VBUS Valid, A-B Session \nValid and session-end voltage thresholds. They are used to drive the session request \nprotocol (SRP), detect valid startup and end-of-session conditions, and constantly \nmonitor the VBUS supply during USB operations.\n•\nVBUS pulsing method circuit used to charge/discharge VBUS through resistors during \nthe SRP (weak drive).\nCaution:\nTo guarantee a correct operation for the USB OTG FS peripheral, the AHB frequency should \nbe higher than 14.2 MHz.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1248/1757\nRM0090 Rev 21\n34.4 \nOTG dual role device (DRD)\nFigure 387. OTG A-B device connection\n1.\nExternal voltage regulator only needed when building a VBUS powered device\n2.\nSTMPS2141STR needed only if the application has to support a VBUS powered device. A basic power \nswitch can be used if 5 V are available on the application board.\n34.4.1 \nID line detection\nThe host or peripheral (the default) role is assumed depending on the ID input pin \n(OTG_FS_ID). The ID line status is determined on plugging in the USB, depending on which \nside of the USB cable is connected to the micro-AB receptacle.\n•\nIf the B-side of the USB cable is connected with a floating ID wire, the integrated pull-\nup resistor detects a high ID level and the default Peripheral role is confirmed. In this \nconfiguration the OTG_FS complies with the standard FSM described by section 6.8.2: \nOn-The-Go B-device of the On-The-Go Specification Rev1.3 supplement to the \nUSB2.0.\n•\nIf the A-side of the USB cable is connected with a grounded ID, the OTG_FS issues an \nID line status change interrupt (CIDSCHG bit in OTG_FS_GINTSTS) for host software \ninitialization, and automatically switches to the host role. In this configuration the \nOTG_FS complies with the standard FSM described by section 6.8.1: On-The-Go A-\ndevice of the On-The-Go Specification Rev1.3 supplement to the USB2.0.\n34.4.2 \nHNP dual role device\nThe HNP capable bit in the Global USB configuration register (HNPCAP bit in OTG_FS_ \nGUSBCFG) enables the OTG_FS core to dynamically change its role from A-host to A-\nperipheral and vice-versa, or from B-Peripheral to B-host and vice-versa according to the \nhost negotiation protocol (HNP). The current device status can be read by the combined \nvalues of the Connector ID Status bit in the Global OTG control and status register (CIDSTS \nbit in OTG_FS_GOTGCTL) and the current mode of operation bit in the global interrupt and \nstatus register (CMOD bit in OTG_FS_GINTSTS).\nThe HNP program model is described in detail in Section 34.17: OTG_FS programming \nmodel.\nSTM32 MCU\nSTMPS2141STR\nCurrent-limited \npower distribution \nswitch (2)\nVDD\nVBUS\nDP\nVSS\nPA9\nPA12\nPA11\nUSB micro-AB connector\nDM\nGPIO+IRQ\nGPIO\nEN\nOvercurrent\n5 V Pwr\n5 V to VDD\nvoltage regulator\nVDD\nID\nPA10\nOSC_IN\nOSC_OUT\nMS19904V4\n\n\n<>\n\nRM0090 Rev 21\n1249/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34.4.3 \nSRP dual role device\nThe SRP capable bit in the global USB configuration register (SRPCAP bit in \nOTG_FS_GUSBCFG) enables the OTG_FS core to switch off the generation of VBUS for \nthe A-device to save power. Note that the A-device is always in charge of driving VBUS \nregardless of the host or peripheral role of the OTG_FS.\nthe SRP A/B-device program model is described in detail in Section 34.17: OTG_FS \nprogramming model.\n34.5 \nUSB peripheral\nThis section gives the functional description of the OTG_FS in the USB peripheral mode. \nThe OTG_FS works as an USB peripheral in the following circumstances:\n•\nOTG B-Peripheral\n–\nOTG B-device default state if B-side of USB cable is plugged in\n•\nOTG A-Peripheral\n–\nOTG A-device state after the HNP switches the OTG_FS to its peripheral role\n•\nB-device\n–\nIf the ID line is present, functional and connected to the B-side of the USB cable, \nand the HNP-capable bit in the Global USB Configuration register (HNPCAP bit in \nOTG_FS_GUSBCFG) is cleared (see On-The-Go Rev1.3 par. 6.8.3).\n•\nPeripheral only (see Figure 388: USB peripheral-only connection)\n–\nThe force device mode bit in the Global USB configuration register (FDMOD in \nOTG_FS_GUSBCFG) is set to 1, forcing the OTG_FS core to work as a USB \nperipheral-only (see On-The-Go Rev1.3 par. 6.8.3). In this case, the ID line is \nignored even if present on the USB connector.\nNote:\nTo build a bus-powered device implementation in case of the B-device or peripheral-only \nconfiguration, an external regulator has to be added that generates the VDD chip-supply \nfrom VBUS.\nThe VBUS pin can be freed by disabling the VBUS sensing option. This is done by setting the \nNOVBUSSENS bit in the OTG_FS_GCCFG register. In this case the VBUS is considered \ninternally to be always at VBUS valid level (5 V). \n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1250/1757\nRM0090 Rev 21\nFigure 388. USB peripheral-only connection\n1.\nUse a regulator to build a bus-powered device.\n34.5.1 \nSRP-capable peripheral\nThe SRP capable bit in the Global USB configuration register (SRPCAP bit in \nOTG_FS_GUSBCFG) enables the OTG_FS to support the session request protocol (SRP). \nIn this way, it allows the remote A-device to save power by switching off VBUS while the USB \nsession is suspended.\nThe SRP peripheral mode program model is described in detail in the B-device session \nrequest protocol section.\n34.5.2 \nPeripheral states\nPowered state\nThe VBUS input detects the B-Session valid voltage by which the USB peripheral is allowed \nto enter the powered state (see USB2.0 par9.1). The OTG_FS then automatically connects \nthe DP pull-up resistor to signal full-speed device connection to the host and generates the \nsession request interrupt (SRQINT bit in OTG_FS_GINTSTS) to notify the powered state.\nThe VBUS input also ensures that valid VBUS levels are supplied by the host during USB \noperations. If a drop in VBUS below B-session valid happens to be detected (for instance \nbecause of a power disturbance or if the host port has been switched off), the OTG_FS \nautomatically disconnects and the session end detected (SEDET bit in \nOTG_FS_GOTGINT) interrupt is generated to notify that the OTG_FS has exited the \npowered state.\nIn the powered state, the OTG_FS expects to receive some reset signaling from the host. \nNo other USB operation is possible. When a reset signaling is received the reset detected \ninterrupt (USBRST in OTG_FS_GINTSTS) is generated. When the reset signaling is \ncomplete, the enumeration done interrupt (ENUMDNE bit in OTG_FS_GINTSTS) is \ngenerated and the OTG_FS enters the Default state.\nSTM32 MCU\n5V to VDD\nVolatge regulator\nVDD\nVBUS\nDP\nVSS\nPA9\nPA12\nPA11\nUSB Std-B connector\nDM\nOSC_IN\nOSC_OUT\nMS19905V4\n\n\n<>\n\nRM0090 Rev 21\n1251/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nSoft disconnect\nThe powered state can be exited by software with the soft disconnect feature. The DP pull-\nup resistor is removed by setting the soft disconnect bit in the device control register (SDIS \nbit in OTG_FS_DCTL), causing a device disconnect detection interrupt on the host side \neven though the USB cable was not really removed from the host port.\nDefault state\nIn the Default state the OTG_FS expects to receive a SET_ADDRESS command from the \nhost. No other USB operation is possible. When a valid SET_ADDRESS command is \ndecoded on the USB, the application writes the corresponding number into the device \naddress field in the device configuration register (DAD bit in OTG_FS_DCFG). The \nOTG_FS then enters the address state and is ready to answer host transactions at the \nconfigured USB address.\nSuspended state\nThe OTG_FS peripheral constantly monitors the USB activity. After counting 3 ms of USB \nidleness, the early suspend interrupt (ESUSP bit in OTG_FS_GINTSTS) is issued, and \nconfirmed 3 ms later, if appropriate, by the suspend interrupt (USBSUSP bit in \nOTG_FS_GINTSTS). The device suspend bit is then automatically set in the device status \nregister (SUSPSTS bit in OTG_FS_DSTS) and the OTG_FS enters the suspended state.\nThe suspended state may optionally be exited by the device itself. In this case the \napplication sets the remote wake-up signaling bit in the device control register (RWUSIG bit \nin OTG_FS_DCTL) and clears it after 1 to 15 ms.\nWhen a resume signaling is detected from the host, the resume interrupt (WKUPINT bit in \nOTG_FS_GINTSTS) is generated and the device suspend bit is automatically cleared.\n34.5.3 \nPeripheral endpoints\nThe OTG_FS core instantiates the following USB endpoints:\n•\nControl endpoint 0:\n–\nBidirectional and handles control messages only\n–\nSeparate set of registers to handle in and out transactions\n–\nProper control (OTG_FS_DIEPCTL0/OTG_FS_DOEPCTL0), transfer \nconfiguration (OTG_FS_DIEPTSIZ0/OTG_FS_DIEPTSIZ0), and status-interrupt \n(OTG_FS_DIEPINTx/)OTG_FS_DOEPINT0) registers. The available set of bits \ninside the control and transfer size registers slightly differs from that of other \nendpoints\n•\n3 IN endpoints\n–\nEach of them can be configured to support the isochronous, bulk or interrupt \ntransfer type\n–\nEach of them has proper control (OTG_FS_DIEPCTLx), transfer configuration \n(OTG_FS_DIEPTSIZx), and status-interrupt (OTG_FS_DIEPINTx) registers\n–\nThe Device IN endpoints common interrupt mask register (OTG_FS_DIEPMSK) is \navailable to enable/disable a single kind of endpoint interrupt source on all of the \nIN endpoints (EP0 included)\n–\nSupport for incomplete isochronous IN transfer interrupt (IISOIXFR bit in \nOTG_FS_GINTSTS), asserted when there is at least one isochronous IN endpoint \n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1252/1757\nRM0090 Rev 21\non which the transfer is not completed in the current frame. This interrupt is \nasserted along with the end of periodic frame interrupt \n(OTG_FS_GINTSTS/EOPF).\n•\n3 OUT endpoints\n–\nEach of them can be configured to support the isochronous, bulk or interrupt \ntransfer type\n–\nEach of them has a proper control (OTG_FS_DOEPCTLx), transfer configuration \n(OTG_FS_DOEPTSIZx) and status-interrupt (OTG_FS_DOEPINTx) register\n–\nDevice Out endpoints common interrupt mask register (OTG_FS_DOEPMSK) is \navailable to enable/disable a single kind of endpoint interrupt source on all of the \nOUT endpoints (EP0 included)\n–\nSupport for incomplete isochronous OUT transfer interrupt (INCOMPISOOUT bit \nin OTG_FS_GINTSTS), asserted when there is at least one isochronous OUT \nendpoint on which the transfer is not completed in the current frame. This interrupt \nis asserted along with the end of periodic frame interrupt \n(OTG_FS_GINTSTS/EOPF).\nEndpoint control\n•\nThe following endpoint controls are available to the application through the device \nendpoint-x IN/OUT control register (DIEPCTLx/DOEPCTLx):\n–\nEndpoint enable/disable\n–\nEndpoint activate in current configuration\n–\nProgram USB transfer type (isochronous, bulk, interrupt)\n–\nProgram supported packet size\n–\nProgram Tx-FIFO number associated with the IN endpoint\n–\nProgram the expected or transmitted data0/data1 PID (bulk/interrupt only)\n–\nProgram the even/odd frame during which the transaction is received or \ntransmitted (isochronous only)\n–\nOptionally program the NAK bit to always negative-acknowledge the host \nregardless of the FIFO status\n–\nOptionally program the STALL bit to always stall host tokens to that endpoint\n–\nOptionally program the SNOOP mode for OUT endpoint not to check the CRC \nfield of received data\nEndpoint transfer\nThe device endpoint-x transfer size registers (DIEPTSIZx/DOEPTSIZx) allow the application \nto program the transfer size parameters and read the transfer status. Programming must be \ndone before setting the endpoint enable bit in the endpoint control register. Once the \nendpoint is enabled, these fields are read-only as the OTG FS core updates them with the \ncurrent transfer status.\nThe following transfer parameters can be programmed:\n•\nTransfer size in bytes\n•\nNumber of packets that constitute the overall transfer size\n\n\n<>\n\nRM0090 Rev 21\n1253/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nEndpoint status/interrupt\nThe device endpoint-x interrupt registers (DIEPINTx/DOPEPINTx) indicate the status of an \nendpoint with respect to USB- and AHB-related events. The application must read these \nregisters when the OUT endpoint interrupt bit or the IN endpoint interrupt bit in the core \ninterrupt register (OEPINT bit in OTG_FS_GINTSTS or IEPINT bit in OTG_FS_GINTSTS, \nrespectively) is set. Before the application can read these registers, it must first read the \ndevice all endpoints interrupt (OTG_FS_DAINT) register to get the exact endpoint number \nfor the device endpoint-x interrupt register. The application must clear the appropriate bit in \nthis register to clear the corresponding bits in the DAINT and GINTSTS registers\nThe peripheral core provides the following status checks and interrupt generation:\n•\nTransfer completed interrupt, indicating that data transfer was completed on both the \napplication (AHB) and USB sides\n•\nSetup stage has been done (control-out only)\n•\nAssociated transmit FIFO is half or completely empty (in endpoints)\n•\nNAK acknowledge has been transmitted to the host (isochronous-in only)\n•\nIN token received when Tx-FIFO was empty (bulk-in/interrupt-in only)\n•\nOut token received when endpoint was not yet enabled\n•\nBabble error condition has been detected\n•\nEndpoint disable by application is effective\n•\nEndpoint NAK by application is effective (isochronous-in only)\n•\nMore than 3 back-to-back setup packets were received (control-out only)\n•\nTimeout condition detected (control-in only)\n•\nIsochronous out packet has been dropped, without generating an interrupt\n34.6 \nUSB host\nThis section gives the functional description of the OTG_FS in the USB host mode. The \nOTG_FS works as a USB host in the following circumstances:\n•\nOTG A-host\n–\nOTG A-device default state when the A-side of the USB cable is plugged in\n•\nOTG B-host\n–\nOTG B-device after HNP switching to the host role\n•\nA-device\n–\nIf the ID line is present, functional and connected to the A-side of the USB cable, \nand the HNP-capable bit is cleared in the Global USB Configuration register \n(HNPCAP bit in OTG_FS_GUSBCFG). Integrated pull-down resistors are \nautomatically set on the DP/DM lines.\n•\nHost only (see Figure 389: USB host-only connection).\n–\nThe force host mode bit in the global USB configuration register (FHMOD bit in \nOTG_FS_GUSBCFG) forces the OTG_FS core to work as a USB host-only. In this \ncase, the ID line is ignored even if present on the USB connector. Integrated pull-\ndown resistors are automatically set on the DP/DM lines.\nNote:\nOn-chip 5 V VBUS generation is not supported. For this reason, a charge pump or, if 5 V are \navailable on the application board, a basic power switch must be added externally to drive \n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1254/1757\nRM0090 Rev 21\nthe 5 V VBUS line. The external charge pump can be driven by any GPIO output. This is \nrequired for the OTG A-host, A-device and host-only configurations.\nThe VBUS input ensures that valid VBUS levels are supplied by the charge pump during USB \noperations while the charge pump overcurrent output can be input to any GPIO pin \nconfigured to generate port interrupts. The overcurrent ISR must promptly disable the VBUS \ngeneration.\nThe VBUS pin can be freed by disabling the VBUS sensing option. This is done by setting the \nNOVBUSSENS bit in the OTG_FS_GCCFG register. In this case the VBUS is considered \ninternally to be always at VBUS valid level (5 V). \nFigure 389. USB host-only connection\n1.\nSTMPS2141STR needed only if the application has to support a VBUS powered device. A basic power \nswitch can be used if 5 V are available on the application board.\n2.\nVDD range is between 2 V and 3.6 V.\n34.6.1 \nSRP-capable host\nSRP support is available through the SRP capable bit in the global USB configuration \nregister (SRPCAP bit in OTG_FS_GUSBCFG). With the SRP feature enabled, the host can \nsave power by switching off the VBUS power while the USB session is suspended.\nThe SRP host mode program model is described in detail in the A-device session request \nprotocol section.\n34.6.2 \nUSB host states\nHost port power\nOn-chip 5 V VBUS generation is not supported. For this reason, a charge pump or, if 5 V are \navailable on the application board, a basic power switch, must be added externally to drive \nthe 5 V VBUS line. The external charge pump can be driven by any GPIO output. When the \napplication decides to power on VBUS using the chosen GPIO, it must also set the port \npower bit in the host port control and status register (PPWR bit in OTG_FS_HPRT).\nMSv36915V2\nSTMPS2141STR\nCurrent-limited\n power distribution \nswitch(2)\nOSC_IN\nOSC_OUT\nGPIO\nGPIO + IRQ\nEN\nOvercurrent\n5 V\n5 V Pwr\nVBUS\nDM\nDP\nVSS\nUSB Std-A connector\nVDD\n\n\n<>\n\nRM0090 Rev 21\n1255/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nVBUS valid\nWhen HNP or SRP is enabled the VBUS sensing pin (PA9) pin should be connected to \nVBUS. The VBUS input ensures that valid VBUS levels are supplied by the charge pump \nduring USB operations. Any unforeseen VBUS voltage drop below the VBUS valid threshold \n(4.25 V) leads to an OTG interrupt triggered by the session end detected bit (SEDET bit in \nOTG_FS_GOTGINT). The application is then required to remove the VBUS power and clear \nthe port power bit. \nWhen HNP and SRP are both disabled, the VBUS sensing pin (PA9) should not be \nconnected to VBUS. This pin can be can be used as GPIO.\nThe charge pump overcurrent flag can also be used to prevent electrical damage. Connect \nthe overcurrent flag output from the charge pump to any GPIO input and configure it to \ngenerate a port interrupt on the active level. The overcurrent ISR must promptly disable the \nVBUS generation and clear the port power bit.\nHost detection of a peripheral connection\nIf SRP or HNP are enabled, even if USB peripherals or B-devices can be attached at any \ntime, the OTG_FS does not detect any bus connection until VBUS is no longer sensed at a \nvalid level (5 V). When VBUS is at a valid level and a remote B-device is attached, the \nOTG_FS core issues a host port interrupt triggered by the device connected bit in the host \nport control and status register (PCDET bit in OTG_FS_HPRT).\nWhen HNP and SRP are both disabled, USB peripherals or B-device are detected as soon \nas they are connected. The OTG_FS core issues a host port interrupt triggered by the \ndevice connected bit in the host port control and status (PCDET bit in OTG_FS_HPRT).\nHost detection of peripheral a disconnection\nThe peripheral disconnection event triggers the disconnect detected interrupt (DISCINT bit \nin OTG_FS_GINTSTS).\nHost enumeration\nAfter detecting a peripheral connection the host must start the enumeration process by \nsending USB reset and configuration commands to the new peripheral.\nBefore starting to drive a USB reset, the application waits for the OTG interrupt triggered by \nthe debounce done bit (DBCDNE bit in OTG_FS_GOTGINT), which indicates that the bus is \nstable again after the electrical debounce caused by the attachment of a pull-up resistor on \nDP (FS) or DM (LS).\nThe application drives a USB reset signaling (single-ended zero) over the USB by keeping \nthe port reset bit set in the host port control and status register (PRST bit in \nOTG_FS_HPRT) for a minimum of 10 ms and a maximum of 20 ms. The application takes \ncare of the timing count and then of clearing the port reset bit.\nOnce the USB reset sequence has completed, the host port interrupt is triggered by the port \nenable/disable change bit (PENCHNG bit in OTG_FS_HPRT). This informs the application \nthat the speed of the enumerated peripheral can be read from the port speed field in the \nhost port control and status register (PSPD bit in OTG_FS_HPRT) and that the host is \nstarting to drive SOFs (FS) or Keep alives (LS). The host is now ready to complete the \nperipheral enumeration by sending peripheral configuration commands.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1256/1757\nRM0090 Rev 21\nHost suspend\nThe application decides to suspend the USB activity by setting the port suspend bit in the \nhost port control and status register (PSUSP bit in OTG_FS_HPRT). The OTG_FS core \nstops sending SOFs and enters the suspended state.\nThe suspended state can be optionally exited on the remote device’s initiative (remote \nwake-up). In this case the remote wake-up interrupt (WKUPINT bit in OTG_FS_GINTSTS) \nis generated upon detection of a remote wake-up signaling, the port resume bit in the host \nport control and status register (PRES bit in OTG_FS_HPRT) self-sets, and resume \nsignaling is automatically driven over the USB. The application must time the resume \nwindow and then clear the port resume bit to exit the suspended state and restart the SOF.\nIf the suspended state is exited on the host initiative, the application must set the port \nresume bit to start resume signaling on the host port, time the resume window and finally \nclear the port resume bit.\n34.6.3 \nHost channels\nThe OTG_FS core instantiates 8 host channels. Each host channel supports an USB host \ntransfer (USB pipe). The host is not able to support more than 8 transfer requests at the \nsame time. If more than 8 transfer requests are pending from the application, the host \ncontroller driver (HCD) must re-allocate channels when they become available from \nprevious duty, that is, after receiving the transfer completed and channel halted interrupts.\nEach host channel can be configured to support in/out and any type of periodic/nonperiodic \ntransaction. Each host channel makes us of proper control (HCCHARx), transfer \nconfiguration (HCTSIZx) and status/interrupt (HCINTx) registers with associated mask \n(HCINTMSKx) registers.\nHost channel control\n•\nThe following host channel controls are available to the application through the host \nchannel-x characteristics register (HCCHARx):\n–\nChannel enable/disable\n–\nProgram the FS/LS speed of target USB peripheral\n–\nProgram the address of target USB peripheral\n–\nProgram the endpoint number of target USB peripheral\n–\nProgram the transfer IN/OUT direction\n–\nProgram the USB transfer type (control, bulk, interrupt, isochronous)\n–\nProgram the maximum packet size (MPS)\n–\nProgram the periodic transfer to be executed during odd/even frames\nHost channel transfer\nThe host channel transfer size registers (HCTSIZx) allow the application to program the \ntransfer size parameters, and read the transfer status. Programming must be done before \nsetting the channel enable bit in the host channel characteristics register. Once the endpoint \n\n\n<>\n\nRM0090 Rev 21\n1257/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nis enabled the packet count field is read-only as the OTG FS core updates it according to \nthe current transfer status.\n•\nThe following transfer parameters can be programmed:\n–\ntransfer size in bytes\n–\nnumber of packets making up the overall transfer size\n–\ninitial data PID\nHost channel status/interrupt\nThe host channel-x interrupt register (HCINTx) indicates the status of an endpoint with \nrespect to USB- and AHB-related events. The application must read these register when the \nhost channels interrupt bit in the core interrupt register (HCINT bit in OTG_FS_GINTSTS) is \nset. Before the application can read these registers, it must first read the host all channels \ninterrupt (HCAINT) register to get the exact channel number for the host channel-x interrupt \nregister. The application must clear the appropriate bit in this register to clear the \ncorresponding bits in the HAINT and GINTSTS registers. The mask bits for each interrupt \nsource of each channel are also available in the OTG_FS_HCINTMSK-x register.\n•\nThe host core provides the following status checks and interrupt generation:\n–\nTransfer completed interrupt, indicating that the data transfer is complete on both \nthe application (AHB) and USB sides\n–\nChannel has stopped due to transfer completed, USB transaction error or disable \ncommand from the application\n–\nAssociated transmit FIFO is half or completely empty (IN endpoints)\n–\nACK response received\n–\nNAK response received\n–\nSTALL response received\n–\nUSB transaction error due to CRC failure, timeout, bit stuff error, false EOP\n–\nBabble error\n–\nfraMe overrun\n–\ndAta toggle error\n34.6.4 \nHost scheduler\nThe host core features a built-in hardware scheduler which is able to autonomously re-order \nand manage the USB transaction requests posted by the application. At the beginning of \neach frame the host executes the periodic (isochronous and interrupt) transactions first, \nfollowed by the nonperiodic (control and bulk) transactions to achieve the higher level of \npriority granted to the isochronous and interrupt transfer types by the USB specification. \nThe host processes the USB transactions through request queues (one for periodic and one \nfor nonperiodic). Each request queue can hold up to 8 entries. Each entry represents a \npending transaction request from the application, and holds the IN or OUT channel number \nalong with other information to perform a transaction on the USB. The order in which the \nrequests are written to the queue determines the sequence of the transactions on the USB \ninterface.\nAt the beginning of each frame, the host processes the periodic request queue first, followed \nby the nonperiodic request queue. The host issues an incomplete periodic transfer interrupt \n(IPXFR bit in OTG_FS_GINTSTS) if an isochronous or interrupt transaction scheduled for \nthe current frame is still pending at the end of the current frame. The OTG HS core is fully \n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1258/1757\nRM0090 Rev 21\nresponsible for the management of the periodic and nonperiodic request queues.The \nperiodic transmit FIFO and queue status register (HPTXSTS) and nonperiodic transmit \nFIFO and queue status register (HNPTXSTS) are read-only registers which can be used by \nthe application to read the status of each request queue. They contain: \n•\nThe number of free entries currently available in the periodic (nonperiodic) request \nqueue (8 max) \n•\nFree space currently available in the periodic (nonperiodic) Tx-FIFO (out-transactions) \n•\nIN/OUT token, host channel number and other status information.\nAs request queues can hold a maximum of 8 entries each, the application can push to \nschedule host transactions in advance with respect to the moment they physically reach the \nSB for a maximum of 8 pending periodic transactions plus 8 pending nonperiodic \ntransactions.\nTo post a transaction request to the host scheduler (queue) the application must check that \nthere is at least 1 entry available in the periodic (nonperiodic) request queue by reading the \nPTXQSAV bits in the OTG_FS_HNPTXSTS register or NPTQXSAV bits in the \nOTG_FS_HNPTXSTS register. \n34.7 \nSOF trigger\nFigure 390. SOF connectivity\nThe OTG FS core provides means to monitor, track and configure SOF framing in the host \nand peripheral, as well as an SOF pulse output connectivity feature.\nSuch utilities are especially useful for adaptive audio clock generation techniques, where \nthe audio peripheral needs to synchronize to the isochronous stream provided by the PC, or \nthe host needs to trim its framing rate according to the requirements of the audio peripheral.\n34.7.1 \nHost SOFs\nIn host mode the number of PHY clocks occurring between the generation of two \nconsecutive SOF (FS) or Keep-alive (LS) tokens is programmable in the host frame interval \nregister (HFIR), thus providing application control over the SOF framing period. An interrupt \nSTM32 MCU\nVBUS\nD+\nVSS\nPA8\nPA12\nPA11\nUSB mic ro-AB connector\nD-\nID\nTIM2\nITR1\nSOF \npulse\nSOFgen\nPA9\nPA10\nSOF pulse output, to \nexternal audio control\nMS19907V3\n\n\n<>\n\nRM0090 Rev 21\n1259/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nis generated at any start of frame (SOF bit in OTH_FS_GINTSTS). The current frame \nnumber and the time remaining until the next SOF are tracked in the host frame number \nregister (HFNUM).\nAn SOF pulse signal, generated at any SOF starting token and with a width of 20 HCLK \ncycles, can be made available externally on the OTG_FS_SOF pin using the SOFOUTEN \nbit in the global control and configuration register. The SOF pulse is also internally \nconnected to the input trigger of timer 2 (TIM2), so that the input capture feature, the output \ncompare feature and the timer can be triggered by the SOF pulse. The TIM2 connection is \nenabled through the ITR1_RMP bits of TIM2_OR register.\n34.7.2 \nPeripheral SOFs\nIn device mode, the start of frame interrupt is generated each time an SOF token is received \non the USB (SOF bit in OTH_FS_GINTSTS). The corresponding frame number can be read \nfrom the device status register (FNSOF bit in OTG_FS_DSTS). An SOF pulse signal with a \nwidth of 20 HCLK cycles is also generated and can be made available externally on the \nOTG_FS_SOF pin by using the SOF output enable bit in the global control and configuration \nregister (SOFOUTEN bit in OTG_FS_GCCFG). The SOF pulse signal is also internally \nconnected to the TIM2 input trigger, so that the input capture feature, the output compare \nfeature and the timer can be triggered by the SOF pulse. The TIM2 connection is enabled \nthrough the ITR1_RMP bits of the TIM2 option register (TIM2_OR).\nThe end of periodic frame interrupt (GINTSTS/EOPF) is used to notify the application when \n80%, 85%, 90% or 95% of the time frame interval elapsed depending on the periodic frame \ninterval field in the device configuration register (PFIVL bit in OTG_FS_DCFG). This feature \ncan be used to determine if all of the isochronous traffic for that frame is complete.\n34.8 \nOTG low-power modes\nTable 198 below defines the STM32 low power modes and their compatibility with the OTG.\n \nTable 198. Compatibility of STM32 low power modes with the OTG\nMode\nDescription\nUSB compatibility\nRun\nMCU fully active\nRequired when USB not in \nsuspend state.\nSleep\nUSB suspend exit causes the device to exit Sleep mode. \nPeripheral registers content is kept.\nAvailable while USB is in \nsuspend state. \nStop\nUSB suspend exit causes the device to exit Stop mode. \nPeripheral registers content is kept(1).\n1.\nWithin Stop mode there are different possible settings. Some restrictions may also exist, please refer to \nSection 5: Power controller (PWR) to understand which (if any) restrictions apply when using OTG.\nAvailable while USB is in \nsuspend state. \nStandby\nPowered-down. The peripheral must be reinitialized after \nexiting Standby mode.\nNot compatible with USB \napplications.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1260/1757\nRM0090 Rev 21\nThe power consumption of the OTG PHY is controlled by three bits in the general core \nconfiguration register:\n•\nPHY power down (GCCFG/PWRDWN)\nIt switches on/off the full-speed transceiver module of the PHY. It must be preliminarily \nset to allow any USB operation.\n•\nA-VBUS sensing enable (GCCFG/VBUSASEN)\nIt switches on/off the VBUS comparators associated with A-device operations. It must \nbe set when in A-device (USB host) mode and during HNP.\n•\nB-VBUS sensing enable (GCCFG/VBUSASEN)\nIt switches on/off the VBUS comparators associated with B-device operations. It must \nbe set when in B-device (USB peripheral) mode and during HNP.\nPower reduction techniques are available while in the USB suspended state, when the USB \nsession is not yet valid or the device is disconnected.\n•\nStop PHY clock (STPPCLK bit in OTG_FS_PCGCCTL)\nWhen setting the stop PHY clock bit in the clock gating control register, most of the \n48 MHz clock domain internal to the OTG full-speed core is switched off by clock \ngating. The dynamic power consumption due to the USB clock switching activity is cut \neven if the 48 MHz clock input is kept running by the application\nMost of the transceiver is also disabled, and only the part in charge of detecting the \nasynchronous resume or remote wake-up event is kept alive.\n•\nGate HCLK (GATEHCLK bit in OTG_FS_PCGCCTL)\nWhen setting the Gate HCLK bit in the clock gating control register, most of the system \nclock domain internal to the OTG_FS core is switched off by clock gating. Only the \nregister read and write interface is kept alive. The dynamic power consumption due to \nthe USB clock switching activity is cut even if the system clock is kept running by the \napplication for other purposes.\n•\nUSB system stop\nWhen the OTG_FS is in the USB suspended state, the application may decide to \ndrastically reduce the overall power consumption by a complete shut down of all the \nclock sources in the system. USB System Stop is activated by first setting the Stop \nPHY clock bit and then configuring the system deep sleep mode in the power control \nsystem module (PWR).\nThe OTG_FS core automatically reactivates both system and USB clocks by \nasynchronous detection of remote wake-up (as an host) or resume (as a device) \nsignaling on the USB.\nTo save dynamic power, the USB data FIFO is clocked only when accessed by the OTG_FS \ncore.\n34.9 \nDynamic update of the OTG_FS_HFIR register\nThe USB core embeds a dynamic trimming capability of SOF framing period in host mode \nallowing to synchronize an external device with the SOF frames. \nWhen the OTG_FS_HFIR register is changed within a current SOF frame, the SOF period \ncorrection is applied in the next frame as described in Figure 391.\n\n\n<>\n\nRM0090 Rev 21\n1261/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nFigure 391. Updating OTG_FS_HFIR dynamically\n34.10 \nUSB data FIFOs\nThe USB system features 1.25 Kbyte of dedicated RAM with a sophisticated FIFO control \nmechanism. The packet FIFO controller module in the OTG_FS core organizes RAM space \ninto Tx-FIFOs into which the application pushes the data to be temporarily stored before the \nUSB transmission, and into a single Rx FIFO where the data received from the USB are \ntemporarily stored before retrieval (popped) by the application. The number of instructed \nFIFOs and how these are organized inside the RAM depends on the device’s role. In \nperipheral mode an additional Tx-FIFO is instructed for each active IN endpoint. Any FIFO \nsize is software configured to better meet the application requirements.\n400\n…\n…\n…\n…\n450\nLatency \nSOF \nreload \nOTG_FS_HFIR \nwrite \nvalue \nFrame\ntimer \nOld OTG_FS_HIFR value\n= 400 periods\nOTG_FS_HIFR value\n= 450 periods+HIFR write latency\nNew OTG_FS_HIFR value\n= 450 periods\n1\n400\n0\n399\n1\n400\n0\n399\n450\n449\n1\n450\n0\n449\n1\n450\n0\n449\nOTG_FS_HFIR \nai184\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1262/1757\nRM0090 Rev 21\n34.11 \nPeripheral FIFO architecture\nFigure 392. Device-mode FIFO address mapping and AHB FIFO access mapping\n34.11.1 \nPeripheral Rx FIFO\nThe OTG peripheral uses a single receive FIFO that receives the data directed to all OUT \nendpoints. Received packets are stacked back-to-back until free space is available in the \nRx-FIFO. The status of the received packet (which contains the OUT endpoint destination \nnumber, the byte count, the data PID and the validity of the received data) is also stored by \nthe core on top of the data payload. When no more space is available, host transactions are \nNACKed and an interrupt is received on the addressed endpoint. The size of the receive \nFIFO is configured in the receive FIFO Size register (GRXFSIZ).\nThe single receive FIFO architecture makes it more efficient for the USB peripheral to fill in \nthe receive RAM buffer:\n•\nAll OUT endpoints share the same RAM buffer (shared FIFO)\n•\nThe OTG FS core can fill in the receive FIFO up to the limit for any host sequence of \nOUT tokens\nThe application keeps receiving the Rx-FIFO non-empty interrupt (RXFLVL bit in \nOTG_FS_GINTSTS) as long as there is at least one packet available for download. It reads \nthe packet information from the receive status read and pop register (GRXSTSP) and finally \npops data off the receive FIFO by reading from the endpoint-related pop address.\nMSv72655V1\nIN endpoint Tx FIFO #nDFIFO \npush accessfrom AHB\nAny OUT endpoint DFIFO \npopaccess from AHB\nDedicated \nTxFIFO #n \ncontrol(optional)\nDedicated \nTxFIFO #1 \ncontrol(optional)\nRx FIFO control\nIN endpoint Tx FIFO #1DFIFO \npush accessfrom AHB\nMAC pop\nMAC pop\nMAC push\nSingle dataFIFO\nTx FIFO #npacket\nTx FIFO #0 packet\nDIEPTXF2[31:16]\nDIEPTXF2[15:0]\nDIEPTXF1[31:16]\nGNPTXFSIZ[31:16]\nIN endpoint Tx FIFO #0DFIFO \npush accessfrom AHB\nDedicated \nTxFIFO #0 \ncontrol(optional)\nMAC pop\nTx FIFO #1 packet\nRx packets\n...\n...\n...\nGNPTXFSIZ[15:0]\nGRXFSIZ[15:0]\nA1 = 0\n(Rx start address \nfixed to 0)\nDIEPTXFx[15:0]\nDIEPTXF1[15:0]\n\n\n<>\n\nRM0090 Rev 21\n1263/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34.11.2 \nPeripheral Tx FIFOs\nThe core has a dedicated FIFO for each IN endpoint. The application configures FIFO sizes \nby writing the non periodic transmit FIFO size register (OTG_FS_TX0FSIZ) for IN endpoint0 \nand the device IN endpoint transmit FIFOx registers (DIEPTXFx) for IN endpoint-x.\n34.12 \nHost FIFO architecture\nFigure 393. Host-mode FIFO address mapping and AHB FIFO access mapping\n34.12.1 \nHost Rx FIFO\nThe host uses one receiver FIFO for all periodic and nonperiodic transactions. The FIFO is \nused as a receive buffer to hold the received data (payload of the received packet) from the \nUSB until it is transferred to the system memory. Packets received from any remote IN \nendpoint are stacked back-to-back until free space is available. The status of each received \npacket with the host channel destination, byte count, data PID and validity of the received \ndata are also stored into the FIFO. The size of the receive FIFO is configured in the receive \nFIFO size register (GRXFSIZ).\nThe single receive FIFO architecture makes it highly efficient for the USB host to fill in the \nreceive data buffer:\n•\nAll IN configured host channels share the same RAM buffer (shared FIFO)\n•\nThe OTG FS core can fill in the receive FIFO up to the limit for any sequence of IN \ntokens driven by the host software\nThe application receives the Rx FIFO not-empty interrupt as long as there is at least one \npacket available for download. It reads the packet information from the receive status read \nand pop register and finally pops the data off the receive FIFO.\nAny periodic channel\nDFIFO push access\nfrom AHB\nAny channel DFIFO pop\naccess from AHB\nPeriodic Tx\nFIFO control\n(optional)\nNon-periodic\nTx FIFO control\nRx FIFO control\nAny non-periodic\nchannel DFIFO push\naccess from AHB\nMAC pop\nMAC pop\nMAC push\nSingle data\nFIFO\nPeriodic Tx packets\nPeriodic Tx packets\nRx packets\nHPTXFSIZ[31:16]\nHPTXFSIZ[15:0]\nNPTXFSIZ[31:16]\nNPTXFSIZ[15:0]\nRXFSIZ[31:16]\nRx start address\nfixed to 0\nA1 = 0\nai15610\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1264/1757\nRM0090 Rev 21\n34.12.2 \nHost Tx FIFOs\nThe host uses one transmit FIFO for all non-periodic (control and bulk) OUT transactions \nand one transmit FIFO for all periodic (isochronous and interrupt) OUT transactions. FIFOs \nare used as transmit buffers to hold the data (payload of the transmit packet) to be \ntransmitted over the USB. The size of the periodic (nonperiodic) Tx FIFO is configured in the \nhost periodic (nonperiodic) transmit FIFO size (HPTXFSIZ/HNPTXFSIZ) register.\nThe two Tx FIFO implementation derives from the higher priority granted to the periodic type \nof traffic over the USB frame. At the beginning of each frame, the built-in host scheduler \nprocesses the periodic request queue first, followed by the nonperiodic request queue.\nThe two transmit FIFO architecture provides the USB host with separate optimization for \nperiodic and nonperiodic transmit data buffer management:\n•\nAll host channels configured to support periodic (nonperiodic) transactions in the OUT \ndirection share the same RAM buffer (shared FIFOs)\n•\nThe OTG FS core can fill in the periodic (nonperiodic) transmit FIFO up to the limit for \nany sequence of OUT tokens driven by the host software\nThe OTG_FS core issues the periodic Tx FIFO empty interrupt (PTXFE bit in \nOTG_FS_GINTSTS) as long as the periodic Tx-FIFO is half or completely empty, \ndepending on the value of the periodic Tx-FIFO empty level bit in the AHB configuration \nregister (PTXFELVL bit in OTG_FS_GAHBCFG). The application can push the transmission \ndata in advance as long as free space is available in both the periodic Tx FIFO and the \nperiodic request queue. The host periodic transmit FIFO and queue status register \n(HPTXSTS) can be read to know how much space is available in both.\nOTG_FS core issues the non periodic Tx FIFO empty interrupt (NPTXFE bit in \nOTG_FS_GINTSTS) as long as the nonperiodic Tx FIFO is half or completely empty \ndepending on the non periodic Tx FIFO empty level bit in the AHB configuration register \n(TXFELVL bit in OTG_FS_GAHBCFG). The application can push the transmission data as \nlong as free space is available in both the nonperiodic Tx FIFO and nonperiodic request \nqueue. The host nonperiodic transmit FIFO and queue status register (HNPTXSTS) can be \nread to know how much space is available in both.\n34.13 \nFIFO RAM allocation\n34.13.1 \nDevice mode\nReceive FIFO RAM allocation: the application should allocate RAM for SETUP Packets: \n10 locations must be reserved in the receive FIFO to receive SETUP packets on control \nendpoint. The core does not use these locations, which are reserved for SETUP packets, to \nwrite any other data. One location is to be allocated for Global OUT NAK. Status information \nis written to the FIFO along with each received packet. Therefore, a minimum space of \n(Largest Packet Size / 4) + 1 must be allocated to receive packets. If multiple isochronous \nendpoints are enabled, then at least two (Largest Packet Size / 4) + 1 spaces must be \nallocated to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 1 \nspaces are recommended so that when the previous packet is being transferred to the CPU, \nthe USB can receive the subsequent packet. \nAlong with the last packet for each endpoint, transfer complete status information is also \npushed to the FIFO. Typically, one location for each OUT endpoint is recommended.\n\n\n<>\n\nRM0090 Rev 21\n1265/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nTransmit FIFO RAM allocation: the minimum RAM space required for each IN Endpoint \nTransmit FIFO is the maximum packet size for that particular IN endpoint. \nNote:\nMore space allocated in the transmit IN Endpoint FIFO results in better performance on the \nUSB. \n34.13.2 \nHost mode\nReceive FIFO RAM allocation\nStatus information is written to the FIFO along with each received packet. Therefore, a \nminimum space of (Largest Packet Size / 4) + 1 must be allocated to receive packets. If \nmultiple isochronous channels are enabled, then at least two (Largest Packet Size / 4) + 1 \nspaces must be allocated to receive back-to-back packets. Typically, two (Largest Packet \nSize / 4) + 1 spaces are recommended so that when the previous packet is being \ntransferred to the CPU, the USB can receive the subsequent packet. \nAlong with the last packet in the host channel, transfer complete status information is also \npushed to the FIFO. So one location must be allocated for this. \nTransmit FIFO RAM allocation\nThe minimum amount of RAM required for the host Non-periodic Transmit FIFO is the \nlargest maximum packet size among all supported non-periodic OUT channels.\nTypically, two Largest Packet Sizes worth of space is recommended, so that when the \ncurrent packet is under transfer to the USB, the CPU can get the next packet.\nThe minimum amount of RAM required for host periodic Transmit FIFO is the largest \nmaximum packet size out of all the supported periodic OUT channels. If there is at least one \nIsochronous OUT endpoint, then the space must be at least two times the maximum packet \nsize of that channel. \nNote:\nMore space allocated in the Transmit Non-periodic FIFO results in better performance on \nthe USB.\n34.14 \nUSB system performance\nBest USB and system performance is achieved owing to the large RAM buffers, the highly \nconfigurable FIFO sizes, the quick 32-bit FIFO access through AHB push/pop registers and, \nespecially, the advanced FIFO control mechanism. Indeed, this mechanism allows the \nOTG_FS to fill in the available RAM space at best regardless of the current USB sequence. \nWith these features:\n•\nThe application gains good margins to calibrate its intervention in order to optimize the \nCPU bandwidth usage:\n–\nIt can accumulate large amounts of transmission data in advance compared to \nwhen they are effectively sent over the USB\n–\nIt benefits of a large time margin to download data from the single receive FIFO\n•\nThe USB Core is able to maintain its full operating rate, that is to provide maximum full-\nspeed bandwidth with a great margin of autonomy versus application intervention:\n–\nIt has a large reserve of transmission data at its disposal to autonomously manage \nthe sending of data over the USB\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1266/1757\nRM0090 Rev 21\n–\nIt has a lot of empty space available in the receive buffer to autonomously fill it in \nwith the data coming from the USB\nAs the OTG_FS core is able to fill in the 1.25 Kbyte RAM buffer very efficiently, and as \n1.25 Kbyte of transmit/receive data is more than enough to cover a full speed frame, the \nUSB system is able to withstand the maximum full-speed data rate for up to one USB frame \n(1 ms) without any CPU intervention.\n34.15 \nOTG_FS interrupts\nWhen the OTG_FS controller is operating in one mode, either device or host, the application \nmust not access registers from the other mode. If an illegal access occurs, a mode \nmismatch interrupt is generated and reflected in the Core interrupt register (MMIS bit in the \nOTG_FS_GINTSTS register). When the core switches from one mode to the other, the \nregisters in the new mode of operation must be reprogrammed as they would be after a \npower-on reset.\nFigure 394 shows the interrupt hierarchy.\n\n\n<>\n\nRM0090 Rev 21\n1267/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nFigure 394. Interrupt hierarchy\n1.\nOTG_FS_WKUP become active (high state) when resume condition occurs during L1 SLEEP or L2 SUSPEND states.\nMSv36921V3\nOTG_DAINTMSK\nDevice all endpoints interrupt mask \nregister\nOTG_DIEPMSK/\nOTG_DOEPMSK\nDevice IN/OUT endpoints common \ninterrupt mask register\nOTG_HCTINTMSKx\nHost channels interrupt mask registers\nOTG_HAINTMSK\nHost all channels interrupt mask register\n31:26\n25 24\n23:20\n19 18\n17:3\n2\n1:0\nOTG_HCTINTx\nHost channels interrupt registers\nOTG_HAINT\nHost all channels interrupt register\nOTG_HPRT\nHost port control and status register\nOTG_DAINT\nDevice all endpoints interrupt register\n(15 + #EP):16\nOUT endpoints\n(#EP-1):0\nIN endpoints\nOTG_GOTGINT\nOTG interrupt register\nOTG_DIEPINTx/\nOTG_DOEPINTx\nDevice IN/OUT endpoint interrupt \nregisters\nOTG_GINTSTS\nCore register interrupt\nOTG_GINTMSK\nCore interrupt mask register\nOTG_AHBCFG\nAHB configuration register\nGlobal interrupt mask (bit 0)\nOR\nAND\nGlobal interrupt\nOTG_FS\nWakeup interrupt \nOTG_FS_WKUP\nAND\n(1)\nx = 0\nx = #HC-1\nx = 0\nx = #HC-1\nHCINT\nHPRTINT\nOEPINP\nIEPINT\nOTGINT\n...\n...\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1268/1757\nRM0090 Rev 21\n34.16 \nOTG_FS control and status registers\nBy reading from and writing to the control and status registers (CSRs) through the AHB \nslave interface, the application controls the OTG_FS controller. These registers are 32 bits \nwide, and the addresses are 32-bit block aligned. The OTG_FS registers must be accessed \nby words (32 bits).\nCSRs are classified as follows:\n•\nCore global registers\n•\nHost-mode registers\n•\nHost global registers\n•\nHost port CSRs\n•\nHost channel-specific registers\n•\nDevice-mode registers\n•\nDevice global registers\n•\nDevice endpoint-specific registers\n•\nPower and clock-gating registers\n•\nData FIFO (DFIFO) access registers\nOnly the Core global, Power and clock-gating, Data FIFO access, and host port control and \nstatus registers can be accessed in both host and device modes. When the OTG_FS \ncontroller is operating in one mode, either device or host, the application must not access \nregisters from the other mode. If an illegal access occurs, a mode mismatch interrupt is \ngenerated and reflected in the Core interrupt register (MMIS bit in the OTG_FS_GINTSTS \nregister). When the core switches from one mode to the other, the registers in the new mode \nof operation must be reprogrammed as they would be after a power-on reset.\n\n\n<>\n\nRM0090 Rev 21\n1269/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34.16.1 \nCSR memory map\nThe host and device mode registers occupy different addresses. All registers are \nimplemented in the AHB clock domain.\nFigure 395. CSR memory map\n1.\nx = 3 in device mode and x = 7 in host mode.\nGlobal CSR map\nThese registers are available in both host and device modes.\n \n0000h\nCore global CSRs (1 Kbyte)\n0400h\nHost mode CSRs (1 Kbyte)\n0800h\nDevice mode CSRs (1.5 Kbyte)\n0E00h\nPower and clock gating CSRs (0.5 Kbyte)\n1000h\nDevice EP 0/Host channel 0 FIFO (4 Kbyte)\n2000h\nDevice EP1/Host channel 1 FIFO (4 Kbyte)\n3000h\nDevice EP (x – 1)(1)/Host channel (x – 1)(1) FIFO (4 Kbyte)\nDevice EP x(1)/Host channel x(1) FIFO (4 Kbyte)\nReserved\nDFIFO\npush/pop\nto this region\n2 0000h\n3 FFFFh\nDirect access to data FIFO RAM\nfor debugging (128 Kbyte)\nDFIFO\ndebug read/\nwrite to this\nregion\nai15615b\nTable 199. Core global control and status registers (CSRs)\nAcronym\nAddress \noffset\nRegister name\nOTG_FS_GOTGCTL\n0x000\nOTG_FS control and status register (OTG_FS_GOTGCTL) on page 1274\nOTG_FS_GOTGINT\n0x004\nOTG_FS interrupt register (OTG_FS_GOTGINT) on page 1275\nOTG_FS_GAHBCFG\n0x008\nOTG_FS AHB configuration register (OTG_FS_GAHBCFG) on page 1277\nOTG_FS_GUSBCFG\n0x00C\nOTG_FS USB configuration register (OTG_FS_GUSBCFG) on page 1278\nOTG_FS_GRSTCTL\n0x010\nOTG_FS reset register (OTG_FS_GRSTCTL) on page 1280\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1270/1757\nRM0090 Rev 21\nHost-mode CSR map\nThese registers must be programmed every time the core changes to host mode.\n \nOTG_FS_GINTSTS\n0x014\nOTG_FS core interrupt register (OTG_FS_GINTSTS) on page 1282\nOTG_FS_GINTMSK\n0x018\nOTG_FS interrupt mask register (OTG_FS_GINTMSK) on page 1286\nOTG_FS_GRXSTSR\n0x01C\nOTG_FS Receive status debug read/OTG status read and pop registers \n(OTG_FS_GRXSTSR/OTG_FS_GRXSTSP) on page 1289\nOTG_FS_GRXSTSP\n0x020\nOTG_FS_GRXFSIZ\n0x024\nOTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) on page 1290\nOTG_FS_HNPTXFSIZ/ \nOTG_FS_DIEPTXF0(1)\n0x028\nOTG_FS Host non-periodic transmit FIFO size register \n(OTG_FS_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size \n(OTG_FS_DIEPTXF0)\nOTG_FS_HNPTXSTS\n0x02C\nOTG_FS non-periodic transmit FIFO/queue status register \n(OTG_FS_HNPTXSTS) on page 1291\nOTG_FS_GCCFG\n0x038\nOTG_FS general core configuration register (OTG_FS_GCCFG) on \npage 1292\nOTG_FS_CID\n0x03C\nOTG_FS core ID register (OTG_FS_CID) on page 1293\nOTG_FS_HPTXFSIZ\n0x100\nOTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) on \npage 1294\nOTG_FS_DIEPTXFx\n0x104\n0x108\n0x10C\nOTG_FS device IN endpoint transmit FIFO size register \n(OTG_FS_DIEPTXFx) (x = 1..3, where x is the FIFO_number) on page 1294\n1.\nThe general rule is to use OTG_FS_HNPTXFSIZ for host mode and OTG_FS_DIEPTXF0 for device mode.\nTable 199. Core global control and status registers (CSRs) (continued)\nAcronym\nAddress \noffset\nRegister name\nTable 200. Host-mode control and status registers (CSRs)\nAcronym\nOffset \naddress\nRegister name\nOTG_FS_HCFG\n0x400\nOTG_FS Host configuration register (OTG_FS_HCFG) on page 1295\nOTG_FS_HFIR\n0x404\nOTG_FS Host frame interval register (OTG_FS_HFIR) on page 1295\nOTG_FS_HFNUM\n0x408\nOTG_FS Host frame number/frame time remaining register \n(OTG_FS_HFNUM) on page 1296\nOTG_FS_HPTXSTS\n0x410\nOTG_FS_Host periodic transmit FIFO/queue status register \n(OTG_FS_HPTXSTS) on page 1296\nOTG_FS_HAINT\n0x414\nOTG_FS Host all channels interrupt register (OTG_FS_HAINT) on \npage 1297\nOTG_FS_HAINTMSK\n0x418\nOTG_FS Host all channels interrupt mask register (OTG_FS_HAINTMSK) \non page 1298\n\n\n<>\n\nRM0090 Rev 21\n1271/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nDevice-mode CSR map\nThese registers must be programmed every time the core changes to device mode.\n \nOTG_FS_HPRT\n0x440\nOTG_FS Host port control and status register (OTG_FS_HPRT) on \npage 1298\nOTG_FS_HCCHARx\n0x500\n0x520\n...\n0x5E0\nOTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx) \n(x = 0..7, where x = Channel_number) on page 1301\nOTG_FS_HCINTx\n0x508\nOTG_FS Host channel-x interrupt register (OTG_FS_HCINTx) (x = 0..7, \nwhere x = Channel_number) on page 1302\nOTG_FS_HCINTMSKx\n0x50C\nOTG_FS Host channel-x interrupt mask register (OTG_FS_HCINTMSKx) \n(x = 0..7, where x = Channel_number) on page 1303\nOTG_FS_HCTSIZx\n0x510\nOTG_FS Host channel-x transfer size register (OTG_FS_HCTSIZx) \n(x = 0..7, where x = Channel_number) on page 1304\nTable 200. Host-mode control and status registers (CSRs) (continued)\nAcronym\nOffset \naddress\nRegister name\nTable 201. Device-mode control and status registers\nAcronym\nOffset \naddress\nRegister name\nOTG_FS_DCFG\n0x800\nOTG_FS device configuration register (OTG_FS_DCFG) on page 1305\nOTG_FS_DCTL\n0x804\nOTG_FS device control register (OTG_FS_DCTL) on page 1306\nOTG_FS_DSTS\n0x808\nOTG_FS device status register (OTG_FS_DSTS) on page 1307\nOTG_FS_DIEPMSK\n0x810\nOTG_FS device IN endpoint common interrupt mask register \n(OTG_FS_DIEPMSK) on page 1308\nOTG_FS_DOEPMSK\n0x814\nOTG_FS device OUT endpoint common interrupt mask register \n(OTG_FS_DOEPMSK) on page 1309\nOTG_FS_DAINT\n0x818\nOTG_FS device all endpoints interrupt register (OTG_FS_DAINT) on \npage 1310\nOTG_FS_DAINTMSK\n0x81C\nOTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) on \npage 1311\nOTG_FS_DVBUSDIS\n0x828\nOTG_FS device VBUS discharge time register (OTG_FS_DVBUSDIS) on \npage 1311\nOTG_FS_DVBUSPULSE\n0x82C\nOTG_FS device VBUS pulsing time register (OTG_FS_DVBUSPULSE) \non page 1311\nOTG_FS_DIEPEMPMSK\n0x834\nOTG_FS device IN endpoint FIFO empty interrupt mask register: \n(OTG_FS_DIEPEMPMSK) on page 1312\nOTG_FS_DIEPCTL0\n0x900\nOTG_FS device control IN endpoint 0 control register \n(OTG_FS_DIEPCTL0) on page 1312\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1272/1757\nRM0090 Rev 21\n \nData FIFO (DFIFO) access register map\nThese registers, available in both host and device modes, are used to read or write the FIFO \nspace for a specific endpoint or a channel, in a given direction. If a host channel is of type \nIN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the \nFIFO can only be written on the channel.\n \nOTG_FS_DIEPCTLx\n0x920\n0x940\n0x960\nOTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3, \nwhere x = Endpoint_number) on page 1314\nOTG_FS_DIEPINTx\n0x908\nOTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) \n(x = 0..3, where x = Endpoint_number) on page 1321\nOTG_FS_DIEPTSIZ0\n0x910\nOTG_FS device IN endpoint 0 transfer size register \n(OTG_FS_DIEPTSIZ0) on page 1323\nOTG_FS_DTXFSTSx \n0x918\nOTG_FS device IN endpoint transmit FIFO status register \n(OTG_FS_DTXFSTSx) (x = 0..3, where x = Endpoint_number) on \npage 1327\nOTG_FS_DIEPTSIZx\n0x930\n0x950\n0x970\nOTG_FS device endpoint-x transfer size register (OTG_FS_DIEPTSIZx) \n(x = 1..3, where x = Endpoint_number) on page 1326\nOTG_FS_DOEPCTL0\n0xB00\nOTG_FS device control OUT endpoint 0 control register \n(OTG_FS_DOEPCTL0) on page 1317\nOTG_FS_DOEPCTLx\n0xB20\n0xB40\n0xB60\nOTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3, \nwhere x = Endpoint_number) on page 1314\nOTG_FS_DOEPINTx\n0xB08\nOTG_FS device endpoint-x interrupt register (OTG_FS_DOEPINTx) \n(x = 0..3, where x = Endpoint_number) on page 1322\nOTG_FS_DOEPTSIZ0\n0xB10\nOTG_FS device OUT endpoint 0 transfer size register \n(OTG_FS_DOEPTSIZ0) on page 1325\nOTG_FS_DOEPTSIZx\n0xB30\n0xB50\n0xB70\nOTG_FS device OUT endpoint-x transfer size register \n(OTG_FS_DOEPTSIZx) (x = 1..3, where x = Endpoint_number) on \npage 1327\nTable 201. Device-mode control and status registers (continued)\nAcronym\nOffset \naddress\nRegister name\nTable 202. Data FIFO (DFIFO) access register map\nFIFO access register section\nAddress range\nAccess\nDevice IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access\nDevice OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access\n0x1000–0x1FFC\nw\nr\nDevice IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access\nDevice OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access\n0x2000–0x2FFC\nw\nr\n\n\n<>\n\nRM0090 Rev 21\n1273/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nPower and clock gating CSR map\nThere is a single register for power and clock gating. It is available in both host and device \nmodes.\n \n...\n...\n...\nDevice IN Endpoint x(1)/Host OUT Channel x(1): DFIFO Write Access\nDevice OUT Endpoint x(1)/Host IN Channel x(1): DFIFO Read Access 0xX000–0xXFFC\nw\nr\n1.\nWhere x is 3 in device mode and 7 in host mode.\nTable 203. Power and clock gating control and status registers\nRegister name\nAcronym\nOffset address: 0xE00–0xFFF\nPower and clock gating control register\nOTG_FS_PCGCCTL\n0xE00-0xE04\nReserved\n-\n0xE05–0xFFF\nTable 202. Data FIFO (DFIFO) access register map (continued)\nFIFO access register section\nAddress range\nAccess\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1274/1757\nRM0090 Rev 21\n34.16.2 \nOTG_FS global registers\nThese registers are available in both host and device modes, and do not need to be \nreprogrammed when switching between these modes.\nBit values in the register descriptions are expressed in binary unless otherwise specified.\nOTG_FS control and status register (OTG_FS_GOTGCTL)\nAddress offset: 0x000\nReset value: 0x0001 0000\nThe OTG_FS_GOTGCTL register controls the behavior and reflects the status of the OTG \nfunction of the core.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBSVLD\nASVLD\nDBCT\nCIDSTS\nReserved\nDHNPEN\nHSHNPEN\nHNPRQ\nHNGSCS\nReserved\nSRQ\nSRQSCS\nr\nr\nr\nr\nrw\nrw\nrw\nr\nrw\nr\nBits 31:20 Reserved, must be kept at reset value.\nBit 19 BSVLD: B-session valid\nIndicates the device mode transceiver status.\n0: B-session is not valid.\n1: B-session is valid.\nIn OTG mode, you can use this bit to determine if the device is connected or disconnected.\nNote: Only accessible in device mode.\nBit 18 ASVLD: A-session valid\nIndicates the host mode transceiver status.\n0: A-session is not valid\n1: A-session is valid\nNote: Only accessible in host mode.\nBit 17 DBCT: Long/short debounce time\nIndicates the debounce time of a detected connection.\n0: Long debounce time, used for physical connections (100 ms + 2.5 µs)\n1: Short debounce time, used for soft connections (2.5 µs)\nNote: Only accessible in host mode.\nBit 16 CIDSTS: Connector ID status\nIndicates the connector ID status on a connect event.\n0: The OTG_FS controller is in A-device mode\n1: The OTG_FS controller is in B-device mode\nNote: Accessible in both device and host modes.\nBits 15:12 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n1275/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS interrupt register (OTG_FS_GOTGINT)\nAddress offset: 0x04\nReset value: 0x0000 0000\nBit 11 DHNPEN: Device HNP enabled\nThe application sets this bit when it successfully receives a SetFeature.SetHNPEnable \ncommand from the connected USB host.\n0: HNP is not enabled in the application\n1: HNP is enabled in the application\nNote: Only accessible in device mode.\nBit 10 HSHNPEN: host set HNP enable\nThe application sets this bit when it has successfully enabled HNP (using the \nSetFeature.SetHNPEnable command) on the connected device.\n0: Host Set HNP is not enabled\n1: Host Set HNP is enabled\nNote: Only accessible in host mode.\nBit 9 HNPRQ: HNP request\nThe application sets this bit to initiate an HNP request to the connected USB host. The \napplication can clear this bit by writing a 0 when the host negotiation success status change \nbit in the OTG_FS_GOTGINT register (HNSSCHG bit in OTG_FS_GOTGINT) is set. The \ncore clears this bit when the HNSSCHG bit is cleared.\n0: No HNP request\n1: HNP request\nNote: Only accessible in device mode.\nBit 8 HNGSCS: Host negotiation success\nThe core sets this bit when host negotiation is successful. The core clears this bit when the \nHNP Request (HNPRQ) bit in this register is set.\n0: Host negotiation failure\n1: Host negotiation success\nNote: Only accessible in device mode.\nBits 7:2 Reserved, must be kept at reset value.\nBit 1 SRQ: Session request\nThe application sets this bit to initiate a session request on the USB. The application can \nclear this bit by writing a 0 when the host negotiation success status change bit in the \nOTG_FS_GOTGINT register (HNSSCHG bit in OTG_FS_GOTGINT) is set. The core clears \nthis bit when the HNSSCHG bit is cleared.\nIf you use the USB 1.1 full-speed serial transceiver interface to initiate the session request, \nthe application must wait until VBUS discharges to 0.2 V, after the B-Session Valid bit in this \nregister (BSVLD bit in OTG_FS_GOTGCTL) is cleared.\n0: No session request\n1: Session request\nNote: Only accessible in device mode.\nBit 0 SRQSCS: Session request success\nThe core sets this bit when a session request initiation is successful.\n0: Session request failure\n1: Session request success\nNote: Only accessible in device mode.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1276/1757\nRM0090 Rev 21\nThe application reads this register whenever there is an OTG interrupt and clears the bits in \nthis register to clear the OTG interrupt.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDBCDNE\nADTOCHG\nHNGDET\nReserved\nHNSSCHG\nSRSSCHG\nReserved\nSEDET\nRes.\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nBits 31:20 Reserved, must be kept at reset value.\nBit 19 DBCDNE: Debounce done\nThe core sets this bit when the debounce is completed after the device connect. The \napplication can start driving USB reset after seeing this interrupt. This bit is only valid when \nthe HNP Capable or SRP Capable bit is set in the OTG_FS_GUSBCFG register (HNPCAP \nbit or SRPCAP bit in OTG_FS_GUSBCFG, respectively).\nNote: Only accessible in host mode.\nBit 18 ADTOCHG: A-device timeout change\nThe core sets this bit to indicate that the A-device has timed out while waiting for the B-device \nto connect.\nNote: Accessible in both device and host modes.\nBit 17 HNGDET: Host negotiation detected\nThe core sets this bit when it detects a host negotiation request on the USB. \nNote: Accessible in both device and host modes.\nBits 16:10 Reserved, must be kept at reset value.\nBit 9 HNSSCHG: Host negotiation success status change\nThe core sets this bit on the success or failure of a USB host negotiation request. The \napplication must read the host negotiation success bit of the OTG_FS_GOTGCTL register \n(HNGSCS in OTG_FS_GOTGCTL) to check for success or failure.\nNote: Accessible in both device and host modes.\nBits 7:3 Reserved, must be kept at reset value.\nBit 8 SRSSCHG: Session request success status change\nThe core sets this bit on the success or failure of a session request. The application must \nread the session request success bit in the OTG_FS_GOTGCTL register (SRQSCS bit in \nOTG_FS_GOTGCTL) to check for success or failure.\nNote: Accessible in both device and host modes.\nBit 2 SEDET: Session end detected\nThe core sets this bit to indicate that the level of the voltage on VBUS is no longer valid for a \nB-Peripheral session when VBUS < 0.8 V.\nBits 1:0 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n1277/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS AHB configuration register (OTG_FS_GAHBCFG)\nAddress offset: 0x008\nReset value: 0x0000 0000\nThis register can be used to configure the core after power-on or a change in mode. This \nregister mainly contains AHB system-related configuration parameters. Do not change this \nregister after the initial programming. The application must program this register before \nstarting any transactions on either the AHB or the USB.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPTXFELVL\nTXFELVL\nReserved\nGINTMSK\nrw\nrw\nrw\nBits 31:9 Reserved, must be kept at reset value.\nBit 8 PTXFELVL: Periodic TxFIFO empty level\nIndicates when the periodic TxFIFO empty interrupt bit in the OTG_FS_GINTSTS register \n(PTXFE bit in OTG_FS_GINTSTS) is triggered.\n0: PTXFE (in OTG_FS_GINTSTS) interrupt indicates that the Periodic TxFIFO is half empty\n1: PTXFE (in OTG_FS_GINTSTS) interrupt indicates that the Periodic TxFIFO is completely \nempty\nNote: Only accessible in host mode.\nBit 7 TXFELVL: TxFIFO empty level\nIn device mode, this bit indicates when IN endpoint Transmit FIFO empty interrupt (TXFE in \nOTG_FS_DIEPINTx.) is triggered.\n0: the TXFE (in OTG_FS_DIEPINTx) interrupt indicates that the IN Endpoint TxFIFO is half \nempty\n1: the TXFE (in OTG_FS_DIEPINTx) interrupt indicates that the IN Endpoint TxFIFO is \ncompletely empty\nIn host mode, this bit indicates when the nonperiodic Tx FIFO empty interrupt (NPTXFE bit in \nOTG_FS_GINTSTS) is triggered:\n0: the NPTXFE (in OTG_FS_GINTSTS) interrupt indicates that the nonperiodic Tx FIFO is \nhalf empty\n1: the NPTXFE (in OTG_FS_GINTSTS) interrupt indicates that the nonperiodic Tx FIFO is \ncompletely empty\nBits 6:1 Reserved, must be kept at reset value.\nBit 0 GINTMSK: Global interrupt mask\nThe application uses this bit to mask or unmask the interrupt line assertion to itself. \nIrrespective of this bit’s setting, the interrupt status registers are updated by the core.\n0: Mask the interrupt assertion to the application.\n1: Unmask the interrupt assertion to the application.\nNote: Accessible in both device and host modes.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1278/1757\nRM0090 Rev 21\nOTG_FS USB configuration register (OTG_FS_GUSBCFG)\nAddress offset: 0x00C\nReset value: 0x0000 0A40\nThis register can be used to configure the core after power-on or a changing to host mode \nor device mode. It contains USB and USB-PHY related configuration parameters. The \napplication must program this register before starting any transactions on either the AHB or \nthe USB. Do not make changes to this register after the initial programming.\n \n \n31\n30\n29\n28 27 26 25 24 23 22 21 20 19 18 17 16 15 14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCTXPKT\nFDMOD\nFHMOD\nReserved\nTRDT\nHNPCA\nP\nSRPCAP\nRes.\nPHYSEL\nReserved\nTOCAL\nrw\nrw\nrw\nrw\nrw\nrw\nr\nrw\nBit 31 CTXPKT: Corrupt Tx packet\nThis bit is for debug purposes only. Never set this bit to 1.\nNote: Accessible in both device and host modes.\nBit 30 FDMOD: Force device mode\nWriting a 1 to this bit forces the core to device mode irrespective of the OTG_FS_ID input \npin.\n0: Normal mode\n1: Force device mode\nAfter setting the force bit, the application must wait at least 25 ms before the change takes \neffect.\nNote: Accessible in both device and host modes.\nBit 29 FHMOD: Force host mode\nWriting a 1 to this bit forces the core to host mode irrespective of the OTG_FS_ID input pin.\n0: Normal mode\n1: Force host mode\nAfter setting the force bit, the application must wait at least 25 ms before the change takes \neffect.\nNote: Accessible in both device and host modes.\nBits 28:14 Reserved, must be kept at reset value.\nBits 13:10 TRDT: USB turnaround time\nThese bits allow setting the turnaround time in PHY clocks. They must be configured \naccording to Table 204: TRDT values, depending on the application AHB frequency. Higher \nTRDT values allow stretching the USB response time to IN tokens in order to compensate for \nlonger AHB read access latency to the Data FIFO. \nNote: Only accessible in device mode.\nBit 9 HNPCAP: HNP-capable\nThe application uses this bit to control the OTG_FS controller’s HNP capabilities.\n0: HNP capability is not enabled.\n1: HNP capability is enabled.\nNote: Accessible in both device and host modes.\n\n\n<>\n\nRM0090 Rev 21\n1279/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n \nBit 8 SRPCAP: SRP-capable\nThe application uses this bit to control the OTG_FS controller’s SRP capabilities. If the core \noperates as a non-SRP-capable \nB-device, it cannot request the connected A-device (host) to activate VBUS and start a \nsession.\n0: SRP capability is not enabled.\n1: SRP capability is enabled.\nNote: Accessible in both device and host modes.\nBit 7 Reserved, must be kept at reset value.\nBit 6 PHYSEL: Full speed serial transceiver select\nThis bit is always 1 with read-only access.\nBits 5:3 Reserved, must be kept at reset value.\nBits 2:0 TOCAL: FS timeout calibration\nThe number of PHY clocks that the application programs in this field is added to the full-\nspeed interpacket timeout duration in the core to account for any additional delays \nintroduced by the PHY. This can be required, because the delay introduced by the PHY in \ngenerating the line state condition can vary from one PHY to another.\nThe USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The \napplication must program this field based on the speed of enumeration. The number of bit \ntimes added per PHY clock is 0.25 bit times.\nTable 204. TRDT values\nAHB frequency range (MHz)\nTRDT minimum value\nMin.\nMax\n14.2\n15\n0xF\n15\n16\n0xE\n16\n17.2\n0xD\n17.2\n18.5\n0xC\n18.5\n20\n0xB\n20\n21.8\n0xA\n21.8\n24\n0x9\n24\n27.5\n0x8\n27.5\n32\n0x7\n32\n-\n0x6\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1280/1757\nRM0090 Rev 21\nOTG_FS reset register (OTG_FS_GRSTCTL)\nAddress offset: 0x010\nReset value: 0x8000 0000\nThe application uses this register to reset various hardware features inside the core.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nAHBIDL\nReserved\nTXFNUM\nTXFFLSH\nRXFFLSH\nReserved\nFCRST\nHSRST\nCSRST\nr\nrw\nrs\nrs\nrs\nrs\nrs\nBit 31 AHBIDL: AHB master idle\nIndicates that the AHB master state machine is in the Idle condition.\nNote: Accessible in both device and host modes.\nBits 30:11 Reserved, must be kept at reset value.\nBits 10:6 TXFNUM: TxFIFO number\nThis is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not \nbe changed until the core clears the TxFIFO Flush bit.\n00000:\n–\nNon-periodic TxFIFO flush in host mode\n–\nTx FIFO 0 flush in device mode\n00001:\n–\nPeriodic TxFIFO flush in host mode\n–\nTXFIFO 1 flush in device mode \n00010: TXFIFO 2 flush in device mode \n...\n00101: TXFIFO 15 flush in device mode \n10000: Flush all the transmit FIFOs in device or host mode.\nNote: Accessible in both device and host modes.\nBit 5 TXFFLSH: TxFIFO flush\nThis bit selectively flushes a single or all transmit FIFOs, but cannot do so if the core is in the \nmidst of a transaction.\nThe application must write this bit only after checking that the core is neither writing to the \nTxFIFO nor reading from the TxFIFO. Verify using these registers:\nRead—NAK Effective Interrupt ensures the core is not reading from the FIFO\nWrite—AHBIDL bit in OTG_FS_GRSTCTL ensures the core is not writing anything to the \nFIFO.\nNote: Accessible in both device and host modes.\nBit 4 RXFFLSH: RxFIFO flush\nThe application can flush the entire RxFIFO using this bit, but must first ensure that the core \nis not in the middle of a transaction.\nThe application must only write to this bit after checking that the core is neither reading from \nthe RxFIFO nor writing to the RxFIFO.\nThe application must wait until the bit is cleared before performing any other operations. This \nbit requires 8 clocks (slowest of PHY or AHB clock) to clear.\nNote: Accessible in both device and host modes.\nBit 3 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n1281/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nBit 2 FCRST: Host frame counter reset\nThe application writes this bit to reset the frame number counter inside the core. When the \nframe counter is reset, the subsequent SOF sent out by the core has a frame number of 0.\nNote: Only accessible in host mode.\nBit 1 HSRST: HCLK soft reset\nThe application uses this bit to flush the control logic in the AHB Clock domain. Only AHB \nClock Domain pipelines are reset.\nFIFOs are not flushed with this bit.\nAll state machines in the AHB clock domain are reset to the Idle state after terminating the \ntransactions on the AHB, following the protocol.\nCSR control bits used by the AHB clock domain state machines are cleared.\nTo clear this interrupt, status mask bits that control the interrupt status and are generated by \nthe AHB clock domain state machine are cleared.\nBecause interrupt status bits are not cleared, the application can get the status of any core \nevents that occurred after it set this bit.\nThis is a self-clearing bit that the core clears after all necessary logic is reset in the core. This \ncan take several clocks, depending on the core’s current state.\nNote: Accessible in both device and host modes.\nBit 0 CSRST: Core soft reset\nResets the HCLK and PCLK domains as follows:\nClears the interrupts and all the CSR register bits except for the following bits:\n– RSTPDMODL bit in OTG_FS_PCGCCTL\n– GAYEHCLK bit in OTG_FS_PCGCCTL\n– PWRCLMP bit in OTG_FS_PCGCCTL\n– STPPCLK bit in OTG_FS_PCGCCTL\n– FSLSPCS bit in OTG_FS_HCFG\n– DSPD bit in OTG_FS_DCFG\nAll module state machines (except for the AHB slave unit) are reset to the Idle state, and all \nthe transmit FIFOs and the receive FIFO are flushed.\nAny transactions on the AHB Master are terminated as soon as possible, after completing the \nlast data phase of an AHB transfer. Any transactions on the USB are terminated immediately.\nThe application can write to this bit any time it wants to reset the core. This is a self-clearing \nbit and the core clears this bit after all the necessary logic is reset in the core, which can take \nseveral clocks, depending on the current state of the core. Once this bit has been cleared, \nthe software must wait at least 3 PHY clocks before accessing the PHY domain \n(synchronization delay). The software must also check that bit 31 in this register is set to 1 \n(AHB Master is Idle) before starting any operation.\nTypically, the software reset is used during software development and also when you \ndynamically change the PHY selection bits in the above listed USB configuration registers. \nWhen you change the PHY, the corresponding clock for the PHY is selected and used in the \nPHY domain. Once a new clock is selected, the PHY domain has to be reset for proper \noperation.\nNote: Accessible in both device and host modes.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1282/1757\nRM0090 Rev 21\nOTG_FS core interrupt register (OTG_FS_GINTSTS)\nAddress offset: 0x014\nReset value: 0x0400 0020\nThis register interrupts the application for system-level events in the current mode (device \nmode or host mode).\nSome of the bits in this register are valid only in host mode, while others are valid in device \nmode only. This register also indicates the current mode. To clear the interrupt status bits of \nthe rc_w1 type, the application must write 1 into the bit.\nThe FIFO status interrupts are read-only; once software reads from or writes to the FIFO \nwhile servicing these interrupts, FIFO interrupt conditions are cleared automatically.\nThe application must clear the OTG_FS_GINTSTS register at initialization before \nunmasking the interrupt bit to avoid any interrupts generated prior to initialization.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nWKUINT\nSRQINT\nDISCINT\nCIDSCHG\nReserved\nPTXFE\nHCINT\nHPRTINT\nReserved\nIPXFR/INCOMPISOOUT\nIISOIXFR\nOEPINT\nIEPINT\nReserved\nEOPF\nISOODRP\nENUMDNE\nUSBRST\nUSBSUSP\nESUSP\nReserved\nGONAKEFF\nGINAKEFF\nNPTXFE\nRXFLVL\nSOF\nOTGINT\nMMIS\nCMOD\nrc_w1\nr\nr\nr\nRes.\nrc_w1\nr\nr\nrc_w1\nr\nr\nr\nr\nrc_w1\nr\nrc_w1\nr\nBit 31 WKUPINT: Resume/remote wake-up detected interrupt\nIn device mode, this interrupt is asserted when a resume is detected on the USB. In host \nmode, this interrupt is asserted when a remote wake-up is detected on the USB.\nNote: Accessible in both device and host modes.\nBit 30 SRQINT: Session request/new session detected interrupt\nIn host mode, this interrupt is asserted when a session request is detected from the device. \nIn device mode, this interrupt is asserted when VBUS is in the valid range for a B-peripheral \ndevice. Accessible in both device and host modes.\nBit 29 DISCINT: Disconnect detected interrupt\nAsserted when a device disconnect is detected.\nNote: Only accessible in host mode.\nBit 28 CIDSCHG: Connector ID status change\nThe core sets this bit when there is a change in connector ID status.\nNote: Accessible in both device and host modes.\nBit 27 Reserved, must be kept at reset value.\nBit 26 PTXFE: Periodic TxFIFO empty\nAsserted when the periodic transmit FIFO is either half or completely empty and there is \nspace for at least one entry to be written in the periodic request queue. The half or \ncompletely empty status is determined by the periodic TxFIFO empty level bit in the \nOTG_FS_GAHBCFG register (PTXFELVL bit in OTG_FS_GAHBCFG).\nNote: Only accessible in host mode.\n\n\n<>\n\nRM0090 Rev 21\n1283/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nBit 25 HCINT: Host channels interrupt\nThe core sets this bit to indicate that an interrupt is pending on one of the channels of the \ncore (in host mode). The application must read the OTG_FS_HAINT register to determine \nthe exact number of the channel on which the interrupt occurred, and then read the \ncorresponding OTG_FS_HCINTx register to determine the exact cause of the interrupt. The \napplication must clear the appropriate status bit in the OTG_FS_HCINTx register to clear \nthis bit.\nNote: Only accessible in host mode.\nBit 24 HPRTINT: Host port interrupt\nThe core sets this bit to indicate a change in port status of one of the OTG_FS controller \nports in host mode. The application must read the OTG_FS_HPRT register to determine the \nexact event that caused this interrupt. The application must clear the appropriate status bit in \nthe OTG_FS_HPRT register to clear this bit.\nNote: Only accessible in host mode.\nBits 23:22 Reserved, must be kept at reset value.\nBit 21 IPXFR: Incomplete periodic transfer\nIn host mode, the core sets this interrupt bit when there are incomplete periodic transactions \nstill pending, which are scheduled for the current frame.\nINCOMPISOOUT: Incomplete isochronous OUT transfer\nIn device mode, the core sets this interrupt to indicate that there is at least one isochronous \nOUT endpoint on which the transfer is not completed in the current frame. This interrupt is \nasserted along with the End of periodic frame interrupt (EOPF) bit in this register.\nBit 20 IISOIXFR: Incomplete isochronous IN transfer\nThe core sets this interrupt to indicate that there is at least one isochronous IN endpoint on \nwhich the transfer is not completed in the current frame. This interrupt is asserted along with \nthe End of periodic frame interrupt (EOPF) bit in this register.\nNote: Only accessible in device mode.\nBit 19 OEPINT: OUT endpoint interrupt\nThe core sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of \nthe core (in device mode). The application must read the OTG_FS_DAINT register to \ndetermine the exact number of the OUT endpoint on which the interrupt occurred, and then \nread the corresponding OTG_FS_DOEPINTx register to determine the exact cause of the \ninterrupt. The application must clear the appropriate status bit in the corresponding \nOTG_FS_DOEPINTx register to clear this bit.\nNote: Only accessible in device mode.\nBit 18 IEPINT: IN endpoint interrupt\nThe core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the \ncore (in device mode). The application must read the OTG_FS_DAINT register to determine \nthe exact number of the IN endpoint on which the interrupt occurred, and then read the \ncorresponding OTG_FS_DIEPINTx register to determine the exact cause of the interrupt. \nThe application must clear the appropriate status bit in the corresponding \nOTG_FS_DIEPINTx register to clear this bit.\nNote: Only accessible in device mode.\nBits 17:16 Reserved, must be kept at reset value.\nBit 15 EOPF: End of periodic frame interrupt\nIndicates that the period specified in the periodic frame interval field of the OTG_FS_DCFG \nregister (PFIVL bit in OTG_FS_DCFG) has been reached in the current frame.\nNote: Only accessible in device mode.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1284/1757\nRM0090 Rev 21\nBit 14 ISOODRP: Isochronous OUT packet dropped interrupt\nThe core sets this bit when it fails to write an isochronous OUT packet into the RxFIFO \nbecause the RxFIFO does not have enough space to accommodate a maximum size packet \nfor the isochronous OUT endpoint.\nNote: Only accessible in device mode.\nBit 13 ENUMDNE: Enumeration done\nThe core sets this bit to indicate that speed enumeration is complete. The application must \nread the OTG_FS_DSTS register to obtain the enumerated speed.\nNote: Only accessible in device mode.\nBit 12 USBRST: USB reset\nThe core sets this bit to indicate that a reset is detected on the USB.\nNote: Only accessible in device mode.\nBit 11 USBSUSP: USB suspend\nThe core sets this bit to indicate that a suspend was detected on the USB. The core enters \nthe Suspended state when there is no activity on the data lines for a period of 3 ms.\nNote: Only accessible in device mode.\nBit 10 ESUSP: Early suspend\nThe core sets this bit to indicate that an Idle state has been detected on the USB for 3 ms.\nNote: Only accessible in device mode.\nBits 9:8 Reserved, must be kept at reset value.\nBit 7 GONAKEFF: Global OUT NAK effective\nIndicates that the Set global OUT NAK bit in the OTG_FS_DCTL register (SGONAK bit in \nOTG_FS_DCTL), set by the application, has taken effect in the core. This bit can be cleared \nby writing the Clear global OUT NAK bit in the OTG_FS_DCTL register (CGONAK bit in \nOTG_FS_DCTL).\nNote: Only accessible in device mode.\nBit 6 GINAKEFF: Global IN non-periodic NAK effective\nIndicates that the Set global non-periodic IN NAK bit in the OTG_FS_DCTL register \n(SGINAK bit in OTG_FS_DCTL), set by the application, has taken effect in the core. That is, \nthe core has sampled the Global IN NAK bit set by the application. This bit can be cleared by \nclearing the Clear global non-periodic IN NAK bit in the OTG_FS_DCTL register (CGINAK \nbit in OTG_FS_DCTL).\nThis interrupt does not necessarily mean that a NAK handshake is sent out on the USB. The \nSTALL bit takes precedence over the NAK bit.\nNote: Only accessible in device mode.\nBit 5 NPTXFE: Non-periodic TxFIFO empty\nThis interrupt is asserted when the non-periodic TxFIFO is either half or completely empty, \nand there is space for at least one entry to be written to the non-periodic transmit request \nqueue. The half or completely empty status is determined by the non-periodic TxFIFO empty \nlevel bit in the OTG_FS_GAHBCFG register (TXFELVL bit in OTG_FS_GAHBCFG).\nNote: Accessible in host mode only.\nBit 4 RXFLVL: RxFIFO non-empty\nIndicates that there is at least one packet pending to be read from the RxFIFO.\nNote: Accessible in both host and device modes.\n\n\n<>\n\nRM0090 Rev 21\n1285/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nBit 3 SOF: Start of frame\nIn host mode, the core sets this bit to indicate that an SOF (FS), or Keep-Alive (LS) is \ntransmitted on the USB. The application must write a 1 to this bit to clear the interrupt.\nIn device mode, in the core sets this bit to indicate that an SOF token has been received on \nthe USB. The application can read the Device Status register to get the current frame \nnumber. This interrupt is seen only when the core is operating in FS.\nNote: Accessible in both host and device modes.\nBit 2 OTGINT: OTG interrupt\nThe core sets this bit to indicate an OTG protocol event. The application must read the OTG \nInterrupt Status (OTG_FS_GOTGINT) register to determine the exact event that caused this \ninterrupt. The application must clear the appropriate status bit in the OTG_FS_GOTGINT \nregister to clear this bit.\nNote: Accessible in both host and device modes.\nBit 1 MMIS: Mode mismatch interrupt\nThe core sets this bit when the application is trying to access:\n–\nA host mode register, when the core is operating in device mode\n–\nA device mode register, when the core is operating in host mode\nThe register access is completed on the AHB with an OKAY response, but is ignored by the \ncore internally and does not affect the operation of the core.\nNote: Accessible in both host and device modes.\nBit 0 CMOD: Current mode of operation\nIndicates the current mode.\n0: Device mode\n1: Host mode\nNote: Accessible in both host and device modes.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1286/1757\nRM0090 Rev 21\nOTG_FS interrupt mask register (OTG_FS_GINTMSK)\nAddress offset: 0x018\nReset value: 0x0000 0000\nThis register works with the Core interrupt register to interrupt the application. When an \ninterrupt bit is masked, the interrupt associated with that bit is not generated. However, the \nCore Interrupt (OTG_FS_GINTSTS) register bit corresponding to that interrupt is still set.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nWUIM\nSRQIM\nDISCINT\nCIDSCHGM\nReserved\nPTXFEM\nHCIM\nPRTIM\nReserved\nIPXFRM/IISOOXFRM\nIISOIXFRM\nOEPINT\nIEPINT\nReserved\nEOPFM\nISOODRPM\nENUMDNEM\nUSBRST\nUSBSUSPM\nESUSPM\nReserved\nGONAKEFFM\nGINAKEFFM\nNPTXFEM\nRXFLVLM\nSOFM\nOTGINT\nMMISM\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 WUIM: Resume/remote wake-up detected interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both host and device modes.\nBit 30 SRQIM: Session request/new session detected interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both host and device modes.\nBit 29 DISCINT: Disconnect detected interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 28 CIDSCHGM: Connector ID status change mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both host and device modes.\nBit 27 Reserved, must be kept at reset value.\nBit 26 PTXFEM: Periodic TxFIFO empty mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in host mode.\nBit 25 HCIM: Host channels interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in host mode.\nBit 24 PRTIM: Host port interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in host mode.\n\n\n<>\n\nRM0090 Rev 21\n1287/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nBits 23:22 Reserved, must be kept at reset value.\nBit 21 IPXFRM: Incomplete periodic transfer mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in host mode.\nIISOOXFRM: Incomplete isochronous OUT transfer mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 20 IISOIXFRM: Incomplete isochronous IN transfer mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 19 OEPINT: OUT endpoints interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 18 IEPINT: IN endpoints interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBits 17:16 Reserved, must be kept at reset value.\nBit 15 EOPFM: End of periodic frame interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 14 ISOODRPM: Isochronous OUT packet dropped interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 13 ENUMDNEM: Enumeration done mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 12 USBRST: USB reset mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 11 USBSUSPM: USB suspend mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1288/1757\nRM0090 Rev 21\nBit 10 ESUSPM: Early suspend mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBits 9:8 Reserved, must be kept at reset value.\nBit 7 GONAKEFFM: Global OUT NAK effective mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 6 GINAKEFFM: Global non-periodic IN NAK effective mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 5 NPTXFEM: Non-periodic TxFIFO empty mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in Host mode.\nBit 4 RXFLVLM: Receive FIFO non-empty mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both device and host modes.\nBit 3 SOFM: Start of frame mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both device and host modes.\nBit 2 OTGINT: OTG interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both device and host modes.\nBit 1 MMISM: Mode mismatch interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both device and host modes.\nBit 0 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n1289/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS Receive status debug read/OTG status read and pop registers \n(OTG_FS_GRXSTSR/OTG_FS_GRXSTSP)\nAddress offset for Read: 0x01C\nAddress offset for Pop: 0x020\nReset value: 0x0000 0000\nA read to the Receive status debug read register returns the contents of the top of the \nReceive FIFO. A read to the Receive status read and pop register additionally pops the top \ndata entry out of the RxFIFO.\nThe receive status contents must be interpreted differently in host and device modes. The \ncore ignores the receive status pop/read when the receive FIFO is empty and returns a \nvalue of 0x0000 0000. The application must only pop the Receive Status FIFO when the \nReceive FIFO non-empty bit of the Core interrupt register (RXFLVL bit in \nOTG_FS_GINTSTS) is asserted.\nHost mode\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPKTSTS\nDPID\nBCNT\nCHNUM\nr\nr\nr\nr\nBits 31:21 Reserved, must be kept at reset value.\nBits 20:17 PKTSTS: Packet status\nIndicates the status of the received packet\n0010: IN data packet received\n0011: IN transfer completed (triggers an interrupt)\n0101: Data toggle error (triggers an interrupt)\n0111: Channel halted (triggers an interrupt)\nOthers: Reserved\nBits 16:15 DPID: Data PID\nIndicates the Data PID of the received packet\n00: DATA0\n10: DATA1\n01: DATA2\n11: MDATA\nBits 14:4 BCNT: Byte count\nIndicates the byte count of the received IN data packet.\nBits 3:0 CHNUM: Channel number\nIndicates the channel number to which the current received packet belongs.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1290/1757\nRM0090 Rev 21\nDevice mode\n \n \nOTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)\nAddress offset: 0x024\nReset value: 0x0000 0200\nThe application can program the RAM size that must be allocated to the RxFIFO.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFRMNUM\nPKTSTS\nDPID\nBCNT\nEPNUM\nr\nr\nr\nr\nr\nBits 31:25 Reserved, must be kept at reset value.\nBits 24:21 FRMNUM: Frame number\nThis is the least significant 4 bits of the frame number in which the packet is received on the \nUSB. This field is supported only when isochronous OUT endpoints are supported.\nBits 20:17 PKTSTS: Packet status\nIndicates the status of the received packet\n0001: Global OUT NAK (triggers an interrupt)\n0010: OUT data packet received\n0011: OUT transfer completed (triggers an interrupt)\n0100: SETUP transaction completed (triggers an interrupt)\n0110: SETUP data packet received\nOthers: Reserved\nBits 16:15 DPID: Data PID\nIndicates the Data PID of the received OUT data packet\n00: DATA0\n10: DATA1\n01: DATA2\n11: MDATA\nBits 14:4 BCNT: Byte count\nIndicates the byte count of the received data packet.\nBits 3:0 EPNUM: Endpoint number\nIndicates the endpoint number to which the current received packet belongs.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRXFD\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 RXFD: RxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nMaximum value is 256\nThe power-on reset value of this register is specified as the largest Rx data FIFO depth.\n\n\n<>\n\nRM0090 Rev 21\n1291/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS Host non-periodic transmit FIFO size register \n(OTG_FS_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_FS_DIEPTXF0)\nAddress offset: 0x028\nReset value: 0x0000 0200\n \nHost mode\n \nDevice mode\n \nOTG_FS non-periodic transmit FIFO/queue status register \n(OTG_FS_HNPTXSTS)\nAddress offset: 0x02C\nReset value: 0x0008 0200\nNote:\nIn Device mode, this register is not valid.\nThis read-only register contains the free space information for the non-periodic TxFIFO and \nthe non-periodic transmit request queue.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nNPTXFD/TX0FD\nNPTXFSA/TX0FSA\nrw\nrw\nBits 31:16 NPTXFD: Non-periodic TxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nMaximum value is 256\nBits 15:0 NPTXFSA: Non-periodic transmit RAM start address\nThis field contains the memory start address for non-periodic transmit FIFO RAM.\nBits 31:16 TX0FD: Endpoint 0 TxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nMaximum value is 256\nBits 15:0 TX0FSA: Endpoint 0 transmit RAM start address\nThis field contains the memory start address for the endpoint 0 transmit FIFO RAM.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNPTXQTOP\nNPTQXSAV\nNPTXFSAV\nr\nr\nr\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1292/1757\nRM0090 Rev 21\n \nOTG_FS general core configuration register (OTG_FS_GCCFG)\nAddress offset: 0x038\nReset value: 0x0000 XXXX\n \nBit 31 Reserved, must be kept at reset value.\nBits 30:24 NPTXQTOP: Top of the non-periodic transmit request queue\nEntry in the non-periodic Tx request queue that is currently being processed by the MAC.\nBits 30:27: Channel/endpoint number\nBits 26:25:\n–\n00: IN/OUT token\n–\n01: Zero-length transmit packet (device IN/host OUT)\n–\n11: Channel halt command\nBit 24: Terminate (last entry for selected channel/endpoint)\nBits 23:16 NPTQXSAV: Non-periodic transmit request queue space available\nIndicates the amount of free space available in the non-periodic transmit request queue. \nThis queue holds both IN and OUT requests in host mode. Device mode has only IN \nrequests.\n00: Non-periodic transmit request queue is full\n01: 1 location available\n10: 2 locations available\nbxn: n locations available (0 ≤ n ≤ 8)\nOthers: Reserved\nBits 15:0 NPTXFSAV: Non-periodic TxFIFO space available\nIndicates the amount of free space available in the non-periodic TxFIFO.\nValues are in terms of 32-bit words.\n00: Non-periodic TxFIFO is full\n01: 1 word available\n10: 2 words available\n0xn: n words available (where 0 ≤ n ≤ 256)\nOthers: Reserved\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNOVBUSSENS\nSOFOUTEN\nVBUSBSEN\nVBUSASEN\nReserved\n.PWRDWN\nReserved\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n1293/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n \nOTG_FS core ID register (OTG_FS_CID)\nAddress offset: 0x03C\nReset value:0x0000 1200\nThis is a register containing the Product ID as reset value.\n \n \nBits 31:22 Reserved, must be kept at reset value.\nBit 21 NOVBUSSENS: VBUS sensing disable option\nWhen this bit is set, VBUS is considered internally to be always at VBUS valid level (5 V). This \noption removes the need for a dedicated VBUS pad, and leave this pad free to be used for \nother purposes such as a shared functionality. VBUS connection can be remapped on \nanother general purpose input pad and monitored by software. \nThis option is only suitable for host-only or device-only applications. \n0: VBUS sensing available by hardware \n1: VBUS sensing not available by hardware. \nBit 20 SOFOUTEN: SOF output enable\n0: SOF pulse not available on PAD (OTG_FS_SOF)\n1: SOF pulse available on PAD (OTG_FS_SOF)\nBit 19 VBUSBSEN: Enable the VBUS sensing “B” device\n0: VBUS sensing “B” disabled\n1: VBUS sensing “B” enabled\nBit 18 VBUSASEN: Enable the VBUS sensing “A” device\n0: VBUS sensing “A” disabled\n1: VBUS sensing “A” enabled\nBit 17 Reserved, must be kept at reset value.\nBit 16 PWRDWN: Power down\nUsed to activate the transceiver in transmission/reception\n0: Power down active\n1: Power down deactivated (“Transceiver active”)\nBits 15:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPRODUCT_ID\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 PRODUCT_ID: Product ID field\nApplication-programmable ID field.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1294/1757\nRM0090 Rev 21\nOTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)\nAddress offset: 0x100\nReset value: 0x0200 0400\n \n \nOTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXFx) \n(x = 1..3, where x is the FIFO_number)\nAddress offset: 0x104 + 0x04 * (x -1)\nReset value: 0x0200 0200\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPTXFSIZ\nPTXSA\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 PTXFD: Host periodic TxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nBits 15:0 PTXSA: Host periodic TxFIFO start address\nThe power-on reset value of this register is the sum of the largest Rx data FIFO depth and \nlargest non-periodic Tx data FIFO depth.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nINEPTXFD\nINEPTXSA\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 INEPTXFD: IN endpoint TxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nThe power-on reset value of this register is specified as the largest IN endpoint FIFO \nnumber depth.\nBits 15:0 INEPTXSA: IN endpoint FIFOx transmit RAM start address\nThis field contains the memory start address for IN endpoint transmit FIFOx. The address \nmust be aligned with a 32-bit memory location. \n\n\n<>\n\nRM0090 Rev 21\n1295/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34.16.3 \nHost-mode registers\nBit values in the register descriptions are expressed in binary unless otherwise specified.\nHost-mode registers affect the operation of the core in the host mode. Host mode registers \nmust not be accessed in device mode, as the results are undefined. Host mode registers \ncan be categorized as follows:\nOTG_FS Host configuration register (OTG_FS_HCFG)\nAddress offset: 0x400\nReset value: 0x0000 0000\nThis register configures the core after power-on. Do not make changes to this register after \ninitializing the host.\n \n \nOTG_FS Host frame interval register (OTG_FS_HFIR)\nAddress offset: 0x404\nReset value: 0x0000 EA60\nThis register stores the frame interval information for the current speed to which the \nOTG_FS controller has enumerated.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFSLSS\nFSLSPCS\nr\nrw\nrw\nBits 31:3 Reserved, must be kept at reset value.\nBit 2 FSLSS: FS- and LS-only support\nThe application uses this bit to control the core’s enumeration speed. Using this bit, the \napplication can make the core enumerate as an FS host, even if the connected device \nsupports HS traffic. Do not make changes to this field after initial programming.\n1: FS/LS-only, even if the connected device can support HS (read-only)\nBits 1:0 FSLSPCS: FS/LS PHY clock select\nWhen the core is in FS host mode\n01: PHY clock is running at 48 MHz\nOthers: Reserved\nWhen the core is in LS host mode\n00: Reserved\n01: Select 48 MHz PHY clock frequency \n10: Select 6 MHz PHY clock frequency \n11: Reserved\nNote: The FSLSPCS must be set on a connection event according to the speed of the \nconnected device (after changing this bit, a software reset must be performed).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFRIVL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1296/1757\nRM0090 Rev 21\n \nOTG_FS Host frame number/frame time remaining register (OTG_FS_HFNUM)\nAddress offset: 0x408\nReset value: 0x0000 3FFF\nThis register indicates the current frame number. It also indicates the time remaining (in \nterms of the number of PHY clocks) in the current frame.\n \n \nOTG_FS_Host periodic transmit FIFO/queue status register \n(OTG_FS_HPTXSTS)\nAddress offset: 0x410\nReset value: 0x0008 0100\nThis read-only register contains the free space information for the periodic TxFIFO and the \nperiodic transmit request queue.\n \nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 FRIVL: Frame interval\nThe value that the application programs to this field specifies the interval between two \nconsecutive SOFs (FS) or Keep-Alive tokens (LS). This field contains the number of PHY \nclocks that constitute the required frame interval. The application can write a value to this \nregister only after the Port enable bit of the host port control and status register (PENA bit in \nOTG_FS_HPRT) has been set. If no value is programmed, the core calculates the value \nbased on the PHY clock specified in the FS/LS PHY Clock Select field of the host \nconfiguration register (FSLSPCS in OTG_FS_HCFG). Do not change the value of this field \nafter the initial configuration.\n– Frame interval = 1 ms × (FRIVL - 1)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFTREM\nFRNUM\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 FTREM: Frame time remaining\nIndicates the amount of time remaining in the current frame, in terms of PHY clocks. This \nfield decrements on each PHY clock. When it reaches zero, this field is reloaded with the \nvalue in the Frame interval register and a new SOF is transmitted on the USB.\nBits 15:0 FRNUM: Frame number\nThis field increments when a new SOF is transmitted on the USB, and is cleared to 0 when \nit reaches 0x3FFF.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPTXQTOP\nPTXQSAV\nPTXFSAVL\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n\n\n<>\n\nRM0090 Rev 21\n1297/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n \nOTG_FS Host all channels interrupt register (OTG_FS_HAINT)\nAddress offset: 0x414\nReset value: 0x0000 000\nWhen a significant event occurs on a channel, the host all channels interrupt register \ninterrupts the application using the host channels interrupt bit of the Core interrupt register \n(HCINT bit in OTG_FS_GINTSTS). This is shown in Figure 394. There is one interrupt bit \nper channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the \napplication sets and clears bits in the corresponding host channel-x interrupt register.\n \n \nBits 31:24 PTXQTOP: Top of the periodic transmit request queue\nThis indicates the entry in the periodic Tx request queue that is currently being processed by \nthe MAC.\nThis register is used for debugging.\nBit 31: Odd/Even frame\n–\n0: send in even frame\n–\n1: send in odd frame\nBits 30:27: Channel/endpoint number\nBits 26:25: Type\n–\n00: IN/OUT\n–\n01: Zero-length packet\n–\n11: Disable channel command\nBit 24: Terminate (last entry for the selected channel/endpoint)\nBits 23:16 PTXQSAV: Periodic transmit request queue space available\nIndicates the number of free locations available to be written in the periodic transmit request \nqueue. This queue holds both IN and OUT requests.\n00: Periodic transmit request queue is full\n01: 1 location available\n10: 2 locations available\nbxn: n locations available (0 ≤ n ≤ 8)\nOthers: Reserved\nBits 15:0 PTXFSAVL: Periodic transmit data FIFO space available\nIndicates the number of free locations available to be written to in the periodic TxFIFO.\nValues are in terms of 32-bit words\n0000: Periodic TxFIFO is full\n0001: 1 word available\n0010: 2 words available\nbxn: n words available (where 0 ≤ n ≤ PTXFD)\nOthers: Reserved\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nHAINT\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 HAINT: Channel interrupts\nOne bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1298/1757\nRM0090 Rev 21\nOTG_FS Host all channels interrupt mask register (OTG_FS_HAINTMSK)\nAddress offset: 0x418\nReset value: 0x0000 0000\nThe host all channel interrupt mask register works with the host all channel interrupt register \nto interrupt the application when an event occurs on a channel. There is one interrupt mask \nbit per channel, up to a maximum of 16 bits.\n \n \nOTG_FS Host port control and status register (OTG_FS_HPRT)\nAddress offset: 0x440\nReset value: 0x0000 0000\nThis register is available only in host mode. Currently, the OTG host supports only one port.\nA single register holds USB port-related information such as USB reset, enable, suspend, \nresume, connect status, and test mode for each port. It is shown in Figure 394. The rc_w1 \nbits in this register can trigger an interrupt to the application through the host port interrupt \nbit of the core interrupt register (HPRTINT bit in OTG_FS_GINTSTS). On a Port Interrupt, \nthe application must read this register and clear the bit that caused the interrupt. For the \nrc_w1 bits, the application must write a 1 to the bit to clear the interrupt.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nHAINTM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 HAINTM: Channel interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nOne bit per channel: Bit 0 for channel 0, bit 15 for channel 15\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPSPD\nPTCTL\nPPWR\nPLSTS\nReserved\nPRST\nPSUSP\nPRES\nPOCCHNG\nPOCA\nPENCHNG\nPENA\nPCDET\nPCSTS\nr\nr\nrw\nrw\nrw\nrw\nrw\nr\nr\nrw\nrs\nrw\nrc_\nw1\nr\nrc_\nw1\nrc_\nw0\nrc_\nw1\nr\nBits 31:19 Reserved, must be kept at reset value.\nBits 18:17 PSPD: Port speed\nIndicates the speed of the device attached to this port.\n01: Full speed\n10: Low speed\n11: Reserved\n\n\n<>\n\nRM0090 Rev 21\n1299/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nBits 16:13 PTCTL: Port test control\nThe application writes a nonzero value to this field to put the port into a Test mode, and the \ncorresponding pattern is signaled on the port.\n0000: Test mode disabled\n0001: Test_J mode\n0010: Test_K mode\n0011: Test_SE0_NAK mode\n0100: Test_Packet mode\n0101: Test_Force_Enable\nOthers: Reserved\nBit 12 PPWR: Port power\nThe application uses this field to control power to this port, and the core clears this bit on an \novercurrent condition.\n0: Power off\n1: Power on\nBits 11:10 PLSTS: Port line status\nIndicates the current logic level USB data lines\nBit 10: Logic level of OTG_FS_DP\nBit 11: Logic level of OTG_FS_DM\nBit 9 Reserved, must be kept at reset value.\nBit 8 PRST: Port reset\nWhen the application sets this bit, a reset sequence is started on this port. The application \nmust time the reset period and clear this bit after the reset sequence is complete.\n0: Port not in reset\n1: Port in reset\nThe application must leave this bit set for a minimum duration of at least 10 ms to start a \nreset on the port. The application can leave it set for another 10 ms in addition to the \nrequired minimum duration, before clearing the bit, even though there is no maximum limit \nset by the USB standard.\nBit 7 PSUSP: Port suspend\nThe application sets this bit to put this port in Suspend mode. The core only stops sending \nSOFs when this is set. To stop the PHY clock, the application must set the Port clock stop \nbit, which asserts the suspend input pin of the PHY.\nThe read value of this bit reflects the current suspend status of the port. This bit is cleared \nby the core after a remote wake-up signal is detected or the application sets the Port reset \nbit or Port resume bit in this register or the Resume/remote wake-up detected interrupt bit or \nDisconnect detected interrupt bit in the Core interrupt register (WKUINT or DISCINT in \nOTG_FS_GINTSTS, respectively).\n0: Port not in Suspend mode\n1: Port in Suspend mode\nBit 6 PRES: Port resume\nThe application sets this bit to drive resume signaling on the port. The core continues to \ndrive the resume signal until the application clears this bit.\nIf the core detects a USB remote wake-up sequence, as indicated by the Port \nresume/remote wake-up detected interrupt bit of the Core interrupt register (WKUINT bit in \nOTG_FS_GINTSTS), the core starts driving resume signaling without application \nintervention and clears this bit when it detects a disconnect condition. The read value of this \nbit indicates whether the core is currently driving resume signaling.\n0: No resume driven\n1: Resume driven\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1300/1757\nRM0090 Rev 21\nBit 5 POCCHNG: Port overcurrent change\nThe core sets this bit when the status of the Port overcurrent active bit (bit 4) in this register \nchanges.\nBit 4 POCA: Port overcurrent active\nIndicates the overcurrent condition of the port.\n0: No overcurrent condition\n1: Overcurrent condition\nBit 3 PENCHNG: Port enable/disable change\nThe core sets this bit when the status of the Port enable bit 2 in this register changes.\nBit 2 PENA: Port enable\nA port is enabled only by the core after a reset sequence, and is disabled by an overcurrent \ncondition, a disconnect condition, or by the application clearing this bit. The application \ncannot set this bit by a register write. It can only clear it to disable the port. This bit does not \ntrigger any interrupt to the application.\n0: Port disabled\n1: Port enabled\nBit 1 PCDET: Port connect detected\nThe core sets this bit when a device connection is detected to trigger an interrupt to the \napplication using the host port interrupt bit in the Core interrupt register (HPRTINT bit in \nOTG_FS_GINTSTS). The application must write a 1 to this bit to clear the interrupt.\nBit 0 PCSTS: Port connect status\n0: No device is attached to the port\n1: A device is attached to the port\n\n\n<>\n\nRM0090 Rev 21\n1301/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx) \n(x = 0..7, where x = Channel_number)\nAddress offset: 0x500 + 0x20 * x\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nrs\nrs\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 CHENA: Channel enable\nThis field is set by the application and cleared by the OTG host.\n0: Channel disabled\n1: Channel enabled\nBit 30 CHDIS: Channel disable\nThe application sets this bit to stop transmitting/receiving data on a channel, even before \nthe transfer for that channel is complete. The application must wait for the Channel disabled \ninterrupt before treating the channel as disabled.\nBit 29 ODDFRM: Odd frame\nThis field is set (reset) by the application to indicate that the OTG host must perform a \ntransfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) \ntransactions.\n0: Even frame\n1: Odd frame\nBits 28:22 DAD: Device address\nThis field selects the specific device serving as the data source or sink.\nBits 21:20 MCNT: Multicount\nThis field indicates to the host the number of transactions that must be executed per frame \nfor this periodic endpoint. For non-periodic transfers, this field is not used\n00: Reserved. This field yields undefined results\n01: 1 transaction\n10: 2 transactions per frame to be issued for this endpoint\n11: 3 transactions per frame to be issued for this endpoint\nNote: This field must be set to at least 01.\nBits 19:18 EPTYP: Endpoint type\nIndicates the transfer type selected.\n00: Control\n01: Isochronous\n10: Bulk\n11: Interrupt\nBit 17 LSDEV: Low-speed device\nThis field is set by the application to indicate that this channel is communicating to a low-\nspeed device.\nBit 16 Reserved, must be kept at reset value.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1302/1757\nRM0090 Rev 21\nOTG_FS Host channel-x interrupt register (OTG_FS_HCINTx) (x = 0..7, where \nx = Channel_number)\nAddress offset: 0x508 + 0x20 * x\nReset value: 0x0000 0000\nThis register indicates the status of a channel with respect to USB- and AHB-related events. \nIt is shown in Figure 394. The application must read this register when the host channels \ninterrupt bit in the Core interrupt register (HCINT bit in OTG_FS_GINTSTS) is set. Before \nthe application can read this register, it must first read the host all channels interrupt \n(OTG_FS_HAINT) register to get the exact channel number for the host channel-x interrupt \nregister. The application must clear the appropriate bit in this register to clear the \ncorresponding bits in the OTG_FS_HAINT and OTG_FS_GINTSTS registers.\n \n \nBit 15 EPDIR: Endpoint direction\nIndicates whether the transaction is IN or OUT.\n0: OUT\n1: IN\nBits 14:11 EPNUM: Endpoint number\nIndicates the endpoint number on the device serving as the data source or sink.\nBits 10:0 MPSIZ: Maximum packet size\nIndicates the maximum packet size of the associated endpoint.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nBits 31:11 Reserved, must be kept at reset value.\nBit 10 DTERR: Data toggle error\nBit 9 FRMOR: Frame overrun\nBit 8 BBERR: Babble error\nBit 7 TXERR: Transaction error\nIndicates one of the following errors occurred on the USB.\nCRC check failure\nTimeout\nBit stuff error\nFalse EOP\nBit 6 Reserved, must be kept at reset value.\nBit 5 ACK: ACK response received/transmitted interrupt\nBit 4 NAK: NAK response received interrupt\nBit 3 STALL: STALL response received interrupt\n\n\n<>\n\nRM0090 Rev 21\n1303/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS Host channel-x interrupt mask register (OTG_FS_HCINTMSKx) \n(x = 0..7, where x = Channel_number)\nAddress offset: 0x50C + 0x20 * x\nReset value: 0x0000 0000\nThis register reflects the mask for each channel status described in the previous section.\n \n \nBit 2 Reserved, must be kept at reset value.\nBit 1 CHH: Channel halted\nIndicates the transfer completed abnormally either because of any USB transaction error or \nin response to disable request by the application.\nBit 0 XFRC: Transfer completed\nTransfer completed normally without any errors.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:11 Reserved, must be kept at reset value.\nBit 10 DTERRM: Data toggle error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 9 FRMORM: Frame overrun mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 8 BBERRM: Babble error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 7 TXERRM: Transaction error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 6 Reserved, must be kept at reset value.\nBit 5 ACKM: ACK response received/transmitted interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 4 NAKM: NAK response received interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 3 STALLM: STALL response received interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1304/1757\nRM0090 Rev 21\nOTG_FS Host channel-x transfer size register (OTG_FS_HCTSIZx) (x = 0..7, \nwhere x = Channel_number)\nAddress offset: 0x510 + 0x20 * x\nReset value: 0x0000 0000\n \n \nBit 2 Reserved, must be kept at reset value.\nBit 1 CHHM: Channel halted mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 0 XFRCM: Transfer completed mask\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDPID\nPKTCNT\nXFRSIZ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBits 30:29 DPID: Data PID\nThe application programs this field with the type of PID to use for the initial transaction. The \nhost maintains this field for the rest of the transfer.\n00: DATA0\n01: DATA2\n10: DATA1\n11: MDATA (non-control)/SETUP (control)\nBits 28:19 PKTCNT: Packet count\nThis field is programmed by the application with the expected number of packets to be \ntransmitted (OUT) or received (IN).\nThe host decrements this count on every successful transmission or reception of an OUT/IN \npacket. Once this count reaches zero, the application is interrupted to indicate normal \ncompletion.\nBits 18:0 XFRSIZ: Transfer size\nFor an OUT, this field is the number of data bytes the host sends during the transfer.\nFor an IN, this field is the buffer size that the application has reserved for the transfer. The \napplication is expected to program this field as an integer multiple of the maximum packet \nsize for IN transactions (periodic and non-periodic).\n\n\n<>\n\nRM0090 Rev 21\n1305/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34.16.4 \nDevice-mode registers\nOTG_FS device configuration register (OTG_FS_DCFG)\nAddress offset: 0x800\nReset value: 0x0220 0000\nThis register configures the core in device mode after power-on or after certain control \ncommands or enumeration. Do not make changes to this register after initial programming.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPFIVL\nDAD\nReserved\nNZLSOHSK\nDSPD\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:13 Reserved, must be kept at reset value.\nBits 12:11 PFIVL: Periodic frame interval\nIndicates the time within a frame at which the application must be notified using the end of \nperiodic frame interrupt. This can be used to determine if all the isochronous traffic for that \nframe is complete.\n00: 80% of the frame interval\n01: 85% of the frame interval\n10: 90% of the frame interval\n11: 95% of the frame interval\nBits 10:4 DAD: Device address\nThe application must program this field after every SetAddress control command.\nBit 3 Reserved, must be kept at reset value.\nBit 2 NZLSOHSK: Non-zero-length status OUT handshake\nThe application can use this field to select the handshake the core sends on receiving a \nnonzero-length data packet during the OUT transaction of a control transfer’s Status stage.\n1: Send a STALL handshake on a nonzero-length status OUT transaction and do not send \nthe received OUT packet to the application.\n0: Send the received OUT packet to the application (zero-length or nonzero-length) and \nsend a handshake based on the NAK and STALL bits for the endpoint in the Device \nendpoint control register.\nBits 1:0 DSPD: Device speed\nIndicates the speed at which the application requires the core to enumerate, or the \nmaximum speed the application can support. However, the actual bus speed is determined \nonly after the chirp sequence is completed, and is based on the speed of the USB host to \nwhich the core is connected.\n00: Reserved\n01: Reserved\n10: Reserved\n11: Full speed (USB 1.1 transceiver clock is 48 MHz)\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1306/1757\nRM0090 Rev 21\nOTG_FS device control register (OTG_FS_DCTL)\nAddress offset: 0x804\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPOPRGDNE\nCGONAK\nSGONAK\nCGINAK\nSGINAK\nTCTL\nGONSTS\nGINSTS\nSDIS\nRWUSIG\nrw\nw\nw\nw\nw\nrw\nrw\nrw\nr\nr\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBit 11 POPRGDNE: Power-on programming done\nThe application uses this bit to indicate that register programming is completed after a \nwake-up from power down mode.\nBit 10 CGONAK: Clear global OUT NAK\nWriting 1 to this field clears the Global OUT NAK.\nBit 9 SGONAK: Set global OUT NAK\nWriting 1 to this field sets the Global OUT NAK.\nThe application uses this bit to send a NAK handshake on all OUT endpoints.\nThe application must set the this bit only after making sure that the Global OUT NAK \neffective bit in the Core interrupt register (GONAKEFF bit in OTG_FS_GINTSTS) is cleared.\nBit 8 CGINAK: Clear global IN NAK\nWriting 1 to this field clears the Global IN NAK.\nBit 7 SGINAK: Set global IN NAK\nWriting 1 to this field sets the Global non-periodic IN NAK. The application uses this bit to \nsend a NAK handshake on all non-periodic IN endpoints.\nThe application must set this bit only after making sure that the Global IN NAK effective bit \nin the Core interrupt register (GINAKEFF bit in OTG_FS_GINTSTS) is cleared.\nBits 6:4 TCTL: Test control\n000: Test mode disabled\n001: Test_J mode\n010: Test_K mode\n011: Test_SE0_NAK mode\n100: Test_Packet mode\n101: Test_Force_Enable\nOthers: Reserved\nBit 3 GONSTS: Global OUT NAK status\n0: A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.\n1: No data is written to the RxFIFO, irrespective of space availability. Sends a NAK \nhandshake on all packets, except on SETUP transactions. All isochronous OUT packets are \ndropped.\n\n\n<>\n\nRM0090 Rev 21\n1307/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nTable 205 contains the minimum duration (according to device state) for which the Soft \ndisconnect (SDIS) bit must be set for the USB host to detect a device disconnect. To \naccommodate clock jitter, it is recommended that the application add some extra delay to \nthe specified minimum duration.\n \nOTG_FS device status register (OTG_FS_DSTS)\nAddress offset: 0x808\nReset value: 0x0000 0010\nThis register indicates the status of the core with respect to USB-related events. It must be \nread on interrupts from the device all interrupts (OTG_FS_DAINT) register.\n \n \nBit 2 GINSTS: Global IN NAK status\n0: A handshake is sent out based on the data availability in the transmit FIFO.\n1: A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data \navailability in the transmit FIFO.\nBit 1 SDIS: Soft disconnect\nThe application uses this bit to signal the USB OTG core to perform a soft disconnect. As \nlong as this bit is set, the host does not see that the device is connected, and the device \ndoes not receive signals on the USB. The core stays in the disconnected state until the \napplication clears this bit.\n0: Normal operation. When this bit is cleared after a soft disconnect, the core generates a \ndevice connect event to the USB host. When the device is reconnected, the USB host \nrestarts device enumeration.\n1: The core generates a device disconnect event to the USB host.\nBit 0 RWUSIG: Remote wake-up signaling\nWhen the application sets this bit, the core initiates remote signaling to wake up the USB \nhost. The application must set this bit to instruct the core to exit the Suspend state. As \nspecified in the USB 2.0 specification, the application must clear this bit 1 ms to 15 ms after \nsetting it.\nTable 205. Minimum duration for soft disconnect\nOperating speed\nDevice state\nMinimum duration\nFull speed\nSuspended\n1 ms + 2.5 µs\nFull speed\nIdle\n2.5 µs\nFull speed\nNot Idle or Suspended (Performing transactions)\n2.5 µs\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFNSOF\nReserved\nEERR\nENUMSPD\nSUSPSTS\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:22 Reserved, must be kept at reset value.\nBits 21:8 FNSOF: Frame number of the received SOF\nBits 7:4 Reserved, must be kept at reset value.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1308/1757\nRM0090 Rev 21\nOTG_FS device IN endpoint common interrupt mask register \n(OTG_FS_DIEPMSK)\nAddress offset: 0x810\nReset value: 0x0000 0000\nThis register works with each of the OTG_FS_DIEPINTx registers for all endpoints to \ngenerate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the \nOTG_FS_DIEPINTx register can be masked by writing to the corresponding bit in this \nregister. Status bits are masked by default.\n \n \nBit 3 EERR: Erratic error\nThe core sets this bit to report any erratic errors.\nDue to erratic errors, the OTG_FS controller goes into Suspended state and an interrupt is \ngenerated to the application with Early suspend bit of the OTG_FS_GINTSTS register \n(ESUSP bit in OTG_FS_GINTSTS). If the early suspend is asserted due to an erratic error, \nthe application can only perform a soft disconnect recover.\nBits 2:1 ENUMSPD: Enumerated speed\nIndicates the speed at which the OTG_FS controller has come up after speed detection \nthrough a chirp sequence.\n01: Reserved\n10: Reserved\n11: Full speed (PHY clock is running at 48 MHz)\nOthers: reserved\nBit 0 SUSPSTS: Suspend status\nIn device mode, this bit is set as long as a Suspend condition is detected on the USB. The \ncore enters the Suspended state when there is no activity on the USB data lines for a period \nof 3 ms. The core comes out of the suspend:\n– When there is an activity on the USB data lines\n– When the application writes to the Remote wake-up signaling bit in the OTG_FS_DCTL \nregister (RWUSIG bit in OTG_FS_DCTL).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNAKM\nReserved\nINEPNEM\nINEPNMM\nITTXFEMSK\nTOM\nReserved\nEPDM\nXFRCM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:14 Reserved, must be kept at reset value.\nBit 13 NAKM: NAK interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBits 12:7 Reserved, must be kept at reset value.\nBit 6 INEPNEM: IN endpoint NAK effective mask\n0: Masked interrupt\n1: Unmasked interrupt\n\n\n<>\n\nRM0090 Rev 21\n1309/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS device OUT endpoint common interrupt mask register \n(OTG_FS_DOEPMSK)\nAddress offset: 0x814\nReset value: 0x0000 0000\nThis register works with each of the OTG_FS_DOEPINTx registers for all endpoints to \ngenerate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in \nthe OTG_FS_DOEPINTx register can be masked by writing into the corresponding bit in this \nregister. Status bits are masked by default.\n \nBit 5 INEPNMM: IN token received with EP mismatch mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 4 ITTXFEMSK: IN token received when TxFIFO empty mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 3 TOM: Timeout condition mask (Non-isochronous endpoints)\n0: Masked interrupt\n1: Unmasked interrupt\nBit 2 Reserved, must be kept at reset value.\nBit 1 EPDM: Endpoint disabled interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 0 XFRCM: Transfer completed interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNAK\nBERRM\nReserved\nOUTPKTERRM\nReserved\nSTSPHSRXM\n OTEPDM\nSTUPM\nReserved\nEPDM\nXFRCM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:14 Reserved, must be kept at reset value.\nBit 13 NAKMSK: NAK interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 12 BERRM: Babble error interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBits 11:9 Reserved, must be kept at reset value.\nBit 8 OUTPKTERRM: Out packet error mask\n0: Masked interrupt\n1: Unmasked interrupt\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1310/1757\nRM0090 Rev 21\nOTG_FS device all endpoints interrupt register (OTG_FS_DAINT)\nAddress offset: 0x818\nReset value: 0x0000 0000\nWhen a significant event occurs on an endpoint, a OTG_FS_DAINT register interrupts the \napplication using the Device OUT endpoints interrupt bit or Device IN endpoints interrupt bit \nof the OTG_FS_GINTSTS register (OEPINT or IEPINT in OTG_FS_GINTSTS, \nrespectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT \nendpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN \nand OUT interrupt bits are used. Bits in this register are set and cleared when the \napplication sets and clears bits in the corresponding Device Endpoint-x interrupt register \n(OTG_FS_DIEPINTx/OTG_FS_DOEPINTx).\n \n \nBits 7:6 Reserved, must be kept at reset value.\nBit 5 STSPHSRXM: Status phase received for control write mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 4 OTEPDM: OUT token received when endpoint disabled mask\nApplies to control OUT endpoints only.\n0: Masked interrupt\n1: Unmasked interrupt\nBit 3 STUPM: SETUP phase done mask\nApplies to control endpoints only.\n0: Masked interrupt\n1: Unmasked interrupt\nBit 2 Reserved, must be kept at reset value.\nBit 1 EPDM: Endpoint disabled interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 0 XFRCM: Transfer completed interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOEPINT\nIEPINT\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 OEPINT: OUT endpoint interrupt bits\nOne bit per OUT endpoint: \nBit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3.\nBits 15:0 IEPINT: IN endpoint interrupt bits\nOne bit per IN endpoint: \nBit 0 for IN endpoint 0, bit 3 for endpoint 3.\n\n\n<>\n\nRM0090 Rev 21\n1311/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)\nAddress offset: 0x81C\nReset value: 0x0000 0000\nThe OTG_FS_DAINTMSK register works with the Device endpoint interrupt register to \ninterrupt the application when an event occurs on a device endpoint. However, the \nOTG_FS_DAINT register bit corresponding to that interrupt is still set.\n \n \nOTG_FS device VBUS discharge time register (OTG_FS_DVBUSDIS)\nAddress offset: 0x0828\nReset value: 0x0000 17D7\nThis register specifies the VBUS discharge time after VBUS pulsing during SRP.\n \n \nOTG_FS device VBUS pulsing time register (OTG_FS_DVBUSPULSE)\nAddress offset: 0x082C\nReset value: 0x0000 05B8\nThis register specifies the VBUS pulsing time during SRP.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOEPM\nIEPM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 OEPM: OUT EP interrupt mask bits\nOne per OUT endpoint:\nBit 16 for OUT EP 0, bit 19 for OUT EP 3\n0: Masked interrupt\n1: Unmasked interrupt\nBits 15:0 IEPM: IN EP interrupt mask bits\nOne bit per IN endpoint:\nBit 0 for IN EP 0, bit 3 for IN EP 3\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nVBUSDT\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 VBUSDT: Device VBUS discharge time\nSpecifies the VBUS discharge time after VBUS pulsing during SRP. This value equals:\nVBUS discharge time in PHY clocks / 1 024\nDepending on your VBUS load, this value may need adjusting.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1312/1757\nRM0090 Rev 21\n \n \nOTG_FS device IN endpoint FIFO empty interrupt mask register: \n(OTG_FS_DIEPEMPMSK)\nAddress offset: 0x834\nReset value: 0x0000 0000\nThis register is used to control the IN endpoint FIFO empty interrupt generation \n(TXFE_OTG_FS_DIEPINTx).\n \n \nOTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)\nAddress offset: 0x900\nReset value: 0x0000 0000\nThis section describes the OTG_FS_DIEPCTL0 register. Nonzero control endpoints use \nregisters for endpoints 1–3.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDVBUSP\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 DVBUSP: Device VBUS pulsing time\nSpecifies the VBUS pulsing time during SRP. This value equals:\nVBUS pulsing time in PHY clocks / 1 024\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nINEPTXFEM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 INEPTXFEM: IN EP Tx FIFO empty interrupt mask bits\nThese bits act as mask bits for OTG_FS_DIEPINTx.\nTXFE interrupt one bit per IN endpoint:\nBit 0 for IN endpoint 0, bit 3 for IN endpoint 3\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEPENA\nEPDIS\nReserved\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nReserved\nUSBAEP\nReserved\nMPSIZ\nr\nr\nw\nw\nrw\nrw\nrw\nrw\nrs\nr\nr\nr\nr\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n1313/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n \nBit 31 EPENA: Endpoint enable\nThe application sets this bit to start transmitting data on the endpoint 0.\nThe core clears this bit before setting any of the following interrupts on this endpoint:\n– Endpoint disabled\n– Transfer completed\nBit 30 EPDIS: Endpoint disable\nThe application sets this bit to stop transmitting data on an endpoint, even before the \ntransfer for that endpoint is complete. The application must wait for the Endpoint disabled \ninterrupt before treating the endpoint as disabled. The core clears this bit before setting the \nEndpoint disabled interrupt. The application must set this bit only if Endpoint enable is \nalready set for this endpoint.\nBits 29:28 Reserved, must be kept at reset value.\nBit 27 SNAK: Set NAK\nA write to this bit sets the NAK bit for the endpoint.\nUsing this bit, the application can control the transmission of NAK handshakes on an \nendpoint. The core can also set this bit for an endpoint after a SETUP packet is received on \nthat endpoint.\nBit 26 CNAK: Clear NAK\nA write to this bit clears the NAK bit for the endpoint.\nBits 25:22 TXFNUM: TxFIFO number\nThis value is set to the FIFO number that is assigned to IN endpoint 0.\nBit 21 STALL: STALL handshake\nThe application can only set this bit, and the core clears it when a SETUP token is received \nfor this endpoint. If a NAK bit, a Global IN NAK or Global OUT NAK is set along with this bit, \nthe STALL bit takes priority.\nBit 20 Reserved, must be kept at reset value.\nBits 19:18 EPTYP: Endpoint type\nHardcoded to ‘00’ for control.\nBit 17 NAKSTS: NAK status\nIndicates the following:\n0: The core is transmitting non-NAK handshakes based on the FIFO status\n1: The core is transmitting NAK handshakes on this endpoint.\nWhen this bit is set, either by the application or core, the core stops transmitting data, even \nif there are data available in the TxFIFO. Irrespective of this bit’s setting, the core always \nresponds to SETUP data packets with an ACK handshake.\nBit 16 Reserved, must be kept at reset value.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1314/1757\nRM0090 Rev 21\nOTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3, where \nx = Endpoint_number)\nAddress offset: 0x900 + 0x20 * x\nReset value: 0x0000 0000\nThe application uses this register to control the behavior of each logical endpoint other than \nendpoint 0.\n \n \nBit 15 USBAEP: USB active endpoint\nThis bit is always set to 1, indicating that control endpoint 0 is always active in all \nconfigurations and interfaces.\nBits 14:2 Reserved, must be kept at reset value.\nBits 1:0 MPSIZ: Maximum packet size\nThe application must program this field with the maximum packet size for the current logical \nendpoint.\n00: 64 bytes\n01: 32 bytes\n10: 16 bytes\n11: 8 bytes\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nrs\nrs\nw\nw\nw\nw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nr\nr\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 EPENA: Endpoint enable\nThe application sets this bit to start transmitting data on an endpoint.\nThe core clears this bit before setting any of the following interrupts on this endpoint:\n–\nSETUP phase done\n–\nEndpoint disabled\n–\nTransfer completed\nBit 30 EPDIS: Endpoint disable\nThe application sets this bit to stop transmitting/receiving data on an endpoint, even before \nthe transfer for that endpoint is complete. The application must wait for the Endpoint \ndisabled interrupt before treating the endpoint as disabled. The core clears this bit before \nsetting the Endpoint disabled interrupt. The application must set this bit only if Endpoint \nenable is already set for this endpoint.\nBit 29 SODDFRM: Set odd frame\nApplies to isochronous IN and OUT endpoints only.\nWriting to this field sets the Even/Odd frame (EONUM) field to odd frame.\n\n\n<>\n\nRM0090 Rev 21\n1315/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nBit 28 SD0PID: Set DATA0 PID\nApplies to interrupt/bulk IN endpoints only.\nWriting to this field sets the endpoint data PID (DPID) field in this register to DATA0.\nSEVNFRM: Set even frame\nApplies to isochronous IN endpoints only.\nWriting to this field sets the Even/Odd frame (EONUM) field to even frame.\nBit 27 SNAK: Set NAK\nA write to this bit sets the NAK bit for the endpoint.\nUsing this bit, the application can control the transmission of NAK handshakes on an \nendpoint. The core can also set this bit for OUT endpoints on a Transfer completed interrupt, \nor after a SETUP is received on the endpoint.\nBit 26 CNAK: Clear NAK\nA write to this bit clears the NAK bit for the endpoint.\nBits 25:22 TXFNUM: TxFIFO number\nThese bits specify the FIFO number associated with this endpoint. Each active IN endpoint \nmust be programmed to a separate FIFO number.\nThis field is valid only for IN endpoints.\nBit 21 STALL: STALL handshake\nApplies to non-control, non-isochronous IN endpoints only (access type is rw).\nThe application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK \nbit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. \nOnly the application can clear this bit, never the core.\nBit 20 Reserved, must be kept at reset value.\nBits 19:18 EPTYP: Endpoint type\nThis is the transfer type supported by this logical endpoint.\n00: Control\n01: Isochronous\n10: Bulk\n11: Interrupt\nBit 17 NAKSTS: NAK status\nIt indicates the following:\n0: The core is transmitting non-NAK handshakes based on the FIFO status.\n1: The core is transmitting NAK handshakes on this endpoint.\nWhen either the application or the core sets this bit:\nFor non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, \neven if there are data available in the TxFIFO.\nFor isochronous IN endpoints: The core sends out a zero-length data packet, even if there \nare data available in the TxFIFO.\nIrrespective of this bit’s setting, the core always responds to SETUP data packets with an \nACK handshake.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1316/1757\nRM0090 Rev 21\nBit 16 EONUM: Even/odd frame\nApplies to isochronous IN endpoints only.\nIndicates the frame number in which the core transmits/receives isochronous data for this \nendpoint. The application must program the even/odd frame number in which it intends to \ntransmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM \nfields in this register.\n0: Even frame\n1: Odd frame\nDPID: Endpoint data PID\nApplies to interrupt/bulk IN endpoints only.\nContains the PID of the packet to be received or transmitted on this endpoint. The \napplication must program the PID of the first packet to be received or transmitted on this \nendpoint, after the endpoint is activated. The application uses the SD0PID register field to \nprogram either DATA0 or DATA1 PID.\n0: DATA0\n1: DATA1\nBit 15 USBAEP: USB active endpoint\nIndicates whether this endpoint is active in the current configuration and interface. The core \nclears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving \nthe SetConfiguration and SetInterface commands, the application must program endpoint \nregisters accordingly and set this bit.\nBits 14:11 Reserved, must be kept at reset value.\nBits 10:0 MPSIZ: Maximum packet size\nThe application must program this field with the maximum packet size for the current logical \nendpoint. This value is in bytes.\n\n\n<>\n\nRM0090 Rev 21\n1317/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS device control OUT endpoint 0 control register \n(OTG_FS_DOEPCTL0)\nAddress offset: 0xB00\nReset value: 0x0000 8000\nThis section describes the OTG_FS_DOEPCTL0 register. Nonzero control endpoints use \nregisters for endpoints 1–3.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEPENA\nEPDIS\nReserved\nSNAK\nCNAK\nReserved\nSTALL\nSNPM\nEPTYP\nNAKSTS\nReserved\nUSBAEP\nReserved\nMPSIZ\nw\nr\nw\nw\nrs\nrw\nr\nr\nr\nr\nr\nr\nBit 31 EPENA: Endpoint enable\nThe application sets this bit to start transmitting data on endpoint 0.\nThe core clears this bit before setting any of the following interrupts on this endpoint:\n–\nSETUP phase done\n–\nEndpoint disabled\n–\nTransfer completed\nBit 30 EPDIS: Endpoint disable\nThe application cannot disable control OUT endpoint 0.\nBits 29:28 Reserved, must be kept at reset value.\nBit 27 SNAK: Set NAK\nA write to this bit sets the NAK bit for the endpoint.\nUsing this bit, the application can control the transmission of NAK handshakes on an \nendpoint. The core can also set this bit on a Transfer completed interrupt, or after a SETUP \nis received on the endpoint.\nBit 26 CNAK: Clear NAK\nA write to this bit clears the NAK bit for the endpoint.\nBits 25:22 Reserved, must be kept at reset value.\nBit 21 STALL: STALL handshake\nThe application can only set this bit, and the core clears it, when a SETUP token is received \nfor this endpoint. If a NAK bit or Global OUT NAK is set along with this bit, the STALL bit \ntakes priority. Irrespective of this bit’s setting, the core always responds to SETUP data \npackets with an ACK handshake.\nBit 20 SNPM: Snoop mode\nThis bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check \nthe correctness of OUT packets before transferring them to application memory.\nBits 19:18 EPTYP: Endpoint type\nHardcoded to 2’b00 for control.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1318/1757\nRM0090 Rev 21\nOTG_FS device endpoint-x control register (OTG_FS_DOEPCTLx) (x = 1..3, \nwhere x = Endpoint_number)\nAddress offset for OUT endpoints: 0xB00 + 0x20 * x\nReset value: 0x0000 0000\nThe application uses this register to control the behavior of each logical endpoint other than \nendpoint 0.\n \n \nBit 17 NAKSTS: NAK status\nIndicates the following:\n0: The core is transmitting non-NAK handshakes based on the FIFO status.\n1: The core is transmitting NAK handshakes on this endpoint.\nWhen either the application or the core sets this bit, the core stops receiving data, even if \nthere is space in the RxFIFO to accommodate the incoming packet. Irrespective of this bit’s \nsetting, the core always responds to SETUP data packets with an ACK handshake.\nBit 16 Reserved, must be kept at reset value.\nBit 15 USBAEP: USB active endpoint\nThis bit is always set to 1, indicating that a control endpoint 0 is always active in all \nconfigurations and interfaces.\nBits 14:2 Reserved, must be kept at reset value.\nBits 1:0 MPSIZ: Maximum packet size\nThe maximum packet size for control OUT endpoint 0 is the same as what is programmed in \ncontrol IN endpoint 0.\n00: 64 bytes\n01: 32 bytes\n10: 16 bytes\n11: 8 bytes\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEPENA\nEPDIS\nSODDFRM/SD1PID\nSD0PID/SEVNFRM\nSNAK\nCNAK\nReserved\nSTALL\nSNPM\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nrs\nrs\nw\nw\nw\nw\nrw\nrw\nrw\nrw\nr\nr\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 EPENA: Endpoint enable\nApplies to IN and OUT endpoints.\nThe application sets this bit to start transmitting data on an endpoint.\nThe core clears this bit before setting any of the following interrupts on this endpoint:\n–\nSETUP phase done\n–\nEndpoint disabled\n–\nTransfer completed\n\n\n<>\n\nRM0090 Rev 21\n1319/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nBit 30 EPDIS: Endpoint disable\nThe application sets this bit to stop transmitting/receiving data on an endpoint, even before \nthe transfer for that endpoint is complete. The application must wait for the Endpoint \ndisabled interrupt before treating the endpoint as disabled. The core clears this bit before \nsetting the Endpoint disabled interrupt. The application must set this bit only if Endpoint \nenable is already set for this endpoint.\nBit 29 SD1PID: Set DATA1 PID\nApplies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the endpoint \ndata PID (DPID) field in this register to DATA1.\nSODDFRM: Set odd frame\nApplies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd \nframe (EONUM) field to odd frame.\nBit 28 SD0PID: Set DATA0 PID\nApplies to interrupt/bulk OUT endpoints only.\nWriting to this field sets the endpoint data PID (DPID) field in this register to DATA0.\nSEVNFRM: Set even frame\nApplies to isochronous OUT endpoints only.\nWriting to this field sets the Even/Odd frame (EONUM) field to even frame.\nBit 27 SNAK: Set NAK\nA write to this bit sets the NAK bit for the endpoint.\nUsing this bit, the application can control the transmission of NAK handshakes on an \nendpoint. The core can also set this bit for OUT endpoints on a Transfer Completed \ninterrupt, or after a SETUP is received on the endpoint.\nBit 26 CNAK: Clear NAK\nA write to this bit clears the NAK bit for the endpoint.\nBits 25:22 Reserved, must be kept at reset value.\nBit 21 STALL: STALL handshake\nApplies to non-control, non-isochronous OUT endpoints only (access type is rw).\nThe application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK \nbit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes \npriority. Only the application can clear this bit, never the core.\nBit 20 SNPM: Snoop mode\nThis bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check \nthe correctness of OUT packets before transferring them to application memory.\nBits 19:18 EPTYP: Endpoint type\nThis is the transfer type supported by this logical endpoint.\n00: Control\n01: Isochronous\n10: Bulk\n11: Interrupt\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1320/1757\nRM0090 Rev 21\nBit 17 NAKSTS: NAK status\nIndicates the following:\n0: The core is transmitting non-NAK handshakes based on the FIFO status.\n1: The core is transmitting NAK handshakes on this endpoint.\nWhen either the application or the core sets this bit:\nThe core stops receiving any data on an OUT endpoint, even if there is space in the \nRxFIFO to accommodate the incoming packet.\nIrrespective of this bit’s setting, the core always responds to SETUP data packets with an \nACK handshake.\nBit 16 EONUM: Even/odd frame\nApplies to isochronous IN and OUT endpoints only.\nIndicates the frame number in which the core transmits/receives isochronous data for this \nendpoint. The application must program the even/odd frame number in which it intends to \ntransmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM \nfields in this register.\n0: Even frame\n1: Odd frame\nDPID: Endpoint data PID\nApplies to interrupt/bulk OUT endpoints only.\nContains the PID of the packet to be received or transmitted on this endpoint. The \napplication must program the PID of the first packet to be received or transmitted on this \nendpoint, after the endpoint is activated. The application uses the SD0PID register field to \nprogram either DATA0 or DATA1 PID.\n0: DATA0\n1: DATA1\nBit 15 USBAEP: USB active endpoint\nIndicates whether this endpoint is active in the current configuration and interface. The core \nclears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving \nthe SetConfiguration and SetInterface commands, the application must program endpoint \nregisters accordingly and set this bit.\nBits 14:11 Reserved, must be kept at reset value.\nBits 10:0 MPSIZ: Maximum packet size\nThe application must program this field with the maximum packet size for the current logical \nendpoint. This value is in bytes.\n\n\n<>\n\nRM0090 Rev 21\n1321/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) (x = 0..3, \nwhere x = Endpoint_number)\nAddress offset: 0x908 + 0x20 * x\nReset value: 0x0000 0080\nThis register indicates the status of an endpoint with respect to USB- and AHB-related \nevents. It is shown in Figure 394. The application must read this register when the IN \nendpoints interrupt bit of the Core interrupt register (IEPINT in OTG_FS_GINTSTS) is set. \nBefore the application can read this register, it must first read the device all endpoints \ninterrupt (OTG_FS_DAINT) register to get the exact endpoint number for the Device \nendpoint-x interrupt register. The application must clear the appropriate bit in this register to \nclear the corresponding bits in the OTG_FS_DAINT and OTG_FS_GINTSTS registers.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nReserved\nEPDISD\nXFRC\nrc_\nw1\nrc_\nw1\nr\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nBits 31:14 Reserved, must be kept at reset value.\nBit 13 NAK: NAK input\nThe core generates this interrupt when a NAK is transmitted or received by the device. In \ncase of isochronous IN endpoints the interrupt gets generated when a zero length packet is \ntransmitted due to unavailability of data in the Tx FIFO.\nBit 12 Reserved, must be kept at reset value.\nBit 11 PKTDRPSTS: Packet dropped status\nThis bit indicates to the application that an ISOC OUT packet has been dropped. This bit \ndoes not have an associated mask bit and does not generate an interrupt.\nBits 10:8 Reserved, must be kept at reset value.\nBit 7 TXFE: Transmit FIFO empty\nThis interrupt is asserted when the TxFIFO for this endpoint is either half or completely \nempty. The half or completely empty status is determined by the TxFIFO Empty Level bit in \nthe OTG_FS_GAHBCFG register (TXFELVL bit in OTG_FS_GAHBCFG).\nBit 6 INEPNE: IN endpoint NAK effective\nThis bit can be cleared when the application clears the IN endpoint NAK by writing to the \nCNAK bit in OTG_FS_DIEPCTLx.\nThis interrupt indicates that the core has sampled the NAK bit set (either by the application \nor by the core). The interrupt indicates that the IN endpoint NAK bit set by the application \nhas taken effect in the core.\nThis interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit \ntakes priority over a NAK bit.\nBit 5 INEPNM: IN token received with EP mismatch.\nIndicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other \nthan the one for which the IN token was received. This interrupt is asserted on the endpoint \nfor which the IN token was received.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1322/1757\nRM0090 Rev 21\nOTG_FS device endpoint-x interrupt register (OTG_FS_DOEPINTx) (x = 0..3, \nwhere x = Endpoint_number)\nAddress offset: 0xB08 + 0x20 * x\nReset value: 0x0000 0080\nThis register indicates the status of an endpoint with respect to USB- and AHB-related \nevents. It is shown in Figure 394. The application must read this register when the OUT \nEndpoints Interrupt bit of the OTG_FS_GINTSTS register (OEPINT bit in \nOTG_FS_GINTSTS) is set. Before the application can read this register, it must first read \nthe OTG_FS_DAINT register to get the exact endpoint number for the OTG_FS_DOEPINTx \nregister. The application must clear the appropriate bit in this register to clear the \ncorresponding bits in the OTG_FS_DAINT and OTG_FS_GINTSTS registers.\n \n \nBit 4 ITTXFE: IN token received when TxFIFO is empty\nApplies to non-periodic IN endpoints only.\nIndicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) \nwas empty. This interrupt is asserted on the endpoint for which the IN token was received.\nBit 3 TOC: Timeout condition\nApplies only to Control IN endpoints.\nIndicates that the core has detected a timeout condition on the USB for the last IN token on \nthis endpoint. \nBit 2 Reserved, must be kept at reset value.\nBit 1 EPDISD: Endpoint disabled interrupt\nThis bit indicates that the endpoint is disabled per the application’s request.\nBit 0 XFRC: Transfer completed interrupt\nThis field indicates that the programmed transfer is complete on the AHB as well as on the \nUSB, for this endpoint.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nSTSPHSRX\nOTEPDIS\nSTUP\nReserved\nEPDISD\nXFRC\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nBits 31:14 Reserved, must be kept at reset value.\nBit 13 NAK: NAK input\nThe core generates this interrupt when a NAK is transmitted or received by the device. In \ncase of isochronous IN endpoints the interrupt gets generated when a zero length packet is \ntransmitted due to unavailability of data in the Tx FIFO.\nBit 12 BERR: Babble error interrupt\nThe core generates this interrupt when babble is received for the endpoint.\nBits 11:9 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n1323/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS device IN endpoint 0 transfer size register (OTG_FS_DIEPTSIZ0)\nAddress offset: 0x910\nReset value: 0x0000 0000\nThe application must modify this register before enabling endpoint 0. Once endpoint 0 is \nenabled using the endpoint enable bit in the device control endpoint 0 control registers \n(EPENA in OTG_FS_DIEPCTL0), the core modifies this register. The application can only \nread this register once the core has cleared the Endpoint enable bit.\nNonzero endpoints use the registers for endpoints 1–3.\n \n \nBit 8 OUTPKTERR: OUT packet error\nThis interrupt is asserted when the core detects an overflow or a CRC error for an OUT \npacket. This interrupt is valid only when thresholding is enabled.\nBits 7:6 Reserved, must be kept at reset value.\nBit 5 STSPHSRX: Status phase received for control write\nThis interrupt is generated only after the core has transferred all the data that the host has \nsent during the data phase of a control write transfer, to the system memory buffer. The \ninterrupt indicates to the application that the host has switched from data phase to the status \nphase of a control write transfer. The application can use this interrupt to ACK or STALL the \nstatus phase, after it has decoded the data phase.\nBit 4 OTEPDIS: OUT token received when endpoint disabled\nApplies only to control OUT endpoints.\nIndicates that an OUT token was received when the endpoint was not yet enabled. This \ninterrupt is asserted on the endpoint for which the OUT token was received.\nBit 3 STUP: SETUP phase done\nApplies to control OUT endpoint only.\nIndicates that the SETUP phase for the control endpoint is complete and no more back-to-\nback SETUP packets were received for the current control transfer. On this interrupt, the \napplication can decode the received SETUP data packet.\nBit 2 Reserved, must be kept at reset value.\nBit 1 EPDISD: Endpoint disabled interrupt\nThis bit indicates that the endpoint is disabled per the application’s request.\nBit 0 XFRC: Transfer completed interrupt\nThis field indicates that the programmed transfer is complete on the AHB as well as on the \nUSB, for this endpoint.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPKTCNT\nReserved\nXFRSIZ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1324/1757\nRM0090 Rev 21\nBits 31:21 Reserved, must be kept at reset value.\nBits 20:19 PKTCNT: Packet count\nIndicates the total number of USB packets that constitute the Transfer Size amount of data \nfor endpoint 0.\nThis field is decremented every time a packet (maximum size or short packet) is read from \nthe TxFIFO.\nBits 18:7 Reserved, must be kept at reset value.\nBits 6:0 XFRSIZ: Transfer size\nIndicates the transfer size in bytes for endpoint 0. The core interrupts the application only \nafter it has exhausted the transfer size amount of data. The transfer size can be set to the \nmaximum packet size of the endpoint, to be interrupted at the end of each packet.\nThe core decrements this field every time a packet from the external memory is written to \nthe TxFIFO.\n\n\n<>\n\nRM0090 Rev 21\n1325/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS device OUT endpoint 0 transfer size register (OTG_FS_DOEPTSIZ0)\nAddress offset: 0xB10\nReset value: 0x0000 0000\nThe application must modify this register before enabling endpoint 0. Once endpoint 0 is \nenabled using the Endpoint enable bit in the OTG_FS_DOEPCTL0 registers (EPENA bit in \nOTG_FS_DOEPCTL0), the core modifies this register. The application can only read this \nregister once the core has cleared the Endpoint enable bit.\nNonzero endpoints use the registers for endpoints 1–3.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSTUPCNT\nReserved\nPKTCNT\nReserved\nXFRSIZ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBits 30:29 STUPCNT: SETUP packet count\nThis field specifies the number of back-to-back SETUP data packets the endpoint can \nreceive.\n01: 1 packet\n10: 2 packets\n11: 3 packets\nBits 28:20 Reserved, must be kept at reset value.\nBit 19 PKTCNT: Packet count\nThis field is decremented to zero after a packet is written into the RxFIFO.\nBits 18:7 Reserved, must be kept at reset value.\nBits 6:0 XFRSIZ: Transfer size\nIndicates the transfer size in bytes for endpoint 0. The core interrupts the application only \nafter it has exhausted the transfer size amount of data. The transfer size can be set to the \nmaximum packet size of the endpoint, to be interrupted at the end of each packet.\nThe core decrements this field every time a packet is read from the RxFIFO and written to \nthe external memory.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1326/1757\nRM0090 Rev 21\nOTG_FS device endpoint-x transfer size register (OTG_FS_DIEPTSIZx) \n(x = 1..3, where x = Endpoint_number)\nAddress offset: 0x910 + 0x20 * x\nReset value: 0x0000 0000\nThe application must modify this register before enabling the endpoint. Once the endpoint is \nenabled using the Endpoint enable bit in the OTG_FS_DIEPCTLx registers (EPENA bit in \nOTG_FS_DIEPCTLx), the core modifies this register. The application can only read this \nregister once the core has cleared the Endpoint enable bit.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPKTCNT\nXFRSIZ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:29 Reserved, must be kept at reset value.\nBit 28:19 PKTCNT: Packet count\nIndicates the total number of USB packets that constitute the Transfer Size amount of data \nfor this endpoint. \nThis field is decremented every time a packet (maximum size or short packet) is read from \nthe TxFIFO.\nBits 18:0 XFRSIZ: Transfer size\nThis field contains the transfer size in bytes for the current endpoint. The core only interrupts \nthe application after it has exhausted the transfer size amount of data. The transfer size can \nbe set to the maximum packet size of the endpoint, to be interrupted at the end of each \npacket.\nThe core decrements this field every time a packet from the external memory is written to the \nTxFIFO.\n\n\n<>\n\nRM0090 Rev 21\n1327/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS device IN endpoint transmit FIFO status register \n(OTG_FS_DTXFSTSx) (x = 0..3, where x = Endpoint_number)\nAddress offset for IN endpoints: 0x918 + 0x20 * x\nThis read-only register contains the free space information for the Device IN endpoint \nTxFIFO.\n \n \nOTG_FS device OUT endpoint-x transfer size register (OTG_FS_DOEPTSIZx) \n(x = 1..3, where x = Endpoint_number)\nAddress offset: 0xB10 + 0x20 * x\nReset value: 0x0000 0000\nThe application must modify this register before enabling the endpoint. Once the endpoint is \nenabled using Endpoint Enable bit of the OTG_FS_DOEPCTLx registers (EPENA bit in \nOTG_FS_DOEPCTLx), the core modifies this register. The application can only read this \nregister once the core has cleared the Endpoint enable bit.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nINEPTFSAV\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31:16 Reserved, must be kept at reset value.\n15:0 INEPTFSAV: IN endpoint TxFIFO space available\nIndicates the amount of free space available in the Endpoint TxFIFO.\nValues are in terms of 32-bit words:\n0x0: Endpoint TxFIFO is full\n0x1: 1 word available\n0x2: 2 words available\n0xn: n words available\nOthers: Reserved\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRXDPID/S\nTUPCNT\nPKTCNT\nXFRSIZ\nr/rw\nr/rw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBits 30:29 RXDPID: Received data PID\nApplies to isochronous OUT endpoints only.\nThis is the data PID received in the last packet for this endpoint.\n00: DATA0\n01: DATA2\n10: DATA1\n11: MDATA\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1328/1757\nRM0090 Rev 21\n34.16.5 \nOTG_FS power and clock gating control register\n(OTG_FS_PCGCCTL)\nAddress offset: 0xE00\nReset value: 0x0000 0000\nThis register is available in host and device modes.\n \n \nSTUPCNT: SETUP packet count\nApplies to control OUT Endpoints only.\nThis field specifies the number of back-to-back SETUP data packets the endpoint can \nreceive.\n01: 1 packet\n10: 2 packets\n11: 3 packets\nBit 28:19 PKTCNT: Packet count\nIndicates the total number of USB packets that constitute the Transfer Size amount of data \nfor this endpoint.\nThis field is decremented every time a packet (maximum size or short packet) is written to \nthe RxFIFO.\nBits 18:0 XFRSIZ: Transfer size\nThis field contains the transfer size in bytes for the current endpoint. The core only interrupts \nthe application after it has exhausted the transfer size amount of data. The transfer size can \nbe set to the maximum packet size of the endpoint, to be interrupted at the end of each \npacket.\nThe core decrements this field every time a packet is read from the RxFIFO and written to \nthe external memory.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPHYSUSP\nReserved\nGATEHCLK\nSTPPCLK\nrw\nrw\nrw\nBit 31:5 Reserved, must be kept at reset value.\nBit 4 PHYSUSP: PHY Suspended\nIndicates that the PHY has been suspended. This bit is updated once the PHY is suspended \nafter the application has set the STPPCLK bit (bit 0).\nBits 3:2 Reserved, must be kept at reset value.\nBit 1 GATEHCLK: Gate HCLK\nThe application sets this bit to gate HCLK to modules other than the AHB Slave and Master \nand wake-up logic when the USB is suspended or the session is not valid. The application \nclears this bit when the USB is resumed or a new session starts.\nBit 0 STPPCLK: Stop PHY clock\nThe application sets this bit to stop the PHY clock when the USB is suspended, the session \nis not valid, or the device is disconnected. The application clears this bit when the USB is \nresumed or a new session starts.\n\n\n<>\n\nRM0090 Rev 21\n1329/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34.16.6 \nOTG_FS register map\nThe table below gives the USB OTG register map and reset values.\n \nTable 206. OTG_FS register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x000\nOTG_FS_GOTG\nCTL\nReserved\nBSVLD\nASVLD\nDBCT\nCIDSTS\nReserved\nDHNPEN\nHSHNPEN\nHNPRQ\nHNGSCS\nReserved\nSRQ\nSRQSCS\nReset value\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0x004\nOTG_FS_GOTG\nINT\nReserved\nDBCDNE\nADTOCHG\nHNGDET\nReserved\nHNSSCHG\nSRSSCHG\nReserved\nSEDET\nRes.\nReset value\n0\n0\n0\n0\n0\n0\n0x008\nOTG_FS_GAHB\nCFG\nReserved\nPTXFELVL\nTXFELVL\nReserved\nGINTMSK\nReset value\n0\n0\n0\n0x00C\nOTG_FS_GUSB\nCFG\nCTXPKT\nFDMOD\nFHMOD\nReserved\nTRDT\nHNPCA\nSRPCAP\nReserved\nPHYSEL\nReserved\nTOCAL\nReset value\n0\n0\n0\n0\n0\n1\n0\n1\n0\n0\n0\n0\n0\n0x010\nOTG_FS_GRST\nCTL\nAHBIDL\nReserved\nTXFNUM\nTXFFLSH\nRXFFLSH\nReserved\nFCRST\nHSRST\nCSRST\nReset value\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x014\nOTG_FS_GINTS\nTS\nWKUINT\nSRQINT\nDISCINT\nCIDSCHG\nReserved\nPTXFE\nHCINT\nHPRTINT\nReserved\nIPXFR/INCOMPISOOUT\nIISOIXFR\nOEPINT\nIEPINT\nReserved\nEOPF\nISOODRP\nENUMDNE\nUSBRST\nUSBSUSP\nESUSP\nReserved\nGONAKEFF\nGINAKEFF\nNPTXFE\nRXFLVL\nSOF\nOTGINT\nMMIS\nCMOD\nReset value\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0x018\nOTG_FS_GINT\nMSK\nWUIM\nSRQIM\nDISCINT\nCIDSCHGM\nReserved\nPTXFEM\nHCIM\nPRTIM\nReserved\nIPXFRM/IISOOXFRM\nIISOIXFRM\nOEPINT\nIEPINT\nReserved\nEOPFM\nISOODRPM\nENUMDNEM\nUSBRST\nUSBSUSPM\nESUSPM\nReserved\nGONAKEFFM\nGINAKEFFM\nNPTXFEM\nRXFLVLM\nSOFM\nOTGINT\nMMISM\nReserved\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x01C\nOTG_FS_GRXS\nTSR (host \nmode)\nReserved\nPKTSTS\nDPID\nBCNT\nCHNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nOTG_FS_GRXS\nTSR (Device \nmode)\nReserved\nFRMNUM\nPKTSTS\nDPID\nBCNT\nEPNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1330/1757\nRM0090 Rev 21\n0x020\nOTG_FS_GRXS\nTSR (host \nmode)\nReserved\nPKTSTS\nDPID\nBCNT\nCHNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nOTG_FS_GRXS\nTSPR (Device \nmode)\nReserved\nFRMNUM\nPKTSTS\nDPID\nBCNT\nEPNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x024\nOTG_FS_GRXF\nSIZ\nReserved\nRXFD\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x028\nOTG_FS_HNPT\nXFSIZ/ \nOTG_FS_DIEPT\nXF0\nNPTXFD/TX0FD\nNPTXFSA/TX0FSA\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x02C\nOTG_FS_HNPT\nXSTS\nRes.\nNPTXQTOP\nNPTQXSAV\nNPTXFSAV\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x038\nOTG_FS_\nGCCFG\nReserved\nNOVBUSSENS\nSOFOUTEN\nVBUSBSEN\nVBUSASEN\nReserved\n.PWRDWN\nReserved\nReset value\n0\n0\n0\n0\n0\n0x03C\nOTG_FS_CID\nPRODUCT_ID\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x100\nOTG_FS_HPTX\nFSIZ\nPTXFSIZ\nPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x104\nOTG_FS_DIEPT\nXF1\nINEPTXFD\nINEPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x108\nOTG_FS_DIEPT\nXF2\nINEPTXFD\nINEPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10C\nOTG_FS_DIEPT\nXF3\nINEPTXFD\nINEPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x400\nOTG_FS_HCFG\nReserved\nFSLSS\nFSLSPCS\nReset value\n0\n0\n0\n0x404\nOTG_FS_HFIR\nReserved\nFRIVL\nReset value\n1\n1\n1\n0\n1\n0\n1\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0x408\nOTG_FS_HFNU\nM\nFTREM\nFRNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\nTable 206. OTG_FS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1331/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n0x410\nOTG_FS_HPTX\nSTS\nPTXQTOP\nPTXQSAV\nPTXFSAVL\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\n0x414\nOTG_FS_HAINT\nReserved\nHAINT\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x418\nOTG_FS_HAINT\nMSK\nReserved\nHAINTM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x440\nOTG_FS_HPRT\nReserved\nPSPD\nPTCTL\nPPWR\nPLSTS\nReserved\nPRST\nPSUSP\nPRES\nPOCCHNG\nPOCA\nPENCHNG\nPENA\nPCDET\nPCSTS\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x500\nOTG_FS_HCCH\nAR0\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x520\nOTG_FS_HCCH\nAR1\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x540\nOTG_FS_HCCH\nAR2\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x560\nOTG_FS_HCCH\nAR3\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x580\nOTG_FS_HCCH\nAR4\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5A0\nOTG_FS_HCCH\nAR5\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5C0\nOTG_FS_HCCH\nAR6\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5E0\nOTG_FS_HCCH\nAR7\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x508\nOTG_FS_HCINT\n0\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 206. OTG_FS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1332/1757\nRM0090 Rev 21\n0x528\nOTG_FS_HCINT\n1\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x548\nOTG_FS_HCINT\n2\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x568\nOTG_FS_HCINT\n3\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x588\nOTG_FS_HCINT\n4\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5A8\nOTG_FS_HCINT\n5\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5C8\nOTG_FS_HCINT\n6\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5E8\nOTG_FS_HCINT\n7\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x50C\nOTG_FS_HCINT\nMSK0\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x52C\nOTG_FS_HCINT\nMSK1\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x54C\nOTG_FS_HCINT\nMSK2\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x56C\nOTG_FS_HCINT\nMSK3\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x58C\nOTG_FS_HCINT\nMSK4\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 206. OTG_FS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1333/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n0x5AC\nOTG_FS_HCINT\nMSK5\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5CC\nOTG_FS_HCINT\nMSK6\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5EC\nOTG_FS_HCINT\nMSK7\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x510\nOTG_FS_HCTSI\nZ0\nReserved\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x530\nOTG_FS_HCTSI\nZ1\nReserved\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x550\nOTG_FS_HCTSI\nZ2\nReserved\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x570\nOTG_FS_HCTSI\nZ3\nReserved\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x590\nOTG_FS_HCTSI\nZ4\nReserved\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5B0\nOTG_FS_HCTSI\nZ5\nReserved\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5D0\nOTG_FS_HCTSI\nZ6\nReserved\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5F0\nOTG_FS_HCTSI\nZ7\nReserved\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x800\nOTG_FS_DCFG\nReserved\nPFIVL\nDAD\nReserved\nNZLSOHSK\nDSPD\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x804\nOTG_FS_DCTL\nReserved\nPOPRGDNE\nCGONAK\nSGONAK\nCGINAK\nSGINAK\nTCTL\nGONSTS\nGINSTS\nSDIS\nRWUSIG\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 206. OTG_FS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1334/1757\nRM0090 Rev 21\n0x808\nOTG_FS_DSTS\nReserved\nFNSOF\nReserved\nEERR\nENUMSPD\nSUSPSTS\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x810\nOTG_FS_DIEPM\nSK\nReserved\nNAKM\nReserved\nINEPNEM\nINEPNMM\nITTXFEMSK\nTOM\nReserved\nEPDM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0x814\nOTG_FS_DOEP\nMSK\nReserved\nNAKMSK\nBERRM\nReserved\nOUTPKTERRM\nReserved\nSTSPHSRXM\n OTEPDM\nSTUPM\nReserved\nEPDM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x818\nOTG_FS_DAINT\nOEPINT\nIEPINT\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x81C\nOTG_FS_DAINT\nMSK\nOEPM\nIEPM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x828\nOTG_FS_DVBU\nSDIS\nReserved\nVBUSDT\nReset value\n0\n0\n0\n1\n0\n1\n1\n1\n1\n1\n0\n1\n0\n1\n1\n1\n0x82C\nOTG_FS_DVBU\nSPULSE\nReserved\nDVBUSP\nReset value\n0\n1\n0\n1\n1\n0\n1\n1\n1\n0\n0\n0\n0x834\nOTG_FS_DIEPE\nMPMSK\nReserved\nINEPTXFEM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x900\nOTG_FS_DIEPC\nTL0\nEPENA\nEPDIS\nReserved\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTY\nP\nNAKSTS\nReserved\nUSBAEP\nReserved\nMPSI\nZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0x918\nTG_FS_DTXFST\nS0\nReserved\nINEPTFSAV\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x920\nOTG_FS_DIEPC\nTL1\nEPENA\nEPDIS\nSODDFRM/SD1PID\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x938\nTG_FS_DTXFST\nS1\nReserved\nINEPTFSAV\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 206. OTG_FS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1335/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n0x940\nOTG_FS_DIEPC\nTL2\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x958\nTG_FS_DTXFST\nS2\nReserved\nINEPTFSAV\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x960\nOTG_FS_DIEPC\nTL3\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x978\nTG_FS_DTXFST\nS3\nReserved\nINEPTFSAV\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB00\nOTG_FS_DOEP\nCTL0\nEPENA\nEPDIS\nReserved\nSNAK\nCNAK\nReserved\nSTALL\nSNPM\nEPTY\nP\nNAKSTS\nReserved\nUSBAEP\nReserved\nMPSI\nZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0xB20\nOTG_FS_DOEP\nCTL1\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nReserved\nSTALL\nSNPM\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB40\nOTG_FS_DOEP\nCTL2\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nReserved\nSTALL\nSNPM\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB60\nOTG_FS_DOEP\nCTL3\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nReserved\nSTALL\nSNPM\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x908\nOTG_FS_DIEPI\nNT0\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nReserved\nEPDISD\nXFRC\nReset value\n0\n0\n1\n0\n0\n0\n0\n0\n0\nTable 206. OTG_FS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1336/1757\nRM0090 Rev 21\n0x928\nOTG_FS_DIEPI\nNT1\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nReserved\nEPDISD\nXFRC\nReset value\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0x948\nOTG_FS_DIEPI\nNT2\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nReserved\nEPDISD\nXFRC\nReset value\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0x968\nOTG_FS_DIEPI\nNT3\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nReserved\nEPDISD\nXFRC\nReset value\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0xB08\nOTG_FS_DOEPI\nNT0\nReserved\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nSTSPHSRX\nOTEPDIS\nSTUP\nReserved\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0xB28\nOTG_FS_DOEPI\nNT1\nReserved\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nSTSPHSRX\nOTEPDIS\nSTUP\nReserved\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0xB48\nOTG_FS_DOEPI\nNT2\nReserved\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nSTSPHSRX\nOTEPDIS\nSTUP\nReserved\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0xB68\nOTG_FS_DOEPI\nNT3\nReserved\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nSTSPHSRX\nOTEPDIS\nSTUP\nReserved\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x910\nOTG_FS_DIEPT\nSIZ0\nReserved\nPKTC\nNT\nReserved\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x930\nOTG_FS_DIEPT\nSIZ1\nReserved\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x950\nOTG_FS_DIEPT\nSIZ2\nReserved\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x970\nOTG_FS_DIEPT\nSIZ3\nReserved\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 206. OTG_FS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1337/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0xB10\nOTG_FS_DOEP\nTSIZ0\nReserved\nSTUP\nCNT\nReserved\nPKTCNT\nReserved\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB30\nOTG_FS_DOEP\nTSIZ1\nReserved\nRXDPID/\nSTUPCNT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB50\nOTG_FS_DOEP\nTSIZ2\nReserved\nRXDPID/\nSTUPCNT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB70\nOTG_FS_DOEP\nTSIZ3\nReserved\nRXDPID/\nSTUPCNT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xE00\nOTG_FS_PCGC\nCTL\nReserved\nPHYSUSP\nReserved\nGATEHCLK\nSTPPCLK\nReset value\nTable 206. OTG_FS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1338/1757\nRM0090 Rev 21\n34.17 \nOTG_FS programming model\n34.17.1 \nCore initialization\nThe application must perform the core initialization sequence. If the cable is connected \nduring power-up, the current mode of operation bit in the OTG_FS_GINTSTS (CMOD bit in \nOTG_FS_GINTSTS) reflects the mode. The OTG_FS controller enters host mode when an \n“A” plug is connected or device mode when a “B” plug is connected.\nThis section explains the initialization of the OTG_FS controller after power-on. The \napplication must follow the initialization sequence irrespective of host or device mode \noperation. All core global registers are initialized according to the core’s configuration:\n1.\nProgram the following fields in the OTG_FS_GAHBCFG register:\n–\nGlobal interrupt mask bit GINTMSK = 1\n–\nRxFIFO non-empty (RXFLVL bit in OTG_FS_GINTSTS)\n–\nPeriodic TxFIFO empty level\n2. \nProgram the following fields in the OTG_FS_GUSBCFG register:\n–\nHNP capable bit \n–\nSRP capable bit\n–\nFS timeout calibration field\n–\nUSB turnaround time field\n3. \nThe software must unmask the following bits in the OTG_FS_GINTMSK register:\nOTG interrupt mask\nMode mismatch interrupt mask\n4. \nThe software can read the CMOD bit in OTG_FS_GINTSTS to determine whether the \nOTG_FS controller is operating in host or device mode.\n\n\n<>\n\nRM0090 Rev 21\n1339/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34.17.2 \nHost initialization\nTo initialize the core as host, the application must perform the following steps:\n1.\nProgram the HPRTINT in the OTG_FS_GINTMSK register to unmask\n2. \nProgram the OTG_FS_HCFG register to select full-speed host\n3. \nProgram the PPWR bit in OTG_FS_HPRT to 1. This drives VBUS on the USB.\n4. \nWait for the PCDET interrupt in OTG_FS_HPRT0. This indicates that a device is \nconnecting to the port.\n5. \nProgram the PRST bit in OTG_FS_HPRT to 1. This starts the reset process.\n6. \nWait at least 10 ms for the reset process to complete.\n7. \nProgram the PRST bit in OTG_FS_HPRT to 0.\n8. \nWait for the PENCHNG interrupt in OTG_FS_HPRT.\n9. \nRead the PSPD bit in OTG_FS_HPRT to get the enumerated speed.\n10. Program the HFIR register with a value corresponding to the selected PHY clock 1\n11. Program the FSLSPCS field in the OTG_FS_HCFG register following the speed of the \ndevice detected in step 9. If FSLSPCS has been changed a port reset must be \nperformed.\n12. Program the OTG_FS_GRXFSIZ register to select the size of the receive FIFO.\n13. Program the OTG_FS_HNPTXFSIZ register to select the size and the start address of \nthe Non-periodic transmit FIFO for non-periodic transactions.\n14. Program the OTG_FS_HPTXFSIZ register to select the size and start address of the \nperiodic transmit FIFO for periodic transactions.\nTo communicate with devices, the system software must initialize and enable at least one \nchannel.\n34.17.3 \nDevice initialization\nThe application must perform the following steps to initialize the core as a device on power-\nup or after a mode change from host to device.\n1.\nProgram the following fields in the OTG_FS_DCFG register:\n–\nDevice speed\n–\nNon-zero-length status OUT handshake\n2. \nProgram the OTG_FS_GINTMSK register to unmask the following interrupts:\n–\nUSB reset\n–\nEnumeration done\n–\nEarly suspend\n–\nUSB suspend\n–\nSOF\n3. \nProgram the VBUSBSEN bit in the OTG_FS_GCCFG register to enable VBUS sensing \nin “B” device mode and supply the 5 volts across the pull-up resistor on the DP line.\n4. \nWait for the USBRST interrupt in OTG_FS_GINTSTS. It indicates that a reset has been \ndetected on the USB that lasts for about 10 ms on receiving this interrupt.\nWait for the ENUMDNE interrupt in OTG_FS_GINTSTS. This interrupt indicates the end of \nreset on the USB. On receiving this interrupt, the application must read the OTG_FS_DSTS \n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1340/1757\nRM0090 Rev 21\nregister to determine the enumeration speed and perform the steps listed in Endpoint \ninitialization on enumeration completion on page 1356. \nAt this point, the device is ready to accept SOF packets and perform control transfers on \ncontrol endpoint 0.\n34.17.4 \nHost programming model\nChannel initialization\nThe application must initialize one or more channels before it can communicate with \nconnected devices. To initialize and enable a channel, the application must perform the \nfollowing steps:\n1.\nProgram the OTG_FS_GINTMSK register to unmask the following:\n2. \nChannel interrupt\n–\nNon-periodic transmit FIFO empty for OUT transactions (applicable when \noperating in pipelined transaction-level with the packet count field programmed \nwith more than one).\n–\nNon-periodic transmit FIFO half-empty for OUT transactions (applicable when \noperating in pipelined transaction-level with the packet count field programmed \nwith more than one).\n3. \nProgram the OTG_FS_HAINTMSK register to unmask the selected channels’ \ninterrupts.\n4. \nProgram the OTG_FS_HCINTMSK register to unmask the transaction-related \ninterrupts of interest given in the host channel interrupt register.\n5. \nProgram the selected channel’s OTG_FS_HCTSIZx register with the total transfer size, \nin bytes, and the expected number of packets, including short packets. The application \nmust program the PID field with the initial data PID (to be used on the first OUT \ntransaction or to be expected from the first IN transaction).\n6. \nProgram the OTG_FS_HCCHARx register of the selected channel with the device’s \nendpoint characteristics, such as type, speed, direction, and so forth. (The channel can \nbe enabled by setting the channel enable bit to 1 only when the application is ready to \ntransmit or receive any packet).\nHalting a channel\nThe application can disable any channel by programming the OTG_FS_HCCHARx register \nwith the CHDIS and CHENA bits set to 1. This enables the OTG_FS host to flush the posted \nrequests (if any) and generates a channel halted interrupt. The application must wait for the \nCHH interrupt in OTG_FS_HCINTx before reallocating the channel for other transactions. \nThe OTG_FS host does not interrupt the transaction that has already been started on the \nUSB.\nBefore disabling a channel, the application must ensure that there is at least one free space \navailable in the non-periodic request queue (when disabling a non-periodic channel) or the \nperiodic request queue (when disabling a periodic channel). The application can simply \nflush the posted requests when the Request queue is full (before disabling the channel), by \nprogramming the OTG_FS_HCCHARx register with the CHDIS bit set to 1, and the CHENA \nbit cleared to 0.\nThe application is expected to disable a channel on any of the following conditions:\n\n\n<>\n\nRM0090 Rev 21\n1341/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n1.\nWhen an STALL, TXERR, BBERR or DTERR interrupt in OTG_FS_HCINTx is received \nfor an IN or OUT channel. The application must be able to receive other interrupts \n(DTERR, Nak, Data, TXERR) for the same channel before receiving the halt.\n2. \nWhen a DISCINT (Disconnect Device) interrupt in OTG_FS_GINTSTS is received. \n(The application is expected to disable all enabled channels).\n3. \nWhen the application aborts a transfer before normal completion.\nOperational model\nThe application must initialize a channel before communicating to the connected device. \nThis section explains the sequence of operation to be performed for different types of USB \ntransactions.\n•\nWriting the transmit FIFO\nThe OTG_FS host automatically writes an entry (OUT request) to the periodic/non-\nperiodic request queue, along with the last word write of a packet. The application must \nensure that at least one free space is available in the periodic/non-periodic request \nqueue before starting to write to the transmit FIFO. The application must always write \nto the transmit FIFO in words. If the packet size is non-word aligned, the application \nmust use padding. The OTG_FS host determines the actual packet size based on the \nprogrammed maximum packet size and transfer size.\nFigure 396. Transmit FIFO write task\n•\nReading the receive FIFO\n \nMPS: Maximum packet size\nStart\nai15673b\nWait for NPTXFE/PTXFE\ninterrupt in\nOTG_FS_GINTSTS\nRead GNPTXSTS/HPTXFSIZ\nregisters for available FIFO\n and queue spaces\n1 MPS or\nLPS FIFO space\navailable?\nWrite 1 packet\ndata to\ntransmit FIFO\nMore packets\nto send?\nDone\nNo\nNo\nYes\nYes\nLPS: Last packet size\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1342/1757\nRM0090 Rev 21\nThe application must ignore all packet statuses other than IN data packet (bx0010).\nFigure 397. Receive FIFO read task\n•\nBulk and control OUT/SETUP transactions\nA typical bulk or control OUT/SETUP pipelined transaction-level operation is shown in \nFigure 398. See channel 1 (ch_1). Two bulk OUT packets are transmitted. A control \nSETUP transaction operates in the same way but has only one packet. The \nassumptions are:\n–\nThe application is attempting to send two maximum-packet-size packets (transfer \nsize = 1, 024 bytes).\n–\nThe non-periodic transmit FIFO can hold two packets (128 bytes for FS).\n–\nThe non-periodic request queue depth = 4.\n•\nNormal bulk and control OUT/SETUP operations\nThe sequence of operations in (channel 1) is as follows:\na) \nInitialize channel 1\nb) \nWrite the first packet for channel 1\nc) \nAlong with the last word write, the core writes an entry to the non-periodic request \nqueue\nd) \nAs soon as the non-periodic queue becomes non-empty, the core attempts to \nsend an OUT token in the current frame\ne) \nWrite the second (last) packet for channel 1\nf) \nThe core generates the XFRC interrupt as soon as the last transaction is \ncompleted successfully\nRXFLVL\ninterrupt ?\nRead the received \npacket from the \nReceive FIFO\nRead\nOTG_FS_GRXSTSP\nPKTSTS\n0b0010?\n \nYes\nYes\nUnmask RXFLVL\n \ninterrupt\nBCNT > 0?\n \nNo\nMask RXFLVL\ninterrupt\nYes\nUnmask RXFLVL\n \ninterrupt\nNo\nNo\nStart\nai15674\n\n\n<>\n\nRM0090 Rev 21\n1343/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\ng) \nIn response to the XFRC interrupt, de-allocate the channel for other transfers\nh) \nHandling non-ACK responses\nFigure 398. Normal bulk/control OUT/SETUP and bulk/control IN transactions\nThe channel-specific interrupt service routine for bulk and control OUT/SETUP \ntransactions is shown in the following code samples.\n•\nInterrupt service routine for bulk/control OUT/SETUP and bulk/control IN \ntransactions\na) \nBulk/Control OUT/SETUP\nUnmask (NAK/TXERR/STALL/XFRC)\nif (XFRC)\n{\nACK\nHost\nApplication\nDevice\nAHB\nUSB\nOUT\nDATA0\nMPS\n1 \nMPS\n1 \nMPS\nwrite_tx_fifo\n(ch_1)\ninit_reg(ch_1)\nset_ch_en\n(ch_2)\ninit_reg(ch_2)\nwrite_tx_fifo\n(ch_1)\nset_ch_en\n(ch_2)\nch_2\nch_2\nch_1\nch_1\nDe-allocate\n(ch_1)\nIN\nch_2\nch_2\nch_2\nch_1\nACK\nOUT\nset_ch_en\n(ch_2)\nNon-Periodic Request \nQueue\nAssume that this queue \ncan hold 4 entries.\n4\n1\n6\nACK\nDATA0\nIN\nACK\nread_rx_sts\nread_rx_fifo\n1 \nMPS\nset_ch_en\n(ch_2)\n1 \nMPS\nread_rx_stsre\nad_rx_fifo\nread_rx_sts\nDisable\n(ch_2)\n1\n2\n3\n4\n5\n6\n7\nDe-allocate\n(ch_2)\nCHH interrupt\nr\nch_2\n2\n3\n5\n7\n8\n9\n12\n13\nread_rx_sts\n10\n11\nDATA1 \nMPS\nDATA1\nai15675\nRXFLVL interrupt\nXFRC interrupt\nRXFLVL interrupt\nRXFLVL interrupt\nRXFLVL interrupt\nXFRC interrupt\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1344/1757\nRM0090 Rev 21\nReset Error Count\nMask ACK\nDe-allocate Channel\n}\nelse if (STALL)\n{\nTransfer Done = 1\nUnmask CHH\nDisable Channel\n}\nelse if (NAK or TXERR )\n{\nRewind Buffer Pointers\nUnmask CHH\nDisable Channel\nif (TXERR)\n{\nIncrement Error Count\nUnmask ACK\n}\nelse\n{\nReset Error Count\n}\n}\nelse if (CHH)\n{\nMask CHH\nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\nelse\n{\nRe-initialize Channel\n}\n}\nelse if (ACK)\n{\nReset Error Count\nMask ACK\n}\nThe application is expected to write the data packets into the transmit FIFO as and \nwhen the space is available in the transmit FIFO and the Request queue. The \napplication can make use of the NPTXFE interrupt in OTG_FS_GINTSTS to find the \ntransmit FIFO space.\nb) \nBulk/Control IN\nUnmask (TXERR/XFRC/BBERR/STALL/DTERR)\nif (XFRC)\n{\nReset Error Count\n\n\n<>\n\nRM0090 Rev 21\n1345/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nUnmask CHH\nDisable Channel\nReset Error Count\nMask ACK\n}\nelse if (TXERR or BBERR or STALL)\n{\nUnmask CHH\nDisable Channel\nif (TXERR)\n{\nIncrement Error Count\nUnmask ACK\n}\n}\nelse if (CHH)\n{\nMask CHH\nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\nelse\n{\nRe-initialize Channel\n}\n}\nelse if (ACK)\n{\nReset Error Count\nMask ACK\n}\nelse if (DTERR)\n{\nReset Error Count\n}\nThe application is expected to write the requests as and when the Request queue space is \navailable and until the XFRC interrupt is received.\n•\nBulk and control IN transactions\nA typical bulk or control IN pipelined transaction-level operation is shown in Figure 399. \nSee channel 2 (ch_2). The assumptions are:\n–\nThe application is attempting to receive two maximum-packet-size packets \n(transfer size = 1 024 bytes).\n–\nThe receive FIFO can contain at least one maximum-packet-size packet and two \nstatus words per packet (72 bytes for FS).\n–\nThe non-periodic request queue depth = 4.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1346/1757\nRM0090 Rev 21\nFigure 399. Bulk/control IN transactions\nThe sequence of operations is as follows:\na) \nInitialize channel 2.\nb) \nSet the CHENA bit in HCCHAR2 to write an IN request to the non-periodic request \nqueue.\nc) \nThe core attempts to send an IN token after completing the current OUT \ntransaction.\nd) \nThe core generates an RXFLVL interrupt as soon as the received packet is written \nto the receive FIFO.\ne) \nIn response to the RXFLVL interrupt, mask the RXFLVL interrupt and read the \nreceived packet status to determine the number of bytes received, then read the \nreceive FIFO accordingly. Following this, unmask the RXFLVL interrupt.\nACK\nHost\nApplication\nDevice\nAHB\nUSB\nOUT\nDATA0\nMPS\n1 \nMPS\n1 \nMPS\nwrite_tx_fifo\n(ch_1)\ninit_reg(ch_1)\nset_ch_en\n(ch_2)\ninit_reg(ch_2)\nwrite_tx_fifo\n(ch_1)\nset_ch_en\n(ch_2)\nch_2\nch_2\nch_1\nch_1\nDe-allocate\n(ch_1)\nIN\nch_2\nch_2\nch_2\nch_1\nACK\nOUT\nset_ch_en\n(ch_2)\nNon-Periodic Request \nQueue\nAssume that this queue \ncan hold 4 entries.\n4\n1\n6\nACK\nDATA0\nIN\nACK\nread_rx_sts\nread_rx_fifo\n1 \nMPS\nset_ch_en\n(ch_2)\n1 \nMPS\nread_rx_stsre\nad_rx_fifo\nread_rx_sts\nDisable\n(ch_2)\n1\n2\n3\n4\n5\n6\n7\nDe-allocate\n(ch_2)\nCHH interrupt\nr\nch_2\n2\n3\n5\n7\n8\n9\n12\n13\nread_rx_sts\n10\n11\nDATA1 \nMPS\nDATA1\nai15675\nRXFLVL interrupt\nXFRC interrupt\nRXFLVL interrupt\nRXFLVL interrupt\nRXFLVL interrupt\nXFRC interrupt\n\n\n<>\n\nRM0090 Rev 21\n1347/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nf) \nThe core generates the RXFLVL interrupt for the transfer completion status entry \nin the receive FIFO.\ng) \nThe application must read and ignore the receive packet status when the receive \npacket status is not an IN data packet (PKTSTS in GRXSTSR ≠0b0010).\nh) \nThe core generates the XFRC interrupt as soon as the receive packet status is \nread.\ni) \nIn response to the XFRC interrupt, disable the channel and stop writing the \nOTG_FS_HCCHAR2 register for further requests. The core writes a channel \ndisable request to the non-periodic request queue as soon as the \nOTG_FS_HCCHAR2 register is written.\nj) \nThe core generates the RXFLVL interrupt as soon as the halt status is written to \nthe receive FIFO.\nk) \nRead and ignore the receive packet status.\nl) \nThe core generates a CHH interrupt as soon as the halt status is popped from the \nreceive FIFO.\nm) In response to the CHH interrupt, de-allocate the channel for other transfers.\nn) \nHandling non-ACK responses\n•\nControl transactions\nSetup, Data, and Status stages of a control transfer must be performed as three \nseparate transfers. Setup-, Data- or Status-stage OUT transactions are performed \nsimilarly to the bulk OUT transactions explained previously. Data- or Status-stage IN \ntransactions are performed similarly to the bulk IN transactions explained previously. \nFor all three stages, the application is expected to set the EPTYP field in \nOTG_FS_HCCHAR1 to Control. During the Setup stage, the application is expected to \nset the PID field in OTG_FS_HCTSIZ1 to SETUP.\n•\nInterrupt OUT transactions\nA typical interrupt OUT operation is shown in Figure 400. The assumptions are:\n–\nThe application is attempting to send one packet in every frame (up to 1 maximum \npacket size), starting with the odd frame (transfer size = 1 024 bytes)\n–\nThe periodic transmit FIFO can hold one packet (1 KB)\n–\nPeriodic request queue depth = 4\nThe sequence of operations is as follows:\na) \nInitialize and enable channel 1. The application must set the ODDFRM bit in \nOTG_FS_HCCHAR1.\nb) \nWrite the first packet for channel 1. \nc) \nAlong with the last word write of each packet, the OTG_FS host writes an entry to \nthe periodic request queue.\nd) \nThe OTG_FS host attempts to send an OUT token in the next (odd) frame.\ne) \nThe OTG_FS host generates an XFRC interrupt as soon as the last packet is \ntransmitted successfully.\nf) \nIn response to the XFRC interrupt, reinitialize the channel for the next transfer.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1348/1757\nRM0090 Rev 21\nFigure 400. Normal interrupt OUT/IN transactions\n•\nInterrupt service routine for interrupt OUT/IN transactions\na) \nInterrupt OUT\nUnmask (NAK/TXERR/STALL/XFRC/FRMOR)\nif (XFRC)\n{\nReset Error Count\nMask ACK\nDe-allocate Channel\n}\nelse\nif (STALL or FRMOR)\n{\nMask ACK\nUnmask CHH\nHost\nApplication\nDevice\nAHB\nUSB\nOUT\nDATA0\nMPS\n1 \nMPS\n1 \nMPS\nwrite_tx_fifo\n(ch_1)\ninit_reg(ch_1)\nset_ch_en\n(ch_2)\ninit_reg(ch_2)\nwrite_tx_fifo\n(ch_1)\nIN\nOUT\nDATA1\nMPS\nPeriodic Request Queue\nAssume that this queue \ncan hold 4 entries.\n1\n5\nDATA0\nIN\nRXFLVL interrupt\n1 \nMPS\nread_rx_sts\nread_rx_fifo\nread_rx_sts\n1\n2\n3\n4\n6\n2\n3\n6\n7\n8\n9\nOdd\n(micro)\nframe\nEven\n(micro)\nframe\ninit_reg(ch_1)\nset_ch_en\n(ch_2)\ninit_reg(ch_2)\nwrite_tx_fifo\n(ch_1)\ninit_reg(ch_1)\n1 \nMPS\nDATA1\n5\n4\nACK\nACK\nACK\nch_1\nch_2\nch_2\nch_1\nai15676\nRXFLVL interrupt\nXFRC interrupt\nXFRC interrupt\nXFRC interrupt\n\n\n<>\n\nRM0090 Rev 21\n1349/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nDisable Channel\nif (STALL)\n{\nTransfer Done = 1\n}\n}\nelse\nif (NAK or TXERR)\n{\nRewind Buffer Pointers\nReset Error Count\nMask ACK\nUnmask CHH\nDisable Channel\n}\nelse\nif (CHH)\n{\nMask CHH\nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\nelse\n{\nRe-initialize Channel (in next b_interval - 1 Frame)\n}\n}\nelse\nif (ACK)\n{\nReset Error Count\nMask ACK\n}\nThe application uses the NPTXFE interrupt in OTG_FS_GINTSTS to find the transmit \nFIFO space.\nb) \nInterrupt IN\nUnmask (NAK/TXERR/XFRC/BBERR/STALL/FRMOR/DTERR)\nif (XFRC)\n{\nReset Error Count\nMask ACK\nif (OTG_FS_HCTSIZx.PKTCNT == 0)\n{\nDe-allocate Channel\n}\nelse\n{\nTransfer Done = 1\nUnmask CHH\nDisable Channel\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1350/1757\nRM0090 Rev 21\n}\n}\nelse\nif (STALL or FRMOR or NAK or DTERR or BBERR)\n{\nMask ACK\nUnmask CHH\nDisable Channel\n \nif (STALL or BBERR)\n{\nReset Error Count\nTransfer Done = 1\n}\nelse\nif (!FRMOR)\n{\nReset Error Count\n}\n}\nelse\nif (TXERR)\n{\nIncrement Error Count\nUnmask ACK\nUnmask CHH\nDisable Channel\n}\nelse\nif (CHH)\n{\nMask CHH\n \nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\n \nelse\n \nRe-initialize Channel (in next b_interval - 1 /Frame)\n}\n}\nelse\nif (ACK)\n{\nReset Error Count\nMask ACK\n\n\n<>\n\nRM0090 Rev 21\n1351/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n}\n•\nInterrupt IN transactions\nThe assumptions are:\n–\nThe application is attempting to receive one packet (up to 1 maximum packet size) \nin every frame, starting with odd (transfer size = 1 024 bytes).\n–\nThe receive FIFO can hold at least one maximum-packet-size packet and two \nstatus words per packet (1 031 bytes).\n–\nPeriodic request queue depth = 4.\n•\nNormal interrupt IN operation\nThe sequence of operations is as follows:\na) \nInitialize channel 2. The application must set the ODDFRM bit in \nOTG_FS_HCCHAR2.\nb) \nSet the CHENA bit in OTG_FS_HCCHAR2 to write an IN request to the periodic \nrequest queue. \nc) \nThe OTG_FS host writes an IN request to the periodic request queue for each \nOTG_FS_HCCHAR2 register write with the CHENA bit set.\nd) \nThe OTG_FS host attempts to send an IN token in the next (odd) frame.\ne) \nAs soon as the IN packet is received and written to the receive FIFO, the OTG_FS \nhost generates an RXFLVL interrupt.\nf) \nIn response to the RXFLVL interrupt, read the received packet status to determine \nthe number of bytes received, then read the receive FIFO accordingly. The \napplication must mask the RXFLVL interrupt before reading the receive FIFO, and \nunmask after reading the entire packet.\ng) \nThe core generates the RXFLVL interrupt for the transfer completion status entry \nin the receive FIFO. The application must read and ignore the receive packet \nstatus when the receive packet status is not an IN data packet (PKTSTS in \nGRXSTSR ≠0b0010).\nh) \nThe core generates an XFRC interrupt as soon as the receive packet status is \nread.\ni) \nIn response to the XFRC interrupt, read the PKTCNT field in OTG_FS_HCTSIZ2. \nIf the PKTCNT bit in OTG_FS_HCTSIZ2 is not equal to 0, disable the channel \nbefore re-initializing the channel for the next transfer, if any). If PKTCNT bit in \n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1352/1757\nRM0090 Rev 21\nOTG_FS_HCTSIZ2 = 0, reinitialize the channel for the next transfer. This time, the \napplication must reset the ODDFRM bit in OTG_FS_HCCHAR2.\n•\nIsochronous OUT transactions\nA typical isochronous OUT operation is shown in Figure 401. The assumptions are:\n–\nThe application is attempting to send one packet every frame (up to 1 maximum \npacket size), starting with an odd frame. (transfer size = 1 024 bytes).\n–\nThe periodic transmit FIFO can hold one packet (1 KB).\n–\nPeriodic request queue depth = 4.\nThe sequence of operations is as follows:\na) \nInitialize and enable channel 1. The application must set the ODDFRM bit in \nOTG_FS_HCCHAR1.\nb) \nWrite the first packet for channel 1.\nc) \nAlong with the last word write of each packet, the OTG_FS host writes an entry to \nthe periodic request queue.\nd) \nThe OTG_FS host attempts to send the OUT token in the next frame (odd).\ne) \nThe OTG_FS host generates the XFRC interrupt as soon as the last packet is \ntransmitted successfully.\nf) \nIn response to the XFRC interrupt, reinitialize the channel for the next transfer.\ng) \nHandling non-ACK responses\n\n\n<>\n\nRM0090 Rev 21\n1353/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nFigure 401. Normal isochronous OUT/IN transactions\n•\nInterrupt service routine for isochronous OUT/IN transactions\nCode sample: Isochronous OUT\nUnmask (FRMOR/XFRC)\nif (XFRC)\n{\nDe-allocate Channel\n}\nelse\nif (FRMOR)\n{\nUnmask CHH\nDisable Channel\n}\nHost\nApplication\nDevice\nAHB\nUSB\nOUT\nDATA0\nMPS\n1 \nMPS\n1 \nMPS\nwrite_tx_fifo\n(ch_1)\ninit_reg(ch_1)\nset_ch_en\n(ch_2)\ninit_reg(ch_2)\nwrite_tx_fifo\n(ch_1)\nIN\nOUT\nDATA1\nMPS\nPeriodic Request Queue\nAssume that this queue \ncan hold 4 entries.\n1\n5\nDATA0\nIN\nRXFLVL interrupt\n1 \nMPS\nread_rx_sts\nread_rx_fifo\nread_rx_sts\n1\n2\n3\n4\n6\n2\n3\n6\n7\n8\n9\nOdd\n(micro)\nframe\nEven\n(micro)\nframe\ninit_reg(ch_1)\nset_ch_en\n(ch_2)\ninit_reg(ch_2)\nwrite_tx_fifo\n(ch_1)\ninit_reg(ch_1)\n1 \nMPS\nDATA1\n5\n4\nACK\nACK\nACK\nch_1\nch_2\nch_2\nch_1\nai15676\nRXFLVL interrupt\nXFRC interrupt\nXFRC interrupt\nXFRC interrupt\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1354/1757\nRM0090 Rev 21\nelse\nif (CHH)\n{\nMask CHH\nDe-allocate Channel\n}\nCode sample: Isochronous IN\nUnmask (TXERR/XFRC/FRMOR/BBERR)\nif (XFRC or FRMOR)\n{\nif (XFRC and (OTG_FS_HCTSIZx.PKTCNT == 0))\n{\nReset Error Count\nDe-allocate Channel\n}\nelse\n{\nUnmask CHH\nDisable Channel\n}\n}\nelse\nif (TXERR or BBERR)\n{\nIncrement Error Count\nUnmask CHH\nDisable Channel\n}\nelse\nif (CHH)\n{\nMask CHH\nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\nelse\n{\nRe-initialize Channel\n}\n}\n\n\n<>\n\nRM0090 Rev 21\n1355/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n \n•\nIsochronous IN transactions\nThe assumptions are:\n–\nThe application is attempting to receive one packet (up to 1 maximum packet size) \nin every frame starting with the next odd frame (transfer size = 1 024 bytes).\n–\nThe receive FIFO can hold at least one maximum-packet-size packet and two \nstatus word per packet (1 031 bytes).\n–\nPeriodic request queue depth = 4.\nThe sequence of operations is as follows:\na) \nInitialize channel 2. The application must set the ODDFRM bit in \nOTG_FS_HCCHAR2.\nb) \nSet the CHENA bit in OTG_FS_HCCHAR2 to write an IN request to the periodic \nrequest queue. \nc) \nThe OTG_FS host writes an IN request to the periodic request queue for each \nOTG_FS_HCCHAR2 register write with the CHENA bit set.\nd) \nThe OTG_FS host attempts to send an IN token in the next odd frame.\ne) \nAs soon as the IN packet is received and written to the receive FIFO, the OTG_FS \nhost generates an RXFLVL interrupt.\nf) \nIn response to the RXFLVL interrupt, read the received packet status to determine \nthe number of bytes received, then read the receive FIFO accordingly. The \napplication must mask the RXFLVL interrupt before reading the receive FIFO, and \nunmask it after reading the entire packet.\ng) \nThe core generates an RXFLVL interrupt for the transfer completion status entry in \nthe receive FIFO. This time, the application must read and ignore the receive \npacket status when the receive packet status is not an IN data packet (PKTSTS bit \nin OTG_FS_GRXSTSR ≠0b0010).\nh) \nThe core generates an XFRC interrupt as soon as the receive packet status is \nread.\ni) \nIn response to the XFRC interrupt, read the PKTCNT field in OTG_FS_HCTSIZ2. \nIf PKTCNT ≠0 in OTG_FS_HCTSIZ2, disable the channel before re-initializing the \nchannel for the next transfer, if any. If PKTCNT = 0 in OTG_FS_HCTSIZ2, \nreinitialize the channel for the next transfer. This time, the application must reset \nthe ODDFRM bit in OTG_FS_HCCHAR2.\n•\nSelecting the queue depth\nChoose the periodic and non-periodic request queue depths carefully to match the \nnumber of periodic/non-periodic endpoints accessed.\nThe non-periodic request queue depth affects the performance of non-periodic \ntransfers. The deeper the queue (along with sufficient FIFO size), the more often the \ncore is able to pipeline non-periodic transfers. If the queue size is small, the core is \nable to put in new requests only when the queue space is freed up.\nThe core’s periodic request queue depth is critical to perform periodic transfers as \nscheduled. Select the periodic queue depth, based on the number of periodic transfers \nscheduled in a microframe. If the periodic request queue depth is smaller than the \nperiodic transfers scheduled in a microframe, a frame overrun condition occurs.\n•\nHandling babble conditions\nOTG_FS controller handles two cases of babble: packet babble and port babble. \nPacket babble occurs if the device sends more data than the maximum packet size for \n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1356/1757\nRM0090 Rev 21\nthe channel. Port babble occurs if the core continues to receive data from the device at \nEOF2 (the end of frame 2, which is very close to SOF).\nWhen OTG_FS controller detects a packet babble, it stops writing data into the Rx \nbuffer and waits for the end of packet (EOP). When it detects an EOP, it flushes already \nwritten data in the Rx buffer and generates a Babble interrupt to the application.\nWhen OTG_FS controller detects a port babble, it flushes the RxFIFO and disables the \nport. The core then generates a Port disabled interrupt (HPRTINT in \nOTG_FS_GINTSTS, PENCHNG in OTG_FS_HPRT). On receiving this interrupt, the \napplication must determine that this is not due to an overcurrent condition (another \ncause of the Port Disabled interrupt) by checking POCA in OTG_FS_HPRT, then \nperform a soft reset. The core does not send any more tokens after it has detected a \nport babble condition.\n34.17.5 \nDevice programming model\nEndpoint initialization on USB reset\n1.\nSet the NAK bit for all OUT endpoints\n–\nSNAK = 1 in OTG_FS_DOEPCTLx (for all OUT endpoints)\n2. \nUnmask the following interrupt bits\n–\nINEP0 = 1 in OTG_FS_DAINTMSK (control 0 IN endpoint)\n–\nOUTEP0 = 1 in OTG_FS_DAINTMSK (control 0 OUT endpoint)\n–\nSTUP = 1 in DOEPMSK\n–\nXFRC = 1 in DOEPMSK\n–\nXFRC = 1 in DIEPMSK\n–\nTOC = 1 in DIEPMSK\n3. \nSet up the Data FIFO RAM for each of the FIFOs\n–\nProgram the OTG_FS_GRXFSIZ register, to be able to receive control OUT data \nand setup data. If thresholding is not enabled, at a minimum, this must be equal to \n1 max packet size of control endpoint 0 + 2 words (for the status of the control \nOUT data packet) + 10 words (for setup packets).\n–\nProgram the OTG_FS_TX0FSIZ register (depending on the FIFO number chosen) \nto be able to transmit control IN data. At a minimum, this must be equal to 1 max \npacket size of control endpoint 0.\n4. \nProgram the following fields in the endpoint-specific registers for control OUT endpoint \n0 to receive a SETUP packet\n–\nSTUPCNT = 3 in OTG_FS_DOEPTSIZ0 (to receive up to 3 back-to-back SETUP \npackets)\nAt this point, all initialization required to receive SETUP packets is done.\nEndpoint initialization on enumeration completion\n1.\nOn the Enumeration Done interrupt (ENUMDNE in OTG_FS_GINTSTS), read the \nOTG_FS_DSTS register to determine the enumeration speed.\n2. \nProgram the MPSIZ field in OTG_FS_DIEPCTL0 to set the maximum packet size. This \nstep configures control endpoint 0. The maximum packet size for a control endpoint \ndepends on the enumeration speed.\n\n\n<>\n\nRM0090 Rev 21\n1357/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nAt this point, the device is ready to receive SOF packets and is configured to perform control \ntransfers on control endpoint 0.\nEndpoint initialization on SetAddress command\nThis section describes what the application must do when it receives a SetAddress \ncommand in a SETUP packet.\n1.\nProgram the OTG_FS_DCFG register with the device address received in the \nSetAddress command\n2. \nProgram the core to send out a status IN packet\nEndpoint initialization on SetConfiguration/SetInterface command\nThis section describes what the application must do when it receives a SetConfiguration or \nSetInterface command in a SETUP packet.\n1.\nWhen a SetConfiguration command is received, the application must program the \nendpoint registers to configure them with the characteristics of the valid endpoints in \nthe new configuration.\n2. \nWhen a SetInterface command is received, the application must program the endpoint \nregisters of the endpoints affected by this command.\n3. \nSome endpoints that were active in the prior configuration or alternate setting are not \nvalid in the new configuration or alternate setting. These invalid endpoints must be \ndeactivated.\n4. \nUnmask the interrupt for each active endpoint and mask the interrupts for all inactive \nendpoints in the OTG_FS_DAINTMSK register.\n5. \nSet up the Data FIFO RAM for each FIFO.\n6. \nAfter all required endpoints are configured; the application must program the core to \nsend a status IN packet.\nAt this point, the device core is configured to receive and transmit any type of data packet.\nEndpoint activation\nThis section describes the steps required to activate a device endpoint or to configure an \nexisting device endpoint to a new type.\n1.\nProgram the characteristics of the required endpoint into the following fields of the \nOTG_FS_DIEPCTLx register (for IN or bidirectional endpoints) or the \nOTG_FS_DOEPCTLx register (for OUT or bidirectional endpoints).\n–\nMaximum packet size\n–\nUSB active endpoint = 1\n–\nEndpoint start data toggle (for interrupt and bulk endpoints)\n–\nEndpoint type\n–\nTxFIFO number\n2. \nOnce the endpoint is activated, the core starts decoding the tokens addressed to that \nendpoint and sends out a valid handshake for each valid token received for the \nendpoint.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1358/1757\nRM0090 Rev 21\nEndpoint deactivation\nThis section describes the steps required to deactivate an existing endpoint.\n1.\nIn the endpoint to be deactivated, clear the USB active endpoint bit in the \nOTG_FS_DIEPCTLx register (for IN or bidirectional endpoints) or the \nOTG_FS_DOEPCTLx register (for OUT or bidirectional endpoints).\n2. \nOnce the endpoint is deactivated, the core ignores tokens addressed to that endpoint, \nwhich results in a timeout on the USB.\nNote:\nThe application must meet the following conditions to set up the device core to handle \ntraffic:\nNPTXFEM and RXFLVLM in the OTG_FS_GINTMSK register must be cleared.\n34.17.6 \nOperational model\nSETUP and OUT data transfers\nThis section describes the internal data flow and application-level operations during data \nOUT transfers and SETUP transactions.\n•\nPacket read\nThis section describes how to read packets (OUT data and SETUP packets) from the \nreceive FIFO.\n1.\nOn catching an RXFLVL interrupt (OTG_FS_GINTSTS register), the application must \nread the Receive status pop register (OTG_FS_GRXSTSP).\n2. \nThe application can mask the RXFLVL interrupt (in OTG_FS_GINTSTS) by writing to \nRXFLVL = 0 (in OTG_FS_GINTMSK), until it has read the packet from the receive \nFIFO.\n3. \nIf the received packet’s byte count is not 0, the byte count amount of data is popped \nfrom the receive Data FIFO and stored in memory. If the received packet byte count is \n0, no data is popped from the receive data FIFO.\n4. \nThe receive FIFO’s packet status readout indicates one of the following:\na) \nGlobal OUT NAK pattern:\nPKTSTS = Global OUT NAK, BCNT = 0x000, EPNUM = Don’t Care (0x0), \nDPID = Don’t Care (0b00).\nThese data indicate that the global OUT NAK bit has taken effect.\nb) \nSETUP packet pattern:\nPKTSTS = SETUP, BCNT = 0x008, EPNUM = Control EP Num, DPID = D0. \nThese data indicate that a SETUP packet for the specified endpoint is now \navailable for reading from the receive FIFO.\nc) \nSetup stage done pattern:\nPKTSTS = Setup Stage Done, BCNT = 0x0, EPNUM = Control EP Num, \nDPID = Don’t Care (0b00).\nThese data indicate that the Setup stage for the specified endpoint has completed \nand the Data stage has started. After this entry is popped from the receive FIFO, \nthe core asserts a Setup interrupt on the specified control OUT endpoint.\nd) \nData OUT packet pattern:\nPKTSTS = DataOUT, BCNT = size of the received data OUT packet (0 ≤BCNT \n≤1 024), EPNUM = EPNUM on which the packet was received, DPID = Actual \nData PID.\n\n\n<>\n\nRM0090 Rev 21\n1359/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\ne) \nData transfer completed pattern:\nPKTSTS = Data OUT Transfer Done, BCNT = 0x0, EPNUM = OUT EP Num \non which the data transfer is complete, DPID = Don’t Care (0b00).\nThese data indicate that an OUT data transfer for the specified OUT endpoint has \ncompleted. After this entry is popped from the receive FIFO, the core asserts a \nTransfer Completed interrupt on the specified OUT endpoint.\n5. \nAfter the data payload is popped from the receive FIFO, the RXFLVL interrupt \n(OTG_FS_GINTSTS) must be unmasked.\n6. \nSteps 1–5 are repeated every time the application detects assertion of the interrupt line \ndue to RXFLVL in OTG_FS_GINTSTS. Reading an empty receive FIFO can result in \nundefined core behavior.\nFigure 402 provides a flowchart of the above procedure.\nFigure 402. Receive FIFO packet read\n•\nSETUP transactions\nThis section describes how the core handles SETUP packets and the application’s \nsequence for handling SETUP transactions.\n•\nApplication requirements\n1.\nTo receive a SETUP packet, the STUPCNT field (OTG_FS_DOEPTSIZx) in a control \nOUT endpoint must be programmed to a non-zero value. When the application \nprograms the STUPCNT field to a non-zero value, the core receives SETUP packets \nand writes them to the receive FIFO, irrespective of the NAK status and EPENA bit \nsetting in OTG_FS_DOEPCTLx. The STUPCNT field is decremented every time the \ncontrol endpoint receives a SETUP packet. If the STUPCNT field is not programmed to \na proper value before receiving a SETUP packet, the core still receives the SETUP \npacket and decrements the STUPCNT field, but the application may not be able to \nword_cnt =\nBCNT[11:2] +\nC\n \n(BCNT[1] | BCNT[1])\nrcv_out_pkt()\nrd_data = rd_reg (OTG_FS_GRXSTSP);\nmem[0: word_cnt – 1] =\nrd_rxfifo(rd_data.EPNUM, \nword_cnt)\nN\nrd_data.BCNT = 0\n \nwait until RXFLVL in OTG_FS_GINTSTSG\npacket \nstore in \nmemory\nY\nai15677b\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1360/1757\nRM0090 Rev 21\ndetermine the correct number of SETUP packets received in the Setup stage of a \ncontrol transfer.\n–\nSTUPCNT = 3 in OTG_FS_DOEPTSIZx\n2. \nThe application must always allocate some extra space in the Receive data FIFO, to be \nable to receive up to three SETUP packets on a control endpoint.\n–\nThe space to be reserved is 10 words. Three words are required for the first \nSETUP packet, 1 word is required for the Setup stage done word and 6 words are \nrequired to store two extra SETUP packets among all control endpoints.\n–\n3 words per SETUP packet are required to store 8 bytes of SETUP data and 4 \nbytes of SETUP status (Setup packet pattern). The core reserves this space in the \nreceive data FIFO to write SETUP data only, and never uses this space for data \npackets.\n3. \nThe application must read the 2 words of the SETUP packet from the receive FIFO. \n4. \nThe application must read and discard the Setup stage done word from the receive \nFIFO.\n•\nInternal data flow\n1.\nWhen a SETUP packet is received, the core writes the received data to the receive \nFIFO, without checking for available space in the receive FIFO and irrespective of the \nendpoint’s NAK and STALL bit settings.\n–\nThe core internally sets the IN NAK and OUT NAK bits for the control IN/OUT \nendpoints on which the SETUP packet was received.\n2. \nFor every SETUP packet received on the USB, 3 words of data are written to the \nreceive FIFO, and the STUPCNT field is decremented by 1.\n–\nThe first word contains control information used internally by the core\n–\nThe second word contains the first 4 bytes of the SETUP command\n–\nThe third word contains the last 4 bytes of the SETUP command\n3. \nWhen the Setup stage changes to a Data IN/OUT stage, the core writes an entry \n(Setup stage done word) to the receive FIFO, indicating the completion of the Setup \nstage.\n4. \nOn the AHB side, SETUP packets are emptied by the application.\n5. \nWhen the application pops the Setup stage done word from the receive FIFO, the core \ninterrupts the application with an STUP interrupt (OTG_FS_DOEPINTx), indicating it \ncan process the received SETUP packet.\n–\nThe core clears the endpoint enable bit for control OUT endpoints.\n•\nApplication programming sequence\n1.\nProgram the OTG_FS_DOEPTSIZx register.\n–\nSTUPCNT = 3\n2. \nWait for the RXFLVL interrupt (OTG_FS_GINTSTS) and empty the data packets from \nthe receive FIFO.\n3. \nAssertion of the STUP interrupt (OTG_FS_DOEPINTx) marks a successful completion \nof the SETUP Data Transfer.\n–\nOn this interrupt, the application must read the OTG_FS_DOEPTSIZx register to \ndetermine the number of SETUP packets received and process the last received \nSETUP packet.\n\n\n<>\n\nRM0090 Rev 21\n1361/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nFigure 403. Processing a SETUP packet\n•\nHandling more than three back-to-back SETUP packets\nPer the USB 2.0 specification, normally, during a SETUP packet error, a host does not send \nmore than three back-to-back SETUP packets to the same endpoint. However, the USB 2.0 \nspecification does not limit the number of back-to-back SETUP packets a host can send to \nthe same endpoint. When this condition occurs, the OTG_FS controller generates an \ninterrupt (B2BSTUP in OTG_FS_DOEPINTx).\n•\nSetting the global OUT NAK\nInternal data flow\n1.\nWhen the application sets the Global OUT NAK (SGONAK bit in OTG_FS_DCTL), the \ncore stops writing data, except SETUP packets, to the receive FIFO. Irrespective of the \nspace availability in the receive FIFO, non-isochronous OUT tokens receive a NAK \nhandshake response, and the core ignores isochronous OUT data packets\n2. \nThe core writes the Global OUT NAK pattern to the receive FIFO. The application must \nreserve enough receive FIFO space to write this data pattern.\n3. \nWhen the application pops the Global OUT NAK pattern word from the receive FIFO, \nthe core sets the GONAKEFF interrupt (OTG_FS_GINTSTS).\n4. \nOnce the application detects this interrupt, it can assume that the core is in Global OUT \nNAK mode. The application can clear this interrupt by clearing the SGONAK bit in \nOTG_FS_DCTL.\nWait for STUP in OTG_FS_DOEPINTx\nrem_supcnt = \nrd_reg(DOEPTSIZx)\nsetup_cmd[31:0] = mem[4 – 2 * rem_supcnt]\nsetup_cmd[63:32] = mem[5 – 2 * rem_supcnt]\nctrl-rd/wr/2 stage\nFind setup cmd type\nWrite\n2-stage\nRead\nsetup_np_in_pkt\nStatus IN phase\nrcv_out_pkt\nData OUT phase\nsetup_np_in_pkt\nData IN phase\nai15678\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1362/1757\nRM0090 Rev 21\nApplication programming sequence\n1.\nTo stop receiving any kind of data in the receive FIFO, the application must set the \nGlobal OUT NAK bit by programming the following field:\n–\nSGONAK = 1 in OTG_FS_DCTL\n2. \nWait for the assertion of the GONAKEFF interrupt in OTG_FS_GINTSTS. When \nasserted, this interrupt indicates that the core has stopped receiving any type of data \nexcept SETUP packets.\n3. \nThe application can receive valid OUT packets after it has set SGONAK in \nOTG_FS_DCTL and before the core asserts the GONAKEFF interrupt \n(OTG_FS_GINTSTS).\n4. \nThe application can temporarily mask this interrupt by writing to the GINAKEFFM bit in \nthe OTG_FS_GINTMSK register.\n–\nGINAKEFFM = 0 in the OTG_FS_GINTMSK register \n5. \nWhenever the application is ready to exit the Global OUT NAK mode, it must clear the \nSGONAK bit in OTG_FS_DCTL. This also clears the GONAKEFF interrupt \n(OTG_FS_GINTSTS).\n–\nOTG_FS_DCTL = 1 in CGONAK\n6. \nIf the application has masked this interrupt earlier, it must be unmasked as follows:\n–\nGINAKEFFM = 1 in GINTMSK\n•\nDisabling an OUT endpoint\nThe application must use this sequence to disable an OUT endpoint that it has enabled.\nApplication programming sequence\n1.\nBefore disabling any OUT endpoint, the application must enable Global OUT NAK \nmode in the core.\n–\nSGONAK = 1 in OTG_FS_DCTL\n2. \nWait for the GONAKEFF interrupt (OTG_FS_GINTSTS)\n3. \nDisable the required OUT endpoint by programming the following fields:\n–\nEPDIS = 1 in OTG_FS_DOEPCTLx\n–\nSNAK = 1 in OTG_FS_DOEPCTLx\n4. \nWait for the EPDISD interrupt (OTG_FS_DOEPINTx), which indicates that the OUT \nendpoint is completely disabled. When the EPDISD interrupt is asserted, the core also \nclears the following bits:\n–\nEPDIS = 0 in OTG_FS_DOEPCTLx\n–\nEPENA = 0 in OTG_FS_DOEPCTLx\n5. \nThe application must clear the Global OUT NAK bit to start receiving data from other \nnon-disabled OUT endpoints.\n–\nSGONAK = 0 in OTG_FS_DCTL\n•\nTransfer Stop Programming for OUT endpoints\nThe application must use the following programing sequence to stop any transfers (because \nof an interrupt from the host, typically a reset).\n\n\n<>\n\nRM0090 Rev 21\n1363/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nSequence of operations:\n1.\nEnable all OUT endpoints by setting\n–\nEPENA = 1 in all OTG_FS_DOEPCTLx registers.\n2. \nFlush the RxFIFO as follows\n–\nPoll OTG_FS_GRSTCTL.AHBIDL until it is 1. This indicates that AHB master is \nidle.\n–\nPerform read modify write operation on OTG_FS_GRSTCTL.RXFFLSH =1\n–\nPoll OTG_FS_GRSTCTL.RXFFLSH until it is 0, but also using a timeout of less \nthan 10 milli-seconds (corresponds to minimum reset signaling duration). If 0 is \nseen before the timeout, then the RxFIFO flush is successful. If at the moment the \ntimeout occurs, there is still a 1, (this may be due to a packet on EP0 coming from \nthe host) then go back (once only) to the previous step (“Perform read modify write \noperation”).\n3. \nBefore disabling any OUT endpoint, the application must enable Global OUT NAK \nmode in the core, according to the instructions in “Setting the global OUT NAK on \npage 1361”. This ensures that data in the RxFIFO is sent to the application \nsuccessfully. Set SGONAK = 1 in OTG_FS_DCTL\n4. \nWait for the GONAKEFF interrupt (OTG_FS_GINTSTS)\n5. \nDisable all active OUT endpoints by programming the following register bits:\n–\nEPDIS = 1 in registers OTG_FS_DOEPCTLx\n–\nSNAK = 1 in registers OTG_FS_DOEPCTLx\n6. \nWait for the EPDIS interrupt in OTG_FS_DOEPINTx for each OUT endpoint \nprogrammed in the previous step. The EPDIS interrupt in OTG_FS_DOEPINTx \nindicates that the corresponding OUT endpoint is completely disabled. When the \nEPDIS interrupt is asserted, the following bits are cleared:\n–\nEPENA = 0 in registers OTG_FS_DOEPCTLx\n–\nEPDIS = 0 in registers OTG_FS_DOEPCTLx\n–\nSNAK = 0 in registers OTG_FS_DOEPCTLx\n•\nGeneric non-isochronous OUT data transfers\nThis section describes a regular non-isochronous OUT data transfer (control, bulk, or \ninterrupt).\nApplication requirements\n1.\nBefore setting up an OUT transfer, the application must allocate a buffer in the memory \nto accommodate all data to be received as part of the OUT transfer.\n2. \nFor OUT transfers, the transfer size field in the endpoint’s transfer size register must be \na multiple of the maximum packet size of the endpoint, adjusted to the word boundary.\n–\ntransfer size[EPNUM] = n × (MPSIZ[EPNUM] + 4 – (MPSIZ[EPNUM] mod 4))\n–\npacket count[EPNUM] = n\n–\nn > 0\n3. \nOn any OUT endpoint interrupt, the application must read the endpoint’s transfer size \nregister to calculate the size of the payload in the memory. The received payload size \ncan be less than the programmed transfer size.\n–\nPayload size in memory = application programmed initial transfer size – core \nupdated final transfer size\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1364/1757\nRM0090 Rev 21\n–\nNumber of USB packets in which this payload was received = application \nprogrammed initial packet count – core updated final packet count\nInternal data flow\n1.\nThe application must set the transfer size and packet count fields in the endpoint-\nspecific registers, clear the NAK bit, and enable the endpoint to receive the data.\n2. \nOnce the NAK bit is cleared, the core starts receiving data and writes it to the receive \nFIFO, as long as there is space in the receive FIFO. For every data packet received on \nthe USB, the data packet and its status are written to the receive FIFO. Every packet \n(maximum packet size or short packet) written to the receive FIFO decrements the \npacket count field for that endpoint by 1.\n–\nOUT data packets received with bad data CRC are flushed from the receive FIFO \nautomatically.\n–\nAfter sending an ACK for the packet on the USB, the core discards non-\nisochronous OUT data packets that the host, which cannot detect the ACK, re-\nsends. The application does not detect multiple back-to-back data OUT packets \non the same endpoint with the same data PID. In this case the packet count is not \ndecremented.\n–\nIf there is no space in the receive FIFO, isochronous or non-isochronous data \npackets are ignored and not written to the receive FIFO. Additionally, non-\nisochronous OUT tokens receive a NAK handshake reply.\n–\nIn all the above three cases, the packet count is not decremented because no data \nare written to the receive FIFO.\n3. \nWhen the packet count becomes 0 or when a short packet is received on the endpoint, \nthe NAK bit for that endpoint is set. Once the NAK bit is set, the isochronous or non-\nisochronous data packets are ignored and not written to the receive FIFO, and non-\nisochronous OUT tokens receive a NAK handshake reply.\n4. \nAfter the data are written to the receive FIFO, the application reads the data from the \nreceive FIFO and writes it to external memory, one packet at a time per endpoint.\n5. \nAt the end of every packet write on the AHB to external memory, the transfer size for \nthe endpoint is decremented by the size of the written packet.\n6. \nThe OUT data transfer completed pattern for an OUT endpoint is written to the receive \nFIFO on one of the following conditions:\n–\nThe transfer size is 0 and the packet count is 0\n–\nThe last OUT data packet written to the receive FIFO is a short packet\n(0 ≤packet size < maximum packet size)\n7. \nWhen either the application pops this entry (OUT data transfer completed), a transfer \ncompleted interrupt is generated for the endpoint and the endpoint enable is cleared.\n\n\n<>\n\nRM0090 Rev 21\n1365/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nApplication programming sequence\n1.\nProgram the OTG_FS_DOEPTSIZx register for the transfer size and the corresponding \npacket count.\n2. \nProgram the OTG_FS_DOEPCTLx register with the endpoint characteristics, and set \nthe EPENA and CNAK bits.\n–\nEPENA = 1 in OTG_FS_DOEPCTLx\n–\nCNAK = 1 in OTG_FS_DOEPCTLx\n3. \nWait for the RXFLVL interrupt (in OTG_FS_GINTSTS) and empty the data packets \nfrom the receive FIFO.\n–\nThis step can be repeated many times, depending on the transfer size.\n4. \nAsserting the XFRC interrupt (OTG_FS_DOEPINTx) marks a successful completion of \nthe non-isochronous OUT data transfer.\n5. \nRead the OTG_FS_DOEPTSIZx register to determine the size of the received data \npayload.\n•\nGeneric isochronous OUT data transfer\nThis section describes a regular isochronous OUT data transfer.\nApplication requirements\n1.\nAll the application requirements for non-isochronous OUT data transfers also apply to \nisochronous OUT data transfers.\n2. \nFor isochronous OUT data transfers, the transfer size and packet count fields must \nalways be set to the number of maximum-packet-size packets that can be received in a \nsingle frame and no more. Isochronous OUT data transfers cannot span more than 1 \nframe.\n3. \nThe application must read all isochronous OUT data packets from the receive FIFO \n(data and status) before the end of the periodic frame (EOPF interrupt in \nOTG_FS_GINTSTS).\n4. \nTo receive data in the following frame, an isochronous OUT endpoint must be enabled \nafter the EOPF (OTG_FS_GINTSTS) and before the SOF (OTG_FS_GINTSTS).\nInternal data flow\n1.\nThe internal data flow for isochronous OUT endpoints is the same as that for non-\nisochronous OUT endpoints, but for a few differences.\n2. \nWhen an isochronous OUT endpoint is enabled by setting the Endpoint Enable and \nclearing the NAK bits, the Even/Odd frame bit must also be set appropriately. The core \nreceives data on an isochronous OUT endpoint in a particular frame only if the \nfollowing condition is met:\n–\nEONUM (in OTG_FS_DOEPCTLx) = SOFFN[0] (in OTG_FS_DSTS)\n3. \nWhen the application completely reads an isochronous OUT data packet (data and \nstatus) from the receive FIFO, the core updates the RXDPID field in \nOTG_FS_DOEPTSIZx with the data PID of the last isochronous OUT data packet read \nfrom the receive FIFO.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1366/1757\nRM0090 Rev 21\nApplication programming sequence\n1.\nProgram the OTG_FS_DOEPTSIZx register for the transfer size and the corresponding \npacket count\n2. \nProgram the OTG_FS_DOEPCTLx register with the endpoint characteristics and set \nthe Endpoint Enable, ClearNAK, and Even/Odd frame bits.\n–\nEPENA = 1\n–\nCNAK = 1\n–\nEONUM = (0: Even/1: Odd)\n3. \nWait for the RXFLVL interrupt (in OTG_FS_GINTSTS) and empty the data packets \nfrom the receive FIFO\n–\nThis step can be repeated many times, depending on the transfer size.\n4. \nThe assertion of the XFRC interrupt (in OTG_FS_DOEPINTx) marks the completion of \nthe isochronous OUT data transfer. This interrupt does not necessarily mean that the \ndata in memory are good.\n5. \nThis interrupt cannot always be detected for isochronous OUT transfers. Instead, the \napplication can detect the IISOOXFRM interrupt in OTG_FS_GINTSTS.\n6. \nRead the OTG_FS_DOEPTSIZx register to determine the size of the received transfer \nand to determine the validity of the data received in the frame. The application must \ntreat the data received in memory as valid only if one of the following conditions is met:\n–\nRXDPID = D0 (in OTG_FS_DOEPTSIZx) and the number of USB packets in \nwhich this payload was received = 1\n–\nRXDPID = D1 (in OTG_FS_DOEPTSIZx) and the number of USB packets in \nwhich this payload was received = 2\n–\nRXDPID = D2 (in OTG_FS_DOEPTSIZx) and the number of USB packets in \nwhich this payload was received = 3\nThe number of USB packets in which this payload was received =\nApplication programmed initial packet count – Core updated final packet count\nThe application can discard invalid data packets.\n•\nIncomplete isochronous OUT data transfers\nThis section describes the application programming sequence when isochronous OUT data \npackets are dropped inside the core.\nInternal data flow\n1.\nFor isochronous OUT endpoints, the XFRC interrupt (in OTG_FS_DOEPINTx) may not \nalways be asserted. If the core drops isochronous OUT data packets, the application \ncould fail to detect the XFRC interrupt (OTG_FS_DOEPINTx) under the following \ncircumstances:\n–\nWhen the receive FIFO cannot accommodate the complete ISO OUT data packet, \nthe core drops the received ISO OUT data\n–\nWhen the isochronous OUT data packet is received with CRC errors\n–\nWhen the isochronous OUT token received by the core is corrupted\n–\nWhen the application is very slow in reading the data from the receive FIFO\n2. \nWhen the core detects an end of periodic frame before transfer completion to all \nisochronous OUT endpoints, it asserts the incomplete Isochronous OUT data interrupt \n(IISOOXFRM in OTG_FS_GINTSTS), indicating that an XFRC interrupt (in \nOTG_FS_DOEPINTx) is not asserted on at least one of the isochronous OUT \n\n\n<>\n\nRM0090 Rev 21\n1367/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nendpoints. At this point, the endpoint with the incomplete transfer remains enabled, but \nno active transfers remain in progress on this endpoint on the USB.\nApplication programming sequence\n1.\nAsserting the IISOOXFRM interrupt (OTG_FS_GINTSTS) indicates that in the current \nframe, at least one isochronous OUT endpoint has an incomplete transfer.\n2. \nIf this occurs because isochronous OUT data is not completely emptied from the \nendpoint, the application must ensure that the application empties all isochronous OUT \ndata (data and status) from the receive FIFO before proceeding.\n–\nWhen all data are emptied from the receive FIFO, the application can detect the \nXFRC interrupt (OTG_FS_DOEPINTx). In this case, the application must re-\nenable the endpoint to receive isochronous OUT data in the next frame.\n3. \nWhen it receives an IISOOXFRM interrupt (in OTG_FS_GINTSTS), the application \nmust read the control registers of all isochronous OUT endpoints \n(OTG_FS_DOEPCTLx) to determine which endpoints had an incomplete transfer in the \ncurrent microframe. An endpoint transfer is incomplete if both the following conditions \nare met:\n–\nEONUM bit (in OTG_FS_DOEPCTLx) = SOFFN[0] (in OTG_FS_DSTS)\n–\nEPENA = 1 (in OTG_FS_DOEPCTLx)\n4. \nThe previous step must be performed before the SOF interrupt (in OTG_FS_GINTSTS) \nis detected, to ensure that the current frame number is not changed.\n5. \nFor isochronous OUT endpoints with incomplete transfers, the application must discard \nthe data in the memory and disable the endpoint by setting the EPDIS bit in \nOTG_FS_DOEPCTLx.\n6. \nWait for the EPDIS interrupt (in OTG_FS_DOEPINTx) and enable the endpoint to \nreceive new data in the next frame.\n–\nBecause the core can take some time to disable the endpoint, the application may \nnot be able to receive the data in the next frame after receiving bad isochronous \ndata.\n•\nStalling a non-isochronous OUT endpoint\nThis section describes how the application can stall a non-isochronous endpoint.\n1.\nPut the core in the Global OUT NAK mode.\n2. \nDisable the required endpoint\n–\nWhen disabling the endpoint, instead of setting the SNAK bit in \nOTG_FS_DOEPCTL, set STALL = 1 (in OTG_FS_DOEPCTL).\nThe STALL bit always takes precedence over the NAK bit.\n3. \nWhen the application is ready to end the STALL handshake for the endpoint, the \nSTALL bit (in OTG_FS_DOEPCTLx) must be cleared.\n4. \nIf the application is setting or clearing a STALL for an endpoint due to a \nSetFeature.Endpoint Halt or ClearFeature.Endpoint Halt command, the STALL bit must \nbe set or cleared before the application sets up the Status stage transfer on the control \nendpoint.\nExamples\nThis section describes and depicts some fundamental transfer types and scenarios.\n•\nBulk OUT transaction\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1368/1757\nRM0090 Rev 21\nFigure 404 depicts the reception of a single Bulk OUT Data packet from the USB to the AHB \nand describes the events involved in the process.\nFigure 404. Bulk OUT transaction\nAfter a SetConfiguration/SetInterface command, the application initializes all OUT endpoints \nby setting CNAK = 1 and EPENA = 1 (in OTG_FS_DOEPCTLx), and setting a suitable \nXFRSIZ and PKTCNT in the OTG_FS_DOEPTSIZx register.\n1.\nhost attempts to send data (OUT token) to an endpoint.\n2. \nWhen the core receives the OUT token on the USB, it stores the packet in the RxFIFO \nbecause space is available there.\n3. \nAfter writing the complete packet in the RxFIFO, the core then asserts the RXFLVL \ninterrupt (in OTG_FS_GINTSTS).\n4. \nOn receiving the PKTCNT number of USB packets, the core internally sets the NAK bit \nfor this endpoint to prevent it from receiving any more packets.\n5. \nThe application processes the interrupt and reads the data from the RxFIFO.\n6. \nWhen the application has read all the data (equivalent to XFRSIZ), the core generates \nan XFRC interrupt (in OTG_FS_DOEPINTx).\n7. \nThe application processes the interrupt and uses the setting of the XFRC interrupt bit \n(in OTG_FS_DOEPINTx) to determine that the intended transfer is complete.\nIN data transfers\n•\nPacket write\nThis section describes how the application writes data packets to the endpoint FIFO when \ndedicated transmit FIFOs are enabled.\n1.\nThe application can either choose the polling or the interrupt mode.\ninit_out_ep\n Host\nDevice\nUSB\nOUT\nACK\nRXFLVL intr\n i\nwr_reg (DOEPTSIZx)\nwr_reg(DOEPCTLx)\n64 bytes\nOUT\nNAK\nxact_1\nApplication\nXFRC \nintr\nDOEPCTLx.NAK=1\nPKTCNT 0\nXFRSIZ = 0\nr\n \n \nidle until intr\nrcv_out_pkt()\nidle until intr\nOn new xfer\nor RxFIFO\nnot empty\n1\n2\n3\n4\n5\n6\n7\n8\nXFRSIZ = 64 bytes\nPKTCNT = 1\nEPENA = 1\nCNAK = 1\nai15679b\n\n\n<>\n\nRM0090 Rev 21\n1369/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n–\nIn polling mode, the application monitors the status of the endpoint transmit data \nFIFO by reading the OTG_FS_DTXFSTSx register, to determine if there is enough \nspace in the data FIFO.\n–\nIn interrupt mode, the application waits for the TXFE interrupt (in \nOTG_FS_DIEPINTx) and then reads the OTG_FS_DTXFSTSx register, to \ndetermine if there is enough space in the data FIFO.\n–\nTo write a single non-zero length data packet, there must be space to write the \nentire packet in the data FIFO.\n–\nTo write zero length packet, the application must not look at the FIFO space.\n2. \nUsing one of the above mentioned methods, when the application determines that \nthere is enough space to write a transmit packet, the application must first write into the \nendpoint control register, before writing the data into the data FIFO. Typically, the \napplication, must do a read modify write on the OTG_FS_DIEPCTLx register to avoid \nmodifying the contents of the register, except for setting the Endpoint Enable bit.\nThe application can write multiple packets for the same endpoint into the transmit FIFO, if \nspace is available. For periodic IN endpoints, the application must write packets only for one \nmicroframe. It can write packets for the next periodic transaction only after getting transfer \ncomplete for the previous transaction.\n•\nSetting IN endpoint NAK\nInternal data flow\n1.\nWhen the application sets the IN NAK for a particular endpoint, the core stops \ntransmitting data on the endpoint, irrespective of data availability in the endpoint’s \ntransmit FIFO.\n2. \nNon-isochronous IN tokens receive a NAK handshake reply\n–\nIsochronous IN tokens receive a zero-data-length packet reply\n3. \nThe core asserts the INEPNE (IN endpoint NAK effective) interrupt in \nOTG_FS_DIEPINTx in response to the SNAK bit in OTG_FS_DIEPCTLx.\n4. \nOnce this interrupt is seen by the application, the application can assume that the \nendpoint is in IN NAK mode. This interrupt can be cleared by the application by setting \nthe CNAK bit in OTG_FS_DIEPCTLx.\nApplication programming sequence\n1.\nTo stop transmitting any data on a particular IN endpoint, the application must set the \nIN NAK bit. To set this bit, the following field must be programmed.\n–\nSNAK = 1 in OTG_FS_DIEPCTLx\n2. \nWait for assertion of the INEPNE interrupt in OTG_FS_DIEPINTx. This interrupt \nindicates that the core has stopped transmitting data on the endpoint.\n3. \nThe core can transmit valid IN data on the endpoint after the application has set the \nNAK bit, but before the assertion of the NAK Effective interrupt.\n4. \nThe application can mask this interrupt temporarily by writing to the INEPNEM bit in \nDIEPMSK.\n–\nINEPNEM = 0 in DIEPMSK\n5. \nTo exit Endpoint NAK mode, the application must clear the NAK status bit (NAKSTS) in \nOTG_FS_DIEPCTLx. This also clears the INEPNE interrupt (in OTG_FS_DIEPINTx).\n–\nCNAK = 1 in OTG_FS_DIEPCTLx\n6. \nIf the application masked this interrupt earlier, it must be unmasked as follows:\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1370/1757\nRM0090 Rev 21\n–\nINEPNEM = 1 in DIEPMSK\n•\nIN endpoint disable\nUse the following sequence to disable a specific IN endpoint that has been previously \nenabled.\nApplication programming sequence\n1.\nThe application must stop writing data on the AHB for the IN endpoint to be disabled.\n2. \nThe application must set the endpoint in NAK mode. \n–\nSNAK = 1 in OTG_FS_DIEPCTLx\n3. \nWait for the INEPNE interrupt in OTG_FS_DIEPINTx.\n4. \nSet the following bits in the OTG_FS_DIEPCTLx register for the endpoint that must be \ndisabled.\n–\nEPDIS = 1 in OTG_FS_DIEPCTLx\n–\nSNAK = 1 in OTG_FS_DIEPCTLx\n5. \nAssertion of the EPDISD interrupt in OTG_FS_DIEPINTx indicates that the core has \ncompletely disabled the specified endpoint. Along with the assertion of the interrupt, the \ncore also clears the following bits:\n–\nEPENA = 0 in OTG_FS_DIEPCTLx\n–\nEPDIS = 0 in OTG_FS_DIEPCTLx\n6. \nThe application must read the OTG_FS_DIEPTSIZx register for the periodic IN EP, to \ncalculate how much data on the endpoint were transmitted on the USB.\n7. \nThe application must flush the data in the Endpoint transmit FIFO, by setting the \nfollowing fields in the OTG_FS_GRSTCTL register:\n–\nTXFNUM (in OTG_FS_GRSTCTL) = Endpoint transmit FIFO number\n–\nTXFFLSH in (OTG_FS_GRSTCTL) = 1\nThe application must poll the OTG_FS_GRSTCTL register, until the TXFFLSH bit is cleared \nby the core, which indicates the end of flush operation. To transmit new data on this \nendpoint, the application can re-enable the endpoint at a later point.\n•\nTransfer Stop Programming for IN endpoints\nThe application must use the following programing sequence to stop any transfers (because \nof an interrupt from the host, typically a reset).\n\n\n<>\n\nRM0090 Rev 21\n1371/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nSequence of operations:\n1.\nDisable the IN endpoint by setting:\n–\nEPDIS = 1 in all OTG_FS_DIEPCTLx registers\n2. \nWait for the EPDIS interrupt in OTG_FS_DIEPINTx, which indicates that the IN \nendpoint is completely disabled. When the EPDIS interrupt is asserted the following \nbits are cleared:\n–\nEPDIS = 0 in OTG_FS_DIEPCTLx\n–\nEPENA = 0 in OTG_FS_DIEPCTLx\n3. \nFlush the TxFIFO by programming the following bits:\n–\nTXFFLSH = 1 in OTG_FS_GRSTCTL\n–\nTXFNUM = “FIFO number specific to endpoint” in OTG_FS_GRSTCTL\n4. \nThe application can start polling till TXFFLSH in OTG_FS_GRSTCTL is cleared. When \nthis bit is cleared, it ensures that there is no data left in the Tx FIFO.\n•\nGeneric non-periodic IN data transfers\nApplication requirements\n1.\nBefore setting up an IN transfer, the application must ensure that all data to be \ntransmitted as part of the IN transfer are part of a single buffer.\n2. \nFor IN transfers, the Transfer Size field in the Endpoint Transfer Size register denotes a \npayload that constitutes multiple maximum-packet-size packets and a single short \npacket. This short packet is transmitted at the end of the transfer.\n–\nTo transmit a few maximum-packet-size packets and a short packet at the end of \nthe transfer:\nTransfer size[EPNUM] = x × MPSIZ[EPNUM] + sp\nIf (sp > 0), then packet count[EPNUM] = x + 1. \nOtherwise, packet count[EPNUM] = x\n–\nTo transmit a single zero-length data packet:\nTransfer size[EPNUM] = 0\nPacket count[EPNUM] = 1\n–\nTo transmit a few maximum-packet-size packets and a zero-length data packet at \nthe end of the transfer, the application must split the transfer into two parts. The \nfirst sends maximum-packet-size data packets and the second sends the zero-\nlength data packet alone.\nFirst transfer: transfer size[EPNUM] = x × MPSIZ[epnum]; packet count = n;\nSecond transfer: transfer size[EPNUM] = 0; packet count = 1;\n3. \nOnce an endpoint is enabled for data transfers, the core updates the Transfer size \nregister. At the end of the IN transfer, the application must read the Transfer size \nregister to determine how much data posted in the transmit FIFO have already been \nsent on the USB.\n4. \nData fetched into transmit FIFO = Application-programmed initial transfer size – core-\nupdated final transfer size\n–\nData transmitted on USB = (application-programmed initial packet count – Core \nupdated final packet count) × MPSIZ[EPNUM]\n–\nData yet to be transmitted on USB = (Application-programmed initial transfer size \n– data transmitted on USB)\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1372/1757\nRM0090 Rev 21\nInternal data flow\n1.\nThe application must set the transfer size and packet count fields in the endpoint-\nspecific registers and enable the endpoint to transmit the data.\n2. \nThe application must also write the required data to the transmit FIFO for the endpoint.\n3. \nEvery time a packet is written into the transmit FIFO by the application, the transfer size \nfor that endpoint is decremented by the packet size. The data is fetched from the \nmemory by the application, until the transfer size for the endpoint becomes 0. After \nwriting the data into the FIFO, the “number of packets in FIFO” count is incremented \n(this is a 3-bit count, internally maintained by the core for each IN endpoint transmit \nFIFO. The maximum number of packets maintained by the core at any time in an IN \nendpoint FIFO is eight). For zero-length packets, a separate flag is set for each FIFO, \nwithout any data in the FIFO.\n4. \nOnce the data are written to the transmit FIFO, the core reads them out upon receiving \nan IN token. For every non-isochronous IN data packet transmitted with an ACK \nhandshake, the packet count for the endpoint is decremented by one, until the packet \ncount is zero. The packet count is not decremented on a timeout.\n5. \nFor zero length packets (indicated by an internal zero length flag), the core sends out a \nzero-length packet for the IN token and decrements the packet count field.\n6. \nIf there are no data in the FIFO for a received IN token and the packet count field for \nthat endpoint is zero, the core generates an “IN token received when TxFIFO is empty” \n(ITTXFE) Interrupt for the endpoint, provided that the endpoint NAK bit is not set. The \ncore responds with a NAK handshake for non-isochronous endpoints on the USB.\n7. \nThe core internally rewinds the FIFO pointers and no timeout interrupt is generated.\n8. \nWhen the transfer size is 0 and the packet count is 0, the transfer complete (XFRC) \ninterrupt for the endpoint is generated and the endpoint enable is cleared.\nApplication programming sequence\n1.\nProgram the OTG_FS_DIEPTSIZx register with the transfer size and corresponding \npacket count.\n2. \nProgram the OTG_FS_DIEPCTLx register with the endpoint characteristics and set the \nCNAK and EPENA (Endpoint Enable) bits.\n3. \nWhen transmitting non-zero length data packet, the application must poll the \nOTG_FS_DTXFSTSx register (where x is the FIFO number associated with that \nendpoint) to determine whether there is enough space in the data FIFO. The \napplication can optionally use TXFE (in OTG_FS_DIEPINTx) before writing the data.\n•\nGeneric periodic IN data transfers\nThis section describes a typical periodic IN data transfer.\nApplication requirements\n1.\nApplication requirements 1, 2, 3, and 4 of Generic non-periodic IN data transfers also \napply to periodic IN data transfers, except for a slight modification of requirement 2.\n–\nThe application can only transmit multiples of maximum-packet-size data packets \nor multiples of maximum-packet-size packets, plus a short packet at the end. To \ntransmit a few maximum-packet-size packets and a short packet at the end of the \ntransfer, the following conditions must be met:\ntransfer size[EPNUM] = x × MPSIZ[EPNUM] + sp\n(where x is an integer ≥ 0, and 0 ≤ sp < MPSIZ[EPNUM])\nIf (sp > 0), packet count[EPNUM] = x + 1\nOtherwise, packet count[EPNUM] = x;\n\n\n<>\n\nRM0090 Rev 21\n1373/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nMCNT[EPNUM] = packet count[EPNUM]\n–\nThe application cannot transmit a zero-length data packet at the end of a transfer. \nIt can transmit a single zero-length data packet by itself. To transmit a single zero-\nlength data packet:\n–\ntransfer size[EPNUM] = 0\npacket count[EPNUM] = 1\nMCNT[EPNUM] = packet count[EPNUM]\n2. \nThe application can only schedule data transfers one frame at a time.\n–\n(MCNT – 1) × MPSIZ ≤XFERSIZ ≤MCNT × MPSIZ\n–\nPKTCNT = MCNT (in OTG_FS_DIEPTSIZx)\n–\nIf XFERSIZ < MCNT × MPSIZ, the last data packet of the transfer is a short \npacket.\n–\nNote that: MCNT is in OTG_FS_DIEPTSIZx, MPSIZ is in OTG_FS_DIEPCTLx, \nPKTCNT is in OTG_FS_DIEPTSIZx and XFERSIZ is in OTG_FS_DIEPTSIZx\n3. \nThe complete data to be transmitted in the frame must be written into the transmit FIFO \nby the application, before the IN token is received. Even when 1 word of the data to be \ntransmitted per frame is missing in the transmit FIFO when the IN token is received, the \ncore behaves as when the FIFO is empty. When the transmit FIFO is empty:\n–\nA zero data length packet would be transmitted on the USB for isochronous IN \nendpoints\n–\nA NAK handshake would be transmitted on the USB for interrupt IN endpoints\nInternal data flow\n1.\nThe application must set the transfer size and packet count fields in the endpoint-\nspecific registers and enable the endpoint to transmit the data.\n2. \nThe application must also write the required data to the associated transmit FIFO for \nthe endpoint.\n3. \nEvery time the application writes a packet to the transmit FIFO, the transfer size for that \nendpoint is decremented by the packet size. The data are fetched from application \nmemory until the transfer size for the endpoint becomes 0.\n4. \nWhen an IN token is received for a periodic endpoint, the core transmits the data in the \nFIFO, if available. If the complete data payload (complete packet, in dedicated FIFO \nmode) for the frame is not present in the FIFO, then the core generates an IN token \nreceived when TxFIFO empty interrupt for the endpoint.\n–\nA zero-length data packet is transmitted on the USB for isochronous IN endpoints\n–\nA NAK handshake is transmitted on the USB for interrupt IN endpoints\n5. \nThe packet count for the endpoint is decremented by 1 under the following conditions:\n–\nFor isochronous endpoints, when a zero- or non-zero-length data packet is \ntransmitted\n–\nFor interrupt endpoints, when an ACK handshake is transmitted\n–\nWhen the transfer size and packet count are both 0, the transfer completed \ninterrupt for the endpoint is generated and the endpoint enable is cleared.\n6. \nAt the “Periodic frame Interval” (controlled by PFIVL in OTG_FS_DCFG), when the \ncore finds non-empty any of the isochronous IN endpoint FIFOs scheduled for the \ncurrent frame non-empty, the core generates an IISOIXFR interrupt in \nOTG_FS_GINTSTS.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1374/1757\nRM0090 Rev 21\nApplication programming sequence\n1.\nProgram the OTG_FS_DIEPCTLx register with the endpoint characteristics and set the \nCNAK and EPENA bits.\n2. \nWrite the data to be transmitted in the next frame to the transmit FIFO.\n3. \nAsserting the ITTXFE interrupt (in OTG_FS_DIEPINTx) indicates that the application \nhas not yet written all data to be transmitted to the transmit FIFO.\n4. \nIf the interrupt endpoint is already enabled when this interrupt is detected, ignore the \ninterrupt. If it is not enabled, enable the endpoint so that the data can be transmitted on \nthe next IN token attempt.\n5. \nAsserting the XFRC interrupt (in OTG_FS_DIEPINTx) with no ITTXFE interrupt in \nOTG_FS_DIEPINTx indicates the successful completion of an isochronous IN transfer. \nA read to the OTG_FS_DIEPTSIZx register must give transfer size = 0 and packet \ncount = 0, indicating all data were transmitted on the USB.\n6. \nAsserting the XFRC interrupt (in OTG_FS_DIEPINTx), with or without the ITTXFE \ninterrupt (in OTG_FS_DIEPINTx), indicates the successful completion of an interrupt \nIN transfer. A read to the OTG_FS_DIEPTSIZx register must give transfer size = 0 and \npacket count = 0, indicating all data were transmitted on the USB.\n7. \nAsserting the incomplete isochronous IN transfer (IISOIXFR) interrupt in \nOTG_FS_GINTSTS with none of the aforementioned interrupts indicates the core did \nnot receive at least 1 periodic IN token in the current frame.\n•\nIncomplete isochronous IN data transfers\nThis section describes what the application must do on an incomplete isochronous IN data \ntransfer.\nInternal data flow\n1.\nAn isochronous IN transfer is treated as incomplete in one of the following conditions:\na) \nThe core receives a corrupted isochronous IN token on at least one isochronous \nIN endpoint. In this case, the application detects an incomplete isochronous IN \ntransfer interrupt (IISOIXFR in OTG_FS_GINTSTS).\nb) \nThe application is slow to write the complete data payload to the transmit FIFO \nand an IN token is received before the complete data payload is written to the \nFIFO. In this case, the application detects an IN token received when TxFIFO \nempty interrupt in OTG_FS_DIEPINTx. The application can ignore this interrupt, \nas it eventually results in an incomplete isochronous IN transfer interrupt \n(IISOIXFR in OTG_FS_GINTSTS) at the end of periodic frame.\nThe core transmits a zero-length data packet on the USB in response to the \nreceived IN token.\n2. \nThe application must stop writing the data payload to the transmit FIFO as soon as \npossible.\n3. \nThe application must set the NAK bit and the disable bit for the endpoint.\n4. \nThe core disables the endpoint, clears the disable bit, and asserts the Endpoint Disable \ninterrupt for the endpoint.\nApplication programming sequence\n1.\nThe application can ignore the IN token received when TxFIFO empty interrupt in \nOTG_FS_DIEPINTx on any isochronous IN endpoint, as it eventually results in an \nincomplete isochronous IN transfer interrupt (in OTG_FS_GINTSTS).\n\n\n<>\n\nRM0090 Rev 21\n1375/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n2. \nAssertion of the incomplete isochronous IN transfer interrupt (in OTG_FS_GINTSTS) \nindicates an incomplete isochronous IN transfer on at least one of the isochronous IN \nendpoints.\n3. \nThe application must read the Endpoint Control register for all isochronous IN \nendpoints to detect endpoints with incomplete IN data transfers.\n4. \nThe application must stop writing data to the Periodic Transmit FIFOs associated with \nthese endpoints on the AHB.\n5. \nProgram the following fields in the OTG_FS_DIEPCTLx register to disable the \nendpoint:\n–\nSNAK = 1 in OTG_FS_DIEPCTLx\n–\nEPDIS = 1 in OTG_FS_DIEPCTLx\n6. \nThe assertion of the Endpoint Disabled interrupt in OTG_FS_DIEPINTx indicates that \nthe core has disabled the endpoint.\n–\nAt this point, the application must flush the data in the associated transmit FIFO or \noverwrite the existing data in the FIFO by enabling the endpoint for a new transfer \nin the next microframe. To flush the data, the application must use the \nOTG_FS_GRSTCTL register.\n•\nStalling non-isochronous IN endpoints\nThis section describes how the application can stall a non-isochronous endpoint.\nApplication programming sequence\n1.\nDisable the IN endpoint to be stalled. Set the STALL bit as well.\n2. \nEPDIS = 1 in OTG_FS_DIEPCTLx, when the endpoint is already enabled\n–\nSTALL = 1 in OTG_FS_DIEPCTLx\n–\nThe STALL bit always takes precedence over the NAK bit\n3. \nAssertion of the Endpoint Disabled interrupt (in OTG_FS_DIEPINTx) indicates to the \napplication that the core has disabled the specified endpoint.\n4. \nThe application must flush the non-periodic or periodic transmit FIFO, depending on \nthe endpoint type. In case of a non-periodic endpoint, the application must re-enable \nthe other non-periodic endpoints that do not need to be stalled, to transmit data.\n5. \nWhenever the application is ready to end the STALL handshake for the endpoint, the \nSTALL bit must be cleared in OTG_FS_DIEPCTLx.\n6. \nIf the application sets or clears a STALL bit for an endpoint due to a \nSetFeature.Endpoint Halt command or ClearFeature.Endpoint Halt command, the \nSTALL bit must be set or cleared before the application sets up the Status stage \ntransfer on the control endpoint.\nSpecial case: stalling the control OUT endpoint\nThe core must stall IN/OUT tokens if, during the data stage of a control transfer, the host \nsends more IN/OUT tokens than are specified in the SETUP packet. In this case, the \napplication must enable the ITTXFE interrupt in OTG_FS_DIEPINTx and the OTEPDIS \ninterrupt in OTG_FS_DOEPINTx during the data stage of the control transfer, after the core \nhas transferred the amount of data specified in the SETUP packet. Then, when the \napplication receives this interrupt, it must set the STALL bit in the corresponding endpoint \ncontrol register, and clear this interrupt.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1376/1757\nRM0090 Rev 21\n34.17.7 \nWorst case response time\nWhen the OTG_FS controller acts as a device, there is a worst case response time for any \ntokens that follow an isochronous OUT. This worst case response time depends on the AHB \nclock frequency.\nThe core registers are in the AHB domain, and the core does not accept another token \nbefore updating these register values. The worst case is for any token following an \nisochronous OUT, because for an isochronous transaction, there is no handshake and the \nnext token could come sooner. This worst case value is 7 PHY clocks when the AHB clock \nis the same as the PHY clock. When the AHB clock is faster, this value is smaller.\nIf this worst case condition occurs, the core responds to bulk/interrupt tokens with a NAK \nand drops isochronous and SETUP tokens. The host interprets this as a timeout condition \nfor SETUP and retries the SETUP packet. For isochronous transfers, the Incomplete \nisochronous IN transfer interrupt (IISOIXFR) and Incomplete isochronous OUT transfer \ninterrupt (IISOOXFR) inform the application that isochronous IN/OUT packets were \ndropped.\nChoosing the value of TRDT in OTG_FS_GUSBCFG\nThe value in TRDT (OTG_FS_GUSBCFG) is the time it takes for the MAC, in terms of PHY \nclocks after it has received an IN token, to get the FIFO status, and thus the first data from \nthe PFC block. This time involves the synchronization delay between the PHY and AHB \nclocks. The worst case delay for this is when the AHB clock is the same as the PHY clock. \nIn this case, the delay is 5 clocks.\nOnce the MAC receives an IN token, this information (token received) is synchronized to the \nAHB clock by the PFC (the PFC runs on the AHB clock). The PFC then reads the data from \nthe SPRAM and writes them into the dual clock source buffer. The MAC then reads the data \nout of the source buffer (4 deep).\nIf the AHB is running at a higher frequency than the PHY, the application can use a smaller \nvalue for TRDT (in OTG_FS_GUSBCFG).\nFigure 405 has the following signals:\n•\ntkn_rcvd: Token received information from MAC to PFC\n•\ndynced_tkn_rcvd: Doubled sync tkn_rcvd, from PCLK to HCLK domain\n•\nspr_read: Read to SPRAM\n•\nspr_addr: Address to SPRAM\n•\nspr_rdata: Read data from SPRAM\n•\nsrcbuf_push: Push to the source buffer\n•\nsrcbuf_rdata: Read data from the source buffer. Data seen by MAC\nRefer to Table 204: TRDT values for the values of TRDT versus AHB clock frequency. \n\n\n<>\n\nRM0090 Rev 21\n1377/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nFigure 405. TRDT max timing case \n34.17.8 \nOTG programming model\nThe OTG_FS controller is an OTG device supporting HNP and SRP. When the core is \nconnected to an “A” plug, it is referred to as an A-device. When the core is connected to a \n“B” plug it is referred to as a B-device. In host mode, the OTG_FS controller turns off VBUS \nto conserve power. SRP is a method by which the B-device signals the A-device to turn on \nVBUS power. A device must perform both data-line pulsing and VBUS pulsing, but a host can \ndetect either data-line pulsing or VBUS pulsing for SRP. HNP is a method by which the B-\ndevice negotiates and switches to host role. In Negotiated mode after HNP, the B-device \nsuspends the bus and reverts to the device role.\n1\n2\n3\n4\n5\n6\n7\n8\n0ns\n50ns\n100ns\n150ns\n200ns\nHCLK\nPCLK\ntkn_rcvd\ndsynced_tkn_rcvd\nspr_read\nspr_addr\nspr_rdata\nsrcbuf_push\nsrcbuf_rdata\n5 Clocks\nD1\nA1\nD1\nai15680\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1378/1757\nRM0090 Rev 21\nA-device session request protocol\nThe application must set the SRP-capable bit in the Core USB configuration register. This \nenables the OTG_FS controller to detect SRP as an A-device.\nFigure 406. A-device SRP\n1.\nDRV_VBUS = VBUS drive signal to the PHY\nVBUS_VALID = VBUS valid signal from PHY\nA_VALID = A-peripheral VBUS level signal to PHY\nD+ = Data plus line\nD- = Data minus line\n1.\nTo save power, the application suspends and turns off port power when the bus is idle \nby writing the port suspend and port power bits in the host port control and status \nregister.\n2. \nPHY indicates port power off by deasserting the VBUS_VALID signal.\n3. \nThe device must detect SE0 for at least 2 ms to start SRP when VBUS power is off.\n4. \nTo initiate SRP, the device turns on its data line pull-up resistor for 5 to 10 ms. The \nOTG_FS controller detects data-line pulsing.\n5. \nThe device drives VBUS above the A-device session valid (2.0 V minimum) for VBUS \npulsing.\nThe OTG_FS controller interrupts the application on detecting SRP. The Session \nrequest detected bit is set in Global interrupt status register (SRQINT set in \nOTG_FS_GINTSTS).\n6. \nThe application must service the Session request detected interrupt and turn on the \nport power bit by writing the port power bit in the host port control and status register. \nThe PHY indicates port power-on by asserting the VBUS_VALID signal.\n7. \nWhen the USB is powered, the device connects, completing the SRP process.\nai15681\nDRV_VBUS\nVBUS_VALID\nA_VALID\nD+\nD-\nSuspend\nVBUS pulsing\nData line pulsing\nConnect\n1\n6\n2\n5\n3\n4\n7\nLow\n\n\n<>\n\nRM0090 Rev 21\n1379/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nB-device session request protocol\nThe application must set the SRP-capable bit in the Core USB configuration register. This \nenables the OTG_FS controller to initiate SRP as a B-device. SRP is a means by which the \nOTG_FS controller can request a new session from the host.\nFigure 407. B-device SRP\n1.\nVBUS_VALID = VBUS valid signal from PHY\nB_VALID = B-peripheral valid session to PHY\nDISCHRG_VBUS = discharge signal to PHY\nSESS_END = session end signal to PHY\nCHRG_VBUS = charge VBUS signal to PHY\nDP = Data plus line\nDM = Data minus line\n1.\nTo save power, the host suspends and turns off port power when the bus is idle.\nThe OTG_FS controller sets the early suspend bit in the Core interrupt register after 3 \nms of bus idleness. Following this, the OTG_FS controller sets the USB suspend bit in \nthe Core interrupt register.\nThe OTG_FS controller informs the PHY to discharge VBUS.\n2. \nThe PHY indicates the session’s end to the device. This is the initial condition for SRP. \nThe OTG_FS controller requires 2 ms of SE0 before initiating SRP.\nFor a USB 1.1 full-speed serial transceiver, the application must wait until VBUS \ndischarges to 0.2 V after BSVLD (in OTG_FS_GOTGCTL) is deasserted. This \ndischarge time can be obtained from the transceiver vendor and varies from one \ntransceiver to another.\n3. \nThe USB OTG core informs the PHY to speed up VBUS discharge.\n4. \nThe application initiates SRP by writing the session request bit in the OTG Control and \nstatus register. The OTG_FS controller perform data-line pulsing followed by VBUS \npulsing.\n5. \nThe host detects SRP from either the data-line or VBUS pulsing, and turns on VBUS. \nThe PHY indicates VBUS power-on to the device.\nai15682\nVBUS_VALID\nB_VALID\nDISCHRG_VBUS\nSESS_END\nDP\nDM\nCHRG_VBUS\nSuspend\nData line pulsing\nConnect\nVBUS pulsing\n1\n6\n2\n3\n4\n5\n8\n7\nLow\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1380/1757\nRM0090 Rev 21\n6. \nThe OTG_FS controller performs VBUS pulsing.\nThe host starts a new session by turning on VBUS, indicating SRP success. The \nOTG_FS controller interrupts the application by setting the session request success \nstatus change bit in the OTG interrupt status register. The application reads the session \nrequest success bit in the OTG control and status register.\n7. \nWhen the USB is powered, the OTG_FS controller connects, completing the SRP \nprocess.\nA-device host negotiation protocol\nHNP switches the USB host role from the A-device to the B-device. The application must set \nthe HNP-capable bit in the Core USB configuration register to enable the OTG_FS \ncontroller to perform HNP as an A-device.\nFigure 408. A-device HNP\n1.\nDPPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DP line inside the PHY.\nDMPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DM line inside the PHY.\n1.\nThe OTG_FS controller sends the B-device a SetFeature b_hnp_enable descriptor to \nenable HNP support. The B-device’s ACK response indicates that the B-device \nsupports HNP. The application must set host Set HNP Enable bit in the OTG Control \nai15683\nOTG core\nDP\nDM\nDPPULLDOWN\nDMPULLDOWN\nHost\nDevice\nHost\n1\nSuspend 2\n3\n4\n5\nReset\n6\nTraffic\n7\n8\nConnect\nTraffic\n\n\n<>\n\nRM0090 Rev 21\n1381/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nand status register to indicate to the OTG_FS controller that the B-device supports \nHNP.\n2. \nWhen it has finished using the bus, the application suspends by writing the Port \nsuspend bit in the host port control and status register.\n3. \nWhen the B-device observes a USB suspend, it disconnects, indicating the initial \ncondition for HNP. The B-device initiates HNP only when it must switch to the host role; \notherwise, the bus continues to be suspended.\nThe OTG_FS controller sets the host negotiation detected interrupt in the OTG \ninterrupt status register, indicating the start of HNP.\nThe OTG_FS controller deasserts the DM pull down and DM pull down in the PHY to \nindicate a device role. The PHY enables the OTG_FS_DP pull-up resistor to indicate a \nconnect for B-device.\nThe application must read the current mode bit in the OTG Control and status register \nto determine device mode operation.\n4. \nThe B-device detects the connection, issues a USB reset, and enumerates the \nOTG_FS controller for data traffic.\n5. \nThe B-device continues the host role, initiating traffic, and suspends the bus when \ndone.\nThe OTG_FS controller sets the early suspend bit in the Core interrupt register after 3 \nms of bus idleness. Following this, the OTG_FS controller sets the USB Suspend bit in \nthe Core interrupt register.\n6. \nIn Negotiated mode, the OTG_FS controller detects the suspend, disconnects, and \nswitches back to the host role. The OTG_FS controller asserts the DM pull down and \nDM pull down in the PHY to indicate its assumption of the host role.\n7. \nThe OTG_FS controller sets the Connector ID status change interrupt in the OTG \nInterrupt Status register. The application must read the connector ID status in the OTG \nControl and Status register to determine the OTG_FS controller operation as an A-\ndevice. This indicates the completion of HNP to the application. The application must \nread the Current mode bit in the OTG control and status register to determine host \nmode operation.\n8. \nThe B-device connects, completing the HNP process.\n\n\n<>\n\nUSB on-the-go full-speed (OTG_FS)\nRM0090\n1382/1757\nRM0090 Rev 21\nB-device host negotiation protocol\nHNP switches the USB host role from B-device to A-device. The application must set the \nHNP-capable bit in the Core USB configuration register to enable the OTG_FS controller to \nperform HNP as a B-device.\nFigure 409. B-device HNP\n1.\nDPPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DP line inside the PHY.\nDMPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DM line inside the PHY.\n1.\nThe A-device sends the SetFeature b_hnp_enable descriptor to enable HNP support. \nThe OTG_FS controller’s ACK response indicates that it supports HNP. The application \nmust set the device HNP enable bit in the OTG Control and status register to indicate \nHNP support.\nThe application sets the HNP request bit in the OTG Control and status register to \nindicate to the OTG_FS controller to initiate HNP.\n2. \nWhen it has finished using the bus, the A-device suspends by writing the Port suspend \nbit in the host port control and status register.\nThe OTG_FS controller sets the Early suspend bit in the Core interrupt register after 3 \nms of bus idleness. Following this, the OTG_FS controller sets the USB suspend bit in \nthe Core interrupt register.\nThe OTG_FS controller disconnects and the A-device detects SE0 on the bus, \nindicating HNP. The OTG_FS controller asserts the DP pull down and DM pull down in \nthe PHY to indicate its assumption of the host role.\nThe A-device responds by activating its OTG_FS_DP pull-up resistor within 3 ms of \ndetecting SE0. The OTG_FS controller detects this as a connect.\nThe OTG_FS controller sets the host negotiation success status change interrupt in the \nOTG Interrupt status register, indicating the HNP status. The application must read the \nhost negotiation success bit in the OTG Control and status register to determine host \nnegotiation success. The application must read the current Mode bit in the Core \ninterrupt register (OTG_FS_GINTSTS) to determine host mode operation.\n3. \nThe application sets the reset bit (PRST in OTG_FS_HPRT) and the OTG_FS \ncontroller issues a USB reset and enumerates the A-device for data traffic.\nai15684\nOTG core\nDP\nDM\nDPPULLDOWN\nDMPULLDOWN\nHost\nDevice\nDevice\n1\nSuspend 2\n3\n4\n5\nReset\n6\nTraffic\n7\n8\nConnect\nTraffic\n\n\n<>\n\nRM0090 Rev 21\n1383/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n4. \nThe OTG_FS controller continues the host role of initiating traffic, and when done, \nsuspends the bus by writing the Port suspend bit in the host port control and status \nregister.\n5. \nIn Negotiated mode, when the A-device detects a suspend, it disconnects and switches \nback to the host role. The OTG_FS controller deasserts the DP pull down and DM pull \ndown in the PHY to indicate the assumption of the device role.\n6. \nThe application must read the current mode bit in the Core interrupt \n(OTG_FS_GINTSTS) register to determine the host mode operation.\n7. \nThe OTG_FS controller connects, completing the HNP process.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1384/1757\nRM0090 Rev 21\n35 \nUSB on-the-go high-speed (OTG_HS)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n35.1 \nOTG_HS introduction\nPortions Copyright (c) 2004, 2005 Synopsys, Inc. All rights reserved. Used with permission.\nThis section presents the architecture and the programming model of the OTG_HS \ncontroller.\nThe following acronyms are used throughout the section:\nReferences are made to the following documents:\n•\nUSB On-The-Go Supplement, Revision 1.3\n•\nUniversal Serial Bus Revision 2.0 Specification\nThe OTG_HS is a dual-role device (DRD) controller that supports both peripheral and host \nfunctions and is fully compliant with the On-The-Go Supplement to the USB 2.0 \nSpecification. It can also be configured as a host-only or peripheral-only controller, fully \ncompliant with the USB 2.0 Specification. In host mode, the OTG_HS supports high-speed \n(HS, 480 Mbits/s), full-speed (FS, 12 Mbits/s) and low-speed (LS, 1.5 Mbits/s) transfers \nwhereas in peripheral mode, it only supports high-speed (HS, 480Mbits/s) and full-speed \n(FS, 12 Mbits/s) transfers. The OTG_HS supports both HNP and SRP. The only external \ndevice required is a charge pump for VBUS in OTG mode.\n35.2 \nOTG_HS main features\nThe main features can be divided into three categories: general, host-mode and peripheral-\nmode features.\nFS\nfull-speed\nHS\nHigh-speed\nLS\nLow-speed\nUSB\nUniversal serial bus\nOTG\nOn-the-go\nPHY\nPhysical layer\nMAC\n Media access controller\nPFC\n Packet FIFO controller\nUTMI\nUSB Transceiver Macrocell Interface\nULPI\nUTMI+ Low Pin Interface\n\n\n<>\n\nRM0090 Rev 21\n1385/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n35.2.1 \nGeneral features\nThe OTG_HS interface main features are the following:\n•\nIt is USB-IF certified in compliance with the Universal Serial Bus Revision 2.0 \nSpecification\n•\nIt supports 3 PHY interfaces\n–\nAn on-chip full-speed PHY\n–\nAn ULPI interface for external high-speed PHY.\n•\nIt supports the host negotiation protocol (HNP) and the session request protocol (SRP) \n•\nIt allows the host to turn VBUS off to save power in OTG applications, with no need for \nexternal components\n•\nIt allows to monitor VBUS levels using internal comparators\n•\nIt supports dynamic host-peripheral role switching\n•\nIt is software-configurable to operate as:\n–\nAn SRP-capable USB HS/FS peripheral (B-device)\n–\nAn SRP-capable USB HS/FS/low-speed host (A-device) \n–\nAn USB OTG FS dual-role device\n•\nIt supports HS/FS SOFs as well as low-speed (LS) keep-alive tokens with:\n–\nSOF pulse PAD output capability\n–\nSOF pulse internal connection to timer 2 (TIM2)\n–\nConfigurable framing period\n–\nConfigurable end-of-frame interrupt\n•\nIt embeds an internal DMA with shareholding support and software selectable AHB \nburst type in DMA mode\n•\nIt has power saving features such as system clock stop during USB suspend, switching \noff of the digital core internal clock domains, PHY and DFIFO power management\n•\nIt features a dedicated 4-Kbyte data RAM with advanced FIFO management:\n–\nThe memory partition can be configured into different FIFOs to allow flexible and \nefficient use of RAM\n–\nEach FIFO can contain multiple packets\n–\nMemory allocation is performed dynamically\n–\nThe FIFO size can be configured to values that are not powers of 2 to allow the \nuse of contiguous memory locations\n•\nIt ensures a maximum USB bandwidth of up to one frame without application \nintervention\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1386/1757\nRM0090 Rev 21\n35.2.2 \nHost-mode features\nThe OTG_HS interface features in host mode are the following:\n•\nIt requires an external charge pump to generate VBUS\n•\nIt has up to 12 host channels (pipes), each channel being dynamically reconfigurable to \nsupport any kind of USB transfer\n•\nIt features a built-in hardware scheduler holding:\n–\nUp to 8 interrupt plus isochronous transfer requests in the periodic hardware \nqueue\n–\nUp to 8 control plus bulk transfer requests in the nonperiodic hardware queue\n•\nIt manages a shared RX FIFO, a periodic TX FIFO, and a nonperiodic TX FIFO for \nefficient usage of the USB data RAM\n•\nIt features dynamic trimming capability of SOF framing period in host mode.\n35.2.3 \nPeripheral-mode features\nThe OTG_HS interface main features in peripheral mode are the following:\n•\nIt has 1 bidirectional control endpoint 0\n•\nIt has 5 IN endpoints (EP) configurable to support bulk, interrupt or isochronous \ntransfers\n•\nIt has 5 OUT endpoints configurable to support bulk, interrupt or isochronous transfers\n•\nIt manages a shared Rx FIFO and a Tx-OUT FIFO for efficient usage of the USB data \nRAM\n•\nIt manages up to 6 dedicated Tx-IN FIFOs (one for each IN-configured EP) to reduce \nthe application load\n•\nIt features soft disconnect capability\n35.3 \nOTG_HS functional description\nFigure 410 shows the OTG_HS interface block diagram.\n\n\n<>\n\nRM0090 Rev 21\n1387/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nFigure 410. USB OTG interface block diagram\n1.\nThe USB DMA cannot directly address the internal Flash memory.\n35.3.1 \nOTG pins\n \n35.3.2 \nHigh-speed OTG PHY\nThe USB OTG HS core embeds an ULPI interface to connect an external HS phy.\nMSv43325V1\nData FIFO \nSingle-port RAM \n(SPRAM)\nAHB \nmaster \ninterface\nAHB \nslave \ninterface\nCPU\nMemory\nPeripheral 1\nPeripheral 2\nData FIFO\nRAM interface\nAHB (application bus)\nOTG_HS\n(USB OTG HS core)\nOTG_HS_DP\nOTG_HS_DM\nOTG_HS_ID\nOTG_HS_VBUS\nOTG FS PHY \ntransceiver\nOTG_HS_SOF\nULPI interface (12 pins)\nULPI PHY\n(external\ncomponent)\nUSB2.0 (D+/D-)\nULPI_CK;\nULPI_DIR;\nULPI_STP;\nULPI_NXT;\nULPI_D0-7\nNVIC\nInterrupt: EP1 out\nInterrupt: EP1 in\nInterrupt: global\nInterrupt: async wakeup\nOTG detections\nEXTI\nEXTI\nserial\nTable 207. OTG_HS input/output pins\nSignal name\nSignal type\nDescription\nOTG_HS_DP\nDigital input/output\nUSB OTG D+ line\nOTG_HS_DM\nDigital input/output\nUSB OTG D- line\nOTG_HS_ID\nDigital input\nUSB OTG ID\nOTG_HS_VBUS\nAnalog input\nUSB OTG VBUS\nOTG_HS_SOF\nDigital output\nUSB OTG Start Of Frame (visibility)\nOTG_HS_ULPI_CK\nDigital input\nUSB OTG ULPI clock\nOTG_HS_ULPI_DIR\nDigital input\nUSB OTG ULPI data bus direction control\nOTG_HS_ULPI_STP\nDigital output\nUSB OTG ULPI data stream stop\nOTG_HS_ULPI_NXT\nDigital input\nUSB OTG ULPI next data stream request\nOTG_HS_ULPI_D[0..7]\nDigital input/output\nUSB OTG ULPI 8-bit bi-directional data bus\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1388/1757\nRM0090 Rev 21\n35.3.3 \nEmbedded Full-speed OTG PHY\nThe full-speed OTG PHY includes the following components:\n•\nFS/LS transceiver module used by both host and Device. It directly drives transmission \nand reception on the single-ended USB lines.\n•\nIntegrated ID pull-up resistor used to sample the ID line for A/B Device identification.\n•\nDP/DM integrated pull-up and pull-down resistors controlled by the OTG_HS core \ndepending on the current role of the device. As a peripheral, it enables the DP pull-up \nresistor to signal full-speed peripheral connections as soon as VBUS is sensed to be at \na valid level (B-session valid). In host mode, pull-down resistors are enabled on both \nDP/DM. Pull-up and pull-down resistors are dynamically switched when the peripheral \nrole is changed via the host negotiation protocol (HNP).\n•\nPull-up/pull-down resistor ECN circuit\nThe DP pull-up consists of 2 resistors controlled separately from the OTG_HS as per \nthe resistor Engineering Change Notice applied to USB Rev2.0. The dynamic trimming \nof the DP pull-up strength allows to achieve a better noise rejection and Tx/Rx signal \nquality.\n•\nVBUS sensing comparators with hysteresis used to detect VBUS_VALID, A-B Session \nValid and session-end voltage thresholds. They are used to drive the session request \nprotocol (SRP), detect valid startup and end-of-session conditions, and constantly \nmonitor the VBUS supply during USB operations.\n•\nVBUS pulsing method circuit used to charge/discharge VBUS through resistors during \nthe SRP (weak drive).\nCaution:\nTo guarantee a correct operation for the USB OTG HS peripheral, the AHB frequency \nshould be higher than 30 MHz.\n35.4 \nOTG dual-role device\n35.4.1 \nID line detection\nThe host or peripheral (the default) role depends on the level of the ID input line. It is \ndetermined when the USB cable is plugged in and depends on which side of the USB cable \nis connected to the micro-AB receptacle:\n•\nIf the B-side of the USB cable is connected with a floating ID wire, the integrated pull-\nup resistor detects a high ID level and the default peripheral role is confirmed. In this \nconfiguration the OTG_HS conforms to the FSM standard described in \nsection 6.8.2. On-The-Go B-device of the USB On-The-Go Supplement, Revision 1.3.\n•\nIf the A-side of the USB cable is connected with a grounded ID, the OTG_HS issues an \nID line status change interrupt (CIDSCHG bit in the OTG_HS_GINTSTS register) for \nhost software initialization, and automatically switches to host role. In this configuration \nthe OTG_HS conforms to the FSM standard described by section 6.8.1: On-The-Go A- \nDevice of the USB On-The-Go Supplement, Revision 1.3.\n35.4.2 \nHNP dual role device\nThe HNP capable bit in the Global USB configuration register (HNPCAP bit in the \nOTG_HS_ GUSBCFG register) configures the OTG_HS core to dynamically change from \nA-host to A-device role and vice-versa, or from B-device to B-host role and vice-versa, \naccording to the host negotiation protocol (HNP). The current device status is defined by the \n\n\n<>\n\nRM0090 Rev 21\n1389/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\ncombination of the Connector ID Status bit in the Global OTG control and status register \n(CIDSTS bit in OTG_HS_GOTGCTL) and the current mode of operation bit in the global \ninterrupt and status register (CMOD bit in OTG_HS_GINTSTS).\nThe HNP programming model is described in detail in Section 35.13: OTG_HS \nprogramming model.\n35.4.3 \nSRP dual-role device\nThe SRP capable bit in the global USB configuration register (SRPCAP bit in \nOTG_HS_GUSBCFG) configures the OTG_HS core to switch VBUS off for the A-device in \norder to save power. The A-device is always in charge of driving VBUS regardless of the \nOTG_HS role (host or peripheral). The SRP A/B-device program model is described in \ndetail in Section 35.13: OTG_HS programming model. \n35.5 \nUSB functional description in peripheral mode\nThe OTG_HS operates as an USB peripheral in the following circumstances:\n•\nOTG B-device\nOTG B-device default state if the B-side of USB cable is plugged in\n•\nOTG A-device\nOTG A-device state after the HNP switches the OTG_HS to peripheral role\n•\nB-Device\nIf the ID line is present, functional and connected to the B-side of the USB cable, and \nthe HNP-capable bit in the Global USB Configuration register (HNPCAP bit in \nOTG_HS_GUSBCFG) is cleared (see On-The-Go specification Revision 1.3 section \n6.8.3).\n•\nPeripheral only (see Figure 388: USB peripheral-only connection)\nThe force peripheral mode bit in the Global USB configuration register (FDMOD in \nOTG_HS_GUSBCFG) is set to 1, forcing the OTG_HS core to operate in USB \nperipheral-only mode (see On-The-Go specification Revision 1.3 section 6.8.3). In this \ncase, the ID line is ignored even if it is available on the USB connector.\nNote:\nTo build a bus-powered device architecture in the B-Device or peripheral-only configuration, \nan external regulator must be added to generate the VDD supply voltage from VBUS.\n35.5.1 \nSRP-capable peripheral\nThe SRP capable bit in the Global USB configuration register (SRPCAP bit in \nOTG_HS_GUSBCFG) configures the OTG_HS to support the session request protocol \n(SRP). As a result, it allows the remote A-device to save power by switching VBUS off when \nthe USB session is suspended.\nThe SRP peripheral mode program model is described in detail in Section : B-device \nsession request protocol.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1390/1757\nRM0090 Rev 21\n35.5.2 \nPeripheral states\nPowered state\nThe VBUS input detects the B-session valid voltage used to put the USB peripheral in the \nPowered state (see USB2.0 specification section 9.1). The OTG_HS then automatically \nconnects the DP pull-up resistor to signal full-speed device connection to the host, and \ngenerates the session request interrupt (SRQINT bit in OTG_HS_GINTSTS) to notify the \nPowered state. The VBUS input also ensures that valid VBUS levels are supplied by the host \nduring USB operations. If VBUS drops below the B-session valid voltage (for example \nbecause power disturbances occurred or the host port has been switched off), the OTG_HS \nautomatically disconnects and the session end detected (SEDET bit in \nOTG_HS_GOTGINT) interrupt is generated to notify that the OTG_HS has exited the \nPowered state. \nIn Powered state, the OTG_HS expects a reset from the host. No other USB operations are \npossible. When a reset is received, the reset detected interrupt (USBRST in \nOTG_HS_GINTSTS) is generated. When the reset is complete, the enumeration done \ninterrupt (ENUMDNE bit in OTG_HS_GINTSTS) is generated and the OTG_HS enters the \nDefault state.\nSoft disconnect\nThe Powered state can be exited by software by using the soft disconnect feature. The DP \npull-up resistor is removed by setting the Soft disconnect bit in the device control register \n(SDIS bit in OTG_HS_DCTL), thus generating a device disconnect detection interrupt on \nthe host side even though the USB cable was not really unplugged from the host port.\nDefault state\nIn Default state the OTG_HS expects to receive a SET_ADDRESS command from the host. \nNo other USB operations are possible. When a valid SET_ADDRESS command is decoded \non the USB, the application writes the corresponding number into the device address field in \nthe device configuration register (DAD bit in OTG_HS_DCFG). The OTG_HS then enters \nthe address state and is ready to answer host transactions at the configured USB address.\nSuspended state\nThe OTG_HS peripheral constantly monitors the USB activity. When the USB remains idle \nfor 3 ms, the early suspend interrupt (ESUSP bit in OTG_HS_GINTSTS) is issued. It is \nconfirmed 3 ms later, if appropriate, by generating a suspend interrupt (USBSUSP bit in \nOTG_HS_GINTSTS). The device suspend bit is then automatically set in the device status \nregister (SUSPSTS bit in OTG_HS_DSTS) and the OTG_HS enters the Suspended state.\nThe device can also exit from the Suspended state by itself. In this case the application sets \nthe remote wake-up signaling bit in the device control register (RWUSIG bit in \nOTG_HS_DCTL) and clears it after 1 to 15 ms.\nWhen a resume signaling is detected from the host, the resume interrupt (WKUPINT bit in \nOTG_HS_GINTSTS) is generated and the device suspend bit is automatically cleared.\n\n\n<>\n\nRM0090 Rev 21\n1391/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n35.5.3 \nPeripheral endpoints\nThe OTG_HS core instantiates the following USB endpoints:\n•\nControl endpoint 0\nThis endpoint is bidirectional and handles control messages only.\nIt has a separate set of registers to handle IN and OUT transactions, as well as \ndedicated control (OTG_HS_DIEPCTL0/OTG_HS_DOEPCTL0), transfer configuration \n(OTG_HS_DIEPTSIZ0/OTG_HS_DIEPTSIZ0), and status-interrupt \n(OTG_HS_DIEPINTx/)OTG_HS_DOEPINT0) registers. The bits available inside the \ncontrol and transfer size registers slightly differ from other endpoints.\n•\n5 IN endpoints\n–\nThey can be configured to support the isochronous, bulk or interrupt transfer type.\n–\nThey feature dedicated control (OTG_HS_DIEPCTLx), transfer configuration \n(OTG_HS_DIEPTSIZx), and status-interrupt (OTG_HS_DIEPINTx) registers.\n–\nThe Device IN endpoints common interrupt mask register (OTG_HS_DIEPMSK) \nallows to enable/disable a single endpoint interrupt source on all of the \nIN endpoints (EP0 included).\n–\nThey support incomplete isochronous IN transfer interrupt (IISOIXFR bit in \nOTG_HS_GINTSTS). This interrupt is asserted when there is at least one \nisochronous IN endpoint for which the transfer is not completed in the current \nframe. This interrupt is asserted along with the end of periodic frame interrupt \n(OTG_HS_GINTSTS/EOPF).\n•\n5 OUT endpoints\n–\nThey can be configured to support the isochronous, bulk or interrupt transfer type.\n–\nThey feature dedicated control (OTG_HS_DOEPCTLx), transfer configuration \n(OTG_HS_DOEPTSIZx) and status-interrupt (OTG_HS_DOEPINTx) registers.\n–\nThe Device Out endpoints common interrupt mask register \n(OTG_HS_DOEPMSK) allows to enable/disable a single endpoint interrupt source \non all OUT endpoints (EP0 included).\n–\nThey support incomplete isochronous OUT transfer interrupt (INCOMPISOOUT \nbit in OTG_HS_GINTSTS). This interrupt is asserted when there is at least one \nisochronous OUT endpoint on which the transfer is not completed in the current \nframe. This interrupt is asserted along with the end of periodic frame interrupt \n(OTG_HS_GINTSTS/EOPF).\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1392/1757\nRM0090 Rev 21\nEndpoint controls\nThe following endpoint controls are available through the device endpoint-x IN/OUT control \nregister (DIEPCTLx/DOEPCTLx):\n•\nEndpoint enable/disable\n•\nEndpoint activation in current configuration\n•\nProgram the USB transfer type (isochronous, bulk, interrupt)\n•\nProgram the supported packet size\n•\nProgram the Tx-FIFO number associated with the IN endpoint\n•\nProgram the expected or transmitted data0/data1 PID (bulk/interrupt only)\n•\nProgram the even/odd frame during which the transaction is received or transmitted \n(isochronous only)\n•\nOptionally program the NAK bit to always send a negative acknowledge to the host \nregardless of the FIFO status\n•\nOptionally program the STALL bit to always stall host tokens to that endpoint\n•\nOptionally program the Snoop mode for OUT endpoint where the received data CRC is \nnot checked\nEndpoint transfer\nThe device endpoint-x transfer size registers (DIEPTSIZx/DOEPTSIZx) allow the application \nto program the transfer size parameters and read the transfer status.\nThe programming operation must be performed before setting the endpoint enable bit in the \nendpoint control register. \nOnce the endpoint is enabled, these fields are read-only as the OTG FS core updates them \nwith the current transfer status.\nThe following transfer parameters can be programmed:\n•\nTransfer size in bytes\n•\nNumber of packets constituting the overall transfer size.\nEndpoint status/interrupt\nThe device endpoint-x interrupt registers (DIEPINTx/DOPEPINTx) indicate the status of an \nendpoint with respect to USB- and AHB-related events. The application must read these \nregisters when the OUT endpoint interrupt bit or the IN endpoint interrupt bit in the core \ninterrupt register (OEPINT bit in OTG_HS_GINTSTS or IEPINT bit in OTG_HS_GINTSTS, \nrespectively) is set. Before the application can read these registers, it must first read the \ndevice all endpoints interrupt register (OTG_HS_DAINT) to get the exact endpoint number \nfor the device endpoint-x interrupt register. The application must clear the appropriate bit in \nthis register to clear the corresponding bits in the DAINT and GINTSTS registers.\n\n\n<>\n\nRM0090 Rev 21\n1393/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nThe peripheral core provides the following status checks and interrupt generation:\n•\nTransfer completed interrupt, indicating that data transfer has completed on both the \napplication (AHB) and USB sides\n•\nSetup stage done (control-out only)\n•\nAssociated transmit FIFO is half or completely empty (in endpoints)\n•\nNAK acknowledge transmitted to the host (isochronous-in only)\n•\nIN token received when Tx-FIFO was empty (bulk-in/interrupt-in only)\n•\nOUT token received when endpoint was not yet enabled\n•\nBabble error condition detected\n•\nEndpoint disable by application is effective\n•\nEndpoint NAK by application is effective (isochronous-in only)\n•\nMore than 3 back-to-back setup packets received (control-out only)\n•\nTimeout condition detected (control-in only)\n•\nIsochronous out packet dropped without generating an interrupt\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1394/1757\nRM0090 Rev 21\n35.6 \nUSB functional description on host mode\nThis section gives the functional description of the OTG_HS in the USB host mode. The \nOTG_HS works as a USB host in the following circumstances:\n•\nOTG A-host\nOTG A-device default state when the A-side of the USB cable is plugged in\n•\nOTG B-host\nOTG B-device after HNP switching to the host role\n•\nA-device\nIf the ID line is present, functional and connected to the A-side of the USB cable, and \nthe HNP-capable bit is cleared in the Global USB Configuration register (HNPCAP bit \nin OTG_HS_GUSBCFG). Integrated pull-down resistors are automatically set on the \nDP/DM lines.\n•\nHost only (Figure 389: USB host-only connection).\nThe force host mode bit in the global USB configuration register (FHMOD bit in \nOTG_HS_GUSBCFG) forces the OTG_HS core to operate in USB host-only mode. In \nthis case, the ID line is ignored even if it is available on the USB connector. Integrated \npull-down resistors are automatically set on the OTG_HS_FS_DP/OTG_HS_FS_DM \nlines.\nNote:\nOn-chip 5 V VBUS generation is not supported. As a result, a charge pump or a basic power \nswitch (if a 5 V supply is available on the application board) must be added externally to \ndrive the 5 V VBUS line. The external charge pump can be driven by any GPIO output. This \nis required for the OTG A-host, A-device and host-only configurations.\nThe VBUS input ensures that valid VBUS levels are supplied by the charge pump during USB \noperations while the charge pump overcurrent output can be input to any GPIO pin \nconfigured to generate port interrupts. The overcurrent ISR must promptly disable the VBUS \ngeneration.\nFigure 411. USB host-only connection\n35.6.1 \nSRP-capable host\nSRP support is available through the SRP capable bit in the global USB configuration \nregister (SRPCAP bit in OTG_HS_GUSBCFG). When the SRP feature is enabled, the host \ncan save power by switching off the VBUS power while the USB session is suspended. The \nMSv36915V2\nSTMPS2141STR\nCurrent-limited\n power distribution \nswitch(2)\nOSC_IN\nOSC_OUT\nGPIO\nGPIO + IRQ\nEN\nOvercurrent\n5 V\n5 V Pwr\nVBUS\nDM\nDP\nVSS\nUSB Std-A connector\nVDD\n\n\n<>\n\nRM0090 Rev 21\n1395/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nSRP host mode program model is described in detail in Section : A-device session request \nprotocol.\n35.6.2 \nUSB host states\nHost port power \nOn-chip 5 V VBUS generation is not supported. As a result, a charge pump or a basic power \nswitch (if a 5 V supply voltage is available on the application board) must be added \nexternally to drive the 5 V VBUS line. The external charge pump can be driven by any GPIO \noutput. When the application powers on VBUS through the selected GPIO, it must also set \nthe port power bit in the host port control and status register (PPWR bit in OTG_HS_HPRT).\nVBUS valid\nWhen SRP or HNP is enabled the VBUS sensing pin (PB13) pin should be connected to \nVBUS. The VBUS input ensures that valid VBUS levels are supplied by the charge pump \nduring USB operations. Any unforeseen VBUS voltage drop below the VBUS valid threshold \n(4.25 V) generates an OTG interrupt triggered by the session end detected bit (SEDET bit in \nOTG_HS_GOTGINT). The application must then switch the VBUS power off and clear the \nport power bit. \nWhen HNP and SRP are both disabled, the VBUS sensing pin (PB13) should not be \nconnected to VBUS. This pin can be can be used as GPIO.\nThe charge pump overcurrent flag can also be used to prevent electrical damage. Connect \nthe overcurrent flag output from the charge pump to any GPIO input, and configure it to \ngenerate a port interrupt on the active level. The overcurrent ISR must promptly disable the \nVBUS generation and clear the port power bit.\nDetection of peripheral connection by the host\nIf SRP or HNP are enabled, even if USB peripherals or B-devices can be attached at any \ntime, the OTG_HS does not detect a bus connection until the end of the VBUS sensing \n(VBUS over 4.75 V).\nWhen VBUS is at a valid level and a remote B-device is attached, the OTG_HS core issues a \nhost port interrupt triggered by the device connected bit in the host port control and status \nregister (PCDET bit in OTG_HS_HPRT).\nWhen HNP and SRP are both disabled, USB peripherals or B-device are detected as \nsoon as they are connected. The OTG_HS core issues a host port interrupt triggered by \nthe device connected bit in the host port control and status (PCDET bit in OTG_HS_HPRT).\nDetection of peripheral disconnection by the host\nThe peripheral disconnection event triggers the disconnect detected interrupt (DISCINT bit \nin OTG_HS_GINTSTS).\nHost enumeration\nAfter detecting a peripheral connection, the host must start the enumeration process by \nissuing an USB reset and configuration commands to the new peripheral.\nBefore sending an USB reset, the application waits for the OTG interrupt triggered by the \ndebounce done bit (DBCDNE bit in OTG_HS_GOTGINT), which indicates that the bus is \n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1396/1757\nRM0090 Rev 21\nstable again after the electrical debounce caused by the attachment of a pull-up resistor on \nOTG_HS_FS_DP (full speed) or OTG_HS_FS_DM (low speed).\nThe application issues an USB reset (single-ended zero) via the USB by keeping the port \nreset bit set in the Host port control and status register (PRST bit in OTG_HS_HPRT) for a \nminimum of 10 ms and a maximum of 20 ms. The application monitors the time and then \nclears the port reset bit.\nOnce the USB reset sequence has completed, the host port interrupt is triggered by the port \nenable/disable change bit (PENCHNG bit in OTG_HS_HPRT) to inform the application that \nthe speed of the enumerated peripheral can be read from the port speed field in the host \nport control and status register (PSPD bit in OTG_HS_HPRT), and that the host is starting \nto drive SOFs (full speed) or keep-alive tokens (low speed). The host is then ready to \ncomplete the peripheral enumeration by sending peripheral configuration commands.\nHost suspend\nThe application can decide to suspend the USB activity by setting the port suspend bit in the \nhost port control and status register (PSUSP bit in OTG_HS_HPRT). The OTG_HS core \nstops sending SOFs and enters the Suspended state.\nThe Suspended state can be exited on the remote device initiative (remote wake-up). In this \ncase the remote wake-up interrupt (WKUPINT bit in OTG_HS_GINTSTS) is generated upon \ndetection of a remote wake-up event, the port resume bit in the host port control and status \nregister (PRES bit in OTG_HS_HPRT) is set, and a resume signaling is automatically \nissued on the USB. The application must monitor the resume window duration, and then \nclear the port resume bit to exit the Suspended state and restart the SOF.\nIf the Suspended state is exited on the host initiative, the application must set the port \nresume bit to start resume signaling on the host port, monitor the resume window duration \nand then clear the port resume bit.\n35.6.3 \nHost channels\nThe OTG_HS core instantiates 12 host channels. Each host channel supports an USB host \ntransfer (USB pipe). The host is not able to support more than 8 transfer requests \nsimultaneously. If more than 8 transfer requests are pending from the application, the host \ncontroller driver (HCD) must re-allocate channels when they become available, that is, after \nreceiving the transfer completed and channel halted interrupts.\nEach host channel can be configured to support IN/OUT and any type of \nperiodic/nonperiodic transaction. Each host channel has dedicated control (HCCHARx), \ntransfer configuration (HCTSIZx) and status/interrupt (HCINTx) registers with associated \nmask (HCINTMSKx) registers.\n\n\n<>\n\nRM0090 Rev 21\n1397/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nHost channel controls\nThe following host channel controls are available through the host channel-x characteristics \nregister (HCCHARx):\n•\nChannel enable/disable\n•\nProgram the HS/FS/LS speed of target USB peripheral\n•\nProgram the address of target USB peripheral\n•\nProgram the endpoint number of target USB peripheral\n•\nProgram the transfer IN/OUT direction\n•\nProgram the USB transfer type (control, bulk, interrupt, isochronous)\n•\nProgram the maximum packet size (MPS)\n•\nProgram the periodic transfer to be executed during odd/even frames\nHost channel transfer\nThe host channel transfer size registers (HCTSIZx) allow the application to program the \ntransfer size parameters, and read the transfer status.\nThe programming operation must be performed before setting the channel enable bit in the \nhost channel characteristics register. Once the endpoint is enabled, the packet count field is \nread-only as the OTG HS core updates it according to the current transfer status.\nThe following transfer parameters can be programmed:\n•\nTransfer size in bytes\n•\nNumber of packets constituting the overall transfer size\n•\nInitial data PID\nHost channel status/interrupt\nThe host channel-x interrupt register (HCINTx) indicates the status of an endpoint with \nrespect to USB- and AHB-related events. The application must read these register when the \nhost channels interrupt bit in the core interrupt register (HCINT bit in OTG_HS_GINTSTS) is \nset. Before the application can read these registers, it must first read the host all channels \ninterrupt (HCAINT) register to get the exact channel number for the host channel-x interrupt \nregister. The application must clear the appropriate bit in this register to clear the \ncorresponding bits in the HAINT and GINTSTS registers. The mask bits for each interrupt \nsource of each channel are also available in the OTG_HS_HCINTMSK-x register.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1398/1757\nRM0090 Rev 21\nThe host core provides the following status checks and interrupt generation:\n•\nTransfer completed interrupt, indicating that the data transfer is complete on both the \napplication (AHB) and USB sides\n•\nChannel stopped due to transfer completed, USB transaction error or disable \ncommand from the application\n•\nAssociated transmit FIFO half or completely empty (IN endpoints)\n•\nACK response received\n•\nNAK response received\n•\nSTALL response received\n•\nUSB transaction error due to CRC failure, timeout, bit stuff error, false EOP\n•\nBabble error\n•\nFrame overrun\n•\nData toggle error\n35.6.4 \nHost scheduler\nThe host core features a built-in hardware scheduler which is able to autonomously re-order \nand manage the USB the transaction requests posted by the application. At the beginning of \neach frame the host executes the periodic (isochronous and interrupt) transactions first, \nfollowed by the nonperiodic (control and bulk) transactions to achieve the higher level of \npriority granted to the isochronous and interrupt transfer types by the USB specification.\nThe host processes the USB transactions through request queues (one for periodic and one \nfor nonperiodic). Each request queue can hold up to 8 entries. Each entry represents a \npending transaction request from the application, and holds the IN or OUT channel number \nalong with other information to perform a transaction on the USB. The order in which the \nrequests are written to the queue determines the sequence of the transactions on the USB \ninterface. \nAt the beginning of each frame, the host processes the periodic request queue first, followed \nby the nonperiodic request queue. The host issues an incomplete periodic transfer interrupt \n(IPXFR bit in OTG_HS_GINTSTS) if an isochronous or interrupt transaction scheduled for \nthe current frame is still pending at the end of the current frame. The OTG HS core is fully \nresponsible for the management of the periodic and nonperiodic request queues.The \nperiodic transmit FIFO and queue status register (HPTXSTS) and nonperiodic transmit \nFIFO and queue status register (HNPTXSTS) are read-only registers which can be used by \nthe application to read the status of each request queue. They contain: \n•\nThe number of free entries currently available in the periodic (nonperiodic) request \nqueue (8 max) \n•\nFree space currently available in the periodic (nonperiodic) Tx-FIFO (out-transactions)\n•\nIN/OUT token, host channel number and other status information.\nAs request queues can hold a maximum of 8 entries each, the application can push to \nschedule host transactions in advance with respect to the moment they physically reach the \nUSB for a maximum of 8 pending periodic transactions plus 8 pending nonperiodic \ntransactions.\nTo post a transaction request to the host scheduler (queue) the application must check that \nthere is at least 1 entry available in the periodic (nonperiodic) request queue by reading the \nPTXQSAV bits in the OTG_HS_HNPTXSTS register or NPTQXSAV bits in the \nOTG_HS_HNPTXSTS register. \n\n\n<>\n\nRM0090 Rev 21\n1399/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n35.7 \nSOF trigger\nThe OTG FS core allows to monitor, track and configure SOF framing in the host and \nperipheral. It also features an SOF pulse output connectivity.\nThese capabilities are particularly useful to implement adaptive audio clock generation \ntechniques, where the audio peripheral needs to synchronize to the isochronous stream \nprovided by the PC, or the host needs trimming its framing rate according to the \nrequirements of the audio peripheral.\n35.7.1 \nHost SOFs\nIn host mode the number of PHY clocks occurring between the generation of two \nconsecutive SOF (FS) or keep-alive (LS) tokens is programmable in the host frame interval \nregister (OTG_HS_HFIR), thus providing application control over the SOF framing period. \nAn interrupt is generated at any start of frame (SOF bit in OTG_HS_GINTSTS). The current \nframe number and the time remaining until the next SOF are tracked in the host frame \nnumber register (OTG_HS_HFNUM).\nAn SOF pulse signal is generated at any SOF starting token and with a width of 20 HCLK \ncycles. It can be made available externally on the SOF pin using the SOFOUTEN bit in the \nglobal control and configuration register. The SOF pulse is also internally connected to the \ninput trigger of timer 2 (TIM2), so that the input capture feature, the output compare feature \nand the timer can be triggered by the SOF pulse. The TIM2 connection is enabled through \nITR1_RMP bits of TIM2_OR register.\nFigure 412. SOF trigger output to TIM2 ITR1 connection\n35.7.2 \nPeripheral SOFs\nIn peripheral mode, the start of frame interrupt is generated each time an SOF token is \nreceived on the USB (SOF bit in OTG_HS_GINTSTS). The corresponding frame number \ncan be read from the device status register (FNSOF bit in OTG_HS_DSTS). An SOF pulse \nsignal with a width of 20 HCLK cycles is also generated and can be made available \nexternally on the SOF pin by using the SOF output enable bit in the global control and \nconfiguration register (SOFOUTEN bit in OTG_HS_GCCFG). The SOF pulse signal is also \ninternally connected to the TIM2 input trigger, so that the input capture feature, the output \ncompare feature and the timer can be triggered by the SOF pulse (see Figure 412). The \nTIM2 connection is enabled through ITR1_RMP bits of TIM2_OR register.\nSOF\npulse\nITR1\nTIM2\nOTG_HS_Core\nSOF output pulse\nUSB Micro-AB connector\nVBUS\nDP\nDM\nID\nai16092\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1400/1757\nRM0090 Rev 21\nThe end of periodic frame interrupt (GINTSTS/EOPF) is used to notify the application when \n80%, 85%, 90% or 95% of the time frame interval elapsed depending on the periodic frame \ninterval field in the device configuration register (PFIVL bit in OTG_HS_DCFG). \nThis feature can be used to determine if all of the isochronous traffic for that frame is \ncomplete.\n35.8 \nOTG_HS low-power modes\nTable 208 below defines the STM32 low power modes and their compatibility with the OTG.\n \nThe following bits and procedures reduce power consumption.\nThe power consumption of the OTG PHY is controlled by three bits in the general core \nconfiguration register:\n•\nPHY power down (GCCFG/PWRDWN)\nThis bit switches on/off the PHY full-speed transceiver module. It must be preliminarily \nset to allow any USB operation.\n•\nA-VBUS sensing enable (GCCFG/VBUSASEN)\nThis bit switches on/off the VBUS comparators associated with A-device operations. It \nmust be set when in A-device (USB host) mode and during HNP.\n•\nB-VBUS sensing enable (GCCFG/VBUSASEN)\nThis bit switches on/off the VBUS comparators associated with B-device operations. It \nmust be set when in B-device (USB peripheral) mode and during HNP.\nPower reduction techniques are available in the USB suspended state, when the USB \nsession is not yet valid or the device is disconnected.\n•\nStop PHY clock (STPPCLK bit in OTG_HS_PCGCCTL)\n–\nWhen setting the stop PHY clock bit in the clock gating control register, most of the \nclock domain internal to the OTG high-speed core is switched off by clock gating. \nTable 208. Compatibility of STM32 low power modes with the OTG\nMode\nDescription\nUSB compatibility\nRun\nMCU fully active\nRequired when USB not in \nsuspend state.\nSleep\nUSB suspend exit causes the device to exit Sleep mode. Peripheral \nregisters content is kept.\nAvailable while USB is in \nsuspend state. \nStop\nUSB suspend exit causes the device to exit Stop mode. Peripheral \nregisters content is kept(1).\nAvailable while USB is in \nsuspend state. \nStandby\nPowered-down. The peripheral must be reinitialized after exiting \nStandby mode.\nNot compatible with USB \napplications.\n1.\nWithin Stop mode there are different possible settings. Some restrictions may also exist, please refer to Section 5: Power \ncontroller (PWR) to understand which (if any) restrictions apply when using OTG.\n\n\n<>\n\nRM0090 Rev 21\n1401/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nThe dynamic power consumption due to the USB clock switching activity is cut \neven if the clock input is kept running by the application\n–\nMost of the transceiver is also disabled, and only the part in charge of detecting \nthe asynchronous resume or remote wake-up event is kept alive.\n•\nGate HCLK (GATEHCLK bit in OTG_HS_PCGCCTL)\nWhen setting the Gate HCLK bit in the clock gating control register, most of the system \nclock domain internal to the OTG_HS core is switched off by clock gating. Only the \nregister read and write interface is kept alive. The dynamic power consumption due to \nthe USB clock switching activity is cut even if the system clock is kept running by the \napplication for other purposes.\n•\nUSB system stop\n–\nWhen the OTG_HS is in USB suspended state, the application can decide to \ndrastically reduce the overall power consumption by shutting down all the clock \nsources in the system. USB System Stop is activated by first setting the Stop PHY \nclock bit and then configuring the system deep sleep mode in the powercontrol \nsystem module (PWR).\n–\nThe OTG_HS core automatically reactivates both system and USB clocks by \nasynchronous detection of remote wake-up (as an host) or resume (as a Device) \nsignaling on the USB.\n35.9 \nDynamic update of the OTG_HS_HFIR register\nThe USB core embeds a dynamic trimming capability of micro-SOF framing period in host \nmode allowing to synchronize an external device with the micro-SOF frames. \nWhen the OTG_HS_HFIR register is changed within a current micro-SOF frame, the SOF \nperiod correction is applied in the next frame as described in Figure 413.\nFigure 413. Updating OTG_HS_HFIR dynamically\n400\n…\n…\n…\n…\n…\n450\nLatency \nSOF\nreload \nOTG_HS_HFIR \nwrite \nvalue \nFrame\ntimer \nOld OTG_HS_HIFR value\n= 400 periods\nOTG_HS_HIFR value\n= 450 periods+HIFR write latency\nNew OTG_HS_HIFR value\n= 450 periods\n1\n400\n0\n399\n1\n400\n0\n399\n450\n449\n1\n450\n0\n449\n1\n450\n0\n449\nOTG_HS_HFIR \nai18439b\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1402/1757\nRM0090 Rev 21\n35.10 \nFIFO RAM allocation\n35.10.1 \nPeripheral mode\nReceive FIFO RAM\nFor Receive FIFO RAM, the application should allocate RAM for SETUP packets: 10 \nlocations must be reserved in the receive FIFO to receive SETUP packets on control \nendpoints. These locations are reserved for SETUP packets and are not used by the core to \nwrite any other data. \nOne location must be allocated for Global OUT NAK. Status information are also written to \nthe FIFO along with each received packet. Therefore, a minimum space of (Largest Packet \nSize / 4) + 1 must be allocated to receive packets. If a high-bandwidth endpoint or multiple \nisochronous endpoints are enabled, at least two spaces of (Largest Packet Size / 4) + 1 \nmust be allotted to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 1 \nspaces are recommended so that when the previous packet is being transferred to AHB, the \nUSB can receive the subsequent packet. \nAlong with each endpoints last packet, transfer complete status information are also pushed \nto the FIFO. Typically, one location for each OUT endpoint is recommended.\nTransmit FIFO RAM\nFor Transmit FIFO RAM, the minimum RAM space required for each IN Endpoint Transmit \nFIFO is the maximum packet size for this IN endpoint. \nNote:\nMore space allocated in the transmit IN Endpoint FIFO results in a better performance on \nthe USB. \n35.10.2 \nHost mode\nReceive FIFO RAM\nFor Receive FIFO RAM allocation, Status information are written to the FIFO along with \neach received packet. Therefore, a minimum space of (Largest Packet Size / 4) + 1 must be \nallocated to receive packets. If a high-bandwidth channel or multiple isochronous channels \nare enabled, at least two spaces of (Largest Packet Size / 4) + 1 must be allocated to \nreceive back-to-back packets. Typically, two (Largest Packet Size / 4) + 1 spaces are \nrecommended so that when the previous packet is being transferred to AHB, the USB can \nreceive the subsequent packet. \nAlong with each host channels last packet, transfer complete status information are also \npushed to the FIFO. As a consequence, one location must be allocated to store this data. \nTransmit FIFO RAM\nFor Transmit FIFO RAM allocation, the minimum amount of RAM required for the host \nnonperiodic Transmit FIFO is the largest maximum packet size for all supported nonperiodic \nOUT channels. Typically, a space corresponding to two Largest Packet Size is \nrecommended, so that when the current packet is being transferred to the USB, the AHB \ncan transmit the subsequent packet.\nThe minimum amount of RAM required for Host periodic Transmit FIFO is the largest \nmaximum packet size for all supported periodic OUT channels. If there is at least one High \n\n\n<>\n\nRM0090 Rev 21\n1403/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBandwidth Isochronous OUT endpoint, then the space must be at least two times the \nmaximum packet size for that channel. \nNote:\nMore space allocated in the Transmit nonperiodic FIFO results in better performance on the \nUSB.\nWhen operating in DMA mode, the DMA address register for each host channel (HCDMAn) \nis stored in the SPRAM (FIFO). One location for each channel must be reserved for this.\n35.11 \nOTG_HS interrupts\nWhen the OTG_HS controller is operating in one mode, either peripheral or host, the \napplication must not access registers from the other mode. If an illegal access occurs, a \nmode mismatch interrupt is generated and reflected in the Core interrupt register (MMIS bit \nin the OTG_HS_GINTSTS register). When the core switches from one mode to the other, \nthe registers in the new mode of operation must be reprogrammed as they would be after a \npower-on reset.\nFigure 414 shows the interrupt hierarchy.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1404/1757\nRM0090 Rev 21\nFigure 414. Interrupt hierarchy\n1.\nOTG_HS_WKUP becomes active (high state) when resume condition occurs during L1 SLEEP or L2 SUSPEND states.\nMSv47472V2\nOTG_DEACHINTMSK\nDevice each endpoint interrupt mask \nregister\nOTG_DAINTMSK\nDevice all endpoints interrupt mask \nregister\nOTG_DIEPMSK/\nOTG_DOEPMSK\nDevice IN/OUT endpoints common \ninterrupt mask register\nOTG_DIEPEACHMSK1/\nOTG_DOEPEACHMSK1\nDevice each IN/OUT endpoint interrupt \nmask registers\nOTG_HCTINTMSKx\nHost channels interrupt mask registers\nOTG_HAINTMSK\nHost all channels interrupt mask register\n31:26\n25 24\n23:20\n19 18\n17:3\n2\n1:0\nOTG_HCTINTx\nHost channels interrupt registers\nOTG_HAINT\nHost all channels interrupt register\nOTG_HPRT\nHost port control and status register\nOTG_DAINT\nDevice all endpoints interrupt register\n(15 + #EP):16\nOUT endpoints\n(#EP-1):0\nIN endpoints\nOTG_GOTGINT\nOTG interrupt register\nOTG_DEACHINT\nDevice each endpoint interrupt register\n17\nEP1OUT\n1\nEP1IN\nOTG_DIEPINTx/\nOTG_DOEPINTx\nDevice IN/OUT endpoint interrupt \nregisters\nOTG_GINTSTS\nCore register interrupt\nOTG_GINTMSK\nCore interrupt mask register\nOTG_AHBCFG\nAHB configuration register\nGlobal interrupt mask (bit 0)\nOR\nAND\nAND\n(1)\nx = 0\nx = #HC-1\nx = 0\nx = #HC-1\nHCINT\nHPRTINT\nOEPINP\nIEPINT\nOTGINT\n...\n...\nGlobal interrupt\nOTG_HS\nWakeup interrupt \nOTG_HS_WKUP\nEP1_OUT interrupt OTG_HS_EP1_OUT\nEP1_IN interrupt OTG_HS_EP1_IN\n\n\n<>\n\nRM0090 Rev 21\n1405/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n35.12 \nOTG_HS control and status registers\nBy reading from and writing to the control and status registers (CSRs) through the AHB \nslave interface, the application controls the OTG_HS controller. These registers are 32 bits \nwide, and the addresses are 32-bit block aligned. The OTG_HS registers must be accessed \nby words (32 bits). CSRs are classified as follows:\n•\nCore global registers\n•\nHost-mode registers\n•\nHost global registers\n•\nHost port CSRs\n•\nHost channel-specific registers\n•\nDevice-mode registers\n•\nDevice global registers\n•\nDevice endpoint-specific registers\n•\nPower and clock-gating registers\n•\nData FIFO (DFIFO) access registers\nOnly the Core global, Power and clock-gating, Data FIFO access, and host port control and \nstatus registers can be accessed in both host and peripheral modes. When the OTG_HS \ncontroller is operating in one mode, either peripheral or host, the application must not \naccess registers from the other mode. If an illegal access occurs, a mode mismatch \ninterrupt is generated and reflected in the Core interrupt register (MMIS bit in the \nOTG_HS_GINTSTS register). When the core switches from one mode to the other, the \nregisters in the new mode of operation must be reprogrammed as they would be after a \npower-on reset.\n \n35.12.1 \nCSR memory map\nThe host and peripheral mode registers occupy different addresses. All registers are \nimplemented in the AHB clock domain.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1406/1757\nRM0090 Rev 21\nFigure 415. CSR memory map\n1.\nx = 5 in peripheral mode and x = 11 in host mode.\nGlobal CSR map\nThese registers are available in both host and peripheral modes.\n \n0000h\nCore global CSRs (1 Kbyte)\n0400h\nHost mode CSRs (1 Kbyte)\n0800h\nDevice mode CSRs (1.5 Kbyte)\n0E00h\nPower and clock gating CSRs (0.5 Kbyte)\n1000h\nDevice EP 0/Host channel 0 FIFO (4 Kbyte)\n2000h\nDevice EP1/Host channel 1 FIFO (4 Kbyte)\n3000h\nDevice EP (x – 1)(1)/Host channel (x – 1)(1) FIFO (4 Kbyte)\nDevice EP x(1)/Host channel x(1) FIFO (4 Kbyte)\nReserved\nDFIFO\npush/pop\nto this region\n2 0000h\n3 FFFFh\nDirect access to data FIFO RAM\nfor debugging (128 Kbyte)\nDFIFO\ndebug read/\nwrite to this\nregion\nai15615b\nTable 209. Core global control and status registers (CSRs)\nAcronym\nAddress \noffset\nRegister name\nOTG_HS_GOTGCTL\n0x000\nOTG_HS control and status register (OTG_HS_GOTGCTL) on page 1411\nOTG_HS_GOTGINT\n0x004\nOTG_HS interrupt register (OTG_HS_GOTGINT) on page 1412\nOTG_HS_GAHBCFG\n0x008\nOTG_HS AHB configuration register (OTG_HS_GAHBCFG) on page 1414\nOTG_HS_GUSBCFG\n0x00C\nOTG_HS USB configuration register (OTG_HS_GUSBCFG) on page 1415\nOTG_HS_GRSTCTL\n0x010\nOTG_HS reset register (OTG_HS_GRSTCTL) on page 1418\nOTG_HS_GINTSTS\n0x014\nOTG_HS core interrupt register (OTG_HS_GINTSTS) on page 1421\nOTG_HS_GINTMSK\n0x018\nOTG_HS interrupt mask register (OTG_HS_GINTMSK) on page 1425\n\n\n<>\n\nRM0090 Rev 21\n1407/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n \nHost-mode CSR map\nThese registers must be programmed every time the core changes to host mode.\n \nOTG_HS_GRXSTSR\n0x01C\nOTG_HS Receive status debug read/OTG status read and pop registers \n(OTG_HS_GRXSTSR/OTG_HS_GRXSTSP) on page 1428\nOTG_HS_GRXSTSP\n0x020\nOTG_HS_GRXFSIZ\n0x024\nOTG_HS Receive FIFO size register (OTG_HS_GRXFSIZ) on page 1429\nOTG_HS_GNPTXFSIZ/\nOTG_HS_TX0FSIZ\n0x028\nOTG_HS nonperiodic transmit FIFO size/Endpoint 0 transmit FIFO size \nregister (OTG_HS_GNPTXFSIZ/OTG_HS_TX0FSIZ) on page 1430\nOTG_HS_GNPTXSTS\n0x02C\nOTG_HS nonperiodic transmit FIFO/queue status register \n(OTG_HS_GNPTXSTS) on page 1430\nOTG_HS_GCCFG\n0x038\nOTG_HS general core configuration register (OTG_HS_GCCFG) on \npage 1431\nOTG_HS_CID\n0x03C\nOTG_HS core ID register (OTG_HS_CID) on page 1432\nOTG_HS_HPTXFSIZ\n0x100\nOTG_HS Host periodic transmit FIFO size register (OTG_HS_HPTXFSIZ) \non page 1432\nOTG_HS_DIEPTXFx\n0x104\n0x108\n...\n0x114\nOTG_HS device IN endpoint transmit FIFO size register \n(OTG_HS_DIEPTXFx) (x = 1..5, where x is the FIFO_number) on page 1433\nTable 209. Core global control and status registers (CSRs) (continued)\nAcronym\nAddress \noffset\nRegister name\nTable 210. Host-mode control and status registers (CSRs)\nAcronym\nOffset \naddress\nRegister name\nOTG_HS_HCFG\n0x400\nOTG_HS host configuration register (OTG_HS_HCFG) on page 1433\nOTG_HS_HFIR\n0x404\nOTG_HS Host frame interval register (OTG_HS_HFIR) on page 1435\nOTG_HS_HFNUM\n0x408\nOTG_HS host frame number/frame time remaining register \n(OTG_HS_HFNUM) on page 1435\nOTG_HS_HPTXSTS\n0x410\nOTG_HS_Host periodic transmit FIFO/queue status register \n(OTG_HS_HPTXSTS) on page 1436\nOTG_HS_HAINT\n0x414\nOTG_HS Host all channels interrupt register (OTG_HS_HAINT) on \npage 1437\nOTG_HS_HAINTMSK\n0x418\nOTG_HS host all channels interrupt mask register (OTG_HS_HAINTMSK) \non page 1437\nOTG_HS_HPRT\n0x440\nOTG_HS host port control and status register (OTG_HS_HPRT) on \npage 1438\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1408/1757\nRM0090 Rev 21\nDevice-mode CSR map\nThese registers must be programmed every time the core changes to peripheral mode.\n \nOTG_HS_HCCHARx\n0x500\n0x520\n...\n0x660\nOTG_HS host channel-x characteristics register (OTG_HS_HCCHARx) \n(x = 0..11, where x = Channel_number) on page 1440\nOTG_HS_HCSPLTx\n0x504\nOTG_HS host channel-x split control register (OTG_HS_HCSPLTx) \n(x = 0..11, where x = Channel_number) on page 1442\nOTG_HS_HCINTx\n0x508\nOTG_HS host channel-x interrupt register (OTG_HS_HCINTx) (x = 0..11, \nwhere x = Channel_number) on page 1443\nOTG_HS_HCINTMSKx\n0x50C\nOTG_HS host channel-x interrupt mask register (OTG_HS_HCINTMSKx) \n(x = 0..11, where x = Channel_number) on page 1444\nOTG_HS_HCTSIZx\n0x510\nOTG_HS host channel-x transfer size register (OTG_HS_HCTSIZx) \n(x = 0..11, where x = Channel_number) on page 1445\nOTG_HS_HCDMAx\n0x514\nOTG_HS host channel-x DMA address register (OTG_HS_HCDMAx) \n(x = 0..11, where x = Channel_number) on page 1446\nTable 210. Host-mode control and status registers (CSRs) (continued)\nAcronym\nOffset \naddress\nRegister name\nTable 211. Device-mode control and status registers\nAcronym\nOffset \naddress\nRegister name\nOTG_HS_DCFG\n0x800\nOTG_HS device configuration register (OTG_HS_DCFG) on \npage 1446\nOTG_HS_DCTL\n0x804\nOTG_HS device control register (OTG_HS_DCTL) on page 1448\nOTG_HS_DSTS\n0x808\nOTG_HS device status register (OTG_HS_DSTS) on page 1450\nOTG_HS_DIEPMSK\n0x810\nOTG_HS device IN endpoint common interrupt mask register \n(OTG_HS_DIEPMSK) on page 1451\nOTG_HS_DOEPMSK\n0x814\nOTG_HS device OUT endpoint common interrupt mask register \n(OTG_HS_DOEPMSK) on page 1452\nOTG_HS_DAINT\n0x818\nOTG_HS device all endpoints interrupt register (OTG_HS_DAINT) \non page 1453\nOTG_HS_DAINTMSK\n0x81C\nOTG_HS all endpoints interrupt mask register \n(OTG_HS_DAINTMSK) on page 1454\nOTG_HS_DVBUSDIS\n0x828\nOTG_HS device VBUS discharge time register \n(OTG_HS_DVBUSDIS) on page 1454\nOTG_HS_DVBUSPULSE\n0x82C\nOTG_HS device VBUS pulsing time register \n(OTG_HS_DVBUSPULSE) on page 1455\nOTG_HS_DTHRCTL\n0x830\nOTG_HS Device threshold control register (OTG_HS_DTHRCTL) \non page 1456\n\n\n<>\n\nRM0090 Rev 21\n1409/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS_DIEPEMPMSK\n0x834\nOTG_HS device IN endpoint FIFO empty interrupt mask register: \n(OTG_HS_DIEPEMPMSK) on page 1457\nOTG_HS_DEACHINT\n0x838\nOTG_HS device each endpoint interrupt register \n(OTG_HS_DEACHINT) on page 1457\nOTG_HS_DEACHINTMSK\n0x83C\nOTG_HS device each endpoint interrupt register mask \n(OTG_HS_DEACHINTMSK) on page 1458\nOTG_HS_DIEPEACHMSK1\n0x844\nOTG_HS device each in endpoint-1 interrupt register \n(OTG_HS_DIEPEACHMSK1) on page 1458\nOTG_HS_DOEPEACHMSK1\n0x884\nOTG_HS device each OUT endpoint-1 interrupt register \n(OTG_HS_DOEPEACHMSK1) on page 1459\nOTG_HS_DIEPCTLx\n0x900\n0x920\n...\n0x9A0\nOTG device endpoint-x control register (OTG_HS_DIEPCTLx) (x = \n0..5, where x = Endpoint_number) on page 1460\nOTG_HS_DIEPINTx\n0x908\nOTG_HS device endpoint-x interrupt register \n(OTG_HS_DIEPINTx) (x = 0..5, where x = Endpoint_number) on \npage 1467\nOTG_HS_DIEPTSIZ0\n0x910\nOTG_HS device IN endpoint 0 transfer size register \n(OTG_HS_DIEPTSIZ0) on page 1470\nOTG_HS_DIEPDMAx/\nOTG_HS_DOEPDMAx\n0x914/0xB14\nOTG_HS device endpoint-x DMA address register \n(OTG_HS_DIEPDMAx / OTG_HS_DOEPDMAx) (x = 0..5, where \nx = Endpoint_number) on page 1474\nOTG_HS_DTXFSTSx \n0x918\nOTG_HS device IN endpoint transmit FIFO status register \n(OTG_HS_DTXFSTSx) (x = 0..5, where x = Endpoint_number) on \npage 1473\nOTG_HS_DIEPTSIZx\n0x930\n0x950\n...\n0x9B0\nOTG_HS device endpoint-x transfer size register \n(OTG_HS_DIEPTSIZx) (x = 1..5, where x = Endpoint_number) on \npage 1472\nOTG_HS_DOEPCTL0\n0xB00\nOTG_HS device control OUT endpoint 0 control register \n(OTG_HS_DOEPCTL0) on page 1463\nOTG_HS_DOEPSIZ0\n0xB10\nOTG_HS device OUT endpoint 0 transfer size register \n(OTG_HS_DOEPTSIZ0) on page 1471\nOTG_HS_DOEPCTLx\n0xB20\n0xB40\n...\n0xBA0\nOTG_HS device endpoint-x control register \n(OTG_HS_DOEPCTLx) (x = 1..5, where x = Endpoint_number) on \npage 1464\nTable 211. Device-mode control and status registers (continued)\nAcronym\nOffset \naddress\nRegister name\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1410/1757\nRM0090 Rev 21\nData FIFO (DFIFO) access register map\nThese registers, available in both host and peripheral modes, are used to read or write the \nFIFO space for a specific endpoint or a channel, in a given direction. If a host channel is of \ntype IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type \nOUT, the FIFO can only be written on the channel.\n \nPower and clock gating CSR map\nThere is a single register for power and clock gating. It is available in both host and \nperipheral modes.\n \n35.12.2 \nOTG_HS global registers\nThese registers are available in both host and peripheral modes, and do not need to be \nreprogrammed when switching between these modes.\nOTG_HS_DOEPINTx\n0xB08\n0xB28\n...\n0xBA8\nOTG_HS device endpoint-x interrupt register \n(OTG_HS_DOEPINTx) (x = 0..5, where x = Endpoint_number) on \npage 1469\nOTG_HS_DOEPTSIZx\n0xB30\n0xB50\n...\n0xBB0\nOTG_HS device endpoint-x transfer size register \n(OTG_HS_DOEPTSIZx) (x = 1..5, where x = Endpoint_number) \non page 1473\nTable 211. Device-mode control and status registers (continued)\nAcronym\nOffset \naddress\nRegister name\nTable 212. Data FIFO (DFIFO) access register map\nFIFO access register section\nAddress range\nAccess\nDevice IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access\nDevice OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access\n0x1000–0x1FFC\nw\nr\nDevice IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access\nDevice OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access\n0x2000–0x2FFC\nw\nr\n...\n...\n...\nDevice IN Endpoint x(1)/Host OUT Channel x(1): DFIFO Write Access\nDevice OUT Endpoint x(1)/Host IN Channel x(1): DFIFO Read Access\n1.\nWhere x is 5 in peripheral mode and 11 in host mode.\n0xX000–0xXFFC\nw\nr\nTable 213. Power and clock gating control and status registers\nRegister name\nAcronym\nOffset address: 0xE00–0xFFF\nPower and clock gating control register\nOTG_HS_PCGCCTL\n0xE00-0xE04\nReserved\n-\n0xE05–0xFFF\n\n\n<>\n\nRM0090 Rev 21\n1411/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBit values in the register descriptions are expressed in binary unless otherwise specified.\nOTG_HS control and status register (OTG_HS_GOTGCTL)\nAddress offset: 0x000\nReset value: 0x0001 0000\nThe OTG control and status register controls the behavior and reflects the status of the OTG \nfunction of the core.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBSVLD\nASVLD\nDBCT\nCIDSTS\nReserved\nDHNPEN\nHSHNPEN\nHNPRQ\nHNGSCS\nReserved\nSRQ\nSRQSCS\nr\nr\nr\nr\nrw\nrw\nrw\nr\nrw\nr\nBits 31:20 Reserved, must be kept at reset value.\nBit 19 BSVLD: B-session valid\nIndicates the peripheral mode transceiver status.\n0: B-session is not valid.\n1: B-session is valid.\nIn OTG mode, you can use this bit to determine if the device is connected or disconnected.\nNote: Only accessible in peripheral mode.\nBit 18 ASVLD: A-session valid\nIndicates the host mode transceiver status.\n0: A-session is not valid\n1: A-session is valid\nNote: Only accessible in host mode.\nBit 17 DBCT: Long/short debounce time\nIndicates the debounce time of a detected connection.\n0: Long debounce time, used for physical connections (100 ms + 2.5 µs)\n1: Short debounce time, used for soft connections (2.5 µs)\nNote: Only accessible in host mode.\nBit 16 CIDSTS: Connector ID status\nIndicates the connector ID status on a connect event.\n0: The OTG_HS controller is in A-device mode\n1: The OTG_HS controller is in B-device mode\nNote: Accessible in both peripheral and host modes.\nBits 15:12 Reserved, must be kept at reset value.\nBit 11 DHNPEN: Device HNP enabled\nThe application sets this bit when it successfully receives a SetFeature.SetHNPEnable \ncommand from the connected USB host.\n0: HNP is not enabled in the application\n1: HNP is enabled in the application\nNote: Only accessible in peripheral mode.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1412/1757\nRM0090 Rev 21\nOTG_HS interrupt register (OTG_HS_GOTGINT)\nAddress offset: 0x04\nReset value: 0x0000 0000\nThe application reads this register whenever there is an OTG interrupt and clears the bits in \nthis register to clear the OTG interrupt.\nBit 10 HSHNPEN: Host set HNP enable\nThe application sets this bit when it has successfully enabled HNP (using the \nSetFeature.SetHNPEnable command) on the connected device.\n0: Host Set HNP is not enabled\n1: Host Set HNP is enabled\nNote: Only accessible in host mode.\nBit 9 HNPRQ: HNP request\nThe application sets this bit to initiate an HNP request to the connected USB host. The \napplication can clear this bit by writing a 0 when the host negotiation success status change \nbit in the OTG interrupt register (HNSSCHG bit in OTG_HS_GOTGINT) is set. The core \nclears this bit when the HNSSCHG bit is cleared.\n0: No HNP request\n1: HNP request\nNote: Only accessible in peripheral mode.\nBit 8 HNGSCS: Host negotiation success\nThe core sets this bit when host negotiation is successful. The core clears this bit when the \nHNP Request (HNPRQ) bit in this register is set.\n0: Host negotiation failure\n1: Host negotiation success\nNote: Only accessible in peripheral mode.\nBits 7:2 Reserved, must be kept at reset value.\nBit 1 SRQ: Session request\nThe application sets this bit to initiate a session request on the USB. The application can \nclear this bit by writing a 0 when the host negotiation success status change bit in the OTG \nInterrupt register (HNSSCHG bit in OTG_HS_GOTGINT) is set. The core clears this bit when \nthe HNSSCHG bit is cleared.\nIf you use the USB 1.1 full-speed serial transceiver interface to initiate the session request, \nthe application must wait until VBUS discharges to 0.2 V, after the B-Session Valid bit in this \nregister (BSVLD bit in OTG_HS_GOTGCTL) is cleared.\n0: No session request\n1: Session request\nNote: Only accessible in peripheral mode.\nBit 0 SRQSCS: Session request success\nThe core sets this bit when a session request initiation is successful.\n0: Session request failure\n1: Session request success\nNote: Only accessible in peripheral mode.\n\n\n<>\n\nRM0090 Rev 21\n1413/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDBCDNE\nADTOCHG\nHNGDET\nReserved\nHNSSCHG\nSRSSCHG\nReserved\nSEDET\nRes.\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nBits 31:20 Reserved, must be kept at reset value.\nBit 19 DBCDNE: Debounce done\nThe core sets this bit when the debounce is completed after the device connect. The \napplication can start driving USB reset after seeing this interrupt. This bit is only valid when \nthe HNP Capable or SRP Capable bit is set in the Core USB Configuration register (HNPCAP \nbit or SRPCAP bit in OTG_HS_GUSBCFG, respectively).\nNote: Only accessible in host mode.\nBit 18 ADTOCHG: A-device timeout change\nThe core sets this bit to indicate that the A-device has timed out while waiting for the B-device \nto connect.\nNote: Accessible in both peripheral and host modes.\nBit 17 HNGDET: Host negotiation detected\nThe core sets this bit when it detects a host negotiation request on the USB. \nNote: Accessible in both peripheral and host modes.\nBits 16:10 Reserved, must be kept at reset value.\nBit 9 HNSSCHG: Host negotiation success status change\nThe core sets this bit on the success or failure of a USB host negotiation request. The \napplication must read the host negotiation success bit of the OTG Control and Status register \n(HNGSCS in OTG_HS_GOTGCTL) to check for success or failure.\nNote: Accessible in both peripheral and host modes.\nBits 7:3 Reserved, must be kept at reset value.\nBit 8 SRSSCHG: Session request success status change\nThe core sets this bit on the success or failure of a session request. The application must \nread the session request success bit in the OTG Control and status register (SRQSCS bit in \nOTG_HS_GOTGCTL) to check for success or failure.\nNote: Accessible in both peripheral and host modes.\nBit 2 SEDET: Session end detected\nThe core sets this bit to indicate that the level of the voltage on VBUS is no longer valid for a \nB-device session when VBUS < 0.8 V.\nBits 1:0 Reserved, must be kept at reset value.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1414/1757\nRM0090 Rev 21\nOTG_HS AHB configuration register (OTG_HS_GAHBCFG)\nAddress offset: 0x008\nReset value: 0x0000 0000\nThis register can be used to configure the core after power-on or a change in mode. This \nregister mainly contains AHB system-related configuration parameters. Do not change this \nregister after the initial programming. The application must program this register before \nstarting any transactions on either the AHB or the USB.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPTXFELVL\nTXFELVL\nReserved\nDMAEN\nHBSTLEN\nGINT\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:20 Reserved, must be kept at reset value.\nBit 8 PTXFELVL: Periodic TxFIFO empty level\nIndicates when the periodic TxFIFO empty interrupt bit in the Core interrupt register (PTXFE \nbit in OTG_HS_GINTSTS) is triggered.\n0: PTXFE (in OTG_HS_GINTSTS) interrupt indicates that the Periodic TxFIFO is half empty\n1: PTXFE (in OTG_HS_GINTSTS) interrupt indicates that the Periodic TxFIFO is completely \nempty\nNote: Only accessible in host mode.\nBit 7 TXFELVL: TxFIFO empty level\nIn peripheral mode, this bit indicates when the IN endpoint Transmit FIFO empty interrupt \n(TXFE in OTG_HS_DIEPINTx.) is triggered.\n0: TXFE (in OTG_HS_DIEPINTx) interrupt indicates that the IN Endpoint TxFIFO is half \nempty\n1: TXFE (in OTG_HS_DIEPINTx) interrupt indicates that the IN Endpoint TxFIFO is \ncompletely empty\nNote: Only accessible in peripheral mode.\nBit 6 Reserved, must be kept at reset value.\nBits5 DMAEN: DMA enable\n0: The core operates in slave mode\n1: The core operates in DMA mode\nBits 4:1 HBSTLEN: Burst length/type\n0000 Single\n0001 INCR\n0011 INCR4\n0101 INCR8\n0111 INCR16\nOthers: Reserved \nBit 0 GINT: Global interrupt mask\nThis bit is used to mask or unmask the interrupt line assertion to the application. Irrespective \nof this bit setting, the interrupt status registers are updated by the core.\n0: Mask the interrupt assertion to the application.\n1: Unmask the interrupt assertion to the application\nNote: Accessible in both peripheral and host modes.\n\n\n<>\n\nRM0090 Rev 21\n1415/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS USB configuration register (OTG_HS_GUSBCFG)\nAddress offset: 0x00C\nReset value: 0x0000 1440\nThis register can be used to configure the core after power-on or a changing to host mode \nor peripheral mode. It contains USB and USB-PHY related configuration parameters. The \napplication must program this register before starting any transactions on either the AHB or \nthe USB. Do not make changes to this register after the initial programming.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCTXPKT\nFDMOD\nFHMOD\nReserved\nULPIIPD\nPTCI\nPCCI\nTSDPS\nULPIEVBUSI\nULPIEVBUSD\nULPICSM\nULPIAR\nULPIFSLS\nReserved\nPHYLPCS\nReserved\nTRDT\nHNPCAP\nSRPCAP\nReserved\nPHYSEL\nReserved\nTOCAL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 CTXPKT: Corrupt Tx packet\nThis bit is for debug purposes only. Never set this bit to 1.\nNote: Accessible in both peripheral and host modes.\nBit 30 FDMOD: Forced peripheral mode\nWriting a 1 to this bit forces the core to peripheral mode irrespective of the OTG_HS_ID input \npin.\n0: Normal mode\n1: Forced peripheral mode\nAfter setting the force bit, the application must wait at least 25 ms before the change takes \neffect.\nNote: Accessible in both peripheral and host modes.\nBit 29 FHMOD: Forced host mode\nWriting a 1 to this bit forces the core to host mode irrespective of the OTG_HS_ID input pin.\n0: Normal mode\n1: Forced host mode\nAfter setting the force bit, the application must wait at least 25 ms before the change takes \neffect.\nNote: Accessible in both peripheral and host modes.\nBits 28:26 Reserved, must be kept at reset value.\nBit 25 ULPIIPD: ULPI interface protect disable\nThis bit controls the circuitry built in the PHY to protect the ULPI interface when the link tri-\nstates stp and data. Any pull-up or pull-down resistors employed by this feature can be \ndisabled. Please refer to the ULPI specification for more details.\n0: Enables the interface protection circuit\n1: Disables the interface protection circuit \nBit 24 PTCI: Indicator pass through\nThis bit controls whether the complement output is qualified with the internal VBUS valid \ncomparator before being used in the VBUS state in the RX CMD. Please refer to the ULPI \nspecification for more details.\n0: Complement Output signal is qualified with the Internal VBUS valid comparator\n1: Complement Output signal is not qualified with the Internal VBUS valid comparator\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1416/1757\nRM0090 Rev 21\nBit 23 PCCI: Indicator complement\nThis bit controls the PHY to invert the ExternalVbusIndicator input signal, and generate the \ncomplement output. Please refer to the ULPI specification for more details.\n0: PHY does not invert the ExternalVbusIndicator signal\n1: PHY inverts ExternalVbusIndicator signal\nBit 22 TSDPS: TermSel DLine pulsing selection\nThis bit selects utmi_termselect to drive the data line pulse during SRP (session request \nprotocol).\n0: Data line pulsing using utmi_txvalid (default)\n1: Data line pulsing using utmi_termsel\nBit 21 ULPIEVBUSI: ULPI external VBUS indicator\nThis bit indicates to the ULPI PHY to use an external VBUS overcurrent indicator.\n0: PHY uses an internal VBUS valid comparator\n1: PHY uses an external VBUS valid comparator\nBit 20 ULPIEVBUSD: ULPI External VBUS Drive\nThis bit selects between internal or external supply to drive 5 V on VBUS, in the ULPI PHY.\n0: PHY drives VBUS using internal charge pump (default)\n1: PHY drives VBUS using external supply.\nBit 19 ULPICSM: ULPI Clock SuspendM\nThis bit sets the ClockSuspendM bit in the interface control register on the ULPI PHY. This bit \napplies only in the serial and carkit modes.\n0: PHY powers down the internal clock during suspend\n1: PHY does not power down the internal clock\nBit 18 ULPIAR: ULPI Auto-resume\nThis bit sets the AutoResume bit in the interface control register on the ULPI PHY.\n0: PHY does not use AutoResume feature\n1: PHY uses AutoResume feature\nBit 17 ULPIFSLS: ULPI FS/LS select\nThe application uses this bit to select the FS/LS serial interface for the ULPI PHY. This bit is \nvalid only when the FS serial transceiver is selected on the ULPI PHY. \n0: ULPI interface\n1: ULPI FS/LS serial interface\nBit 16\nReserved, must be kept at reset value.\nBit 15 PHYLPCS: PHY Low-power clock select\nThis bit selects either 480 MHz or 48 MHz (low-power) PHY mode. In FS and LS modes, the \nPHY can usually operate on a 48 MHz clock to save power.\n0: 480 MHz internal PLL clock\n1: 48 MHz external clock\nIn 480 MHz mode, the UTMI interface operates at either 60 or 30 MHz, depending on \nwhether the 8- or 16-bit data width is selected. In 48 MHz mode, the UTMI interface operates \nat 48 MHz in FS and LS modes.\nBit 14 Reserved, must be kept at reset value.\nBits 13:10 TRDT: USB turnaround time\nThese bits allows to set the turnaround time in PHY clocks. They must be configured \naccording to Table 214: TRDT values, depending on the application AHB frequency. Higher \nTRDT values allow stretching the USB response time to IN tokens in order to compensate for \nlonger AHB read access latency to the Data FIFO. \n\n\n<>\n\nRM0090 Rev 21\n1417/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n \n \nBit 9 HNPCAP: HNP-capable\nThe application uses this bit to control the OTG_HS controller’s HNP capabilities.\n0: HNP capability is not enabled\n1: HNP capability is enabled\nNote: Accessible in both peripheral and host modes.\nBit 8 SRPCAP: SRP-capable\nThe application uses this bit to control the OTG_HS controller’s SRP capabilities. If the core \noperates as a nonSRP-capable B-device, it cannot request the connected A-device (host) to \nactivate VBUS and start a session.\n0: SRP capability is not enabled\n1: SRP capability is enabled\nNote: Accessible in both peripheral and host modes.\nBit 7 Reserved, must be kept at reset value.\nBit 6 PHYSEL: USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select\n0: USB 2.0 high-speed ULPI PHY\n1: USB 1.1 full-speed serial transceiver \nBits 5:3\nReserved, must be kept at reset value.\nBits 2:0 TOCAL: FS timeout calibration\nThe number of PHY clocks that the application programs in this field is added to the full-\nspeed interpacket timeout duration in the core to account for any additional delays \nintroduced by the PHY. This can be required, because the delay introduced by the PHY in \ngenerating the line state condition can vary from one PHY to another.\nThe USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The \napplication must program this field based on the speed of enumeration. The number of bit \ntimes added per PHY clock is 0.25 bit times.\nTable 214. TRDT values\nAHB frequency range (MHz)\nTRDT minimum value\nMin.\nMax\n30\n-\n0x9\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1418/1757\nRM0090 Rev 21\nOTG_HS reset register (OTG_HS_GRSTCTL)\nAddress offset: 0x010\nReset value: 0x8000 0000\nThe application uses this register to reset various hardware features inside the core.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nAHBIDL\nDMAREQ\nReserved\nTXFNUM\nTXFFLSH\nRXFFLSH\nReserved\nFCRST\nHSRST\nCSRST\nr\nr\nrw\nrs\nrs\nrs\nrs\nrs\nBit 31 AHBIDL: AHB master idle\nIndicates that the AHB master state machine is in the Idle condition.\nNote: Accessible in both peripheral and host modes.\nBit 30 DMAREQ: DMA request signal\nThis bit indicates that the DMA request is in progress. Used for debug.\nBits 29:11\nReserved, must be kept at reset value.\nBits 10:6 TXFNUM: TxFIFO number\nThis is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not \nbe changed until the core clears the TxFIFO Flush bit.\n00000:\n– Nonperiodic TxFIFO flush in host mode\n– Tx FIFO 0 flush in peripheral mode\n00001:\n– Periodic TxFIFO flush in host mode\n– TXFIFO 1 flush in peripheral mode \n00010: TXFIFO 2 flush in peripheral mode \n...\n00101: TXFIFO 15 flush in peripheral mode \n10000: Flush all the transmit FIFOs in peripheral or host mode.\nNote: Accessible in both peripheral and host modes.\nBit 5 TXFFLSH: TxFIFO flush\nThis bit selectively flushes a single or all transmit FIFOs, but cannot do so if the core is in the \nmidst of a transaction.\nThe application must write this bit only after checking that the core is neither writing to the \nTxFIFO nor reading from the TxFIFO. Verify using these registers:\n–\nRead: the NAK effective interrupt ensures the core is not reading from the FIFO\n–\nWrite: the AHBIDL bit in OTG_HS_GRSTCTL ensures that the core is not writing \nanything to the FIFO\nNote: Accessible in both peripheral and host modes.\n\n\n<>\n\nRM0090 Rev 21\n1419/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBit 4 RXFFLSH: RxFIFO flush\nThe application can flush the entire RxFIFO using this bit, but must first ensure that the core \nis not in the middle of a transaction.\nThe application must only write to this bit after checking that the core is neither reading from \nthe RxFIFO nor writing to the RxFIFO.\nThe application must wait until the bit is cleared before performing any other operation. This \nbit requires 8 clocks (slowest of PHY or AHB clock) to be cleared.\nNote: Accessible in both peripheral and host modes.\nBit 3\nReserved, must be kept at reset value.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1420/1757\nRM0090 Rev 21\nBit 2 FCRST: Host frame counter reset\nThe application writes this bit to reset the (micro) frame number counter inside the core. \nWhen the (micro) frame counter is reset, the subsequent SOF sent out by the core has a \nframe number of 0.\nNote: Only accessible in host mode.\nBit 1 HSRST: HCLK soft reset\nThe application uses this bit to flush the control logic in the AHB Clock domain. Only AHB \nClock Domain pipelines are reset.\nFIFOs are not flushed with this bit.\nAll state machines in the AHB clock domain are reset to the Idle state after terminating the \ntransactions on the AHB, following the protocol.\nCSR control bits used by the AHB clock domain state machines are cleared.\nTo clear this interrupt, status mask bits that control the interrupt status and are generated by \nthe AHB clock domain state machine are cleared.\nBecause interrupt status bits are not cleared, the application can get the status of any core \nevents that occurred after it set this bit.\nThis is a self-clearing bit that the core clears after all necessary logic is reset in the core. This \ncan take several clocks, depending on the core’s current state.\nNote: Accessible in both peripheral and host modes.\nBit 0 CSRST: Core soft reset\nResets the HCLK and PCLK domains as follows:\nClears the interrupts and all the CSR register bits except for the following bits:\n– RSTPDMODL bit in OTG_HS_PCGCCTL\n– GAYEHCLK bit in OTG_HS_PCGCCTL\n– PWRCLMP bit in OTG_HS_PCGCCTL\n– STPPCLK bit in OTG_HS_PCGCCTL\n– FSLSPCS bit in OTG_HS_HCFG\n– DSPD bit in OTG_HS_DCFG\nAll module state machines (except for the AHB slave unit) are reset to the Idle state, and all \nthe transmit FIFOs and the receive FIFO are flushed.\nAny transactions on the AHB Master are terminated as soon as possible, after completing the \nlast data phase of an AHB transfer. Any transactions on the USB are terminated immediately.\nThe application can write to this bit any time it wants to reset the core. This is a self-clearing bit \nand the core clears this bit after all the necessary logic is reset in the core, which can take \nseveral clocks, depending on the current state of the core. Once this bit has been cleared, the \nsoftware must wait at least 3 PHY clocks before accessing the PHY domain (synchronization \ndelay). The software must also check that bit 31 in this register is set to 1 (AHB Master is Idle) \nbefore starting any operation.\nTypically, the software reset is used during software development and also when you \ndynamically change the PHY selection bits in the above listed USB configuration registers. \nWhen you change the PHY, the corresponding clock for the PHY is selected and used in the \nPHY domain. Once a new clock is selected, the PHY domain has to be reset for proper \noperation.\nNote: Accessible in both peripheral and host modes.\n\n\n<>\n\nRM0090 Rev 21\n1421/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS core interrupt register (OTG_HS_GINTSTS)\nAddress offset: 0x014\nReset value: 0x0400 0020\nThis register interrupts the application for system-level events in the current mode \n(peripheral mode or host mode).\nSome of the bits in this register are valid only in host mode, while others are valid in \nperipheral mode only. This register also indicates the current mode. To clear the interrupt \nstatus bits of the rc_w1 type, the application must write 1 into the bit.\nThe FIFO status interrupts are read-only; once software reads from or writes to the FIFO \nwhile servicing these interrupts, FIFO interrupt conditions are cleared automatically.\nThe application must clear the OTG_HS_GINTSTS register at initialization before \nunmasking the interrupt bit to avoid any interrupts generated prior to initialization.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nWKUINT\nSRQINT\nDISCINT\nCIDSCHG\nReserved\nPTXFE\nHCINT\nHPRTINT\nReserved\nDATAFSUSP\nIPXFR/INCOMPISOOUT\nIISOIXFR\nOEPINT\nIEPINT\nReserved\nEOPF\nISOODRP\nENUMDNE\nUSBRST\nUSBSUSP\nESUSP\nReserved\nGONAKEFF\nGINAKEFF\nNPTXFE\nRXFLVL\nSOF\nOTGINT\nMMIS\nCMOD\nrc_w1\nr\nr\nr\nrc_w1\nr\nr\nrc_w1\nr\nr\nr\nr\nrc_w1\nr\nrc_w1\nr\nBit 31 WKUPINT: Resume/remote wake-up detected interrupt\nIn peripheral mode, this interrupt is asserted when a resume is detected on the USB. In host \nmode, this interrupt is asserted when a remote wake-up is detected on the USB.\nNote: Accessible in both peripheral and host modes.\nBit 30 SRQINT: Session request/new session detected interrupt\nIn host mode, this interrupt is asserted when a session request is detected from the device. \nIn peripheral mode, this interrupt is asserted when VBUS is in the valid range for a B-device \ndevice. Accessible in both peripheral and host modes.\nBit 29 DISCINT: Disconnect detected interrupt\nAsserted when a device disconnect is detected.\nNote: Only accessible in host mode.\nBit 28 CIDSCHG: Connector ID status change\nThe core sets this bit when there is a change in connector ID status.\nNote: Accessible in both peripheral and host modes.\nBit 27 Reserved, must be kept at reset value.\nBit 26 PTXFE: Periodic TxFIFO empty\nAsserted when the periodic transmit FIFO is either half or completely empty and there is \nspace for at least one entry to be written in the periodic request queue. The half or \ncompletely empty status is determined by the periodic TxFIFO empty level bit in the Core \nAHB configuration register (PTXFELVL bit in OTG_HS_GAHBCFG).\nNote: Only accessible in host mode.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1422/1757\nRM0090 Rev 21\nBit 25 HCINT: Host channels interrupt\nThe core sets this bit to indicate that an interrupt is pending on one of the channels of the \ncore (in host mode). The application must read the host all channels interrupt \n(OTG_HS_HAINT) register to determine the exact number of the channel on which the \ninterrupt occurred, and then read the corresponding host channel-x interrupt \n(OTG_HS_HCINTx) register to determine the exact cause of the interrupt. The application \nmust clear the appropriate status bit in the OTG_HS_HCINTx register to clear this bit.\nNote: Only accessible in host mode.\nBit 24 HPRTINT: Host port interrupt\nThe core sets this bit to indicate a change in port status of one of the OTG_HS controller \nports in host mode. The application must read the host port control and status \n(OTG_HS_HPRT) register to determine the exact event that caused this interrupt. The \napplication must clear the appropriate status bit in the host port control and status register to \nclear this bit.\nNote: Only accessible in host mode.\nBits 23 Reserved, must be kept at reset value.\nBit 22 DATAFSUSP: Data fetch suspended\nThis interrupt is valid only in DMA mode. This interrupt indicates that the core has stopped \nfetching data for IN endpoints due to the unavailability of TxFIFO space or request queue \nspace. This interrupt is used by the application for an endpoint mismatch algorithm. For \nexample, after detecting an endpoint mismatch, the application:\n–\nSets a global nonperiodic IN NAK handshake\n–\nDisables IN endpoints \n–\nFlushes the FIFO\n–\nDetermines the token sequence from the IN token sequence learning queue\n–\nRe-enables the endpoints\n–\nClears the global nonperiodic IN NAK handshake If the global nonperiodic IN NAK \nis cleared, the core has not yet fetched data for the IN endpoint, and the IN token is \nreceived: the core generates an “IN token received when FIFO empty” interrupt. \nThe OTG then sends a NAK response to the host. To avoid this scenario, the \napplication can check the FetSusp interrupt in OTG_HS_GINTSTS, which ensures \nthat the FIFO is full before clearing a global NAK handshake. Alternatively, the \napplication can mask the “IN token received when FIFO empty” interrupt when \nclearing a global IN NAK handshake.\nBit 21 IPXFR: Incomplete periodic transfer\nIn host mode, the core sets this interrupt bit when there are incomplete periodic transactions \nstill pending, which are scheduled for the current frame.\nNote: Only accessible in host mode.\nINCOMPISOOUT: Incomplete isochronous OUT transfer\nIn peripheral mode, the core sets this interrupt to indicate that there is at least one \nisochronous OUT endpoint on which the transfer is not completed in the current frame. This \ninterrupt is asserted along with the End of periodic frame interrupt (EOPF) bit in this register.\nNote: Only accessible in peripheral mode.\nBit 20 IISOIXFR: Incomplete isochronous IN transfer\nThe core sets this interrupt to indicate that there is at least one isochronous IN endpoint on \nwhich the transfer is not completed in the current frame. This interrupt is asserted along with \nthe End of periodic frame interrupt (EOPF) bit in this register.\nNote: Only accessible in peripheral mode.\n\n\n<>\n\nRM0090 Rev 21\n1423/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBit 19 OEPINT: OUT endpoint interrupt\nThe core sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of \nthe core (in peripheral mode). The application must read the device all endpoints interrupt \n(OTG_HS_DAINT) register to determine the exact number of the OUT endpoint on which \nthe interrupt occurred, and then read the corresponding device OUT Endpoint-x Interrupt \n(OTG_HS_DOEPINTx) register to determine the exact cause of the interrupt. The \napplication must clear the appropriate status bit in the corresponding OTG_HS_DOEPINTx \nregister to clear this bit.\nNote: Only accessible in peripheral mode.\nBit 18 IEPINT: IN endpoint interrupt\nThe core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the \ncore (in peripheral mode). The application must read the device All Endpoints Interrupt \n(OTG_HS_DAINT) register to determine the exact number of the IN endpoint on which the \ninterrupt occurred, and then read the corresponding device IN Endpoint-x interrupt \n(OTG_HS_DIEPINTx) register to determine the exact cause of the interrupt. The application \nmust clear the appropriate status bit in the corresponding OTG_HS_DIEPINTx register to \nclear this bit.\nNote: Only accessible in peripheral mode.\nBits 17:16 Reserved, must be kept at reset value.\nBit 15 EOPF: End of periodic frame interrupt\nIndicates that the period specified in the periodic frame interval field of the device \nconfiguration register (PFIVL bit in OTG_HS_DCFG) has been reached in the current frame.\nNote: Only accessible in peripheral mode.\nBit 14 ISOODRP: Isochronous OUT packet dropped interrupt\nThe core sets this bit when it fails to write an isochronous OUT packet into the RxFIFO \nbecause the RxFIFO does not have enough space to accommodate a maximum size packet \nfor the isochronous OUT endpoint.\nNote: Only accessible in peripheral mode.\nBit 13 ENUMDNE: Enumeration done\nThe core sets this bit to indicate that speed enumeration is complete. The application must \nread the device Status (OTG_HS_DSTS) register to obtain the enumerated speed.\nNote: Only accessible in peripheral mode.\nBit 12 USBRST: USB reset\nThe core sets this bit to indicate that a reset is detected on the USB.\nNote: Only accessible in peripheral mode.\nBit 11 USBSUSP: USB suspend\nThe core sets this bit to indicate that a suspend was detected on the USB. The core enters \nthe Suspended state when there is no activity on the data lines for a period of 3 ms.\nNote: Only accessible in peripheral mode.\nBit 10 ESUSP: Early suspend\nThe core sets this bit to indicate that an Idle state has been detected on the USB for 3 ms.\nNote: Only accessible in peripheral mode.\nBits 9:8\nReserved, must be kept at reset value.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1424/1757\nRM0090 Rev 21\nBit 7 GONAKEFF: Global OUT NAK effective\nIndicates that the Set global OUT NAK bit in the Device control register (SGONAK bit in \nOTG_HS_DCTL), set by the application, has taken effect in the core. This bit can be cleared \nby writing the Clear global OUT NAK bit in the Device control register (CGONAK bit in \nOTG_HS_DCTL).\nNote: Only accessible in peripheral mode.\nBit 6 GINAKEFF: Global IN nonperiodic NAK effective\nIndicates that the Set global nonperiodic IN NAK bit in the Device control register (SGINAK \nbit in OTG_HS_DCTL), set by the application, has taken effect in the core. That is, the core \nhas sampled the Global IN NAK bit set by the application. This bit can be cleared by clearing \nthe Clear global nonperiodic IN NAK bit in the Device control register (CGINAK bit in \nOTG_HS_DCTL).\nThis interrupt does not necessarily mean that a NAK handshake is sent out on the USB. The \nSTALL bit takes precedence over the NAK bit.\nNote: Only accessible in peripheral mode.\nBit 5 NPTXFE: Nonperiodic TxFIFO empty\nThis interrupt is asserted when the nonperiodic TxFIFO is either half or completely empty, \nand there is space in at least one entry to be written to the nonperiodic transmit request \nqueue. The half or completely empty status is determined by the nonperiodic TxFIFO empty \nlevel bit in the OTG_HS_GAHBCFG register (TXFELVL bit in OTG_HS_GAHBCFG). \nNote: Only accessible in host mode.\nBit 4 RXFLVL: RxFIFO nonempty\nIndicates that there is at least one packet pending to be read from the RxFIFO.\nNote: Accessible in both host and peripheral modes.\nBit 3 SOF: Start of frame\nIn host mode, the core sets this bit to indicate that an SOF (FS), or Keep-Alive (LS) is \ntransmitted on the USB. The application must write a 1 to this bit to clear the interrupt.\nIn peripheral mode, in the core sets this bit to indicate that an SOF token has been received \non the USB. The application can read the Device Status register to get the current frame \nnumber. This interrupt is seen only when the core is operating in FS.\nNote: Accessible in both host and peripheral modes.\nBit 2 OTGINT: OTG interrupt\nThe core sets this bit to indicate an OTG protocol event. The application must read the OTG \nInterrupt Status (OTG_HS_GOTGINT) register to determine the exact event that caused this \ninterrupt. The application must clear the appropriate status bit in the OTG_HS_GOTGINT \nregister to clear this bit.\nNote: Accessible in both host and peripheral modes.\nBit 1 MMIS: Mode mismatch interrupt\nThe core sets this bit when the application is trying to access:\nA host mode register, when the core is operating in peripheral mode\nA peripheral mode register, when the core is operating in host mode\nThe register access is completed on the AHB with an OKAY response, but is ignored by the \ncore internally and does not affect the operation of the core.\nNote: Accessible in both host and peripheral modes.\nBit 0 CMOD: Current mode of operation\nIndicates the current mode.\n0: Peripheral mode\n1: Host mode\nNote: Accessible in both host and peripheral modes.\n\n\n<>\n\nRM0090 Rev 21\n1425/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS interrupt mask register (OTG_HS_GINTMSK)\nAddress offset: 0x018\nReset value: 0x0000 0000\nThis register works with the Core interrupt register to interrupt the application. When an \ninterrupt bit is masked, the interrupt associated with that bit is not generated. However, the \nCore Interrupt (OTG_HS_GINTSTS) register bit corresponding to that interrupt is still set.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nWUIM\nSRQIM\nDISCINT\nCIDSCHGM\nReserved\nPTXFEM\nHCIM\nPRTIM\nReserved\nFSUSPM\nIPXFRM/IISOOXFRM\nIISOIXFRM\nOEPINT\nIEPINT\nReserved\nEOPFM\nISOODRPM\nENUMDNEM\nUSBRST\nUSBSUSPM\nESUSPM\nReserved\nGONAKEFFM\nGINAKEFFM\nNPTXFEM\nRXFLVLM\nSOFM\nOTGINT\nMMISM\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 WUIM: Resume/remote wake-up detected interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both host and peripheral modes.\nBit 30 SRQIM: Session request/new session detected interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both host and peripheral modes.\nBit 29 DISCINT: Disconnect detected interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both host and peripheral modes.\nBit 28 CIDSCHGM: Connector ID status change mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both host and peripheral modes.\nBit 27 Reserved, must be kept at reset value.\nBit 26 PTXFEM: Periodic TxFIFO empty mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in host mode.\nBit 25 HCIM: Host channels interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in host mode.\nBit 24 PRTIM: Host port interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in host mode.\nBit 23 Reserved, must be kept at reset value.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1426/1757\nRM0090 Rev 21\nBit 22 FSUSPM: Data fetch suspended mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 21 IPXFRM: Incomplete periodic transfer mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in host mode.\nIISOOXFRM: Incomplete isochronous OUT transfer mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 20 IISOIXFRM: Incomplete isochronous IN transfer mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 19 OEPINT: OUT endpoints interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 18 IEPINT: IN endpoints interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBits 17:16 Reserved, must be kept at reset value.\nBit 15 EOPFM: End of periodic frame interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 14 ISOODRPM: Isochronous OUT packet dropped interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 13 ENUMDNEM: Enumeration done mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 12 USBRST: USB reset mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 11 USBSUSPM: USB suspend mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\n\n\n<>\n\nRM0090 Rev 21\n1427/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBit 10 ESUSPM: Early suspend mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBits 9:8 Reserved, must be kept at reset value.\nBit 7 GONAKEFFM: Global OUT NAK effective mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 6 GINAKEFFM: Global nonperiodic IN NAK effective mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 5 NPTXFEM: Nonperiodic TxFIFO empty mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both peripheral and host modes.\nBit 4 RXFLVLM: Receive FIFO nonempty mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both peripheral and host modes.\nBit 3 SOFM: Start of frame mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both peripheral and host modes.\nBit 2 OTGINT: OTG interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both peripheral and host modes.\nBit 1 MMISM: Mode mismatch interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both peripheral and host modes.\nBit 0 Reserved, must be kept at reset value.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1428/1757\nRM0090 Rev 21\nOTG_HS Receive status debug read/OTG status read and pop registers \n(OTG_HS_GRXSTSR/OTG_HS_GRXSTSP)\nAddress offset for Read: 0x01C\nAddress offset for Pop: 0x020\nReset value: 0x0000 0000\nA read to the Receive status debug read register returns the contents of the top of the \nReceive FIFO. A read to the Receive status read and pop register additionally pops the top \ndata entry out of the RxFIFO.\nThe receive status contents must be interpreted differently in host and peripheral modes. \nThe core ignores the receive status pop/read when the receive FIFO is empty and returns a \nvalue of 0x0000 0000. The application must only pop the Receive Status FIFO when the \nReceive FIFO nonempty bit of the Core interrupt register (RXFLVL bit in \nOTG_HS_GINTSTS) is asserted.\nHost mode:\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPKTSTS\nDPID\nBCNT\nCHNUM\nr\nr\nr\nr\nBits 31:21 Reserved, must be kept at reset value.\nBits 20:17 PKTSTS: Packet status\nIndicates the status of the received packet\n0010: IN data packet received\n0011: IN transfer completed (triggers an interrupt)\n0101: Data toggle error (triggers an interrupt)\n0111: Channel halted (triggers an interrupt)\nOthers: Reserved\nBits 16:15 DPID: Data PID\nIndicates the Data PID of the received packet\n00: DATA0\n10: DATA1\n01: DATA2\n11: MDATA\nBits 14:4 BCNT: Byte count\nIndicates the byte count of the received IN data packet.\nBits 3:0 CHNUM: Channel number\nIndicates the channel number to which the current received packet belongs.\n\n\n<>\n\nRM0090 Rev 21\n1429/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nPeripheral mode:\n \n \nOTG_HS Receive FIFO size register (OTG_HS_GRXFSIZ)\nAddress offset: 0x024\nReset value: 0x0000 0400\nThe application can program the RAM size that must be allocated to the RxFIFO.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFRMNUM\nPKTSTS\nDPID\nBCNT\nEPNUM\nr\nr\nr\nr\nr\nBits 31:25 Reserved, must be kept at reset value.\nBits 24:21 FRMNUM: Frame number\nThis is the least significant 4 bits of the frame number in which the packet is received on the \nUSB. This field is supported only when isochronous OUT endpoints are supported.\nBits 20:17 PKTSTS: Packet status\nIndicates the status of the received packet\n0001: Global OUT NAK (triggers an interrupt)\n0010: OUT data packet received\n0011: OUT transfer completed (triggers an interrupt)\n0100: SETUP transaction completed (triggers an interrupt)\n0110: SETUP data packet received\nOthers: Reserved\nBits 16:15 DPID: Data PID\nIndicates the Data PID of the received OUT data packet\n00: DATA0\n10: DATA1\n01: DATA2\n11: MDATA\nBits 14:4 BCNT: Byte count\nIndicates the byte count of the received data packet.\nBits 3:0 EPNUM: Endpoint number\nIndicates the endpoint number to which the current received packet belongs.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRXFD\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 RXFD: RxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nMaximum value is 1024\nThe power-on reset value of this register is specified as the largest Rx data FIFO depth.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1430/1757\nRM0090 Rev 21\nOTG_HS nonperiodic transmit FIFO size/Endpoint 0 transmit FIFO size \nregister (OTG_HS_GNPTXFSIZ/OTG_HS_TX0FSIZ)\nAddress offset: 0x028\nReset value: 0x0000 0200\nHost mode:\n \nPeripheral mode:\n \n \nOTG_HS nonperiodic transmit FIFO/queue status register \n(OTG_HS_GNPTXSTS)\nAddress offset: 0x02C\nReset value: 0x0008 0400\nNote:\nIn peripheral mode, this register is not valid.\nThis read-only register contains the free space information for the nonperiodic TxFIFO and \nthe nonperiodic transmit request queue.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nNPTXFD\nNPTXFSA\nrw\nrw\nBits 31:16 NPTXFD: Nonperiodic TxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nMaximum value is 1024\nBits 15:0 NPTXFSA: Nonperiodic transmit RAM start address\nThis field contains the memory start address for nonperiodic transmit FIFO RAM.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTX0FD\nTX0FSA\nr/rw\nr/rw\nBits 31:16 T0XFD: Endpoint 0 TxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nMaximum value is 256\nBits 15:0 TX0FSA: Endpoint 0 transmit RAM start address\nThis field contains the memory start address for Endpoint 0 transmit FIFO RAM.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNPTXQTOP\nNPTQXSAV\nNPTXFSAV\nr\nr\nr\n\n\n<>\n\nRM0090 Rev 21\n1431/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n \nOTG_HS general core configuration register (OTG_HS_GCCFG)\nAddress offset: 0x038\nReset value: 0x0000 XXXX\n \nBit 31 Reserved, must be kept at reset value.\nBits 30:24 NPTXQTOP: Top of the nonperiodic transmit request queue\nEntry in the nonperiodic Tx request queue that is currently being processed by the MAC.\nBits [30:27]: Channel/endpoint number\nBits [26:25]:\n–\n00: IN/OUT token\n–\n01: Zero-length transmit packet (device IN/host OUT)\n–\n10: PING/CSPLIT token \n–\n11: Channel halt command\nBit [24]: Terminate (last entry for selected channel/endpoint)\nBits 23:16 NPTQXSAV: Nonperiodic transmit request queue space available\nIndicates the amount of free space available in the nonperiodic transmit request queue. \nThis queue holds both IN and OUT requests in host mode. Peripheral mode has only IN \nrequests.\n00: Nonperiodic transmit request queue is full\n01: dx1 location available\n10: dx2 locations available\nbxn: dxn locations available (0 ≤n ≤dx8)\nOthers: Reserved\nBits 15:0 NPTXFSAV: Nonperiodic TxFIFO space available\nIndicates the amount of free space available in the nonperiodic TxFIFO.\nValues are in terms of 32-bit words.\n00: Nonperiodic TxFIFO is full\n01: dx1 word available\n10: dx2 words available\n0xn: dxn words available (where 0 ≤n ≤dx1024)\nOthers: Reserved\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNOVBUSSENS\nSOFOUTEN\nVBUSBSEN\nVBUSASEN\nI2CPADEN\n.PWRDWN\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1432/1757\nRM0090 Rev 21\n \nOTG_HS core ID register (OTG_HS_CID)\nAddress offset: 0x03C\nReset value:0x0000 1100\nThis is a register containing the Product ID as reset value.\n \n \nOTG_HS Host periodic transmit FIFO size register (OTG_HS_HPTXFSIZ)\nAddress offset: 0x100\nReset value: 0x0200 0800\nBits 31:22 Reserved, must be kept at reset value.\nBit 21 NOVBUSSENS: VBUS sensing disable option\nWhen this bit is set, VBUS is considered internally to be always at VBUS valid level (5 V). This \noption removes the need for a dedicated VBUS pad, and leave this pad free to be used for \nother purposes such as a shared functionality. VBUS connection can be remapped on \nanother general purpose input pad and monitored by software. \nThis option is only suitable for host-only or device-only applications. \n0: VBUS sensing available by hardware \n1: VBUS sensing not available by hardware. \nBit 20 SOFOUTEN: SOF output enable\n0: SOF pulse not available on PAD\n1: SOF pulse available on PAD\nBit 19 VBUSBSEN: Enable the VBUS sensing “B” device\n0: VBUS sensing “B” disabled\n1: VBUS sensing “B” enabled\nBit 18 VBUSASEN: Enable the VBUS sensing “A” device\n0: VBUS sensing “A” disabled\n1: VBUS sensing “A” enabled\nBit 17 I2CPADEN: Enable I2C bus connection for the external I2C PHY interface.\n0: I2C bus disabled\n1: I2C bus enabled\nBit 16 PWRDWN: Power down\nUsed to activate the transceiver in transmission/reception\n0: Power down active\n1: Power down deactivated (“Transceiver active”)\nBits 15:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPRODUCT_ID\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 PRODUCT_ID: Product ID field\nApplication-programmable ID field.\n\n\n<>\n\nRM0090 Rev 21\n1433/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n \n \nOTG_HS device IN endpoint transmit FIFO size register (OTG_HS_DIEPTXFx) \n(x = 1..5, where x is the FIFO_number)\nAddress offset: 0x104 + 0x04 * (x - 1)\nReset value: 0x02000400\n \n \n35.12.3 \nHost-mode registers\nBit values in the register descriptions are expressed in binary unless otherwise specified.\nHost-mode registers affect the operation of the core in the host mode. Host mode registers \nmust not be accessed in peripheral mode, as the results are undefined. Host mode registers \ncan be categorized as follows:\nOTG_HS host configuration register (OTG_HS_HCFG)\nAddress offset: 0x400\nReset value: 0x0000 0000\nThis register configures the core after power-on. Do not change to this register after \ninitializing the host.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPTXFD\nPTXSA\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 PTXFD: Host periodic TxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nMaximum value is 512\nBits 15:0 PTXSA: Host periodic TxFIFO start address\nThe power-on reset value of this register is the sum of the largest Rx data FIFO depth and \nlargest nonperiodic Tx data FIFO depth.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nINEPTXFD\nINEPTXSA\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 INEPTXFD: IN endpoint TxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nMaximum value is 512\nThe power-on reset value of this register is specified as the largest IN endpoint FIFO \nnumber depth.\nBits 15:0 INEPTXSA: IN endpoint FIFOx transmit RAM start address\nThis field contains the memory start address for IN endpoint transmit FIFOx. The address \nmust be aligned with a 32-bit memory location. \n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1434/1757\nRM0090 Rev 21\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFSLSS\nFSLSPCS\nr\nrw\nrw\nBits 31:3 Reserved, must be kept at reset value.\nBit 2 FSLSS: FS- and LS-only support\nThe application uses this bit to control the core’s enumeration speed. Using this bit, the \napplication can make the core enumerate as an FS host, even if the connected device \nsupports HS traffic. Do not make changes to this field after initial programming.\n0: HS/FS/LS, based on the maximum speed supported by the connected device \n1: FS/LS-only, even if the connected device can support HS (read-only)\nBits 1:0 FSLSPCS: FS/LS PHY clock select\nWhen the core is in FS host mode:\n01: PHY clock is running at 48 MHz\nOthers: Reserved\nWhen the core is in LS host mode:\n00: Reserved\n01: PHY clock is running at 48 MHz.\n10: Select 6 MHz PHY clock frequency\n11: Reserved\nNote: The FSLSPCS bit must be set on a connection event according to the speed of the \nconnected device. A software reset must be performed after changing this bit.\n\n\n<>\n\nRM0090 Rev 21\n1435/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS Host frame interval register (OTG_HS_HFIR)\nAddress offset: 0x404\nReset value: 0x0000 EA60\nThis register stores the frame interval information for the current speed to which the \nOTG_HS controller has enumerated.\n \n \nOTG_HS host frame number/frame time remaining register \n(OTG_HS_HFNUM)\nAddress offset: 0x408\nReset value: 0x0000 3FFF\nThis register indicates the current frame number. It also indicates the time remaining (in \nterms of the number of PHY clocks) in the current frame.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFRIVL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 FRIVL: Frame interval\nThe value that the application programs to this field specifies the interval between two \nconsecutive SOFs (FS), micro-SOFs (HS) or Keep-Alive tokens (LS). This field contains the \nnumber of PHY clocks that constitute the required frame interval. The application can write a \nvalue to this register only after the Port enable bit of the host port control and status register \n(PENA bit in OTG_HS_HPRT) has been set. If no value is programmed, the core calculates \nthe value based on the PHY clock specified in the FS/LS PHY Clock Select field of the Host \nconfiguration register (FSLSPCS in OTG_HS_HCFG):\nframe duration × PHY clock frequency\n– Frame interval = 1 ms × (FRIVL - 1)\nNote: The FRIVL bit can be modified whenever the application needs to change the Frame \ninterval time.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFTREM\nFRNUM\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 FTREM: Frame time remaining\nIndicates the amount of time remaining in the current frame, in terms of PHY clocks. This \nfield decrements on each PHY clock. When it reaches zero, this field is reloaded with the \nvalue in the Frame interval register and a new SOF is transmitted on the USB.\nBits 15:0 FRNUM: Frame number\nThis field increments when a new SOF is transmitted on the USB, and is cleared to 0 when \nit reaches 0x3FFF.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1436/1757\nRM0090 Rev 21\nOTG_HS_Host periodic transmit FIFO/queue status register \n(OTG_HS_HPTXSTS)\nAddress offset: 0x410\nReset value: 0x0008 0100\nThis read-only register contains the free space information for the periodic TxFIFO and the \nperiodic transmit request queue.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPTXQTOP\nPTXQSAV\nPTXFSAVL\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:24 PTXQTOP: Top of the periodic transmit request queue\nThis indicates the entry in the periodic Tx request queue that is currently being processed by \nthe MAC.\nThis register is used for debugging.\nBit [31]: Odd/Even frame\n–\n0: send in even (micro) frame\n–\n1: send in odd (micro) frame\nBits [30:27]: Channel/endpoint number\nBits [26:25]: Type\n–\n00: IN/OUT\n–\n01: Zero-length packet\n–\n11: Disable channel command\nBit [24]: Terminate (last entry for the selected channel/endpoint)\nBits 23:16 PTXQSAV: Periodic transmit request queue space available\nIndicates the number of free locations available to be written in the periodic transmit request \nqueue. This queue holds both IN and OUT requests.\n00: Periodic transmit request queue is full\n01: dx1 location available\n10: dx2 locations available\nbxn: dxn locations available (0 ≤dxn ≤PTXFD)\nOthers: Reserved\nBits 15:0 PTXFSAVL: Periodic transmit data FIFO space available\nIndicates the number of free locations available to be written to in the periodic TxFIFO.\nValues are in terms of 32-bit words\n0000: Periodic TxFIFO is full\n0001: dx1 word available\n0010: dx2 words available\nbxn: dxn words available (where 0 ≤dxn ≤dx512)\nOthers: Reserved\n\n\n<>\n\nRM0090 Rev 21\n1437/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS Host all channels interrupt register (OTG_HS_HAINT)\nAddress offset: 0x414\nReset value: 0x0000 000\nWhen a significant event occurs on a channel, the host all channels interrupt register \ninterrupts the application using the host channels interrupt bit of the Core interrupt register \n(HCINT bit in OTG_HS_GINTSTS). This is shown in Figure 414. There is one interrupt bit \nper channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the \napplication sets and clears bits in the corresponding host channel-x interrupt register.\n \n \nOTG_HS host all channels interrupt mask register (OTG_HS_HAINTMSK)\nAddress offset: 0x418\nReset value: 0x0000 0000\nThe host all channel interrupt mask register works with the host all channel interrupt register \nto interrupt the application when an event occurs on a channel. There is one interrupt mask \nbit per channel, up to a maximum of 16 bits.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nHAINT\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 HAINT: Channel interrupts\nOne bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nHAINTM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 HAINTM: Channel interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nOne bit per channel: Bit 0 for channel 0, bit 15 for channel 15\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1438/1757\nRM0090 Rev 21\nOTG_HS host port control and status register (OTG_HS_HPRT)\nAddress offset: 0x440\nReset value: 0x0000 0000\nThis register is available only in host mode. Currently, the OTG host supports only one port.\nA single register holds USB port-related information such as USB reset, enable, suspend, \nresume, connect status, and test mode for each port. It is shown in Figure 414. The rc_w1 \nbits in this register can trigger an interrupt to the application through the host port interrupt \nbit of the core interrupt register (HPRTINT bit in OTG_HS_GINTSTS). On a Port Interrupt, \nthe application must read this register and clear the bit that caused the interrupt. For the \nrc_w1 bits, the application must write a 1 to the bit to clear the interrupt.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPSPD\nPTCTL\nPPWR\nPLSTS\nReserved\nPRST\nPSUSP\nPRES\nPOCCHNG\nPOCA\nPENCHNG\nPENA\nPCDET\nPCSTS\nr\nr\nrw\nrw\nrw\nrw\nrw\nr\nr\nrw\nrs\nrw\nrc_\nw1\nr\nrc_\nw1\nrc_\nw0\nrc_\nw1\nr\nBits 31:19 Reserved, must be kept at reset value.\nBits 18:17 PSPD: Port speed\nIndicates the speed of the device attached to this port.\n00: High speed\n01: Full speed\n10: Low speed\n11: Reserved\nBits 16:13 PTCTL: Port test control\nThe application writes a nonzero value to this field to put the port into a Test mode, and the \ncorresponding pattern is signaled on the port.\n0000: Test mode disabled\n0001: Test_J mode\n0010: Test_K mode\n0011: Test_SE0_NAK mode\n0100: Test_Packet mode\n0101: Test_Force_Enable\nOthers: Reserved\nBit 12 PPWR: Port power\nThe application uses this field to control power to this port, and the core clears this bit on an \novercurrent condition.\n0: Power off\n1: Power on\nBits 11:10 PLSTS: Port line status\nIndicates the current logic level USB data lines\nBit [10]: Logic level of OTG_HS_FS_DP\nBit [11]: Logic level of OTG_HS_FS_DM\nBit 9 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n1439/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBit 8 PRST: Port reset\nWhen the application sets this bit, a reset sequence is started on this port. The application \nmust time the reset period and clear this bit after the reset sequence is complete.\n0: Port not in reset\n1: Port in reset\nThe application must leave this bit set for a minimum duration of at least 10 ms to start a \nreset on the port. The application can leave it set for another 10 ms in addition to the \nrequired minimum duration, before clearing the bit, even though there is no maximum limit \nset by the USB standard.\nHigh speed: 50 ms\nFull speed/Low speed: 10 ms\nBit 7 PSUSP: Port suspend\nThe application sets this bit to put this port in Suspend mode. The core only stops sending \nSOFs when this is set. To stop the PHY clock, the application must set the Port clock stop \nbit, which asserts the suspend input pin of the PHY.\nThe read value of this bit reflects the current suspend status of the port. This bit is cleared \nby the core after a remote wake-up signal is detected or the application sets the Port reset \nbit or Port resume bit in this register or the Resume/remote wake-up detected interrupt bit or \nDisconnect detected interrupt bit in the Core interrupt register (WKUINT or DISCINT in \nOTG_HS_GINTSTS, respectively).\n0: Port not in Suspend mode\n1: Port in Suspend mode\nBit 6\nPRES: Port resume\nThe application sets this bit to drive resume signaling on the port. The core continues to \ndrive the resume signal until the application clears this bit.\nIf the core detects a USB remote wake-up sequence, as indicated by the Port \nresume/remote wake-up detected interrupt bit of the Core interrupt register (WKUINT bit in \nOTG_HS_GINTSTS), the core starts driving resume signaling without application \nintervention and clears this bit when it detects a disconnect condition. The read value of this \nbit indicates whether the core is currently driving resume signaling.\n0: No resume driven\n1: Resume driven\nBit 5 POCCHNG: Port overcurrent change\nThe core sets this bit when the status of the Port overcurrent active bit (bit 4) in this register \nchanges.\nBit 4 POCA: Port overcurrent active\nIndicates the overcurrent condition of the port.\n0: No overcurrent condition\n1: Overcurrent condition\nBit 3 PENCHNG: Port enable/disable change\nThe core sets this bit when the status of the Port enable bit [2] in this register changes.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1440/1757\nRM0090 Rev 21\nOTG_HS host channel-x characteristics register (OTG_HS_HCCHARx) \n(x = 0..11, where x = Channel_number)\nAddress offset: 0x500 + 0x20 * x\nReset value: 0x0000 0000\n \n \nBit 2 PENA: Port enable\nA port is enabled only by the core after a reset sequence, and is disabled by an overcurrent \ncondition, a disconnect condition, or by the application clearing this bit. The application \ncannot set this bit by a register write. It can only clear it to disable the port. This bit does not \ntrigger any interrupt to the application.\n0: Port disabled\n1: Port enabled\nBit 1 PCDET: Port connect detected\nThe core sets this bit when a device connection is detected to trigger an interrupt to the \napplication using the host port interrupt bit in the Core interrupt register (HPRTINT bit in \nOTG_HS_GINTSTS). The application must write a 1 to this bit to clear the interrupt.\nBit 0 PCSTS: Port connect status\n0: No device is attached to the port\n1: A device is attached to the port\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nrs\nrs\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 CHENA: Channel enable\nThis field is set by the application and cleared by the OTG host.\n0: Channel disabled\n1: Channel enabled\nBit 30 CHDIS: Channel disable\nThe application sets this bit to stop transmitting/receiving data on a channel, even before \nthe transfer for that channel is complete. The application must wait for the Channel disabled \ninterrupt before treating the channel as disabled.\nBit 29 ODDFRM: Odd frame\nThis field is set (reset) by the application to indicate that the OTG host must perform a \ntransfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) \ntransactions.\n0: Even (micro) frame\n1: Odd (micro) frame\nBits 28:22 DAD: Device address\nThis field selects the specific device serving as the data source or sink.\n\n\n<>\n\nRM0090 Rev 21\n1441/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBits 21:20 MC: Multi Count (MC) / Error Count (EC)\n– When the split enable bit (SPLITEN) in the host channel-x split control register \n(OTG_HS_HCSPLTx) is reset (0), this field indicates to the host the number of transactions \nthat must be executed per micro-frame for this periodic endpoint. For nonperiodic transfers, \nthis field specifies the number of packets to be fetched for this channel before the internal \nDMA engine changes arbitration.\n00: Reserved This field yields undefined results\n01: 1 transaction\nb10: 2 transactions to be issued for this endpoint per micro-frame\n11: 3 transactions to be issued for this endpoint per micro-frame.\n– When the SPLITEN bit is set (1) in OTG_HS_HCSPLTx, this field indicates the number of \nimmediate retries to be performed for a periodic split transaction on transaction errors. This \nfield must be set to at least 01.\nBits 19:18 EPTYP: Endpoint type\nIndicates the transfer type selected.\n00: Control\n01: Isochronous\n10: Bulk\n11: Interrupt\nBit 17 LSDEV: Low-speed device\nThis field is set by the application to indicate that this channel is communicating to a low-\nspeed device.\nBit 16 Reserved, must be kept at reset value.\nBit 15 EPDIR: Endpoint direction\nIndicates whether the transaction is IN or OUT.\n0: OUT\n1: IN\nBits 14:11 EPNUM: Endpoint number\nIndicates the endpoint number on the device serving as the data source or sink.\nBits 10:0 MPSIZ: Maximum packet size\nIndicates the maximum packet size of the associated endpoint.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1442/1757\nRM0090 Rev 21\nOTG_HS host channel-x split control register (OTG_HS_HCSPLTx) (x = 0..11, \nwhere x = Channel_number)\nAddress offset: 0x504 + 0x20 * x\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 SPLITEN: Split enable\nThe application sets this bit to indicate that this channel is enabled to perform split \ntransactions.\nBits 30:17\nReserved, must be kept at reset value.\nBit 16 COMPLSPLT: Do complete split\nThe application sets this bit to request the OTG host to perform a complete split transaction. \nBits 15:14 XACTPOS: Transaction position\nThis field is used to determine whether to send all, first, middle, or last payloads with each \nOUT transaction.\n11: All. This is the entire data payload of this transaction (which is less than or equal to 188 \nbytes)\n10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes)\n00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes)\n01: End. This is the last payload of this transaction (which is larger than 188 bytes)\nBits 13:7 HUBADDR: Hub address\nThis field holds the device address of the transaction translator’s hub.\nBits 6:0 PRTADDR: Port address\nThis field is the port number of the recipient transaction translator.\n\n\n<>\n\nRM0090 Rev 21\n1443/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS host channel-x interrupt register (OTG_HS_HCINTx) (x = 0..11, where \nx = Channel_number)\nAddress offset: 0x508 + 0x20 * x\nReset value: 0x0000 0000\nThis register indicates the status of a channel with respect to USB- and AHB-related events. \nIt is shown in Figure 414. The application must read this register when the host channels \ninterrupt bit in the Core interrupt register (HCINT bit in OTG_HS_GINTSTS) is set. Before \nthe application can read this register, it must first read the host all channels interrupt \n(OTG_HS_HAINT) register to get the exact channel number for the host channel-x interrupt \nregister. The application must clear the appropriate bit in this register to clear the \ncorresponding bits in the OTG_HS_HAINT and OTG_HS_GINTSTS registers.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nBits 31:11 Reserved, must be kept at reset value.\nBit 10 DTERR: Data toggle error\nBit 9 FRMOR: Frame overrun\nBit 8 BBERR: Babble error\nBit 7 TXERR: Transaction error\nIndicates one of the following errors occurred on the USB.\nCRC check failure\nTimeout\nBit stuff error\nFalse EOP\nBit 6 NYET: Response received interrupt\nBit 5 ACK: ACK response received/transmitted interrupt\nBit 4 NAK: NAK response received interrupt\nBit 3 STALL: STALL response received interrupt\nBit 2 AHBERR: AHB error\nThis error is generated only in Internal DMA mode when an AHB error occurs during an AHB \nread/write operation. The application can read the corresponding DMA channel address \nregister to get the error address.\nBit 1 CHH: Channel halted\nIndicates the transfer completed abnormally either because of any USB transaction error or in \nresponse to disable request by the application.\nBit 0 XFRC: Transfer completed\nTransfer completed normally without any errors.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1444/1757\nRM0090 Rev 21\nOTG_HS host channel-x interrupt mask register (OTG_HS_HCINTMSKx) \n(x = 0..11, where x = Channel_number)\nAddress offset: 0x50C + 0x20 * x\nReset value: 0x0000 0000\nThis register reflects the mask for each channel status described in the previous section.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:11 Reserved, must be kept at reset value.\nBit 10 DTERRM: Data toggle error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 9 FRMORM: Frame overrun mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 8 BBERRM: Babble error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 7 TXERRM: Transaction error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 6 NYET: response received interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 5 ACKM: ACK response received/transmitted interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 4 NAKM: NAK response received interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 3 STALLM: STALL response received interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\n\n\n<>\n\nRM0090 Rev 21\n1445/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS host channel-x transfer size register (OTG_HS_HCTSIZx) (x = 0..11, \nwhere x = Channel_number)\nAddress offset: 0x510 + 0x20 * x\nReset value: 0x0000 0000\n \n \nBit 2 AHBERRM: AHB error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 1 CHHM: Channel halted mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 0 XFRCM: Transfer completed mask\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 DOPING: Do ping\nThis bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING \nprotocol.\nNote: Do not set this bit for IN transfers. If this bit is set for IN transfers it disables the channel. \nBits 30:29 DPID: Data PID\nThe application programs this field with the type of PID to use for the initial transaction. The \nhost maintains this field for the rest of the transfer.\n00: DATA0\n01: DATA2\n10: DATA1\n11: MDATA (noncontrol)/SETUP (control)\nBits 28:19 PKTCNT: Packet count\nThis field is programmed by the application with the expected number of packets to be \ntransmitted (OUT) or received (IN).\nThe host decrements this count on every successful transmission or reception of an OUT/IN \npacket. Once this count reaches zero, the application is interrupted to indicate normal \ncompletion.\nBits 18:0 XFRSIZ: Transfer size\nFor an OUT, this field is the number of data bytes the host sends during the transfer.\nFor an IN, this field is the buffer size that the application has reserved for the transfer. The \napplication is expected to program this field as an integer multiple of the maximum packet \nsize for IN transactions (periodic and nonperiodic).\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1446/1757\nRM0090 Rev 21\nOTG_HS host channel-x DMA address register (OTG_HS_HCDMAx) (x = 0..11, \nwhere x = Channel_number)\nAddress offset: 0x514 + 0x20 * x\nReset value: 0x0000 0000\n \n \n35.12.4 \nDevice-mode registers\nOTG_HS device configuration register (OTG_HS_DCFG)\nAddress offset: 0x800\nReset value: 0x0220 0000\nThis register configures the core in peripheral mode after power-on or after certain control \ncommands or enumeration. Do not make changes to this register after initial programming.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDMAADDR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 DMAADDR: DMA address\nThis field holds the start address in the external memory from which the data for the endpoint \nmust be fetched or to which it must be stored. This register is incremented on every AHB \ntransaction. \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPERSCHIVL\nReserved\nReserved\nPFIVL\nDAD\nReserved\nNZLSOHSK\nDSPD\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:26 Reserved, must be kept at reset value.\nBits 25:24 PERSCHIVL: Periodic scheduling interval\nThis field specifies the amount of time the Internal DMA engine must allocate for fetching \nperiodic IN endpoint data. Based on the number of periodic endpoints, this value must be \nspecified as 25, 50 or 75% of the (micro)frame.\n–\nWhen any periodic endpoints are active, the internal DMA engine allocates the \nspecified amount of time in fetching periodic IN endpoint data\n–\nWhen no periodic endpoint is active, then the internal DMA engine services \nnonperiodic endpoints, ignoring this field\n–\nAfter the specified time within a (micro)frame, the DMA switches to fetching \nnonperiodic endpoints\n00: 25% of (micro)frame\n01: 50% of (micro)frame\n10: 75% of (micro)frame\n11: Reserved\nBits 23:13 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n1447/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBits 12:11 PFIVL: Periodic (micro)frame interval\nIndicates the time within a (micro) frame at which the application must be notified using the \nend of periodic (micro) frame interrupt. This can be used to determine if all the isochronous \ntraffic for that frame is complete.\n00: 80% of the frame interval\n01: 85% of the frame interval\n10: 90% of the frame interval\n11: 95% of the frame interval\nBits 10:4 DAD: Device address\nThe application must program this field after every SetAddress control command.\nBit 3 Reserved, must be kept at reset value.\nBit 2 NZLSOHSK: Nonzero-length status OUT handshake\nThe application can use this field to select the handshake the core sends on receiving a \nnonzero-length data packet during the OUT transaction of a control transfer’s Status stage.\n1: Send a STALL handshake on a nonzero-length status OUT transaction and do not send \nthe received OUT packet to the application.\n0: Send the received OUT packet to the application (zero-length or nonzero-length) and \nsend a handshake based on the NAK and STALL bits for the endpoint in the device endpoint \ncontrol register.\nBits 1:0 DSPD: Device speed\nIndicates the speed at which the application requires the core to enumerate, or the \nmaximum speed the application can support. However, the actual bus speed is determined \nonly after the chirp sequence is completed, and is based on the speed of the USB host to \nwhich the core is connected.\n00: High speed\n01: Full speed using external ULPI PHY\n10: Reserved\n11: Full speed using internal embedded PHY\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1448/1757\nRM0090 Rev 21\nOTG_HS device control register (OTG_HS_DCTL)\nAddress offset: 0x804\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPOPRGDNE\nCGONAK\nSGONAK\nCGINAK\nSGINAK\nTCTL\nGONSTS\nGINSTS\nSDIS\nRWUSIG\nrw\nw\nw\nw\nw\nrw\nrw\nrw\nr\nr\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBit 11 POPRGDNE: Power-on programming done\nThe application uses this bit to indicate that register programming is completed after a \nwake-up from power down mode.\nBit 10 CGONAK: Clear global OUT NAK\nWriting 1 to this field clears the Global OUT NAK.\nBit 9 SGONAK: Set global OUT NAK\nWriting 1 to this field sets the Global OUT NAK.\nThe application uses this bit to send a NAK handshake on all OUT endpoints.\nThe application must set the this bit only after making sure that the Global OUT NAK \neffective bit in the Core interrupt register (GONAKEFF bit in OTG_HS_GINTSTS) is \ncleared.\nBit 8 CGINAK: Clear global IN NAK\nWriting 1 to this field clears the Global IN NAK.\nBit 7 SGINAK: Set global IN NAK\nWriting 1 to this field sets the Global nonperiodic IN NAK.The application uses this bit to \nsend a NAK handshake on all nonperiodic IN endpoints.\nThe application must set this bit only after making sure that the Global IN NAK effective bit \nin the Core interrupt register (GINAKEFF bit in OTG_HS_GINTSTS) is cleared.\nBits 6:4 TCTL: Test control\n000: Test mode disabled\n001: Test_J mode\n010: Test_K mode\n011: Test_SE0_NAK mode\n100: Test_Packet mode\n101: Test_Force_Enable\nOthers: Reserved\nBit 3 GONSTS: Global OUT NAK status\n0: A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.\n1: No data is written to the RxFIFO, irrespective of space availability. Sends a NAK \nhandshake on all packets, except on SETUP transactions. All isochronous OUT packets are \ndropped.\n\n\n<>\n\nRM0090 Rev 21\n1449/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nTable 215 contains the minimum duration (according to device state) for which the Soft \ndisconnect (SDIS) bit must be set for the USB host to detect a device disconnect. To \naccommodate clock jitter, it is recommended that the application add some extra delay to \nthe specified minimum duration.\n \nBit 2 GINSTS: Global IN NAK status\n0: A handshake is sent out based on the data availability in the transmit FIFO.\n1: A NAK handshake is sent out on all nonperiodic IN endpoints, irrespective of the data \navailability in the transmit FIFO.\nBit 1 SDIS: Soft disconnect\nThe application uses this bit to signal the USB OTG core to perform a soft disconnect. As \nlong as this bit is set, the host does not see that the device is connected, and the device \ndoes not receive signals on the USB. The core stays in the disconnected state until the \napplication clears this bit.\n0: Normal operation. When this bit is cleared after a soft disconnect, the core generates a \ndevice connect event to the USB host. When the device is reconnected, the USB host \nrestarts device enumeration.\n1: The core generates a device disconnect event to the USB host.\nBit 0 RWUSIG: Remote wake-up signaling\nWhen the application sets this bit, the core initiates remote signaling to wake up the USB \nhost. The application must set this bit to instruct the core to exit the Suspend state. As \nspecified in the USB 2.0 specification, the application must clear this bit 1 ms to 15 ms after \nsetting it.\nTable 215. Minimum duration for soft disconnect\nOperating speed\nDevice state\nMinimum duration\nHigh speed\nNot Idle or Suspended (Performing transactions) \n125 µs\nFull speed\nSuspended\n1 ms + 2.5 µs\nFull speed\nIdle\n2.5 µs\nFull speed\nNot Idle or Suspended (Performing transactions)\n2.5 µs\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1450/1757\nRM0090 Rev 21\nOTG_HS device status register (OTG_HS_DSTS)\nAddress offset: 0x808\nReset value: 0x0000 0010\nThis register indicates the status of the core with respect to USB-related events. It must be \nread on interrupts from the device all interrupts (OTG_HS_DAINT) register.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFNSOF\nReserved\nEERR\nENUMSPD\nSUSPSTS\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:22 Reserved, must be kept at reset value.\nBits 21:8 FNSOF: Frame number of the received SOF\nBits 7:4 Reserved, must be kept at reset value.\nBit 3 EERR: Erratic error\nThe core sets this bit to report any erratic errors.\nDue to erratic errors, the OTG_HS controller goes into Suspended state and an interrupt is \ngenerated to the application with Early suspend bit of the Core interrupt register (ESUSP bit \nin OTG_HS_GINTSTS). If the early suspend is asserted due to an erratic error, the \napplication can only perform a soft disconnect recover.\nBits 2:1 ENUMSPD: Enumerated speed\nIndicates the speed at which the OTG_HS controller has come up after speed detection \nthrough a chirp sequence.\n00: High speed\n01: Reserved\n10: Reserved\n11: Full speed (PHY clock is running at 48 MHz)\nOthers: reserved\nBit 0 SUSPSTS: Suspend status\nIn peripheral mode, this bit is set as long as a Suspend condition is detected on the USB. \nThe core enters the Suspended state when there is no activity on the USB data lines for a \nperiod of 3 ms. The core comes out of the suspend:\n– When there is an activity on the USB data lines\n– When the application writes to the Remote wake-up signaling bit in the Device control \nregister (RWUSIG bit in OTG_HS_DCTL).\n\n\n<>\n\nRM0090 Rev 21\n1451/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device IN endpoint common interrupt mask register \n(OTG_HS_DIEPMSK)\nAddress offset: 0x810\nReset value: 0x0000 0000\nThis register works with each of the Device IN endpoint interrupt (OTG_HS_DIEPINTx) \nregisters for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt \nfor a specific status in the OTG_HS_DIEPINTx register can be masked by writing to the \ncorresponding bit in this register. Status bits are masked by default.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNAKM\nReserved\nTXFURM\nReserved\nINEPNEM\nINEPNMM\nITTXFEMSK\nTOM\nAHBERRM\nEPDM\nXFRCM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:10 Reserved, must be kept at reset value.\nBit 13 NAKM: NAK interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBits 12:9 Reserved, must be kept at reset value.\nBit 8 TXFURM: FIFO underrun mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 7 Reserved, must be kept at reset value.\nBit 6 INEPNEM: IN endpoint NAK effective mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 5 INEPNMM: IN token received with EP mismatch mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 4 ITTXFEMSK: IN token received when TxFIFO empty mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 3 TOM: Timeout condition mask (nonisochronous endpoints)\n0: Masked interrupt\n1: Unmasked interrupt\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1452/1757\nRM0090 Rev 21\nOTG_HS device OUT endpoint common interrupt mask register \n(OTG_HS_DOEPMSK)\nAddress offset: 0x814\nReset value: 0x0000 0000\nThis register works with each of the Device OUT endpoint interrupt (OTG_HS_DOEPINTx) \nregisters for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint \ninterrupt for a specific status in the OTG_HS_DOEPINTx register can be masked by writing \ninto the corresponding bit in this register. Status bits are masked by default.\n \nBit 2 AHBERRM: AHB error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 1 EPDM: Endpoint disabled interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 0 XFRCM: Transfer completed interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNYETMSK\nNAKMSK\nBERRM\nReserved\nOPEM\nReserved\n B2BSTUP\nSTSPHSRXM\n OTEPDM\nSTUPM\nAHBERRM\nEPDM\nXFRCM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:15 Reserved, must be kept at reset value.\nBit 14 NYETMSK: NYET interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 13 NAKMSK: NAK interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 12 BERRM: Babble error interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBits 11:9 Reserved, must be kept at reset value.\nBit 8 OPEM: OUT packet error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 7 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n1453/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device all endpoints interrupt register (OTG_HS_DAINT)\nAddress offset: 0x818\nReset value: 0x0000 0000\nWhen a significant event occurs on an endpoint, a device all endpoints interrupt register \ninterrupts the application using the Device OUT endpoints interrupt bit or Device IN \nendpoints interrupt bit of the Core interrupt register (OEPINT or IEPINT in \nOTG_HS_GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum \nof 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the \ncorresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared \nwhen the application sets and clears bits in the corresponding Device Endpoint-x interrupt \nregister (OTG_HS_DIEPINTx/OTG_HS_DOEPINTx).\n \nBit 6 B2BSTUP: Back-to-back SETUP packets received mask\nApplies to control OUT endpoints only.\n0: Masked interrupt\n1: Unmasked interrupt\nBit 5 STSPHSRXM: Status phase received for control write mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 4 OTEPDM: OUT token received when endpoint disabled mask\nApplies to control OUT endpoints only.\n0: Masked interrupt\n1: Unmasked interrupt\nBit 3 STUPM: SETUP phase done mask\nApplies to control endpoints only.\n0: Masked interrupt\n1: Unmasked interrupt\nBit 2 AHBERRM: AHB error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 1 EPDM: Endpoint disabled interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 0 XFRCM: Transfer completed interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOEPINT\nIEPINT\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1454/1757\nRM0090 Rev 21\n \nOTG_HS all endpoints interrupt mask register (OTG_HS_DAINTMSK)\nAddress offset: 0x81C\nReset value: 0x0000 0000\nThe device endpoint interrupt mask register works with the device endpoint interrupt register \nto interrupt the application when an event occurs on a device endpoint. However, the device \nall endpoints interrupt (OTG_HS_DAINT) register bit corresponding to that interrupt is still \nset.\n \n \nOTG_HS device VBUS discharge time register (OTG_HS_DVBUSDIS)\nAddress offset: 0x0828\nReset value: 0x0000 17D7\nThis register specifies the VBUS discharge time after VBUS pulsing during SRP.\n \n \nBits 31:16 OEPINT: OUT endpoint interrupt bits\nOne bit per OUT endpoint: \nBit 16 for OUT endpoint 0, bit 31 for OUT endpoint 15\nBits 15:0 IEPINT: IN endpoint interrupt bits\nOne bit per IN endpoint: \nBit 0 for IN endpoint 0, bit 15 for endpoint 15\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOEPM\nIEPM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 OEPM: OUT EP interrupt mask bits\nOne per OUT endpoint:\nBit 16 for OUT EP 0, bit 19 for OUT EP 3\n0: Masked interrupt\n1: Unmasked interrupt\nBits 15:0 IEPM: IN EP interrupt mask bits\nOne bit per IN endpoint:\nBit 0 for IN EP 0, bit 3 for IN EP 3\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nVBUSDT\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 VBUSDT: Device VBUS discharge time\nSpecifies the VBUS discharge time after VBUS pulsing during SRP. This value equals:\nVBUS discharge time in PHY clocks / 1 024\nDepending on your VBUS load, this value may need adjusting.\n\n\n<>\n\nRM0090 Rev 21\n1455/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device VBUS pulsing time register (OTG_HS_DVBUSPULSE)\nAddress offset: 0x082C\nReset value: 0x0000 05B8\nThis register specifies the VBUS pulsing time during SRP.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDVBUSP\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 DVBUSP: Device VBUS pulsing time\nSpecifies the VBUS pulsing time during SRP. This value equals:\nVBUS pulsing time in PHY clocks / 1 024\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1456/1757\nRM0090 Rev 21\nOTG_HS Device threshold control register (OTG_HS_DTHRCTL)\nAddress offset: 0x0830\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nARPEN\nReserved\nRXTHRLEN\nRXTHREN\nReserved\nTXTHRLEN\nISOTHREN\nNONISOTHREN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBit 27 ARPEN: Arbiter parking enable\nThis bit controls internal DMA arbiter parking for IN endpoints. When thresholding is enabled \nand this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token \nreceived on the USB. This is done to avoid getting into underrun conditions. By default \nparking is enabled.\nBit 26\nReserved, must be kept at reset value.\nBits 25: 17 RXTHRLEN: Receive threshold length\nThis field specifies the receive thresholding size in words. This field also specifies the \namount of data received on the USB before the core can start transmitting on the AHB. The \nthreshold length has to be at least eight words. The recommended value for RXTHRLEN is \nto be the same as the programmed AHB burst length (HBSTLEN bit in \nOTG_HS_GAHBCFG). \nBit 16 RXTHREN: Receive threshold enable\nWhen this bit is set, the core enables thresholding in the receive direction.\nBits 15: 11\nReserved, must be kept at reset value.\nBits 10:2 TXTHRLEN: Transmit threshold length\nThis field specifies the transmit thresholding size in words. This field specifies the amount of \ndata in bytes to be in the corresponding endpoint transmit FIFO, before the core can start \ntransmitting on the USB. The threshold length has to be at least eight words. This field \ncontrols both isochronous and nonisochronous IN endpoint thresholds. The recommended \nvalue for TXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit \nin OTG_HS_GAHBCFG).\nBit 1 ISOTHREN: ISO IN endpoint threshold enable\nWhen this bit is set, the core enables thresholding for isochronous IN endpoints.\nBit 0 NONISOTHREN: Nonisochronous IN endpoints threshold enable\nWhen this bit is set, the core enables thresholding for nonisochronous IN endpoints. \n\n\n<>\n\nRM0090 Rev 21\n1457/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device IN endpoint FIFO empty interrupt mask register: \n(OTG_HS_DIEPEMPMSK)\nAddress offset: 0x834\nReset value: 0x0000 0000\nThis register is used to control the IN endpoint FIFO empty interrupt generation \n(TXFE_OTG_HS_DIEPINTx).\n \n \nOTG_HS device each endpoint interrupt register (OTG_HS_DEACHINT)\nAddress offset: 0x0838\nReset value: 0x0000 0000\nThere is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nINEPTXFEM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 INEPTXFEM: IN EP Tx FIFO empty interrupt mask bits\nThese bits act as mask bits for OTG_HS_DIEPINTx.\nTXFE interrupt one bit per IN endpoint:\nBit 0 for IN endpoint 0, bit 15 for IN endpoint 15\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOEP1INT\nReserved\nIEP1INT\nReserved\nr\nr\nBits 31:18 Reserved, must be kept at reset value.\nBit 17 OEP1INT: OUT endpoint 1 interrupt bit \nBits 16:2 Reserved, must be kept at reset value.\nBit 1 IEP1INT: IN endpoint 1interrupt bit \nBit 0\nReserved, must be kept at reset value.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1458/1757\nRM0090 Rev 21\nOTG_HS device each endpoint interrupt register mask \n(OTG_HS_DEACHINTMSK)\nAddress offset: 0x083C\nReset value: 0x0000 0000\nThere is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT.\n \nOTG_HS device each in endpoint-1 interrupt register \n(OTG_HS_DIEPEACHMSK1)\nAddress offset: 0x844\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOEP1INTM\nReserved\nIEP1INTM\nReserved\nrw\nrw\nBits 31:18 Reserved, must be kept at reset value.\nBit 17 OEP1INTM: OUT Endpoint 1 interrupt mask bit \nBits 16:2\nReserved, must be kept at reset value.\nBit 1 IEP1INTM: IN Endpoint 1 interrupt mask bit \nBit 0\nReserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNAKM\nReserved\nBIM\nTXFURM\nReserved\nINEPNEM\nINEPNMM\nITTXFEMSK\nTOM\nAHBERRM\nEPDM\nXFRCM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:14 Reserved, must be kept at reset value.\nBit 13 NAKM: NAK interrupt mask\n0: Masked interrupt\n1: unmasked interrupt\nBit 12:10 Reserved, must be kept at reset value.\nBit 9 BIM: BNA interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 8 TXFURM: FIFO underrun mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 7 Reserved, must be kept at reset value.\n\n\n<>\n\nRM0090 Rev 21\n1459/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device each OUT endpoint-1 interrupt register \n(OTG_HS_DOEPEACHMSK1)\nAddress offset: 0x884\nReset value: 0x0000 0000\n \n \nBit 6 INEPNEM: IN endpoint NAK effective mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 5 INEPNMM: IN token received with EP mismatch mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 4 ITTXFEMSK: IN token received when TxFIFO empty mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 3 TOM: Timeout condition mask (nonisochronous endpoints)\n0: Masked interrupt\n1: Unmasked interrupt\nBit 2 AHBERRM: AHB error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 1 EPDM: Endpoint disabled interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 0 XFRCM: Transfer completed interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNYETM\nNAKM\nBERRM\nReserved\nBIM\nTXFURM\nReserved\nINEPNEM\nINEPNMM\nITTXFEMSK\nTOM\nAHBERRM\nEPDM\nXFRCM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:15 Reserved, must be kept at reset value.\nBit 14 NYETM: NYET interrupt mask\n0: Masked interrupt\n1: unmasked interrupt\nBit 13 NAKM: NAK interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 12 BERRM: Bubble error interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 11:10 Reserved, must be kept at reset value.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1460/1757\nRM0090 Rev 21\nOTG device endpoint-x control register (OTG_HS_DIEPCTLx) (x = 0..5, where \nx = Endpoint_number)\nAddress offset: 0x900 + 0x20 * x\nReset value: 0x0000 0000\nThe application uses this register to control the behavior of each logical endpoint other than \nendpoint 0.\n \n \nBit 9 BIM: BNA interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 8 OPEM: OUT packet error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBits 7:3 Reserved, must be kept at reset value.\nBit 2 AHBERRM: AHB error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 1 EPDM: Endpoint disabled interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 0 XFRCM: Transfer completed interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nStall\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nrs\nrs\nw\nw\nw\nw\nrw\nrw\nrw\nrw\nrw/\nrs\nrw\nrw\nr\nr\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n1461/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBit 31 EPENA: Endpoint enable\nThe application sets this bit to start transmitting data on an endpoint.\nThe core clears this bit before setting any of the following interrupts on this endpoint:\n– SETUP phase done\n– Endpoint disabled\n– Transfer completed\nBit 30 EPDIS: Endpoint disable\nThe application sets this bit to stop transmitting/receiving data on an endpoint, even before \nthe transfer for that endpoint is complete. The application must wait for the Endpoint \ndisabled interrupt before treating the endpoint as disabled. The core clears this bit before \nsetting the Endpoint disabled interrupt. The application must set this bit only if Endpoint \nenable is already set for this endpoint.\nBit 29 SODDFRM: Set odd frame\nApplies to isochronous IN and OUT endpoints only.\nWriting to this field sets the Even/Odd frame (EONUM) field to odd frame.\nBit 28 SD0PID: Set DATA0 PID\nApplies to interrupt/bulk IN endpoints only.\nWriting to this field sets the endpoint data PID (DPID) field in this register to DATA0.\nSEVNFRM: Set even frame\nApplies to isochronous IN endpoints only.\nWriting to this field sets the Even/Odd frame (EONUM) field to even frame.\nBit 27\nSNAK: Set NAK\nA write to this bit sets the NAK bit for the endpoint.\nUsing this bit, the application can control the transmission of NAK handshakes on an \nendpoint. The core can also set this bit for OUT endpoints on a Transfer completed interrupt, \nor after a SETUP is received on the endpoint.\nBit 26 CNAK: Clear NAK\nA write to this bit clears the NAK bit for the endpoint.\nBits 25:22 TXFNUM: TxFIFO number\nThese bits specify the FIFO number associated with this endpoint. Each active IN endpoint \nmust be programmed to a separate FIFO number.\nThis field is valid only for IN endpoints.\nBit 21 STALL: STALL handshake\nApplies to noncontrol, nonisochronous IN endpoints only (access type is rw).\nThe application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK \nbit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. \nOnly the application can clear this bit, never the core.\nApplies to control endpoints only (access type is rs).\nThe application can only set this bit, and the core clears it, when a SETUP token is received \nfor this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, \nthe STALL bit takes priority. Irrespective of this bit’s setting, the core always responds to \nSETUP data packets with an ACK handshake.\nBit 20 Reserved, must be kept at reset value.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1462/1757\nRM0090 Rev 21\nBits 19:18 EPTYP: Endpoint type\nThis is the transfer type supported by this logical endpoint.\n00: Control\n01: Isochronous\n10: Bulk\n11: Interrupt\nBit 17 NAKSTS: NAK status\nIt indicates the following:\n0: The core is transmitting nonNAK handshakes based on the FIFO status.\n1: The core is transmitting NAK handshakes on this endpoint.\nWhen either the application or the core sets this bit:\nFor nonisochronous IN endpoints: The core stops transmitting any data on an IN endpoint, \neven if there are data available in the TxFIFO.\nFor isochronous IN endpoints: The core sends out a zero-length data packet, even if there \nare data available in the TxFIFO.\nIrrespective of this bit’s setting, the core always responds to SETUP data packets with an ACK \nhandshake.\nBit 16 EONUM: Even/odd frame\nApplies to isochronous IN endpoints only.\nIndicates the frame number in which the core transmits/receives isochronous data for this \nendpoint. The application must program the even/odd frame number in which it intends to \ntransmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM \nfields in this register.\n0: Even frame\n1: Odd frame\nDPID: Endpoint data PID\nApplies to interrupt/bulk IN endpoints only.\nContains the PID of the packet to be received or transmitted on this endpoint. The \napplication must program the PID of the first packet to be received or transmitted on this \nendpoint, after the endpoint is activated. The application uses the SD0PID register field to \nprogram either DATA0 or DATA1 PID.\n0: DATA0\n1: DATA1\nBit 15 USBAEP: USB active endpoint\nIndicates whether this endpoint is active in the current configuration and interface. The core \nclears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving \nthe SetConfiguration and SetInterface commands, the application must program endpoint \nregisters accordingly and set this bit.\nBits 14:11 Reserved, must be kept at reset value.\nBits 10:0 MPSIZ: Maximum packet size\nThe application must program this field with the maximum packet size for the current logical \nendpoint. This value is in bytes.\n\n\n<>\n\nRM0090 Rev 21\n1463/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device control OUT endpoint 0 control register \n(OTG_HS_DOEPCTL0)\nAddress offset: 0xB00\nReset value: 0x0000 8000\nThis section describes the device control OUT endpoint 0 control register. Nonzero control \nendpoints use registers for endpoints 1–15.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEPENA\nEPDIS\nReserved\nSNAK\nCNAK\nReserved\nStall\nSNPM\nEPTYP\nNAKSTS\nReserved\nUSBAEP\nReserved\nMPSIZ\nw\nr\nw\nw\nrs\nrw\nr\nr\nr\nr\nr\nr\nBit 31 EPENA: Endpoint enable\nThe application sets this bit to start transmitting data on endpoint 0.\nThe core clears this bit before setting any of the following interrupts on this endpoint:\n– SETUP phase done\n– Endpoint disabled\n– Transfer completed\nBit 30 EPDIS: Endpoint disable\nThe application cannot disable control OUT endpoint 0.\nBits 29:28 Reserved, must be kept at reset value.\nBit 27 SNAK: Set NAK\nA write to this bit sets the NAK bit for the endpoint.\nUsing this bit, the application can control the transmission of NAK handshakes on an \nendpoint. The core can also set this bit on a Transfer completed interrupt, or after a SETUP \nis received on the endpoint.\nBit 26 CNAK: Clear NAK\nA write to this bit clears the NAK bit for the endpoint.\nBits 25:22 Reserved, must be kept at reset value.\nBit 21 STALL: STALL handshake\nThe application can only set this bit, and the core clears it, when a SETUP token is received \nfor this endpoint. If a NAK bit or Global OUT NAK is set along with this bit, the STALL bit \ntakes priority. Irrespective of this bit’s setting, the core always responds to SETUP data \npackets with an ACK handshake.\nBit 20 SNPM: Snoop mode\nThis bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check \nthe correctness of OUT packets before transferring them to application memory.\nBits 19:18 EPTYP: Endpoint type\nHardcoded to 2’b00 for control.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1464/1757\nRM0090 Rev 21\nOTG_HS device endpoint-x control register (OTG_HS_DOEPCTLx) (x = 1..5, \nwhere x = Endpoint_number)\nAddress offset for OUT endpoints: 0xB00 + 0x20 * x\nReset value: 0x0000 0000\nThe application uses this register to control the behavior of each logical endpoint other than \nendpoint 0.\n \n \nBit 17 NAKSTS: NAK status\nIndicates the following:\n0: The core is transmitting nonNAK handshakes based on the FIFO status.\n1: The core is transmitting NAK handshakes on this endpoint.\nWhen either the application or the core sets this bit, the core stops receiving data, even if \nthere is space in the RxFIFO to accommodate the incoming packet. Irrespective of this bit’s \nsetting, the core always responds to SETUP data packets with an ACK handshake.\nBit 16 Reserved, must be kept at reset value.\nBit 15 USBAEP: USB active endpoint\nThis bit is always set to 1, indicating that a control endpoint 0 is always active in all \nconfigurations and interfaces.\nBits 14:2 Reserved, must be kept at reset value.\nBits 1:0 MPSIZ: Maximum packet size\nThe maximum packet size for control OUT endpoint 0 is the same as what is programmed in \ncontrol IN endpoint 0.\n00: 64 bytes\n01: 32 bytes\n10: 16 bytes\n11: 8 bytes\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nReserved\nStall\nSNPM\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nrs\nrs\nw\nw\nw\nw\nrw\nrw\nrw\nrw\nr\nr\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n1465/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBit 31 EPENA: Endpoint enable\nApplies to IN and OUT endpoints.\nThe application sets this bit to start transmitting data on an endpoint.\nThe core clears this bit before setting any of the following interrupts on this endpoint:\n– SETUP phase done\n– Endpoint disabled\n– Transfer completed\nBit 30 EPDIS: Endpoint disable\nThe application sets this bit to stop transmitting/receiving data on an endpoint, even before \nthe transfer for that endpoint is complete. The application must wait for the Endpoint \ndisabled interrupt before treating the endpoint as disabled. The core clears this bit before \nsetting the Endpoint disabled interrupt. The application must set this bit only if Endpoint \nenable is already set for this endpoint.\nBit 29 SODDFRM: Set odd frame\nApplies to isochronous OUT endpoints only.\nWriting to this field sets the Even/Odd frame (EONUM) field to odd frame.\nBit 28 SD0PID: Set DATA0 PID\nApplies to interrupt/bulk OUT endpoints only.\nWriting to this field sets the endpoint data PID (DPID) field in this register to DATA0.\nSEVNFRM: Set even frame\nApplies to isochronous OUT endpoints only.\nWriting to this field sets the Even/Odd frame (EONUM) field to even frame.\nBit 27 SNAK: Set NAK\nA write to this bit sets the NAK bit for the endpoint.\nUsing this bit, the application can control the transmission of NAK handshakes on an \nendpoint. The core can also set this bit for OUT endpoints on a Transfer Completed \ninterrupt, or after a SETUP is received on the endpoint.\nBit 26 CNAK: Clear NAK\nA write to this bit clears the NAK bit for the endpoint.\nBits 25:22 Reserved, must be kept at reset value.\nBit 21 STALL: STALL handshake\nApplies to noncontrol, nonisochronous OUT endpoints only (access type is rw).\nThe application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK \nbit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes \npriority. Only the application can clear this bit, never the core.\nBit 20 SNPM: Snoop mode\nThis bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check \nthe correctness of OUT packets before transferring them to application memory.\nBits 19:18 EPTYP: Endpoint type\nThis is the transfer type supported by this logical endpoint.\n00: Control\n01: Isochronous\n10: Bulk\n11: Interrupt\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1466/1757\nRM0090 Rev 21\nBit 17 NAKSTS: NAK status\nIndicates the following:\n0: The core is transmitting nonNAK handshakes based on the FIFO status.\n1: The core is transmitting NAK handshakes on this endpoint.\nWhen either the application or the core sets this bit:\nThe core stops receiving any data on an OUT endpoint, even if there is space in the \nRxFIFO to accommodate the incoming packet.\nIrrespective of this bit’s setting, the core always responds to SETUP data packets with an \nACK handshake.\nBit 16 EONUM: Even/odd frame\nApplies to isochronous IN and OUT endpoints only.\nIndicates the frame number in which the core transmits/receives isochronous data for this \nendpoint. The application must program the even/odd frame number in which it intends to \ntransmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM \nfields in this register.\n0: Even frame\n1: Odd frame\nDPID: Endpoint data PID\nApplies to interrupt/bulk OUT endpoints only.\nContains the PID of the packet to be received or transmitted on this endpoint. The \napplication must program the PID of the first packet to be received or transmitted on this \nendpoint, after the endpoint is activated. The application uses the SD0PID register field to \nprogram either DATA0 or DATA1 PID.\n0: DATA0\n1: DATA1\nBit 15 USBAEP: USB active endpoint\nIndicates whether this endpoint is active in the current configuration and interface. The core \nclears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving \nthe SetConfiguration and SetInterface commands, the application must program endpoint \nregisters accordingly and set this bit.\nBits 14:11 Reserved, must be kept at reset value.\nBits 10:0 MPSIZ: Maximum packet size\nThe application must program this field with the maximum packet size for the current logical \nendpoint. This value is in bytes.\n\n\n<>\n\nRM0090 Rev 21\n1467/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device endpoint-x interrupt register (OTG_HS_DIEPINTx) (x = 0..5, \nwhere x = Endpoint_number)\nAddress offset: 0x908 + 0x20 * x\nReset value: 0x0000 0080\nThis register indicates the status of an endpoint with respect to USB- and AHB-related \nevents. It is shown in Figure 414. The application must read this register when the IN \nendpoints interrupt bit of the Core interrupt register (IEPINT in OTG_HS_GINTSTS) is set. \nBefore the application can read this register, it must first read the device all endpoints \ninterrupt (OTG_HS_DAINT) register to get the exact endpoint number for the device \nendpoint-x interrupt register. The application must clear the appropriate bit in this register to \nclear the corresponding bits in the OTG_HS_DAINT and OTG_HS_GINTSTS registers.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nrc_\nw1\nrc_\nw1\nrc_\nw1\nr\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nBits 31:14 Reserved, must be kept at reset value.\nBit 13 NAK: NAK interrupt\nThe core generates this interrupt when a NAK is transmitted or received by the device. In \ncase of isochronous IN endpoints the interrupt gets generated when a zero length packet is \ntransmitted due to unavailability of data in the Tx FIFO.\nBit 12 Reserved, must be kept at reset value.\nBit 11 PKTDRPSTS: Packet dropped status\nThis bit indicates to the application that an ISOC OUT packet has been dropped. This bit \ndoes not have an associated mask bit and does not generate an interrupt.\nBits 10:9\nReserved, must be kept at reset value.\nBit 8 TXFIFOUDRN: Transmit Fifo Underrun (TxfifoUndrn) The core generates this interrupt when it \ndetects a transmit FIFO underrun condition for this endpoint. \nDependency: This interrupt is valid only when Thresholding is enabled \nBit 7 TXFE: Transmit FIFO empty\nThis interrupt is asserted when the TxFIFO for this endpoint is either half or completely \nempty. The half or completely empty status is determined by the TxFIFO empty level bit in \nthe Core AHB configuration register (TXFELVL bit in OTG_HS_GAHBCFG).\nBit 6 INEPNE: IN endpoint NAK effective\nThis bit can be cleared when the application clears the IN endpoint NAK by writing to the \nCNAK bit in OTG_HS_DIEPCTLx.\nThis interrupt indicates that the core has sampled the NAK bit set (either by the application \nor by the core). The interrupt indicates that the IN endpoint NAK bit set by the application \nhas taken effect in the core.\nThis interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit \ntakes priority over a NAK bit.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1468/1757\nRM0090 Rev 21\nBit 5 INEPNM: IN token received with EP mismatch\nIndicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other \nthan the one for which the IN token was received. This interrupt is asserted on the endpoint \nfor which the IN token was received.\nBit 4 ITTXFE: IN token received when TxFIFO is empty\nApplies to nonperiodic IN endpoints only.\nIndicates that an IN token was received when the associated TxFIFO (periodic/nonperiodic) \nwas empty. This interrupt is asserted on the endpoint for which the IN token was received.\nBit 3 TOC: Timeout condition\nApplies only to Control IN endpoints.\nIndicates that the core has detected a timeout condition on the USB for the last IN token on \nthis endpoint. \nBit 2 AHBERR: AHB error\nThis is generated only in internal DMA mode when there is an AHB error during an AHB \nread/write. The application can read the corresponding endpoint DMA address register to \nget the error address.\nBit 1 EPDISD: Endpoint disabled interrupt\nThis bit indicates that the endpoint is disabled per the application’s request.\nBit 0 XFRC: Transfer completed interrupt\nThis field indicates that the programmed transfer is complete on the AHB as well as on the \nUSB, for this endpoint.\n\n\n<>\n\nRM0090 Rev 21\n1469/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device endpoint-x interrupt register (OTG_HS_DOEPINTx) (x = 0..5, \nwhere x = Endpoint_number)\nAddress offset: 0xB08 + 0x20 * x\nReset value: 0x0000 0080\nThis register indicates the status of an endpoint with respect to USB- and AHB-related \nevents. It is shown in Figure 414. The application must read this register when the OUT \nEndpoints Interrupt bit of the Core interrupt register (OEPINT bit in OTG_HS_GINTSTS) is \nset. Before the application can read this register, it must first read the device all endpoints \ninterrupt (OTG_HS_DAINT) register to get the exact endpoint number for the device \nEndpoint-x interrupt register. The application must clear the appropriate bit in this register to \nclear the corresponding bits in the OTG_HS_DAINT and OTG_HS_GINTSTS registers.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nBits 31:15 Reserved, must be kept at reset value.\nBit 14 NYET: NYET interrupt\nThe core generates this interrupt when a NYET response is transmitted for a \nnonisochronous OUT endpoint.\nBit 13 NAK: NAK input\nThe core generates this interrupt when a NAK is transmitted or received by the device. In \ncase of isochronous IN endpoints the interrupt gets generated when a zero length packet is \ntransmitted due to unavailability of data in the Tx FIFO.\nBit 12 BERR: Babble error interrupt\nThe core generates this interrupt when babble is received for the endpoint.\nBits 11:9 Reserved, must be kept at reset value.\nBit 8 OUTPKTERR: OUT packet error\nThis interrupt is asserted when the core detects an overflow or a CRC error for an OUT \npacket. This interrupt is valid only when thresholding is enabled.\nBit 7 Reserved, must be kept at reset value.\nBit 6 B2BSTUP: Back-to-back SETUP packets received\nApplies to Control OUT endpoint only.\nThis bit indicates that the core has received more than three back-to-back SETUP packets \nfor this particular endpoint.\nBit 5\nReserved, must be kept at reset value.\nBit 4 OTEPDIS: OUT token received when endpoint disabled\nApplies only to control OUT endpoint.\nIndicates that an OUT token was received when the endpoint was not yet enabled. This \ninterrupt is asserted on the endpoint for which the OUT token was received.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1470/1757\nRM0090 Rev 21\nOTG_HS device IN endpoint 0 transfer size register (OTG_HS_DIEPTSIZ0)\nAddress offset: 0x910\nReset value: 0x0000 0000\nThe application must modify this register before enabling endpoint 0. Once endpoint 0 is \nenabled using the endpoint enable bit in the device control endpoint 0 control registers \n(EPENA in OTG_HS_DIEPCTL0), the core modifies this register. The application can only \nread this register once the core has cleared the Endpoint enable bit.\nNonzero endpoints use the registers for endpoints 1–15.\n \n \nBit 3 STUP: SETUP phase done\nApplies to control OUT endpoints only.\nIndicates that the SETUP phase for the control endpoint is complete and no more back-to-\nback SETUP packets were received for the current control transfer. On this interrupt, the \napplication can decode the received SETUP data packet.\nBit 2 AHBERR: AHB error\nThis is generated only in internal DMA mode when there is an AHB error during an AHB \nread/write. The application can read the corresponding endpoint DMA address register to \nget the error address.\nBit 1 EPDISD: Endpoint disabled interrupt\nThis bit indicates that the endpoint is disabled per the application’s request.\nBit 0 XFRC: Transfer completed interrupt\nThis field indicates that the programmed transfer is complete on the AHB as well as on the \nUSB, for this endpoint.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPKTCNT\nReserved\nXFRSIZ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:21 Reserved, must be kept at reset value.\nBits 20:19 PKTCNT: Packet count\nIndicates the total number of USB packets that constitute the Transfer Size amount of data \nfor endpoint 0.\nThis field is decremented every time a packet (maximum size or short packet) is read from \nthe TxFIFO.\nBits 18:7 Reserved, must be kept at reset value.\nBits 6:0 XFRSIZ: Transfer size\nIndicates the transfer size in bytes for endpoint 0. The core interrupts the application only \nafter it has exhausted the transfer size amount of data. The transfer size can be set to the \nmaximum packet size of the endpoint, to be interrupted at the end of each packet.\nThe core decrements this field every time a packet from the external memory is written to \nthe TxFIFO.\n\n\n<>\n\nRM0090 Rev 21\n1471/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device OUT endpoint 0 transfer size register (OTG_HS_DOEPTSIZ0)\nAddress offset: 0xB10\nReset value: 0x0000 0000\nThe application must modify this register before enabling endpoint 0. Once endpoint 0 is \nenabled using the Endpoint enable bit in the device control endpoint 0 control registers \n(EPENA bit in OTG_HS_DOEPCTL0), the core modifies this register. The application can \nonly read this register once the core has cleared the Endpoint enable bit.\nNonzero endpoints use the registers for endpoints 1–15.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSTUPC\nNT\nReserved\nPKTCNT\nReserved\nXFRSIZ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBits 30:29 STUPCNT: SETUP packet count\nThis field specifies the number of back-to-back SETUP data packets the endpoint can \nreceive.\n01: 1 packet\n10: 2 packets\n11: 3 packets\nBits 28:20 Reserved, must be kept at reset value.\nBit 19 PKTCNT: Packet count\nThis field is decremented to zero after a packet is written into the RxFIFO.\nBits 18:7 Reserved, must be kept at reset value.\nBits 6:0 XFRSIZ: Transfer size\nIndicates the transfer size in bytes for endpoint 0. The core interrupts the application only \nafter it has exhausted the transfer size amount of data. The transfer size can be set to the \nmaximum packet size of the endpoint, to be interrupted at the end of each packet.\nThe core decrements this field every time a packet is read from the RxFIFO and written to \nthe external memory.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1472/1757\nRM0090 Rev 21\nOTG_HS device endpoint-x transfer size register (OTG_HS_DIEPTSIZx) \n(x = 1..5, where x = Endpoint_number)\nAddress offset: 0x910 + 0x20 * x\nReset value: 0x0000 0000\nThe application must modify this register before enabling the endpoint. Once the endpoint is \nenabled using the Endpoint enable bit in the device endpoint-x control registers (EPENA bit \nin OTG_HS_DIEPCTLx), the core modifies this register. The application can only read this \nregister once the core has cleared the Endpoint enable bit.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMCNT\nPKTCNT\nXFRSIZ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBits 30:29 MCNT: Multi count\nFor periodic IN endpoints, this field indicates the number of packets that must be transmitted \nper frame on the USB. The core uses this field to calculate the data PID for isochronous IN \nendpoints.\n01: 1 packet\n10: 2 packets\n11: 3 packets\nBit 28:19 PKTCNT: Packet count\nIndicates the total number of USB packets that constitute the Transfer Size amount of data \nfor this endpoint. \nThis field is decremented every time a packet (maximum size or short packet) is read from \nthe TxFIFO.\nBits 18:0 XFRSIZ: Transfer size\nThis field contains the transfer size in bytes for the current endpoint. The core only interrupts \nthe application after it has exhausted the transfer size amount of data. The transfer size can \nbe set to the maximum packet size of the endpoint, to be interrupted at the end of each \npacket.\nThe core decrements this field every time a packet from the external memory is written to the \nTxFIFO.\n\n\n<>\n\nRM0090 Rev 21\n1473/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device IN endpoint transmit FIFO status register \n(OTG_HS_DTXFSTSx) (x = 0..5, where x = Endpoint_number)\nAddress offset for IN endpoints: 0x918 + 0x20 + x\nThis read-only register contains the free space information for the Device IN endpoint \nTxFIFO.\n \n \nOTG_HS device endpoint-x transfer size register (OTG_HS_DOEPTSIZx) \n(x = 1..5, where x = Endpoint_number)\nAddress offset: 0xB10 + 0x20 * x\nReset value: 0x0000 0000\nThe application must modify this register before enabling the endpoint. Once the endpoint is \nenabled using Endpoint Enable bit of the device endpoint-x control registers (EPENA bit in \nOTG_HS_DOEPCTLx), the core modifies this register. The application can only read this \nregister once the core has cleared the Endpoint enable bit.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nINEPTFSAV\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31:16 Reserved, must be kept at reset value.\n15:0 INEPTFSAV: IN endpoint TxFIFO space avail ()\nIndicates the amount of free space available in the Endpoint TxFIFO.\nValues are in terms of 32-bit words:\n0x0: Endpoint TxFIFO is full\n0x1: 1 word available\n0x2: 2 words available\n0xn: n words available (0 < n < 512)\nOthers: Reserved\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRXDPID/S\nTUPCNT\nPKTCNT\nXFRSIZ\nr/rw\nr/rw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1474/1757\nRM0090 Rev 21\n \nOTG_HS device endpoint-x DMA address register (OTG_HS_DIEPDMAx / \nOTG_HS_DOEPDMAx) (x = 0..5, where x = Endpoint_number)\nAddress offset for IN endpoints: 0x914 + 0x20 * x\nReset value: 0xXXXX XXXX\nAddress offset for OUT endpoints: 0xB14 + 0x20 * x\nReset value: 0xXXXX XXXX\n \nBit 31 Reserved, must be kept at reset value.\nBits 30:29 RXDPID: Received data PID (access type is \"r\")\nApplies to isochronous OUT endpoints only.\nThis is the data PID received in the last packet for this endpoint.\n00: DATA0\n01: DATA2\n10: DATA1\n11: MDATA\nSTUPCNT: SETUP packet count (access type is \"rw\")\nApplies to control OUT Endpoints only.\nThis field specifies the number of back-to-back SETUP data packets the endpoint can \nreceive.\n01: 1 packet\n10: 2 packets\n11: 3 packets\nBit 28:19 PKTCNT: Packet count\nIndicates the total number of USB packets that constitute the Transfer Size amount of data \nfor this endpoint.\nThis field is decremented every time a packet (maximum size or short packet) is written to \nthe RxFIFO.\nBits 18:0 XFRSIZ: Transfer size\nThis field contains the transfer size in bytes for the current endpoint. The core only interrupts \nthe application after it has exhausted the transfer size amount of data. The transfer size can \nbe set to the maximum packet size of the endpoint, to be interrupted at the end of each \npacket.\nThe core decrements this field every time a packet is read from the RxFIFO and written to \nthe external memory.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDMAADDR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 DMAADDR: DMA address\nThis bit holds the start address of the external memory for storing or fetching endpoint data.\nNote: For control endpoints, this field stores control OUT data packets as well as SETUP \ntransaction data packets. When more than three SETUP packets are received back-to-\nback, the SETUP data packet in the memory is overwritten. This register is incremented \non every AHB transaction. The application can give only a word-aligned address.\n\n\n<>\n\nRM0090 Rev 21\n1475/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n35.12.5 \nOTG_HS power and clock gating control register\n(OTG_HS_PCGCCTL)\nAddress offset: 0xE00\nReset value: 0x0000 0000\nThis register is available in host and peripheral modes.\n \n \n35.12.6 \nOTG_HS register map\nThe table below gives the USB OTG register map and reset values.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPHYSUSP\nReserved\nGATEHCLK\nSTPPCLK\nrw\nrw\nrw\nBit 31:5 Reserved, must be kept at reset value.\nBit 4 PHYSUSP: PHY suspended\nIndicates that the PHY has been suspended. This bit is updated once the PHY is suspended \nafter the application has set the STPPCLK bit (bit 0).\nBits 3:2 Reserved, must be kept at reset value.\nBit 1 GATEHCLK: Gate HCLK\nThe application sets this bit to gate HCLK to modules other than the AHB Slave and Master \nand wake-up logic when the USB is suspended or the session is not valid. The application \nclears this bit when the USB is resumed or a new session starts.\nBit 0 STPPCLK: Stop PHY clock\nThe application sets this bit to stop the PHY clock when the USB is suspended, the session \nis not valid, or the device is disconnected. The application clears this bit when the USB is \nresumed or a new session starts.\nTable 216. OTG_HS register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x000\nOTG_HS_GO\nTGCTL\nReserved\nBSVLD\nASVLD\nDBCT\nCIDSTS\nReserved\nDHNPEN\nHSHNPEN\nHNPRQ\nHNGSCS\nReserved\nSRQ\nSRQSCS\nReset value\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0x004\nOTG_HS_GO\nTGINT\nReserved\nDBCDNE\nADTOCHG\nHNGDET\nReserved\nHNSSCHG\nSRSSCHG\nReserved\nSEDET\nRes.\nReset value\n0\n0\n0\n0\n0\n0\n0x008\nOTG_HS_GA\nHBCFG\nReserved\nPTXFELVL\nTXFELVL\nReserved\nGINT\nReset value\n0\n0\n0\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1476/1757\nRM0090 Rev 21\n0x00C\nOTG_HS_GU\nSBCFG\nCTXPKT\nFDMOD\nFHMOD\nReserved\nULPIIPD\nPTCI\nPCCI\nTSDPS\nULPIEVBUSI\nULPIEVBUSD\nULPICSM\nULPIAR\nULPIFSLS\nReserved\nPHYLPCS\nReserved\nTRDT\nHNPCAP\nSRPCAP\nReserved\nPHYSEL\nReserve\nd\nTOCAL\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n1\n0\n0\n1\n0\n0\n0\n0x010\nOTG_HS_GR\nSTCTL\nAHBIDL\nDMAREQ\nReserved\nTXFNUM\nTXFFLSH\nRXFFLSH\nReserved\nFCRST\nHSRST\nCSRST\nReset value\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x014\nOTG_HS_GIN\nTSTS\nWKUINT\nSRQINT\nDISCINT\nCIDSCHG\nReserved\nPTXFE\nHCINT\nHPRTINT\nReserved\nDATAFSUSP\nIPXFR/INCOMPISOOUT\nIISOIXFR\nOEPINT\nIEPINT\nReserved\nEOPF\nISOODRP\nENUMDNE\nUSBRST\nUSBSUSP\nESUSP\nReserved\nGONAKEFF\nGINAKEFF\nNPTXFE\nRXFLVL\nSOF\nOTGINT\nMMIS\nCMOD\nReset value\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0x018\nOTG_HS_GIN\nTMSK\nWUIM\nSRQIM\nDISCINT\nCIDSCHGM\nReserved\nPTXFEM\nHCIM\nPRTIM\nReserved\nFSUSPM\nIPXFRM/IISOOXFRM\nIISOIXFRM\nOEPINT\nIEPINT\nReserved\nEOPFM\nISOODRPM\nENUMDNEM\nUSBRST\nUSBSUSPM\nESUSPM\nReserved\nGONAKEFFM\nGINAKEFFM\nNPTXFEM\nRXFLVLM\nSOFM\nOTGINT\nMMISM\nReserved\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x01C\nOTG_HS_GR\nXSTSR (Host \nmode)\nReserved\nPKTSTS\nDPID\nBCNT\nCHNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nOTG_HS_GR\nXSTSR \n(peripheral \nmode)\nReserved\nFRMNUM\nPKTSTS\nDPID\nBCNT\nEPNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x020\nOTG_HS_GR\nXSTSP (Host \nmode)\nReserved\nPKTSTS\nDPID\nBCNT\nCHNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nOTG_HS_GR\nXSTSP \n(peripheral \nmode)\nReserved\nFRMNUM\nPKTSTS\nDPID\nBCNT\nEPNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x024\nOTG_HS_GR\nXFSIZ\nReserved\nRXFD\nReset value\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1477/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n0x028\nOTG_HS_GN\nPTXFSIZ \n(Host mode)\nNPTXFD\nNPTXFSA\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\nOTG_HS_GN\nPTXFSIZ\n(peripheral \nmode)\nTX0FD\nTX0FSA\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x02C\nOTG_HS_GN\nPTXSTS\nRes.\nNPTXQTOP\nNPTQXSAV\nNPTXFSAV\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x030\nOTG_HS_GI2\nCCTL\nBSYDNE\nRW\nReserved\nI2CDATSE0\nI2CDEVADR\nReserved\nACK\nI2CEN\nADDR\nREGADDR\nRWDATA\n0x038\nOTG_HS_GC\nCFG\nReserved\nNOVBUSSENS\nSOFOUTEN\nVBUSBSEN\nVBUSASEN\n.I2CPADEN\n.PWRDWN\nReserved\nReset value\n0\n0\n0\n0\n0\n0\n0x03C\nOTG_HS_CID\nPRODUCT_ID\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0x100\nOTG_HS_HPT\nXFSIZ\nPTXFD\nPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x104\nOTG_HS_DIE\nPTXF1\nINEPTXFD\nINEPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x108\nOTG_HS_DIE\nPTXF2\nINEPTXFD\nINEPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10C\nOTG_HS_DIE\nPTXF3\nINEPTXFD\nINEPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x110\nOTG_HS_DIE\nPTXF4\nINEPTXFD\nINEPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x400\nOTG_HS_HCF\nG\nReserved\nFSLSS\nFSLSPCS\nReset value\n0\n0\n0\n0x404\nOTG_HS_HFI\nR\nReserved\nFRIVL\nReset value\n1\n1\n1\n0\n1\n0\n1\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0x408\nOTG_HS_HFN\nUM\nFTREM\nFRNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x410\nOTG_HS_HPT\nXSTS\nPTXQTOP\nPTXQSAV\nPTXFSAVL\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1478/1757\nRM0090 Rev 21\n0x414\nOTG_HS_HAI\nNT\nReserved\nHAINT\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x418\nOTG_HS_HAI\nNTMSK\nReserved\nHAINTM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x440\nOTG_HS_HPR\nT\nReserved\nPSP\nD\nPTCTL\nPPWR\nPLSTS\nReserved\nPRST\nPSUSP\nPRES\nPOCCHNG\nPOCA\nPENCHNG\nPENA\nPCDET\nPCSTS\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x500\nOTG_HS_HC\nCHAR0\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x520\nOTG_HS_HC\nCHAR1\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x540\nOTG_HS_HC\nCHAR2\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x560\nOTG_HS_HC\nCHAR3\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x580\nOTG_HS_HC\nCHAR4\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5A0\nOTG_HS_HC\nCHAR5\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5C0\nOTG_HS_HC\nCHAR6\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5E0\nOTG_HS_HC\nCHAR7\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x600\nOTG_HS_HC\nCHAR8\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1479/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n0x620\nOTG_HS_HC\nCHAR9\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x640\nOTG_HS_HC\nCHAR10\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x660\nOTG_HS_HC\nCHAR11\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x504\nOTG_HS_HCS\nPLT0\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x508\nOTG_HS_HCI\nNT0\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x524\nOTG_HS_HCS\nPL1\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x528\nOTG_HS_HCI\nNT1\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x544\nOTG_HS_HCS\nPLT2\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x548\nOTG_HS_HCI\nNT2\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x564\nOTG_HS_HCS\nPLT3\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x568\nOTG_HS_HCI\nNT3\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1480/1757\nRM0090 Rev 21\n0x584\nOTG_HS_HCS\nPLT4\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x588\nOTG_HS_HCI\nNT4\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5A4\nOTG_HS_HCS\nPLT5\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5A8\nOTG_HS_HCI\nNT5\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5C4\nOTG_HS_HCS\nPLT6\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5C8\nOTG_HS_HCI\nNT6\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5E4\nOTG_HS_HCS\nPLT7\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5E8\nOTG_HS_HCI\nNT7\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x604\nOTG_HS_HCS\nPLT8\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x608\nOTG_HS_HCI\nNT8\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1481/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n0x624\nOTG_HS_HCS\nPLT9\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x628\nOTG_HS_HCI\nNT9\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x644\nOTG_HS_HCS\nPLT10\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x648\nOTG_HS_HCI\nNT10\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x664\nOTG_HS_HCS\nPLT11\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x668\nOTG_HS_HCI\nNT11\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x50C\nOTG_HS_HCI\nNTMSK0\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x52C\nOTG_HS_HCI\nNTMSK1\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x54C\nOTG_HS_HCI\nNTMSK2\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x56C\nOTG_HS_HCI\nNTMSK3\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x58C\nOTG_HS_HCI\nNTMSK4\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1482/1757\nRM0090 Rev 21\n0x5AC\nOTG_HS_HCI\nNTMSK5\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5CC\nOTG_HS_HCI\nNTMSK6\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5EC\nOTG_HS_HCI\nNTMSK7\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x60C\nOTG_HS_HCI\nNTMSK8\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x62C\nOTG_HS_HCI\nNTMSK9\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x64C\nOTG_HS_HCI\nNTMSK10\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x66C\nOTG_HS_HCI\nNTMSK11\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x510\nOTG_HS_HCT\nSIZ0\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x530\nOTG_HS_HCT\nSIZ1\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x550\nOTG_HS_HCT\nSIZ2\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x570\nOTG_HS_HCT\nSIZ3\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1483/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n0x590\nOTG_HS_HCT\nSIZ4\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5B0\nOTG_HS_HCT\nSIZ5\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5D0\nOTG_HS_HCT\nSIZ6\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5F0\nOTG_HS_HCT\nSIZ7\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x610\nOTG_HS_HCT\nSIZ8\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x630\nOTG_HS_HCT\nSIZ9\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x650\nOTG_HS_HCT\nSIZ10\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x670\nOTG_HS_HCT\nSIZ11\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x514\nOTG_HS_HC\nDMA0\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x524\nOTG_HS_HC\nDMA1\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x544\nOTG_HS_HC\nDMA2\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x564\nOTG_HS_HC\nDMA3\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x584\nOTG_HS_HC\nDMA4\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5A4\nOTG_HS_HC\nDMA5\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1484/1757\nRM0090 Rev 21\n0x5C4\nOTG_HS_HC\nDMA6\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5E4\nOTG_HS_HC\nDMA7\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x604\nOTG_HS_HC\nDMA8\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x624\nOTG_HS_HC\nDMA9\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x644\nOTG_HS_HC\nDMA10\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x664\nOTG_HS_HC\nDMA11\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x800\nOTG_HS_\nDCFG\nReserved\nPERSCHIVL\nReserved\nReserved\nPFIVL\nDAD\nReserved\nNZLSOHSK\nDSPD\nReset value\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x804\nOTG_HS_DCT\nL\nReserved\nPOPRGDNE\nCGONAK\nSGONAK\nCGINAK\nSGINAK\nTCTL\nGONSTS\nGINSTS\nSDIS\nRWUSIG\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x808\nOTG_HS_DST\nS\nReserved\nFNSOF\nReserved\nEERR\nENUMSPD\nSUSPSTS\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x810\nOTG_HS_DIE\nPMSK\nReserved\nNAKM\nReserved\nTXFURM\nReserved\nINEPNEM\nINEPNMM\nITTXFEMSK\nTOM\nAHBERRM\nEPDM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x814\nOTG_HS_DO\nEPMSK\nReserved\nNYETMSK\nNAKMSK\nBERRM\nReserved\nOPEM\nReserved\n B2BSTUP\nSTSPHSRXM\n OTEPDM\nSTUPM\nAHBERRM\nEPDM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x818\nOTG_HS_DAI\nNT\nOEPINT\nIEPINT\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x81C\nOTG_HS_DAI\nNTMSK\nOEPM\nIEPM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x828\nOTG_HS_DVB\nUSDIS\nReserved\nVBUSDT\nReset value\n0\n0\n0\n1\n0\n1\n1\n1\n1\n1\n0\n1\n0\n1\n1\n1\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1485/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n0x82C\nOTG_HS_DVB\nUSPULSE\nReserved\nDVBUSP\nReset value\n0\n1\n0\n1\n1\n0\n1\n1\n1\n0\n0\n0\n0x830\nOTG_HS_DTH\nRCTL\nReserved\nARPEN\nReserved\nRXTHRLEN\nRXTHREN\nReserved\nTXTHRLEN\nISOTHREN\nNONISOTHREN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x834\nOTG_HS_DIE\nPEMPMSK\nReserved\nINEPTXFEM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x838\nOTG_HS_DEA\nCHINT\nReserved\nReserved\nReserved\nReset value\n0\n0\n0x83C\nOTG_HS_DEA\nCHINTMSK\nReserved\nReserved\nReserved\nReset value\n0\n0\n0x844\nOTG_HS_DIE\nPEACHMSK1\nReserved\nNAKM\nReserve\nd\nBIM\nTXFURM\nReserved\nINEPNEM\nINEPNMM\nITTXFEMSK\nTOM\nAHBERRM\nEPDM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x884\nOTG_HS_DO\nEPEACHMSK\n1\nReserved\nNYETM\nNAKM\nBERRM\nReserved\nBIM\nTXFURM\nReserved\nINEPNEM\nINEPNMM\nITTXFEMSK\nTOM\nAHBERRM\nEPDM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x900\nOTG_HS_DIE\nPCTL0\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x918\nOTG_HS_DTX\nFSTS0\nReserved\nINEPTFSAV\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x920\nOTG_HS_DIE\nPCTL1\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nStall\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x938\nOTG_HS_DTX\nFSTS1\nReserved\nINEPTFSAV\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1486/1757\nRM0090 Rev 21\n0x940\nOTG_HS_DIE\nPCTL2\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nStall\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x958\nOTG_HS_DTX\nFSTS2\nReserved\nINEPTFSAV\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x960\nOTG_HS_DIE\nPCTL3\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nStall\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x978\nOTG_HS_DTX\nFSTS3\nReserved\nINEPTFSAV\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x980\nOTG_HS_DIE\nPCTL4\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nStall\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x9A0\nOTG_HS_DIE\nPCTL5\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x9C0\nOTG_HS_DIE\nPCTL6\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x9E0\nOTG_HS_DIE\nPCTL7\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB00\nOTG_HS_DO\nEPCTL0\nEPENA\nEPDIS\nReserved\nSNAK\nCNAK\nReserved\nSTALL\nSNPM\nEPT\nYP\nNAKSTS\nReserved\nUSBAEP\nReserved\nMPSI\nZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1487/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n0xB20\nOTG_HS_DO\nEPCTL1\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nReserved\nSTALL\nSNPM\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB40\nOTG_HS_DO\nEPCTL2\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nReserved\nStall\nSNPM\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB60\nOTG_HS_DO\nEPCTL3\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nReserved\nStall\nSNPM\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x908\nOTG_HS_DIE\nPINT0\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0x928\nOTG_HS_DIE\nPINT1\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0x948\nOTG_HS_DIE\nPINT2\nReserved\nNAK\nBERR\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nReset value\n0\nReserved\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0x968\nOTG_HS_DIE\nPINT3\nReserved\nNAK\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0x988\nOTG_HS_DIE\nPINT4\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1488/1757\nRM0090 Rev 21\n0x9A8\nOTG_HS_DIE\nPINT5\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0x9C8\nOTG_HS_DIE\nPINT6\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0x9E8\nOTG_HS_DIE\nPINT7\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0xB08\nOTG_HS_DO\nEPINT0\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0xB28\nOTG_HS_DO\nEPINT1\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB48\nOTG_HS_DO\nEPINT2\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB68\nOTG_HS_DO\nEPINT3\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB88\nOTG_HS_DO\nEPINT4\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xBA8\nOTG_HS_DO\nEPINT5\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1489/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n0xBC8\nOTG_HS_DO\nEPINT6\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xBE8\nOTG_HS_DO\nEPINT7\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x910\nOTG_HS_DIE\nPTSIZ0\nReserved\nPKT\nCNT\nReserved\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x930\nOTG_HS_DIE\nPTSIZ1\nReserved\nMCN\nT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x934\nOTG_HS_DIE\nPDMA1\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x93C\nOTG_HS_DIE\nPDMAB1\nDMABADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x950\nOTG_HS_DIE\nPTSIZ2\nReserved\nMCN\nT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x954\nOTG_HS_DIE\nPDMA2\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x95C\nOTG_HS_DIE\nPDMAB2\nDMABADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x970\nOTG_HS_DIE\nPTSIZ3\nReserved\nMCN\nT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x974\nOTG_HS_DIE\nPDMA3\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x97C\nOTG_HS_DIE\nPDMAB3\nDMABADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB10\nOTG_HS_DO\nEPTSIZ0\nReserved\nSTU\nPCN\nT\nReserved\nPKTCNT\nReserved\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB30\nOTG_HS_DO\nEPTSIZ1\nReserved\nRXDPID/\nSTUPCNT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB34\nOTG_HS_DO\nEPDMA1\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1490/1757\nRM0090 Rev 21\nRefer to Section 2.3: Memory map for the register boundary addresses.\n35.13 \nOTG_HS programming model\n35.13.1 \nCore initialization\nThe application must perform the core initialization sequence. If the cable is connected \nduring power-up, the current mode of operation bit in the Core interrupt register (CMOD bit \nin OTG_HS_GINTSTS) reflects the mode. The OTG_HS controller enters host mode when \nan “A” plug is connected or peripheral mode when a “B” plug is connected.\nThis section explains the initialization of the OTG_HS controller after power-on. The \napplication must follow the initialization sequence irrespective of host or peripheral mode \noperation. All core global registers are initialized according to the core’s configuration:\n0xB3C\nOTG_HS_DO\nEPDMAB1\nDMABADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB50\nOTG_HS_DO\nEPTSIZ2\nReserved\nRXDPID/\nSTUPCNT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB54\nOTG_HS_DO\nEPDMA2\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB5C\nOTG_HS_DO\nEPDMAB2\nDMABADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB70\nOTG_HS_DO\nEPTSIZ3\nReserved\nRXDPID/\nSTUPCNT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB74\nOTG_HS_DO\nEPDMA3\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB7C\nOTG_HS_DO\nEPDMAB3\nDMABADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xE00\nOTG_HS_PC\nGCCTL\nReserved\nPHYSUSP\nReserved\nGATEHCLK\nSTPPCLK\nReset value\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1491/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n1.\nProgram the following fields in the Global AHB configuration (OTG_HS_GAHBCFG) \nregister:\n–\nDMA mode bit\n–\nAHB burst length field\n–\nGlobal interrupt mask bit GINT = 1\n–\nRxFIFO nonempty (RXFLVL bit in OTG_HS_GINTSTS)\n–\nPeriodic TxFIFO empty level\n2. \nProgram the following fields in OTG_HS_GUSBCFG register:\n–\nHNP capable bit \n–\nSRP capable bit\n–\nFS timeout calibration field\n–\nUSB turnaround time field\n3. \nThe software must unmask the following bits in the GINTMSK register:\nOTG interrupt mask\nMode mismatch interrupt mask\n4. \nThe software can read the CMOD bit in OTG_HS_GINTSTS to determine whether the \nOTG_HS controller is operating in host or peripheral mode.\n35.13.2 \nHost initialization\nTo initialize the core as host, the application must perform the following steps:\n1.\nProgram the HPRTINT in GINTMSK to unmask\n2. \nProgram the OTG_HS_HCFG register to select full-speed host\n3. \nProgram the PPWR bit in OTG_HS_HPRT to 1. This drives VBUS on the USB.\n4. \nWait for the PCDET interrupt in OTG_HS_HPRT0. This indicates that a device is \nconnecting to the port.\n5. \nProgram the PRST bit in OTG_HS_HPRT to 1. This starts the reset process.\n6. \nWait at least 10 ms for the reset process to complete.\n7. \nProgram the PRST bit in OTG_HS_HPRT to 0.\n8. \nWait for the PENCHNG interrupt in OTG_HS_HPRT.\n9. \nRead the PSPD bit in OTG_HS_HPRT to get the enumerated speed.\n10. Program the HFIR register with a value corresponding to the selected PHY clock 1.\n11. Program the FSLSPCS field in OTG_HS_HCFG register according to the speed of the \ndetected device read in step 9. If FSLSPCS has been changed, reset the port.\n12. Program the OTG_HS_GRXFSIZ register to select the size of the receive FIFO.\n13. Program the OTG_HS_GNPTXFSIZ register to select the size and the start address of \nthe nonperiodic transmit FIFO for nonperiodic transactions.\n14. Program the OTG_HS_HPTXFSIZ register to select the size and start address of the \nperiodic transmit FIFO for periodic transactions.\nTo communicate with devices, the system software must initialize and enable at least one \nchannel.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1492/1757\nRM0090 Rev 21\n35.13.3 \nDevice initialization\nThe application must perform the following steps to initialize the core as a device on power-\nup or after a mode change from host to device.\n1.\nProgram the following fields in the OTG_HS_DCFG register:\n–\nDevice speed\n–\nNonzero-length status OUT handshake\n2. \nProgram the OTG_HS_GINTMSK register to unmask the following interrupts:\n–\nUSB reset\n–\nEnumeration done\n–\nEarly suspend\n–\nUSB suspend\n–\nSOF\n3. \nProgram the VBUSBSEN bit in the OTG_HS_GCCFG register to enable VBUS sensing \nin “B” peripheral mode and supply the 5 volts across the pull-up resistor on the DP line.\n4. \nWait for the USBRST interrupt in OTG_HS_GINTSTS. It indicates that a reset has \nbeen detected on the USB that lasts for about 10 ms on receiving this interrupt.\nWait for the ENUMDNE interrupt in OTG_HS_GINTSTS. This interrupt indicates the end of \nreset on the USB. On receiving this interrupt, the application must read the OTG_HS_DSTS \nregister to determine the enumeration speed and perform the steps listed in Endpoint \ninitialization on enumeration completion on page 1519. \nAt this point, the device is ready to accept SOF packets and perform control transfers on \ncontrol endpoint 0.\n35.13.4 \nDMA mode\nThe OTG host uses the AHB master interface to fetch the transmit packet data (AHB to \nUSB) and receive the data update (USB to AHB). The AHB master uses the programmed \nDMA address (HCDMAx register in host mode and DIEPDMAx/DOEPDMAx register in \nperipheral mode) to access the data buffers.\n35.13.5 \nHost programming model\nChannel initialization\nThe application must initialize one or more channels before it can communicate with \nconnected devices. To initialize and enable a channel, the application must perform the \nfollowing steps:\n\n\n<>\n\nRM0090 Rev 21\n1493/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n1.\nProgram the GINTMSK register to unmask the following:\n2. \nChannel interrupt\n–\nNonperiodic transmit FIFO empty for OUT transactions (applicable for Slave mode \nthat operates in pipelined transaction-level with the packet count field \nprogrammed with more than one).\n–\nNonperiodic transmit FIFO half-empty for OUT transactions (applicable for Slave \nmode that operates in pipelined transaction-level with the packet count field \nprogrammed with more than one).\n3. \nProgram the OTG_HS_HAINTMSK register to unmask the selected channels’ \ninterrupts.\n4. \nProgram the OTG_HS_HCINTMSK register to unmask the transaction-related \ninterrupts of interest given in the host channel interrupt register.\n5. \nProgram the selected channel’s OTG_HS_HCTSIZx register with the total transfer size, \nin bytes, and the expected number of packets, including short packets. The application \nmust program the PID field with the initial data PID (to be used on the first OUT \ntransaction or to be expected from the first IN transaction).\n6. \nProgram the selected channels in the OTG_HS_HCSPLTx register(s) with the hub and \nport addresses (split transactions only).\n7. \nProgram the selected channels in the HCDMAx register(s) with the buffer start address.\n8. \nProgram the OTG_HS_HCCHARx register of the selected channel with the device’s \nendpoint characteristics, such as type, speed, direction, and so forth. (The channel can \nbe enabled by setting the channel enable bit to 1 only when the application is ready to \ntransmit or receive any packet).\nHalting a channel\nThe application can disable any channel by programming the OTG_HS_HCCHARx register \nwith the CHDIS and CHENA bits set to 1. This enables the OTG_HS host to flush the posted \nrequests (if any) and generates a channel halted interrupt. The application must wait for the \nCHH interrupt in OTG_HS_HCINTx before reallocating the channel for other transactions. \nThe OTG_HS host does not interrupt the transaction that has already been started on the \nUSB.\nTo disable a channel in DMA mode operation, the application does not need to check for \nspace in the request queue. The OTG_HS host checks for space to write the disable \nrequest on the disabled channel’s turn during arbitration. Meanwhile, all posted requests are \ndropped from the request queue when the CHDIS bit in HCCHARx is set to 1. \nBefore disabling a channel, the application must ensure that there is at least one free space \navailable in the nonperiodic request queue (when disabling a nonperiodic channel) or the \nperiodic request queue (when disabling a periodic channel). The application can simply \nflush the posted requests when the Request queue is full (before disabling the channel), by \nprogramming the OTG_HS_HCCHARx register with the CHDIS bit set to 1, and the CHENA \nbit cleared to 0.\nThe application is expected to disable a channel on any of the following conditions:\n1.\nWhen an XFRC interrupt in OTG_HS_HCINTx is received during a nonperiodic IN \ntransfer or high-bandwidth interrupt IN transfer (Slave mode only)\n2. \nWhen an STALL, TXERR, BBERR or DTERR interrupt in OTG_HS_HCINTx is \nreceived for an IN or OUT channel (Slave mode only). For high-bandwidth interrupt INs \nin Slave mode, once the application has received a DTERR interrupt it must disable the \n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1494/1757\nRM0090 Rev 21\nchannel and wait for a channel halted interrupt. The application must be able to receive \nother interrupts (DTERR, NAK, Data, TXERR) for the same channel before receiving \nthe halt.\n3. \nWhen a DISCINT (Disconnect Device) interrupt in OTG_HS_GINTSTS is received. \n(The application is expected to disable all enabled channels\n4. \nWhen the application aborts a transfer before normal completion.\nPing protocol\nWhen the OTG_HS host operates in high speed, the application must initiate the ping \nprotocol when communicating with high-speed bulk or control (data and status stage) OUT \nendpoints.\nThe application must initiate the ping protocol when it receives a NAK/NYET/TXERR \ninterrupt. When the HS_OTG host receives one of the above responses, it does not \ncontinue any transaction for a specific endpoint, drops all posted or fetched OUT requests \n(from the request queue), and flushes the corresponding data (from the transmit FIFO).\nThis is valid in slave mode only. In Slave mode, the application can send a ping token either \nby setting the DOPING bit in HCTSIZx before enabling the channel or by just writing the \nHCTSIZx register with the DOPING bit set when the channel is already enabled. This \nenables the HS_OTG host to write a ping request entry to the request queue. The \napplication must wait for the response to the ping token (a NAK, ACK, or TXERR interrupt) \nbefore continuing the transaction or sending another ping token. The application can \ncontinue the data transaction only after receiving an ACK from the OUT endpoint for the \nrequested ping. In DMA mode operation, the application does not need to set the DOPING \nbit in HCTSIZx for a NAK/NYET response in case of Bulk/Control OUT. The OTG_HS host \nautomatically sets the DOPING bit in HCTSIZx, and issues the ping tokens for Bulk/Control \nOUT. The HS_OTG host continues sending ping tokens until it receives an ACK, and then \nswitches automatically to the data transaction.\nOperational model\nThe application must initialize a channel before communicating to the connected device. \nThis section explains the sequence of operation to be performed for different types of USB \ntransactions.\n•\nWriting the transmit FIFO\nThe OTG_HS host automatically writes an entry (OUT request) to the periodic/nonperiodic \nrequest queue, along with the last word write of a packet. The application must ensure that \nat least one free space is available in the periodic/nonperiodic request queue before starting \nto write to the transmit FIFO. The application must always write to the transmit FIFO in \nwords. If the packet size is non-word-aligned, the application must use padding. The \nOTG_HS host determines the actual packet size based on the programmed maximum \npacket size and transfer size.\n\n\n<>\n\nRM0090 Rev 21\n1495/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nFigure 416. Transmit FIFO write task\nMSv65219V1\n1 MPS\nor LPS FIFO space\navailable?\nWait for\nTXFELVL or PTXFELVL \ninterrupt in \nOTG_HS_GAHBCFG\nWrite 1 packet \ndata to\nTransmit FIFO\nMore packets\nto send?\nRead GNPTXSTS/HPTXFSIZ \nregisters for available FIFO \nand queue spaces\nStart\nDone\nNo\nYes\nYes\nNo\nMPS: Maximum packet size\nLPS: Last packet size\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1496/1757\nRM0090 Rev 21\n•\nReading the receive FIFO\nThe application must ignore all packet statuses other than IN data packet (bx0010).\nFigure 417. Receive FIFO read task\n•\nBulk and control OUT/SETUP transactions\nA typical bulk or control OUT/SETUP pipelined transaction-level operation is shown in \nFigure 418. See channel 1 (ch_1). Two bulk OUT packets are transmitted. A control \nSETUP transaction operates in the same way but has only one packet. The \nassumptions are:\n–\nThe application is attempting to send two maximum-packet-size packets (transfer \nsize = 1, 024 bytes).\n–\nThe nonperiodic transmit FIFO can hold two packets (128 bytes for FS).\n–\nThe nonperiodic request queue depth = 4.\n•\nNormal bulk and control OUT/SETUP operations\nThe sequence of operations for channel 1 is as follows:\na) \nInitialize channel 1\nb) \nWrite the first packet for channel 1\nMSv65220V1\nRXFLVL\ninterrupt?\nRead the received\npacket from the\nReceive FIFO\nRead \nOTG_HS_GRXSTSP\nPKTSTS\n0b0010?\nUnmask RXFLVL\ninterrupt\nBCNT > 0?\nMask RXFLVL\ninterrupt\nUnmask RXFLVL\ninterrupt\nStart\nNo\nNo\nNo\nYes\nYes\nYes\n\n\n<>\n\nRM0090 Rev 21\n1497/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nc) \nAlong with the last word write, the core writes an entry to the nonperiodic request \nqueue\nd) \nAs soon as the nonperiodic queue becomes nonempty, the core attempts to send \nan OUT token in the current frame\ne) \nWrite the second (last) packet for channel 1\nf) \nThe core generates the XFRC interrupt as soon as the last transaction is \ncompleted successfully\ng) \nIn response to the XFRC interrupt, de-allocate the channel for other transfers\nh) \nHandling nonACK responses\nFigure 418. Normal bulk/control OUT/SETUP and bulk/control IN transactions - DMA\nmode\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1498/1757\nRM0090 Rev 21\nFigure 419. Normal bulk/control OUT/SETUP and bulk/control IN transactions - Slave\nmode\nThe channel-specific interrupt service routine for bulk and control OUT/SETUP \ntransactions in Slave mode is shown in the following code samples.\n•\nInterrupt service routine for bulk/control OUT/SETUP and bulk/control IN \ntransactions\na) \nBulk/Control OUT/SETUP\nUnmask (NAK/TXERR/STALL/XFRC)\nif (XFRC)\n{\nReset Error Count\n\n\n<>\n\nRM0090 Rev 21\n1499/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nMask ACK\nDe-allocate Channel\n}\nelse if (STALL)\n{\nTransfer Done = 1\nUnmask CHH\nDisable Channel\n}\nelse if (NAK or TXERR )\n{\nRewind Buffer Pointers\nUnmask CHH\nDisable Channel\nif (TXERR)\n{\nIncrement Error Count\nUnmask ACK\n}\nelse\n{\nReset Error Count\n}\n}\nelse if (CHH)\n{\nMask CHH\nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\nelse\n{\nRe-initialize Channel\n}\n}\nelse if (ACK)\n{\nReset Error Count\nMask ACK\n}\nThe application is expected to write the data packets into the transmit FIFO as and \nwhen the space is available in the transmit FIFO and the Request queue. The \napplication can make use of the NPTXFE interrupt in OTG_HS_GINTSTS to find the \ntransmit FIFO space.\nb) \nBulk/Control IN\nUnmask (TXERR/XFRC/BBERR/STALL/DTERR)\nif (XFRC)\n{\nReset Error Count\nUnmask CHH\nDisable Channel\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1500/1757\nRM0090 Rev 21\nReset Error Count\nMask ACK\n}\nelse if (TXERR or BBERR or STALL)\n{\nUnmask CHH\nDisable Channel\nif (TXERR)\n{\nIncrement Error Count\nUnmask ACK\n}\n}\nelse if (CHH)\n{\nMask CHH\nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\nelse\n{\nRe-initialize Channel\n}\n}\nelse if (ACK)\n{\nReset Error Count\nMask ACK\n}\nelse if (DTERR)\n{\nReset Error Count\n}\nThe application is expected to write the requests as and when the Request queue \nspace is available and until the XFRC interrupt is received.\n•\nBulk and control IN transactions\nA typical bulk or control IN pipelined transaction-level operation is shown in Figure 420. \nSee channel 2 (ch_2). The assumptions are:\n–\nThe application is attempting to receive two maximum-packet-size packets \n(transfer size = 1 024 bytes).\n–\nThe receive FIFO can contain at least one maximum-packet-size packet and two \nstatus words per packet (72 bytes for FS).\n–\nThe nonperiodic request queue depth = 4.\n\n\n<>\n\nRM0090 Rev 21\n1501/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nFigure 420. Bulk/control IN transactions - DMA mode\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1502/1757\nRM0090 Rev 21\nFigure 421. Bulk/control IN transactions - Slave mode\nThe sequence of operations is as follows:\na) \nInitialize channel 2.\nb) \nSet the CHENA bit in HCCHAR2 to write an IN request to the nonperiodic request \nqueue.\nc) \nThe core attempts to send an IN token after completing the current OUT \ntransaction.\nd) \nThe core generates an RXFLVL interrupt as soon as the received packet is written \nto the receive FIFO.\ne) \nIn response to the RXFLVL interrupt, mask the RXFLVL interrupt and read the \nreceived packet status to determine the number of bytes received, then read the \n\n\n<>\n\nRM0090 Rev 21\n1503/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nreceive FIFO accordingly. Following this, unmask the RXFLVL interrupt.\nf) \nThe core generates the RXFLVL interrupt for the transfer completion status entry \nin the receive FIFO.\ng) \nThe application must read and ignore the receive packet status when the receive \npacket status is not an IN data packet (PKTSTS in GRXSTSR ≠0b0010).\nh) \nThe core generates the XFRC interrupt as soon as the receive packet status is \nread.\ni) \nIn response to the XFRC interrupt, disable the channel and stop writing the \nOTG_HS_HCCHAR2 register for further requests. The core writes a channel \ndisable request to the nonperiodic request queue as soon as the \nOTG_HS_HCCHAR2 register is written.\nj) \nThe core generates the RXFLVL interrupt as soon as the halt status is written to \nthe receive FIFO.\nk) \nRead and ignore the receive packet status.\nl) \nThe core generates a CHH interrupt as soon as the halt status is popped from the \nreceive FIFO.\nm) In response to the CHH interrupt, de-allocate the channel for other transfers.\nn) \nHandling nonACK responses\n•\nControl transactions in slave mode\nSetup, Data, and Status stages of a control transfer must be performed as three \nseparate transfers. Setup-, Data- or Status-stage OUT transactions are performed \nsimilarly to the bulk OUT transactions explained previously. Data- or Status-stage IN \ntransactions are performed similarly to the bulk IN transactions explained previously. \nFor all three stages, the application is expected to set the EPTYP field in \nOTG_HS_HCCHAR1 to Control. During the Setup stage, the application is expected to \nset the PID field in OTG_HS_HCTSIZ1 to SETUP.\n•\nInterrupt OUT transactions\nA typical interrupt OUT operation in Slave mode is shown in Figure 422. The \nassumptions are:\n–\nThe application is attempting to send one packet in every frame (up to 1 maximum \npacket size), starting with the odd frame (transfer size = 1 024 bytes)\n–\nThe periodic transmit FIFO can hold one packet (1 KB)\n–\nPeriodic request queue depth = 4\nThe sequence of operations is as follows:\na) \nInitialize and enable channel 1. The application must set the ODDFRM bit in \nOTG_HS_HCCHAR1.\nb) \nWrite the first packet for channel 1. For a high-bandwidth interrupt transfer, the \napplication must write the subsequent packets up to MCNT (maximum number of \npackets to be transmitted in the next frame times) before switching to another \nchannel.\nc) \nAlong with the last word write of each packet, the OTG_HS host writes an entry to \nthe periodic request queue.\nd) \nThe OTG_HS host attempts to send an OUT token in the next (odd) frame.\ne) \nThe OTG_HS host generates an XFRC interrupt as soon as the last packet is \ntransmitted successfully.\nf) \nIn response to the XFRC interrupt, reinitialize the channel for the next transfer.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1504/1757\nRM0090 Rev 21\nFigure 422. Normal interrupt OUT/IN transactions - DMA mode\n\n\n<>\n\nRM0090 Rev 21\n1505/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nFigure 423. Normal interrupt OUT/IN transactions - Slave mode\n•\nInterrupt service routine for interrupt OUT/IN transactions\na) \nInterrupt OUT\nUnmask (NAK/TXERR/STALL/XFRC/FRMOR)\nif (XFRC)\n{\nReset Error Count\nMask ACK\nDe-allocate Channel\n}\nelse\nif (STALL or FRMOR)\n{\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1506/1757\nRM0090 Rev 21\nMask ACK\nUnmask CHH\nDisable Channel\nif (STALL)\n{\nTransfer Done = 1\n}\n}\nelse\nif (NAK or TXERR)\n{\nRewind Buffer Pointers\nReset Error Count\nMask ACK\nUnmask CHH\nDisable Channel\n}\nelse\nif (CHH)\n{\nMask CHH\nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\nelse\n{\nRe-initialize Channel (in next b_interval - 1 Frame)\n}\n}\nelse\nif (ACK)\n{\nReset Error Count\nMask ACK\n}\nThe application is expected to write the data packets into the transmit FIFO when the \nspace is available in the transmit FIFO and the Request queue up to the count \nspecified in the MCNT field before switching to another channel. The application uses \nthe NPTXFE interrupt in OTG_HS_GINTSTS to find the transmit FIFO space.\nb) \nInterrupt IN\nUnmask (NAK/TXERR/XFRC/BBERR/STALL/FRMOR/DTERR)\nif (XFRC)\n{\nReset Error Count\nMask ACK\nif (OTG_HS_HCTSIZx.PKTCNT == 0)\n{\nDe-allocate Channel\n}\nelse\n{\n\n\n<>\n\nRM0090 Rev 21\n1507/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nTransfer Done = 1\nUnmask CHH\nDisable Channel\n}\n}\nelse\nif (STALL or FRMOR or NAK or DTERR or BBERR)\n{\nMask ACK\nUnmask CHH\nDisable Channel\n \nif (STALL or BBERR)\n{\nReset Error Count\nTransfer Done = 1\n}\nelse\nif (!FRMOR)\n{\nReset Error Count\n}\n}\nelse\nif (TXERR)\n{\nIncrement Error Count\nUnmask ACK\nUnmask CHH\nDisable Channel\n}\nelse\nif (CHH)\n{\nMask CHH\n \nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\n \nelse\n \nRe-initialize Channel (in next b_interval - 1 /Frame)\n}\n}\nelse\nif (ACK)\n{\nReset Error Count\nMask ACK\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1508/1757\nRM0090 Rev 21\n}\nThe application is expected to write the requests for the same channel when the \nRequest queue space is available up to the count specified in the MCNT field before \nswitching to another channel (if any).\n•\nInterrupt IN transactions\nThe assumptions are:\n–\nThe application is attempting to receive one packet (up to 1 maximum packet size) \nin every frame, starting with odd (transfer size = 1 024 bytes).\n–\nThe receive FIFO can hold at least one maximum-packet-size packet and two \nstatus words per packet (1 031 bytes).\n–\nPeriodic request queue depth = 4.\n•\nNormal interrupt IN operation\nThe sequence of operations is as follows:\na) \nInitialize channel 2. The application must set the ODDFRM bit in \nOTG_HS_HCCHAR2.\nb) \nSet the CHENA bit in OTG_HS_HCCHAR2 to write an IN request to the periodic \nrequest queue. For a high-bandwidth interrupt transfer, the application must write \nthe OTG_HS_HCCHAR2 register MCNT (maximum number of expected packets \nin the next frame times) before switching to another channel.\nc) \nThe OTG_HS host writes an IN request to the periodic request queue for each \nOTG_HS_HCCHAR2 register write with the CHENA bit set.\nd) \nThe OTG_HS host attempts to send an IN token in the next (odd) frame.\ne) \nAs soon as the IN packet is received and written to the receive FIFO, the OTG_HS \nhost generates an RXFLVL interrupt.\nf) \nIn response to the RXFLVL interrupt, read the received packet status to determine \nthe number of bytes received, then read the receive FIFO accordingly. The \napplication must mask the RXFLVL interrupt before reading the receive FIFO, and \nunmask after reading the entire packet.\ng) \nThe core generates the RXFLVL interrupt for the transfer completion status entry \nin the receive FIFO. The application must read and ignore the receive packet \nstatus when the receive packet status is not an IN data packet (PKTSTS in \nGRXSTSR ≠0b0010).\nh) \nThe core generates an XFRC interrupt as soon as the receive packet status is \nread.\ni) \nIn response to the XFRC interrupt, read the PKTCNT field in OTG_HS_HCTSIZ2. \nIf the PKTCNT bit in OTG_HS_HCTSIZ2 is not equal to 0, disable the channel \nbefore re-initializing the channel for the next transfer, if any). If PKTCNT bit in \n\n\n<>\n\nRM0090 Rev 21\n1509/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS_HCTSIZ2 = 0, reinitialize the channel for the next transfer. This time, the \napplication must reset the ODDFRM bit in OTG_HS_HCCHAR2.\n•\nIsochronous OUT transactions\nA typical isochronous OUT operation in Slave mode is shown in Figure 424. The \nassumptions are:\n–\nThe application is attempting to send one packet every frame (up to 1 maximum \npacket size), starting with an odd frame. (transfer size = 1 024 bytes).\n–\nThe periodic transmit FIFO can hold one packet (1 KB).\n–\nPeriodic request queue depth = 4.\nThe sequence of operations is as follows:\na) \nInitialize and enable channel 1. The application must set the ODDFRM bit in \nOTG_HS_HCCHAR1.\nb) \nWrite the first packet for channel 1. For a high-bandwidth isochronous transfer, the \napplication must write the subsequent packets up to MCNT (maximum number of \npackets to be transmitted in the next frame times before switching to another \nchannel.\nc) \nAlong with the last word write of each packet, the OTG_HS host writes an entry to \nthe periodic request queue.\nd) \nThe OTG_HS host attempts to send the OUT token in the next frame (odd).\ne) \nThe OTG_HS host generates the XFRC interrupt as soon as the last packet is \ntransmitted successfully.\nf) \nIn response to the XFRC interrupt, reinitialize the channel for the next transfer.\ng) \nHandling nonACK responses\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1510/1757\nRM0090 Rev 21\nFigure 424. Normal isochronous OUT/IN transactions - DMA mode\n\n\n<>\n\nRM0090 Rev 21\n1511/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nFigure 425. Normal isochronous OUT/IN transactions - Slave mode\n•\nInterrupt service routine for isochronous OUT/IN transactions\nCode sample: Isochronous OUT\nUnmask (FRMOR/XFRC)\nif (XFRC)\n{\nDe-allocate Channel\n}\nelse\nif (FRMOR)\n{\nUnmask CHH\nDisable Channel\n}\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1512/1757\nRM0090 Rev 21\nelse\nif (CHH)\n{\nMask CHH\nDe-allocate Channel\n}\nCode sample: Isochronous IN\nUnmask (TXERR/XFRC/FRMOR/BBERR)\nif (XFRC or FRMOR)\n{\nif (XFRC and (OTG_HS_HCTSIZx.PKTCNT == 0))\n{\nReset Error Count\nDe-allocate Channel\n}\nelse\n{\nUnmask CHH\nDisable Channel\n}\n}\nelse\nif (TXERR or BBERR)\n{\nIncrement Error Count\nUnmask CHH\nDisable Channel\n}\nelse\nif (CHH)\n{\nMask CHH\nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\nelse\n{\nRe-initialize Channel\n}\n}\n\n\n<>\n\nRM0090 Rev 21\n1513/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n \n•\nIsochronous IN transactions\nThe assumptions are:\n–\nThe application is attempting to receive one packet (up to 1 maximum packet size) \nin every frame starting with the next odd frame (transfer size = 1 024 bytes).\n–\nThe receive FIFO can hold at least one maximum-packet-size packet and two \nstatus words per packet (1 031 bytes).\n–\nPeriodic request queue depth = 4.\nThe sequence of operations is as follows:\na) \nInitialize channel 2. The application must set the ODDFRM bit in \nOTG_HS_HCCHAR2.\nb) \nSet the CHENA bit in OTG_HS_HCCHAR2 to write an IN request to the periodic \nrequest queue. For a high-bandwidth isochronous transfer, the application must \nwrite the OTG_HS_HCCHAR2 register MCNT (maximum number of expected \npackets in the next frame times) before switching to another channel.\nc) \nThe OTG_HS host writes an IN request to the periodic request queue for each \nOTG_HS_HCCHAR2 register write with the CHENA bit set.\nd) \nThe OTG_HS host attempts to send an IN token in the next odd frame.\ne) \nAs soon as the IN packet is received and written to the receive FIFO, the OTG_HS \nhost generates an RXFLVL interrupt.\nf) \nIn response to the RXFLVL interrupt, read the received packet status to determine \nthe number of bytes received, then read the receive FIFO accordingly. The \napplication must mask the RXFLVL interrupt before reading the receive FIFO, and \nunmask it after reading the entire packet.\ng) \nThe core generates an RXFLVL interrupt for the transfer completion status entry in \nthe receive FIFO. This time, the application must read and ignore the receive \npacket status when the receive packet status is not an IN data packet (PKTSTS bit \nin OTG_HS_GRXSTSR ≠0b0010).\nh) \nThe core generates an XFRC interrupt as soon as the receive packet status is \nread.\ni) \nIn response to the XFRC interrupt, read the PKTCNT field in OTG_HS_HCTSIZ2. \nIf PKTCNT ≠0 in OTG_HS_HCTSIZ2, disable the channel before re-initializing \nthe channel for the next transfer, if any. If PKTCNT = 0 in OTG_HS_HCTSIZ2, \nreinitialize the channel for the next transfer. This time, the application must reset \nthe ODDFRM bit in OTG_HS_HCCHAR2.\n•\nSelecting the queue depth\nChoose the periodic and nonperiodic request queue depths carefully to match the \nnumber of periodic/nonperiodic endpoints accessed.\nThe nonperiodic request queue depth affects the performance of nonperiodic transfers. \nThe deeper the queue (along with sufficient FIFO size), the more often the core is able \nto pipeline nonperiodic transfers. If the queue size is small, the core is able to put in \nnew requests only when the queue space is freed up.\nThe core’s periodic request queue depth is critical to perform periodic transfers as \nscheduled. Select the periodic queue depth, based on the number of periodic transfers \nscheduled in a micro-frame. In Slave mode, however, the application must also take \ninto account the disable entry that must be put into the queue. So, if there are two \nnonhigh-bandwidth periodic endpoints, the periodic request queue depth must be at \nleast 4. If at least one high-bandwidth endpoint is supported, the queue depth must be \n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1514/1757\nRM0090 Rev 21\n8. If the periodic request queue depth is smaller than the periodic transfers scheduled \nin a micro-frame, a frame overrun condition occurs.\n•\nHandling babble conditions\nOTG_HS controller handles two cases of babble: packet babble and port babble. \nPacket babble occurs if the device sends more data than the maximum packet size for \nthe channel. Port babble occurs if the core continues to receive data from the device at \nEOF2 (the end of frame 2, which is very close to SOF).\nWhen OTG_HS controller detects a packet babble, it stops writing data into the Rx \nbuffer and waits for the end of packet (EOP). When it detects an EOP, it flushes already \nwritten data in the Rx buffer and generates a Babble interrupt to the application.\nWhen OTG_HS controller detects a port babble, it flushes the RxFIFO and disables the \nport. The core then generates a Port disabled interrupt (HPRTINT in \nOTG_HS_GINTSTS, PENCHNG in OTG_HS_HPRT). On receiving this interrupt, the \napplication must determine that this is not due to an overcurrent condition (another \ncause of the Port Disabled interrupt) by checking POCA in OTG_HS_HPRT, then \nperform a soft reset. The core does not send any more tokens after it has detected a \nport babble condition.\n•\nBulk and control OUT/SETUP transactions in DMA mode\nThe sequence of operations is as follows:\na) \nInitialize and enable channel 1 as explained in Section : Channel initialization.\nb) \nThe HS_OTG host starts fetching the first packet as soon as the channel is \nenabled. For internal DMA mode, the OTG_HS host uses the programmed DMA \naddress to fetch the packet.\nc) \nAfter fetching the last word of the second (last) packet, the OTG_HS host masks \nchannel 1 internally for further arbitration.\nd) \nThe HS_OTG host generates a CHH interrupt as soon as the last packet is sent.\ne) \nIn response to the CHH interrupt, de-allocate the channel for other transfers.\n•\nNAK and NYET handling with internal DMA\na) \nThe OTG_HS host sends a bulk OUT transaction.\nb) \nThe device responds with NAK or NYET.\nc) \nIf the application has unmasked NAK or NYET, the core generates the \ncorresponding interrupt(s) to the application. The application is not required to \nservice these interrupts, since the core takes care of rewinding the buffer pointers \nand re-initializing the Channel without application intervention.\nd) \nThe core automatically issues a ping token.\ne) \nWhen the device returns an ACK, the core continues with the transfer. Optionally, \nthe application can utilize these interrupts, in which case the NAK or NYET \ninterrupt is masked by the application.\nThe core does not generate a separate interrupt when NAK or NYET is received by the \nhost functionality.\n•\nBulk and control IN transactions in DMA mode\nThe sequence of operations is as follows:\na) \nInitialize and enable the used channel (channel x) as explained in Section : \nChannel initialization.\nb) \nThe OTG_HS host writes an IN request to the request queue as soon as the \nchannel receives the grant from the arbiter (arbitration is performed in a round-\nrobin fashion).\n\n\n<>\n\nRM0090 Rev 21\n1515/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nc) \nThe OTG_HS host starts writing the received data to the system memory as soon \nas the last byte is received with no errors.\nd) \nWhen the last packet is received, the OTG_HS host sets an internal flag to remove \nany extra IN requests from the request queue.\ne) \nThe OTG_HS host flushes the extra requests.\nf) \nThe final request to disable channel x is written to the request queue. At this point, \nchannel 2 is internally masked for further arbitration.\ng) \nThe OTG_HS host generates the CHH interrupt as soon as the disable request \ncomes to the top of the queue.\nh) \nIn response to the CHH interrupt, de-allocate the channel for other transfers.\n•\nInterrupt OUT transactions in DMA mode\na) \nInitialize and enable channel x as explained in Section : Channel initialization.\nb) \nThe OTG_HS host starts fetching the first packet as soon the channel is enabled \nand writes the OUT request along with the last word fetch. In high-bandwidth \ntransfers, the HS_OTG host continues fetching the next packet (up to the value \nspecified in the MC field) before switching to the next channel.\nc) \nThe OTG_HS host attempts to send the OUT token at the beginning of the next \nodd frame/micro-frame.\nd) \nAfter successfully transmitting the packet, the OTG_HS host generates a CHH \ninterrupt.\ne) \nIn response to the CHH interrupt, reinitialize the channel for the next transfer.\n•\nInterrupt IN transactions in DMA mode\nThe sequence of operations (channelx) is as follows:\na) \nInitialize and enable channel x as explained in Section : Channel initialization.\nb) \nThe OTG_HS host writes an IN request to the request queue as soon as the \nchannel x gets the grant from the arbiter (round-robin with fairness). In high-\nbandwidth transfers, the OTG_HS host writes consecutive writes up to MC times.\nc) \nThe OTG_HS host attempts to send an IN token at the beginning of the next (odd) \nframe/micro-frame.\nd) \nAs soon the packet is received and written to the receive FIFO, the OTG_HS host \ngenerates a CHH interrupt.\ne) \nIn response to the CHH interrupt, reinitialize the channel for the next transfer.\n•\nIsochronous OUT transactions in DMA mode\na) \nInitialize and enable channel x as explained in Section : Channel initialization.\nb) \nThe OTG_HS host starts fetching the first packet as soon as the channel is \nenabled, and writes the OUT request along with the last word fetch. In high-\nbandwidth transfers, the OTG_HS host continues fetching the next packet (up to \nthe value specified in the MC field) before switching to the next channel.\nc) \nThe OTG_HS host attempts to send an OUT token at the beginning of the next \n(odd) frame/micro-frame.\nd) \nAfter successfully transmitting the packet, the HS_OTG host generates a CHH \ninterrupt.\ne) \nIn response to the CHH interrupt, reinitialize the channel for the next transfer.\n•\nIsochronous IN transactions in DMA mode\nThe sequence of operations ((channel x) is as follows:\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1516/1757\nRM0090 Rev 21\na) \nInitialize and enable channel x as explained in Section : Channel initialization.\nb) \nThe OTG_HS host writes an IN request to the request queue as soon as the \nchannel x gets the grant from the arbiter (round-robin with fairness). In high-\nbandwidth transfers, the OTG_HS host performs consecutive write operations up \nto MC times.\nc) \nThe OTG_HS host attempts to send an IN token at the beginning of the next (odd) \nframe/micro-frame.\nd) \nAs soon the packet is received and written to the receive FIFO, the OTG_HS host \ngenerates a CHH interrupt.\ne) \nIn response to the CHH interrupt, reinitialize the channel for the next transfer.\n•\nBulk and control OUT/SETUP split transactions in DMA mode\nThe sequence of operations in (channel x) is as follows:\na) \nInitialize and enable channel x for start split as explained in Section : Channel \ninitialization. \nb) \nThe OTG_HS host starts fetching the first packet as soon the channel is enabled \nand writes the OUT request along with the last word fetch.\nc) \nAfter successfully transmitting start split, the OTG_HS host generates the CHH \ninterrupt.\nd) \nIn response to the CHH interrupt, set the COMPLSPLT bit in HCSPLT1 to send the \ncomplete split.\ne) \nAfter successfully transmitting complete split, the OTG_HS host generates the \nCHH interrupt.\nf) \nIn response to the CHH interrupt, de-allocate the channel.\n•\nBulk/Control IN split transactions in DMA mode\nThe sequence of operations (channel x) is as follows:\na) \nInitialize and enable channel x as explained in Section : Channel initialization.\nb) \nThe OTG_HS host writes the start split request to the nonperiodic request after \ngetting the grant from the arbiter. The OTG_HS host masks the channel x \ninternally for the arbitration after writing the request.\nc) \nAs soon as the IN token is transmitted, the OTG_HS host generates the CHH \ninterrupt.\nd) \nIn response to the CHH interrupt, set the COMPLSPLT bit in HCSPLT2 and re-\nenable the channel to send the complete split token. This unmasks channel x for \narbitration.\ne) \nThe OTG_HS host writes the complete split request to the nonperiodic request \nafter receiving the grant from the arbiter.\nf) \nThe OTG_HS host starts writing the packet to the system memory after receiving \nthe packet successfully.\ng) \nAs soon as the received packet is written to the system memory, the OTG_HS \nhost generates a CHH interrupt.\nh) \nIn response to the CHH interrupt, de-allocate the channel.\n•\nInterrupt OUT split transactions in DMA mode\nThe sequence of operations in (channel x) is as follows:\na) \nInitialize and enable channel 1 for start split as explained in Section : Channel \ninitialization. The application must set the ODDFRM bit in HCCHAR1.\nb) \nThe HS_OTG host starts reading the packet.\n\n\n<>\n\nRM0090 Rev 21\n1517/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nc) \nThe HS_OTG host attempts to send the start split transaction.\nd) \nAfter successfully transmitting the start split, the OTG_HS host generates the \nCHH interrupt.\ne) \nIn response to the CHH interrupt, set the COMPLSPLT bit in HCSPLT1 to send the \ncomplete split.\nf) \nAfter successfully completing the complete split transaction, the OTG_HS host \ngenerates the CHH interrupt.\ng) \nIn response to CHH interrupt, de-allocate the channel.\n•\nInterrupt IN split transactions in DMA mode\nThe sequence of operations in (channel x) is as follows:\na) \nInitialize and enable channel x for start split as explained in Section : Channel \ninitialization.\nb) \nThe OTG_HS host writes an IN request to the request queue as soon as channel \nx receives the grant from the arbiter.\nc) \nThe OTG_HS host attempts to send the start split IN token at the beginning of the \nnext odd micro-frame.\nd) \nThe OTG_HS host generates the CHH interrupt after successfully transmitting the \nstart split IN token.\ne) \nIn response to the CHH interrupt, set the COMPLSPLT bit in HCSPLT2 to send the \ncomplete split.\nf) \nAs soon as the packet is received successfully, the OTG_HS host starts writing the \ndata to the system memory.\ng) \nThe OTG_HS host generates the CHH interrupt after transferring the received \ndata to the system memory.\nh) \nIn response to the CHH interrupt, de-allocate or reinitialize the channel for the next \nstart split.\n•\nIsochronous OUT split transactions in DMA mode\nThe sequence of operations (channel x) is as follows:\na) \nInitialize and enable channel x for start split (begin) as explained in Section : \nChannel initialization. The application must set the ODDFRM bit in HCCHAR1. \nProgram the MPS field.\nb) \nThe HS_OTG host starts reading the packet.\nc) \nAfter successfully transmitting the start split (begin), the HS_OTG host generates \nthe CHH interrupt.\nd) \nIn response to the CHH interrupt, reinitialize the registers to send the start split \n(end). \ne) \nAfter successfully transmitting the start split (end), the OTG_HS host generates a \nCHH interrupt.\nf) \nIn response to the CHH interrupt, de-allocate the channel.\n•\nIsochronous IN split transactions in DMA mode\nThe sequence of operations (channel x) is as follows:\na) \nInitialize and enable channel x for start split as explained in Section : Channel \ninitialization.\nb) \nThe OTG_HS host writes an IN request to the request queue as soon as channel \nx receives the grant from the arbiter.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1518/1757\nRM0090 Rev 21\nc) \nThe OTG_HS host attempts to send the start split IN token at the beginning of the \nnext odd micro-frame.\nd) \nThe OTG_HS host generates the CHH interrupt after successfully transmitting the \nstart split IN token.\ne) \nIn response to the CHH interrupt, set the COMPLSPLT bit in HCSPLT2 to send the \ncomplete split.\nf) \nAs soon as the packet is received successfully, the OTG_HS host starts writing the \ndata to the system memory.\ng) \nThe OTG_HS host generates the CHH interrupt after transferring the received \ndata to the system memory. In response to the CHH interrupt, de-allocate the \nchannel or reinitialize the channel for the next start split.\n35.13.6 \nDevice programming model\nEndpoint initialization on USB reset\n1.\nSet the NAK bit for all OUT endpoints\n–\nSNAK = 1 in OTG_HS_DOEPCTLx (for all OUT endpoints)\n2. \nUnmask the following interrupt bits\n–\nINEP0 = 1 in OTG_HS_DAINTMSK (control 0 IN endpoint)\n–\nOUTEP0 = 1 in OTG_HS_DAINTMSK (control 0 OUT endpoint)\n–\nSTUP = 1 in DOEPMSK\n–\nXFRC = 1 in DOEPMSK\n–\nXFRC = 1 in DIEPMSK\n–\nTOC = 1 in DIEPMSK\n3. \nSet up the Data FIFO RAM for each of the FIFOs\n–\nProgram the OTG_HS_GRXFSIZ register, to be able to receive control OUT data \nand setup data. If thresholding is not enabled, at a minimum, this must be equal to \n1 max packet size of control endpoint 0 + 2 words (for the status of the control \nOUT data packet) + 10 words (for setup packets).\n–\nProgram the OTG_HS_TX0FSIZ register (depending on the FIFO number \nchosen) to be able to transmit control IN data. At a minimum, this must be equal to \n1 max packet size of control endpoint 0.\n4. \nProgram the following fields in the endpoint-specific registers for control OUT endpoint \n0 to receive a SETUP packet\n–\nSTUPCNT = 3 in OTG_HS_DOEPTSIZ0 (to receive up to 3 back-to-back SETUP \npackets)\n5. \nIn DMA mode, the DOEPDMA0 register should have a valid memory address to store \nany SETUP packets received.\nAt this point, all initialization required to receive SETUP packets is done.\n\n\n<>\n\nRM0090 Rev 21\n1519/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nEndpoint initialization on enumeration completion\n1.\nOn the Enumeration Done interrupt (ENUMDNE in OTG_HS_GINTSTS), read the \nOTG_HS_DSTS register to determine the enumeration speed.\n2. \nProgram the MPSIZ field in OTG_HS_DIEPCTL0 to set the maximum packet size. This \nstep configures control endpoint 0. The maximum packet size for a control endpoint \ndepends on the enumeration speed.\n3. \nIn DMA mode, program the DOEPCTL0 register to enable control OUT endpoint 0, to \nreceive a SETUP packet.\n–\nEPENA bit in DOEPCTL0 = 1\nAt this point, the device is ready to receive SOF packets and is configured to perform control \ntransfers on control endpoint 0.\nEndpoint initialization on SetAddress command\nThis section describes what the application must do when it receives a SetAddress \ncommand in a SETUP packet.\n1.\nProgram the OTG_HS_DCFG register with the device address received in the \nSetAddress command\n1.\nProgram the core to send out a status IN packet\nEndpoint initialization on SetConfiguration/SetInterface command\nThis section describes what the application must do when it receives a SetConfiguration or \nSetInterface command in a SETUP packet.\n1.\nWhen a SetConfiguration command is received, the application must program the \nendpoint registers to configure them with the characteristics of the valid endpoints in \nthe new configuration.\n2. \nWhen a SetInterface command is received, the application must program the endpoint \nregisters of the endpoints affected by this command.\n3. \nSome endpoints that were active in the prior configuration or alternate setting are not \nvalid in the new configuration or alternate setting. These invalid endpoints must be \ndeactivated.\n4. \nUnmask the interrupt for each active endpoint and mask the interrupts for all inactive \nendpoints in the OTG_HS_DAINTMSK register.\n5. \nSet up the Data FIFO RAM for each FIFO.\n6. \nAfter all required endpoints are configured; the application must program the core to \nsend a status IN packet.\nAt this point, the device core is configured to receive and transmit any type of data packet.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1520/1757\nRM0090 Rev 21\nEndpoint activation\nThis section describes the steps required to activate a device endpoint or to configure an \nexisting device endpoint to a new type.\n1.\nProgram the characteristics of the required endpoint into the following fields of the \nOTG_HS_DIEPCTLx register (for IN or bidirectional endpoints) or the \nOTG_HS_DOEPCTLx register (for OUT or bidirectional endpoints).\n–\nMaximum packet size\n–\nUSB active endpoint = 1\n–\nEndpoint start data toggle (for interrupt and bulk endpoints)\n–\nEndpoint type\n–\nTxFIFO number\n2. \nOnce the endpoint is activated, the core starts decoding the tokens addressed to that \nendpoint and sends out a valid handshake for each valid token received for the \nendpoint.\nEndpoint deactivation\nThis section describes the steps required to deactivate an existing endpoint.\n1.\nIn the endpoint to be deactivated, clear the USB active endpoint bit in the \nOTG_HS_DIEPCTLx register (for IN or bidirectional endpoints) or the \nOTG_HS_DOEPCTLx register (for OUT or bidirectional endpoints).\n2. \nOnce the endpoint is deactivated, the core ignores tokens addressed to that endpoint, \nwhich results in a timeout on the USB.\nNote:\nThe application must meet the following conditions to set up the device core to handle \ntraffic:\nNPTXFEM and RXFLVLM in GINTMSK must be cleared.\n35.13.7 \nOperational model\nSETUP and OUT data transfers\nThis section describes the internal data flow and application-level operations during data \nOUT transfers and SETUP transactions.\n•\nPacket read\nThis section describes how to read packets (OUT data and SETUP packets) from the \nreceive FIFO in Slave mode.\n1.\nOn catching an RXFLVL interrupt (OTG_HS_GINTSTS register), the application must \nread the Receive status pop register (OTG_HS_GRXSTSP).\n2. \nThe application can mask the RXFLVL interrupt (in OTG_HS_GINTSTS) by writing to \nRXFLVL = 0 (in GINTMSK), until it has read the packet from the receive FIFO.\n3. \nIf the received packet’s byte count is not 0, the byte count amount of data is popped \nfrom the receive Data FIFO and stored in memory. If the received packet byte count is \n0, no data is popped from the receive data FIFO.\n\n\n<>\n\nRM0090 Rev 21\n1521/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n4. \nThe receive FIFO packet status readout indicates one of the following:\na) \nGlobal OUT NAK pattern:\nPKTSTS = Global OUT NAK, BCNT = 0x000, EPNUM = Don’t Care (0x0), \nDPID = Don’t Care (0b00).\nThese data indicate that the global OUT NAK bit has taken effect.\nb) \nSETUP packet pattern:\nPKTSTS = SETUP, BCNT = 0x008, EPNUM = Control EP Num, DPID = D0. \nThese data indicate that a SETUP packet for the specified endpoint is now \navailable for reading from the receive FIFO.\nc) \nSetup stage done pattern:\nPKTSTS = Setup Stage Done, BCNT = 0x0, EPNUM = Control EP Num, \nDPID = Don’t Care (0b00).\nThese data indicate that the Setup stage for the specified endpoint has completed \nand the Data stage has started. After this entry is popped from the receive FIFO, \nthe core asserts a Setup interrupt on the specified control OUT endpoint.\nd) \nData OUT packet pattern:\nPKTSTS = DataOUT, BCNT = size of the received data OUT packet \n(0 ≤BCNT ≤1 024), EPNUM = EPNUM on which the packet was received, \nDPID = Actual Data PID.\ne) \nData transfer completed pattern:\nPKTSTS = Data OUT Transfer Done, BCNT = 0x0, EPNUM = OUT EP Num \non which the data transfer is complete, DPID = Don’t Care (0b00).\nThese data indicate that an OUT data transfer for the specified OUT endpoint has \ncompleted. After this entry is popped from the receive FIFO, the core asserts a \nTransfer Completed interrupt on the specified OUT endpoint.\n5. \nAfter the data payload is popped from the receive FIFO, the RXFLVL interrupt \n(OTG_HS_GINTSTS) must be unmasked.\n6. \nSteps 1–5 are repeated every time the application detects assertion of the interrupt line \ndue to RXFLVL in OTG_HS_GINTSTS. Reading an empty receive FIFO can result in \nundefined core behavior.\nFigure 426 provides a flowchart of the above procedure.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1522/1757\nRM0090 Rev 21\nFigure 426. Receive FIFO packet read in slave mode\n•\nSETUP transactions\nThis section describes how the core handles SETUP packets and the application’s \nsequence for handling SETUP transactions.\n•\nApplication requirements\n1.\nTo receive a SETUP packet, the STUPCNT field (OTG_HS_DOEPTSIZx) in a control \nOUT endpoint must be programmed to a nonzero value. When the application \nprograms the STUPCNT field to a nonzero value, the core receives SETUP packets \nand writes them to the receive FIFO, irrespective of the NAK status and EPENA bit \nsetting in OTG_HS_DOEPCTLx. The STUPCNT field is decremented every time the \ncontrol endpoint receives a SETUP packet. If the STUPCNT field is not programmed to \na proper value before receiving a SETUP packet, the core still receives the SETUP \npacket and decrements the STUPCNT field, but the application may not be able to \ndetermine the correct number of SETUP packets received in the Setup stage of a \ncontrol transfer.\n–\nSTUPCNT = 3 in OTG_HS_DOEPTSIZx\n2. \nThe application must always allocate some extra space in the Receive data FIFO, to be \nable to receive up to three SETUP packets on a control endpoint.\n–\nThe space to be reserved is 10 words. Three words are required for the first \nSETUP packet, 1 word is required for the Setup stage done word and 6 words are \nrequired to store two extra SETUP packets among all control endpoints.\n–\n3 words per SETUP packet are required to store 8 bytes of SETUP data and 4 \nbytes of SETUP status (Setup packet pattern). The core reserves this space in the \nreceive data.\n–\nFIFO to write SETUP data only, and never uses this space for data packets.\nMSv65221V1\nrd_data = rd_reg(OTG_HS_GRXSTSP);\nmem[0:dword_cnt-1] = \nrd_rxfifo(rd_data.EPNUM,\ndword_cnt)\nrd_data.BCNT = 0\nWait until RXFLVL in OTG_HS_GINTSTSG\ndword_cnt =\nBCNT[11:2] +\n(BCNT[1]| BCNT[1])\nrcv_out_pkt()\nPacket \nstore in \nmemory\nN\nY\n\n\n<>\n\nRM0090 Rev 21\n1523/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n3. \nThe application must read the 2 words of the SETUP packet from the receive FIFO. \n4. \nThe application must read and discard the Setup stage done word from the receive \nFIFO.\n•\nInternal data flow\n5. \nWhen a SETUP packet is received, the core writes the received data to the receive \nFIFO, without checking for available space in the receive FIFO and irrespective of the \nendpoint’s NAK and STALL bit settings.\n–\nThe core internally sets the IN NAK and OUT NAK bits for the control IN/OUT \nendpoints on which the SETUP packet was received.\n6. \nFor every SETUP packet received on the USB, 3 words of data are written to the \nreceive FIFO, and the STUPCNT field is decremented by 1.\n–\nThe first word contains control information used internally by the core\n–\nThe second word contains the first 4 bytes of the SETUP command\n–\nThe third word contains the last 4 bytes of the SETUP command\n7. \nWhen the Setup stage changes to a Data IN/OUT stage, the core writes an entry \n(Setup stage done word) to the receive FIFO, indicating the completion of the Setup \nstage.\n8. \nOn the AHB side, SETUP packets are emptied by the application.\n9. \nWhen the application pops the Setup stage done word from the receive FIFO, the core \ninterrupts the application with an STUP interrupt (OTG_HS_DOEPINTx), indicating it \ncan process the received SETUP packet.\n–\nThe core clears the endpoint enable bit for control OUT endpoints.\n•\nApplication programming sequence\n1.\nProgram the OTG_HS_DOEPTSIZx register.\n–\nSTUPCNT = 3\n2. \nWait for the RXFLVL interrupt (OTG_HS_GINTSTS) and empty the data packets from \nthe receive FIFO.\n3. \nAssertion of the STUP interrupt (OTG_HS_DOEPINTx) marks a successful completion \nof the SETUP Data Transfer.\n–\nOn this interrupt, the application must read the OTG_HS_DOEPTSIZx register to \ndetermine the number of SETUP packets received and process the last received \nSETUP packet.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1524/1757\nRM0090 Rev 21\nFigure 427. Processing a SETUP packet\n•\nHandling more than three back-to-back SETUP packets\nPer the USB 2.0 specification, normally, during a SETUP packet error, a host does not send \nmore than three back-to-back SETUP packets to the same endpoint. However, the USB 2.0 \nspecification does not limit the number of back-to-back SETUP packets a host can send to \nthe same endpoint. When this condition occurs, the OTG_HS controller generates an \ninterrupt (B2BSTUP in OTG_HS_DOEPINTx).\n•\nSetting the global OUT NAK\nInternal data flow:\n1.\nWhen the application sets the Global OUT NAK (SGONAK bit in OTG_HS_DCTL), the \ncore stops writing data, except SETUP packets, to the receive FIFO. Irrespective of the \nspace availability in the receive FIFO, nonisochronous OUT tokens receive a NAK \nhandshake response, and the core ignores isochronous OUT data packets\n2. \nThe core writes the Global OUT NAK pattern to the receive FIFO. The application must \nreserve enough receive FIFO space to write this data pattern.\n3. \nWhen the application pops the Global OUT NAK pattern word from the receive FIFO, \nthe core sets the GONAKEFF interrupt (OTG_HS_GINTSTS).\n4. \nOnce the application detects this interrupt, it can assume that the core is in Global OUT \nNAK mode. The application can clear this interrupt by clearing the SGONAK bit in \nOTG_HS_DCTL.\nMSv65222V1\nWait for STUP in OTG_HS_DOEPINTx\nrem_supcnt =\nrd_reg(DOEPTSIZx))\nsetup_cmd[31:0] = mem[4 – 2 * rem_supcnt]\nsetup_cmd[63:32] = mem[5 – 2* rem_supcnt]\nctrl-rd/wr/2 stage\nFind setup cmd type\nSetup_np_in_pkt\nStatus IN phase\nrcv_out_pkt\nData OUT phase\nSetup_np_in_pkt\nData IN phase\nWrite\nRead\n2-stage\n\n\n<>\n\nRM0090 Rev 21\n1525/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nApplication programming sequence:\n1.\nTo stop receiving any kind of data in the receive FIFO, the application must set the \nGlobal OUT NAK bit by programming the following field:\n–\nSGONAK = 1 in OTG_HS_DCTL\n2. \nWait for the assertion of the GONAKEFF interrupt in OTG_HS_GINTSTS. When \nasserted, this interrupt indicates that the core has stopped receiving any type of data \nexcept SETUP packets.\n3. \nThe application can receive valid OUT packets after it has set SGONAK in \nOTG_HS_DCTL and before the core asserts the GONAKEFF interrupt \n(OTG_HS_GINTSTS).\n4. \nThe application can temporarily mask this interrupt by writing to the GINAKEFFM bit in \nGINTMSK.\n–\nGINAKEFFM = 0 in GINTMSK\n5. \nWhenever the application is ready to exit the Global OUT NAK mode, it must clear the \nSGONAK bit in OTG_HS_DCTL. This also clears the GONAKEFF interrupt \n(OTG_HS_GINTSTS).\n–\nOTG_HS_DCTL = 1 in CGONAK\n6. \nIf the application has masked this interrupt earlier, it must be unmasked as follows:\n–\nGINAKEFFM = 1 in GINTMSK\n•\nDisabling an OUT endpoint\nThe application must use this sequence to disable an OUT endpoint that it has enabled.\nApplication programming sequence:\n1.\nBefore disabling any OUT endpoint, the application must enable Global OUT NAK \nmode in the core.\n–\nSGONAK = 1 in OTG_HS_DCTL\n2. \nWait for the GONAKEFF interrupt (OTG_HS_GINTSTS)\n3. \nDisable the required OUT endpoint by programming the following fields:\n–\nEPDIS = 1 in OTG_HS_DOEPCTLx\n–\nSNAK = 1 in OTG_HS_DOEPCTLx\n4. \nWait for the EPDISD interrupt (OTG_HS_DOEPINTx), which indicates that the OUT \nendpoint is completely disabled. When the EPDISD interrupt is asserted, the core also \nclears the following bits:\n–\nEPDIS = 0 in OTG_HS_DOEPCTLx\n–\nEPENA = 0 in OTG_HS_DOEPCTLx\n5. \nThe application must clear the Global OUT NAK bit to start receiving data from other \nnondisabled OUT endpoints.\n–\nSGONAK = 0 in OTG_HS_DCTL\n•\nTransfer Stop Programming for OUT endpoints\nThe application must use the following programing sequence to stop any transfers (because \nof an interrupt from the host, typically a reset).\nSequence of operations:\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1526/1757\nRM0090 Rev 21\n1.\nEnable all OUT endpoints by setting\n–\nEPENA = 1 in all OTG_HS_DOEPCTLx registers.\n2. \nFlush the RxFIFO as follows\n–\nPoll OTG_HS_GRSTCTL.AHBIDL until it is 1. This indicates that AHB master is \nidle.\n–\nPerform read modify write operation on OTG_HS_GRSTCTL.RXFFLSH =1\n–\nPoll OTG_HS_GRSTCTL.RXFFLSH until it is 0, but also using a timeout of less \nthan 10 milli-seconds (corresponds to minimum reset signaling duration). If 0 is \nseen before the timeout, then the RxFIFO flush is successful. If at the moment the \ntimeout occurs, there is still a 1, (this may be due to a packet on EP0 coming from \nthe host) then go back (once only) to the previous step (“Perform read modify write \noperation”).\n3. \nBefore disabling any OUT endpoint, the application must enable Global OUT NAK \nmode in the core, according to the instructions in “Setting the global OUT NAK on \npage 1524”. This ensures that data in the RxFIFO is sent to the application \nsuccessfully. Set SGONAK = 1 in OTG_HS_DCTL\n4. \nWait for the GONAKEFF interrupt (OTG_HS_GINTSTS)\n5. \nDisable all active OUT endpoints by programming the following register bits:\n–\nEPDIS = 1 in registers OTG_HS_DOEPCTLx\n–\nSNAK = 1 in registers OTG_HS_DOEPCTLx\n6. \nWait for the EPDIS interrupt in OTG_HS_DOEPINTx for each OUT endpoint \nprogrammed in the previous step. The EPDIS interrupt in OTG_HS_DOEPINTx \nindicates that the corresponding OUT endpoint is completely disabled. When the \nEPDIS interrupt is asserted, the following bits are cleared:\n–\nEPENA = 0 in registers OTG_HS_DOEPCTLx\n–\nEPDIS = 0 in registers OTG_HS_DOEPCTLx\n–\nSNAK = 0 in registers OTG_HS_DOEPCTLx\n•\nGeneric non-isochronous OUT data transfers\nThis section describes a regular nonisochronous OUT data transfer (control, bulk, or \ninterrupt).\nApplication requirements:\n1.\nBefore setting up an OUT transfer, the application must allocate a buffer in the memory \nto accommodate all data to be received as part of the OUT transfer.\n2. \nFor OUT transfers, the transfer size field in the endpoint’s transfer size register must be \na multiple of the maximum packet size of the endpoint, adjusted to the word boundary.\n–\ntransfer size[EPNUM] = n × (MPSIZ[EPNUM] + 4 – (MPSIZ[EPNUM] mod 4))\n–\npacket count[EPNUM] = n\n–\nn > 0\n3. \nOn any OUT endpoint interrupt, the application must read the endpoint’s transfer size \nregister to calculate the size of the payload in the memory. The received payload size \ncan be less than the programmed transfer size.\n–\nPayload size in memory = application programmed initial transfer size – core \nupdated final transfer size\n–\nNumber of USB packets in which this payload was received = application \nprogrammed initial packet count – core updated final packet count\n\n\n<>\n\nRM0090 Rev 21\n1527/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nInternal data flow:\n1.\nThe application must set the transfer size and packet count fields in the endpoint-\nspecific registers, clear the NAK bit, and enable the endpoint to receive the data.\n2. \nOnce the NAK bit is cleared, the core starts receiving data and writes it to the receive \nFIFO, as long as there is space in the receive FIFO. For every data packet received on \nthe USB, the data packet and its status are written to the receive FIFO. Every packet \n(maximum packet size or short packet) written to the receive FIFO decrements the \npacket count field for that endpoint by 1.\n–\nOUT data packets received with bad data CRC are flushed from the receive FIFO \nautomatically.\n–\nAfter sending an ACK for the packet on the USB, the core discards \nnonisochronous OUT data packets that the host, which cannot detect the ACK, re-\nsends. The application does not detect multiple back-to-back data OUT packets \non the same endpoint with the same data PID. In this case the packet count is not \ndecremented.\n–\nIf there is no space in the receive FIFO, isochronous or nonisochronous data \npackets are ignored and not written to the receive FIFO. Additionally, \nnonisochronous OUT tokens receive a NAK handshake reply.\n–\nIn all the above three cases, the packet count is not decremented because no data \nare written to the receive FIFO.\n3. \nWhen the packet count becomes 0 or when a short packet is received on the endpoint, \nthe NAK bit for that endpoint is set. Once the NAK bit is set, the isochronous or \nnonisochronous data packets are ignored and not written to the receive FIFO, and \nnonisochronous OUT tokens receive a NAK handshake reply.\n4. \nAfter the data are written to the receive FIFO, the application reads the data from the \nreceive FIFO and writes it to external memory, one packet at a time per endpoint.\n5. \nAt the end of every packet write on the AHB to external memory, the transfer size for \nthe endpoint is decremented by the size of the written packet.\n6. \nThe OUT data transfer completed pattern for an OUT endpoint is written to the receive \nFIFO on one of the following conditions:\n–\nThe transfer size is 0 and the packet count is 0\n–\nThe last OUT data packet written to the receive FIFO is a short packet\n(0 ≤packet size < maximum packet size)\n7. \nWhen either the application pops this entry (OUT data transfer completed), a transfer \ncompleted interrupt is generated for the endpoint and the endpoint enable is cleared.\nApplication programming sequence:\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1528/1757\nRM0090 Rev 21\n1.\nProgram the OTG_HS_DOEPTSIZx register for the transfer size and the \ncorresponding packet count.\n2. \nProgram the OTG_HS_DOEPCTLx register with the endpoint characteristics, and set \nthe EPENA and CNAK bits.\n–\nEPENA = 1 in OTG_HS_DOEPCTLx\n–\nCNAK = 1 in OTG_HS_DOEPCTLx\n3. \nWait for the RXFLVL interrupt (in OTG_HS_GINTSTS) and empty the data packets \nfrom the receive FIFO.\n–\nThis step can be repeated many times, depending on the transfer size.\n4. \nAsserting the XFRC interrupt (OTG_HS_DOEPINTx) marks a successful completion of \nthe nonisochronous OUT data transfer.\n5. \nRead the OTG_HS_DOEPTSIZx register to determine the size of the received data \npayload.\n•\nGeneric isochronous OUT data transfer\nThis section describes a regular isochronous OUT data transfer.\nApplication requirements:\n1.\nAll the application requirements for nonisochronous OUT data transfers also apply to \nisochronous OUT data transfers.\n2. \nFor isochronous OUT data transfers, the transfer size and packet count fields must \nalways be set to the number of maximum-packet-size packets that can be received in a \nsingle frame and no more. Isochronous OUT data transfers cannot span more than 1 \nframe.\n3. \nThe application must read all isochronous OUT data packets from the receive FIFO \n(data and status) before the end of the periodic frame (EOPF interrupt in \nOTG_HS_GINTSTS).\n4. \nTo receive data in the following frame, an isochronous OUT endpoint must be enabled \nafter the EOPF (OTG_HS_GINTSTS) and before the SOF (OTG_HS_GINTSTS).\nInternal data flow:\n1.\nThe internal data flow for isochronous OUT endpoints is the same as that for \nnonisochronous OUT endpoints, but for a few differences.\n2. \nWhen an isochronous OUT endpoint is enabled by setting the Endpoint Enable and \nclearing the NAK bits, the Even/Odd frame bit must also be set appropriately. The core \nreceives data on an isochronous OUT endpoint in a particular frame only if the \nfollowing condition is met:\n–\nEONUM (in OTG_HS_DOEPCTLx) = SOFFN[0] (in OTG_HS_DSTS)\n3. \nWhen the application completely reads an isochronous OUT data packet (data and \nstatus) from the receive FIFO, the core updates the RXDPID field in \nOTG_HS_DOEPTSIZx with the data PID of the last isochronous OUT data packet read \nfrom the receive FIFO.\nApplication programming sequence:\n\n\n<>\n\nRM0090 Rev 21\n1529/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n1.\nProgram the OTG_HS_DOEPTSIZx register for the transfer size and the \ncorresponding packet count\n2. \nProgram the OTG_HS_DOEPCTLx register with the endpoint characteristics and set \nthe Endpoint Enable, ClearNAK, and Even/Odd frame bits.\n–\nEPENA = 1\n–\nCNAK = 1\n–\nEONUM = (0: Even/1: Odd)\n3. \nIn Slave mode, wait for the RXFLVL interrupt (in OTG_HS_GINTSTS) and empty the \ndata packets from the receive FIFO\n–\nThis step can be repeated many times, depending on the transfer size.\n4. \nThe assertion of the XFRC interrupt (in OTG_HS_DOEPINTx) marks the completion of \nthe isochronous OUT data transfer. This interrupt does not necessarily mean that the \ndata in memory are good.\n5. \nThis interrupt cannot always be detected for isochronous OUT transfers. Instead, the \napplication can detect the IISOOXFRM interrupt in OTG_HS_GINTSTS.\n6. \nRead the OTG_HS_DOEPTSIZx register to determine the size of the received transfer \nand to determine the validity of the data received in the frame. The application must \ntreat the data received in memory as valid only if one of the following conditions is met:\n–\nRXDPID = D0 (in OTG_HS_DOEPTSIZx) and the number of USB packets in \nwhich this payload was received = 1\n–\nRXDPID = D1 (in OTG_HS_DOEPTSIZx) and the number of USB packets in \nwhich this payload was received = 2\n–\nRXDPID = D2 (in OTG_HS_DOEPTSIZx) and the number of USB packets in \nwhich this payload was received = 3\nThe number of USB packets in which this payload was received =\nApplication programmed initial packet count – Core updated final packet count\nThe application can discard invalid data packets.\n•\nIncomplete isochronous OUT data transfers\nThis section describes the application programming sequence when isochronous OUT data \npackets are dropped inside the core.\nInternal data flow:\n1.\nFor isochronous OUT endpoints, the XFRC interrupt (in OTG_HS_DOEPINTx) may not \nalways be asserted. If the core drops isochronous OUT data packets, the application \ncould fail to detect the XFRC interrupt (OTG_HS_DOEPINTx) under the following \ncircumstances:\n–\nWhen the receive FIFO cannot accommodate the complete ISO OUT data packet, \nthe core drops the received ISO OUT data\n–\nWhen the isochronous OUT data packet is received with CRC errors\n–\nWhen the isochronous OUT token received by the core is corrupted\n–\nWhen the application is very slow in reading the data from the receive FIFO\n2. \nWhen the core detects an end of periodic frame before transfer completion to all \nisochronous OUT endpoints, it asserts the incomplete Isochronous OUT data interrupt \n(IISOOXFRM in OTG_HS_GINTSTS), indicating that an XFRC interrupt (in \nOTG_HS_DOEPINTx) is not asserted on at least one of the isochronous OUT \nendpoints. At this point, the endpoint with the incomplete transfer remains enabled, but \nno active transfers remain in progress on this endpoint on the USB.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1530/1757\nRM0090 Rev 21\nApplication programming sequence:\n1.\nAsserting the IISOOXFRM interrupt (OTG_HS_GINTSTS) indicates that in the current \nframe, at least one isochronous OUT endpoint has an incomplete transfer.\n2. \nIf this occurs because isochronous OUT data is not completely emptied from the \nendpoint, the application must ensure that the application empties all isochronous OUT \ndata (data and status) from the receive FIFO before proceeding.\n–\nWhen all data are emptied from the receive FIFO, the application can detect the \nXFRC interrupt (OTG_HS_DOEPINTx). In this case, the application must re-\nenable the endpoint to receive isochronous OUT data in the next frame.\n3. \nWhen it receives an IISOOXFRM interrupt (in OTG_HS_GINTSTS), the application \nmust read the control registers of all isochronous OUT endpoints \n(OTG_HS_DOEPCTLx) to determine which endpoints had an incomplete transfer in \nthe current micro-frame. An endpoint transfer is incomplete if both the following \nconditions are met:\n–\nEONUM bit (in OTG_HS_DOEPCTLx) = SOFFN[0] (in OTG_HS_DSTS)\n–\nEPENA = 1 (in OTG_HS_DOEPCTLx)\n4. \nThe previous step must be performed before the SOF interrupt (in \nOTG_HS_GINTSTS) is detected, to ensure that the current frame number is not \nchanged.\n5. \nFor isochronous OUT endpoints with incomplete transfers, the application must discard \nthe data in the memory and disable the endpoint by setting the EPDIS bit in \nOTG_HS_DOEPCTLx.\n6. \nWait for the EPDIS interrupt (in OTG_HS_DOEPINTx) and enable the endpoint to \nreceive new data in the next frame.\n–\nBecause the core can take some time to disable the endpoint, the application may \nnot be able to receive the data in the next frame after receiving bad isochronous \ndata.\n•\nStalling a nonisochronous OUT endpoint\nThis section describes how the application can stall a nonisochronous endpoint.\n1.\nPut the core in the Global OUT NAK mode.\n2. \nDisable the required endpoint\n–\nWhen disabling the endpoint, instead of setting the SNAK bit in \nOTG_HS_DOEPCTL, set STALL = 1 (in OTG_HS_DOEPCTL).\nThe STALL bit always takes precedence over the NAK bit.\n3. \nWhen the application is ready to end the STALL handshake for the endpoint, the \nSTALL bit (in OTG_HS_DOEPCTLx) must be cleared.\n4. \nIf the application is setting or clearing a STALL for an endpoint due to a \nSetFeature.Endpoint Halt or ClearFeature.Endpoint Halt command, the STALL bit must \nbe set or cleared before the application sets up the Status stage transfer on the control \nendpoint.\nExamples\nThis section describes and depicts some fundamental transfer types and scenarios.\n•\nSlave mode bulk OUT transaction\nFigure 428 depicts the reception of a single Bulk OUT Data packet from the USB to the AHB \nand describes the events involved in the process.\n\n\n<>\n\nRM0090 Rev 21\n1531/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nFigure 428. Slave mode bulk OUT transaction\nAfter a SetConfiguration/SetInterface command, the application initializes all OUT endpoints \nby setting CNAK = 1 and EPENA = 1 (in OTG_HS_DOEPCTLx), and setting a suitable \nXFRSIZ and PKTCNT in the OTG_HS_DOEPTSIZx register.\n1.\nHost attempts to send data (OUT token) to an endpoint.\n2. \nWhen the core receives the OUT token on the USB, it stores the packet in the RxFIFO \nbecause space is available there.\n3. \nAfter writing the complete packet in the RxFIFO, the core then asserts the RXFLVL \ninterrupt (in OTG_HS_GINTSTS).\n4. \nOn receiving the PKTCNT number of USB packets, the core internally sets the NAK bit \nfor this endpoint to prevent it from receiving any more packets.\n5. \nThe application processes the interrupt and reads the data from the RxFIFO.\n6. \nWhen the application has read all the data (equivalent to XFRSIZ), the core generates \nan XFRC interrupt (in OTG_HS_DOEPINTx).\n7. \nThe application processes the interrupt and uses the setting of the XFRC interrupt bit \n(in OTG_HS_DOEPINTx) to determine that the intended transfer is complete.\nIN data transfers\n•\nPacket write\nThis section describes how the application writes data packets to the endpoint FIFO in Slave \nmode when dedicated transmit FIFOs are enabled.\ninit_out_ep\n Host\nDevice\nUSB\nOUT\nACK\nRXFLVL intr\n i\nwr_reg (DOEPTSIZx)\nwr_reg(DOEPCTLx)\n512 bytes\nOUT\nNAK\nxact_1\nApplication\nXFRC \nintr\nDOEPCTLx.NAK=1\nPKTCNT 0\nXFRSIZ = 0\nr\n \n \nidle until intr\nrcv_out_pkt()\nidle until intr\nOn new xfer\nor RxFIFO\nnot empty\n1\n2\n3\n4\n5\n6\n7\n8\nXFRSIZ = 512 bytes\nPKTCNT = 1\nEPENA = 1\nCNAK = 1\nai15679\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1532/1757\nRM0090 Rev 21\n1.\nThe application can either choose the polling or the interrupt mode.\n–\nIn polling mode, the application monitors the status of the endpoint transmit data \nFIFO by reading the OTG_HS_DTXFSTSx register, to determine if there is \nenough space in the data FIFO.\n–\nIn interrupt mode, the application waits for the TXFE interrupt (in \nOTG_HS_DIEPINTx) and then reads the OTG_HS_DTXFSTSx register, to \ndetermine if there is enough space in the data FIFO.\n–\nTo write a single nonzero length data packet, there must be space to write the \nentire packet in the data FIFO.\n–\nTo write zero length packet, the application must not look at the FIFO space.\n2. \nUsing one of the above mentioned methods, when the application determines that \nthere is enough space to write a transmit packet, the application must first write into the \nendpoint control register, before writing the data into the data FIFO. Typically, the \napplication, must do a read modify write on the OTG_HS_DIEPCTLx register to avoid \nmodifying the contents of the register, except for setting the Endpoint Enable bit.\nThe application can write multiple packets for the same endpoint into the transmit FIFO, if \nspace is available. For periodic IN endpoints, the application must write packets only for one \nmicro-frame. It can write packets for the next periodic transaction only after getting transfer \ncomplete for the previous transaction.\n•\nSetting IN endpoint NAK\nInternal data flow:\n1.\nWhen the application sets the IN NAK for a particular endpoint, the core stops \ntransmitting data on the endpoint, irrespective of data availability in the endpoint’s \ntransmit FIFO.\n2. \nNonisochronous IN tokens receive a NAK handshake reply\n–\nIsochronous IN tokens receive a zero-data-length packet reply\n3. \nThe core asserts the INEPNE (IN endpoint NAK effective) interrupt in \nOTG_HS_DIEPINTx in response to the SNAK bit in OTG_HS_DIEPCTLx.\n4. \nOnce this interrupt is seen by the application, the application can assume that the \nendpoint is in IN NAK mode. This interrupt can be cleared by the application by setting \nthe CNAK bit in OTG_HS_DIEPCTLx.\nApplication programming sequence:\n\n\n<>\n\nRM0090 Rev 21\n1533/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n1.\nTo stop transmitting any data on a particular IN endpoint, the application must set the \nIN NAK bit. To set this bit, the following field must be programmed.\n–\nSNAK = 1 in OTG_HS_DIEPCTLx\n2. \nWait for assertion of the INEPNE interrupt in OTG_HS_DIEPINTx. This interrupt \nindicates that the core has stopped transmitting data on the endpoint.\n3. \nThe core can transmit valid IN data on the endpoint after the application has set the \nNAK bit, but before the assertion of the NAK Effective interrupt.\n4. \nThe application can mask this interrupt temporarily by writing to the INEPNEM bit in \nDIEPMSK.\n–\nINEPNEM = 0 in DIEPMSK\n5. \nTo exit Endpoint NAK mode, the application must clear the NAK status bit (NAKSTS) in \nOTG_HS_DIEPCTLx. This also clears the INEPNE interrupt (in OTG_HS_DIEPINTx).\n–\nCNAK = 1 in OTG_HS_DIEPCTLx\n6. \nIf the application masked this interrupt earlier, it must be unmasked as follows:\n–\nINEPNEM = 1 in DIEPMSK\n•\nIN endpoint disable\nUse the following sequence to disable a specific IN endpoint that has been previously \nenabled.\nApplication programming sequence:\n1.\nThe application must stop writing data on the AHB for the IN endpoint to be disabled.\n2. \nThe application must set the endpoint in NAK mode. \n–\nSNAK = 1 in OTG_HS_DIEPCTLx\n3. \nWait for the INEPNE interrupt in OTG_HS_DIEPINTx.\n4. \nSet the following bits in the OTG_HS_DIEPCTLx register for the endpoint that must be \ndisabled.\n–\nEPDIS = 1 in OTG_HS_DIEPCTLx\n–\nSNAK = 1 in OTG_HS_DIEPCTLx\n5. \nAssertion of the EPDISD interrupt in OTG_HS_DIEPINTx indicates that the core has \ncompletely disabled the specified endpoint. Along with the assertion of the interrupt, the \ncore also clears the following bits:\n–\nEPENA = 0 in OTG_HS_DIEPCTLx\n–\nEPDIS = 0 in OTG_HS_DIEPCTLx\n6. \nThe application must read the OTG_HS_DIEPTSIZx register for the periodic IN EP, to \ncalculate how much data on the endpoint were transmitted on the USB.\n7. \nThe application must flush the data in the Endpoint transmit FIFO, by setting the \nfollowing fields in the OTG_HS_GRSTCTL register:\n–\nTXFNUM (in OTG_HS_GRSTCTL) = Endpoint transmit FIFO number\n–\nTXFFLSH in (OTG_HS_GRSTCTL) = 1\nThe application must poll the OTG_HS_GRSTCTL register, until the TXFFLSH bit is cleared \nby the core, which indicates the end of flush operation. To transmit new data on this \nendpoint, the application can re-enable the endpoint at a later point.\n•\nTransfer Stop Programming for IN endpoints\nThe application must use the following programing sequence to stop any transfers (because \nof an interrupt from the host, typically a reset).\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1534/1757\nRM0090 Rev 21\nSequence of operations:\n1.\nDisable the IN endpoint by setting:\n–\nEPDIS = 1 in all OTG_HS_DIEPCTLx registers\n2. \nWait for the EPDIS interrupt in OTG_HS_DIEPINTx, which indicates that the IN \nendpoint is completely disabled. When the EPDIS interrupt is asserted the following \nbits are cleared:\n–\nEPDIS = 0 in OTG_HS_DIEPCTLx\n–\nEPENA = 0 in OTG_HS_DIEPCTLx\n3. \nFlush the TxFIFO by programming the following bits:\n–\nTXFFLSH = 1 in OTG_HS_GRSTCTL\n–\nTXFNUM = “FIFO number specific to endpoint” in OTG_HS_GRSTCTL\n4. \nThe application can start polling till TXFFLSH in OTG_HS_GRSTCTL is cleared. When \nthis bit is cleared, it ensures that there is no data left in the Tx FIFO.\n•\nGeneric non-periodic IN data transfers\nApplication requirements:\n1.\nBefore setting up an IN transfer, the application must ensure that all data to be \ntransmitted as part of the IN transfer are part of a single buffer.\n2. \nFor IN transfers, the Transfer Size field in the Endpoint Transfer Size register denotes a \npayload that constitutes multiple maximum-packet-size packets and a single short \npacket. This short packet is transmitted at the end of the transfer.\n–\nTo transmit a few maximum-packet-size packets and a short packet at the end of \nthe transfer:\nTransfer size[EPNUM] = x × MPSIZ[EPNUM] + sp\nIf (sp > 0), then packet count[EPNUM] = x + 1. \nOtherwise, packet count[EPNUM] = x\n–\nTo transmit a single zero-length data packet:\nTransfer size[EPNUM] = 0\nPacket count[EPNUM] = 1\n–\nTo transmit a few maximum-packet-size packets and a zero-length data packet at \nthe end of the transfer, the application must split the transfer into two parts. The \nfirst sends maximum-packet-size data packets and the second sends the zero-\nlength data packet alone.\nFirst transfer: transfer size[EPNUM] = x × MPSIZ[epnum]; packet count = n;\nSecond transfer: transfer size[EPNUM] = 0; packet count = 1;\n3. \nOnce an endpoint is enabled for data transfers, the core updates the Transfer size \nregister. At the end of the IN transfer, the application must read the Transfer size \nregister to determine how much data posted in the transmit FIFO have already been \nsent on the USB.\n4. \nData fetched into transmit FIFO = Application-programmed initial transfer size – core-\nupdated final transfer size\n–\nData transmitted on USB = (application-programmed initial packet count – Core \nupdated final packet count) × MPSIZ[EPNUM]\n–\nData yet to be transmitted on USB = (Application-programmed initial transfer size \n– data transmitted on USB)\nInternal data flow:\n\n\n<>\n\nRM0090 Rev 21\n1535/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n1.\nThe application must set the transfer size and packet count fields in the endpoint-\nspecific registers and enable the endpoint to transmit the data.\n2. \nThe application must also write the required data to the transmit FIFO for the endpoint.\n3. \nEvery time a packet is written into the transmit FIFO by the application, the transfer size \nfor that endpoint is decremented by the packet size. The data is fetched from the \nmemory by the application, until the transfer size for the endpoint becomes 0. After \nwriting the data into the FIFO, the “number of packets in FIFO” count is incremented \n(this is a 3-bit count, internally maintained by the core for each IN endpoint transmit \nFIFO. The maximum number of packets maintained by the core at any time in an IN \nendpoint FIFO is eight). For zero-length packets, a separate flag is set for each FIFO, \nwithout any data in the FIFO.\n4. \nOnce the data are written to the transmit FIFO, the core reads them out upon receiving \nan IN token. For every nonisochronous IN data packet transmitted with an ACK \nhandshake, the packet count for the endpoint is decremented by one, until the packet \ncount is zero. The packet count is not decremented on a timeout.\n5. \nFor zero length packets (indicated by an internal zero length flag), the core sends out a \nzero-length packet for the IN token and decrements the packet count field.\n6. \nIf there are no data in the FIFO for a received IN token and the packet count field for \nthat endpoint is zero, the core generates an “IN token received when TxFIFO is empty” \n(ITTXFE) Interrupt for the endpoint, provided that the endpoint NAK bit is not set. The \ncore responds with a NAK handshake for nonisochronous endpoints on the USB.\n7. \nThe core internally rewinds the FIFO pointers and no timeout interrupt is generated.\n8. \nWhen the transfer size is 0 and the packet count is 0, the transfer complete (XFRC) \ninterrupt for the endpoint is generated and the endpoint enable is cleared.\nApplication programming sequence:\n1.\nProgram the OTG_HS_DIEPTSIZx register with the transfer size and corresponding \npacket count.\n2. \nProgram the OTG_HS_DIEPCTLx register with the endpoint characteristics and set the \nCNAK and EPENA (Endpoint Enable) bits.\n3. \nWhen transmitting nonzero length data packet, the application must poll the \nOTG_HS_DTXFSTSx register (where x is the FIFO number associated with that \nendpoint) to determine whether there is enough space in the data FIFO. The \napplication can optionally use TXFE (in OTG_HS_DIEPINTx) before writing the data.\n•\nGeneric periodic IN data transfers\nThis section describes a typical periodic IN data transfer.\nApplication requirements:\n1.\nApplication requirements 1, 2, 3, and 4 of Generic non-periodic IN data transfers on \npage 1534also apply to periodic IN data transfers, except for a slight modification of \nrequirement 2.\n–\nThe application can only transmit multiples of maximum-packet-size data packets \nor multiples of maximum-packet-size packets, plus a short packet at the end. To \n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1536/1757\nRM0090 Rev 21\ntransmit a few maximum-packet-size packets and a short packet at the end of the \ntransfer, the following conditions must be met:\ntransfer size[EPNUM] = x × MPSIZ[EPNUM] + sp\n(where x is an integer ≥0, and 0 ≤sp < MPSIZ[EPNUM])\nIf (sp > 0), packet count[EPNUM] = x + 1\nOtherwise, packet count[EPNUM] = x;\nMCNT[EPNUM] = packet count[EPNUM]\n–\nThe application cannot transmit a zero-length data packet at the end of a transfer. \nIt can transmit a single zero-length data packet by itself. To transmit a single zero-\nlength data packet:\n–\ntransfer size[EPNUM] = 0\npacket count[EPNUM] = 1\nMCNT[EPNUM] = packet count[EPNUM]\n2. \nThe application can only schedule data transfers one frame at a time.\n–\n(MCNT – 1) × MPSIZ ≤XFERSIZ ≤MCNT × MPSIZ\n–\nPKTCNT = MCNT (in OTG_HS_DIEPTSIZx)\n–\nIf XFERSIZ < MCNT × MPSIZ, the last data packet of the transfer is a short \npacket.\n–\nNote that: MCNT is in OTG_HS_DIEPTSIZx, MPSIZ is in OTG_HS_DIEPCTLx, \nPKTCNT is in OTG_HS_DIEPTSIZx and XFERSIZ is in OTG_HS_DIEPTSIZx\n3. \nThe complete data to be transmitted in the frame must be written into the transmit FIFO \nby the application, before the IN token is received. Even when 1 word of the data to be \ntransmitted per frame is missing in the transmit FIFO when the IN token is received, the \ncore behaves as when the FIFO is empty. When the transmit FIFO is empty:\n–\nA zero data length packet would be transmitted on the USB for isochronous IN \nendpoints\n–\nA NAK handshake would be transmitted on the USB for interrupt IN endpoints\n4. \nFor a high-bandwidth IN endpoint with three packets in a frame, the application can \nprogram the endpoint FIFO size to be 2 × max_pkt_size and have the third packet \nloaded in after the first packet has been transmitted on the USB.\nInternal data flow:\n1.\nThe application must set the transfer size and packet count fields in the endpoint-\nspecific registers and enable the endpoint to transmit the data.\n2. \nThe application must also write the required data to the associated transmit FIFO for \nthe endpoint.\n3. \nEvery time the application writes a packet to the transmit FIFO, the transfer size for that \nendpoint is decremented by the packet size. The data are fetched from application \nmemory until the transfer size for the endpoint becomes 0.\n4. \nWhen an IN token is received for a periodic endpoint, the core transmits the data in the \nFIFO, if available. If the complete data payload (complete packet, in dedicated FIFO \n\n\n<>\n\nRM0090 Rev 21\n1537/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nmode) for the frame is not present in the FIFO, then the core generates an IN token \nreceived when TxFIFO empty interrupt for the endpoint.\n–\nA zero-length data packet is transmitted on the USB for isochronous IN endpoints\n–\nA NAK handshake is transmitted on the USB for interrupt IN endpoints\n5. \nThe packet count for the endpoint is decremented by 1 under the following conditions:\n–\nFor isochronous endpoints, when a zero- or nonzero-length data packet is \ntransmitted\n–\nFor interrupt endpoints, when an ACK handshake is transmitted\n–\nWhen the transfer size and packet count are both 0, the transfer completed \ninterrupt for the endpoint is generated and the endpoint enable is cleared.\n6. \nAt the “Periodic frame Interval” (controlled by PFIVL in OTG_HS_DCFG), when the \ncore finds nonempty any of the isochronous IN endpoint FIFOs scheduled for the \ncurrent frame nonempty, the core generates an IISOIXFR interrupt in \nOTG_HS_GINTSTS.\nApplication programming sequence:\n1.\nProgram the OTG_HS_DIEPCTLx register with the endpoint characteristics and set the \nCNAK and EPENA bits.\n2. \nWrite the data to be transmitted in the next frame to the transmit FIFO.\n3. \nAsserting the ITTXFE interrupt (in OTG_HS_DIEPINTx) indicates that the application \nhas not yet written all data to be transmitted to the transmit FIFO.\n4. \nIf the interrupt endpoint is already enabled when this interrupt is detected, ignore the \ninterrupt. If it is not enabled, enable the endpoint so that the data can be transmitted on \nthe next IN token attempt.\n5. \nAsserting the XFRC interrupt (in OTG_HS_DIEPINTx) with no ITTXFE interrupt in \nOTG_HS_DIEPINTx indicates the successful completion of an isochronous IN transfer. \nA read to the OTG_HS_DIEPTSIZx register must give transfer size = 0 and packet \ncount = 0, indicating all data were transmitted on the USB.\n6. \nAsserting the XFRC interrupt (in OTG_HS_DIEPINTx), with or without the ITTXFE \ninterrupt (in OTG_HS_DIEPINTx), indicates the successful completion of an interrupt \nIN transfer. A read to the OTG_HS_DIEPTSIZx register must give transfer size = 0 and \npacket count = 0, indicating all data were transmitted on the USB.\n7. \nAsserting the incomplete isochronous IN transfer (IISOIXFR) interrupt in \nOTG_HS_GINTSTS with none of the aforementioned interrupts indicates the core did \nnot receive at least 1 periodic IN token in the current frame.\n•\nIncomplete isochronous IN data transfers\nThis section describes what the application must do on an incomplete isochronous IN data \ntransfer.\nInternal data flow:\n1.\nAn isochronous IN transfer is treated as incomplete in one of the following conditions:\na) \nThe core receives a corrupted isochronous IN token on at least one isochronous \nIN endpoint. In this case, the application detects an incomplete isochronous IN \ntransfer interrupt (IISOIXFR in OTG_HS_GINTSTS).\nb) \nThe application is slow to write the complete data payload to the transmit FIFO \nand an IN token is received before the complete data payload is written to the \nFIFO. In this case, the application detects an IN token received when TxFIFO \nempty interrupt in OTG_HS_DIEPINTx. The application can ignore this interrupt, \n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1538/1757\nRM0090 Rev 21\nas it eventually results in an incomplete isochronous IN transfer interrupt \n(IISOIXFR in OTG_HS_GINTSTS) at the end of periodic frame.\nThe core transmits a zero-length data packet on the USB in response to the \nreceived IN token.\n2. \nThe application must stop writing the data payload to the transmit FIFO as soon as \npossible.\n3. \nThe application must set the NAK bit and the disable bit for the endpoint.\n4. \nThe core disables the endpoint, clears the disable bit, and asserts the Endpoint Disable \ninterrupt for the endpoint.\nApplication programming sequence\n1.\nThe application can ignore the IN token received when TxFIFO empty interrupt in \nOTG_HS_DIEPINTx on any isochronous IN endpoint, as it eventually results in an \nincomplete isochronous IN transfer interrupt (in OTG_HS_GINTSTS).\n2. \nAssertion of the incomplete isochronous IN transfer interrupt (in OTG_HS_GINTSTS) \nindicates an incomplete isochronous IN transfer on at least one of the isochronous IN \nendpoints.\n3. \nThe application must read the Endpoint Control register for all isochronous IN \nendpoints to detect endpoints with incomplete IN data transfers.\n4. \nThe application must stop writing data to the Periodic Transmit FIFOs associated with \nthese endpoints on the AHB.\n5. \nProgram the following fields in the OTG_HS_DIEPCTLx register to disable the \nendpoint:\n–\nSNAK = 1 in OTG_HS_DIEPCTLx\n–\nEPDIS = 1 in OTG_HS_DIEPCTLx\n6. \nThe assertion of the Endpoint Disabled interrupt in OTG_HS_DIEPINTx indicates that \nthe core has disabled the endpoint.\n–\nAt this point, the application must flush the data in the associated transmit FIFO or \noverwrite the existing data in the FIFO by enabling the endpoint for a new transfer \nin the next micro-frame. To flush the data, the application must use the \nOTG_HS_GRSTCTL register.\n•\nStalling nonisochronous IN endpoints\nThis section describes how the application can stall a nonisochronous endpoint.\nApplication programming sequence:\n\n\n<>\n\nRM0090 Rev 21\n1539/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n1.\nDisable the IN endpoint to be stalled. Set the STALL bit as well.\n2. \nEPDIS = 1 in OTG_HS_DIEPCTLx, when the endpoint is already enabled\n–\nSTALL = 1 in OTG_HS_DIEPCTLx\n–\nThe STALL bit always takes precedence over the NAK bit\n3. \nAssertion of the Endpoint Disabled interrupt (in OTG_HS_DIEPINTx) indicates to the \napplication that the core has disabled the specified endpoint.\n4. \nThe application must flush the nonperiodic or periodic transmit FIFO, depending on the \nendpoint type. In case of a nonperiodic endpoint, the application must re-enable the \nother nonperiodic endpoints that do not need to be stalled, to transmit data.\n5. \nWhenever the application is ready to end the STALL handshake for the endpoint, the \nSTALL bit must be cleared in OTG_HS_DIEPCTLx.\n6. \nIf the application sets or clears a STALL bit for an endpoint due to a \nSetFeature.Endpoint Halt command or ClearFeature.Endpoint Halt command, the \nSTALL bit must be set or cleared before the application sets up the Status stage \ntransfer on the control endpoint.\nSpecial case: stalling the control OUT endpoint\nThe core must stall IN/OUT tokens if, during the data stage of a control transfer, the host \nsends more IN/OUT tokens than are specified in the SETUP packet. In this case, the \napplication must enable the ITTXFE interrupt in OTG_HS_DIEPINTx and the OTEPDIS \ninterrupt in OTG_HS_DOEPINTx during the data stage of the control transfer, after the core \nhas transferred the amount of data specified in the SETUP packet. Then, when the \napplication receives this interrupt, it must set the STALL bit in the corresponding endpoint \ncontrol register, and clear this interrupt.\n35.13.8 \nWorst case response time\nWhen the OTG_HS controller acts as a device, there is a worst case response time for any \ntokens that follow an isochronous OUT. This worst case response time depends on the AHB \nclock frequency.\nThe core registers are in the AHB domain, and the core does not accept another token \nbefore updating these register values. The worst case is for any token following an \nisochronous OUT, because for an isochronous transaction, there is no handshake and the \nnext token could come sooner. This worst case value is 7 PHY clocks when the AHB clock \nis the same as the PHY clock. When the AHB clock is faster, this value is smaller.\nIf this worst case condition occurs, the core responds to bulk/interrupt tokens with a NAK \nand drops isochronous and SETUP tokens. The host interprets this as a timeout condition \nfor SETUP and retries the SETUP packet. For isochronous transfers, the Incomplete \nisochronous IN transfer interrupt (IISOIXFR) and Incomplete isochronous OUT transfer \ninterrupt (IISOOXFR) inform the application that isochronous IN/OUT packets were \ndropped.\nChoosing the value of TRDT in OTG_HS_GUSBCFG\nThe value in TRDT (OTG_HS_GUSBCFG) is the time it takes for the MAC, in terms of PHY \nclocks after it has received an IN token, to get the FIFO status, and thus the first data from \nthe PFC block. This time involves the synchronization delay between the PHY and AHB \nclocks. The worst case delay for this is when the AHB clock is the same as the PHY clock. \nIn this case, the delay is 5 clocks.\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1540/1757\nRM0090 Rev 21\nOnce the MAC receives an IN token, this information (token received) is synchronized to the \nAHB clock by the PFC (the PFC runs on the AHB clock). The PFC then reads the data from \nthe SPRAM and writes them into the dual clock source buffer. The MAC then reads the data \nout of the source buffer (4 deep).\nIf the AHB is running at a higher frequency than the PHY, the application can use a smaller \nvalue for TRDT (in OTG_HS_GUSBCFG).\nFigure 429 has the following signals:\n•\ntkn_rcvd: Token received information from MAC to PFC\n•\ndynced_tkn_rcvd: Doubled sync tkn_rcvd, from PCLK to HCLK domain\n•\nspr_read: Read to SPRAM\n•\nspr_addr: Address to SPRAM\n•\nspr_rdata: Read data from SPRAM\n•\nsrcbuf_push: Push to the source buffer\n•\nsrcbuf_rdata: Read data from the source buffer. Data seen by MAC\nRefer to Table 214: TRDT values for the values of TRDT versus AHB clock frequency. \nFigure 429. TRDT max timing case \n1\n2\n3\n4\n5\n6\n7\n8\n0ns\n50ns\n100ns\n150ns\n200ns\nHCLK\nPCLK\ntkn_rcvd\ndsynced_tkn_rcvd\nspr_read\nspr_addr\nspr_rdata\nsrcbuf_push\nsrcbuf_rdata\n5 Clocks\nD1\nA1\nD1\nai15680\n\n\n<>\n\nRM0090 Rev 21\n1541/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n35.13.9 \nOTG programming model\nThe OTG_HS controller is an OTG device supporting HNP and SRP. When the core is \nconnected to an “A” plug, it is referred to as an A-device. When the core is connected to a \n“B” plug it is referred to as a B-device. In host mode, the OTG_HS controller turns off VBUS \nto conserve power. SRP is a method by which the B-device signals the A-device to turn on \nVBUS power. A device must perform both data-line pulsing and VBUS pulsing, but a host can \ndetect either data-line pulsing or VBUS pulsing for SRP. HNP is a method by which the B-\ndevice negotiates and switches to host role. In Negotiated mode after HNP, the B-device \nsuspends the bus and reverts to the device role.\nA-device session request protocol\nThe application must set the SRP-capable bit in the Core USB configuration register. This \nenables the OTG_HS controller to detect SRP as an A-device.\nFigure 430. A-device SRP\n1.\nDRV_VBUS = VBUS drive signal to the PHY\nVBUS_VALID = VBUS valid signal from PHY\nA_VALID = A-device VBUS level signal to PHY\nDP = Data plus line\nDM = Data minus line\nai15681b\nDRV_VBUS\nVBUS_VALID\nA_VALID\nOTG_HS_FS_DP\nOTG_HS_FS_DM\nSuspend\nVBUS pulsing\nData line pulsing\nConnect\n1\n6\n2\n5\n3\n4\n7\nLow\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1542/1757\nRM0090 Rev 21\n1.\nTo save power, the application suspends and turns off port power when the bus is idle \nby writing the port suspend and port power bits in the host port control and status \nregister.\n2. \nPHY indicates port power off by deasserting the VBUS_VALID signal.\n3. \nThe device must detect SE0 for at least 2 ms to start SRP when VBUS power is off.\n4. \nTo initiate SRP, the device turns on its data line pull-up resistor for 5 to 10 ms. The \nOTG_HS controller detects data-line pulsing.\n5. \nThe device drives VBUS above the A-device session valid (2.0 V minimum) for VBUS \npulsing.\nThe OTG_HS controller interrupts the application on detecting SRP. The Session \nrequest detected bit is set in Global interrupt status register (SRQINT set in \nOTG_HS_GINTSTS).\n6. \nThe application must service the Session request detected interrupt and turn on the \nport power bit by writing the port power bit in the host port control and status register. \nThe PHY indicates port power-on by asserting the VBUS_VALID signal.\n7. \nWhen the USB is powered, the device connects, completing the SRP process.\nB-device session request protocol\nThe application must set the SRP-capable bit in the Core USB configuration register. This \nenables the OTG_HS controller to initiate SRP as a B-device. SRP is a means by which the \nOTG_HS controller can request a new session from the host.\nFigure 431. B-device SRP\n1.\nVBUS_VALID = VBUS valid signal from PHY\nB_VALID = B-device valid session to PHY\nDISCHRG_VBUS = discharge signal to PHY\nSESS_END = session end signal to PHY\nCHRG_VBUS = charge VBUS signal to PHY\nDP = Data plus line\nDM = Data minus line\nai1568b2\nVBUS_VALID\nB_VALID\nDISCHRG_VBUS\nSESS_END\nOTG_HS_FS_DP\nOTG_HS_FS_DM\nCHRG_VBUS\nSuspend\nData line pulsing\nConnect\nVBUS pulsing\n1\n6\n2\n3\n4\n5\n8\n7\nLow\n\n\n<>\n\nRM0090 Rev 21\n1543/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n1.\nTo save power, the host suspends and turns off port power when the bus is idle.\nThe OTG_HS controller sets the early suspend bit in the Core interrupt register after 3 \nms of bus idleness. Following this, the OTG_HS controller sets the USB suspend bit in \nthe Core interrupt register.\nThe OTG_HS controller informs the PHY to discharge VBUS.\n2. \nThe PHY indicates the session’s end to the device. This is the initial condition for SRP. \nThe OTG_HS controller requires 2 ms of SE0 before initiating SRP.\nFor a USB 1.1 full-speed serial transceiver, the application must wait until VBUS \ndischarges to 0.2 V after BSVLD (in OTG_HS_GOTGCTL) is deasserted. This \ndischarge time can be obtained from the transceiver vendor and varies from one \ntransceiver to another.\n3. \nThe USB OTG core informs the PHY to speed up VBUS discharge.\n4. \nThe application initiates SRP by writing the session request bit in the OTG Control and \nstatus register. The OTG_HS controller perform data-line pulsing followed by VBUS \npulsing.\n5. \nThe host detects SRP from either the data-line or VBUS pulsing, and turns on VBUS. \nThe PHY indicates VBUS power-on to the device.\n6. \nThe OTG_HS controller performs VBUS pulsing.\nThe host starts a new session by turning on VBUS, indicating SRP success. The \nOTG_HS controller interrupts the application by setting the session request success \nstatus change bit in the OTG interrupt status register. The application reads the session \nrequest success bit in the OTG control and status register.\n7. \nWhen the USB is powered, the OTG_HS controller connects, completing the SRP \nprocess.\nA-device host negotiation protocol\nHNP switches the USB host role from the A-device to the B-device. The application must set \nthe HNP-capable bit in the Core USB configuration register to enable the OTG_HS \ncontroller to perform HNP as an A-device.\nFigure 432. A-device HNP\n1.\nDPPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DP line inside the PHY.\nDMPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DM line inside the PHY.\nai15683b\nOTG core\nDP\nDM\nDPPULLDOWN\nDMPULLDOWN\nHost\nDevice\nHost\n1\nSuspend 2\n3\n4\n5\nReset\n6\nTraffic\n7\n8\nConnect\nTraffic\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1544/1757\nRM0090 Rev 21\n1.\nThe OTG_HS controller sends the B-device a SetFeature b_hnp_enable descriptor to \nenable HNP support. The B-device’s ACK response indicates that the B-device \nsupports HNP. The application must set host Set HNP Enable bit in the OTG Control \nand status register to indicate to the OTG_HS controller that the B-device supports \nHNP.\n2. \nWhen it has finished using the bus, the application suspends by writing the Port \nsuspend bit in the host port control and status register.\n3. \nWhen the B-device observes a USB suspend, it disconnects, indicating the initial \ncondition for HNP. The B-device initiates HNP only when it must switch to the host role; \notherwise, the bus continues to be suspended.\nThe OTG_HS controller sets the host negotiation detected interrupt in the OTG \ninterrupt status register, indicating the start of HNP.\nThe OTG_HS controller deasserts the DM pull down and DM pull down in the PHY to \nindicate a device role. The PHY enables the OTG_HS_DP pull-up resistor to indicate a \nconnect for B-device.\nThe application must read the current mode bit in the OTG Control and status register \nto determine peripheral mode operation.\n4. \nThe B-device detects the connection, issues a USB reset, and enumerates the \nOTG_HS controller for data traffic.\n5. \nThe B-device continues the host role, initiating traffic, and suspends the bus when \ndone.\nThe OTG_HS controller sets the early suspend bit in the Core interrupt register after 3 \nms of bus idleness. Following this, the OTG_HS controller sets the USB Suspend bit in \nthe Core interrupt register.\n6. \nIn Negotiated mode, the OTG_HS controller detects the suspend, disconnects, and \nswitches back to the host role. The OTG_HS controller asserts the DM pull down and \nDM pull down in the PHY to indicate its assumption of the host role.\n7. \nThe OTG_HS controller sets the Connector ID status change interrupt in the OTG \nInterrupt Status register. The application must read the connector ID status in the OTG \nControl and Status register to determine the OTG_HS controller operation as an A-\ndevice. This indicates the completion of HNP to the application. The application must \nread the Current mode bit in the OTG control and status register to determine host \nmode operation.\n8. \nThe B-device connects, completing the HNP process.\nB-device host negotiation protocol\nHNP switches the USB host role from B-device to A-device. The application must set the \nHNP-capable bit in the Core USB configuration register to enable the OTG_HS controller to \nperform HNP as a B-device.\n\n\n<>\n\nRM0090 Rev 21\n1545/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nFigure 433. B-device HNP\n1.\nDPPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DP line inside the PHY.\nDMPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DM line inside the PHY.\n1.\nThe A-device sends the SetFeature b_hnp_enable descriptor to enable HNP support. \nThe OTG_HS controller’s ACK response indicates that it supports HNP. The \napplication must set the Device HNP enable bit in the OTG Control and status register \nto indicate HNP support.\nThe application sets the HNP request bit in the OTG Control and status register to \nindicate to the OTG_HS controller to initiate HNP.\n2. \nWhen it has finished using the bus, the A-device suspends by writing the Port suspend \nbit in the host port control and status register.\nThe OTG_HS controller sets the Early suspend bit in the Core interrupt register after 3 \nms of bus idleness. Following this, the OTG_HS controller sets the USB suspend bit in \nthe Core interrupt register.\nThe OTG_HS controller disconnects and the A-device detects SE0 on the bus, \nindicating HNP. The OTG_HS controller asserts the DP pull down and DM pull down in \nthe PHY to indicate its assumption of the host role.\nThe A-device responds by activating its OTG_HS_DP pull-up resistor within 3 ms of \ndetecting SE0. The OTG_HS controller detects this as a connect.\nThe OTG_HS controller sets the host negotiation success status change interrupt in \nthe OTG Interrupt status register, indicating the HNP status. The application must read \nthe host negotiation success bit in the OTG Control and status register to determine \nai15684b\nOTG core\nDP\nDM\nDPPULLDOWN\nDMPULLDOWN\nHost\nDevice\nDevice\n1\nSuspend 2\n3\n4\n5\nReset\n6\nTraffic\n7\n8\nConnect\nTraffic\n\n\n<>\n\nUSB on-the-go high-speed (OTG_HS)\nRM0090\n1546/1757\nRM0090 Rev 21\nhost negotiation success. The application must read the current Mode bit in the Core \ninterrupt register (OTG_HS_GINTSTS) to determine host mode operation.\n3. \nThe application sets the reset bit (PRST in OTG_HS_HPRT) and the OTG_HS \ncontroller issues a USB reset and enumerates the A-device for data traffic.\n4. \nThe OTG_HS controller continues the host role of initiating traffic, and when done, \nsuspends the bus by writing the Port suspend bit in the host port control and status \nregister.\n5. \nIn Negotiated mode, when the A-device detects a suspend, it disconnects and switches \nback to the host role. The OTG_HS controller deasserts the DP pull down and DM pull \ndown in the PHY to indicate the assumption of the device role.\n6. \nThe application must read the current mode bit in the Core interrupt \n(OTG_HS_GINTSTS) register to determine the host mode operation.\n7. \nThe OTG_HS controller connects, completing the HNP process.\n \n\n\n<>\n\nRM0090 Rev 21\n1547/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n36 \nFlexible static memory controller (FSMC)\nThis section applies to the whole STM32F40x/41x family only.\n36.1 \nFSMC main features\nThe FSMC block is able to interface with synchronous and asynchronous memories and \n16-bit PC memory cards. Its main purpose is to:\n•\nTranslate the AHB transactions into the appropriate external device protocol\n•\nMeet the access timing requirements of the external devices\nAll external memories share the addresses, data and control signals with the controller. \nEach external device is accessed by means of a unique chip select. The FSMC performs \nonly one access at a time to an external device.\nThe FSMC has the following main features:\n•\nInterfaces with static memory-mapped devices including: \n–\nStatic random access memory (SRAM)\n–\nNOR/OneNAND flash memory\n–\nPSRAM (4 memory banks)\n•\nTwo banks of NAND Flash with ECC hardware that checks up to 8 Kbytes of data\n•\n16-bit PC Card compatible devices\n•\nSupports burst mode access to synchronous devices (NOR flash and PSRAM)\n•\n8- or 16-bit wide databus\n•\nIndependent chip select control for each memory bank\n•\nIndependent configuration for each memory bank\n•\nProgrammable timings to support a wide range of devices, in particular:\n–\nProgrammable wait states (up to 15)\n–\nProgrammable bus turnaround cycles (up to 15)\n–\nProgrammable output enable and write enable delays (up to 15)\n–\nIndependent read and write timings and protocol, so as to support the widest \nvariety of memories and timings\n•\nWrite enable and byte lane select outputs for use with PSRAM and SRAM devices\n•\nTranslation of 32-bit wide AHB transactions into consecutive 16-bit or 8-bit accesses to \nexternal 16-bit or 8-bit devices\n•\nA Write FIFO, 2-word long (16-word long for STM32F42x and STM32F43x), each word \nis 32 bits wide, only stores data and not the address. Therefore, this FIFO only buffers \nAHB write burst transactions. This makes it possible to write to slow memories and free \nthe AHB quickly for other operations. Only one burst at a time is buffered: if a new AHB \nburst or single transaction occurs while an operation is in progress, the FIFO is \ndrained. The FSMC inserts wait states until the current memory access is complete.\n•\nExternal asynchronous wait control\nThe FSMC registers that define the external device type and associated characteristics are \nusually set at boot time and do not change until the next reset or power-up. However, it is \npossible to change the settings at any time.\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1548/1757\nRM0090 Rev 21\n36.2 \nBlock diagram\nThe FSMC consists of four main blocks:\n•\nThe AHB interface (including the FSMC configuration registers)\n•\nThe NOR flash/PSRAM controller\n•\nThe NAND Flash/PC Card controller\n•\nThe external device interface\nThe block diagram is shown in Figure 434.\nFigure 434. FSMC block diagram\n36.3 \nAHB interface\nThe AHB slave interface enables internal CPUs and other bus master peripherals to access \nthe external static memories.\nAHB transactions are translated into the external device protocol. In particular, if the \nselected external memory is 16 or 8 bits wide, 32-bit wide transactions on the AHB are split \ninto consecutive 16- or 8-bit accesses. The FSMC Chip Select (FSMC_NEx) does not \nAHB bus\nFSMC interrupt to NVIC\nNOR/PSRAM\nmemory \ncontroller\nHCLK\nFrom clock\ncontroller\nNAND/PC Card\nmemory\ncontroller\nsignals\nNAND\nShared\nsignals\nsignals\nNOR/PSRAM\nFSMC_NE[4:1]\nFSMC_NL (or NADV)\nFSMC_NWAIT\nFSMC_NOE\nFSMC_NWE\nFSMC_NIORD\nFSMC_NREG\nFSMC_CD\nsignals\nPC Card\nai15591b\nFSMC_NBL[1:0]\nFSMC_NCE[3:2]\nFSMC_INT[3:2]\nFSMC_INTR\nFSMC_NCE4_1\nFSMC_NCE4_2\nFSMC_NIOWR\nFSMC_CLK\nConfiguration\nregisters\nFSMC_A[25:0]\nFSMC_D[15:0]\n\n\n<>\n\nRM0090 Rev 21\n1549/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\ntoggle between consecutive accesses except when performing accesses in mode D with the \nextended mode enabled.\nThe FSMC generates an AHB error in the following conditions:\n•\nWhen reading or writing to an FSMC bank which is not enabled\n•\nWhen reading or writing to the NOR flash bank while the FACCEN bit is reset in the \nFSMC_BCRx register.\n•\nWhen reading or writing to the PC Card banks while the input pin FSMC_CD (Card \nPresence Detection) is low.\nThe effect of this AHB error depends on the AHB master which has attempted the R/W \naccess:\n•\nIf it is the Cortex®-M4 with FPU CPU, a hard fault interrupt is generated\n•\nIf is a DMA, a DMA transfer error is generated and the corresponding DMA channel is \nautomatically disabled. \nThe AHB clock (HCLK) is the reference clock for the FSMC.\n36.3.1 \nSupported memories and transactions\nGeneral transaction rules\nThe requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the \naccessed external device has a fixed data width. This may lead to inconsistent transfers.\nTherefore, some simple transaction rules must be followed:\n•\nAHB transaction size and memory data size are equal\nThere is no issue in this case.\n•\nAHB transaction size is greater than the memory size\nIn this case, the FSMC splits the AHB transaction into smaller consecutive memory \naccesses in order to meet the external data width.\n•\nAHB transaction size is smaller than the memory size\nAsynchronous transfers may or not be consistent depending on the type of external \ndevice.\n–\nAsynchronous accesses to devices that have the byte select feature (SRAM, \nROM, PSRAM).\na) FSMC allows write transactions accessing the right data through its byte lanes \nNBL[1:0]\nb) Read transactions are allowed. All memory bytes are read and the useless \nones are discarded. The NBL[1:0] are kept low during read transactions. \n–\nAsynchronous accesses to devices that do not have the byte select feature (NOR \nand NAND Flash 16-bit).\nThis situation occurs when a byte access is requested to a 16-bit wide flash \nmemory. Clearly, the device cannot be accessed in byte mode (only 16-bit words \ncan be read from/written to the flash memory) therefore:\na) \nWrite transactions are not allowed\nb) \nRead transactions are allowed. All memory bytes are read and the useless ones \nare discarded. The NBL[1:0] are set to 0 during read transactions.\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1550/1757\nRM0090 Rev 21\nConfiguration registers\nThe FSMC can be configured using a register set. See Section 36.5.6, for a detailed \ndescription of the NOR flash/PSRAM control registers. See Section 36.6.8, for a detailed \ndescription of the NAND Flash/PC Card registers.\n36.4 \nExternal device address mapping\nFrom the FSMC point of view, the external memory is divided into 4 fixed-size banks of \n256 Mbytes each (Refer to Figure 435):\n•\nBank 1 used to address up to four NOR flash or PSRAM memory devices. This bank is \nsplit into 4 NOR/PSRAM subbanks with four dedicated chip selects, as follows:\n–\nBank 1 - NOR/PSRAM 1\n–\nBank 1 - NOR/PSRAM 2\n–\nBank 1 - NOR/PSRAM 3\n–\nBank 1 - NOR/PSRAM 4\n•\nBanks 2 and 3 used to address NAND Flash devices (1 device per bank)\n•\nBank 4 used to address a PC Card device\nFor each bank the type of memory to be used is user-defined in the Configuration register.\nFigure 435. FSMC memory banks\n36.4.1 \nNOR/PSRAM address mapping\nHADDR[27:26] bits are used to select one of the four memory banks as shown in Table 217.\nBank 1\nNAND Flash\nNOR / PSRAM\nSupported memory type\nBanks\n4 × 64 MB\n6000 0000h\n6FFF FFFFh\nAddress\n7000 0000h\n7FFF FFFFh\n8000 0000h\n8FFF FFFFh\n9000 0000h\n9FFF FFFFh\nBank 2\n4 × 64 MB\nBank 3\n4 × 64 MB\nBank 4\n4 × 64 MB\nPC Card\nai14719\n\n\n<>\n\nRM0090 Rev 21\n1551/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \nHADDR[25:0] contain the external memory address. Since HADDR is a byte address \nwhereas the memory is addressed in words, the address actually issued to the memory \nvaries according to the memory data width, as shown in the following table.\n \nWrap support for NOR flash/PSRAM\nWrap burst mode for synchronous memories is not supported. The memories must be \nconfigured in linear burst mode of undefined length.\n36.4.2 \nNAND/PC Card address mapping\nIn this case, three banks are available, each of them divided into memory spaces as \nindicated in Table 219.\n \nTable 217. NOR/PSRAM bank selection\nHADDR[27:26](1)\n1.\nHADDR are internal AHB address lines that are translated to external memory.\nSelected bank\n00 \nBank 1 - NOR/PSRAM 1\n01 \nBank 1 - NOR/PSRAM 2\n10 \nBank 1 - NOR/PSRAM 3\n11 \nBank 1 - NOR/PSRAM 4\nTable 218. External memory address\nMemory width(1)\n1.\nIn case of a 16-bit external memory width, the FSMC internally uses HADDR[25:1] to generate the address \nfor external memory FSMC_A[24:0].\nWhatever the external memory width (16-bit or 8-bit), FSMC_A[0] should be connected to external memory \naddress A[0].\nData address issued to the memory\nMaximum memory capacity (bits) \n8-bit \nHADDR[25:0] \n64 Mbyte x 8 = 512 Mbit \n16-bit\nHADDR[25:1] >> 1 \n64 Mbyte/2 x 16 = 512 Mbit \nTable 219. Memory mapping and timing registers\nStart address\nEnd address\nFSMC Bank\nMemory space\nTiming register\n0x9C00 0000\n0x9FFF FFFF\nBank 4 - PC card\nI/O\nFSMC_PIO4 (0xB0)\n0x9800 0000\n0x9BFF FFFF\nAttribute\n FSMC_PATT4 (0xAC)\n0x9000 0000\n0x93FF FFFF\nCommon\n FSMC_PMEM4 (0xA8)\n0x8800 0000\n0x8BFF FFFF\nBank 3 - NAND Flash\nAttribute\n FSMC_PATT3 (0x8C)\n0x8000 0000\n0x83FF FFFF\nCommon\n FSMC_PMEM3 (0x88)\n0x7800 0000\n0x7BFF FFFF\nBank 2- NAND Flash\nAttribute\nFSMC_PATT2 (0x6C)\n0x7000 0000\n0x73FF FFFF\nCommon\n FSMC_PMEM2 (0x68)\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1552/1757\nRM0090 Rev 21\nFor NAND Flash memory, the common and attribute memory spaces are subdivided into \nthree sections (see in Table 220 below) located in the lower 256 Kbytes:\n•\nData section (first 64 Kbytes in the common/attribute memory space)\n•\nCommand section (second 64 Kbytes in the common / attribute memory space)\n•\nAddress section (next 128 Kbytes in the common / attribute memory space)\n \nThe application software uses the 3 sections to access the NAND Flash memory:\n•\nTo send a command to NAND Flash memory: the software must write the command \nvalue to any memory location in the command section.\n•\nTo specify the NAND Flash address that must be read or written: the software \nmust write the address value to any memory location in the address section. Since an \naddress can be 4 or 5 bytes long (depending on the actual memory size), several \nconsecutive writes to the address section are needed to specify the full address.\n•\nTo read or write data: the software reads or writes the data value from or to any \nmemory location in the data section.\nSince the NAND Flash memory automatically increments addresses, there is no need to \nincrement the address of the data section to access consecutive memory locations.\n36.5 \nNOR flash/PSRAM controller\nThe FSMC generates the appropriate signal timings to drive the following types of \nmemories:\n•\nAsynchronous SRAM and ROM\n–\n8-bit\n–\n16-bit\n–\n32-bit\n•\nPSRAM (Cellular RAM)\n–\nAsynchronous mode\n–\nBurst mode for synchronous accesses\n–\nMultiplexed or nonmultiplexed\n•\nNOR flash\n–\nAsynchronous mode\n–\nBurst mode for synchronous accesses\n–\nMultiplexed or nonmultiplexed\nThe FSMC outputs a unique chip select signal NE[4:1] per bank. All the other signals \n(addresses, data and control) are shared.\nTable 220. NAND bank selections\nSection name\nHADDR[17:16]\nAddress range\nAddress section \n1X \n0x020000-0x03FFFF \nCommand section \n01 \n0x010000-0x01FFFF \nData section \n00 \n0x000000-0x0FFFF \n\n\n<>\n\nRM0090 Rev 21\n1553/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nFor synchronous accesses, the FSMC issues the clock (CLK) to the selected external \ndevice only during the read/write transactions. This clock is a submultiple of the HCLK clock. \nThe size of each bank is fixed and equal to 64 Mbytes.\nEach bank is configured by means of dedicated registers (see Section 36.5.6).\nThe programmable memory parameters include access timings (see Table 221) and support \nfor wait management (for PSRAM and NOR flash accessed in burst mode).\n \n36.5.1 \nExternal memory interface signals\nTable 222, Table 223 and Table 224 list the signals that are typically used to interface NOR \nflash, SRAM and PSRAM.\nNote:\nPrefix “N”. specifies the associated signal as active low.\nNOR flash, nonmultiplexed I/Os\n \nTable 221. Programmable NOR/PSRAM access parameters\nParameter \nFunction \nAccess mode \nUnit \nMin. \nMax. \nAddress \nsetup\nDuration of the address \nsetup phase \nAsynchronous\nAHB clock cycle \n(HCLK) \n0\n15\nAddress hold\nDuration of the address hold \nphase \nAsynchronous, \nmuxed I/Os \nAHB clock cycle \n(HCLK) \n1\n15\nData setup\nDuration of the data setup \nphase \nAsynchronous\nAHB clock cycle \n(HCLK) \n1\n256 \nBus turn\nDuration of the bus \nturnaround phase \nAsynchronous and \nsynchronous \nread/write\nAHB clock cycle \n(HCLK) \n0\n15\nClock divide \nratio\nNumber of AHB clock cycles \n(HCLK) to build one memory \nclock cycle (CLK) \nSynchronous\nAHB clock cycle \n(HCLK) \n2\n16 \nData latency\nNumber of clock cycles to \nissue to the memory before \nthe first data of the burst \nSynchronous\nMemory clock \ncycle (CLK) \n2\n17 \nTable 222. Nonmultiplexed I/O NOR flash\nFSMC signal name\nI/O\nFunction\nCLK \nO \nClock (for synchronous access) \nA[25:0] \nO \nAddress bus \nD[15:0] \nI/O \nBidirectional data bus \nNE[x]\nO \nChip select, x = 1..4\nNOE\nO \nOutput enable \nNWE\nO \nWrite enable \nNL(=NADV)\nO \nLatch enable (this signal is called address \nvalid, NADV, by some NOR flash devices) \nNWAIT\nI \nNOR flash wait input signal to the FSMC \n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1554/1757\nRM0090 Rev 21\nNOR flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 \naddress lines).\nNOR flash, multiplexed I/Os\n \nNOR-flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 \naddress lines).\nPSRAM/SRAM, nonmultiplexed I/Os\n \nPSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 \naddress lines).\nPSRAM, multiplexed I/Os\nTable 223. Multiplexed I/O NOR flash\nFSMC signal name \nI/O\nFunction \nCLK \nO \nClock (for synchronous access) \nA[25:16] \nO \nAddress bus \nAD[15:0] \nI/O \n16-bit multiplexed, bidirectional address/data bus\nNE[x]\nO \nChip select, x = 1..4\nNOE\nO \nOutput enable \nNWE\nO \nWrite enable \nNL(=NADV)\nO \nLatch enable (this signal is called address valid, NADV, by some NOR \nflash devices) \nNWAIT\nI \nNOR flash wait input signal to the FSMC \nTable 224. Nonmultiplexed I/Os PSRAM/SRAM\nFSMC signal name\nI/O \nFunction \nCLK \nO \nClock (only for PSRAM synchronous access) \nA[25:0] \nO \nAddress bus \nD[15:0] \nI/O \nData bidirectional bus \nNE[x]\nO \nChip select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))\nNOE\nO \nOutput enable \nNWE\nO \nWrite enable \nNL(= NADV)\nO \nAddress valid only for PSRAM input (memory signal name: NADV) \nNWAIT\nI \nPSRAM wait input signal to the FSMC \nNBL[1] \nO \nUpper byte enable (memory signal name: NUB) \nNBL[0] \nO \nLowed byte enable (memory signal name: NLB) \n\n\n<>\n\nRM0090 Rev 21\n1555/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \nPSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 \naddress lines).\n36.5.2 \nSupported memories and transactions\nTable 226 below displays an example of the supported devices, access modes and \ntransactions when the memory data bus is 16-bit for NOR, PSRAM and SRAM. \nTransactions not allowed (or not supported) by the FSMC in this example appear in gray.\n \nTable 225. Multiplexed I/O PSRAM\nFSMC signal name\nI/O \nFunction \nCLK \nO \nClock (for synchronous access) \nA[25:16] \nO \nAddress bus \nAD[15:0] \nI/O \n16-bit multiplexed, bidirectional address/data bus\nNE[x]\nO \nChip select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))\nNOE\nO \nOutput enable \nNWE\nO \nWrite enable \nNL(= NADV)\nO \nAddress valid PSRAM input (memory signal name: NADV) \nNWAIT\nI \nPSRAM wait input signal to the FSMC \nNBL[1] \nO \nUpper byte enable (memory signal name: NUB) \nNBL[0] \nO \nLowed byte enable (memory signal name: NLB) \nTable 226. NOR flash/PSRAM controller: example of supported memories and transactions\nDevice\nMode\nR/W\nAHB \ndata \nsize\nMemory \ndata size\nAllowed/\nnot \nallowed\nComments\nNOR flash\n(muxed I/Os and \nnonmuxed I/Os) \nAsynchronous\nR \n8 \n16 \nY \n-\nAsynchronous \nW \n8 \n16 \nN \n-\nAsynchronous\nR \n16 \n16 \nY \n-\nAsynchronous\nW \n16 \n16 \nY \n-\nAsynchronous \nR \n32 \n16 \nY \nSplit into two FSMC accesses \nAsynchronous \nW \n32 \n16 \nY \nSplit into two FSMC accesses \nAsynchronous page\nR \n-\n16 \nN \nMode is not supported \nSynchronous \nR \n8 \n16 \nN \n-\nSynchronous \nR \n16 \n16 \nY \n-\nSynchronous \nR \n32 \n16 \nY \n-\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1556/1757\nRM0090 Rev 21\n36.5.3 \nGeneral timing rules\nSignals synchronization\n•\nAll controller output signals change on the rising edge of the internal clock (HCLK)\n•\nIn synchronous mode (read or write), all output signals change on the rising edge of \nHCLK. Whatever the CLKDIV value, all outputs change as follows:\n–\nNOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the \nfalling edge of FSMC_CLK clock.\n–\nNOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising \nedge of FSMC_CLK clock.\nPSRAM \n(multiplexed and \nnonmultiplexed \nI/Os)\nAsynchronous\nR \n8 \n16 \nY \n-\nAsynchronous \nW \n8 \n16 \nY \nUse of byte lanes NBL[1:0] \nAsynchronous\nR \n16 \n16 \nY \n-\nAsynchronous\nW \n16 \n16 \nY \n-\nAsynchronous \nR \n32 \n16 \nY \nSplit into two FSMC accesses \nAsynchronous \nW \n32 \n16 \nY \nSplit into two FSMC accesses \nAsynchronous page\nR \n-\n16 \nN \nMode is not supported \nSynchronous \nR \n8 \n16 \nN \n-\nSynchronous \nR \n16 \n16 \nY \n-\nSynchronous \nR \n32 \n16 \nY \n-\nSynchronous\nW\n8\n16\nY\nUse of byte lanes NBL[1:0]\nSynchronous\nW\n16 / 32\n16\nY\n-\nSRAM and ROM\nAsynchronous \nR \n8 / 16 \n16\nY \n-\nAsynchronous \nW \n8 / 16 \n16\nY \nUse of byte lanes NBL[1:0]\nAsynchronous \nR \n32 \n16\nY \nSplit into two FSMC accesses \nAsynchronous \nW \n32 \n16\nY \nSplit into two FSMC accesses. \nUse of byte lanes NBL[1:0]\nTable 226. NOR flash/PSRAM controller: example of supported memories and transactions \nDevice\nMode\nR/W\nAHB \ndata \nsize\nMemory \ndata size\nAllowed/\nnot \nallowed\nComments\n\n\n<>\n\nRM0090 Rev 21\n1557/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n36.5.4 \nNOR flash/PSRAM controller asynchronous transactions\nAsynchronous static memories (NOR flash memory, PSRAM, SRAM)\n•\nSignals are synchronized by the internal clock HCLK. This clock is not issued to the \nmemory\n•\nThe FSMC always samples the data before de-asserting the NOE signals. This \nguarantees that the memory data-hold timing constraint is met (chip enable high to \ndata transition, usually 0 ns min.)\n•\nIf the extended mode is enabled (EXTMOD bit is set in the FSMC_BCRx register), up \nto four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and \nD modes for read and write operations. For example, read operation can be performed \nin mode A and write in mode B.\n•\nIf the extended mode is disabled (EXTMOD bit is reset in the FSMC_BCRx register), \nthe FSMC can operate in Mode1 or Mode2 as follows:\n–\nMode 1 is the default mode when SRAM/PSRAM memory type is selected \n(MTYP[0:1] = 0x0 or 0x01 in the FSMC_BCRx register)\n–\nMode 2 is the default mode when NOR memory type is selected (MTYP[0:1] = \n0x10 in the FSMC_BCRx register).\nMode 1 - SRAM/PSRAM (CRAM)\nThe next figures show the read and write transactions for the supported modes followed by \nthe required configuration of FSMC _BCRx, and FSMC_BTRx/FSMC_BWTRx registers. \nFigure 436. Mode1 read accesses\n1.\nNBL[1:0] are driven low during read access.\nA[25:0]\nNOE\nADDSET\nDATAST \nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNBL[1:0]\ndata driven\nby memory\nai15557\nHigh\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1558/1757\nRM0090 Rev 21\nFigure 437. Mode1 write accesses\nThe one HCLK cycle at the end of the write transaction helps guarantee the address and \ndata hold time after the NWE rising edge. Due to the presence of this one HCLK cycle, the \nDATAST value must be greater than zero (DATAST > 0).\n \nTable 227. FSMC_BCRx bit fields\nBit number\nBit name\nValue to set\n31-20\nReserved\n0x000\n19\nCBURSTRW\n0x0 (no effect on asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect on asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at 0.\n14\nEXTMOD\n0x0\n13\nWAITEN\n0x0 (no effect on asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0\n7 \nReserved\n0x1\n6 \nFACCEN\nDon’t care\n5-4 \nMWID\nAs needed\n3-2 \nMTYP[0:1]\nAs needed, exclude 0x2 (NOR flash)\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNBL[1:0]\ndata driven by FSMC\nai15558\n1HCLK\n\n\n<>\n\nRM0090 Rev 21\n1559/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \nMode A - SRAM/PSRAM (CRAM) OE toggling\nFigure 438. ModeA read accesses\n1.\nNBL[1:0] are driven low during read access.\n1 \nMUXE\n0x0\n0 \nMBKEN \n0x1\nTable 228. FSMC_BTRx bit fields\nBit number\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\nDon’t care\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST+1 HCLK cycles for \nwrite accesses, DATAST HCLK cycles for read accesses). \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles).\nMinimum value for ADDSET is 0.\nTable 227. FSMC_BCRx bit fields (continued)\nBit number\nBit name\nValue to set\nA[25:0]\nNOE\nADDSET \nDATAST\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNBL[1:0]\ndata driven\nby memory\nai15559\nHigh\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1560/1757\nRM0090 Rev 21\nFigure 439. ModeA write accesses\nThe differences compared with mode1 are the toggling of NOE and the independent read \nand write timings.\n \nTable 229. FSMC_BCRx bit fields\nBit \nnumber\nBit name \nValue to set\n31-20\nReserved\n0x000\n19\nCBURSTRW\n0x0 (no effect on asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect on asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at \n0.\n14 \nEXTMOD\n0x1\n13\nWAITEN\n0x0 (no effect on asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0\n7 \nReserved\n0x1\n6 \nFACCEN\nDon’t care\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[0:1]\nAs needed, exclude 0x2 (NOR flash)\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNBL[1:0]\ndata driven by FSMC\nai15560\n1HCLK\n\n\n<>\n\nRM0090 Rev 21\n1561/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \n \n1 \nMUXEN\n0x0\n0 \nMBKEN\n0x1\nTable 230. FSMC_BTRx bit fields\nBit \nnumber\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x0\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for \nread accesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for read \naccesses.\nMinimum value for ADDSET is 0.\nTable 231. FSMC_BWTRx bit fields\nBit \nnumber\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x0\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST+1 HCLK cycles for \nwrite accesses, \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for write \naccesses.\nMinimum value for ADDSET is 0.\nTable 229. FSMC_BCRx bit fields (continued)\nBit \nnumber\nBit name \nValue to set\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1562/1757\nRM0090 Rev 21\nMode 2/B - NOR flash\nFigure 440. Mode2 and mode B read accesses\nFigure 441. Mode2 write accesses\nA[25:0]\nNOE\nADDSET \nDATAST\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven\nby memory\nai15561\nHigh\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven by FSMC\nai15562\n1HCLK\n\n\n<>\n\nRM0090 Rev 21\n1563/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nFigure 442. Mode B write accesses \nThe differences with mode1 are the toggling of NWE and the independent read and write \ntimings when extended mode is set (Mode B).\n \nTable 232. FSMC_BCRx bit fields\nBit \nnumber\nBit name \nValue to set \n31-20\nReserved\n0x000\n19\nCBURSTRW\n0x0 (no effect on asynchronous mode)\n18:16\nReserved\n0x0 (no effect on asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at \n0.\n14 \nEXTMOD\n0x1 for mode B, 0x0 for mode 2\n13\nWAITEN\n0x0 (no effect on asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0 \n7 \nReserved\n0x1\n6 \nFACCEN\n0x1\n5-4 \nMWID \nAs needed\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven by FSMC\nai15563\n1HCLK\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1564/1757\nRM0090 Rev 21\n \n \nNote:\nThe FSMC_BWTRx register is valid only if extended mode is set (mode B), otherwise all its \ncontent is don’t care.\n3-2 \nMTYP[0:1]\n0x2 (NOR flash memory)\n1 \nMUXEN\n0x0 \n0 \nMBKEN\n0x1 \nTable 233. FSMC_BTRx bit fields\nBit \nnumber\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x1\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for \nread accesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for read \naccesses.\nMinimum value for ADDSET is 0.\nTable 234. FSMC_BWTRx bit fields\nBit \nnumber\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x1\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST+1 HCLK cycles for \nwrite accesses, \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for write \naccesses.\nMinimum value for ADDSET is 0.\nTable 232. FSMC_BCRx bit fields (continued)\nBit \nnumber\nBit name \nValue to set \n\n\n<>\n\nRM0090 Rev 21\n1565/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nMode C - NOR flash - OE toggling\nFigure 443. Mode C read accesses \nFigure 444. Mode C write accesses \nThe differences compared with mode1 are the toggling of NOE and the independent read \nand write timings.\nA[25:0]\nNOE\nADDSET \nDATAST\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven\nby memory\nai15564\nHigh\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven by FSMC\nai15565\n1HCLK\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1566/1757\nRM0090 Rev 21\n \n \nTable 235. FSMC_BCRx bit fields\nBit No.\nBit name\nValue to set\n31-20\nReserved\n0x000\n19\nCBURSTRW\n0x0 (no effect on asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect on asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep \nat 0.\n14 \nEXTMOD\n0x1\n13\nWAITEN\n0x0 (no effect on asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0 \n7 \nReserved\n0x1\n6 \nFACCEN\n0x1\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[0:1]\n0x2 (NOR flash memory)\n1 \nMUXEN\n0x0\n0 \nMBKEN\n0x1\nTable 236. FSMC_BTRx bit fields\nBit \nnumber\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x2\n27-24\nDATLAT\n0x0\n23-20\nCLKDIV\n0x0\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for \nread accesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for read \naccesses.\nMinimum value for ADDSET is 0.\n\n\n<>\n\nRM0090 Rev 21\n1567/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \n \nMode D - asynchronous access with extended address\nFigure 445. Mode D read accesses\nTable 237. FSMC_BWTRx bit fields\nBit \nnumber\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x2\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST+1 HCLK cycles for \nwrite accesses, \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for write \naccesses.\nMinimum value for ADDSET is 0.\nA[25:0]\nNOE\nADDSET \nDATAST\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven\nby memory\nai15566\nHigh\nADDHLD\nHCLK cycles\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1568/1757\nRM0090 Rev 21\nFigure 446. Mode D write accesses\nThe differences with mode1 are the toggling of NOE that goes on toggling after NADV \nchanges and the independent read and write timings.\n \nTable 238. FSMC_BCRx bit fields\nBit No.\nBit name \nValue to set \n31-20\nReserved\n0x000\n19\nCBURSTRW\n0x0 (no effect on asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect on asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep \nat 0.\n14 \nEXTMOD\n0x1\n13\nWAITEN\n0x0 (no effect on asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0 \n7 \nReserved\n0x1\n6 \nFACCEN\nSet according to memory support\n5-4 \nMWID\nAs needed\n\n\n<>\n\nRM0090 Rev 21\n1569/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \n \n3-2 \nMTYP[0:1]\nAs needed\n1 \nMUXEN\n0x0 \n0 \nMBKEN\n0x1 \nTable 239. FSMC_BTRx bit fields\nBit No.\nBit name\nValue to set \n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x3\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for \nread accesses. \n7-4\nADDHLD\nDuration of the middle phase of the read access (ADDHLD HCLK \ncycles) \n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for read \naccesses. Minimum value for ADDSET is 0.\nTable 240. FSMC_BWTRx bit fields\nBit No.\nBit name\nValue to set \n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x3\n27-24\nDATLAT\n0x0\n23-20\nCLKDIV\n0x0\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST+1 HCLK cycles) for \nwrite accesses\n7-4\nADDHLD\nDuration of the middle phase of the write access (ADDHLD HCLK \ncycles) \n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET+1 HCLK cycles) for \nwrite accesses. Minimum value for ADDSET is 0.\nTable 238. FSMC_BCRx bit fields (continued)\nBit No.\nBit name \nValue to set \n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1570/1757\nRM0090 Rev 21\nMuxed mode - multiplexed asynchronous access to NOR flash memory\nFigure 447. Multiplexed read accesses\nFigure 448. Multiplexed write accesses\nThe difference with mode D is the drive of the lower address byte(s) on the databus.\nA[25:16]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nAD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven by FSMC\nai15569\n1HCLK\nADDHLD\nHCLK cycles\nLower address\n\n\n<>\n\nRM0090 Rev 21\n1571/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \n \nWAIT management in asynchronous accesses\nIf the asynchronous memory asserts a WAIT signal to indicate that it is not yet ready to \naccept or to provide data, the ASYNCWAIT bit has to be set in FSMC_BCRx register.\nTable 241. FSMC_BCRx bit fields\nBit No.\nBit name\nValue to set\n31-21\nReserved\n0x000\n19\nCBURSTRW\n0x0 (no effect on asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect on asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at \n0.\n14 \nEXTMOD\n0x0\n13\nWAITEN\n0x0 (no effect on asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care \n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0 \n7 \nReserved\n0x1\n6 \nFACCEN\n0x1\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[0:1] \n0x2 (NOR flash memory)\n1 \nMUXEN\n0x1\n0 \nMBKEN\n0x1 \nTable 242. FSMC_BTRx bit fields\nBit No.\nBit name \nValue to set \n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x0\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles for \nread accesses and DATAST+1 HCLK cycles for write accesses). \n7-4\nADDHLD\nDuration of the middle phase of the access (ADDHLD HCLK cycles).\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles). \nMinimum value for ADDSET is 1.\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1572/1757\nRM0090 Rev 21\nIf the WAIT signal is active (high or low depending on the WAITPOL bit), the second access \nphase (Data setup phase) programmed by the DATAST bits, is extended until WAIT \nbecomes inactive. Unlike the data setup phase, the first access phases (Address setup and \nAddress hold phases), programmed by the ADDSET[3:0] and ADDHLD bits, are not WAIT \nsensitive and so they are not prolonged.\nThe data setup phase (DATAST in the FSMC_BTRx register) must be programmed so that \nWAIT can be detected 4 HCLK cycles before the end of memory transaction. The following \ncases must be considered:\n1.\nDATAST in FSMC_BTRx register) Memory asserts the WAIT signal aligned to \nNOE/NWE which toggles: \n2. \nMemory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):\nif \nthen \notherwise \nwhere max_wait_assertion_time is the maximum time taken by the memory to assert \nthe WAIT signal once NEx/NOE/NWE is low.\nFigure 449 and Figure 450 show the number of HCLK clock cycles that are added to the \nmemory access after WAIT is released by the asynchronous memory (independently of the \nabove cases).\nDATAST\n4\nHCLK\n×\n(\n)\nmax_wait_assertion_time\n+\n≥\nmax_wait_assertion_time\naddress_phase\nhold_phase\n+\n>\nDATAST\n4\nHCLK\n×\n(\n)\nmax_wait_assertion_time\naddress_phase\n–\nhold_phase\n–\n(\n)\n+\n≥\nDATAST\n4\nHCLK\n×\n≥\n\n\n<>\n\nRM0090 Rev 21\n1573/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nFigure 449. Asynchronous wait during a read access \n1.\nNWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register. \nFigure 450. Asynchronous wait during a write access \n1.\nNWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register. \nA[25:0]\nNOE\n4HCLK \nMemory transaction\nNWAIT\nD[15:0]\nNEx\ndata driven \nby memory\nai18471b\naddress phase\ndon’t care\ndata setup phase\ndon’t care\nA[25:0]\nNWE\nMemory transaction\nNWAIT\nD[15:0]\nNEx\ndata driven by FSMC\nai15797c\n3HCLK \naddress phase\ndata setup phase\n1HCLK \ndon’t care\ndon’t care\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1574/1757\nRM0090 Rev 21\n36.5.5 \nSynchronous transactions\nThe memory clock, CLK, is a submultiple of HCLK according to the value of parameter \nCLKDIV.\nNOR flash memories specify a minimum time from NADV assertion to CLK high. To meet \nthis constraint, the FSMC does not issue the clock to the memory during the first internal \nclock cycle of the synchronous access (before NADV assertion). This guarantees that the \nrising edge of the memory clock occurs in the middle of the NADV low pulse.\nData latency versus NOR flash latency\nThe data latency is the number of cycles to wait before sampling the data. The DATLAT \nvalue must be consistent with the latency value specified in the NOR flash configuration \nregister. The FSMC does not include the clock cycle when NADV is low in the data latency \ncount.\nCaution:\nSome NOR flash memories include the NADV Low cycle in the data latency count, so the \nexact relation between the latency and the FMSC DATLAT parameter can be either of:\n•\nNOR flash latency = (DATLAT + 2) CLK clock cycles\n•\nNOR flash latency = (DATLAT + 3) CLK clock cycles\nSome recent memories assert NWAIT during the latency phase. In such cases DATLAT can \nbe set to its minimum value. As a result, the FSMC samples the data and waits long enough \nto evaluate if the data are valid. Thus the FSMC detects when the memory exits latency and \nreal data are taken.\nOther memories do not assert NWAIT during latency. In this case the latency must be set \ncorrectly for both the FSMC and the memory, otherwise invalid data are mistaken for good \ndata, or valid data are lost in the initial phase of the memory access.\nSingle-burst transfer\nWhen the selected bank is configured in burst mode for synchronous accesses, if for \nexample an AHB single-burst transaction is requested on 16-bit memories, the FSMC \nperforms a burst transaction of length 1 (if the AHB transfer is 16-bit), or length 2 (if the AHB \ntransfer is 32-bit) and de-assert the chip select signal when the last data is strobed.\nClearly, such a transfer is not the most efficient in terms of cycles (compared to an \nasynchronous read). Nevertheless, a random asynchronous access would first require to re-\nprogram the memory access mode, which would altogether last longer.\nCross boundary page for Cellular RAM 1.5\nCellular RAM 1.5 does not allow burst access to cross the page boundary. The FSMC \ncontroller allows to split automatically the burst access when the memory page size is \nreached by configuring the CPSIZE bits in the FSMC_BCR1 register following the memory \npage size.\nWait management\nFor synchronous NOR flash memories, NWAIT is evaluated after the programmed latency \nperiod, (DATLAT+2) CLK clock cycles.\nIf NWAIT is sensed active (low level when WAITPOL = 0, high level when WAITPOL = 1), \nwait states are inserted until NWAIT is sensed inactive (high level when WAITPOL = 0, low \nlevel when WAITPOL = 1).\n\n\n<>\n\nRM0090 Rev 21\n1575/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nWhen NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1) \nor on the next clock edge (bit WAITCFG = 0).\nDuring wait-state insertion via the NWAIT signal, the controller continues to send clock \npulses to the memory, keeping the chip select and output enable signals valid, and does not \nconsider the data valid.\nThere are two timing configurations for the NOR flash NWAIT signal in burst mode:\n•\nFlash memory asserts the NWAIT signal one data cycle before the wait state (default \nafter reset)\n•\nFlash memory asserts the NWAIT signal during the wait state\nThese two NOR flash wait state configurations are supported by the FSMC, individually for \neach chip select, thanks to the WAITCFG bit in the FSMC_BCRx registers (x = 0..3).\nFigure 451. Wait configurations\naaddr[15:0]\ndata\ndata\naddr[25:16]\nMemory transaction = burst of 4 half words\nHCLK\nCLK\nA[25:16]\nNADV\nNWAIT\n(WAITCFG = 1)\nA/D[15:0]\ninserted wait state\ndata\nNWAIT\n(WAITCFG = 0)\nai15798b\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1576/1757\nRM0090 Rev 21\nFigure 452. Synchronous multiplexed read mode - NOR, PSRAM (CRAM)\n1.\nByte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, \nthey are held low. \n2.\nNWAIT polarity is set to 0.\n \nTable 243. FSMC_BCRx bit fields\nBit No.\nBit name\nValue to set\n31-20\nReserved\n0x000\n19\nCBURSTRW\nNo effect on synchronous read\n18-16\nCPSIZE\nAs needed (0x1 for CRAM 1.5)\n15\nASCYCWAIT\n0x0\n14 \nEXTMOD\n0x0\n13\nWAITEN\nSet to 1 if the memory supports this feature, otherwise keep at 0.\n12\nWREN\nno effect on synchronous read\n11\nWAITCFG\nto be set according to memory\n10\nWRAPMOD\n0x0\n9 \nWAITPOL\nto be set according to memory\n8 \nBURSTEN\n0x1\n7 \nReserved\n0x1\n6 \nFACCEN\nSet according to memory support (NOR flash memory)\n5-4 \nMWID \nAs needed\nAddr[15:0]\ndata\ndata\naddr[25:16]\nMemory transaction = burst of 4 half words\nHCLK\nCLK\nA[25:16]\nNEx\nNOE\nNWE\nHigh\nNADV\nNWAIT\n(WAITCFG=\n0)\nA/D[15:0]\n1 clock\ncycle\n1 clock\ncycle\n(DATLAT + 2)\ninserted wait state\nData strobes\nai17723f\nCLK cycles\ndata\ndata\nData strobes\n\n\n<>\n\nRM0090 Rev 21\n1577/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \n3-2 \nMTYP[0:1]\n0x1 or 0x2\n1 \nMUXEN\nAs needed\n0 \nMBKEN\n0x1 \nTable 244. FSMC_BTRx bit fields\nBit No.\nBit name\nValue to set\n31:30\nReserved\n0x0\n29:28\nACCMOD\n0x0\n27-24\nDATLAT\nData latency\n23-20\nCLKDIV\n0x0 to get CLK = HCLK (not supported)\n0x1 to get CLK = 2 × HCLK\n..\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK)\n15-8\nDATAST\nDon’t care\n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDon’t care\nTable 243. FSMC_BCRx bit fields (continued)\nBit No.\nBit name\nValue to set\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1578/1757\nRM0090 Rev 21\nFigure 453. Synchronous multiplexed write mode - PSRAM (CRAM)\n1.\nMemory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.\n2.\nNWAIT polarity is set to 0.\n3.\nByte Lane (NBL) outputs are not shown, they are held low while NEx is active.\nAddr[15:0]\ndata\naddr[25:16]\nMemory transaction = burst of 2 half words\nHCLK\nCLK\nA[25:16]\nNEx\nNOE\nNWE\nHi-Z\nNADV\nNWAIT\n(WAITCFG = 0)\nA/D[15:0]\n1 clock 1 clock\n(DATLAT + 2)\ninserted wait state\nai14731f\n CLK cycles\ndata\nTable 245. FSMC_BCRx bit fields\nBit No.\nBit name\nValue to set\n31-20\nReserved\n0x000\n19\nCBURSTRW\n0x1\n18-16\nCPSIZE\nAs needed (0x1 for CRAM 1.5)\n15\nASCYCWAIT\n0x0\n14 \nEXTMOD\n0x0\n13\nWAITEN\nSet to 1 if the memory supports this feature, otherwise keep at 0.\n12\nWREN\n0x1\n11\nWAITCFG\n0x0\n10\nWRAPMOD\n0x0\n\n\n<>\n\nRM0090 Rev 21\n1579/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \n9 \nWAITPOL\nto be set according to memory\n8 \nBURSTEN\nno effect on synchronous write\n7 \nReserved\n0x1\n6 \nFACCEN\nSet according to memory support\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[0:1]\n0x1\n1 \nMUXEN\nAs needed\n0 \nMBKEN\n0x1 \nTable 246. FSMC_BTRx bit fields\nBit No.\nBit name\nValue to set\n31:30\nReserved\n0x0\n29:28\nACCMOD\n0x0\n27-24\nDATLAT\nData latency\n23-20\nCLKDIV\n0x0 to get CLK = HCLK (not supported)\n0x1 to get CLK = 2 × HCLK\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDon’t care\n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDon’t care\nTable 245. FSMC_BCRx bit fields (continued)\nBit No.\nBit name\nValue to set\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1580/1757\nRM0090 Rev 21\n36.5.6 \nNOR/PSRAM control registers\nThe NOR/PSRAM control registers have to be accessed by words (32 bits).\nSRAM/NOR-flash chip-select control registers 1..4 (FSMC_BCR1..4)\nAddress offset: 0xA000 0000 + 8 * (x – 1), x = 1...4\nReset value: 0x0000 30DB for Bank1 and 0x0000 30D2 for Bank 2 to 4\nThis register contains the control information of each memory bank, used for SRAMs, \nPSRAM and NOR flash memories.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCBURSTRW\nCPSIZE[2:0]\nASCYCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[1:0]\nMUXEN\nMBKEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31: 20 Reserved, must be kept at reset value.\nBit 19 CBURSTRW: Write burst enable.\nFor Cellular RAM (PSRAM) memories, this bit enables the synchronous burst protocol \nduring write operations. The enable bit for synchronous read accesses is the BURSTEN \nbit in the FSMC_BCRx register.\n0: Write operations are always performed in asynchronous mode\n1: Write operations are performed in synchronous mode.\nBits 18: 16 CPSIZE[2:0]: CRAM page size.\nThese are used for Cellular RAM 1.5 which does not allow burst access to cross the \naddress boundaries between pages. When these bits are configured, the FSMC \ncontroller splits automatically the burst access when the memory page size is reached \n(refer to memory datasheet for page size).\n000: No burst split when crossing page boundary (default after reset)\n001: 128 bytes\n010: 256 bytes\n011: 512 bytes\n100: 1024 bytes\nOthers: reserved.\nBit 15 ASYNCWAIT: Wait signal during asynchronous transfers\nThis bit enables/disables the FSMC to use the wait signal even during an asynchronous \nprotocol.\n0: NWAIT signal is not taken into account when running an asynchronous protocol \n(default after reset)\n1: NWAIT signal is taken into account when running an asynchronous protocol\n\n\n<>\n\nRM0090 Rev 21\n1581/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nBit 14 EXTMOD: Extended mode enable.\nThis bit enables the FSMC to program the write timings for non-multiplexed \nasynchronous accesses inside the FSMC_BWTR register, thus resulting in different \ntimings for read and write operations.\n0: values inside FSMC_BWTR register are not taken into account (default after reset)\n1: values inside FSMC_BWTR register are taken into account\nNote: When the extended mode is disabled, the FSMC can operate in Mode1 or Mode2 \nas follows:\n–\nMode 1 is the default mode when the SRAM/PSRAM memory type is selected \n(MTYP [0:1]=0x0 or 0x01)\n–\nMode 2 is the default mode when the NOR memory type is selected \n(MTYP [0:1]= 0x10).\nBit 13 WAITEN: Wait enable bit.\nThis bit enables/disables wait-state insertion via the NWAIT signal when accessing the \nflash memory in synchronous mode.\n0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after \nthe programmed flash latency period)\n1: NWAIT signal is enabled (its level is taken into account after the programmed flash \nlatency period to insert wait states if asserted) (default after reset)\nBit 12 WREN: Write enable bit.\nThis bit indicates whether write operations are enabled/disabled in the bank by the \nFSMC:\n0: Write operations are disabled in the bank by the FSMC, an AHB error is reported,\n1: Write operations are enabled for the bank by the FSMC (default after reset).\nBit 11 WAITCFG: Wait timing configuration.\nThe NWAIT signal indicates whether the data from the memory are valid or if a wait state \nmust be inserted when accessing the flash memory in synchronous mode. This \nconfiguration bit determines if NWAIT is asserted by the memory one clock cycle before \nthe wait state or during the wait state:\n0: NWAIT signal is active one data cycle before wait state (default after reset),\n1: NWAIT signal is active during wait state (not used for PRAM).\nBit 10 WRAPMOD: Wrapped burst mode support.\nDefines whether the controller splits or not an AHB burst wrap access into two linear \naccesses. Valid only when accessing memories in burst mode\n0: Direct wrapped burst is not enabled (default after reset),\n1: Direct wrapped burst is enabled.\nNote: This bit has no effect as the CPU and DMA cannot generate wrapping burst \ntransfers.\nBit 9 WAITPOL: Wait signal polarity bit.\nDefines the polarity of the wait signal from memory. Valid only when accessing the \nmemory in burst mode:\n0: NWAIT active low (default after reset),\n1: NWAIT active high.\nBit 8 BURSTEN: Burst enable bit.\nThis bit enables/disables synchronous accesses during read operations. It is valid only \nfor synchronous memories operating in burst mode:\n0: Burst mode disabled (default after reset). Read accesses are performed in \nasynchronous mode. \n1: Burst mode enable. Read accesses are performed in synchronous mode. \n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1582/1757\nRM0090 Rev 21\nBit 7 Reserved, must be kept at reset value.\nBit 6 FACCEN: Flash access enable\nEnables NOR flash memory access operations.\n0: Corresponding NOR flash memory access is disabled\n1: Corresponding NOR flash memory access is enabled (default after reset)\nBits 5:4 MWID[1:0]: Memory databus width.\nDefines the external memory device width, valid for all type of memories.\n00: 8 bits,\n01: 16 bits (default after reset),\n10: reserved, do not use,\n11: reserved, do not use.\nBits 3:2 MTYP[1:0]: Memory type.\nDefines the type of external memory attached to the corresponding memory bank:\n00: SRAM (default after reset for Bank 2...4)\n01: PSRAM (CRAM)\n10: NOR flash/OneNAND flash (default after reset for Bank 1)\n11: reserved\nBit 1 MUXEN: Address/data multiplexing enable bit.\nWhen this bit is set, the address and data values are multiplexed on the databus, valid \nonly with NOR and PSRAM memories:\n0: Address/Data nonmultiplexed\n1: Address/Data multiplexed on databus (default after reset)\nBit 0 MBKEN: Memory bank enable bit.\nEnables the memory bank. After reset Bank1 is enabled, all others are disabled. \nAccessing a disabled bank causes an ERROR on AHB bus.\n0: Corresponding memory bank is disabled\n1: Corresponding memory bank is enabled\n\n\n<>\n\nRM0090 Rev 21\n1583/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nSRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4)\nAddress offset: 0xA000 0000 + 0x04 + 8 * (x – 1), x = 1..4\nReset value: 0x0FFF FFFF\nFSMC_BTRx bits are written by software to add a delay at the end of a read /write \ntransaction. This delay allows matching the minimum time between consecutive \ntransactions (tEHEL from NEx high to FSMC_NEx low) and the maximum time required by \nthe memory to free the data bus after a read access (tEHQZ).\nThis register contains the control information of each memory bank, used for SRAMs, \nPSRAM and NOR flash memories.If the EXTMOD bit is set in the FSMC_BCRx register, \nthen this register is partitioned for write and read access, that is, 2 registers are available: \none to configure read accesses (this register) and one to configure write accesses \n(FSMC_BWTRx registers).\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0]\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30\nReserved, must be kept at reset value.\nBits 29:28 ACCMOD[1:0]: Access mode\nSpecifies the asynchronous access modes as shown in the timing diagrams. These bits are \ntaken into account only when the EXTMOD bit in the FSMC_BCRx register is 1.\n00: access mode A\n01: access mode B\n10: access mode C\n11: access mode D\nBits 27:24 DATLAT[3:0]: Data latency for synchronous memory (see note below bit description table)\nFor synchronous accesses with read/write burst mode enabled (BURSTEN / CBURSTRW bits \nset), this field defines the number of memory clock cycles (+2) to issue to the memory before \nreading/writing the first data. This timing parameter is not expressed in HCLK periods, but in \nFSMC_CLK periods. For asynchronous accesses, this value is don't care. \n0000: Data latency of 2 CLK clock cycles for first burst access\n1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)\nBits 23:20 CLKDIV[3:0]: Clock divide ratio (for FSMC_CLK signal)\nDefines the period of FSMC_CLK clock output signal, expressed in number of HCLK cycles:\n0000: Reserved\n0001: FSMC_CLK period = 2 × HCLK periods\n0010: FSMC_CLK period = 3 × HCLK periods\n1111: FSMC_CLK period = 16 × HCLK periods (default value after reset) \nIn asynchronous NOR flash, SRAM or PSRAM accesses, this value is don’t care.\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1584/1757\nRM0090 Rev 21\nBits 19:16 BUSTURN[3:0]: Bus turnaround phase duration\nThese bits are written by software to add a delay at the end of a write-to-read (and read-to \nwrite) transaction. The programmed bus turnaround delay is inserted between an \nasynchronous read (muxed or D mode) or a write transaction and any other \nasynchronous/synchronous read or write to/from a static bank (for a read operation, the bank \ncan be the same or a different one; for a write operation, the bank can be different except in r \nmuxed or D mode).\nIn some cases, the bus turnaround delay is fixed, whatever the programmed BUSTURN \nvalues: \n– No bus turnaround delay is inserted between two consecutive asynchronous write transfers \nto the same static memory bank except in muxed and D mode.\n– A bus turnaround delay of 1 FSMC clock cycle is inserted between:\n–\nTwo consecutive asynchronous read transfers to the same static memory bank \nexcept for muxed and D modes. \n–\nAn asynchronous read to an asynchronous or synchronous write to any static bank \nor dynamic bank except for muxed and D modes.\n–\nAn asynchronous (modes 1, 2, A, B or C) read and a read operation from another \nstatic bank.\n– A bus turnaround delay of 2 FSMC clock cycles is inserted between:\n–\nTwo consecutive synchronous write accesses (in burst or single mode) to the same \nbank\n–\nA synchronous write (burst or single) access and an asynchronous write or read \ntransfer to or from static memory bank (the bank can be the same or different in case \nof a read operation). \n–\nTwo consecutive synchronous read accesses (in burst or single mode) followed by a \nany synchronous/asynchronous read or write from/to another static memory bank.\n– A bus turnaround delay of 3 FSMC clock cycles is inserted between:\n–\nTwo consecutive synchronous write operations (in burst or single mode) to different \nstatic banks.\n–\nA synchronous write access (in burst or single mode) and a synchronous read \naccess from the same or to a different bank.\n0000: BUSTURN phase duration = 0 HCLK clock cycle added\n...\n1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)\n\n\n<>\n\nRM0090 Rev 21\n1585/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nNote:\nPSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these \nmemories issue the NWAIT signal during the whole latency phase to prolong the latency as \nneeded.\nWith PSRAMs (CRAMs) the DATLAT field must be set to 0, so that the FSMC exits its \nlatency phase soon and starts sampling NWAIT from memory, then starts to read or write \nwhen the memory is ready.\nThis method can be used also with the latest generation of synchronous flash memories that \nissue the NWAIT signal, unlike older flash memories (check the datasheet of the specific \nflash memory being used).\nBits 15:8 DATAST[7:0]: Data-phase duration\nThese bits are written by software to define the duration of the data phase (refer to Figure 436 \nto Figure 448), used in asynchronous accesses:\n0000 0000: Reserved\n0000 0001: DATAST phase duration = 1 × HCLK clock cycles\n0000 0010: DATAST phase duration = 2 × HCLK clock cycles\n...\n1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)\nFor each memory type and access mode data-phase duration, refer to the respective figure \n(Figure 436 to Figure 448).\nExample: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock \ncycles.\nNote: In synchronous accesses, this value is don't care.\nBits 7:4 ADDHLD[3:0]: Address-hold phase duration\nThese bits are written by software to define the duration of the address hold phase (refer to \nFigure 445 to Figure 448), used in mode D and multiplexed accesses:\n0000: Reserved\n0001: ADDHLD phase duration =1 × HCLK clock cycle\n0010: ADDHLD phase duration = 2 × HCLK clock cycle\n...\n1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)\nFor each access mode address-hold phase duration, refer to the respective figure (Figure 445 \nto Figure 448).\nNote: In synchronous accesses, this value is not used, the address hold phase is always 1 \nmemory clock period duration.\nBits 3:0 ADDSET[3:0]: Address setup phase duration\nThese bits are written by software to define the duration of the address setup phase (refer to \nFigure 436 to Figure 448), used in SRAMs, ROMs and asynchronous NOR flash and PSRAM \naccesses:\n0000: ADDSET phase duration = 0 × HCLK clock cycle\n...\n1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)\nFor each access mode address setup phase duration, refer to the respective figure (refer to \nFigure 436 to Figure 448).\nNote: In synchronous NOR flash and PSRAM accesses, this value is don’t care.\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1586/1757\nRM0090 Rev 21\nSRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4)\nAddress offset: 0xA000 0000 + 0x104 + 8 * (x – 1), x = 1...4\nReset value: 0x0FFF FFFF\nThis register contains the control information of each memory bank, used for SRAMs, \nPSRAMs and NOR flash memories. This register is active for write asynchronous access \nonly when the EXTMOD bit is set in the FSMC_BCRx register.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nACCM\nOD[2:0]\nReserved\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30\nReserved, must be kept at reset value.\nBits 29:28 ACCMOD[2:0]: Access mode.\nSpecifies the asynchronous access modes as shown in the next timing diagrams.These bits are \ntaken into account only when the EXTMOD bit in the FSMC_BCRx register is 1.\n00: access mode A\n01: access mode B\n10: access mode C\n11: access mode D\nBits 27:20\nReserved, must be kept at reset value.\nBits 19:16 BUSTURN[3:0]: Bus turnaround phase duration\nThe programmed bus turnaround delay is inserted between a an asynchronous write transfer and \nany other asynchronous/synchronous read or write transfer to/from a static bank (for a read \noperation, the bank can be the same or a different one; for a write operation, the bank can be \ndifferent except in r muxed or D mode).\nIn some cases, the bus turnaround delay is fixed, whatever the programmed BUSTURN values: \n– No bus turnaround delay is inserted between two consecutive asynchronous write transfers to the \nsame static memory bank except in muxed and D mode.\n– A bus turnaround delay of 2 FSMC clock cycles is inserted between:\n–\nTwo consecutive synchronous write accesses (in burst or single mode) to the same bank.\n–\nA synchronous write transfer (in burst or single mode) and an asynchronous write or read \ntransfer to/from static a memory bank.\n– A bus turnaround delay of 3 FSMC clock cycles is inserted between:\n–\nTwo consecutive synchronous write accesses (in burst or single mode) to different static \nbanks.\n–\nA synchronous write transfer (in burst or single mode) and a synchronous read from the \nsame or from a different bank.\n0000: BUSTURN phase duration = 0 HCLK clock cycle added\n... \n1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) \n\n\n<>\n\nRM0090 Rev 21\n1587/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n36.6 \nNAND Flash/PC Card controller\nThe FSMC generates the appropriate signal timings to drive the following types of device:\n•\nNAND Flash\n–\n8-bit\n–\n16-bit\n•\n16-bit PC Card compatible devices\nThe NAND/PC Card controller can control three external banks. Bank 2 and bank 3 support \nNAND Flash devices. Bank 4 supports PC Card devices.\nEach bank is configured by means of dedicated registers (Section 36.6.8). The \nprogrammable memory parameters include access timings (shown in Table 247) and ECC \nconfiguration.\nBits 15:8 DATAST[7:0]: Data-phase duration.\nThese bits are written by software to define the duration of the data phase (refer to Figure 436 to \nFigure 448), used in asynchronous SRAM, PSRAM and NOR flash memory accesses:\n0000 0000: Reserved\n0000 0001: DATAST phase duration = 1 × HCLK clock cycles\n0000 0010: DATAST phase duration = 2 × HCLK clock cycles\n...\n1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)\nNote: In synchronous accesses, this value is don't care.\nBits 7:4 ADDHLD[3:0]: Address-hold phase duration.\nThese bits are written by software to define the duration of the address hold phase (refer to \nFigure 445 to Figure 448), used in asynchronous multiplexed accesses:\n0000: Reserved\n0001: ADDHLD phase duration = 1 × HCLK clock cycle\n0010: ADDHLD phase duration = 2 × HCLK clock cycle\n...\n1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)\nNote: In synchronous NOR flash accesses, this value is not used, the address hold phase is always \n1 flash clock period duration.\nBits 3:0 ADDSET[3:0]: Address setup phase duration.\nThese bits are written by software to define the duration of the address setup phase in HCLK cycles \n(refer to Figure 445 to Figure 448), used in asynchronous accessed:\n0000: ADDSET phase duration = 0 × HCLK clock cycle\n...\n1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)\nNote: In synchronous NOR flash and PSRAM accesses, this value is don’t care.\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1588/1757\nRM0090 Rev 21\n \n36.6.1 \nExternal memory interface signals\nThe following tables list the signals that are typically used to interface NAND Flash and PC \nCard.\nNote:\nPrefix “N”. specifies the associated signal as active low.\n8-bit NAND Flash\n t\nThere is no theoretical capacity limitation as the FSMC can manage as many address \ncycles as needed.\nTable 247. Programmable NAND/PC Card access parameters\nParameter\nFunction\nAccess mode\nUnit\nMin. Max. \nMemory setup \ntime\nNumber of clock cycles (HCLK) \nto set up the address before the \ncommand assertion\nRead/Write \nAHB clock cycle \n(HCLK) \n1 \n255\nMemory wait\nMinimum duration (HCLK clock \ncycles) of the command assertion Read/Write \nAHB clock cycle \n(HCLK) \n2\n256 \nMemory hold \nNumber of clock cycles (HCLK) \nto hold the address (and the data \nin case of a write access) after \nthe command de-assertion \nRead/Write \nAHB clock cycle \n(HCLK) \n1 \n254\nMemory \ndatabus high-Z \nNumber of clock cycles (HCLK) \nduring which the databus is kept \nin high-Z state after the start of a \nwrite access \nWrite \nAHB clock cycle \n(HCLK) \n0 \n255 \nTable 248. 8-bit NAND Flash\nFSMC signal name\nI/O \nFunction\nA[17] \nO \nNAND Flash address latch enable (ALE) signal \nA[16] \nO \nNAND Flash command latch enable (CLE) signal \nD[7:0] \nI/O \n8-bit multiplexed, bidirectional address/data bus \nNCE[x]\nO\nChip select, x = 2, 3\nNOE(= NRE)\nO \nOutput enable (memory signal name: read enable, NRE) \nNWE\nO \nWrite enable \nNWAIT/INT[3:2]\nI \nNAND Flash ready/busy input signal to the FSMC \n\n\n<>\n\nRM0090 Rev 21\n1589/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n16-bit NAND Flash\n \nThere is no theoretical capacity limitation as the FSMC can manage as many address \ncycles as needed.\n16-bit PC Card\nTable 249. 16-bit NAND Flash\nFSMC signal name \nI/O \nFunction \nA[17]\nO \nNAND Flash address latch enable (ALE) signal \nA[16] \nO \nNAND Flash command latch enable (CLE) signal \nD[15:0] \nI/O \n16-bit multiplexed, bidirectional address/data bus \nNCE[x]\nO\nChip select, x = 2, 3\nNOE(= NRE)\nO \nOutput enable (memory signal name: read enable, NRE) \nNWE\nO \nWrite enable \nNWAIT/INT[3:2]\nI \nNAND Flash ready/busy input signal to the FSMC \nTable 250. 16-bit PC Card\nFSMC signal name\nI/O\nFunction\nA[10:0]\nO\nAddress bus\nNIORD\nO\nOutput enable for I/O space\nNIOWR\nO\nWrite enable for I/O space\nNREG\nO\nRegister signal indicating if access is in Common or Attribute space\nD[15:0]\nI/O\nBidirectional databus\nNCE4_1\nO\nChip select 1\nNCE4_2\nO\nChip select 2 (indicates if access is 16-bit or 8-bit)\nNOE\nO\nOutput enable in Common and in Attribute space\nNWE\nO\nWrite enable in Common and in Attribute space\nNWAIT\nI\nPC Card wait input signal to the FSMC (memory signal name \nIORDY)\nINTR\nI\nPC Card interrupt to the FSMC (only for PC Cards that can generate \nan interrupt)\nCD\nI\nPC Card presence detection. Active high. If an access is performed \nto the PC Card banks while CD is low, an AHB error is generated. \nRefer to Section 36.3: AHB interface\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1590/1757\nRM0090 Rev 21\n36.6.2 \nNAND Flash / PC Card supported memories and transactions\nTable 251 below shows the supported devices, access modes and transactions. \nTransactions not allowed (or not supported) by the NAND Flash / PC Card controller appear \nin gray.\n \n36.6.3 \nTiming diagrams for NAND and PC Card\nEach PC Card/CompactFlash and NAND Flash memory bank is managed through a set of \nregisters:\n•\nControl register: FSMC_PCRx\n•\nInterrupt status register: FSMC_SRx\n•\nECC register: FSMC_ECCRx\n•\nTiming register for Common memory space: FSMC_PMEMx\n•\nTiming register for Attribute memory space: FSMC_PATTx\n•\nTiming register for I/O space: FSMC_PIOx\nEach timing configuration register contains three parameters used to define number of \nHCLK cycles for the three phases of any PC Card/CompactFlash or NAND Flash access, \nplus one parameter that defines the timing for starting driving the databus in the case of a \nwrite. Figure 454 shows the timing parameter definitions for common memory accesses, \nknowing that Attribute and I/O (only for PC Card) memory space access timings are similar.\nTable 251. Supported memories and transactions\nDevice\nMode \nR/W \nAHB \ndata size\nMemory \ndata size\nAllowed/\nnot allowed\nComments \nNAND 8-bit \nAsynchronous R \n8 \n8 \nY \n-\nAsynchronous W \n8 \n8 \nY \n-\nAsynchronous R \n16 \n8 \nY \nSplit into 2 FSMC accesses \nAsynchronous W \n16 \n8 \nY \nSplit into 2 FSMC accesses \nAsynchronous R \n32 \n8 \nY \nSplit into 4 FSMC accesses \nAsynchronous W \n32 \n8 \nY \nSplit into 4 FSMC accesses \nNAND 16-bit \nAsynchronous R \n8 \n16 \nY \n-\nAsynchronous W \n8 \n16 \nN \n-\nAsynchronous R \n16 \n16 \nY \n-\nAsynchronous W \n16 \n16 \nY \n-\nAsynchronous R \n32 \n16 \nY \nSplit into 2 FSMC accesses \nAsynchronous W \n32 \n16 \nY \nSplit into 2 FSMC accesses \n\n\n<>\n\nRM0090 Rev 21\n1591/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nFigure 454. NAND/PC Card controller timing for common memory access \n1.\nNOE remains high (inactive) during write access. NWE remains high (inactive) during read access.\n2.\nFor write accesses, the hold phase delay is (MEMHOLD) x HCLK cycles, while it is (MEMHOLD + 2) x \nHCLK cycles for read accesses.\n36.6.4 \nNAND Flash operations\nThe command latch enable (CLE) and address latch enable (ALE) signals of the NAND \nFlash device are driven by some address signals of the FSMC controller. This means that to \nsend a command or an address to the NAND Flash memory, the CPU has to perform a write \nto a certain address in its memory space.\nA typical page read operation from the NAND Flash device is as follows:\n1.\nProgram and enable the corresponding memory bank by configuring the FSMC_PCRx \nand FSMC_PMEMx (and for some devices, FSMC_PATTx, see Section 36.6.5) \nregisters according to the characteristics of the NAND Flash (PWID bits for the databus \nwidth of the NAND Flash, PTYP = 1, PWAITEN = 0 or 1 as needed, see Common \nmemory space timing register 2..4 (FSMC_PMEM2..4) for timing configuration).\n2. \nThe CPU performs a byte write in the common memory space, with data byte equal to \none Flash command byte (for example 0x00 for Samsung NAND Flash devices). The \nCLE input of the NAND Flash is active during the write strobe (low pulse on NWE), thus \nthe written byte is interpreted as a command by the NAND Flash. Once the command \nis latched by the NAND Flash device, it does not need to be written for the following \npage read operations.\n3. \nThe CPU can send the start address (STARTAD) for a read operation by writing the \nrequired bytes (for example four bytes or three for smaller capacity devices), \nSTARTAD[7:0], STARTAD[15:8], STARTAD[23:16] and finally STARTAD[25:24] for \n64 Mb x 8 bit NAND Flash) in the common memory or attribute space. The ALE input of \nthe NAND Flash device is active during the write strobe (low pulse on NWE), thus the \ni15570b\nHCLK\nA[25:0]\nNCEx\nNREG,\nNIOW,\nNIOR\nNWE,\nNOE(1)\nwrite_data\nread_data\nHigh\nValid\nMEMxSET + 1\nMEMxWAIT + 1\nMEMxHOLD + 1\nMEMxHIZ\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1592/1757\nRM0090 Rev 21\nwritten bytes are interpreted as the start address for read operations. Using the \nattribute memory space makes it possible to use a different timing configuration of the \nFSMC, which can be used to implement the prewait functionality needed by some \nNAND Flash memories (see details in Section 36.6.5).\n4. \nThe controller waits for the NAND Flash to be ready (R/NB signal high) to become \nactive, before starting a new access (to same or another memory bank). While waiting, \nthe controller maintains the NCE signal active (low).\n5. \nThe CPU can then perform byte read operations in the common memory space to read \nthe NAND Flash page (data field + Spare field) byte by byte.\n6. \nThe next NAND Flash page can be read without any CPU command or address write \noperation, in three different ways:\n–\nby simply performing the operation described in step 5\n–\na new random address can be accessed by restarting the operation at step 3\n–\na new command can be sent to the NAND Flash device by restarting at step 2\n36.6.5 \nNAND Flash prewait functionality\nSome NAND Flash devices require that, after writing the last part of the address, the \ncontroller wait for the R/NB signal to go low as shown in Figure 455.\nFigure 455. Access to non ‘CE don’t care’ NAND-Flash\n1.\nCPU wrote byte 0x00 at address 0x7001 0000.\n2.\nCPU wrote byte A7-A0 at address 0x7002 0000.\n3.\nCPU wrote byte A15-A8 at address 0x7002 0000.\n4.\nCPU wrote byte A23-A16 at address 0x7002 0000.\n5.\nCPU wrote byte A25-A24 at address 0x7802 0000: FSMC performs a write access using FSMC_PATT2 \ntiming definition, where ATTHOLD ≥ 7 (providing that (7+1) × HCLK = 112 ns > tWB max). This guarantees \nthat NCE remains low until R/NB goes low and high again (only requested for NAND Flash memories \nwhere NCE is not don’t care).\nNCE\nNOE\nI/O[7:0]\nR/NB\nai17733b\nHigh\ntWB\nCLE\nALE\n0x00\nA7-A0\nA15-A8\nA23-A16\nA25-A14\ntR\nNWE\n(1)\n(2)\n(3)\n(4)\n(5)\nNCE must stay low\n\n\n<>\n\nRM0090 Rev 21\n1593/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nWhen this functionality is needed, it can be guaranteed by programming the MEMHOLD \nvalue to meet the tWB timing. However CPU read accesses to the NAND Flash memory has \na hold delay of (MEMHOLD + 2) x HCLK cycles, while CPU write accesses have a hold \ndelay of (MEMHOLD) x HCLK cycles. \nTo overcome this timing constraint, the attribute memory space can be used by \nprogramming its timing register with an ATTHOLD value that meets the tWB timing, and \nleaving the MEMHOLD value at its minimum. Then, the CPU must use the common memory \nspace for all NAND Flash read and write accesses, except when writing the last address \nbyte to the NAND Flash device, where the CPU must write to the attribute memory space.\n36.6.6 \nComputation of the error correction code (ECC)\nin NAND Flash memory\nThe FSMC PC-Card controller includes two error correction code computation hardware \nblocks, one per memory bank. They are used to reduce the host CPU workload when \nprocessing the error correction code by software in the system.\nThese two registers are identical and associated with bank 2 and bank 3, respectively. As a \nconsequence, no hardware ECC computation is available for memories connected to bank \n4.\nThe error correction code (ECC) algorithm implemented in the FSMC can perform 1-bit error \ncorrection and 2-bit error detection per 256, 512, 1 024, 2 048, 4 096 or 8 192 bytes read \nfrom or written to NAND Flash memory. It is based on the Hamming coding algorithm and \nconsists in calculating the row and column parity.\nThe ECC modules monitor the NAND Flash databus and read/write signals (NCE and NWE) \neach time the NAND Flash memory bank is active.\nThe functional operations are:\n•\nWhen access to NAND Flash is made to bank 2 or bank 3, the data present on the \nD[15:0] bus is latched and used for ECC computation. \n•\nWhen access to NAND Flash occurs at any other address, the ECC logic is idle, and \ndoes not perform any operation. Thus, write operations for defining commands or \naddresses to NAND Flash are not taken into account for ECC computation.\nOnce the desired number of bytes has been read from/written to the NAND Flash by the \nhost CPU, the FSMC_ECCR2/3 registers must be read in order to retrieve the computed \nvalue. Once read, they should be cleared by resetting the ECCEN bit to zero. To compute a \nnew data block, the ECCEN bit must be set to one in the FSMC_PCR2/3 registers.\nTo perform an ECC computation:\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1594/1757\nRM0090 Rev 21\n1.\nEnable the ECCEN bit in the FSMC_PCR2/3 register.\n2. \nWrite data to the NAND Flash memory page. While the NAND page is written, the ECC \nblock computes the ECC value. \n3. \nRead the ECC value available in the FSMC_ECCR2/3 register and store it in a \nvariable.\n4. \nClear the ECCEN bit and then enable it in the FSMC_PCR2/3 register before reading \nback the written data from the NAND page. While the NAND page is read, the ECC \nblock computes the ECC value. \n5. \nRead the new ECC value available in the FSMC_ECCR2/3 register.\n6. \nIf the two ECC values are the same, no correction is required, otherwise there is an \nECC error and the software correction routine returns information on whether the error \ncan be corrected or not. \n36.6.7 \nPC Card/CompactFlash operations\nAddress spaces and memory accesses \nThe FSMC supports Compact Flash storage or PC Cards in Memory Mode and I/O Mode \n(True IDE mode is not supported).\nThe Compact Flash storage and PC Cards are made of 3 memory spaces:\n•\nCommon Memory Space\n•\nAttribute Space\n•\nI/O Memory Space\nThe nCE2 and nCE1 pins (FSMC_NCE4_2 and FSMC_NCE4_1 respectively) select the \ncard and indicate whether a byte or a word operation is being performed: nCE2 accesses \nthe odd byte on D15-8 and nCE1 accesses the even byte on D7-0 if A0=0 or the odd byte on \nD7-0 if A0=1. The full word is accessed on D15-0 if both nCE2 and nCE1 are low.\nThe memory space is selected by asserting low nOE for read accesses or nWE for write \naccesses, combined with the low assertion of nCE2/nCE1 and nREG.\n•\nIf pin nREG=1 during the memory access, the common memory space is selected\n•\nIf pin nREG=0 during the memory access, the attribute memory space is selected\nThe I/O Space is selected by asserting low nIORD for read accesses or nIOWR for write \naccesses [instead of nOE/nWE for memory Space], combined with nCE2/nCE1. Note that \nnREG must also be asserted low during accesses to I/O Space.\nThree type of accesses are allowed for a 16-bit PC Card:\n•\nAccesses to Common Memory Space for data storage can be either 8-bit accesses at \neven addresses or 16 bit AHB accesses. \nNote that 8-bit accesses at odd addresses are not supported and do not lead to the low \nassertion of nCE2. A 32-bit AHB request is translated into two 16-bit memory \naccesses.\n•\nAccesses to Attribute Memory Space where the PC Card stores configuration \ninformation are limited to 8-bit AHB accesses at even addresses.\nNote that a 16-bit AHB access is converted into a single 8-bit memory transfer: nCE1 is \nasserted low, nCE2 is asserted high and only the even Byte on D7-D0 is valid. Instead \n\n\n<>\n\nRM0090 Rev 21\n1595/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\na 32-bit AHB access is converted into two 8-bit memory transfers at even addresses: \nnCE1 is asserted low, NCE2 is asserted high and only the even bytes are valid.\n•\nAccesses to I/O Space can be performed either through AHB 8-bit or 16-bit accesses.\n \nThe FSMC Bank 4 gives access to those 3 memory spaces as described in Section 36.4.2: \nNAND/PC Card address mapping and Table 219: Memory mapping and timing registers.\nWait Feature \nThe CompactFlash Storage or PC Card may request the FSMC to extend the length of the \naccess phase programmed by MEMWAITx/ATTWAITx/IOWAITx bits, asserting the nWAIT \nsignal after nOE/nWE or nIORD/nIOWR activation if the wait feature is enabled through the \nPWAITEN bit in the FSMC_PCRx register. In order to detect the nWAIT assertion correctly, \nthe MEMWAITx/ATTWAITx/IOWAITx bits must be programmed as follows:\nTable 252. 16-bit PC-Card signals and access type \nnCE2\nnCE1\nnREG\nnOE/nWE\nnIORD /nIOWR\nA10\nA9\nA7-1\nA0 \nSpace \nAccess Type\nAllowed/not \nAllowed \n1\n0\n1\n0\n1\nX\nX\nX-X\nX\nCommon \nMemory \nSpace\nRead/Write byte on D7-D0\nYES\n0\n1\n1\n0\n1\nX\nX\nX-X\nX\nRead/Write byte on D15-D8\nNot supported\n0\n0\n1\n0\n1\nX\nX\nX-X\n0\nRead/Write word on D15-D0\nYES\nX\n0\n0\n0\n1\n0\n1\nX-X\n0\nAttribute \nSpace\nRead or Write Configuration \nregisters\nYES\nX\n0\n0\n0\n1\n0\n0\nX-X\n0\nRead or Write CIS (Card \nInformation Structure)\nYES\n1\n0\n0\n0\n1\nX\nX\nX-X\n1\nAttribute \nSpace\nInvalid Read or Write (odd \naddress)\nYES\n0\n1\n0\n0\n1\nX\nX\nX-X\nx\nInvalid Read or Write (odd \naddress)\nYES\n1\n0\n0\n1\n0\nX\nX\nX-X\n0\nI/O space\nRead Even Byte on D7-0 \nYES\n1\n0\n0\n1\n0\nX\nX\nX-X\n1\nRead Odd Byte on D7-0\nYES\n1\n0\n0\n1\n0\nX\nX\nX-X\n0\nWrite Even Byte on D7-0 \nYES\n1\n0\n0\n1\n0\nX\nX\nX-X\n1\nWrite Odd Byte on D7-0 \nYES\n0\n0\n0\n1\n0\nX\nX\nX-X\n0\nRead Word on D15-0\nYES\n0\n0\n0\n1\n0\nX\nX\nX-X\n0\nWrite word on D15-0 \nYES\n0\n1\n0\n1\n0\nX\nX\nX-X\nX\nRead Odd Byte on D15-8\nNot supported\n0\n1\n0\n1\n0\nX\nX\nX-X\nX\nWrite Odd Byte on D15-8\nNot supported\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1596/1757\nRM0090 Rev 21\nxxWAITx >= 4 + max_wait_assertion_time/HCLK\nWhere max_wait_assertion_time is the maximum time taken by NWAIT to go low once \nnOE/nWE or nIORD/nIOWR is low.\nAfter the de-assertion of nWAIT, the FSMC extends the WAIT phase for 4 HCLK clock \ncycles. \n36.6.8 \nNAND Flash/PC Card control registers\nThe NAND Flash/PC Card control registers have to be accessed by words (32 bits).\nPC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4)\nAddress offset: 0xA0000000 + 0x40 + 0x20 * (x – 1), x = 2..4\nReset value: 0x0000 0018\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nECCPS[2:0]\nTAR[2:0]\nTCLR[2:0]\nRes.\nECCEN\nPWID[1:0]\nPTYP\nPBKEN\nPWAITEN\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:20 Reserved, must be kept at reset value.\nBits 19:17 ECCPS[2:0]: ECC page size.\nDefines the page size for the extended ECC:\n000: 256 bytes\n001: 512 bytes\n010: 1024 bytes\n011: 2048 bytes\n100: 4096 bytes\n101: 8192 bytes\nBits 16:13 TAR[2:0]: ALE to RE delay.\nSets time from ALE low to RE low in number of AHB clock cycles (HCLK).\nTime is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period\n0000: 1 HCLK cycle (default)\n1111: 16 HCLK cycles\nNote: SET is MEMSET or ATTSET according to the addressed space.\nBits 12:9 TCLR[2:0]: CLE to RE delay.\nSets time from CLE low to RE low in number of AHB clock cycles (HCLK).\nTime is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period\n0000: 1 HCLK cycle (default)\n1111: 16 HCLK cycles\nNote: SET is MEMSET or ATTSET according to the addressed space.\nBits 8:7 Reserved, must be kept at reset value.\nBit 6 ECCEN: ECC computation logic enable bit\n0: ECC logic is disabled and reset (default after reset),\n1: ECC logic is enabled.\n\n\n<>\n\nRM0090 Rev 21\n1597/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nFIFO status and interrupt register 2..4 (FSMC_SR2..4)\nAddress offset: 0xA000 0000 + 0x44 + 0x20 * (x-1), x = 2..4\nReset value: 0x0000 0040\nThis register contains information about FIFO status and interrupt. The FSMC has a FIFO \nthat is used when writing to memories to store up to16 words of data from the AHB.\nThis is used to quickly write to the AHB and free it for transactions to peripherals other than \nthe FSMC, while the FSMC is draining its FIFO into the memory. This register has one of its \nbits that indicates the status of the FIFO, for ECC purposes.\nThe ECC is calculated while the data are written to the memory, so in order to read the \ncorrect ECC the software must wait until the FIFO is empty.\n \nBits 5:4 PWID[1:0]: Databus width.\nDefines the external memory device width.\n00: 8 bits\n01: 16 bits (default after reset). This value is mandatory for PC Cards.\n10: reserved, do not use\n11: reserved, do not use\nBit 3 PTYP: Memory type.\nDefines the type of device attached to the corresponding memory bank:\n0: PC Card, CompactFlash, CF+ or PCMCIA\n1: NAND Flash (default after reset)\nBit 2 PBKEN: PC Card/NAND Flash memory bank enable bit.\nEnables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB \nbus \n0: Corresponding memory bank is disabled (default after reset)\n1: Corresponding memory bank is enabled\nBit 1 PWAITEN: Wait feature enable bit.\nEnables the Wait feature for the PC Card/NAND Flash memory bank:\n0: disabled\n1: enabled\nNote: For a PC Card, when the wait feature is enabled, the MEMWAITx/ATTWAITx/IOWAITx \nbits must be programmed to a value as follows:\nxxWAITx ≥ 4 + max_wait_assertion_time/HCLK\nWhere max_wait_assertion_time is the maximum time taken by NWAIT to go low once \nnOE/nWE or nIORD/nIOWR is low.\nBit 0\nReserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFEMPT\nIFEN\nILEN\nIREN\nIFS\nILS\nIRS\nr\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1598/1757\nRM0090 Rev 21\n \nCommon memory space timing register 2..4 (FSMC_PMEM2..4)\nAddress offset: Address: 0xA000 0000 + 0x48 + 0x20 * (x – 1), x = 2..4\nReset value: 0xFCFC FCFC\nEach FSMC_PMEMx (x = 2..4) read/write register contains the timing information for PC \nCard or NAND Flash memory bank x, used for access to the common memory space of the \n16-bit PC Card/CompactFlash, or to access the NAND Flash for command, address write \naccess and data read/write access.\n \nBits 31:7\nReserved, must be kept at reset value.\nBit 6\nFEMPT: FIFO empty.\nRead-only bit that provides the status of the FIFO\n0: FIFO not empty\n1: FIFO empty\nBit 5\nIFEN: Interrupt falling edge detection enable bit\n0: Interrupt falling edge detection request disabled\n1: Interrupt falling edge detection request enabled\nBit 4\nILEN: Interrupt high-level detection enable bit\n0: Interrupt high-level detection request disabled\n1: Interrupt high-level detection request enabled\nBit 3\nIREN: Interrupt rising edge detection enable bit\n0: Interrupt rising edge detection request disabled\n1: Interrupt rising edge detection request enabled\nBit 2\nIFS: Interrupt falling edge status\nThe flag is set by hardware and reset by software.\n0: No interrupt falling edge occurred\n1: Interrupt falling edge occurred\nNote: This bit is set by programming it to 1 by software. \nBit 1\nILS: Interrupt high-level status\nThe flag is set by hardware and reset by software.\n0: No Interrupt high-level occurred\n1: Interrupt high-level occurred\nBit 0\nIRS: Interrupt rising edge status\nThe flag is set by hardware and reset by software.\n0: No interrupt rising edge occurred\n1: Interrupt rising edge occurred\nNote: This bit is set by programming it to 1 by software. \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMEMHIZ[7:0]\nMEMHOLD[7:0]\nMEMWAIT[7:0]\nMEMSET[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n1599/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \nAttribute memory space timing registers 2..4 (FSMC_PATT2..4)\nAddress offset: 0xA000 0000 + 0x4C + 0x20 * (x – 1), x = 2..4\nReset value: 0xFCFC FCFC\nEach FSMC_PATTx (x = 2..4) read/write register contains the timing information for PC \nCard/CompactFlash or NAND Flash memory bank x. It is used for 8-bit accesses to the \nattribute memory space of the PC Card/CompactFlash or to access the NAND Flash for the \nlast address write access if the timing must differ from that of previous accesses (for \nReady/Busy management, refer to Section 36.6.5: NAND Flash prewait functionality).\n \nBits 31:24 MEMHIZx[7:0]: Common memory x databus HiZ time\nDefines the number of HCLK clock cycles during which the databus is kept in HiZ after the \nstart of a PC Card/NAND Flash write access to common memory space on socket x. Only \nvalid for write transaction:\n0000 0000: 1 HCLK cycle\n1111 1110: 255 HCLK cycles\n1111 1111: Reserved\nBits 23:16 MEMHOLDx[7:0]: Common memory x hold time\nFor NAND Flash read accesses to the common memory space, these bits define the \nnumber of (HCLK+2) clock cycles during which the address is held after the command is \ndeasserted (NWE, NOE).\nFor NAND Flash write accesses to the common memory space, these bits define the \nnumber of HCLK clock cycles during which the data are held after the command is \ndeasserted (NWE, NOE).\n0000 0000: Reserved\n0000 0001: 1 HCLK cycle for write accesses, 3 HCLK cycles for read accesses\n1111 1110: 254 HCLK cycle for write accesses, 256 HCLK cycles for read accesses\n1111 1111: Reserved\nBits 15:8 MEMWAITx[7:0]: Common memory x wait time\nDefines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, \nNOE), for PC Card/NAND Flash read or write access to common memory space on socket \nx. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) \nat the end of the programmed value of HCLK:\n0000 0000: Reserved\n0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)\n1111 1110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)\n1111 1111: Reserved.\nBits 7:0 MEMSETx[7:0]: Common memory x setup time\nDefines the number of HCLK () clock cycles to set up the address before the command \nassertion (NWE, NOE), for PC Card/NAND Flash read or write access to common memory \nspace on socket x:\n0000 0000: 1 HCLK cycle\n1111 1110: 255 HCLK cycles\n1111 1111: Reserved \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nATTHIZ[7:0]\nATTHOLD[7:0]\nATTWAIT[7:0]\nATTSET[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1600/1757\nRM0090 Rev 21\n \nI/O space timing register 4 (FSMC_PIO4)\nAddress offset: 0xA000 0000 + 0xB0\nReset value: 0xFCFCFCFC\nThe FSMC_PIO4 read/write registers contain the timing information used to gain access to \nthe I/O space of the 16-bit PC Card/CompactFlash.\n \nBits 31:24 ATTHIZ[7:0]: Attribute memory x databus HiZ time\nDefines the number of HCLK clock cycles during which the databus is kept in HiZ after the \nstart of a PC CARD/NAND Flash write access to attribute memory space on socket x. Only \nvalid for write transaction:\n0000 0000: 0 HCLK cycle\n1111 1110: 255 HCLK cycles\n1111 1111: Reserved.\nBits 23:16 ATTHOLD[7:0]: Attribute memory x hold time\nFor PC Card/NAND Flash read accesses to attribute memory space on socket x, these bits \ndefine the number of HCLK clock cycles (HCLK +2) clock cycles during which the address is \nheld after the command is deasserted (NWE, NOE).\nFor PC Card/NAND Flash write accesses to attribute memory space on socket x, these bits \ndefine the number of HCLK clock cycles during which the data are held after the command \nis deasserted (NWE, NOE).\n0000 0000: reserved\n0000 0001: 1 HCLK cycle for write access, 3 HCLK cycles for read accesses\n1111 1110: 254 HCLK cycle for write access, 256 HCLK cycles for read accesses\n1111 1111: Reserved\nBits 15:8 ATTWAIT[7:0]: Attribute memory x wait time\nDefines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, \nNOE), for PC Card/NAND Flash read or write access to attribute memory space on socket x. \nThe duration for command assertion is extended if the wait signal (NWAIT) is active (low) at \nthe end of the programmed value of HCLK:\n0000 0000: Reserved\n0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)\n1111 1111: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)\n1111 1111: Reserved.\nBits 7:0 ATTSET[7:0]: Attribute memory x setup time\nDefines the number of HCLK (+1) clock cycles to set up address before the command \nassertion (NWE, NOE), for PC CARD/NAND Flash read or write access to attribute memory \nspace on socket x:\n0000 0000: 1 HCLK cycle\n1111 1110: 255 HCLK cycles\n1111 1111: Reserved. \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nIOHIZ[7:0]\nIOHOLD[7:0]\nIOWAIT[7:0]\nIOSET[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nRM0090 Rev 21\n1601/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \nECC result registers 2/3 (FSMC_ECCR2/3)\nAddress offset: 0xA000 0000 + 0x54 + 0x20 * (x – 1), x = 2 or 3\nReset value: 0x0000 0000\nThese registers contain the current error correction code value computed by the ECC \ncomputation modules of the FSMC controller (one module per NAND Flash memory bank). \nWhen the CPU reads the data from a NAND Flash memory page at the correct address \n(refer to Section 36.6.6: Computation of the error correction code (ECC) in NAND Flash \nmemory), the data read from or written to the NAND Flash are processed automatically by \nECC computation module. At the end of X bytes read (according to the ECCPS field in the \nFSMC_PCRx registers), the CPU must read the computed ECC value from the \nFSMC_ECCx registers, and then verify whether these computed parity data are the same \nas the parity value recorded in the spare area, to determine whether a page is valid, and, to \ncorrect it if applicable. The FSMC_ECCRx registers should be cleared after being read by \nsetting the ECCEN bit to zero. For computing a new data block, the ECCEN bit must be set \nto one.\n \nBits 31:24 IOHIZ[7:0]: I/O x databus HiZ time\nDefines the number of HCLK clock cycles during which the databus is kept in HiZ after the start \nof a PC Card write access to I/O space on socket x. Only valid for write transaction:\n0000 0000: 0 HCLK cycle\n1111 1111: 255 HCLK cycles (default value after reset)\nBits 23:16 IOHOLD[7:0]: I/O x hold time\nDefines the number of HCLK clock cycles to hold address (and data for write access) after the \ncommand deassertion (NWE, NOE), for PC Card read or write access to I/O space on socket \nx:\n0000 0000: reserved\n0000 0001: 1 HCLK cycle\n1111 1111: 255 HCLK cycles (default value after reset)\nBits 15:8 IOWAIT[7:0]: I/O x wait time\nDefines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE, \nSMNOE), for PC Card read or write access to I/O space on socket x. The duration for \ncommand assertion is extended if the wait signal (NWAIT) is active (low) at the end of the \nprogrammed value of HCLK:\n0000 0000: reserved, do not use this value\n0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)\n1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) \n(default value after reset)\nBits 7:0 IOSET[7:0]: I/O x setup time\nDefines the number of HCLK (+1) clock cycles to set up the address before the command \nassertion (NWE, NOE), for PC Card read or write access to I/O space on socket x:\n0000 0000: 1 HCLK cycle\n1111 1111: 256 HCLK cycles (default value after reset)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nECCx[31:0]\nr\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1602/1757\nRM0090 Rev 21\n \n \nBits 31:0 ECCx[31:0]: ECC result\nThis field provides the value computed by the ECC computation logic. Table 253 hereafter \ndescribes the contents of these bit fields.\nTable 253. ECC result relevant bits\nECCPS[2:0]\nPage size in bytes\nECC bits\n000\n256\nECC[21:0]\n001\n512\nECC[23:0]\n010\n1024\nECC[25:0]\n011\n2048\nECC[27:0]\n100\n4096\nECC[29:0]\n101\n8192\nECC[31:0]\n\n\n<>\n\nRM0090 Rev 21\n1603/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n36.6.9 \nFSMC register map\nThe following table summarizes the FSMC registers. \n \nTable 254. FSMC register map\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0000\nFSMC_BCR1\nReserved\nCBURSTRW\nCPSIZE[2:0]\nASYNCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[0:1]\nMUXEN\nMBKEN\n0008\nFSMC_BCR2\nReserved\nCBURSTRW\nCPSIZE[2:0]\nASYNCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[0:1]\nMUXEN\nMBKEN\n0010\nFSMC_BCR3\nReserved\nCBURSTRW\nCPSIZE[2:0]\nASYNCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[0:1]\nMUXEN\nMBKEN\n0018\nFSMC_BCR4\nReserved\nCBURSTRW\nCPSIZE[2:0]\nASYNCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[0:1]\nMUXEN\nMBKEN\n0004\nFSMC_BTR1\nRes.\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0]\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\n000C\nFSMC_BTR2\nRes.\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0]\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\n0014\nFSMC_BTR3\nRes.\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0]\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\n001C\nFSMC_BTR4\nRes.\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0]\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\n0104\nFSMC_BWTR\n1\nRes.\nACC\nMOD\n[1:0]\nRes.\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\n010C\nFSMC_BWTR\n2\nRes.\nACC\nMOD\n[1:0]\nRes.\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\n\n\n<>\n\nFlexible static memory controller (FSMC)\nRM0090\n1604/1757\nRM0090 Rev 21\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0114\nFSMC_BWTR\n3\nRes.\nACC\nMOD\n[1:0]\nRes.\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\n011C\nFSMC_BWTR\n4\nRes.\nACC\nMOD\n[1:0]\nRes.\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\n0xA000\n0060\nFSMC_PCR2\nReserved\nECCPS[2:0]\nTAR[2:0]\nTCLR[2:0]\nRes.\nECCEN\nPWID[1:0]\nPTYP\nPBKEN\nPWAITEN\nReserved\n0xA000\n0080\nFSMC_PCR3\nReserved\nECCPS[2:0]\nTAR[2:0]\nTCLR[2:0]\nRes.\nECCEN\nPWID[1:0]\nPTYP\nPBKEN\nPWAITEN\nReserved\n0xA000\n00A0\nFSMC_PCR4\nReserved\nECCPS[2:0]\nTAR[2:0]\nTCLR[2:0]\nRes.\nECCEN\nPWID[1:0]\nPTYP\nPBKEN\nPWAITEN\nReserved\n0xA000\n0064\nFSMC_SR2\nReserved\nFEMPT\nIFEN\nILEN\nIREN\nIFS\nILS\nIRS\n0xA000\n0084\nFSMC_SR3\nReserved\nFEMPT\nIFEN\nILEN\nIREN\nIFS\nILS\nIRS\n0xA000\n00A4\nFSMC_SR4\nReserved\nFEMPT\nIFEN\nILEN\nIREN\nIFS\nILS\nIRS\n0xA000\n0068\nFSMC_PMEM\n2\nMEMHIZ[7:0]\nMEMHOLD[7:0]\nMEMWAIT[7:0]\nMEMSET[7:0]\n0xA000\n0088\nFSMC_PMEM\n3\nMEMHIZ[7:0]\nMEMHOLD[7:0]\nMEMWAIT[7:0]\nMEMSET[7:0]\n0xA000\n00A8\nFSMC_PMEM\n4\nMEMHIZ[7:0]\nMEMHOLD[7:0]\nMEMWAIT[7:0]\nMEMSET[7:0]\n0xA000\n006C\nFSMC_PATT2\nATTHIZ[7:0]\nATTHOLD[7:0]\nATTWAIT[7:0]\nATTSET[7:0]\n0xA000\n008C\nFSMC_PATT3\nATTHIZ[7:0]\nATTHOLD[7:0]\nATTWAIT[7:0]\nATTSET[7:0]\n0xA000\n00AC\nFSMC_PATT4\nATTHIZ[7:0]\nATTHOLD[7:0]\nATTWAIT[7:0]\nATTSET[7:0]\n0xA000\n00B0\nFSMC_PIO4\nIOHIZ[7:0]\nIOHOLD[7:0]\nIOWAIT[7:0]\nIOSET[7:0]\n0xA000\n0074\nFSMC_ECCR2\nECC[31:0]\n0xA000\n0094\nFSMC_ECCR3\nECC[31:0]\nTable 254. FSMC register map (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1605/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n37 \nFlexible memory controller (FMC)\nThe Flexible memory controller (FMC) includes three memory controllers:\n•\nThe NOR/PSRAM memory controller \n•\nThe NAND/PC Card memory controller\n•\nThe Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller \nThis section applies to STM32F42xxx and STM32F43xxx only.\n37.1 \nFMC main features\nThe FMC functional block makes the interface with synchronous and asynchronous static \nmemories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:\n•\nto translate AHB transactions into the appropriate external device protocol\n•\nto meet the access time requirements of the external memory devices\nAll external memories share the addresses, data and control signals with the controller. \nEach external device is accessed by means of a unique Chip Select. The FMC performs \nonly one access at a time to an external device.\nThe main features of the FMC controller are the following:\n•\nInterface with static-memory mapped devices including: \n–\nStatic random access memory (SRAM)\n–\nNOR Flash memory/OneNAND Flash memory\n–\nPSRAM (4 memory banks)\n–\n16-bit PC Card compatible devices\n–\nTwo banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of \ndata\n•\nInterface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories\n•\nBurst mode support for faster access to synchronous devices such as NOR Flash \nmemory, PSRAM and SDRAM)\n•\nProgrammable continuous clock output for asynchronous and synchronous accesses\n•\n8-,16- or 32-bit wide data bus\n•\nIndependent Chip Select control for each memory bank\n•\nIndependent configuration for each memory bank\n•\nWrite enable and byte lane select outputs for use with PSRAM, SRAM and SDRAM \ndevices\n•\nExternal asynchronous wait control\n•\nWrite Data FIFO with 16 x33-bit depth\n•\nWrite Address FIFO with 16x30-bit depth\n•\nCacheable Read FIFO with 6 x32-bit depth (6 x14-bit address tag) for SDRAM \ncontroller.\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1606/1757\nRM0090 Rev 21\nThe FMC embeds two Write FIFOs: a Write Data FIFO with a 16x33-bit depth and a Write \nAddress FIFO with a 16x30-bit depth. \n•\nThe Write Data FIFO stores the AHB data to be written to the memory (up to 32 bits) \nplus one bit for the AHB transfer (burst or not sequential mode)\n•\nThe Write Address FIFO stores the AHB address (up to 28 bits) plus the AHB data size \n(up to 2 bits). When operating in burst mode, only the start address is stored except \nwhen crossing a page boundary (for PSRAM and SDRAM). In this case, the AHB burst \nis broken into two FIFO entries.\nAt startup the FMC pins must be configured by the user application. The FMC I/O pins which \nare not used by the application can be used for other purposes.\nThe FMC registers that define the external device type and associated characteristics are \nusually set at boot time and do not change until the next reset or power-up. However, the \nsettings can be changed at any time.\n37.2 \nBlock diagram\nThe FMC consists of five main blocks:\n•\nThe AHB interface (including the FMC configuration registers)\n•\nThe NOR Flash/PSRAM/SRAM controller\n•\nThe NAND Flash/PC Card controller\n•\nThe SDRAM controller\n•\nThe external device interface\nThe block diagram is shown in Figure 456.\n\n\n<>\n\nRM0090 Rev 21\n1607/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nFigure 456. FMC block diagram\n37.3 \nAHB interface\nThe AHB slave interface allows internal CPUs and other bus master peripherals to access \nthe external memories.\nAHB transactions are translated into the external device protocol. In particular, if the \nselected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split \ninto consecutive 16- or 8-bit accesses. The FMC Chip Select (FMC_NEx) does not toggle \nbetween consecutive accesses except when performing accesses in mode D with the \nextended mode enabled.\nMS30443V5\nHCLK\nNAND/PC Card\nmemory\ncontroller\nNAND\nsignals\nShared \nsignals\nNOR/PSRAM\nsignals\nFMC_NE[4:1]\nFMC_NL(or NADV)\nFMC_NWAIT\nFMC_D[31:0]\nFMC_NOE\nFMC_NWE\nFMC_NIORD\nFMC_NREG\nFMC_CD\nPC Card \nsignals\nFMC_NBL[3:0]\nFMC_NCE[3:2]\nFMC_INT[3:2]\nFMC_INTR\nFMC_NCE4_1\nFMC_NCE4_2\nFMC_NIOWR\nFMC_CLK\nSDRAM\ncontroller\nFMC_SDNWE\nFMC_SDCKE[1:0]\nFMC_SDNE[1:0]\nFMC_NRAS\nFMC_NCAS\nSDRAM\nsignals\nFMC_A[25:0]\nNOR/PSRAM/SRAM \nShared signals\nSRAM/PSRAM/SDRAM \nShared signals\nFMC_SDCLK\nFMC interrupts to NVIC\nFrom clock\ncontroller\nConfiguration\nregisters\nNOR/PSRAM\nmemory\ncontroller\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1608/1757\nRM0090 Rev 21\nThe FMC generates an AHB error in the following conditions:\n•\nWhen reading or writing to an FMC bank (Bank 1 to 4) which is not enabled.\n•\nWhen reading or writing to the NOR Flash bank while the FACCEN bit is reset in the \nFMC_BCRx register.\n•\nWhen reading or writing to the PC Card banks while the FMC_CD input pin (Card \nPresence Detection) is low.\n•\nWhen writing to a write protected SDRAM bank (WP bit set in the SDRAM_SDCRx \nregister).\n•\nWhen the SDRAM address range is violated (access to reserved address range)\nThe effect of an AHB error depends on the AHB master which has attempted the R/W \naccess:\n•\nIf the access has been attempted by the Cortex®-M4 with FPU CPU, a hard fault \ninterrupt is generated.\n•\nIf the access has been performed by a DMA controller, a DMA transfer error is \ngenerated and the corresponding DMA channel is automatically disabled. \nThe AHB clock (HCLK) is the reference clock for the FMC.\n37.3.1 \nSupported memories and transactions\nGeneral transaction rules\nThe requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the \naccessed external device has a fixed data width. This may lead to inconsistent transfers.\nTherefore, some simple transaction rules must be followed:\n•\nAHB transaction size and memory data size are equal\nThere is no issue in this case.\n•\nAHB transaction size is greater than the memory size:\nIn this case, the FMC splits the AHB transaction into smaller consecutive memory \naccesses to meet the external data width. The FMC Chip Select (FMC_NEx) does not \ntoggle between the consecutive accesses.\n•\nAHB transaction size is smaller than the memory size:\nThe transfer may or not be consistent depending on the type of external device:\n–\nAccesses to devices that have the byte select feature (SRAM, ROM, PSRAM, \nSDRAM)\nIn this case, the FMC allows read/write transactions and accesses the right data \nthrough its byte lanes BL[3:0]. \nbyte to be written are addressed by NBL[3:0]. \nAll memory byte are read (NBL[3:0] are driven low during read transaction) and \nthe useless ones are discarded.\n–\nAccesses to devices that do not have the byte select feature (16-bit NOR and \nNAND Flash memories)\nThis situation occurs when a byte access is requested to a 16-bit wide Flash \nmemory. Since the device cannot be accessed in byte mode (only 16-bit words \ncan be read/written from/to the Flash memory), Write transactions and Read \ntransactions are allowed (the controller reads the entire 16-bit memory word and \nuses only the required byte).\n\n\n<>\n\nRM0090 Rev 21\n1609/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nConfiguration registers\nThe FMC can be configured through a set of registers. Refer to Section 37.5.6, for a \ndetailed description of the NOR Flash/PSRAM controller registers. Refer to Section 37.6.8, \nfor a detailed description of the NAND Flash/PC Card registers and to Section 37.7.5 for a \ndetailed description of the SDRAM controller registers.\n37.4 \nExternal device address mapping\nFrom the FMC point of view, the external memory is divided into 6 fixed-size banks of \n256 Mbyte each (see Figure 457):\n•\nBank 1 used to address up to 4 NOR Flash memory or PSRAM devices. This bank is \nsplit into 4 NOR/PSRAM subbanks with 4 dedicated Chip Selects, as follows:\n–\nBank 1 - NOR/PSRAM 1\n–\nBank 1 - NOR/PSRAM 2\n–\nBank 1 - NOR/PSRAM 3\n–\nBank 1 - NOR/PSRAM 4\n•\nBanks 2 and 3 used to address NAND Flash memory devices (1 device per bank)\n•\nBank 4 used to address a PC Card\n•\nBank 5 and 6 used to address SDRAM devices (1 device per bank).\nFor each bank the type of memory to be used can be configured by the user application \nthrough the Configuration register.\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1610/1757\nRM0090 Rev 21\nFigure 457. FMC memory banks\n37.4.1 \nNOR/PSRAM address mapping\nHADDR[27:26] bits are used to select one of the four memory banks as shown in Table 255.\n \nBank 1\n4 x 64 MB\nNOR/PSRAM/SRAM\nSupported memory type\nBank\n0x6000 0000\nAddress\nPC Card\nMS30444V2\nSDRAM\n0x6FFF FFFF\n0x7000 0000\n0x7FFF FFFF\n0x8000 0000\n0x8FFF FFFF\n0x9000 0000\n0x9FFF FFFF\n0xC000 0000\n0xCFFF FFFF\n0xD000 0000\n0xDFFF FFFF\nBank 2\n4 x 64 MB\nBank 3\n4 x 64 MB\nBank 4\n4 x 64 MB\nSDRAM Bank 1\n4 x 64 MB\nSDRAM Bank 2\n4 x 64 MB\nNAND Flash memory\nTable 255. NOR/PSRAM bank selection\nHADDR[27:26](1)\n1.\nHADDR are internal AHB address lines that are translated to external memory.\nSelected bank\n00 \nBank 1 - NOR/PSRAM 1\n01 \nBank 1 - NOR/PSRAM 2\n10 \nBank 1 - NOR/PSRAM 3\n11 \nBank 1 - NOR/PSRAM 4\n\n\n<>\n\nRM0090 Rev 21\n1611/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nThe HADDR[25:0] bits contain the external memory address. Since HADDR is a byte \naddress whereas the memory is addressed at word level, the address actually issued to the \nmemory varies according to the memory data width, as shown in the following table.\n \nWrap support for NOR Flash/PSRAM\nWrap burst mode for synchronous memories is not supported. The memories must be \nconfigured in linear burst mode of undefined length.\n37.4.2 \nNAND Flash memory/PC Card address mapping\nIn this case, three banks are available, each of them being divided into memory areas as \nindicated in Table 257.\n \nFor NAND Flash memory, the common and attribute memory spaces are subdivided into \nthree sections (see in Table 258 below) located in the lower 256 Kbytes:\n•\nData section (first 64 Kbytes in the common/attribute memory space)\n•\nCommand section (second 64 Kbytes in the common / attribute memory space)\n•\nAddress section (next 128 Kbytes in the common / attribute memory space)\nTable 256. NOR/PSRAM External memory address\nMemory width(1)\n1.\nIn case of a 16-bit external memory width, the FMC internally uses HADDR[25:1] to generate the address \nfor external memory FMC_A[24:0]. In case of a 32-bit memory width, the FMC internally uses \nHADDR[25:2] to generate the external address. \nWhatever the external memory width, FMC_A[0] should be connected to external memory address A[0].\nData address issued to the memory\nMaximum memory capacity (bits) \n8-bit \nHADDR[25:0] \n64 Mbyte x 8 = 512 Mbit \n16-bit\nHADDR[25:1] >> 1 \n64 Mbyte/2 x 16 = 512 Mbit \n32-bit\nHADDR[25:2] >> 2\n64 Mbyte/4 x 32 = 512 Mbit \nTable 257. NAND/PC Card memory mapping and timing registers\nStart address\nEnd address\nFMC bank\nMemory space\nTiming register\n0x9C00 0000\n0x9FFF FFFF\nBank 4 - PC card\nI/O\nFMC_PIO4 (0xB0)\n0x9800 0000\n0x9BFF FFFF\nAttribute\n FMC_PATT4 (0xAC)\n0x9000 0000\n0x93FF FFFF\nCommon\n FMC_PMEM4 (0xA8)\n0x8800 0000\n0x8BFF FFFF\nBank 3 - NAND Flash\nAttribute\n FMC_PATT3 (0x8C)\n0x8000 0000\n0x83FF FFFF\nCommon\n FMC_PMEM3 (0x88)\n0x7800 0000\n0x7BFF FFFF\nBank 2- NAND Flash\nAttribute\nFMC_PATT2 (0x6C)\n0x7000 0000\n0x73FF FFFF\nCommon\n FMC_PMEM2 (0x68)\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1612/1757\nRM0090 Rev 21\n \nThe application software uses the 3 sections to access the NAND Flash memory:\n•\nTo send a command to NAND Flash memory, the software must write the command \nvalue to any memory location in the command section.\n•\nTo specify the NAND Flash address that must be read or written, the software \nmust write the address value to any memory location in the address section. Since an \naddress can be 4 or 5 byte long (depending on the actual memory size), several \nconsecutive write operations to the address section are required to specify the full \naddress.\n•\nTo read or write data, the software reads or writes the data from/to any memory \nlocation in the data section.\nSince the NAND Flash memory automatically increments addresses, there is no need to \nincrement the address of the data section to access consecutive memory locations.\n37.4.3 \nSDRAM address mapping \nThe HADDR[28] bit (internal AHB address line 28) is used to select one of the two memory \nbanks as indicated in Table 259.\n \nThe following table shows SDRAM mapping for an 13-bit row ,a 11-bit column and 4 internal \nbank configurations.\n \nTable 258. NAND bank selection\nSection name\nHADDR[17:16]\nAddress range\nAddress section \n1X \n0x020000-0x03FFFF \nCommand section \n01 \n0x010000-0x01FFFF \nData section \n00 \n0x000000-0x0FFFF \nTable 259. SDRAM bank selection\nHADDR[28]\nSelected bank\nControl register\nTiming register\n0\nSDRAM Bank1\nFMC_SDCR1\nFMC_SDTR1\n1\nSDRAM Bank2\nFMC_SDCR2\nFMC_SDTR2\nTable 260. SDRAM address mapping\nMemory width(1)\nInternal bank\nRow address\nColumn \naddress(2)\nMaximum \nmemory capacity \n(Mbyte)\n8-bit\nHADDR[25:24]\nHADDR[23:11]\nHADDR[10:0]\n64 Mbyte: \n4 x 8K x 2K\n16-bit\nHADDR[26:25]\nHADDR[24:12]\nHADDR[11:1]\n128 Mbyte: \n4 x 8K x 2K x 2\n32-bit\nHADDR[27:26]\nHADDR[25:13]\nHADDR[12:2]\n256 Mbyte:\n4 x 8K x 2K x 4\n\n\n<>\n\nRM0090 Rev 21\n1613/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nThe HADDR[27:0] bits are translated to external SDRAM address depending on the \nSDRAM controller configuration:\n•\nData size:8, 16 or 32 bits\n•\nRow size:11, 12 or 13 bits\n•\nColumn size: 8, 9, 10 or 11 bits\n•\nNumber of internal banks: two or four internal banks\nTable 261 to Table 263 shows the SDRAM address mapping versus the SDRAM controller \nconfiguration. \n ) \n1.\nWhen interfacing with a 16-bit memory, the FMC internally uses the HADDR[11:1] internal AHB address \nlines to generate the external address. When interfacing with a 32-bit memory, the FMC internally uses \nHADDR[12:2] lines to generate the external address. Whatever the memory width, FMC_A[0] has to be \nconnected to the external memory address A[0].\n2.\nThe AutoPrecharge is not supported. FMC_A[10] must be connected to the external memory address \nA[10] but it is always driven ‘low’.\nTable 261. SDRAM address mapping with 8-bit data bus width(1)(2)\nRow size \nconfiguration\nHADDR(AHB Internal Address Lines)\n27 26 25 24\n23\n22\n21\n20\n19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\n11-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[7:0]\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[8:0]\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[9:0]\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[10:0]\n12-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[7:0]\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[8:0]\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[9:0]\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[10:0]\n13-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[7:0]\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[8:0]\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[9:0]\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[10:0]\n1.\nBANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’.\n2.\nAccess to Reserved (Res.) address range generates an AHB error.\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1614/1757\nRM0090 Rev 21\n )\n \nTable 262. SDRAM address mapping with 16-bit data bus width(1)(2)\nRow size \nConfiguration\nHADDR(AHB address Lines)\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n11-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[7:0]\nBM0(3)\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[8:0]\nBM0\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[9:0]\nBM0\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[10:0]\nBM0\n12-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[7:0]\nBM0\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[8:0]\nBM0\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[9:0]\nBM0\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[10:0]\nBM0\n13-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[7:0]\nBM0\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[8:0]\nBM0\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[9:0]\nBM0\nRe\ns.\nBank\n[1:0]\nRow[12:0]\nColumn[10:0]\nBM0\n1.\nBANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’.\n2.\nAccess to Reserved space (Res.) generates an AHB error. \n3.\nBM0: is the byte mask for 16-bit access.\nTable 263. SDRAM address mapping with 32-bit data bus width(1)(2)\nRow size \nconfiguration\nHADDR(AHB address Lines)\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n11-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[7:0]\nBM[1:0](3)\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[8:0]\nBM[1:0]\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[9:0]\nBM[1:0]\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[10:0]\nBM[1:0]\n12-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[7:0]\nBM[1:0]\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[8:0]\nBM[1:0]\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[9:0]\nBM[1:0]\nRes. Bank\n[1:0]\nRow[11:0]\nColumn[10:0]\nBM[1:0]\n\n\n<>\n\nRM0090 Rev 21\n1615/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n37.5 \nNOR Flash/PSRAM controller\nThe FMC generates the appropriate signal timings to drive the following types of memories:\n•\nAsynchronous SRAM and ROM\n–\n8 bits\n–\n16 bits\n–\n32 bits\n•\nPSRAM (Cellular RAM)\n–\nAsynchronous mode\n–\nBurst mode for synchronous accesses\n–\nMultiplexed or non-multiplexed\n•\nNOR Flash memory\n–\nAsynchronous mode \n–\nBurst mode for synchronous accesses\n–\nMultiplexed or non-multiplexed\nThe FMC outputs a unique Chip Select signal, NE[4:1], per bank. All the other signals \n(addresses, data and control) are shared.\nThe FMC supports a wide range of devices through a programmable timings among which:\n•\nProgrammable wait states (up to 15)\n•\nProgrammable bus turnaround cycles (up to 15)\n•\nProgrammable output enable and write enable delays (up to 15)\n•\nIndependent read and write timings and protocol to support the widest variety of \nmemories and timings\n•\nProgrammable continuous clock (FMC_CLK) output.\nThe FMC Clock (FMC_CLK) is a submultiple of the HCLK clock. It can be delivered to the \nselected external device either during synchronous accesses only or during asynchronous \n13-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[7:0]\nBM[1:0]\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[8:0]\nBM[1:0]\nRes. Bank\n[1:0]\nRow[12:0]\nColumn[9:0]\nBM[1:0]\nBank\n[1:0]\nRow[12:0]\nColumn[10:0]\nBM[1:0]\n1.\nBANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’.\n2.\nAccess to Reserved space (Res.) generates an AHB error.\n3.\nBM[1:0]: is the byte mask for 32-bit access.\nTable 263. SDRAM address mapping with 32-bit data bus width(1)(2) (continued)\nRow size \nconfiguration\nHADDR(AHB address Lines)\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1616/1757\nRM0090 Rev 21\nand synchronous accesses depending on the CCKEN bit configuration in the FMC_BCR1 \nregister:\n•\nIf the CCLKEN bit is reset, the FMC generates the clock (CLK) only during \nsynchronous accesses (Read/write transactions). \n•\nIf the CCLKEN bit is set, the FMC generates a continuous clock during asynchronous \nand synchronous accesses. To generate the FMC_CLK continuous clock, Bank 1 must \nbe configured in synchronous mode (see Section 37.5.6: NOR/PSRAM controller \nregisters). Since the same clock is used for all synchronous memories, when a \ncontinuous output clock is generated and synchronous accesses are performed, the \nAHB data size has to be the same as the memory data width (MWID) otherwise the \nFMC_CLK frequency is changed depending on AHB data transaction (refer to \nSection 37.5.5: Synchronous transactions for FMC_CLK divider ratio formula). \nThe size of each bank is fixed and equal to 64 Mbyte. Each bank is configured through \ndedicated registers (see Section 37.5.6: NOR/PSRAM controller registers).\nThe programmable memory parameters include access times (see Table 264) and support \nfor wait management (for PSRAM and NOR Flash accessed in burst mode).\n \n37.5.1 \nExternal memory interface signals\nTable 265, Table 266 and Table 267 list the signals that are typically used to interface with \nNOR Flash memory, SRAM and PSRAM.\nNote:\nThe prefix “N” identifies the signals which are active low.\nTable 264. Programmable NOR/PSRAM access parameters\nParameter \nFunction \nAccess mode \nUnit \nMin. \nMax. \nAddress \nsetup\nDuration of the address \nsetup phase \nAsynchronous \nAHB clock cycle \n(HCLK) \n0\n15\nAddress hold\nDuration of the address hold \nphase \nAsynchronous, \nmuxed I/Os \nAHB clock cycle \n(HCLK) \n1\n15\nData setup\nDuration of the data setup \nphase \nAsynchronous \nAHB clock cycle \n(HCLK) \n1\n256\nBust turn\nDuration of the bus \nturnaround phase \nAsynchronous and \nsynchronous \nread/write\nAHB clock cycle \n(HCLK) \n0\n15\nClock divide \nratio\nNumber of AHB clock cycles \n(HCLK) to build one memory \nclock cycle (CLK) \nSynchronous\nAHB clock cycle \n(HCLK) \n2\n16 \nData latency\nNumber of clock cycles to \nissue to the memory before \nthe first data of the burst \nSynchronous\nMemory clock \ncycle (CLK) \n2\n17 \n\n\n<>\n\nRM0090 Rev 21\n1617/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nNOR Flash memory, non-multiplexed I/Os\n \nThe maximum capacity is 512 Mbits (26 address lines).\nNOR Flash memory, 16-bit multiplexed I/Os\n \nThe maximum capacity is 512 Mbits.\nPSRAM/SRAM, non-multiplexed I/Os\n \nTable 265. Non-multiplexed I/O NOR Flash memory\nFMC signal name\nI/O\nFunction\nCLK \nO \nClock (for synchronous access) \nA[25:0] \nO \nAddress bus \nD[31:0] \nI/O \nBidirectional data bus \nNE[x]\nO \nChip Select, x = 1..4\nNOE\nO \nOutput enable \nNWE\nO \nWrite enable \nNL(=NADV)\nO \nLatch enable (this signal is called address \nvalid, NADV, by some NOR Flash devices) \nNWAIT\nI \nNOR Flash wait input signal to the FMC \nTable 266. 16-bit multiplexed I/O NOR Flash memory\nFMC signal name \nI/O \nFunction \nCLK \nO \nClock (for synchronous access) \nA[25:16] \nO \nAddress bus \nAD[15:0] \nI/O \n16-bit multiplexed, bidirectional address/data bus (the 16-bit address \nA[15:0] and data D[15:0] are multiplexed on the databus)\nNE[x]\nO \nChip Select, x = 1..4\nNOE\nO \nOutput enable \nNWE\nO \nWrite enable \nNL(=NADV)\nO \nLatch enable (this signal is called address valid, NADV, by some NOR \nFlash devices) \nNWAIT\nI \nNOR Flash wait input signal to the FMC \nTable 267. Non-multiplexed I/Os PSRAM/SRAM\nFMC signal name\nI/O \nFunction \nCLK \nO \nClock (only for PSRAM synchronous access) \nA[25:0] \nO \nAddress bus \nD[31:0] \nI/O \nData bidirectional bus \n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1618/1757\nRM0090 Rev 21\nThe maximum capacity is 512 Mbits.\nPSRAM, 16-bit multiplexed I/Os\n \nThe maximum capacity is 512 Mbits (26 address lines).\n37.5.2 \nSupported memories and transactions\nTable 269 below shows an example of the supported devices, access modes and \ntransactions when the memory data bus is 16-bit wide for NOR Flash memory, PSRAM and \nSRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in \nthis example.\nNE[x]\nO \nChip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. \nCRAM))\nNOE\nO \nOutput enable \nNWE\nO \nWrite enable \nNL(= NADV)\nO \nAddress valid only for PSRAM input (memory signal name: NADV) \nNWAIT\nI \nPSRAM wait input signal to the FMC \nNBL[3] \nO \nByte3 Upper byte enable (memory signal name: NUB) \nNBL[2] \nO \nByte2 Lowed byte enable (memory signal name: NLB) \nNBL[1] \nO \nByte1 Upper byte enable (memory signal name: NLB) \nNBL[0] \nO \nByte0 Lower byte enable (memory signal name: NLB) \nTable 268. 16-Bit multiplexed I/O PSRAM\nFMC signal name\nI/O \nFunction \nCLK \nO \nClock (for synchronous access) \nA[25:16] \nO \nAddress bus \nAD[15:0] \nI/O \n16-bit multiplexed, bidirectional address/data bus (the 16-bit address \nA[15:0] and data D[15:0] are multiplexed on the databus)\nNE[x]\nO \nChip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. \nCRAM))\nNOE\nO \nOutput enable \nNWE\nO \nWrite enable \nNL(= NADV)\nO \nAddress valid PSRAM input (memory signal name: NADV) \nNWAIT\nI \nPSRAM wait input signal to the FMC \nNBL[1] \nO \nUpper byte enable (memory signal name: NUB) \nNBL[0] \nO \nLowed byte enable (memory signal name: NLB) \nTable 267. Non-multiplexed I/Os PSRAM/SRAM (continued)\nFMC signal name\nI/O \nFunction \n\n\n<>\n\nRM0090 Rev 21\n1619/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n Table 269. NOR Flash/PSRAM: Example of supported memories and transactions\nDevice\nMode\nR/W\nAHB \ndata \nsize\nMemory \ndata size\nAllowed/\nnot \nallowed \nComments\nNOR Flash \n(muxed I/Os \nand nonmuxed \nI/Os) \nAsynchronous\nR \n8 \n16 \nY \n-\nAsynchronous \nW \n8 \n16 \nN \n-\nAsynchronous\nR \n16 \n16 \nY \n-\nAsynchronous\nW \n16 \n16 \nY \n-\nAsynchronous \nR \n32 \n16 \nY \nSplit into 2 FMC accesses \nAsynchronous \nW \n32 \n16 \nY \nSplit into 2 FMC accesses \nAsynchronous \npage \nR \n-\n16 \nN \nMode is not supported \nSynchronous \nR \n8 \n16 \nN \n-\nSynchronous \nR \n16 \n16 \nY \n-\nSynchronous \nR \n32 \n16 \nY \n-\nPSRAM \n(multiplexed \nI/Os and non-\nmultiplexed \nI/Os)\nAsynchronous\nR \n8 \n16 \nY \n-\nAsynchronous \nW \n8 \n16 \nY \nUse of byte lanes NBL[1:0] \nAsynchronous\nR \n16 \n16 \nY \n-\nAsynchronous\nW \n16 \n16 \nY \n-\nAsynchronous \nR \n32 \n16 \nY \nSplit into 2 FMC accesses \nAsynchronous \nW \n32 \n16 \nY \nSplit into 2 FMC accesses \nAsynchronous \npage \nR \n-\n16 \nN \nMode is not supported \nSynchronous \nR \n8 \n16 \nN \n-\nSynchronous \nR \n16 \n16 \nY \n-\nSynchronous \nR \n32 \n16 \nY \n-\nSynchronous\nW\n8\n16\nY\nUse of byte lanes NBL[1:0]\nSynchronous\nW\n16/32\n16\nY\n-\nSRAM and \nROM\nAsynchronous \nR \n8 / 16 \n16\nY \n-\nAsynchronous \nW \n8 / 16 \n16\nY \nUse of byte lanes NBL[1:0] \nAsynchronous \nR \n32 \n16\nY \nSplit into 2 FMC accesses \nAsynchronous \nW \n32 \n16\nY \nSplit into 2 FMC accesses \nUse of byte lanes NBL[1:0]\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1620/1757\nRM0090 Rev 21\n37.5.3 \nGeneral timing rules\nSignals synchronization\n•\nAll controller output signals change on the rising edge of the internal clock (HCLK)\n•\nIn synchronous mode (read or write), all output signals change on the rising edge of \nHCLK. Whatever the CLKDIV value, all outputs change as follows:\n–\nNOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the \nfalling edge of FMC_CLK clock.\n–\nNOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising \nedge of FMC_CLK clock.\n37.5.4 \nNOR Flash/PSRAM controller asynchronous transactions\nAsynchronous static memories (NOR Flash, PSRAM, SRAM)\n•\nSignals are synchronized by the internal clock HCLK. This clock is not issued to the \nmemory\n•\nThe FMC always samples the data before de-asserting the NOE signal. This \nguarantees that the memory data hold timing constraint is met (minimum Chip Enable \nhigh to data transition is usually 0 ns)\n•\nIf the extended mode is enabled (EXTMOD bit is set in the FMC_BCRx register), up to \nfour extended modes (A, B, C and D) are available. It is possible to mix A, B, C and D \nmodes for read and write operations. For example, read operation can be performed in \nmode A and write in mode B.\n•\nIf the extended mode is disabled (EXTMOD bit is reset in the FMC_BCRx register), the \nFMC can operate in Mode1 or Mode2 as follows:\n–\nMode 1 is the default mode when SRAM/PSRAM memory type is selected \n(MTYP[1:0] = 0x0 or 0x01 in the FMC_BCRx register)\n–\nMode 2 is the default mode when NOR memory type is selected \n(MTYP[1:0] = 0x10 in the FMC_BCRx register).\n\n\n<>\n\nRM0090 Rev 21\n1621/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nMode 1 - SRAM/PSRAM (CRAM)\nThe next figures show the read and write transactions for the supported modes followed by \nthe required configuration of FMC _BCRx, and FMC_BTRx/FMC_BWTRx registers. \nFigure 458. Mode1 read access waveforms\nFigure 459. Mode1 write access waveforms\nA[25:0]\nNOE\nADDSET\nDATAST \nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\nHCLK cycles\nNWE\nNBL[3:0]\ndata driven\nby memory\nMS30452V1\nHigh\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\nHCLK cycles\nNWE\nNBL[3:0]\ndata driven by FSMC\nMS30453V1\n1HCLK\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1622/1757\nRM0090 Rev 21\nThe one HCLK cycle at the end of the write transaction helps guarantee the address and \ndata hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the \nDATAST value must be greater than zero (DATAST > 0).\n \n \nTable 270. FMC_BCRx bit fields\nBit \nnumber\nBit name\nValue to set\n31-21\nReserved\n0x000\n20\nCCLKEN\nAs needed\n19\nCBURSTRW\n0x0 (no effect in asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect in asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at \n0.\n14\nEXTMOD\n0x0\n13\nWAITEN\n0x0 (no effect in asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0\n7 \nReserved\n0x1\n6 \nFACCEN\nDon’t care\n5-4 \nMWID\nAs needed\n3-2 \nMTYP[1:0]\nAs needed, exclude 0x2 (NOR Flash memory)\n1 \nMUXE\n0x0\n0 \nMBKEN \n0x1\nTable 271. FMC_BTRx bit fields\nBit \nnumber\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\nDon’t care\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST+1 HCLK cycles for \nwrite accesses, DATAST HCLK cycles for read accesses). \n\n\n<>\n\nRM0090 Rev 21\n1623/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nMode A - SRAM/PSRAM (CRAM) OE toggling\nFigure 460. ModeA read access waveforms\n1.\nNBL[3:0] are driven low during the read access\n7-4\nADDHLD\nDon’t care\n3-0\nADDSET\nDuration of the first access phase (ADDSET HCLK cycles).\nMinimum value for ADDSET is 0.\nTable 271. FMC_BTRx bit fields (continued)\nBit \nnumber\nBit name\nValue to set\nA[25:0]\nNOE\nADDSET \nDATAST\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\nHCLK cycles\nNWE\nNBL[3:0]\ndata driven\nby memory\nMS30454V1\nHigh\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1624/1757\nRM0090 Rev 21\nFigure 461. ModeA write access waveforms\nThe differences compared with mode1 are the toggling of NOE and the independent read \nand write timings.\n \nTable 272. FMC_BCRx bit fields\nBit \nnumber\nBit name \nValue to set\n31-21\nReserved\n0x000\n20\nCCLKEN\nAs needed\n19\nCBURSTRW\n0x0 (no effect in asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect in asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at \n0.\n14 \nEXTMOD\n0x1\n13\nWAITEN\n0x0 (no effect in asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0\n7 \nReserved\n0x1\n6 \nFACCEN\nDon’t care\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\nHCLK cycles\nNWE\nNBL[3:0]\ndata driven by FSMC\nMS30455V1\n1HCLK\n\n\n<>\n\nRM0090 Rev 21\n1625/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n \n \n5-4 \nMWID \nAs needed\n3-2 \nMTYP[1:0]\nAs needed, exclude 0x2 (NOR Flash memory)\n1 \nMUXEN\n0x0\n0 \nMBKEN\n0x1\nTable 273. FMC_BTRx bit fields\nBit \nnumber\nBit name \nValue to set \n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x0\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for read \naccesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for read \naccesses.\nMinimum value for ADDSET is 0.\nTable 274. FMC_BWTRx bit fields\nBit \nnumber\nBit name \nValue to set \n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x0\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for write \naccesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for write \naccesses.\nMinimum value for ADDSET is 0.\nTable 272. FMC_BCRx bit fields (continued)\nBit \nnumber\nBit name \nValue to set\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1626/1757\nRM0090 Rev 21\nMode 2/B - NOR Flash\nFigure 462. Mode2 and mode B read access waveforms\n1.\nNBL[3:0] are driven low during the read access\nFigure 463. Mode2 write access waveforms\nA[25:0]\nNOE\nADDSET \nDATAST\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven\nby memory\nMS30456V1\nHigh\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\nHCLK cycles\nNWE\nNADV\ndata driven by FSMC\nMS30457V1\n1HCLK\n\n\n<>\n\nRM0090 Rev 21\n1627/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nFigure 464. ModeB write access waveforms \nThe differences with mode1 are the toggling of NWE and the independent read and write \ntimings when extended mode is set (Mode B).\n \nTable 275. FMC_BCRx bit fields\nBit \nnumber\nBit name \nValue to set \n31-21\nReserved\n0x000\n20\nCCLKEN\nAs needed\n19\nCBURSTRW\n0x0 (no effect in asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect in asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at \n0.\n14 \nEXTMOD\n0x1 for mode B, 0x0 for mode 2\n13\nWAITEN\n0x0 (no effect in asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0 \n7 \nReserved\n0x1\n6 \nFACCEN\n0x1\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven by FSMC\nMS30458V1.\n1HCLK\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1628/1757\nRM0090 Rev 21\n \n \nNote:\nThe FMC_BWTRx register is valid only if the extended mode is set (mode B), otherwise its \ncontent is don’t care.\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[1:0]\n0x2 (NOR Flash memory)\n1 \nMUXEN\n0x0 \n0 \nMBKEN\n0x1 \nTable 276. FMC_BTRx bit fields\nBit number\nBit name \nValue to set \n31-30\nReserved\n0x0\n29-28\nACCMOD\n0x1 if extended mode is set\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the access second phase (DATAST HCLK cycles) for \nread accesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the access first phase (ADDSET HCLK cycles) for read \naccesses. Minimum value for ADDSET is 0.\nTable 277. FMC_BWTRx bit fields\nBit number\nBit name \nValue to set \n31-30\nReserved\n0x0\n29-28\nACCMOD\n0x1 if extended mode is set\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the access second phase (DATAST HCLK cycles) for \nwrite accesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the access first phase (ADDSET HCLK cycles) for write \naccesses. Minimum value for ADDSET is 0.\nTable 275. FMC_BCRx bit fields (continued)\nBit \nnumber\nBit name \nValue to set \n\n\n<>\n\nRM0090 Rev 21\n1629/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nMode C - NOR Flash - OE toggling\nFigure 465. ModeC read access waveforms \nFigure 466. ModeC write access waveforms \nThe differences compared with mode1 are the toggling of NOE and the independent read \nand write timings.\nA[25:0]\nNOE\nADDSET \nDATAST\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven\nby memory\nMS30459V1\nHigh\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven by FSMC\nMS30460V1\n1HCLK\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1630/1757\nRM0090 Rev 21\n \n \nTable 278. FMC_BCRx bit fields\nBit No.\nBit name\nValue to set\n31-21\nReserved\n0x000\n20\nCCLKEN\nAs needed\n19\nCBURSTRW\n0x0 (no effect in asynchronous mode)\n18:16\nReserved\n0x0 (no effect in asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at 0.\n14 \nEXTMOD\n0x1\n13\nWAITEN\n0x0 (no effect in asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0 \n7 \nReserved\n0x1\n6 \nFACCEN\n0x1\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[1:0]\n0x02 (NOR Flash memory)\n1 \nMUXEN\n0x0 \n0 \nMBKEN\n0x1 \nTable 279. FMC_BTRx bit fields\nBit No.\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x2\n27-24\nDATLAT\n0x0\n23-20\nCLKDIV\n0x0\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for \nread accesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for read \naccesses. Minimum value for ADDSET is 0.\n\n\n<>\n\nRM0090 Rev 21\n1631/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n \nMode D - asynchronous access with extended address\nFigure 467. ModeD read access waveforms\nTable 280. FMC_BWTRx bit fields\nBit No.\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x2\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for \nwrite accesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for write \naccesses. Minimum value for ADDSET is 0.\nA[25:0]\nNOE\nADDSET \nDATAST\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven\nby memory\nMS30461V1\nHigh\nADDHLD\nHCLK cycles\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1632/1757\nRM0090 Rev 21\nFigure 468. ModeD write access waveforms\nThe differences with mode1 are the toggling of NOE that goes on toggling after NADV \nchanges and the independent read and write timings.\n \nTable 281. FMC_BCRx bit fields\nBit No.\nBit name \nValue to set \n31-21\nReserved\n0x000\n20\nCCLKEN\nAs needed\n19\nCBURSTRW\n0x0 (no effect in asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect in asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep \nat 0.\n14 \nEXTMOD\n0x1\n13\nWAITEN\n0x0 (no effect in asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0 \n7 \nReserved\n0x1\n6 \nFACCEN\nSet according to memory support\n5-4 \nMWID\nAs needed\nA[25:0]\nNOE\nADDSET \n(DATAST+ 1)\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\nHCLK cycles\nNWE\nNADV\ndata driven by FSMC\nMS30462V1\n1HCLK\nADDHLD\nHCLK cycles\n\n\n<>\n\nRM0090 Rev 21\n1633/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n \n \n3-2 \nMTYP[1:0]\nAs needed\n1 \nMUXEN\n0x0 \n0 \nMBKEN\n0x1 \nTable 282. FMC_BTRx bit fields\nBit No.\nBit name\nValue to set \n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x3\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for \nread accesses. \n7-4\nADDHLD\nDuration of the middle phase of the read access (ADDHLD HCLK \ncycles) \n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for read \naccesses. Minimum value for ADDSET is 1.\nTable 283. FMC_BWTRx bit fields\nBit No.\nBit name\nValue to set \n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x3\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST + 1 HCLK cycles) for \nwrite accesses. \n7-4\nADDHLD\nDuration of the middle phase of the write access (ADDHLD HCLK \ncycles) \n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for write \naccesses. Minimum value for ADDSET is 1.\nTable 281. FMC_BCRx bit fields (continued)\nBit No.\nBit name \nValue to set \n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1634/1757\nRM0090 Rev 21\nMuxed mode - multiplexed asynchronous access to NOR Flash memory\nFigure 469. Muxed read access waveforms\nFigure 470. Muxed write access waveforms\nThe difference with mode D is the drive of the lower address byte(s) on the data bus.\nA[25:16]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nAD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven by FSMC\nai15569\n1HCLK\nADDHLD\nHCLK cycles\nLower address\n\n\n<>\n\nRM0090 Rev 21\n1635/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n \n \nWAIT management in asynchronous accesses\nIf the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to \naccept or to provide data, the ASYNCWAIT bit has to be set in FMC_BCRx register.\nTable 284. FMC_BCRx bit fields\nBit No.\nBit name\nValue to set\n31-21\nReserved\n0x000\n20\nCCLKEN\nAs needed\n19\nCBURSTRW\n0x0 (no effect in asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect in asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at \n0.\n14 \nEXTMOD\n0x0\n13\nWAITEN\n0x0 (no effect in asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0 \n7 \nReserved\n0x1\n6 \nFACCEN\n0x1\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[1:0]\n0x2 (NOR Flash memory)\n1 \nMUXEN\n0x1\n0 \nMBKEN\n0x1 \nTable 285. FMC_BTRx bit fields\nBit No.\nBit name \nValue to set \n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x0\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles for \nread accesses and DATAST+1 HCLK cycles for write accesses). \n7-4\nADDHLD\nDuration of the middle phase of the access (ADDHLD HCLK cycles).\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles). \nMinimum value for ADDSET is 1.\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1636/1757\nRM0090 Rev 21\nIf the WAIT signal is active (high or low depending on the WAITPOL bit), the second access \nphase (Data setup phase), programmed by the DATAST bits, is extended until WAIT \nbecomes inactive. Unlike the data setup phase, the first access phases (Address setup and \nAddress hold phases), programmed by the ADDSET[3:0] and ADDHLD bits, are not WAIT \nsensitive and so they are not prolonged.\nThe data setup phase must be programmed so that WAIT can be detected 4 HCLK cycles \nbefore the end of the memory transaction. The following cases must be considered:\n1.\nThe memory asserts the WAIT signal aligned to NOE/NWE which toggles:\n2. \nThe memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):\nif \nthen:\notherwise\nwhere max_wait_assertion_time is the maximum time taken by the memory to assert \nthe WAIT signal once NEx/NOE/NWE is low.\nFigure 471 and Figure 472 show the number of HCLK clock cycles that are added to the \nmemory access phase after WAIT is released by the asynchronous memory (independently \nof the above cases).\nFigure 471. Asynchronous wait during a read access waveforms\n1.\nNWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register. \nDATAST\n4\nHCLK\n×\n(\n)\nmax_wait_assertion_time\n+\n≥\nmax_wait_assertion_time\naddress_phase\nhold_phase\n+\n>\nDATAST\n4\nHCLK\n×\n(\n)\nmax_wait_assertion_time\naddress_phase\n–\nhold_phase\n–\n(\n)\n+\n≥\nDATAST\n4\nHCLK\n×\n≥\nA[25:0]\nNOE\n4HCLK \nMemory transaction\nD[15:0]\nNEx\ndata driven by memory\nMS30463V2\naddress phase\ndata setup phase\nNWAIT\ndon’t care\ndon’t care\n\n\n<>\n\nRM0090 Rev 21\n1637/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nFigure 472. Asynchronous wait during a write access waveforms\n1.\nNWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register. \n37.5.5 \nSynchronous transactions\nThe memory clock, FMC_CLK, is a submultiple of HCLK. It depends on the value of \nCLKDIV and the MWID/ AHB data size, following the formula given below:\nIf MWID is 16 or 8 bits, the FMC_CLK divider ratio is always defined by the programmed \nCLKDIV value.\nIf MWID is 32 bits, the FMC_CLK divider ratio depends also on AHB data size.\nExample: \n•\nIf CLKDIV=1, MWID=32 bits, AHB data size=8 bits, FMC_CLK=HCLK/4.\n•\nIf CLKDIV=1, MWID=16 bits, AHB data size=8 bits, FMC_CLK=HCLK/2.\nNOR Flash memories specify a minimum time from NADV assertion to CLK high. To meet \nthis constraint, the FMC does not issue the clock to the memory during the first internal \nclock cycle of the synchronous access (before NADV assertion). This guarantees that the \nrising edge of the memory clock occurs in the middle of the NADV low pulse.\nData latency versus NOR memory latency\nThe data latency is the number of cycles to wait before sampling the data. The DATLAT \nvalue must be consistent with the latency value specified in the NOR Flash configuration \nA[25:0]\nNWE\nMemory transaction\nD[15:0]\nNEx\ndata driven by FSMC\nMS30464V2\n3HCLK \naddress phase\ndata setup phase\n1HCLK \nNWAIT\ndon’t care\ndon’t care\nFMC_CLK divider ratio\nmax CLKDIV\n1\n+\nMWID AHB data size\n(\n)\n(\n,\n)\n=\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1638/1757\nRM0090 Rev 21\nregister. The FMC does not include the clock cycle when NADV is low in the data latency \ncount.\nCaution:\nSome NOR Flash memories include the NADV Low cycle in the data latency count, so that \nthe exact relation between the NOR Flash latency and the FMC DATLAT parameter can be \neither:\n•\nNOR Flash latency = (DATLAT + 2) CLK clock cycles\n•\nor NOR Flash latency = (DATLAT + 3) CLK clock cycles\nSome recent memories assert NWAIT during the latency phase. In such cases DATLAT can \nbe set to its minimum value. As a result, the FMC samples the data and waits long enough \nto evaluate if the data are valid. Thus the FMC detects when the memory exits latency and \nreal data are processed.\nOther memories do not assert NWAIT during latency. In this case the latency must be set \ncorrectly for both the FMC and the memory, otherwise invalid data are mistaken for good \ndata, or valid data are lost in the initial phase of the memory access.\nSingle-burst transfer\nWhen the selected bank is configured in burst mode for synchronous accesses, if for \nexample an AHB single-burst transaction is requested on 16-bit memories, the FMC \nperforms a burst transaction of length 1 (if the AHB transfer is 16 bits), or length 2 (if the \nAHB transfer is 32 bits) and de-assert the Chip Select signal when the last data is strobed.\nSuch transfers are not the most efficient in terms of cycles compared to asynchronous read \noperations. Nevertheless, a random asynchronous access would first require to re-program \nthe memory access mode, which would altogether last longer.\nCross boundary page for Cellular RAM 1.5\nCellular RAM 1.5 does not allow burst access to cross the page boundary. The FMC \ncontroller allows to split automatically the burst access when the memory page size is \nreached by configuring the CPSIZE bits in the FMC_BCR1 register following the memory \npage size.\nWait management\nFor synchronous NOR Flash memories, NWAIT is evaluated after the programmed latency \nperiod, which corresponds to (DATLAT+2) CLK clock cycles.\nIf NWAIT is active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait \nstates are inserted until NWAIT is inactive (high level when WAITPOL = 0, low level when \nWAITPOL = 1).\nWhen NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1) \nor on the next clock edge (bit WAITCFG = 0).\nDuring wait-state insertion via the NWAIT signal, the controller continues to send clock \npulses to the memory, keeping the Chip Select and output enable signals valid. It does not \nconsider the data as valid.\nIn burst mode, there are two timing configurations for the NOR Flash NWAIT signal:\n•\nThe Flash memory asserts the NWAIT signal one data cycle before the wait state \n(default after reset).\n•\nThe Flash memory asserts the NWAIT signal during the wait state\n\n\n<>\n\nRM0090 Rev 21\n1639/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nThe FMC supports both NOR Flash wait state configurations, for each Chip Select, thanks \nto the WAITCFG bit in the FMC_BCRx registers (x = 0..3).\nFigure 473. Wait configuration waveforms\nFigure 474. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM)\n1.\nByte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, \naddr[15:0]\ndata\ndata\naddr[25:16]\nMemory transaction = burst of 4 half words\nHCLK\nCLK\nA[25:16]\nNADV\nNWAIT\n(WAITCFG = 1)\nA/D[15:0]\ninserted wait state\ndata\nNWAIT\n(WAITCFG = 0)\nai15798c\nAddr[15:0]\ndata\ndata\naddr[25:16]\nMemory transaction = burst of 4 half words\nHCLK\nCLK\nA[25:16]\nNEx\nNOE\nNWE\nHigh\nNADV\nNWAIT\n(WAITCFG=\n0)\nA/D[15:0]\n1 clock\ncycle\n1 clock\ncycle\n(DATLAT + 2)\ninserted wait state\nData strobes\nai17723f\nCLK cycles\ndata\ndata\nData strobes\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1640/1757\nRM0090 Rev 21\nthey are held low.\n \n \nTable 286. FMC_BCRx bit fields\nBit No.\nBit name\nValue to set\n31-21 \nReserved\n0x000\n20\nCCLKEN\nAs needed\n19\nCBURSTRW\nNo effect on synchronous read\n18-16\nCPSIZE\nAs needed (0x1 for CRAM 1.5)\n15\nASYNCWAIT\n0x0\n14 \nEXTMOD\n0x0\n13\nWAITEN\nto be set to 1 if the memory supports this feature, to be kept at 0 \notherwise\n12\nWREN\nno effect on synchronous read\n11\nWAITCFG\nto be set according to memory\n10\nWRAPMOD\n0x0\n9 \nWAITPOL\nto be set according to memory\n8 \nBURSTEN\n0x1\n7 \nReserved\n0x1\n6 \nFACCEN\nSet according to memory support (NOR Flash memory)\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[1:0]\n0x1 or 0x2\n1 \nMUXEN\nAs needed\n0 \nMBKEN\n0x1 \nTable 287. FMC_BTRx bit fields\nBit No.\nBit name\nValue to set\n31:30\nReserved\n0x0\n29:28\nACCMOD\n0x0\n27-24\nDATLAT\nData latency\n27-24\nDATLAT\nData latency\n23-20\nCLKDIV\n0x0 to get CLK = HCLK (Not supported)\n0x1 to get CLK = 2 × HCLK\n..\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK)\n15-8\nDATAST\nDon’t care\n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDon’t care\n\n\n<>\n\nRM0090 Rev 21\n1641/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nFigure 475. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)\n1.\nThe memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed \nto 0.\n2.\nByte Lane (NBL) outputs are not shown, they are held low while NEx is active.\n \nAddr[15:0]\ndata\naddr[25:16]\nMemory transaction = burst of 2 half words\nHCLK\nCLK\nA[25:16]\nNEx\nNOE\nNWE\nHi-Z\nNADV\nNWAIT\n(WAITCFG = 0)\nA/D[15:0]\n1 clock 1 clock\n(DATLAT + 2)\ninserted wait state\nai14731f\n CLK cycles\ndata\nTable 288. FMC_BCRx bit fields\nBit No.\nBit name\nValue to set\n31-20\nReserved\n0x000\n20\nCCLKEN\nAs needed\n19\nCBURSTRW\n0x1\n18-16\nCPSIZE\nAs needed (0x1 for CRAM 1.5)\n15\nASYNCWAIT\n0x0\n14 \nEXTMOD\n0x0\n13\nWAITEN\nto be set to 1 if the memory supports this feature, to be kept at 0 \notherwise.\n12\nWREN\n0x1\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1642/1757\nRM0090 Rev 21\n \n11\nWAITCFG\n0x0\n10\nWRAPMOD\n0x0\n9 \nWAITPOL\nto be set according to memory\n8 \nBURSTEN\nno effect on synchronous write\n7 \nReserved\n0x1\n6 \nFACCEN\nSet according to memory support\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[1:0]\n0x1\n1 \nMUXEN\nAs needed\n0 \nMBKEN\n0x1 \nTable 289. FMC_BTRx bit fields\nBit No.\nBit name\nValue to set\n31-30\nReserved\n0x0\n29:28\nACCMOD\n0x0\n27-24\nDATLAT\nData latency\n23-20\nCLKDIV\n0x0 to get CLK = HCLK (not supported)\n0x1 to get CLK = 2 × HCLK\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK)\n15-8\nDATAST\nDon’t care\n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDon’t care\nTable 288. FMC_BCRx bit fields (continued)\nBit No.\nBit name\nValue to set\n\n\n<>\n\nRM0090 Rev 21\n1643/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n37.5.6 \nNOR/PSRAM controller registers\nSRAM/NOR-Flash chip-select control registers 1..4 (FMC_BCR1..4)\nAddress offset: 8 * (x – 1), x = 1...4\nReset value: 0x0000 30DB for Bank1 and 0x0000 30D2 for Bank 2 to 4\nThis register contains the control information of each memory bank, used for SRAMs, \nPSRAM and NOR Flash memories.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCCLKEN\nCBURSTRW\nCPSIZE[2:0]\nASCYCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[1:0]\nMUXEN\nMBKEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31: 21 Reserved, must be kept at reset value\nBit 20 CCLKEN: Continuous Clock Enable.\nThis bit enables the FMC_CLK clock output to external memory devices.\n0: The FMC_CLK is only generated during the synchronous memory access (read/write \ntransaction). The FMC_CLK clock ratio is specified by the programmed CLKDIV value in the \nFMC_BCRx register (default after reset) .\n1: The FMC_CLK is generated continuously during asynchronous and synchronous access. The \nFMC_CLK clock is activated when the CCLKEN is set.\nNote: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the \nFMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the \nFMC_CLK continuous clock.\nNote: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the \nFMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care.\nNote: If the synchronous mode is used and CCLKEN bit is set, the synchronous memories \nconnected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in \nthe FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)\nBit 19 CBURSTRW: Write burst enable.\nFor PSRAM (CRAM) operating in burst mode, the bit enables synchronous accesses during write \noperations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx \nregister.\n0: Write operations are always performed in asynchronous mode\n1: Write operations are performed in synchronous mode.\nBits 18:16 CPSIZE[2:0]: CRAM page size.\nThese are used for Cellular RAM 1.5 which does not allow burst access to cross the address \nboundaries between pages. When these bits are configured, the FMC controller splits automatically \nthe burst access when the memory page size is reached (refer to memory datasheet for page size).\n000: No burst split when crossing page boundary (default after reset)\n001: 128 bytes\n010: 256 bytes\n011: 512 bytes\n100: 1024 bytes\nOthers: reserved\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1644/1757\nRM0090 Rev 21\nBit 15 ASYNCWAIT: Wait signal during asynchronous transfers\nThis bit enables/disables the FMC to use the wait signal even during an asynchronous protocol.\n0: NWAIT signal is not taken in to account when running an asynchronous protocol (default after \nreset)\n1: NWAIT signal is taken in to account when running an asynchronous protocol\nBit 14 EXTMOD: Extended mode enable.\nThis bit enables the FMC to program the write timings for non-multiplexed asynchronous accesses \ninside the FMC_BWTR register, thus resulting in different timings for read and write operations.\n0: values inside FMC_BWTR register are not taken into account (default after reset)\n1: values inside FMC_BWTR register are taken into account\nNote: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows:\n–\nMode 1 is the default mode when the SRAM/PSRAM memory type is selected \n(MTYP[1:0] =0x0 or 0x01)\n–\nMode 2 is the default mode when the NOR memory type is selected (MTYP[1:0] = 0x10).\nBit 13 WAITEN: Wait enable bit.\nThis bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in \nsynchronous mode.\n0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the \nprogrammed Flash latency period)\n1: NWAIT signal is enabled (its level is taken into account after the programmed latency period to \ninsert wait states if asserted) (default after reset)\nBit 12 WREN: Write enable bit.\nThis bit indicates whether write operations are enabled/disabled in the bank by the FMC:\n0: Write operations are disabled in the bank by the FMC, an AHB error is reported,\n1: Write operations are enabled for the bank by the FMC (default after reset).\nBit 11 WAITCFG: Wait timing configuration.\nThe NWAIT signal indicates whether the data from the memory are valid or if a wait state must be \ninserted when accessing the memory in synchronous mode. This configuration bit determines if \nNWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:\n0: NWAIT signal is active one data cycle before wait state (default after reset),\n1: NWAIT signal is active during wait state (not used for PSRAM).\nBit 10 WRAPMOD: Wrapped burst mode support.\nDefines whether the controller splits or not an AHB burst wrap access into two linear accesses. Valid \nonly when accessing memories in burst mode\n0: Direct wrapped burst is not enabled (default after reset),\n1: Direct wrapped burst is enabled.\nNote: This bit has no effect as the CPU and DMA cannot generate wrapping burst transfers.\nBit 9 WAITPOL: Wait signal polarity bit.\nDefines the polarity of the wait signal from memory used for either in synchronous or asynchronous \nmode:\n0: NWAIT active low (default after reset),\n1: NWAIT active high.\nBit 8 BURSTEN: Burst enable bit.\nThis bit enables/disables synchronous accesses during read operations. It is valid only for \nsynchronous memories operating in burst mode:\n0: Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode. \n1: Burst mode enable. Read accesses are performed in synchronous mode. \nBit 7 Reserved, must be kept at reset value\n\n\n<>\n\nRM0090 Rev 21\n1645/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nSRAM/NOR-Flash chip-select timing registers 1..4 (FMC_BTR1..4)\nAddress offset: 0x04 + 8 * (x – 1), x = 1..4\nReset value: 0x0FFF FFFF\nReset value: 0x0FFF FFFF\nFMC_BTRx bits are written by software to add a delay at the end of a read /write \ntransaction. This delay allows matching the minimum time between consecutive \ntransactions (tEHEL from NEx high to FMC_NEx low) and the maximum time required by the \nmemory to free the data bus after a read access (tEHQZ).\nThis register contains the control information of each memory bank, used for SRAMs, \nPSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then \nthis register is partitioned for write and read access, that is, 2 registers are available: one to \nconfigure read accesses (this register) and one to configure write accesses (FMC_BWTRx \nregisters).\nBit 6 FACCEN: Flash access enable\nEnables NOR Flash memory access operations.\n0: Corresponding NOR Flash memory access is disabled\n1: Corresponding NOR Flash memory access is enabled (default after reset)\nBits 5:4 MWID[1:0]: Memory data bus width.\nDefines the external memory device width, valid for all type of memories.\n00: 8 bits,\n01: 16 bits (default after reset),\n10: 32 bits,\n11: reserved, do not use.\nBits 3:2 MTYP[1:0]: Memory type.\nDefines the type of external memory attached to the corresponding memory bank:\n00: SRAM (default after reset for Bank 2...4)\n01: PSRAM (CRAM)\n10: NOR Flash/OneNAND Flash (default after reset for Bank 1)\n11: reserved\nBit 1 MUXEN: Address/data multiplexing enable bit.\nWhen this bit is set, the address and data values are multiplexed on the data bus, valid only with \nNOR and PSRAM memories:\n0: Address/Data nonmultiplexed\n1: Address/Data multiplexed on databus (default after reset)\nBit 0 MBKEN: Memory bank enable bit.\nEnables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a \ndisabled bank causes an ERROR on AHB bus.\n0: Corresponding memory bank is disabled\n1: Corresponding memory bank is enabled\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1646/1757\nRM0090 Rev 21\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV3:0]\nBUSTURN3:0]\nDATAST7:0]\nADDHLD3:0]\nADDSET[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value\nBits 29:28 ACCMOD[1:0]: Access mode\nSpecifies the asynchronous access modes as shown in the timing diagrams. These bits are \ntaken into account only when the EXTMOD bit in the FMC_BCRx register is 1.\n00: access mode A\n01: access mode B\n10: access mode C\n11: access mode D\nBits 27:24 DATLAT[3:0]: Data latency for synchronous NOR Flash memory (see note below bit \ndescription table)\nFor synchronous accesses with read/write burst mode enabled (BURSTEN / CBURSTRW bits \nset), this field defines the number of memory clock cycles (+2) to issue to the memory before \nreading/writing the first data. This timing parameter is not expressed in HCLK periods, but in \nFMC_CLK periods. For asynchronous accesses, this value is don't care. \n0000: Data latency of 2 CLK clock cycles for first burst access\n1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)\nBits 23:20 CLKDIV[3:0]: Clock divide ratio (for FMC_CLK signal)\nDefines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles:\n0000: Reserved\n0001: FMC_CLK period = 2 × HCLK periods\n0010: FMC_CLK period = 3 × HCLK periods\n1111: FMC_CLK period = 16 × HCLK periods (default value after reset) \nIn asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care.\nNote: Refer to section 37.5.5: Synchronous transactions for FMC_CLK divider ratio formula)\n\n\n<>\n\nRM0090 Rev 21\n1647/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nBits 19:16 BUSTURN[3:0]: Bus turnaround phase duration\nThese bits are written by software to add a delay at the end of a write-to-read (and read-to-\nwrite) transaction. This delay allows to match the minimum time between consecutive \ntransactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory \nto free the data bus after a read access (tEHQZ). The programmed bus turnaround delay is \ninserted between an asynchronous read (muxed or mode D) or write transaction and any \nother asynchronous /synchronous read or write to or from a static bank. The bank can be the \nsame or different in case of read, in case of write the bank can be different except for muxed \nor mode D.\nIn some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is \nfixed as follows:\n• The bus turnaround delay is not inserted between two consecutive asynchronous write \ntransfers to the same static memory bank except for modes muxed and D.\n• There is a bus turnaround delay of 1 FMC clock cycle between:\n–Two consecutive asynchronous read transfers to the same static memory bank except for \nmodes muxed and D. \n–An asynchronous read to an asynchronous or synchronous write to any static bank or \ndynamic bank except for modes muxed and D.\n–An asynchronous (modes 1, 2, A, B or C) read and a read from another static bank.\n• There is a bus turnaround delay of 2 FMC clock cycle between:\n–Two consecutive synchronous writes (burst or single) to the same bank.\n–A synchronous write (burst or single) access and an asynchronous write or read transfer to \nor from static memory bank (the bank can be the same or different for the case of read.\n–Two consecutive synchronous reads (burst or single) followed by any \nsynchronous/asynchronous read or write from/to another static memory bank.\n• There is a bus turnaround delay of 3 FMC clock cycle between:\n–Two consecutive synchronous writes (burst or single) to different static bank.\n–A synchronous write (burst or single) access and a synchronous read from the same or a \ndifferent bank.\n0000: BUSTURN phase duration = 0 HCLK clock cycle added\n... \n1111: BUSTURN phase duration = 15 x HCLK clock cycles added (default value after reset) \n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1648/1757\nRM0090 Rev 21\nNote:\nPSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these \nmemories issue the NWAIT signal during the whole latency phase to prolong the latency as \nneeded.\nWith PSRAMs (CRAMs) the filled DATLAT must be set to 0, so that the FMC exits its latency \nphase soon and starts sampling NWAIT from memory, then starts to read or write when the \nmemory is ready.\nThis method can be used also with the latest generation of synchronous Flash memories \nthat issue the NWAIT signal, unlike older Flash memories (check the datasheet of the \nspecific Flash memory being used).\nBits 15:8 DATAST[7:0]: Data-phase duration\nThese bits are written by software to define the duration of the data phase (refer to Figure 458 \nto Figure 470), used in asynchronous accesses:\n0000 0000: Reserved\n0000 0001: DATAST phase duration = 1 × HCLK clock cycles\n0000 0010: DATAST phase duration = 2 × HCLK clock cycles\n...\n1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)\nFor each memory type and access mode data-phase duration, please refer to the respective \nfigure (Figure 458 to Figure 470).\nExample: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock \ncycles.\nNote: In synchronous accesses, this value is don’t care.\nBits 7:4 ADDHLD[3:0]: Address-hold phase duration\nThese bits are written by software to define the duration of the address hold phase (refer to \nFigure 467 to Figure 470), used in mode D or multiplexed accesses:\n0000: Reserved\n0001: ADDHLD phase duration =1 × HCLK clock cycle\n0010: ADDHLD phase duration = 2 × HCLK clock cycle\n...\n1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)\nFor each access mode address-hold phase duration, please refer to the respective figure \n(Figure 467 to Figure 470).\nNote: In synchronous accesses, this value is not used, the address hold phase is always 1 \nmemory clock period duration.\nBits 3:0 ADDSET[3:0]: Address setup phase duration\nThese bits are written by software to define the duration of the address setup phase (refer to \nFigure 458 to Figure 470), used in SRAMs, ROMs and asynchronous NOR Flash and PSRAM \naccesses:\n0000: ADDSET phase duration = 0 × HCLK clock cycle\n...\n1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)\nFor each access mode address setup phase duration, please refer to the respective figure \n(refer to Figure 458 to Figure 470).\nNote: In synchronous accesses, this value is don’t care.\nIn Muxed mode or Mode D, the minimum value for ADDSET is 1.\n\n\n<>\n\nRM0090 Rev 21\n1649/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nSRAM/NOR-Flash write timing registers 1..4 (FMC_BWTR1..4)\nAddress offset: 0x104 + 8 * (x – 1), x = 1...4\nReset value: 0x0FFF FFFF\nThis register contains the control information of each memory bank. It is used for SRAMs, \nPSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx \nregister, then this register is active for write access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nACCMOD[1:0]\nReserved\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value\nBits 29:28 ACCMOD[1:0]: Access mode.\nSpecifies the asynchronous access modes as shown in the next timing diagrams.These bits are \ntaken into account only when the EXTMOD bit in the FMC_BCRx register is 1.\n00: access mode A\n01: access mode B\n10: access mode C\n11: access mode D\nBits 27:20 Reserved, must be kept at reset value\nBits 19:16 BUSTURN[3:0]: Bus turnaround phase duration\nThe programmed bus turnaround delay is inserted between an asynchronous write transfer and \nany other asynchronous /synchronous read or write transfer to or from a static bank. The bank can \nbe the same or different in case of read, in case of write the bank can be different expect for muxed \nor mode D.\nIn some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as\nfollows:\n• The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to \nthe same static memory bank except for modes muxed and D.\n• There is a bus turnaround delay of 2 FMC clock cycle between:\n–Two consecutive synchronous writes (burst or single) to the same bank.\n–A synchronous write (burst or single) transfer and an asynchronous write or read transfer to or \nfrom static memory bank.\n• There is a bus turnaround delay of 3 FMC clock cycle between:\n–Two consecutive synchronous writes (burst or single) to different static bank.\n–A synchronous write (burst or single) transfer and a synchronous read from the same or a \ndifferent bank.\n0000: BUSTURN phase duration = 0 HCLK clock cycle added\n... \n1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1650/1757\nRM0090 Rev 21\n37.6 \nNAND Flash/PC Card controller\nThe FMC generates the appropriate signal timings to drive the following types of device:\n•\n8- and 16-bit NAND Flash memories\n•\n16-bit PC Card compatible devices\nThe NAND Flash/PC Card controller can control three external banks, Bank 2, 3 and 4:\n•\nBank 2 and Bank 3 support NAND Flash devices\n•\nBank 4 supports PC Card devices.\nEach bank is configured through dedicated registers (Section 37.6.8). The programmable \nmemory parameters include access timings (shown in Table 290) and ECC configuration.\nBits 15:8 DATAST[3:0]: Data-phase duration.\nThese bits are written by software to define the duration of the data phase (refer toFigure 458 to \nFigure 470), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:\n0000 0000: Reserved\n0000 0001: DATAST phase duration = 1 × HCLK clock cycles\n0000 0010: DATAST phase duration = 2 × HCLK clock cycles\n...\n1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)\nBits 7:4 ADDHLD[3:0]: Address-hold phase duration.\nThese bits are written by software to define the duration of the address hold phase (refer to \nFigure 467 to Figure 470), used in asynchronous multiplexed accesses:\n0000: Reserved\n0001: ADDHLD phase duration = 1 × HCLK clock cycle\n0010: ADDHLD phase duration = 2 × HCLK clock cycle\n...\n1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)\nNote: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always \n1 Flash clock period duration.\nBits 3:0 ADDSET[3:0]: Address setup phase duration.\nThese bits are written by software to define the duration of the address setup phase in HCLK cycles \n(refer to Figure 467 to Figure 470), used in asynchronous accesses:\n0000: ADDSET phase duration = 0 × HCLK clock cycle\n...\n1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)\nNote: In synchronous NOR Flash and PSRAM accesses, this value is not used, the address setup \nphase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value \nis 1.\n\n\n<>\n\nRM0090 Rev 21\n1651/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n \n37.6.1 \nExternal memory interface signals\nThe following tables list the signals that are typically used to interface NAND Flash memory \nand PC Card.\nNote:\nThe prefix “N” identifies the signals which are active low.\n8-bit NAND Flash memory\n t\nTheoretically, there is no capacity limitation as the FMC can manage as many address \ncycles as needed.\nTable 290. Programmable NAND Flash/PC Card access parameters\nParameter\nFunction\nAccess mode\nUnit\nMin. Max. \nMemory setup \ntime\nNumber of clock cycles (HCLK) \nrequired to set up the address \nbefore the command assertion\nRead/Write \nAHB clock cycle \n(HCLK) \n1 \n256 \nMemory wait\nMinimum duration (in HCLK clock \ncycles) of the command assertion \nRead/Write \nAHB clock cycle \n(HCLK) \n2\n255 \nMemory hold \nNumber of clock cycles (HCLK) \nduring which the address must be \nheld (as well as the data if a write \naccess is performed) after the \ncommand de-assertion \nRead/Write \nAHB clock cycle \n(HCLK) \n1 \n254\nMemory \ndatabus high-Z \nNumber of clock cycles (HCLK) \nduring which the data bus is kept \nin high-Z state after a write \naccess has started\nWrite \nAHB clock cycle \n(HCLK) \n1 \n255 \nTable 291. 8-bit NAND Flash\nFMC signal name\nI/O \nFunction\nA[17] \nO \nNAND Flash address latch enable (ALE) signal \nA[16] \nO \nNAND Flash command latch enable (CLE) signal \nD[7:0] \nI/O \n8-bit multiplexed, bidirectional address/data bus \nNCE[x]\nO\nChip Select, x = 2, 3\nNOE(= NRE)\nO \nOutput enable (memory signal name: read enable, NRE) \nNWE\nO \nWrite enable \nNWAIT/INT[3:2]\nI \nNAND Flash ready/busy input signal to the FMC \n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1652/1757\nRM0090 Rev 21\n16-bit NAND Flash memory\n \nTheoretically, there is no capacity limitation as the FMC can manage as many address \ncycles as needed.\n \nTable 292. 16-bit NAND Flash\nFMC signal name \nI/O \nFunction \nA[17]\nO \nNAND Flash address latch enable (ALE) signal \nA[16] \nO \nNAND Flash command latch enable (CLE) signal \nD[15:0] \nI/O \n16-bit multiplexed, bidirectional address/data bus \nNCE[x]\nO\nChip Select, x = 2, 3\nNOE(= NRE)\nO \nOutput enable (memory signal name: read enable, NRE) \nNWE\nO \nWrite enable \nNWAIT/INT[3:2]\nI \nNAND Flash ready/busy input signal to the FMC \nTable 293. 16-bit PC Card\nFMC signal name\nI/O\nFunction\nA[10:0]\nO\nAddress bus\nNIORD\nO\nOutput enable for I/O space\nNIOWR\nO\nWrite enable for I/O space\nNREG\nO\nRegister signal indicating if access is in Common or Attribute space\nD[15:0]\nI/O\nBidirectional databus\nNCE4_1\nO\nChip Select 1\nNCE4_2\nO\nChip Select 2 (indicates if access is 16-bit or 8-bit)\nNOE\nO\nOutput enable in Common and in Attribute space\nNWE\nO\nWrite enable in Common and in Attribute space\nNWAIT\nI\nPC Card wait input signal to the FMC (memory signal name IORDY)\nINTR\nI\nPC Card interrupt to the FMC (only for PC Cards that can generate \nan interrupt)\nCD\nI\nPC Card presence detection. Active high. If an access is performed \nto the PC Card banks while CD is low, an AHB error is generated. \nRefer to Section 37.3: AHB interface\n\n\n<>\n\nRM0090 Rev 21\n1653/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n37.6.2 \nNAND Flash / PC Card supported memories and transactions\nTable 294 shows the supported devices, access modes and transactions. Transactions not \nallowed (or not supported) by the NAND Flash / PC Card controller are shown in gray.\n \n37.6.3 \nTiming diagrams for NAND Flash memory and PC Card\nEach PC Card/CompactFlash and NAND Flash memory bank is managed through a set of \nregisters:\n•\nControl register: FMC_PCRx\n•\nInterrupt status register: FMC_SRx\n•\nECC register: FMC_ECCRx\n•\nTiming register for Common memory space: FMC_PMEMx\n•\nTiming register for Attribute memory space: FMC_PATTx\n•\nTiming register for I/O space: FMC_PIOx\nEach timing configuration register contains three parameters used to define number of \nHCLK cycles for the three phases of any PC Card/CompactFlash or NAND Flash access, \nplus one parameter that defines the timing for starting driving the data bus when a write \naccess is performed. Figure 476 shows the timing parameter definitions for common \nmemory accesses, knowing that Attribute and I/O (only for PC Card) memory space access \ntimings are similar.\nTable 294. Supported memories and transactions\nDevice\nMode \nR/W \nAHB \ndata size\nMemory \ndata size\nAllowed/\nnot allowed\nComments \nNAND 8-bit \nAsynchronous R \n8 \n8 \nY \n-\nAsynchronous W \n8 \n8 \nY \n-\nAsynchronous R \n16 \n8 \nY \nSplit into 2 FMC accesses \nAsynchronous W \n16 \n8 \nY \nSplit into 2 FMC accesses \nAsynchronous R \n32 \n8 \nY \nSplit into 4 FMC accesses \nAsynchronous W \n32 \n8 \nY \nSplit into 4 FMC accesses \nNAND 16-bit \nAsynchronous R \n8 \n16 \nY \n-\nAsynchronous W \n8 \n16 \nN \n-\nAsynchronous R \n16 \n16 \nY \n-\nAsynchronous W \n16 \n16 \nY \n-\nAsynchronous R \n32 \n16 \nY \nSplit into 2 FMC accesses \nAsynchronous W \n32 \n16 \nY \nSplit into 2 FMC accesses \n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1654/1757\nRM0090 Rev 21\nFigure 476. NAND Flash/PC Card controller waveforms for common memory access\n1.\nNOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses.\n2.\nFor write accesses, the hold phase delay is (MEMHOLD) x HCLK cycles, while it is (MEMHOLD + 2) x \nHCLK cycles for read accesses.\n37.6.4 \nNAND Flash operations\nThe command latch enable (CLE) and address latch enable (ALE) signals of the NAND \nFlash memory device are driven by address signals from the FMC controller. This means \nthat to send a command or an address to the NAND Flash memory, the CPU has to perform \na write to a specific address in its memory space.\nA typical page read operation from the NAND Flash device requires the following steps:\n3. \nProgram and enable the corresponding memory bank by configuring the FMC_PCRx \nand FMC_PMEMx (and for some devices, FMC_PATTx, see Section 37.6.5: NAND \nFlash prewait functionality) registers according to the characteristics of the NAND \nFlash memory (PWID bits for the data bus width of the NAND Flash, PTYP = 1, \nPWAITEN = 0 or 1 as needed, see section Section 37.4.2: NAND Flash memory/PC \nCard address mapping for timing configuration).\n4. \nThe CPU performs a byte write to the common memory space, with data byte equal to \none Flash command byte (for example 0x00 for Samsung NAND Flash devices). The \nLE input of the NAND Flash memory is active during the write strobe (low pulse on \nNWE), thus the written byte is interpreted as a command by the NAND Flash memory. \nOnce the command is latched by the memory device, it does not need to be written \nagain for the following page read operations.\n5. \nThe CPU can send the start address (STARTAD) for a read operation by writing four \nbyte (or three for smaller capacity devices), STARTAD[7:0], STARTAD[16:9], \nSTARTAD[24:17] and finally STARTAD[25] (for 64 Mb x 8 bit NAND Flash memories) in \nthe common memory or attribute space. The ALE input of the NAND Flash device is \nactive during the write strobe (low pulse on NWE), thus the written byte are interpreted \nas the start address for read operations. Using the attribute memory space makes it \npossible to use a different timing configuration of the FMC, which can be used to \nMS33733V2\nHCLK\nA[25:0]\nNCEx\nNREG,\nNIOW,\nNIOR\nNWE,\nNOE\n(1)\nwrite_data\nread_data\nHigh\nValid\nMEMxSET\n + 1\nMEMxWAIT + 1\nMEMxHOLD \nMEMxHIZ\n\n\n<>\n\nRM0090 Rev 21\n1655/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nimplement the prewait functionality needed by some NAND Flash memories (see \ndetails in Section 37.6.5: NAND Flash prewait functionality).\n6. \nThe controller waits for the NAND Flash memory to be ready (R/NB signal high), before \nstarting a new access to the same or another memory bank. While waiting, the \ncontroller holds the NCE signal active (low).\n7. \nThe CPU can then perform byte read operations from the common memory space to \nread the NAND Flash page (data field + Spare field) byte by byte.\n8. \nThe next NAND Flash page can be read without any CPU command or address write \noperation. This can be done in three different ways:\n–\nby simply performing the operation described in step 5\n–\na new random address can be accessed by restarting the operation at step 3\n–\na new command can be sent to the NAND Flash device by restarting at step 2\n37.6.5 \nNAND Flash prewait functionality\nSome NAND Flash devices require that, after writing the last part of the address, the \ncontroller waits for the R/NB signal to go low. (see Figure 457).\nFigure 477. Access to non ‘CE don’t care’ NAND-Flash\n1.\nCPU wrote byte 0x00 at address 0x7001 0000.\n2.\nCPU wrote byte A7~A0 at address 0x7002 0000.\n3.\nCPU wrote byte A16~A9 at address 0x7002 0000.\n4.\nCPU wrote byte A24~A17 at address 0x7002 0000.\n5.\nCPU wrote byte A25 at address 0x7802 0000: FMC performs a write access using FMC_PATT2 timing \ndefinition, where ATTHOLD ≥ 7 (providing that (7+1) × HCLK = 112 ns > tWB max). This guarantees that \nNCE remains low until R/NB goes low and high again (only requested for NAND Flash memories where \nNCE is not don’t care).\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1656/1757\nRM0090 Rev 21\nWhen this functionality is required, it can be ensured by programming the MEMHOLD value \nto meet the tWB timing. However CPU read accesses to the NAND Flash memory has a hold \ndelay of (MEMHOLD + 2) x HCLK cycles, while CPU write accesses have a hold delay of \n(MEMHOLD) x HCLK cycles. \nTo cope with this timing constraint, the attribute memory space can be used by \nprogramming its timing register with an ATTHOLD value that meets the tWB timing, and by \nkeeping the MEMHOLD value at its minimum value. The CPU must then use the common \nmemory space for all NAND Flash read and write accesses, except when writing the last \naddress byte to the NAND Flash device, where the CPU must write to the attribute memory \nspace.\n37.6.6 \nComputation of the error correction code (ECC) \nin NAND Flash memory\nThe FMC PC Card controller includes two error correction code computation hardware \nblocks, one per memory bank. They reduce the host CPU workload when processing the \nECC by software.\nThese two ECC blocks are identical and associated with Bank 2 and Bank 3. As a \nconsequence, no hardware ECC computation is available for memories connected to Bank \n4.\nThe ECC algorithm implemented in the FMC can perform 1-bit error correction and 2-bit \nerror detection per 256, 512, 1 024, 2 048, 4 096 or 8 192 byte read or written from/to the \nNAND Flash memory. It is based on the Hamming coding algorithm and consists in \ncalculating the row and column parity.\nThe ECC modules monitor the NAND Flash data bus and read/write signals (NCE and \nNWE) each time the NAND Flash memory bank is active.\nThe ECC operates as follows:\n•\nWhen accessing NAND Flash memory bank 2 or bank 3, the data present on the \nD[15:0] bus is latched and used for ECC computation. \n•\nWhen accessing any other address in NAND Flash memory, the ECC logic is idle, and \ndoes not perform any operation. As a result, write operations to define commands or \naddresses to the NAND Flash memory are not taken into account for ECC \ncomputation.\nOnce the desired number of byte has been read/written from/to the NAND Flash memory by \nthe host CPU, the FMC_ECCR2/3 registers must be read to retrieve the computed value. \nOnce read, they should be cleared by resetting the ECCEN bit to ‘0’. To compute a new data \nblock, the ECCEN bit must be set to one in the FMC_PCR2/3 registers.\n\n\n<>\n\nRM0090 Rev 21\n1657/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nTo perform an ECC computation:\n1.\nEnable the ECCEN bit in the FMC_PCR2/3 register.\n2. \nWrite data to the NAND Flash memory page. While the NAND page is written, the ECC \nblock computes the ECC value. \n3. \nRead the ECC value available in the FMC_ECCR2/3 register and store it in a variable.\n4. \nClear the ECCEN bit and then enable it in the FMC_PCR2/3 register before reading \nback the written data from the NAND page. While the NAND page is read, the ECC \nblock computes the ECC value. \n5. \nRead the new ECC value available in the FMC_ECCR2/3 register.\n6. \nIf the two ECC values are the same, no correction is required, otherwise there is an \nECC error and the software correction routine returns information on whether the error \ncan be corrected or not. \n37.6.7 \nPC Card/CompactFlash operations\nAddress spaces and memory accesses \nThe FMC supports CompactFlash devices and PC Cards in Memory mode and I/O mode \n(True IDE mode is not supported).\nThe CompactFlash and PC Cards are made of 3 memory spaces:\n•\nCommon Memory space\n•\nAttribute space\n•\nI/O Memory space\nThe nCE2 and nCE1 pins (FMC_NCE4_2 and FMC_NCE4_1 respectively) select the card \nand indicate whether a byte or a word operation is being performed: nCE2 accesses the odd \nbyte on D15-8 and nCE1 accesses the even byte on D7-0 if A0=0 or the odd byte on D7-0 if \nA0=1. The full word is accessed on D15-0 if both nCE2 and nCE1 are low.\nThe memory space is selected by asserting low nOE for read accesses or nWE for write \naccesses, combined with the low assertion of nCE2/nCE1 and nREG.\n•\nIf pin nREG=1 during the memory access, the common memory space is selected\n•\nIf pin nREG=0 during the memory access, the attribute memory space is selected\nThe I/O space is selected by asserting nIORD space for read accesses or nIOWR for write \naccesses [instead of nOE/nWE for memory space], combined with nCE2/nCE1. Note that \nnREG must also be asserted low when accessing I/O space.\nThree type of accesses are allowed for a 16-bit PC Card:\n•\nAccesses to Common Memory space for data storage can be either 8-bit accesses at \neven addresses or 16-bit AHB accesses. \nNote that 8-bit accesses at odd addresses are not supported and nCE2 is not driven \nlow. A 32-bit AHB request is translated into two 16-bit memory accesses.\n•\nAccesses to Attribute Memory space where the PC Card stores configuration \ninformation are limited to 8-bit AHB accesses at even addresses.\nNote that a 16-bit AHB access is converted into a single 8-bit memory transfer: nCE1 is \nasserted low, nCE2 is asserted high and only the even byte on D7-D0 are valid. Instead \na 32-bit AHB access is converted into two 8-bit memory transfers at even addresses: \nnCE1 is asserted low, NCE2 is asserted high and only the even byte are valid.\n•\nAccesses to I/O space can be either 8-bit or 16 bit AHB accesses. \n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1658/1757\nRM0090 Rev 21\n \nFMC Bank 4 gives access to those 3 memory spaces as described in Section 37.4.2: NAND \nFlash memory/PC Card address mapping and Table 257: NAND/PC Card memory mapping \nand timing registers.\nWait feature\nThe CompactFlash or PC Card may request the FMC to extend the length of the access \nphase programmed by MEMWAITx/ATTWAITx/IOWAITx bits, asserting the nWAIT signal \nafter nOE/nWE or nIORD/nIOWR activation if the wait feature is enabled through the \nPWAITEN bit in the FMC_PCRx register. To detect correctly the nWAIT assertion, the \nMEMWAITx/ATTWAITx/IOWAITx bits must be programmed as follows:\nwhere max_wait_assertion_time is the maximum time taken by NWAIT to go low once \nnOE/nWE or nIORD/nIOWR is low.\nAfter WAIT de-assertion, the FMC extends the WAIT phase for 4 HCLK clock cycles. \nTable 295. 16-bit PC-Card signals and access type \nnCE2\nnCE1\nnREG\nnOE/nWE\nnIORD \nA10\nA9\nA7-1\nA0 \nSpace \nAccess type\nAllowed/not \nAllowed \n1\n0\n1\n0\n1\nX\nX\nX-X\nX\nCommon \nMemory \nSpace\nRead/Write byte on D7-D0\nYES\n0\n1\n1\n0\n1\nX\nX\nX-X\nX\nRead/Write byte on D15-D8\nNot supported\n0\n0\n1\n0\n1\nX\nX\nX-X\n0\nRead/Write word on D15-D0\nYES\nX\n0\n0\n0\n1\n0\n1\nX-X\n0\nAttribute \nSpace\nRead or Write Configuration \nRegisters\nYES\nX\n0\n0\n0\n1\n0\n0\nX-X\n0\nRead or Write CIS (Card \nInformation Structure)\nYES\n1\n0\n0\n0\n1\nX\nX\nX-X\n1\n Attribute \nSpace\nInvalid Read or Write (odd \naddress)\nYES\n0\n1\n0\n0\n1\nX\nX\nX-X\nx\nInvalid Read or Write (odd \naddress)\nYES\n1\n0\n0\n1\n0\nX\nX\nX-X\n0\nI/O space\nRead Even Byte on D7-0 \nYES\n1\n0\n0\n1\n0\nX\nX\nX-X\n1\nRead Odd Byte on D7-0\nYES\n1\n0\n0\n1\n0\nX\nX\nX-X\n0\nWrite Even Byte on D7-0 \nYES\n1\n0\n0\n1\n0\nX\nX\nX-X\n1\nWrite Odd Byte on D7-0 \nYES\n0\n0\n0\n1\n0\nX\nX\nX-X\n0\nRead Word on D15-0\nYES\n0\n0\n0\n1\n0\nX\nX\nX-X\n0\nWrite word on D15-0 \nYES\n0\n1\n0\n1\n0\nX\nX\nX-X\nX\nRead Odd Byte on D15-8\nNot supported\n0\n1\n0\n1\n0\nX\nX\nX-X\nX\nWrite Odd Byte on D15-8\nNot supported\nxxWAITx\n4\nmax_wait_assertion_time\nHCLK\n-------------------------------------------------------------------\n+\n≥\n\n\n<>\n\nRM0090 Rev 21\n1659/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n37.6.8 \nNAND Flash/PC Card controller registers\nPC Card/NAND Flash control registers 2..4 (FMC_PCR2..4)\nAddress offset: 0x40 + 0x20 * (x – 1), x = 2..4\nReset value: 0x0000 0018\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nECCPS[2:0]\nTAR[3:0]\nTCLR[3:0]\nReserved\nECCEN\nPWID[1:0]\nPTYP\nPBKEN\nPWAITEN\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:20 Reserved, must be kept at reset value\nBits 19:17 ECCPS[2:0]: ECC page size.\nDefines the page size for the extended ECC:\n000: 256 byte\n001: 512 byte\n010: 1024 byte\n011: 2048 byte\n100: 4096 byte\n101: 8192 byte\nBits 16:13 TAR[3:0]: ALE to RE delay.\nSets time from ALE low to RE low in number of AHB clock cycles (HCLK).\nTime is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period\n0000: 1 HCLK cycle (default)\n1111: 16 HCLK cycles\nNote: SET is MEMSET or ATTSET according to the addressed space.\nBits 12:9 TCLR[3:0]: CLE to RE delay.\nSets time from CLE low to RE low in number of AHB clock cycles (HCLK).\nTime is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period\n0000: 1 HCLK cycle (default)\n1111: 16 HCLK cycles\nNote: SET is MEMSET or ATTSET according to the addressed space.\nBits 8:7 Reserved, must be kept at reset value\nBit 6 ECCEN: ECC computation logic enable bit\n0: ECC logic is disabled and reset (default after reset),\n1: ECC logic is enabled.\nBits 5:4 PWID[1:0]: Data bus width.\nDefines the external memory device width.\n00: 8 bits \n01: 16 bits (default after reset). This value is mandatory for PC Cards.\n10: reserved, do not use\n11: reserved, do not use\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1660/1757\nRM0090 Rev 21\nFIFO status and interrupt register 2..4 (FMC_SR2..4)\nAddress offset: 0x44 + 0x20 * (x-1), x = 2..4\nReset value: 0x0000 0040\nThis register contains information about the FIFO status and interrupt. The FMC features a \nFIFO that is used when writing to memories to transfer up to 16 words of data from the AHB.\nThis is used to quickly write to the FIFO and free the AHB for transactions to peripherals \nother than the FMC, while the FMC is draining its FIFO into the memory. One of these \nregister bits indicates the status of the FIFO, for ECC purposes.\nThe ECC is calculated while the data are written to the memory. To read the correct ECC, \nthe software must consequently wait until the FIFO is empty.\n \n \nBit 3 PTYP: Memory type.\nDefines the type of device attached to the corresponding memory bank:\n0: PC Card, CompactFlash, CF+ or PCMCIA\n1: NAND Flash (default after reset)\nBit 2 PBKEN: PC Card/NAND Flash memory bank enable bit.\nEnables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB \nbus\n0: Corresponding memory bank is disabled (default after reset)\n1: Corresponding memory bank is enabled\nBit 1 PWAITEN: Wait feature enable bit.\nEnables the Wait feature for the PC Card/NAND Flash memory bank:\n0: disabled\n1: enabled\nNote: For a PC Card, when the wait feature is enabled, the MEMWAITx/ATTWAITx/IOWAITx \nbits must be programmed to a value as follows:\nxxWAITx ≥ 4 + max_wait_assertion_time/HCLK\nWhere max_wait_assertion_time is the maximum time taken by NWAIT to go low once \nnOE/nWE or nIORD/nIOWR is low.\nBit 0 Reserved.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFEMPT\nIFEN\nILEN\nIREN\nIFS\nILS\nIRS\nr\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:7 Reserved, must be kept at reset value\nBit 6 FEMPT: FIFO empty.\nRead-only bit that provides the status of the FIFO\n0: FIFO not empty\n1: FIFO empty\nBit 5 IFEN: Interrupt falling edge detection enable bit\n0: Interrupt falling edge detection request disabled\n1: Interrupt falling edge detection request enabled\n\n\n<>\n\nRM0090 Rev 21\n1661/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nCommon memory space timing register 2..4 (FMC_PMEM2..4)\nAddress offset: Address: 0x48 + 0x20 * (x – 1), x = 2..4\nReset value: 0xFCFC FCFC\nEach FMC_PMEMx (x = 2..4) read/write register contains the timing information for PC Card \nor NAND Flash memory bank x. This information is used to access either the common \nmemory space of the 16-bit PC Card/CompactFlash, or the NAND Flash for command, \naddress write access and data read/write access.\n \n \nBit 4 ILEN: Interrupt high-level detection enable bit\n0: Interrupt high-level detection request disabled\n1: Interrupt high-level detection request enabled\nBit 3 IREN: Interrupt rising edge detection enable bit\n0: Interrupt rising edge detection request disabled\n1: Interrupt rising edge detection request enabled\nBit 2 IFS: Interrupt falling edge status\nThe flag is set by hardware and reset by software.\n0: No interrupt falling edge occurred\n1: Interrupt falling edge occurred\nNote: This bit is set by programming it to 1 by software. \nBit 1 ILS: Interrupt high-level status\nThe flag is set by hardware and reset by software.\n0: No Interrupt high-level occurred\n1: Interrupt high-level occurred\nBit 0 IRS: Interrupt rising edge status\nThe flag is set by hardware and reset by software.\n0: No interrupt rising edge occurred\n1: Interrupt rising edge occurred\nNote: This bit is set by programming it to 1 by software. \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMEMHIZ[7:0]\nMEMHOLD[7:0]\nMEMWAIT[7:0]\nMEMSET[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 MEMHIZ[7:0]: Common memory x data bus Hi-Z time\nDefines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the \nstart of a PC Card/NAND Flash write access to common memory space on socket x. This is \nonly valid for write transactions:\n0000 0000: 1 HCLK cycle\n1111 1110: 255 HCLK cycles\n1111 1111: Reserved.\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1662/1757\nRM0090 Rev 21\nAttribute memory space timing registers 2..4 (FMC_PATT2..4)\nAddress offset: 0x4C + 0x20 * (x – 1), x = 2..4\nReset value: 0xFCFC FCFC\nEach FMC_PATTx (x = 2..4) read/write register contains the timing information for PC \nCard/CompactFlash or NAND Flash memory bank x. It is used for 8-bit accesses to the \nattribute memory space of the PC Card/CompactFlash or to access the NAND Flash for the \nlast address write access if the timing must differ from that of previous accesses (for \nReady/Busy management, refer to Section 37.6.5: NAND Flash prewait functionality).\n \n \nBits 23:16 MEMHOLD[7:0]: Common memory x hold time\nFor NAND Flash read accesses to the common memory space, these bits define the \nnumber of (HCLK+2) clock cycles during which the address is held after the command is \ndeasserted (NWE, NOE).\nFor NAND Flash write accesses to the common memory space, these bits define the \nnumber of HCLK clock cycles during which the data are held after the command is \ndeasserted (NWE, NOE).\n0000 0000: reserved\n0000 0001: 1 HCLK cycle for write accesses, 3 HCLK cycles for read accesses\n1111 1110: 254 HCLK cycle for write accesses, 256 HCLK cycles for read accesses\n1111 1111: Reserved.\nBits 15:8 MEMWAIT[7:0]: Common memory x wait time\nDefines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, \nNOE), for PC Card/NAND Flash read or write access to common memory space on socket \nx. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) \nat the end of the programmed value of HCLK:\n0000 0000: reserved\n0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)\n1111 1110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)\n1111 1111: Reserved\nBits 7:0 MEMSET[7:0]: Common memory x setup time\nDefines the number of HCLK (+1) clock cycles to set up the address before the command \nassertion (NWE, NOE), for PC Card/NAND Flash read or write access to common memory \nspace on socket x:\n0000 0000: 1 HCLK cycle\n1111 1110: 255 HCLK cycles\n1111 1111: Reserved.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nATTHIZ[7:0]\nATTHOLD[7:0]\nATTWAIT[7:0]\nATTSET[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 ATTHIZ[7:0]: Attribute memory x data bus Hi-Z time\nDefines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the \nstart of a PC CARD/NAND Flash write access to attribute memory space on socket x. Only \nvalid for write transaction:\n0000 0000: 0 HCLK cycle\n1111 1110: 255 HCLK cycles\n1111 1111: Reserved.\n\n\n<>\n\nRM0090 Rev 21\n1663/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nI/O space timing register 4 (FMC_PIO4)\nAddress offset: 0xB0\nReset value: 0xFCFCFCFC\nThe FMC_PIO4 read/write registers contain the timing information used to access the I/O \nspace of the 16-bit PC Card/CompactFlash.\n \n \nBits 23:16 ATTHOLD[7:0]: Attribute memory x hold time\nFor PC Card/NAND Flash read accesses to attribute memory space on socket x, these bits \ndefine the number of HCLK clock cycles (HCLK +2) clock cycles during which the address is \nheld after the command is deasserted (NWE, NOE).\nFor PC Card/NAND Flash write accesses to attribute memory space on socket x, these bits \ndefine the number of HCLK clock cycles during which the data are held after the command \nis deasserted (NWE, NOE).\n0000 0000: Reserved\n0000 0001: 1 HCLK cycle for write access, 3 HCLK cycles for read accesses\n1111 1110: 254 HCLK cycle for write access, 256 HCLK cycles for read accesses\n1111 1111: Reserved.\nBits 15:8 ATTWAIT[7:0]: Attribute memory x wait time\nDefines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, \nNOE), for PC Card/NAND Flash read or write access to attribute memory space on socket x. \nThe duration for command assertion is extended if the wait signal (NWAIT) is active (low) at \nthe end of the programmed value of HCLK:\n0000 0000: reserved\n0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)\n1111 1110: 255 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)\n1111 1111: Reserved\nBits 7:0 ATTSET[7:0]: Attribute memory x setup time\nDefines the number of HCLK (+1) clock cycles to set up address before the command \nassertion (NWE, NOE), for PC CARD/NAND Flash read or write access to attribute memory \nspace on socket x:\n0000 0000: 1 HCLK cycle\n1111 1110: 255 HCLK cycles\n1111 1111: Reserved\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nIOHIZ[7:0]\nIOHOLD[7:0]\nIOWAIT[7:0]\nIOSET[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1664/1757\nRM0090 Rev 21\nBits 31:24 IOHIZ[7:0]: I/O x data bus Hi-Z time\nDefines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the \nstart of a PC Card write access to I/O space on socket x. Only valid for write transaction:\n0000 0000: 0 HCLK cycle\n1111 1111: 255 HCLK cycles\nBits 23:16 IOHOLD[7:0]: I/O x hold time\nDefines the number of HCLK clock cycles during which the address is held (and data for write \naccess) after the command deassertion (NWE, NOE), for PC Card read or write access to I/O \nspace on socket x:\n0000 0000: reserved\n0000 0001: 1 HCLK cycle\n1111 1111: 255 HCLK cycles \nBits 15:8 IOWAIT[7:0]: I/O x wait time\nDefines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE, \nSMNOE), for PC Card read or write access to I/O space on socket x. The duration for \ncommand assertion is extended if the wait signal (NWAIT) is active (low) at the end of the \nprogrammed value of HCLK:\n0000 0000: reserved, do not use this value\n0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)\n1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) \nBits 7:0 IOSET[7:0]: I/O x setup time\nDefines the number of HCLK (+1) clock cycles to set up the address before the command \nassertion (NWE, NOE), for PC Card read or write access to I/O space on socket x:\n0000 0000: 1 HCLK cycle\n1111 1111: 256 HCLK cycles\n\n\n<>\n\nRM0090 Rev 21\n1665/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nECC result registers 2/3 (FMC_ECCR2/3)\nAddress offset: 0x54 + 0x20 * (x – 1), x = 2 or 3\nReset value: 0x0000 0000\nThese registers contain the current error correction code value computed by the ECC \ncomputation modules of the FMC controller (one module per NAND Flash memory bank). \nWhen the CPU reads the data from a NAND Flash memory page at the correct address \n(refer to Section 37.6.6: Computation of the error correction code (ECC) in NAND Flash \nmemory), the data read/written from/to the NAND Flash memory are processed \nautomatically by the ECC computation module. When X byte have been read (according to \nthe ECCPS field in the FMC_PCRx registers), the CPU must read the computed ECC value \nfrom the FMC_ECCx registers. It then verifies if these computed parity data are the same as \nthe parity value recorded in the spare area, to determine whether a page is valid, and, to \ncorrect it otherwise. The FMC_ECCRx registers should be cleared after being read by \nsetting the ECCEN bit to ‘0’. To compute a new data block, the ECCEN bit must be set to ’1’.\n \n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nECC[31:0]\nr\nBits 31:0 ECC[31:0]: ECC result\nThis field contains the value computed by the ECC computation logic. Table 296 describes the \ncontents of these bit fields.\nTable 296. ECC result relevant bits\nECCPS[2:0]\nPage size in byte\nECC bits\n000\n256\nECC[21:0]\n001\n512\nECC[23:0]\n010\n1024\nECC[25:0]\n011\n2048\nECC[27:0]\n100\n4096\nECC[29:0]\n101\n8192\nECC[31:0]\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1666/1757\nRM0090 Rev 21\n37.7 \nSDRAM controller\n37.7.1 \nSDRAM controller main features\nThe main features of the SDRAM controller are the following:\n•\nTwo SDRAM banks with independent configuration\n•\n8-bit, 16-bit, 32-bit data bus width\n•\n13-bits Address Row, 11-bits Address Column, 4 internal banks: 4x16Mx32bit \n(256 MB), 4x16Mx16bit (128 MB), 4x16Mx8bit (64 MB)\n•\nWord, half-word, byte access\n•\nSDRAM clock can be HCLK/2 or HCLK/3\n•\nAutomatic row and bank boundary management \n•\nMultibank ping-pong access\n•\nProgrammable timing parameters \n•\nAutomatic Refresh operation with programmable Refresh rate\n•\nSelf-refresh mode\n•\nPower-down mode\n•\nSDRAM power-up initialization by software\n•\nCAS latency of 1,2,3 \n•\nCacheable Read FIFO with depth of 6 lines x32-bit (6 x14-bit address tag)\n37.7.2 \nSDRAM External memory interface signals\nAt startup, the SDRAM I/O pins used to interface the FMC SDRAM controller with the \nexternal SDRAM devices must configured by the user application. The SDRAM controller \nI/O pins which are not used by the application, can be used for other purposes.\n \nTable 297. SDRAM signals\nSDRAM signal \nI/O \ntype\nDescription\nAlternate function\nSDCLK\nO\nSDRAM clock\n-\nSDCKE[1:0]\nO\nSDCKE0: SDRAM Bank 1 Clock Enable \nSDCKE1: SDRAM Bank 2 Clock Enable\n-\nSDNE[1:0]\nO\nSDNE0: SDRAM Bank 1 Chip Enable \nSDNE1: SDRAM Bank 2 Chip Enable\n-\nA[12:0]\nO\nAddress\nFMC_A[12:0]\nD[31:0]\nI/O\nBidirectional data bus\nFMC_D[31:0]\nBA[1:0]\nO\nBank Address\nFMC_A[15:14]\nNRAS\nO\nRow Address Strobe\n-\nNCAS\nO\nColumn Address Strobe\n-\nSDNWE\nO\nWrite Enable\n-\nNBL[3:0]\nO\nOutput Byte Mask for write accesses \n(memory signal name: DQM[3:0]) \n FMC_NBL[3:0]\n\n\n<>\n\nRM0090 Rev 21\n1667/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n37.7.3 \nSDRAM controller functional description\nAll SDRAM controller outputs (signals, address and data) change on the falling edge of the \nmemory clock (FMC_SDCLK).\nSDRAM initialization\nThe initialization sequence is managed by software. If the two banks are used, the \ninitialization sequence must be generated simultaneously to Bank 1and Bank 2 by setting \nthe Target Bank bits CTB1 and CTB2 in the FMC_SDCMR register:\n1.\nProgram the memory device features into the FMC_SDCRx register.The SDRAM clock \nfrequency, RBURST and RPIPE must be programmed in the FMC_SDCR1 register.\n2. \nProgram the memory device timing into the FMC_SDTRx register. The TRP and TRC \ntimings must be programmed in the FMC_SDTR1 register.\n3. \nSet MODE bits to ‘001’ and configure the Target Bank bits (CTB1 and/or CTB2) in the \nFMC_SDCMR register to start delivering the clock to the memory (SDCKE is driven \nhigh).\n4. \nWait during the prescribed delay period. Typical delay is around 100 μs (refer to the \nSDRAM datasheet for the required delay after power-up).\n5. \nSet MODE bits to ‘010’ and configure the Target Bank bits (CTB1 and/or CTB2) in the \nFMC_SDCMR register to issue a “Precharge All” command.\n6. \nSet MODE bits to ‘011’, and configure the Target Bank bits (CTB1 and/or CTB2) as well \nas the number of consecutive Auto-refresh commands (NRFS) in the FMC_SDCMR \nregister. Refer to the SDRAM datasheet for the number of Auto-refresh commands that \nshould be issued. Typical number is 8.\n7. \nConfigure the MRD field according to your SDRAM device, set the MODE bits to '100', \nand configure the Target Bank bits (CTB1 and/or CTB2) in the FMC_SDCMR register \nto issue a \"Load Mode Register\" command in order to program the SDRAM. In \nparticular: \na) \nThe CAS latency must be selected following configured value in FMC_SDCR1/2 \nregisters \nb) \nThe Burst Length (BL) of 1 must be selected by configuring the M[2:0] bits to 000 \nin the mode register (refer to the SDRAM datasheet). If the Mode Register is not \nthe same for both SDRAM banks, this step has to be repeated twice, once for \neach bank, and the Target Bank bits set accordingly.\n8. \nProgram the refresh rate in the FMC_SDRTR register\nThe refresh rate corresponds to the delay between refresh cycles. Its value must be \nadapted to SDRAM devices.\n9. \nFor mobile SDRAM devices, to program the extended mode register it should be done \nonce the SDRAM device is initialized: First, a dummy read access should be performed \nwhile BA1=1 and BA=0 (refer to SDRAM address mapping section for BA[1:0] address \nmapping) in order to select the extended mode register instead of Load mode register \nand then program the needed value. \nAt this stage the SDRAM device is ready to accept commands. If a system reset occurs \nduring an ongoing SDRAM access, the data bus might still be driven by the SDRAM device. \nTherefor the SDRAM device must be first reinitialized after reset before issuing any new \naccess by the NOR Flash/PSRAM/SRAM or NAND Flash/PC Card controller. \nNote:\nIf two SDRAM devices are connected to the FMC, all the accesses performed at the same \ntime to both devices by the Command Mode register (Load Mode Register and Self-refresh \n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1668/1757\nRM0090 Rev 21\ncommands) are issued using the timing parameters configured for SDRAM Bank 1 (TMRD, \nTRAS and TXSR timings) in the FMC_SDTR1 register.\nSDRAM controller write cycle\nThe SDRAM controller accepts single and burst write requests and translates them into \nsingle memory accesses. In both cases, the SDRAM controller keeps track of the active row \nfor each bank to be able to perform consecutive write accesses to different banks (Multibank \nping-pong access). \nBefore performing any write access, the SDRAM bank write protection must be disabled by \nclearing the WP bit in the FMC_SDCRx register.\nFigure 478. Burst write SDRAM access waveforms\nThe SDRAM controller always checks the next access. \n•\nIf the next access is in the same row or in another active row, the write operation is \ncarried out, \n•\nif the next access targets another row (not active), the SDRAM controller generates a \nprecharge command, activates the new row and initiates a write command. \nMS30448V3\nNRAS\nA[12:0]\nSDCLK\nRow n \nColc\nSDNE\nTRCD = 3\nSDNWE\nCola\nCold\nColb\nCole Colf\nCog Colh Coli\nColj\nColk Coll\nNCAS\nDATA[31:0]\nDnc\nDne\nDna\nDnf\nDng Dnh Dni\nDnj\nDnk\nDnl\nDnb\nDnd\n\n\n<>\n\nRM0090 Rev 21\n1669/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nSDRAM controller read cycle\nThe SDRAM controller accepts single and burst read requests and translates them into \nsingle memory accesses. In both cases, the SDRAM controller keeps track of the active row \nin each bank to be able to perform consecutive read accesses in different banks (Multibank \nping-pong access). \nFigure 479. Burst read SDRAM access\nThe FMC SDRAM controller features a Cacheable read FIFO (6 lines x 32 bits). It is used to \nstore data read in advance during the CAS latency period and during the RPIPE delay. The \nfollowing the formula is applied:\nThe RBURST bit must be set in the FMC_SDCR1 register to anticipate the next read \naccess.\nExample:\n•\nCAS latency = 3, RPIPE delay = 0: 4 data (not committed) are stored in the FIFO.\n•\nCAS latency = 3, RPIPE delay = 2: 5 data (not committed) are stored in the FIFO. \nThe read FIFO features a 14-bit address tag to each line to identify its content: 11 bits for the \ncolumn address, 2 bits to select the internal bank and the active row, and 1 bit to select the \nSDRAM device\nWhen the end of the row is reached in advance during an AHB burst read, the data read in \nadvance (not committed) are not stored in the read FIFO. For single read access, data are \ncorrectly stored in the FIFO.\nMS30449V3\nNRAS\nA[12:0]\nSDCLK\nRow n \nColc\nSDNE\nTRCD = 3\nNWE\nCola\nCold\nColb\nCole\nColf\nNCAS\nDATA[31:0]\nDnc\nDne\nDna\nDnf\nDnb\nDnd\nCAS latency = 2\nNumber of anticipated data\nCAS latency\n1\nRPIPE delay\n(\n)\n2\n⁄\n+\n+\n=\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1670/1757\nRM0090 Rev 21\nEach time a read request occurs, the SDRAM controller checks:\n•\nIf the address matches one of the address tags, data are directly read from the FIFO \nand the corresponding address tag/ line content is cleared and the remaining data in \nthe FIFO are compacted to avoid empty lines. \n•\nOtherwise, a new read command is issued to the memory and the FIFO is updated with \nnew data. If the FIFO is full, the older data are lost. \nFigure 480. Logic diagram of Read access with RBURST bit set (CAS=2, RPIPE=0)\nDuring a write access or a Precharge command, the read FIFO is flushed and ready to be \nfilled with new data.\nAfter the first read request, if the current access was not performed to a row boundary, the \nSDRAM controller anticipates the next read access during the CAS latency period and the \nRPIPE delay (if configured). This is done by incrementing the memory address. The \nfollowing condition must be met: \n•\nRBURST control bit should be set to ‘1’ in the FMC_SDCR1 register.\nMS30445V1\nAHB Master\n@0x04\n@0x08\nData 2\nData 3\n...\n...\nSDRAM\nDevice\n(CAS = 2) \nread request@0x00\nData 1\n6 lines FIFO\nAdd. Tag read FIFO\nData stored in FIFO\nin advance during\nthe CAS latency period\nAddress matches with \none of the address tags\nFMC SDRAM Controller\n2nd Read access\n: Requested data was previously stored in the FIFO \n1st Read access: Requested data is not in the FIFO\nAHB Master\n@0x04\n@0x08\nData 2\nData 3\n...\n...\nSDRAM\nDevice\n(CAS = 2) \nread request@0x04\nData 2\n6 lines FIFO\nData read from FIFO\nFMC SDRAM Controller\nAdd. Tag read FIFO\n\n\n<>\n\nRM0090 Rev 21\n1671/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nThe address management depends on the next AHB request: \n•\nNext AHB request is sequential (AHB Burst)\nIn this case, the SDRAM controller increments the address.\n•\nNext AHB request is not sequential\n–\nIf the new read request targets the same row or another active row, the new \naddress is passed to the memory and the master is stalled for the CAS latency \nperiod, waiting for the new data from memory.\n–\nIf the new read request does not target an active row, the SDRAM controller \ngenerates a Precharge command, activates the new row, and initiates a read \ncommand.\nIf the RURST is reset, the read FIFO is not used.\nRow and bank boundary management \nWhen a read or write access crosses a row boundary, if the next read or write access is \nsequential and the current access was performed to a row boundary, the SDRAM controller \nexecutes the following operations:\n1.\nPrecharge of the active row,\n2. \nActivation of the new row \n3. \nStart of a read/write command. \nAt a row boundary, the automatic activation of the next row is supported for all columns and \ndata bus width configurations.\nIf necessary, the SDRAM controller inserts additional clock cycles between the following \ncommands:\n•\nBetween Precharge and Active commands to match TRP parameter (only if the next \naccess is in a different row in the same bank), \n•\nBetween Active and Read commands to match the TRCD parameter. \nThese parameters are defined into the FMC_SDTRx register.\nRefer to Figure 481 and Figure 482 for read and burst write access crossing a row \nboundary.\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1672/1757\nRM0090 Rev 21\nFigure 481. Read access crossing row boundary\nFigure 482. Write access crossing row boundary\nMS30446V2\nData[31:0]\nNCAS\nNRAS\nA[12:0]\nSDCLK\nCol a\nCol a Col b\nRow n +1\nDna\nDn+1 a\nSDNE\nTRP = 3\nCAS latency = 2\nNWE\nPrecharge\nActivate Row\nRead Command\nRow n\nTRCD = 3\nMS30447V2\nData[31:0]\nNCAS\nNRAS\nA[12:0]\nSDCLK\nCna\nCola\nRow n+1\nDna\nDn+1a\nSDNE\nTRP = 3\nNWE\nPrecharge\nActivate Row\nWrite command\nColb\nColb\nDnb\nDn+1b\nTRCD = 3\n\n\n<>\n\nRM0090 Rev 21\n1673/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nIf the next access is sequential and the current access crosses a bank boundary, the \nSDRAM controller activates the first row in the next bank and initiates a new read/write \ncommand. Two cases are possible:\n•\nIf the current bank is not the last one, the active row in the new bank must be \nprecharged. At a bank boundary, the automatic activation of the next row is supported \nfor all rows/columns and data bus width configuration.\n•\nFor 13-bit row address, 11-bit column address, 4 internal banks and bus width 32-bit \nSDRAM memories, if the current bank is the last one and the selected SDRAM device \nis connected to Bank 1, the SDRAM controller continues to read/write from the second \nSDRAM device (assuming it has been initialized):\na) \nThe SDRAM controller activates the first row (after precharging the active row, if \nthere is already an active row in the first internal bank, and initiates a new \nread/write command.\nb) \nIf the first row is already activated, the SDRAM controller just initiates a read/write \ncommand.\nNote:\nAt bank boundary, if the current bank is the last one, the automatic activation of the next row \nis supported only when addressing 13-bit rows, 11-bit columns, 4 internal banks and 32-bit \ndata bus SDRAM devices. Otherwise, the SDRAM address range is violated and an AHB \nerror is generated.\nSDRAM controller refresh cycle\nThe Auto-refresh command is used to refresh the SDRAM device content. The SDRAM \ncontroller periodically issues auto-refresh commands. An internal counter is loaded with the \nCOUNT value in the register FMC_SDRTR. This value defines the number of memory clock \ncycles between the refresh cycles (refresh rate). When this counter reaches zero, an \ninternal pulse is generated.\nIf a memory access is ongoing, the auto-refresh request is delayed. However, if the memory \naccess and the auto-refresh requests are generated simultaneously, the auto-refresh \nrequest takes precedence. \nIf the memory access occurs during an auto-refresh operation, the request is buffered and \nprocessed when the auto-refresh is complete.\nIf a new auto-refresh request occurs while the previous one was not served, the RE \n(Refresh Error) bit is set in the Status register. An Interrupt is generated if it has been \nenabled (REIE = ‘1’).\nIf SDRAM lines are not in idle state (not all row are closed), the SDRAM controller generates \na PALL (Precharge ALL) command before the auto-refresh.\nIf the Auto-refresh command is generated by the FMC_SDCMR Command Mode register \n(Mode bits = ‘011’), a PALL command (Mode bits =’ 010’) must be issued first.\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1674/1757\nRM0090 Rev 21\n37.7.4 \nLow power modes\nTwo low power modes are available:\n•\nSelf-refresh mode\nThe auto-refresh cycles are performed by the SDRAM device itself to retain data \nwithout external clocking.\n•\nPower-down mode\nThe auto-refresh cycles are performed by the SDRAM controller.\nSelf-refresh mode\nThis mode is selected by setting the MODE bits to ‘101’ and by configuring the Target Bank \nbits (CTB1 and/or CTB2) in the FMC_SDCMR register.\nThe SDRAM clock stops running after a TRAS delay and the internal refresh timer stops \ncounting only if one of the following conditions is met:\n•\nA Self-refresh command is issued to both devices \n•\nOne of the devices is not activated (SDRAM bank is not initialized).\nBefore entering Self-Refresh mode, the SDRAM controller automatically issues a PALL \ncommand.\nIf the Write data FIFO is not empty, all data are sent to the memory before activating the \nSelf-refresh mode and the BUSY status flag remains set.\nIn Self-refresh mode, all SDRAM device inputs become don’t care except for SDCKE which \nremains low. \nThe SDRAM device must remain in Self-refresh mode for a minimum period of time of \nTRAS and can remain in Self-refresh mode for an indefinite period beyond that. To \nguarantee this minimum period, the BUSY status flag remains high after the Self-refresh \nactivation during a TRAS delay. \nAs soon as an SDRAM device is selected, the SDRAM controller generates a sequence of \ncommands to exit from Self-refresh mode. After the memory access, the selected device \nremains in Normal mode.\nTo exit from Self-refresh, the MODE bits must be set to ‘000’ (Normal mode) and the Target \nBank bits (CTB1 and/or CTB2) must be configured in the FMC_SDCMR register.\n\n\n<>\n\nRM0090 Rev 21\n1675/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nFigure 483. Self-refresh mode\nPower-down mode\nThis mode is selected by setting the MODE bits to ‘110’ and by configuring the Target Bank \nbits (CTB1 and/or CTB2) in the FMC_SDCMR register. \nPRECHARGE\nSDCLK\nSDCKE\nT0\nT1\nT2\nTn+1\nT0+1\nT0+2\ntRAS(min)\nCOMMAND\nNOP\nAUTO\nREFRESH\nNOP or COMMAND \nINHERIT\nAUTO\nREFRESH\nDOM/\nDOML/DOMU\nA0- A9\nA11, A12\nA10\nALL \nBANKS\nData[31:0] Hi-Z\ntRP\nPrecharge all\nactive banks\nEnter Self-refresh mode\nCLK stable prior to existing\nSelf-refresh mode\nExit Self-refresh mode\n(restart refresh timebase)\ntXSR\nMS30450V1\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1676/1757\nRM0090 Rev 21\nFigure 484. Power-down mode\nIf the Write data FIFO is not empty, all data are sent to the memory before activating the \nPower-down mode.\nAs soon as an SDRAM device is selected, the SDRAM controller exits from the Power-down \nmode. After the memory access, the selected SDRAM device remains in Normal mode.\nDuring Power-down mode, all SDRAM device input and output buffers are deactivated \nexcept for the SDCKE which remains low. \nThe SDRAM device cannot remain in Power-down mode longer than the refresh period and \ncannot perform the Auto-refresh cycles by itself. Therefore, the SDRAM controller carries \nout the refresh operation by executing the operations below:\n1.\nExit from Power-down mode and drive the SDCKE high\n2. \nGenerate the PALL command only if a row was active during Power-down mode\n3. \nGenerate the auto-refresh command \n4. \nDrive SDCKE low again to return to Power-down mode.\nTo exit from Power-down mode, the MODE bits must be set to ‘000’ (Normal mode) and the \nTarget Bank bits (CTB1 and/or CTB2) must be configured in the FMC_SDCMR register.\nSDCLK\nSDCKE\nCOMMAND\nNOP\nNOP \nACTIVE\nInput buffers gated off\nAll banks idle\nEnter Power-down\nExit Power-down\ntRCD\ntRAS\ntRC\nMS30451V1\n\n\n<>\n\nRM0090 Rev 21\n1677/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n37.7.5 \nSDRAM controller registers\nSDRAM Control registers 1,2 (FMC_SDCR1,2)\nAddress offset: 0x140+ 4* (x – 1), x = 1,2\nReset value: 0x0000 02D0\nThis register contains the control parameters for each SDRAM memory bank\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRPIPE[1:0]\nRBURST.\nSDCLK[1:0]\nWP\nCAS[1:0]\nNB\nMWID[1:0]\nNR[1:0]\nNC[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:15 Reserved, must be kept at reset value\nBits 14:13 RPIPE[1:0]: Read pipe\nThese bits define the delay, in HCLK clock cycles, for reading data after CAS latency.\n00: No HCLK clock cycle delay \n01: One HCLK clock cycle delay\n10: Two HCLK clock cycle delay\n11: reserved, do not use\nNote: The corresponding bits in the FMC_SDCR2 register are read only.\nBit 12 RBURST: Burst read\nThis bit enables burst read mode. The SDRAM controller anticipates the next read commands\nduring the CAS latency and stores data in the Read FIFO.\n0: single read requests are not managed as bursts\n1: single read requests are always managed as bursts\nNote: The corresponding bit in the FMC_SDCR2 register is don’t care.\nBits 11:10 SDCLK[1:0]: SDRAM clock configuration\nThese bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock \nbefore changing the frequency. In this case the SDRAM must be re-initialized.\n00: SDCLK clock disabled\n01: Reserved\n10: SDCLK period = 2 x HCLK periods\n11: SDCLK period = 3 x HCLK periods\nNote: The corresponding bits in the FMC_SDCR2 register are read only.\nBit 9 WP: Write protection\nThis bit enables write mode access to the SDRAM bank.\n0: Write accesses allowed\n1: Write accesses ignored\nBits 8:7 CAS[1:0]: CAS Latency\nThis bits sets the SDRAM CAS latency in number of memory clock cycles\n00: reserved, do not use.\n01: 1 cycle\n10: 2 cycles\n11: 3 cycles\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1678/1757\nRM0090 Rev 21\nNote:\nBefore modifying the RBURST or RPIPE settings or disabling the SDCLK clock, the user \nmust first send a PALL command to make sure ongoing operations are complete.\nSDRAM Timing registers 1,2 (FMC_SDTR1,2)\nAddress offset: 0x148 + 4 * (x – 1), x = 1,2\nReset value: 0x0FFF FFFF\nThis register contains the timing parameters of each SDRAM bank\n \nBit 6 NB: Number of internal banks\nThis bit sets the number of internal banks.\n0: Two internal Banks\n1: Four internal Banks\nBits 5:4 MWID[1:0]: Memory data bus width.\nThese bits define the memory device width.\n00: 8 bits\n01: 16 bits\n10: 32 bits\n11: reserved, do not use.\nBits 3:2 NR[1:0]: Number of row address bits\nThese bits define the number of bits of a row address.\n00: 11 bit\n01: 12 bits\n10: 13 bits\n11: reserved, do not use.\nBits 1:0 NC[1:0]: Number of column address bits\nThese bits define the number of bits of a column address.\n00: 8 bits\n01: 9 bits\n10: 10 bits\n11: 11 bits.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTRCD[3:0]\nTRP[3:0\nTWR[3:0\nTRC[3:0\nTRAS[3:0\nTXSR[3:0\nTMRD[3:0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value\nBits 27:24 TRCD[3:0]: Row to column delay\nThese bits define the delay between the Activate command and a Read/Write command in number of \nmemory clock cycles.\n0000: 1 cycle.\n0001: 2 cycles\n....\n1111: 16 cycles\n\n\n<>\n\nRM0090 Rev 21\n1679/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nBits 23:20 TRP[3:0]: Row precharge delay\nThese bits define the delay between a Precharge command and another command in number of \nmemory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM \ndevices are used, the TRP must be programmed with the timing of the slowest device.\n0000: 1 cycle\n0001: 2 cycles\n....\n1111: 16 cycles\nNote: The corresponding bits in the FMC_SDTR2 register are don’t care.\nBits 19:16 TWR[3:0]: Recovery delay\nThese bits define the delay between a Write and a Precharge command in number of memory clock \ncycles.\n0000: 1 cycle\n0001: 2 cycles\n....\n1111: 16 cycles\nNote: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM \ndatasheet, and to guarantee that:\nTWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP\nExample: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be \nprogrammed to 0x1.\nIf two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed \nwith the same TWR timing corresponding to the slowest SDRAM device.\nBits 15:12 TRC[3:0]: Row cycle delay\nThese bits define the delay between the Refresh command and the Activate command, as well as d \nthe delay between two consecutive Refresh commands. It is expressed in number of memory clock \ncycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are \nused, the TRC must be programmed with the timings of the slowest device.\n0000: 1 cycle\n0001: 2 cycles\n....\n1111: 16 cycles\nNote: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM \ndevice datasheet.\nNote: The corresponding bits in the FMC_SDTR2 register are don’t care.\nBits 11:8 TRAS[3:0]: Self refresh time\nThese bits define the minimum Self-refresh period in number of memory clock cycles.\n0000: 1 cycle\n0001: 2 cycles\n....\n1111: 16 cycles\nBits 7:4 TXSR[3:0]: Exit Self-refresh delay\nThese bits define the delay from releasing the Self-refresh command to issuing the Activate \ncommand in number of memory clock cycles.\n0000: 1 cycle\n0001: 2 cycles\n....\n1111: 16 cycles\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1680/1757\nRM0090 Rev 21\nNote:\nIf two SDRAM devices are connected, all the accesses performed simultaneously to both \ndevices by the Command Mode register (Load Mode Register and Self-refresh commands) \nare issued using the timing parameters configured for Bank 1 (TMRD, TRAS and TXSR \ntimings) in the FMC_SDTR1 register.\nThe TRP and TRC timings are only configured in the FMC_SDTR1 register. If two SDRAM \ndevices are used, the TRP and TRC timings must be programmed with the timings of the \nslowest device. \nSDRAM Command Mode register (FMC_SDCMR)\nAddress offset: 0x150 \nReset value: 0x0000 0000\nThis register contains the command issued when the SDRAM device is accessed. This \nregister is used to initialize the SDRAM device, and to activate the Self-refresh and the \nPower-down modes. As soon as the MODE field is written, the command is issued only to \none or to both SDRAM banks according to CTB1 and CTB2 command bits. This register is \nthe same for both SDRAM banks.\n \nBits 3:0 TMRD[3:0]: Load Mode Register to Active \nThese bits define the delay between a Load Mode Register command and an Active or Refresh \ncommand in number of memory clock cycles.\n0000: 1 cycle\n0001: 2 cycles\n....\n1111: 16 cycles\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMRD[11:0]\nNRFS[3:0]\nCTB1\nCTB2\nMODE[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nw\nw\nw\nw\nw\nBits 31:22 Reserved, must be kept at reset value\nBits 21:9 MRD[11:0]: Mode Register definition\nThis 13-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using \nthe Load Mode Register command.\nBits 8:5 NRFS[3:0]: Number of Auto-refresh\nThese bits define the number of consecutive Auto-refresh commands issued when MODE = ‘011’.\n0000: 1 Auto-refresh cycle\n0001: 2 Auto-refresh cycles\n....\n1110: 15 Auto-refresh cycles\n1111: Reserved\nBit 4 CTB1: Command Target Bank 1\nThis bit indicates whether the command is issued to SDRAM Bank 1 or not.\n0: Command not issued to SDRAM Bank 1\n1: Command issued to SDRAM Bank 1\n\n\n<>\n\nRM0090 Rev 21\n1681/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nSDRAM Refresh Timer register (FMC_SDRTR)\nAddress offset:0x154\nReset value: 0x0000 0000\nThis register sets the refresh rate in number of SDCLK clock cycles between the refresh \ncycles by configuring the Refresh Timer Count value.\nExample\n \nwhere 64 ms is the SDRAM refresh period.\n \nThe refresh rate must be increased by 20 SDRAM clock cycles (as in the above example) to \nobtain a safe margin if an internal refresh request occurs when a read request has been \naccepted. It corresponds to a COUNT value of ‘0000111000000’ (448). \nThis 13-bit field is loaded into a timer which is decremented using the SDRAM clock. This \ntimer generates a refresh pulse when zero is reached. The COUNT value must be set at \nleast to 41 SDRAM clock cycles.\nAs soon as the FMC_SDRTR register is programmed, the timer starts counting. If the value \nprogrammed in the register is ’0’, no refresh is carried out. This register must not be \nreprogrammed after the initialization procedure to avoid modifying the refresh rate.\nEach time a refresh pulse is generated, this 13-bit COUNT field is reloaded into the counter.\nBit 3 CTB2: Command Target Bank 2\nThis bit indicates whether the command is issued to SDRAM Bank 2 or not.\n0: Command not issued to SDRAM Bank 2\n1: Command issued to SDRAM Bank 2\nBits 2:0 MODE[2:0]: Command mode\nThese bits define the command issued to the SDRAM device.\n000: Normal Mode\n001: Clock Configuration Enable\n010: PALL (“All Bank Precharge”) command\n011: Auto-refresh command\n100: Load Mode Register\n101: Self-refresh command\n110: Power-down command\n111: Reserved\nNote: When a command is issued, at least one Command Target Bank bit ( CBT1 or CBT2) must be \nset. If both banks are used, the commands must be issued to the two banks at the same time \nby setting the CBT1 and CBT2 bits.\nRefresh rate\nSDRAM refresh rate\nSDRAM clock frequency\n×\n(\n)\n20\n–\n=\nSDRAM refresh rate\nSDRAM refresh period\nNumber of rows\n⁄\n=\nSDRAM refresh rate\n64 ms\n8196rows\n(\n)\n⁄\n7.81μs\n=\n=\n7.81μs\n60MHz\n×\n468.6\n=\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1682/1757\nRM0090 Rev 21\nIf a memory access is in progress, the Auto-refresh request is delayed. However, if the \nmemory access and Auto-refresh requests are generated simultaneously, the Auto-refresh \ntakes precedence. If the memory access occurs during a refresh operation, the request is \nbuffered to be processed when the refresh is complete.\nThis register common to SDRAM bank 1 and bank 2.\n .\n \nNote:\nThe programmed COUNT value must not be equal to the sum of the following timings: \nTWR+TRP+TRC+TRCD+4 memory clock cycles . \nSDRAM Status register (FMC_SDSR)\nAddress offset: 0x158\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nREIE\nCOUNT[12:0]\nCRE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nw\nBits 31: 15 Reserved, must be kept at reset value\nBit 14 REIE: RES Interrupt Enable\n0: Interrupt is disabled\n1: An Interrupt is generated if RE = 1\nBits 13:1 COUNT[12:0]: Refresh Timer Count\nThis 13-bit field defines the refresh rate of the SDRAM device. It is expressed in number of memory \nclock cycles. It must be set at least to 41 SDRAM clock cycles (0x29).\nCOUNT = (SDRAM refresh rate x SDRAM clock frequency) - 20\nSDRAM refresh rate = SDRAM refresh period / Number of rows\nBit 0 CRE: Clear Refresh error flag\nThis bit is used to clear the Refresh Error Flag (RE) in the Status Register.\n0: no effect\n1: Refresh Error flag is cleared\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBUSY\nMODES2[1:0]\nMODES1[1:0]\nRE\nr\nr\nr\nr\nr\nr\nBits 31:5 Reserved, must be kept at reset value\nBit 5 BUSY: Busy status \nThis bit defines the status of the SDRAM controller after a Command Mode request\n0: SDRAM Controller is ready to accept a new request\n1; SDRAM Controller is not ready to accept a new request\nBits 4:3 MODES2[1:0]: Status Mode for Bank 2\nThis bit defines the Status Mode of SDRAM Bank 2.\n00: Normal Mode \n01: Self-refresh mode\n10: Power-down mode\n\n\n<>\n\nRM0090 Rev 21\n1683/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n37.8 \nFMC register map \nThe following table summarizes the FMC registers. \n \nBits 2:1 MODES1[1:0]: Status Mode for Bank 1\nThis bit defines the Status Mode of SDRAM Bank 1.\n00: Normal Mode \n01: Self-refresh mode\n10: Power-down mode\nBit 0 RE: Refresh error flag\n0: No refresh error has been detected\n1: A refresh error has been detected\nAn interrupt is generated if REIE = 1 and RE = 1\nTable 298. FMC register map\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nFMC_BCR1\nReserved\nCCLKEN\nCBURSTRW\nCPSIZE[2:0]\nASYNCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[1:0]\nMUXEN\nMBKEN\n0x08\nFMC_BCR2\nReserved\nCBURSTRW\nCPSIZE[2:0]\nASYNCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[1:0]\nMUXEN\nMBKEN\n0x10\nFMC_BCR3\nReserved\nCBURSTRW\nCPSIZE[2:0]\nASYNCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[1:0]\nMUXEN\nMBKEN\n0x18\nFMC_BCR4\nReserved\nCBURSTRW\nCPSIZE[2:0]\nASYNCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[1:0]\nMUXEN\nMBKEN\n0x04\nFMC_BTR1\nRes.\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0] BUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0] ADDSET[3:0]\n0x0C\nFMC_BTR2\nRes.\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0] BUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0] ADDSET[3:0]\n0x14\nFMC_BTR3\nRes.\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0] BUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0] ADDSET[3:0]\n0x1C\nFMC_BTR4\nRes.\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0] BUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0] ADDSET[3:0]\n0x104\nFMC_BWTR1\nRes.\nACCMOD[1:0]\nRes.\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0] ADDSET[3:0]\n\n\n<>\n\nFlexible memory controller (FMC)\nRM0090\n1684/1757\nRM0090 Rev 21\n0x10C\nFMC_BWTR2\nRes.\nACCMOD[1:0]\nRes.\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0] ADDSET[3:0]\n0x104\nFMC_BWTR3\nRes.\nACCMOD[1:0]\nRes.\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0] ADDSET[3:0]\n0x10C\nFMC_BWTR4\nRes.\nACCMOD[1:0]\nRes.\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0] ADDSET[3:0]\n0x60\nFMC_PCR2\nReserved\nECCPS[2:0]\nTAR[3:0]\nTCLR[3:0]\nRes.\nECCEN\nPWID[1:0]\nPTYP\nPBKEN\nPWAITEN\nReserved\n0x80\nFMC_PCR3\nReserved\nECCPS[2:0]\nTAR[3:0]\nTCLR[3:0]\nRes.\nECCEN\nPWID[1:0]\nPTYP\nPBKEN\nPWAITEN\nReserved\n0xA0\nFMC_PCR4\nReserved\nECCPS[2:0]\nTAR[3:0]\nTCLR[3:0]\nRes.\nECCEN\nPWID[1:0]\nPTYP\nPBKEN\nPWAITEN\nReserved\n0x64\nFMC_SR2\nReserved\nFEMPT\nIFEN\nILEN\nIREN\nIFS\nILS\nIRS\n0x84\nFMC_SR3\nReserved\nFEMPT\nIFEN\nILEN\nIREN\nIFS\nILS\nIRS\n0xA4\nFMC_SR4\nReserved\nFEMPT\nIFEN\nILEN\nIREN\nIFS\nILS\nIRS\n0x68\nFMC_PMEM2\nMEMHIZ[7:0]\nMEMHOLD[7:0]\nMEMWAIT[7:0]\nMEMSET[7:0]\n0x88\nFMC_PMEM3\nMEMHIZ[7:0]\nMEMHOLD[7:0]\nMEMWAIT[7:0]\nMEMSET[7:0]\n0xA8\nFMC_PMEM4\nMEMHIZ[7:0]\nMEMHOLD[7:0]\nMEMWAIT[7:0]\nMEMSET[7:0]\n0x6C\nFMC_PATT2\nATTHIZ[7:0]\nATTHOLD[7:0]\nATTWAIT[7:0]\nATTSET[7:0]\n0x8C\nFMC_PATT3\nATTHIZ[7:0]\nATTHOLD[7:0]\nATTWAIT[7:0]\nATTSET[7:0]\n0xAC\nFMC_PATT4\nATTHIZ[7:0]\nATTHOLD[7:0]\nATTWAIT[7:0]\nATTSET[7:0]\n0xB0\nFMC_PIO4\nIOHIZ[7:0]\nIOHOLD[7:0]\nIOWAIT[7:0]\nIOSET[7:0]\n0x74\nFMC_ECCR2\nECC[31:0]\n0x94\nFMC_ECCR3\nECC[31:0]\n0x140\nFMC_SDCR_1\nReserved\nRPIPE[1:0]\nRBURST\nCLK[1:0]\nWP\nCAS[1:0]\nNB\nMWID[1:0]\nNR[1:0]\nNC[1:0]\n0x144\nFMC_SDCR_2\nReserved\nCLK[1:0]\nWP\nCAS[1:0]\nNB\nMWID[1:0]\nNR[1:0]\nNC[1:0]\n0x148\nFMC_SDTR1\nReserved\nTRCD[3:0]\nTRP[3:0]\nTWR[3:0]\nTRC[3:0]\nTRAS[3:0]\nTXSR[3:0]\nTMRD[3:0]\n0x14C\nFMC_SDTR2\nReserved\nTRCD[3:0]\nTRP[3:0]\nTWR[3:0]\nTRC[3:0]\nTRAS[3:0]\nTXSR[3:0]\nTMRD[3:0]\n0x150\nFMC_SDCMR\nReserved\nMRD[12:0]\nNRFS[3:0]\nCTB1\nCTB2\nMODE[2:0]\nTable 298. FMC register map (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nRM0090 Rev 21\n1685/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n0x154\nFMC_SDRTR\nReserved\nREIE\nCOUNT[12:0]\nCRE\n0x158\nFMC_SDSR\nReserved\nBUSY\nMODES2[1:0]\nMODES1[1:0]\nRE\nTable 298. FMC register map (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n\n\n<>\n\nDebug support (DBG)\nRM0090\n1686/1757\nRM0090 Rev 21\n38 \nDebug support (DBG)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n38.1 \nOverview\nThe STM32F4xx are built around a Cortex®-M4 with FPU core, which contains hardware \nextensions for advanced debugging features. The debug extensions allow the core to be \nstopped either on a given instruction fetch (breakpoint), or on data access (watchpoint). \nWhen stopped, the core’s internal state and the system’s external state may be examined. \nOnce examination is complete, the core and the system may be restored and program \nexecution resumed.\nThe debug features are used by the debugger host when connecting to and debugging the \nSTM32F4xx MCUs.\nTwo interfaces for debug are available:\n•\nSerial wire\n•\nJTAG debug port\nFigure 485. Block diagram of STM32 MCU and Cortex®-M4 with FPU-level debug \nsupport\nNote:\nThe debug features embedded in the Cortex®-M4 with FPU core are a subset of the Arm® \nCoreSight Design Kit.\nestricted Di\nCortex-M4\ncore\nSWJ-DP\nAHB-AP\nBridge\nNVIC\nDWT\nFPB\nITM\nTPIU\nDCode\ninterface\nSystem\ninterface\nInternal private\nperipheral bus (PPB)\nExternal private\nperipheral bus (PPB)\nBus matrix\nData\nTrace port\nDBGMCU\nSTM32F4xx debug support \n \nCortex-M4 debug suppo rt\nJTMS/\nJTDI\nJTDO/\nNJTRST\nJTCK/\nSWDIO\nSWCLK\nTRACESWO\nTRACESWO\nTRACECK\nTRACED[3:0]\nMS19908V3\n\n\n<>\n\nRM0090 Rev 21\n1687/1757\nRM0090\nDebug support (DBG)\n1716\nThe Arm® Cortex®-M4 with FPU core provides integrated on-chip debug support. It is \ncomprised of:\n•\nSWJ-DP: Serial wire / JTAG debug port\n•\nAHP-AP: AHB access port\n•\nITM: Instrumentation trace macrocell\n•\nFPB: Flash patch breakpoint\n•\nDWT: Data watchpoint trigger\n•\nTPUI: Trace port unit interface (available on larger packages, where the corresponding \npins are mapped)\n•\nETM: Embedded Trace Macrocell (available on larger packages, where the \ncorresponding pins are mapped)\nIt also includes debug features dedicated to the STM32F4xx:\n•\nFlexible debug pinout assignment\n•\nMCU debug box (support for low-power modes, control over peripheral clocks, etc.)\nNote:\nFor further information on debug functionality supported by the Arm® Cortex®-M4 with FPU \ncore, refer to the Cortex®-M4 with FPU -r0p1 Technical Reference Manual and to the \nCoreSight Design Kit-r0p1 TRM (see Section 38.2).\n38.2 \nReference Arm® documentation\n•\nCortex®-M4 with FPU r0p1 Technical Reference Manual (TRM)\n(see Related documents on page 1)\n•\nArm® Debug Interface V5\n•\nArm® CoreSight Design Kit revision r0p1 Technical Reference Manual\n38.3 \nSWJ debug port (serial wire and JTAG)\nThe core of the STM32F4xx integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an \nArm® standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW-\nDP (2-pin) interface.\n•\nThe JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the \nAHP-AP port.\n•\nThe Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the \nAHP-AP port.\nIn the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG \npins of the JTAG-DP.\n\n\n<>\n\nDebug support (DBG)\nRM0090\n1688/1757\nRM0090 Rev 21\nFigure 486. SWJ debug port\nFigure 486 shows that the asynchronous TRACE output (TRACESWO) is multiplexed with \nTDO. This means that the asynchronous trace can only be used with SW-DP, not JTAG-DP. \n38.3.1 \nMechanism to select the JTAG-DP or the SW-DP\nBy default, the JTAG-Debug Port is active.\nIf the debugger host wants to switch to the SW-DP, it must provide a dedicated JTAG \nsequence on TMS/TCK (respectively mapped to SWDIO and SWCLK) which disables the \nJTAG-DP and enables the SW-DP. This way it is possible to activate the SWDP using only \nthe SWCLK and SWDIO pins.\nThis sequence is:\n1.\nSend more than 50 TCK cycles with TMS (SWDIO) =1\n2. \nSend the 16-bit sequence on TMS (SWDIO) = 0111100111100111 (MSB transmitted \nfirst)\n3. \nSend more than 50 TCK cycles with TMS (SWDIO) =1\n38.4 \nPinout and debug port pins\nThe STM32F4xx MCUs are available in various packages with different numbers of \navailable pins. As a result, some functionality (ETM) related to pin availability may differ \nbetween packages.\n\n\n<>\n\nRM0090 Rev 21\n1689/1757\nRM0090\nDebug support (DBG)\n1716\n38.4.1 \nSWJ debug port pins\nFive pins are used as outputs from the STM32F4xx for the SWJ-DP as alternate functions of \ngeneral-purpose I/Os. These pins are available on all packages.\n \n38.4.2 \nFlexible SWJ-DP pin assignment\nAfter RESET (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned \nas dedicated pins immediately usable by the debugger host (note that the trace outputs are \nnot assigned except if explicitly programmed by the debugger host).\nHowever, the STM32F4xx MCUs offers the possibility of disabling some or all of the SWJ-\nDP ports and so, of releasing the associated pins for general-purpose IO (GPIO) usage. For \nmore details on how to disable SWJ-DP port pins, please refer to Section 8.3.2: I/O pin \nmultiplexer and mapping.\n \n38.4.3 \nInternal pull-up and pull-down on JTAG pins\nIt is necessary to ensure that the JTAG input pins are not floating since they are directly \nconnected to flip-flops to control the debug mode features. Special care must be taken with \nthe SWCLK/TCK pin which is directly connected to the clock of some of these flip-flops.\nTable 299. SWJ debug port pins\nSWJ-DP pin name\nJTAG debug port\nSW debug port\nPin \nassignment\nType\nDescription\nType\nDebug assignment\nJTMS/SWDIO\nI\nJTAG Test Mode Selection\nIO\nSerial Wire Data Input/Output\nPA13\nJTCK/SWCLK\nI\nJTAG Test Clock\nI\nSerial Wire Clock\nPA14\nJTDI\nI\nJTAG Test Data Input\n-\n-\nPA15\nJTDO/TRACESWO\nO\nJTAG Test Data Output\n-\nTRACESWO if async trace is \nenabled\nPB3\nNJTRST\nI\nJTAG Test nReset\n-\n-\nPB4\nTable 300. Flexible SWJ-DP pin assignment\nAvailable debug ports\nSWJ IO pin assigned\nPA13 /\nJTMS /\nSWDIO\nPA14 /\nJTCK /\nSWCLK\nPA15 /\nJTDI\nPB3 / \nJTDO\nPB4 /\nNJTRST\nFull SWJ (JTAG-DP + SW-DP) - Reset State\nX\nX\nX\nX\nX\nFull SWJ (JTAG-DP + SW-DP) but without NJTRST\nX\nX\nX\nX\nJTAG-DP Disabled and SW-DP Enabled\nX\nX\nJTAG-DP Disabled and SW-DP Disabled\nReleased\n\n\n<>\n\nDebug support (DBG)\nRM0090\n1690/1757\nRM0090 Rev 21\nTo avoid any uncontrolled IO levels, the device embeds internal pull-ups and pull-downs on \nthe JTAG input pins:\n•\nNJTRST: Internal pull-up\n•\nJTDI: Internal pull-up\n•\nJTMS/SWDIO: Internal pull-up\n•\nTCK/SWCLK: Internal pull-down\nOnce a JTAG IO is released by the user software, the GPIO controller takes control again. \nThe reset states of the GPIO control registers put the I/Os in the equivalent state:\n•\nNJTRST: AF input pull-up\n•\nJTDI: AF input pull-up\n•\nJTMS/SWDIO: AF input pull-up\n•\nJTCK/SWCLK: AF input pull-down \n•\nJTDO: AF output floating\nThe software can then use these I/Os as standard GPIOs.\nNote:\nThe JTAG IEEE standard recommends to add pull-ups on TDI, TMS and nTRST but there is \nno special recommendation for TCK. However, for JTCK, the device needs an integrated \npull-down.\nHaving embedded pull-ups and pull-downs removes the need to add external resistors.\n\n\n<>\n\nRM0090 Rev 21\n1691/1757\nRM0090\nDebug support (DBG)\n1716\n38.4.4 \nUsing serial wire and releasing the unused debug pins as GPIOs\nTo use the serial wire DP to release some GPIOs, the user software must change the GPIO \n(PA15, PB3 and PB4) configuration mode in the GPIO_MODER register. This releases \nPA15, PB3 and PB4 which now become available as GPIOs.\nWhen debugging, the host performs the following actions:\n•\nUnder system reset, all SWJ pins are assigned (JTAG-DP + SW-DP).\n•\nUnder system reset, the debugger host sends the JTAG sequence to switch from the \nJTAG-DP to the SW-DP.\n•\nStill under system reset, the debugger sets a breakpoint on vector reset.\n•\nThe system reset is released and the Core halts.\n•\nAll the debug communications from this point are done using the SW-DP. The other \nJTAG pins can then be reassigned as GPIOs by the user software.\nNote:\nFor user software designs, note that:\nTo release the debug pins, remember that they are first configured either in input-pull-up \n(nTRST, TMS, TDI) or pull-down (TCK) or output tristate (TDO) for a certain duration after \nreset until the instant when the user software releases the pins.\nWhen debug pins (JTAG or SW or TRACE) are mapped, changing the corresponding IO pin \nconfiguration in the IOPORT controller has no effect.\n38.5 \nSTM32F4xx JTAG TAP connection\nThe STM32F4xx MCUs integrate two serially connected JTAG TAPs, the boundary scan \nTAP (IR is 5-bit wide) and the Cortex®-M4 with FPU TAP (IR is 4-bit wide).\nTo access the TAP of the Cortex®-M4 with FPU for debug purposes:\n1.\nFirst, it is necessary to shift the BYPASS instruction of the boundary scan TAP.\n2. \nThen, for each IR shift, the scan chain contains 9 bits (=5+4) and the unused TAP \ninstruction must be shifted in using the BYPASS instruction.\n3. \nFor each data shift, the unused TAP, which is in BYPASS mode, adds 1 extra data bit in \nthe data scan chain.\nNote:\nImportant: Once Serial-Wire is selected using the dedicated Arm® JTAG sequence, the \nboundary scan TAP is automatically disabled (JTMS forced high).\n\n\n<>\n\nDebug support (DBG)\nRM0090\n1692/1757\nRM0090 Rev 21\nFigure 487. JTAG TAP connections\nBoundary scan\nTAP\nNJTRST\nCortex-M4 TAP \nJTMS\nTMS nTRST\nTMS nTRST\nJTDI\nJTDO\nTDI\nTDO\nTDI\nTDO\nSW-DP\nSTM32F4xxx\nSelected\nIR is 5-bit wide\nIR is 4-bit wide\nMS19929V2\n\n\n<>\n\nRM0090 Rev 21\n1693/1757\nRM0090\nDebug support (DBG)\n1716\n38.6 \nID codes and locking mechanism\nThere are several ID codes inside the STM32F4xx MCUs. ST strongly recommends tools \ndesigners to lock their debuggers using the MCU DEVICE ID code located in the external \nPPB memory map at address 0xE0042000.\n38.6.1 \nMCU device ID code\nThe STM32F4xx MCUs integrate an MCU ID code. This ID identifies the ST MCU part-\nnumber and the die revision. It is part of the DBG_MCU component and is mapped on the \nexternal PPB bus (see Section 38.16). This code is accessible using the JTAG debug port \n(four to five pins) or the SW debug port (two pins) or by the user software. It is even \naccessible while the MCU is under system reset. \nOnly the DEV_ID[11:0] must be used for identification by the debugger/programmer tools.\nDBGMCU_IDCODE\nAddress: 0xE004 2000\nOnly 32-bits access supported. Read-only.\n \n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nREV_ID[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDEV_ID[11:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 REV_ID[15:0] Revision identifier\nThis field indicates the revision of the device.\nSTM32F405xx/07xx and STM32F415xx/17xx devices:\n0x1000 = Revision A\n0x1001 = Revision Z\n0x1003 = Revision 1\n0x1007 = Revision 2\n0x100F= Revision Y and 4\n0x101F= Revision 5 and 6\nSTM32F42xxx and STM32F43xxx devices:\n0x1000 = Revision A\n0x1003 = Revision Y\n0x1007 = Revision 1\n0x2001= Revision 3\n0x2003= Revision 4, 5 and B\nBits 15:12 Reserved, must be kept at reset value.\nBits 11:0 DEV_ID[11:0]: Device identifier (STM32F405xx/07xx and STM32F415xx/17xx)\nThe device ID is 0x413.\nBits 11:0 DEV_ID[11:0]: Device identifier (STM32F42xxx and STM32F43xxx)\nThe device ID is 0x419\n\n\n<>\n\nDebug support (DBG)\nRM0090\n1694/1757\nRM0090 Rev 21\n38.6.2 \nBoundary scan TAP\nJTAG ID code\nThe TAP of the STM32F4xx BSC (boundary scan) integrates a JTAG ID code equal to .\n•\n0x06413041 for STM32F405xx/07xx and STM32F415xx/17xx devices\n•\n0x06419041 for STM32F42xxx and STM32F43xxx devices \n38.6.3 \nCortex®-M4 with FPU TAP\nThe TAP of the Arm® Cortex®-M4 with FPU integrates a JTAG ID code. This ID code is the \nArm® default one and has not been modified. This code is only accessible by the JTAG \nDebug Port, it is 0x4BA00477 (corresponds to Cortex®-M4 with FPU r0p1, see \nSection 38.2).\n38.6.4 \nCortex®-M4 with FPU JEDEC-106 ID code\nThe Arm® Cortex®-M4 with FPU integrates a JEDEC-106 ID code. It is located in the 4 KB \nROM table mapped on the internal PPB bus at address 0xE00FF000_0xE00FFFFF. \nThis code is accessible by the JTAG Debug Port (4 to 5 pins) or by the SW Debug Port (two \npins) or by the user software.\n38.7 \nJTAG debug port\nA standard JTAG state machine is implemented with a 4-bit instruction register (IR) and five \ndata registers (for full details, refer to the Cortex®-M4 with FPU r0p1 Technical Reference \nManual (TRM), for references, see Section 38.2).\n \nTable 301. JTAG debug port data registers\nIR(3:0)\nData register\nDetails\n1111\nBYPASS\n[1 bit]\n-\n1110\nIDCODE\n[32 bits]\nID CODE\n0x4BA00477 (Arm® Cortex®-M4 with FPU r0p1 ID Code)\n1010\nDPACC \n[35 bits]\nDebug port access register\nThis initiates a debug port and allows access to a debug port register.\n– When transferring data IN: \nBits 34:3 = DATA[31:0] = 32-bit data to transfer for a write request\nBits 2:1 = A[3:2] = 2-bit address of a debug port register.\nBit 0 = RnW = Read request (1) or write request (0).\n– When transferring data OUT: \nBits 34:3 = DATA[31:0] = 32-bit data which is read following a read \nrequest\nBits 2:0 = ACK[2:0] = 3-bit Acknowledge:\n010 = OK/FAULT\n001 = WAIT\nOTHER = reserved\nRefer to Table 302 for a description of the A[3:2] bits\n\n\n<>\n\nRM0090 Rev 21\n1695/1757\nRM0090\nDebug support (DBG)\n1716\n \n1011\nAPACC\n[35 bits]\nAccess port access register\nInitiates an access port and allows access to an access port register.\n– When transferring data IN: \nBits 34:3 = DATA[31:0] = 32-bit data to shift in for a write request\nBits 2:1 = A[3:2] = 2-bit address (sub-address AP registers).\nBit 0 = RnW= Read request (1) or write request (0).\n– When transferring data OUT: \nBits 34:3 = DATA[31:0] = 32-bit data which is read following a read \nrequest \nBits 2:0 = ACK[2:0] = 3-bit Acknowledge:\n010 = OK/FAULT\n001 = WAIT\nOTHER = reserved\nThere are many AP registers (see AHB-AP) addressed as the \ncombination of:\n– The shifted value A[3:2]\n– The current value of the DP SELECT register\n1000\nABORT\n[35 bits]\nAbort register\n– Bits 31:1 = Reserved\n– Bit 0 = DAPABORT: write 1 to generate a DAP abort.\nTable 302. 32-bit debug port registers addressed through the shifted value A[3:2] \nAddress\nA[3:2] value\nDescription\n0x0\n00\nReserved, must be kept at reset value.\n0x4\n01\nDP CTRL/STAT register. Used to:\n– Request a system or debug power-up\n– Configure the transfer operation for AP accesses\n– Control the pushed compare and pushed verify operations.\n– Read some status flags (overrun, power-up acknowledges)\n0x8\n10\nDP SELECT register: Used to select the current access port and the \nactive 4-words register window.\n– Bits 31:24: APSEL: select the current AP\n– Bits 23:8: reserved\n– Bits 7:4: APBANKSEL: select the active 4-words register window on the \ncurrent AP\n– Bits 3:0: reserved\n0xC\n11\nDP RDBUFF register: Used to allow the debugger to get the final result \nafter a sequence of operations (without requesting new JTAG-DP \noperation)\nTable 301. JTAG debug port data registers (continued)\nIR(3:0)\nData register\nDetails\n\n\n<>\n\nDebug support (DBG)\nRM0090\n1696/1757\nRM0090 Rev 21\n38.8 \nSW debug port\n38.8.1 \nSW protocol introduction\nThis synchronous serial protocol uses two pins:\n•\nSWCLK: clock from host to target\n•\nSWDIO: bidirectional\nThe protocol allows two banks of registers (DPACC registers and APACC registers) to be \nread and written to.\nBits are transferred LSB-first on the wire.\nFor SWDIO bidirectional management, the line must be pulled-up on the board (100 KΩ \nrecommended by Arm®).\nEach time the direction of SWDIO changes in the protocol, a turnaround time is inserted \nwhere the line is not driven by the host nor the target. By default, this turnaround time is one \nbit time, however this can be adjusted by configuring the SWCLK frequency.\n38.8.2 \nSW protocol sequence\nEach sequence consist of three phases:\n1.\nPacket request (8 bits) transmitted by the host \n2. \nAcknowledge response (3 bits) transmitted by the target\n3. \nData transfer phase (33 bits) transmitted by the host or the target\n \nRefer to the Cortex®-M4 with FPU r0p1 TRM for a detailed description of DPACC and \nAPACC registers.\nThe packet request is always followed by the turnaround time (default 1 bit) where neither \nthe host nor target drive the line.\nTable 303. Packet request (8-bits)\nBit\nName\nDescription\n0\nStart\nMust be “1”\n1\nAPnDP\n0: DP Access\n1: AP Access\n2\nRnW\n0: Write Request\n1: Read Request\n4:3\nA[3:2]\nAddress field of the DP or AP registers (refer to Table 302)\n5\nParity\nSingle bit parity of preceding bits\n6\nStop\n0\n7\nPark\nNot driven by the host. Must be read as “1” by the target because of \nthe pull-up\n\n\n<>\n\nRM0090 Rev 21\n1697/1757\nRM0090\nDebug support (DBG)\n1716\n \nThe ACK Response must be followed by a turnaround time only if it is a READ transaction \nor if a WAIT or FAULT acknowledge has been received.\n \nThe DATA transfer must be followed by a turnaround time only if it is a READ transaction.\n38.8.3 \nSW-DP state machine (reset, idle states, ID code)\nThe State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It \nfollows the JEP-106 standard. This ID code is the default Arm® one and is set to \n0x2BA01477 (corresponding to Cortex®-M4 with FPU r0p1). \nNote:\nNote that the SW-DP state machine is inactive until the target reads this ID code.\n•\nThe SW-DP state machine is in RESET STATE either after power-on reset, or after the \nDP has switched from JTAG to SWD or after the line is high for more than 50 cycles \n•\nThe SW-DP state machine is in IDLE STATE if the line is low for at least two cycles \nafter RESET state.\n•\nAfter RESET state, it is mandatory to first enter into an IDLE state AND to perform a \nREAD access of the DP-SW ID CODE register. Otherwise, the target issues a FAULT \nacknowledge response on another transactions.\nFurther details of the SW-DP state machine can be found in the Cortex®-M4 with FPU r0p1 \nTRM and the CoreSight Design Kit r0p1 TRM.\n38.8.4 \nDP and AP read/write accesses\n•\nRead accesses to the DP are not posted: the target response can be immediate (if \nACK=OK) or can be delayed (if ACK=WAIT).\n•\nRead accesses to the AP are posted. This means that the result of the access is \nreturned on the next transfer. If the next access to be done is NOT an AP access, then \nthe DP-RDBUFF register must be read to obtain the result.\nThe READOK flag of the DP-CTRL/STAT register is updated on every AP read access \nor RDBUFF read request to know if the AP read access was successful.\n•\nThe SW-DP implements a write buffer (for both DP or AP writes), that enables it to \naccept a write operation even when other transactions are still outstanding. If the write \nbuffer is full, the target acknowledge response is “WAIT”. With the exception of \nTable 304. ACK response (3 bits)\nBit\nName\nDescription\n0..2\nACK\n001: FAULT\n010: WAIT\n100: OK\nTable 305. DATA transfer (33 bits)\nBit\nName\nDescription\n0..31\nWDATA or RDATA\nWrite or Read data\n32\nParity\nSingle parity of the 32 data bits\n\n\n<>\n\nDebug support (DBG)\nRM0090\n1698/1757\nRM0090 Rev 21\nIDCODE read or CTRL/STAT read or ABORT write which are accepted even if the write \nbuffer is full.\n•\nBecause of the asynchronous clock domains SWCLK and HCLK, two extra SWCLK \ncycles are needed after a write transaction (after the parity bit) to make the write \neffective internally. These cycles must be applied while driving the line low (IDLE state)\nThis is particularly important when writing the CTRL/STAT for a power-up request. If the \nnext transaction (requiring a power-up) occurs immediately, it fails.\n38.8.5 \nSW-DP registers\nAccess to these registers are initiated when APnDP=0\n \n38.8.6 \nSW-AP registers\nAccess to these registers are initiated when APnDP=1\nThere are many AP registers (see AHB-AP) addressed as the combination of:\n•\nThe shifted value A[3:2]\n•\nThe current value of the DP SELECT register\nTable 306. SW-DP registers\nA[3:2]\nR/W\nCTRLSEL bit \nof SELECT \nregister\nRegister\nNotes\n00\nRead\n-\nIDCODE\nThe manufacturer code is not set to ST code. \n0x2BA01477 (identifies the SW-DP)\n00\nWrite\n-\nABORT\n-\n01\nRead/Write\n0\nDP-\nCTRL/STAT\nPurpose is to:\n– request a system or debug power-up\n– configure the transfer operation for AP \naccesses\n– control the pushed compare and pushed verify \noperations.\n– read some status flags (overrun, power-up \nacknowledges)\n01\nRead/Write\n1\nWIRE \nCONTROL\nPurpose is to configure the physical serial port \nprotocol (like the duration of the turnaround \ntime)\n10\nRead\n-\nREAD \nRESEND\nEnables recovery of the read data from a \ncorrupted debugger transfer, without repeating \nthe original AP transfer.\n10\nWrite\n-\nSELECT\nThe purpose is to select the current access port \nand the active 4-words register window\n11\nRead/Write\n-\nREAD \nBUFFER\nThis read buffer is useful because AP accesses \nare posted (the result of a read AP request is \navailable on the next AP transaction).\nThis read buffer captures data from the AP, \npresented as the result of a previous read, \nwithout initiating a new transaction\n\n\n<>\n\nRM0090 Rev 21\n1699/1757\nRM0090\nDebug support (DBG)\n1716\n38.9 \nAHB-AP (AHB access port) - valid for both JTAG-DP\nand SW-DP\nFeatures:\n•\nSystem access is independent of the processor status. \n•\nEither SW-DP or JTAG-DP accesses AHB-AP.\n•\nThe AHB-AP is an AHB master into the Bus Matrix. Consequently, it can access all the \ndata buses (Dcode Bus, System Bus, internal and external PPB bus) but the ICode \nbus.\n•\nBitband transactions are supported.\n•\nAHB-AP transactions bypass the FPB.\nThe address of the 32-bits AHP-AP resisters are 6-bits wide (up to 64 words or 256 bytes) \nand consists of:\nc) \nBits [7:4] = the bits [7:4] APBANKSEL of the DP SELECT register\nd) \nBits [3:2] = the 2 address bits of A[3:2] of the 35-bit packet request for SW-DP.\nThe AHB-AP of the Cortex®-M4 with FPU includes 9 x 32-bits registers:\n \nRefer to the Cortex®-M4 with FPU r0p1 TRM for further details.\nTable 307. Cortex®-M4 with FPU AHB-AP registers\nAddress \noffset\nRegister name\nNotes\n0x00\nAHB-AP Control and Status \nWord\nConfigures and controls transfers through the AHB \ninterface (size, hprot, status on current transfer, address \nincrement type\n0x04\nAHB-AP Transfer Address\n-\n0x0C\nAHB-AP Data Read/Write\n-\n0x10\nAHB-AP Banked Data 0 \nDirectly maps the 4 aligned data words without rewriting \nthe Transfer Address register.\n0x14\nAHB-AP Banked Data 1 \n0x18\nAHB-AP Banked Data 2 \n0x1C\nAHB-AP Banked Data 3 \n0xF8\nAHB-AP Debug ROM Address\nBase Address of the debug interface\n0xFC\nAHB-AP ID register\n-\n\n\n<>\n\nDebug support (DBG)\nRM0090\n1700/1757\nRM0090 Rev 21\n38.10 \nCore debug\nCore debug is accessed through the core debug registers. Debug access to these registers \nis by means of the Advanced High-performance Bus (AHB-AP) port. The processor can \naccess these registers directly over the internal Private Peripheral Bus (PPB).\nIt consists of 4 registers:\n \nNote:\nImportant: these registers are not reset by a system reset. They are only reset by a power-\non reset.\nRefer to the Cortex®-M4 with FPU r0p1 TRM for further details.\nTo Halt on reset, it is necessary to:\n•\nenable the bit0 (VC_CORRESET) of the Debug and Exception Monitor Control register\n•\nenable the bit0 (C_DEBUGEN) of the Debug Halting Control and Status register.\nTable 308. Core debug registers\nRegister\nDescription\nDHCSR\nThe 32-bit Debug Halting Control and Status register\nThis provides status information about the state of the processor enable core debug \nhalt and step the processor\nDCRSR\nThe 17-bit Debug Core register Selector register: \nThis selects the processor register to transfer data to or from.\nDCRDR\nThe 32-bit Debug Core register Data register: \nThis holds data for reading and writing registers to and from the processor selected \nby the DCRSR (Selector) register.\nDEMCR\nThe 32-bit Debug Exception and Monitor Control register: \nThis provides Vector Catching and Debug Monitor Control. This register contains a \nbit named TRCENA which enable the use of a TRACE.\n\n\n<>\n\nRM0090 Rev 21\n1701/1757\nRM0090\nDebug support (DBG)\n1716\n38.11 \nCapability of the debugger host to connect under system \nreset\nThe reset system of the STM32F4xx MCU comprises the following reset sources:\n•\nPOR (power-on reset) which asserts a RESET at each power-up.\n•\nInternal watchdog reset\n•\nSoftware reset\n•\nExternal reset\nThe Cortex®-M4 with FPU differentiates the reset of the debug part (generally \nPORRESETn) and the other one (SYSRESETn)\nThis way, it is possible for the debugger to connect under System Reset, programming the \nCore Debug registers to halt the core when fetching the reset vector. Then the host can \nrelease the system reset and the core immediately halts without having executed any \ninstructions. In addition, it is possible to program any debug features under System Reset.\nNote:\nIt is highly recommended for the debugger host to connect (set a breakpoint in the reset \nvector) under system reset.\n38.12 \nFPB (Flash patch breakpoint)\nThe FPB unit:\n•\nimplements hardware breakpoints\n•\npatches code and data from code space to system space. This feature gives the \npossibility to correct software bugs located in the Code Memory Space.\nThe use of a Software Patch or a Hardware Breakpoint is exclusive.\nThe FPB consists of:\n•\n2 literal comparators for matching against literal loads from Code Space and remapping \nto a corresponding area in the System Space.\n•\n6 instruction comparators for matching against instruction fetches from Code Space. \nThey can be used either to remap to a corresponding area in the System Space or to \ngenerate a Breakpoint Instruction to the core.\n\n\n<>\n\nDebug support (DBG)\nRM0090\n1702/1757\nRM0090 Rev 21\n38.13 \nDWT (data watchpoint trigger)\nThe DWT unit consists of four comparators. They are configurable as:\n•\na hardware watchpoint or\n•\na trigger to an ETM or\n•\na PC sampler or\n•\na data address sampler\nThe DWT also provides some means to give some profiling informations. For this, some \ncounters are accessible to give the number of:\n•\nClock cycle\n•\nFolded instructions\n•\nLoad store unit (LSU) operations\n•\nSleep cycles\n•\nCPI (clock per instructions)\n•\nInterrupt overhead\n38.14 \nITM (instrumentation trace macrocell)\n38.14.1 \nGeneral description\nThe ITM is an application-driven trace source that supports printf style debugging to trace \nOperating System (OS) and application events, and emits diagnostic system information. \nThe ITM emits trace information as packets which can be generated as:\n•\nSoftware trace. Software can write directly to the ITM stimulus registers to emit \npackets.\n•\nHardware trace. The DWT generates these packets, and the ITM emits them.\n•\nTime stamping. Timestamps are emitted relative to packets. The ITM contains a 21-bit \ncounter to generate the timestamp. The Cortex®-M4 with FPU clock or the bit clock rate \nof the Serial Wire Viewer (SWV) output clocks the counter.\nThe packets emitted by the ITM are output to the TPIU (Trace Port Interface Unit). The \nformatter of the TPIU adds some extra packets (refer to TPIU) and then output the complete \npackets sequence to the debugger host.\nThe bit TRCEN of the Debug Exception and Monitor Control register must be enabled \nbefore programming or using the ITM.\n38.14.2 \nTime stamp packets, synchronization and overflow packets\nTime stamp packets encode time stamp information, generic control and synchronization. It \nuses a 21-bit timestamp counter (with possible prescalers) which is reset at each time \nstamp packet emission. This counter can be either clocked by the CPU clock or the SWV \nclock.\nA synchronization packet consists of 6 bytes equal to 0x80_00_00_00_00_00 which is \nemitted to the TPIU as 00 00 00 00 00 80 (LSB emitted first). \nA synchronization packet is a timestamp packet control. It is emitted at each DWT trigger. \n\n\n<>\n\nRM0090 Rev 21\n1703/1757\nRM0090\nDebug support (DBG)\n1716\nFor this, the DWT must be configured to trigger the ITM: the bit CYCCNTENA (bit0) of the \nDWT Control register must be set. In addition, the bit2 (SYNCENA) of the ITM Trace Control \nregister must be set.\nNote:\nIf the SYNENA bit is not set, the DWT generates Synchronization triggers to the TPIU which \nsends only TPIU synchronization packets and not ITM synchronization packets.\nAn overflow packet consists is a special timestamp packets which indicates that data has \nbeen written but the FIFO was full.\n \nTable 309. Main ITM registers\nAddress\nRegister\nDetails\n@E0000FB0\nITM lock access\nWrite 0xC5ACCE55 to unlock Write Access to the other ITM \nregisters\n@E0000E80\nITM trace control\nBits 31-24 = Always 0\nBits 23 = Busy\nBits 22-16 = 7-bits ATB ID which identifies the source of the \ntrace data.\nBits 15-10 = Always 0\nBits 9:8 = TSPrescale = Time Stamp Prescaler\nBits 7-5 = Reserved\nBit 4 = SWOENA = Enable SWV behavior (to clock the \ntimestamp counter by the SWV clock).\nBit 3 = DWTENA: Enable the DWT Stimulus\nBit 2 = SYNCENA: this bit must be to 1 to enable the DWT to \ngenerate synchronization triggers so that the TPIU can then \nemit the synchronization packets.\nBit 1 = TSENA (Timestamp Enable)\nBit 0 = ITMENA: Global Enable Bit of the ITM\n@E0000E40\nITM trace privilege\nBit 3: mask to enable tracing ports31:24\nBit 2: mask to enable tracing ports23:16\nBit 1: mask to enable tracing ports15:8\nBit 0: mask to enable tracing ports7:0\n@E0000E00\nITM trace enable\nEach bit enables the corresponding Stimulus port to generate \ntrace.\n@E0000000-\nE000007C\nStimulus port \nregisters 0-31\nWrite the 32-bits data on the selected Stimulus Port (32 \navailable) to be traced out.\n\n\n<>\n\nDebug support (DBG)\nRM0090\n1704/1757\nRM0090 Rev 21\nExample of configuration\nTo output a simple value to the TPIU:\n•\nConfigure the TPIU and assign TRACE I/Os by configuring the DBGMCU_CR (refer to \nSection 38.17.2 and Section 38.16.3)\n•\nWrite 0xC5ACCE55 to the ITM Lock Access register to unlock the write access to the \nITM registers\n•\nWrite 0x00010005 to the ITM Trace Control register to enable the ITM with Sync \nenabled and an ATB ID different from 0x00\n•\nWrite 0x1 to the ITM Trace Enable register to enable the Stimulus Port 0\n•\nWrite 0x1 to the ITM Trace Privilege register to unmask stimulus ports 7:0\n•\nWrite the value to output in the Stimulus Port register 0: this can be done by software \n(using a printf function)\n38.15 \nETM (Embedded Trace Macrocell™)\n38.15.1 \nETM general description\nThe ETM enables the reconstruction of program execution. Data are traced using the Data \nWatchpoint and Trace (DWT) component or the Instruction Trace Macrocell (ITM) whereas \ninstructions are traced using the Embedded Trace Macrocell (ETM).\nThe ETM transmits information as packets and is triggered by embedded resources. These \nresources must be programmed independently and the trigger source is selected using the \nTrigger Event register (0xE0041008). An event could be a simple event (address match \nfrom an address comparator) or a logic equation between 2 events. The trigger source is \none of the fourth comparators of the DWT module, The following events can be monitored:\n•\nClock cycle matching\n•\nData address matching\nFor more informations on the trigger resources refer to Section 38.13.\nThe packets transmitted by the ETM are output to the TPIU (Trace Port Interface Unit). The \nformatter of the TPIU adds some extra packets (refer to Section 38.17) and then outputs the \ncomplete packet sequence to the debugger host.\n38.15.2 \nETM signal protocol and packet types\nThis part is described in the chapter 7 ETMv3 Signal Protocol of the Arm® IHI 0014N \ndocument.\n\n\n<>\n\nRM0090 Rev 21\n1705/1757\nRM0090\nDebug support (DBG)\n1716\n38.15.3 \nMain ETM registers\nFor more information on registers refer to the chapter 3 of the Arm® IHI 0014N specification.\n \n38.15.4 \nETM configuration example\nTo output a simple value to the TPIU:\n•\nConfigure the TPIU and enable the I/IO_TRACEN to assign TRACE I/Os in the \nSTM32F4xx debug configuration register.\n•\nWrite 0xC5AC CE55 to the ETM Lock Access register to unlock the write access to the \nITM registers\n•\nWrite 0x0000 1D1E to the ETM control register (configure the trace)\n•\nWrite 0x0000 406F to the ETM Trigger Event register (define the trigger event)\n•\nWrite 0x0000 006F to the ETM Trace Enable Event register (define an event to \nstart/stop)\n•\nWrite 0x0200 00000x0000 0001 to the ETM Trace Start/stop register (enable the trace)\n•\nWrite 0x0000191E to the ETM Control register (end of configuration)\n38.16 \nMCU debug component (DBGMCU)\nThe MCU debug component helps the debugger provide support for: \n•\nLow-power modes\n•\nClock control for timers, watchdog, I2C and bxCAN during a breakpoint\n•\nControl of the trace pins assignment\n38.16.1 \nDebug support for low-power modes\nTo enter low-power mode, the instruction WFI or WFE must be executed.\nThe MCU implements several low-power modes which can either deactivate the CPU clock \nor reduce the power of the CPU.\nTable 310. Main ETM registers\nAddress\nRegister\nDetails\n0xE0041FB0 ETM Lock Access\nWrite 0xC5ACCE55 to unlock the write access to the \nother ETM registers.\n0xE0041000 ETM Control\nThis register controls the general operation of the ETM, \nfor instance how tracing is enabled.\n0xE0041010 ETM Status\nThis register provides information about the current status \nof the trace and trigger logic.\n0xE0041008 ETM Trigger Event\nThis register defines the event that controls trigger.\n0xE004101C ETM Trace Enable \nControl\nThis register defines which comparator is selected.\n0xE0041020 ETM Trace Enable Event\nThis register defines the trace enabling event.\n0xE0041024 ETM Trace Start/Stop\nThis register defines the traces used by the trigger source \nto start and stop the trace, respectively.\n\n\n<>\n\nDebug support (DBG)\nRM0090\n1706/1757\nRM0090 Rev 21\nThe core does not allow FCLK or HCLK to be turned off during a debug session. As these \nare required for the debugger connection, during a debug, they must remain active. The \nMCU integrates special means to allow the user to debug software in low-power modes.\nFor this, the debugger host must first set some debug configuration registers to change the \nlow-power mode behavior:\n•\nIn Sleep mode, DBG_SLEEP bit of DBGMCU_CR register must be previously set by \nthe debugger. This feeds HCLK with the same clock that is provided to FCLK (system \nclock previously configured by the software).\n•\nIn Stop mode, the bit DBG_STOP must be previously set by the debugger. This \nenables the internal RC oscillator clock to feed FCLK and HCLK in STOP mode.\n38.16.2 \nDebug support for timers, watchdog, bxCAN and I2C\nDuring a breakpoint, it is necessary to choose how the counter of timers and watchdog must \nbehave:\n•\nThey can continue to count inside a breakpoint. This is usually required when a PWM is \ncontrolling a motor, for example.\n•\nThey can stop to count inside a breakpoint. This is required for watchdog purposes.\nFor the bxCAN, the user can choose to block the update of the receive register during a \nbreakpoint.\nFor the I2C, the user can choose to block the SMBUS timeout during a breakpoint.\nFor timers having complementary outputs, when the counter is stopped \n(DBG_TIMx_STOP = 1), the outputs are disabled (as if the MOE bit was reset) for safety \npurposes.\n38.16.3 \nDebug MCU configuration register\nThis register allows the configuration of the MCU under DEBUG. This concerns:\n•\nLow-power mode support\n•\nTimer and watchdog counter support\n•\nbxCAN communication support\n•\nTrace pin assignment\nThis DBGMCU_CR is mapped on the External PPB bus at address 0xE0042004\nIt is asynchronously reset by the PORESET (and not the system reset). It can be written by \nthe debugger under system reset.\nIf the debugger host does not support these features, it is still possible for the user software \nto write to these registers.\nDBGMCU_CR register\nAddress: 0xE004 2004\nOnly 32-bit access supported\nPOR Reset: 0x0000 0000 (not reset by system reset)\n\n\n<>\n\nRM0090 Rev 21\n1707/1757\nRM0090\nDebug support (DBG)\n1716\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTRACE_\nMODE\n[1:0]\nTRACE\n_IOEN\nReserved\nDBG_\nSTAND\nBY\nDBG_\nSTOP\nDBG_\nSLEEP\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBits 7:5 TRACE_MODE[1:0] and TRACE_IOEN: Trace pin assignment control\n– With TRACE_IOEN=0:\nTRACE_MODE=xx: TRACE pins not assigned (default state)\n– With TRACE_IOEN=1:\n–\nTRACE_MODE=00: TRACE pin assignment for Asynchronous mode\n–\nTRACE_MODE=01: TRACE pin assignment for Synchronous mode with a \nTRACEDATA size of 1\n–\nTRACE_MODE=10: TRACE pin assignment for Synchronous mode with a \nTRACEDATA size of 2\n–\nTRACE_MODE=11: TRACE pin assignment for Synchronous mode with a \nTRACEDATA size of 4\nBits 4:3 Reserved, must be kept at reset value.\nBit 2 DBG_STANDBY: Debug Standby mode\n0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.\nFrom software point of view, exiting from Standby is identical than fetching reset vector \n(except a few status bit indicated that the MCU is resuming from Standby)\n1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and FCLK and \nHCLK are provided by the internal RC oscillator which remains active. In addition, the MCU \ngenerate a system reset during Standby mode so that exiting from Standby is identical than \nfetching from reset\nBit 1 DBG_STOP: Debug Stop mode\n0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all clocks (including \nHCLK and FCLK). When exiting from STOP mode, the clock configuration is identical to the \none after RESET (CPU clocked by the 8 MHz internal RC oscillator (HSI)). Consequently, \nthe software must reprogram the clock controller to enable the PLL, the Xtal, etc.\n1: (FCLK=On, HCLK=On) In this case, when entering STOP mode, FCLK and HCLK are \nprovided by the internal RC oscillator which remains active in STOP mode. When exiting \nSTOP mode, the software must reprogram the clock controller to enable the PLL, the Xtal, \netc. (in the same way it would do in case of DBG_STOP=0)\nBit 0 DBG_SLEEP: Debug Sleep mode\n0: (FCLK=On, HCLK=Off) In Sleep mode, FCLK is clocked by the system clock as \npreviously configured by the software while HCLK is disabled.\nIn Sleep mode, the clock controller configuration is not reset and remains in the previously \nprogrammed state. Consequently, when exiting from Sleep mode, the software does not \nneed to reconfigure the clock controller.\n1: (FCLK=On, HCLK=On) In this case, when entering Sleep mode, HCLK is fed by the same \nclock that is provided to FCLK (system clock as previously configured by the software). \n\n\n<>\n\nDebug support (DBG)\nRM0090\n1708/1757\nRM0090 Rev 21\n38.16.4 \nDebug MCU APB1 freeze register (DBGMCU_APB1_FZ)\nThe DBGMCU_APB1_FZ register is used to configure the MCU under Debug. It concerns \nAPB1 peripherals. It is mapped on the external PPB bus at address 0xE004 2008.\nThe register is asynchronously reset by the POR (and not the system reset). It can be \nwritten by the debugger under system reset.\nAddress : 0xE004 2008\nOnly 32-bits access are supported.\nPower-on reset (POR): 0x0000 0000 (not reset by system reset)\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nDBG_CAN2_STOP\nDBG_CAN1_STOP\nReserved\nDBG_I2C3_SMBUS_TIMEOUT\nDBG_I2C2_SMBUS_TIMEOUT\nDBG_I2C1_SMBUS_TIMEOUT\nReserved\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDBG_IWDG_STOP\nDBG_WWDG_STOP\nDBG_RTC_STOP\nReserved\nDBG_TIM14_STOP\nDBG_TIM13_STOP\nDBG_TIM12_STOP\nDBG_TIM7_STOP\nDBG_TIM6_STOP\nDBG_TIM5_STOP\nDBG_TIM4_STOP\nDBG_TIM3_STOP\nDBG_TIM2_STOP\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:27\nReserved, must be kept at reset value.\nBit 26 DBG_CAN2_STOP: Debug CAN2 stopped when Core is halted\n0: Same behavior as in normal mode\n1: The CAN2 receive registers are frozen\nBit 25 DBG_CAN1_STOP: Debug CAN2 stopped when Core is halted\n0: Same behavior as in normal mode\n1: The CAN2 receive registers are frozen\nBit 24\nReserved, must be kept at reset value.\nBit 23 DBG_I2C3_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted\n0: Same behavior as in normal mode\n1: The SMBUS timeout is frozen\nBit 22 DBG_I2C2_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted\n0: Same behavior as in normal mode\n1: The SMBUS timeout is frozen\nBit 21 DBG_I2C1_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted\n0: Same behavior as in normal mode\n1: The SMBUS timeout is frozen\n\n\n<>\n\nRM0090 Rev 21\n1709/1757\nRM0090\nDebug support (DBG)\n1716\n38.16.5 \nDebug MCU APB2 Freeze register (DBGMCU_APB2_FZ)\nThe DBGMCU_APB2_FZ register is used to configure the MCU under Debug. It concerns \nAPB2 peripherals.\nThis register is mapped on the external PPB bus at address 0xE004 200C\nIt is asynchronously reset by the POR (and not the system reset). It can be written by the \ndebugger under system reset.\nAddress: 0xE004 200C\nOnly 32-bit access is supported.\nPOR: 0x0000 0000 (not reset by system reset)\n \n \nBit 20:13\nReserved, must be kept at reset value.\nBit 12 DBG_IWDG_STOP: Debug independent watchdog stopped when core is halted\n0: The independent watchdog counter clock continues even if the core is halted\n1: The independent watchdog counter clock is stopped when the core is halted\nBit 11 DBG_WWDG_STOP: Debug Window Watchdog stopped when Core is halted\n0: The window watchdog counter clock continues even if the core is halted\n1: The window watchdog counter clock is stopped when the core is halted\nBit 10 DBG_RTC_STOP: RTC stopped when Core is halted\n0: The RTC counter clock continues even if the core is halted\n1: The RTC counter clock is stopped when the core is halted\nBit 9\nReserved, must be kept at reset value.\nBits 8:0 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=2..7, 12..14)\n0: The clock of the involved timer counter is fed even if the core is halted \n1: The clock of the involved timer counter is stopped and the outputs are disabled when the \ncore is halted\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nDBG_TIM11\n_STOP\nDBG_TIM10\n_STOP\nDBG_TIM9_\nSTOP\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDBG_TIM8_\nSTOP\nDBG_TIM1_\nSTOP\nrw\nrw\nBits 31:19\nReserved, must be kept at reset value.\nBits 18:16 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=9..11)\n0: The clock of the involved timer counter is fed even if the core is halted \n1: The clock of the involved timer counter is stopped and the outputs are disabled when the \ncore is halted\n\n\n<>\n\nDebug support (DBG)\nRM0090\n1710/1757\nRM0090 Rev 21\n38.17 \nTPIU (trace port interface unit)\n38.17.1 \nIntroduction\nThe TPIU acts as a bridge between the on-chip trace data from the ITM and the ETM.\nThe output data stream encapsulates the trace source ID, that is then captured by a trace \nport analyzer (TPA).\nThe core embeds a simple TPIU, especially designed for low-cost debug (consisting of a \nspecial version of the CoreSight TPIU).\nFigure 488. TPIU block diagram\nBits 15:\nReserved, must be kept at reset value.\nBit 1 DBG_TIM8_STOP: TIM8 counter stopped when core is halted\n0: The clock of the involved timer counter is fed even if the core is halted \n1: The clock of the involved timer counter is stopped and the outputs are disabled when the \ncore is halted\nBit 0 DBG_TIM1_STOP: TIM1 counter stopped when core is halted\n0: The clock of the involved timer counter is fed even if the core is halted \n1: The clock of the involved timer counter is stopped and the outputs are disabled when the \ncore is halted\n\n\n<>\n\nRM0090 Rev 21\n1711/1757\nRM0090\nDebug support (DBG)\n1716\n38.17.2 \nTRACE pin assignment\n•\nAsynchronous mode\nThe asynchronous mode requires 1 extra pin and is available on all packages. It is only \navailable if using Serial Wire mode (not in JTAG mode).\n \n•\nSynchronous mode\nThe synchronous mode requires from 2 to 6 extra pins depending on the data trace \nsize and is only available in the larger packages. In addition it is available in JTAG \nmode and in Serial Wire mode and provides better bandwidth output capabilities than \nasynchronous trace.\n \nTPUI TRACE pin assignment\nBy default, these pins are NOT assigned. They can be assigned by setting the \nTRACE_IOEN and TRACE_MODE bits in the MCU Debug component configuration \nregister. This configuration has to be done by the debugger host.\nIn addition, the number of pins to assign depends on the trace configuration (asynchronous \nor synchronous). \n•\nAsynchronous mode: 1 extra pin is needed\n•\nSynchronous mode: from 2 to 5 extra pins are needed depending on the size of the \ndata trace port register (1, 2 or 4):\n–\nTRACECK\n–\nTRACED(0) if port size is configured to 1, 2 or 4\n–\nTRACED(1) if port size is configured to 2 or 4\n–\nTRACED(2) if port size is configured to 4\n–\nTRACED(3) if port size is configured to 4\nTo assign the TRACE pin, the debugger host must program the bits TRACE_IOEN and \nTRACE_MODE[1:0] of the Debug MCU configuration register (DBGMCU_CR). By default \nthe TRACE pins are not assigned.\nThis register is mapped on the external PPB and is reset by the PORESET (and not by the \nSYSTEM reset). It can be written by the debugger under SYSTEM reset.\nTable 311. Asynchronous TRACE pin assignment\nTPUI pin name\nTrace synchronous mode\nSTM32F4xx pin \nassignment\nType\nDescription\nTRACESWO\nO\nTRACE Async Data Output\nPB3\nTable 312. Synchronous TRACE pin assignment\nTPUI pin name\nTrace synchronous mode\nSTM32F4xxpin \nassignment\nType\nDescription\nTRACECK\nO\nTRACE Clock\nPE2\nTRACED[3:0]\nO\nTRACE Sync Data Outputs\nCan be 1, 2 or 4.\nPE[6:3]\n\n\n<>\n\nDebug support (DBG)\nRM0090\n1712/1757\nRM0090 Rev 21\n \nNote:\nBy default, the TRACECLKIN input clock of the TPIU is tied to GND. It is assigned to HCLK \ntwo clock cycles after the bit TRACE_IOEN has been set.\nThe debugger must then program the Trace Mode by writing the PROTOCOL[1:0] bits in the \nSPP_R (Selected Pin Protocol) register of the TPIU.\n•\nPROTOCOL=00: Trace Port Mode (synchronous)\n•\nPROTOCOL=01 or 10: Serial Wire (Manchester or NRZ) Mode (asynchronous mode).\nDefault state is 01\nIt then also configures the TRACE port size by writing the bits [3:0] in the CPSPS_R \n(Current Sync Port Size register) of the TPIU:\n•\n0x1 for 1 pin (default state)\n•\n0x2 for 2 pins\n•\n0x8 for 4 pins\n38.17.3 \nTPUI formatter\nThe formatter protocol outputs data in 16-byte frames:\n•\nseven bytes of data\n•\neight bytes of mixed-use bytes consisting of:\n–\n1 bit (LSB) to indicate it is a DATA byte (‘0) or an ID byte (‘1).\n–\n7 bits (MSB) which can be data or change of source ID trace.\n•\none byte of auxiliary bits where each bit corresponds to one of the eight mixed-use \nbytes:\n–\nif the corresponding byte was a data, this bit gives bit0 of the data.\n–\nif the corresponding byte was an ID change, this bit indicates when that ID change \ntakes effect.\nTable 313. Flexible TRACE pin assignment\nDBGMCU_CR\nregister\nPins \nassigned\nfor:\nTRACE IO pin assigned\nTRACE\n_IOEN\nTRACE\n_MODE\n[1:0]\nPB3 /JTDO/ \nTRACESWO\nPE2/\nTRACECK\nPE3 /\nTRACED[0]\nPE4 /\nTRACED[1]\nPE5 /\nTRACED[2]\nPE6 /\nTRACED[3]\n0\nXX\nNo Trace \n(default state)\nReleased (1)\n-\n1\n00\nAsynchronous \nTrace\nTRACESWO\n-\n-\nReleased\n(usable as GPIO)\n1\n01\nSynchronous \nTrace 1 bit\nReleased (1)\nTRACECK\nTRACED[0]\n-\n-\n-\n1\n10\nSynchronous \nTrace 2 bit\nTRACECK\nTRACED[0]\nTRACED[1]\n-\n-\n1\n11\nSynchronous \nTrace 4 bit\nTRACECK\nTRACED[0]\nTRACED[1]\nTRACED[2]\nTRACED[3]\n1.\nWhen Serial Wire mode is used, it is released. But when JTAG is used, it is assigned to JTDO.\n\n\n<>\n\nRM0090 Rev 21\n1713/1757\nRM0090\nDebug support (DBG)\n1716\nNote:\nRefer to the Arm® CoreSight Architecture Specification v1.0 (Arm® IHI 0029B) for further \ninformation\n38.17.4 \nTPUI frame synchronization packets\nThe TPUI can generate two types of synchronization packets:\n•\nThe Frame Synchronization packet (or Full Word Synchronization packet) \nIt consists of the word: 0x7F_FF_FF_FF (LSB emitted first). This sequence can not \noccur at any other time provided that the ID source code 0x7F has not been used.\nIt is output periodically between frames. \nIn continuous mode, the TPA must discard all these frames once a synchronization \nframe has been found.\n•\nThe Half-Word Synchronization packet \nIt consists of the half word: 0x7F_FF (LSB emitted first).\nIt is output periodically between or within frames. \nThese packets are only generated in continuous mode and enable the TPA to detect \nthat the TRACE port is in IDLE mode (no TRACE to be captured). When detected by \nthe TPA, it must be discarded.\n38.17.5 \nTransmission of the synchronization frame packet\nThere is no Synchronization Counter register implemented in the TPIU of the core. \nConsequently, the synchronization trigger can only be generated by the DWT. Refer to the \nregisters DWT Control register (bits SYNCTAP[11:10]) and the DWT Current PC Sampler \nCycle Count register.\nThe TPUI Frame synchronization packet (0x7F_FF_FF_FF) is emitted:\n•\nafter each TPIU reset release. This reset is synchronously released with the rising \nedge of the TRACECLKIN clock. This means that this packet is transmitted when the \nTRACE_IOEN bit in the DBGMCU_CFG register is set. In this case, the word \n0x7F_FF_FF_FF is not followed by any formatted packet.\n•\nat each DWT trigger (assuming DWT has been previously configured). Two cases \noccur:\n–\nIf the bit SYNENA of the ITM is reset, only the word 0x7F_FF_FF_FF is emitted \nwithout any formatted stream which follows.\n–\nIf the bit SYNENA of the ITM is set, then the ITM synchronization packets follow \n(0x80_00_00_00_00_00), formatted by the TPUI (trace source ID added). \n38.17.6 \nSynchronous mode\nThe trace data output size can be configured to 4, 2 or 1 pin: TRACED(3:0)\nThe output clock is output to the debugger (TRACECK)\nHere, TRACECLKIN is driven internally and is connected to HCLK only when TRACE is \nused.\nNote:\nIn this synchronous mode, it is not required to provide a stable clock frequency.\nThe TRACE I/Os (including TRACECK) are driven by the rising edge of TRACLKIN (equal \nto HCLK). Consequently, the output frequency of TRACECK is equal to HCLK/2.\n\n\n<>\n\nDebug support (DBG)\nRM0090\n1714/1757\nRM0090 Rev 21\n38.17.7 \nAsynchronous mode\nThis is a low cost alternative to output the trace using only 1 pin: this is the asynchronous \noutput pin TRACESWO. Obviously there is a limited bandwidth. \nTRACESWO is multiplexed with JTDO when using the SW-DP pin. This way, this \nfunctionality is available in all STM32F4xx packages.\nThis asynchronous mode requires a constant frequency for TRACECLKIN. For the standard \nUART (NRZ) capture mechanism, 5% accuracy is needed. The Manchester encoded \nversion is tolerant up to 10%.\n38.17.8 \nTRACECLKIN connection inside the STM32F4xx\nIn the STM32F4xx, this TRACECLKIN input is internally connected to HCLK. This means \nthat when in asynchronous trace mode, the application is restricted to use to time frames \nwhere the CPU frequency is stable.\nNote:\nImportant: when using asynchronous trace: it is important to be aware that:\nThe default clock of the STM32F4xx MCUs is the internal RC oscillator. Its frequency under \nreset is different from the one after reset release. This is because the RC calibration is the \ndefault one under system reset and is updated at each system reset release.\nConsequently, the trace port analyzer (TPA) must not enable the trace (with the \nTRACE_IOEN bit) under system reset, because a Synchronization Frame Packet is issued \nwith a different bit time than trace packets which are transmitted after reset release.\n38.17.9 \nTPIU registers\nThe TPIU APB registers can be read and written only if the bit TRCENA of the Debug \nException and Monitor Control register (DEMCR) is set. Otherwise, the registers are read as \nzero (the output of this bit enables the PCLK of the TPIU).\n \nTable 314. Important TPIU registers\nAddress\nRegister\nDescription\n0xE0040004\nCurrent port size\nAllows the trace port size to be selected:\nBit 0: Port size = 1\nBit 1: Port size = 2\nBit 2: Port size = 3, not supported\nBit 3: Port Size = 4\nOnly 1 bit must be set. By default, the port size is one bit. (0x00000001)\n0xE00400F0\nSelected pin protocol\nAllows the Trace Port Protocol to be selected:\nBit1:0= \n00: Sync Trace Port Mode\n01: Serial Wire Output - manchester (default value)\n10: Serial Wire Output - NRZ\n11: reserved\n\n\n<>\n\nRM0090 Rev 21\n1715/1757\nRM0090\nDebug support (DBG)\n1716\n38.17.10 Example of configuration\n•\nSet the bit TRCENA in the Debug Exception and Monitor Control register (DEMCR)\n•\nWrite the TPIU Current Port Size register to the desired value (default is 0x1 for a 1-bit \nport size)\n•\nWrite TPIU Formatter and Flush Control register to 0x102 (default value)\n•\nWrite the TPIU Select Pin Protocol to select the sync or async mode. Example: 0x2 for \nasync NRZ mode (UART like)\n•\nWrite the DBGMCU control register to 0x20 (bit IO_TRACEN) to assign TRACE I/Os \nfor async mode. A TPIU Sync packet is emitted at this time (FF_FF_FF_7F)\n•\nConfigure the ITM and write the ITM Stimulus register to output a value\n0xE0040304\nFormatter and flush \ncontrol\nBits 31-9 = always ‘0\nBit 8 = TrigIn = always ‘1 to indicate that triggers are indicated\nBits 7-4 = always 0\nBits 3-2 = always 0\nBit 1 = EnFCont. In Sync Trace mode (Select_Pin_Protocol register \nbit1:0=00), this bit is forced to ‘1: the formatter is automatically enabled in \ncontinuous mode. In asynchronous mode (Select_Pin_Protocol register \nbit1:0 <> 00), this bit can be written to activate or not the formatter.\nBit 0 = always 0\nThe resulting default value is 0x102\nNote: In synchronous mode, because the TRACECTL pin is not mapped \noutside the chip, the formatter is always enabled in continuous mode -this \nway the formatter inserts some control packets to identify the source of the \ntrace packets).\n0xE0040300\nFormatter and flush \nstatus\nNot used in Cortex®-M4 with FPU, always read as 0x00000008\nTable 314. Important TPIU registers (continued)\nAddress\nRegister\nDescription\n\n\n<>\n\nDebug support (DBG)\nRM0090\n1716/1757\nRM0090 Rev 21\n38.18 \nDBG register map\nThe following table summarizes the Debug registers. \n \n \nTable 315. DBG register map and reset values\nAddr.\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0xE004 \n2000\nDBGMCU\n_IDCODE\nREV_ID\nReserved\nDEV_ID\nReset value(1)\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\n0xE004 \n2004\nDBGMCU_CR\nReserved\nDBG_TIM7_STOP\nDBG_TIM6_STOP\nDBG_TIM5_STOP\nDBG_TIM8_STOP\nDBG_I2C2_SMBUS_TIMEOUT\nReserved\nTRACE_MODE[1:0]\nTRACE_IOEN\nReserved\nDBG_STANDBY\nDBG_STOP\nDBG_SLEEP\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xE004 \n2008\nDBGMCU_\nAPB1_FZ\nReserved\nDBG_CAN2_STOP\nDBG_CAN1_STOP\nReserved\nDBG_I2C3_SMBUS_TIMEOUT\nDBG_I2C2_SMBUS_TIMEOUT\nDBG_I2C1_SMBUS_TIMEOUT\nReserved\nDBG_IWDG_STOP\nDBG_WWDG_STOP\nReserved\nDBG_RTC_STOP\nDBG_TIM14_STOP\nDBG_TIM13_STOP\nDBG_TIM12_STOP\nDBG_TIM7_STOP\nDBG_TIM6_STOP\nDBG_TIM5_STOP\nDBG_TIM4_STOP\nDBG_TIM3_STOP\nDBG_TIM2_STOP\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xE004 \n200C\nDBGMCU_\nAPB2_FZ\nReserved\nDBG_TIM11_STOP\nDBG_TIM10_STOP\nDBG_TIM9_STOP\nReserved\nDBG_TIM8_STOP\nDBG_TIM1_STOP\nReset value\n0\n0\n0\n0\n0\n1.\nThe reset value is product dependent. For more information, refer to Section 38.6.1: MCU device ID code.\n\n\n<>\n\nRM0090 Rev 21\n1717/1757\nRM0090\nDevice electronic signature\n1718\n39 \nDevice electronic signature\nThe electronic signature is stored in the Flash memory area. It can be read using the \nJTAG/SWD or the CPU. It contains factory-programmed identification data that allow the \nuser firmware or other external devices to automatically match its interface to the \ncharacteristics of the STM32F4xx microcontrollers.\n39.1 \nUnique device ID register (96 bits)\nThe unique device identifier is ideally suited:\n•\nfor use as serial numbers (for example USB string serial numbers or other end \napplications)\n•\nfor use as security keys in order to increase the security of code in Flash memory while \nusing and combining this unique ID with software cryptographic primitives and \nprotocols before programming the internal Flash memory\n•\nto activate secure boot processes, etc.\nThe 96-bit unique device identifier provides a reference number which is unique for any \ndevice and in any context. These bits can never be altered by the user.\nThe 96-bit unique device identifier can also be read in single bytes/half-words/words in \ndifferent ways and then be concatenated using a custom algorithm.\nBase address: 0x1FFF 7A10\nAddress offset: 0x00\nRead only = 0xXXXX XXXX where X is factory-programmed\n \n \nAddress offset: 0x04\nRead only = 0xXXXX XXXX where X is factory-programmed\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nUID(31:0)\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 UID(31:0): X and Y coordinates on the wafer\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nUID(63:48)\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nUID(47:32)\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n\n\n<>\n\nDevice electronic signature\nRM0090\n1718/1757\nRM0090 Rev 21\n \nAddress offset: 0x08\nRead only = 0xXXXX XXXX where X is factory-programmed\n \n \n39.2 \nFlash size\nBase address: 0x1FFF 7A22\nAddress offset: 0x00\nRead only = 0xXXXX where X is factory-programmed\n \n \nBits 31:8 UID(63:40): LOT_NUM[23:0]\nLot number (ASCII encoded).\nBits 7:0 UID(39:32): WAF_NUM[7:0]\nWafer number (ASCII encoded).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nUID(95:80)\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nUID(79:64)\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 UID(95:64): LOT_NUM[55:24]\nLot number (ASCII encoded).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nF_SIZE\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 15:0 F_ID(15:0): Flash memory size\nThis bitfield indicates the size of the device Flash memory expressed in Kbytes.\nAs an example, 0x0400 corresponds to 1024 Kbytes.\n\n\n<>\n\nRM0090 Rev 21\n1719/1757\nRM0090\nImportant security notice\n1719\n40 \nImportant security notice\nThe STMicroelectronics group of companies (ST) places a high value on product security, \nwhich is why the ST product(s) identified in this documentation may be certified by various \nsecurity certification bodies and/or may implement our own security measures as set forth \nherein. However, no level of security certification and/or built-in security measures can \nguarantee that ST products are resistant to all forms of attacks. As such, it is the \nresponsibility of each of ST's customers to determine if the level of security provided in an \nST product meets the customer needs both in relation to the ST product alone, as well as \nwhen combined with other components and/or software for the customer end product or \napplication. In particular, take note that:\n•\nST products may have been certified by one or more security certification bodies, such \nas Platform Security Architecture (www.psacertified.org) and/or Security Evaluation \nstandard for IoT Platforms (www.trustcb.com). For details concerning whether the ST \nproduct(s) referenced herein have received security certification along with the level \nand current status of such certification, either visit the relevant certification standards \nwebsite or go to the relevant product page on www.st.com for the most up to date \ninformation. As the status and/or level of security certification for an ST product can \nchange from time to time, customers should re-check security certification status/level \nas needed. If an ST product is not shown to be certified under a particular security \nstandard, customers should not assume it is certified. \n•\nCertification bodies have the right to evaluate, grant and revoke security certification in \nrelation to ST products. These certification bodies are therefore independently \nresponsible for granting or revoking security certification for an ST product, and ST \ndoes not take any responsibility for mistakes, evaluations, assessments, testing, or \nother activity carried out by the certification body with respect to any ST product. \n•\nIndustry-based cryptographic algorithms (such as AES, DES, or MD5) and other open \nstandard technologies which may be used in conjunction with an ST product are based \non standards which were not developed by ST. ST does not take responsibility for any \nflaws in such cryptographic algorithms or open technologies or for any methods which \nhave been or may be developed to bypass, decrypt or crack such algorithms or \ntechnologies. \n•\nWhile robust security testing may be done, no level of certification can absolutely \nguarantee protections against all attacks, including, for example, against advanced \nattacks which have not been tested for, against new or unidentified forms of attack, or \nagainst any form of attack when using an ST product outside of its specification or \nintended use, or in conjunction with other components or software which are used by \ncustomer to create their end product or application. ST is not responsible for resistance \nagainst such attacks. As such, regardless of the incorporated security features and/or \nany information or support that may be provided by ST, each customer is solely \nresponsible for determining if the level of attacks tested for meets their needs, both in \nrelation to the ST product alone and when incorporated into a customer end product or \napplication. \n•\nAll security features of ST products (inclusive of any hardware, software, \ndocumentation, and the like), including but not limited to any enhanced security \nfeatures added by ST, are provided on an \"AS IS\" BASIS. AS SUCH, TO THE EXTENT \nPERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS \nOR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF \nMERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the \napplicable written and signed contract terms specifically provide otherwise.\n\n\n<>\n\nRevision history\nRM0090\n1720/1757\nRM0090 Rev 21\n41 \nRevision history\n \nTable 316. Document revision history\nDate\nVersion\nChanges\n15-Sep-2011\n1\nInitial release.\n19-Oct-2012\n2\nUpdated reference documents and added Table 1: Applicable products on cover \npage.\nMEMORY:\nUpdated Section 2: Memory and bus architecture.\nPWR:\nUpdated VDDA and VREF+ decoupling capacitor in Figure 7: Power supply \noverview.\nVOSRDY bit changed to read-only in Section 5.4.3: PWR power control/status \nregister (PWR_CSR).\nRemoved VDDA in Section 5.2.3: Programmable voltage detector (PVD) and \nremove VDDA in PVDO bit description (Section 5.4.3: PWR power control/status \nregister (PWR_CSR)).\nRCC:\nUpdated Figure 20: Simplified diagram of the reset circuit and minimum reset pulse \nduration guaranteed by pulse generator restricted to internal reset sources.\nGPIOs:\nUpdated Section 8.3.1: General-purpose I/O (GPIO).\nDMA:\nUpdated direct mode description in Section 10.2: DMA main features.\nUpdated direct mode description in Section : Memory-to-peripheral mode, and \nSection 10.3.12: FIFO/: Direct mode.\nUpdated register access in Section 10.5: DMA registers.\nModified Stream2 /Channel 2 in Table 42: DMA1 request mapping.\nAdded note related to EN bit in Section 10.5.5: DMA stream x configuration register \n(DMA_SxCR) (x = 0..7). Updated definition of NDT[15:0] bits in Section 10.5.6: \nDMA stream x number of data register (DMA_SxNDTR) (x = 0..7).\nInterrupts:\nUpdated number of maskable interrupts to 82 in Section 12.1.1: NVIC featuress.\nUpdated Section 12.2: External interrupt/event controller (EXTI).\n\n\n<>\n\nRM0090 Rev 21\n1721/1757\nRM0090\nRevision history\n1751\n19-Oct-2012\n2 \n(continued)\nADC:\nChanged ADCCLK frequency to 30 MHz in Section 13.5: Channel-wise \nprogrammable sampling timee.\nAdded recovery from ADC sequence in Section 13.8.1: Using the DMA and Section \n13.8.2: Managing a sequence of conversions without using the DMA.\nUpdated AWDIE in Section 13.13.2: ADC control register 1 (ADC_CR1). Added \nread and write access in Section 13.13: ADC registers.\nAdvanced control timers (TIM1 and TIM8):\nUpdated 16-bit prescaler range in Section 17.2: TIM1 and TIM8 main features.\nUpdated OC1 block diagram in Figure 114: Output stage of capture/compare \nchannel (channel 1 to 3).\nUpdated update event generation in Upcounting mode and Downcounting mode in \nSection 17.3.2: Counter modes and Section 17.3.3: Repetition counter.\nUpdated bits that control the dead-time generation in Section 17.3.11: \nComplementary outputs and dead-time insertion.\nUpdated ways to generate a break in Section 17.3.12: Using the break function.\nChanged OCxREF to ETR in the example given in Section 17.3.13: Clearing the \nOCxREF signal on an external event and changed\nOCREF_CLR to ETRF in Figure 124: Clearing TIMx OCxREF.\nUpdated configuration for example of counter operation in encoder\ninterface mode in Section 17.3.16: Encoder interface mode.\nAdded register access in Section 17.4: TIM1 and TIM8 registers.\nChanged definition of ARR[15:0] bits in Section 17.4.12: TIM1 and TIM8 auto-\nreload register (TIMx_ARR).\nUpdated BKE definition in Section 17.4.18: TIM1 and TIM8 break and dead-time \nregister (TIMx_BDTR).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRevision history\nRM0090\n1722/1757\nRM0090 Rev 21\n19-Oct-2012\n2 \n(continued)\nGeneral purpose timers (TIM2 to TIM5):\nRemoved all references to “repetition counter”.\nAdded Figure 134: General-purpose timer block diagram.\nUpdated 16-bit prescaler range in Section 18.2: TIM2 to TIM5 main features.\nExternal clock mode 2 ETR restricted to TIM2 to TIM4 in\nSection 18.3.3: Clock selection and Section 18.3.6: PWM input mode.\nUpdated Section 18.3.9: PWM mode and Section 18.3.11: Clearing the OCxREF \nsignal on an external event.\nUpdated Figure 174: Master/Slave timer example to change ITR1 to\nITR0.\nUpdated read and write access to registers in Section 18.4: TIM2 to TIM5 \nregisterss.\nRestored bits 15 to 8 of TIMx_SMCR as well as Table 98: TIMx internal trigger \nconnection in Section 14.4.3.\nRemoved note 1 related to OC1M bits in Section 18.4.13: TIMx capture/compare \nregister 1 (TIMx_CCR1).\nUpdated TIMx_CCER bit description for TIM2 to TIM5 in\nSection 18.4.9: TIMx capture/compare enable register (TIMx_CCER).\nGeneral purpose timers (TIM9 to TIM14):\nUpdated 16-bit prescaler range in Section 19.2.1: TIM9/TIM12 main features and \nSection 19.2.2: TIM10/TIM11 and TIM13/TIM14 main features.\nUpdated Figure 181: General-purpose timer block diagram (TIM10/11/13/14)) to \nremove TRGO trigger controller output.\nAdded register access in Section 19.4: TIM9 and TIM12 registers\nand Section 19.5: TIM10/11/13/14 registers.\nBasic timers (TIM6 and TIM7):\nRemoved all references to “repetition counter”.\nUpdated 16-bit prescaler range in Section 20.2: TIM6 and TIM7 main features.\nHASH:\nUpdated Section 25.3.1: Duration of the processing.\nRNG:\nUpdated Section 24.1: RNG introduction.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRM0090 Rev 21\n1723/1757\nRM0090\nRevision history\n1751\n19-Oct-2012\n2 \n(continued)\nRTC:\nUpdated Figure 237: RTC block diagram.\nAdded formula to compute fck_apre in Figure 26.3.1: Clock and prescalers.\nUpdated Section 26.3.9: RTC reference clock detection.\nUpdated Section : RTC register write protection.\nAdded RTC_SSR shadow register in Section 26.3.6: Reading the calendar.\nUpdated description of DC[4:0] bits in Section 26.6.7: RTC calibration register \n(RTC_CALIBR).\nRenamed RTC_BKxR into RTC_BKPxR in Table 121: RTC register map and reset \nvalues.\nAdded power-on reset value and changed reset value to system\nreset value in Section 26.6.11: RTC sub second register (RTC_SSR).\nUpdated definition of ALARMOUTTYPE in Section 26.6.17: RTC tamper and \nalternate function configuration register (RTC_TAFCR).\nI2C:\nModified Section 27.3.8: DMA requests.\nUpdated bit 14 description in Section 27.6.3: I2C Own address register 1 \n(I2C_OAR1)).\nUpdated definition of PE bit and note related to SWRST bit; moved\nnote related to STOP bit to the whole register in Section 27.6.1: I2C Control register \n1 (I2C_CR1).\nUSART:\nSection 30.6.6: Control register 3 (USART_CR3)): removed notes\nrelated to UART5 in DMAT and DMAR description.\nUpdated TTable 142: Error calculation for programmed baud rates at fPCLK = 42 \nMHz or fPCLK = 84 Hz, oversampling by 16 and\nTable 143: Error calculation for programmed baud rates at fPCLK = 42 MHz or \nfPCLK = 84 MHz, oversampling by 8.\nSPI/I2S:\nUpdated Section 28.1: SPI introduction.\nChanged I2S simplex communication/mode to half-duplex communication/mode. \nUpdated flags in reception/transmission modes in Section 28.2.2: I2S features. \nAdded Frame error flag in Table 128: I2S interrupt requests. \nAdded register access in Section 28.5: SPI and I2S registers.\nUpdated ERRIE definition in Section 28.5.2: SPI control register 2 (SPI_CR2).\nRenamed TIFRFE to FRE and definition updated in Section 28.5.3: SPI status \nregister (SPI_SR).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRevision history\nRM0090\n1724/1757\nRM0090 Rev 21\n19-Oct-2012\n2 \n(continued)\nSDIO:\nUpdated value and description for bits [45:40] and [7:1] in Table 176: R4 response. \nUpdated value at bits [45:40] in Table 178: R5 response.\nCAN:\nUpdated Figure 335: Dual CAN block diagram.\nModified definition of CAN2SB bits in Section : CAN filter master register \n(CAN_FMR).\nAdded register access in Section 32.9: CAN registers\nETHERNET:\nUpdated standard for precision networked clock synchronization in Section 33.1: \nEthernet introduction and Section 33.2.1: MAC core features.\nUpdated CR bit definition in Section : Ethernet MAC MII address register \n(ETH_MACMIIAR).\nReplace RTPR by PM bit in Table 192: Source address filtering.\nUSB OTG FS\nUpdated remote wake-up signaling bit and the resume\ninterrupt in Section : Suspended state.\nAdded peripheral register access in Section 34.16: OTG_FS control and status \nregisterss.\nUpdated INEPTXSA description in OTG_FS_DIEPTXFx.\nChanged PHYSEL from bit 7 to bit 6 of the OTG_FS_GUSBCFG\nregister.\nUSB OTG HS\nUpdated remote wake-up signaling bit and the resume\ninterrupt in Section : Suspended state.\nAdded peripheral register access in Section 35.12: OTG_HS control and status \nregisters.\nUpdated OTG_HS_CID reset value. \nUpdated INEPTXSA description in OTG_HS_DIEPTXFx.\nUpdated FSLSPCS for LS host mode, added PHYSEL in Section : OTG_HS host \nconfiguration register (OTG_HS_HCFG).\nRenamed PHYSEL into PHSEL and changed from bit 7 to bit 6 of\nthe OTG_HS_GUSBCFG register.\nUpdated OTG_HS_DIEPEACHMSK1 and OTG_HS_DOEPEACHMSK1 reset \nvalues.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRM0090 Rev 21\n1725/1757\nRM0090\nRevision history\n1751\n19-Oct-2012\n2 \n(continued)\nFSMC:\nUpdated step b) in Section 36.3.1: Supported memories and transactions.\nUpdated Table 196: FSMC_BTRx bit fields.\nChanged Clock divide ration min in Table 246: Programmable NAND/PC Card \naccess parameters.\nUpdated case of synchronous accesses in Section 36.5: NOR Flash/PSRAM \ncontroller.\nChanged minimum value for ADDSET to 0 in Table 203, Table 206, Table 207, \nTable 209, and Table 210.\nMove note from Figure 437: Mode1 write accesses and Figure 436: Mode1 read \naccesses. Move note from Figure 439: ModeA write accesses to Figure 438: \nModeA read accesses.\nUpdated Section : WAIT management in asynchronous accesses.\nAdded register access in Section 36.5.6: NOR/PSRAM control registers and \nSection 36.6.2: NAND Flash / PC Card supported memories and transactions.\nRemoved caution note in Section 36.6.1: External memory interface signalss.\nUpdated Table 249: 16-bit PC Card.\nUpdated step 3 in Section 36.6.4: NAND Flash operations.\nUpdated Figure 455: Access to non ‘CE don’t care’ NAND-Flash and note below in \nSection 36.6.5: NAND Flash prewait functionality. \nUpdated access to I/O Space in Section 36.6.7: PC Card/CompactFlash \noperationss. Updated Table 251: 16-bit PC-Card signals and access type. Updated \nBUSTURN bit definition in Section : SRAM/NOR-Flash chip-select timing registers \n1..4 (FSMC_BTR1..4)). Changed bits 16 to 19 to BUSTURN in Section : \nSRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4)\nDEBUG: \nUpdated Section 38.4.3: Internal pull-up and pull-down on JTAG pins.\nElectronic signature\nUpdated Section 24: Device electronic signature introduction. \nUpdated REV_ID[15:0] to add revision Z in Section 24.1: Unique device ID register \n(96 bits).\nUpdated address and example in Section 24.2: Flash size.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRevision history\nRM0090\n1726/1757\nRM0090 Rev 21\n13-Nov-2012\n3\nAdded STM32F42x and STM32F43x devices.\nRemoved reference du Flash programming manual on cover page. Added Section \n2.3.2: Flash memory overview and Section 3: Embedded Flash memory interface. \nChange RTC_50Hz into RTC_REFIN in Section 8.3.2: I/O pin multiplexer and \nmapping. Modified RTC alternate function naming in Section 8: General-purpose \nI/Os (GPIO) and Section 26: Real-time clock (RTC).\nUpdated max. input frequency in Section 26.3.1: Clock and prescalers.\nChanged bit access type from ‘rw’ to ‘w’ and bit description updated in Section \n10.5.3: DMA low interrupt flag clear register (DMA_LIFCR) and Section 10.5.4: \nDMA high interrupt flag clear register (DMA_HIFCR). \nUpdated Figure 18: Frequency measurement with TIM5 in Input capture mode.\nUpdated Section : Signals synchronization in Section 36: Flexible static memory \ncontroller (FSMC)\nSection 34: USB on-the-go full-speed (OTG_FS): updated Section Figure 389.: \nUSB host-only connection, Section : VBUS valid, and Section : Host detection of a \nperipheral connection.\nSection 35: USB on-the-go high-speed (OTG_HS): updated Section : VBUS valid, \nand Section : Detection of peripheral connection by the host.\n19-Feb-2013\n4\nUpdated Section 2: Memory and bus architecture.\nUpdated Figure 1: System architecture for STM32F405xx/07xx and \nSTM32F415xx/17xx devices, and Figure 1: System architecture for \nSTM32F405xx/07xx and STM32F415xx/17xx devices. Updated Table 4: Memory \nmapping vs. Boot mode/physical remap. Updated Figure 5: Sequential 32-bit \ninstruction execution. removed note 1 from Table 13: Maximum program/erase \nparallelism. \nPWR:\nUpdated Figure 7: Power supply overview.\nUpdated Section 5.1.3: Voltage regulator.\nAdded ADCDC1 bit in Section 5.5.1: PWR power control register (PWR_CR) for \nSTM32F42xxx and STM32F43xxx.\nSYSCFG:\nAdded ADCxDC2 bit in Section 8.2.3: SYSCFG peripheral mode configuration \nregister (SYSCFG_PMC) for STM32F42xxx and STM32F43xxx.\nADC:\nUpdated Section 13.9.3: Interleaved mode, Section 13.9.4: Alternate trigger mode, \nand Section 13.9.5: Combined regular/injected simultaneous mode to describe \ncase of interrupted conversion.\nUpdated Section : Temperature sensor, VREFINT and VBAT internal channels, \nSection 13.10: Temperature sensor, and Section 13.11: Battery charge monitoring.\nRTC:\nUpdated BKP[31:0] bit description in Section 26.6.20: RTC backup registers \n(RTC_BKPxR).\nI2C:\nUpdated Section 27.3.5: Programmable noise filter.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRM0090 Rev 21\n1727/1757\nRM0090\nRevision history\n1751\n19-Feb-2013\n4 \n(continued)\nFSMC: \nUpdated write FIFO size in Section 36.1: FSMC main features.\nUpdated Figure 434: FSMC block diagram.\nUpdated Section 36.5.4: NOR Flash/PSRAM controller asynchronous transactions.\nModified differences between Mode B and mode 1 in Section : Mode 2/B - NOR \nFlash.\nModified differences between Mode C and mode 1 in Section : Mode C - NOR \nFlash - OE toggling.\nModified differences between Mode D and mode 1 in Section : Mode D - \nasynchronous access with extended address.\nUpdated NWAIT signal in Figure 449: Asynchronous wait during a read access, \nFigure 450: Asynchronous wait during a write access, Figure 451: Wait \nconfigurations, Figure 452: Synchronous multiplexed read mode - NOR, PSRAM \n(CRAM), and Figure 453: Synchronous multiplexed write mode - PSRAM (CRAM).\nUpdated Table 195 to Table 214.\nUpdated Section : SRAM/NOR-Flash chip-select control registers 1..4 \n(FSMC_BCR1..4).\nDEBUG\nUpdated Figure 485: Block diagram of STM32 MCU and Cortex®-M4 with FPU-\nlevel debug support.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRevision history\nRM0090\n1728/1757\nRM0090 Rev 21\n15-Sep-2013\n5\nAdded STM32F429xx and STM32F439xx part numbers.\nReplaced FSMC by FMC added Chrom-ART Accelerator, LCD-TFT and SAI \ninterface.\nUpdated Figure 2: System architecture for STM32F42xxx and STM32F43xxx \ndevices.\nPWR:\nUpdated Section 5.2.2: Brownout reset (BOR).\nAdded note related to CSS enabling in Entering Stop mode sections in Section \n5.3.4: Stop mode (STM32F405xx/07xx and STM32F415xx/17xx) and Section 5.3.5: \nStop mode (STM32F42xxx and STM32F43xxx). Updated Stop mode entry in Table \n27 and Table 29.\nUpdated WUF bit defienition in PWR_CSR registers. Changed CWUF and CSBF \naccess type to ‘w’ in PWR_CR register. \nRCC: Updated LSEBYP bit definition in RCC_BDCR register.\nGPIOs:\nUpdated description of OSPEEDR bits. Removed frequency value in description of \nOSPEEDR bits.Corrected typos: \"IDRy[15:0]\" replaced with \"IDRy\" in \"GPIOx_IDR\" \nregister, \"ODRy[15:0]\" replaced with \"ODRy\" in \"GPIOx_ODR\" register and \n\"OTy[1:0]\" replaced with \"OTy\" in \"GPIOx_OTYPER\" register.\nDCMI: Updated Section 15.4: DCMI clocks.\nIWDG: Corrected Figure 213: Independent watchdog block diagram.\nRTC: \nReplaced all occurrences of “power-on reset” with “backup domain reset”. Added \ncaution note under Table 121: RTC register map and reset values. Changed SHPF \nbit type to ‘r’ in Section 26.6.4: RTC initialization and status register (RTC_ISR)..\nSPI: Updated definition of ERRIE bit in Section 28.5.2: SPI control register 2 \n(SPI_CR2).\nUART: \nUpdated Section 30.3.8: LIN (local interconnection network) mode.\nRemoved note in Section 30.3.13: Continuous communication using DMA. \nETHERNET:\nModified ETH_MACA0HR (and ETH_DMABMR reset values.\nUpdated definitions of TSTS bit in ETH_MACSR, and TSTTR in ETH_PTPTSSR.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRM0090 Rev 21\n1729/1757\nRM0090\nRevision history\n1751\n15-Sep-2013\n5 \n(continued)\nUSB OTG-FS:\nRemoved note related to VDD range limitation below Figure 387: OTG A-B device \nconnection and Figure 388: USB peripheral-only connection.\nFSMC:\nUpdated Table 229, Table 232, Table 235, Table 239.\nReplaced all occurences of DATALAT by DATLAT and SRAM/CRAM by \nSRAM/PSRAM in the whole section. \nUpdated Section 36.1: FSMC main features. Changed bits 27 to 20 of \nFSMC_BWTR1..4 to reserved.\nUpdated Section 36.6.7: PC Card/CompactFlash operations. \nUpdated WREN bit in Table 231, Table 232, Table 233, Table 236, Table 239, Table \n242, Table 245, and Table 249. \nUpdated Section 36.5.4: NOR Flash/PSRAM controller asynchronous transactions, \nSection : SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4), \nSection : SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) and \nSection : SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4).\nUpdated definition of PWID in Section : PC Card/NAND Flash control registers 2..4 \n(FSMC_PCR2..4).\nFMC: \nUpdated TRDC definition in Section : SDRAM Timing registers 1,2 \n(FMC_SDTR1,2).\nDEBUG: updated Figure 487: JTAG TAP connections.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRevision history\nRM0090\n1730/1757\nRM0090 Rev 21\n03-Feb-2014\n6\nAdded note related to over-drive mode unavailable in 1.8 to 2.1 V VDD range in \nSection 3.5.1: Relation between CPU clock frequency and Flash memory read \ntime.\nUpdated maximum CPU frequency in Section 3.5.2: Adaptive real-time memory \naccelerator (ART Accelerator™).\nPWR: \nUpdated Run mode/ over-drive mode in Section 5.1.4: Voltage regulator for \nSTM32F42xxx and STM32F43xxx.\nRCC for STM32F42/43xx: \nChanged APB1/2 and AHB maximum frequencies.xw\nGPIOs: \nUpdated Figure 27: Selecting an alternate function on STM32F42xxx and \nSTM32F43xxx.\nDMA: \nUpdated Section 10.3.7: Pointer incrementation and Section 10.3.11: Single and \nburst transfers.. \nINTERRUPTS AND EVENTS:\nUpdated Table 62: Vector table for STM32F42xxx and STM32F43xxx.\nADC: \nUpdated Section 13.3.10: Discontinuous mode/Section : Regular group.\nDCMI: \nUpdated Section 15.5.2: DCMI physical interface.\nLTDC: \nUpdated resolution in note below Figure 82: LCD-TFT Synchronous timings.\nTIM1 and 8: \nAdded note related to IC1F in Section 17.4.7: TIM1 and TIM8 capture/compare \nmode register 1 (TIMx_CCMR1).\nTIM2 to 5: \nUpdated note related to IC1F in Section 18.4.7: TIMx capture/compare mode \nregister 1 (TIMx_CCMR1).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRM0090 Rev 21\n1731/1757\nRM0090\nRevision history\n1751\n03-Feb-2014\n6 \n(continued)\nTIM9 to 14: \nUpdated note related to IC1F in Section 19.5.5: TIM10/11/13/14 capture/compare \nmode register 1 (TIMx_CCMR1).\nRTC: \nUpdated Section 26.3.11: RTC smooth digital calibration.\nChanged ALRBIE to ALRBE (bit 9) in Section 26.6.3: RTC control register \n(RTC_CR).\nI2C: \nIntroduced Sm (standard mode) and Fm (fast mode) acronyms. \nFSMC: \nUpdated BUSTURN definition in Table 245: FSMC_BTRx bit fields.\nFMC:\nAdded Mobile LPSDR SDRAM.\nUpdated Section : SDRAM initialization and Section : SDRAM controller read cycle \nand Figure 476: NAND Flash/PC Card controller waveforms for common memory \naccess. \nUpdated Section : SRAM/NOR-Flash chip-select control registers 1..4 \n(FMC_BCR1..4), Section : SRAM/NOR-Flash chip-select timing registers 1..4 \n(FMC_BTR1..4), Section : SRAM/NOR-Flash write timing registers 1..4 \n(FMC_BWTR1..4), Section : SDRAM Timing registers 1,2 (FMC_SDTR1,2) and \nSection : SDRAM Refresh Timer register (FMC_SDRTR).\nRemoved mention “default valeur after reset” in Section : Common memory space \ntiming register 2..4 (FMC_PMEM2..4), Section : Attribute memory space timing \nregisters 2..4 (FMC_PATT2..4), and Section : I/O space timing register 4 \n(FMC_PIO4).\nUpdated BUSTURN definition in Table 288: FMC_BTRx bit fields.\nUpdated REV_ID bits in Section 38.6.1: MCU device ID code.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRevision history\nRM0090\n1732/1757\nRM0090 Rev 21\n15-May-2014\n7\nEmbedded Flash memory interface:\nUpdated Section : Physical remap in STM32F42xxx and STM32F43xxx. Updated \nbank 2 selection in Section 2.4: Boot configuration. Updated notes related to MERx \nand SER bits in Section : Mass Erase. Updated Section 3.7.5: Proprietary code \nreadout protection (PCROP). Updated FLASH_OPTCR register reset value for \nSTM32F42/43xx in Section 3.9.10: Flash option control register (FLASH_OPTCR) \nfor STM32F42xxx and STM32F43xxx and Section 3.9.11: Flash option control \nregister (FLASH_OPTCR1) for STM32F42xxx and STM32F43xxx.\nRCC (STM32F42/43xx): \nUpdated PPLN caution note in Section 6.3.2: RCC PLL configuration register \n(RCC_PLLCFGR)\nSYSCFG\nUpdated MEM_MODE in Section 9.3.1: SYSCFG memory remap register \n(SYSCFG_MEMRMP)\nLTDC: \nChanged resolution do XGA (1024x768) in Section 16.2: LTDC main features, \nSection 16.4.1: LTDC Global configuration parameters, and updated Section \n16.7.3: LTDC Active Width Configuration Register (LTDC_AWCR).\nRTC\nAdded note in Section 26.3.14: Calibration clock output.\nTIMER 1/8: \nRemoved note related to IC1F bits in Section 17.4.7: TIM1 and TIM8 \ncapture/compare mode register 1 (TIMx_CCMR1), \nTIM2 to 5: \nReplaced IC2S by CC2S. \nUpdated Figure 161: Output stage of capture/compare channel (channel 1). \nRemoved note related to IC1F bits in Section 18.4.7: TIMx capture/compare mode \nregister 1 (TIMx_CCMR1).\nTIM9 to 14: \nRemoved note related to IC1F bits in Section 19.5.5: TIM10/11/13/14 \ncapture/compare mode register 1 (TIMx_CCMR1).\nUSB OTG-HS:\nUpdated DSPD definition in Section : OTG_HS device configuration register \n(OTG_HS_DCFG).\nFSMC\nUpdated DATLAT bits definition in Section : SRAM/NOR-Flash chip-select timing \nregisters 1..4 (FSMC_BTR1..4).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRM0090 Rev 21\n1733/1757\nRM0090\nRevision history\n1751\n15-May-2014\n7 \n(continued)\nFMC\nUpdated Figure 474: Synchronous multiplexed read mode waveforms - NOR, \nPSRAM (CRAM). Updated DATLAT bits definition in Section : SRAM/NOR-Flash \nchip-select timing registers 1..4 (FMC_BTR1..4). \nUpdated FMC_BWTRx register address offsets in Table 297: FMC register map.\nDEBUG\nAdded revision code ‘3’ in Section : DBGMCU_IDCODE.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRevision history\nRM0090\n1734/1757\nRM0090 Rev 21\n14-Oct-2014\n8\nMemory and bus architecture: \nUpdated Table 3: Memory mapping vs. Boot mode/physical remap in \nSTM32F405xx/07xx and STM32F415xx/17xx and Table 4: Memory mapping vs. \nBoot mode/physical remap in STM32F42xxx and STM32F43xxx.\nRCC (STM32F40/41xx) and RCC (STM32F42/43xx): \nRemoved all references to Flash programming manual. Changed \nRCC_AHB1LPENR, RCC_APB1LPENR, RCC_APB2LPENR, RCC_PLLI2SCFGR \nand RCC_APB2LPENR reset values.\nUpdated access type to “r” for bits 24 to 31 in RCC_CSR. \nGPIOs:\nUpdated Figure 27: Selecting an alternate function on STM32F42xxx and \nSTM32F43xxx.\nIWDG\nUpdate note in Table 107: Min/max IWDG timeout period (in ms) at 32 kHz (LSI).\nCRYPTO and HASH\nRemoved STM32F405/407xx and STM32F42xx from the whole sections. \nRemoved STM32F405/407xx and STM32F42xx from the whole section. \nTIM10/11/13/14\nAdded TIMx_DIER description in Section 19.5: TIM10/11/13/14 registers.\nETHERNET:\nUpdated Table 187: Clock range.\nUSB OTG FS:\nRemoved TRDT formula in Section 34.17.7: Worst case response time and added \nTable 203: TRDT values.\nUSB OTG HS:\nRemoved TRDT formula in Section 35.13.8: Worst case response time and added \nTable 213: TRDT values.\nFSMC:\nUpdated EXTMOD definition in Section : SRAM/NOR-Flash chip-select control \nregisters 1..4 (FSMC_BCR1..4).\nUpdated ADDSET definition in Section : SRAM/NOR-Flash chip-select timing \nregisters 1..4 (FSMC_BTR1..4) and Section : SRAM/NOR-Flash write timing \nregisters 1..4 (FSMC_BWTR1..4).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRM0090 Rev 21\n1735/1757\nRM0090\nRevision history\n1751\n14-Oct-2014\n8 \n(continued)\nFMC:\nModified step 7 in Section : SDRAM initialization.\nModified SDRAM refresh rate equations and example in Section : SDRAM Refresh \nTimer register (FMC_SDRTR) and updated definition of COUNT bits. \nUpdated EXTMOD definition in Section : SRAM/NOR-Flash chip-select control \nregisters 1..4 (FMC_BCR1..4).\nUpdated ADDSET definition in Section : SRAM/NOR-Flash chip-select timing \nregisters 1..4 (FMC_BTR1..4) and Section : SRAM/NOR-Flash write timing \nregisters 1..4 (FMC_BWTR1..4).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRevision history\nRM0090\n1736/1757\nRM0090 Rev 21\n16-Mar-2015\n9\nPWR: \nUpdated Section 5.1.2: Battery backup domain.\nUpdated Table 23: Low-power mode summary to add Return from ISR as entry \ncondition. \nAdded Section : Entering low-power mode and Section : Exiting low-power mode.\nUpdated Section : Entering Sleep mode, Section : Exiting Sleep mode, Table 24: \nSleep-now entry and exit and Table 25: Sleep-on-exit entry and exit.\nUpdated Section : Entering Stop mode (for STM32F405xx/07xx and \nSTM32F415xx/17xx), Section : Exiting Stop mode (for STM32F405xx/07xx and \nSTM32F415xx/17xx) and Table 27: Stop mode entry and exit (for \nSTM32F405xx/07xx and STM32F415xx/17xx). Updated Section : Entering Stop \nmode (STM32F42xxx and STM32F43xxx), Section : Exiting Stop mode \n(STM32F42xxx and STM32F43xxx) and Table 29: Stop mode entry and exit \n(STM32F42xxx and STM32F43xxx).\nUpdated Section : Entering Standby mode, Section : Exiting Standby mode and \nTable 30: Standby mode entry and exit.\nRCC:\nUpdated bits 24 to 31 access type in Section 7.3.21: RCC clock control & status \nregister (RCC_CSR). \nGPIOs:\nAdded port A reset value in Section 8.4.3: GPIO port output speed register \n(GPIOx_OSPEEDR) (x = A..I/J/K).\nDMA:\nUpdate FTH[1:0] description in Section 10.5.10: DMA stream x FIFO control \nregister (DMA_SxFCR) (x = 0..7).\nTIM2/5:\nRegister format changed to 32 bits instead of 16 in Section 18.4.10: TIMx counter \n(TIMx_CNT) and Section 18.4.12: TIMx auto-reload register (TIMx_ARR).\nTIM9 to 14: \nUpdated Table 101: TIMx internal trigger connection\nWWDG:\nUpdated Figure 214: Watchdog block diagram and Section 22.4: How to program \nthe watchdog timeout. \nUpdated Figure 215: Window watchdog timing diagram\nRNG:\nReplaced PLL48CLK by RNG_CLK in the whole section. \nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRM0090 Rev 21\n1737/1757\nRM0090\nRevision history\n1751\n16-Mar-2015\n9 \n(continued)\nI2C2: \nUpdated FREQ[5:0] description in Section 27.6.2: I2C Control register 2 \n(I2C_CR2). \nUSART:\nRemoved note related to RXNEIE in Section : Reception using DMA\nFSMC:\nUpdated Figure 474: Synchronous multiplexed read mode waveforms - NOR, \nPSRAM (CRAM).\nUSB OTG FS\nUpdated Table 203: TRDT values\nFMC\nUpdated FMC_NL in Figure 456: FMC block diagram.\nUpdated ‘Memory wait’ and ‘Memory data bus high-z’ parameters in Table 289: \nProgrammable NAND Flash/PC Card access parameters.\nUpdated Section : Common memory space timing register 2..4 (FMC_PMEM2..4).\nUpdated Figure 476: NAND Flash/PC Card controller waveforms for common \nmemory access.\nDEBUG:\nUpdated REV_ID[15:0) and JTAG ID code in Section 38.6.1: MCU device ID code \nand Section 38.6.2: Boundary scan TAP, respectively\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRevision history\nRM0090\n1738/1757\nRM0090 Rev 21\n28-Jul-2015\n10\nEmbedded Flash memory interface\nUpdated Section 3.7.5: Proprietary code readout protection (PCROP),\nPower controller (PWR)\nAdded the last sentence in Subsection: Entering low-power mode of Section 5.3: \nLow-power modes,\nAdded the bullet points about the interrupt in mode entry in Table 24: Sleep-now \nentry and exit, Table 25: Sleep-on-exit entry and exit, Table 27: Stop mode entry \nand exit (for STM32F405xx/07xx and STM32F415xx/17xx), Table 29: Stop mode \nentry and exit (STM32F42xxx and STM32F43xxx)\nAdded the last point to Mode entry, on return from ISR in Table 30: Standby mode \nentry and exit,\nAdded the note in Section: Entering sleep mode in Section 5.3.3: Sleep mode.\nGeneral-purpose I/Os (GPIO)\nUpdated OSPEED[1:0] definition of GPIOx_OSPEEDR register in Section 8.4.3: \nGPIO port output speed register (GPIOx_OSPEEDR) (x = A..I/J/K)\nLCD-TFT Controller (LTDC)\nCorrected the bit field for WHSTPOS in the second bullet point in Section: Window \nin Section 16.4.2: Layer programmable parameters.\nAdvanced-control timers (TIM1&TIM8)\nAdded the note in Section 17.3.20: Timer synchronization,\nUpdated ETF[3:0] description in Section 17.4.3: TIM1 and TIM8 slave mode control \nregister (TIMx_SMCR),\nUpdated IC1F[3:0] description in Section 17.4.7: TIM1 and TIM8 capture/compare \nmode register 1 (TIMx_CCMR1),\nAdded the note to MMS2 bit description in Section 17.4.8: TIM1 and TIM8 \ncapture/compare mode register 2 (TIMx_CCMR2),\nAdded the note to SMS[2:0] bit description in Section 17.4.3: TIM1 and TIM8 slave \nmode control register (TIMx_SMCR).\nGeneral-purpose timers (TIM2 to TIM5)\nAdded the note in Section 18.3.15: Timer synchronization,\nUpdated SMS[2:0] description in Section 18.4.3: TIMx slave mode control register \n(TIMx_SMCR),\nAdded the note to MMS2 bit description in Section 18.4.2: TIMx control register 2 \n(TIMx_CR2),\nAdded the note to SMS[2:0] bit description in Section 18.4.3: TIMx slave mode \ncontrol register (TIMx_SMCR).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRM0090 Rev 21\n1739/1757\nRM0090\nRevision history\n1751\n28-Jul-2015\n10 \n(Continued)\nGeneral-purpose timers (TIM9 to TIM14)\nAdded the note in Section 19.3.12: Timer synchronization (TIM9/12),\nAdded the note to MMS2 bit description,\nAdded the note to SMS[2:0] bit description in Section 19.4.2: TIM9/12 slave mode \ncontrol register (TIMx_SMCR).\nWindow watchdog (WWDG)\nUpdated.Figure 214: Watchdog block diagram\nController area network (bxCAN)\nReplaced tCAN with tq,\nFlexible static memory controller (FSMC)\nAdded the paragraph about Cross boundary page for Cellular RAM 1.5 in Section \n36.5.5: Synchronous transactions,\nUpdated MEMHIZx, MEMHOLDx, MEMSETx bit field descriptions for \nFSMC_PME2..4 register in Section 36.5.5: Synchronous transactions,\nUpdated ATTSET, ATTHOLD, ATTHIZ bit field descriptions for FSMC_PATT2..4 \nregister in Section 36.5.5: Synchronous transactions,\nUpdated IRS and IFS bit descriptions for FMC_SR2..4 in Section 36.5.5: \nSynchronous transactions,\nRenamed ADDSET as ADDSET[3:0] and MTYP as MTYP[1:0],\nAddition of CPSIZE in FSMC_BCRx bit fields in Table 226: FSMC_BCRx bit fields, \nTable 228: FSMC_BCRx bit fields, Table 231: FSMC_BCRx bit fields, Table 234: \nFSMC_BCRx bit fields, Table 237: FSMC_BCRx bit fields, Table 240: FSMC_BCRx \nbit fields, Table 242: FSMC_BCRx bit fields,\nAdded CPIZE[2:0] in FMC_BCR1...4 registers in ,Section 36.5.6: NOR/PSRAM \ncontrol registers Section NOR/PSRAM control re\nAdded CPSIZE[2:0] for FMC_BCRx registers in Section 36.6.9: FSMC register \nmap.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRevision history\nRM0090\n1740/1757\nRM0090 Rev 21\n28-Jul-2015\n10 \n(Continued)\nFlexible memory controller (FMC)\nAdded the paragraph about Cross boundary page for Cellular RAM 1.5 in Section \n37.5.5: Synchronous transactions,\nUpdated BUSTURN bit field description for FMC_BTR1..4 register in Section \n37.5.6: NOR/PSRAM controller registers,\nUpdated MEMHIZx, MEMHOLDx, MEMSETx bit field descriptions for \nFMC_PME2..4 register in Section 37.6.8: NAND Flash/PC Card controller registers,\nUpdated ATTSET, ATTHOLD, ATTHIZ bit field descriptions for FMC_PATT2..4 \nregister in Section 37.6.8: NAND Flash/PC Card controller registers,\nUpdated IRS and IFS bit descriptions for FMC_SR2..4 in Section 37.6.8: NAND \nFlash/PC Card controller registers,\nUpdated the section SDRAM initialization with the last item in the numbered list in \nSection 37.7.5: SDRAM controller registers,\nRenamed ADDSET as ADDSET[3:0] and MTYP as MTYP[1:0],\nAddition of CPSIZE in Table 269: FMC_BCRx bit fields, Table 271: FMC_BCRx bit \nfields, Table 274: FMC_BCRx bit fields, Table 277: FMC_BCRx bit fields, Table 280: \nFMC_BCRx bit fields, Table 283: FMC_BCRx bit fields, Table 285: FMC_BCRx bit \nfields, Table 287: FMC_BCRx bit fields,\nAdded the paragraph about Cross boundary page for Cellular RAM 1.5 in Section \n37.5.5: Synchronous transactions,\nAdded CPIZE[2:0] in FMC_BCR1...4 registers in Section 37.5.6: NOR/PSRAM \ncontroller registers, \nAdded CPSIZE[2:0] for FMC_BCRx registers in Section 37.8: FMC register map.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRM0090 Rev 21\n1741/1757\nRM0090\nRevision history\n1751\n20-Oct-2015\n11\nReset and clock controller (RCC)\nUpdated STM32F405/407/415/417xx Figure 21: Clock tree.\nUpdated \nGeneral purpose I/O (GPIOs)\nChanged definition of OSPEEDR bits in Section 8.4.3: GPIO port output speed \nregister (GPIOx_OSPEEDR) (x = A..I/J/K).\nLCD-TFT display controller (LTDC):\nChanged LRDC_IER into LTDC_IER in Section 16.5: LTDC interrupts. \nUpdated AHBP[11:0], AAV[11:0 and TOTALW[11:0 in Table 92: LTDC register map \nand reset values.\nController area network (bxCAN):\nUpdated Section 32.3.4: Acceptance filters and Section 32.7.4: Identifier filtering.\nFlexible static memory controller (FSMC)\nUpdated BUSTURN description in Section : SRAM/NOR-Flash write timing \nregisters 1..4 (FSMC_BWTR1..4) and Section : SRAM/NOR-Flash chip-select \ntiming registers 1..4 (FSMC_BTR1..4)\nUpdated note related to IRS and IFS bits in Section : FIFO status and interrupt \nregister 2..4 (FSMC_SR2..4).\nFlexible memory controller (FMC)\nUpdated paragraph related to the cacheable read FIFO in Section : SDRAM \ncontroller read cycle.\nUpdated BUSTURN description in Section : SRAM/NOR-Flash write timing \nregisters 1..4 (FMC_BWTR1..4) and Section : SRAM/NOR-Flash chip-select timing \nregisters 1..4 (FMC_BTR1..4).\nUpdated note related to IRS and IFS bits in Section : FIFO status and interrupt \nregister 2..4 (FMC_SR2..4).\nReal-time clock (RTC2)\nUpdated WUCKSEL prescaler input in Figure 237: RTC block diagram.\nUpdated 3rd step in Section : Programming the wakeup timer.\nUpdated WUTWF bit definition in Section 26.6.4: RTC initialization and status \nregister (RTC_ISR).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRevision history\nRM0090\n1742/1757\nRM0090 Rev 21\n17-May-2016\n12\n Flash memory interface\nRemoved note related to boot from Bank 2 in Section 2.4: Boot configuration.\nUpdated notes in Section 3.7.3: Read protection (RDP).\nChanged number of LATENCY bits in Section 3.9.2: Flash access control register \n(FLASH_ACR) for STM32F42xxx and STM32F43xxx\nIn Table 9: 1 Mbyte dual bank Flash memory organization (STM32F42xxx and \nSTM32F43xxx): updated sector 19 size and option bytes (bank 2) address range.\nPower control (PWR) \nRemoved reference to low-power mode in Section 5.1.4: Voltage regulator for \nSTM32F42xxx and STM32F43xxx, Section : Entering Stop mode (STM32F42xxx \nand STM32F43xxx) and Section : Exiting Stop mode (STM32F42xxx and \nSTM32F43xxx).\nAnalog-to-digital converter (ADC)\nAdded note related to ADC_HTR and ADC_LTR register programming in Section \n13.13.7: ADC watchdog higher threshold register (ADC_HTR) and Section 13.13.8: \nADC watchdog lower threshold register (ADC_LTR).\nChrom-Art Accelerator™ controller (DMA2D)\nUpdated Section 11.3.12: DMA2D transfer control (start, suspend, abort and \ncompletion).\nSection 11.5.8: DMA2D foreground PFC control register (DMA2D_FGPFCCR): \nupdated START bit access type\nSection 11.5.10: DMA2D background PFC control register (DMA2D_BGPFCCR): \nupdated START bit access and description. \nLCD-TFT controller (LTDC)\nUpdated Section 16.3.2: LTDC reset and clocks. \nModified LCD_DE description in Table 89: LCD-TFT pins and signal interface.\nModified Section 16.7.15: LTDC Layerx Window Horizontal Position Configuration \nRegister (LTDC_LxWHPCR) (where x=1..2) and Section 16.7.16: LTDC Layerx \nWindow Vertical Position Configuration Register (LTDC_LxWVPCR) (where \nx=1..2).\nGeneral-purpose timers (TIM2 to TIM5)\nUpdated Section 18.4.11: TIMx prescaler (TIMx_PSC).\nGeneral-purpose timers (TIM9 to TIM14)\nAdded OPM bit in Section 19.5.1: TIM10/11/13/14 control register 1 (TIMx_CR1).\nUpdated Section 19.4.9: TIM9/12 prescaler (TIMx_PSC) and Section 19.5.8: \nTIM10/11/13/14 prescaler (TIMx_PSC).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRM0090 Rev 21\n1743/1757\nRM0090\nRevision history\n1751\n17-May-2016\n12 \n(continued)\nGeneral-purpose timers (TIM6 and TIM7)\nUpdated Section 20.4.7: TIM6 and TIM7 prescaler (TIMx_PSC).\nReal-time clock (RTC)\nUpdated conditions for running under System reset in Section 26.3.7: Resetting the \nRTC.\nUpdated Section 26.3.14: Calibration clock output.\nAdded note related to TSE in Section 26.6.3: RTC control register (RTC_CR). \nUpdated caution note related to TAMP1TRG in Section 26.6.17: RTC tamper and \nalternate function configuration register (RTC_TAFCR) register.\nUniversal synchronous asynchronous receiver transmitter (USART)\nReplaced all occurrences of nCTS by CTS, nRTS by RTS and SCLK by CK.\nFlexible static memory controller (FSMC)\nUpdated Section 36.3: AHB interface.\nAdded note related to the hold phase delay below Figure 454: NAND/PC Card \ncontroller timing for common memory access. \nUpdated Section 36.6.5: NAND Flash prewait functionality.\nUpdated BUSTURN description in Section : SRAM/NOR-Flash chip-select timing \nregisters 1..4 (FSMC_BTR1..4).\nUpdated MEMHOLDx in Section : Common memory space timing register 2..4 \n(FSMC_PMEM2..4) and ATTHOLD in Section : Attribute memory space timing \nregisters 2..4 (FSMC_PATT2..4).\nFlexible memory controller (FMC)\nUpdated Section 37.3: AHB interface.\nAdded note related to the hold phase delay below Figure 476: NAND Flash/PC \nCard controller waveforms for common memory access. \nUpdated Section 37.6.5: NAND Flash prewait functionality.\nUpdated BUSTURN description in Section : SRAM/NOR-Flash chip-select timing \nregisters 1..4 (FMC_BTR1..4).\nUpdated MEMHOLDx in Section : Common memory space timing register 2..4 \n(FMC_PMEM2..4) and ATTHOLD in Section : Attribute memory space timing \nregisters 2..4 (FMC_PATT2..4).\nDebug (DBG)\nUpdated value to be programmed to the ETM Trace Start/stop register to enable the \ntrace in Section 38.15.4: ETM configuration example.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRevision history\nRM0090\n1744/1757\nRM0090 Rev 21\n20-Sep-2016\n13\nAnalog-to-digital converter (ADC) \nUpdated DMA mode 1 and DMA mode 3 description in Section 13.9: Multi ADC \nmode.\nLCD-TFT controller\nUpdated values to be programmed to LTDC_SSCR in Section : Example of \nSynchronous timings configuration\nUpdated Section 16.4.2: Layer programmable parameters/Windowing. \nAdvanced-control timers (TIM1 and TIM8)\nUpdated Section 17.3.21: Debug mode.\nExtended Section 17.4.20: TIM1 and TIM8 DMA address for full transfer \n(TIMx_DMAR) to 32 bits. \nUpdated Table 95: Output control bits for complementary OCx and OCxN channels \nwith break feature output state for MOE = 0.\nUpdated TIM1 and TIM8 auto-reload register (TIMx_ARR) reset value. \nUpdated TIMx_CCR1/2/3/4 description when CC1 channel is configured as inputs \nand changed bit access type to rw/ro.\nGeneral-purpose timers (TIM2 to TIM5)\nUpdated TIMx auto-reload register (TIMx_ARR) reset value.\nUpdated TIMx_CCR1/2/3/4 description when CC1 channel is configured as inputs \nand changed bit access type to rw/ro.\nGeneral-purpose timers (TIM9 to TIM14)\nUpdated TIM9/12 auto-reload register (TIMx_ARR) and TIM10/11/13/14 auto-\nreload register (TIMx_ARR) reset value.\nUpdated TIMx_CCR1 description when CC1 channel is configured as inputs and \nchanged bit access type to rw/ro.\nBasic timers (TIM6 to TIM7)\nUpdated TIM6 and TIM7 auto-reload register (TIMx_ARR).\nSecure digital input/output interface (SDIO)\nUpdated Section 31.1: SDIO main features up to 50 MHz.\nUpdated Section 31.3: SDIO functional description SDIO_CK description.\nUpdated note removing 48 MHz in Section 31.9.1: SDIO power control register \n(SDIO_POWER), Section 31.9.2: SDI clock control register (SDIO_CLKCR), \nSection 31.9.4: SDIO command register (SDIO_CMD) and Section 31.9.9: SDIO \ndata control register (SDIO_DCTRL).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRM0090 Rev 21\n1745/1757\nRM0090\nRevision history\n1751\n20-Sep-2016\n13 \n(continued)\nFMC\nUpdate BUSTURN bit description in Section : SRAM/NOR-Flash chip-select timing \nregisters 1..4 (FMC_BTR1..4) and Section : SRAM/NOR-Flash write timing \nregisters 1..4 (FMC_BWTR1..4). \nDebug support\nSpecified behavior of timers with complementary outputs in Section 38.16.2: Debug \nsupport for timers, watchdog, bxCAN and I2C. \nUpdated DBG_TIMx_STOP bit description in Section 38.16.4: Debug MCU APB1 \nfreeze register (DBGMCU_APB1_FZ) and Section 38.16.4: Debug MCU APB1 \nfreeze register (DBGMCU_APB1_FZ).\nElectronic signature\nUpdated Section 24.1: Unique device ID register (96 bits).\n21-Apr-2017\n14\nUpdated:\n– Section 5.5.2: PWR power control/status register (PWR_CSR) for STM32F42xxx \nand STM32F43xxx\n– Section 6.3.14: RCC APB2 peripheral clock enable register (RCC_APB2ENR)\n– Section 14.3.5: DAC output voltage\n– Section 38.6.1: MCU device ID code\n– Figure 237: RTC block diagram\nDeleted:\n– Section 7.3.15: RCC APB2 peripheral clock enable register(RCC_APB2ENR)\n18-Jul-2017\n15\nUpdated:\n– Section 3.9.10: Flash option control register (FLASH_OPTCR) for STM32F42xxx \nand STM32F43xxx\n– OTG_FS USB configuration register (OTG_FS_GUSBCFG)\n– Table 142: Error calculation for programmed baud rates at fPCLK = 42 MHz or \nfPCLK = 84 Hz, oversampling by 16 and Table 143: Error calculation for \nprogrammed baud rates at fPCLK = 42 MHz or fPCLK = 84 MHz, oversampling \nby 8.\n23-Apr-2018\n16\nUpdated:\n– Section 30.6.1: Status register (USART_SR)\n– Section 34.16.4: Device-mode registers\n– Section 34.17.6: Operational model\n– Section 35.12.4: Device-mode registers\n– Section 34: USB on-the-go full-speed (OTG_FS)\n– Table 199: Host-mode control and status registers (CSRs)\n– Table 205: OTG_FS register map and reset values\n– Table 210: Device-mode control and status registers\n– Table 215: OTG_HS register map and reset values\nAdded: \n– Figure 412: SOF trigger output to TIM2 ITR1 connection\n– RXOLNY register changed from SPI_CR2 to SPI_CR1 in Section 28.3.4: \nConfiguring the SPI for half-duplex communication and Unidirectional receive-\nonly procedure (BIDIMODE=0 and RXONLY=1)\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRevision history\nRM0090\n1746/1757\nRM0090 Rev 21\n07-Jun-2018\n17\nUpdated:\n– Figure 16: Clock tree (STM32F42xxx an STM32F43xxx) and Figure 21: Clock \ntree (STM32F405xx/07xx and STM32F415xx/17xx)\n– Figure 27: Selecting an alternate function on STM32F42xxx and STM32F43xxx\n– Table 61: Vector table for STM32F405xx/07xx and STM32F415xx/17xx and Table \n62: Vector table for STM32F42xxx and STM32F43xxx\n– Section 29.17.5: SAI xInterrupt mask register (SAI_xIM) where x is A or B\n– Section 38.6.1: MCU device ID code\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRM0090 Rev 21\n1747/1757\nRM0090\nRevision history\n1751\n25-Feb-2019\n18\nSection 6: Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nUpdated OTGHSULPILPEN bit description in RCC AHB1 peripheral clock enable in \nlow power mode register (RCC_AHB1LPENR) and OTGHSULPIEN bit description \nin RCC AHB1 peripheral clock register (RCC_AHB1ENR).\nSection 7: Reset and clock control for STM32F405xx/07xx and \nSTM32F415xx/17xx(RCC):\nUpdated RCC APB2 peripheral clock enabled in low power mode register \n(RCC_APB2LPENR) reset value.\nUpdated OTGHSULPILPEN bit description in RCC AHB1 peripheral clock enable in \nlow power mode register (RCC_AHB1LPENR) and OTGHSULPIEN bit description \nin RCC AHB1 peripheral clock enable register (RCC_AHB1ENR).\nSection 13: Analog-to-digital converter (ADC)\nUpdate Section : Dual ADC mode.\nSection 17: Advanced-control timers (TIM1 and TIM8)\nUpdated Figure 113: Capture/compare channel 1 main circuit.\nFigure 19: General-purpose timers (TIM9 to TIM14)\nUpdated Figure 194: Capture/compare channel 1 main circuit.\nSection 34: USB on-the-go full-speed (OTG_FS)\nUpdated Section : SETUP and OUT data transfers and Updated Section : IN data \ntransfers. Modified Table 200: Device-mode control and status registers.\nSection 35: USB on-the-go high-speed (OTG_HS)\nUpdated Table 208: Core global control and status registers (CSRs) and Table 210: \nDevice-mode control and status registers.\nUpdated Section : OTG_HS device IN endpoint transmit FIFO size register \n(OTG_HS_DIEPTXFx) (x = 1..5, where x is the FIFO_number), Section : OTG \ndevice endpoint-x control register (OTG_HS_DIEPCTLx) (x = 0..5, where x = \nEndpoint_number), Section : OTG_HS device endpoint-x control register \n(OTG_HS_DOEPCTLx) (x = 1..5, where x = Endpoint_number), Section : OTG_HS \ndevice endpoint-x interrupt register (OTG_HS_DIEPINTx) (x = 0..5, where x = \nEndpoint_number), Section : OTG_HS device endpoint-x interrupt register \n(OTG_HS_DOEPINTx) (x = 0..5, where x = Endpoint_number), Section : OTG_HS \ndevice endpoint-x DMA address register (OTG_HS_DIEPDMAx / \nOTG_HS_DOEPDMAx) (x = 0..5, where x = Endpoint_number).\nUpdated Section : SETUP and OUT data transfers and Section : IN data transfers.\nSection 38: Debug support (DBG)\nUpdated REV_ID in DBGMCU_CR register.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRevision history\nRM0090\n1748/1757\nRM0090 Rev 21\n25-Feb-2021\n19\nUpdated:\n– Section 2: Memory and bus architecture:\n– Figure 1: System architecture for STM32F405xx/07xx and STM32F415xx/17xx \ndevices\n– Figure 2: System architecture for STM32F42xxx and STM32F43xxx devices\n– Section 3: Embedded Flash memory interface:\n– Table 16: Description of the option bytes (STM32F405xx/07xx and \nSTM32F415xx/17xx)\n– Table 17: Description of the option bytes (STM32F42xxx and STM32F43xxx)\n– Section 12: Interrupts and events:\n– Table 61: Vector table for STM32F405xx/07xx and STM32F415xx/17xx\n– Table 62: Vector table for STM32F42xxx and STM32F43xxx\n– Section 13: Analog-to-digital converter (ADC):\n– Section 13.3.5: Continuous conversion mode\n– Section 13.8.1: Using the DMA\n– Section 13.10: Temperature sensor\n– Section 17: Advanced-control timers (TIM1 and TIM8):\n– Figure 86: Advanced-control timer block diagram\n– Section 17.4.9: TIM1 and TIM8 capture/compare enable register (TIMx_CCER)\n– Section 27: Inter-integrated circuit (I2C) interface:\n– Section 27.6.2: I2C Control register 2 (I2C_CR2)\n– Section 27.6.8: I2C Clock control register (I2C_CCR)\n– Section 31: Secure digital input/output interface (SDIO):\n– Section 31.9.2: SDI clock control register (SDIO_CLKCR)\n– Section 32: Controller area network (bxCAN):\n– Section 32.4.1: Initialization mode\n– Section 33: Ethernet (ETH): media access control (MAC) with DMA controller:\n– Section : TxDMA operation: default (non-OSF) mode\n– Section : Normal Tx DMA descriptors\n– Section 35: USB on-the-go high-speed (OTG_HS):\n– Section : Host port power\n– Section : OTG_HS core interrupt register (OTG_HS_GINTSTS)\n– Section : OTG_HS all endpoints interrupt mask register (OTG_HS_DAINTMSK)\n– Table 215: OTG_HS register map and reset values\n– Section 35.13.2: Host initialization\n– Figure 416: Transmit FIFO write task\n– Figure 417: Receive FIFO read task\n– Figure 426: Receive FIFO packet read in slave mode\n– Figure 427: Processing a SETUP packet\n– Section 38: Debug support (DBG):\n– Section : DBGMCU_IDCODE\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRM0090 Rev 21\n1749/1757\nRM0090\nRevision history\n1751\n05-Feb-2024\n20\nSection : Introduction:\n– Mentioned that the microcontrollers include ST state-of-the-art patented \ntechnology\n– Added errata sheets in the list of reference documents. \nSection 2: Memory and bus architecture\n– Section 2.3.1: Embedded SRAM, updated the SRAM that can be accessed \nthrough System or I-Code/D-Code bus.\nSection 3.4: Embedded flash memory in STM32F42xxx and STM32F43xxx\n– Updated Bank 2 section 14 base address in Table 12: Flash module - 2 Mbyte \ndual bank organization (STM32F42xxx and STM32F43xxx).\n– Specified that dual bank organization is not available on 512 Kbyte devices, and \nadded Table 16: 512 Kbyte single bank flash memory organization \n(STM32F42xxx and STM32F43xxx).\n– Updated Section 3.8.2: Program/erase parallelism.\n– In Section 3.9.3: Read protection (RDP), added note concerning RDP when \ndebugger is connected through JTAG/SWD. \nSection 5: Power controller (PWR)\n– Updated Figure 12: Power-on reset/power-down reset waveform.\n– Updated no external battery use case in Section 5.1.2: Battery backup domain.\n– Updated DBP bit description in PWR power control register (PWR_CR) for \nSTM32F405xx/07xx and STM32F415xx/17xx and PWR power control register \n(PWR_CR) for STM32F42xxx and STM32F43xxx.\n– Updated BRE bit description in PWR power control/status register (PWR_CSR) \nfor STM32F405xx/07xx and STM32F415xx/17xx and PWR power control/status \nregister (PWR_CSR) for STM32F42xxx and STM32F43xxx.\nSection 6: Reset and clock control for STM32F42xxx and STM32F43xxx and \nNA(RCC)\n– Updated Section 6.1.1: System reset and Section 6.1.3: Backup domain reset.\n– Updated ethernet PTP clock in Figure 16: Clock tree.\n– Added note regarding backup domain reset in BDRST bit of RCC Backup domain \ncontrol register (RCC_BDCR).\n– Added register reset values in Table 38: RCC register map and reset values for \nSTM32F42xxx and STM32F43xxx\nSection 7: Reset and clock control for STM32F405xx/07xx and \nSTM32F415xx/17xx(RCC)\n– Updated Section 7.1.1: System reset and Section 7.1.3: Backup domain reset.\n– Updated ethernet PTP clock in Figure 21: Clock tree\n– Added note regarding backup domain reset in BDRST bit of RCC Backup domain \ncontrol register (RCC_BDCR).\n– Added register reset values in Table 39: RCC register map and reset values for \nSTM32F405xx/07xx and STM32F415xx/17xx\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRevision history\nRM0090\n1750/1757\nRM0090 Rev 21\n05-Feb-2024\n20 \n(continued)\nSection 10: DMA controller (DMA)\nUpdated DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7) address \noffset.\nSection 12: Interrupts and events\nChanged Pending register (EXTI_PR) reset value to 0x0000 0000.\nSection 17: Advanced-control timers (TIM1 and TIM8)\nUpdated Section 17.3.7: PWM input mode.\nUpdated SMS in Section 17.4.3: TIM1 and TIM8 slave mode control register \n(TIMx_SMCR).\nUpdated OC1PE in Section 17.4.7: TIM1 and TIM8 capture/compare mode register \n1 (TIMx_CCMR1).\nSection 22: Window watchdog (WWDG)\nUpdated tWWDG equation in Section 22.4: How to program the watchdog timeout.\nSection 26: Real-time clock (RTC)\n– Updated HSE clock in Figure 237: RTC block diagram (NA devices).\n– Updated Section 26.3.6: Reading the calendar.\nSection 29: Serial audio interface (SAI)\n– In the whole section, replaced TDM by free protocol mode.\n– In Section 29.18.4: SAI x frame configuration register (SAI_XFRCR) where x is A \nor B, specified that FRL[7:0] must be configured when the audio block is \ndisabled.\nSection 34: USB on-the-go full-speed (OTG_FS)\n– Updated Figure 392: Device-mode FIFO address mapping and AHB FIFO \naccess mapping.\n– Modified OTG_FS USB configuration register \n(OTG_FS_GUSBCFG)OTG_FS_GUSBCFG reset value.\nSection 33: Ethernet (ETH): media access control (MAC) with DMA controller\nUpdated bits that control the checksum in Section : Transmit checksum offload\nSection 38: Debug support (DBG)\nRemoved note on APB bridge write buffer after Table 302: Flexible SWJ-DP pin \nassignment\nUpdated REV_ID[15:0] in Section : DBGMCU_IDCODE\nSection 39: Device electronic signature\nUpdated Section 39.1: Unique device ID register (96 bits)\nAdded Section 40: Important security notice.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nRM0090 Rev 21\n1751/1757\nRM0090\nRevision history\n1751\n07-Jun-2024\n21\nUpdated the note in Bit[11:0] description of Section 27.6.8: I2C Clock control \nregister (I2C_CCR).\nFixed typo in Section 12.1.3: Interrupt and exception vectors.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n\n\n<>\n\nIndex\nRM0090\n1752/1751\nRM0090 Rev 21\nIndex\nA\nADC_CCR . . . . . . . . . . . . . . . . . . . . . . . . . . .430\nADC_CDR . . . . . . . . . . . . . . . . . . . . . . . . . . .433\nADC_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .419\nADC_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .421\nADC_CSR . . . . . . . . . . . . . . . . . . . . . . . . . . .429\nADC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . .428\nADC_HTR . . . . . . . . . . . . . . . . . . . . . . . . . . .424\nADC_JDRx . . . . . . . . . . . . . . . . . . . . . . . . . . .428\nADC_JOFRx . . . . . . . . . . . . . . . . . . . . . . . . .424\nADC_JSQR . . . . . . . . . . . . . . . . . . . . . . . . . .427\nADC_LTR . . . . . . . . . . . . . . . . . . . . . . . . . . . .425\nADC_SMPR1 . . . . . . . . . . . . . . . . . . . . . . . . .423\nADC_SMPR2 . . . . . . . . . . . . . . . . . . . . . . . . .423\nADC_SQR1 . . . . . . . . . . . . . . . . . . . . . . . . . .425\nADC_SQR2 . . . . . . . . . . . . . . . . . . . . . . . . . .426\nADC_SQR3 . . . . . . . . . . . . . . . . . . . . . . . . . .426\nADC_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .418\nC\nCAN_BTR . . . . . . . . . . . . . . . . . . . . . . . . . .1109\nCAN_ESR . . . . . . . . . . . . . . . . . . . . . . . . . .1108\nCAN_FA1R . . . . . . . . . . . . . . . . . . . . . . . . .1119\nCAN_FFA1R . . . . . . . . . . . . . . . . . . . . . . . .1119\nCAN_FiRx . . . . . . . . . . . . . . . . . . . . . . . . . .1120\nCAN_FM1R . . . . . . . . . . . . . . . . . . . . . . . . .1118\nCAN_FMR . . . . . . . . . . . . . . . . . . . . . . . . . .1117\nCAN_FS1R . . . . . . . . . . . . . . . . . . . . . . . . .1118\nCAN_IER . . . . . . . . . . . . . . . . . . . . . . . . . . .1106\nCAN_MCR . . . . . . . . . . . . . . . . . . . . . . . . . .1100\nCAN_MSR . . . . . . . . . . . . . . . . . . . . . . . . . .1102\nCAN_RDHxR . . . . . . . . . . . . . . . . . . . . . . . .1116\nCAN_RDLxR . . . . . . . . . . . . . . . . . . . . . . . .1116\nCAN_RDTxR . . . . . . . . . . . . . . . . . . . . . . . .1115\nCAN_RF0R . . . . . . . . . . . . . . . . . . . . . . . . .1105\nCAN_RF1R . . . . . . . . . . . . . . . . . . . . . . . . .1106\nCAN_RIxR . . . . . . . . . . . . . . . . . . . . . . . . . .1114\nCAN_TDHxR . . . . . . . . . . . . . . . . . . . . . . . .1113\nCAN_TDLxR . . . . . . . . . . . . . . . . . . . . . . . .1113\nCAN_TDTxR . . . . . . . . . . . . . . . . . . . . . . . .1112\nCAN_TIxR . . . . . . . . . . . . . . . . . . . . . . . . . .1111\nCAN_TSR . . . . . . . . . . . . . . . . . . . . . . . . . .1103\nCRC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . .115\nCRC_IDR . . . . . . . . . . . . . . . . . . . . . . . . . . . .115\nCRYP_CR . . . . . . . . . . . . . . . . . . . . . . .751, 753\nCRYP_DIN . . . . . . . . . . . . . . . . . . . . . . . . . . .757\nCRYP_DMACR . . . . . . . . . . . . . . . . . . . . . . .759\nCRYP_DOUT . . . . . . . . . . . . . . . . . . . . . . . . 758\nCRYP_IMSCR . . . . . . . . . . . . . . . . . . . . . . . . 759\nCRYP_IV0LR . . . . . . . . . . . . . . . . . . . . . . . . 763\nCRYP_IV0RR . . . . . . . . . . . . . . . . . . . . . . . . 763\nCRYP_IV1LR . . . . . . . . . . . . . . . . . . . . . . . . 764\nCRYP_IV1RR . . . . . . . . . . . . . . . . . . . . . . . . 764\nCRYP_K0LR . . . . . . . . . . . . . . . . . . . . . . . . . 761\nCRYP_K0RR . . . . . . . . . . . . . . . . . . . . . . . . . 761\nCRYP_K1LR . . . . . . . . . . . . . . . . . . . . . . . . . 762\nCRYP_K1RR . . . . . . . . . . . . . . . . . . . . . . . . . 762\nCRYP_K2LR . . . . . . . . . . . . . . . . . . . . . . . . . 762\nCRYP_K2RR . . . . . . . . . . . . . . . . . . . . . . . . . 762\nCRYP_K3LR . . . . . . . . . . . . . . . . . . . . . . . . . 762\nCRYP_K3RR . . . . . . . . . . . . . . . . . . . . . . . . . 763\nCRYP_MISR . . . . . . . . . . . . . . . . . . . . . . . . . 760\nCRYP_RISR . . . . . . . . . . . . . . . . . . . . . . . . . 760\nCRYP_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . 756\nD\nDAC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448\nDAC_DHR12L1 . . . . . . . . . . . . . . . . . . . . . . . 452\nDAC_DHR12L2 . . . . . . . . . . . . . . . . . . . . . . . 453\nDAC_DHR12LD . . . . . . . . . . . . . . . . . . . . . . 454\nDAC_DHR12R1 . . . . . . . . . . . . . . . . . . . . . . 451\nDAC_DHR12R2 . . . . . . . . . . . . . . . . . . . . . . 453\nDAC_DHR12RD . . . . . . . . . . . . . . . . . . . . . . 454\nDAC_DHR8R1 . . . . . . . . . . . . . . . . . . . . . . . 452\nDAC_DHR8R2 . . . . . . . . . . . . . . . . . . . . . . . 453\nDAC_DHR8RD . . . . . . . . . . . . . . . . . . . . . . . 455\nDAC_DOR1 . . . . . . . . . . . . . . . . . . . . . . . . . . 455\nDAC_DOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 455\nDAC_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456\nDAC_SWTRIGR . . . . . . . . . . . . . . . . . . . . . . 451\nDBGMCU_APB1_FZ . . . . . . . . . . . . . . . . . . 1708\nDBGMCU_APB2_FZ . . . . . . . . . . . . . . . . . . 1709\nDBGMCU_CR . . . . . . . . . . . . . . . . . . . . . . . 1706\nDBGMCU_IDCODE . . . . . . . . . . . . . . . . . . 1693\nDCMI_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . 470\nDCMI_CWSIZE . . . . . . . . . . . . . . . . . . . . . . . 480\nDCMI_CWSTRT . . . . . . . . . . . . . . . . . . . . . . 480\nDCMI_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . 481\nDCMI_ESCR . . . . . . . . . . . . . . . . . . . . . . . . . 478\nDCMI_ESUR . . . . . . . . . . . . . . . . . . . . . . . . . 479\nDCMI_ICR . . . . . . . . . . . . . . . . . . . . . . . . . . . 477\nDCMI_IER . . . . . . . . . . . . . . . . . . . . . . . . . . . 475\nDCMI_MIS . . . . . . . . . . . . . . . . . . . . . . . . . . . 476\nDCMI_RIS . . . . . . . . . . . . . . . . . . . . . . . . . . . 474\nDCMI_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . 473\n\n\n<>\n\nRM0090\nIndex\nRM0090 Rev 21\n1753/1751\nDMA_HIFCR . . . . . . . . . . . . . . . . . . . . . . . . .330\nDMA_HISR . . . . . . . . . . . . . . . . . . . . . . . . . . .329\nDMA_LIFCR . . . . . . . . . . . . . . . . . . . . . . . . . .330\nDMA_LISR . . . . . . . . . . . . . . . . . . . . . . . . . . .328\nDMA_SxCR . . . . . . . . . . . . . . . . . . . . . . . . . .331\nDMA_SxFCR . . . . . . . . . . . . . . . . . . . . . . . . .336\nDMA_SxM0AR . . . . . . . . . . . . . . . . . . . . . . . .335\nDMA_SxM1AR . . . . . . . . . . . . . . . . . . . . . . . .335\nDMA_SxNDTR . . . . . . . . . . . . . . . . . . . . . . . .334\nDMA_SxPAR . . . . . . . . . . . . . . . . . . . . . . . . .335\nE\nETH_DMABMR . . . . . . . . . . . . . . . . . . . . . .1226\nETH_DMACHRBAR . . . . . . . . . . . . . . . . . . .1239\nETH_DMACHRDR . . . . . . . . . . . . . . . . . . . .1238\nETH_DMACHTBAR . . . . . . . . . . . . . . . . . . .1238\nETH_DMACHTDR . . . . . . . . . . . . . . . . . . . .1238\nETH_DMAIER . . . . . . . . . . . . . . . . . . . . . . .1235\nETH_DMAMFBOCR . . . . . . . . . . . . . . . . . .1237\nETH_DMAOMR . . . . . . . . . . . . . . . . . . . . . .1232\nETH_DMARDLAR . . . . . . . . . . . . . . . . . . . .1228\nETH_DMARPDR . . . . . . . . . . . . . . . . . . . . .1228\nETH_DMARSWTR . . . . . . . . . . . . . . . . . . . .1237\nETH_DMASR . . . . . . . . . . . . . . . . . . . . . . . .1229\nETH_DMATDLAR . . . . . . . . . . . . . . . . . . . .1229\nETH_DMATPDR . . . . . . . . . . . . . . . . . . . . .1227\nETH_MACA0HR . . . . . . . . . . . . . . . . . . . . .1208\nETH_MACA0LR . . . . . . . . . . . . . . . . . . . . . .1209\nETH_MACA1HR . . . . . . . . . . . . . . . . . . . . .1209\nETH_MACA1LR . . . . . . . . . . . . . . . . . . . . . .1210\nETH_MACA2HR . . . . . . . . . . . . . . . . . . . . .1210\nETH_MACA2LR . . . . . . . . . . . . . . . . . . . . . .1211\nETH_MACA3HR . . . . . . . . . . . . . . . . . . . . .1212\nETH_MACA3LR . . . . . . . . . . . . . . . . . . . . . .1212\nETH_MACCR . . . . . . . . . . . . . . . . . . . . . . . .1194\nETH_MACDBGR . . . . . . . . . . . . . . . . . . . . .1205\nETH_MACFCR . . . . . . . . . . . . . . . . . . . . . . .1201\nETH_MACFFR . . . . . . . . . . . . . . . . . . . . . . .1197\nETH_MACHTHR . . . . . . . . . . . . . . . . . . . . .1198\nETH_MACHTLR . . . . . . . . . . . . . . . . . . . . . .1199\nETH_MACIMR . . . . . . . . . . . . . . . . . . . . . . .1208\nETH_MACMIIAR . . . . . . . . . . . . . . . . . . . . .1199\nETH_MACMIIDR . . . . . . . . . . . . . . . . . . . . .1200\nETH_MACPMTCSR . . . . . . . . . . . . . . . . . . .1204\nETH_MACRWUFFR . . . . . . . . . . . . . . . . . .1203\nETH_MACSR . . . . . . . . . . . . . . . . . . . . . . . .1207\nETH_MACVLANTR . . . . . . . . . . . . . . . . . . .1202\nETH_MMCCR . . . . . . . . . . . . . . . . . . . . . . .1213\nETH_MMCRFAECR . . . . . . . . . . . . . . . . . . .1218\nETH_MMCRFCECR . . . . . . . . . . . . . . . . . .1217\nETH_MMCRGUFCR . . . . . . . . . . . . . . . . . .1218\nETH_MMCRIMR . . . . . . . . . . . . . . . . . . . . . 1215\nETH_MMCRIR . . . . . . . . . . . . . . . . . . . . . . 1213\nETH_MMCTGFCR . . . . . . . . . . . . . . . . . . . 1217\nETH_MMCTGFMSCCR . . . . . . . . . . . . . . . 1217\nETH_MMCTGFSCCR . . . . . . . . . . . . . . . . . 1216\nETH_MMCTIMR . . . . . . . . . . . . . . . . . . . . . 1216\nETH_MMCTIR . . . . . . . . . . . . . . . . . . . . . . . 1214\nETH_PTPPPSCR . . . . . . . . . . . . . . . . . . . . 1225\nETH_PTPSSIR . . . . . . . . . . . . . . . . . . . . . . 1221\nETH_PTPTSAR . . . . . . . . . . . . . . . . . . . . . . 1223\nETH_PTPTSCR . . . . . . . . . . . . . . . . . . . . . 1218\nETH_PTPTSHR . . . . . . . . . . . . . . . . . . . . . 1221\nETH_PTPTSHUR . . . . . . . . . . . . . . . . . . . . 1222\nETH_PTPTSLR . . . . . . . . . . . . . . . . . . . . . . 1222\nETH_PTPTSLUR . . . . . . . . . . . . . . . . . . . . 1223\nETH_PTPTSSR . . . . . . . . . . . . . . . . . . . . . . 1224\nETH_PTPTTHR . . . . . . . . . . . . . . . . . . . . . . 1224\nETH_PTPTTLR . . . . . . . . . . . . . . . . . . . . . . 1224\nEXTI_EMR . . . . . . . . . . . . . . . . . . . . . . . . . . 387\nEXTI_FTSR . . . . . . . . . . . . . . . . . . . . . . . . . . 388\nEXTI_IMR . . . . . . . . . . . . . . . . . . . . . . . . . . . 387\nEXTI_PR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389\nEXTI_RTSR . . . . . . . . . . . . . . . . . . . . . . . . . . 388\nEXTI_SWIER . . . . . . . . . . . . . . . . . . . . . . . . . 389\nF\nFLITF_FCR . . . . . . . . . . . . . . . . . . . . . . 104, 106\nFLITF_FKEYR . . . . . . . . . . . . . . . . . . . . . . . . 101\nFLITF_FOPTCR . . . . . . . . . . . . . . 107, 109, 111\nFLITF_FOPTKEYR . . . . . . . . . . . . . . . . . . . . 101\nFLITF_FSR . . . . . . . . . . . . . . . . . . . . . . 102-103\nFSMC_BCR1..4 . . . . . . . . . . . . . . . . . 1580, 1643\nFSMC_BTR1..4 . . . . . . . . . . . . . . . . . 1583, 1645\nFSMC_BWTR1..4 . . . . . . . . . . . . . . . 1586, 1649\nFSMC_PCR2..4 . . . . . . . . . . . . . . . . . . . . . . 1596\nFSMC_PMEM2..4 . . . . . . . . . . . . . . . . . . . . 1598\nFSMC_SR2..4 . . . . . . . . . . . . . . . . . . . . . . . 1597\nG\nGPIOx_AFRH . . . . . . . . . . . . . . . . . . . . . . . . 289\nGPIOx_AFRL . . . . . . . . . . . . . . . . . . . . . . . . 288\nGPIOx_BSRR . . . . . . . . . . . . . . . . . . . . . . . . 287\nGPIOx_IDR . . . . . . . . . . . . . . . . . . . . . . . . . . 286\nGPIOx_LCKR . . . . . . . . . . . . . . . . . . . . . . . . 287\nGPIOx_MODER . . . . . . . . . . . . . . . . . . . . . . 284\nGPIOx_ODR . . . . . . . . . . . . . . . . . . . . . . . . . 286\nGPIOx_OSPEEDR . . . . . . . . . . . . . . . . . . . . 285\nGPIOx_OTYPER . . . . . . . . . . . . . . . . . . . . . . 284\nGPIOx_PUPDR . . . . . . . . . . . . . . . . . . . . . . . 285\n\n\n<>\n\nIndex\nRM0090\n1754/1751\nRM0090 Rev 21\nH\nHASH_CR . . . . . . . . . . . . . . . . . . . . . . .785, 788\nHASH_CSRx . . . . . . . . . . . . . . . . . . . . . . . . .797\nHASH_DIN . . . . . . . . . . . . . . . . . . . . . . . . . . .791\nHASH_HR0 . . . . . . . . . . . . . . . . . . . . . . . . . .793\nHASH_HR1 . . . . . . . . . . . . . . . . . . . . . . 793-794\nHASH_HR2 . . . . . . . . . . . . . . . . . . . . . . 793-794\nHASH_HR3 . . . . . . . . . . . . . . . . . . . . . . . . . .794\nHASH_HR4 . . . . . . . . . . . . . . . . . . . . . . . . . .794\nHASH_IMR . . . . . . . . . . . . . . . . . . . . . . . . . . .795\nHASH_SR . . . . . . . . . . . . . . . . . . . . . . . . . . .796\nHASH_STR . . . . . . . . . . . . . . . . . . . . . . . . . .792\nI\nI2C_CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . .873\nI2C_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .863\nI2C_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .865\nI2C_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .868\nI2C_OAR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .867\nI2C_OAR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .867\nI2C_SR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .868\nI2C_SR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .871\nI2C_TRISE . . . . . . . . . . . . . . . . . . . . . . . . . . .874\nIWDG_KR . . . . . . . . . . . . . . . . . . . . . . . . . . .713\nIWDG_PR . . . . . . . . . . . . . . . . . . . . . . . . . . .713\nIWDG_RLR . . . . . . . . . . . . . . . . . . . . . . . . . .714\nIWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . . .714\nO\nOTG_FS_CID . . . . . . . . . . . . . . . . . . . . . . . .1293\nOTG_FS_DAINT . . . . . . . . . . . . . . . . . . . . .1310\nOTG_FS_DAINTMSK . . . . . . . . . . . . . . . . .1311\nOTG_FS_DCFG . . . . . . . . . . . . . . . . . . . . . .1305\nOTG_FS_DCTL . . . . . . . . . . . . . . . . . . . . . .1306\nOTG_FS_DIEPCTL0 . . . . . . . . . . . . . . . . . .1312\nOTG_FS_DIEPCTLx . . . . . . . . . . . . . . . . . .1314\nOTG_FS_DIEPEMPMSK . . . . . . . . . . . . . . .1312\nOTG_FS_DIEPINTx . . . . . . . . . . . . . . . . . . .1321\nOTG_FS_DIEPMSK . . . . . . . . . . . . . . . . . . .1308\nOTG_FS_DIEPTSIZ0 . . . . . . . . . . . . . . . . . .1323\nOTG_FS_DIEPTSIZx . . . . . . . . . . . . . . . . . .1326\nOTG_FS_DIEPTXF0 . . . . . . . . . . . . . . . . . .1291\nOTG_FS_DIEPTXFx . . . . . . . . . . . . . . . . . .1294\nOTG_FS_DOEPCTL0 . . . . . . . . . . . . . . . . .1317\nOTG_FS_DOEPCTLx . . . . . . . . . . . . . . . . .1318\nOTG_FS_DOEPINTx . . . . . . . . . . . . . . . . . .1322\nOTG_FS_DOEPMSK . . . . . . . . . . . . . . . . . .1309\nOTG_FS_DOEPTSIZ0 . . . . . . . . . . . . . . . . .1325\nOTG_FS_DOEPTSIZx . . . . . . . . . . . . . . . . .1327\nOTG_FS_DSTS . . . . . . . . . . . . . . . . . . . . . .1307\nOTG_FS_DTXFSTSx . . . . . . . . . . . . . . . . . 1327\nOTG_FS_DVBUSDIS . . . . . . . . . . . . . . . . . 1311\nOTG_FS_DVBUSPULSE . . . . . . . . . . . . . . 1311\nOTG_FS_GAHBCFG . . . . . . . . . . . . . . . . . 1277\nOTG_FS_GCCFG . . . . . . . . . . . . . . . . . . . . 1292\nOTG_FS_GINTMSK . . . . . . . . . . . . . . . . . . 1286\nOTG_FS_GINTSTS . . . . . . . . . . . . . . . . . . 1282\nOTG_FS_GOTGCTL . . . . . . . . . . . . . . . . . . 1274\nOTG_FS_GOTGINT . . . . . . . . . . . . . . . . . . 1275\nOTG_FS_GRSTCTL . . . . . . . . . . . . . . . . . . 1280\nOTG_FS_GRXFSIZ . . . . . . . . . . . . . . . . . . 1290\nOTG_FS_GRXSTSP . . . . . . . . . . . . . . . . . . 1289\nOTG_FS_GRXSTSR . . . . . . . . . . . . . . . . . . 1289\nOTG_FS_GUSBCFG . . . . . . . . . . . . . . . . . 1278\nOTG_FS_HAINT . . . . . . . . . . . . . . . . . . . . . 1297\nOTG_FS_HAINTMSK . . . . . . . . . . . . . . . . . 1298\nOTG_FS_HCCHARx . . . . . . . . . . . . . . . . . . 1301\nOTG_FS_HCFG . . . . . . . . . . . . . . . . . . . . . 1295\nOTG_FS_HCINTMSKx . . . . . . . . . . . . . . . . 1303\nOTG_FS_HCINTx . . . . . . . . . . . . . . . . . . . . 1302\nOTG_FS_HCTSIZx . . . . . . . . . . . . . . . . . . . 1304\nOTG_FS_HFIR . . . . . . . . . . . . . . . . . . . . . . 1295\nOTG_FS_HFNUM . . . . . . . . . . . . . . . . . . . . 1296\nOTG_FS_HNPTXFSIZ . . . . . . . . . . . . . . . . 1291\nOTG_FS_HNPTXSTS . . . . . . . . . . . . . . . . . 1291\nOTG_FS_HPRT . . . . . . . . . . . . . . . . . . . . . 1298\nOTG_FS_HPTXFSIZ . . . . . . . . . . . . . . . . . . 1294\nOTG_FS_HPTXSTS . . . . . . . . . . . . . . . . . . 1296\nOTG_FS_PCGCCTL . . . . . . . . . . . . . . . . . . 1328\nOTG_HS_CID . . . . . . . . . . . . . . . . . . . . . . . 1432\nOTG_HS_DAINT . . . . . . . . . . . . . . . . . . . . . 1453\nOTG_HS_DAINTMSK . . . . . . . . . . . . . . . . . 1454\nOTG_HS_DCFG . . . . . . . . . . . . . . . . . . . . . 1446\nOTG_HS_DCTL . . . . . . . . . . . . . . . . . . . . . 1448\nOTG_HS_DEACHINT . . . . . . . . . . . . . . . . . 1457\nOTG_HS_DEACHINTMSK . . . . . . . . . . . . . 1458\nOTG_HS_DIEPCTLx . . . . . . . . . . . . . . . . . . 1460\nOTG_HS_DIEPDMAx . . . . . . . . . . . . . . . . . 1474\nOTG_HS_DIEPEACHMSK1 . . . . . . . . . . . . 1458\nOTG_HS_DIEPEMPMSK . . . . . . . . . . . . . . 1457\nOTG_HS_DIEPINTx . . . . . . . . . . . . . . . . . . 1467\nOTG_HS_DIEPMSK . . . . . . . . . . . . . . . . . . 1451\nOTG_HS_DIEPTSIZ0 . . . . . . . . . . . . . . . . . 1470\nOTG_HS_DIEPTSIZx . . . . . . . . . . . . . . . . . 1472\nOTG_HS_DIEPTXFx . . . . . . . . . . . . . . . . . . 1433\nOTG_HS_DOEPCTL0 . . . . . . . . . . . . . . . . . 1463\nOTG_HS_DOEPCTLx . . . . . . . . . . . . . . . . . 1464\nOTG_HS_DOEPDMAx . . . . . . . . . . . . . . . . 1474\nOTG_HS_DOEPEACHMSK1 . . . . . . . . . . . 1459\nOTG_HS_DOEPINTx . . . . . . . . . . . . . . . . . 1469\nOTG_HS_DOEPMSK . . . . . . . . . . . . . . . . . 1452\nOTG_HS_DOEPTSIZ0 . . . . . . . . . . . . . . . . 1471\n\n\n<>\n\nRM0090\nIndex\nRM0090 Rev 21\n1755/1751\nOTG_HS_DOEPTSIZx . . . . . . . . . . . . . . . . .1473\nOTG_HS_DSTS . . . . . . . . . . . . . . . . . . . . . .1450\nOTG_HS_DTHRCTL . . . . . . . . . . . . . . . . . .1456\nOTG_HS_DTXFSTSx . . . . . . . . . . . . . . . . .1473\nOTG_HS_DVBUSDIS . . . . . . . . . . . . . . . . .1454\nOTG_HS_DVBUSPULSE . . . . . . . . . . . . . .1455\nOTG_HS_GAHBCFG . . . . . . . . . . . . . . . . . .1414\nOTG_HS_GCCFG . . . . . . . . . . . . . . . . . . . .1431\nOTG_HS_GINTMSK . . . . . . . . . . . . . . . . . .1425\nOTG_HS_GINTSTS . . . . . . . . . . . . . . . . . . .1421\nOTG_HS_GNPTXFSIZ . . . . . . . . . . . . . . . .1430\nOTG_HS_GNPTXSTS . . . . . . . . . . . . . . . . .1430\nOTG_HS_GOTGCTL . . . . . . . . . . . . . . . . . .1411\nOTG_HS_GOTGINT . . . . . . . . . . . . . . . . . .1412\nOTG_HS_GRSTCTL . . . . . . . . . . . . . . . . . .1418\nOTG_HS_GRXFSIZ . . . . . . . . . . . . . . . . . . .1429\nOTG_HS_GRXSTSP . . . . . . . . . . . . . . . . . .1428\nOTG_HS_GRXSTSR . . . . . . . . . . . . . . . . . .1428\nOTG_HS_GUSBCFG . . . . . . . . . . . . . . . . . .1415\nOTG_HS_HAINT . . . . . . . . . . . . . . . . . . . . .1437\nOTG_HS_HAINTMSK . . . . . . . . . . . . . . . . .1437\nOTG_HS_HCCHARx . . . . . . . . . . . . . . . . . .1440\nOTG_HS_HCDMAx . . . . . . . . . . . . . . . . . . .1446\nOTG_HS_HCFG . . . . . . . . . . . . . . . . . . . . .1433\nOTG_HS_HCINTMSKx . . . . . . . . . . . . . . . .1444\nOTG_HS_HCINTx . . . . . . . . . . . . . . . . . . . .1443\nOTG_HS_HCSPLTx . . . . . . . . . . . . . . . . . .1442\nOTG_HS_HCTSIZx . . . . . . . . . . . . . . . . . . .1445\nOTG_HS_HFIR . . . . . . . . . . . . . . . . . . . . . .1435\nOTG_HS_HFNUM . . . . . . . . . . . . . . . . . . . .1435\nOTG_HS_HPRT . . . . . . . . . . . . . . . . . . . . . .1438\nOTG_HS_HPTXFSIZ . . . . . . . . . . . . . . . . . .1432\nOTG_HS_HPTXSTS . . . . . . . . . . . . . . . . . .1436\nOTG_HS_PCGCCTL . . . . . . . . . . . . . . . . . .1475\nOTG_HS_TX0FSIZ . . . . . . . . . . . . . . . . . . .1430\nP\nPWR_CR . . . . . . . . . . . . . . . . . . . . . . . .142, 146\nPWR_CSR . . . . . . . . . . . . . . . . . . . . . . .143, 149\nR\nRCC_AHB1ENR . . . . . . . . . . . . . . . . . .182, 244\nRCC_AHB1LPENR . . . . . . . . . . . . . . . .191, 252\nRCC_AHB1RSTR . . . . . . . . . . . . . . . . .172, 235\nRCC_AHB2ENR . . . . . . . . . . . . . . . . . .184, 246\nRCC_AHB2LPENR . . . . . . . . . . . . . . . .194, 254\nRCC_AHB2RSTR . . . . . . . . . . . . . . . . .175, 238\nRCC_AHB3ENR . . . . . . . . . . . . . . . . . .185, 247\nRCC_AHB3LPENR . . . . . . . . . . . . . . . .195, 255\nRCC_AHB3RSTR . . . . . . . . . . . . . . . . .176, 239\nRCC_APB1ENR . . . . . . . . . . . . . . . . . . .185, 247\nRCC_APB1LPENR . . . . . . . . . . . . . . . . 195, 256\nRCC_APB1RSTR . . . . . . . . . . . . . . . . . 176, 239\nRCC_APB2ENR . . . . . . . . . . . . . . . . . . 189, 250\nRCC_APB2LPENR . . . . . . . . . . . . . . . . 199, 259\nRCC_APB2RSTR . . . . . . . . . . . . . . . . . 180, 242\nRCC_BDCR . . . . . . . . . . . . . . . . . . . . . 201, 261\nRCC_CFGR . . . . . . . . . . . . . . . . . . . . . 167, 230\nRCC_CIR . . . . . . . . . . . . . . . . . . . . . . . 169, 232\nRCC_CR . . . . . . . . . . . . . . . . . . . . . . . . 163, 226\nRCC_CSR . . . . . . . . . . . . . . . . . . . . . . . 202, 262\nRCC_PLLCFGR . . . . . .165, 205, 208, 228, 265\nRCC_SSCGR . . . . . . . . . . . . . . . . . . . . 204, 264\nRNG_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772\nRNG_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773\nRNG_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772\nRTC_ALRMAR . . . . . . . . . . . . . . . . . . . . . . . 828\nRTC_ALRMBR . . . . . . . . . . . . . . . . . . . . . . . 829\nRTC_ALRMBSSR . . . . . . . . . . . . . . . . . . . . . 838\nRTC_BKxR . . . . . . . . . . . . . . . . . . . . . . . . . . 839\nRTC_CALIBR . . . . . . . . . . . . . . . . . . . . . . . . 827\nRTC_CALR . . . . . . . . . . . . . . . . . . . . . . . . . . 833\nRTC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821\nRTC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820\nRTC_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823\nRTC_PRER . . . . . . . . . . . . . . . . . . . . . . . . . . 826\nRTC_SHIFTR . . . . . . . . . . . . . . . . . . . . . . . . 831\nRTC_SSR . . . . . . . . . . . . . . . . . . . . . . . . . . . 830\nRTC_TR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819\nRTC_TSDR . . . . . . . . . . . . . . . . . . . . . . . . . . 832\nRTC_TSSSR . . . . . . . . . . . . . . . . . . . . . . . . . 833\nRTC_TSTR . . . . . . . . . . . . . . . . . . . . . . . . . . 831\nRTC_WPR . . . . . . . . . . . . . . . . . . . . . . . . . . . 830\nRTC_WUTR . . . . . . . . . . . . . . . . . . . . . . . . . 826\nS\nSDIO_CLKCR . . . . . . . . . . . . . . . . . . . . . . . 1064\nSDIO_DCOUNT . . . . . . . . . . . . . . . . . . . . . 1070\nSDIO_DCTRL . . . . . . . . . . . . . . . . . . . . . . . 1069\nSDIO_DLEN . . . . . . . . . . . . . . . . . . . . . . . . 1068\nSDIO_DTIMER . . . . . . . . . . . . . . . . . . . . . . 1067\nSDIO_FIFO . . . . . . . . . . . . . . . . . . . . . . . . . 1077\nSDIO_FIFOCNT . . . . . . . . . . . . . . . . . . . . . 1076\nSDIO_ICR . . . . . . . . . . . . . . . . . . . . . . . . . . 1072\nSDIO_MASK . . . . . . . . . . . . . . . . . . . . . . . . 1074\nSDIO_POWER . . . . . . . . . . . . . . . . . . . . . . 1063\nSDIO_RESPCMD . . . . . . . . . . . . . . . . . . . . 1066\nSDIO_RESPx . . . . . . . . . . . . . . . . . . . . . . . 1067\nSDIO_STA . . . . . . . . . . . . . . . . . . . . . . . . . . 1071\nSPI_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919\nSPI_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921\nSPI_CRCPR . . . . . . . . . . . . . . . . . . . . . . . . . 924\n\n\n<>\n\nIndex\nRM0090\n1756/1751\nRM0090 Rev 21\nSPI_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .923\nSPI_I2SCFGR . . . . . . . . . . . . . . . . . . . . . . . .925\nSPI_I2SPR . . . . . . . . . . . . . . . . . . . . . . . . . . .927\nSPI_RXCRCR . . . . . . . . . . . . . . . . . . . . . . . .924\nSPI_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .922\nSPI_TXCRCR . . . . . . . . . . . . . . . . . . . . . . . .925\nSYSCFG_EXTICR1 . . . . . . . . . . . . . . . .294, 300\nSYSCFG_EXTICR2 . . . . . . . . . . . . . . . .294, 301\nSYSCFG_EXTICR3 . . . . . . . . . . . . . . . .295, 301\nSYSCFG_EXTICR4 . . . . . . . . . . . . . . . .296, 302\nSYSCFG_MEMRMP . . . . . . . . . . . . . . .292, 297\nT\nTIM2_OR . . . . . . . . . . . . . . . . . . . . . . . . . . . .649\nTIM5_OR . . . . . . . . . . . . . . . . . . . . . . . . . . . .650\nTIMx_ARR . . . . . . . . . . . . . . 645, 685, 695, 709\nTIMx_BDTR . . . . . . . . . . . . . . . . . . . . . . . . . .586\nTIMx_CCER . . . . . . . . . . . . . 579, 643, 684, 694\nTIMx_CCMR1 . . . . . . . . . . . 575, 639, 681, 691\nTIMx_CCMR2 . . . . . . . . . . . . . . . . . . . .577, 642\nTIMx_CCR1 . . . . . . . . . . . . . 584, 646, 686, 696\nTIMx_CCR2 . . . . . . . . . . . . . . . . . 585, 646, 686\nTIMx_CCR3 . . . . . . . . . . . . . . . . . . . . . .585, 647\nTIMx_CCR4 . . . . . . . . . . . . . . . . . . . . . .586, 647\nTIMx_CNT . . . . . . . . . . 583, 645, 685, 695, 708\nTIMx_CR1 . . . . . . . . . . 564, 630, 675, 689, 705\nTIMx_CR2 . . . . . . . . . . . . . . . . . . 565, 632, 707\nTIMx_DCR . . . . . . . . . . . . . . . . . . . . . . .588, 648\nTIMx_DIER . . . . . . . . . . 570, 635, 677, 690, 707\nTIMx_DMAR . . . . . . . . . . . . . . . . . . . . . .589, 649\nTIMx_EGR . . . . . . . . . . 573, 638, 680, 691, 708\nTIMx_PSC . . . . . . . . . . 583, 645, 685, 695, 709\nTIMx_RCR . . . . . . . . . . . . . . . . . . . . . . . . . . .584\nTIMx_SMCR . . . . . . . . . . . . . . . . . 568, 633, 676\nTIMx_SR . . . . . . . . . . . 572, 636, 679, 690, 708\nU\nUSART_BRR . . . . . . . . . . . . . . . . . . . . . . . .1013\nUSART_CR1 . . . . . . . . . . . . . . . . . . . . . . . .1013\nUSART_CR2 . . . . . . . . . . . . . . . . . . . . . . . .1016\nUSART_CR3 . . . . . . . . . . . . . . . . . . . . . . . .1017\nUSART_DR . . . . . . . . . . . . . . . . . . . . . . . . .1013\nUSART_GTPR . . . . . . . . . . . . . . . . . . . . . . .1020\nUSART_SR . . . . . . . . . . . . . . . . . . . . . . . . .1010\nW\nWWDG_CFR . . . . . . . . . . . . . . . . . . . . . . . . .721\nWWDG_CR . . . . . . . . . . . . . . . . . . . . . . . . . .720\nWWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . .721\n\n\n<>\n\nRM0090 Rev 21\n1757/1757\nRM0090\n1757\nIMPORTANT NOTICE – READ CAREFULLY\nSTMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and \nimprovements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on \nST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order \nacknowledgment.\nPurchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or \nthe design of purchasers’ products.\nNo license, express or implied, to any intellectual property right is granted by ST herein.\nResale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.\nST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other \nproduct or service names are the property of their respective owners.\nInformation in this document supersedes and replaces information previously supplied in any prior versions of this document.\n© 2024 STMicroelectronics – All rights reserved\n", "document_metadata": { "format": "PDF 1.3", "title": "STM32F405/415, STM32F407/417, STM32F427/437 and STM32F429/439 advanced Arm®-based 32-bit MCUs - Reference manual", "author": "STMICROELECTRONICS", "subject": "This reference manual targets application developers. It provides complete information on how to use the STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx and STM32F43xxx microcontroller memory and peripherals.", "keywords": "", "creator": "C2 v20.4.0000 build 240 - c2_rendition_config : Techlit_Active", "producer": "Acrobat Elements 15.0 (Windows); modified using iText 2.1.7 by 1T3XT", "creationDate": "D:20240607121139Z", "modDate": "D:20240610092438+02'00'", "trapped": "", "encryption": null }, "page_count": 1757, "toc": [ [ 1, "1 Documentation conventions", 57 ], [ 2, "1.1 List of abbreviations for registers", 57 ], [ 2, "1.2 Glossary", 58 ], [ 2, "1.3 Peripheral availability", 58 ], [ 1, "2 Memory and bus architecture", 59 ], [ 2, "2.1 System architecture", 59 ], [ 3, "2.1.1 I-bus", 62 ], [ 3, "2.1.2 D-bus", 62 ], [ 3, "2.1.3 S-bus", 62 ], [ 3, "2.1.4 DMA memory bus", 63 ], [ 3, "2.1.5 DMA peripheral bus", 63 ], [ 3, "2.1.6 Ethernet DMA bus", 63 ], [ 3, "2.1.7 USB OTG HS DMA bus", 63 ], [ 3, "2.1.8 LCD-TFT controller DMA bus", 63 ], [ 3, "2.1.9 DMA2D bus", 63 ], [ 3, "2.1.10 BusMatrix", 63 ], [ 3, "2.1.11 AHB/APB bridges (APB)", 64 ], [ 2, "2.2 Memory organization", 64 ], [ 2, "2.3 Memory map", 64 ], [ 3, "2.3.1 Embedded SRAM", 68 ], [ 3, "2.3.2 Flash memory overview", 68 ], [ 3, "2.3.3 Bit banding", 68 ], [ 4, "Example", 69 ], [ 2, "2.4 Boot configuration", 69 ], [ 3, "Embedded bootloader", 70 ], [ 3, "Physical remap in STM32F405xx/07xx and STM32F415xx/17xx", 70 ], [ 3, "Physical remap in STM32F42xxx and STM32F43xxx", 71 ], [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.1 Introduction", 73 ], [ 2, "3.2 Main features", 73 ], [ 2, "3.3 Embedded flash memory in STM32F405xx/07xx and STM32F415xx/17xx", 74 ], [ 2, "3.4 Embedded flash memory in STM32F42xxx and STM32F43xxx", 76 ], [ 2, "3.5 Read interface", 80 ], [ 3, "3.5.1 Relation between CPU clock frequency and flash memory read time", 80 ], [ 4, "Increasing the CPU frequency", 82 ], [ 4, "Decreasing the CPU frequency", 82 ], [ 3, "3.5.2 Adaptive real-time memory accelerator (ART Accelerator™)", 82 ], [ 4, "Instruction prefetch", 82 ], [ 4, "Instruction cache memory", 84 ], [ 4, "Data management", 84 ], [ 2, "3.6 Erase and program operations", 84 ], [ 3, "3.6.1 Unlocking the Flash control register", 84 ], [ 3, "3.6.2 Program/erase parallelism", 85 ], [ 3, "3.6.3 Erase", 85 ], [ 4, "Sector Erase", 85 ], [ 4, "Bank erase in STM32F42xxx and STM32F43xxx devices", 86 ], [ 4, "Mass Erase", 86 ], [ 3, "3.6.4 Programming", 86 ], [ 4, "Standard programming", 86 ], [ 4, "Programming errors", 87 ], [ 4, "Programming and caches", 87 ], [ 3, "3.6.5 Read-while-write (RWW)", 87 ], [ 4, "Read from bank 1 while erasing bank 2", 87 ], [ 4, "Read from bank 1 while programming bank 2", 87 ], [ 3, "3.6.6 Interrupts", 88 ], [ 2, "3.7 Option bytes", 88 ], [ 3, "3.7.1 Description of user option bytes", 88 ], [ 3, "3.7.2 Programming user option bytes", 92 ], [ 4, "Modifying user option bytes on STM32F405xx/07xx and STM32F415xx/17xx", 92 ], [ 4, "Modifying user option bytes on STM32F42xxx and STM32F43xxx", 92 ], [ 3, "3.7.3 Read protection (RDP)", 93 ], [ 3, "3.7.4 Write protections", 95 ], [ 4, "Write protection error flag", 96 ], [ 3, "3.7.5 Proprietary code readout protection (PCROP)", 96 ], [ 2, "3.8 One-time programmable bytes", 98 ], [ 2, "3.9 Flash interface registers", 99 ], [ 3, "3.9.1 Flash access control register (FLASH_ACR) for STM32F405xx/07xx and STM32F415xx/17xx", 99 ], [ 3, "3.9.2 Flash access control register (FLASH_ACR) for STM32F42xxx and STM32F43xxx", 100 ], [ 3, "3.9.3 Flash key register (FLASH_KEYR)", 101 ], [ 3, "3.9.4 Flash option key register (FLASH_OPTKEYR)", 101 ], [ 3, "3.9.5 Flash status register (FLASH_SR) for STM32F405xx/07xx and STM32F415xx/17xx", 102 ], [ 3, "3.9.6 Flash status register (FLASH_SR) for STM32F42xxx and STM32F43xxx", 103 ], [ 3, "3.9.7 Flash control register (FLASH_CR) for STM32F405xx/07xx and STM32F415xx/17xx", 104 ], [ 3, "3.9.8 Flash control register (FLASH_CR) for STM32F42xxx and STM32F43xxx", 106 ], [ 3, "3.9.9 Flash option control register (FLASH_OPTCR) for STM32F405xx/07xx and STM32F415xx/17xx", 107 ], [ 3, "3.9.10 Flash option control register (FLASH_OPTCR) for STM32F42xxx and STM32F43xxx", 109 ], [ 3, "3.9.11 Flash option control register (FLASH_OPTCR1) for STM32F42xxx and STM32F43xxx", 111 ], [ 3, "3.9.12 Flash interface register map", 112 ], [ 1, "4 CRC calculation unit", 114 ], [ 2, "4.1 CRC introduction", 114 ], [ 2, "4.2 CRC main features", 114 ], [ 2, "4.3 CRC functional description", 115 ], [ 2, "4.4 CRC registers", 115 ], [ 3, "4.4.1 Data register (CRC_DR)", 115 ], [ 3, "4.4.2 Independent data register (CRC_IDR)", 115 ], [ 3, "4.4.3 Control register (CRC_CR)", 116 ], [ 3, "4.4.4 CRC register map", 116 ], [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.1 Power supplies", 117 ], [ 3, "5.1.1 Independent A/D converter supply and reference voltage", 118 ], [ 3, "5.1.2 Battery backup domain", 119 ], [ 4, "Backup domain description", 119 ], [ 4, "Backup domain access", 120 ], [ 4, "RTC and RTC backup registers", 120 ], [ 4, "Backup SRAM", 120 ], [ 3, "5.1.3 Voltage regulator for STM32F405xx/07xx and STM32F415xx/17xx", 121 ], [ 3, "5.1.4 Voltage regulator for STM32F42xxx and STM32F43xxx", 122 ], [ 4, "Entering Over-drive mode", 124 ], [ 4, "Exiting from Over-drive mode", 124 ], [ 2, "5.2 Power supply supervisor", 125 ], [ 3, "5.2.1 Power-on reset (POR)/power-down reset (PDR)", 125 ], [ 3, "5.2.2 Brownout reset (BOR)", 126 ], [ 3, "5.2.3 Programmable voltage detector (PVD)", 126 ], [ 2, "5.3 Low-power modes", 127 ], [ 3, "Entering low-power mode", 128 ], [ 3, "Exiting low-power mode", 128 ], [ 3, "5.3.1 Slowing down system clocks", 129 ], [ 3, "5.3.2 Peripheral clock gating", 129 ], [ 3, "5.3.3 Sleep mode", 130 ], [ 4, "Entering Sleep mode", 130 ], [ 4, "Exiting Sleep mode", 130 ], [ 3, "5.3.4 Stop mode (STM32F405xx/07xx and STM32F415xx/17xx)", 131 ], [ 4, "Entering Stop mode (for STM32F405xx/07xx and STM32F415xx/17xx)", 132 ], [ 4, "Exiting Stop mode (for STM32F405xx/07xx and STM32F415xx/17xx)", 133 ], [ 3, "5.3.5 Stop mode (STM32F42xxx and STM32F43xxx)", 134 ], [ 4, "Entering Stop mode (STM32F42xxx and STM32F43xxx)", 135 ], [ 4, "Exiting Stop mode (STM32F42xxx and STM32F43xxx)", 136 ], [ 3, "5.3.6 Standby mode", 137 ], [ 4, "Entering Standby mode", 138 ], [ 4, "Exiting Standby mode", 138 ], [ 4, "I/O states in Standby mode", 139 ], [ 4, "Debug mode", 139 ], [ 3, "5.3.7 Programming the RTC alternate functions to wake up the device from the Stop and Standby modes", 139 ], [ 4, "RTC alternate functions to wake up the device from the Stop mode", 140 ], [ 4, "RTC alternate functions to wake up the device from the Standby mode", 140 ], [ 4, "Safe RTC alternate function wake-up flag clearing sequence", 140 ], [ 2, "5.4 Power control registers (STM32F405xx/07xx and STM32F415xx/17xx)", 142 ], [ 3, "5.4.1 PWR power control register (PWR_CR) for STM32F405xx/07xx and STM32F415xx/17xx", 142 ], [ 3, "5.4.2 PWR power control/status register (PWR_CSR) for STM32F405xx/07xx and STM32F415xx/17xx", 143 ], [ 2, "5.5 Power control registers (STM32F42xxx and STM32F43xxx)", 146 ], [ 3, "5.5.1 PWR power control register (PWR_CR) for STM32F42xxx and STM32F43xxx", 146 ], [ 3, "5.5.2 PWR power control/status register (PWR_CSR) for STM32F42xxx and STM32F43xxx", 149 ], [ 2, "5.6 PWR register map", 151 ], [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.1 Reset", 152 ], [ 3, "6.1.1 System reset", 152 ], [ 4, "Software reset", 152 ], [ 4, "Low-power management reset", 152 ], [ 3, "6.1.2 Power reset", 152 ], [ 3, "6.1.3 Backup domain reset", 153 ], [ 2, "6.2 Clocks", 153 ], [ 3, "6.2.1 HSE clock", 156 ], [ 4, "External source (HSE bypass)", 156 ], [ 4, "External crystal/ceramic resonator (HSE crystal)", 156 ], [ 3, "6.2.2 HSI clock", 157 ], [ 4, "Calibration", 157 ], [ 3, "6.2.3 PLL configuration", 157 ], [ 3, "6.2.4 LSE clock", 158 ], [ 4, "External source (LSE bypass)", 158 ], [ 3, "6.2.5 LSI clock", 158 ], [ 3, "6.2.6 System clock (SYSCLK) selection", 158 ], [ 3, "6.2.7 Clock security system (CSS)", 159 ], [ 3, "6.2.8 RTC/AWU clock", 159 ], [ 3, "6.2.9 Watchdog clock", 160 ], [ 3, "6.2.10 Clock-out capability", 160 ], [ 3, "6.2.11 Internal/external clock measurement using TIM5/TIM11", 160 ], [ 4, "Internal/external clock measurement using TIM5 channel4", 160 ], [ 4, "Internal/external clock measurement using TIM11 channel1", 161 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.1 RCC clock control register (RCC_CR)", 163 ], [ 3, "6.3.2 RCC PLL configuration register (RCC_PLLCFGR)", 165 ], [ 3, "6.3.3 RCC clock configuration register (RCC_CFGR)", 167 ], [ 3, "6.3.4 RCC clock interrupt register (RCC_CIR)", 169 ], [ 3, "6.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)", 172 ], [ 3, "6.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR)", 175 ], [ 3, "6.3.7 RCC AHB3 peripheral reset register (RCC_AHB3RSTR)", 176 ], [ 3, "6.3.8 RCC APB1 peripheral reset register (RCC_APB1RSTR)", 176 ], [ 3, "6.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR)", 180 ], [ 3, "6.3.10 RCC AHB1 peripheral clock register (RCC_AHB1ENR)", 182 ], [ 3, "6.3.11 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)", 184 ], [ 3, "6.3.12 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)", 185 ], [ 3, "6.3.13 RCC APB1 peripheral clock enable register (RCC_APB1ENR)", 185 ], [ 3, "6.3.14 RCC APB2 peripheral clock enable register (RCC_APB2ENR)", 189 ], [ 3, "6.3.15 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR)", 191 ], [ 3, "6.3.16 RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR)", 194 ], [ 3, "6.3.17 RCC AHB3 peripheral clock enable in low power mode register (RCC_AHB3LPENR)", 195 ], [ 3, "6.3.18 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR)", 195 ], [ 3, "6.3.19 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR)", 199 ], [ 3, "6.3.20 RCC Backup domain control register (RCC_BDCR)", 201 ], [ 3, "6.3.21 RCC clock control & status register (RCC_CSR)", 202 ], [ 3, "6.3.22 RCC spread spectrum clock generation register (RCC_SSCGR)", 204 ], [ 3, "6.3.23 RCC PLLI2S configuration register (RCC_PLLI2SCFGR)", 205 ], [ 3, "6.3.24 RCC PLL configuration register (RCC_PLLSAICFGR)", 208 ], [ 3, "6.3.25 RCC Dedicated Clock Configuration Register (RCC_DCKCFGR)", 209 ], [ 3, "6.3.26 RCC register map", 212 ], [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.1 Reset", 215 ], [ 3, "7.1.1 System reset", 215 ], [ 4, "Software reset", 215 ], [ 4, "Low-power management reset", 216 ], [ 3, "7.1.2 Power reset", 216 ], [ 3, "7.1.3 Backup domain reset", 216 ], [ 2, "7.2 Clocks", 217 ], [ 3, "7.2.1 HSE clock", 219 ], [ 4, "External source (HSE bypass)", 220 ], [ 4, "External crystal/ceramic resonator (HSE crystal)", 220 ], [ 3, "7.2.2 HSI clock", 220 ], [ 4, "Calibration", 221 ], [ 3, "7.2.3 PLL configuration", 221 ], [ 3, "7.2.4 LSE clock", 221 ], [ 4, "External source (LSE bypass)", 222 ], [ 3, "7.2.5 LSI clock", 222 ], [ 3, "7.2.6 System clock (SYSCLK) selection", 222 ], [ 3, "7.2.7 Clock security system (CSS)", 222 ], [ 3, "7.2.8 RTC/AWU clock", 223 ], [ 3, "7.2.9 Watchdog clock", 223 ], [ 3, "7.2.10 Clock-out capability", 224 ], [ 3, "7.2.11 Internal/external clock measurement using TIM5/TIM11", 224 ], [ 4, "Internal/external clock measurement using TIM5 channel4", 224 ], [ 4, "Internal/external clock measurement using TIM11 channel1", 225 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.1 RCC clock control register (RCC_CR)", 226 ], [ 3, "7.3.2 RCC PLL configuration register (RCC_PLLCFGR)", 228 ], [ 3, "7.3.3 RCC clock configuration register (RCC_CFGR)", 230 ], [ 3, "7.3.4 RCC clock interrupt register (RCC_CIR)", 232 ], [ 3, "7.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)", 235 ], [ 3, "7.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR)", 238 ], [ 3, "7.3.7 RCC AHB3 peripheral reset register (RCC_AHB3RSTR)", 239 ], [ 3, "7.3.8 RCC APB1 peripheral reset register (RCC_APB1RSTR)", 239 ], [ 3, "7.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR)", 242 ], [ 3, "7.3.10 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)", 244 ], [ 3, "7.3.11 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)", 246 ], [ 3, "7.3.12 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)", 247 ], [ 3, "7.3.13 RCC APB1 peripheral clock enable register (RCC_APB1ENR)", 247 ], [ 3, "7.3.14 RCC APB2 peripheral clock enable register (RCC_APB2ENR)", 250 ], [ 3, "7.3.15 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR)", 252 ], [ 3, "7.3.16 RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR)", 254 ], [ 3, "7.3.17 RCC AHB3 peripheral clock enable in low power mode register (RCC_AHB3LPENR)", 255 ], [ 3, "7.3.18 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR)", 256 ], [ 3, "7.3.19 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR)", 259 ], [ 3, "7.3.20 RCC Backup domain control register (RCC_BDCR)", 261 ], [ 3, "7.3.21 RCC clock control & status register (RCC_CSR)", 262 ], [ 3, "7.3.22 RCC spread spectrum clock generation register (RCC_SSCGR)", 264 ], [ 3, "7.3.23 RCC PLLI2S configuration register (RCC_PLLI2SCFGR)", 265 ], [ 3, "7.3.24 RCC register map", 267 ], [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.1 GPIO introduction", 270 ], [ 2, "8.2 GPIO main features", 270 ], [ 2, "8.3 GPIO functional description", 270 ], [ 3, "8.3.1 General-purpose I/O (GPIO)", 272 ], [ 3, "8.3.2 I/O pin multiplexer and mapping", 273 ], [ 3, "8.3.3 I/O port control registers", 277 ], [ 3, "8.3.4 I/O port data registers", 277 ], [ 3, "8.3.5 I/O data bitwise handling", 277 ], [ 3, "8.3.6 GPIO locking mechanism", 277 ], [ 3, "8.3.7 I/O alternate function input/output", 278 ], [ 3, "8.3.8 External interrupt/wake-up lines", 278 ], [ 3, "8.3.9 Input configuration", 278 ], [ 3, "8.3.10 Output configuration", 279 ], [ 3, "8.3.11 Alternate function configuration", 280 ], [ 3, "8.3.12 Analog configuration", 281 ], [ 3, "8.3.13 Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins", 281 ], [ 3, "8.3.14 Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins", 281 ], [ 3, "8.3.15 Selection of RTC_AF1 and RTC_AF2 alternate functions", 282 ], [ 2, "8.4 GPIO registers", 284 ], [ 3, "8.4.1 GPIO port mode register (GPIOx_MODER) (x = A..I/J/K)", 284 ], [ 3, "8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..I/J/K)", 284 ], [ 3, "8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..I/J/K)", 285 ], [ 3, "8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..I/J/K)", 285 ], [ 3, "8.4.5 GPIO port input data register (GPIOx_IDR) (x = A..I/J/K)", 286 ], [ 3, "8.4.6 GPIO port output data register (GPIOx_ODR) (x = A..I/J/K)", 286 ], [ 3, "8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..I/J/K)", 287 ], [ 3, "8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..I/J/K)", 287 ], [ 3, "8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..I/J/K)", 288 ], [ 3, "8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..I/J)", 289 ], [ 3, "8.4.11 GPIO register map", 290 ], [ 1, "9 System configuration controller (SYSCFG)", 292 ], [ 2, "9.1 I/O compensation cell", 292 ], [ 2, "9.2 SYSCFG registers for STM32F405xx/07xx and STM32F415xx/17xx", 292 ], [ 3, "9.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP)", 292 ], [ 3, "9.2.2 SYSCFG peripheral mode configuration register (SYSCFG_PMC)", 293 ], [ 3, "9.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)", 294 ], [ 3, "9.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)", 294 ], [ 3, "9.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)", 295 ], [ 3, "9.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)", 296 ], [ 3, "9.2.7 Compensation cell control register (SYSCFG_CMPCR)", 296 ], [ 3, "9.2.8 SYSCFG register maps for STM32F405xx/07xx and STM32F415xx/17xx", 297 ], [ 2, "9.3 SYSCFG registers for STM32F42xxx and STM32F43xxx", 297 ], [ 3, "9.3.1 SYSCFG memory remap register (SYSCFG_MEMRMP)", 297 ], [ 3, "9.3.2 SYSCFG peripheral mode configuration register (SYSCFG_PMC)", 299 ], [ 3, "9.3.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)", 300 ], [ 3, "9.3.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)", 301 ], [ 3, "9.3.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)", 301 ], [ 3, "9.3.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)", 302 ], [ 3, "9.3.7 Compensation cell control register (SYSCFG_CMPCR)", 303 ], [ 3, "9.3.8 SYSCFG register maps for STM32F42xxx and STM32F43xxx", 304 ], [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.1 DMA introduction", 305 ], [ 2, "10.2 DMA main features", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.1 General description", 307 ], [ 3, "10.3.2 DMA transactions", 309 ], [ 3, "10.3.3 Channel selection", 310 ], [ 3, "10.3.4 Arbiter", 311 ], [ 3, "10.3.5 DMA streams", 312 ], [ 3, "10.3.6 Source, destination and transfer modes", 312 ], [ 4, "Peripheral-to-memory mode", 312 ], [ 4, "Memory-to-peripheral mode", 313 ], [ 4, "Memory-to-memory mode", 314 ], [ 3, "10.3.7 Pointer incrementation", 315 ], [ 3, "10.3.8 Circular mode", 316 ], [ 3, "10.3.9 Double buffer mode", 316 ], [ 3, "10.3.10 Programmable data width, packing/unpacking, endianess", 317 ], [ 3, "10.3.11 Single and burst transfers", 319 ], [ 3, "10.3.12 FIFO", 320 ], [ 4, "FIFO structure", 320 ], [ 4, "FIFO threshold and burst configuration", 321 ], [ 4, "FIFO flush", 322 ], [ 4, "Direct mode", 322 ], [ 3, "10.3.13 DMA transfer completion", 322 ], [ 3, "10.3.14 DMA transfer suspension", 323 ], [ 3, "10.3.15 Flow controller", 324 ], [ 3, "10.3.16 Summary of the possible DMA configurations", 325 ], [ 3, "10.3.17 Stream configuration procedure", 325 ], [ 3, "10.3.18 Error management", 326 ], [ 2, "10.4 DMA interrupts", 327 ], [ 2, "10.5 DMA registers", 328 ], [ 3, "10.5.1 DMA low interrupt status register (DMA_LISR)", 328 ], [ 3, "10.5.2 DMA high interrupt status register (DMA_HISR)", 329 ], [ 3, "10.5.3 DMA low interrupt flag clear register (DMA_LIFCR)", 330 ], [ 3, "10.5.4 DMA high interrupt flag clear register (DMA_HIFCR)", 330 ], [ 3, "10.5.5 DMA stream x configuration register (DMA_SxCR) (x = 0..7)", 331 ], [ 3, "10.5.6 DMA stream x number of data register (DMA_SxNDTR) (x = 0..7)", 334 ], [ 3, "10.5.7 DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7)", 335 ], [ 3, "10.5.8 DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7)", 335 ], [ 3, "10.5.9 DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7)", 335 ], [ 3, "10.5.10 DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7)", 336 ], [ 3, "10.5.11 DMA register map", 338 ], [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.1 DMA2D introduction", 342 ], [ 2, "11.2 DMA2D main features", 343 ], [ 2, "11.3 DMA2D functional description", 343 ], [ 3, "11.3.1 General description", 343 ], [ 3, "11.3.2 DMA2D control", 344 ], [ 3, "11.3.3 DMA2D foreground and background FIFOs", 344 ], [ 3, "11.3.4 DMA2D foreground and background pixel format converter (PFC)", 345 ], [ 3, "11.3.5 DMA2D foreground and background CLUT interface", 347 ], [ 3, "11.3.6 DMA2D blender", 348 ], [ 3, "11.3.7 DMA2D output PFC", 348 ], [ 3, "11.3.8 DMA2D output FIFO", 349 ], [ 3, "11.3.9 DMA2D AHB master port timer", 349 ], [ 3, "11.3.10 DMA2D transactions", 350 ], [ 3, "11.3.11 DMA2D configuration", 350 ], [ 4, "Register-to-memory", 350 ], [ 4, "Memory-to-memory", 350 ], [ 4, "Memory-to-memory with PFC", 351 ], [ 4, "Memory-to-memory with PFC and blending", 352 ], [ 4, "Configuration error detection", 352 ], [ 3, "11.3.12 DMA2D transfer control (start, suspend, abort and completion)", 353 ], [ 3, "11.3.13 Watermark", 354 ], [ 3, "11.3.14 Error management", 354 ], [ 3, "11.3.15 AHB dead time", 354 ], [ 2, "11.4 DMA2D interrupts", 354 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.1 DMA2D control register (DMA2D_CR)", 355 ], [ 3, "11.5.2 DMA2D Interrupt Status Register (DMA2D_ISR)", 357 ], [ 3, "11.5.3 DMA2D interrupt flag clear register (DMA2D_IFCR)", 358 ], [ 3, "11.5.4 DMA2D foreground memory address register (DMA2D_FGMAR)", 359 ], [ 3, "11.5.5 DMA2D foreground offset register (DMA2D_FGOR)", 359 ], [ 3, "11.5.6 DMA2D background memory address register (DMA2D_BGMAR)", 360 ], [ 3, "11.5.7 DMA2D background offset register (DMA2D_BGOR)", 360 ], [ 3, "11.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR)", 361 ], [ 3, "11.5.9 DMA2D foreground color register (DMA2D_FGCOLR)", 363 ], [ 3, "11.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR)", 364 ], [ 3, "11.5.11 DMA2D background color register (DMA2D_BGCOLR)", 366 ], [ 3, "11.5.12 DMA2D foreground CLUT memory address register (DMA2D_FGCMAR)", 366 ], [ 3, "11.5.13 DMA2D background CLUT memory address register (DMA2D_BGCMAR)", 367 ], [ 3, "11.5.14 DMA2D output PFC control register (DMA2D_OPFCCR)", 367 ], [ 3, "11.5.15 DMA2D output color register (DMA2D_OCOLR)", 368 ], [ 3, "11.5.16 DMA2D output memory address register (DMA2D_OMAR)", 369 ], [ 3, "11.5.17 DMA2D output offset register (DMA2D_OOR)", 370 ], [ 3, "11.5.18 DMA2D number of line register (DMA2D_NLR)", 370 ], [ 3, "11.5.19 DMA2D line watermark register (DMA2D_LWR)", 371 ], [ 3, "11.5.20 DMA2D AHB master timer configuration register (DMA2D_AMTCR)", 371 ], [ 3, "11.5.21 DMA2D register map", 372 ], [ 1, "12 Interrupts and events", 374 ], [ 2, "12.1 Nested vectored interrupt controller (NVIC)", 374 ], [ 3, "12.1.1 NVIC features", 374 ], [ 3, "12.1.2 SysTick calibration value register", 374 ], [ 3, "12.1.3 Interrupt and exception vectors", 374 ], [ 2, "12.2 External interrupt/event controller (EXTI)", 374 ], [ 3, "12.2.1 EXTI main features", 382 ], [ 3, "12.2.2 EXTI block diagram", 383 ], [ 3, "12.2.3 Wake-up event management", 383 ], [ 3, "12.2.4 Functional description", 383 ], [ 4, "Hardware interrupt selection", 384 ], [ 4, "Hardware event selection", 384 ], [ 4, "Software interrupt/event selection", 384 ], [ 3, "12.2.5 External interrupt/event line mapping", 385 ], [ 2, "12.3 EXTI registers", 387 ], [ 3, "12.3.1 Interrupt mask register (EXTI_IMR)", 387 ], [ 3, "12.3.2 Event mask register (EXTI_EMR)", 387 ], [ 3, "12.3.3 Rising trigger selection register (EXTI_RTSR)", 388 ], [ 3, "12.3.4 Falling trigger selection register (EXTI_FTSR)", 388 ], [ 3, "12.3.5 Software interrupt event register (EXTI_SWIER)", 389 ], [ 3, "12.3.6 Pending register (EXTI_PR)", 389 ], [ 3, "12.3.7 EXTI register map", 390 ], [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.1 ADC introduction", 391 ], [ 2, "13.2 ADC main features", 391 ], [ 2, "13.3 ADC functional description", 392 ], [ 3, "13.3.1 ADC on-off control", 393 ], [ 3, "13.3.2 ADC clock", 393 ], [ 3, "13.3.3 Channel selection", 393 ], [ 4, "Temperature sensor, VREFINT and VBAT internal channels", 394 ], [ 3, "13.3.4 Single conversion mode", 394 ], [ 3, "13.3.5 Continuous conversion mode", 395 ], [ 3, "13.3.6 Timing diagram", 395 ], [ 3, "13.3.7 Analog watchdog", 395 ], [ 3, "13.3.8 Scan mode", 396 ], [ 3, "13.3.9 Injected channel management", 397 ], [ 4, "Triggered injection", 397 ], [ 4, "Auto-injection", 397 ], [ 3, "13.3.10 Discontinuous mode", 398 ], [ 4, "Regular group", 398 ], [ 4, "Injected group", 398 ], [ 2, "13.4 Data alignment", 399 ], [ 2, "13.5 Channel-wise programmable sampling time", 400 ], [ 2, "13.6 Conversion on external trigger and trigger polarity", 400 ], [ 2, "13.7 Fast conversion mode", 402 ], [ 2, "13.8 Data management", 403 ], [ 3, "13.8.1 Using the DMA", 403 ], [ 3, "13.8.2 Managing a sequence of conversions without using the DMA", 403 ], [ 3, "13.8.3 Conversions without DMA and without overrun detection", 404 ], [ 2, "13.9 Multi ADC mode", 404 ], [ 3, "13.9.1 Injected simultaneous mode", 407 ], [ 4, "Dual ADC mode", 408 ], [ 4, "Triple ADC mode", 408 ], [ 3, "13.9.2 Regular simultaneous mode", 408 ], [ 4, "Dual ADC mode", 409 ], [ 4, "Triple ADC mode", 409 ], [ 3, "13.9.3 Interleaved mode", 410 ], [ 4, "Dual ADC mode", 410 ], [ 4, "Triple ADC mode", 410 ], [ 3, "13.9.4 Alternate trigger mode", 411 ], [ 4, "Dual ADC mode", 412 ], [ 4, "Triple ADC mode", 413 ], [ 3, "13.9.5 Combined regular/injected simultaneous mode", 413 ], [ 3, "13.9.6 Combined regular simultaneous + alternate trigger mode", 414 ], [ 2, "13.10 Temperature sensor", 415 ], [ 3, "Main features", 415 ], [ 3, "Reading the temperature", 416 ], [ 2, "13.11 Battery charge monitoring", 417 ], [ 2, "13.12 ADC interrupts", 417 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.1 ADC status register (ADC_SR)", 418 ], [ 3, "13.13.2 ADC control register 1 (ADC_CR1)", 419 ], [ 3, "13.13.3 ADC control register 2 (ADC_CR2)", 421 ], [ 3, "13.13.4 ADC sample time register 1 (ADC_SMPR1)", 423 ], [ 3, "13.13.5 ADC sample time register 2 (ADC_SMPR2)", 423 ], [ 3, "13.13.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)", 424 ], [ 3, "13.13.7 ADC watchdog higher threshold register (ADC_HTR)", 424 ], [ 3, "13.13.8 ADC watchdog lower threshold register (ADC_LTR)", 425 ], [ 3, "13.13.9 ADC regular sequence register 1 (ADC_SQR1)", 425 ], [ 3, "13.13.10 ADC regular sequence register 2 (ADC_SQR2)", 426 ], [ 3, "13.13.11 ADC regular sequence register 3 (ADC_SQR3)", 426 ], [ 3, "13.13.12 ADC injected sequence register (ADC_JSQR)", 427 ], [ 3, "13.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4)", 428 ], [ 3, "13.13.14 ADC regular data register (ADC_DR)", 428 ], [ 3, "13.13.15 ADC Common status register (ADC_CSR)", 429 ], [ 3, "13.13.16 ADC common control register (ADC_CCR)", 430 ], [ 3, "13.13.17 ADC common regular data register for dual and triple modes (ADC_CDR)", 433 ], [ 3, "13.13.18 ADC register map", 433 ], [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.1 DAC introduction", 436 ], [ 2, "14.2 DAC main features", 436 ], [ 2, "14.3 DAC functional description", 438 ], [ 3, "14.3.1 DAC channel enable", 438 ], [ 3, "14.3.2 DAC output buffer enable", 438 ], [ 3, "14.3.3 DAC data format", 438 ], [ 3, "14.3.4 DAC conversion", 439 ], [ 3, "14.3.5 DAC output voltage", 440 ], [ 3, "14.3.6 DAC trigger selection", 440 ], [ 3, "14.3.7 DMA request", 441 ], [ 4, "DMA underrun", 441 ], [ 3, "14.3.8 Noise generation", 441 ], [ 3, "14.3.9 Triangle-wave generation", 442 ], [ 2, "14.4 Dual DAC channel conversion", 443 ], [ 3, "14.4.1 Independent trigger without wave generation", 444 ], [ 3, "14.4.2 Independent trigger with single LFSR generation", 444 ], [ 3, "14.4.3 Independent trigger with different LFSR generation", 444 ], [ 3, "14.4.4 Independent trigger with single triangle generation", 445 ], [ 3, "14.4.5 Independent trigger with different triangle generation", 445 ], [ 3, "14.4.6 Simultaneous software start", 445 ], [ 3, "14.4.7 Simultaneous trigger without wave generation", 446 ], [ 3, "14.4.8 Simultaneous trigger with single LFSR generation", 446 ], [ 3, "14.4.9 Simultaneous trigger with different LFSR generation", 446 ], [ 3, "14.4.10 Simultaneous trigger with single triangle generation", 447 ], [ 3, "14.4.11 Simultaneous trigger with different triangle generation", 447 ], [ 2, "14.5 DAC registers", 448 ], [ 3, "14.5.1 DAC control register (DAC_CR)", 448 ], [ 3, "14.5.2 DAC software trigger register (DAC_SWTRIGR)", 451 ], [ 3, "14.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1)", 451 ], [ 3, "14.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)", 452 ], [ 3, "14.5.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)", 452 ], [ 3, "14.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)", 453 ], [ 3, "14.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)", 453 ], [ 3, "14.5.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)", 453 ], [ 3, "14.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD)", 454 ], [ 3, "14.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD)", 454 ], [ 3, "14.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD)", 455 ], [ 3, "14.5.12 DAC channel1 data output register (DAC_DOR1)", 455 ], [ 3, "14.5.13 DAC channel2 data output register (DAC_DOR2)", 455 ], [ 3, "14.5.14 DAC status register (DAC_SR)", 456 ], [ 3, "14.5.15 DAC register map", 456 ], [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.1 DCMI introduction", 458 ], [ 2, "15.2 DCMI main features", 458 ], [ 2, "15.3 DCMI pins", 458 ], [ 2, "15.4 DCMI clocks", 458 ], [ 2, "15.5 DCMI functional overview", 459 ], [ 3, "15.5.1 DMA interface", 460 ], [ 3, "15.5.2 DCMI physical interface", 460 ], [ 4, "8-bit data", 461 ], [ 4, "10-bit data", 461 ], [ 4, "12-bit data", 462 ], [ 4, "14-bit data", 462 ], [ 3, "15.5.3 Synchronization", 462 ], [ 4, "Hardware synchronization mode", 464 ], [ 4, "Embedded data synchronization mode", 464 ], [ 4, "Example", 465 ], [ 3, "15.5.4 Capture modes", 465 ], [ 4, "Snapshot mode (single frame)", 465 ], [ 4, "Continuous grab mode", 466 ], [ 3, "15.5.5 Crop feature", 466 ], [ 3, "15.5.6 JPEG format", 468 ], [ 3, "15.5.7 FIFO", 468 ], [ 2, "15.6 Data format description", 468 ], [ 3, "15.6.1 Data formats", 468 ], [ 3, "15.6.2 Monochrome format", 469 ], [ 3, "15.6.3 RGB format", 469 ], [ 3, "15.6.4 YCbCr format", 469 ], [ 2, "15.7 DCMI interrupts", 470 ], [ 2, "15.8 DCMI register description", 470 ], [ 3, "15.8.1 DCMI control register 1 (DCMI_CR)", 470 ], [ 3, "15.8.2 DCMI status register (DCMI_SR)", 473 ], [ 3, "15.8.3 DCMI raw interrupt status register (DCMI_RIS)", 474 ], [ 3, "15.8.4 DCMI interrupt enable register (DCMI_IER)", 475 ], [ 3, "15.8.5 DCMI masked interrupt status register (DCMI_MIS)", 476 ], [ 3, "15.8.6 DCMI interrupt clear register (DCMI_ICR)", 477 ], [ 3, "15.8.7 DCMI embedded synchronization code register (DCMI_ESCR)", 478 ], [ 3, "15.8.8 DCMI embedded synchronization unmask register (DCMI_ESUR)", 479 ], [ 3, "15.8.9 DCMI crop window start (DCMI_CWSTRT)", 480 ], [ 3, "15.8.10 DCMI crop window size (DCMI_CWSIZE)", 480 ], [ 3, "15.8.11 DCMI data register (DCMI_DR)", 481 ], [ 3, "15.8.12 DCMI register map", 481 ], [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.1 Introduction", 483 ], [ 2, "16.2 LTDC main features", 483 ], [ 2, "16.3 LTDC functional description", 484 ], [ 3, "16.3.1 LTDC block diagram", 484 ], [ 3, "16.3.2 LTDC reset and clocks", 484 ], [ 3, "16.3.3 LCD-TFT pins and signal interface", 486 ], [ 2, "16.4 LTDC programmable parameters", 486 ], [ 3, "16.4.1 LTDC Global configuration parameters", 486 ], [ 4, "Synchronous Timings:", 486 ], [ 4, "Example of Synchronous timings configuration", 488 ], [ 4, "Programmable polarity", 488 ], [ 4, "Background Color", 488 ], [ 4, "Dithering", 488 ], [ 4, "Reload Shadow registers", 489 ], [ 4, "Interrupt generation event", 489 ], [ 3, "16.4.2 Layer programmable parameters", 489 ], [ 4, "Windowing", 489 ], [ 4, "Pixel input Format", 490 ], [ 4, "Color Look-Up Table (CLUT)", 491 ], [ 4, "Color Frame Buffer Address", 492 ], [ 4, "Color Frame Buffer Length", 492 ], [ 4, "Color Frame Buffer Pitch", 492 ], [ 4, "Layer Blending", 492 ], [ 4, "Default color", 493 ], [ 4, "Color Keying", 493 ], [ 2, "16.5 LTDC interrupts", 493 ], [ 2, "16.6 LTDC programming procedure", 495 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.1 LTDC Synchronization Size Configuration Register (LTDC_SSCR)", 496 ], [ 3, "16.7.2 LTDC Back Porch Configuration Register (LTDC_BPCR)", 496 ], [ 3, "16.7.3 LTDC Active Width Configuration Register (LTDC_AWCR)", 497 ], [ 3, "16.7.4 LTDC Total Width Configuration Register (LTDC_TWCR)", 498 ], [ 3, "16.7.5 LTDC Global Control Register (LTDC_GCR)", 498 ], [ 3, "16.7.6 LTDC Shadow Reload Configuration Register (LTDC_SRCR)", 500 ], [ 3, "16.7.7 LTDC Background Color Configuration Register (LTDC_BCCR)", 500 ], [ 3, "16.7.8 LTDC Interrupt Enable Register (LTDC_IER)", 501 ], [ 3, "16.7.9 LTDC Interrupt Status Register (LTDC_ISR)", 502 ], [ 3, "16.7.10 LTDC Interrupt Clear Register (LTDC_ICR)", 502 ], [ 3, "16.7.11 LTDC Line Interrupt Position Configuration Register (LTDC_LIPCR)", 503 ], [ 3, "16.7.12 LTDC Current Position Status Register (LTDC_CPSR)", 503 ], [ 3, "16.7.13 LTDC Current Display Status Register (LTDC_CDSR)", 504 ], [ 3, "16.7.14 LTDC Layerx Control Register (LTDC_LxCR) (where x=1..2)", 505 ], [ 3, "16.7.15 LTDC Layerx Window Horizontal Position Configuration Register (LTDC_LxWHPCR) (where x=1..2)", 506 ], [ 3, "16.7.16 LTDC Layerx Window Vertical Position Configuration Register (LTDC_LxWVPCR) (where x=1..2)", 507 ], [ 3, "16.7.17 LTDC Layerx Color Keying Configuration Register (LTDC_LxCKCR) (where x=1..2)", 508 ], [ 3, "16.7.18 LTDC Layerx Pixel Format Configuration Register (LTDC_LxPFCR) (where x=1..2)", 508 ], [ 3, "16.7.19 LTDC Layerx Constant Alpha Configuration Register (LTDC_LxCACR) (where x=1..2)", 509 ], [ 3, "16.7.20 LTDC Layerx Default Color Configuration Register (LTDC_LxDCCR) (where x=1..2)", 509 ], [ 3, "16.7.21 LTDC Layerx Blending Factors Configuration Register (LTDC_LxBFCR) (where x=1..2)", 511 ], [ 3, "16.7.22 LTDC Layerx Color Frame Buffer Address Register (LTDC_LxCFBAR) (where x=1..2)", 512 ], [ 3, "16.7.23 LTDC Layerx Color Frame Buffer Length Register (LTDC_LxCFBLR) (where x=1..2)", 512 ], [ 3, "16.7.24 LTDC Layerx ColorFrame Buffer Line Number Register (LTDC_LxCFBLNR) (where x=1..2)", 513 ], [ 3, "16.7.25 LTDC Layerx CLUT Write Register (LTDC_LxCLUTWR) (where x=1..2)", 514 ], [ 3, "16.7.26 LTDC register map", 515 ], [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.1 TIM1 and TIM8 introduction", 518 ], [ 2, "17.2 TIM1 and TIM8 main features", 519 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.1 Time-base unit", 521 ], [ 4, "Prescaler description", 521 ], [ 3, "17.3.2 Counter modes", 523 ], [ 4, "Upcounting mode", 523 ], [ 4, "Downcounting mode", 526 ], [ 4, "Center-aligned mode (up/down counting)", 529 ], [ 3, "17.3.3 Repetition counter", 532 ], [ 3, "17.3.4 Clock selection", 535 ], [ 4, "Internal clock source (CK_INT)", 535 ], [ 4, "External clock source mode 1", 535 ], [ 4, "External clock source mode 2", 537 ], [ 3, "17.3.5 Capture/compare channels", 538 ], [ 3, "17.3.6 Input capture mode", 541 ], [ 3, "17.3.7 PWM input mode", 542 ], [ 3, "17.3.8 Forced output mode", 542 ], [ 3, "17.3.9 Output compare mode", 543 ], [ 3, "17.3.10 PWM mode", 544 ], [ 4, "PWM edge-aligned mode", 544 ], [ 4, "PWM center-aligned mode", 545 ], [ 3, "17.3.11 Complementary outputs and dead-time insertion", 547 ], [ 4, "Re-directing OCxREF to OCx or OCxN", 548 ], [ 3, "17.3.12 Using the break function", 549 ], [ 3, "17.3.13 Clearing the OCxREF signal on an external event", 552 ], [ 3, "17.3.14 6-step PWM generation", 553 ], [ 3, "17.3.15 One-pulse mode", 554 ], [ 3, "17.3.16 Encoder interface mode", 555 ], [ 3, "17.3.17 Timer input XOR function", 558 ], [ 3, "17.3.18 Interfacing with Hall sensors", 558 ], [ 3, "17.3.19 TIMx and external trigger synchronization", 560 ], [ 4, "Slave mode: Reset mode", 560 ], [ 4, "Slave mode: Gated mode", 561 ], [ 4, "Slave mode: Trigger mode", 562 ], [ 4, "Slave mode: external clock mode 2 + trigger mode", 562 ], [ 3, "17.3.20 Timer synchronization", 563 ], [ 3, "17.3.21 Debug mode", 563 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.1 TIM1 and TIM8 control register 1 (TIMx_CR1)", 564 ], [ 3, "17.4.2 TIM1 and TIM8 control register 2 (TIMx_CR2)", 565 ], [ 3, "17.4.3 TIM1 and TIM8 slave mode control register (TIMx_SMCR)", 568 ], [ 3, "17.4.4 TIM1 and TIM8 DMA/interrupt enable register (TIMx_DIER)", 570 ], [ 3, "17.4.5 TIM1 and TIM8 status register (TIMx_SR)", 572 ], [ 3, "17.4.6 TIM1 and TIM8 event generation register (TIMx_EGR)", 573 ], [ 3, "17.4.7 TIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1)", 575 ], [ 4, "Output compare mode:", 575 ], [ 4, "Input capture mode", 577 ], [ 3, "17.4.8 TIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2)", 577 ], [ 4, "Output compare mode", 578 ], [ 4, "Input capture mode", 579 ], [ 3, "17.4.9 TIM1 and TIM8 capture/compare enable register (TIMx_CCER)", 579 ], [ 3, "17.4.10 TIM1 and TIM8 counter (TIMx_CNT)", 583 ], [ 3, "17.4.11 TIM1 and TIM8 prescaler (TIMx_PSC)", 583 ], [ 3, "17.4.12 TIM1 and TIM8 auto-reload register (TIMx_ARR)", 583 ], [ 3, "17.4.13 TIM1 and TIM8 repetition counter register (TIMx_RCR)", 584 ], [ 3, "17.4.14 TIM1 and TIM8 capture/compare register 1 (TIMx_CCR1)", 584 ], [ 3, "17.4.15 TIM1 and TIM8 capture/compare register 2 (TIMx_CCR2)", 585 ], [ 3, "17.4.16 TIM1 and TIM8 capture/compare register 3 (TIMx_CCR3)", 585 ], [ 3, "17.4.17 TIM1 and TIM8 capture/compare register 4 (TIMx_CCR4)", 586 ], [ 3, "17.4.18 TIM1 and TIM8 break and dead-time register (TIMx_BDTR)", 586 ], [ 3, "17.4.19 TIM1 and TIM8 DMA control register (TIMx_DCR)", 588 ], [ 3, "17.4.20 TIM1 and TIM8 DMA address for full transfer (TIMx_DMAR)", 589 ], [ 4, "Example of how to use the DMA burst feature", 589 ], [ 3, "17.4.21 TIM1 and TIM8 register map", 590 ], [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.1 TIM2 to TIM5 introduction", 592 ], [ 2, "18.2 TIM2 to TIM5 main features", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.1 Time-base unit", 594 ], [ 4, "Prescaler description", 594 ], [ 3, "18.3.2 Counter modes", 595 ], [ 4, "Upcounting mode", 595 ], [ 4, "Downcounting mode", 598 ], [ 4, "Center-aligned mode (up/down counting)", 601 ], [ 3, "18.3.3 Clock selection", 605 ], [ 4, "Internal clock source (CK_INT)", 605 ], [ 4, "External clock source mode 1", 605 ], [ 4, "External clock source mode 2", 607 ], [ 3, "18.3.4 Capture/compare channels", 608 ], [ 3, "18.3.5 Input capture mode", 610 ], [ 3, "18.3.6 PWM input mode", 611 ], [ 3, "18.3.7 Forced output mode", 612 ], [ 3, "18.3.8 Output compare mode", 612 ], [ 3, "18.3.9 PWM mode", 613 ], [ 4, "PWM edge-aligned mode", 614 ], [ 4, "Upcounting configuration", 614 ], [ 4, "Downcounting configuration", 614 ], [ 4, "PWM center-aligned mode", 614 ], [ 3, "18.3.10 One-pulse mode", 616 ], [ 4, "Particular case: OCx fast enable:", 617 ], [ 3, "18.3.11 Clearing the OCxREF signal on an external event", 617 ], [ 3, "18.3.12 Encoder interface mode", 618 ], [ 3, "18.3.13 Timer input XOR function", 621 ], [ 3, "18.3.14 Timers and external trigger synchronization", 621 ], [ 4, "Slave mode: Reset mode", 621 ], [ 4, "Slave mode: Gated mode", 622 ], [ 4, "Slave mode: Trigger mode", 622 ], [ 4, "Slave mode: External Clock mode 2 + trigger mode", 623 ], [ 3, "18.3.15 Timer synchronization", 624 ], [ 4, "Using one timer as prescaler for another timer", 624 ], [ 4, "Using one timer to enable another timer", 625 ], [ 4, "Using one timer to start another timer", 627 ], [ 4, "Starting 2 timers synchronously in response to an external trigger", 628 ], [ 3, "18.3.16 Debug mode", 629 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.1 TIMx control register 1 (TIMx_CR1)", 630 ], [ 3, "18.4.2 TIMx control register 2 (TIMx_CR2)", 632 ], [ 3, "18.4.3 TIMx slave mode control register (TIMx_SMCR)", 633 ], [ 3, "18.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)", 635 ], [ 3, "18.4.5 TIMx status register (TIMx_SR)", 636 ], [ 3, "18.4.6 TIMx event generation register (TIMx_EGR)", 638 ], [ 3, "18.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)", 639 ], [ 4, "Output compare mode", 639 ], [ 4, "Input capture mode", 641 ], [ 3, "18.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)", 642 ], [ 4, "Output compare mode", 642 ], [ 4, "Input capture mode", 643 ], [ 3, "18.4.9 TIMx capture/compare enable register (TIMx_CCER)", 643 ], [ 3, "18.4.10 TIMx counter (TIMx_CNT)", 645 ], [ 3, "18.4.11 TIMx prescaler (TIMx_PSC)", 645 ], [ 3, "18.4.12 TIMx auto-reload register (TIMx_ARR)", 645 ], [ 3, "18.4.13 TIMx capture/compare register 1 (TIMx_CCR1)", 646 ], [ 3, "18.4.14 TIMx capture/compare register 2 (TIMx_CCR2)", 646 ], [ 3, "18.4.15 TIMx capture/compare register 3 (TIMx_CCR3)", 647 ], [ 3, "18.4.16 TIMx capture/compare register 4 (TIMx_CCR4)", 647 ], [ 3, "18.4.17 TIMx DMA control register (TIMx_DCR)", 648 ], [ 3, "18.4.18 TIMx DMA address for full transfer (TIMx_DMAR)", 649 ], [ 4, "Example of how to use the DMA burst feature", 649 ], [ 3, "18.4.19 TIM2 option register (TIM2_OR)", 649 ], [ 3, "18.4.20 TIM5 option register (TIM5_OR)", 650 ], [ 3, "18.4.21 TIMx register map", 651 ], [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.1 TIM9 to TIM14 introduction", 653 ], [ 2, "19.2 TIM9 to TIM14 main features", 653 ], [ 3, "19.2.1 TIM9/TIM12 main features", 653 ], [ 3, "19.2.2 TIM10/TIM11 and TIM13/TIM14 main features", 654 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.1 Time-base unit", 656 ], [ 4, "Prescaler description", 656 ], [ 3, "19.3.2 Counter modes", 658 ], [ 4, "Upcounting mode", 658 ], [ 3, "19.3.3 Clock selection", 661 ], [ 4, "Internal clock source (CK_INT)", 661 ], [ 4, "External clock source mode 1(TIM9 and TIM12)", 661 ], [ 3, "19.3.4 Capture/compare channels", 663 ], [ 3, "19.3.5 Input capture mode", 664 ], [ 3, "19.3.6 PWM input mode (only for TIM9/12)", 666 ], [ 3, "19.3.7 Forced output mode", 667 ], [ 3, "19.3.8 Output compare mode", 667 ], [ 3, "19.3.9 PWM mode", 668 ], [ 4, "PWM edge-aligned mode", 668 ], [ 3, "19.3.10 One-pulse mode", 669 ], [ 3, "19.3.11 TIM9/12 external trigger synchronization", 671 ], [ 4, "Slave mode: Reset mode", 671 ], [ 4, "Slave mode: Gated mode", 672 ], [ 4, "Slave mode: Trigger mode", 673 ], [ 3, "19.3.12 Timer synchronization (TIM9/12)", 674 ], [ 3, "19.3.13 Debug mode", 674 ], [ 2, "19.4 TIM9 and TIM12 registers", 675 ], [ 3, "19.4.1 TIM9/12 control register 1 (TIMx_CR1)", 675 ], [ 3, "19.4.2 TIM9/12 slave mode control register (TIMx_SMCR)", 676 ], [ 3, "19.4.3 TIM9/12 Interrupt enable register (TIMx_DIER)", 677 ], [ 3, "19.4.4 TIM9/12 status register (TIMx_SR)", 679 ], [ 3, "19.4.5 TIM9/12 event generation register (TIMx_EGR)", 680 ], [ 3, "19.4.6 TIM9/12 capture/compare mode register 1 (TIMx_CCMR1)", 681 ], [ 4, "Output compare mode", 681 ], [ 4, "Input capture mode", 683 ], [ 3, "19.4.7 TIM9/12 capture/compare enable register (TIMx_CCER)", 684 ], [ 3, "19.4.8 TIM9/12 counter (TIMx_CNT)", 685 ], [ 3, "19.4.9 TIM9/12 prescaler (TIMx_PSC)", 685 ], [ 3, "19.4.10 TIM9/12 auto-reload register (TIMx_ARR)", 685 ], [ 3, "19.4.11 TIM9/12 capture/compare register 1 (TIMx_CCR1)", 686 ], [ 3, "19.4.12 TIM9/12 capture/compare register 2 (TIMx_CCR2)", 686 ], [ 3, "19.4.13 TIM9/12 register map", 687 ], [ 2, "19.5 TIM10/11/13/14 registers", 689 ], [ 3, "19.5.1 TIM10/11/13/14 control register 1 (TIMx_CR1)", 689 ], [ 3, "19.5.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER)", 690 ], [ 3, "19.5.3 TIM10/11/13/14 status register (TIMx_SR)", 690 ], [ 3, "19.5.4 TIM10/11/13/14 event generation register (TIMx_EGR)", 691 ], [ 3, "19.5.5 TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1)", 691 ], [ 4, "Output compare mode", 692 ], [ 4, "Input capture mode", 693 ], [ 3, "19.5.6 TIM10/11/13/14 capture/compare enable register (TIMx_CCER)", 694 ], [ 3, "19.5.7 TIM10/11/13/14 counter (TIMx_CNT)", 695 ], [ 3, "19.5.8 TIM10/11/13/14 prescaler (TIMx_PSC)", 695 ], [ 3, "19.5.9 TIM10/11/13/14 auto-reload register (TIMx_ARR)", 695 ], [ 3, "19.5.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1)", 696 ], [ 3, "19.5.11 TIM11 option register 1 (TIM11_OR)", 696 ], [ 3, "19.5.12 TIM10/11/13/14 register map", 697 ], [ 1, "20 Basic timers (TIM6 and TIM7)", 699 ], [ 2, "20.1 TIM6 and TIM7 introduction", 699 ], [ 2, "20.2 TIM6 and TIM7 main features", 699 ], [ 2, "20.3 TIM6 and TIM7 functional description", 700 ], [ 3, "20.3.1 Time-base unit", 700 ], [ 4, "Prescaler description", 700 ], [ 3, "20.3.2 Counting mode", 702 ], [ 3, "20.3.3 Clock source", 704 ], [ 3, "20.3.4 Debug mode", 705 ], [ 2, "20.4 TIM6 and TIM7 registers", 705 ], [ 3, "20.4.1 TIM6 and TIM7 control register 1 (TIMx_CR1)", 705 ], [ 3, "20.4.2 TIM6 and TIM7 control register 2 (TIMx_CR2)", 707 ], [ 3, "20.4.3 TIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER)", 707 ], [ 3, "20.4.4 TIM6 and TIM7 status register (TIMx_SR)", 708 ], [ 3, "20.4.5 TIM6 and TIM7 event generation register (TIMx_EGR)", 708 ], [ 3, "20.4.6 TIM6 and TIM7 counter (TIMx_CNT)", 708 ], [ 3, "20.4.7 TIM6 and TIM7 prescaler (TIMx_PSC)", 709 ], [ 3, "20.4.8 TIM6 and TIM7 auto-reload register (TIMx_ARR)", 709 ], [ 3, "20.4.9 TIM6 and TIM7 register map", 710 ], [ 1, "21 Independent watchdog (IWDG)", 711 ], [ 2, "21.1 IWDG introduction", 711 ], [ 2, "21.2 IWDG main features", 711 ], [ 2, "21.3 IWDG functional description", 711 ], [ 3, "21.3.1 Hardware watchdog", 711 ], [ 3, "21.3.2 Register access protection", 711 ], [ 3, "21.3.3 Debug mode", 712 ], [ 2, "21.4 IWDG registers", 713 ], [ 3, "21.4.1 Key register (IWDG_KR)", 713 ], [ 3, "21.4.2 Prescaler register (IWDG_PR)", 713 ], [ 3, "21.4.3 Reload register (IWDG_RLR)", 714 ], [ 3, "21.4.4 Status register (IWDG_SR)", 714 ], [ 3, "21.4.5 IWDG register map", 715 ], [ 1, "22 Window watchdog (WWDG)", 716 ], [ 2, "22.1 WWDG introduction", 716 ], [ 2, "22.2 WWDG main features", 716 ], [ 2, "22.3 WWDG functional description", 716 ], [ 3, "Enabling the watchdog", 717 ], [ 3, "Controlling the downcounter", 717 ], [ 3, "Advanced watchdog interrupt feature", 717 ], [ 2, "22.4 How to program the watchdog timeout", 718 ], [ 2, "22.5 Debug mode", 719 ], [ 2, "22.6 WWDG registers", 720 ], [ 3, "22.6.1 Control register (WWDG_CR)", 720 ], [ 3, "22.6.2 Configuration register (WWDG_CFR)", 721 ], [ 3, "22.6.3 Status register (WWDG_SR)", 721 ], [ 3, "22.6.4 WWDG register map", 722 ], [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.1 CRYP introduction", 723 ], [ 2, "23.2 CRYP main features", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.1 DES/TDES cryptographic core", 726 ], [ 4, "DES and TDES Electronic codebook (DES/TDES-ECB) mode", 727 ], [ 4, "DES and TDES Cipher block chaining (DES/TDES-CBC) mode", 729 ], [ 3, "23.3.2 AES cryptographic core", 731 ], [ 4, "AES Electronic codebook (AES-ECB) mode", 732 ], [ 4, "AES Cipher block chaining (AES-CBC) mode", 733 ], [ 4, "AES counter mode (AES-CTR) mode", 735 ], [ 4, "AES Galois/counter mode (GCM)", 738 ], [ 4, "AES Galois message authentication code (GMAC)", 740 ], [ 4, "AES combined cipher machine (CCM)", 740 ], [ 3, "23.3.3 Data type", 742 ], [ 3, "23.3.4 Initialization vectors - CRYP_IV0...1(L/R)", 745 ], [ 3, "23.3.5 CRYP busy state", 746 ], [ 3, "23.3.6 Procedure to perform an encryption or a decryption", 747 ], [ 4, "Initialization", 747 ], [ 4, "Processing when the DMA is used to transfer the data from/to the memory", 747 ], [ 4, "Processing when the data are transferred by the CPU during interrupts", 748 ], [ 4, "Processing without using the DMA nor interrupts", 748 ], [ 3, "23.3.7 Context swapping", 748 ], [ 4, "Case of the AES and DES", 749 ], [ 4, "Case of the TDES", 749 ], [ 2, "23.4 CRYP interrupts", 750 ], [ 3, "Output FIFO service interrupt - OUTMIS", 750 ], [ 3, "Input FIFO service interrupt - INMIS", 750 ], [ 2, "23.5 CRYP DMA interface", 751 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.1 CRYP control register (CRYP_CR) for STM32F415/417xx", 751 ], [ 3, "23.6.2 CRYP control register (CRYP_CR) for STM32F415/417xx", 753 ], [ 3, "23.6.3 CRYP status register (CRYP_SR)", 756 ], [ 3, "23.6.4 CRYP data input register (CRYP_DIN)", 757 ], [ 3, "23.6.5 CRYP data output register (CRYP_DOUT)", 758 ], [ 3, "23.6.6 CRYP DMA control register (CRYP_DMACR)", 759 ], [ 3, "23.6.7 CRYP interrupt mask set/clear register (CRYP_IMSCR)", 759 ], [ 3, "23.6.8 CRYP raw interrupt status register (CRYP_RISR)", 760 ], [ 3, "23.6.9 CRYP masked interrupt status register (CRYP_MISR)", 760 ], [ 3, "23.6.10 CRYP key registers (CRYP_K0...3(L/R)R)", 761 ], [ 4, "CRYP_K0LR (address offset: 0x20)", 761 ], [ 4, "CRYP_K0RR (address offset: 0x24)", 761 ], [ 4, "CRYP_K1LR (address offset: 0x28)", 762 ], [ 4, "CRYP_K1RR (address offset: 0x2C)", 762 ], [ 4, "CRYP_K2LR (address offset: 0x30)", 762 ], [ 4, "CRYP_K2RR (address offset: 0x34)", 762 ], [ 4, "CRYP_K3LR (address offset: 0x38)", 762 ], [ 4, "CRYP_K3RR (address offset: 0x3C)", 763 ], [ 3, "23.6.11 CRYP initialization vector registers (CRYP_IV0...1(L/R)R)", 763 ], [ 4, "CRYP_IV0LR (address offset: 0x40)", 763 ], [ 4, "CRYP_IV0RR (address offset: 0x44)", 763 ], [ 4, "CRYP_IV1LR (address offset: 0x48)", 764 ], [ 4, "CRYP_IV1RR (address offset: 0x4C)", 764 ], [ 3, "23.6.12 CRYP context swap registers (CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R) for STM32F42xxx and STM32F43xxx", 765 ], [ 4, "CRYP_CSGCMCCMxR: where x=[7:0]", 765 ], [ 4, "CRYP_CSGCMxR: where x=[7:0]", 765 ], [ 3, "23.6.13 CRYP register map", 766 ], [ 1, "24 Random number generator (RNG)", 770 ], [ 2, "24.1 RNG introduction", 770 ], [ 2, "24.2 RNG main features", 770 ], [ 2, "24.3 RNG functional description", 770 ], [ 3, "24.3.1 Operation", 771 ], [ 3, "24.3.2 Error management", 771 ], [ 4, "If the CEIS bit is read as ‘1’ (clock error)", 771 ], [ 4, "If the SEIS bit is read as ‘1’ (seed error)", 771 ], [ 2, "24.4 RNG registers", 771 ], [ 3, "24.4.1 RNG control register (RNG_CR)", 772 ], [ 3, "24.4.2 RNG status register (RNG_SR)", 772 ], [ 3, "24.4.3 RNG data register (RNG_DR)", 773 ], [ 3, "24.4.4 RNG register map", 774 ], [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.1 HASH introduction", 775 ], [ 2, "25.2 HASH main features", 775 ], [ 2, "25.3 HASH functional description", 776 ], [ 3, "25.3.1 Duration of the processing", 778 ], [ 3, "25.3.2 Data type", 778 ], [ 3, "25.3.3 Message digest computing", 780 ], [ 3, "25.3.4 Message padding", 781 ], [ 3, "25.3.5 Hash operation", 782 ], [ 3, "25.3.6 HMAC operation", 782 ], [ 3, "25.3.7 Context swapping", 783 ], [ 4, "Procedure where the data are loaded by software", 784 ], [ 4, "Procedure where the data are loaded by DMA", 784 ], [ 3, "25.3.8 HASH interrupt", 785 ], [ 2, "25.4 HASH registers", 785 ], [ 3, "25.4.1 HASH control register (HASH_CR) for STM32F415/417xx", 785 ], [ 3, "25.4.2 HASH control register (HASH_CR) for STM32F43xxx", 788 ], [ 3, "25.4.3 HASH data input register (HASH_DIN)", 791 ], [ 3, "25.4.4 HASH start register (HASH_STR)", 792 ], [ 3, "25.4.5 HASH digest registers (HASH_HR0..4/5/6/7)", 793 ], [ 4, "HASH_HR0", 793 ], [ 4, "HASH_HR1", 793 ], [ 4, "HASH_HR2", 793 ], [ 4, "HASH_HR3", 794 ], [ 4, "HASH_HR4", 794 ], [ 4, "HASH_HR5", 794 ], [ 4, "HASH_HR6", 794 ], [ 4, "HASH_HR7", 794 ], [ 3, "25.4.6 HASH interrupt enable register (HASH_IMR)", 795 ], [ 3, "25.4.7 HASH status register (HASH_SR)", 796 ], [ 3, "25.4.8 HASH context swap registers (HASH_CSRx)", 797 ], [ 4, "HASH_CSRx", 797 ], [ 3, "25.4.9 HASH register map", 798 ], [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.1 Introduction", 801 ], [ 2, "26.2 RTC main features", 802 ], [ 2, "26.3 RTC functional description", 804 ], [ 3, "26.3.1 Clock and prescalers", 804 ], [ 3, "26.3.2 Real-time clock and calendar", 805 ], [ 3, "26.3.3 Programmable alarms", 805 ], [ 3, "26.3.4 Periodic auto-wakeup", 805 ], [ 3, "26.3.5 RTC initialization and configuration", 806 ], [ 4, "RTC register access", 806 ], [ 4, "RTC register write protection", 806 ], [ 4, "Calendar initialization and configuration", 807 ], [ 4, "Daylight saving time", 807 ], [ 4, "Programming the alarm", 807 ], [ 4, "Programming the wake-up timer", 808 ], [ 3, "26.3.6 Reading the calendar", 808 ], [ 4, "When BYPSHAD control bit is cleared in the RTC_CR register", 808 ], [ 4, "When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow registers)", 809 ], [ 3, "26.3.7 Resetting the RTC", 809 ], [ 3, "26.3.8 RTC synchronization", 809 ], [ 3, "26.3.9 RTC reference clock detection", 810 ], [ 3, "26.3.10 RTC coarse digital calibration", 811 ], [ 4, "Case of RTCCLK=32.768 kHz and PREDIV_A+1=128", 811 ], [ 3, "26.3.11 RTC smooth digital calibration", 812 ], [ 4, "Calibration when PREDIV_A<3", 812 ], [ 4, "Verifying the RTC calibration", 813 ], [ 4, "Re-calibration on-the-fly", 813 ], [ 3, "26.3.12 Timestamp function", 814 ], [ 4, "TIMESTAMP alternate function", 814 ], [ 3, "26.3.13 Tamper detection", 814 ], [ 4, "RTC backup registers", 814 ], [ 4, "Tamper detection initialization", 815 ], [ 4, "Timestamp on tamper event", 815 ], [ 4, "Edge detection on tamper inputs", 815 ], [ 4, "Level detection with filtering on tamper inputs", 815 ], [ 4, "TAMPER alternate function detection", 816 ], [ 3, "26.3.14 Calibration clock output", 816 ], [ 4, "Calibration alternate function output", 816 ], [ 3, "26.3.15 Alarm output", 816 ], [ 4, "Alarm alternate function output", 817 ], [ 2, "26.4 RTC and low-power modes", 817 ], [ 2, "26.5 RTC interrupts", 817 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.1 RTC time register (RTC_TR)", 819 ], [ 3, "26.6.2 RTC date register (RTC_DR)", 820 ], [ 3, "26.6.3 RTC control register (RTC_CR)", 821 ], [ 3, "26.6.4 RTC initialization and status register (RTC_ISR)", 823 ], [ 3, "26.6.5 RTC prescaler register (RTC_PRER)", 826 ], [ 3, "26.6.6 RTC wake-up timer register (RTC_WUTR)", 826 ], [ 3, "26.6.7 RTC calibration register (RTC_CALIBR)", 827 ], [ 3, "26.6.8 RTC alarm A register (RTC_ALRMAR)", 828 ], [ 3, "26.6.9 RTC alarm B register (RTC_ALRMBR)", 829 ], [ 3, "26.6.10 RTC write protection register (RTC_WPR)", 830 ], [ 3, "26.6.11 RTC sub second register (RTC_SSR)", 830 ], [ 3, "26.6.12 RTC shift control register (RTC_SHIFTR)", 831 ], [ 3, "26.6.13 RTC time stamp time register (RTC_TSTR)", 831 ], [ 3, "26.6.14 RTC time stamp date register (RTC_TSDR)", 832 ], [ 3, "26.6.15 RTC timestamp sub second register (RTC_TSSSR)", 833 ], [ 3, "26.6.16 RTC calibration register (RTC_CALR)", 833 ], [ 3, "26.6.17 RTC tamper and alternate function configuration register (RTC_TAFCR)", 835 ], [ 3, "26.6.18 RTC alarm A sub second register (RTC_ALRMASSR)", 837 ], [ 3, "26.6.19 RTC alarm B sub second register (RTC_ALRMBSSR)", 838 ], [ 3, "26.6.20 RTC backup registers (RTC_BKPxR)", 839 ], [ 3, "26.6.21 RTC register map", 839 ], [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.1 I2C introduction", 842 ], [ 2, "27.2 I2C main features", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.1 Mode selection", 843 ], [ 4, "Communication flow", 843 ], [ 3, "27.3.2 I2C slave mode", 846 ], [ 4, "Slave transmitter", 847 ], [ 4, "Slave receiver", 848 ], [ 4, "Closing slave communication", 849 ], [ 3, "27.3.3 I2C master mode", 849 ], [ 4, "SCL master clock generation", 850 ], [ 4, "Start condition", 850 ], [ 4, "Slave address transmission", 850 ], [ 4, "Master transmitter", 851 ], [ 4, "Master receiver", 852 ], [ 3, "27.3.4 Error conditions", 854 ], [ 4, "Bus error (BERR)", 854 ], [ 4, "Acknowledge failure (AF)", 854 ], [ 4, "Arbitration lost (ARLO)", 854 ], [ 4, "Overrun/underrun error (OVR)", 855 ], [ 3, "27.3.5 Programmable noise filter", 855 ], [ 3, "27.3.6 SDA/SCL line control", 856 ], [ 3, "27.3.7 SMBus", 856 ], [ 4, "Introduction", 856 ], [ 4, "Similarities between SMBus and I2C", 856 ], [ 4, "Differences between SMBus and I2C", 857 ], [ 4, "SMBus application usage", 857 ], [ 4, "Device identification", 857 ], [ 4, "Bus protocols", 857 ], [ 4, "Address resolution protocol (ARP)", 857 ], [ 4, "Unique device identifier (UDID)", 857 ], [ 4, "SMBus alert mode", 858 ], [ 4, "Timeout error", 858 ], [ 4, "How to use the interface in SMBus mode", 858 ], [ 3, "27.3.8 DMA requests", 859 ], [ 4, "Transmission using DMA", 859 ], [ 4, "Reception using DMA", 860 ], [ 3, "27.3.9 Packet error checking", 860 ], [ 2, "27.4 I2C interrupts", 861 ], [ 2, "27.5 I2C debug mode", 863 ], [ 2, "27.6 I2C registers", 863 ], [ 3, "27.6.1 I2C Control register 1 (I2C_CR1)", 863 ], [ 3, "27.6.2 I2C Control register 2 (I2C_CR2)", 865 ], [ 3, "27.6.3 I2C Own address register 1 (I2C_OAR1)", 867 ], [ 3, "27.6.4 I2C Own address register 2 (I2C_OAR2)", 867 ], [ 3, "27.6.5 I2C Data register (I2C_DR)", 868 ], [ 3, "27.6.6 I2C Status register 1 (I2C_SR1)", 868 ], [ 3, "27.6.7 I2C Status register 2 (I2C_SR2)", 871 ], [ 3, "27.6.8 I2C Clock control register (I2C_CCR)", 873 ], [ 3, "27.6.9 I2C TRISE register (I2C_TRISE)", 874 ], [ 3, "27.6.10 I2C FLTR register (I2C_FLTR)", 874 ], [ 3, "27.6.11 I2C register map", 875 ], [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.1 SPI introduction", 876 ], [ 2, "28.2 SPI and I2S main features", 877 ], [ 3, "28.2.1 SPI features", 877 ], [ 3, "28.2.2 I2S features", 878 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.1 General description", 879 ], [ 4, "Slave select (NSS) pin management", 880 ], [ 4, "Clock phase and clock polarity", 881 ], [ 4, "Data frame format", 882 ], [ 3, "28.3.2 Configuring the SPI in slave mode", 883 ], [ 4, "Procedure", 883 ], [ 4, "Transmit sequence", 883 ], [ 4, "Receive sequence", 883 ], [ 4, "SPI TI protocol in slave mode", 884 ], [ 3, "28.3.3 Configuring the SPI in master mode", 885 ], [ 4, "Procedure", 885 ], [ 4, "Transmit sequence", 885 ], [ 4, "Receive sequence", 886 ], [ 4, "SPI TI protocol in master mode", 886 ], [ 3, "28.3.4 Configuring the SPI for half-duplex communication", 887 ], [ 4, "1 clock and 1 bidirectional data wire (BIDIMODE = 1)", 887 ], [ 4, "1 clock and 1 unidirectional data wire (BIDIMODE = 0)", 887 ], [ 3, "28.3.5 Data transmission and reception procedures", 888 ], [ 4, "Rx and Tx buffers", 888 ], [ 4, "Start sequence in master mode", 888 ], [ 4, "Start sequence in slave mode", 888 ], [ 4, "Handling data transmission and reception", 889 ], [ 4, "Transmit-only procedure (BIDIMODE=0 RXONLY=0)", 891 ], [ 4, "Bidirectional transmit procedure (BIDIMODE=1 and BIDIOE=1)", 892 ], [ 4, "Unidirectional receive-only procedure (BIDIMODE=0 and RXONLY=1)", 892 ], [ 4, "Bidirectional receive procedure (BIDIMODE=1 and BIDIOE=0)", 893 ], [ 4, "Continuous and discontinuous transfers", 893 ], [ 3, "28.3.6 CRC calculation", 894 ], [ 3, "28.3.7 Status flags", 896 ], [ 4, "Tx buffer empty flag (TXE)", 896 ], [ 4, "Rx buffer not empty (RXNE)", 896 ], [ 4, "BUSY flag", 896 ], [ 3, "28.3.8 Disabling the SPI", 897 ], [ 4, "In master or slave full-duplex mode (BIDIMODE=0, RXONLY=0)", 897 ], [ 4, "In master or slave unidirectional transmit-only mode (BIDIMODE=0, RXONLY=0) or bidirectional transmit mode (BIDIMODE=1, BIDIOE=1)", 897 ], [ 4, "In master unidirectional receive-only mode (MSTR=1, BIDIMODE=0, RXONLY=1) or bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0)", 897 ], [ 4, "In slave receive-only mode (MSTR=0, BIDIMODE=0, RXONLY=1) or bidirectional receive mode (MSTR=0, BIDIMODE=1, BIDOE=0)", 898 ], [ 3, "28.3.9 SPI communication using DMA (direct memory addressing)", 898 ], [ 4, "DMA capability with CRC", 900 ], [ 3, "28.3.10 Error flags", 900 ], [ 4, "Master mode fault (MODF)", 900 ], [ 4, "Overrun condition", 900 ], [ 4, "CRC error", 901 ], [ 4, "TI mode frame format error", 901 ], [ 3, "28.3.11 SPI interrupts", 901 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.1 I2S general description", 902 ], [ 3, "28.4.2 I2S full duplex", 903 ], [ 3, "28.4.3 Supported audio protocols", 904 ], [ 4, "I2S Philips standard", 904 ], [ 4, "MSB justified standard", 906 ], [ 4, "LSB justified standard", 907 ], [ 4, "PCM standard", 910 ], [ 3, "28.4.4 Clock generator", 910 ], [ 3, "28.4.5 I2S master mode", 912 ], [ 4, "Procedure", 913 ], [ 4, "Transmission sequence", 913 ], [ 4, "Reception sequence", 913 ], [ 3, "28.4.6 I2S slave mode", 914 ], [ 4, "Transmission sequence", 915 ], [ 4, "Reception sequence", 915 ], [ 3, "28.4.7 Status flags", 916 ], [ 4, "Busy flag (BSY)", 916 ], [ 4, "Tx buffer empty flag (TXE)", 917 ], [ 4, "RX buffer not empty (RXNE)", 917 ], [ 4, "Channel Side flag (CHSIDE)", 917 ], [ 3, "28.4.8 Error flags", 917 ], [ 4, "Underrun flag (UDR)", 917 ], [ 4, "Overrun flag (OVR)", 917 ], [ 4, "Frame error flag (FRE)", 917 ], [ 3, "28.4.9 I2S interrupts", 918 ], [ 3, "28.4.10 DMA features", 918 ], [ 2, "28.5 SPI and I2S registers", 919 ], [ 3, "28.5.1 SPI control register 1 (SPI_CR1) (not used in I2S mode)", 919 ], [ 3, "28.5.2 SPI control register 2 (SPI_CR2)", 921 ], [ 3, "28.5.3 SPI status register (SPI_SR)", 922 ], [ 3, "28.5.4 SPI data register (SPI_DR)", 923 ], [ 3, "28.5.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I2S mode)", 924 ], [ 3, "28.5.6 SPI RX CRC register (SPI_RXCRCR) (not used in I2S mode)", 924 ], [ 3, "28.5.7 SPI TX CRC register (SPI_TXCRCR) (not used in I2S mode)", 925 ], [ 3, "28.5.8 SPI_I2S configuration register (SPI_I2SCFGR)", 925 ], [ 3, "28.5.9 SPI_I2S prescaler register (SPI_I2SPR)", 927 ], [ 3, "28.5.10 SPI register map", 928 ], [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.1 Introduction", 929 ], [ 2, "29.2 Main features", 930 ], [ 2, "29.3 Functional block diagram", 931 ], [ 2, "29.4 Main SAI modes", 932 ], [ 2, "29.5 SAI synchronization mode", 933 ], [ 3, "Internal synchronization", 933 ], [ 2, "29.6 Audio data size", 933 ], [ 2, "29.7 Frame synchronization", 933 ], [ 3, "29.7.1 Frame length", 934 ], [ 3, "29.7.2 Frame synchronization polarity", 934 ], [ 3, "29.7.3 Frame synchronization active level length", 935 ], [ 3, "29.7.4 Frame synchronization offset", 935 ], [ 3, "29.7.5 FS signal role", 935 ], [ 2, "29.8 Slot configuration", 936 ], [ 2, "29.9 SAI clock generator", 938 ], [ 2, "29.10 Internal FIFOs", 939 ], [ 3, "Interrupt generation in transmitter mode", 940 ], [ 3, "Interrupt generation in reception mode", 940 ], [ 2, "29.11 AC’97 link controller", 942 ], [ 2, "29.12 Specific features", 943 ], [ 3, "29.12.1 Mute mode", 943 ], [ 4, "Transmitter", 943 ], [ 4, "Receiver", 943 ], [ 3, "29.12.2 MONO/STEREO function", 943 ], [ 3, "29.12.3 Companding mode", 944 ], [ 3, "29.12.4 Output data line management on an inactive slot", 945 ], [ 2, "29.13 Error flags", 947 ], [ 3, "29.13.1 FIFO overrun/underrun (OVRUDR)", 947 ], [ 4, "Overrun", 947 ], [ 4, "Underrun", 948 ], [ 3, "29.13.2 Anticipated frame synchronisation detection (AFSDET)", 949 ], [ 3, "29.13.3 Late frame synchronization detection", 949 ], [ 3, "29.13.4 Codec not ready (CNRDY AC’97)", 950 ], [ 3, "29.13.5 Wrong clock configuration in master mode (with NODIV = 0)", 950 ], [ 2, "29.14 Interrupt sources", 951 ], [ 2, "29.15 Disabling the SAI", 951 ], [ 2, "29.16 SAI DMA interface", 952 ], [ 2, "29.17 SAI registers", 953 ], [ 3, "29.17.1 SAI x configuration register 1 (SAI_xCR1) where x is A or B", 953 ], [ 3, "29.17.2 SAI x configuration register 2 (SAI_xCR2) where x is A or B", 956 ], [ 3, "29.17.3 SAI x frame configuration register (SAI_XFRCR) where x is A or B", 958 ], [ 3, "29.17.4 SAI x slot register (SAI_xSLOTR) where x is A or B", 960 ], [ 3, "29.17.5 SAI x interrupt mask register (SAI_xIM) where x is A or B", 961 ], [ 3, "29.17.6 SAI x status register (SAI_xSR) where x is A or B", 963 ], [ 3, "29.17.7 SAI x clear flag register (SAI_xCLRFR) where X is A or B", 965 ], [ 3, "29.17.8 SAI x data register (SAI_xDR) where x is A or B", 966 ], [ 3, "29.17.9 SAI register map", 966 ], [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.1 USART introduction", 968 ], [ 2, "30.2 USART main features", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.1 USART character description", 972 ], [ 3, "30.3.2 Transmitter", 973 ], [ 4, "Character transmission", 973 ], [ 4, "Configurable stop bits", 973 ], [ 4, "Single byte communication", 974 ], [ 4, "Break characters", 975 ], [ 4, "Idle characters", 976 ], [ 3, "30.3.3 Receiver", 976 ], [ 4, "Start bit detection", 976 ], [ 4, "Character reception", 977 ], [ 4, "Break character", 977 ], [ 4, "Idle character", 977 ], [ 4, "Overrun error", 978 ], [ 4, "Selecting the proper oversampling method", 978 ], [ 4, "Framing error", 980 ], [ 4, "Configurable stop bits during reception", 981 ], [ 3, "30.3.4 Fractional baud rate generation", 981 ], [ 4, "How to derive USARTDIV from USART_BRR register values when OVER8=0", 982 ], [ 4, "How to derive USARTDIV from USART_BRR register values when OVER8=1", 982 ], [ 3, "30.3.5 USART receiver tolerance to clock deviation", 991 ], [ 3, "30.3.6 Multiprocessor communication", 992 ], [ 4, "Idle line detection (WAKE=0)", 992 ], [ 4, "Address mark detection (WAKE=1)", 993 ], [ 3, "30.3.7 Parity control", 994 ], [ 4, "Even parity", 994 ], [ 4, "Odd parity", 994 ], [ 4, "Parity checking in reception", 994 ], [ 4, "Parity generation in transmission", 994 ], [ 3, "30.3.8 LIN (local interconnection network) mode", 995 ], [ 4, "LIN transmission", 995 ], [ 4, "LIN reception", 995 ], [ 3, "30.3.9 USART synchronous mode", 997 ], [ 3, "30.3.10 Single-wire half-duplex communication", 999 ], [ 3, "30.3.11 Smartcard", 1000 ], [ 3, "30.3.12 IrDA SIR ENDEC block", 1002 ], [ 4, "IrDA low-power mode", 1003 ], [ 3, "30.3.13 Continuous communication using DMA", 1004 ], [ 4, "Transmission using DMA", 1004 ], [ 4, "Reception using DMA", 1005 ], [ 4, "Error flagging and interrupt generation in multibuffer communication", 1006 ], [ 3, "30.3.14 Hardware flow control", 1006 ], [ 4, "RTS flow control", 1007 ], [ 4, "CTS flow control", 1007 ], [ 2, "30.4 USART interrupts", 1009 ], [ 2, "30.5 USART mode configuration", 1010 ], [ 2, "30.6 USART registers", 1010 ], [ 3, "30.6.1 Status register (USART_SR)", 1010 ], [ 3, "30.6.2 Data register (USART_DR)", 1013 ], [ 3, "30.6.3 Baud rate register (USART_BRR)", 1013 ], [ 3, "30.6.4 Control register 1 (USART_CR1)", 1013 ], [ 3, "30.6.5 Control register 2 (USART_CR2)", 1016 ], [ 3, "30.6.6 Control register 3 (USART_CR3)", 1017 ], [ 3, "30.6.7 Guard time and prescaler register (USART_GTPR)", 1020 ], [ 3, "30.6.8 USART register map", 1021 ], [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.1 SDIO main features", 1022 ], [ 2, "31.2 SDIO bus topology", 1023 ], [ 2, "31.3 SDIO functional description", 1025 ], [ 3, "31.3.1 SDIO adapter", 1026 ], [ 4, "Adapter register block", 1026 ], [ 4, "Control unit", 1027 ], [ 4, "Command path", 1028 ], [ 4, "Data path", 1032 ], [ 4, "Data FIFO", 1035 ], [ 3, "31.3.2 SDIO APB2 interface", 1036 ], [ 4, "SDIO interrupts", 1036 ], [ 4, "SDIO/DMA interface - procedure for data transfers between the SDIO and memory", 1036 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.1 Card identification mode", 1037 ], [ 3, "31.4.2 Card reset", 1037 ], [ 3, "31.4.3 Operating voltage range validation", 1037 ], [ 3, "31.4.4 Card identification process", 1038 ], [ 3, "31.4.5 Block write", 1039 ], [ 3, "31.4.6 Block read", 1040 ], [ 3, "31.4.7 Stream access, stream write and stream read (MultiMediaCard only)", 1040 ], [ 4, "Stream write (MultiMediaCard only)", 1040 ], [ 4, "Stream read (MultiMediaCard only)", 1041 ], [ 3, "31.4.8 Erase: group erase and sector erase", 1042 ], [ 3, "31.4.9 Wide bus selection or deselection", 1042 ], [ 3, "31.4.10 Protection management", 1042 ], [ 4, "Internal card write protection", 1042 ], [ 4, "Mechanical write protect switch", 1043 ], [ 4, "Password protect", 1043 ], [ 4, "Setting the password", 1043 ], [ 4, "Resetting the password", 1044 ], [ 4, "Locking a card", 1044 ], [ 4, "Unlocking the card", 1045 ], [ 4, "Forcing erase", 1045 ], [ 3, "31.4.11 Card status register", 1045 ], [ 3, "31.4.12 SD status register", 1048 ], [ 4, "SIZE_OF_PROTECTED_AREA", 1050 ], [ 4, "SPEED_CLASS", 1050 ], [ 4, "PERFORMANCE_MOVE", 1050 ], [ 4, "AU_SIZE", 1051 ], [ 4, "ERASE_SIZE", 1051 ], [ 4, "ERASE_TIMEOUT", 1052 ], [ 4, "ERASE_OFFSET", 1052 ], [ 3, "31.4.13 SD I/O mode", 1052 ], [ 4, "SD I/O interrupts", 1052 ], [ 4, "SD I/O suspend and resume", 1053 ], [ 4, "SD I/O ReadWait", 1053 ], [ 3, "31.4.14 Commands and responses", 1053 ], [ 4, "Application-specific and general commands", 1053 ], [ 4, "Command types", 1054 ], [ 4, "Command formats", 1054 ], [ 4, "Commands for the MultiMediaCard/SD module", 1054 ], [ 2, "31.5 Response formats", 1057 ], [ 3, "31.5.1 R1 (normal response command)", 1057 ], [ 3, "31.5.2 R1b", 1057 ], [ 3, "31.5.3 R2 (CID, CSD register)", 1057 ], [ 3, "31.5.4 R3 (OCR register)", 1058 ], [ 3, "31.5.5 R4 (Fast I/O)", 1058 ], [ 3, "31.5.6 R4b", 1059 ], [ 3, "31.5.7 R5 (interrupt request)", 1059 ], [ 3, "31.5.8 R6", 1060 ], [ 2, "31.6 SDIO I/O card-specific operations", 1060 ], [ 3, "31.6.1 SDIO I/O read wait operation by SDIO_D2 signaling", 1061 ], [ 3, "31.6.2 SDIO read wait operation by stopping SDIO_CK", 1061 ], [ 3, "31.6.3 SDIO suspend/resume operation", 1061 ], [ 3, "31.6.4 SDIO interrupts", 1061 ], [ 2, "31.7 CE-ATA specific operations", 1062 ], [ 3, "31.7.1 Command completion signal disable", 1062 ], [ 3, "31.7.2 Command completion signal enable", 1062 ], [ 3, "31.7.3 CE-ATA interrupt", 1062 ], [ 3, "31.7.4 Aborting CMD61", 1062 ], [ 2, "31.8 HW flow control", 1063 ], [ 2, "31.9 SDIO registers", 1063 ], [ 3, "31.9.1 SDIO power control register (SDIO_POWER)", 1063 ], [ 3, "31.9.2 SDI clock control register (SDIO_CLKCR)", 1064 ], [ 3, "31.9.3 SDIO argument register (SDIO_ARG)", 1065 ], [ 3, "31.9.4 SDIO command register (SDIO_CMD)", 1065 ], [ 3, "31.9.5 SDIO command response register (SDIO_RESPCMD)", 1066 ], [ 3, "31.9.6 SDIO response 1..4 register (SDIO_RESPx)", 1067 ], [ 3, "31.9.7 SDIO data timer register (SDIO_DTIMER)", 1067 ], [ 3, "31.9.8 SDIO data length register (SDIO_DLEN)", 1068 ], [ 3, "31.9.9 SDIO data control register (SDIO_DCTRL)", 1069 ], [ 3, "31.9.10 SDIO data counter register (SDIO_DCOUNT)", 1070 ], [ 3, "31.9.11 SDIO status register (SDIO_STA)", 1071 ], [ 3, "31.9.12 SDIO interrupt clear register (SDIO_ICR)", 1072 ], [ 3, "31.9.13 SDIO mask register (SDIO_MASK)", 1074 ], [ 3, "31.9.14 SDIO FIFO counter register (SDIO_FIFOCNT)", 1076 ], [ 3, "31.9.15 SDIO data FIFO register (SDIO_FIFO)", 1077 ], [ 3, "31.9.16 SDIO register map", 1077 ], [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.1 bxCAN introduction", 1079 ], [ 2, "32.2 bxCAN main features", 1079 ], [ 3, "Transmission", 1079 ], [ 3, "Reception", 1079 ], [ 3, "Time-triggered communication option", 1079 ], [ 3, "Management", 1079 ], [ 3, "Dual CAN", 1080 ], [ 2, "32.3 bxCAN general description", 1080 ], [ 3, "32.3.1 CAN 2.0B active core", 1080 ], [ 3, "32.3.2 Control, status and configuration registers", 1081 ], [ 3, "32.3.3 Tx mailboxes", 1081 ], [ 3, "32.3.4 Acceptance filters", 1081 ], [ 4, "Receive FIFO", 1081 ], [ 2, "32.4 bxCAN operating modes", 1082 ], [ 3, "32.4.1 Initialization mode", 1083 ], [ 3, "32.4.2 Normal mode", 1083 ], [ 3, "32.4.3 Sleep mode (low-power)", 1083 ], [ 2, "32.5 Test mode", 1084 ], [ 3, "32.5.1 Silent mode", 1084 ], [ 3, "32.5.2 Loop back mode", 1085 ], [ 3, "32.5.3 Loop back combined with silent mode", 1085 ], [ 2, "32.6 Debug mode", 1086 ], [ 2, "32.7 bxCAN functional description", 1086 ], [ 3, "32.7.1 Transmission handling", 1086 ], [ 4, "Transmit priority", 1087 ], [ 4, "Abort", 1087 ], [ 4, "Nonautomatic retransmission mode", 1087 ], [ 3, "32.7.2 Time triggered communication mode", 1088 ], [ 3, "32.7.3 Reception handling", 1088 ], [ 4, "Valid message", 1088 ], [ 4, "FIFO management", 1089 ], [ 4, "Overrun", 1089 ], [ 4, "Reception related interrupts", 1090 ], [ 3, "32.7.4 Identifier filtering", 1090 ], [ 4, "Scalable width", 1090 ], [ 4, "Mask mode", 1090 ], [ 4, "Identifier list mode", 1090 ], [ 4, "Filter bank scale and mode configuration", 1091 ], [ 4, "Filter match index", 1091 ], [ 4, "Filter priority rules", 1093 ], [ 3, "32.7.5 Message storage", 1094 ], [ 4, "Transmit mailbox", 1094 ], [ 4, "Receive mailbox", 1094 ], [ 3, "32.7.6 Error management", 1096 ], [ 4, "Bus-Off recovery", 1096 ], [ 3, "32.7.7 Bit timing", 1096 ], [ 2, "32.8 bxCAN interrupts", 1098 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.1 Register access protection", 1100 ], [ 3, "32.9.2 CAN control and status registers", 1100 ], [ 4, "CAN master control register (CAN_MCR)", 1100 ], [ 4, "CAN master status register (CAN_MSR)", 1102 ], [ 4, "CAN transmit status register (CAN_TSR)", 1103 ], [ 4, "CAN receive FIFO 0 register (CAN_RF0R)", 1105 ], [ 4, "CAN receive FIFO 1 register (CAN_RF1R)", 1106 ], [ 4, "CAN interrupt enable register (CAN_IER)", 1106 ], [ 4, "CAN error status register (CAN_ESR)", 1108 ], [ 4, "CAN bit timing register (CAN_BTR)", 1109 ], [ 3, "32.9.3 CAN mailbox registers", 1110 ], [ 4, "CAN TX mailbox identifier register (CAN_TIxR) (x=0..2)", 1111 ], [ 4, "CAN mailbox data length control and time stamp register (CAN_TDTxR) (x=0..2)", 1112 ], [ 4, "CAN mailbox data low register (CAN_TDLxR) (x=0..2)", 1113 ], [ 4, "CAN mailbox data high register (CAN_TDHxR) (x=0..2)", 1113 ], [ 4, "CAN receive FIFO mailbox identifier register (CAN_RIxR) (x=0..1)", 1114 ], [ 4, "CAN receive FIFO mailbox data length control and time stamp register (CAN_RDTxR) (x=0..1)", 1115 ], [ 4, "CAN receive FIFO mailbox data low register (CAN_RDLxR) (x=0..1)", 1116 ], [ 4, "CAN receive FIFO mailbox data high register (CAN_RDHxR) (x=0..1)", 1116 ], [ 3, "32.9.4 CAN filter registers", 1117 ], [ 4, "CAN filter master register (CAN_FMR)", 1117 ], [ 4, "CAN filter mode register (CAN_FM1R)", 1118 ], [ 4, "CAN filter scale register (CAN_FS1R)", 1118 ], [ 4, "CAN filter FIFO assignment register (CAN_FFA1R)", 1119 ], [ 4, "CAN filter activation register (CAN_FA1R)", 1119 ], [ 4, "Filter bank i register x (CAN_FiRx) (i=0..27, x=1, 2)", 1120 ], [ 3, "32.9.5 bxCAN register map", 1121 ], [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.1 Ethernet introduction", 1125 ], [ 2, "33.2 Ethernet main features", 1125 ], [ 3, "33.2.1 MAC core features", 1126 ], [ 3, "33.2.2 DMA features", 1127 ], [ 3, "33.2.3 PTP features", 1127 ], [ 2, "33.3 Ethernet pins", 1128 ], [ 2, "33.4 Ethernet functional description: SMI, MII and RMII", 1129 ], [ 3, "33.4.1 Station management interface: SMI", 1129 ], [ 4, "SMI frame format", 1130 ], [ 4, "SMI write operation", 1131 ], [ 4, "SMI read operation", 1131 ], [ 4, "SMI clock selection", 1132 ], [ 3, "33.4.2 Media-independent interface: MII", 1132 ], [ 4, "MII clock sources", 1134 ], [ 3, "33.4.3 Reduced media-independent interface: RMII", 1134 ], [ 4, "RMII clock sources", 1135 ], [ 3, "33.4.4 MII/RMII selection", 1135 ], [ 4, "MII/RMII internal clock scheme", 1136 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.1 MAC 802.3 frame format", 1137 ], [ 3, "33.5.2 MAC frame transmission", 1140 ], [ 4, "Automatic CRC and pad generation", 1141 ], [ 4, "Transmit protocol", 1141 ], [ 4, "Transmit scheduler", 1142 ], [ 4, "Transmit flow control", 1142 ], [ 4, "Retransmission during collision", 1143 ], [ 4, "Transmit FIFO flush operation", 1143 ], [ 4, "Transmit status word", 1144 ], [ 4, "Transmit checksum offload", 1144 ], [ 4, "MII/RMII transmit bit order", 1146 ], [ 4, "MII/RMII transmit timing diagrams", 1146 ], [ 3, "33.5.3 MAC frame reception", 1147 ], [ 4, "Receive protocol", 1148 ], [ 4, "Receive CRC: automatic CRC and pad stripping", 1148 ], [ 4, "Receive checksum offload", 1148 ], [ 4, "Receive frame controller", 1149 ], [ 4, "Receive flow control", 1150 ], [ 4, "Receive operation multiframe handling", 1150 ], [ 4, "Error handling", 1150 ], [ 4, "Receive status word", 1151 ], [ 4, "Frame length interface", 1151 ], [ 4, "MII/RMII receive bit order", 1151 ], [ 3, "33.5.4 MAC interrupts", 1152 ], [ 3, "33.5.5 MAC filtering", 1153 ], [ 4, "Address filtering", 1153 ], [ 4, "Unicast destination address filter", 1153 ], [ 4, "Multicast destination address filter", 1154 ], [ 4, "Hash or perfect address filter", 1154 ], [ 4, "Broadcast address filter", 1154 ], [ 4, "Unicast source address filter", 1154 ], [ 4, "Inverse filtering operation", 1154 ], [ 3, "33.5.6 MAC loopback mode", 1156 ], [ 3, "33.5.7 MAC management counters: MMC", 1156 ], [ 4, "Good transmitted and received frames", 1156 ], [ 3, "33.5.8 Power management: PMT", 1157 ], [ 4, "Remote wake-up frame filter register", 1157 ], [ 4, "Remote wake-up frame detection", 1158 ], [ 4, "Magic packet detection", 1158 ], [ 4, "System consideration during power-down", 1159 ], [ 3, "33.5.9 Precision time protocol (IEEE1588 PTP)", 1160 ], [ 4, "Reference timing source", 1161 ], [ 4, "Transmission of frames with the PTP feature", 1162 ], [ 4, "Reception of frames with the PTP feature", 1162 ], [ 4, "System Time correction methods", 1162 ], [ 4, "Programming steps for system time generation initialization", 1164 ], [ 4, "Programming steps for system time update in the Coarse correction method", 1165 ], [ 4, "Programming steps for system time update in the Fine correction method", 1165 ], [ 4, "PTP trigger internal connection with TIM2", 1165 ], [ 4, "PTP pulse-per-second output signal", 1166 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.1 Initialization of a transfer using DMA", 1167 ], [ 3, "33.6.2 Host bus burst access", 1167 ], [ 3, "33.6.3 Host data buffer alignment", 1168 ], [ 3, "33.6.4 Buffer size calculations", 1168 ], [ 3, "33.6.5 DMA arbiter", 1169 ], [ 3, "33.6.6 Error response to DMA", 1169 ], [ 3, "33.6.7 Tx DMA configuration", 1169 ], [ 4, "TxDMA operation: default (non-OSF) mode", 1169 ], [ 4, "TxDMA operation: OSF mode", 1171 ], [ 4, "Transmit frame processing", 1173 ], [ 4, "Transmit polling suspended", 1174 ], [ 4, "Normal Tx DMA descriptors", 1174 ], [ 4, "Enhanced Tx DMA descriptors", 1179 ], [ 3, "33.6.8 Rx DMA configuration", 1181 ], [ 4, "Receive descriptor acquisition", 1183 ], [ 4, "Receive frame processing", 1183 ], [ 4, "Receive process suspended", 1183 ], [ 4, "Normal Rx DMA descriptors", 1184 ], [ 4, "Enhanced Rx DMA descriptors format with IEEE1588 time stamp", 1189 ], [ 3, "33.6.9 DMA interrupts", 1192 ], [ 2, "33.7 Ethernet interrupts", 1193 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC configuration register (ETH_MACCR)", 1194 ], [ 4, "Ethernet MAC frame filter register (ETH_MACFFR)", 1197 ], [ 4, "Ethernet MAC hash table high register (ETH_MACHTHR)", 1198 ], [ 4, "Ethernet MAC hash table low register (ETH_MACHTLR)", 1199 ], [ 4, "Ethernet MAC MII address register (ETH_MACMIIAR)", 1199 ], [ 4, "Ethernet MAC MII data register (ETH_MACMIIDR)", 1200 ], [ 4, "Ethernet MAC flow control register (ETH_MACFCR)", 1201 ], [ 4, "Ethernet MAC VLAN tag register (ETH_MACVLANTR)", 1202 ], [ 4, "Ethernet MAC remote wake-up frame filter register (ETH_MACRWUFFR)", 1203 ], [ 4, "Ethernet MAC PMT control and status register (ETH_MACPMTCSR)", 1204 ], [ 4, "Ethernet MAC debug register (ETH_MACDBGR)", 1205 ], [ 4, "Ethernet MAC interrupt status register (ETH_MACSR)", 1207 ], [ 4, "Ethernet MAC interrupt mask register (ETH_MACIMR)", 1208 ], [ 4, "Ethernet MAC address 0 high register (ETH_MACA0HR)", 1208 ], [ 4, "Ethernet MAC address 0 low register (ETH_MACA0LR)", 1209 ], [ 4, "Ethernet MAC address 1 high register (ETH_MACA1HR)", 1209 ], [ 4, "Ethernet MAC address1 low register (ETH_MACA1LR)", 1210 ], [ 4, "Ethernet MAC address 2 high register (ETH_MACA2HR)", 1210 ], [ 4, "Ethernet MAC address 2 low register (ETH_MACA2LR)", 1211 ], [ 4, "Ethernet MAC address 3 high register (ETH_MACA3HR)", 1212 ], [ 4, "Ethernet MAC address 3 low register (ETH_MACA3LR)", 1212 ], [ 3, "33.8.2 MMC register description", 1213 ], [ 4, "Ethernet MMC control register (ETH_MMCCR)", 1213 ], [ 4, "Ethernet MMC receive interrupt register (ETH_MMCRIR)", 1213 ], [ 4, "Ethernet MMC transmit interrupt register (ETH_MMCTIR)", 1214 ], [ 4, "Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)", 1215 ], [ 4, "Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)", 1216 ], [ 4, "Ethernet MMC transmitted good frames after a single collision counter register (ETH_MMCTGFSCCR)", 1216 ], [ 4, "Ethernet MMC transmitted good frames after more than a single collision counter register (ETH_MMCTGFMSCCR)", 1217 ], [ 4, "Ethernet MMC transmitted good frames counter register (ETH_MMCTGFCR)", 1217 ], [ 4, "Ethernet MMC received frames with CRC error counter register (ETH_MMCRFCECR)", 1217 ], [ 4, "Ethernet MMC received frames with alignment error counter register (ETH_MMCRFAECR)", 1218 ], [ 4, "MMC received good unicast frames counter register (ETH_MMCRGUFCR)", 1218 ], [ 3, "33.8.3 IEEE 1588 time stamp registers", 1218 ], [ 4, "Ethernet PTP time stamp control register (ETH_PTPTSCR)", 1218 ], [ 4, "Ethernet PTP subsecond increment register (ETH_PTPSSIR)", 1221 ], [ 4, "Ethernet PTP time stamp high register (ETH_PTPTSHR)", 1221 ], [ 4, "Ethernet PTP time stamp low register (ETH_PTPTSLR)", 1222 ], [ 4, "Ethernet PTP time stamp high update register (ETH_PTPTSHUR)", 1222 ], [ 4, "Ethernet PTP time stamp low update register (ETH_PTPTSLUR)", 1223 ], [ 4, "Ethernet PTP time stamp addend register (ETH_PTPTSAR)", 1223 ], [ 4, "Ethernet PTP target time high register (ETH_PTPTTHR)", 1224 ], [ 4, "Ethernet PTP target time low register (ETH_PTPTTLR)", 1224 ], [ 4, "Ethernet PTP time stamp status register (ETH_PTPTSSR)", 1224 ], [ 4, "Ethernet PTP PPS control register (ETH_PTPPPSCR)", 1225 ], [ 3, "33.8.4 DMA register description", 1226 ], [ 4, "Ethernet DMA bus mode register (ETH_DMABMR)", 1226 ], [ 4, "Ethernet DMA transmit poll demand register (ETH_DMATPDR)", 1227 ], [ 4, "EHERNET DMA receive poll demand register (ETH_DMARPDR)", 1228 ], [ 4, "Ethernet DMA receive descriptor list address register (ETH_DMARDLAR)", 1228 ], [ 4, "Ethernet DMA transmit descriptor list address register (ETH_DMATDLAR)", 1229 ], [ 4, "Ethernet DMA status register (ETH_DMASR)", 1229 ], [ 4, "Ethernet DMA operation mode register (ETH_DMAOMR)", 1232 ], [ 4, "Ethernet DMA interrupt enable register (ETH_DMAIER)", 1235 ], [ 4, "Ethernet DMA missed frame and buffer overflow counter register (ETH_DMAMFBOCR)", 1237 ], [ 4, "Ethernet DMA receive status watchdog timer register (ETH_DMARSWTR)", 1237 ], [ 4, "Ethernet DMA current host transmit descriptor register (ETH_DMACHTDR)", 1238 ], [ 4, "Ethernet DMA current host receive descriptor register (ETH_DMACHRDR)", 1238 ], [ 4, "Ethernet DMA current host transmit buffer address register (ETH_DMACHTBAR)", 1238 ], [ 4, "Ethernet DMA current host receive buffer address register (ETH_DMACHRBAR)", 1239 ], [ 3, "33.8.5 Ethernet register maps", 1239 ], [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.1 OTG_FS introduction", 1243 ], [ 2, "34.2 OTG_FS main features", 1244 ], [ 3, "34.2.1 General features", 1244 ], [ 3, "34.2.2 Host-mode features", 1245 ], [ 3, "34.2.3 Peripheral-mode features", 1245 ], [ 2, "34.3 OTG_FS functional description", 1246 ], [ 3, "34.3.1 OTG pins", 1246 ], [ 3, "34.3.2 OTG full-speed core", 1246 ], [ 3, "34.3.3 Full-speed OTG PHY", 1247 ], [ 2, "34.4 OTG dual role device (DRD)", 1248 ], [ 3, "34.4.1 ID line detection", 1248 ], [ 3, "34.4.2 HNP dual role device", 1248 ], [ 3, "34.4.3 SRP dual role device", 1249 ], [ 2, "34.5 USB peripheral", 1249 ], [ 3, "34.5.1 SRP-capable peripheral", 1250 ], [ 3, "34.5.2 Peripheral states", 1250 ], [ 4, "Powered state", 1250 ], [ 4, "Soft disconnect", 1251 ], [ 4, "Default state", 1251 ], [ 4, "Suspended state", 1251 ], [ 3, "34.5.3 Peripheral endpoints", 1251 ], [ 4, "Endpoint control", 1252 ], [ 4, "Endpoint transfer", 1252 ], [ 4, "Endpoint status/interrupt", 1253 ], [ 2, "34.6 USB host", 1253 ], [ 3, "34.6.1 SRP-capable host", 1254 ], [ 3, "34.6.2 USB host states", 1254 ], [ 4, "Host port power", 1254 ], [ 4, "VBUS valid", 1255 ], [ 4, "Host detection of a peripheral connection", 1255 ], [ 4, "Host detection of peripheral a disconnection", 1255 ], [ 4, "Host enumeration", 1255 ], [ 4, "Host suspend", 1256 ], [ 3, "34.6.3 Host channels", 1256 ], [ 4, "Host channel control", 1256 ], [ 4, "Host channel transfer", 1256 ], [ 4, "Host channel status/interrupt", 1257 ], [ 3, "34.6.4 Host scheduler", 1257 ], [ 2, "34.7 SOF trigger", 1258 ], [ 3, "34.7.1 Host SOFs", 1258 ], [ 3, "34.7.2 Peripheral SOFs", 1259 ], [ 2, "34.8 OTG low-power modes", 1259 ], [ 2, "34.9 Dynamic update of the OTG_FS_HFIR register", 1260 ], [ 2, "34.10 USB data FIFOs", 1261 ], [ 2, "34.11 Peripheral FIFO architecture", 1262 ], [ 3, "34.11.1 Peripheral Rx FIFO", 1262 ], [ 3, "34.11.2 Peripheral Tx FIFOs", 1263 ], [ 2, "34.12 Host FIFO architecture", 1263 ], [ 3, "34.12.1 Host Rx FIFO", 1263 ], [ 3, "34.12.2 Host Tx FIFOs", 1264 ], [ 2, "34.13 FIFO RAM allocation", 1264 ], [ 3, "34.13.1 Device mode", 1264 ], [ 3, "34.13.2 Host mode", 1265 ], [ 4, "Receive FIFO RAM allocation", 1265 ], [ 4, "Transmit FIFO RAM allocation", 1265 ], [ 2, "34.14 USB system performance", 1265 ], [ 2, "34.15 OTG_FS interrupts", 1266 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.1 CSR memory map", 1269 ], [ 4, "Global CSR map", 1269 ], [ 4, "Host-mode CSR map", 1270 ], [ 4, "Device-mode CSR map", 1271 ], [ 4, "Data FIFO (DFIFO) access register map", 1272 ], [ 4, "Power and clock gating CSR map", 1273 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS control and status register (OTG_FS_GOTGCTL)", 1274 ], [ 4, "OTG_FS interrupt register (OTG_FS_GOTGINT)", 1275 ], [ 4, "OTG_FS AHB configuration register (OTG_FS_GAHBCFG)", 1277 ], [ 4, "OTG_FS USB configuration register (OTG_FS_GUSBCFG)", 1278 ], [ 4, "OTG_FS reset register (OTG_FS_GRSTCTL)", 1280 ], [ 4, "OTG_FS core interrupt register (OTG_FS_GINTSTS)", 1282 ], [ 4, "OTG_FS interrupt mask register (OTG_FS_GINTMSK)", 1286 ], [ 4, "OTG_FS Receive status debug read/OTG status read and pop registers (OTG_FS_GRXSTSR/OTG_FS_GRXSTSP)", 1289 ], [ 4, "OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)", 1290 ], [ 4, "OTG_FS Host non-periodic transmit FIFO size register (OTG_FS_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_FS_DIEPTXF0)", 1291 ], [ 4, "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_HNPTXSTS)", 1291 ], [ 4, "OTG_FS general core configuration register (OTG_FS_GCCFG)", 1292 ], [ 4, "OTG_FS core ID register (OTG_FS_CID)", 1293 ], [ 4, "OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)", 1294 ], [ 4, "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXFx) (x = 1..3, where x is the FIFO_number)", 1294 ], [ 3, "34.16.3 Host-mode registers", 1295 ], [ 4, "OTG_FS Host configuration register (OTG_FS_HCFG)", 1295 ], [ 4, "OTG_FS Host frame interval register (OTG_FS_HFIR)", 1295 ], [ 4, "OTG_FS Host frame number/frame time remaining register (OTG_FS_HFNUM)", 1296 ], [ 4, "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)", 1296 ], [ 4, "OTG_FS Host all channels interrupt register (OTG_FS_HAINT)", 1297 ], [ 4, "OTG_FS Host all channels interrupt mask register (OTG_FS_HAINTMSK)", 1298 ], [ 4, "OTG_FS Host port control and status register (OTG_FS_HPRT)", 1298 ], [ 4, "OTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx) (x = 0..7, where x = Channel_number)", 1301 ], [ 4, "OTG_FS Host channel-x interrupt register (OTG_FS_HCINTx) (x = 0..7, where x = Channel_number)", 1302 ], [ 4, "OTG_FS Host channel-x interrupt mask register (OTG_FS_HCINTMSKx) (x = 0..7, where x = Channel_number)", 1303 ], [ 4, "OTG_FS Host channel-x transfer size register (OTG_FS_HCTSIZx) (x = 0..7, where x = Channel_number)", 1304 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device configuration register (OTG_FS_DCFG)", 1305 ], [ 4, "OTG_FS device control register (OTG_FS_DCTL)", 1306 ], [ 4, "OTG_FS device status register (OTG_FS_DSTS)", 1307 ], [ 4, "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)", 1308 ], [ 4, "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)", 1309 ], [ 4, "OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)", 1310 ], [ 4, "OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)", 1311 ], [ 4, "OTG_FS device VBUS discharge time register (OTG_FS_DVBUSDIS)", 1311 ], [ 4, "OTG_FS device VBUS pulsing time register (OTG_FS_DVBUSPULSE)", 1311 ], [ 4, "OTG_FS device IN endpoint FIFO empty interrupt mask register: (OTG_FS_DIEPEMPMSK)", 1312 ], [ 4, "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)", 1312 ], [ 4, "OTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3, where x = Endpoint_number)", 1314 ], [ 4, "OTG_FS device control OUT endpoint 0 control register (OTG_FS_DOEPCTL0)", 1317 ], [ 4, "OTG_FS device endpoint-x control register (OTG_FS_DOEPCTLx) (x = 1..3, where x = Endpoint_number)", 1318 ], [ 4, "OTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) (x = 0..3, where x = Endpoint_number)", 1321 ], [ 4, "OTG_FS device endpoint-x interrupt register (OTG_FS_DOEPINTx) (x = 0..3, where x = Endpoint_number)", 1322 ], [ 4, "OTG_FS device IN endpoint 0 transfer size register (OTG_FS_DIEPTSIZ0)", 1323 ], [ 4, "OTG_FS device OUT endpoint 0 transfer size register (OTG_FS_DOEPTSIZ0)", 1325 ], [ 4, "OTG_FS device endpoint-x transfer size register (OTG_FS_DIEPTSIZx) (x = 1..3, where x = Endpoint_number)", 1326 ], [ 4, "OTG_FS device IN endpoint transmit FIFO status register (OTG_FS_DTXFSTSx) (x = 0..3, where x = Endpoint_number)", 1327 ], [ 4, "OTG_FS device OUT endpoint-x transfer size register (OTG_FS_DOEPTSIZx) (x = 1..3, where x = Endpoint_number)", 1327 ], [ 3, "34.16.5 OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)", 1328 ], [ 3, "34.16.6 OTG_FS register map", 1329 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.1 Core initialization", 1338 ], [ 3, "34.17.2 Host initialization", 1339 ], [ 3, "34.17.3 Device initialization", 1339 ], [ 3, "34.17.4 Host programming model", 1340 ], [ 4, "Channel initialization", 1340 ], [ 4, "Halting a channel", 1340 ], [ 4, "Operational model", 1341 ], [ 3, "34.17.5 Device programming model", 1356 ], [ 4, "Endpoint initialization on USB reset", 1356 ], [ 4, "Endpoint initialization on enumeration completion", 1356 ], [ 4, "Endpoint initialization on SetAddress command", 1357 ], [ 4, "Endpoint initialization on SetConfiguration/SetInterface command", 1357 ], [ 4, "Endpoint activation", 1357 ], [ 4, "Endpoint deactivation", 1358 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "SETUP and OUT data transfers", 1358 ], [ 4, "Examples", 1367 ], [ 4, "IN data transfers", 1368 ], [ 3, "34.17.7 Worst case response time", 1376 ], [ 4, "Choosing the value of TRDT in OTG_FS_GUSBCFG", 1376 ], [ 3, "34.17.8 OTG programming model", 1377 ], [ 4, "A-device session request protocol", 1378 ], [ 4, "B-device session request protocol", 1379 ], [ 4, "A-device host negotiation protocol", 1380 ], [ 4, "B-device host negotiation protocol", 1382 ], [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.1 OTG_HS introduction", 1384 ], [ 2, "35.2 OTG_HS main features", 1384 ], [ 3, "35.2.1 General features", 1385 ], [ 3, "35.2.2 Host-mode features", 1386 ], [ 3, "35.2.3 Peripheral-mode features", 1386 ], [ 2, "35.3 OTG_HS functional description", 1386 ], [ 3, "35.3.1 OTG pins", 1387 ], [ 3, "35.3.2 High-speed OTG PHY", 1387 ], [ 3, "35.3.3 Embedded Full-speed OTG PHY", 1388 ], [ 2, "35.4 OTG dual-role device", 1388 ], [ 3, "35.4.1 ID line detection", 1388 ], [ 3, "35.4.2 HNP dual role device", 1388 ], [ 3, "35.4.3 SRP dual-role device", 1389 ], [ 2, "35.5 USB functional description in peripheral mode", 1389 ], [ 3, "35.5.1 SRP-capable peripheral", 1389 ], [ 3, "35.5.2 Peripheral states", 1390 ], [ 4, "Powered state", 1390 ], [ 4, "Soft disconnect", 1390 ], [ 4, "Default state", 1390 ], [ 4, "Suspended state", 1390 ], [ 3, "35.5.3 Peripheral endpoints", 1391 ], [ 4, "Endpoint controls", 1392 ], [ 4, "Endpoint transfer", 1392 ], [ 4, "Endpoint status/interrupt", 1392 ], [ 2, "35.6 USB functional description on host mode", 1394 ], [ 3, "35.6.1 SRP-capable host", 1394 ], [ 3, "35.6.2 USB host states", 1395 ], [ 4, "Host port power", 1395 ], [ 4, "VBUS valid", 1395 ], [ 4, "Detection of peripheral connection by the host", 1395 ], [ 4, "Detection of peripheral disconnection by the host", 1395 ], [ 4, "Host enumeration", 1395 ], [ 4, "Host suspend", 1396 ], [ 3, "35.6.3 Host channels", 1396 ], [ 4, "Host channel controls", 1397 ], [ 4, "Host channel transfer", 1397 ], [ 4, "Host channel status/interrupt", 1397 ], [ 3, "35.6.4 Host scheduler", 1398 ], [ 2, "35.7 SOF trigger", 1399 ], [ 3, "35.7.1 Host SOFs", 1399 ], [ 3, "35.7.2 Peripheral SOFs", 1399 ], [ 2, "35.8 OTG_HS low-power modes", 1400 ], [ 2, "35.9 Dynamic update of the OTG_HS_HFIR register", 1401 ], [ 2, "35.10 FIFO RAM allocation", 1402 ], [ 3, "35.10.1 Peripheral mode", 1402 ], [ 4, "Receive FIFO RAM", 1402 ], [ 4, "Transmit FIFO RAM", 1402 ], [ 3, "35.10.2 Host mode", 1402 ], [ 4, "Receive FIFO RAM", 1402 ], [ 4, "Transmit FIFO RAM", 1402 ], [ 2, "35.11 OTG_HS interrupts", 1403 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.1 CSR memory map", 1405 ], [ 4, "Global CSR map", 1406 ], [ 4, "Host-mode CSR map", 1407 ], [ 4, "Device-mode CSR map", 1408 ], [ 4, "Data FIFO (DFIFO) access register map", 1410 ], [ 4, "Power and clock gating CSR map", 1410 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS control and status register (OTG_HS_GOTGCTL)", 1411 ], [ 4, "OTG_HS interrupt register (OTG_HS_GOTGINT)", 1412 ], [ 4, "OTG_HS AHB configuration register (OTG_HS_GAHBCFG)", 1414 ], [ 4, "OTG_HS USB configuration register (OTG_HS_GUSBCFG)", 1415 ], [ 4, "OTG_HS reset register (OTG_HS_GRSTCTL)", 1418 ], [ 4, "OTG_HS core interrupt register (OTG_HS_GINTSTS)", 1421 ], [ 4, "OTG_HS interrupt mask register (OTG_HS_GINTMSK)", 1425 ], [ 4, "OTG_HS Receive status debug read/OTG status read and pop registers (OTG_HS_GRXSTSR/OTG_HS_GRXSTSP)", 1428 ], [ 4, "OTG_HS Receive FIFO size register (OTG_HS_GRXFSIZ)", 1429 ], [ 4, "OTG_HS nonperiodic transmit FIFO size/Endpoint 0 transmit FIFO size register (OTG_HS_GNPTXFSIZ/OTG_HS_TX0FSIZ)", 1430 ], [ 4, "OTG_HS nonperiodic transmit FIFO/queue status register (OTG_HS_GNPTXSTS)", 1430 ], [ 4, "OTG_HS general core configuration register (OTG_HS_GCCFG)", 1431 ], [ 4, "OTG_HS core ID register (OTG_HS_CID)", 1432 ], [ 4, "OTG_HS Host periodic transmit FIFO size register (OTG_HS_HPTXFSIZ)", 1432 ], [ 4, "OTG_HS device IN endpoint transmit FIFO size register (OTG_HS_DIEPTXFx) (x = 1..5, where x is the FIFO_number)", 1433 ], [ 3, "35.12.3 Host-mode registers", 1433 ], [ 4, "OTG_HS host configuration register (OTG_HS_HCFG)", 1433 ], [ 4, "OTG_HS Host frame interval register (OTG_HS_HFIR)", 1435 ], [ 4, "OTG_HS host frame number/frame time remaining register (OTG_HS_HFNUM)", 1435 ], [ 4, "OTG_HS_Host periodic transmit FIFO/queue status register (OTG_HS_HPTXSTS)", 1436 ], [ 4, "OTG_HS Host all channels interrupt register (OTG_HS_HAINT)", 1437 ], [ 4, "OTG_HS host all channels interrupt mask register (OTG_HS_HAINTMSK)", 1437 ], [ 4, "OTG_HS host port control and status register (OTG_HS_HPRT)", 1438 ], [ 4, "OTG_HS host channel-x characteristics register (OTG_HS_HCCHARx) (x = 0..11, where x = Channel_number)", 1440 ], [ 4, "OTG_HS host channel-x split control register (OTG_HS_HCSPLTx) (x = 0..11, where x = Channel_number)", 1442 ], [ 4, "OTG_HS host channel-x interrupt register (OTG_HS_HCINTx) (x = 0..11, where x = Channel_number)", 1443 ], [ 4, "OTG_HS host channel-x interrupt mask register (OTG_HS_HCINTMSKx) (x = 0..11, where x = Channel_number)", 1444 ], [ 4, "OTG_HS host channel-x transfer size register (OTG_HS_HCTSIZx) (x = 0..11, where x = Channel_number)", 1445 ], [ 4, "OTG_HS host channel-x DMA address register (OTG_HS_HCDMAx) (x = 0..11, where x = Channel_number)", 1446 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device configuration register (OTG_HS_DCFG)", 1446 ], [ 4, "OTG_HS device control register (OTG_HS_DCTL)", 1448 ], [ 4, "OTG_HS device status register (OTG_HS_DSTS)", 1450 ], [ 4, "OTG_HS device IN endpoint common interrupt mask register (OTG_HS_DIEPMSK)", 1451 ], [ 4, "OTG_HS device OUT endpoint common interrupt mask register (OTG_HS_DOEPMSK)", 1452 ], [ 4, "OTG_HS device all endpoints interrupt register (OTG_HS_DAINT)", 1453 ], [ 4, "OTG_HS all endpoints interrupt mask register (OTG_HS_DAINTMSK)", 1454 ], [ 4, "OTG_HS device VBUS discharge time register (OTG_HS_DVBUSDIS)", 1454 ], [ 4, "OTG_HS device VBUS pulsing time register (OTG_HS_DVBUSPULSE)", 1455 ], [ 4, "OTG_HS Device threshold control register (OTG_HS_DTHRCTL)", 1456 ], [ 4, "OTG_HS device IN endpoint FIFO empty interrupt mask register: (OTG_HS_DIEPEMPMSK)", 1457 ], [ 4, "OTG_HS device each endpoint interrupt register (OTG_HS_DEACHINT)", 1457 ], [ 4, "OTG_HS device each endpoint interrupt register mask (OTG_HS_DEACHINTMSK)", 1458 ], [ 4, "OTG_HS device each in endpoint-1 interrupt register (OTG_HS_DIEPEACHMSK1)", 1458 ], [ 4, "OTG_HS device each OUT endpoint-1 interrupt register (OTG_HS_DOEPEACHMSK1)", 1459 ], [ 4, "OTG device endpoint-x control register (OTG_HS_DIEPCTLx) (x = 0..5, where x = Endpoint_number)", 1460 ], [ 4, "OTG_HS device control OUT endpoint 0 control register (OTG_HS_DOEPCTL0)", 1463 ], [ 4, "OTG_HS device endpoint-x control register (OTG_HS_DOEPCTLx) (x = 1..5, where x = Endpoint_number)", 1464 ], [ 4, "OTG_HS device endpoint-x interrupt register (OTG_HS_DIEPINTx) (x = 0..5, where x = Endpoint_number)", 1467 ], [ 4, "OTG_HS device endpoint-x interrupt register (OTG_HS_DOEPINTx) (x = 0..5, where x = Endpoint_number)", 1469 ], [ 4, "OTG_HS device IN endpoint 0 transfer size register (OTG_HS_DIEPTSIZ0)", 1470 ], [ 4, "OTG_HS device OUT endpoint 0 transfer size register (OTG_HS_DOEPTSIZ0)", 1471 ], [ 4, "OTG_HS device endpoint-x transfer size register (OTG_HS_DIEPTSIZx) (x = 1..5, where x = Endpoint_number)", 1472 ], [ 4, "OTG_HS device IN endpoint transmit FIFO status register (OTG_HS_DTXFSTSx) (x = 0..5, where x = Endpoint_number)", 1473 ], [ 4, "OTG_HS device endpoint-x transfer size register (OTG_HS_DOEPTSIZx) (x = 1..5, where x = Endpoint_number)", 1473 ], [ 4, "OTG_HS device endpoint-x DMA address register (OTG_HS_DIEPDMAx / OTG_HS_DOEPDMAx) (x = 0..5, where x = Endpoint_number)", 1474 ], [ 3, "35.12.5 OTG_HS power and clock gating control register (OTG_HS_PCGCCTL)", 1475 ], [ 3, "35.12.6 OTG_HS register map", 1475 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.1 Core initialization", 1490 ], [ 3, "35.13.2 Host initialization", 1491 ], [ 3, "35.13.3 Device initialization", 1492 ], [ 3, "35.13.4 DMA mode", 1492 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Channel initialization", 1492 ], [ 4, "Halting a channel", 1493 ], [ 4, "Ping protocol", 1494 ], [ 4, "Operational model", 1494 ], [ 3, "35.13.6 Device programming model", 1518 ], [ 4, "Endpoint initialization on USB reset", 1518 ], [ 4, "Endpoint initialization on enumeration completion", 1519 ], [ 4, "Endpoint initialization on SetAddress command", 1519 ], [ 4, "Endpoint initialization on SetConfiguration/SetInterface command", 1519 ], [ 4, "Endpoint activation", 1520 ], [ 4, "Endpoint deactivation", 1520 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "SETUP and OUT data transfers", 1520 ], [ 4, "Examples", 1530 ], [ 4, "IN data transfers", 1531 ], [ 3, "35.13.8 Worst case response time", 1539 ], [ 4, "Choosing the value of TRDT in OTG_HS_GUSBCFG", 1539 ], [ 3, "35.13.9 OTG programming model", 1541 ], [ 4, "A-device session request protocol", 1541 ], [ 4, "B-device session request protocol", 1542 ], [ 4, "A-device host negotiation protocol", 1543 ], [ 4, "B-device host negotiation protocol", 1544 ], [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.1 FSMC main features", 1547 ], [ 2, "36.2 Block diagram", 1548 ], [ 2, "36.3 AHB interface", 1548 ], [ 3, "36.3.1 Supported memories and transactions", 1549 ], [ 4, "General transaction rules", 1549 ], [ 4, "Configuration registers", 1550 ], [ 2, "36.4 External device address mapping", 1550 ], [ 3, "36.4.1 NOR/PSRAM address mapping", 1550 ], [ 4, "Wrap support for NOR flash/PSRAM", 1551 ], [ 3, "36.4.2 NAND/PC Card address mapping", 1551 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.1 External memory interface signals", 1553 ], [ 4, "NOR flash, nonmultiplexed I/Os", 1553 ], [ 4, "NOR flash, multiplexed I/Os", 1554 ], [ 4, "PSRAM/SRAM, nonmultiplexed I/Os", 1554 ], [ 3, "36.5.2 Supported memories and transactions", 1555 ], [ 3, "36.5.3 General timing rules", 1556 ], [ 4, "Signals synchronization", 1556 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "Asynchronous static memories (NOR flash memory, PSRAM, SRAM)", 1557 ], [ 4, "Mode 1 - SRAM/PSRAM (CRAM)", 1557 ], [ 4, "Mode A - SRAM/PSRAM (CRAM) OE toggling", 1559 ], [ 4, "Mode 2/B - NOR flash", 1562 ], [ 4, "Mode C - NOR flash - OE toggling", 1565 ], [ 4, "Mode D - asynchronous access with extended address", 1567 ], [ 4, "Muxed mode - multiplexed asynchronous access to NOR flash memory", 1570 ], [ 4, "WAIT management in asynchronous accesses", 1571 ], [ 3, "36.5.5 Synchronous transactions", 1574 ], [ 4, "Data latency versus NOR flash latency", 1574 ], [ 4, "Single-burst transfer", 1574 ], [ 4, "Cross boundary page for Cellular RAM 1.5", 1574 ], [ 4, "Wait management", 1574 ], [ 3, "36.5.6 NOR/PSRAM control registers", 1580 ], [ 4, "SRAM/NOR-flash chip-select control registers 1..4 (FSMC_BCR1..4)", 1580 ], [ 4, "SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4)", 1583 ], [ 4, "SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4)", 1586 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.1 External memory interface signals", 1588 ], [ 4, "8-bit NAND Flash", 1588 ], [ 4, "16-bit NAND Flash", 1589 ], [ 4, "16-bit PC Card", 1589 ], [ 3, "36.6.2 NAND Flash / PC Card supported memories and transactions", 1590 ], [ 3, "36.6.3 Timing diagrams for NAND and PC Card", 1590 ], [ 3, "36.6.4 NAND Flash operations", 1591 ], [ 3, "36.6.5 NAND Flash prewait functionality", 1592 ], [ 3, "36.6.6 Computation of the error correction code (ECC) in NAND Flash memory", 1593 ], [ 3, "36.6.7 PC Card/CompactFlash operations", 1594 ], [ 4, "Address spaces and memory accesses", 1594 ], [ 4, "Wait Feature", 1595 ], [ 3, "36.6.8 NAND Flash/PC Card control registers", 1596 ], [ 4, "PC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4)", 1596 ], [ 4, "FIFO status and interrupt register 2..4 (FSMC_SR2..4)", 1597 ], [ 4, "Common memory space timing register 2..4 (FSMC_PMEM2..4)", 1598 ], [ 4, "Attribute memory space timing registers 2..4 (FSMC_PATT2..4)", 1599 ], [ 4, "I/O space timing register 4 (FSMC_PIO4)", 1600 ], [ 4, "ECC result registers 2/3 (FSMC_ECCR2/3)", 1601 ], [ 3, "36.6.9 FSMC register map", 1603 ], [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.1 FMC main features", 1605 ], [ 2, "37.2 Block diagram", 1606 ], [ 2, "37.3 AHB interface", 1607 ], [ 3, "37.3.1 Supported memories and transactions", 1608 ], [ 4, "General transaction rules", 1608 ], [ 4, "Configuration registers", 1609 ], [ 2, "37.4 External device address mapping", 1609 ], [ 3, "37.4.1 NOR/PSRAM address mapping", 1610 ], [ 4, "Wrap support for NOR Flash/PSRAM", 1611 ], [ 3, "37.4.2 NAND Flash memory/PC Card address mapping", 1611 ], [ 3, "37.4.3 SDRAM address mapping", 1612 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.1 External memory interface signals", 1616 ], [ 4, "NOR Flash memory, non-multiplexed I/Os", 1617 ], [ 4, "NOR Flash memory, 16-bit multiplexed I/Os", 1617 ], [ 4, "PSRAM/SRAM, non-multiplexed I/Os", 1617 ], [ 4, "PSRAM, 16-bit multiplexed I/Os", 1618 ], [ 3, "37.5.2 Supported memories and transactions", 1618 ], [ 3, "37.5.3 General timing rules", 1620 ], [ 4, "Signals synchronization", 1620 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "Asynchronous static memories (NOR Flash, PSRAM, SRAM)", 1620 ], [ 4, "Mode 1 - SRAM/PSRAM (CRAM)", 1621 ], [ 4, "Mode A - SRAM/PSRAM (CRAM) OE toggling", 1623 ], [ 4, "Mode 2/B - NOR Flash", 1626 ], [ 4, "Mode C - NOR Flash - OE toggling", 1629 ], [ 4, "Mode D - asynchronous access with extended address", 1631 ], [ 4, "Muxed mode - multiplexed asynchronous access to NOR Flash memory", 1634 ], [ 4, "WAIT management in asynchronous accesses", 1635 ], [ 3, "37.5.5 Synchronous transactions", 1637 ], [ 4, "Data latency versus NOR memory latency", 1637 ], [ 4, "Single-burst transfer", 1638 ], [ 4, "Cross boundary page for Cellular RAM 1.5", 1638 ], [ 4, "Wait management", 1638 ], [ 3, "37.5.6 NOR/PSRAM controller registers", 1643 ], [ 4, "SRAM/NOR-Flash chip-select control registers 1..4 (FMC_BCR1..4)", 1643 ], [ 4, "SRAM/NOR-Flash chip-select timing registers 1..4 (FMC_BTR1..4)", 1645 ], [ 4, "SRAM/NOR-Flash write timing registers 1..4 (FMC_BWTR1..4)", 1649 ], [ 2, "37.6 NAND Flash/PC Card controller", 1650 ], [ 3, "37.6.1 External memory interface signals", 1651 ], [ 4, "8-bit NAND Flash memory", 1651 ], [ 4, "16-bit NAND Flash memory", 1652 ], [ 3, "37.6.2 NAND Flash / PC Card supported memories and transactions", 1653 ], [ 3, "37.6.3 Timing diagrams for NAND Flash memory and PC Card", 1653 ], [ 3, "37.6.4 NAND Flash operations", 1654 ], [ 3, "37.6.5 NAND Flash prewait functionality", 1655 ], [ 3, "37.6.6 Computation of the error correction code (ECC) in NAND Flash memory", 1656 ], [ 3, "37.6.7 PC Card/CompactFlash operations", 1657 ], [ 4, "Address spaces and memory accesses", 1657 ], [ 4, "Wait feature", 1658 ], [ 3, "37.6.8 NAND Flash/PC Card controller registers", 1659 ], [ 4, "PC Card/NAND Flash control registers 2..4 (FMC_PCR2..4)", 1659 ], [ 4, "FIFO status and interrupt register 2..4 (FMC_SR2..4)", 1660 ], [ 4, "Common memory space timing register 2..4 (FMC_PMEM2..4)", 1661 ], [ 4, "Attribute memory space timing registers 2..4 (FMC_PATT2..4)", 1662 ], [ 4, "I/O space timing register 4 (FMC_PIO4)", 1663 ], [ 4, "ECC result registers 2/3 (FMC_ECCR2/3)", 1665 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.1 SDRAM controller main features", 1666 ], [ 3, "37.7.2 SDRAM External memory interface signals", 1666 ], [ 3, "37.7.3 SDRAM controller functional description", 1667 ], [ 4, "SDRAM initialization", 1667 ], [ 4, "SDRAM controller write cycle", 1668 ], [ 4, "SDRAM controller read cycle", 1669 ], [ 4, "Row and bank boundary management", 1671 ], [ 4, "SDRAM controller refresh cycle", 1673 ], [ 3, "37.7.4 Low power modes", 1674 ], [ 4, "Self-refresh mode", 1674 ], [ 4, "Power-down mode", 1675 ], [ 3, "37.7.5 SDRAM controller registers", 1677 ], [ 4, "SDRAM Control registers 1,2 (FMC_SDCR1,2)", 1677 ], [ 4, "SDRAM Timing registers 1,2 (FMC_SDTR1,2)", 1678 ], [ 4, "SDRAM Command Mode register (FMC_SDCMR)", 1680 ], [ 4, "SDRAM Refresh Timer register (FMC_SDRTR)", 1681 ], [ 4, "Example", 1681 ], [ 2, "37.8 FMC register map", 1683 ], [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.1 Overview", 1686 ], [ 2, "38.2 Reference Arm® documentation", 1687 ], [ 2, "38.3 SWJ debug port (serial wire and JTAG)", 1687 ], [ 3, "38.3.1 Mechanism to select the JTAG-DP or the SW-DP", 1688 ], [ 2, "38.4 Pinout and debug port pins", 1688 ], [ 3, "38.4.1 SWJ debug port pins", 1689 ], [ 3, "38.4.2 Flexible SWJ-DP pin assignment", 1689 ], [ 3, "38.4.3 Internal pull-up and pull-down on JTAG pins", 1689 ], [ 3, "38.4.4 Using serial wire and releasing the unused debug pins as GPIOs", 1691 ], [ 2, "38.5 STM32F4xx JTAG TAP connection", 1691 ], [ 2, "38.6 ID codes and locking mechanism", 1693 ], [ 3, "38.6.1 MCU device ID code", 1693 ], [ 4, "DBGMCU_IDCODE", 1693 ], [ 3, "38.6.2 Boundary scan TAP", 1694 ], [ 4, "JTAG ID code", 1694 ], [ 3, "38.6.3 Cortex®-M4 with FPU TAP", 1694 ], [ 3, "38.6.4 Cortex®-M4 with FPU JEDEC-106 ID code", 1694 ], [ 2, "38.7 JTAG debug port", 1694 ], [ 2, "38.8 SW debug port", 1696 ], [ 3, "38.8.1 SW protocol introduction", 1696 ], [ 3, "38.8.2 SW protocol sequence", 1696 ], [ 3, "38.8.3 SW-DP state machine (reset, idle states, ID code)", 1697 ], [ 3, "38.8.4 DP and AP read/write accesses", 1697 ], [ 3, "38.8.5 SW-DP registers", 1698 ], [ 3, "38.8.6 SW-AP registers", 1698 ], [ 2, "38.9 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP", 1699 ], [ 3, "Features:", 1699 ], [ 2, "38.10 Core debug", 1700 ], [ 2, "38.11 Capability of the debugger host to connect under system reset", 1701 ], [ 2, "38.12 FPB (Flash patch breakpoint)", 1701 ], [ 2, "38.13 DWT (data watchpoint trigger)", 1702 ], [ 2, "38.14 ITM (instrumentation trace macrocell)", 1702 ], [ 3, "38.14.1 General description", 1702 ], [ 3, "38.14.2 Time stamp packets, synchronization and overflow packets", 1702 ], [ 4, "Example of configuration", 1704 ], [ 2, "38.15 ETM (Embedded Trace Macrocell™)", 1704 ], [ 3, "38.15.1 ETM general description", 1704 ], [ 3, "38.15.2 ETM signal protocol and packet types", 1704 ], [ 3, "38.15.3 Main ETM registers", 1705 ], [ 3, "38.15.4 ETM configuration example", 1705 ], [ 2, "38.16 MCU debug component (DBGMCU)", 1705 ], [ 3, "38.16.1 Debug support for low-power modes", 1705 ], [ 3, "38.16.2 Debug support for timers, watchdog, bxCAN and I2C", 1706 ], [ 3, "38.16.3 Debug MCU configuration register", 1706 ], [ 4, "DBGMCU_CR register", 1706 ], [ 3, "38.16.4 Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)", 1708 ], [ 3, "38.16.5 Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ)", 1709 ], [ 2, "38.17 TPIU (trace port interface unit)", 1710 ], [ 3, "38.17.1 Introduction", 1710 ], [ 3, "38.17.2 TRACE pin assignment", 1711 ], [ 4, "TPUI TRACE pin assignment", 1711 ], [ 3, "38.17.3 TPUI formatter", 1712 ], [ 3, "38.17.4 TPUI frame synchronization packets", 1713 ], [ 3, "38.17.5 Transmission of the synchronization frame packet", 1713 ], [ 3, "38.17.6 Synchronous mode", 1713 ], [ 3, "38.17.7 Asynchronous mode", 1714 ], [ 3, "38.17.8 TRACECLKIN connection inside the STM32F4xx", 1714 ], [ 3, "38.17.9 TPIU registers", 1714 ], [ 3, "38.17.10 Example of configuration", 1715 ], [ 2, "38.18 DBG register map", 1716 ], [ 1, "39 Device electronic signature", 1717 ], [ 2, "39.1 Unique device ID register (96 bits)", 1717 ], [ 3, "Base address: 0x1FFF 7A10", 1717 ], [ 2, "39.2 Flash size", 1718 ], [ 1, "40 Important security notice", 1719 ], [ 1, "41 Revision history", 1720 ] ], "pages": [ { "page_number": 1, "page_indices": { "start_index": 0, "end_index": 1295 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1 }, "toc_details": [], "page_content": "June 2024\nRM0090 Rev 21\n1/1757\n1\nRM0090\nReference manual\nSTM32F405/415, STM32F407/417, STM32F427/437 and\nSTM32F429/439 advanced Arm®-based 32-bit MCUs\nIntroduction\nThis reference manual targets application developers. It provides complete information on \nhow to use the STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx and \nSTM32F43xxx microcontroller memory and peripherals.\nThe STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx and STM32F43xxx constitute \na family of microcontrollers with different memory sizes, packages and peripherals.\nFor ordering information, mechanical and electrical device characteristics please refer to the \ndatasheets.\nFor information on the Arm® Cortex®-M4 with FPU core, please refer to the Cortex®-M4 with \nFPU Technical Reference Manual.\nThe STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx and STM32F43xxx \nmicrocontrollers include ST state-of-the-art patented technology.\nRelated documents\nAvailable from STMicroelectronics web site (www.st.com):\n•\nSTM32F40x and STM32F41x datasheets\n•\nSTM32F42x and STM32F43x datasheets\n•\nSTM32F40x and STM32F41x errata sheets\n•\nSTM32F42x and STM32F43x errata sheets\n•\nFor information on the Arm® Cortex®-M4 with FPU, refer to the STM32F3xx/F4xxx \nCortex®-M4 with FPU programming manual (PM0214).\nwww.st.com\n" }, { "page_number": 2, "page_indices": { "start_index": 1295, "end_index": 4569 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 2 }, "toc_details": [], "page_content": "Contents\nRM0090\n2/1757\nRM0090 Rev 21\nContents\n1\nDocumentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57\n1.1\nList of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57\n1.2\nGlossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58\n1.3\nPeripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58\n2\nMemory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59\n2.1\nSystem architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59\n2.1.1\nI-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62\n2.1.2\nD-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62\n2.1.3\nS-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62\n2.1.4\nDMA memory bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63\n2.1.5\nDMA peripheral bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63\n2.1.6\nEthernet DMA bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63\n2.1.7\nUSB OTG HS DMA bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63\n2.1.8\nLCD-TFT controller DMA bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63\n2.1.9\nDMA2D bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63\n2.1.10\nBusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63\n2.1.11\nAHB/APB bridges (APB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64\n2.2\nMemory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64\n2.3\nMemory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64\n2.3.1\nEmbedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68\n2.3.2\nFlash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68\n2.3.3\nBit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68\n2.4\nBoot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69\n3\nEmbedded flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73\n3.1\nIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73\n3.2\nMain features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73\n3.3\nEmbedded flash memory in \nSTM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . . . . . . 74\n3.4\nEmbedded flash memory in STM32F42xxx and STM32F43xxx . . . . . . . 76\n3.5\nRead interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80\n3.5.1\nRelation between CPU clock frequency and flash memory read time . . 80\n" }, { "page_number": 3, "page_indices": { "start_index": 4569, "end_index": 7890 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 3 }, "toc_details": [], "page_content": "RM0090 Rev 21\n3/1757\nRM0090\nContents\n39\n3.5.2\nAdaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 82\n3.6\nErase and program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84\n3.6.1\nUnlocking the Flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 84\n3.6.2\nProgram/erase parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85\n3.6.3\nErase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85\n3.6.4\nProgramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86\n3.6.5\nRead-while-write (RWW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87\n3.6.6\nInterrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88\n3.7\nOption bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88\n3.7.1\nDescription of user option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88\n3.7.2\nProgramming user option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92\n3.7.3\nRead protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93\n3.7.4\nWrite protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95\n3.7.5\nProprietary code readout protection (PCROP) . . . . . . . . . . . . . . . . . . . 96\n3.8\nOne-time programmable bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98\n3.9\nFlash interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99\n3.9.1\nFlash access control register (FLASH_ACR) \nfor STM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . . 99\n3.9.2\nFlash access control register (FLASH_ACR) \nfor STM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . 100\n3.9.3\nFlash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101\n3.9.4\nFlash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . 101\n3.9.5\nFlash status register (FLASH_SR) for \nSTM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . . . . 102\n3.9.6\nFlash status register (FLASH_SR) for \nSTM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . 103\n3.9.7\nFlash control register (FLASH_CR) for \nSTM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . . . . 104\n3.9.8\nFlash control register (FLASH_CR) for \nSTM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . 106\n3.9.9\nFlash option control register (FLASH_OPTCR) for \nSTM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . . . . 107\n3.9.10\nFlash option control register (FLASH_OPTCR) \nfor STM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . 109\n3.9.11\nFlash option control register (FLASH_OPTCR1) \nfor STM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . 111\n3.9.12\nFlash interface register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112\n4\nCRC calculation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114\n" }, { "page_number": 4, "page_indices": { "start_index": 7890, "end_index": 11284 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 4 }, "toc_details": [], "page_content": "Contents\nRM0090\n4/1757\nRM0090 Rev 21\n4.1\nCRC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114\n4.2\nCRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114\n4.3\nCRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115\n4.4\nCRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115\n4.4.1\nData register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115\n4.4.2\nIndependent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . 115\n4.4.3\nControl register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116\n4.4.4\nCRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116\n5\nPower controller (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117\n5.1\nPower supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117\n5.1.1\nIndependent A/D converter supply and reference voltage . . . . . . . . . . 118\n5.1.2\nBattery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119\n5.1.3\nVoltage regulator for STM32F405xx/07xx and STM32F415xx/17xx . . 121\n5.1.4\nVoltage regulator for STM32F42xxx and STM32F43xxx . . . . . . . . . . . 122\n5.2\nPower supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125\n5.2.1\nPower-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . 125\n5.2.2\nBrownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126\n5.2.3\nProgrammable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 126\n5.3\nLow-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127\n5.3.1\nSlowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129\n5.3.2\nPeripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129\n5.3.3\nSleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130\n5.3.4\nStop mode (STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . 131\n5.3.5\nStop mode (STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . 134\n5.3.6\nStandby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137\n5.3.7\nProgramming the RTC alternate functions to wake up the device from\nthe Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139\n5.4\nPower control registers (STM32F405xx/07xx and STM32F415xx/17xx) 142\n5.4.1\nPWR power control register (PWR_CR) \nfor STM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . 142\n5.4.2\nPWR power control/status register (PWR_CSR) \nfor STM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . 143\n5.5\nPower control registers (STM32F42xxx and STM32F43xxx) . . . . . . . . . 146\n5.5.1\nPWR power control register (PWR_CR) \nfor STM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . 146\n5.5.2\nPWR power control/status register (PWR_CSR)\nfor STM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . 149\n" }, { "page_number": 5, "page_indices": { "start_index": 11284, "end_index": 14750 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 5 }, "toc_details": [], "page_content": "RM0090 Rev 21\n5/1757\nRM0090\nContents\n39\n5.6\nPWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151\n6\nReset and clock control for \nSTM32F42xxx and STM32F43xxx (RCC) . . . . . . . . . . . . . . . . . . . . . . . 152\n6.1\nReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152\n6.1.1\nSystem reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152\n6.1.2\nPower reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152\n6.1.3\nBackup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153\n6.2\nClocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153\n6.2.1\nHSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156\n6.2.2\nHSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157\n6.2.3\nPLL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157\n6.2.4\nLSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158\n6.2.5\nLSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158\n6.2.6\nSystem clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158\n6.2.7\nClock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159\n6.2.8\nRTC/AWU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159\n6.2.9\nWatchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160\n6.2.10\nClock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160\n6.2.11\nInternal/external clock measurement using TIM5/TIM11 . . . . . . . . . . . 160\n6.3\nRCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163\n6.3.1\nRCC clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 163\n6.3.2\nRCC PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . 165\n6.3.3\nRCC clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . 167\n6.3.4\nRCC clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . 169\n6.3.5\nRCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . 172\n6.3.6\nRCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . 175\n6.3.7\nRCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . 176\n6.3.8\nRCC APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . 176\n6.3.9\nRCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . 180\n6.3.10\nRCC AHB1 peripheral clock register (RCC_AHB1ENR) . . . . . . . . . . . 182\n6.3.11\nRCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . 184\n6.3.12\nRCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . . 185\n6.3.13\nRCC APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . 185\n6.3.14\nRCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . 189\n6.3.15\nRCC AHB1 peripheral clock enable in low power mode register\n(RCC_AHB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191\n" }, { "page_number": 6, "page_indices": { "start_index": 14750, "end_index": 18297 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 6 }, "toc_details": [], "page_content": "Contents\nRM0090\n6/1757\nRM0090 Rev 21\n6.3.16\nRCC AHB2 peripheral clock enable in low power mode register\n(RCC_AHB2LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194\n6.3.17\nRCC AHB3 peripheral clock enable in low power mode register\n(RCC_AHB3LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195\n6.3.18\nRCC APB1 peripheral clock enable in low power mode register\n(RCC_APB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195\n6.3.19\nRCC APB2 peripheral clock enabled in low power mode register\n(RCC_APB2LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199\n6.3.20\nRCC Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . 201\n6.3.21\nRCC clock control & status register (RCC_CSR) . . . . . . . . . . . . . . . . 202\n6.3.22\nRCC spread spectrum clock generation register (RCC_SSCGR) . . . . 204\n6.3.23\nRCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . . . . . . 205\n6.3.24\nRCC PLL configuration register (RCC_PLLSAICFGR) . . . . . . . . . . . . 208\n6.3.25\nRCC Dedicated Clock Configuration Register (RCC_DCKCFGR) . . . 209\n6.3.26\nRCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212\n7\nReset and clock control for \nSTM32F405xx/07xx and STM32F415xx/17xx(RCC) . . . . . . . . . . . . . . 215\n7.1\nReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215\n7.1.1\nSystem reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215\n7.1.2\nPower reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216\n7.1.3\nBackup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216\n7.2\nClocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217\n7.2.1\nHSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219\n7.2.2\nHSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220\n7.2.3\nPLL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221\n7.2.4\nLSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221\n7.2.5\nLSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222\n7.2.6\nSystem clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222\n7.2.7\nClock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222\n7.2.8\nRTC/AWU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223\n7.2.9\nWatchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223\n7.2.10\nClock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224\n7.2.11\nInternal/external clock measurement using TIM5/TIM11 . . . . . . . . . . . 224\n7.3\nRCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226\n7.3.1\nRCC clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 226\n7.3.2\nRCC PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . 228\n7.3.3\nRCC clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . 230\n" }, { "page_number": 7, "page_indices": { "start_index": 18297, "end_index": 21712 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 7 }, "toc_details": [], "page_content": "RM0090 Rev 21\n7/1757\nRM0090\nContents\n39\n7.3.4\nRCC clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . 232\n7.3.5\nRCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . 235\n7.3.6\nRCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . 238\n7.3.7\nRCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . 239\n7.3.8\nRCC APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . 239\n7.3.9\nRCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . 242\n7.3.10\nRCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . 244\n7.3.11\nRCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . 246\n7.3.12\nRCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . . 247\n7.3.13\nRCC APB1 peripheral clock enable register\n(RCC_APB1ENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247\n7.3.14\nRCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . 250\n7.3.15\nRCC AHB1 peripheral clock enable in low power mode register\n(RCC_AHB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252\n7.3.16\nRCC AHB2 peripheral clock enable in low power mode register\n(RCC_AHB2LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254\n7.3.17\nRCC AHB3 peripheral clock enable in low power mode register\n(RCC_AHB3LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255\n7.3.18\nRCC APB1 peripheral clock enable in low power mode register\n(RCC_APB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256\n7.3.19\nRCC APB2 peripheral clock enabled in low power mode \n register (RCC_APB2LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259\n7.3.20\nRCC Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . 261\n7.3.21\nRCC clock control & status register (RCC_CSR) . . . . . . . . . . . . . . . . 262\n7.3.22\nRCC spread spectrum clock generation register (RCC_SSCGR) . . . . 264\n7.3.23\nRCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . . . . . . 265\n7.3.24\nRCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267\n8\nGeneral-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270\n8.1\nGPIO introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270\n8.2\nGPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270\n8.3\nGPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270\n8.3.1\nGeneral-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272\n8.3.2\nI/O pin multiplexer and mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273\n8.3.3\nI/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277\n8.3.4\nI/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277\n8.3.5\nI/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277\n8.3.6\nGPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277\n8.3.7\nI/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278\n" }, { "page_number": 8, "page_indices": { "start_index": 21712, "end_index": 25131 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 8 }, "toc_details": [], "page_content": "Contents\nRM0090\n8/1757\nRM0090 Rev 21\n8.3.8\nExternal interrupt/wake-up lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278\n8.3.9\nInput configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278\n8.3.10\nOutput configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279\n8.3.11\nAlternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280\n8.3.12\nAnalog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281\n8.3.13\nUsing the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15\nport pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281\n8.3.14\nUsing the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins . . . . 281\n8.3.15\nSelection of RTC_AF1 and RTC_AF2 alternate functions . . . . . . . . . . 282\n8.4\nGPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284\n8.4.1\nGPIO port mode register (GPIOx_MODER) (x = A..I/J/K) . . . . . . . . . . 284\n8.4.2\nGPIO port output type register (GPIOx_OTYPER) \n(x = A..I/J/K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284\n8.4.3\nGPIO port output speed register (GPIOx_OSPEEDR)\n(x = A..I/J/K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285\n8.4.4\nGPIO port pull-up/pull-down register (GPIOx_PUPDR)\n(x = A..I/J/K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285\n8.4.5\nGPIO port input data register (GPIOx_IDR) (x = A..I/J/K) . . . . . . . . . . 286\n8.4.6\nGPIO port output data register (GPIOx_ODR) (x = A..I/J/K) . . . . . . . . 286\n8.4.7\nGPIO port bit set/reset register (GPIOx_BSRR) (x = A..I/J/K) . . . . . . . 287\n8.4.8\nGPIO port configuration lock register (GPIOx_LCKR)\n(x = A..I/J/K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287\n8.4.9\nGPIO alternate function low register (GPIOx_AFRL) (x = A..I/J/K) . . . 288\n8.4.10\nGPIO alternate function high register (GPIOx_AFRH)\n(x = A..I/J) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289\n8.4.11\nGPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290\n9\nSystem configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 292\n9.1\nI/O compensation cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292\n9.2\nSYSCFG registers for STM32F405xx/07xx and STM32F415xx/17xx . . 292\n9.2.1\nSYSCFG memory remap register (SYSCFG_MEMRMP) . . . . . . . . . . 292\n9.2.2\nSYSCFG peripheral mode configuration register (SYSCFG_PMC) . . 293\n9.2.3\nSYSCFG external interrupt configuration register 1\n(SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294\n9.2.4\nSYSCFG external interrupt configuration register 2\n(SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294\n9.2.5\nSYSCFG external interrupt configuration register 3\n(SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295\n9.2.6\nSYSCFG external interrupt configuration register 4\n(SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296\n" }, { "page_number": 9, "page_indices": { "start_index": 25131, "end_index": 28629 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 9 }, "toc_details": [], "page_content": "RM0090 Rev 21\n9/1757\nRM0090\nContents\n39\n9.2.7\nCompensation cell control register (SYSCFG_CMPCR) . . . . . . . . . . . 296\n9.2.8\nSYSCFG register maps for \nSTM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . . . . 297\n9.3\nSYSCFG registers for STM32F42xxx and STM32F43xxx . . . . . . . . . . . 297\n9.3.1\nSYSCFG memory remap register (SYSCFG_MEMRMP) . . . . . . . . . . 297\n9.3.2\nSYSCFG peripheral mode configuration register (SYSCFG_PMC) . . 299\n9.3.3\nSYSCFG external interrupt configuration register 1\n(SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300\n9.3.4\nSYSCFG external interrupt configuration register 2\n(SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301\n9.3.5\nSYSCFG external interrupt configuration register 3\n(SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301\n9.3.6\nSYSCFG external interrupt configuration register 4\n(SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302\n9.3.7\nCompensation cell control register (SYSCFG_CMPCR) . . . . . . . . . . . 303\n9.3.8\nSYSCFG register maps for STM32F42xxx and STM32F43xxx . . . . . . 304\n10\nDMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305\n10.1\nDMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305\n10.2\nDMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305\n10.3\nDMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307\n10.3.1\nGeneral description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307\n10.3.2\nDMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309\n10.3.3\nChannel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310\n10.3.4\nArbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311\n10.3.5\nDMA streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312\n10.3.6\nSource, destination and transfer modes . . . . . . . . . . . . . . . . . . . . . . . 312\n10.3.7\nPointer incrementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315\n10.3.8\nCircular mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316\n10.3.9\nDouble buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316\n10.3.10\nProgrammable data width, packing/unpacking, endianess . . . . . . . . . 317\n10.3.11\nSingle and burst transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319\n10.3.12\nFIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320\n10.3.13\nDMA transfer completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322\n10.3.14\nDMA transfer suspension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323\n10.3.15\nFlow controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324\n10.3.16\nSummary of the possible DMA configurations . . . . . . . . . . . . . . . . . . . 325\n10.3.17\nStream configuration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325\n" }, { "page_number": 10, "page_indices": { "start_index": 28629, "end_index": 32121 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 10 }, "toc_details": [], "page_content": "Contents\nRM0090\n10/1757\nRM0090 Rev 21\n10.3.18\nError management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326\n10.4\nDMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327\n10.5\nDMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328\n10.5.1\nDMA low interrupt status register (DMA_LISR) . . . . . . . . . . . . . . . . . . 328\n10.5.2\nDMA high interrupt status register (DMA_HISR) . . . . . . . . . . . . . . . . . 329\n10.5.3\nDMA low interrupt flag clear register (DMA_LIFCR) . . . . . . . . . . . . . . 330\n10.5.4\nDMA high interrupt flag clear register (DMA_HIFCR) . . . . . . . . . . . . . 330\n10.5.5\nDMA stream x configuration register (DMA_SxCR) (x = 0..7) . . . . . . . 331\n10.5.6\nDMA stream x number of data register (DMA_SxNDTR) (x = 0..7) . . . 334\n10.5.7\nDMA stream x peripheral address register (DMA_SxPAR) (x = 0..7) . 335\n10.5.8\nDMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7) 335\n10.5.9\nDMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7) 335\n10.5.10\nDMA stream x FIFO control register (DMA_SxFCR) (x = 0..7) . . . . . . 336\n10.5.11\nDMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338\n11\nChrom-Art Accelerator™ controller (DMA2D) . . . . . . . . . . . . . . . . . . 342\n11.1\nDMA2D introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342\n11.2\nDMA2D main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343\n11.3\nDMA2D functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343\n11.3.1\nGeneral description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343\n11.3.2\nDMA2D control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344\n11.3.3\nDMA2D foreground and background FIFOs . . . . . . . . . . . . . . . . . . . . 344\n11.3.4\nDMA2D foreground and background pixel format converter (PFC) . . . 345\n11.3.5\nDMA2D foreground and background CLUT interface . . . . . . . . . . . . . 347\n11.3.6\nDMA2D blender . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348\n11.3.7\nDMA2D output PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348\n11.3.8\nDMA2D output FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349\n11.3.9\nDMA2D AHB master port timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349\n11.3.10\nDMA2D transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350\n11.3.11\nDMA2D configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350\n11.3.12\nDMA2D transfer control (start, suspend, abort and completion) . . . . . 353\n11.3.13\nWatermark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354\n11.3.14\nError management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354\n11.3.15\nAHB dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354\n11.4\nDMA2D interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354\n11.5\nDMA2D registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355\n" }, { "page_number": 11, "page_indices": { "start_index": 32121, "end_index": 35436 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 11 }, "toc_details": [], "page_content": "RM0090 Rev 21\n11/1757\nRM0090\nContents\n39\n11.5.1\nDMA2D control register (DMA2D_CR) . . . . . . . . . . . . . . . . . . . . . . . . 355\n11.5.2\nDMA2D Interrupt Status Register (DMA2D_ISR) . . . . . . . . . . . . . . . . 357\n11.5.3\nDMA2D interrupt flag clear register (DMA2D_IFCR) . . . . . . . . . . . . . . 358\n11.5.4\nDMA2D foreground memory address register (DMA2D_FGMAR) . . . 359\n11.5.5\nDMA2D foreground offset register (DMA2D_FGOR) . . . . . . . . . . . . . . 359\n11.5.6\nDMA2D background memory address register (DMA2D_BGMAR) . . 360\n11.5.7\nDMA2D background offset register (DMA2D_BGOR) . . . . . . . . . . . . . 360\n11.5.8\nDMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . . 361\n11.5.9\nDMA2D foreground color register (DMA2D_FGCOLR) . . . . . . . . . . . . 363\n11.5.10\nDMA2D background PFC control register (DMA2D_BGPFCCR) . . . . 364\n11.5.11\nDMA2D background color register (DMA2D_BGCOLR) . . . . . . . . . . . 366\n11.5.12\nDMA2D foreground CLUT memory address register\n(DMA2D_FGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366\n11.5.13\nDMA2D background CLUT memory address register\n(DMA2D_BGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367\n11.5.14\nDMA2D output PFC control register (DMA2D_OPFCCR) . . . . . . . . . . 367\n11.5.15\nDMA2D output color register (DMA2D_OCOLR) . . . . . . . . . . . . . . . . . 368\n11.5.16\nDMA2D output memory address register (DMA2D_OMAR) . . . . . . . . 369\n11.5.17\nDMA2D output offset register (DMA2D_OOR) . . . . . . . . . . . . . . . . . . 370\n11.5.18\nDMA2D number of line register (DMA2D_NLR) . . . . . . . . . . . . . . . . . 370\n11.5.19\nDMA2D line watermark register (DMA2D_LWR) . . . . . . . . . . . . . . . . . 371\n11.5.20\nDMA2D AHB master timer configuration register (DMA2D_AMTCR) . 371\n11.5.21\nDMA2D register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372\n12\nInterrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374\n12.1\nNested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 374\n12.1.1\nNVIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374\n12.1.2\nSysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374\n12.1.3\nInterrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374\n12.2\nExternal interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . 374\n12.2.1\nEXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382\n12.2.2\nEXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383\n12.2.3\nWake-up event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383\n12.2.4\nFunctional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383\n12.2.5\nExternal interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . 385\n12.3\nEXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387\n12.3.1\nInterrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 387\n" }, { "page_number": 12, "page_indices": { "start_index": 35436, "end_index": 39092 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 12 }, "toc_details": [], "page_content": "Contents\nRM0090\n12/1757\nRM0090 Rev 21\n12.3.2\nEvent mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387\n12.3.3\nRising trigger selection register (EXTI_RTSR) . . . . . . . . . . . . . . . . . . 388\n12.3.4\nFalling trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . . . . . 388\n12.3.5\nSoftware interrupt event register (EXTI_SWIER) . . . . . . . . . . . . . . . . 389\n12.3.6\nPending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389\n12.3.7\nEXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390\n13\nAnalog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391\n13.1\nADC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391\n13.2\nADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391\n13.3\nADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392\n13.3.1\nADC on-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393\n13.3.2\nADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393\n13.3.3\nChannel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393\n13.3.4\nSingle conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394\n13.3.5\nContinuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395\n13.3.6\nTiming diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395\n13.3.7\nAnalog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395\n13.3.8\nScan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396\n13.3.9\nInjected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397\n13.3.10\nDiscontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398\n13.4\nData alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399\n13.5\nChannel-wise programmable sampling time . . . . . . . . . . . . . . . . . . . . . 400\n13.6\nConversion on external trigger and trigger polarity . . . . . . . . . . . . . . . . 400\n13.7\nFast conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402\n13.8\nData management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403\n13.8.1\nUsing the DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403\n13.8.2\nManaging a sequence of conversions without using the DMA . . . . . . 403\n13.8.3\nConversions without DMA and without overrun detection . . . . . . . . . . 404\n13.9\nMulti ADC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404\n13.9.1\nInjected simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407\n13.9.2\nRegular simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408\n13.9.3\nInterleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410\n13.9.4\nAlternate trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411\n13.9.5\nCombined regular/injected simultaneous mode . . . . . . . . . . . . . . . . . . 413\n13.9.6\nCombined regular simultaneous + alternate trigger mode . . . . . . . . . . 414\n" }, { "page_number": 13, "page_indices": { "start_index": 39092, "end_index": 42760 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 13 }, "toc_details": [], "page_content": "RM0090 Rev 21\n13/1757\nRM0090\nContents\n39\n13.10 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415\n13.11 Battery charge monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417\n13.12 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417\n13.13 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418\n13.13.1\nADC status register (ADC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418\n13.13.2\nADC control register 1 (ADC_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 419\n13.13.3\nADC control register 2 (ADC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 421\n13.13.4\nADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 423\n13.13.5\nADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 423\n13.13.6\nADC injected channel data offset register x (ADC_JOFRx) (x=1..4) . . 424\n13.13.7\nADC watchdog higher threshold register (ADC_HTR) . . . . . . . . . . . . . 424\n13.13.8\nADC watchdog lower threshold register (ADC_LTR) . . . . . . . . . . . . . . 425\n13.13.9\nADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 425\n13.13.10 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 426\n13.13.11 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 426\n13.13.12 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 427\n13.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . . . . . . . . . . . 428\n13.13.14 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 428\n13.13.15 ADC Common status register (ADC_CSR) . . . . . . . . . . . . . . . . . . . . . 429\n13.13.16 ADC common control register (ADC_CCR) . . . . . . . . . . . . . . . . . . . . . 430\n13.13.17 ADC common regular data register for dual and triple modes\n(ADC_CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433\n13.13.18 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433\n14\nDigital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436\n14.1\nDAC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436\n14.2\nDAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436\n14.3\nDAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438\n14.3.1\nDAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438\n14.3.2\nDAC output buffer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438\n14.3.3\nDAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438\n14.3.4\nDAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439\n14.3.5\nDAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440\n14.3.6\nDAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440\n14.3.7\nDMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441\n14.3.8\nNoise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441\n14.3.9\nTriangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442\n" }, { "page_number": 14, "page_indices": { "start_index": 42760, "end_index": 46184 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 14 }, "toc_details": [], "page_content": "Contents\nRM0090\n14/1757\nRM0090 Rev 21\n14.4\nDual DAC channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443\n14.4.1\nIndependent trigger without wave generation . . . . . . . . . . . . . . . . . . . 444\n14.4.2\nIndependent trigger with single LFSR generation . . . . . . . . . . . . . . . . 444\n14.4.3\nIndependent trigger with different LFSR generation . . . . . . . . . . . . . . 444\n14.4.4\nIndependent trigger with single triangle generation . . . . . . . . . . . . . . . 445\n14.4.5\nIndependent trigger with different triangle generation . . . . . . . . . . . . . 445\n14.4.6\nSimultaneous software start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445\n14.4.7\nSimultaneous trigger without wave generation . . . . . . . . . . . . . . . . . . 446\n14.4.8\nSimultaneous trigger with single LFSR generation . . . . . . . . . . . . . . . 446\n14.4.9\nSimultaneous trigger with different LFSR generation . . . . . . . . . . . . . 446\n14.4.10\nSimultaneous trigger with single triangle generation . . . . . . . . . . . . . . 447\n14.4.11\nSimultaneous trigger with different triangle generation . . . . . . . . . . . . 447\n14.5\nDAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448\n14.5.1\nDAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448\n14.5.2\nDAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . 451\n14.5.3\nDAC channel1 12-bit right-aligned data holding register\n(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451\n14.5.4\nDAC channel1 12-bit left aligned data holding register\n(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452\n14.5.5\nDAC channel1 8-bit right aligned data holding register\n(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452\n14.5.6\nDAC channel2 12-bit right aligned data holding register\n(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453\n14.5.7\nDAC channel2 12-bit left aligned data holding register \n(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453\n14.5.8\nDAC channel2 8-bit right-aligned data holding register\n(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453\n14.5.9\nDual DAC 12-bit right-aligned data holding register\n(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454\n14.5.10\nDUAL DAC 12-bit left aligned data holding register\n(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454\n14.5.11\nDUAL DAC 8-bit right aligned data holding register\n(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455\n14.5.12\nDAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 455\n14.5.13\nDAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 455\n14.5.14\nDAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456\n14.5.15\nDAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456\n15\nDigital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458\n" }, { "page_number": 15, "page_indices": { "start_index": 46184, "end_index": 49895 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 15 }, "toc_details": [], "page_content": "RM0090 Rev 21\n15/1757\nRM0090\nContents\n39\n15.1\nDCMI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458\n15.2\nDCMI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458\n15.3\nDCMI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458\n15.4\nDCMI clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458\n15.5\nDCMI functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459\n15.5.1\nDMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460\n15.5.2\nDCMI physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460\n15.5.3\nSynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462\n15.5.4\nCapture modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465\n15.5.5\nCrop feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466\n15.5.6\nJPEG format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468\n15.5.7\nFIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468\n15.6\nData format description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468\n15.6.1\nData formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468\n15.6.2\nMonochrome format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469\n15.6.3\nRGB format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469\n15.6.4\nYCbCr format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469\n15.7\nDCMI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470\n15.8\nDCMI register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470\n15.8.1\nDCMI control register 1 (DCMI_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 470\n15.8.2\nDCMI status register (DCMI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473\n15.8.3\nDCMI raw interrupt status register (DCMI_RIS) . . . . . . . . . . . . . . . . . 474\n15.8.4\nDCMI interrupt enable register (DCMI_IER) . . . . . . . . . . . . . . . . . . . . 475\n15.8.5\nDCMI masked interrupt status register (DCMI_MIS) . . . . . . . . . . . . . . 476\n15.8.6\nDCMI interrupt clear register (DCMI_ICR) . . . . . . . . . . . . . . . . . . . . . . 477\n15.8.7\nDCMI embedded synchronization code register (DCMI_ESCR) . . . . . 478\n15.8.8\nDCMI embedded synchronization unmask register (DCMI_ESUR) . . 479\n15.8.9\nDCMI crop window start (DCMI_CWSTRT) . . . . . . . . . . . . . . . . . . . . . 480\n15.8.10\nDCMI crop window size (DCMI_CWSIZE) . . . . . . . . . . . . . . . . . . . . . . 480\n15.8.11\nDCMI data register (DCMI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481\n15.8.12\nDCMI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481\n16\nLCD-TFT controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483\n16.1\nIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483\n16.2\nLTDC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483\n16.3\nLTDC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484\n" }, { "page_number": 16, "page_indices": { "start_index": 49895, "end_index": 53449 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 16 }, "toc_details": [], "page_content": "Contents\nRM0090\n16/1757\nRM0090 Rev 21\n16.3.1\nLTDC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484\n16.3.2\nLTDC reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484\n16.3.3\nLCD-TFT pins and signal interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 486\n16.4\nLTDC programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486\n16.4.1\nLTDC Global configuration parameters . . . . . . . . . . . . . . . . . . . . . . . . 486\n16.4.2\nLayer programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489\n16.5\nLTDC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493\n16.6\nLTDC programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495\n16.7\nLTDC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496\n16.7.1\nLTDC Synchronization Size Configuration Register (LTDC_SSCR) . . 496\n16.7.2\nLTDC Back Porch Configuration Register (LTDC_BPCR) . . . . . . . . . . 496\n16.7.3\nLTDC Active Width Configuration Register (LTDC_AWCR) . . . . . . . . . 497\n16.7.4\nLTDC Total Width Configuration Register (LTDC_TWCR) . . . . . . . . . . 498\n16.7.5\nLTDC Global Control Register (LTDC_GCR) . . . . . . . . . . . . . . . . . . . . 498\n16.7.6\nLTDC Shadow Reload Configuration Register (LTDC_SRCR) . . . . . . 500\n16.7.7\nLTDC Background Color Configuration Register (LTDC_BCCR) . . . . 500\n16.7.8\nLTDC Interrupt Enable Register (LTDC_IER) . . . . . . . . . . . . . . . . . . . 501\n16.7.9\nLTDC Interrupt Status Register (LTDC_ISR) . . . . . . . . . . . . . . . . . . . . 502\n16.7.10\nLTDC Interrupt Clear Register (LTDC_ICR) . . . . . . . . . . . . . . . . . . . . . 502\n16.7.11\nLTDC Line Interrupt Position Configuration Register (LTDC_LIPCR) . 503\n16.7.12\nLTDC Current Position Status Register (LTDC_CPSR) . . . . . . . . . . . . 503\n16.7.13\nLTDC Current Display Status Register (LTDC_CDSR) . . . . . . . . . . . . 504\n16.7.14\nLTDC Layerx Control Register (LTDC_LxCR) (where x=1..2) . . . . . . . 505\n16.7.15\nLTDC Layerx Window Horizontal Position Configuration Register\n(LTDC_LxWHPCR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 506\n16.7.16\nLTDC Layerx Window Vertical Position Configuration Register\n(LTDC_LxWVPCR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 507\n16.7.17\nLTDC Layerx Color Keying Configuration Register (LTDC_LxCKCR)\n(where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508\n16.7.18\nLTDC Layerx Pixel Format Configuration Register (LTDC_LxPFCR)\n(where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508\n16.7.19\nLTDC Layerx Constant Alpha Configuration Register (LTDC_LxCACR)\n(where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509\n16.7.20\nLTDC Layerx Default Color Configuration Register (LTDC_LxDCCR)\n(where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509\n16.7.21\nLTDC Layerx Blending Factors Configuration Register (LTDC_LxBFCR)\n(where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511\n16.7.22\nLTDC Layerx Color Frame Buffer Address Register (LTDC_LxCFBAR)\n(where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512\n" }, { "page_number": 17, "page_indices": { "start_index": 53449, "end_index": 57195 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 17 }, "toc_details": [], "page_content": "RM0090 Rev 21\n17/1757\nRM0090\nContents\n39\n16.7.23\nLTDC Layerx Color Frame Buffer Length Register (LTDC_LxCFBLR)\n(where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512\n16.7.24\nLTDC Layerx ColorFrame Buffer Line Number Register\n(LTDC_LxCFBLNR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 513\n16.7.25\nLTDC Layerx CLUT Write Register (LTDC_LxCLUTWR) \n(where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514\n16.7.26\nLTDC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515\n17\nAdvanced-control timers (TIM1 and TIM8) . . . . . . . . . . . . . . . . . . . . . 518\n17.1\nTIM1 and TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518\n17.2\nTIM1 and TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519\n17.3\nTIM1 and TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . 521\n17.3.1\nTime-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521\n17.3.2\nCounter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523\n17.3.3\nRepetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532\n17.3.4\nClock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535\n17.3.5\nCapture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538\n17.3.6\nInput capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541\n17.3.7\nPWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542\n17.3.8\nForced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542\n17.3.9\nOutput compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543\n17.3.10\nPWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544\n17.3.11\nComplementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 547\n17.3.12\nUsing the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549\n17.3.13\nClearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 552\n17.3.14\n6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553\n17.3.15\nOne-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554\n17.3.16\nEncoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555\n17.3.17\nTimer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558\n17.3.18\nInterfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558\n17.3.19\nTIMx and external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 560\n17.3.20\nTimer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563\n17.3.21\nDebug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563\n17.4\nTIM1 and TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564\n17.4.1\nTIM1 and TIM8 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . 564\n17.4.2\nTIM1 and TIM8 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . 565\n17.4.3\nTIM1 and TIM8 slave mode control register (TIMx_SMCR) . . . . . . . . 568\n17.4.4\nTIM1 and TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . 570\n" }, { "page_number": 18, "page_indices": { "start_index": 57195, "end_index": 60727 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 18 }, "toc_details": [], "page_content": "Contents\nRM0090\n18/1757\nRM0090 Rev 21\n17.4.5\nTIM1 and TIM8 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . 572\n17.4.6\nTIM1 and TIM8 event generation register (TIMx_EGR) . . . . . . . . . . . . 573\n17.4.7\nTIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . 575\n17.4.8\nTIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . 577\n17.4.9\nTIM1 and TIM8 capture/compare enable register (TIMx_CCER) . . . . 579\n17.4.10\nTIM1 and TIM8 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 583\n17.4.11\nTIM1 and TIM8 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 583\n17.4.12\nTIM1 and TIM8 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . 583\n17.4.13\nTIM1 and TIM8 repetition counter register (TIMx_RCR) . . . . . . . . . . . 584\n17.4.14\nTIM1 and TIM8 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . 584\n17.4.15\nTIM1 and TIM8 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . 585\n17.4.16\nTIM1 and TIM8 capture/compare register 3 (TIMx_CCR3) . . . . . . . . . 585\n17.4.17\nTIM1 and TIM8 capture/compare register 4 (TIMx_CCR4) . . . . . . . . . 586\n17.4.18\nTIM1 and TIM8 break and dead-time register (TIMx_BDTR) . . . . . . . 586\n17.4.19\nTIM1 and TIM8 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . 588\n17.4.20\nTIM1 and TIM8 DMA address for full transfer (TIMx_DMAR) . . . . . . . 589\n17.4.21\nTIM1 and TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590\n18\nGeneral-purpose timers (TIM2 to TIM5) . . . . . . . . . . . . . . . . . . . . . . . . 592\n18.1\nTIM2 to TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592\n18.2\nTIM2 to TIM5 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592\n18.3\nTIM2 to TIM5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594\n18.3.1\nTime-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594\n18.3.2\nCounter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595\n18.3.3\nClock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605\n18.3.4\nCapture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608\n18.3.5\nInput capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610\n18.3.6\nPWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611\n18.3.7\nForced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612\n18.3.8\nOutput compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612\n18.3.9\nPWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613\n18.3.10\nOne-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616\n18.3.11\nClearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 617\n18.3.12\nEncoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618\n18.3.13\nTimer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621\n18.3.14\nTimers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 621\n18.3.15\nTimer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624\n" }, { "page_number": 19, "page_indices": { "start_index": 60727, "end_index": 64350 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 19 }, "toc_details": [], "page_content": "RM0090 Rev 21\n19/1757\nRM0090\nContents\n39\n18.3.16\nDebug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629\n18.4\nTIM2 to TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630\n18.4.1\nTIMx control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 630\n18.4.2\nTIMx control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 632\n18.4.3\nTIMx slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . 633\n18.4.4\nTIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 635\n18.4.5\nTIMx status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636\n18.4.6\nTIMx event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 638\n18.4.7\nTIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 639\n18.4.8\nTIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . 642\n18.4.9\nTIMx capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . 643\n18.4.10\nTIMx counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645\n18.4.11\nTIMx prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645\n18.4.12\nTIMx auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 645\n18.4.13\nTIMx capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 646\n18.4.14\nTIMx capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 646\n18.4.15\nTIMx capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . 647\n18.4.16\nTIMx capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . 647\n18.4.17\nTIMx DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . 648\n18.4.18\nTIMx DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . 649\n18.4.19\nTIM2 option register (TIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649\n18.4.20\nTIM5 option register (TIM5_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650\n18.4.21\nTIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651\n19\nGeneral-purpose timers (TIM9 to TIM14) . . . . . . . . . . . . . . . . . . . . . . . 653\n19.1\nTIM9 to TIM14 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653\n19.2\nTIM9 to TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653\n19.2.1\nTIM9/TIM12 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653\n19.2.2\nTIM10/TIM11 and TIM13/TIM14 main features . . . . . . . . . . . . . . . . . . 654\n19.3\nTIM9 to TIM14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 656\n19.3.1\nTime-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656\n19.3.2\nCounter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658\n19.3.3\nClock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661\n19.3.4\nCapture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663\n19.3.5\nInput capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664\n19.3.6\nPWM input mode (only for TIM9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . 666\n19.3.7\nForced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667\n" }, { "page_number": 20, "page_indices": { "start_index": 64350, "end_index": 67862 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 20 }, "toc_details": [], "page_content": "Contents\nRM0090\n20/1757\nRM0090 Rev 21\n19.3.8\nOutput compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667\n19.3.9\nPWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668\n19.3.10\nOne-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669\n19.3.11\nTIM9/12 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . 671\n19.3.12\nTimer synchronization (TIM9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674\n19.3.13\nDebug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674\n19.4\nTIM9 and TIM12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675\n19.4.1\nTIM9/12 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 675\n19.4.2\nTIM9/12 slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . 676\n19.4.3\nTIM9/12 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . . 677\n19.4.4\nTIM9/12 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 679\n19.4.5\nTIM9/12 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . 680\n19.4.6\nTIM9/12 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . 681\n19.4.7\nTIM9/12 capture/compare enable register (TIMx_CCER) . . . . . . . . . . 684\n19.4.8\nTIM9/12 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685\n19.4.9\nTIM9/12 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685\n19.4.10\nTIM9/12 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . 685\n19.4.11\nTIM9/12 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . 686\n19.4.12\nTIM9/12 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . 686\n19.4.13\nTIM9/12 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687\n19.5\nTIM10/11/13/14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689\n19.5.1\nTIM10/11/13/14 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . 689\n19.5.2\nTIM10/11/13/14 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . 690\n19.5.3\nTIM10/11/13/14 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . 690\n19.5.4\nTIM10/11/13/14 event generation register (TIMx_EGR) . . . . . . . . . . . 691\n19.5.5\nTIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) . . 691\n19.5.6\nTIM10/11/13/14 capture/compare enable register (TIMx_CCER) . . . . 694\n19.5.7\nTIM10/11/13/14 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 695\n19.5.8\nTIM10/11/13/14 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 695\n19.5.9\nTIM10/11/13/14 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . 695\n19.5.10\nTIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . 696\n19.5.11\nTIM11 option register 1 (TIM11_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . 696\n19.5.12\nTIM10/11/13/14 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697\n20\nBasic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699\n20.1\nTIM6 and TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699\n20.2\nTIM6 and TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699\n" }, { "page_number": 21, "page_indices": { "start_index": 67862, "end_index": 71398 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 21 }, "toc_details": [], "page_content": "RM0090 Rev 21\n21/1757\nRM0090\nContents\n39\n20.3\nTIM6 and TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . 700\n20.3.1\nTime-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700\n20.3.2\nCounting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702\n20.3.3\nClock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704\n20.3.4\nDebug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705\n20.4\nTIM6 and TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705\n20.4.1\nTIM6 and TIM7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . 705\n20.4.2\nTIM6 and TIM7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . 707\n20.4.3\nTIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . 707\n20.4.4\nTIM6 and TIM7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . 708\n20.4.5\nTIM6 and TIM7 event generation register (TIMx_EGR) . . . . . . . . . . . . 708\n20.4.6\nTIM6 and TIM7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 708\n20.4.7\nTIM6 and TIM7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 709\n20.4.8\nTIM6 and TIM7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . 709\n20.4.9\nTIM6 and TIM7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710\n21\nIndependent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711\n21.1\nIWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .711\n21.2\nIWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .711\n21.3\nIWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .711\n21.3.1\nHardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711\n21.3.2\nRegister access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711\n21.3.3\nDebug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712\n21.4\nIWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713\n21.4.1\nKey register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713\n21.4.2\nPrescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713\n21.4.3\nReload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714\n21.4.4\nStatus register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714\n21.4.5\nIWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715\n22\nWindow watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716\n22.1\nWWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716\n22.2\nWWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716\n22.3\nWWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716\n22.4\nHow to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 718\n22.5\nDebug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719\n" }, { "page_number": 22, "page_indices": { "start_index": 71398, "end_index": 74861 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 22 }, "toc_details": [], "page_content": "Contents\nRM0090\n22/1757\nRM0090 Rev 21\n22.6\nWWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720\n22.6.1\nControl register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720\n22.6.2\nConfiguration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 721\n22.6.3\nStatus register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721\n22.6.4\nWWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722\n23\nCryptographic processor (CRYP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723\n23.1\nCRYP introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723\n23.2\nCRYP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723\n23.3\nCRYP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725\n23.3.1\nDES/TDES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726\n23.3.2\nAES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731\n23.3.3\nData type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742\n23.3.4\nInitialization vectors - CRYP_IV0...1(L/R) . . . . . . . . . . . . . . . . . . . . . . 745\n23.3.5\nCRYP busy state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746\n23.3.6\nProcedure to perform an encryption or a decryption . . . . . . . . . . . . . . 747\n23.3.7\nContext swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748\n23.4\nCRYP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750\n23.5\nCRYP DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751\n23.6\nCRYP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751\n23.6.1\nCRYP control register (CRYP_CR) for STM32F415/417xx . . . . . . . . . 751\n23.6.2\nCRYP control register (CRYP_CR) for STM32F415/417xx . . . . . . . . . 753\n23.6.3\nCRYP status register (CRYP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756\n23.6.4\nCRYP data input register (CRYP_DIN) . . . . . . . . . . . . . . . . . . . . . . . . 757\n23.6.5\nCRYP data output register (CRYP_DOUT) . . . . . . . . . . . . . . . . . . . . . 758\n23.6.6\nCRYP DMA control register (CRYP_DMACR) . . . . . . . . . . . . . . . . . . . 759\n23.6.7\nCRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . . . . . . . . 759\n23.6.8\nCRYP raw interrupt status register (CRYP_RISR) . . . . . . . . . . . . . . . 760\n23.6.9\nCRYP masked interrupt status register (CRYP_MISR) . . . . . . . . . . . . 760\n23.6.10\nCRYP key registers (CRYP_K0...3(L/R)R) . . . . . . . . . . . . . . . . . . . . . 761\n23.6.11\nCRYP initialization vector registers (CRYP_IV0...1(L/R)R) . . . . . . . . . 763\n23.6.12\nCRYP context swap registers (CRYP_CSGCMCCM0..7R and\nCRYP_CSGCM0..7R) for STM32F42xxx and STM32F43xxx . . . . . . . 765\n23.6.13\nCRYP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766\n24\nRandom number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770\n24.1\nRNG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770\n" }, { "page_number": 23, "page_indices": { "start_index": 74861, "end_index": 78458 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 23 }, "toc_details": [], "page_content": "RM0090 Rev 21\n23/1757\nRM0090\nContents\n39\n24.2\nRNG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770\n24.3\nRNG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770\n24.3.1\nOperation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771\n24.3.2\nError management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771\n24.4\nRNG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771\n24.4.1\nRNG control register (RNG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772\n24.4.2\nRNG status register (RNG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772\n24.4.3\nRNG data register (RNG_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773\n24.4.4\nRNG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774\n25\nHash processor (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775\n25.1\nHASH introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775\n25.2\nHASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775\n25.3\nHASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776\n25.3.1\nDuration of the processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778\n25.3.2\nData type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778\n25.3.3\nMessage digest computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780\n25.3.4\nMessage padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781\n25.3.5\nHash operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782\n25.3.6\nHMAC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782\n25.3.7\nContext swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783\n25.3.8\nHASH interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785\n25.4\nHASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785\n25.4.1\nHASH control register (HASH_CR) for STM32F415/417xx . . . . . . . . . 785\n25.4.2\nHASH control register (HASH_CR) for STM32F43xxx . . . . . . . . . . . . 788\n25.4.3\nHASH data input register (HASH_DIN) . . . . . . . . . . . . . . . . . . . . . . . . 791\n25.4.4\nHASH start register (HASH_STR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792\n25.4.5\nHASH digest registers (HASH_HR0..4/5/6/7) . . . . . . . . . . . . . . . . . . . 793\n25.4.6\nHASH interrupt enable register (HASH_IMR) . . . . . . . . . . . . . . . . . . . 795\n25.4.7\nHASH status register (HASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796\n25.4.8\nHASH context swap registers (HASH_CSRx) . . . . . . . . . . . . . . . . . . . 797\n25.4.9\nHASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798\n26\nReal-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801\n26.1\nIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801\n26.2\nRTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802\n" }, { "page_number": 24, "page_indices": { "start_index": 78458, "end_index": 82248 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 24 }, "toc_details": [], "page_content": "Contents\nRM0090\n24/1757\nRM0090 Rev 21\n26.3\nRTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804\n26.3.1\nClock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804\n26.3.2\nReal-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805\n26.3.3\nProgrammable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805\n26.3.4\nPeriodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805\n26.3.5\nRTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 806\n26.3.6\nReading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808\n26.3.7\nResetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809\n26.3.8\nRTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809\n26.3.9\nRTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810\n26.3.10\nRTC coarse digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811\n26.3.11\nRTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812\n26.3.12\nTimestamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814\n26.3.13\nTamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814\n26.3.14\nCalibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816\n26.3.15\nAlarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816\n26.4\nRTC and low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817\n26.5\nRTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817\n26.6\nRTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819\n26.6.1\nRTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819\n26.6.2\nRTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820\n26.6.3\nRTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821\n26.6.4\nRTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . . 823\n26.6.5\nRTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . . 826\n26.6.6\nRTC wake-up timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . 826\n26.6.7\nRTC calibration register (RTC_CALIBR) . . . . . . . . . . . . . . . . . . . . . . . 827\n26.6.8\nRTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . . 828\n26.6.9\nRTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . . 829\n26.6.10\nRTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . . 830\n26.6.11\nRTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . . 830\n26.6.12\nRTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . . 831\n26.6.13\nRTC time stamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . 831\n26.6.14\nRTC time stamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . . 832\n26.6.15\nRTC timestamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . . 833\n26.6.16\nRTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . . 833\n26.6.17\nRTC tamper and alternate function configuration register\n(RTC_TAFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835\n" }, { "page_number": 25, "page_indices": { "start_index": 82248, "end_index": 85885 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 25 }, "toc_details": [], "page_content": "RM0090 Rev 21\n25/1757\nRM0090\nContents\n39\n26.6.18\nRTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . . 837\n26.6.19\nRTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . . 838\n26.6.20\nRTC backup registers (RTC_BKPxR) . . . . . . . . . . . . . . . . . . . . . . . . . 839\n26.6.21\nRTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839\n27\nInter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 842\n27.1\nI2C introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842\n27.2\nI2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842\n27.3\nI2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843\n27.3.1\nMode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843\n27.3.2\nI2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846\n27.3.3\nI2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849\n27.3.4\nError conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854\n27.3.5\nProgrammable noise filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855\n27.3.6\nSDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856\n27.3.7\nSMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856\n27.3.8\nDMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859\n27.3.9\nPacket error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860\n27.4\nI2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861\n27.5\nI2C debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863\n27.6\nI2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863\n27.6.1\nI2C Control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863\n27.6.2\nI2C Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865\n27.6.3\nI2C Own address register 1 (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . 867\n27.6.4\nI2C Own address register 2 (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . 867\n27.6.5\nI2C Data register (I2C_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868\n27.6.6\nI2C Status register 1 (I2C_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868\n27.6.7\nI2C Status register 2 (I2C_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871\n27.6.8\nI2C Clock control register (I2C_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . 873\n27.6.9\nI2C TRISE register (I2C_TRISE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874\n27.6.10\nI2C FLTR register (I2C_FLTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874\n27.6.11\nI2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875\n28\nSerial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876\n28.1\nSPI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876\n28.2\nSPI and I2S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877\n" }, { "page_number": 26, "page_indices": { "start_index": 85885, "end_index": 89797 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 26 }, "toc_details": [], "page_content": "Contents\nRM0090\n26/1757\nRM0090 Rev 21\n28.2.1\nSPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877\n28.2.2\nI2S features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878\n28.3\nSPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879\n28.3.1\nGeneral description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879\n28.3.2\nConfiguring the SPI in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 883\n28.3.3\nConfiguring the SPI in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 885\n28.3.4\nConfiguring the SPI for half-duplex communication . . . . . . . . . . . . . . . 887\n28.3.5\nData transmission and reception procedures . . . . . . . . . . . . . . . . . . . 888\n28.3.6\nCRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894\n28.3.7\nStatus flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896\n28.3.8\nDisabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897\n28.3.9\nSPI communication using DMA (direct memory addressing) . . . . . . . . 898\n28.3.10\nError flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900\n28.3.11\nSPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901\n28.4\nI2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902\n28.4.1\nI2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902\n28.4.2\nI2S full duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903\n28.4.3\nSupported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904\n28.4.4\nClock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910\n28.4.5\nI2S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912\n28.4.6\nI2S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914\n28.4.7\nStatus flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916\n28.4.8\nError flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917\n28.4.9\nI2S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918\n28.4.10\nDMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918\n28.5\nSPI and I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919\n28.5.1\nSPI control register 1 (SPI_CR1) (not used in I2S mode) . . . . . . . . . . 919\n28.5.2\nSPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921\n28.5.3\nSPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922\n28.5.4\nSPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923\n28.5.5\nSPI CRC polynomial register (SPI_CRCPR) (not used in I2S\nmode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924\n28.5.6\nSPI RX CRC register (SPI_RXCRCR) (not used in I2S mode) . . . . . . 924\n28.5.7\nSPI TX CRC register (SPI_TXCRCR) (not used in I2S mode) . . . . . . . 925\n28.5.8\nSPI_I2S configuration register (SPI_I2SCFGR) . . . . . . . . . . . . . . . . . . 925\n28.5.9\nSPI_I2S prescaler register (SPI_I2SPR) . . . . . . . . . . . . . . . . . . . . . . . 927\n28.5.10\nSPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928\n" }, { "page_number": 27, "page_indices": { "start_index": 89797, "end_index": 93540 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 27 }, "toc_details": [], "page_content": "RM0090 Rev 21\n27/1757\nRM0090\nContents\n39\n29\nSerial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929\n29.1\nIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929\n29.2\nMain features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930\n29.3\nFunctional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931\n29.4\nMain SAI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932\n29.5\nSAI synchronization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933\n29.6\nAudio data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933\n29.7\nFrame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933\n29.7.1\nFrame length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934\n29.7.2\nFrame synchronization polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934\n29.7.3\nFrame synchronization active level length . . . . . . . . . . . . . . . . . . . . . . 935\n29.7.4\nFrame synchronization offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935\n29.7.5\nFS signal role . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935\n29.8\nSlot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936\n29.9\nSAI clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938\n29.10 Internal FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939\n29.11 AC’97 link controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942\n29.12 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943\n29.12.1\nMute mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943\n29.12.2\nMONO/STEREO function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943\n29.12.3\nCompanding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944\n29.12.4\nOutput data line management on an inactive slot . . . . . . . . . . . . . . . . 945\n29.13 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947\n29.13.1\nFIFO overrun/underrun (OVRUDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 947\n29.13.2\nAnticipated frame synchronisation detection (AFSDET) . . . . . . . . . . . 949\n29.13.3\nLate frame synchronization detection . . . . . . . . . . . . . . . . . . . . . . . . . 949\n29.13.4\nCodec not ready (CNRDY AC’97) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950\n29.13.5\nWrong clock configuration in master mode (with NODIV = 0) . . . . . . . 950\n29.14 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951\n29.15 Disabling the SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951\n29.16 SAI DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952\n29.17 SAI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953\n29.17.1\nSAI x configuration register 1 (SAI_xCR1) where x is A or B . . . . . . . . 953\n29.17.2\nSAI x configuration register 2 (SAI_xCR2) where x is A or B . . . . . . . . 956\n29.17.3\nSAI x frame configuration register (SAI_XFRCR) where x is A or B . . 958\n" }, { "page_number": 28, "page_indices": { "start_index": 93540, "end_index": 97208 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 28 }, "toc_details": [], "page_content": "Contents\nRM0090\n28/1757\nRM0090 Rev 21\n29.17.4\nSAI x slot register (SAI_xSLOTR) where x is A or B . . . . . . . . . . . . . . 960\n29.17.5\nSAI x interrupt mask register (SAI_xIM) where x is A or B . . . . . . . . . . 961\n29.17.6\nSAI x status register (SAI_xSR) where x is A or B . . . . . . . . . . . . . . . . 963\n29.17.7\nSAI x clear flag register (SAI_xCLRFR) where X is A or B . . . . . . . . . 965\n29.17.8\nSAI x data register (SAI_xDR) where x is A or B . . . . . . . . . . . . . . . . . 966\n29.17.9\nSAI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966\n30\nUniversal synchronous asynchronous receiver\ntransmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968\n30.1\nUSART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968\n30.2\nUSART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968\n30.3\nUSART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969\n30.3.1\nUSART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972\n30.3.2\nTransmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973\n30.3.3\nReceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976\n30.3.4\nFractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981\n30.3.5\nUSART receiver tolerance to clock deviation . . . . . . . . . . . . . . . . . . . . 991\n30.3.6\nMultiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992\n30.3.7\nParity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994\n30.3.8\nLIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 995\n30.3.9\nUSART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997\n30.3.10\nSingle-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 999\n30.3.11\nSmartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000\n30.3.12\nIrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002\n30.3.13\nContinuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . 1004\n30.3.14\nHardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006\n30.4\nUSART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009\n30.5\nUSART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010\n30.6\nUSART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010\n30.6.1\nStatus register (USART_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010\n30.6.2\nData register (USART_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013\n30.6.3\nBaud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013\n30.6.4\nControl register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013\n30.6.5\nControl register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016\n30.6.6\nControl register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017\n30.6.7\nGuard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . 1020\n30.6.8\nUSART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021\n" }, { "page_number": 29, "page_indices": { "start_index": 97208, "end_index": 101024 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 29 }, "toc_details": [], "page_content": "RM0090 Rev 21\n29/1757\nRM0090\nContents\n39\n31\nSecure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . 1022\n31.1\nSDIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022\n31.2\nSDIO bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023\n31.3\nSDIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025\n31.3.1\nSDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026\n31.3.2\nSDIO APB2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036\n31.4\nCard functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037\n31.4.1\nCard identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037\n31.4.2\nCard reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037\n31.4.3\nOperating voltage range validation . . . . . . . . . . . . . . . . . . . . . . . . . . 1037\n31.4.4\nCard identification process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038\n31.4.5\nBlock write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039\n31.4.6\nBlock read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040\n31.4.7\nStream access, stream write and stream read \n(MultiMediaCard only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040\n31.4.8\nErase: group erase and sector erase . . . . . . . . . . . . . . . . . . . . . . . . 1042\n31.4.9\nWide bus selection or deselection . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042\n31.4.10\nProtection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042\n31.4.11\nCard status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045\n31.4.12\nSD status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048\n31.4.13\nSD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052\n31.4.14\nCommands and responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053\n31.5\nResponse formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057\n31.5.1\nR1 (normal response command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057\n31.5.2\nR1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057\n31.5.3\nR2 (CID, CSD register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057\n31.5.4\nR3 (OCR register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058\n31.5.5\nR4 (Fast I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058\n31.5.6\nR4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059\n31.5.7\nR5 (interrupt request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059\n31.5.8\nR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060\n31.6\nSDIO I/O card-specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060\n31.6.1\nSDIO I/O read wait operation by SDIO_D2 signaling . . . . . . . . . . . . 1061\n31.6.2\nSDIO read wait operation by stopping SDIO_CK . . . . . . . . . . . . . . . 1061\n31.6.3\nSDIO suspend/resume operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061\n31.6.4\nSDIO interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061\n" }, { "page_number": 30, "page_indices": { "start_index": 101024, "end_index": 104576 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 30 }, "toc_details": [], "page_content": "Contents\nRM0090\n30/1757\nRM0090 Rev 21\n31.7\nCE-ATA specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062\n31.7.1\nCommand completion signal disable . . . . . . . . . . . . . . . . . . . . . . . . . 1062\n31.7.2\nCommand completion signal enable . . . . . . . . . . . . . . . . . . . . . . . . . 1062\n31.7.3\nCE-ATA interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062\n31.7.4\nAborting CMD61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062\n31.8\nHW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063\n31.9\nSDIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063\n31.9.1\nSDIO power control register (SDIO_POWER) . . . . . . . . . . . . . . . . . . 1063\n31.9.2\nSDI clock control register (SDIO_CLKCR) . . . . . . . . . . . . . . . . . . . . 1064\n31.9.3\nSDIO argument register (SDIO_ARG) . . . . . . . . . . . . . . . . . . . . . . . . 1065\n31.9.4\nSDIO command register (SDIO_CMD) . . . . . . . . . . . . . . . . . . . . . . . 1065\n31.9.5\nSDIO command response register (SDIO_RESPCMD) . . . . . . . . . . 1066\n31.9.6\nSDIO response 1..4 register (SDIO_RESPx) . . . . . . . . . . . . . . . . . . 1067\n31.9.7\nSDIO data timer register (SDIO_DTIMER) . . . . . . . . . . . . . . . . . . . . 1067\n31.9.8\nSDIO data length register (SDIO_DLEN) . . . . . . . . . . . . . . . . . . . . . 1068\n31.9.9\nSDIO data control register (SDIO_DCTRL) . . . . . . . . . . . . . . . . . . . . 1069\n31.9.10\nSDIO data counter register (SDIO_DCOUNT) . . . . . . . . . . . . . . . . . 1070\n31.9.11\nSDIO status register (SDIO_STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071\n31.9.12\nSDIO interrupt clear register (SDIO_ICR) . . . . . . . . . . . . . . . . . . . . . 1072\n31.9.13\nSDIO mask register (SDIO_MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . 1074\n31.9.14\nSDIO FIFO counter register (SDIO_FIFOCNT) . . . . . . . . . . . . . . . . . 1076\n31.9.15\nSDIO data FIFO register (SDIO_FIFO) . . . . . . . . . . . . . . . . . . . . . . . 1077\n31.9.16\nSDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077\n32\nController area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079\n32.1\nbxCAN introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079\n32.2\nbxCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079\n32.3\nbxCAN general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080\n32.3.1\nCAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080\n32.3.2\nControl, status and configuration registers . . . . . . . . . . . . . . . . . . . . 1081\n32.3.3\nTx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081\n32.3.4\nAcceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081\n32.4\nbxCAN operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082\n32.4.1\nInitialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083\n32.4.2\nNormal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083\n32.4.3\nSleep mode (low-power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083\n" }, { "page_number": 31, "page_indices": { "start_index": 104576, "end_index": 108299 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 31 }, "toc_details": [], "page_content": "RM0090 Rev 21\n31/1757\nRM0090\nContents\n39\n32.5\nTest mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084\n32.5.1\nSilent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084\n32.5.2\nLoop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085\n32.5.3\nLoop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . 1085\n32.6\nDebug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086\n32.7\nbxCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086\n32.7.1\nTransmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086\n32.7.2\nTime triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 1088\n32.7.3\nReception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088\n32.7.4\nIdentifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090\n32.7.5\nMessage storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094\n32.7.6\nError management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096\n32.7.7\nBit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096\n32.8\nbxCAN interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098\n32.9\nCAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1100\n32.9.1\nRegister access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100\n32.9.2\nCAN control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100\n32.9.3\nCAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110\n32.9.4\nCAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117\n32.9.5\nbxCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121\n33\nEthernet (ETH): media access control (MAC) with\nDMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125\n33.1\nEthernet introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1125\n33.2\nEthernet main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1125\n33.2.1\nMAC core features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126\n33.2.2\nDMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127\n33.2.3\nPTP features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127\n33.3\nEthernet pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1128\n33.4\nEthernet functional description: SMI, MII and RMII . . . . . . . . . . . . . . . .1129\n33.4.1\nStation management interface: SMI . . . . . . . . . . . . . . . . . . . . . . . . . 1129\n33.4.2\nMedia-independent interface: MII . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132\n33.4.3\nReduced media-independent interface: RMII . . . . . . . . . . . . . . . . . . 1134\n33.4.4\nMII/RMII selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135\n33.5\nEthernet functional description: MAC 802.3 . . . . . . . . . . . . . . . . . . . . . .1136\n33.5.1\nMAC 802.3 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137\n" }, { "page_number": 32, "page_indices": { "start_index": 108299, "end_index": 112022 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 32 }, "toc_details": [], "page_content": "Contents\nRM0090\n32/1757\nRM0090 Rev 21\n33.5.2\nMAC frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140\n33.5.3\nMAC frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147\n33.5.4\nMAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152\n33.5.5\nMAC filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153\n33.5.6\nMAC loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1156\n33.5.7\nMAC management counters: MMC . . . . . . . . . . . . . . . . . . . . . . . . . . 1156\n33.5.8\nPower management: PMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1157\n33.5.9\nPrecision time protocol (IEEE1588 PTP) . . . . . . . . . . . . . . . . . . . . . . 1160\n33.6\nEthernet functional description: DMA controller operation . . . . . . . . . . .1166\n33.6.1\nInitialization of a transfer using DMA . . . . . . . . . . . . . . . . . . . . . . . . . 1167\n33.6.2\nHost bus burst access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167\n33.6.3\nHost data buffer alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168\n33.6.4\nBuffer size calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168\n33.6.5\nDMA arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169\n33.6.6\nError response to DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169\n33.6.7\nTx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169\n33.6.8\nRx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181\n33.6.9\nDMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192\n33.7\nEthernet interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1193\n33.8\nEthernet register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1194\n33.8.1\nMAC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194\n33.8.2\nMMC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213\n33.8.3\nIEEE 1588 time stamp registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218\n33.8.4\nDMA register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226\n33.8.5\nEthernet register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239\n34\nUSB on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . . . . . . . . . . 1243\n34.1\nOTG_FS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243\n34.2\nOTG_FS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1244\n34.2.1\nGeneral features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1244\n34.2.2\nHost-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245\n34.2.3\nPeripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245\n34.3\nOTG_FS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246\n34.3.1\nOTG pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246\n34.3.2\nOTG full-speed core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246\n34.3.3\nFull-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1247\n" }, { "page_number": 33, "page_indices": { "start_index": 112022, "end_index": 115861 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 33 }, "toc_details": [], "page_content": "RM0090 Rev 21\n33/1757\nRM0090\nContents\n39\n34.4\nOTG dual role device (DRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248\n34.4.1\nID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248\n34.4.2\nHNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248\n34.4.3\nSRP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249\n34.5\nUSB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249\n34.5.1\nSRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250\n34.5.2\nPeripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250\n34.5.3\nPeripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251\n34.6\nUSB host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253\n34.6.1\nSRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254\n34.6.2\nUSB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254\n34.6.3\nHost channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256\n34.6.4\nHost scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257\n34.7\nSOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258\n34.7.1\nHost SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258\n34.7.2\nPeripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259\n34.8\nOTG low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259\n34.9\nDynamic update of the OTG_FS_HFIR register . . . . . . . . . . . . . . . . . . 1260\n34.10 USB data FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261\n34.11 Peripheral FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262\n34.11.1\nPeripheral Rx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262\n34.11.2\nPeripheral Tx FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263\n34.12 Host FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263\n34.12.1\nHost Rx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263\n34.12.2\nHost Tx FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264\n34.13 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264\n34.13.1\nDevice mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264\n34.13.2\nHost mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265\n34.14 USB system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265\n34.15 OTG_FS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266\n34.16 OTG_FS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . 1268\n34.16.1\nCSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269\n34.16.2\nOTG_FS global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274\n34.16.3\nHost-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295\n34.16.4\nDevice-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305\n" }, { "page_number": 34, "page_indices": { "start_index": 115861, "end_index": 119550 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 34 }, "toc_details": [], "page_content": "Contents\nRM0090\n34/1757\nRM0090 Rev 21\n34.16.5\nOTG_FS power and clock gating control register\n(OTG_FS_PCGCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1328\n34.16.6\nOTG_FS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1329\n34.17 OTG_FS programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1338\n34.17.1\nCore initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1338\n34.17.2\nHost initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1339\n34.17.3\nDevice initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1339\n34.17.4\nHost programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1340\n34.17.5\nDevice programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356\n34.17.6\nOperational model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358\n34.17.7\nWorst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1376\n34.17.8\nOTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377\n35\nUSB on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . . . . . . . . . . 1384\n35.1\nOTG_HS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384\n35.2\nOTG_HS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384\n35.2.1\nGeneral features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385\n35.2.2\nHost-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386\n35.2.3\nPeripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386\n35.3\nOTG_HS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386\n35.3.1\nOTG pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387\n35.3.2\nHigh-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387\n35.3.3\nEmbedded Full-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388\n35.4\nOTG dual-role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388\n35.4.1\nID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388\n35.4.2\nHNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388\n35.4.3\nSRP dual-role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1389\n35.5\nUSB functional description in peripheral mode . . . . . . . . . . . . . . . . . . 1389\n35.5.1\nSRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1389\n35.5.2\nPeripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1390\n35.5.3\nPeripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1391\n35.6\nUSB functional description on host mode . . . . . . . . . . . . . . . . . . . . . . 1394\n35.6.1\nSRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394\n35.6.2\nUSB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395\n35.6.3\nHost channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396\n35.6.4\nHost scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1398\n" }, { "page_number": 35, "page_indices": { "start_index": 119550, "end_index": 123225 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 35 }, "toc_details": [], "page_content": "RM0090 Rev 21\n35/1757\nRM0090\nContents\n39\n35.7\nSOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399\n35.7.1\nHost SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399\n35.7.2\nPeripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399\n35.8\nOTG_HS low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400\n35.9\nDynamic update of the OTG_HS_HFIR register . . . . . . . . . . . . . . . . . 1401\n35.10 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402\n35.10.1\nPeripheral mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402\n35.10.2\nHost mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402\n35.11 OTG_HS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1403\n35.12 OTG_HS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . 1405\n35.12.1\nCSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1405\n35.12.2\nOTG_HS global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410\n35.12.3\nHost-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433\n35.12.4\nDevice-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446\n35.12.5\nOTG_HS power and clock gating control register\n(OTG_HS_PCGCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475\n35.12.6\nOTG_HS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475\n35.13 OTG_HS programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490\n35.13.1\nCore initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490\n35.13.2\nHost initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491\n35.13.3\nDevice initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492\n35.13.4\nDMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492\n35.13.5\nHost programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492\n35.13.6\nDevice programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518\n35.13.7\nOperational model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520\n35.13.8\nWorst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1539\n35.13.9\nOTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541\n36\nFlexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . 1547\n36.1\nFSMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547\n36.2\nBlock diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1548\n36.3\nAHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1548\n36.3.1\nSupported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 1549\n36.4\nExternal device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1550\n36.4.1\nNOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1550\n36.4.2\nNAND/PC Card address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551\n" }, { "page_number": 36, "page_indices": { "start_index": 123225, "end_index": 126784 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 36 }, "toc_details": [], "page_content": "Contents\nRM0090\n36/1757\nRM0090 Rev 21\n36.5\nNOR flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1552\n36.5.1\nExternal memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1553\n36.5.2\nSupported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 1555\n36.5.3\nGeneral timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1556\n36.5.4\nNOR flash/PSRAM controller asynchronous transactions . . . . . . . . . 1557\n36.5.5\nSynchronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1574\n36.5.6\nNOR/PSRAM control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1580\n36.6\nNAND Flash/PC Card controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1587\n36.6.1\nExternal memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588\n36.6.2\nNAND Flash / PC Card supported memories and transactions . . . . . 1590\n36.6.3\nTiming diagrams for NAND and PC Card . . . . . . . . . . . . . . . . . . . . . 1590\n36.6.4\nNAND Flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1591\n36.6.5\nNAND Flash prewait functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . 1592\n36.6.6\nComputation of the error correction code (ECC)\nin NAND Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1593\n36.6.7\nPC Card/CompactFlash operations . . . . . . . . . . . . . . . . . . . . . . . . . . 1594\n36.6.8\nNAND Flash/PC Card control registers . . . . . . . . . . . . . . . . . . . . . . . 1596\n36.6.9\nFSMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603\n37\nFlexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605\n37.1\nFMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605\n37.2\nBlock diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606\n37.3\nAHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607\n37.3.1\nSupported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 1608\n37.4\nExternal device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609\n37.4.1\nNOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610\n37.4.2\nNAND Flash memory/PC Card address mapping . . . . . . . . . . . . . . . 1611\n37.4.3\nSDRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612\n37.5\nNOR Flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1615\n37.5.1\nExternal memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1616\n37.5.2\nSupported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 1618\n37.5.3\nGeneral timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1620\n37.5.4\nNOR Flash/PSRAM controller asynchronous transactions . . . . . . . . 1620\n37.5.5\nSynchronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1637\n37.5.6\nNOR/PSRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643\n37.6\nNAND Flash/PC Card controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650\n37.6.1\nExternal memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651\n" }, { "page_number": 37, "page_indices": { "start_index": 126784, "end_index": 130274 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 37 }, "toc_details": [], "page_content": "RM0090 Rev 21\n37/1757\nRM0090\nContents\n39\n37.6.2\nNAND Flash / PC Card supported memories and transactions . . . . . 1653\n37.6.3\nTiming diagrams for NAND Flash memory and PC Card . . . . . . . . . 1653\n37.6.4\nNAND Flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654\n37.6.5\nNAND Flash prewait functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655\n37.6.6\nComputation of the error correction code (ECC) \nin NAND Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656\n37.6.7\nPC Card/CompactFlash operations . . . . . . . . . . . . . . . . . . . . . . . . . . 1657\n37.6.8\nNAND Flash/PC Card controller registers . . . . . . . . . . . . . . . . . . . . . 1659\n37.7\nSDRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666\n37.7.1\nSDRAM controller main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666\n37.7.2\nSDRAM External memory interface signals . . . . . . . . . . . . . . . . . . . . 1666\n37.7.3\nSDRAM controller functional description . . . . . . . . . . . . . . . . . . . . . . 1667\n37.7.4\nLow power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674\n37.7.5\nSDRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1677\n37.8\nFMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1683\n38\nDebug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1686\n38.1\nOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1686\n38.2\nReference Arm® documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1687\n38.3\nSWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . 1687\n38.3.1\nMechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . 1688\n38.4\nPinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1688\n38.4.1\nSWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689\n38.4.2\nFlexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689\n38.4.3\nInternal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . 1689\n38.4.4\nUsing serial wire and releasing the unused debug pins as GPIOs . . 1691\n38.5\nSTM32F4xx JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 1691\n38.6\nID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693\n38.6.1\nMCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693\n38.6.2\nBoundary scan TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1694\n38.6.3\nCortex®-M4 with FPU TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1694\n38.6.4\nCortex®-M4 with FPU JEDEC-106 ID code . . . . . . . . . . . . . . . . . . . . 1694\n38.7\nJTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1694\n38.8\nSW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696\n38.8.1\nSW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696\n38.8.2\nSW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696\n" }, { "page_number": 38, "page_indices": { "start_index": 130274, "end_index": 133898 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 38 }, "toc_details": [], "page_content": "Contents\nRM0090\n38/1757\nRM0090 Rev 21\n38.8.3\nSW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . 1697\n38.8.4\nDP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697\n38.8.5\nSW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698\n38.8.6\nSW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698\n38.9\nAHB-AP (AHB access port) - valid for both JTAG-DP\nand SW-DP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699\n38.10 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700\n38.11 Capability of the debugger host to connect under system reset . . . . . 1701\n38.12 FPB (Flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1701\n38.13 DWT (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702\n38.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . 1702\n38.14.1\nGeneral description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702\n38.14.2\nTime stamp packets, synchronization and overflow packets . . . . . . . 1702\n38.15 ETM (Embedded Trace Macrocell™) . . . . . . . . . . . . . . . . . . . . . . . . . . 1704\n38.15.1\nETM general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704\n38.15.2\nETM signal protocol and packet types . . . . . . . . . . . . . . . . . . . . . . . . 1704\n38.15.3\nMain ETM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705\n38.15.4\nETM configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705\n38.16 MCU debug component (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . . 1705\n38.16.1\nDebug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 1705\n38.16.2\nDebug support for timers, watchdog, bxCAN and I2C . . . . . . . . . . . . 1706\n38.16.3\nDebug MCU configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 1706\n38.16.4\nDebug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . . . . . 1708\n38.16.5\nDebug MCU APB2 Freeze register (DBGMCU_APB2_FZ) . . . . . . . . 1709\n38.17 TPIU (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710\n38.17.1\nIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710\n38.17.2\nTRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711\n38.17.3\nTPUI formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712\n38.17.4\nTPUI frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . 1713\n38.17.5\nTransmission of the synchronization frame packet . . . . . . . . . . . . . . 1713\n38.17.6\nSynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713\n38.17.7\nAsynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714\n38.17.8\nTRACECLKIN connection inside the STM32F4xx . . . . . . . . . . . . . . . 1714\n38.17.9\nTPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714\n38.17.10 Example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715\n38.18 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1716\n" }, { "page_number": 39, "page_indices": { "start_index": 133898, "end_index": 134488 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 39 }, "toc_details": [], "page_content": "RM0090 Rev 21\n39/1757\nRM0090\nContents\n39\n39\nDevice electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1717\n39.1\nUnique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1717\n39.2\nFlash size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718\n40\nImportant security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719\n41\nRevision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720\n" }, { "page_number": 40, "page_indices": { "start_index": 134488, "end_index": 139571 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 40 }, "toc_details": [], "page_content": "List of tables\nRM0090\n40/1757\nRM0090 Rev 21\nList of tables\nTable 1.\nSTM32F4xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64\nTable 2.\nBoot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69\nTable 3.\nMemory mapping vs. Boot mode/physical remap\nin STM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71\nTable 4.\nMemory mapping vs. Boot mode/physical remap\nin STM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71\nTable 5.\nFlash module organization (STM32F40x and STM32F41x) . . . . . . . . . . . . . . . . . . . . . . . . 75\nTable 6.\nFlash module - 2 Mbyte dual bank organization (STM32F42xxx and STM32F43xxx) . . . . 77\nTable 7.\n1 Mbyte flash memory single bank vs dual bank organization\n (STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78\nTable 8.\n1 Mbyte single bank flash memory organization\n(STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78\nTable 9.\n1 Mbyte dual bank flash memory organization (STM32F42xxx and STM32F43xxx) . . . . . 79\nTable 10.\n512 Kbyte single bank flash memory organization\n(STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80\nTable 11.\nNumber of wait states according to CPU clock (HCLK) frequency \n(STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81\nTable 12.\nNumber of wait states according to CPU clock (HCLK) frequency\n (STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81\nTable 13.\nMaximum program/erase parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85\nTable 14.\nFlash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88\nTable 15.\nOption byte organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88\nTable 16.\nDescription of the option bytes (STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . 89\nTable 17.\nDescription of the option bytes \n(STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90\nTable 18.\nAccess versus read protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95\nTable 19.\nOTP area organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98\nTable 20.\nFlash register map and reset values\n(STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112\nTable 21.\nFlash register map and reset values (STM32F42xxx and STM32F43xxx). . . . . . . . . . . . 112\nTable 22.\nCRC calculation unit register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116\nTable 23.\nVoltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . 123\nTable 24.\nLow-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129\nTable 25.\nSleep-now entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130\nTable 26.\nSleep-on-exit entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131\nTable 27.\nStop operating modes\n(STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132\nTable 28.\nStop mode entry and exit (for STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . . 133\nTable 29.\nStop operating modes (STM32F42xxx and STM32F43xxx). . . . . . . . . . . . . . . . . . . . . . . 135\nTable 30.\nStop mode entry and exit (STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . . . . 137\nTable 31.\nStandby mode entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138\nTable 32.\nPWR - register map and reset values for\nSTM32F405xx/07xx and STM32F415xx/17xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151\nTable 33.\nPWR - register map and reset values for STM32F42xxx and STM32F43xxx . . . . . . . . . 151\nTable 34.\nRCC register map and reset values for STM32F42xxx and STM32F43xxx . . . . . . . . . . . 212\nTable 35.\nRCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267\nTable 36.\nPort bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271\nTable 37.\nFlexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274\n" }, { "page_number": 41, "page_indices": { "start_index": 139571, "end_index": 146292 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 41 }, "toc_details": [], "page_content": "RM0090 Rev 21\n41/1757\nRM0090\nList of tables\n46\nTable 38.\nRTC_AF1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282\nTable 39.\nRTC_AF2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283\nTable 40.\nGPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290\nTable 41.\nSYSCFG register map and reset values\n(STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297\nTable 42.\nSYSCFG register map and reset values (STM32F42xxx and STM32F43xxx). . . . . . . . . 304\nTable 43.\nDMA1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310\nTable 44.\nDMA2 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311\nTable 45.\nSource and destination address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312\nTable 46.\nSource and destination address registers in Double buffer mode (DBM=1). . . . . . . . . . . 317\nTable 47.\nPacking/unpacking & endian behavior (bit PINC = MINC = 1) . . . . . . . . . . . . . . . . . . . . . 318\nTable 48.\nRestriction on NDT versus PSIZE and MSIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319\nTable 49.\nFIFO threshold configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321\nTable 50.\nPossible DMA configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325\nTable 51.\nDMA interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327\nTable 52.\nDMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338\nTable 53.\nSupported color mode in input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345\nTable 54.\nData order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346\nTable 55.\nAlpha mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347\nTable 56.\nSupported CLUT color mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348\nTable 57.\nCLUT data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348\nTable 58.\nSupported color mode in output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349\nTable 59.\nData order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349\nTable 60.\nDMA2D interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354\nTable 61.\nDMA2D register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372\nTable 62.\nVector table for STM32F405xx/07xx and STM32F415xx/17xx. . . . . . . . . . . . . . . . . . . . . 375\nTable 63.\nVector table for STM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378\nTable 64.\nExternal interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 390\nTable 65.\nExternal interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 390\nTable 66.\nADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393\nTable 67.\nAnalog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396\nTable 68.\nConfiguring the trigger polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400\nTable 69.\nExternal trigger for regular channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401\nTable 70.\nExternal trigger for injected channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402\nTable 71.\nADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417\nTable 72.\nADC global register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433\nTable 73.\nADC register map and reset values for each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434\nTable 74.\nADC register map and reset values (common ADC registers) . . . . . . . . . . . . . . . . . . . . . 435\nTable 75.\nDAC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437\nTable 76.\nExternal triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440\nTable 77.\nDAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456\nTable 78.\nDCMI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458\nTable 79.\nDCMI signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460\nTable 80.\nPositioning of captured data bytes in 32-bit words (8-bit width) . . . . . . . . . . . . . . . . . . . . 461\nTable 81.\nPositioning of captured data bytes in 32-bit words (10-bit width) . . . . . . . . . . . . . . . . . . . 461\nTable 82.\nPositioning of captured data bytes in 32-bit words (12-bit width) . . . . . . . . . . . . . . . . . . . 462\nTable 83.\nPositioning of captured data bytes in 32-bit words (14-bit width) . . . . . . . . . . . . . . . . . . . 462\nTable 84.\nData storage in monochrome progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . 469\nTable 85.\nData storage in RGB progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469\nTable 86.\nData storage in YCbCr progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470\nTable 87.\nDCMI interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470\nTable 88.\nDCMI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481\n" }, { "page_number": 42, "page_indices": { "start_index": 146292, "end_index": 152832 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 42 }, "toc_details": [], "page_content": "List of tables\nRM0090\n42/1757\nRM0090 Rev 21\nTable 89.\nLTDC registers versus clock domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485\nTable 90.\nLCD-TFT pins and signal interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486\nTable 91.\nPixel Data mapping versus Color Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490\nTable 92.\nLTDC interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494\nTable 93.\nLTDC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515\nTable 94.\nCounting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556\nTable 95.\nTIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570\nTable 96.\nOutput control bits for complementary OCx and OCxN channels with\nbreak feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582\nTable 97.\nTIM1 and TIM8 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590\nTable 98.\nCounting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619\nTable 99.\nTIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635\nTable 100.\nOutput control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644\nTable 101.\nTIM2 to TIM5 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651\nTable 102.\nTIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677\nTable 103.\nOutput control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685\nTable 104.\nTIM9/12 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687\nTable 105.\nOutput control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694\nTable 106.\nTIM10/11/13/14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697\nTable 107.\nTIM6 and TIM7 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710\nTable 108.\nMin/max IWDG timeout period (in ms) at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . 712\nTable 109.\nIWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715\nTable 110.\nMinimum and maximum timeout values at 30 MHz (fPCLK1). . . . . . . . . . . . . . . . . . . . . . . 719\nTable 111.\nWWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722\nTable 112.\nNumber of cycles required to process each 128-bit block\n(STM32F415/417xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723\nTable 113.\nNumber of cycles required to process each 128-bit block\n(STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723\nTable 114.\nData types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743\nTable 115.\nCRYP register map and reset values for STM32F415/417xx. . . . . . . . . . . . . . . . . . . . . . 766\nTable 116.\nCRYP register map and reset values for STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . 767\nTable 117.\nRNG register map and reset map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774\nTable 118.\nHASH register map and reset values on STM32F415/417xx . . . . . . . . . . . . . . . . . . . . . . 798\nTable 119.\nHASH register map and reset values on STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . 799\nTable 120.\nEffect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817\nTable 121.\nInterrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818\nTable 122.\nRTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839\nTable 123.\nMaximum DNF[3:0] value to be compliant with Thd:dat(max) . . . . . . . . . . . . . . . . . . . . . 855\nTable 124.\nSMBus vs. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857\nTable 125.\nI2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861\nTable 126.\nI2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875\nTable 127.\nSPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901\nTable 128.\nAudio frequency precision (for PLLM VCO = 1 MHz or 2 MHz) . . . . . . . . . . . . . . . . . . . . 912\nTable 129.\nI2S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918\nTable 130.\nSPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928\nTable 131.\nExample of possible audio frequency sampling range . . . . . . . . . . . . . . . . . . . . . . . . . . . 939\nTable 132.\nInterrupt sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951\nTable 133.\nSAI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966\nTable 134.\nNoise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980\nTable 135.\nError calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 12 MHz,\noversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983\nTable 136.\nError calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK =12 MHz,\n" }, { "page_number": 43, "page_indices": { "start_index": 152832, "end_index": 159661 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 43 }, "toc_details": [], "page_content": "RM0090 Rev 21\n43/1757\nRM0090\nList of tables\n46\noversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984\nTable 137.\nError calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz,\noversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984\nTable 138.\nError calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz,\noversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985\nTable 139.\nError calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,\noversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986\nTable 140.\nError calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,\noversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986\nTable 141.\nError calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,\noversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987\nTable 142.\nError calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,\noversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988\nTable 143.\nError calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 Hz,\noversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989\nTable 144.\nError calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 MHz,\noversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990\nTable 145.\nUSART receiver’s tolerance when DIV fraction is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991\nTable 146.\nUSART receiver tolerance when DIV_Fraction is different from 0 . . . . . . . . . . . . . . . . . . 992\nTable 147.\nFrame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994\nTable 148.\nUSART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009\nTable 149.\nUSART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010\nTable 150.\nUSART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021\nTable 151.\nSDIO I/O definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026\nTable 152.\nCommand format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030\nTable 153.\nShort response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031\nTable 154.\nLong response format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031\nTable 155.\nCommand path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031\nTable 156.\nData token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034\nTable 157.\nTransmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035\nTable 158.\nReceive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036\nTable 159.\nCard status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046\nTable 160.\nSD status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049\nTable 161.\nSpeed class code field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050\nTable 162.\nPerformance move field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050\nTable 163.\nAU_SIZE field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051\nTable 164.\nMaximum AU size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051\nTable 165.\nErase size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051\nTable 166.\nErase timeout field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052\nTable 167.\nErase offset field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052\nTable 168.\nBlock-oriented write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054\nTable 169.\nBlock-oriented write protection commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055\nTable 170.\nErase commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055\nTable 171.\nI/O mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056\nTable 172.\nLock card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056\nTable 173.\nApplication-specific commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056\nTable 174.\nR1 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057\nTable 175.\nR2 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058\nTable 176.\nR3 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058\nTable 177.\nR4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058\nTable 178.\nR4b response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059\nTable 179.\nR5 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059\n" }, { "page_number": 44, "page_indices": { "start_index": 159661, "end_index": 166489 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 44 }, "toc_details": [], "page_content": "List of tables\nRM0090\n44/1757\nRM0090 Rev 21\nTable 180.\nR6 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060\nTable 181.\nResponse type and SDIO_RESPx registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067\nTable 182.\nSDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077\nTable 183.\nTransmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094\nTable 184.\nReceive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094\nTable 185.\nbxCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121\nTable 186.\nAlternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128\nTable 187.\nManagement frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130\nTable 188.\nClock range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132\nTable 189.\nTX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133\nTable 190.\nRX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134\nTable 191.\nFrame statuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149\nTable 192.\nDestination address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155\nTable 193.\nSource address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1156\nTable 194.\nReceive descriptor 0 - encoding for bits 7, 5 and 0 (normal descriptor\nformat only, EDFE=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187\nTable 195.\nTime stamp snapshot dependency on registers bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220\nTable 196.\nEthernet register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239\nTable 197.\nOTG_FS input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246\nTable 198.\nCompatibility of STM32 low power modes with the OTG . . . . . . . . . . . . . . . . . . . . . . . . 1259\nTable 199.\nCore global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269\nTable 200.\nHost-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270\nTable 201.\nDevice-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271\nTable 202.\nData FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272\nTable 203.\nPower and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273\nTable 204.\nTRDT values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279\nTable 205.\nMinimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307\nTable 206.\nOTG_FS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1329\nTable 207.\nOTG_HS input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387\nTable 208.\nCompatibility of STM32 low power modes with the OTG . . . . . . . . . . . . . . . . . . . . . . . . 1400\nTable 209.\nCore global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406\nTable 210.\nHost-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407\nTable 211.\nDevice-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408\nTable 212.\nData FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410\nTable 213.\nPower and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410\nTable 214.\nTRDT values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417\nTable 215.\nMinimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1449\nTable 216.\nOTG_HS register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475\nTable 217.\nNOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551\nTable 218.\nExternal memory address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551\nTable 219.\nMemory mapping and timing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551\nTable 220.\nNAND bank selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1552\nTable 221.\nProgrammable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1553\nTable 222.\nNonmultiplexed I/O NOR flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1553\nTable 223.\nMultiplexed I/O NOR flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1554\nTable 224.\nNonmultiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1554\nTable 225.\nMultiplexed I/O PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1555\nTable 226.\nNOR flash/PSRAM controller: example of supported memories and transactions. . . . . 1555\nTable 227.\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558\nTable 228.\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559\nTable 229.\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560\nTable 230.\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561\n" }, { "page_number": 45, "page_indices": { "start_index": 166489, "end_index": 173495 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 45 }, "toc_details": [], "page_content": "RM0090 Rev 21\n45/1757\nRM0090\nList of tables\n46\nTable 231.\nFSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561\nTable 232.\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563\nTable 233.\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564\nTable 234.\nFSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564\nTable 235.\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566\nTable 236.\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566\nTable 237.\nFSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1567\nTable 238.\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1568\nTable 239.\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1569\nTable 240.\nFSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1569\nTable 241.\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571\nTable 242.\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571\nTable 243.\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1576\nTable 244.\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577\nTable 245.\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1578\nTable 246.\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1579\nTable 247.\nProgrammable NAND/PC Card access parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588\nTable 248.\n8-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588\nTable 249.\n16-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1589\nTable 250.\n16-bit PC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1589\nTable 251.\nSupported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1590\nTable 252.\n16-bit PC-Card signals and access type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1595\nTable 253.\nECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1602\nTable 254.\nFSMC register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603\nTable 255.\nNOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610\nTable 256.\nNOR/PSRAM External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1611\nTable 257.\nNAND/PC Card memory mapping and timing registers . . . . . . . . . . . . . . . . . . . . . . . . . 1611\nTable 258.\nNAND bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612\nTable 259.\nSDRAM bank selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612\nTable 260.\nSDRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612\nTable 261.\nSDRAM address mapping with 8-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613\nTable 262.\nSDRAM address mapping with 16-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . 1614\nTable 263.\nSDRAM address mapping with 32-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . 1614\nTable 264.\nProgrammable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1616\nTable 265.\nNon-multiplexed I/O NOR Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617\nTable 266.\n16-bit multiplexed I/O NOR Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617\nTable 267.\nNon-multiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617\nTable 268.\n16-Bit multiplexed I/O PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1618\nTable 269.\nNOR Flash/PSRAM: Example of supported memories and transactions . . . . . . . . . . . . 1619\nTable 270.\nFMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622\nTable 271.\nFMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622\nTable 272.\nFMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624\nTable 273.\nFMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1625\nTable 274.\nFMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1625\nTable 275.\nFMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627\nTable 276.\nFMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628\nTable 277.\nFMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628\nTable 278.\nFMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1630\nTable 279.\nFMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1630\nTable 280.\nFMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631\nTable 281.\nFMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632\nTable 282.\nFMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633\n" }, { "page_number": 46, "page_indices": { "start_index": 173495, "end_index": 178158 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 46 }, "toc_details": [], "page_content": "List of tables\nRM0090\n46/1757\nRM0090 Rev 21\nTable 283.\nFMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633\nTable 284.\nFMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635\nTable 285.\nFMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635\nTable 286.\nFMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640\nTable 287.\nFMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640\nTable 288.\nFMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641\nTable 289.\nFMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642\nTable 290.\nProgrammable NAND Flash/PC Card access parameters . . . . . . . . . . . . . . . . . . . . . . . 1651\nTable 291.\n8-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651\nTable 292.\n16-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652\nTable 293.\n16-bit PC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652\nTable 294.\nSupported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653\nTable 295.\n16-bit PC-Card signals and access type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658\nTable 296.\nECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665\nTable 297.\nSDRAM signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666\nTable 298.\nFMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1683\nTable 299.\nSWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689\nTable 300.\nFlexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689\nTable 301.\nJTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1694\nTable 302.\n32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . 1695\nTable 303.\nPacket request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696\nTable 304.\nACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697\nTable 305.\nDATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697\nTable 306.\nSW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698\nTable 307.\n Cortex®-M4 with FPU AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699\nTable 308.\nCore debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700\nTable 309.\nMain ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703\nTable 310.\nMain ETM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705\nTable 311.\nAsynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711\nTable 312.\nSynchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711\nTable 313.\nFlexible TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712\nTable 314.\nImportant TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714\nTable 315.\nDBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1716\nTable 316.\nDocument revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720\n" }, { "page_number": 47, "page_indices": { "start_index": 178158, "end_index": 184007 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 47 }, "toc_details": [], "page_content": "RM0090 Rev 21\n47/1757\nRM0090\nList of figures\n56\nList of figures\nFigure 1.\nSystem architecture for STM32F405xx/07xx and STM32F415xx/17xx devices. . . . . . . . . 60\nFigure 2.\nSystem architecture for STM32F42xxx and STM32F43xxx devices . . . . . . . . . . . . . . . . . 62\nFigure 3.\nFlash memory interface connection inside system architecture\n (STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73\nFigure 4.\nFlash memory interface connection inside system architecture\n(STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74\nFigure 5.\nSequential 32-bit instruction execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83\nFigure 6.\nRDP levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95\nFigure 7.\nPCROP levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97\nFigure 8.\nCRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114\nFigure 9.\nPower supply overview for STM32F405xx/07xx and STM32F415xx/17xx. . . . . . . . . . . . 117\nFigure 10.\nPower supply overview for STM32F42xxx and STM32F43xxx. . . . . . . . . . . . . . . . . . . . . 118\nFigure 11.\nBackup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121\nFigure 12.\nPower-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125\nFigure 13.\nBOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126\nFigure 14.\nPVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127\nFigure 15.\nSimplified diagram of the reset circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153\nFigure 16.\nClock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154\nFigure 17.\nHSE/ LSE clock sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156\nFigure 18.\nFrequency measurement with TIM5 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . . 161\nFigure 19.\nFrequency measurement with TIM11 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . 162\nFigure 20.\nSimplified diagram of the reset circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216\nFigure 21.\nClock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218\nFigure 22.\nHSE/ LSE clock sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220\nFigure 23.\nFrequency measurement with TIM5 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . . 225\nFigure 24.\nFrequency measurement with TIM11 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . 225\nFigure 25.\nBasic structure of a five-volt tolerant I/O port bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271\nFigure 26.\nSelecting an alternate function on STM32F405xx/07xx and STM32F415xx/17xx . . . . 275\nFigure 27.\nSelecting an alternate function on STM32F42xxx and STM32F43xxx . . . . . . . . . . . . . . 276\nFigure 28.\nInput floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279\nFigure 29.\nOutput configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280\nFigure 30.\nAlternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280\nFigure 31.\nHigh impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281\nFigure 32.\nDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307\nFigure 33.\nSystem implementation of the two DMA controllers \n(STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308\nFigure 34.\nSystem implementation of the two DMA controllers\n(STM32F42xxx and STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309\nFigure 35.\nChannel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310\nFigure 36.\nPeripheral-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313\nFigure 37.\nMemory-to-peripheral mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314\nFigure 38.\nMemory-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315\nFigure 39.\nFIFO structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320\nFigure 40.\nDMA2D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344\nFigure 41.\nExternal interrupt/event controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383\nFigure 42.\nExternal interrupt/event GPIO mapping\n(STM32F405xx/07xx and STM32F415xx/17xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385\nFigure 43.\nExternal interrupt/event GPIO mapping (STM32F42xxx and STM32F43xxx) . . . . . . . . . 386\n" }, { "page_number": 48, "page_indices": { "start_index": 184007, "end_index": 190622 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 48 }, "toc_details": [], "page_content": "List of figures\nRM0090\n48/1757\nRM0090 Rev 21\nFigure 44.\nSingle ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392\nFigure 45.\nTiming diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395\nFigure 46.\nAnalog watchdog’s guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396\nFigure 47.\nInjected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397\nFigure 48.\nRight alignment of 12-bit data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399\nFigure 49.\nLeft alignment of 12-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399\nFigure 50.\nLeft alignment of 6-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399\nFigure 51.\nMulti ADC block diagram(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405\nFigure 52.\nInjected simultaneous mode on 4 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . . 408\nFigure 53.\nInjected simultaneous mode on 4 channels: triple ADC mode . . . . . . . . . . . . . . . . . . . . . 408\nFigure 54.\nRegular simultaneous mode on 16 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . 409\nFigure 55.\nRegular simultaneous mode on 16 channels: triple ADC mode . . . . . . . . . . . . . . . . . . . . 409\nFigure 56.\nInterleaved mode on 1 channel in continuous conversion mode: dual ADC mode. . . . . . 410\nFigure 57.\nInterleaved mode on 1 channel in continuous conversion mode: triple ADC mode . . . . . 411\nFigure 58.\nAlternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412\nFigure 59.\nAlternate trigger: 4 injected channels (each ADC) in discontinuous mode. . . . . . . . . . . . 413\nFigure 60.\nAlternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413\nFigure 61.\nAlternate + regular simultaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414\nFigure 62.\nCase of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415\nFigure 63.\nTemperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 416\nFigure 64.\nDAC channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437\nFigure 65.\nData registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439\nFigure 66.\nData registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439\nFigure 67.\nTiming diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 440\nFigure 68.\nDAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442\nFigure 69.\nDAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 442\nFigure 70.\nDAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443\nFigure 71.\nDAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 443\nFigure 72.\nDCMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459\nFigure 73.\nTop-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460\nFigure 74.\nDCMI signal waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461\nFigure 75.\nTiming diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463\nFigure 76.\nFrame capture waveforms in Snapshot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465\nFigure 77.\nFrame capture waveforms in continuous grab mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466\nFigure 78.\nCoordinates and size of the window after cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467\nFigure 79.\nData capture waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467\nFigure 80.\nPixel raster scan order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468\nFigure 81.\nLTDC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484\nFigure 82.\nLCD-TFT Synchronous timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487\nFigure 83.\nLayer window programmable parameters: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490\nFigure 84.\nBlending two layers with background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493\nFigure 85.\nInterrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494\nFigure 86.\nAdvanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520\nFigure 87.\nCounter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 522\nFigure 88.\nCounter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 522\nFigure 89.\nCounter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523\nFigure 90.\nCounter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524\nFigure 91.\nCounter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524\nFigure 92.\nCounter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524\nFigure 93.\nCounter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 525\nFigure 94.\nCounter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 525\nFigure 95.\nCounter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527\n" }, { "page_number": 49, "page_indices": { "start_index": 190622, "end_index": 197133 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 49 }, "toc_details": [], "page_content": "RM0090 Rev 21\n49/1757\nRM0090\nList of figures\n56\nFigure 96.\nCounter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527\nFigure 97.\nCounter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528\nFigure 98.\nCounter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528\nFigure 99.\nCounter timing diagram, update event when repetition counter is not used. . . . . . . . . . . 529\nFigure 100. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 530\nFigure 101. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530\nFigure 102. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 531\nFigure 103. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531\nFigure 104. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 532\nFigure 105. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . . . . . . . . . . 532\nFigure 106. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 534\nFigure 107. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 535\nFigure 108. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536\nFigure 109. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537\nFigure 110. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537\nFigure 111. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538\nFigure 112. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 539\nFigure 113. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539\nFigure 114. Output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 540\nFigure 115. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 540\nFigure 116. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542\nFigure 117. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544\nFigure 118. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545\nFigure 119. Center-aligned PWM waveforms (ARR=8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546\nFigure 120. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548\nFigure 121. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 548\nFigure 122. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 548\nFigure 123. Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551\nFigure 124. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552\nFigure 125. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553\nFigure 126. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554\nFigure 127. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 557\nFigure 128. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 557\nFigure 129. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559\nFigure 130. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560\nFigure 131. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561\nFigure 132. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562\nFigure 133. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 563\nFigure 134. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593\nFigure 135. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 595\nFigure 136. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 595\nFigure 137. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596\nFigure 138. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596\nFigure 139. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597\nFigure 140. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597\nFigure 141. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 598\nFigure 142. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 598\nFigure 143. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599\nFigure 144. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600\nFigure 145. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600\nFigure 146. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600\nFigure 147. Counter timing diagram, Update event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601\n" }, { "page_number": 50, "page_indices": { "start_index": 197133, "end_index": 203738 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 50 }, "toc_details": [], "page_content": "List of figures\nRM0090\n50/1757\nRM0090 Rev 21\nFigure 148. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 602\nFigure 149. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602\nFigure 150. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 603\nFigure 151. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603\nFigure 152. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 604\nFigure 153. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . . . . . . . . . . 604\nFigure 154. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 605\nFigure 155. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606\nFigure 156. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607\nFigure 157. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607\nFigure 158. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608\nFigure 159. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 608\nFigure 160. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609\nFigure 161. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 609\nFigure 162. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611\nFigure 163. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613\nFigure 164. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614\nFigure 165. Center-aligned PWM waveforms (ARR=8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615\nFigure 166. Example of one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616\nFigure 167. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618\nFigure 168. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 620\nFigure 169. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 620\nFigure 170. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621\nFigure 171. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622\nFigure 172. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623\nFigure 173. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 624\nFigure 174. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624\nFigure 175. Gating timer 2 with OC1REF of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625\nFigure 176. Gating timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626\nFigure 177. Triggering timer 2 with update of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627\nFigure 178. Triggering timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628\nFigure 179. Triggering timer 1 and 2 with timer 1 TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629\nFigure 180. General-purpose timer block diagram (TIM9 and TIM12) . . . . . . . . . . . . . . . . . . . . . . . . 654\nFigure 181. General-purpose timer block diagram (TIM10/11/13/14)\n. . . . . . . . . . . . . . . . . . . . . . . . 655\nFigure 182. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 657\nFigure 183. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 657\nFigure 184. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658\nFigure 185. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659\nFigure 186. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659\nFigure 187. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659\nFigure 188. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 660\nFigure 189. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 660\nFigure 190. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 661\nFigure 191. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662\nFigure 192. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662\nFigure 193. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 663\nFigure 194. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664\nFigure 195. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 664\nFigure 196. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666\nFigure 197. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668\nFigure 198. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669\nFigure 199. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670\n" }, { "page_number": 51, "page_indices": { "start_index": 203738, "end_index": 210536 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 51 }, "toc_details": [], "page_content": "RM0090 Rev 21\n51/1757\nRM0090\nList of figures\n56\nFigure 200. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672\nFigure 201. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673\nFigure 202. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673\nFigure 203. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699\nFigure 204. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 701\nFigure 205. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 701\nFigure 206. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702\nFigure 207. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703\nFigure 208. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703\nFigure 209. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703\nFigure 210. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not\npreloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704\nFigure 211. Counter timing diagram, update event when ARPE=1 (TIMx_ARR\npreloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704\nFigure 212. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 705\nFigure 213. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712\nFigure 214. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717\nFigure 215. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718\nFigure 216. Block diagram (STM32F415/417xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725\nFigure 217. Block diagram (STM32F43xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726\nFigure 218. DES/TDES-ECB mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728\nFigure 219. DES/TDES-ECB mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728\nFigure 220. DES/TDES-CBC mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730\nFigure 221. DES/TDES-CBC mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731\nFigure 222. AES-ECB mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732\nFigure 223. AES-ECB mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733\nFigure 224. AES-CBC mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734\nFigure 225. AES-CBC mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735\nFigure 226. AES-CTR mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736\nFigure 227. AES-CTR mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737\nFigure 228. Initial counter block structure for the Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737\nFigure 229. 64-bit block construction according to DATATYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744\nFigure 230. Initialization vectors use in the TDES-CBC encryption. . . . . . . . . . . . . . . . . . . . . . . . . . . 746\nFigure 231. CRYP interrupt mapping diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751\nFigure 232. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770\nFigure 233. Block diagram for STM32F415/417xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776\nFigure 234. Block diagram for STM32F43xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777\nFigure 235. Bit, byte and half-word swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779\nFigure 236. HASH interrupt mapping diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785\nFigure 237. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803\nFigure 238. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844\nFigure 239. I2C block diagram for STM32F40x/41x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845\nFigure 240. I2C block diagram for STM32F42x/43x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846\nFigure 241. Transfer sequence diagram for slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848\nFigure 242. Transfer sequence diagram for slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849\nFigure 243. Transfer sequence diagram for master transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852\nFigure 244. Transfer sequence diagram for master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853\nFigure 245. I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862\nFigure 246. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879\nFigure 247. Single master/ single slave application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880\nFigure 248. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882\nFigure 249. TI mode - Slave mode, single transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884\n" }, { "page_number": 52, "page_indices": { "start_index": 210536, "end_index": 217009 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 52 }, "toc_details": [], "page_content": "List of figures\nRM0090\n52/1757\nRM0090 Rev 21\nFigure 250. TI mode - Slave mode, continuous transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885\nFigure 251. TI mode - master mode, single transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886\nFigure 252. TI mode - master mode, continuous transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887\nFigure 253. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and\nRXONLY=0) in case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890\nFigure 254. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0,\nRXONLY=0) in case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891\nFigure 255. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0)\nin case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892\nFigure 256. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of \ncontinuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892\nFigure 257. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1)\nin case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893\nFigure 258. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) \nin case of discontinuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894\nFigure 259. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899\nFigure 260. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899\nFigure 261. TI mode frame format error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901\nFigure 262. I2S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902\nFigure 263. I2S full duplex block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903\nFigure 264. I2S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . . . . . . . . . . . . . . 905\nFigure 265. I2S Philips standard waveforms (24-bit frame with CPOL = 0). . . . . . . . . . . . . . . . . . . . . 905\nFigure 266. Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905\nFigure 267. Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906\nFigure 268. I2S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . . . . . . 906\nFigure 269. Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906\nFigure 270. MSB justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . . . . . . . . . . . . . . 907\nFigure 271. MSB justified 24-bit frame length with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907\nFigure 272. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0. . . . . . . . . . . . . . . . 907\nFigure 273. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . 908\nFigure 274. LSB justified 24-bit frame length with CPOL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908\nFigure 275. Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908\nFigure 276. Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909\nFigure 277. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 909\nFigure 278. Example of LSB justified 16-bit extended to 32-bit packet frame . . . . . . . . . . . . . . . . . . . 909\nFigure 279. PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910\nFigure 280. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 910\nFigure 281. Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911\nFigure 282. I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911\nFigure 283. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931\nFigure 284. Audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933\nFigure 285. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . . . . . . . . 935\nFigure 286. FS role is start of frame (FSDEF = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936\nFigure 287. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . . . . . . . . . . . . . . . . . . . . . . 937\nFigure 288. First bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937\nFigure 289. Audio block clock generator overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938\nFigure 290. AC’97 audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942\nFigure 291. Data companding hardware in an audio block in the SAI . . . . . . . . . . . . . . . . . . . . . . . . . 944\nFigure 292. Tristate strategy on SD output line on an inactive slot . . . . . . . . . . . . . . . . . . . . . . . . . . . 946\nFigure 293. Tristate on output data line in a protocol like I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947\nFigure 294. Overrun detection error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948\nFigure 295. FIFO underrun event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949\n" }, { "page_number": 53, "page_indices": { "start_index": 217009, "end_index": 224068 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 53 }, "toc_details": [], "page_content": "RM0090 Rev 21\n53/1757\nRM0090\nList of figures\n56\nFigure 296. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971\nFigure 297. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972\nFigure 298. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974\nFigure 299. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975\nFigure 300. Start bit detection when oversampling by 16 or 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976\nFigure 301. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979\nFigure 302. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980\nFigure 303. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993\nFigure 304. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993\nFigure 305. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . . . . . . . . . . . . . . 996\nFigure 306. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 997\nFigure 307. USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998\nFigure 308. USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998\nFigure 309. USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999\nFigure 310. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999\nFigure 311. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000\nFigure 312. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001\nFigure 313. IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003\nFigure 314. IrDA data modulation (3/16) -Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003\nFigure 315. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005\nFigure 316. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006\nFigure 317. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006\nFigure 318. RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007\nFigure 319. CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008\nFigure 320. USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009\nFigure 321. SDIO “no response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023\nFigure 322. SDIO (multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023\nFigure 323. SDIO (multiple) block write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024\nFigure 324. SDIO sequential read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024\nFigure 325. SDIO sequential write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024\nFigure 326. SDIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025\nFigure 327. SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026\nFigure 328. Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027\nFigure 329. SDIO adapter command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028\nFigure 330. Command path state machine (CPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029\nFigure 331. SDIO command transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030\nFigure 332. Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032\nFigure 333. Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033\nFigure 334. CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080\nFigure 335. Dual CAN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082\nFigure 336. bxCAN operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084\nFigure 337. bxCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085\nFigure 338. bxCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085\nFigure 339. bxCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086\nFigure 340. Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088\nFigure 341. Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089\nFigure 342. Filter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . 1091\nFigure 343. Example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092\nFigure 344. Filtering mechanism - Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093\nFigure 345. CAN error state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095\nFigure 346. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097\nFigure 347. CAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098\n" }, { "page_number": 54, "page_indices": { "start_index": 224068, "end_index": 231057 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 54 }, "toc_details": [], "page_content": "List of figures\nRM0090\n54/1757\nRM0090 Rev 21\nFigure 348. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099\nFigure 349. RX and TX mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110\nFigure 350. ETH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129\nFigure 351. SMI interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130\nFigure 352. MDIO timing and frame structure - Write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131\nFigure 353. MDIO timing and frame structure - Read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132\nFigure 354. Media independent interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132\nFigure 355. MII clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134\nFigure 356. Reduced media-independent interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135\nFigure 357. RMII clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135\nFigure 358. Clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136\nFigure 359. Address field format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138\nFigure 360. MAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139\nFigure 361. Tagged MAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140\nFigure 362. Transmission bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146\nFigure 363. Transmission with no collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146\nFigure 364. Transmission with collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147\nFigure 365. Frame transmission in MMI and RMII modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147\nFigure 366. Receive bit order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151\nFigure 367. Reception with no error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152\nFigure 368. Reception with errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152\nFigure 369. Reception with false carrier indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152\nFigure 370. MAC core interrupt masking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153\nFigure 371. Wake-up frame filter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1157\nFigure 372. Networked time synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161\nFigure 373. System time update using the Fine correction method. . . . . . . . . . . . . . . . . . . . . . . . . . 1163\nFigure 374. PTP trigger output to TIM2 ITR1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165\nFigure 375. PPS output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166\nFigure 376. Descriptor ring and chain structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167\nFigure 377. TxDMA operation in Default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171\nFigure 378. TxDMA operation in OSF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173\nFigure 379. Normal transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174\nFigure 380. Enhanced transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180\nFigure 381. Receive DMA operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182\nFigure 382. Normal Rx DMA descriptor structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184\nFigure 383. Enhanced receive descriptor field format with IEEE1588 time stamp enabled. . . . . . . . 1190\nFigure 384. Interrupt scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193\nFigure 385. Ethernet MAC remote wake-up frame filter register (ETH_MACRWUFFR) . . . . . . . . . . 1203\nFigure 386. OTG full-speed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246\nFigure 387. OTG A-B device connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248\nFigure 388. USB peripheral-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250\nFigure 389. USB host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254\nFigure 390. SOF connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258\nFigure 391. Updating OTG_FS_HFIR dynamically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261\nFigure 392. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . 1262\nFigure 393. Host-mode FIFO address mapping and AHB FIFO access mapping. . . . . . . . . . . . . . . 1263\nFigure 394. Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267\nFigure 395. CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269\nFigure 396. Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341\nFigure 397. Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342\nFigure 398. Normal bulk/control OUT/SETUP and bulk/control IN transactions . . . . . . . . . . . . . . . . 1343\nFigure 399. Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346\n" }, { "page_number": 55, "page_indices": { "start_index": 231057, "end_index": 238054 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 55 }, "toc_details": [], "page_content": "RM0090 Rev 21\n55/1757\nRM0090\nList of figures\n56\nFigure 400. Normal interrupt OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348\nFigure 401. Normal isochronous OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353\nFigure 402. Receive FIFO packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1359\nFigure 403. Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361\nFigure 404. Bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368\nFigure 405. TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377\nFigure 406. A-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378\nFigure 407. B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1379\nFigure 408. A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1380\nFigure 409. B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1382\nFigure 410. USB OTG interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387\nFigure 411. USB host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394\nFigure 412. SOF trigger output to TIM2 ITR1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399\nFigure 413. Updating OTG_HS_HFIR dynamically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401\nFigure 414. Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404\nFigure 415. CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406\nFigure 416. Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495\nFigure 417. Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1496\nFigure 418. Normal bulk/control OUT/SETUP and bulk/control IN transactions - DMA\nmode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497\nFigure 419. Normal bulk/control OUT/SETUP and bulk/control IN transactions - Slave\nmode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1498\nFigure 420. Bulk/control IN transactions - DMA mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501\nFigure 421. Bulk/control IN transactions - Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502\nFigure 422. Normal interrupt OUT/IN transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504\nFigure 423. Normal interrupt OUT/IN transactions - Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505\nFigure 424. Normal isochronous OUT/IN transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . 1510\nFigure 425. Normal isochronous OUT/IN transactions - Slave mode . . . . . . . . . . . . . . . . . . . . . . . . 1511\nFigure 426. Receive FIFO packet read in slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522\nFigure 427. Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524\nFigure 428. Slave mode bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531\nFigure 429. TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1540\nFigure 430. A-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541\nFigure 431. B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542\nFigure 432. A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1543\nFigure 433. B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1545\nFigure 434. FSMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1548\nFigure 435. FSMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1550\nFigure 436. Mode1 read accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1557\nFigure 437. Mode1 write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558\nFigure 438. ModeA read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559\nFigure 439. ModeA write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560\nFigure 440. Mode2 and mode B read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562\nFigure 441. Mode2 write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562\nFigure 442. Mode B write accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563\nFigure 443. Mode C read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1565\nFigure 444. Mode C write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1565\nFigure 445. Mode D read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1567\nFigure 446. Mode D write accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1568\nFigure 447. Multiplexed read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1570\nFigure 448. Multiplexed write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1570\nFigure 449. Asynchronous wait during a read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1573\n" }, { "page_number": 56, "page_indices": { "start_index": 238054, "end_index": 243073 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 56 }, "toc_details": [], "page_content": "List of figures\nRM0090\n56/1757\nRM0090 Rev 21\nFigure 450. Asynchronous wait during a write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1573\nFigure 451. Wait configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575\nFigure 452. Synchronous multiplexed read mode - NOR, PSRAM (CRAM) . . . . . . . . . . . . . . . . . . . 1576\nFigure 453. Synchronous multiplexed write mode - PSRAM (CRAM) . . . . . . . . . . . . . . . . . . . . . . . . 1578\nFigure 454. NAND/PC Card controller timing for common memory access . . . . . . . . . . . . . . . . . . . 1591\nFigure 455. Access to non ‘CE don’t care’ NAND-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1592\nFigure 456. FMC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607\nFigure 457. FMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610\nFigure 458. Mode1 read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621\nFigure 459. Mode1 write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621\nFigure 460. ModeA read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1623\nFigure 461. ModeA write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624\nFigure 462. Mode2 and mode B read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1626\nFigure 463. Mode2 write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1626\nFigure 464. ModeB write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627\nFigure 465. ModeC read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629\nFigure 466. ModeC write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629\nFigure 467. ModeD read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631\nFigure 468. ModeD write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632\nFigure 469. Muxed read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634\nFigure 470. Muxed write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634\nFigure 471. Asynchronous wait during a read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 1636\nFigure 472. Asynchronous wait during a write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 1637\nFigure 473. Wait configuration waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639\nFigure 474. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . . . . . . . 1639\nFigure 475. Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . . . . . . . . . . . . 1641\nFigure 476. NAND Flash/PC Card controller waveforms for common memory access. . . . . . . . . . . 1654\nFigure 477. Access to non ‘CE don’t care’ NAND-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655\nFigure 478. Burst write SDRAM access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668\nFigure 479. Burst read SDRAM access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669\nFigure 480. Logic diagram of Read access with RBURST bit set (CAS=2, RPIPE=0) . . . . . . . . . . . 1670\nFigure 481. Read access crossing row boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672\nFigure 482. Write access crossing row boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672\nFigure 483. Self-refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1675\nFigure 484. Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1676\nFigure 485. Block diagram of STM32 MCU and Cortex®-M4 with FPU-level debug support . . . . . . 1686\nFigure 486. SWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1688\nFigure 487. JTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692\nFigure 488. TPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710\n" }, { "page_number": 57, "page_indices": { "start_index": 243073, "end_index": 244492 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 57 }, "toc_details": [ [ 1, "1 Documentation conventions", 57 ], [ 2, "1.1 List of abbreviations for registers", 57 ] ], "page_content": "RM0090 Rev 21\n57/1757\nRM0090\nDocumentation conventions\n113\n1 \nDocumentation conventions\nThe STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx and STM32F43xxx devices \nhave an Arm®(a) Cortex®-M4 with FPU core.\n1.1 \nList of abbreviations for registers\nThe following abbreviations are used in register descriptions:\n \na.\nArm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.\nread/write (rw)\nSoftware can read and write to these bits.\nread-only (r)\nSoftware can only read these bits. \nwrite-only (w)\nSoftware can only write to this bit. Reading the bit returns the reset \nvalue.\nread/clear (rc_w1)\nSoftware can read as well as clear this bit by writing 1. Writing ‘0’ has \nno effect on the bit value.\nread/clear (rc_w0)\nSoftware can read as well as clear this bit by writing 0. Writing ‘1’ has \nno effect on the bit value.\nread/clear by read \n(rc_r)\nSoftware can read this bit. Reading this bit automatically clears it to ‘0’. \nWriting ‘0’ has no effect on the bit value.\nread/set (rs)\nSoftware can read as well as set this bit. Writing ‘0’ has no effect on the \nbit value.\nread-only write \ntrigger (rt_w)\nSoftware can read this bit. Writing ‘0’ or ‘1’ triggers an event but has no \neffect on the bit value.\ntoggle (t)\nSoftware can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect.\nReserved (Res.)\nReserved bit, must be kept at reset value.\n" }, { "page_number": 58, "page_indices": { "start_index": 244492, "end_index": 246369 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 58 }, "toc_details": [ [ 1, "1 Documentation conventions", 57 ], [ 2, "1.2 Glossary", 58 ], [ 2, "1.3 Peripheral availability", 58 ] ], "page_content": "Documentation conventions\nRM0090\n58/1757\nRM0090 Rev 21\n1.2 \nGlossary\nThis section gives a brief definition of acronyms and abbreviations used in this document:\n•\nThe CPU core integrates two debug ports:\n–\nJTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the \nJoint Test Action Group (JTAG) protocol.\n–\nSWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on \nthe Serial Wire Debug (SWD) protocol.\nFor both the JTAG and SWD protocols, please refer to the Cortex®-M4 with FPU \nTechnical Reference Manual\n•\nWord: data/instruction of 32-bit length.\n•\nHalf word: data/instruction of 16-bit length.\n•\nByte: data of 8-bit length.\n•\nDouble word: data of 64-bit length.\n•\nIAP (in-application programming): IAP is the ability to reprogram the flash memory of a \nmicrocontroller while the user program is running.\n•\nICP (in-circuit programming): ICP is the ability to program the flash memory of a \nmicrocontroller using the JTAG protocol, the SWD protocol or the bootloader while the \ndevice is mounted on the user application board.\n•\nI-Code: this bus connects the Instruction bus of the CPU core to the Flash instruction \ninterface. Prefetch is performed on this bus.\n•\nD-Code: this bus connects the D-Code bus (literal load and debug access) of the CPU \nto the Flash data interface.\n•\nOption bytes: product configuration bits stored in the flash memory.\n•\nOBL: option byte loader.\n•\nAHB: advanced high-performance bus.\n•\nCPU: refers to the Cortex®-M4 with FPU core.\n1.3 \nPeripheral availability\nFor peripheral availability and number across all STM32F405xx/07xx and \nSTM32F415xx/17xx sales types, please refer to the STM32F405xx/07xx and \nSTM32F415xx/17xx datasheets.\nFor peripheral availability and number across all STM32F42xxx and STM32F43xxx sales \ntypes, please refer to the STM32F42xxx and STM32F43xxx datasheets.\n" }, { "page_number": 59, "page_indices": { "start_index": 246369, "end_index": 247454 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 59 }, "toc_details": [ [ 1, "2 Memory and bus architecture", 59 ], [ 2, "2.1 System architecture", 59 ] ], "page_content": "RM0090 Rev 21\n59/1757\nRM0090\nMemory and bus architecture\n113\n2 \nMemory and bus architecture\n2.1 \nSystem architecture\nIn STM32F405xx/07xx and STM32F415xx/17xx, the main system consists of 32-bit \nmultilayer AHB bus matrix that interconnects:\nThe main system consists of 32-bit multilayer AHB bus matrix that interconnects:\n•\nEight masters:\n–\nCortex®-M4 with FPU core I-bus, D-bus and S-bus\n–\nDMA1 memory bus\n–\nDMA2 memory bus\n–\nDMA2 peripheral bus\n–\nEthernet DMA bus\n–\nUSB OTG HS DMA bus\n•\nSeven slaves:\n–\nInternal flash memory ICode bus\n–\nInternal flash memory DCode bus\n–\nMain internal SRAM1 (112 KB)\n–\nAuxiliary internal SRAM2 (16 KB)\n–\nAHB1 peripherals including AHB to APB bridges and APB peripherals\n–\nAHB2 peripherals\n–\nFSMC\nThe bus matrix provides access from a master to a slave, enabling concurrent access and \nefficient operation even when several high-speed peripherals work simultaneously. The 64-\nKbyte CCM (core coupled memory) data RAM is not part of the bus matrix and can be \naccessed only through the CPU. This architecture is shown in Figure 1.\n" }, { "page_number": 60, "page_indices": { "start_index": 247454, "end_index": 247907 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 60 }, "toc_details": [ [ 1, "2 Memory and bus architecture", 59 ], [ 2, "2.1 System architecture", 59 ] ], "page_content": "Memory and bus architecture\nRM0090\n60/1757\nRM0090 Rev 21\nFigure 1. System architecture for STM32F405xx/07xx and STM32F415xx/17xx devices\nARM\nCortex-M4\nGP\nDMA1\nGP\nDMA2\nMAC\nEthernet\nUSB OTG\nHS\nBus matrix-S\nICODE\nDCODE\nACCEL\nFlash\nmemory\nSRAM1 \n112 Kbyte\nSRAM2\n16 Kbyte\nAHB1\nperipherals\nAHB2\nFSMC\nStatic MemCtl\nI-bus\nD-bus\nS-bus\nDMA_P1\nDMA_MEM1\nDMA_MEM2\nDMA_P2\nETHERNET_M\nUSB_HS_M\nai18490e\nCCM data RAM \n64-Kbyte\nAPB1\nAPB2\nperipherals\n" }, { "page_number": 61, "page_indices": { "start_index": 247907, "end_index": 248955 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 61 }, "toc_details": [ [ 1, "2 Memory and bus architecture", 59 ], [ 2, "2.1 System architecture", 59 ] ], "page_content": "RM0090 Rev 21\n61/1757\nRM0090\nMemory and bus architecture\n113\nIn the STM32F42xx and STM32F43xx devices, the main system consists of 32-bit multilayer \nAHB bus matrix that interconnects:\n•\nTen masters:\n–\nCortex®-M4 with FPU core I-bus, D-bus and S-bus\n–\nDMA1 memory bus\n–\nDMA2 memory bus\n–\nDMA2 peripheral bus\n–\nEthernet DMA bus\n–\nUSB OTG HS DMA bus\n–\nLCD Controller DMA-bus\n–\nDMA2D (Chrom-Art Accelerator™) memory bus\n•\nEight slaves:\n–\nInternal flash memory ICode bus\n–\nInternal flash memory DCode bus\n–\nMain internal SRAM1 (112 KB)\n–\nAuxiliary internal SRAM2 (16 KB)\n–\nAuxiliary internal SRAM3 (64 KB)\n–\nAHB1peripherals including AHB to APB bridges and APB peripherals\n–\nAHB2 peripherals\n–\nFMC\nThe bus matrix provides access from a master to a slave, enabling concurrent access and \nefficient operation even when several high-speed peripherals work simultaneously. The 64-\nKbyte CCM (core coupled memory) data RAM is not part of the bus matrix and can be \naccessed only through the CPU. This architecture is shown in Figure 2.\n" }, { "page_number": 62, "page_indices": { "start_index": 248955, "end_index": 250484 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 62 }, "toc_details": [ [ 1, "2 Memory and bus architecture", 59 ], [ 2, "2.1 System architecture", 59 ], [ 3, "2.1.1 I-bus", 62 ], [ 3, "2.1.2 D-bus", 62 ], [ 3, "2.1.3 S-bus", 62 ] ], "page_content": "Memory and bus architecture\nRM0090\n62/1757\nRM0090 Rev 21\nFigure 2. System architecture for STM32F42xxx and STM32F43xxx devices\n2.1.1 \nI-bus\nThis bus connects the Instruction bus of the Cortex®-M4 with FPU core to the BusMatrix. \nThis bus is used by the core to fetch instructions. The target of this bus is a memory \ncontaining code (internal flash memory/SRAM or external memories through the \nFSMC/FMC).\n2.1.2 \nD-bus\nThis bus connects the databus of the Cortex®-M4 with FPU to the 64-Kbyte CCM data RAM \nto the BusMatrix. This bus is used by the core for literal load and debug access. The target \nof this bus is a memory containing code or data (internal flash memory or external memories \nthrough the FSMC/FMC).\n2.1.3 \nS-bus\nThis bus connects the system bus of the Cortex®-M4 with FPU core to a BusMatrix. This \nbus is used to access data located in a peripheral or in SRAM. Instructions may also be \nfetched on this bus (less efficient than ICode). The targets of this bus are the internal \nSRAM1, SRAM2 and SRAM3, the AHB1 peripherals including the APB peripherals, the \nAHB2 peripherals and the external memories through the FSMC/FMC.\nARM\nCortex-M4\nGP\nDMA1\nGP\nDMA2\nMAC\nEthernet\nUSB OTG\nHS\nBus matrix-S\nICODE\nDCODE\nACCEL\nFlash\nmemory\nSRAM1 \n112 Kbyte\nSRAM2\n16 Kbyte\nAHB2\nperipherals\nAHB1\nperipherals\nFMC external\nMemCtl\nI-bus\nD-bus\nS-bus\nDMA_P1\nDMA_MEM1\nDMA_MEM2\nDMA_P2\nETHERNET_M\nUSB_HS_M\nMS30421V7\nCCM data RAM \n64-Kbyte\nAPB1\nAPB2\nSRAM3 \n64 Kbyte\nLCD-TFT\nChrom ART Accelerator(DMA2D)\nLCD-TFT_M\nDMA2D\n" }, { "page_number": 63, "page_indices": { "start_index": 250484, "end_index": 252586 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 63 }, "toc_details": [ [ 1, "2 Memory and bus architecture", 59 ], [ 2, "2.1 System architecture", 59 ], [ 3, "2.1.4 DMA memory bus", 63 ], [ 3, "2.1.5 DMA peripheral bus", 63 ], [ 3, "2.1.6 Ethernet DMA bus", 63 ], [ 3, "2.1.7 USB OTG HS DMA bus", 63 ], [ 3, "2.1.8 LCD-TFT controller DMA bus", 63 ], [ 3, "2.1.9 DMA2D bus", 63 ], [ 3, "2.1.10 BusMatrix", 63 ] ], "page_content": "RM0090 Rev 21\n63/1757\nRM0090\nMemory and bus architecture\n113\n2.1.4 \nDMA memory bus\nThis bus connects the DMA memory bus master interface to the BusMatrix. It is used by the \nDMA to perform transfer to/from memories. The targets of this bus are data memories: \ninternal SRAMs (SRAM1, SRAM2 and SRAM3) and external memories through the \nFSMC/FMC.\n2.1.5 \nDMA peripheral bus\nThis bus connects the DMA peripheral master bus interface to the BusMatrix. This bus is \nused by the DMA to access AHB peripherals or to perform memory-to-memory transfers. \nThe targets of this bus are the AHB and APB peripherals plus data memories: internal \nSRAMs (SRAM1, SRAM2 and SRAM3) and external memories through the FSMC/FMC.\n2.1.6 \nEthernet DMA bus\nThis bus connects the Ethernet DMA master interface to the BusMatrix. This bus is used by \nthe Ethernet DMA to load/store data to a memory. The targets of this bus are data \nmemories: internal SRAMs (SRAM1, SRAM2, SRAM3), internal flash memory, and external \nmemories through the FSMC/FMC.\n2.1.7 \nUSB OTG HS DMA bus\nThis bus connects the USB OTG HS DMA master interface to the BusMatrix. This bus is \nused by the USB OTG DMA to load/store data to a memory. The targets of this bus are data \nmemories: internal SRAMs (SRAM1, SRAM2, SRAM3), internal flash memory, and external \nmemories through the FSMC/FMC.\n2.1.8 \nLCD-TFT controller DMA bus\nThis bus connects the LCD controller DMA master interface to the BusMatrix. It is used by \nthe LCD-TFT DMA to load/store data to a memory. The targets of this bus are data \nmemories: internal SRAMs (SRAM1, SRAM2, SRAM3), external memories through FMC, \nand internal flash memory.\n2.1.9 \nDMA2D bus\nThis bus connect the DMA2D master interface to the BusMatrix. This bus is used by the \nDMA2D graphic Accelerator to load/store data to a memory. The targets of this bus are data \nmemories: internal SRAMs (SRAM1, SRAM2, SRAM3), external memories through FMC, \nand internal flash memory.\n2.1.10 \nBusMatrix\nThe BusMatrix manages the access arbitration between masters. The arbitration uses a \nround-robin algorithm.\n" }, { "page_number": 64, "page_indices": { "start_index": 252586, "end_index": 254638 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 64 }, "toc_details": [ [ 1, "2 Memory and bus architecture", 59 ], [ 2, "2.1 System architecture", 59 ], [ 3, "2.1.11 AHB/APB bridges (APB)", 64 ], [ 2, "2.2 Memory organization", 64 ], [ 2, "2.3 Memory map", 64 ] ], "page_content": "Memory and bus architecture\nRM0090\n64/1757\nRM0090 Rev 21\n2.1.11 \nAHB/APB bridges (APB)\nThe two AHB/APB bridges, APB1 and APB2, provide full synchronous connections between \nthe AHB and the two APB buses, allowing flexible selection of the peripheral frequency.\nRefer to the device datasheets for more details on APB1 and APB2 maximum frequencies, \nand to Table 1 for the address mapping of AHB and APB peripherals.\nAfter each device reset, all peripheral clocks are disabled (except for the SRAM and flash \nmemory interface). Before using a peripheral you have to enable its clock in the \nRCC_AHBxENR or RCC_APBxENR register.\nNote:\nWhen a 16- or an 8-bit access is performed on an APB register, the access is transformed \ninto a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.\n2.2 \nMemory organization\nProgram memory, data memory, registers and I/O ports are organized within the same linear \n4 Gbyte address space.\nThe bytes are coded in memory in little endian format. The lowest numbered byte in a word \nis considered the word’s least significant byte and the highest numbered byte, the word’s \nmost significant.\nFor the detailed mapping of peripheral registers, please refer to the related chapters.\nThe addressable memory space is divided into 8 main blocks, each of 512 MB.\nAll the memory areas that are not allocated to on-chip memories and peripherals are \nconsidered “Reserved”). Refer to the memory map figure in the product datasheet.\n2.3 \nMemory map\nSee the datasheet corresponding to your device for a comprehensive diagram of the \nmemory map. Table 1 gives the boundary addresses of the peripherals available in all \nSTM32F4xx devices.\n \nTable 1. STM32F4xx register boundary addresses\nBoundary address\nPeripheral\nBus\nRegister map\n0xA000 0000 - 0xA000 0FFF\nFSMC control register \n(STM32F405xx/07xx \nand \nSTM32F415xx/17xx)/\nFMC control register \n(STM32F42xxx and \nSTM32F43xxx)\nAHB3\nSection 36.6.9: FSMC register map on page 1603\nSection 37.8: FMC register map on page 1683\n" }, { "page_number": 65, "page_indices": { "start_index": 254638, "end_index": 256588 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 65 }, "toc_details": [ [ 1, "2 Memory and bus architecture", 59 ], [ 2, "2.3 Memory map", 64 ] ], "page_content": "RM0090 Rev 21\n65/1757\nRM0090\nMemory and bus architecture\n113\n0x5006 0800 - 0x5006 0BFF\nRNG\nAHB2\nSection 24.4.4: RNG register map on page 774\n0x5006 0400 - 0x5006 07FF\nHASH\nSection 25.4.9: HASH register map on page 798\n0x5006 0000 - 0x5006 03FF\nCRYP\nSection 23.6.13: CRYP register map on page 766\n0x5005 0000 - 0x5005 03FF\nDCMI\nSection 15.8.12: DCMI register map on page 481\n0x5000 0000 - 0x5003 FFFF\nUSB OTG FS\nSection 34.16.6: OTG_FS register map on \npage 1329\n0x4004 0000 - 0x4007 FFFF\nUSB OTG HS\nAHB1\nSection 35.12.6: OTG_HS register map on \npage 1475\n0x4002 B000 - 0x4002 BBFF\nDMA2D\nSection 11.5: DMA2D registers on page 355\n0x4002 8000 - 0x4002 93FF\nETHERNET MAC\nSection 33.8.5: Ethernet register maps on \npage 1239\n0x4002 6400 - 0x4002 67FF\nDMA2\nSection 10.5.11: DMA register map on page 338\n0x4002 6000 - 0x4002 63FF\nDMA1\n0x4002 4000 - 0x4002 4FFF\nBKPSRAM\n-\n0x4002 3C00 - 0x4002 3FFF\nFlash interface \nregister\nSection 3.9: Flash interface registers\n0x4002 3800 - 0x4002 3BFF\nRCC\nSection 7.3.24: RCC register map on page 267\n0x4002 3000 - 0x4002 33FF\nCRC\nSection 4.4.4: CRC register map on page 116\n0x4002 2800 - 0x4002 2BFF\nGPIOK\nSection 8.4.11: GPIO register map on page 290\n0x4002 2400 - 0x4002 27FF\nGPIOJ\n0x4002 2000 - 0x4002 23FF\nGPIOI\nSection 8.4.11: GPIO register map on page 290\n0x4002 1C00 - 0x4002 1FFF\nGPIOH\n0x4002 1800 - 0x4002 1BFF\nGPIOG\n0x4002 1400 - 0x4002 17FF\nGPIOF\n0x4002 1000 - 0x4002 13FF\nGPIOE\n0x4002 0C00 - 0x4002 0FFF\nGPIOD\n0x4002 0800 - 0x4002 0BFF\nGPIOC\n0x4002 0400 - 0x4002 07FF\nGPIOB\n0x4002 0000 - 0x4002 03FF\nGPIOA\n0x4001 6800 - 0x4001 6BFF\nLCD-TFT\nAPB2\nSection 16.7.26: LTDC register map on page 515\n0x4001 5800 - 0x4001 5BFF\nSAI1\nSection 29.17.9: SAI register map on page 966\n0x4001 5400 - 0x4001 57FF\nSPI6\nAPB2\nSection 28.5.10: SPI register map on page 928\n0x4001 5000 - 0x4001 53FF\nSPI5\nTable 1. STM32F4xx register boundary addresses (continued)\nBoundary address\nPeripheral\nBus\nRegister map\n" }, { "page_number": 66, "page_indices": { "start_index": 256588, "end_index": 257952 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 66 }, "toc_details": [ [ 1, "2 Memory and bus architecture", 59 ], [ 2, "2.3 Memory map", 64 ] ], "page_content": "Memory and bus architecture\nRM0090\n66/1757\nRM0090 Rev 21\n0x4001 4800 - 0x4001 4BFF\nTIM11\nAPB2\nSection 19.5.12: TIM10/11/13/14 register map on \npage 697\n0x4001 4400 - 0x4001 47FF\nTIM10\n0x4001 4000 - 0x4001 43FF\nTIM9\nSection 19.4.13: TIM9/12 register map on \npage 687\n0x4001 3C00 - 0x4001 3FFF\nEXTI\nSection 12.3.7: EXTI register map on page 390\n0x4001 3800 - 0x4001 3BFF\nSYSCFG\nSection 9.2.8: SYSCFG register maps for \nSTM32F405xx/07xx and STM32F415xx/17xx on \npage 297 and Section 9.3.8: SYSCFG register \nmaps for STM32F42xxx and STM32F43xxx on \npage 304\n0x4001 3400 - 0x4001 37FF\nSPI4\nAPB2\nSection 28.5.10: SPI register map on page 928\n0x4001 3000 - 0x4001 33FF\nSPI1\nAPB2\nSection 28.5.10: SPI register map on page 928\n0x4001 2C00 - 0x4001 2FFF\nSDIO\nSection 31.9.16: SDIO register map on page 1077\n0x4001 2000 - 0x4001 23FF\nADC1 - ADC2 - ADC3\nSection 13.13.18: ADC register map on page 433\n0x4001 1400 - 0x4001 17FF\nUSART6\nSection 30.6.8: USART register map on page 1021\n0x4001 1000 - 0x4001 13FF\nUSART1\n0x4001 0400 - 0x4001 07FF\nTIM8\nSection 17.4.21: TIM1 and TIM8 register map on \npage 590\n0x4001 0000 - 0x4001 03FF\nTIM1\n0x4000 7C00 - 0x4000 7FFF\nUART8\nAPB1\nSection 30.6.8: USART register map on page 1021\n0x4000 7800 - 0x4000 7BFF\nUART7\nTable 1. STM32F4xx register boundary addresses (continued)\nBoundary address\nPeripheral\nBus\nRegister map\n" }, { "page_number": 67, "page_indices": { "start_index": 257952, "end_index": 259649 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 67 }, "toc_details": [ [ 1, "2 Memory and bus architecture", 59 ], [ 2, "2.3 Memory map", 64 ] ], "page_content": "RM0090 Rev 21\n67/1757\nRM0090\nMemory and bus architecture\n113\n0x4000 7400 - 0x4000 77FF\nDAC\nAPB1\nSection 14.5.15: DAC register map on page 456\n0x4000 7000 - 0x4000 73FF\nPWR\nSection 5.6: PWR register map on page 151\n0x4000 6800 - 0x4000 6BFF\nCAN2\nSection 32.9.5: bxCAN register map on page 1121\n0x4000 6400 - 0x4000 67FF\nCAN1\n0x4000 5C00 - 0x4000 5FFF\nI2C3\nSection 27.6.11: I2C register map on page 875\n0x4000 5800 - 0x4000 5BFF\nI2C2\n0x4000 5400 - 0x4000 57FF\nI2C1\n0x4000 5000 - 0x4000 53FF\nUART5\nSection 30.6.8: USART register map on page 1021\n0x4000 4C00 - 0x4000 4FFF\nUART4\n0x4000 4800 - 0x4000 4BFF\nUSART3 \n0x4000 4400 - 0x4000 47FF\nUSART2\n0x4000 4000 - 0x4000 43FF\nI2S3ext\nSection 28.5.10: SPI register map on page 928\n0x4000 3C00 - 0x4000 3FFF\nSPI3 / I2S3\n0x4000 3800 - 0x4000 3BFF\nSPI2 / I2S2\n0x4000 3400 - 0x4000 37FF\nI2S2ext\n0x4000 3000 - 0x4000 33FF\nIWDG\nSection 21.4.5: IWDG register map on page 715\n0x4000 2C00 - 0x4000 2FFF\nWWDG\nSection 22.6.4: WWDG register map on page 722\n0x4000 2800 - 0x4000 2BFF\nRTC & BKP Registers\nSection 26.6.21: RTC register map on page 839\n0x4000 2000 - 0x4000 23FF\nTIM14\nSection 19.5.12: TIM10/11/13/14 register map on \npage 697\n0x4000 1C00 - 0x4000 1FFF\nTIM13\n0x4000 1800 - 0x4000 1BFF\nTIM12\nSection 19.4.13: TIM9/12 register map on \npage 687\n0x4000 1400 - 0x4000 17FF\nTIM7\nSection 20.4.9: TIM6 and TIM7 register map on \npage 710\n0x4000 1000 - 0x4000 13FF\nTIM6\n0x4000 0C00 - 0x4000 0FFF\nTIM5\nSection 18.4.21: TIMx register map on page 651\n0x4000 0800 - 0x4000 0BFF\nTIM4\n0x4000 0400 - 0x4000 07FF\nTIM3\n0x4000 0000 - 0x4000 03FF\nTIM2\nTable 1. STM32F4xx register boundary addresses (continued)\nBoundary address\nPeripheral\nBus\nRegister map\n" }, { "page_number": 68, "page_indices": { "start_index": 259649, "end_index": 262376 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 68 }, "toc_details": [ [ 1, "2 Memory and bus architecture", 59 ], [ 2, "2.3 Memory map", 64 ], [ 3, "2.3.1 Embedded SRAM", 68 ], [ 3, "2.3.2 Flash memory overview", 68 ], [ 3, "2.3.3 Bit banding", 68 ] ], "page_content": "Memory and bus architecture\nRM0090\n68/1757\nRM0090 Rev 21\n2.3.1 \nEmbedded SRAM\nThe STM32F405xx/07xx and STM32F415xx/17xx feature 4 Kbytes of backup SRAM (see \nSection 5.1.2: Battery backup domain) plus 192 Kbytes of system SRAM.\nThe STM32F42xxx and STM32F43xxx feature 4 Kbytes of backup SRAM (see \nSection 5.1.2: Battery backup domain) plus 256 Kbytes of system SRAM.\nThe embedded SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). \nRead and write operations are performed at CPU speed with 0 wait state. The embedded \nSRAM is divided into up to three blocks:\n•\nSRAM1 and SRAM2 mapped at address 0x2000 0000 and accessible by all AHB \nmasters.\n•\nSRAM3 (available on STM32F42xxx and STM32F43xxx) mapped at address \n0x2002 0000 and accessible by all AHB masters. \n•\nCCM (core coupled memory) mapped at address 0x1000 0000 and accessible only by \nthe CPU through the D-bus.\nThe AHB masters support concurrent SRAM accesses (from the Ethernet or the USB OTG \nHS): for instance, the Ethernet MAC can read/write from/to SRAM2 while the CPU is \nreading/writing from/to SRAM1 or SRAM3.\nThe CPU can access the SRAM1 through the System bus or through the I-Code/D-Code \nbuses when boot from SRAM is selected or when physical remap is selected (Section 9.2.1: \nSYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller). To get \nthe max performance on SRAM execution, physical remap should be selected (boot or \nsoftware selection).\n2.3.2 \nFlash memory overview\nThe flash memory interface manages CPU AHB I-Code and D-Code accesses to the flash \nmemory. It implements the erase and program flash memory operations and the read and \nwrite protection mechanisms. It accelerates code execution with a system of instruction \nprefetch and cache lines.\nThe flash memory is organized as follows:\n•\nA main memory block divided into sectors.\n•\nSystem memory from which the device boots in System memory boot mode\n•\n512 OTP (one-time programmable) bytes for user data.\n•\nOption bytes to configure read and write protection, BOR level, watchdog \nsoftware/hardware and reset when the device is in Standby or Stop mode.\nRefer to Section 3: Embedded flash memory interface for more details.\n2.3.3 \nBit banding\nThe Cortex®-M4 with FPU memory map includes two bit-band regions. These regions map \neach word in an alias region of memory to a bit in a bit-band region of memory. Writing to a \nword in the alias region has the same effect as a read-modify-write operation on the \ntargeted bit in the bit-band region.\nIn the STM32F4xx devices both the peripheral registers and the SRAM are mapped to a bit-\nband region, so that single bit-band write and read operations are allowed. The operations \n" }, { "page_number": 69, "page_indices": { "start_index": 262376, "end_index": 264590 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 69 }, "toc_details": [ [ 1, "2 Memory and bus architecture", 59 ], [ 2, "2.3 Memory map", 64 ], [ 3, "2.3.3 Bit banding", 68 ], [ 4, "Example", 69 ], [ 2, "2.4 Boot configuration", 69 ] ], "page_content": "RM0090 Rev 21\n69/1757\nRM0090\nMemory and bus architecture\n113\nare only available for Cortex®-M4 with FPU accesses, and not from other bus masters (e.g. \nDMA).\nA mapping formula shows how to reference each word in the alias region to a corresponding \nbit in the bit-band region. The mapping formula is:\nbit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4)\nwhere:\n–\nbit_word_addr is the address of the word in the alias memory region that maps to \nthe targeted bit\n–\nbit_band_base is the starting address of the alias region\n–\nbyte_offset is the number of the byte in the bit-band region that contains the \ntargeted bit\n–\nbit_number is the bit position (0-7) of the targeted bit\nExample\nThe following example shows how to map bit 2 of the byte located at SRAM address \n0x20000300 to the alias region:\n0x22006008 = 0x22000000 + (0x300*32) + (2*4)\nWriting to address 0x22006008 has the same effect as a read-modify-write operation on bit \n2 of the byte at SRAM address 0x20000300.\nReading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM \naddress 0x20000300 (0x01: bit set; 0x00: bit reset).\nFor more information on bit-banding, please refer to the Cortex®-M4 with FPU programming \nmanual (see Related documents on page 1).\n2.4 \nBoot configuration\nDue to its fixed memory map, the code area starts from address 0x0000 0000 (accessed \nthrough the ICode/DCode buses) while the data area (SRAM) starts from address \n0x2000 0000 (accessed through the system bus). The Cortex®-M4 with FPU CPU always \nfetches the reset vector on the ICode bus, which implies to have the boot space available \nonly in the code area (typically, flash memory). STM32F4xx microcontrollers implement a \nspecial mechanism to be able to boot from other memories (like the internal SRAM).\nIn the STM32F4xx, three different boot modes can be selected through the BOOT[1:0] pins \nas shown in Table 2.\n \nTable 2. Boot modes\nBoot mode selection pins\nBoot mode\nAliasing\nBOOT1\nBOOT0\nx\n0\nMain flash memory\nMain flash memory is selected as the boot space\n0\n1\nSystem memory\nSystem memory is selected as the boot space\n1\n1\nEmbedded SRAM\nEmbedded SRAM is selected as the boot space\n" }, { "page_number": 70, "page_indices": { "start_index": 264590, "end_index": 267273 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 70 }, "toc_details": [ [ 1, "2 Memory and bus architecture", 59 ], [ 2, "2.4 Boot configuration", 69 ], [ 3, "Embedded bootloader", 70 ], [ 3, "Physical remap in STM32F405xx/07xx and STM32F415xx/17xx", 70 ] ], "page_content": "Memory and bus architecture\nRM0090\n70/1757\nRM0090 Rev 21\nThe values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It \nis up to the user to set the BOOT1 and BOOT0 pins after reset to select the required boot \nmode.\nBOOT0 is a dedicated pin while BOOT1 is shared with a GPIO pin. Once BOOT1 has been \nsampled, the corresponding GPIO pin is free and can be used for other purposes.\nThe BOOT pins are also resampled when the device exits the Standby mode. Consequently, \nthey must be kept in the required Boot mode configuration when the device is in the Standby \nmode. After this startup delay is over, the CPU fetches the top-of-stack value from address \n0x0000 0000, then starts code execution from the boot memory starting from 0x0000 0004.\nNote:\nWhen the device boots from SRAM, in the application initialization code, you have to \nrelocate the vector table in SRAM using the NVIC exception table and the offset register.\nIn STM32F42xxx and STM32F43xxx devices, when booting from the main flash memory, \nthe application software can either boot from bank 1 or from bank 2. By default, boot from \nbank 1 is selected.\nTo select boot from flash memory bank 2, set the BFB2 bit in the user option bytes. When \nthis bit is set and the boot pins are in the boot from main flash memory configuration, the \ndevice boots from system memory, and the boot loader jumps to execute the user \napplication programmed in flash memory bank 2. For further details, please refer to \nAN2606.\nEmbedded bootloader\nThe embedded bootloader mode is used to reprogram the flash memory using one of the \nfollowing serial interfaces:\n•\nUSART1 (PA9/PA10)\n•\nUSART3 (PB10/11 and PC10/11)\n•\nCAN2 (PB5/13)\n•\nUSB OTG FS (PA11/12) in Device mode (DFU: device firmware upgrade).\nThe USART peripherals operate at the internal 16 MHz oscillator (HSI) frequency, while the \nCAN and USB OTG FS require an external clock (HSE) multiple of 1 MHz (ranging from 4 to \n26 MHz).\nThe embedded bootloader code is located in system memory. It is programmed by ST \nduring production. For additional information, refer to application note AN2606.\nPhysical remap in STM32F405xx/07xx and STM32F415xx/17xx\nOnce the boot pins are selected, the application software can modify the memory \naccessible in the code area (in this way the code can be executed through the ICode bus in \nplace of the System bus). This modification is performed by programming the Section 9.2.1: \nSYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller.\nThe following memories can thus be remapped:\n•\nMain flash memory\n•\nSystem memory\n•\nEmbedded SRAM1 (112 KB)\n•\nFSMC bank 1 (NOR/PSRAM 1 and 2)\n" }, { "page_number": 71, "page_indices": { "start_index": 267273, "end_index": 269836 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 71 }, "toc_details": [ [ 1, "2 Memory and bus architecture", 59 ], [ 2, "2.4 Boot configuration", 69 ], [ 3, "Physical remap in STM32F42xxx and STM32F43xxx", 71 ] ], "page_content": "RM0090 Rev 21\n71/1757\nRM0090\nMemory and bus architecture\n113\n \nPhysical remap in STM32F42xxx and STM32F43xxx\nOnce the boot pins are selected, the application software can modify the memory \naccessible in the code area (in this way the code can be executed through the ICode bus in \nplace of the System bus). This modification is performed by programming the Section 9.2.1: \nSYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller.\nThe following memories can thus be remapped:\n•\nMain flash memory\n•\nSystem memory\n•\nEmbedded SRAM1 (112 KB)\n•\nFMC bank 1 (NOR/PSRAM 1 and 2)\n•\nFMC SDRAM bank 1\n \nTable 3. Memory mapping vs. Boot mode/physical remap\nin STM32F405xx/07xx and STM32F415xx/17xx\nAddresses\nBoot/Remap in \nmain flash memory\nBoot/Remap in \nembedded SRAM\nBoot/Remap in \nSystem memory\nRemap in FSMC\n0x2001 C000 - 0x2001 FFFF\nSRAM2 (16 KB)\nSRAM2 (16 KB)\nSRAM2 (16 KB)\nSRAM2 (16 KB)\n0x2000 0000 - 0x2001 BFFF\nSRAM1 (112 KB)\nSRAM1 (112 KB)\nSRAM1 (112 KB)\nSRAM1 (112 KB)\n0x1FFF 0000 - 0x1FFF 77FF\nSystem memory\nSystem memory\nSystem memory\nSystem memory\n0x0810 0000 - 0x0FFF FFFF\nReserved\nReserved\nReserved\nReserved\n0x0800 0000 - 0x080F FFFF\nFlash memory\nFlash memory\nFlash memory\nFlash memory\n0x0400 0000 - 0x07FF FFFF\nReserved\nReserved\nReserved\nFSMC bank 1 \nNOR/PSRAM 2 \n(128 MB Aliased)\n0x0000 0000 - \n0x000F FFFF(1)(2)\nFlash (1 MB) Aliased\nSRAM1 (112 KB) \nAliased\nSystem memory \n(30 KB) Aliased\nFSMC bank 1 \nNOR/PSRAM 1 \n(128 MB Aliased)\n1.\nWhen the FSMC is remapped at address 0x0000 0000, only the first two regions of bank 1 memory controller (bank 1 \nNOR/PSRAM 1 and NOR/PSRAM 2) can be remapped. In remap mode, the CPU can access the external memory via \nICode bus instead of System bus which boosts up the performance.\n2.\nEven when aliased in the boot memory space, the related memory is still accessible at its original memory space.\nTable 4. Memory mapping vs. Boot mode/physical remap\nin STM32F42xxx and STM32F43xxx\nAddresses\nBoot/Remap in \nmain flash memory\nBoot/Remap in \nembedded SRAM\nBoot/Remap in \nSystem memory\nRemap in FMC\n0x2002 0000 - 0x2002 FFFF\nSRAM3 (64 KB)\nSRAM3 (64 KB)\nSRAM3 (64 KB)\nSRAM3 (64 KB)\n0x2001 C000 - 0x2001 FFFF\nSRAM2 (16 KB)\nSRAM2 (16 KB)\nSRAM2 (16 KB)\nSRAM2 (16 KB)\n0x2000 0000 - 0x2001 BFFF\nSRAM1 (112 KB)\nSRAM1 (112 KB)\nSRAM1 (112 KB)\nSRAM1 (112 KB)\n0x1FFF 0000 - 0x1FFF 77FF\nSystem memory\nSystem memory\nSystem memory\nSystem memory\n0x0810 0000 - 0x0FFF FFFF\nReserved\nReserved\nReserved\nReserved\n0x0800 0000 - 0x081F FFFF\nFlash memory\nFlash memory\nFlash memory\nFlash memory\n" }, { "page_number": 72, "page_indices": { "start_index": 269836, "end_index": 270828 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 72 }, "toc_details": [ [ 1, "2 Memory and bus architecture", 59 ], [ 2, "2.4 Boot configuration", 69 ], [ 3, "Physical remap in STM32F42xxx and STM32F43xxx", 71 ] ], "page_content": "Memory and bus architecture\nRM0090\n72/1757\nRM0090 Rev 21\n0x0400 0000 - 0x07FF FFFF\nReserved\nReserved\nReserved\nFMC bank 1 \nNOR/PSRAM 2 \n(128 MB Aliased) \n0x0000 0000 - \n0x001F FFFF(1)(2)\nFlash (2 MB) Aliased\nSRAM1 (112 KB) \nAliased\nSystem memory \n(30 KB) Aliased\nFMC bank 1 \nNOR/PSRAM 1 \n(128 MB Aliased)\nor FMC SDRAM \nbank 1 (128 MB \nAliased)\n1.\nWhen the FMC is remapped at address 0x0000 0000, only the first two regions of bank 1 memory controller (bank 1 \nNOR/PSRAM 1 and NOR/PSRAM 2) or SDRAM bank 1 can be remapped. In remap mode, the CPU can access the \nexternal memory via ICode bus instead of System bus which boosts up the performance.\n2.\nEven when aliased in the boot memory space, the related memory is still accessible at its original memory space.\nTable 4. Memory mapping vs. Boot mode/physical remap\nin STM32F42xxx and STM32F43xxx (continued)\nAddresses\nBoot/Remap in \nmain flash memory\nBoot/Remap in \nembedded SRAM\nBoot/Remap in \nSystem memory\nRemap in FMC\n" }, { "page_number": 73, "page_indices": { "start_index": 270828, "end_index": 272122 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 73 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.1 Introduction", 73 ], [ 2, "3.2 Main features", 73 ] ], "page_content": "RM0090 Rev 21\n73/1757\nRM0090\nEmbedded flash memory interface\n113\n3 \nEmbedded flash memory interface\n3.1 \nIntroduction\nThe flash memory interface manages CPU AHB I-Code and D-Code accesses to the flash \nmemory. It implements the erase and program flash memory operations and the read and \nwrite protection mechanisms.\nThe flash memory interface accelerates code execution with a system of instruction prefetch \nand cache lines.\n3.2 \nMain features\n•\nFlash memory read operations\n•\nFlash memory program/erase operations\n•\nRead / write protections\n•\nPrefetch on I-Code\n•\n64 cache lines of 128 bits on I-Code\n•\n8 cache lines of 128 bits on D-Code\nFigure 3 shows the flash memory interface connection inside the system architecture.\nFigure 3. Flash memory interface connection inside system architecture\n (STM32F405xx/07xx and STM32F415xx/17xx)\nCortex\ncore\nEthernet\nUSB HS\nDMA1\nDMA2\nD-code bus\nI-Code bus\nCortex-M4 with FPU\nI-Code\nD-Code\nS bus\nAHB \nperiph1\nFlash \nmemory\nFlash interface\n \nSRAM and\nExternal \nmemories \nAHB\nperiph2\nFLITF registers\nAHB\n32-bit\ninstruction \nbus\nAccess to instruction in Flash memory\nAccess to data and literal pool in Flash memory \nFLITF register access\n \nMS30468V3\nCCM data \nRAM\nAHB\n32-bit\ndata bus\nAHB\n32-bit\nsystem bus\nFlash \nmemory\nbus \n128 bits\n" }, { "page_number": 74, "page_indices": { "start_index": 272122, "end_index": 273628 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 74 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.3 Embedded flash memory in STM32F405xx/07xx and STM32F415xx/17xx", 74 ] ], "page_content": "Embedded flash memory interface\nRM0090\n74/1757\nRM0090 Rev 21\nFigure 4. Flash memory interface connection inside system architecture\n(STM32F42xxx and STM32F43xxx)\n3.3 \nEmbedded flash memory in \nSTM32F405xx/07xx and STM32F415xx/17xx\nThe flash memory has the following main features:\n•\nCapacity up to 1 Mbyte\n•\n128 bits wide data read\n•\nByte, half-word, word and double word write\n•\nSector and mass erase\n•\nMemory organization\nThe flash memory is organized as follows:\n–\nA main memory block divided into 4 sectors of 16 Kbytes, 1 sector of 64 Kbytes, \nand 7 sectors of 128 Kbytes\n–\nSystem memory from which the device boots in System memory boot mode\n–\n512 OTP (one-time programmable) bytes for user data\nThe OTP area contains 16 additional bytes used to lock the corresponding OTP \ndata block.\n–\nOption bytes to configure read and write protection, BOR level, watchdog \nsoftware/hardware and reset when the device is in Standby or Stop mode.\n•\nLow-power modes (for details refer to the Power control (PWR) section of the reference \nmanual)\nCortex\ncore\nEthernet\nUSB HS\nDMA1\nDMA2\nD-code bus\nI-Code bus\nCortex-M4 with FPU\nI-Code\nD-Code\nS bus\nAHB\nperiph1\nFlash \nmemory\nFlash interface\n \nSRAM and\nexternal \nmemories \nAHB\nperiph2\nFLITF registers\nAHB\n32-bit\ninstruction \nbus\nAccess to instruction in Flash memory\nAccess to data and literal pool in Flash memory \nFLITF register access\n \nMS30466V3\nCCM data \nRAM\nAHB\n32-bit\ndata bus\nAHB\n32-bit\nsystem bus\nFlash \nmemory\nbus \n128 bits\nDMA2D\nLCD-TFT\n" }, { "page_number": 75, "page_indices": { "start_index": 273628, "end_index": 274360 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 75 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.3 Embedded flash memory in STM32F405xx/07xx and STM32F415xx/17xx", 74 ] ], "page_content": "RM0090 Rev 21\n75/1757\nRM0090\nEmbedded flash memory interface\n113\n \nTable 5. Flash module organization (STM32F40x and STM32F41x)\nBlock\nName\nBlock base addresses\nSize\nMain memory\nSector 0\n0x0800 0000 - 0x0800 3FFF\n16 Kbytes\nSector 1\n0x0800 4000 - 0x0800 7FFF\n16 Kbytes\nSector 2\n0x0800 8000 - 0x0800 BFFF\n16 Kbytes\nSector 3\n0x0800 C000 - 0x0800 FFFF\n16 Kbytes\nSector 4\n0x0801 0000 - 0x0801 FFFF\n64 Kbytes\nSector 5\n0x0802 0000 - 0x0803 FFFF\n128 Kbytes\nSector 6\n0x0804 0000 - 0x0805 FFFF\n128 Kbytes\n.\n.\n.\n.\n.\n.\n.\n.\n.\nSector 11\n0x080E 0000 - 0x080F FFFF\n128 Kbytes\nSystem memory\n0x1FFF 0000 - 0x1FFF 77FF\n30 Kbytes\nOTP area \n0x1FFF 7800 - 0x1FFF 7A0F\n528 bytes\nOption bytes\n0x1FFF C000 - 0x1FFF C00F\n16 bytes\n" }, { "page_number": 76, "page_indices": { "start_index": 274360, "end_index": 276690 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 76 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.4 Embedded flash memory in STM32F42xxx and STM32F43xxx", 76 ] ], "page_content": "Embedded flash memory interface\nRM0090\n76/1757\nRM0090 Rev 21\n3.4 \nEmbedded flash memory in STM32F42xxx and STM32F43xxx\nThe flash memory has the following main features:\n•\nCapacity up to 2 Mbyte with dual bank architecture supporting read-while-write \ncapability (RWW)\n•\n128 bits wide data read\n•\nByte, half-word, word and double word write\n•\nSector, bank, and mass erase (both banks)\n•\nDual bank memory organization\nThe dual bank organization is available only on 1 Mbyte and 2 Mbyte devices.\nThe flash memory is organized as follows:\n–\nFor each bank, a main memory block (1 Mbyte) divided into 4 sectors of 16 \nKbytes, 1 sector of 64 Kbytes, and 7 sectors of 128 Kbytes\n–\nSystem memory from which the device boots in System memory boot mode\n–\n512 OTP (one-time programmable) bytes for user data\nThe OTP area contains 16 additional bytes used to lock the corresponding OTP \ndata block.\n–\nOption bytes to configure read and write protection, BOR level, watchdog, dual \nbank boot mode, dual bank feature, software/hardware and reset when the device \nis in Standby or Stop mode.\n•\nDual bank organization on 1 Mbyte devices\nThe dual bank feature on 1 Mbyte devices is enabled by setting the DB1M option bit.\nTo obtain a dual bank flash memory, the last 512 Kbytes of the single bank (sectors \n[8:11]) are re-structured in the same way as the first 512 Kbytes. \nThe sector numbering of dual bank memory organization is different from the single \nbank: the single bank memory contains 12 sectors whereas the dual bank memory \ncontains 16 sectors (see Table 7: 1 Mbyte flash memory single bank vs dual bank \norganization (STM32F42xxx and STM32F43xxx)). \nFor erase operation, the right sector numbering must be considered according the \nDB1M option bit.\n–\nWhen the DB1M bit is reset, the erase operation must be performed on the default \nsector number.\n–\nWhen the DB1M bit is set, to perform an erase operation on bank 2, the sector \nnumber must be programmed (sector number from 12 to 19). Refer to FLASH_CR \nregister for SNB (Sector number) configuration.\nRefer to Table 8: 1 Mbyte single bank flash memory organization (STM32F42xxx and \nSTM32F43xxx) and Table 9: 1 Mbyte dual bank flash memory organization (STM32F42xxx \nand STM32F43xxx) for details on 1 Mbyte single bank and 1 Mbyte dual bank \norganizations.\n" }, { "page_number": 77, "page_indices": { "start_index": 276690, "end_index": 277915 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 77 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.4 Embedded flash memory in STM32F42xxx and STM32F43xxx", 76 ] ], "page_content": "RM0090 Rev 21\n77/1757\nRM0090\nEmbedded flash memory interface\n113\n \nTable 6. Flash module - 2 Mbyte dual bank organization (STM32F42xxx and STM32F43xxx)\nBlock\nBank\nName\nBlock base addresses\nSize\nMain memory\nBank 1\nSector 0\n0x0800 0000 - 0x0800 3FFF\n16 Kbytes\nSector 1\n0x0800 4000 - 0x0800 7FFF\n16 Kbytes\nSector 2\n0x0800 8000 - 0x0800 BFFF\n16 Kbytes\nSector 3\n0x0800 C000 - 0x0800 FFFF\n16 Kbyte\nSector 4\n0x0801 0000 - 0x0801 FFFF\n64 Kbytes\nSector 5\n0x0802 0000 - 0x0803 FFFF\n128 Kbytes\nSector 6\n0x0804 0000 - 0x0805 FFFF \n128 Kbytes\n .\n - \n - \n .\n - \n - \n - \n - \n - \nSector 11\n0x080E 0000 - 0x080F FFFF\n128 Kbytes\nBank 2\nSector 12\n0x0810 0000 - 0x0810 3FFF\n16 Kbytes\nSector 13\n0x0810 4000 - 0x0810 7FFF\n16 Kbytes\nSector 14\n0x0810 8000 - 0x0810 BFFF\n16 Kbytes\nSector 15\n0x0810 C000 - 0x0810 FFFF\n16 Kbytes\nSector 16\n0x0811 0000 - 0x0811 FFFF\n64 Kbytes\nSector 17\n0x0812 0000 - 0x0813 FFFF\n128 Kbytes\nSector 18\n0x0814 0000 - 0x0815 FFFF\n128 Kbytes\n.\n.\n.\n.\n.\n.\n.\n.\n.\nSector 23\n0x081E 0000 - 0x081F FFFF\n128 Kbytes\nSystem memory\n0x1FFF 0000 - 0x1FFF 77FF\n30 Kbytes\nOTP\n0x1FFF 7800 - 0x1FFF 7A0F\n528 bytes\nOption bytes \nBank 1\n0x1FFF C000 - 0x1FFF C00F \n16 bytes\nBank 2\n0x1FFE C000 - 0x1FFE C00F\n16 bytes\n" }, { "page_number": 78, "page_indices": { "start_index": 277915, "end_index": 279585 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 78 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.4 Embedded flash memory in STM32F42xxx and STM32F43xxx", 76 ] ], "page_content": "Embedded flash memory interface\nRM0090\n78/1757\nRM0090 Rev 21\n \n \nTable 7. 1 Mbyte flash memory single bank vs dual bank organization\n (STM32F42xxx and STM32F43xxx)\n 1 Mbyte single bank flash memory (default)\n1 Mbyte dual bank flash memory\nDB1M=0\nDB1M=1\nMain memory\nSector number\nSector size\nMain memory\nSector number\nSector size\n1MB\nSector 0\n16 Kbytes\nBank 1\n512KB\nSector 0\n16 Kbytes\nSector 1\n16 Kbytes\nSector 1\n16 Kbytes\nSector 2\n16 Kbytes\nSector 2\n16 Kbytes\nSector 3\n16 Kbytes\nSector 3\n16 Kbytes\nSector 4\n64 Kbytes\nSector 4\n64 Kbytes\nSector 5\n128 Kbytes\nSector 5\n128 Kbytes\nSector 6\n128 Kbytes\nSector 6\n128 Kbytes\nSector 7\n128 Kbytes\nSector 7\n128 Kbytes\nSector 8\n128 Kbytes\nBank 2\n512KB\nSector 12\n16 Kbytes\nSector 9\n128 Kbytes\nSector 13\n16 Kbytes\nSector 10\n128 Kbytes\nSector 14\n16 Kbytes\nSector 11\n128 Kbytes\nSector 15\n16 Kbytes\n-\n-\nSector 16\n64 Kbytes\n-\n-\nSector 17\n128 Kbytes\n-\n-\nSector 18\n128 Kbytes\n-\n-\nSector 19\n128 Kbytes\nTable 8. 1 Mbyte single bank flash memory organization\n(STM32F42xxx and STM32F43xxx)\nBlock\nBank\nName\nBlock base addresses\nSize\nMain memory\nSingle bank \nSector 0\n0x0800 0000 - 0x0800 3FFF\n16 Kbytes\nSector 1\n0x0800 4000 - 0x0800 7FFF\n16 Kbytes\nSector 2\n0x0800 8000 - 0x0800 BFFF\n16 Kbytes\nSector 3\n0x0800 C000 - 0x0800 FFFF\n16 Kbytes\nSector 4\n0x0801 0000 - 0x0801 FFFF\n64 Kbytes\nSector 5\n0x0802 0000 - 0x0803 FFFF\n128 Kbytes\nSector 6\n0x0804 0000 - 0x0805 FFFF \n128 Kbytes\nSector 7\n0x0806 0000 - 0x0807 FFFF \n128 Kbytes\nSector 8\n0x0808 0000 - 0x0809 FFFF\n128 Kbytes\nSector 9\n0x080A 0000 - 0x080B FFFF\n128 Kbytes\nSector 10\n0x080C 0000 - 0x080D FFFF\n128 Kbytes\nSector 11\n0x080E 0000 - 0x080F FFFF\n128 Kbytes\n" }, { "page_number": 79, "page_indices": { "start_index": 279585, "end_index": 281067 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 79 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.4 Embedded flash memory in STM32F42xxx and STM32F43xxx", 76 ] ], "page_content": "RM0090 Rev 21\n79/1757\nRM0090\nEmbedded flash memory interface\n113\n \nSystem memory\n0x1FFF 0000 - 0x1FFFF 77FF\n30 Kbytes\nOTP\n0x1FFF 7800 - 0x1FFF 7A0F\n528 bytes\nOption bytes \n0x1FFF C000 - 0x1FFF C00F \n16 bytes\n0x1FFE C000 - 0x1FFE C00F\n16 bytes\nTable 8. 1 Mbyte single bank flash memory organization\n(STM32F42xxx and STM32F43xxx) (continued)\nBlock\nBank\nName\nBlock base addresses\nSize\nTable 9. 1 Mbyte dual bank flash memory organization (STM32F42xxx and STM32F43xxx)\nBlock\nName\nBlock base addresses\nSize\nMain memory\nBank 1\nSector 0\n0x0800 0000 - 0x0800 3FFF\n16 Kbytes\nSector 1\n0x0800 4000 - 0x0800 7FFF\n16 Kbytes\nSector 2\n0x0800 8000 - 0x0800 BFFF\n16 Kbytes\nSector 3\n0x0800 C000 - 0x0800 FFFF\n16 Kbyte\nSector 4\n0x0801 0000 - 0x0801 FFFF\n64 Kbytes\nSector 5\n0x0802 0000 - 0x0803 FFFF\n128 Kbytes\nSector 6\n0x0804 0000 - 0x0805 FFFF \n128 Kbytes\n Sector 7\n0x0806 0000 - 0x0807 FFFF \n128 Kbytes\nBank 2\nSector 12\n0x0808 0000 - 0x0808 3FFF\n16 Kbytes\nSector 13\n0x0808 4000 - 0x0808 7FFF\n16 Kbytes\nSector 14\n0x0808 0000 - 0x0808 BFFF\n16 Kbytes\nSector 15\n0x0808 C000 - 0x0808 FFFF\n16 Kbytes\nSector 16\n0x0809 0000 - 0x0809 FFFF\n64 Kbytes\nSector 17\n0x080A 0000 - 0x080B FFFF\n128 Kbytes\nSector 18\n0x080C 0000 - 0x080D FFFF\n128 Kbytes\nSector 19\n0x080E 0000 - 0x080F FFFF\n128 Kbytes\nSystem memory\n0x1FFF 0000 - 0x1FFF 77FF\n30 Kbytes\nOTP\n0x1FFF 7800 - 0x1FFF 7A0F\n528 bytes\nOption bytes \nBank 1\n0x1FFF C000 - 0x1FFF C00F \n16 bytes\nBank 2\n0x1FFE C000 - 0x1FFE C00F\n16 bytes\n" }, { "page_number": 80, "page_indices": { "start_index": 281067, "end_index": 283109 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 80 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.5 Read interface", 80 ], [ 3, "3.5.1 Relation between CPU clock frequency and flash memory read time", 80 ] ], "page_content": "Embedded flash memory interface\nRM0090\n80/1757\nRM0090 Rev 21\n \n3.5 \nRead interface\n3.5.1 \nRelation between CPU clock frequency and flash memory read time\nTo correctly read data from flash memory, the number of wait states (LATENCY) must be \ncorrectly programmed in the Flash access control register (FLASH_ACR) according to the \nfrequency of the CPU clock (HCLK) and the supply voltage of the device. \nThe prefetch buffer must be disabled when the supply voltage is below 2.1 V. The \ncorrespondence between wait states and CPU clock frequency is given in Table 11 and \nTable 12.\nNote:\nOn STM32F405xx/07xx and STM32F415xx/17xx devices: \n- when VOS = '0', the maximum value of fHCLK = 144 MHz. \n- when VOS = '1', the maximum value of fHCLK = 168 MHz. \nOn STM32F42xxx and STM32F43xxx devices:\n- when VOS[1:0] = '0x01', the maximum value of fHCLK is 120 MHz.\n- when VOS[1:0] = '0x10', the maximum value of fHCLK is 144 MHz. It can be extended to \n168 MHz by activating the over-drive mode.\n- when VOS[1:0] = '0x11, the maximum value of fHCLK is 168 MHz. It can be extended to \n180 MHz by activating the over-drive mode. \n- The over-drive mode is not available when VDD ranges from 1.8 to 2.1 V. \nRefer to Section 5.1.4: Voltage regulator for STM32F42xxx and STM32F43xxx for details on \nhow to activate the over-drive mode. \nTable 10. 512 Kbyte single bank flash memory organization\n(STM32F42xxx and STM32F43xxx)\nBlock\nBank\nName\n Block base addresses\nSize\nMain memory\nSingle Bank\nSector 0\n0x0800 0000 - 0x0800 3FFF\n16 Kbytes\nSector 1\n0x0800 4000 - 0x0800 7FFF\n16 Kbytes\nSector 2\n0x0800 8000 - 0x0800 BFFF\n16 Kbytes\nSector 3\n 0x0800 C000 - 0x0800 FFFF\n16 Kbytes\nSector 4\n0x0801 0000 - 0x0801 FFFF\n64 Kbytes\nSector 5\n0x0802 0000 - 0x0803 FFFF\n128 Kbytes\nSector 6\n0x0804 0000 - 0x0805 FFFF\n128 Kbytes\nSector 7\n0x0806 0000 - 0x0807 FFFF\n128 Kbytes\nSystem memory\n0x1FFF 0000 - 0x1FFFF 77FF\n30 Kbytes\nOTP\n0x1FFF 7800 - 0x1FFF 7A0F\n528 bytes\nOption bytes\n0x1FFF C000 - 0x1FFF C00F\n16 bytes\n0x1FFE C000 - 0x1FFE C00F\n16 bytes\n" }, { "page_number": 81, "page_indices": { "start_index": 283109, "end_index": 285302 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 81 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.5 Read interface", 80 ], [ 3, "3.5.1 Relation between CPU clock frequency and flash memory read time", 80 ] ], "page_content": "RM0090 Rev 21\n81/1757\nRM0090\nEmbedded flash memory interface\n113\nAfter reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is configured in the \nFLASH_ACR register.\nIt is highly recommended to use the following software sequences to tune the number of \nwait states needed to access the flash memory with the CPU frequency.\nTable 11. Number of wait states according to CPU clock (HCLK) frequency \n(STM32F405xx/07xx and STM32F415xx/17xx)\nWait states (WS)\n(LATENCY)\nHCLK (MHz)\nVoltage range\n2.7 V - 3.6 V\nVoltage range\n2.4 V - 2.7 V\nVoltage range\n2.1 V - 2.4 V\nVoltage range\n1.8 V - 2.1 V\nPrefetch OFF\n0 WS (1 CPU cycle)\n0 < HCLK ≤ 30\n0 < HCLK ≤ 24\n0 < HCLK ≤ 22\n0 < HCLK ≤ 20\n1 WS (2 CPU cycles)\n30 < HCLK ≤ 60\n24 < HCLK ≤ 48\n22 < HCLK ≤ 44\n20 1, 1->2, 0->2) \nthere is no mass erase.\n•\nLevel 2: debug/chip read protection disabled\nThe read protection Level 2 is activated by writing 0xCC to the RDP option byte. When \nthe read protection Level 2 is set:\n–\nAll protections provided by Level 1 are active. \n–\nBooting from RAM or system memory bootloader is no more allowed.\n–\nJTAG, SWV (single-wire viewer), ETM, and boundary scan are disabled.\n–\nUser option bytes can no longer be changed.\n–\nWhen booting from flash memory, accesses (read, erase and program) to flash \nmemory and backup SRAM from user code are allowed.\nMemory read protection Level 2 is an irreversible operation. When Level 2 is activated, \nthe level of protection cannot be decreased to Level 0 or Level 1.\n" }, { "page_number": 94, "page_indices": { "start_index": 312451, "end_index": 313209 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 94 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.7 Option bytes", 88 ], [ 3, "3.7.3 Read protection (RDP)", 93 ] ], "page_content": "Embedded flash memory interface\nRM0090\n94/1757\nRM0090 Rev 21\nNote:\nIf the read protection is set while the debugger is still connected (or has been connected \nsince the last power-on) through JTAG/SWD, apply a POR (power-on reset) instead of a \nsystem reset. \nIf the read protection is programmed by software (executing from SRAM), perform a POR to \nreload the option byte and clear the detected intrusion. This can be done with a transition \nStandby mode followed by a wake-up.\nThe JTAG port is permanently disabled when Level 2 is active (acting as a JTAG fuse). As a \nconsequence, boundary scan cannot be performed. STMicroelectronics is not able to \nperform analysis on defective parts on which the Level 2 protection has been set. \n" }, { "page_number": 95, "page_indices": { "start_index": 313209, "end_index": 314739 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 95 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.7 Option bytes", 88 ], [ 3, "3.7.4 Write protections", 95 ] ], "page_content": "RM0090 Rev 21\n95/1757\nRM0090\nEmbedded flash memory interface\n113\n --\nFigure 6 shows how to go from one RDP level to another.\nFigure 6. RDP levels\n3.7.4 \nWrite protections\nUp to 24 user sectors in flash memory can be protected against unwanted write operations \ndue to loss of program counter contexts. When the non-write protection nWRPi bit (0 ≤i ≤11) \nin the FLASH_OPTCR or FLASH_OPTCR1 registers is low, the corresponding sector \nTable 18. Access versus read protection level\nMemory area\nProtection \nLevel\nDebug features, Boot from RAM or \nfrom System memory bootloader \nBooting from flash memory\nRead \nWrite \nErase \nRead \nWrite \nErase \nMain Flash Memory \nand Backup SRAM\nLevel 1\nNO\nNO(1)\nYES\nLevel 2\nNO\nYES\nOption Bytes\nLevel 1\nYES\nYES\nLevel 2\nNO\nNO\nOTP\nLevel 1\nNO\nNA\nYES\nNA\nLevel 2\nNO\nNA\nYES\nNA\n1.\nThe main flash memory and backup SRAM are only erased when the RDP changes from level 1 to 0. The OTP area \nremains unchanged.\nLevel 1\nRDP /= AAh\nRDP /= CCh\ndefault\nOptions write (RDP level increase) includes\n- Options erase\n- New options program\nOptions write (RDP level decrease) includes\n- Mass erase\n- Options erase\n- New options program\nOptions write (RDP level identical) includes\n- Options erase\n- New options program\nRDP = AAh\nOthers option(s) modified\nRDP /= AAh & /= CCh\nOthers options modified\nWrite options\nincluding\nRDP = AAh\nWrite options\nincluding\nRDP = CCh\nWrite options\nincluding\nRDP = CCh\nWrite options including\nRDP /= CCh & /= AAh\nLevel 2\nRDP = CCh\nLevel 0 \nRDP = AAh\nMS47541V1\n" }, { "page_number": 96, "page_indices": { "start_index": 314739, "end_index": 317541 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 96 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.7 Option bytes", 88 ], [ 3, "3.7.4 Write protections", 95 ], [ 4, "Write protection error flag", 96 ], [ 3, "3.7.5 Proprietary code readout protection (PCROP)", 96 ] ], "page_content": "Embedded flash memory interface\nRM0090\n96/1757\nRM0090 Rev 21\ncannot be erased or programmed. Consequently, a mass erase cannot be performed if one \nof the sectors is write-protected.\nIf an erase/program operation to a write-protected part of the flash memory is attempted \n(sector protected by write protection bit, OTP part locked or part of the flash memory that \ncan never be written like the ICP), the write protection error flag (WRPERR) is set in the \nFLASH_SR register.\nOn STM32F42xxx and STM32F43xxx devices, when the PCROP mode is set, the active \nlevel of nWRPi is high, and the corresponding sector i is write protected when nWRPi is \nhigh. A PCROP sector is automatically write protected.\nNote:\nWhen the memory read protection level is selected (RDP level = 1), it is not possible to \nprogram or erase flash memory sector i if the CPU debug features are connected (JTAG or \nsingle wire) or boot code is being executed from RAM, even if nWRPi = 1.\nWrite protection error flag\nIf an erase/program operation to a write protected area of the flash memory is performed, \nthe Write Protection Error flag (WRPERR) is set in the FLASH_SR register.\nIf an erase operation is requested, the WRPERR bit is set when:\n•\nMass, bank, sector erase are configured (MER or MER/MER1 and SER = 1)\n•\nA sector erase is requested and the Sector Number SNB field is not valid\n•\nA mass erase is requested while at least one of the user sector is write protected by \noption bit (MER or MER/MER1 = 1 and nWRPi = 0 with 0 ≤ i ≤ 11 bits in the \nFLASH_OPTCRx register\n•\nA sector erase is requested on a write protected sector. (SER = 1, SNB = i and \nnWRPi = 0 with 0 ≤ i ≤ 11 bits in the FLASH_OPTCRx register) \n•\nThe flash memory is readout protected and an intrusion is detected.\nIf a program operation is requested, the WRPERR bit is set when:\n•\nA write operation is performed on system memory or on the reserved part of the user \nspecific sector. \n•\nA write operation is performed to the user configuration sector\n•\nA write operation is performed on a sector write protected by option bit.\n•\nA write operation is requested on an OTP area which is already locked\n•\nThe flash memory is read protected and an intrusion is detected.\n3.7.5 \nProprietary code readout protection (PCROP)\nThe proprietary readout protection (PCROP) is available only on STM32F42xxx and \nSTM32F43xxx devices. \nFlash memory user sectors (0 to 23) can be protected against D-bus read accesses by \nusing the proprietary readout protection (PCROP). \nThe PCROP protection is selected as follows, through the SPRMOD option bit in the \nFLASH_OPTCR register:\n•\nSPRMOD = 0: nWRPi control the write protection of respective user sectors\n•\nSPRMOD = 1: nWRPi control the read and write protection (PCROP) of respective \nuser sectors. \n" }, { "page_number": 97, "page_indices": { "start_index": 317541, "end_index": 319128 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 97 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.7 Option bytes", 88 ], [ 3, "3.7.5 Proprietary code readout protection (PCROP)", 96 ] ], "page_content": "RM0090 Rev 21\n97/1757\nRM0090\nEmbedded flash memory interface\n113\nWhen a sector is readout protected (PCROP mode activated), it can only be accessed for \ncode fetch through ICODE Bus on Flash interface:\n•\nAny read access performed through the D-bus triggers a RDERR flag error.\n•\nAny program/erase operation on a PCROPed sector triggers a WRPERR flag error.\nFigure 7. PCROP levels\nThe deactivation of the SPRMOD and/or the unprotection of PCROPed user sectors can \nonly occur when, at the same time, the RDP level changes from 1 to 0. If this condition is not \nrespected, the user option byte modification is cancelled and the write error WRPERR flag \nis set. The modification of the users option bytes (BOR_LEV, RST_STDBY, ..) is allowed \nsince none of the active nWRPi bits is reset and SPRMOD is kept active.\nNote:\nThe active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).\nIf SPRMOD = 1 and nWRPi =1, then user sector i of bank 1, respectively bank 2 is \nread/write protected (PCROP).\nLevel 1\nLevel 2\nRDP = 0xCC\nRDP /= 0xAA\nRDP /= 0xCC\ndefault\nUser option sector erase \nProgram new options\nGlobal mass erase \nUser option section erase\nProgram new options \nWrite options\nSPMOD = active\nand valid nWRPi*\nNo restriction on \nWrite options\nWrite options\nSPMOD = active\nand valid nWRPi* \nLevel 0\nRDP = 0xAA\nWrite options\nSPMOD = active\nand valid nWRPi* \nWrite options\nSPMOD = active\nand valid nWRPi*\nWrite options\nSPMOD = active\nand valid nWRPi*\n* Valid nWRPi means that none of the nWRP bits set can be reset (transition from 1 to 0)\nMS30467V1\n" }, { "page_number": 98, "page_indices": { "start_index": 319128, "end_index": 320245 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 98 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.8 One-time programmable bytes", 98 ] ], "page_content": "Embedded flash memory interface\nRM0090\n98/1757\nRM0090 Rev 21\n3.8 \nOne-time programmable bytes\nTable 19 shows the organization of the one-time programmable (OTP) part of the OTP area.\n \nThe OTP area is divided into 16 OTP data blocks of 32 bytes and one lock OTP block of 16 \nbytes. The OTP data and lock blocks cannot be erased. The lock block contains 16 bytes \nLOCKBi (0 ≤ i ≤ 15) to lock the corresponding OTP data block (blocks 0 to 15). Each OTP \ndata block can be programmed until the value 0x00 is programmed in the corresponding \nOTP lock byte. The lock bytes must only contain 0x00 and 0xFF values, otherwise the OTP \nbytes might not be taken into account correctly.\nTable 19. OTP area organization\nBlock\n[128:96]\n[95:64]\n[63:32]\n[31:0]\nAddress byte 0\n0\nOTP0\nOTP0\nOTP0\nOTP0\n0x1FFF 7800\nOTP0\nOTP0\nOTP0\nOTP0\n0x1FFF 7810\n1\nOTP1\nOTP1\nOTP1\nOTP1\n0x1FFF 7820\nOTP1\nOTP1\nOTP1\nOTP1\n0x1FFF 7830\n.\n.\n.\n.\n.\n.\n.\n.\n.\n15\nOTP15\nOTP15\nOTP15\nOTP15\n0x1FFF 79E0\nOTP15\nOTP15\nOTP15\nOTP15\n0x1FFF 79F0\nLock block\nLOCKB15 ... \nLOCKB12\nLOCKB11 ... \nLOCKB8\nLOCKB7 ... \nLOCKB4\nLOCKB3 ... \nLOCKB0\n0x1FFF 7A00\n" }, { "page_number": 99, "page_indices": { "start_index": 320245, "end_index": 321847 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 99 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.9 Flash interface registers", 99 ], [ 3, "3.9.1 Flash access control register (FLASH_ACR) for STM32F405xx/07xx and STM32F415xx/17xx", 99 ] ], "page_content": "RM0090 Rev 21\n99/1757\nRM0090\nEmbedded flash memory interface\n113\n3.9 \nFlash interface registers\n3.9.1 \nFlash access control register (FLASH_ACR) \nfor STM32F405xx/07xx and STM32F415xx/17xx\nThe Flash access control register is used to enable/disable the acceleration features and \ncontrol the flash memory access time according to CPU frequency.\nAddress offset: 0x00\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDCRST\nICRST\nDCEN\nICEN\nPRFTEN\nReserved\nLATENCY[2:0]\nrw\nw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:13 Reserved, must be kept cleared.\nBit 12 DCRST: Data cache reset\n0: Data cache is not reset\n1: Data cache is reset\nThis bit can be written only when the D cache is disabled.\nBit 11 ICRST: Instruction cache reset\n0: Instruction cache is not reset\n1: Instruction cache is reset\nThis bit can be written only when the I cache is disabled.\nBit 10 DCEN: Data cache enable\n0: Data cache is disabled\n1: Data cache is enabled\nBit 9 ICEN: Instruction cache enable\n0: Instruction cache is disabled\n1: Instruction cache is enabled\nBit 8 PRFTEN: Prefetch enable\n0: Prefetch is disabled\n1: Prefetch is enabled\nBits 7:3 Reserved, must be kept cleared.\nBits 2:0 LATENCY[2:0]: Latency\nThese bits represent the ratio of the CPU clock period to the flash memory access time.\n000: Zero wait state\n001: One wait state\n010: Two wait states\n011: Three wait states\n100: Four wait states\n101: Five wait states\n110: Six wait states\n111: Seven wait states\n" }, { "page_number": 100, "page_indices": { "start_index": 321847, "end_index": 323358 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 100 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.9 Flash interface registers", 99 ], [ 3, "3.9.2 Flash access control register (FLASH_ACR) for STM32F42xxx and STM32F43xxx", 100 ] ], "page_content": "Embedded flash memory interface\nRM0090\n100/1757\nRM0090 Rev 21\n3.9.2 \nFlash access control register (FLASH_ACR) \nfor STM32F42xxx and STM32F43xxx\nThe Flash access control register is used to enable/disable the acceleration features and \ncontrol the flash memory access time according to CPU frequency.\nAddress offset: 0x00\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDCRST\nICRST\nDCEN\nICEN\nPRFTEN\nReserved\nLATENCY[3:0]\nrw\nw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:13 Reserved, must be kept cleared.\nBit 12 DCRST: Data cache reset\n0: Data cache is not reset\n1: Data cache is reset\nThis bit can be written only when the D cache is disabled.\nBit 11 ICRST: Instruction cache reset\n0: Instruction cache is not reset\n1: Instruction cache is reset\nThis bit can be written only when the I cache is disabled.\nBit 10 DCEN: Data cache enable\n0: Data cache is disabled\n1: Data cache is enabled\nBit 9 ICEN: Instruction cache enable\n0: Instruction cache is disabled\n1: Instruction cache is enabled\nBit 8 PRFTEN: Prefetch enable\n0: Prefetch is disabled\n1: Prefetch is enabled\nBits 7:4 Reserved, must be kept cleared.\nBits 3:0 LATENCY[3:0]: Latency\nThese bits represent the ratio of the CPU clock period to the flash memory access time.\n0000: Zero wait state\n0001: One wait state\n0010: Two wait states\n...\n1110: Fourteen wait states\n1111: Fifteen wait states\n" }, { "page_number": 101, "page_indices": { "start_index": 323358, "end_index": 324729 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 101 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.9 Flash interface registers", 99 ], [ 3, "3.9.3 Flash key register (FLASH_KEYR)", 101 ], [ 3, "3.9.4 Flash option key register (FLASH_OPTKEYR)", 101 ] ], "page_content": "RM0090 Rev 21\n101/1757\nRM0090\nEmbedded flash memory interface\n113\n3.9.3 \nFlash key register (FLASH_KEYR)\nThe Flash key register is used to allow access to the Flash control register and so, to allow \nprogram and erase operations.\nAddress offset: 0x04\nReset value: 0x0000 0000\nAccess: no wait state, word access\n \n \n3.9.4 \nFlash option key register (FLASH_OPTKEYR)\nThe Flash option key register is used to allow program and erase operations in the user \nconfiguration sector.\nAddress offset: 0x08\nReset value: 0x0000 0000\nAccess: no wait state, word access\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nKEY[31:16]\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nKEY[15:0]\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBits 31:0 FKEYR[31:0]: FPEC key\nThe following values must be programmed consecutively to unlock the FLASH_CR register \nand allow programming/erasing it:\na) \nKEY1 = 0x45670123 \nb) \nKEY2 = 0xCDEF89AB \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nOPTKEYR[31:16\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOPTKEYR[15:0]\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBits 31:0 OPTKEYR[31:0]: Option byte key\nThe following values must be programmed consecutively to unlock the FLASH_OPTCR \nregister and allow programming it:\na) \nOPTKEY1 = 0x08192A3B \nb) \nOPTKEY2 = 0x4C5D6E7F \n" }, { "page_number": 102, "page_indices": { "start_index": 324729, "end_index": 326451 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 102 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.9 Flash interface registers", 99 ], [ 3, "3.9.5 Flash status register (FLASH_SR) for STM32F405xx/07xx and STM32F415xx/17xx", 102 ] ], "page_content": "Embedded flash memory interface\nRM0090\n102/1757\nRM0090 Rev 21\n3.9.5 \nFlash status register (FLASH_SR) for \nSTM32F405xx/07xx and STM32F415xx/17xx \nThe Flash status register gives information on ongoing program and erase operations.\nAddress offset: 0x0C\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nBSY\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPGSERR PGPERR PGAERR WRPERR\nReserved\nOPERR\nEOP\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nBits 31:17 Reserved, must be kept cleared.\nBit 16 BSY: Busy\nThis bit indicates that a flash memory operation is in progress. It is set at the beginning of a \nflash memory operation and cleared when the operation finishes or an error occurs.\n0: no flash memory operation ongoing\n1: Flash memory operation ongoing\nBits 15:8 Reserved, must be kept cleared.\nBit 7 PGSERR: Programming sequence error\nSet by hardware when a write access to the flash memory is performed by the code while the \ncontrol register has not been correctly configured.\nCleared by writing 1.\nBit 6 PGPERR: Programming parallelism error\nSet by hardware when the size of the access (byte, half-word, word, double word) during the \nprogram sequence does not correspond to the parallelism configuration PSIZE (x8, x16, x32, \nx64).\nCleared by writing 1.\nBit 5 PGAERR: Programming alignment error\nSet by hardware when the data to program cannot be contained in the same 128-bit flash \nmemory row.\nCleared by writing 1.\nBit 4 WRPERR: Write protection error\nSet by hardware when an address to be erased/programmed belongs to a write-protected part \nof the flash memory.\nCleared by writing 1.\n" }, { "page_number": 103, "page_indices": { "start_index": 326451, "end_index": 328375 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 103 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.9 Flash interface registers", 99 ], [ 3, "3.9.6 Flash status register (FLASH_SR) for STM32F42xxx and STM32F43xxx", 103 ] ], "page_content": "RM0090 Rev 21\n103/1757\nRM0090\nEmbedded flash memory interface\n113\n \n3.9.6 \nFlash status register (FLASH_SR) for \nSTM32F42xxx and STM32F43xxx\nThe Flash status register gives information on ongoing program and erase operations.\nAddress offset: 0x0C\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n \n \nBits 3:2 Reserved, must be kept cleared.\nBit 1 OPERR: Operation error\nSet by hardware when a flash operation (programming / erase /read) request is detected and \ncan not be run because of parallelism, alignment, or write protection error. This bit is set only if \nerror interrupts are enabled (ERRIE = 1).\nBit 0 EOP: End of operation\nSet by hardware when one or more flash memory operations (program/erase) has/have \ncompleted successfully. It is set only if the end of operation interrupts are enabled (EOPIE = 1).\nCleared by writing a 1.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nBSY\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRDERR PGSERR PGPERR PGAERR WRPERR\nReserved\nOPERR\nEOP\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nBits 31:17 Reserved, must be kept cleared.\nBit 16 BSY: Busy\nThis bit indicates that a flash memory operation is in progress to/from one bank. It is set at the \nbeginning of a flash memory operation and cleared when the operation finishes or an error \noccurs.\n0: no flash memory operation ongoing\n1: Flash memory operation ongoing\nBits 15:9 Reserved, must be kept cleared.\nBit 8 RDERR: Proprietary readout protection (PCROP) error\nSet by hardware when a read access through the D-bus is performed to an address belonging \nto a proprietary readout protected Flash sector. \nCleared by writing 1.\nBit 7 PGSERR: Programming sequence error\nSet by hardware when a write access to the flash memory is performed by the code while the \ncontrol register has not been correctly configured.\nCleared by writing 1.\n" }, { "page_number": 104, "page_indices": { "start_index": 328375, "end_index": 330143 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 104 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.9 Flash interface registers", 99 ], [ 3, "3.9.7 Flash control register (FLASH_CR) for STM32F405xx/07xx and STM32F415xx/17xx", 104 ] ], "page_content": "Embedded flash memory interface\nRM0090\n104/1757\nRM0090 Rev 21\n \n3.9.7 \nFlash control register (FLASH_CR) for \nSTM32F405xx/07xx and STM32F415xx/17xx\nThe Flash control register is used to configure and start flash memory operations.\nAddress offset: 0x10\nReset value: 0x8000 0000\nAccess: no wait state when no flash memory operation is ongoing, word, half-word and byte \naccess.\n \nBit 6 PGPERR: Programming parallelism error\nSet by hardware when the size of the access (byte, half-word, word, double word) during the \nprogram sequence does not correspond to the parallelism configuration PSIZE (x8, x16, x32, \nx64).\nCleared by writing 1.\nBit 5 PGAERR: Programming alignment error\nSet by hardware when the data to program cannot be contained in the same 128-bit flash \nmemory row.\nCleared by writing 1.\nBit 4 WRPERR: Write protection error\nSet by hardware when an address to be erased/programmed belongs to a write-protected part \nof the flash memory.\nCleared by writing 1.\nBits 3:2 Reserved, must be kept cleared.\nBit 1 OPERR: Operation error\nSet by hardware when a flash operation (programming/erase/read) request is detected and \ncan not be run because of parallelism, alignment, write or read (PCROP) protection error. This \nbit is set only if error interrupts are enabled (ERRIE = 1).\nBit 0 EOP: End of operation\nSet by hardware when one or more flash memory operations (program/erase) has/have \ncompleted successfully. It is set only if the end of operation interrupts are enabled (EOPIE = 1).\nCleared by writing a 1.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nLOCK\nReserved\nERRIE\nEOPIE\nReserved\nSTRT\nrs\nrw\nrw\nrs\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPSIZE[1:0]\nRes.\nSNB[3:0]\nMER\nSER\nPG\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 105, "page_indices": { "start_index": 330143, "end_index": 331665 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 105 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.9 Flash interface registers", 99 ], [ 3, "3.9.7 Flash control register (FLASH_CR) for STM32F405xx/07xx and STM32F415xx/17xx", 104 ] ], "page_content": "RM0090 Rev 21\n105/1757\nRM0090\nEmbedded flash memory interface\n113\n \nBit 31 LOCK: Lock\nWrite to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is \ncleared by hardware after detecting the unlock sequence.\nIn the event of an unsuccessful unlock operation, this bit remains set until the next reset.\nBits 30:26 Reserved, must be kept cleared.\nBit 25 ERRIE: Error interrupt enable\nThis bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is set \nto 1.\n0: Error interrupt generation disabled\n1: Error interrupt generation enabled\nBit 24 EOPIE: End of operation interrupt enable\nThis bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes to \n1.\n0: Interrupt generation disabled\n1: Interrupt generation enabled\nBits 23:17 Reserved, must be kept cleared.\nBit 16 STRT: Start\nThis bit triggers an erase operation when set. It is set only by software and cleared when the \nBSY bit is cleared.\nBits 15:10 Reserved, must be kept cleared.\nBits 9:8 PSIZE[1:0]: Program size\nThese bits select the program parallelism.\n00 program x8\n01 program x16\n10 program x32\n11 program x64\nBit 7 Reserved, must be kept cleared.\nBits 6:3 SNB[3:0]: Sector number\nThese bits select the sector to erase.\n0000 sector 0\n0001 sector 1\n...\n1011 sector 11\nOthers not allowed\nBit 2 MER: Mass Erase\nErase activated for all user sectors.\nBit 1 SER: Sector Erase\nSector Erase activated.\nBit 0 PG: Programming\nFlash programming activated.\n" }, { "page_number": 106, "page_indices": { "start_index": 331665, "end_index": 333468 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 106 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.9 Flash interface registers", 99 ], [ 3, "3.9.8 Flash control register (FLASH_CR) for STM32F42xxx and STM32F43xxx", 106 ] ], "page_content": "Embedded flash memory interface\nRM0090\n106/1757\nRM0090 Rev 21\n3.9.8 \nFlash control register (FLASH_CR) for \nSTM32F42xxx and STM32F43xxx\nThe Flash control register is used to configure and start flash memory operations.\nAddress offset: 0x10\nReset value: 0x8000 0000\nAccess: no wait state when no flash memory operation is ongoing, word, half-word and byte \naccess.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nLOCK\nReserved\nERRIE\nEOPIE\nReserved\nSTRT\nrs\nrw\nrw\nrs\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMER1\nReserved\nPSIZE[1:0]\nSNB[4:0]\nMER\nSER\nPG\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 LOCK: Lock\nWrite to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is \ncleared by hardware after detecting the unlock sequence.\nIn the event of an unsuccessful unlock operation, this bit remains set until the next reset.\nBits 30:26 Reserved, must be kept cleared.\nBit 25 ERRIE: Error interrupt enable\nThis bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is set \nto 1.\n0: Error interrupt generation disabled\n1: Error interrupt generation enabled\nBit 24 EOPIE: End of operation interrupt enable\nThis bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes to \n1.\n0: Interrupt generation disabled\n1: Interrupt generation enabled\nBits 23:17 Reserved, must be kept cleared.\nBit 16 STRT: Start\nThis bit triggers an erase operation when set. It is set only by software and cleared when the \nBSY bit is cleared.\nBit 15 MER1: Mass Erase of bank 2 sectors\nErase activated for bank 2 user sectors 12 to 23.\nBits 14:10 Reserved, must be kept cleared.\nBits 9:8 PSIZE[1:0]: Program size\nThese bits select the program parallelism.\n00 program x8\n01 program x16\n10 program x32\n11 program x64\n" }, { "page_number": 107, "page_indices": { "start_index": 333468, "end_index": 334717 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 107 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.9 Flash interface registers", 99 ], [ 3, "3.9.9 Flash option control register (FLASH_OPTCR) for STM32F405xx/07xx and STM32F415xx/17xx", 107 ] ], "page_content": "RM0090 Rev 21\n107/1757\nRM0090\nEmbedded flash memory interface\n113\n3.9.9 \nFlash option control register (FLASH_OPTCR) for \nSTM32F405xx/07xx and STM32F415xx/17xx\nThe FLASH_OPTCR register is used to modify the user option bytes.\nAddress offset: 0x14\nReset value: 0x0FFF AAED. The option bits are loaded with values from flash memory at \nreset release.\nAccess: no wait state when no flash memory operation is ongoing, word, half-word and byte \naccess.\n \nBits 7:3 SNB[3:0]: Sector number\nThese bits select the sector to erase.\n0000: sector 0\n0001: sector 1\n...\n01011: sector 11\n01100: not allowed\n01101: not allowed\n01110: not allowed\n01111: not allowed\n10000: section 12\n10001: section 13\n...\n11011 sector 23\n11100: not allowed \n11101: not allowed\n11110: not allowed\n11111: not allowed\nBit 2 MER: Mass Erase of bank 1 sectors\nErase activated of bank 1 sectors.\nBit 1 SER: Sector Erase\nSector Erase activated.\nBit 0 PG: Programming\nFlash programming activated.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nnWRP[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRDP[7:0]\nnRST_\nSTDBY\nnRST_\nSTOP\nWDG_\nSW\nReserve\nd\nBOR_LEV\nOPTST\nRT\nOPTLO\nCK\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrs\nrs\n" }, { "page_number": 108, "page_indices": { "start_index": 334717, "end_index": 336969 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 108 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.9 Flash interface registers", 99 ], [ 3, "3.9.9 Flash option control register (FLASH_OPTCR) for STM32F405xx/07xx and STM32F415xx/17xx", 107 ] ], "page_content": "Embedded flash memory interface\nRM0090\n108/1757\nRM0090 Rev 21\n \nBits 31:28 Reserved, must be kept cleared.\nBits 27:16 nWRP[11:0]: Not write protect\nThese bits contain the value of the write-protection option bytes after reset. They can be \nwritten to program a new write protect value into flash memory. \n0: Write protection active on selected sector\n1: Write protection inactive on selected sector\nBits 15:8 RDP[7:0]: Read protect\nThese bits contain the value of the read-protection option level after reset. They can be written \nto program a new read protection value into flash memory.\n0xAA: Level 0, read protection not active\n0xCC: Level 2, chip read protection active\nOthers: Level 1, read protection of memories active\nBits 7:5 USER[2:0]: User option bytes\nThese bits contain the value of the user option byte after reset. They can be written to program \na new user option byte value into flash memory.\nBit 7: nRST_STDBY\nBit 6: nRST_STOP\nBit 5: WDG_SW\nNote: When changing the WDG mode from hardware to software or from software to \nhardware, a system reset is required to make the change effective.\nBit 4 Reserved, must be kept cleared. Always read as “0”.\nBits 3:2 BOR_LEV[1:0]: BOR reset Level\nThese bits contain the supply level threshold that activates/releases the reset. They can be \nwritten to program a new BOR level. By default, BOR is off. When the supply voltage (VDD) \ndrops below the selected BOR level, a device reset is generated.\n00: BOR Level 3 (VBOR3), brownout threshold level 3\n01: BOR Level 2 (VBOR2), brownout threshold level 2\n10: BOR Level 1 (VBOR1), brownout threshold level 1\n11: BOR off, POR/PDR reset threshold level is applied\nNote: For full details about BOR characteristics, refer to the “Electrical characteristics” section \nin the device datasheet.\nBit 1 OPTSTRT: Option start\nThis bit triggers a user option operation when set. It is set only by software and cleared when \nthe BSY bit is cleared.\nBit 0 OPTLOCK: Option lock\nWrite to 1 only. When this bit is set, it indicates that the FLASH_OPTCR register is locked. This \nbit is cleared by hardware after detecting the unlock sequence.\nIn the event of an unsuccessful unlock operation, this bit remains set until the next reset.\n" }, { "page_number": 109, "page_indices": { "start_index": 336969, "end_index": 339533 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 109 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.9 Flash interface registers", 99 ], [ 3, "3.9.10 Flash option control register (FLASH_OPTCR) for STM32F42xxx and STM32F43xxx", 109 ] ], "page_content": "RM0090 Rev 21\n109/1757\nRM0090\nEmbedded flash memory interface\n113\n3.9.10 \nFlash option control register (FLASH_OPTCR) \nfor STM32F42xxx and STM32F43xxx\nThe FLASH_OPTCR register is used to modify the user option bytes.\nAddress offset: 0x14\nReset value: 0x0FFF AAED. The option bits are loaded with values from flash memory at \nreset release.\nAccess: no wait state when no flash memory operation is ongoing, word, half-word and byte \naccess.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nSPR\nMOD\nDB1M\nReserved\nnWRP[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRDP[7:0]\nnRST_\nSTDBY\nnRST_\nSTOP\nWDG_\nSW\nBFB2\nBOR_LEV\nOPTST\nRT\nOPTLO\nCK\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrs\nrs\nBit 31 SPRMOD: Selection of protection mode for nWPRi bits\n0: PCROP disabled. nWPRi bits used for Write protection on sector i.\n1: PCROP enabled. nWPRi bits used for PCROP protection on sector i\nBit 30 DB1M: Dual-bank on 1 Mbyte flash memory devices \n0: 1 Mbyte single bank flash memory (contiguous addresses in bank1)\n1: 1 Mbyte dual bank flash memory. The flash memory is organized as two banks of \n512 Kbytes each (see Table 7: 1 Mbyte flash memory single bank vs dual bank organization \n(STM32F42xxx and STM32F43xxx) and Table 9: 1 Mbyte dual bank flash memory \norganization (STM32F42xxx and STM32F43xxx)). To perform an erase operation, the right \nsector must be programmed (see Table 7 for information on the sector numbering scheme). \nNote: If DB1M is set and an erase operation is performed on Bank 2 while the default sector \nnumber is selected (as an example, sector 8 is configured instead of sector 12), the \nerase operation on Bank 2 sector is not performed. \nBits 29:28 Reserved, must be kept cleared.\nBits 27:16 nWRP[11:0]: Not write protect\nThese bits contain the value of the write-protection and read-protection (PCROP) option bytes \nfor sectors 0 to 11 after reset. They can be written to program a new write-protect or PCROP \nvalue into flash memory.\nIf SPRMOD is reset:\n0: Write protection active on sector i\n1: Write protection not active on sector i\nIf SPRMOD is set:\n0: PCROP protection not active on sector i\n1: PCROP protection active on sector i\nBits 15:8 RDP[7:0]: Read protect\nThese bits contain the value of the read-protection option level after reset. They can be written \nto program a new read protection value into flash memory.\n0xAA: Level 0, read protection not active\n0xCC: Level 2, chip read protection active\nOthers: Level 1, read protection of memories active\n" }, { "page_number": 110, "page_indices": { "start_index": 339533, "end_index": 341402 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 110 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.9 Flash interface registers", 99 ], [ 3, "3.9.10 Flash option control register (FLASH_OPTCR) for STM32F42xxx and STM32F43xxx", 109 ] ], "page_content": "Embedded flash memory interface\nRM0090\n110/1757\nRM0090 Rev 21\nBits 7:5 USER: User option bytes\nThese bits contain the value of the user option byte after reset. They can be written to program \na new user option byte value into flash memory.\nBit 7: nRST_STDBY\nBit 6: nRST_STOP\nBit 5: WDG_SW\nNote: When changing the WDG mode from hardware to software or from software to \nhardware, a system reset is required to make the change effective.\nBit 4 BFB2: Dual-bank Boot option byte\n0: Dual-bank boot disabled. Boot can be performed either from flash memory bank 1 or from \nsystem memory depending on boot pin state (default)\n1: Dual-bank boot enabled. Boot is always performed from system memory.\nNote: For STM32F42xx and STM32F43xx 1MB part numbers, this option bit must be kept \ncleared when DB1M=0. \nBits 3:2 BOR_LEV: BOR reset Level\nThese bits contain the supply level threshold that activates/releases the reset. They can be \nwritten to program a new BOR level. By default, BOR is off. When the supply voltage (VDD) \ndrops below the selected BOR level, a device reset is generated.\n00: BOR Level 3 (VBOR3), brownout threshold level 3\n01: BOR Level 2 (VBOR2), brownout threshold level 2\n10: BOR Level 1 (VBOR1), brownout threshold level 1\n11: BOR off, POR/PDR reset threshold level is applied\nNote: For full details on BOR characteristics, refer to the “Electrical characteristics” section of \nthe product datasheet.\nBit 1 OPTSTRT: Option start\nThis bit triggers a user option operation when set. It is set only by software and cleared when \nthe BSY bit is cleared.\nBit 0 OPTLOCK: Option lock\nWrite to 1 only. When this bit is set, it indicates that the FLASH_OPTCR register is locked. This \nbit is cleared by hardware after detecting the unlock sequence.\nIn the event of an unsuccessful unlock operation, this bit remains set until the next reset.\n" }, { "page_number": 111, "page_indices": { "start_index": 341402, "end_index": 342679 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 111 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.9 Flash interface registers", 99 ], [ 3, "3.9.11 Flash option control register (FLASH_OPTCR1) for STM32F42xxx and STM32F43xxx", 111 ] ], "page_content": "RM0090 Rev 21\n111/1757\nRM0090\nEmbedded flash memory interface\n113\n3.9.11 \nFlash option control register (FLASH_OPTCR1) \nfor STM32F42xxx and STM32F43xxx \nThis register is available only on STM32F42xxx and STM32F43xxx.\nThe FLASH_OPTCR1 register is used to modify the user option bytes for bank 2.\nAddress offset: 0x18\nReset value: 0x0FFF 0000. The option bits are loaded with values from flash memory at \nreset release.\nAccess: no wait state when no flash memory operation is ongoing, word, half-word and byte \naccess.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nnWRP[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBits 31:28 Reserved, must be kept cleared.\nBits 27:16 nWRP[11:0]: Not write protect\nThese bits contain the value of the write-protection and read-protection (PCROP) option bytes \nfor sectors 0 to 11 after reset. They can be written to program a new write-protect or PCROP \nvalue into flash memory.\nIf SPRMOD is reset (default value):\n0: Write protection active on sector i. \n1: Write protection not active on sector i. \nIf SPRMOD is set:\n0: PCROP protection not active on sector i. \n1: PCROP protection active on sector i.\nBits 15:0 Reserved, must be kept cleared.\n" }, { "page_number": 112, "page_indices": { "start_index": 342679, "end_index": 344398 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 112 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.9 Flash interface registers", 99 ], [ 3, "3.9.12 Flash interface register map", 112 ] ], "page_content": "Embedded flash memory interface\nRM0090\n112/1757\nRM0090 Rev 21\n3.9.12 \nFlash interface register map\n \nTable 20. Flash register map and reset values\n(STM32F405xx/07xx and STM32F415xx/17xx)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nFLASH_ACR\nReserved\nDCRST\nICRST\nDCEN\nICEN\nPRFTEN\nReserved\nLATENCY\n[2:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nFLASH_\nKEYR\nKEY[31:16]\nKEY[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nFLASH_OPT\nKEYR\nOPTKEYR[31:16]\nOPTKEYR[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nFLASH_SR\nReserved\nBSY\nReserved\nPGSERR\nPGPERR\nPGAERR\nWRPERR\nReserved\nOPERR\nEOP\nReset value\n0\n0\n0\n0\n0\n0\n0\n0x10\nFLASH_CR\nLOCK\nReserved\nEOPIE\nReserved\nSTRT\nReserved\nPSIZE[1:0]\nReserved\nSNB[3:0]\nMER\nSER\nPG\nReset value\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nFLASH_\nOPTCR\nReserved\nnWRP[11:0]\nRDP[7:0]\nnRST_STDBY\nnRST_STOP\nWDG_SW\nReserved\nBOR_LEV[1:0]\nOPTSTRT\nOPTLOCK\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0\n1\n0\n1\n0\n1\n0\n1\n1\n1\n1\n1\n0\n1\nTable 21. Flash register map and reset values (STM32F42xxx and STM32F43xxx)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nFLASH_ACR\nReserved\nDCRST\nICRST\nDCEN\nICEN\nPRFTEN\nReserved\nLATENCY[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nFLASH_KEYR\nKEY[31:16]\nKEY[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nFLASH_\nOPTKEYR\nOPTKEYR[31:16]\nOPTKEYR[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nFLASH_SR\nReserved\nBSY\nReserved\nRDERR\nPGSERR\nPGPERR\nPGAERR\nWRPERR\nReserved\nOPERR\nEOP\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n" }, { "page_number": 113, "page_indices": { "start_index": 344398, "end_index": 345085 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 113 }, "toc_details": [ [ 1, "3 Embedded flash memory interface", 73 ], [ 2, "3.9 Flash interface registers", 99 ], [ 3, "3.9.12 Flash interface register map", 112 ] ], "page_content": "RM0090 Rev 21\n113/1757\nRM0090\nEmbedded flash memory interface\n113\n0x10\nFLASH_CR\nLOCK\nReserved\nEOPIE\nReserved\nSTRT\nMER1\nReserved\nPSIZE[1:0]\nSNB[4:0]\nMER\nSER\nPG\nReset value\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nFLASH_OPTCR\nSPRMOD\nDB1M\nReserved\nnWRP[11:0]\nRDP[7:0]\nnRST_STDBY\nnRST_STOP\nWDG_SW\nBFB2\nBOR_LEV[1:0]\nOPTSTRT\nOPTLOCK\nReset value\n0\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0\n1\n0\n1\n0\n1\n0\n1\n1\n1\n0\n1\n1\n0\n1\n0x18\nFLASH_\nOPTCR1\nReserved\nnWRP[11:0]\nReserved\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\nTable 21. Flash register map and reset values (STM32F42xxx and STM32F43xxx) (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 114, "page_indices": { "start_index": 345085, "end_index": 346364 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 114 }, "toc_details": [ [ 1, "4 CRC calculation unit", 114 ], [ 2, "4.1 CRC introduction", 114 ], [ 2, "4.2 CRC main features", 114 ] ], "page_content": "CRC calculation unit\nRM0090\n114/1757\nRM0090 Rev 21\n4 \nCRC calculation unit\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n4.1 \nCRC introduction\nThe CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit \ndata word and a fixed generator polynomial.\nAmong other applications, CRC-based techniques are used to verify data transmission or \nstorage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of \nverifying the flash memory integrity. The CRC calculation unit helps compute a signature of \nthe software during runtime, to be compared with a reference signature generated at link-\ntime and stored at a given memory location.\n4.2 \nCRC main features\n•\nUses CRC-32 (Ethernet) polynomial: 0x4C11DB7\n–\nX32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X + 1\n•\nSingle input/output 32-bit data register\n•\nCRC computation done in 4 AHB clock cycles (HCLK)\n•\nGeneral-purpose 8-bit register (can be used for temporary storage)\nThe block diagram is shown in Figure 8.\nFigure 8. CRC calculation unit block diagram\nAHB bus\n32-bit (read access)\nData register (output)\nCRC computation (polynomial: 0x4C11DB7)\n32-bit (write access)\nData register (input)\nai14968\n" }, { "page_number": 115, "page_indices": { "start_index": 346364, "end_index": 348094 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 115 }, "toc_details": [ [ 1, "4 CRC calculation unit", 114 ], [ 2, "4.3 CRC functional description", 115 ], [ 2, "4.4 CRC registers", 115 ], [ 3, "4.4.1 Data register (CRC_DR)", 115 ], [ 3, "4.4.2 Independent data register (CRC_IDR)", 115 ] ], "page_content": "RM0090 Rev 21\n115/1757\nRM0090\nCRC calculation unit\n116\n4.3 \nCRC functional description\nThe CRC calculation unit mainly consists of a single 32-bit data register, which:\n•\nis used as an input register to enter new data in the CRC calculator (when writing into \nthe register)\n•\nholds the result of the previous CRC calculation (when reading the register)\nEach write operation into the data register creates a combination of the previous CRC value \nand the new one (CRC computation is done on the whole 32-bit data word, and not byte per \nbyte).\nThe write operation is stalled until the end of the CRC computation, thus allowing back-to-\nback write accesses or consecutive write and read accesses.\nThe CRC calculator can be reset to 0xFFFF FFFF with the RESET control bit in the \nCRC_CR register. This operation does not affect the contents of the CRC_IDR register.\n4.4 \nCRC registers\nThe CRC calculation unit contains two data registers and a control register.The peripheral \nThe CRC registers have to be accessed by words (32 bits).\n4.4.1 \nData register (CRC_DR)\nAddress offset: 0x00\nReset value: 0xFFFF FFFF\n \n4.4.2 \nIndependent data register (CRC_IDR)\nAddress offset: 0x04\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDR [31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDR [15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 Data register bits\nUsed as an input register when writing new data into the CRC calculator.\nHolds the previous CRC calculation result when it is read.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nIDR[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 116, "page_indices": { "start_index": 348094, "end_index": 349210 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 116 }, "toc_details": [ [ 1, "4 CRC calculation unit", 114 ], [ 2, "4.4 CRC registers", 115 ], [ 3, "4.4.3 Control register (CRC_CR)", 116 ], [ 3, "4.4.4 CRC register map", 116 ] ], "page_content": "CRC calculation unit\nRM0090\n116/1757\nRM0090 Rev 21\n \n4.4.3 \nControl register (CRC_CR)\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n4.4.4 \nCRC register map\nThe following table provides the CRC register map and reset values. \n \nBits 31:8 Reserved, must be kept at reset value.\nBits 7:0 General-purpose 8-bit data register bits\nCan be used as a temporary storage location for one byte.\nThis register is not affected by CRC resets generated by the RESET bit in the CRC_CR \nregister.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRESET\nw\nBits 31:1 Reserved, must be kept at reset value.\nBit 0 RESET bit\nResets the CRC calculation unit and sets the data register to 0xFFFF FFFF.\nThis bit can only be set, it is automatically cleared by hardware.\nTable 22. CRC calculation unit register map and reset values\nOffset\nRegister\n31-24\n23-16\n15-8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nCRC_DR\nData register\nReset \nvalue\n0xFFFF FFFF\n0x04\nCRC_IDR\nReserved\nIndependent data register\nReset \nvalue\n0x00\n0x08\nCRC_CR\nReserved\nRESET\nReset \nvalue\n0\n" }, { "page_number": 117, "page_indices": { "start_index": 349210, "end_index": 350529 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 117 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.1 Power supplies", 117 ] ], "page_content": "RM0090 Rev 21\n117/1757\nRM0090\nPower controller (PWR)\n151\n5 \nPower controller (PWR)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n5.1 \nPower supplies\nThe device requires a 1.8 to 3.6 V operating voltage supply (VDD). An embedded linear \nvoltage regulator is used to supply the internal 1.2 V digital power.\nThe real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM) \ncan be powered from the VBAT voltage when the main VDD supply is powered off. \nNote:\nDepending on the operating power supply range, some peripheral may be used with limited \nfunctionality and performance. For more details refer to section “General operating \nconditions” in STM32F4xx datasheets.\nFigure 9. Power supply overview for STM32F405xx/07xx and STM32F415xx/17xx\n1.\nVDDA and VSSA must be connected to VDD and VSS, respectively. \nMS19911V2\nBackup circuitry\n(OSC32K,RTC,\nWakeup logic\nBackup registers,\nbackup RAM)\nKernel logic \n(CPU, digital \n& RAM) \nAnalog:\nRCs, \nPLL,..\nPower \nswitch\nVBAT\nGPIOs\nOUT\nIN\n15 × 100 nF\n+ 1 × 4.7 μF\nVBAT =\n1.65 to 3.6V\nVoltage \nregulator\nVDDA\nADC\nLevel shifter\nIO\nLogic\nVDD\n100 nF\n+ 1 μF\nFlash memory\nVCAP_1\nVCAP_2\n2 × 2.2 μF\nBYPASS_REG\nPDR_ON\nReset \ncontroller\nVDD\n1/2/...14/15\nVSS\n1/2/...14/15\nVDD\nVREF+\nVREF-\nVSSA\nVREF\n100 nF\n+ 1 μF\n" }, { "page_number": 118, "page_indices": { "start_index": 350529, "end_index": 351692 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 118 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.1 Power supplies", 117 ], [ 3, "5.1.1 Independent A/D converter supply and reference voltage", 118 ] ], "page_content": "Power controller (PWR)\nRM0090\n118/1757\nRM0090 Rev 21\nFigure 10. Power supply overview for STM32F42xxx and STM32F43xxx\n1.\nVDDA and VSSA must be connected to VDD and VSS, respectively. \n5.1.1 \nIndependent A/D converter supply and reference voltage\nTo improve conversion accuracy, the ADC has an independent power supply which can be \nseparately filtered and shielded from noise on the PCB.\n•\nThe ADC voltage supply input is available on a separate VDDA pin. \n•\nAn isolated supply ground connection is provided on VSSA pin. \nTo ensure a better accuracy of low voltage inputs, the user can connect a separate external \nreference voltage ADC input on VREF. The voltage on VREF ranges from 1.8 V to VDDA.\nMS30482V2\nVDD\n1/2/...14/20\nAnalog: \nRCs, PLL,\n...\nPower switch\nVBAT\nGP I/Os\nOUT\nIN\nKernel logic \n(CPU, \ndigital \n& RAM) \nBackup circuitry\n(OSC32K,RTC,\nBackup registers,\nbackup RAM)\nWakeup logic\n19 × 100 nF\n+ 1 × 4.7 μF\nVBAT =\n 1.65 to 3.6V\n \nVoltage\nregulator\nVSS \n1/2/...14/20\nVDDA\nVREF+\nVREF-\nVSSA\nADC\nLevel shifter\nIO\nLogic\nVDD\n+ 1 μF\nVREF\n100 nF\n+ 1 μF\nVDD\nFlash memory\nVCAP_1\nVCAP_2\n2 × 2.2 μF\nBYPASS_REG\nPDR_ON\nReset \ncontroller\n100 nF\n" }, { "page_number": 119, "page_indices": { "start_index": 351692, "end_index": 353802 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 119 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.1 Power supplies", 117 ], [ 3, "5.1.2 Battery backup domain", 119 ], [ 4, "Backup domain description", 119 ] ], "page_content": "RM0090 Rev 21\n119/1757\nRM0090\nPower controller (PWR)\n151\n5.1.2 \nBattery backup domain\nBackup domain description\nTo retain the content of the RTC backup registers, backup SRAM, and supply the RTC when \nVDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a \nbattery or by another source.\nTo allow the RTC to operate even when the main digital supply (VDD) is turned off, the VBAT \npin powers the following blocks:\n•\nThe RTC\n•\nThe LSE oscillator\n•\nThe backup SRAM when the low-power backup regulator is enabled\n•\nPC13 to PC15 I/Os, plus PI8 I/O (when available) \nThe switch to the VBAT supply is controlled by the power-down reset embedded in the Reset \nblock.\nWarning:\nDuring tRSTTEMPO (temporization at VDD startup) or after a PDR \nis detected, the power switch between VBAT and VDD remains \nconnected to VBAT.\nDuring the startup phase, if VDD is established in less than \ntRSTTEMPO (Refer to the datasheet for the value of tRSTTEMPO) \nand VDD > VBAT + 0.6 V, a current may be injected into VBAT \nthrough an internal diode connected between VDD and the \npower switch (VBAT).\nIf the power supply/battery connected to the VBAT pin cannot \nsupport this current injection, it is strongly recommended to \nconnect an external low-drop diode between this power \nsupply and the VBAT pin.\nIf no external battery is used in the application, it is recommended to connect the VBAT pin \nto VDD supply, and add a 100 nF external decoupling ceramic capacitor on VBAT pin.\nWhen the backup domain is supplied by VDD (analog switch connected to VDD), the \nfollowing functions are available:\n•\nPC14 and PC15 can be used as either GPIO or LSE pins\n•\nPC13 can be used as a GPIOas the RTC_AF1 pin (refer to Table 38: RTC_AF1 pin for \nmore details about this pin configuration)\nNote:\nDue to the fact that the switch only sinks a limited amount of current (3 mA), the use of PI8 \nand PC13 to PC15 GPIOs in output mode is restricted: the speed has to be limited to 2 MHz \nwith a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to \ndrive an LED).\n" }, { "page_number": 120, "page_indices": { "start_index": 353802, "end_index": 356764 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 120 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.1 Power supplies", 117 ], [ 3, "5.1.2 Battery backup domain", 119 ], [ 4, "Backup domain access", 120 ], [ 4, "RTC and RTC backup registers", 120 ], [ 4, "Backup SRAM", 120 ] ], "page_content": "Power controller (PWR)\nRM0090\n120/1757\nRM0090 Rev 21\nWhen the backup domain is supplied by VBAT (analog switch connected to VBAT because \nVDD is not present), the following functions are available:\n•\nPC14 and PC15 can be used as LSE pins only\n•\nPC13 can be used as the RTC_AF1 pin (refer to Table 38: RTC_AF1 pin for more \ndetails about this pin configuration)\n•\nPI8 can be used as RTC_AF2\nBackup domain access\nAfter reset, the backup domain (RTC registers, RTC backup register and backup SRAM) is \nprotected against possible unwanted write accesses. To enable access to the backup \ndomain, proceed as follows:\n•\nAccess to the RTC and RTC backup registers\n1.\nEnable the power interface clock by setting the PWREN bits in the RCC_APB1ENR \nregister (see Section 7.3.13 and Section 6.3.13)\n2. \nSet the DBP bit in the Section 5.4.1 and PWR power control register (PWR_CR) for \nSTM32F42xxx and STM32F43xxx to enable access to the backup domain\n3. \nSelect the RTC clock source: see Section 7.2.8: RTC/AWU clock\n4. \nEnable the RTC clock by programming the RTCEN [15] bit in the Section 7.3.20: RCC \nBackup domain control register (RCC_BDCR)\n•\nAccess to the backup SRAM\n1.\nEnable the power interface clock by setting the PWREN bits in the RCC_APB1ENR \nregister (see Section 7.3.13 and Section 6.3.13 for STM32F405xx/07xx and \nSTM32F415xx/17xx and STM32F42xxx and STM32F43xxx, respectively)\n2. \nSet the DBP bit in the PWR power control register (PWR_CR) for STM32F405xx/07xx \nand STM32F415xx/17xx and PWR power control register (PWR_CR) for \nSTM32F42xxx and STM32F43xxx to enable access to the backup domain\n3. \nEnable the backup SRAM clock by setting BKPSRAMEN bit in the RCC AHB1 \nperipheral clock enable register (RCC_AHB1ENR).\nRTC and RTC backup registers\nThe real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-\nof-day clock/calendar, two programmable alarm interrupts, and a periodic programmable \nwake-up flag with interrupt capability. The RTC contains 20 backup data registers (80 bytes) \nwhich are reset when a tamper detection event occurs. For more details refer to Section 26: \nReal-time clock (RTC).\nBackup SRAM\nThe backup domain includes 4 Kbytes of backup SRAM addressed in 32-bit, 16-bit or 8-bit \nmode. Its content is retained even in Standby or VBAT mode when the low-power backup \nregulator is enabled. It can be considered as an internal EEPROM when VBAT is always \npresent.\nWhen the backup domain is supplied by VDD (analog switch connected to VDD), the backup \nSRAM is powered from VDD which replaces the VBAT power supply to save battery life.\nWhen the backup domain is supplied by VBAT (analog switch connected to VBAT because \nVDD is not present), the backup SRAM is powered by a dedicated low-power regulator. This \nregulator can be ON or OFF depending whether the application needs the backup SRAM \nfunction in Standby and VBAT modes or not. The power-down of this regulator is controlled \n" }, { "page_number": 121, "page_indices": { "start_index": 356764, "end_index": 358850 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 121 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.1 Power supplies", 117 ], [ 3, "5.1.3 Voltage regulator for STM32F405xx/07xx and STM32F415xx/17xx", 121 ] ], "page_content": "RM0090 Rev 21\n121/1757\nRM0090\nPower controller (PWR)\n151\nby a dedicated bit, the BRE control bit of the PWR_CSR register (see Section 5.4.2: PWR \npower control/status register (PWR_CSR) for STM32F405xx/07xx and \nSTM32F415xx/17xx). \nThe backup SRAM is not mass erased by an tamper event. When the Flash memory is read \nprotected, the backup SRAM is also read protected to prevent confidential data, such as \ncryptographic private key, from being accessed. When the protection level change from \nlevel 1 to level 0 is requested, the backup SRAM content is erased.\nFigure 11. Backup domain\n5.1.3 \nVoltage regulator for STM32F405xx/07xx and STM32F415xx/17xx\nAn embedded linear voltage regulator supplies all the digital circuitries except for the backup \ndomain and the Standby circuitry. The regulator output voltage is around 1.2 V.\nThis voltage regulator requires one or two external capacitors to be connected to one or two \ndedicated pins, VCAP_1 and VCAP_2 available in all packages. Specific pins must be \nconnected either to VSS or VDD to activate or deactivate the voltage regulator. These pins \ndepend on the package.\nWhen activated by software, the voltage regulator is always enabled after Reset. It works in \nthree different modes depending on the application modes.\n•\nIn Run mode, the regulator supplies full power to the 1.2 V domain (core, memories \nand digital peripherals). In this mode, the regulator output voltage (around 1.2 V) can \nbe scaled by software to different voltage values:\nScale 1 or scale 2 can be configured on the fly through VOS (bit 15 of the \nPWR_CR register). \nThe voltage scaling allows optimizing the power consumption when the device is \nclocked below the maximum system frequency. \n•\nIn Stop mode, the main regulator or the low-power regulator supplies to the 1.2 V \ndomain, thus preserving the content of registers and internal SRAM. The voltage \nMS30430V1\nVoltage regulator\n3.3 -> 1.2 V\n1.2 V domain\nBackup SRAM\ninterface\nPower switch\nLP voltage regulator\n3.3 -> 1.2 V\nBackup SRAM\n1.2 V\nRTC\nLSE 32.768 Hz\nBackup domain\n" }, { "page_number": 122, "page_indices": { "start_index": 358850, "end_index": 360950 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 122 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.1 Power supplies", 117 ], [ 3, "5.1.4 Voltage regulator for STM32F42xxx and STM32F43xxx", 122 ] ], "page_content": "Power controller (PWR)\nRM0090\n122/1757\nRM0090 Rev 21\nregulator can be put either in main regulator mode (MR) or in low-power mode (LPR). \nThe programmed voltage scale remains the same during Stop mode:\nThe programmed voltage scale remains the same during Stop mode (see \nSection 5.4.1: PWR power control register (PWR_CR) for STM32F405xx/07xx \nand STM32F415xx/17xx).\n•\nIn Standby mode, the regulator is powered down. The content of the registers and \nSRAM are lost except for the Standby circuitry and the backup domain.\nNote:\nFor more details, refer to the voltage regulator section in the STM32F405xx/07xx and \nSTM32F415xx/17xx datasheets. \n5.1.4 \nVoltage regulator for STM32F42xxx and STM32F43xxx\nAn embedded linear voltage regulator supplies all the digital circuitries except for the backup \ndomain and the Standby circuitry. The regulator output voltage is around 1.2 V.\nThis voltage regulator requires two external capacitors to be connected to two dedicated \npins, VCAP_1 and VCAP_2 available in all packages. Specific pins must be connected \neither to VSS or VDD to activate or deactivate the voltage regulator. These pins depend on \nthe package.\nWhen activated by software, the voltage regulator is always enabled after Reset. It works in \nthree different modes depending on the application modes (Run, Stop, or Standby mode).\n•\nIn Run mode, the main regulator supplies full power to the 1.2 V domain (core, \nmemories and digital peripherals). In this mode, the regulator output voltage (around \n1.2 V) can be scaled by software to different voltage values (scale 1, scale 2, and scale \n3 can be configured through VOS[1:0] bits of the PWR_CR register). The scale can be \nmodified only when the PLL is OFF and the HSI or HSE clock source is selected as \nsystem clock source. The new value programmed is active only when the PLL is ON. \nWhen the PLL is OFF, the voltage scale 3 is automatically selected.\nThe voltage scaling allows optimizing the power consumption when the device is \nclocked below the maximum system frequency. After exit from Stop mode, the voltage \n" }, { "page_number": 123, "page_indices": { "start_index": 360950, "end_index": 362914 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 123 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.1 Power supplies", 117 ], [ 3, "5.1.4 Voltage regulator for STM32F42xxx and STM32F43xxx", 122 ] ], "page_content": "RM0090 Rev 21\n123/1757\nRM0090\nPower controller (PWR)\n151\nscale 3 is automatically selected.(see Section 5.4.1: PWR power control register \n(PWR_CR) for STM32F405xx/07xx and STM32F415xx/17xx.\n2 operating modes are available:\n–\nNormal mode: The CPU and core logic operate at maximum frequency at a given \nvoltage scaling (scale 1, scale 2 or scale 3)\n–\nOver-drive mode: This mode allows the CPU and the core logic to operate at a \nhigher frequency than the normal mode for the voltage scaling scale 1 and scale \n2.\n•\nIn Stop mode: the main regulator or low-power regulator supplies a low-power voltage \nto the 1.2V domain, thus preserving the content of registers and internal SRAM.\nThe voltage regulator can be put either in main regulator mode (MR) or in low-power \nmode (LPR). Both modes can be configured by software as follows:\n–\nNormal mode: the 1.2 V domain is preserved in nominal leakage mode. It is the \ndefault mode when the main regulator (MR) or the low-power regulator (LPR) is \nenabled.\n–\nUnder-drive mode: the 1.2 V domain is preserved in reduced leakage mode. This \nmode is only available with the main regulator or in low-power regulator mode \n(see Table 23). \n•\nIn Standby mode: the regulator is powered down. The content of the registers and \nSRAM are lost except for the Standby circuitry and the backup domain.\nNote:\nOver-drive and under-drive mode are not available when the regulator is bypassed.\nFor more details, refer to the voltage regulator section in the STM32F42xxx and \nSTM32F43xxx datasheets.\n Table 23. Voltage regulator configuration mode versus device operating mode(1)\n1.\n‘-’ means that the corresponding configuration is not available. \nVoltage regulator \nconfiguration\nRun mode\nSleep mode\nStop mode\nStandby mode\nNormal mode\nMR\nMR\nMR or LPR\n-\nOver-drive \nmode(2)\n2.\nThe over-drive mode is not available when VDD = 1.8 to 2.1 V.\nMR\nMR\n-\n-\nUnder-drive mode\n-\n-\nMR or LPR\n-\nPower-down \nmode\n-\n-\n-\nYes\n" }, { "page_number": 124, "page_indices": { "start_index": 362914, "end_index": 365434 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 124 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.1 Power supplies", 117 ], [ 3, "5.1.4 Voltage regulator for STM32F42xxx and STM32F43xxx", 122 ], [ 4, "Entering Over-drive mode", 124 ], [ 4, "Exiting from Over-drive mode", 124 ] ], "page_content": "Power controller (PWR)\nRM0090\n124/1757\nRM0090 Rev 21\nEntering Over-drive mode\nIt is recommended to enter Over-drive mode when the application is not running critical \ntasks and when the system clock source is either HSI or HSE. To optimize the configuration \ntime, enable the Over-drive mode during the PLL lock phase. \nTo enter Over-drive mode, follow the sequence below:\n1.\nSelect HSI or HSE as system clock.\n2. \nConfigure RCC_PLLCFGR register and set PLLON bit of RCC_CR register.\n3. \nSet ODEN bit of PWR_CR register to enable the Over-drive mode and wait for the \nODRDY flag to be set in the PWR_CSR register.\n4. \nSet the ODSW bit in the PWR_CR register to switch the voltage regulator from Normal \nmode to Over-drive mode. The System is stalled during the switch but the PLL clock \nsystem is still running during locking phase.\n5. \nWait for the ODSWRDY flag in the PWR_CSR to be set.\n6. \nSelect the required Flash latency as well as AHB and APB prescalers.\n7. \nWait for PLL lock.\n8. \nSwitch the system clock to the PLL.\n9. \nEnable the peripherals that are not generated by the System PLL (I2S clock, LCD-TFT \nclock, SAI1 clock, USB_48MHz clock....).\nNote:\nThe PLLI2S and PLLSAI can be configured at the same time as the system PLL.\nDuring the Over-drive switch activation, no peripheral clocks should be enabled. The \nperipheral clocks must be enabled once the Over-drive mode is activated.\nEntering Stop mode disables the Over-drive mode, as well as the PLL. The application \nsoftware has to configure again the Over-drive mode and the PLL after exiting from Stop \nmode.\nExiting from Over-drive mode\nIt is recommended to exit from Over-drive mode when the application is not running critical \ntasks and when the system clock source is either HSI or HSE.There are two sequences that \nallow exiting from over-drive mode: \n•\nBy resetting simultaneously the ODEN and ODSW bits bit in the PWR_CR register \n(sequence 1)\n•\nBy resetting first the ODSW bit to switch the voltage regulator to Normal mode and then \nresetting the ODEN bit to disable the Over-drive mode (sequence 2).\nExample of sequence 1:\n1.\nSelect HSI or HSE as system clock source.\n2. \nDisable the peripheral clocks that are not generated by the System PLL (I2S clock, \nLCD-TFT clock, SAI1 clock, USB_48MHz clock,....)\n3. \nReset simultaneously the ODEN and the ODSW bits in the PWR_CR register to switch \nback the voltage regulator to Normal mode and disable the Over-drive mode.\n4. \nWait for the ODWRDY flag of PWR_CSR to be reset.\n" }, { "page_number": 125, "page_indices": { "start_index": 365434, "end_index": 366835 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 125 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.2 Power supply supervisor", 125 ], [ 3, "5.2.1 Power-on reset (POR)/power-down reset (PDR)", 125 ] ], "page_content": "RM0090 Rev 21\n125/1757\nRM0090\nPower controller (PWR)\n151\nExample of sequence 2:\n1.\nSelect HSI or HSE as system clock source. \n2. \nDisable the peripheral clocks that are not generated by the System PLL (I2S clock, \nLCD-TFT clock, SAI1 clock, USB_48MHz clock,....).\n3. \nReset the ODSW bit in the PWR_CR register to switch back the voltage regulator to \nNormal mode. The system clock is stalled during voltage switching.\n4. \nWait for the ODWRDY flag of PWR_CSR to be reset.\n5. \nReset the ODEN bit in the PWR_CR register to disable the Over-drive mode.\nNote:\nDuring step 3, the ODEN bit remains set and the Over-drive mode is still enabled but not \nactive (ODSW bit is reset). If the ODEN bit is reset instead, the Over-drive mode is disabled \nand the voltage regulator is switched back to the initial voltage.\n5.2 \nPower supply supervisor\n5.2.1 \nPower-on reset (POR)/power-down reset (PDR)\nThe device has an integrated POR/PDR circuitry that allows proper operation starting\nfrom 1.8 V.\nThe device remains in Reset mode when VDD/VDDA is below a specified threshold, \nVPOR/PDR, without the need for an external reset circuit. For more details concerning the \npower on/power-down reset threshold, refer to the electrical characteristics of the \ndatasheet. \nFigure 12. Power-on reset/power-down reset waveform\nMSv30431V2\nVDD/VDDA\n40 mV\nhysteresis\nPOR\nPOR\nReset\nTemporization\ntRSTTEMPO\n" }, { "page_number": 126, "page_indices": { "start_index": 366835, "end_index": 368182 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 126 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.2 Power supply supervisor", 125 ], [ 3, "5.2.2 Brownout reset (BOR)", 126 ], [ 3, "5.2.3 Programmable voltage detector (PVD)", 126 ] ], "page_content": "Power controller (PWR)\nRM0090\n126/1757\nRM0090 Rev 21\n5.2.2 \nBrownout reset (BOR)\nDuring power on, the Brownout reset (BOR) keeps the device under reset until the supply \nvoltage reaches the specified VBOR threshold.\nVBOR is configured through device option bytes. By default, BOR is off. 3 programmable \nVBOR threshold levels can be selected:\n•\nBOR Level 3 (VBOR3). Brownout threshold level 3.\n•\nBOR Level 2 (VBOR2). Brownout threshold level 2.\n•\nBOR Level 1 (VBOR1). Brownout threshold level 1.\nNote:\nFor full details about BOR characteristics, refer to the \"Electrical characteristics\" section in \nthe device datasheet.\nWhen the supply voltage (VDD) drops below the selected VBOR threshold, a device reset is \ngenerated.\nThe BOR can be disabled by programming the device option bytes. In this case, the \npower-on and power-down is then monitored by the POR/ PDR (see Section 5.2.1: Power-\non reset (POR)/power-down reset (PDR)).\nThe BOR threshold hysteresis is ~100 mV (between the rising and the falling edge of the \nsupply voltage).\nFigure 13. BOR thresholds\n5.2.3 \nProgrammable voltage detector (PVD)\nYou can use the PVD to monitor the VDD power supply by comparing it to a threshold \nselected by the PLS[2:0] bits in the PWR power control register (PWR_CR) for \nMS30433V1\nVDD/VDDA\n100 mV\nhysteresis\nBOR threshold\nReset\n" }, { "page_number": 127, "page_indices": { "start_index": 368182, "end_index": 369750 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 127 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.3 Low-power modes", 127 ] ], "page_content": "RM0090 Rev 21\n127/1757\nRM0090\nPower controller (PWR)\n151\nSTM32F405xx/07xx and STM32F415xx/17xx and PWR power control register (PWR_CR) \nfor STM32F42xxx and STM32F43xxx.\nThe PVD is enabled by setting the PVDE bit.\nA PVDO flag is available, in the PWR power control/status register (PWR_CSR) for \nSTM32F405xx/07xx and STM32F415xx/17xx, to indicate if VDD is higher or lower than the \nPVD threshold. This event is internally connected to the EXTI line16 and can generate an \ninterrupt if enabled through the EXTI registers. The PVD output interrupt can be generated \nwhen VDD drops below the PVD threshold and/or when VDD rises above the PVD threshold \ndepending on EXTI line16 rising/falling edge configuration. As an example the service \nroutine could perform emergency shutdown tasks.\nFigure 14. PVD thresholds\n5.3 \nLow-power modes\nBy default, the microcontroller is in Run mode after a system or a power-on reset. In Run \nmode the CPU is clocked by HCLK and the program code is executed. Several low-power \nmodes are available to save power when the CPU does not need to be kept running, for \nexample when waiting for an external event. It is up to the user to select the mode that gives \nthe best compromise between low-power consumption, short startup time and available \nwake-up sources.\nThe devices feature three low-power modes:\n•\nSleep mode (Cortex®-M4 with FPU core stopped, peripherals kept running)\n•\nStop mode (all clocks are stopped)\n•\nStandby mode (1.2 V domain powered off)\nMS30432V2\nVDD\n100 mV\nhysteresis\nPVD threshold\nPVD output\n" }, { "page_number": 128, "page_indices": { "start_index": 369750, "end_index": 372505 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 128 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.3 Low-power modes", 127 ], [ 3, "Entering low-power mode", 128 ], [ 3, "Exiting low-power mode", 128 ] ], "page_content": "Power controller (PWR)\nRM0090\n128/1757\nRM0090 Rev 21\nIn addition, the power consumption in Run mode can be reduce by one of the following \nmeans:\n•\nSlowing down the system clocks\n•\nGating the clocks to the APBx and AHBx peripherals when they are unused.\nEntering low-power mode\nLow-power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or \nWFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M4 with \nFPU System Control register is set on Return from ISR.\nEntering Low-power mode through WFI or WFE is executed only if no interrupt is pending or \nno event is pending.\nExiting low-power mode\nThe MCU exits from Sleep and Stop modes low-power mode depending on the way the low-\npower mode was entered:\n•\nIf the WFI instruction or Return from ISR was used to enter the low-power mode, any \nperipheral interrupt acknowledged by the NVIC can wake up the device.\n•\nIf the WFE instruction is used to enter the low-power mode, the MCU exits the low-\npower mode as soon as an event occurs. The wake-up event can be generated either \nby:\n–\nNVIC IRQ interrupt:\nWhen SEVONPEND = 0 in the Cortex®-M4 with FPU System Control register: by \nenabling an interrupt in the peripheral control register and in the NVIC. When the \nMCU resumes from WFE, the peripheral interrupt pending bit and the NVIC \nperipheral IRQ channel pending bit (in the NVIC interrupt clear pending register) \nhave to be cleared. Only NVIC interrupts with sufficient priority wakes up and \ninterrupts the MCU.\nWhen SEVONPEND = 1 in the Cortex®-M4 with FPU System Control register: by \nenabling an interrupt in the peripheral control register and optionally in the NVIC. \nWhen the MCU resumes from WFE, the peripheral interrupt pending bit and when \nenabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear \npending register) have to be cleared. All NVIC interrupts wakes up the MCU, even \nthe disabled ones. Only enabled NVIC interrupts with sufficient priority wakes up \nand interrupts the MCU.\n–\nEvent\nThis is done by configuring a EXTI line in event mode. When the CPU resumes \nfrom WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or \nthe NVIC IRQ channel pending bit as the pending bits corresponding to the event \nline is not set. It may be necessary to clear the interrupt flag in the peripheral.\nThe MCU exits from Standby low-power mode through an external reset (NRST pin), an \nIWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs (see \nFigure 237: RTC block diagram).\nAfter waking up from Standby mode, program execution restarts in the same way as after a \nReset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).\n" }, { "page_number": 129, "page_indices": { "start_index": 372505, "end_index": 374335 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 129 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.3 Low-power modes", 127 ], [ 3, "5.3.1 Slowing down system clocks", 129 ], [ 3, "5.3.2 Peripheral clock gating", 129 ] ], "page_content": "RM0090 Rev 21\n129/1757\nRM0090\nPower controller (PWR)\n151\nOnly enabled NVIC interrupts with sufficient priority wakes up and interrupts the MCU.\n5.3.1 \nSlowing down system clocks\nIn Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be \nreduced by programming the prescaler registers. These prescalers can also be used to slow \ndown peripherals before entering Sleep mode. \nFor more details refer to Section 7.3.3: RCC clock configuration register (RCC_CFGR).\n5.3.2 \nPeripheral clock gating\nIn Run mode, the HCLKx and PCLKx for individual peripherals and memories can be \nstopped at any time to reduce power consumption. \nTo further reduce power consumption in Sleep mode the peripheral clocks can be disabled \nprior to executing the WFI or WFE instructions.\nTable 24. Low-power mode summary\nMode name\nEntry\nWake-up\nEffect on 1.2 V \ndomain clocks\nEffect on \nVDD \ndomain \nclocks\nVoltage regulator\nSleep\n(Sleep now or \nSleep-on-\nexit)\nWFI or Return \nfrom ISR\nAny interrupt\nCPU CLK OFF\nno effect on other \nclocks or analog \nclock sources\nNone\nON\nWFE\nWake-up event\nStop\nPDDS and LPDS \nbits + \nSLEEPDEEP bit \n+ WFI, Return \nfrom ISR or WFE\nAny EXTI line (configured \nin the EXTI registers, \ninternal and external lines)\nAll 1.2 V domain \nclocks OFF\nHSI and \nHSE \noscillator\ns OFF\nON or in low- power \nmode (depends on \nPWR power control \nregister (PWR_CR) \nfor \nSTM32F405xx/07x\nx and \nSTM32F415xx/17x\nx and PWR power \ncontrol register \n(PWR_CR) for \nSTM32F405xx/07x\nx and \nSTM32F415xx/17x\nxPWR power \ncontrol register \n(PWR_CR) for \nSTM32F42xxx and \nSTM32F43xxx\nStandby\nPDDS bit + \nSLEEPDEEP bit \n+ WFI, Return \nfrom ISR or WFE \nWKUP pin rising edge, \nRTC alarm (Alarm A or \nAlarm B), RTC Wake-up \nevent, RTC tamper \nevents, RTC time stamp \nevent, external reset in \nNRST pin, IWDG reset\nOFF\n" }, { "page_number": 130, "page_indices": { "start_index": 374335, "end_index": 376243 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 130 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.3 Low-power modes", 127 ], [ 3, "5.3.3 Sleep mode", 130 ], [ 4, "Entering Sleep mode", 130 ], [ 4, "Exiting Sleep mode", 130 ] ], "page_content": "Power controller (PWR)\nRM0090\n130/1757\nRM0090 Rev 21\nPeripheral clock gating is controlled by the AHB1 peripheral clock enable register \n(RCC_AHB1ENR), AHB2 peripheral clock enable register (RCC_AHB2ENR), AHB3 \nperipheral clock enable register (RCC_AHB3ENR) (see Section 7.3.10: RCC AHB1 \nperipheral clock enable register (RCC_AHB1ENR), Section 7.3.11: RCC AHB2 peripheral \nclock enable register (RCC_AHB2ENR), Section 7.3.12: RCC AHB3 peripheral clock \nenable register (RCC_AHB3ENR) for STM32F405xx/07xx and STM32F415xx/17xx, and \nSection 6.3.10: RCC AHB1 peripheral clock register (RCC_AHB1ENR), Section 6.3.11: \nRCC AHB2 peripheral clock enable register (RCC_AHB2ENR), and Section 6.3.12: RCC \nAHB3 peripheral clock enable register (RCC_AHB3ENR) for STM32F42xxx and \nSTM32F43xxx).\nDisabling the peripherals clocks in Sleep mode can be performed automatically by resetting \nthe corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers.\n5.3.3 \nSleep mode\nEntering Sleep mode\nThe Sleep mode is entered according to Section : Entering low-power mode, when the \nSLEEPDEEP bit in the Cortex®-M4 with FPU System Control register is cleared.\nRefer to Table 25 and Table 26 for details on how to enter Sleep mode.\nNote:\nAll interrupt pending bits must be cleared before the sleep mode entry.\nExiting Sleep mode\nThe Sleep mode is exited according to Section : Exiting low-power mode.\nRefer to Table 25 and Table 26 for more details on how to exit Sleep mode.\n \nTable 25. Sleep-now entry and exit\nSleep-now mode\nDescription\nMode entry\nWFI (Wait for Interrupt) or WFE (Wait for Event) while:\n– SLEEPDEEP = 0, and\n– No interrupt (for WFI) or event (for WFE) is pending.\nRefer to the Cortex®-M4 with FPU System Control register. \nOn Return from ISR while: \n– SLEEPDEEP = 0 and \n– SLEEPONEXIT = 1,\n– No interrupt is pending.\nRefer to the Cortex®-M4 with FPU System Control register. \n" }, { "page_number": 131, "page_indices": { "start_index": 376243, "end_index": 378455 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 131 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.3 Low-power modes", 127 ], [ 3, "5.3.4 Stop mode (STM32F405xx/07xx and STM32F415xx/17xx)", 131 ] ], "page_content": "RM0090 Rev 21\n131/1757\nRM0090\nPower controller (PWR)\n151\n \n5.3.4 \nStop mode (STM32F405xx/07xx and STM32F415xx/17xx)\nThe Stop mode is based on the Cortex®-M4 with FPU deepsleep mode combined with \nperipheral clock gating. The voltage regulator can be configured either in normal or low-\npower mode. In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI \nand the HSE RC oscillators are disabled. Internal SRAM and register contents are \npreserved. \nBy setting the FPDS bit in the PWR_CR register, the Flash memory also enters power-down \nmode when the device enters Stop mode. When the Flash memory is in power-down mode, \nan additional startup delay is incurred when waking up from Stop mode (see Table 27: Stop \noperating modes (STM32F405xx/07xx and STM32F415xx/17xx) and Section 5.4.1: PWR \npower control register (PWR_CR) for STM32F405xx/07xx and STM32F415xx/17xx).\nMode exit\nIf WFI or Return from ISR was used for entry:\nInterrupt: Refer to Table 62: Vector table for STM32F405xx/07xx and \nSTM32F415xx/17xx and Table 63: Vector table for STM32F42xxx and \nSTM32F43xxx\nIf WFE was used for entry and SEVONPEND = 0\nWake-up event: Refer to Section 12.2.3: Wake-up event management\nf WFE was used for entry and SEVONPEND = 1\nInterrupt even when disabled in NVIC: refer to Table 62: Vector table for \nSTM32F405xx/07xx and STM32F415xx/17xx and Table 63: Vector table \nfor STM32F42xxx and STM32F43xxx or Wake-up event (see \nSection 12.2.3: Wake-up event management).\nWake-up latency\nNone\nTable 26. Sleep-on-exit entry and exit\nSleep-on-exit\nDescription\nMode entry\nWFI (Wait for Interrupt) or WFE (Wait for Event) while:\n– SLEEPDEEP = 0, and\n– No interrupt (for WFI) or event (for WFE) is pending.\nRefer to the Cortex®-M4 with FPU System Control register. \nOn Return from ISR while: \n– SLEEPDEEP = 0, and \n– SLEEPONEXIT = 1, and\n– No interrupt is pending.\nRefer to the Cortex®-M4 with FPU System Control register. \nMode exit\nInterrupt: refer to Table 62: Vector table for STM32F405xx/07xx and \nSTM32F415xx/17xx and Table 63: Vector table for STM32F42xxx and \nSTM32F43xxx\nWake-up latency\nNone\nTable 25. Sleep-now entry and exit (continued)\nSleep-now mode\nDescription\n" }, { "page_number": 132, "page_indices": { "start_index": 378455, "end_index": 380749 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 132 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.3 Low-power modes", 127 ], [ 3, "5.3.4 Stop mode (STM32F405xx/07xx and STM32F415xx/17xx)", 131 ], [ 4, "Entering Stop mode (for STM32F405xx/07xx and STM32F415xx/17xx)", 132 ] ], "page_content": "Power controller (PWR)\nRM0090\n132/1757\nRM0090 Rev 21\n \nEntering Stop mode (for STM32F405xx/07xx and STM32F415xx/17xx)\nThe Stop mode is entered according to Section : Entering low-power mode, when the \nSLEEPDEEP bit in the Cortex®-M4 with FPU System Control register is set.\nRefer to Table 28 for details on how to enter the Stop mode.\nTo further reduce power consumption in Stop mode, the internal voltage regulator can be put \nin low-power mode. This is configured by the LPDS bit of the PWR power control register \n(PWR_CR) for STM32F405xx/07xx and STM32F415xx/17xx and PWR power control \nregister (PWR_CR) for STM32F42xxx and STM32F43xxx.\nIf Flash memory programming is ongoing, the Stop mode entry is delayed until the memory \naccess is finished. \nIf an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB \naccess is finished.\nIn Stop mode, the following features can be selected by programming individual control bits:\n•\nIndependent watchdog (IWDG): the IWDG is started by writing to its Key register or by \nhardware option. Once started it cannot be stopped except by a Reset. See \nSection 21.3 in Section 21: Independent watchdog (IWDG).\n•\nReal-time clock (RTC): this is configured by the RTCEN bit in the Section 7.3.20: RCC \nBackup domain control register (RCC_BDCR)\n•\nInternal RC oscillator (LSI RC): this is configured by the LSION bit in the \nSection 7.3.21: RCC clock control & status register (RCC_CSR).\n•\nExternal 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the \nSection 7.3.20: RCC Backup domain control register (RCC_BDCR).\nThe ADC or DAC can also consume power during the Stop mode, unless they are disabled \nbefore entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit \nin the DAC_CR register must both be written to 0.\nTable 27. Stop operating modes\n(STM32F405xx/07xx and STM32F415xx/17xx)\nStop mode\nLPDS bit \nFPDS bit\nWake-up latency\n STOP MR\n(Main regulator)\n0\n0\nHSI RC startup time\n STOP MR-FPD\n0\n1\nHSI RC startup time +\nFlash wake-up time from Power \nDown mode\n STOP LP\n1\n0\nHSI RC startup time +\nregulator wake-up time from LP \nmode\n STOP LP-FPD\n1\n1\nHSI RC startup time +\nFlash wake-up time from Power \nDown mode +\nregulator wake-up time from LP \nmode\n" }, { "page_number": 133, "page_indices": { "start_index": 380749, "end_index": 382792 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 133 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.3 Low-power modes", 127 ], [ 3, "5.3.4 Stop mode (STM32F405xx/07xx and STM32F415xx/17xx)", 131 ], [ 4, "Exiting Stop mode (for STM32F405xx/07xx and STM32F415xx/17xx)", 133 ] ], "page_content": "RM0090 Rev 21\n133/1757\nRM0090\nPower controller (PWR)\n151\nNote:\nIf the application needs to disable the external clock before entering Stop mode, the HSEON \nbit must first be disabled and the system clock switched to HSI.\nOtherwise, if the HSEON bit is kept enabled while the external clock (external oscillator) can \nbe removed before entering stop mode, the clock security system (CSS) feature must be \nenabled to detect any external oscillator failure and avoid a malfunction behavior when \nentering stop mode.\nExiting Stop mode (for STM32F405xx/07xx and STM32F415xx/17xx)\nThe Stop mode is exited according to Section : Exiting low-power mode.\nRefer to Table 28 for more details on how to exit Stop mode.\nWhen exiting Stop mode by issuing an interrupt or a wake-up event, the HSI RC oscillator is \nselected as system clock. \nWhen the voltage regulator operates in low-power mode, an additional startup delay is \nincurred when waking up from Stop mode. By keeping the internal regulator ON during Stop \nmode, the consumption is higher although the startup time is reduced.\n Table 28. Stop mode entry and exit (for STM32F405xx/07xx and STM32F415xx/17xx)\nStop mode\nDescription\nMode entry\nWFI (Wait for Interrupt) or WFE (Wait for Event) while:\n– No interrupt (for WFI) or event (for WFE) is pending,\n– SLEEPDEEP bit is set in Cortex®-M4 with FPU System Control register,\n– PDDS bit is cleared in Power Control register (PWR_CR),\n– Select the voltage regulator mode by configuring LPDS bit in PWR_CR.\nOn Return from ISR:\n– No interrupt is pending,\n– SLEEPDEEP bit is set in Cortex®-M4 with FPU System Control register,\n– SLEEPONEXIT = 1, \n– PDDS bit is cleared in Power Control register (PWR_CR).\nNote: To enter Stop mode, all EXTI Line pending bits (in Pending register \n(EXTI_PR)), all peripheral interrupts pending bits, the RTC Alarm \n(Alarm A and Alarm B), RTC wake-up, RTC tamper, and RTC time \nstamp flags, must be reset. Otherwise, the Stop mode entry \nprocedure is ignored and program execution continues.\n" }, { "page_number": 134, "page_indices": { "start_index": 382792, "end_index": 384716 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 134 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.3 Low-power modes", 127 ], [ 3, "5.3.5 Stop mode (STM32F42xxx and STM32F43xxx)", 134 ] ], "page_content": "Power controller (PWR)\nRM0090\n134/1757\nRM0090 Rev 21\n5.3.5 \nStop mode (STM32F42xxx and STM32F43xxx)\nThe Stop mode is based on the Cortex®-M4 with FPU deepsleep mode combined with \nperipheral clock gating. The voltage regulator can be configured either in normal or low-\npower mode. In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI \nand the HSE RC oscillators are disabled. Internal SRAM and register contents are \npreserved. \nIn Stop mode, the power consumption can be further reduced by using additional settings in \nthe PWR_CR register. However this induces an additional startup delay when waking up \nfrom Stop mode (see Table 29).\nMode exit\nIf WFI or Return from ISR was used for entry:\nAny EXTI lines configured in Interrupt mode (the corresponding EXTI \nInterrupt vector must be enabled in the NVIC). The interrupt source can \nbe external interrupts or peripherals with wake-up capability. Refer to \nTable 62: Vector table for STM32F405xx/07xx and STM32F415xx/17xx \non page 375 and Table 63: Vector table for STM32F42xxx and \nSTM32F43xxx.\nIf WFE was used for entry and SEVONPEND = 0\nAny EXTI lines configured in event mode. Refer to Section 12.2.3: Wake-\nup event management on page 383.\nIf WFE was used for entry and SEVONPEND = 1: \n– Any EXTI lines configured in Interrupt mode (even if the corresponding \nEXTI Interrupt vector is disabled in the NVIC). The interrupt source can \nbe an external interrupt or a peripheral with wake-up capability. Refer to \nTable 62: Vector table for STM32F405xx/07xx and STM32F415xx/17xx \non page 375 and Table 63: Vector table for STM32F42xxx and \nSTM32F43xxx.\n– Wake-up event: refer to Section 12.2.3: Wake-up event management on \npage 383.\nWake-up latency\nTable 27: Stop operating modes (STM32F405xx/07xx and \nSTM32F415xx/17xx)\nTable 28. Stop mode entry and exit (for STM32F405xx/07xx and STM32F415xx/17xx) \nStop mode\nDescription\n" }, { "page_number": 135, "page_indices": { "start_index": 384716, "end_index": 386672 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 135 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.3 Low-power modes", 127 ], [ 3, "5.3.5 Stop mode (STM32F42xxx and STM32F43xxx)", 134 ], [ 4, "Entering Stop mode (STM32F42xxx and STM32F43xxx)", 135 ] ], "page_content": "RM0090 Rev 21\n135/1757\nRM0090\nPower controller (PWR)\n151\n \nEntering Stop mode (STM32F42xxx and STM32F43xxx)\nThe Stop mode is entered according to Section : Entering low-power mode, when the \nSLEEPDEEP bit in the Cortex®-M4 with FPU System Control register is set.\nRefer to Table 30 for details on how to enter the Stop mode.\nWhen the microcontroller enters in Stop mode, the voltage scale 3 is automatically selected. \nTo further reduce power consumption in Stop mode, the internal voltage regulator can be put \nin low voltage mode. This is configured by the LPDS, MRUDS, LPUDS and UDEN bits of \nthe PWR power control register (PWR_CR) for STM32F405xx/07xx and \nSTM32F415xx/17xx.\nIf Flash memory programming is ongoing, the Stop mode entry is delayed until the memory \naccess is finished. \nIf an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB \naccess is finished.\nIf the Over-drive mode was enabled before entering Stop mode, it is automatically disabled \nduring when the Stop mode is activated.\nTable 29. Stop operating modes (STM32F42xxx and STM32F43xxx)\nVoltage Regulator Mode \nUDEN[1:0] \nbits \nMRUDS \nbit \nLPUDS \nbit\nLPDS \nbit \nFPDS \nbit\nWake-up latency\nNormal \nmode\nSTOP MR\n(Main Regulator)\n - \n0\n - \n0\n0\nHSI RC startup time\nSTOP MR- FPD\n - \n0\n - \n0\n1\nHSI RC startup time +\nFlash wake-up time from power-\ndown mode\nSTOP LP\n - \n0\n0\n1\n0\nHSI RC startup time +\nregulator wake-up time from LP \nmode\nSTOP LP-FPD\n - \n - \n0\n1\n1\nHSI RC startup time +\nFlash wake-up time from power-\ndown mode +\nregulator wake-up time from LP \nmode\nUnder-\ndrive \nMode\nSTOP UMR-\nFPD\n3\n1\n - \n0\n - \nHSI RC startup time +\nFlash wake-up time from power-\ndown mode +\nMain regulator wake-up time from \nunder-drive mode + Core logic to \nnominal mode\nSTOP ULP-FPD\n3\n - \n1\n1\n - \nHSI RC startup time +\nFlash wake-up time from power-\ndown mode +\nregulator wake-up time from LP \nunder-drive mode + Core logic to \nnominal mode\n" }, { "page_number": 136, "page_indices": { "start_index": 386672, "end_index": 388654 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 136 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.3 Low-power modes", 127 ], [ 3, "5.3.5 Stop mode (STM32F42xxx and STM32F43xxx)", 134 ], [ 4, "Exiting Stop mode (STM32F42xxx and STM32F43xxx)", 136 ] ], "page_content": "Power controller (PWR)\nRM0090\n136/1757\nRM0090 Rev 21\nIn Stop mode, the following features can be selected by programming individual control bits:\n•\nIndependent watchdog (IWDG): the IWDG is started by writing to its Key register or by \nhardware option. Once started it cannot be stopped except by a Reset. See \nSection 21.3 in Section 21: Independent watchdog (IWDG).\n•\nReal-time clock (RTC): this is configured by the RTCEN bit in the Section 7.3.20: RCC \nBackup domain control register (RCC_BDCR)\n•\nInternal RC oscillator (LSI RC): this is configured by the LSION bit in the \nSection 7.3.21: RCC clock control & status register (RCC_CSR).\n•\nExternal 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the \nRCC Backup domain control register (RCC_BDCR).\nThe ADC or DAC can also consume power during the Stop mode, unless they are disabled \nbefore entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit \nin the DAC_CR register must both be written to 0.\nNote:\nBefore entering Stop mode, it is recommended to enable the clock security system (CSS) \nfeature to prevent external oscillator (HSE) failure from impacting the internal MCU \nbehavior.\nExiting Stop mode (STM32F42xxx and STM32F43xxx)\nThe Stop mode is exited according to Section : Exiting low-power mode.\nRefer to Table 30 for more details on how to exit Stop mode.\nWhen exiting Stop mode by issuing an interrupt or a wake-up event, the HSI RC oscillator is \nselected as system clock. \nIf the Under-drive mode was enabled, it is automatically disabled after exiting Stop mode.\nWhen the voltage regulator operates in low voltage mode, an additional startup delay is \nincurred when waking up from Stop mode. By keeping the internal regulator ON during Stop \nmode, the consumption is higher although the startup time is reduced.\nWhen the voltage regulator operates in Under-drive mode, an additional startup delay is \ninduced when waking up from Stop mode.\n" }, { "page_number": 137, "page_indices": { "start_index": 388654, "end_index": 391272 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 137 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.3 Low-power modes", 127 ], [ 3, "5.3.6 Standby mode", 137 ] ], "page_content": "RM0090 Rev 21\n137/1757\nRM0090\nPower controller (PWR)\n151\n \n5.3.6 \nStandby mode\nThe Standby mode allows to achieve the lowest power consumption. It is based on the \nCortex®-M4 with FPU deepsleep mode, with the voltage regulator disabled. The 1.2 V \ndomain is consequently powered off. The PLLs, the HSI oscillator and the HSE oscillator are \nalso switched off. SRAM and register contents are lost except for registers in the backup \ndomain (RTC registers, RTC backup register and backup SRAM), and Standby circuitry (see \nFigure 9).\nTable 30. Stop mode entry and exit (STM32F42xxx and STM32F43xxx)\nStop mode\nDescription\nMode entry\nWFI (Wait for Interrupt) or WFE (Wait for Event) while:\n– No interrupt or event is pending,\n– SLEEPDEEP bit is set in Cortex®-M4 with FPU System Control register,\n– PDDS bit is cleared in Power Control register (PWR_CR),\n– Select the voltage regulator mode by configuring LPDS, MRUDS, LPUDS \nand UDEN bits in PWR_CR (see Table 29: Stop operating modes \n(STM32F42xxx and STM32F43xxx)).\nOn Return from ISR while:\n– No interrupt is pending,\n– SLEEPDEEP bit is set in Cortex®-M4 with FPU System Control register, \nand\n– SLEEPONEXIT = 1, and\n– PDDS is cleared in PWR_CR1.\nNote: To enter Stop mode, all EXTI Line pending bits (in Pending register \n(EXTI_PR)), all peripheral interrupts pending bits, the RTC Alarm \n(Alarm A and Alarm B), RTC wake-up, RTC tamper, and RTC time \nstamp flags, must be reset. Otherwise, the Stop mode entry \nprocedure is ignored and program execution continues.\nMode exit\nIf WFI or Return from ISR was used for entry:\nAll EXTI lines configured in Interrupt mode (the corresponding EXTI \nInterrupt vector must be enabled in the NVIC). The interrupt source can \nbe external interrupts or peripherals with wake-up capability. Refer to \nTable 62: Vector table for STM32F405xx/07xx and STM32F415xx/17xx \non page 375.\nIf WFE was used for entry and SEVONPEND = 0:\nAll EXTI Lines configured in event mode. Refer to Section 12.2.3: Wake-\nup event management on page 383\nIf WFE was used for entry and SEVONPEND = 1: \n– Any EXTI lines configured in Interrupt mode (even if the corresponding \nEXTI Interrupt vector is disabled in the NVIC). The interrupt source can \nbe external interrupts or peripherals with wake-up capability. Refer to \nTable 62: Vector table for STM32F405xx/07xx and STM32F415xx/17xx \non page 375 and Table 63: Vector table for STM32F42xxx and \nSTM32F43xxx.\n– Wake-up event: refer to Section 12.2.3: Wake-up event management on \npage 383.\nWake-up latency\nRefer to Table 29: Stop operating modes (STM32F42xxx and \nSTM32F43xxx)\n" }, { "page_number": 138, "page_indices": { "start_index": 391272, "end_index": 393796 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 138 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.3 Low-power modes", 127 ], [ 3, "5.3.6 Standby mode", 137 ], [ 4, "Entering Standby mode", 138 ], [ 4, "Exiting Standby mode", 138 ] ], "page_content": "Power controller (PWR)\nRM0090\n138/1757\nRM0090 Rev 21\nEntering Standby mode\nThe Standby mode is entered according to Section : Entering low-power mode, when the \nSLEEPDEEP bit in the Cortex®-M4 with FPU System Control register is set. \nRefer to Table 31 for more details on how to enter Standby mode.\nIn Standby mode, the following features can be selected by programming individual control \nbits:\n•\nIndependent watchdog (IWDG): the IWDG is started by writing to its Key register or by \nhardware option. Once started it cannot be stopped except by a reset. See \nSection 21.3 in Section 21: Independent watchdog (IWDG).\n•\nReal-time clock (RTC): this is configured by the RTCEN bit in the backup domain \ncontrol register (RCC_BDCR) \n•\nInternal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status \nregister (RCC_CSR). \n•\nExternal 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the \nbackup domain control register (RCC_BDCR)\nExiting Standby mode\nThe Standby mode is exited according to Section : Exiting low-power mode. The SBF status \nflag in PWR_CR (see Section 5.4.2: PWR power control/status register (PWR_CSR) for \nSTM32F405xx/07xx and STM32F415xx/17xx) indicates that the MCU was in Standby \nmode. All registers are reset after wake-up from Standby except for PWR_CR.\nRefer to Table 31 for more details on how to exit Standby mode.\n \n \nTable 31. Standby mode entry and exit\nStandby mode\nDescription\nMode entry\nWFI (Wait for Interrupt) or WFE (Wait for Event) while:\n– SLEEPDEEP is set in Cortex®-M4 with FPU System Control register,\n– PDDS bit is set in Power Control register (PWR_CR),\n– No interrupt (for WFI) or event (for WFE) is pending,\n– WUF bit is cleared in Power Control register (PWR_CR),\n– the RTC flag corresponding to the chosen wake-up source (RTC Alarm \nA, RTC Alarm B, RTC wake-up, Tamper or Timestamp flags) is cleared\nOn return from ISR while:\n– SLEEPDEEP bit is set in Cortex®-M4 with FPU System Control register, \nand\n– SLEEPONEXIT = 1, and\n– PDDS bit is set in Power Control register (PWR_CR), and\n– No interrupt is pending,\n– WUF bit is cleared in Power Control/Status register (PWR_SR),\n– The RTC flag corresponding to the chosen wake-up source (RTC Alarm \nA, RTC Alarm B, RTC wake-up, Tamper or Timestamp flags) is cleared.\nMode exit\nWKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up, \ntamper event, time stamp event, external reset in NRST pin, IWDG reset.\nWake-up latency\nReset phase.\n" }, { "page_number": 139, "page_indices": { "start_index": 393796, "end_index": 395862 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 139 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.3 Low-power modes", 127 ], [ 3, "5.3.6 Standby mode", 137 ], [ 4, "I/O states in Standby mode", 139 ], [ 4, "Debug mode", 139 ], [ 3, "5.3.7 Programming the RTC alternate functions to wake up the device from the Stop and Standby modes", 139 ] ], "page_content": "RM0090 Rev 21\n139/1757\nRM0090\nPower controller (PWR)\n151\nI/O states in Standby mode\nIn Standby mode, all I/O pins are high impedance except for:\n•\nReset pad (still available)\n•\nRTC_AF1 pin (PC13) if configured for tamper, time stamp, RTC Alarm out, or RTC \nclock calibration out\n•\nWKUP pin (PA0), if enabled\nDebug mode\nBy default, the debug connection is lost if the application puts the MCU in Stop or Standby \nmode while the debug features are used. This is due to the fact that the Cortex®-M4 with \nFPU core is no longer clocked.\nHowever, by setting some configuration bits in the DBGMCU_CR register, the software can \nbe debugged even when using the low-power modes extensively. For more details, refer to \nSection 38.16.1: Debug support for low-power modes.\n5.3.7 \nProgramming the RTC alternate functions to wake up the device from\nthe Stop and Standby modes\nThe MCU can be woken up from a low-power mode by an RTC alternate function.\nThe RTC alternate functions are the RTC alarms (Alarm A and Alarm B), RTC wake-up, \nRTC tamper event detection and RTC time stamp event detection.\nThese RTC alternate functions can wake up the system from the Stop and Standby low-\npower modes.\nThe system can also wake up from low-power modes without depending on an external \ninterrupt (Auto-wake-up mode), by using the RTC alarm or the RTC wake-up events.\nThe RTC provides a programmable time base for waking up from the Stop or Standby mode \nat regular intervals.\nFor this purpose, two of the three alternate RTC clock sources can be selected by \nprogramming the RTCSEL[1:0] bits in the Section 7.3.20: RCC Backup domain control \nregister (RCC_BDCR):\n•\nLow-power 32.768 kHz external crystal oscillator (LSE OSC)\nThis clock source provides a precise time base with a very low-power consumption \n(additional consumption of less than 1 µA under typical conditions)\n•\nLow-power internal RC oscillator (LSI RC)\nThis clock source has the advantage of saving the cost of the 32.768 kHz crystal. This \ninternal RC oscillator is designed to use minimum power.\n" }, { "page_number": 140, "page_indices": { "start_index": 395862, "end_index": 398375 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 140 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.3 Low-power modes", 127 ], [ 3, "5.3.7 Programming the RTC alternate functions to wake up the device from the Stop and Standby modes", 139 ], [ 4, "RTC alternate functions to wake up the device from the Stop mode", 140 ], [ 4, "RTC alternate functions to wake up the device from the Standby mode", 140 ], [ 4, "Safe RTC alternate function wake-up flag clearing sequence", 140 ] ], "page_content": "Power controller (PWR)\nRM0090\n140/1757\nRM0090 Rev 21\nRTC alternate functions to wake up the device from the Stop mode\n•\nTo wake up the device from the Stop mode with an RTC alarm event, it is necessary to:\na) \nConfigure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event \nmodes)\nb) \nEnable the RTC Alarm Interrupt in the RTC_CR register\nc) \nConfigure the RTC to generate the RTC alarm\n•\nTo wake up the device from the Stop mode with an RTC tamper or time stamp event, it \nis necessary to:\na) \nConfigure the EXTI Line 21 to be sensitive to rising edges (Interrupt or Event \nmodes)\nb) \nEnable the RTC time stamp Interrupt in the RTC_CR register or the RTC tamper \ninterrupt in the RTC_TAFCR register\nc) \nConfigure the RTC to detect the tamper or time stamp event\n•\nTo wake up the device from the Stop mode with an RTC wake-up event, it is necessary \nto:\na) \nConfigure the EXTI Line 22 to be sensitive to rising edges (Interrupt or Event \nmodes)\nb) \nEnable the RTC wake-up interrupt in the RTC_CR register\nc) \nConfigure the RTC to generate the RTC Wake-up event \nRTC alternate functions to wake up the device from the Standby mode\n•\nTo wake up the device from the Standby mode with an RTC alarm event, it is necessary \nto:\na) \nEnable the RTC alarm interrupt in the RTC_CR register\nb) \nConfigure the RTC to generate the RTC alarm\n•\nTo wake up the device from the Standby mode with an RTC tamper or time stamp \nevent, it is necessary to:\na) \nEnable the RTC time stamp interrupt in the RTC_CR register or the RTC tamper \ninterrupt in the RTC_TAFCR register\nb) \nConfigure the RTC to detect the tamper or time stamp event\n•\nTo wake up the device from the Standby mode with an RTC wake-up event, it is \nnecessary to:\na) \nEnable the RTC wake-up interrupt in the RTC_CR register\nb) \nConfigure the RTC to generate the RTC wake-up event\nSafe RTC alternate function wake-up flag clearing sequence\nIf the selected RTC alternate function is set before the PWR wake-up flag (WUTF) is \ncleared, it is not detected on the next event as detection is made once on the rising edge.\nTo avoid bouncing on the pins onto which the RTC alternate functions are mapped, and exit \ncorrectly from the Stop and Standby modes, it is recommended to follow the sequence \nbelow before entering the Standby mode:\n•\nWhen using RTC alarm to wake up the device from the low-power modes:\na) \nDisable the RTC alarm interrupt (ALRAIE or ALRBIE bits in the RTC_CR register)\nb) \nClear the RTC alarm (ALRAF/ALRBF) flag\n" }, { "page_number": 141, "page_indices": { "start_index": 398375, "end_index": 399426 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 141 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.3 Low-power modes", 127 ], [ 3, "5.3.7 Programming the RTC alternate functions to wake up the device from the Stop and Standby modes", 139 ], [ 4, "Safe RTC alternate function wake-up flag clearing sequence", 140 ] ], "page_content": "RM0090 Rev 21\n141/1757\nRM0090\nPower controller (PWR)\n151\nc) \nClear the PWR Wake-up (WUF) flag\nd) \nEnable the RTC alarm interrupt\ne) \nRe-enter the low-power mode\n•\nWhen using RTC wake-up to wake up the device from the low-power modes:\na) \nDisable the RTC Wake-up interrupt (WUTIE bit in the RTC_CR register)\nb) \nClear the RTC Wake-up (WUTF) flag\nc) \nClear the PWR Wake-up (WUF) flag\nd) \nEnable the RTC Wake-up interrupt\ne) \nRe-enter the low-power mode\n•\nWhen using RTC tamper to wake up the device from the low-power modes:\na) \nDisable the RTC tamper interrupt (TAMPIE bit in the RTC_TAFCR register)\nb) \nClear the Tamper (TAMP1F/TSF) flag\nc) \nClear the PWR Wake-up (WUF) flag\nd) \nEnable the RTC tamper interrupt\ne) \nRe-enter the low-power mode\n•\nWhen using RTC time stamp to wake up the device from the low-power modes:\na) \nDisable the RTC time stamp interrupt (TSIE bit in RTC_CR)\nb) \nClear the RTC time stamp (TSF) flag\nc) \nClear the PWR Wake-up (WUF) flag\nd) \nEnable the RTC TimeStamp interrupt\ne) \nRe-enter the low-power mode\n" }, { "page_number": 142, "page_indices": { "start_index": 399426, "end_index": 401375 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 142 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.4 Power control registers (STM32F405xx/07xx and STM32F415xx/17xx)", 142 ], [ 3, "5.4.1 PWR power control register (PWR_CR) for STM32F405xx/07xx and STM32F415xx/17xx", 142 ] ], "page_content": "Power controller (PWR)\nRM0090\n142/1757\nRM0090 Rev 21\n5.4 \nPower control registers (STM32F405xx/07xx and \nSTM32F415xx/17xx)\n5.4.1 \nPWR power control register (PWR_CR) \nfor STM32F405xx/07xx and STM32F415xx/17xx\nAddress offset: 0x00\nReset value: 0x0000 4000 (reset by wake-up from Standby mode)\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nVOS\nReserved\nFPDS\nDBP\nPLS[2:0]\nPVDE\nCSBF\nCWUF\nPDDS\nLPDS\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nw\nw\nrw\nrw\nBits 31:15 Reserved, must be kept at reset value.\nBit 14 VOS: Regulator voltage scaling output selection\nThis bit controls the main internal voltage regulator output voltage to achieve a trade-off \nbetween performance and power consumption when the device does not operate at the \nmaximum frequency.\n0: Scale 2 mode\n1: Scale 1 mode (default value at reset) \nBits 13:10 Reserved, must be kept at reset value.\nBit 9 FPDS: Flash power-down in Stop mode\nWhen set, the Flash memory enters power-down mode when the device enters Stop mode. \nThis allows to achieve a lower consumption in stop mode but a longer restart time.\n0: Flash memory not in power-down when the device is in Stop mode\n1: Flash memory in power-down when the device is in Stop mode\nBit 8 DBP: Disable backup domain write protection\nIn reset state, the RCC_BDCR register, the RTC registers (including the backup registers), \nand the BRE bit of the PWR_CSR register, are protected against parasitic write access. This \nbit must be set to enable write access to these registers.\n0: Access to RTC and RTC Backup registers and backup SRAM disabled\n1: Access to RTC and RTC Backup registers and backup SRAM enabled\nNote: Depending on the APB1 prescaler, there is a delay between writing to DBP and the \neffective disabling/enabling of the backup domain protection. Therefore, a dummy read \noperation to the PWR_CR register is required just after writing to the DBP bit.\n" }, { "page_number": 143, "page_indices": { "start_index": 401375, "end_index": 403054 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 143 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.4 Power control registers (STM32F405xx/07xx and STM32F415xx/17xx)", 142 ], [ 3, "5.4.2 PWR power control/status register (PWR_CSR) for STM32F405xx/07xx and STM32F415xx/17xx", 143 ] ], "page_content": "RM0090 Rev 21\n143/1757\nRM0090\nPower controller (PWR)\n151\n5.4.2 \nPWR power control/status register (PWR_CSR) \nfor STM32F405xx/07xx and STM32F415xx/17xx\nAddress offset: 0x04\nReset value: 0x0000 0000 (not reset by wake-up from Standby mode)\nAdditional APB cycles are needed to read this register versus a standard APB read.\n \nBits 7:5 PLS[2:0]: PVD level selection\nThese bits are written by software to select the voltage threshold detected by the \nprogrammable voltage detector\n000: 2.0 V\n001: 2.1 V\n010: 2.3 V\n011: 2.5 V\n100: 2.6 V\n101: 2.7 V\n110: 2.8 V\n111: 2.9 V\nNote: Refer to the electrical characteristics of the datasheet for more details.\nBit 4 PVDE: Programmable voltage detector enable\nThis bit is set and cleared by software. \n0: PVD disabled\n1: PVD enabled\nBit 3 CSBF: Clear standby flag\nThis bit is always read as 0.\n0: No effect\n1: Clear the SBF Standby Flag (write).\nBit 2 CWUF: Clear wake-up flag\nThis bit is always read as 0.\n0: No effect\n1: Clear the WUF Wake-up Flag after 2 System clock cycles\nBit 1 PDDS: Power-down deepsleep\nThis bit is set and cleared by software. It works together with the LPDS bit. \n0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the \nLPDS bit.\n1: Enter Standby mode when the CPU enters deepsleep. \nBit 0 LPDS: Low-power deepsleep\nThis bit is set and cleared by software. It works together with the PDDS bit.\n0: Voltage regulator on during Stop mode\n1: Voltage regulator in low-power mode during Stop mode\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes\nVOS\nRDY\nReserved\nBRE\nEWUP\nReserved\nBRR\nPVDO\nSBF\nWUF\nr\nrw\nrw\nr\nr\nr\nr\n" }, { "page_number": 144, "page_indices": { "start_index": 403054, "end_index": 405382 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 144 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.4 Power control registers (STM32F405xx/07xx and STM32F415xx/17xx)", 142 ], [ 3, "5.4.2 PWR power control/status register (PWR_CSR) for STM32F405xx/07xx and STM32F415xx/17xx", 143 ] ], "page_content": "Power controller (PWR)\nRM0090\n144/1757\nRM0090 Rev 21\n \nBits 31:15 Reserved, must be kept at reset value.\nBit 14 VOSRDY: Regulator voltage scaling output selection ready bit\n0: Not ready \n1: Ready\nBits 13:10 Reserved, must be kept at reset value.\nBit 9 BRE: Backup regulator enable\nWhen set, the Backup regulator (used to maintain backup SRAM content in Standby and \nVBAT modes) is enabled. If BRE is reset, the backup regulator is switched off. The backup \nSRAM can still be used but its content is lost in the Standby and VBAT modes. Once set, the \napplication must wait that the Backup Regulator Ready flag (BRR) is set to indicate that the \ndata written into the RAM is maintained in the Standby and VBAT modes.\n0: Backup regulator disabled\n1: Backup regulator enabled\nNote: This bit is not reset when the device wakes up from Standby mode, by a system reset, \nor by a power reset.\nThe DBP bit of the PWR_CR register must be set before BRE can be written.\nBit 8 EWUP: Enable WKUP pin\nThis bit is set and cleared by software.\n0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wake up \nthe device from Standby mode.\n1: WKUP pin is used for wake-up from Standby mode and forced in input pull down \nconfiguration (rising edge on WKUP pin wakes-up the system from Standby mode).\nNote: This bit is reset by a system reset.\nBits 7:4 Reserved, must be kept at reset value.\nBit 3 BRR: Backup regulator ready\nSet by hardware to indicate that the Backup Regulator is ready.\n0: Backup Regulator not ready\n1: Backup Regulator ready\nNote: This bit is not reset when the device wakes up from Standby mode or by a system reset \nor power reset.\nBit 2 PVDO: PVD output\nThis bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit. \n0: VDD is higher than the PVD threshold selected with the PLS[2:0] bits. \n1: VDD is lower than the PVD threshold selected with the PLS[2:0] bits.\nNote: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after \nStandby or reset until the PVDE bit is set.\nBit 1 SBF: Standby flag\nThis bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down \nreset) or by setting the CSBF bit in the PWR_CR register.\n0: Device has not been in Standby mode\n1: Device has been in Standby mode\n" }, { "page_number": 145, "page_indices": { "start_index": 405382, "end_index": 405922 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 145 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.4 Power control registers (STM32F405xx/07xx and STM32F415xx/17xx)", 142 ], [ 3, "5.4.2 PWR power control/status register (PWR_CSR) for STM32F405xx/07xx and STM32F415xx/17xx", 143 ] ], "page_content": "RM0090 Rev 21\n145/1757\nRM0090\nPower controller (PWR)\n151\nBit 0 WUF: Wake-up flag\nThis bit is set by hardware and cleared either by a system reset or by setting the CWUF bit in \nthe PWR_CR register.\n0: No wake-up event occurred\n1: A wake-up event was received from the WKUP pin or from the RTC alarm (Alarm A or \nAlarm B), RTC Tamper event, RTC TimeStamp event or RTC Wake-up).\nNote: An additional wake-up event is detected if the WKUP pin is enabled (by setting the \nEWUP bit) when the WKUP pin level is already high.\n" }, { "page_number": 146, "page_indices": { "start_index": 405922, "end_index": 407944 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 146 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.5 Power control registers (STM32F42xxx and STM32F43xxx)", 146 ], [ 3, "5.5.1 PWR power control register (PWR_CR) for STM32F42xxx and STM32F43xxx", 146 ] ], "page_content": "Power controller (PWR)\nRM0090\n146/1757\nRM0090 Rev 21\n5.5 \nPower control registers (STM32F42xxx and STM32F43xxx)\n5.5.1 \nPWR power control register (PWR_CR) \nfor STM32F42xxx and STM32F43xxx\nAddress offset: 0x00\nReset value: 0x0000 C000 (reset by wake-up from Standby mode)\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nUDEN[1:0]\nODSWE\nN\nODEN\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nVOS[1:0]\nADCDC1\nRes.\nMRUDS\nLPUDS\nFPDS\nDBP\nPLS[2:0]\nPVDE\nCSBF\nCWUF\nPDDS\nLPDS\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrc_w1\nrc_w1\nrw\nrw\nBits 31:20 Reserved, must be kept at reset value.\nBits 19:18 UDEN[1:0]: Under-drive enable in stop mode\nThese bits are set by software. They allow to achieve a lower power consumption in Stop \nmode but with a longer wake-up time.\nWhen set, the digital area has less leakage consumption when the device enters Stop mode.\n00: Under-drive disable\n01: Reserved\n10: Reserved\n11:Under-drive enable\nBit 17 ODSWEN: Over-drive switching enabled.\nThis bit is set by software. It is cleared automatically by hardware after exiting from Stop \nmode or when the ODEN bit is reset. When set, It is used to switch to Over-drive mode.\nTo set or reset the ODSWEN bit, the HSI or HSE must be selected as system clock. \nThe ODSWEN bit must only be set when the ODRDY flag is set to switch to Over-drive \nmode. \n0: Over-drive switching disabled\n1: Over-drive switching enabled\nNote: On any over-drive switch (enabled or disabled), the system clock is stalled during the \ninternal voltage set up. \nBit 16 ODEN: Over-drive enable \nThis bit is set by software. It is cleared automatically by hardware after exiting from Stop \nmode. It is used to enabled the Over-drive mode in order to reach a higher frequency. \nTo set or reset the ODEN bit, the HSI or HSE must be selected as system clock. When the \nODEN bit is set, the application must first wait for the Over-drive ready flag (ODRDY) to be \nset before setting the ODSWEN bit.\n0: Over-drive disabled\n1: Over-drive enabled\n" }, { "page_number": 147, "page_indices": { "start_index": 407944, "end_index": 410242 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 147 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.5 Power control registers (STM32F42xxx and STM32F43xxx)", 146 ], [ 3, "5.5.1 PWR power control register (PWR_CR) for STM32F42xxx and STM32F43xxx", 146 ] ], "page_content": "RM0090 Rev 21\n147/1757\nRM0090\nPower controller (PWR)\n151\nBits 15:14 VOS[1:0]: Regulator voltage scaling output selection\nThese bits control the main internal voltage regulator output voltage to achieve a trade-off \nbetween performance and power consumption when the device does not operate at the \nmaximum frequency (refer to the STM32F42xx and STM32F43xx datasheets for more \ndetails).\nThese bits can be modified only when the PLL is OFF. The new value programmed is active \nonly when the PLL is ON. When the PLL is OFF, the voltage scale 3 is automatically \nselected.\n00: Reserved (Scale 3 mode selected)\n01: Scale 3 mode\n10: Scale 2 mode\n11: Scale 1 mode (reset value)\nBit 13 ADCDC1: \n0: No effect. \n1: Refer to AN4073 for details on how to use this bit. \nNote: This bit can only be set when operating at supply voltage range 2.7 to 3.6V and when \nthe Prefetch is OFF. \nBit 12 Reserved, must be kept at reset value.\nBit 11 MRUDS: Main regulator in deepsleep under-drive mode\nThis bit is set and cleared by software. \n0: Main regulator ON when the device is in Stop mode\n1: Main Regulator in under-drive mode and Flash memory in power-down when the device is \nin Stop under-drive mode. \nBit 10 LPUDS: Low-power regulator in deepsleep under-drive mode\nThis bit is set and cleared by software. \n0: Low-power regulator ON if LPDS bit is set when the device is in Stop mode\n1: Low-power regulator in under-drive mode if LPDS bit is set and Flash memory in power-\ndown when the device is in Stop under-drive mode.\nBit 9 FPDS: Flash power-down in Stop mode\nWhen set, the Flash memory enters power-down mode when the device enters Stop mode. \nThis allows to achieve a lower consumption in stop mode but a longer restart time.\n0: Flash memory not in power-down when the device is in Stop mode\n1: Flash memory in power-down when the device is in Stop mode\nBit 8 DBP: Disable backup domain write protection\nIn reset state, the RCC_BDCR register, the RTC registers (including the backup registers), \nand the BRE bit of the PWR_CSR register, are protected against parasitic write access. This \nbit must be set to enable write access to these registers.\n0: Access to RTC and RTC Backup registers and backup SRAM disabled\n1: Access to RTC and RTC Backup registers and backup SRAM enabled\n" }, { "page_number": 148, "page_indices": { "start_index": 410242, "end_index": 411475 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 148 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.5 Power control registers (STM32F42xxx and STM32F43xxx)", 146 ], [ 3, "5.5.1 PWR power control register (PWR_CR) for STM32F42xxx and STM32F43xxx", 146 ] ], "page_content": "Power controller (PWR)\nRM0090\n148/1757\nRM0090 Rev 21\nBits 7:5 PLS[2:0]: PVD level selection\nThese bits are written by software to select the voltage threshold detected by the \nprogrammable voltage detector\n000: 2.0 V\n001: 2.1 V\n010: 2.3 V\n011: 2.5 V\n100: 2.6 V\n101: 2.7 V\n110: 2.8 V\n111: 2.9 V\nNote: Refer to the electrical characteristics of the datasheet for more details.\nBit 4 PVDE: Programmable voltage detector enable\nThis bit is set and cleared by software. \n0: PVD disabled\n1: PVD enabled\nBit 3 CSBF: Clear standby flag\nThis bit is always read as 0.\n0: No effect\n1: Clear the SBF Standby Flag (write).\nBit 2 CWUF: Clear wake-up flag\nThis bit is always read as 0.\n0: No effect\n1: Clear the WUF Wake-up Flag after 2 System clock cycles\nBit 1 PDDS: Power-down deepsleep\nThis bit is set and cleared by software. It works together with the LPDS bit. \n0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the \nLPDS bit.\n1: Enter Standby mode when the CPU enters deepsleep. \nBit 0 LPDS: Low-power deepsleep\nThis bit is set and cleared by software. It works together with the PDDS bit.\n0:Main voltage regulator ON during Stop mode\n1: Low-power voltage regulator ON during Stop mode\n" }, { "page_number": 149, "page_indices": { "start_index": 411475, "end_index": 413559 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 149 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.5 Power control registers (STM32F42xxx and STM32F43xxx)", 146 ], [ 3, "5.5.2 PWR power control/status register (PWR_CSR) for STM32F42xxx and STM32F43xxx", 149 ] ], "page_content": "RM0090 Rev 21\n149/1757\nRM0090\nPower controller (PWR)\n151\n5.5.2 \nPWR power control/status register (PWR_CSR)\nfor STM32F42xxx and STM32F43xxx\nAddress offset: 0x04\nReset value: 0x0000 0000 (not reset by wake-up from Standby mode)\nAdditional APB cycles are needed to read this register versus a standard APB read.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nUDRDY[1:0]\nODSWRDY\nODRDY\nrc_w1\nrc_w1\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes\nVOS\nRDY\nReserved\nBRE\nEWUP\nReserved.\nBRR\nPVDO\nSBF\nWUF\nr\nrw\nrw\nr\nr\nr\nr\nBits 31:20 Reserved, must be kept at reset value.\nBits 19:18 UDRDY[1:0]: Under-drive ready flag\nThese bits are set by hardware when MCU entered stop Under-drive mode and exited. \nWhen the under-drive mode is enabled, these bits are not set as long as the MCU has not \nentered stop mode yet. They are cleared by programming them to 1.\n00: Under-drive is disabled\n01: Reserved\n10: Reserved\n11:Under-drive mode is activated in Stop mode.\nBit 17 ODSWRDY: Over-drive mode switching ready\n0: Over-drive mode is not active.\n1: Over-drive mode is active on digital area on 1.2 V domain\nBit 16 ODRDY: Over-drive mode ready\n0: Over-drive mode not ready.\n1: Over-drive mode ready\nBit 14 VOSRDY: Regulator voltage scaling output selection ready bit\n0: Not ready \n1: Ready\nBits 13:10 Reserved, must be kept at reset value.\nBit 9 BRE: Backup regulator enable\nWhen set, the Backup regulator (used to maintain backup SRAM content in Standby and \nVBAT modes) is enabled. If BRE is reset, the backup regulator is switched off. The backup \nSRAM can still be used but its content is lost in the Standby and VBAT modes. Once set, the \napplication must wait that the Backup Regulator Ready flag (BRR) is set to indicate that the \ndata written into the RAM is maintained in the Standby and VBAT modes.\n0: Backup regulator disabled\n1: Backup regulator enabled\nNote: This bit is not reset when the device wakes up from Standby mode, by a system reset, \nor by a power reset.\nThe DBP bit of the PWR_CR register must be set before BRE can be written.\n" }, { "page_number": 150, "page_indices": { "start_index": 413559, "end_index": 415496 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 150 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.5 Power control registers (STM32F42xxx and STM32F43xxx)", 146 ], [ 3, "5.5.2 PWR power control/status register (PWR_CSR) for STM32F42xxx and STM32F43xxx", 149 ] ], "page_content": "Power controller (PWR)\nRM0090\n150/1757\nRM0090 Rev 21\nBit 8 EWUP: Enable WKUP pin\nThis bit is set and cleared by software.\n0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wake up \nthe device from Standby mode.\n1: WKUP pin is used for wake-up from Standby mode and forced in input pull down \nconfiguration (rising edge on WKUP pin wakes-up the system from Standby mode).\nNote: This bit is reset by a system reset.\nBits 7:4 Reserved, must be kept at reset value.\nBit 3 BRR: Backup regulator ready\nSet by hardware to indicate that the Backup Regulator is ready.\n0: Backup Regulator not ready\n1: Backup Regulator ready\nNote: This bit is not reset when the device wakes up from Standby mode or by a system reset \nor power reset.\nBit 2 PVDO: PVD output\nThis bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit. \n0: VDD is higher than the PVD threshold selected with the PLS[2:0] bits. \n1: VDD is lower than the PVD threshold selected with the PLS[2:0] bits.\nNote: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after \nStandby or reset until the PVDE bit is set.\nBit 1 SBF: Standby flag\nThis bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down \nreset) or by setting the CSBF bit in the PWR power control register (PWR_CR) for \nSTM32F405xx/07xx and STM32F415xx/17xx\n0: Device has not been in Standby mode\n1: Device has been in Standby mode\nBit 0 WUF: Wake-up flag\nThis bit is set by hardware and cleared either by a system reset or by setting the CWUF bit in \nthe PWR_CR register.\n0: No wake-up event occurred\n1: A wake-up event was received from the WKUP pin or from the RTC alarm (Alarm A or \nAlarm B), RTC Tamper event, RTC TimeStamp event or RTC Wake-up).\nNote: An additional wake-up event is detected if the WKUP pin is enabled (by setting the \nEWUP bit) when the WKUP pin level is already high.\n" }, { "page_number": 151, "page_indices": { "start_index": 415496, "end_index": 416635 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 151 }, "toc_details": [ [ 1, "5 Power controller (PWR)", 117 ], [ 2, "5.6 PWR register map", 151 ] ], "page_content": "RM0090 Rev 21\n151/1757\nRM0090\nPower controller (PWR)\n151\n5.6 \nPWR register map\nThe following table summarizes the PWR registers.\n \n \nRefer to Section 2.3: Memory map for the register boundary addresses.\nTable 32. PWR - register map and reset values for\nSTM32F405xx/07xx and STM32F415xx/17xx\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x000\nPWR_CR\nReserved\nVOS\nReserved\nFPDS\nDBP\nPLS[2:0]\nPVDE\nCSBF\nCWUF\nPDDS\nLPDS\nReset value\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x004\nPWR_CSR\nReserved\nVOSRDY\nReserved\nBRE\nEWUP\nReserved\nBRR\nPVDO\nSBF\nWUF\nReset value\n0\n0\n0\n0\n0\n0\n0\nTable 33. PWR - register map and reset values for STM32F42xxx and STM32F43xxx\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x000\nPWR_CR\nReserved\nUDEN[1:0]\nODSWEN\nODEN\nVOS[1:0]\nADCDC1\nReserved\nMRUDS\nLPUDS\nFPDS\nDBP\nPLS[2:0]\nPVDE\nCSBF\nCWUF\nPDDS\nLPDS\nReset value\n0\n0\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x004\nPWR_CSR\nReserved\nUDRDY[1:0]\nODSWRDY\nODRDY\nReserved\nVOSRDY\nReserved\nBRE\nEWUP\nReserved\nBRR\nPVDO\nSBF\nWUF\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n" }, { "page_number": 152, "page_indices": { "start_index": 416635, "end_index": 418697 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 152 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.1 Reset", 152 ], [ 3, "6.1.1 System reset", 152 ], [ 4, "Software reset", 152 ], [ 4, "Low-power management reset", 152 ], [ 3, "6.1.2 Power reset", 152 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n152/1757\nRM0090 Rev 21\n6 \nReset and clock control for \nSTM32F42xxx and STM32F43xxx (RCC)\n6.1 \nReset\nThere are three types of reset, defined as system Reset, power Reset and backup domain \nReset. \n6.1.1 \nSystem reset\nA system reset sets all registers to their reset values unless specified otherwise in the \nregister description (see Figure 10).\nA system reset is generated when one of the following events occurs:\n1.\nA low level on the NRST pin (external reset)\n2. \nWindow watchdog end of count condition (WWDG reset)\n3. \nIndependent watchdog end of count condition (IWDG reset)\n4. \nA software reset (SW reset) (see Software reset)\n5. \nLow-power management reset (see Low-power management reset)\nSoftware reset\nThe reset source can be identified by checking the reset flags in the RCC clock control & \nstatus register (RCC_CSR).\nThe SYSRESETREQ bit in Cortex®-M4 with FPU Application Interrupt and Reset Control \nRegister must be set to force a software reset on the device. Refer to the Cortex®-M4 with \nFPU technical reference manual for more details.\nLow-power management reset\nThere are two ways of generating a low-power management reset:\n1.\nReset generated when entering the Standby mode:\nThis type of reset is enabled by resetting the nRST_STDBY bit in the user option bytes. \nIn this case, whenever a Standby mode entry sequence is successfully executed, the \ndevice is reset instead of entering the Standby mode.\n2. \nReset when entering the Stop mode:\nThis type of reset is enabled by resetting the nRST_STOP bit in the user option bytes. \nIn this case, whenever a Stop mode entry sequence is successfully executed, the \ndevice is reset instead of entering the Stop mode.\n6.1.2 \nPower reset\nA power reset is generated when one of the following events occurs: \n1.\nPower-on/power-down reset (POR/PDR reset) or brownout (BOR) reset\n2. \nWhen exiting the Standby mode\nA power reset sets all registers to their reset values except the Backup domain (see \nFigure 10)\n" }, { "page_number": 153, "page_indices": { "start_index": 418697, "end_index": 420727 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 153 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.1 Reset", 152 ], [ 3, "6.1.3 Backup domain reset", 153 ], [ 2, "6.2 Clocks", 153 ] ], "page_content": "RM0090 Rev 21\n153/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nThese sources act on the NRST pin and it is always kept low during the delay phase. The \nRESET service routine vector is fixed at address 0x0000_0004 in the memory map.\nThe system reset signal provided to the device is output on the NRST pin. The pulse \ngenerator guarantees a minimum reset pulse duration of 20 µs for each internal reset \nsource. In case of an external reset, the reset pulse is generated while the NRST pin is \nasserted low.\nFigure 15. Simplified diagram of the reset circuit\nThe Backup domain has two specific resets that affect only the Backup domain (see \nFigure 10).\n6.1.3 \nBackup domain reset\nThe backup domain reset sets all RTC registers, the RCC_BDCR register, and the BRE bit \nof the PWR_CSR register to their reset values. The BKPSRAM is not affected by this reset. \nThe only way of resetting the BKPSRAM is through the Flash interface by requesting a \nprotection level change from 1 to 0.\nA backup domain reset is generated when one of the following events occurs:\n1.\nSoftware reset, triggered by setting the BDRST bit in the RCC Backup domain control \nregister (RCC_BDCR). \n2. \nVDD or VBAT power on, if both supplies have previously been powered off.\nNote:\nThe DBP bit of the PWR_CR register must be set to generate a backup domain reset.\n6.2 \nClocks\nThree different clock sources can be used to drive the system clock (SYSCLK):\n•\nHSI oscillator clock\n•\nHSE oscillator clock\n•\nMain PLL (PLL) clock\nThe devices have the two following secondary clock sources:\n•\n32 kHz low-speed internal RC (LSI RC) which drives the independent watchdog and, \noptionally, the RTC used for Auto-wakeup from the Stop/Standby mode.\n•\n32.768 kHz low-speed external crystal (LSE crystal) which optionally drives the RTC \nclock (RTCCLK)\nNRST\nRPU\nVDD/VDDA\nWWDG reset\nIWDG reset\nPulse\ngenerator\nPower reset\nExternal\nreset\n(min 20 μs)\nSystem reset\nFilter\nSoftware reset\nLow-power management reset\nai16095c\n" }, { "page_number": 154, "page_indices": { "start_index": 420727, "end_index": 422676 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 154 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.2 Clocks", 153 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n154/1757\nRM0090 Rev 21\nEach clock source can be switched on or off independently when it is not used, to optimize \npower consumption.\nFigure 16. Clock tree\n1.\nFor full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in \nthe device datasheet.\n2.\nWhen TIMPRE bit of the RCC_DCKCFGR register is reset, if APBx prescaler is 1, then TIMxCLK = PCLKx, otherwise \nTIMxCLK = 2x PCLKx. \n3.\nWhen TIMPRE bit in the RCC_DCKCFGR register is set, if APBx prescaler is 1,2 or 4, then TIMxCLK = HCLK, otherwise \nTIMxCLK = 4x PCLKx.\nMSv30434V3\nPLL\nMII_RMII_SEL in SYSCFG_PMC to Ethernet MAC\nLSE\nETH_MII_TX_CLK_MII\nOTG_HS_ULPI_CK\nPLLI2SCLK\nFCLK Cortex\nfree-running clock\nAPBx peripheral clocks\n48 MHz\nclocks\nUSBHS\nULPI clock\nEthernet\nPTP clock\nMCO1\nMCO2\nETH_MII_RX_CLK_MI\nI\nOSC32_IN\nOSC32_OUT\nTo Independent\nwatchdog\nLSE\nLSI\nto RTC\nRTCCLK\nRTCSEL[1:0]\nIWDGCLK\nOSC_IN\nOSC_OUT\nPLLCLK\nHSI\nHSI\nHSE\nSW\nSYSCLK\n180 MHz\nmax\nHCLK\nto AHB bus, core,\nmemory and DMA\n180 MHz max.\nto Cortex System timer\nClock \nenable \nPLL48CK\nI2S clocks\nAHB\nPRESC\n/1,2,..512\nMACRMIICLK\nMACTXCLK\nMACRXCLK\nWatchdog\nenable\nRTC\nenable\nPeripheral\nclock enable\n/2 to 31\nPLLI2S\nSYSCLK\nExt. clock \nI2SSRC\nHSE_RTC\nHSE\nI2S_CKIN\nPHY Ethernet\n25 to 50 MHz\nUSB2.0 PHY\n24 to 60 MHz\nPLLSAI\nPLLSAICLK\nPLLLCDCLK\nPLLSAICLK\nSAI1_A clock\nSAI1_B clock\nLCD-TFT \nclock\nLSI RC\n32 kHz\nLSE OSC\n32.768 kHz\n/1 to 5\n/1 to 5\n16 MHz\nHSI RC\n4-26 MHz\nHSE OSC\nVCO\nxN\n/P\n/Q\n/R\n/M\nVCO\nxN\n/P\n/Q\n/R\nDIV\nDIV\nDIV\nVCO\nxN\n/P\n/Q\n/R\n/2,20\nPeripheral\nclock enable\nPeripheral\nclock enable\nPeripheral\nclock enable\nPeripheral\nclock enable\nPeripheral\nclock enable\nPeripheral\nclock enable\nPeripheral\nclock enable\nPeripheral\nclock enable\nPeripheral\nclock enable\nAPBx\nPRESC\n/1,2,4,8,16\nAPBx timer clocks\nif (APBx presc = \n1x1 else x2\nPeripheral clock \nenable\nPeripheral clock \nenable\n/8\n" }, { "page_number": 155, "page_indices": { "start_index": 422676, "end_index": 425845 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 155 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.2 Clocks", 153 ] ], "page_content": "RM0090 Rev 21\n155/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nThe clock controller provides a high degree of flexibility to the application in the choice of the \nexternal crystal or the oscillator to run the core and peripherals at the highest frequency \nand, guarantee the appropriate frequency for peripherals that need a specific clock like \nEthernet, USB OTG FS and HS, I2S, SAI, LTDC, and SDIO.\nSeveral prescalers are used to configure the AHB frequency, the high-speed APB (APB2) \nand the low-speed APB (APB1) domains. The maximum frequency of the AHB domain is \n180 MHz. The maximum allowed frequency of the high-speed APB2 domain is 90 MHz. The \nmaximum allowed frequency of the low-speed APB1 domain is 45 MHz\nAll peripheral clocks are derived from the system clock (SYSCLK) except for:\n•\nThe USB OTG FS clock (48 MHz), the random analog generator (RNG) clock \n(≤48 MHz) and the SDIO clock (≤ 48 MHz) which are coming from a specific output of \nPLL (PLL48CLK)\n•\nI2S clock\nTo achieve high-quality audio performance, the I2S clock can be derived either from a \nspecific PLL (PLLI2S) or from an external clock mapped on the I2S_CKIN pin. For \nmore information about I2S clock frequency and precision, refer to Section 28.4.4: \nClock generator.\n•\nSAI1 clock\nThe SAI1 clock is generated from a specific PLL (PLLSAI or PLLI2S) or from an \nexternal clock mapped on the I2S_CKIN pin. \nThe PLLSAI can be used as clock source for SAI1 peripheral in case the PLLI2S is \nprogrammed to achieve another audio sampling frequency (49.152 MHz or \n11.2896 MHz), and the application requires both frequencies at the same time.\n•\nLTDC clock\nThe LTDC clock is generated from a specific PLL (PLLSAI).\n•\nThe USB OTG HS (60 MHz) clock which is provided from the external PHY\n•\nThe Ethernet MAC clocks (TX, RX and RMII) which are provided from the external \nPHY. For further information on the Ethernet configuration, please refer to \nSection 33.4.4: MII/RMII selection in the Ethernet peripheral description. When the \nEthernet is used, the AHB clock frequency must be at least 25 MHz.\nThe RCC feeds the external clock of the Cortex System Timer (SysTick) with the AHB clock \n(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock \n(HCLK), configurable in the SysTick control and status register.\nThe timer clock frequencies for STM32F42xxx and STM32F43xxx are automatically set by \nhardware. There are two cases depending on the value of TIMPRE bit in RCC_CFGR \nregister:\n•\nIf TIMPRE bit in RCC_DKCFGR register is reset:\nIf the APB prescaler is configured to a division factor of 1, the timer clock frequencies \n(TIMxCLK) are set to PCLKx. Otherwise, the timer clock frequencies are twice the \nfrequency of the APB domain to which the timers are connected: TIMxCLK = 2xPCLKx.\n•\nIf TIMPRE bit in RCC_DKCFGR register is set:\nIf the APB prescaler is configured to a division factor of 1, 2 or 4, the timer clock \nfrequencies (TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies is four \ntimes the frequency of the APB domain to which the timers are connected: TIMxCLK = \n4xPCLKx.\n" }, { "page_number": 156, "page_indices": { "start_index": 425845, "end_index": 427625 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 156 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.2 Clocks", 153 ], [ 3, "6.2.1 HSE clock", 156 ], [ 4, "External source (HSE bypass)", 156 ], [ 4, "External crystal/ceramic resonator (HSE crystal)", 156 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n156/1757\nRM0090 Rev 21\nFCLK acts as Cortex®-M4 with FPU free-running clock. For more details, refer to the \nCortex®-M4 with FPU technical reference manual.\n6.2.1 \nHSE clock\nThe high speed external clock signal (HSE) can be generated from two possible clock \nsources:\n•\nHSE external crystal/ceramic resonator\n•\nHSE external user clock\nThe resonator and the load capacitors have to be placed as close as possible to the \noscillator pins in order to minimize output distortion and startup stabilization time. The \nloading capacitance values must be adjusted according to the selected oscillator.\n \nExternal source (HSE bypass)\nIn this mode, an external clock source must be provided. You select this mode by setting the \nHSEBYP and HSEON bits in the RCC clock control register (RCC_CR). The external clock \nsignal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the \nOSC_OUT pin should be left HI-Z. See Figure 17.\nExternal crystal/ceramic resonator (HSE crystal)\nThe HSE has the advantage of producing a very accurate rate on the main clock.\nThe associated hardware configuration is shown in Figure 17. Refer to the electrical \ncharacteristics section of the datasheet for more details.\nThe HSERDY flag in the RCC clock control register (RCC_CR) indicates if the high-speed \nexternal oscillator is stable or not. At startup, the clock is not released until this bit is set by \nhardware. An interrupt can be generated if enabled in the RCC clock interrupt register \n(RCC_CIR).\nFigure 17. HSE/ LSE clock sources\nHardware configuration\nExternal clock\nCrystal/ceramic \nresonators\nOSC_OUT\nExternal\nsource\n(HI-Z)\nOSC_IN\nOSC_OUT\nLoad\ncapacitors\nCL2\nCL1\n" }, { "page_number": 157, "page_indices": { "start_index": 427625, "end_index": 430478 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 157 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.2 Clocks", 153 ], [ 3, "6.2.2 HSI clock", 157 ], [ 4, "Calibration", 157 ], [ 3, "6.2.3 PLL configuration", 157 ] ], "page_content": "RM0090 Rev 21\n157/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nThe HSE Crystal can be switched on and off using the HSEON bit in the RCC clock control \nregister (RCC_CR).\n6.2.2 \nHSI clock\nThe HSI clock signal is generated from an internal 16 MHz RC oscillator and can be used \ndirectly as a system clock, or used as PLL input.\nThe HSI RC oscillator has the advantage of providing a clock source at low cost (no external \ncomponents). It also has a faster startup time than the HSE crystal oscillator however, even \nwith calibration the frequency is less accurate than an external crystal oscillator or ceramic \nresonator. \nCalibration\nRC oscillator frequencies can vary from one chip to another due to manufacturing process \nvariations, this is why each device is factory calibrated by ST for 1% accuracy at TA= 25 °C.\nAfter reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the RCC clock \ncontrol register (RCC_CR). \nIf the application is subject to voltage or temperature variations this may affect the RC \noscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0] \nbits in the RCC clock control register (RCC_CR).\nThe HSIRDY flag in the RCC clock control register (RCC_CR) indicates if the HSI RC is \nstable or not. At startup, the HSI RC output clock is not released until this bit is set by \nhardware. \nThe HSI RC can be switched on and off using the HSION bit in the RCC clock control \nregister (RCC_CR).\nThe HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal \noscillator fails. Refer to Section 6.2.7: Clock security system (CSS) on page 159.\n6.2.3 \nPLL configuration\nThe STM32F4xx devices feature three PLLs:\n•\nA main PLL (PLL) clocked by the HSE or HSI oscillator and featuring two different \noutput clocks:\n–\nThe first output is used to generate the high speed system clock (up to 180 MHz)\n–\nThe second output is used to generate the clock for the USB OTG FS (48 MHz), \nthe random analog generator (≤ 48 MHz) and the SDIO (≤ 48 MHz). \n•\nTwo dedicated PLLs (PLLI2S and PLLSAI) used to generate an accurate clock to \nachieve high-quality audio performance on the I2S and SAI1 interfaces. PLLSAI is also \nused for the LCD-TFT clock.\nSince the main-PLL configuration parameters cannot be changed once PLL is enabled, it is \nrecommended to configure PLL before enabling it (selection of the HSI or HSE oscillator as \nPLL clock source, and configuration of division factors M, N, P, and Q). \nThe PLLI2S and PLLSAI use the same input clock as PLL (PLLM[5:0] and PLLSRC bits are \ncommon to both PLLs). However, the PLLI2S and PLLSAI have dedicated enable/disable \nand division factors (N and R) configuration bits. Once the PLLI2S and PLLSAI are enabled, \nthe configuration parameters cannot be changed.\n" }, { "page_number": 158, "page_indices": { "start_index": 430478, "end_index": 433394 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 158 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.2 Clocks", 153 ], [ 3, "6.2.4 LSE clock", 158 ], [ 4, "External source (LSE bypass)", 158 ], [ 3, "6.2.5 LSI clock", 158 ], [ 3, "6.2.6 System clock (SYSCLK) selection", 158 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n158/1757\nRM0090 Rev 21\nThe three PLLs are disabled by hardware when entering Stop and Standby modes, or when \nan HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock. RCC \nPLL configuration register (RCC_PLLCFGR),RCC clock configuration register \n(RCC_CFGR), and RCC Dedicated Clock Configuration Register (RCC_DCKCFGR) can be \nused to configure PLL, PLLI2S, and PLLSAI.\n6.2.4 \nLSE clock\nThe LSE clock is generated from a 32.768 kHz low-speed external crystal or ceramic \nresonator. It has the advantage providing a low-power but highly accurate clock source to \nthe real-time clock peripheral (RTC) for clock/calendar or other timing functions. \nThe LSE oscillator is switched on and off using the LSEON bit in RCC Backup domain \ncontrol register (RCC_BDCR). \nThe LSERDY flag in the RCC Backup domain control register (RCC_BDCR) indicates if the \nLSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released \nuntil this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock \ninterrupt register (RCC_CIR).\nExternal source (LSE bypass)\nIn this mode, an external clock source must be provided. It must have a frequency up to \n1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the RCC Backup \ndomain control register (RCC_BDCR). The external clock signal (square, sinus or triangle) \nwith ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be \nleft HI-Z. See Figure 17.\n6.2.5 \nLSI clock\nThe LSI RC acts as an low-power clock source that can be kept running in Stop and \nStandby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The \nclock frequency is around 32 kHz. For more details, refer to the electrical characteristics \nsection of the datasheets.\nThe LSI RC can be switched on and off using the LSION bit in the RCC clock control & \nstatus register (RCC_CSR).\nThe LSIRDY flag in the RCC clock control & status register (RCC_CSR) indicates if the low-\nspeed internal oscillator is stable or not. At startup, the clock is not released until this bit is \nset by hardware. An interrupt can be generated if enabled in the RCC clock interrupt register \n(RCC_CIR).\n6.2.6 \nSystem clock (SYSCLK) selection\nAfter a system reset, the HSI oscillator is selected as the system clock. When a clock source \nis used directly or through PLL as the system clock, it is not possible to stop it.\nA switch from one clock source to another occurs only if the target clock source is ready \n(clock stable after startup delay or PLL locked). If a clock source that is not yet ready is \nselected, the switch occurs when the clock source is ready. Status bits in the RCC clock \ncontrol register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently \nused as the system clock.\n" }, { "page_number": 159, "page_indices": { "start_index": 433394, "end_index": 436633 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 159 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.2 Clocks", 153 ], [ 3, "6.2.7 Clock security system (CSS)", 159 ], [ 3, "6.2.8 RTC/AWU clock", 159 ] ], "page_content": "RM0090 Rev 21\n159/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.2.7 \nClock security system (CSS)\nThe clock security system can be activated by software. In this case, the clock detector is \nenabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.\nIf a failure is detected on the HSE clock, this oscillator is automatically disabled, a clock \nfailure event is sent to the break inputs of advanced-control timers TIM1 and TIM8, and an \ninterrupt is generated to inform the software about the failure (clock security system \ninterrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the \nCortex®-M4 with FPU NMI (non-maskable interrupt) exception vector.\nNote:\nWhen the CSS is enabled, if the HSE clock happens to fail, the CSS generates an interrupt, \nwhich causes the automatic generation of an NMI. The NMI is executed indefinitely unless \nthe CSS interrupt pending bit is cleared. As a consequence, the application has to clear the \nCSS interrupt in the NMI ISR by setting the CSSC bit in the Clock interrupt register \n(RCC_CIR).\nIf the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that \nit is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is \ndetected, then the system clock switches to the HSI oscillator and the HSE oscillator is \ndisabled. \nIf the HSE oscillator clock was the clock source of PLL used as the system clock when the \nfailure occurred, PLL is also disabled. In this case, if the PLLI2S was enabled, it is also \ndisabled when the HSE fails. \n6.2.8 \nRTC/AWU clock\nOnce the RTCCLK clock source has been selected, the only possible way of modifying the \nselection is to reset the power domain.\nThe RTCCLK clock source can be either the HSE 1 MHz (HSE divided by a programmable \nprescaler), the LSE or the LSI clock. This is selected by programming the RTCSEL[1:0] bits \nin the RCC Backup domain control register (RCC_BDCR) and the RTCPRE[4:0] bits in RCC \nclock configuration register (RCC_CFGR). This selection cannot be modified without \nresetting the Backup domain.\nIf the LSE is selected as the RTC clock, the RTC operates normally if the backup or the \nsystem supply disappears. If the LSI is selected as the AWU clock, the AWU state is not \nguaranteed if the system supply disappears. If the HSE oscillator divided by a value \nbetween 2 and 31 is used as the RTC clock, the RTC state is not guaranteed if the backup \nor the system supply disappears.\nThe LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. As a \nconsequence:\n•\nIf LSE is selected as the RTC clock:\n–\nThe RTC continues to work even if the VDD supply is switched off, provided the \nVBAT supply is maintained. \n•\nIf LSI is selected as the Auto-wakeup unit (AWU) clock:\n–\nThe AWU state is not guaranteed if the VDD supply is powered off. Refer to \nSection 6.2.5: LSI clock on page 158 for more details on LSI calibration.\n•\nIf the HSE clock is used as the RTC clock:\n–\nThe RTC state is not guaranteed if the VDD supply is powered off or if the internal \nvoltage regulator is powered off (removing power from the 1.2 V domain).\n" }, { "page_number": 160, "page_indices": { "start_index": 436633, "end_index": 438782 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 160 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.2 Clocks", 153 ], [ 3, "6.2.9 Watchdog clock", 160 ], [ 3, "6.2.10 Clock-out capability", 160 ], [ 3, "6.2.11 Internal/external clock measurement using TIM5/TIM11", 160 ], [ 4, "Internal/external clock measurement using TIM5 channel4", 160 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n160/1757\nRM0090 Rev 21\nNote:\nTo read the RTC calendar register when the APB1 clock frequency is less than seven times \nthe RTC clock frequency (fAPB1 < 7xfRTCLCK), the software must read the calendar time and \ndate registers twice. The data are correct if the second read access to RTC_TR gives the \nsame result than the first one. Otherwise a third read access must be performed.\n6.2.9 \nWatchdog clock\nIf the independent watchdog (IWDG) is started by either hardware option or software \naccess, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator \ntemporization, the clock is provided to the IWDG.\n6.2.10 \nClock-out capability\nTwo microcontroller clock output (MCO) pins are available:\n•\nMCO1\nYou can output four different clock sources onto the MCO1 pin (PA8) using the \nconfigurable prescaler (from 1 to 5):\n–\nHSI clock\n–\nLSE clock\n–\nHSE clock\n–\nPLL clock\nThe desired clock source is selected using the MCO1PRE[2:0] and MCO1[1:0] bits in \nthe RCC clock configuration register (RCC_CFGR).\n•\nMCO2\nYou can output four different clock sources onto the MCO2 pin (PC9) using the \nconfigurable prescaler (from 1 to 5):\n–\nHSE clock\n–\nPLL clock\n–\nSystem clock (SYSCLK)\n–\nPLLI2S clock\nThe desired clock source is selected using the MCO2PRE[2:0] and MCO2 bits in the \nRCC clock configuration register (RCC_CFGR).\nFor the different MCO pins, the corresponding GPIO port has to be programmed in alternate \nfunction mode.\nThe selected clock to output onto MCO must not exceed 100 MHz (the maximum I/O \nspeed).\n6.2.11 \nInternal/external clock measurement using TIM5/TIM11\nIt is possible to indirectly measure the frequencies of all on-board clock source generators \nby means of the input capture of TIM5 channel4 and TIM11 channel1 as shown in Figure 18 \nand Figure 19.\nInternal/external clock measurement using TIM5 channel4\nTIM5 has an input multiplexer which allows choosing whether the input capture is triggered \nby the I/O or by an internal clock. This selection is performed through the TI4_RMP [1:0] bits \nin the TIM5_OR register.\n" }, { "page_number": 161, "page_indices": { "start_index": 438782, "end_index": 441620 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 161 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.2 Clocks", 153 ], [ 3, "6.2.11 Internal/external clock measurement using TIM5/TIM11", 160 ], [ 4, "Internal/external clock measurement using TIM11 channel1", 161 ] ], "page_content": "RM0090 Rev 21\n161/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nThe primary purpose of having the LSE connected to the channel4 input capture is to be \nable to precisely measure the HSI (this requires to have the HSI used as the system clock \nsource). The number of HSI clock counts between consecutive edges of the LSE signal \nprovides a measurement of the internal clock period. Taking advantage of the high precision \nof LSE crystals (typically a few tens of ppm) we can determine the internal clock frequency \nwith the same resolution, and trim the source to compensate for manufacturing-process \nand/or temperature- and voltage-related frequency deviations.\nThe HSI oscillator has dedicated, user-accessible calibration bits for this purpose.\nThe basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the \nprecision is therefore tightly linked to the ratio between the two clock sources. The greater \nthe ratio, the better the measurement.\nIt is also possible to measure the LSI frequency: this is useful for applications that do not \nhave a crystal. The ultralow-power LSI oscillator has a large manufacturing process \ndeviation: by measuring it versus the HSI clock source, it is possible to determine its \nfrequency with the precision of the HSI. The measured value can be used to have more \naccurate RTC time base timeouts (when LSI is used as the RTC clock source) and/or an \nIWDG timeout with an acceptable accuracy.\nUse the following procedure to measure the LSI frequency:\n1.\nEnable the TIM5 timer and configure channel4 in Input capture mode.\n2. \nThis bit is set the TI4_RMP bits in the TIM5_OR register to 0x01 to connect the LSI \nclock internally to TIM5 channel4 input capture for calibration purposes.\n3. \nMeasure the LSI clock frequency using the TIM5 capture/compare 4 event or interrupt.\n4. \nUse the measured LSI frequency to update the prescaler of the RTC depending on the \ndesired time base and/or to compute the IWDG timeout.\nFigure 18. Frequency measurement with TIM5 in Input capture mode\nInternal/external clock measurement using TIM11 channel1\nTIM11 has an input multiplexer which allows choosing whether the input capture is triggered \nby the I/O or by an internal clock. This selection is performed through TI1_RMP [1:0] bits in \nthe TIM11_OR register. The HSE_RTC clock (HSE divided by a programmable prescaler) is \nconnected to channel 1 input capture to have a rough indication of the external crystal \nfrequency. This requires that the HSI is the system clock source. This can be useful for \ninstance to ensure compliance with the IEC 60730/IEC 61335 standards which require to be \nable to determine harmonic or subharmonic frequencies (–50/+100% deviations). \nTIM5\nTI4\nTI4_RMP[1:0]\nGPIO\nRTC_WakeUp_IT\nLSE\nLSI\nai17741V2\n" }, { "page_number": 162, "page_indices": { "start_index": 441620, "end_index": 441853 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 162 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.2 Clocks", 153 ], [ 3, "6.2.11 Internal/external clock measurement using TIM5/TIM11", 160 ], [ 4, "Internal/external clock measurement using TIM11 channel1", 161 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n162/1757\nRM0090 Rev 21\nFigure 19. Frequency measurement with TIM11 in Input capture mode\nTIM11\nTI1\nTI1_RMP[1:0]\nGPIO\nHSE_RTC(1 MHz)\nai18433\n" }, { "page_number": 163, "page_indices": { "start_index": 441853, "end_index": 443583 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 163 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.1 RCC clock control register (RCC_CR)", 163 ] ], "page_content": "RM0090 Rev 21\n163/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3 \nRCC registers\nRefer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in \nregister descriptions.\n6.3.1 \nRCC clock control register (RCC_CR)\nAddress offset: 0x00\nReset value: 0x0000 XX83 where X is undefined.\nAccess: no wait state, word, half-word and byte access\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPLLSAI\nRDY\nPLLSAI\nON\nPLLI2S\nRDY\nPLLI2S\nON\nPLLRD\nY\nPLLON\nReserved\nCSS \nON\nHSE \nBYP\nHSE\nRDY\nHSE \nON\nr\nrw\nr\nrw\nr\nrw\nrw\nrw\nr\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nHSICAL[7:0]\nHSITRIM[4:0]\nRes.\nHSI \nRDY\nHSION\nr\nr\nr\nr\nr\nr\nr\nr\nrw\nrw\nrw\nrw\nrw\nr\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBit 29 PLLSAIRDY: PLLSAI clock ready flag\nSet by hardware to indicate that the PLLSAI is locked.\n0: PLLSAI unlocked\n1: PLLSAI locked\nBit 28 PLLSAION: PLLSAI enable\nSet and cleared by software to enable PLLSAI.\nCleared by hardware when entering Stop or Standby mode. \n0: PLLSAI OFF\n1: PLLSAI ON\nBit 27 PLLI2SRDY: PLLI2S clock ready flag\nSet by hardware to indicate that the PLLI2S is locked.\n0: PLLI2S unlocked\n1: PLLI2S locked\nBit 26 PLLI2SON: PLLI2S enable\nSet and cleared by software to enable PLLI2S.\nCleared by hardware when entering Stop or Standby mode. \n0: PLLI2S OFF\n1: PLLI2S ON\nBit 25 PLLRDY: Main PLL (PLL) clock ready flag\nSet by hardware to indicate that PLL is locked.\n0: PLL unlocked\n1: PLL locked\nBit 24 PLLON: Main PLL (PLL) enable\nSet and cleared by software to enable PLL.\nCleared by hardware when entering Stop or Standby mode. This bit cannot be reset if PLL \nclock is used as the system clock.\n0: PLL OFF\n1: PLL ON\n" }, { "page_number": 164, "page_indices": { "start_index": 443583, "end_index": 446100 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 164 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.1 RCC clock control register (RCC_CR)", 163 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n164/1757\nRM0090 Rev 21\nBits 23:20 Reserved, must be kept at reset value.\nBit 19 CSSON: Clock security system enable\nSet and cleared by software to enable the clock security system. When CSSON is set, the \nclock detector is enabled by hardware when the HSE oscillator is ready, and disabled by \nhardware if an oscillator failure is detected.\n0: Clock security system OFF (Clock detector OFF)\n1: Clock security system ON (Clock detector ON if HSE oscillator is stable, OFF if not)\nBit 18 HSEBYP: HSE clock bypass\nSet and cleared by software to bypass the oscillator with an external clock. The external \nclock must be enabled with the HSEON bit, to be used by the device.\nThe HSEBYP bit can be written only if the HSE oscillator is disabled.\n0: HSE oscillator not bypassed\n1: HSE oscillator bypassed with an external clock\nBit 17 HSERDY: HSE clock ready flag\nSet by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is cleared, \nHSERDY goes low after 6 HSE oscillator clock cycles.\n0: HSE oscillator not ready\n1: HSE oscillator ready\nBit 16 HSEON: HSE clock enable\nSet and cleared by software.\nCleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This \nbit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.\n0: HSE oscillator OFF\n1: HSE oscillator ON\nBits 15:8 HSICAL[7:0]: Internal high-speed clock calibration\nThese bits are initialized automatically at startup.\nBits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming\nThese bits provide an additional user-programmable trimming value that is added to the \nHSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature \nthat influence the frequency of the internal HSI RC.\nBit 2 Reserved, must be kept at reset value.\nBit 1 HSIRDY: Internal high-speed clock ready flag\nSet by hardware to indicate that the HSI oscillator is stable. After the HSION bit is cleared, \nHSIRDY goes low after 6 HSI clock cycles.\n0: HSI oscillator not ready\n1: HSI oscillator ready\nBit 0 HSION: Internal high-speed clock enable\nSet and cleared by software.\nSet by hardware to force the HSI oscillator ON when leaving the Stop or Standby mode or in \ncase of a failure of the HSE oscillator used directly or indirectly as the system clock. This bit \ncannot be cleared if the HSI is used directly or indirectly as the system clock.\n0: HSI oscillator OFF\n1: HSI oscillator ON\n" }, { "page_number": 165, "page_indices": { "start_index": 446100, "end_index": 448053 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 165 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.2 RCC PLL configuration register (RCC_PLLCFGR)", 165 ] ], "page_content": "RM0090 Rev 21\n165/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.2 \nRCC PLL configuration register (RCC_PLLCFGR)\nAddress offset: 0x04\nReset value: 0x2400 3010\nAccess: no wait state, word, half-word and byte access.\nThis register is used to configure the PLL clock outputs according to the formulas:\n•\nf(VCO clock) = f(PLL clock input) × (PLLN / PLLM)\n•\nf(PLL general clock output) = f(VCO clock) / PLLP\n•\nf(USB OTG FS, SDIO, RNG clock output) = f(VCO clock) / PLLQ\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPLLQ3\nPLLQ2\nPLLQ1\nPLLQ0\nReserv\ned\nPLLSR\nC\nReserved\nPLLP1\nPLLP0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserv\ned\nPLLN\nPLLM5\nPLLM4\nPLLM3\nPLLM2\nPLLM1\nPLLM0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBits 27:24 PLLQ: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator \nclocks\nSet and cleared by software to control the frequency of USB OTG FS clock, the random \nnumber generator clock and the SDIO clock. These bits should be written only if PLL is \ndisabled.\nCaution: The USB OTG FS requires a 48 MHz clock to work correctly. The SDIO and the \nrandom number generator need a frequency lower than or equal to 48 MHz to work \ncorrectly.\nUSB OTG FS clock frequency = VCO frequency / PLLQ with 2 ≤ PLLQ ≤ 15\n0000: PLLQ = 0, wrong configuration\n0001: PLLQ = 1, wrong configuration\n0010: PLLQ = 2\n0011: PLLQ = 3\n0100: PLLQ = 4\n...\n1111: PLLQ = 15\nBit 23 Reserved, must be kept at reset value.\nBit 22 PLLSRC: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source\nSet and cleared by software to select PLL and PLLI2S clock source. This bit can be written \nonly when PLL and PLLI2S are disabled.\n0: HSI clock selected as PLL and PLLI2S clock entry\n1: HSE oscillator clock selected as PLL and PLLI2S clock entry\nBits 21:18 Reserved, must be kept at reset value.\n" }, { "page_number": 166, "page_indices": { "start_index": 448053, "end_index": 450212 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 166 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.2 RCC PLL configuration register (RCC_PLLCFGR)", 165 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n166/1757\nRM0090 Rev 21\nBits 17:16 PLLP: Main PLL (PLL) division factor for main system clock\nSet and cleared by software to control the frequency of the general PLL output clock. These \nbits can be written only if PLL is disabled.\nCaution: The software has to set these bits correctly not to exceed 180 MHz on this domain.\nPLL output clock frequency = VCO frequency / PLLP with PLLP = 2, 4, 6, or 8\n00: PLLP = 2\n01: PLLP = 4\n10: PLLP = 6\n11: PLLP = 8\nBits 14:6 PLLN: Main PLL (PLL) multiplication factor for VCO\nSet and cleared by software to control the multiplication factor of the VCO. These bits can \nbe written only when PLL is disabled. Only half-word and word accesses are allowed to \nwrite these bits.\nCaution: The software has to set these bits correctly to ensure that the VCO output \nfrequency is between 100 and 432 MHz. \nVCO output frequency = VCO input frequency × PLLN with 50 ≤ PLLN ≤ 432\n000000000: PLLN = 0, wrong configuration \n000000001: PLLN = 1, wrong configuration\n...\n000110010: PLLN = 50\n...\n001100011: PLLN = 99\n001100100: PLLN = 100\n... \n110110000: PLLN = 432\n110110001: PLLN = 433, wrong configuration\n... \n111111111: PLLN = 511, wrong configuration \nNote: Multiplication factors ranging from 50 and 99 are possible for VCO input frequency \nhigher than 1 MHz. However care must be taken that the minimum VCO output \nfrequency respects the value specified above. \nBits 5:0 PLLM: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock\nSet and cleared by software to divide the PLL and PLLI2S input clock before the VCO. \nThese bits can be written only when the PLL and PLLI2S are disabled.\nCaution: The software has to set these bits correctly to ensure that the VCO input frequency \nranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit \nPLL jitter. \nVCO input frequency = PLL input clock frequency / PLLM with 2 ≤ PLLM ≤ 63\n000000: PLLM = 0, wrong configuration\n000001: PLLM = 1, wrong configuration\n000010: PLLM = 2\n000011: PLLM = 3\n000100: PLLM = 4\n...\n111110: PLLM = 62\n111111: PLLM = 63\n" }, { "page_number": 167, "page_indices": { "start_index": 450212, "end_index": 452388 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 167 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.3 RCC clock configuration register (RCC_CFGR)", 167 ] ], "page_content": "RM0090 Rev 21\n167/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.3 \nRCC clock configuration register (RCC_CFGR)\nAddress offset: 0x08\nReset value: 0x0000 0000\nAccess: 0 ≤ wait state ≤ 2, word, half-word and byte access\n1 or 2 wait states inserted only if the access occurs during a clock source switch.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMCO2\nMCO2 PRE[2:0]\nMCO1 PRE[2:0]\nI2SSC\nR\nMCO1\nRTCPRE[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPPRE2[2:0]\nPPRE1[2:0]\nReserved\nHPRE[3:0]\nSWS1\nSWS0\nSW1\nSW0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nr\nr\nrw\nrw\nBits 31:30 MCO2[1:0]: Microcontroller clock output 2\nSet and cleared by software. Clock source selection may generate glitches on MCO2. It is \nhighly recommended to configure these bits only after reset before enabling the external \noscillators and the PLLs.\n00: System clock (SYSCLK) selected\n01: PLLI2S clock selected\n10: HSE oscillator clock selected\n11: PLL clock selected\nBits 27:29 MCO2PRE: MCO2 prescaler\nSet and cleared by software to configure the prescaler of the MCO2. Modification of this \nprescaler may generate glitches on MCO2. It is highly recommended to change this \nprescaler only after reset before enabling the external oscillators and the PLLs.\n0xx: no division\n100: division by 2\n101: division by 3\n110: division by 4\n111: division by 5\nBits 24:26 MCO1PRE: MCO1 prescaler\nSet and cleared by software to configure the prescaler of the MCO1. Modification of this \nprescaler may generate glitches on MCO1. It is highly recommended to change this \nprescaler only after reset before enabling the external oscillators and the PLL.\n0xx: no division\n100: division by 2\n101: division by 3\n110: division by 4\n111: division by 5\nBit 23 I2SSRC: I2S clock selection\nSet and cleared by software. This bit allows to select the I2S clock source between the \nPLLI2S clock and the external clock. It is highly recommended to change this bit only after \nreset and before enabling the I2S module.\n0: PLLI2S clock used as I2S clock source\n1: External clock mapped on the I2S_CKIN pin used as I2S clock source\n" }, { "page_number": 168, "page_indices": { "start_index": 452388, "end_index": 454265 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 168 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.3 RCC clock configuration register (RCC_CFGR)", 167 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n168/1757\nRM0090 Rev 21\nBits 22:21 MCO1: Microcontroller clock output 1\nSet and cleared by software. Clock source selection may generate glitches on MCO1. It is \nhighly recommended to configure these bits only after reset before enabling the external \noscillators and PLL.\n00: HSI clock selected\n01: LSE oscillator selected\n10: HSE oscillator clock selected\n11: PLL clock selected\nBits 20:16 RTCPRE: HSE division factor for RTC clock\nSet and cleared by software to divide the HSE clock input clock to generate a 1 MHz clock \nfor RTC.\nCaution: The software has to set these bits correctly to ensure that the clock supplied to the \nRTC is 1 MHz. These bits must be configured if needed before selecting the RTC \nclock source.\n00000: no clock\n00001: no clock\n00010: HSE/2\n00011: HSE/3\n00100: HSE/4\n...\n11110: HSE/30\n11111: HSE/31\nBits 15:13 PPRE2: APB high-speed prescaler (APB2)\nSet and cleared by software to control APB high-speed clock division factor.\nCaution: The software has to set these bits correctly not to exceed 90 MHz on this domain. \nThe clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after \nPPRE2 write.\n0xx: AHB clock not divided\n100: AHB clock divided by 2\n101: AHB clock divided by 4\n110: AHB clock divided by 8\n111: AHB clock divided by 16\nBits 12:10 PPRE1: APB Low speed prescaler (APB1)\nSet and cleared by software to control APB low-speed clock division factor.\nCaution: The software has to set these bits correctly not to exceed 45 MHz on this domain. \nThe clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after \nPPRE1 write.\n0xx: AHB clock not divided\n100: AHB clock divided by 2\n101: AHB clock divided by 4\n110: AHB clock divided by 8\n111: AHB clock divided by 16\nBits 9:8 Reserved, must be kept at reset value.\n" }, { "page_number": 169, "page_indices": { "start_index": 454265, "end_index": 456197 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 169 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.4 RCC clock interrupt register (RCC_CIR)", 169 ] ], "page_content": "RM0090 Rev 21\n169/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.4 \nRCC clock interrupt register (RCC_CIR)\nAddress offset: 0x0C\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n \nBits 7:4 HPRE: AHB prescaler\nSet and cleared by software to control AHB clock division factor.\nCaution: The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after \nHPRE write.\nCaution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.\n0xxx: system clock not divided\n1000: system clock divided by 2\n1001: system clock divided by 4\n1010: system clock divided by 8\n1011: system clock divided by 16\n1100: system clock divided by 64\n1101: system clock divided by 128\n1110: system clock divided by 256\n1111: system clock divided by 512\nBits 3:2 SWS: System clock switch status\nSet and cleared by hardware to indicate which clock source is used as the system clock.\n00: HSI oscillator used as the system clock\n01: HSE oscillator used as the system clock\n10: PLL used as the system clock\n11: not applicable\nBits 1:0 SW: System clock switch\nSet and cleared by software to select the system clock source.\nSet by hardware to force the HSI selection when leaving the Stop or Standby mode or in \ncase of failure of the HSE oscillator used directly or indirectly as the system clock.\n00: HSI oscillator selected as system clock\n01: HSE oscillator selected as system clock\n10: PLL selected as system clock\n11: not allowed\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nCSSC\nPLLSAI\nRDYC\nPLLI2S \nRDYC\nPLL \nRDYC\nHSE \nRDYC\nHSI \nRDYC\nLSE \nRDYC\nLSI \nRDYC\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserv\ned\nPLLSAI\nRDYIE\nPLLI2S \nRDYIE\nPLL \nRDYIE\nHSE \nRDYIE\nHSI \nRDYIE\nLSE \nRDYIE\nLSI \nRDYIE\nCSSF\nPLLSAI\nRDYF\nPLLI2S\nRDYF\nPLL \nRDYF\nHSE \nRDYF\nHSI \nRDYF\nLSE \nRDYF\nLSI \nRDYF\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nr\nr\nr\nr\nr\nr\nr\nr\n" }, { "page_number": 170, "page_indices": { "start_index": 456197, "end_index": 457968 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 170 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.4 RCC clock interrupt register (RCC_CIR)", 169 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n170/1757\nRM0090 Rev 21\n \nBits 31:24 Reserved, must be kept at reset value.\nBit 23 CSSC: Clock security system interrupt clear\nThis bit is set by software to clear the CSSF flag.\n0: No effect\n1: Clear CSSF flag\nBit 22 PLLSAIRDYC: PLLSAI Ready Interrupt Clear\nThis bit is set by software to clear PLLSAIRDYF flag. It is reset by hardware when the \nPLLSAIRDYF is cleared.\n0: PLLSAIRDYF not cleared\n1: PLLSAIRDYF cleared\nBit 21 PLLI2SRDYC: PLLI2S ready interrupt clear\nThis bit is set by software to clear the PLLI2SRDYF flag.\n0: No effect\n1: PLLI2SRDYF cleared\nBit 20 PLLRDYC: Main PLL(PLL) ready interrupt clear\nThis bit is set by software to clear the PLLRDYF flag.\n0: No effect\n1: PLLRDYF cleared\nBit 19 HSERDYC: HSE ready interrupt clear\nThis bit is set by software to clear the HSERDYF flag.\n0: No effect\n1: HSERDYF cleared\nBit 18 HSIRDYC: HSI ready interrupt clear\nThis bit is set software to clear the HSIRDYF flag.\n0: No effect\n1: HSIRDYF cleared\nBit 17 LSERDYC: LSE ready interrupt clear\nThis bit is set by software to clear the LSERDYF flag.\n0: No effect\n1: LSERDYF cleared\nBit 16 LSIRDYC: LSI ready interrupt clear\nThis bit is set by software to clear the LSIRDYF flag.\n0: No effect\n1: LSIRDYF cleared\nBit 15 Reserved, must be kept at reset value.\nBit 14 PLLSAIRDYIE: PLLSAI Ready Interrupt Enable\nThis bit is set and reset by software to enable/disable interrupt caused by PLLSAI lock.\n0: PLLSAI lock interrupt disabled\n1: PLLSAI lock interrupt enabled\nBit 13 PLLI2SRDYIE: PLLI2S ready interrupt enable\nThis bit is set and cleared by software to enable/disable interrupt caused by PLLI2S lock.\n0: PLLI2S lock interrupt disabled\n1: PLLI2S lock interrupt enabled\n" }, { "page_number": 171, "page_indices": { "start_index": 457968, "end_index": 460276 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 171 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.4 RCC clock interrupt register (RCC_CIR)", 169 ] ], "page_content": "RM0090 Rev 21\n171/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable\nThis bit is set and cleared by software to enable/disable interrupt caused by PLL lock.\n0: PLL lock interrupt disabled\n1: PLL lock interrupt enabled\nBit 11 HSERDYIE: HSE ready interrupt enable\nThis bit is set and cleared by software to enable/disable interrupt caused by the HSE \noscillator stabilization.\n0: HSE ready interrupt disabled\n1: HSE ready interrupt enabled\nBit 10 HSIRDYIE: HSI ready interrupt enable\nThis bit is set and cleared by software to enable/disable interrupt caused by the HSI \noscillator stabilization.\n0: HSI ready interrupt disabled\n1: HSI ready interrupt enabled\nBit 9 LSERDYIE: LSE ready interrupt enable\nThis bit is set and cleared by software to enable/disable interrupt caused by the LSE \noscillator stabilization.\n0: LSE ready interrupt disabled\n1: LSE ready interrupt enabled\nBit 8 LSIRDYIE: LSI ready interrupt enable\nThis bit is set and cleared by software to enable/disable interrupt caused by LSI oscillator \nstabilization.\n0: LSI ready interrupt disabled\n1: LSI ready interrupt enabled\nBit 7 CSSF: Clock security system interrupt flag\nThis bit is set by hardware when a failure is detected in the HSE oscillator.\nIt is cleared by software by setting the CSSC bit.\n0: No clock security interrupt caused by HSE clock failure\n1: Clock security interrupt caused by HSE clock failure\nBit 6 PLLSAIRDYF: PLLSAI Ready Interrupt flag\nThis bit is set by hardware when the PLLSAI is locked and PLLSAIRDYIE is set.\nIt is cleared by software by setting the PLLSAIRDYC bit.\n0: No clock ready interrupt caused by PLLSAI lock\n1: Clock ready interrupt caused by PLLSAI lock\nBit 5 PLLI2SRDYF: PLLI2S ready interrupt flag\nThis bit is set by hardware when the PLLI2S is locked and PLLI2SRDYIE is set.\nIt is cleared by software by setting the PLLRI2SDYC bit.\n0: No clock ready interrupt caused by PLLI2S lock\n1: Clock ready interrupt caused by PLLI2S lock\nBit 4 PLLRDYF: Main PLL (PLL) ready interrupt flag\nThis bit is set by hardware when PLL is locked and PLLRDYIE is set.\nIt is cleared by software setting the PLLRDYC bit.\n0: No clock ready interrupt caused by PLL lock\n1: Clock ready interrupt caused by PLL lock\n" }, { "page_number": 172, "page_indices": { "start_index": 460276, "end_index": 462391 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 172 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)", 172 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n172/1757\nRM0090 Rev 21\n6.3.5 \nRCC AHB1 peripheral reset register (RCC_AHB1RSTR)\nAddress offset: 0x10\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \nBit 3 HSERDYF: HSE ready interrupt flag\nThis bit is set by hardware when External High Speed clock becomes stable and \nHSERDYIE is set.\nIt is cleared by software by setting the HSERDYC bit.\n0: No clock ready interrupt caused by the HSE oscillator\n1: Clock ready interrupt caused by the HSE oscillator\nBit 2 HSIRDYF: HSI ready interrupt flag\nThis bit is set by hardware when the Internal High Speed clock becomes stable and \nHSIRDYIE is set.\nIt is cleared by software by setting the HSIRDYC bit.\n0: No clock ready interrupt caused by the HSI oscillator\n1: Clock ready interrupt caused by the HSI oscillator\nBit 1 LSERDYF: LSE ready interrupt flag\nThis bit is set by hardware when the External Low Speed clock becomes stable and \nLSERDYIE is set.\nIt is cleared by software by setting the LSERDYC bit.\n0: No clock ready interrupt caused by the LSE oscillator\n1: Clock ready interrupt caused by the LSE oscillator\nBit 0 LSIRDYF: LSI ready interrupt flag\nThis bit is set by hardware when the internal low speed clock becomes stable and \nLSIRDYIE is set.\nIt is cleared by software by setting the LSIRDYC bit.\n0: No clock ready interrupt caused by the LSI oscillator\n1: Clock ready interrupt caused by the LSI oscillator\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nOTGH\nS\nRST\nReserved\nETHMAC\nRST\nRes.\nDMA2D\nRST\nDMA2\nRST\nDMA1\nRST\nReserved\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCRCR\nST\nRes.\nGPIOK\nRST\nGPIOJ\nRST\nGPIOI\nRST\nGPIOH\nRST\nGPIOGG\nRST\nGPIOF\nRST\nGPIOE\nRST\nGPIOD\nRST\nGPIOC\nRST\nGPIOB\nRST\nGPIOA\nRST\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBit 29 OTGHSRST: USB OTG HS module reset\nThis bit is set and cleared by software.\n0: does not reset the USB OTG HS module\n1: resets the USB OTG HS module\nBits 28:26 Reserved, must be kept at reset value.\n" }, { "page_number": 173, "page_indices": { "start_index": 462391, "end_index": 463813 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 173 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)", 172 ] ], "page_content": "RM0090 Rev 21\n173/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 25 ETHMACRST: Ethernet MAC reset\nThis bit is set and cleared by software.\n0: does not reset Ethernet MAC\n1: resets Ethernet MAC\nBit 24 Reserved, must be kept at reset value.\nBit 23 DMA2DRST: DMA2D reset\nThis bit is set and reset by software.\n0: does not reset DMA2D\n1: resets DMA2D\nBit 22 DMA2RST: DMA2 reset\nThis bit is set and cleared by software.\n0: does not reset DMA2\n1: resets DMA2\nBit 21 DMA1RST: DMA2 reset\nThis bit is set and cleared by software.\n0: does not reset DMA2\n1: resets DMA2\nBits 20:13 Reserved, must be kept at reset value.\nBit 12 CRCRST: CRC reset\nThis bit is set and cleared by software.\n0: does not reset CRC\n1: resets CRC\nBit 11 Reserved, must be kept at reset value.\nBit 10 GPIOKRST: IO port K reset\nThis bit is set and cleared by software.\n0: does not reset IO port K\n1: resets IO port K\nBit 9 GPIOJRST: IO port J reset\nThis bit is set and cleared by software.\n0: does not reset IO port J\n1: resets IO port J\nBit 8 GPIOIRST: IO port I reset\nThis bit is set and cleared by software.\n0: does not reset IO port I\n1: resets IO port I\nBit 7 GPIOHRST: IO port H reset\nThis bit is set and cleared by software.\n0: does not reset IO port H\n1: resets IO port H\nBit 6 GPIOGRST: IO port G reset\nThis bit is set and cleared by software.\n0: does not reset IO port G\n1: resets IO port G\n" }, { "page_number": 174, "page_indices": { "start_index": 463813, "end_index": 464654 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 174 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)", 172 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n174/1757\nRM0090 Rev 21\nBit 5 GPIOFRST: IO port F reset\nThis bit is set and cleared by software.\n0: does not reset IO port F\n1: resets IO port F\nBit 4 GPIOERST: IO port E reset\nThis bit is set and cleared by software.\n0: does not reset IO port E\n1: resets IO port E\nBit 3 GPIODRST: IO port D reset\nThis bit is set and cleared by software.\n0: does not reset IO port D\n1: resets IO port D\nBit 2 GPIOCRST: IO port C reset\nThis bit is set and cleared by software.\n0: does not reset IO port C\n1: resets IO port C\nBit 1 GPIOBRST: IO port B reset\nThis bit is set and cleared by software.\n0: does not reset IO port B\n1:resets IO port B\nBit 0 GPIOARST: IO port A reset\nThis bit is set and cleared by software.\n0: does not reset IO port A\n1: resets IO port A\n" }, { "page_number": 175, "page_indices": { "start_index": 464654, "end_index": 465950 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 175 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR)", 175 ] ], "page_content": "RM0090 Rev 21\n175/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.6 \nRCC AHB2 peripheral reset register (RCC_AHB2RSTR)\nAddress offset: 0x14\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOTGFS\nRST\nRNG\nRST\nHASH\nRST\nCRYP\nRST\nReserved\nDCMI\nRST\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBit 7 OTGFSRST: USB OTG FS module reset\nSet and cleared by software.\n0: does not reset the USB OTG FS module\n1: resets the USB OTG FS module\nBit 6 RNGRST: Random number generator module reset\nSet and cleared by software.\n0: does not reset the random number generator module\n1: resets the random number generator module\nBit 5 HASHRST: Hash module reset\nSet and cleared by software.\n0: does not reset the HASH module\n1: resets the HASH module\nBit 4 CRYPRST: Cryptographic module reset\nSet and cleared by software.\n0: does not reset the cryptographic module\n1: resets the cryptographic module\nBits 3:1 Reserved, must be kept at reset value.\nBit 0 DCMIRST: Camera interface reset\nSet and cleared by software.\n0: does not reset the Camera interface\n1: resets the Camera interface \n" }, { "page_number": 176, "page_indices": { "start_index": 465950, "end_index": 467169 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 176 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.7 RCC AHB3 peripheral reset register (RCC_AHB3RSTR)", 176 ], [ 3, "6.3.8 RCC APB1 peripheral reset register (RCC_APB1RSTR)", 176 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n176/1757\nRM0090 Rev 21\n6.3.7 \nRCC AHB3 peripheral reset register (RCC_AHB3RSTR)\nAddress offset: 0x18\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n6.3.8 \nRCC APB1 peripheral reset register (RCC_APB1RSTR)\nAddress offset: 0x20\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFMCRST\nrw\nBits 31:1 Reserved, must be kept at reset value.\nBit 0 FMCRST: Flexible memory controller module reset\nSet and cleared by software.\n0: does not reset the FMC module\n1: resets the FMC module\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nUART8R\nST\nUART7R\nST\nDACRST\nPWR\nRST\nReser-\nved\nCAN2\nRST\nCAN1\nRST\nReser-\nved\nI2C3\nRST\nI2C2\nRST\nI2C1\nRST\nUART5 \nRST\nUART4\nRST\nUART3\nRST\nUART2\nRST\nReser-\nved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSPI3\nRST\nSPI2\nRST\nReserved\nWWDG\nRST\nReserved\nTIM14\nRST\nTIM13\nRST\nTIM12\nRST\nTIM7\nRST\nTIM6\nRST\nTIM5\nRST\nTIM4\nRST\nTIM3\nRST\nTIM2\nRST\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 177, "page_indices": { "start_index": 467169, "end_index": 468498 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 177 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.8 RCC APB1 peripheral reset register (RCC_APB1RSTR)", 176 ] ], "page_content": "RM0090 Rev 21\n177/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 31 UART8RST: UART8 reset\nSet and cleared by software.\n0: does not reset UART8\n1: resets UART8\nBit 30 UART7RST: UART7 reset\nSet and cleared by software.\n0: does not reset UART7\n1: resets UART7\nBit 29 DACRST: DAC reset\nSet and cleared by software.\n0: does not reset the DAC interface\n1: resets the DAC interface\nBit 28 PWRRST: Power interface reset\nSet and cleared by software.\n0: does not reset the power interface\n1: resets the power interface\nBit 27 Reserved, must be kept at reset value.\nBit 26 CAN2RST: CAN2 reset\nSet and cleared by software.\n0: does not reset CAN2\n1: resets CAN2\nBit 25 CAN1RST: CAN1 reset\nSet and cleared by software.\n0: does not reset CAN1\n1: resets CAN1\nBit 24 Reserved, must be kept at reset value.\nBit 23 I2C3RST: I2C3 reset\nSet and cleared by software.\n0: does not reset I2C3\n1: resets I2C3\nBit 22 I2C2RST: I2C2 reset\nSet and cleared by software.\n0: does not reset I2C2\n1: resets I2C2\nBit 21 I2C1RST: I2C1 reset\nSet and cleared by software.\n0: does not reset I2C1\n1: resets I2C1\nBit 20 UART5RST: UART5 reset\nSet and cleared by software.\n0: does not reset UART5\n1: resets UART5\nBit 19 UART4RST: USART4 reset\nSet and cleared by software.\n0: does not reset UART4\n1: resets UART4\n" }, { "page_number": 178, "page_indices": { "start_index": 468498, "end_index": 469763 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 178 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.8 RCC APB1 peripheral reset register (RCC_APB1RSTR)", 176 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n178/1757\nRM0090 Rev 21\nBit 18 USART3RST: USART3 reset\nSet and cleared by software.\n0: does not reset USART3\n1: resets USART3\nBit 17 USART2RST: USART2 reset\nSet and cleared by software.\n0: does not reset USART2\n1: resets USART2\nBit 16 Reserved, must be kept at reset value.\nBit 15 SPI3RST: SPI3 reset\nSet and cleared by software.\n0: does not reset SPI3\n1: resets SPI3\nBit 14 SPI2RST: SPI2 reset\nSet and cleared by software.\n0: does not reset SPI2\n1: resets SPI2\nBits 13:12 Reserved, must be kept at reset value.\nBit 11 WWDGRST: Window watchdog reset\nSet and cleared by software.\n0: does not reset the window watchdog\n1: resets the window watchdog\nBits 10:9 Reserved, must be kept at reset value.\nBit 8 TIM14RST: TIM14 reset\nSet and cleared by software.\n0: does not reset TIM14\n1: resets TIM14\nBit 7 TIM13RST: TIM13 reset\nSet and cleared by software.\n0: does not reset TIM13\n1: resets TIM13\nBit 6 TIM12RST: TIM12 reset\nSet and cleared by software.\n0: does not reset TIM12\n1: resets TIM12\nBit 5 TIM7RST: TIM7 reset\nSet and cleared by software.\n0: does not reset TIM7\n1: resets TIM7\nBit 4 TIM6RST: TIM6 reset\nSet and cleared by software.\n0: does not reset TIM6\n1: resets TIM6\n" }, { "page_number": 179, "page_indices": { "start_index": 469763, "end_index": 470255 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 179 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.8 RCC APB1 peripheral reset register (RCC_APB1RSTR)", 176 ] ], "page_content": "RM0090 Rev 21\n179/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 3 TIM5RST: TIM5 reset\nSet and cleared by software.\n0: does not reset TIM5\n1: resets TIM5\nBit 2 TIM4RST: TIM4 reset\nSet and cleared by software.\n0: does not reset TIM4\n1: resets TIM4\nBit 1 TIM3RST: TIM3 reset\nSet and cleared by software.\n0: does not reset TIM3\n1: resets TIM3\nBit 0 TIM2RST: TIM2 reset\nSet and cleared by software.\n0: does not reset TIM2\n1: resets TIM2\n" }, { "page_number": 180, "page_indices": { "start_index": 470255, "end_index": 471797 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 180 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR)", 180 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n180/1757\nRM0090 Rev 21\n6.3.9 \nRCC APB2 peripheral reset register (RCC_APB2RSTR)\nAddress offset: 0x24\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nLTD\nCRST\nReserved\nSAI1\nRST\nSPI6\nRST\nSPI5\nRST\nRes.\nTIM11\nRST\nTIM10\nRST\nTIM9\nRST\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReser-\nved\nSYSCF\nG RST\nSPI4\nRST\nSPI1\nRST\nSDIO\nRST\nReserved\nADC\nRST\nReserved\nUSART\n6\nRST\nUSART\n1\nRST\nReserved\nTIM8\nRST\nTIM1\nRST\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:27 Reserved, must be kept at reset value.\nBit 26 LTDCRST: LTDC reset\nThis bit is set and reset by software.\n0: does not reset LCD-TFT\n1: resets LCD-TFT\nBits 27:23 Reserved, must be kept at reset value.\nBit 22 SAI1RST: SAI1 reset\nThis bit is set and reset by software.\n0: does not reset SAI1\n1: resets SAI1\nBit 21 SPI6RST: SPI6 reset\nThis bit is set and cleared by software.\n0: does not reset SPI6\n1: resets SPI6\nBit 20 SPI5RST: SPI5 reset\nThis bit is set and cleared by software.\n0: does not reset SPI5\n1: resets SPI5\nBit 19 Reserved, must be kept at reset value.\nBit 18 TIM11RST: TIM11 reset\nThis bit is set and cleared by software.\n0: does not reset TIM11\n1: resets TIM14\nBit 17 TIM10RST: TIM10 reset\nThis bit is set and cleared by software.\n0: does not reset TIM10\n1: resets TIM10\nBit 16 TIM9RST: TIM9 reset\nThis bit is set and cleared by software.\n0: does not reset TIM9\n1: resets TIM9\n" }, { "page_number": 181, "page_indices": { "start_index": 471797, "end_index": 473241 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 181 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR)", 180 ] ], "page_content": "RM0090 Rev 21\n181/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 15 Reserved, must be kept at reset value.\nBit 14 SYSCFGRST: System configuration controller reset\nThis bit is set and cleared by software.\n0: does not reset the System configuration controller\n1: resets the System configuration controller\nBit 13 SPI4RST: SPI4 reset\nThis bit is set and cleared by software.\n0: does not reset SPI4\n1: resets SPI4\nBit 12 SPI1RST: SPI1 reset\nThis bit is set and cleared by software.\n0: does not reset SPI1\n1: resets SPI1\nBit 11 SDIORST: SDIO reset\nThis bit is set and cleared by software.\n0: does not reset the SDIO module\n1: resets the SDIO module\nBits 10:9 Reserved, must be kept at reset value.\nBit 8 ADCRST: ADC interface reset (common to all ADCs)\nThis bit is set and cleared by software.\n0: does not reset the ADC interface\n1: resets the ADC interface\nBits 7:6 Reserved, must be kept at reset value.\nBit 5 USART6RST: USART6 reset\nThis bit is set and cleared by software.\n0: does not reset USART6\n1: resets USART6\nBit 4\nUSART1RST: USART1 reset\nThis bit is set and cleared by software.\n0: does not reset USART1\n1: resets USART1\nBits 3:2 Reserved, must be kept at reset value.\nBit 1 TIM8RST: TIM8 reset\nThis bit is set and cleared by software.\n0: does not reset TIM8\n1: resets TIM8\nBit 0 TIM1RST: TIM1 reset\nThis bit is set and cleared by software.\n0: does not reset TIM1\n1: resets TIM1\n" }, { "page_number": 182, "page_indices": { "start_index": 473241, "end_index": 475159 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 182 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.10 RCC AHB1 peripheral clock register (RCC_AHB1ENR)", 182 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n182/1757\nRM0090 Rev 21\n6.3.10 \nRCC AHB1 peripheral clock register (RCC_AHB1ENR)\nAddress offset: 0x30\nReset value: 0x0010 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReser-\nved\nOTGH\nS \nULPIE\nN\nOTGH\nSEN\nETHM\nACPTP\nEN\nETHM\nACRXE\nN\nETHM\nACTXE\nN\nETHMA\nCEN\nRes.\nDMA2D\nEN\nDMA2E\nN\nDMA1E\nN\nCCMDAT\nARAMEN\nRes.\nBKPSR\nAMEN\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCRCE\nN\nRes.\nGPIOK\nEN\nGPIOJ\nEN\nGPIOIE\nN\nGPIOH\nEN\nGPIOG\nEN\nGPIOFE\nN\nGPIOEEN\nGPIOD\nEN\nGPIOC\nEN\nGPIO\nBEN\nGPIO\nAEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBit 30 OTGHSULPIEN: USB OTG HSULPI clock enable\nThis bit is set and cleared by software. It must be cleared when the OTG_HS is used in FS \nmode.\n0: USB OTG HS ULPI clock disabled\n1: USB OTG HS ULPI clock enabled\nBit 29 OTGHSEN: USB OTG HS clock enable\nThis bit is set and cleared by software.\n0: USB OTG HS clock disabled\n1: USB OTG HS clock enabled\nBit 28 ETHMACPTPEN: Ethernet PTP clock enable\nThis bit is set and cleared by software.\n0: Ethernet PTP clock disabled\n1: Ethernet PTP clock enabled\nBit 27 ETHMACRXEN: Ethernet Reception clock enable\nThis bit is set and cleared by software.\n0: Ethernet Reception clock disabled\n1: Ethernet Reception clock enabled\nBit 26 ETHMACTXEN: Ethernet Transmission clock enable\nThis bit is set and cleared by software.\n0: Ethernet Transmission clock disabled\n1: Ethernet Transmission clock enabled\nBit 25 ETHMACEN: Ethernet MAC clock enable\nThis bit is set and cleared by software.\n0: Ethernet MAC clock disabled\n1: Ethernet MAC clock enabled\nBit 24 Reserved, must be kept at reset value.\nBit 23 DMA2DEN: DMA2D clock enable\nThis bit is set and cleared by software.\n0: DMA2D clock disabled\n1: DMA2D clock enabled\n" }, { "page_number": 183, "page_indices": { "start_index": 475159, "end_index": 476768 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 183 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.10 RCC AHB1 peripheral clock register (RCC_AHB1ENR)", 182 ] ], "page_content": "RM0090 Rev 21\n183/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 22 DMA2EN: DMA2 clock enable\nThis bit is set and cleared by software.\n0: DMA2 clock disabled\n1: DMA2 clock enabled\nBit 21 DMA1EN: DMA1 clock enable\nThis bit is set and cleared by software.\n0: DMA1 clock disabled\n1: DMA1 clock enabled\nBit 20 CCMDATARAMEN: CCM data RAM clock enable\nThis bit is set and cleared by software. \n0: CCM data RAM clock disabled\n1: CCM data RAM clock enabled\nBit 19 Reserved, must be kept at reset value.\nBit 18 BKPSRAMEN: Backup SRAM interface clock enable\nThis bit is set and cleared by software.\n0: Backup SRAM interface clock disabled\n1: Backup SRAM interface clock enabled\nBits 17:13 Reserved, must be kept at reset value.\nBit 12 CRCEN: CRC clock enable\nThis bit is set and cleared by software.\n0: CRC clock disabled\n1: CRC clock enabled\nBit 11 Reserved, must be kept at reset value.\nBit 10 GPIOKEN: IO port K clock enable\nThis bit is set and cleared by software.\n0: IO port K clock disabled\n1: IO port K clock enabled\nBit 9 GPIOJEN: IO port J clock enable\nThis bit is set and cleared by software.\n0: IO port J clock disabled\n1: IO port J clock enabled\nBit 8 GPIOIEN: IO port I clock enable\nThis bit is set and cleared by software.\n0: IO port I clock disabled\n1: IO port I clock enabled\nBit 7 GPIOHEN: IO port H clock enable\nThis bit is set and cleared by software.\n0: IO port H clock disabled\n1: IO port H clock enabled\nBit 6 GPIOGEN: IO port G clock enable\nThis bit is set and cleared by software.\n0: IO port G clock disabled\n1: IO port G clock enabled\n" }, { "page_number": 184, "page_indices": { "start_index": 476768, "end_index": 478402 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 184 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.11 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)", 184 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n184/1757\nRM0090 Rev 21\n6.3.11 \nRCC AHB2 peripheral clock enable register (RCC_AHB2ENR)\nAddress offset: 0x34\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \nBit 5 GPIOFEN: IO port F clock enable\nThis bit is set and cleared by software.\n0: IO port F clock disabled\n1: IO port F clock enabled\nBit 4 GPIOEEN: IO port E clock enable\nThis bit is set and cleared by software.\n0: IO port E clock disabled\n1: IO port E clock enabled\nBit 3 GPIODEN: IO port D clock enable\nThis bit is set and cleared by software.\n0: IO port D clock disabled\n1: IO port D clock enabled\nBit 2 GPIOCEN: IO port C clock enable\nThis bit is set and cleared by software.\n0: IO port C clock disabled\n1: IO port C clock enabled\nBit 1 GPIOBEN: IO port B clock enable\nThis bit is set and cleared by software.\n0: IO port B clock disabled\n1: IO port B clock enabled\nBit 0 GPIOAEN: IO port A clock enable\nThis bit is set and cleared by software.\n0: IO port A clock disabled\n1: IO port A clock enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOTGFS\nEN\nRNG\nEN\nHASH\nEN\nCRYP\nEN\nReserved\nDCMI\nEN\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBit 7 OTGFSEN: USB OTG FS clock enable\nThis bit is set and cleared by software.\n0: USB OTG FS clock disabled\n1: USB OTG FS clock enabled\nBit 6 RNGEN: Random number generator clock enable\nThis bit is set and cleared by software.\n0: Random number generator clock disabled\n1: Random number generator clock enabled\n" }, { "page_number": 185, "page_indices": { "start_index": 478402, "end_index": 480133 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 185 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.12 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)", 185 ], [ 3, "6.3.13 RCC APB1 peripheral clock enable register (RCC_APB1ENR)", 185 ] ], "page_content": "RM0090 Rev 21\n185/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.12 \nRCC AHB3 peripheral clock enable register (RCC_AHB3ENR)\nAddress offset: 0x38\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n6.3.13 \nRCC APB1 peripheral clock enable register (RCC_APB1ENR)\nAddress offset: 0x40\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \nBit 5 HASHEN: Hash modules clock enable\nThis bit is set and cleared by software.\n0: Hash modules clock disabled\n1: Hash modules clock enabled\nBit 4 CRYPEN: Cryptographic modules clock enable\nThis bit is set and cleared by software.\n0: cryptographic module clock disabled\n1: cryptographic module clock enabled\nBits 3:1 Reserved, must be kept at reset value.\nBit 0 DCMIEN: Camera interface enable\nThis bit is set and cleared by software.\n0: Camera interface clock disabled\n1: Camera interface clock enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFMCEN\nrw\nBits 31:1 Reserved, must be kept at reset value.\nBit 0 FMCEN: Flexible memory controller module clock enable\nThis bit is set and cleared by software.\n0: FMC module clock disabled\n1: FMC module clock enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nUART8\nEN\nUART7\nEN\nDAC\nEN\nPWR\nEN\nReser-\nved\nCAN2\nEN\nCAN1\nEN\nReser-\nved\nI2C3\nEN\nI2C2\nEN\nI2C1\nEN\nUART5\nEN\nUART4\nEN\nUSART\n3\nEN\nUSART\n2\nEN\nReser-\nved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSPI3\nEN\nSPI2\nEN\nReserved\nWWDG\nEN\nReserved\nTIM14\nEN\nTIM13\nEN\nTIM12\nEN\nTIM7\nEN\nTIM6 \nEN\nTIM5\nEN\nTIM4\nEN\nTIM3\nEN\nTIM2\nEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 186, "page_indices": { "start_index": 480133, "end_index": 481738 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 186 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.13 RCC APB1 peripheral clock enable register (RCC_APB1ENR)", 185 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n186/1757\nRM0090 Rev 21\n \nBit 31 UART8EN: UART8 clock enable\nThis bit is set and cleared by software.\n0: UART8 clock disabled\n1: UART8 clock enabled\nBit 30 UART7EN: UART7 clock enable\nThis bit is set and cleared by software.\n0: UART7 clock disabled\n1: UART7 clock enabled\nBit 29 DACEN: DAC interface clock enable\nThis bit is set and cleared by software.\n0: DAC interface clock disabled\n1: DAC interface clock enable\nBit 28 PWREN: Power interface clock enable\nThis bit is set and cleared by software.\n0: Power interface clock disabled\n1: Power interface clock enable\nBit 27 Reserved, must be kept at reset value.\nBit 26 CAN2EN: CAN 2 clock enable\nThis bit is set and cleared by software.\n0: CAN 2 clock disabled\n1: CAN 2 clock enabled\nBit 25 CAN1EN: CAN 1 clock enable\nThis bit is set and cleared by software.\n0: CAN 1 clock disabled\n1: CAN 1 clock enabled\nBit 24 Reserved, must be kept at reset value.\nBit 23 I2C3EN: I2C3 clock enable\nThis bit is set and cleared by software.\n0: I2C3 clock disabled\n1: I2C3 clock enabled\nBit 22 I2C2EN: I2C2 clock enable\nThis bit is set and cleared by software.\n0: I2C2 clock disabled\n1: I2C2 clock enabled\nBit 21 I2C1EN: I2C1 clock enable\nThis bit is set and cleared by software.\n0: I2C1 clock disabled\n1: I2C1 clock enabled\nBit 20 UART5EN: UART5 clock enable\nThis bit is set and cleared by software.\n0: UART5 clock disabled\n1: UART5 clock enabled\nBit 19 UART4EN: UART4 clock enable\nThis bit is set and cleared by software.\n0: UART4 clock disabled\n1: UART4 clock enabled\n" }, { "page_number": 187, "page_indices": { "start_index": 481738, "end_index": 483248 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 187 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.13 RCC APB1 peripheral clock enable register (RCC_APB1ENR)", 185 ] ], "page_content": "RM0090 Rev 21\n187/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 18 USART3EN: USART3 clock enable\nThis bit is set and cleared by software.\n0: USART3 clock disabled\n1: USART3 clock enabled\nBit 17 USART2EN: USART2 clock enable\nThis bit is set and cleared by software.\n0: USART2 clock disabled\n1: USART2 clock enabled\nBit 16 Reserved, must be kept at reset value.\nBit 15 SPI3EN: SPI3 clock enable\nThis bit is set and cleared by software.\n0: SPI3 clock disabled\n1: SPI3 clock enabled\nBit 14 SPI2EN: SPI2 clock enable\nThis bit is set and cleared by software.\n0: SPI2 clock disabled\n1: SPI2 clock enabled\nBits 13:12 Reserved, must be kept at reset value.\nBit 11 WWDGEN: Window watchdog clock enable\nThis bit is set and cleared by software.\n0: Window watchdog clock disabled\n1: Window watchdog clock enabled\nBit 10:9 Reserved, must be kept at reset value.\nBit 8 TIM14EN: TIM14 clock enable\nThis bit is set and cleared by software.\n0: TIM14 clock disabled\n1: TIM14 clock enabled\nBit 7 TIM13EN: TIM13 clock enable\nThis bit is set and cleared by software.\n0: TIM13 clock disabled\n1: TIM13 clock enabled\nBit 6 TIM12EN: TIM12 clock enable\nThis bit is set and cleared by software.\n0: TIM12 clock disabled\n1: TIM12 clock enabled\nBit 5 TIM7EN: TIM7 clock enable\nThis bit is set and cleared by software.\n0: TIM7 clock disabled\n1: TIM7 clock enabled\nBit 4 TIM6EN: TIM6 clock enable\nThis bit is set and cleared by software.\n0: TIM6 clock disabled\n1: TIM6 clock enabled\n" }, { "page_number": 188, "page_indices": { "start_index": 483248, "end_index": 483836 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 188 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.13 RCC APB1 peripheral clock enable register (RCC_APB1ENR)", 185 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n188/1757\nRM0090 Rev 21\nBit 3 TIM5EN: TIM5 clock enable\nThis bit is set and cleared by software.\n0: TIM5 clock disabled\n1: TIM5 clock enabled\nBit 2 TIM4EN: TIM4 clock enable\nThis bit is set and cleared by software.\n0: TIM4 clock disabled\n1: TIM4 clock enabled\nBit 1 TIM3EN: TIM3 clock enable\nThis bit is set and cleared by software.\n0: TIM3 clock disabled\n1: TIM3 clock enabled\nBit 0 TIM2EN: TIM2 clock enable\nThis bit is set and cleared by software.\n0: TIM2 clock disabled\n1: TIM2 clock enabled\n" }, { "page_number": 189, "page_indices": { "start_index": 483836, "end_index": 485474 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 189 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.14 RCC APB2 peripheral clock enable register (RCC_APB2ENR)", 189 ] ], "page_content": "RM0090 Rev 21\n189/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.14 \nRCC APB2 peripheral clock enable register (RCC_APB2ENR)\nAddress offset: 0x44\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nLTDC\nEN\nReserved\nSAI1EN SPI6EN SPI5EN\nRes.\nTIM11\nEN\nTIM10\nEN\nTIM9\nEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReser-\nved\nSYSCF\nG EN\nSPI4E\nN\nSPI1\nEN\nSDIO\nEN\nADC3\nEN\nADC2\nEN\nADC1\nEN\nReserved\nUSART\n6\nEN\nUSART\n1\nEN\nReserved\nTIM8\nEN\nTIM1\nEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:27 Reserved, must be kept at reset value.\nBit 26 LTDCEN: LTDC clock enable\nThis bit is set and cleared by software.\n0: LTDC clock disabled\n1: LTDC clock enabled\nBits 27: 23 Reserved, must be kept at reset value.\nBit 22 SAI1EN: SAI1 clock enable\nThis bit is set and cleared by software.\n0: SAI1 clock disabled\n1: SAI1 clock enabled\nBit 21 SPI6EN: SPI6 clock enable\nThis bit is set and cleared by software.\n0: SPI6 clock disabled\n1: SPI6 clock enabled\nBit 20 SPI5EN: SPI5 clock enable\nThis bit is set and cleared by software.\n0: SPI5 clock disabled\n1: SPI5 clock enabled\nBit 18 TIM11EN: TIM11 clock enable\nThis bit is set and cleared by software.\n0: TIM11 clock disabled\n1: TIM11 clock enabled\nBit 17 TIM10EN: TIM10 clock enable\nThis bit is set and cleared by software.\n0: TIM10 clock disabled\n1: TIM10 clock enabled\nBit 16 TIM9EN: TIM9 clock enable\nThis bit is set and cleared by software.\n0: TIM9 clock disabled\n1: TIM9 clock enabled\nBit 15 Reserved, must be kept at reset value.\n" }, { "page_number": 190, "page_indices": { "start_index": 485474, "end_index": 487102 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 190 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.14 RCC APB2 peripheral clock enable register (RCC_APB2ENR)", 189 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n190/1757\nRM0090 Rev 21\nBit 14 SYSCFGEN: System configuration controller clock enable\nThis bit is set and cleared by software.\n0: System configuration controller clock disabled\n1: System configuration controller clock enabled\nBit 13 SPI4EN: SPI4 clock enable\nThis bit is set and cleared by software.\n0: SPI4 clock disabled\n1: SPI4 clock enabled\nBit 12 SPI1EN: SPI1 clock enable\nThis bit is set and cleared by software.\n0: SPI1 clock disabled\n1: SPI1 clock enabled\nBit 11 SDIOEN: SDIO clock enable\nThis bit is set and cleared by software.\n0: SDIO module clock disabled\n1: SDIO module clock enabled\nBit 10 ADC3EN: ADC3 clock enable\nThis bit is set and cleared by software.\n0: ADC3 clock disabled\n1: ADC3 clock enabled\nBit 9\nADC2EN: ADC2 clock enable\nThis bit is set and cleared by software.\n0: ADC2 clock disabled\n1: ADC2 clock enabled\nBit 8\nADC1EN: ADC1 clock enable\nThis bit is set and cleared by software.\n0: ADC1 clock disabled\n1: ADC1 clock enabled\nBits 7:6 Reserved, must be kept at reset value.\nBit 5 USART6EN: USART6 clock enable\nThis bit is set and cleared by software.\n0: USART6 clock disabled\n1: USART6 clock enabled\nBit 4 USART1EN: USART1 clock enable\nThis bit is set and cleared by software.\n0: USART1 clock disabled\n1: USART1 clock enabled\nBits 3:2 Reserved, must be kept at reset value.\nBit 1 TIM8EN: TIM8 clock enable\nThis bit is set and cleared by software.\n0: TIM8 clock disabled\n1: TIM8 clock enabled\nBit 0 TIM1EN: TIM1 clock enable\nThis bit is set and cleared by software.\n0: TIM1 clock disabled\n1: TIM1 clock enabled\n" }, { "page_number": 191, "page_indices": { "start_index": 487102, "end_index": 489333 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 191 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.15 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR)", 191 ] ], "page_content": "RM0090 Rev 21\n191/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.15 \nRCC AHB1 peripheral clock enable in low power mode register\n(RCC_AHB1LPENR)\nAddress offset: 0x50\nReset value: 0x7EEF 97FF\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nRes.\nOTGHS\nULPILPE\nN\nOTGH\nS\nLPEN\nETHPT\nP\nLPEN\nETHRX\nLPEN\nETHTX\nLPEN\nETHMA\nC\nLPEN\nRes.\nDMA2D\nLPEN\nDMA2\nLPEN\nDMA1\nLPEN\nRes.\nSRAM3\nLPEN\nBKPSRA\nM\nLPEN\nSRAM\n2\nLPEN\nSRAM\n1\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFLITF\nLPEN\nReserved\nCRC\nLPEN\nRes.\nGPIOK\nLPEN\nGPIOIJ\nLPEN\nGPIOI\nLPEN\nGPIOH\nLPEN\nGPIOG\nG\nLPEN\nGPIO\nF\nLPEN\nGPIOE\nLPEN\nGPIOD\nLPEN\nGPIOC\nLPEN\nGPIOB\nLPEN\nGPIOA\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBit 30 OTGHSULPILPEN: USB OTG HS ULPI clock enable during Sleep mode\nThis bit is set and cleared by software. It must be cleared when the OTG_HS is used in FS \nmode.\n0: USB OTG HS ULPI clock disabled during Sleep mode\n1: USB OTG HS ULPI clock enabled during Sleep mode\nBit 29 OTGHSLPEN: USB OTG HS clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: USB OTG HS clock disabled during Sleep mode\n1: USB OTG HS clock enabled during Sleep mode\nBit 28 ETHMACPTPLPEN: Ethernet PTP clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Ethernet PTP clock disabled during Sleep mode\n1: Ethernet PTP clock enabled during Sleep mode\nBit 27 ETHMACRXLPEN: Ethernet reception clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Ethernet reception clock disabled during Sleep mode\n1: Ethernet reception clock enabled during Sleep mode\nBit 26 ETHMACTXLPEN: Ethernet transmission clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Ethernet transmission clock disabled during sleep mode\n1: Ethernet transmission clock enabled during sleep mode\nBit 25 ETHMACLPEN: Ethernet MAC clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Ethernet MAC clock disabled during Sleep mode\n1: Ethernet MAC clock enabled during Sleep mode\nBit 24 Reserved, must be kept at reset value.\n" }, { "page_number": 192, "page_indices": { "start_index": 489333, "end_index": 491547 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 192 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.15 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR)", 191 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n192/1757\nRM0090 Rev 21\nBit 23 DMA2DLPEN: DMA2D clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: DMA2D clock disabled during Sleep mode\n1: DMA2D clock enabled during Sleep mode\nBit 22 DMA2LPEN: DMA2 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: DMA2 clock disabled during Sleep mode\n1: DMA2 clock enabled during Sleep mode\nBit 21 DMA1LPEN: DMA1 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: DMA1 clock disabled during Sleep mode\n1: DMA1 clock enabled during Sleep mode\nBit 20 Reserved, must be kept at reset value.\nBit 19 SRAM3LPEN: SRAM3 interface clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SRAM3 interface clock disabled during Sleep mode\n1: SRAM3 interface clock enabled during Sleep mode\nBit 18 BKPSRAMLPEN: Backup SRAM interface clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Backup SRAM interface clock disabled during Sleep mode\n1: Backup SRAM interface clock enabled during Sleep mode\nBit 17 SRAM2LPEN: SRAM2 interface clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SRAM2 interface clock disabled during Sleep mode\n1: SRAM2 interface clock enabled during Sleep mode\nBit 16 SRAM1LPEN: SRAM1 interface clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SRAM1 interface clock disabled during Sleep mode\n1: SRAM1 interface clock enabled during Sleep mode\nBit 15 FLITFLPEN: Flash interface clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Flash interface clock disabled during Sleep mode\n1: Flash interface clock enabled during Sleep mode\nBits 14:13 Reserved, must be kept at reset value.\nBit 12 CRCLPEN: CRC clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: CRC clock disabled during Sleep mode\n1: CRC clock enabled during Sleep mode\nBit 11 Reserved, must be kept at reset value.\nBit 10 GPIOKLPEN: IO port K clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port K clock disabled during Sleep mode\n1: IO port K clock enabled during Sleep mode\n" }, { "page_number": 193, "page_indices": { "start_index": 491547, "end_index": 493556 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 193 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.15 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR)", 191 ] ], "page_content": "RM0090 Rev 21\n193/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 9 GPIOJLPEN: IO port J clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port J clock disabled during Sleep mode\n1: IO port J clock enabled during Sleep mode\nBit 8 GPIOILPEN: IO port I clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port I clock disabled during Sleep mode\n1: IO port I clock enabled during Sleep mode\nBit 7\nGPIOHLPEN: IO port H clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port H clock disabled during Sleep mode\n1: IO port H clock enabled during Sleep mode\nBits 6 GPIOGLPEN: IO port G clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port G clock disabled during Sleep mode\n1: IO port G clock enabled during Sleep mode\nBit 5 GPIOFLPEN: IO port F clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port F clock disabled during Sleep mode\n1: IO port F clock enabled during Sleep mode\nBit 4 GPIOELPEN: IO port E clock enable during Sleep mode\nSet and cleared by software.\n0: IO port E clock disabled during Sleep mode\n1: IO port E clock enabled during Sleep mode\nBit 3 GPIODLPEN: IO port D clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port D clock disabled during Sleep mode\n1: IO port D clock enabled during Sleep mode\nBit 2 GPIOCLPEN: IO port C clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port C clock disabled during Sleep mode\n1: IO port C clock enabled during Sleep mode\nBit 1 GPIOBLPEN: IO port B clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: IO port B clock disabled during Sleep mode\n1: IO port B clock enabled during Sleep mode\nBit 0 GPIOALPEN: IO port A clock enable during sleep mode\nThis bit is set and cleared by software.\n0: IO port A clock disabled during Sleep mode\n1: IO port A clock enabled during Sleep mode\n" }, { "page_number": 194, "page_indices": { "start_index": 493556, "end_index": 495200 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 194 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.16 RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR)", 194 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n194/1757\nRM0090 Rev 21\n6.3.16 \nRCC AHB2 peripheral clock enable in low power mode register\n(RCC_AHB2LPENR)\nAddress offset: 0x54\nReset value: 0x0000 00F1\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOTGFS\nLPEN\nRNG\nLPEN\nHASH\nLPEN\nCRYP\nLPEN\nReserved\nDCMI\nLPEN\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBit 7 OTGFSLPEN: USB OTG FS clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: USB OTG FS clock disabled during Sleep mode\n1: USB OTG FS clock enabled during Sleep mode\nBit 6 RNGLPEN: Random number generator clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Random number generator clock disabled during Sleep mode\n1: Random number generator clock enabled during Sleep mode\nBit 5 HASHLPEN: Hash modules clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Hash modules clock disabled during Sleep mode\n1: Hash modules clock enabled during Sleep mode\nBit 4 CRYPLPEN: Cryptography modules clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: cryptography modules clock disabled during Sleep mode\n1: cryptography modules clock enabled during Sleep mode\nBits 3:1 Reserved, must be kept at reset value.\nBit 0 DCMILPEN: Camera interface enable during Sleep mode\nThis bit is set and cleared by software.\n0: Camera interface clock disabled during Sleep mode\n1: Camera interface clock enabled during Sleep mode\n" }, { "page_number": 195, "page_indices": { "start_index": 495200, "end_index": 496583 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 195 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.17 RCC AHB3 peripheral clock enable in low power mode register (RCC_AHB3LPENR)", 195 ], [ 3, "6.3.18 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR)", 195 ] ], "page_content": "RM0090 Rev 21\n195/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.17 \nRCC AHB3 peripheral clock enable in low power mode register\n(RCC_AHB3LPENR)\nAddress offset: 0x58\nReset value: 0x0000 0001\nAccess: no wait state, word, half-word and byte access.\n \n \n6.3.18 \nRCC APB1 peripheral clock enable in low power mode register\n(RCC_APB1LPENR)\nAddress offset: 0x60\nReset value: 0xF6FE C9FF\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFMC\nLPEN\nrw\nBits 31:1Reserved, must be kept at reset value.\nBit 0\nFMCLPEN: Flexible memory controller module clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: FMC module clock disabled during Sleep mode\n1: FMC module clock enabled during Sleep mode\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nUART8\nLPEN\nUART7\nLPEN\nDAC\nLPEN\nPWR\nLPEN\nRESER\nVED\nCAN2\nLPEN\nCAN1\nLPEN\nReser-\nved\nI2C3\nLPEN\nI2C2\nLPEN\nI2C1\nLPEN\nUART5\nLPEN\nUART4\nLPEN\nUSART\n3\nLPEN\nUSART\n2\nLPEN\nReser-\nved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSPI3\nLPEN\nSPI2\nLPEN\nReserved\nWWDG\nLPEN\nReserved\nTIM14\nLPEN\nTIM13\nLPEN\nTIM12\nLPEN\nTIM7\nLPEN\nTIM6 \nLPEN\nTIM5\nLPEN\nTIM4\nLPEN\nTIM3\nLPEN\nTIM2\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 196, "page_indices": { "start_index": 496583, "end_index": 498796 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 196 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.18 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR)", 195 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n196/1757\nRM0090 Rev 21\nBit 31 UART8LPEN: UART8 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: UART8 clock disabled during Sleep mode\n1: UART8 clock enabled during Sleep mode\nBit 30 UART7LPEN: UART7 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: UART7 clock disabled during Sleep mode\n1: UART7 clock enabled during Sleep mode\nBit 29 DACLPEN: DAC interface clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: DAC interface clock disabled during Sleep mode\n1: DAC interface clock enabled during Sleep mode\nBit 28 PWRLPEN: Power interface clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Power interface clock disabled during Sleep mode\n1: Power interface clock enabled during Sleep mode\nBit 27 Reserved, must be kept at reset value.\nBit 26 CAN2LPEN: CAN 2 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: CAN 2 clock disabled during sleep mode\n1: CAN 2 clock enabled during sleep mode\nBit 25 CAN1LPEN: CAN 1 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: CAN 1 clock disabled during Sleep mode\n1: CAN 1 clock enabled during Sleep mode\nBit 24 Reserved, must be kept at reset value.\nBit 23 I2C3LPEN: I2C3 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: I2C3 clock disabled during Sleep mode\n1: I2C3 clock enabled during Sleep mode\nBit 22 I2C2LPEN: I2C2 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: I2C2 clock disabled during Sleep mode\n1: I2C2 clock enabled during Sleep mode\nBit 21 I2C1LPEN: I2C1 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: I2C1 clock disabled during Sleep mode\n1: I2C1 clock enabled during Sleep mode\nBit 20 UART5LPEN: UART5 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: UART5 clock disabled during Sleep mode\n1: UART5 clock enabled during Sleep mode\nBit 19 UART4LPEN: UART4 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: UART4 clock disabled during Sleep mode\n1: UART4 clock enabled during Sleep mode\n" }, { "page_number": 197, "page_indices": { "start_index": 498796, "end_index": 500867 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 197 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.18 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR)", 195 ] ], "page_content": "RM0090 Rev 21\n197/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBit 18\nUSART3LPEN: USART3 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: USART3 clock disabled during Sleep mode\n1: USART3 clock enabled during Sleep mode\nBit 17 USART2LPEN: USART2 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: USART2 clock disabled during Sleep mode\n1: USART2 clock enabled during Sleep mode\nBit 16 Reserved, must be kept at reset value.\nBit 15 SPI3LPEN: SPI3 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SPI3 clock disabled during Sleep mode\n1: SPI3 clock enabled during Sleep mode\nBit 14 SPI2LPEN: SPI2 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SPI2 clock disabled during Sleep mode\n1: SPI2 clock enabled during Sleep mode\nBits 13:12 Reserved, must be kept at reset value.\nBit 11 WWDGLPEN: Window watchdog clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: Window watchdog clock disabled during sleep mode\n1: Window watchdog clock enabled during sleep mode\nBits 10:9 Reserved, must be kept at reset value.\nBit 8 TIM14LPEN: TIM14 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM14 clock disabled during Sleep mode\n1: TIM14 clock enabled during Sleep mode\nBit 7 TIM13LPEN: TIM13 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM13 clock disabled during Sleep mode\n1: TIM13 clock enabled during Sleep mode\nBit 6 TIM12LPEN: TIM12 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM12 clock disabled during Sleep mode\n1: TIM12 clock enabled during Sleep mode\nBit 5 TIM7LPEN: TIM7 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM7 clock disabled during Sleep mode\n1: TIM7 clock enabled during Sleep mode\nBit 4 TIM6LPEN: TIM6 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM6 clock disabled during Sleep mode\n1: TIM6 clock enabled during Sleep mode\n" }, { "page_number": 198, "page_indices": { "start_index": 500867, "end_index": 501679 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 198 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.18 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR)", 195 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n198/1757\nRM0090 Rev 21\nBit 3 TIM5LPEN: TIM5 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM5 clock disabled during Sleep mode\n1: TIM5 clock enabled during Sleep mode\nBit 2 TIM4LPEN: TIM4 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM4 clock disabled during Sleep mode\n1: TIM4 clock enabled during Sleep mode\nBit 1 TIM3LPEN: TIM3 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM3 clock disabled during Sleep mode\n1: TIM3 clock enabled during Sleep mode\nBit 0\nTIM2LPEN: TIM2 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM2 clock disabled during Sleep mode\n1: TIM2 clock enabled during Sleep mode\n" }, { "page_number": 199, "page_indices": { "start_index": 501679, "end_index": 503602 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 199 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.19 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR)", 199 ] ], "page_content": "RM0090 Rev 21\n199/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.19 \nRCC APB2 peripheral clock enabled in low power mode register\n(RCC_APB2LPENR)\nAddress offset: 0x64\nReset value: 0x0x0477 7F33 \nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nLTDC\nLPEN\nReserved\nSAI1\nLPEN\nSPI6\nLPEN\nSPI5\nLPEN\nReser-\nved\nTIM11\nLPEN\nTIM10\nLPEN\nTIM9\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReser-\nved\nSYSC\nFG\nLPEN\nSPI4\nLPEN\nSPI1\nLPEN\nSDIO\nLPEN\nADC3\nLPEN\nADC2\nLPEN\nADC1\nLPEN\nReserved\nUSART\n6\nLPEN\nUSART\n1\nLPEN\nReserved\nTIM8\nLPEN\nTIM1\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:27 Reserved, must be kept at reset value.\nBit 26 LTDCLPEN: LTDC clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: LTDC clock disabled during Sleep mode\n1: LTDC clock enabled during Sleep mode\nBits 25:23 Reserved, must be kept at reset value.\nBit 22 SAI1LPEN: SAI1 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SAI1 clock disabled during Sleep mode\n1: SAI1 clock enabled during Sleep mode\nBit 21 SPI6LPEN: SPI6 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SPI6 clock disabled during Sleep mode\n1: SPI6 clock enabled during Sleep mode\nBit 20 SPI5LPEN: SPI5 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SPI5 clock disabled during Sleep mode\n1: SPI5 clock enabled during Sleep mode\nBit 19 Reserved, must be kept at reset value.\nBit 18 TIM11LPEN: TIM11 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM11 clock disabled during Sleep mode\n1: TIM11 clock enabled during Sleep mode\nBit 17 TIM10LPEN: TIM10 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM10 clock disabled during Sleep mode\n1: TIM10 clock enabled during Sleep mode\n" }, { "page_number": 200, "page_indices": { "start_index": 503602, "end_index": 505674 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 200 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.19 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR)", 199 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n200/1757\nRM0090 Rev 21\nBit 16 TIM9LPEN: TIM9 clock enable during sleep mode\nThis bit is set and cleared by software.\n0: TIM9 clock disabled during Sleep mode\n1: TIM9 clock enabled during Sleep mode\nBit 15 Reserved, must be kept at reset value.\nBit 14 SYSCFGLPEN: System configuration controller clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: System configuration controller clock disabled during Sleep mode\n1: System configuration controller clock enabled during Sleep mode\nBit 13 SPI4LPEN: SPI4 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SPI4 clock disabled during Sleep mode\n1: SPI4 clock enabled during Sleep mode\nBit 12 SPI1LPEN: SPI1 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SPI1 clock disabled during Sleep mode\n1: SPI1 clock enabled during Sleep mode\nBit 11 SDIOLPEN: SDIO clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: SDIO module clock disabled during Sleep mode\n1: SDIO module clock enabled during Sleep mode\nBit 10 ADC3LPEN: ADC 3 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: ADC 3 clock disabled during Sleep mode\n1: ADC 3 clock enabled during Sleep mode\nBit 9 ADC2LPEN: ADC2 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: ADC2 clock disabled during Sleep mode\n1: ADC2 clock enabled during Sleep mode\nBit 8 ADC1LPEN: ADC1 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: ADC1 clock disabled during Sleep mode\n1: ADC1 clock enabled during Sleep mode\nBits 7:6 Reserved, must be kept at reset value.\nBit 5 USART6LPEN: USART6 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: USART6 clock disabled during Sleep mode\n1: USART6 clock enabled during Sleep mode\nBit 4 USART1LPEN: USART1 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: USART1 clock disabled during Sleep mode\n1: USART1 clock enabled during Sleep mode\n" }, { "page_number": 201, "page_indices": { "start_index": 505674, "end_index": 507852 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 201 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.20 RCC Backup domain control register (RCC_BDCR)", 201 ] ], "page_content": "RM0090 Rev 21\n201/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.20 \nRCC Backup domain control register (RCC_BDCR)\nAddress offset: 0x70\nReset value: 0x0000 0000, reset by Backup domain reset.\nAccess: 0 ≤ wait state ≤ 3, word, half-word and byte access\nWait states are inserted in case of successive accesses to this register.\nThe LSEON, LSEBYP, RTCSEL and RTCEN bits in the RCC Backup domain control \nregister (RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are \nwrite-protected and the DBP bit in the PWR power control register (PWR_CR) for \nSTM32F42xxx and STM32F43xxx has to be set before these can be modified. Refer to \nSection 6.1.1: System reset on page 152 for further information. These bits are only reset \nafter a Backup domain Reset (see Section 6.1.3: Backup domain reset). Any internal or \nexternal Reset has no effect on these bits.\n \n \nBits 3:2 Reserved, must be kept at reset value.\nBit 1 TIM8LPEN: TIM8 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM8 clock disabled during Sleep mode\n1: TIM8 clock enabled during Sleep mode\nBit 0 TIM1LPEN: TIM1 clock enable during Sleep mode\nThis bit is set and cleared by software.\n0: TIM1 clock disabled during Sleep mode\n1: TIM1 clock enabled during Sleep mode\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nBDRST\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRTCEN\nReserved\nRTCSEL[1:0]\nReserved\nLSEBY\nP\nLSERD\nY\nLSEON\nrw\nrw\nrw\nrw\nr\nrw\nBits 31:17 Reserved, must be kept at reset value.\nBit 16 BDRST: Backup domain software reset\nThis bit is set and cleared by software.\n0: Reset not activated\n1: Resets the entire Backup domain\nNote: The BKPSRAM is not affected by this reset, the only way of resetting the BKPSRAM is \nthrough the Flash interface when a protection level change from level 1 to level 0 is \nrequested.\nThe backup domain software reset does not take effect until the DBP bit of the \nPWR_CR register is set.\nBit 15 RTCEN: RTC clock enable\nThis bit is set and cleared by software.\n0: RTC clock disabled\n1: RTC clock enabled\nBits 14:10 Reserved, must be kept at reset value.\n" }, { "page_number": 202, "page_indices": { "start_index": 507852, "end_index": 509746 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 202 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.21 RCC clock control & status register (RCC_CSR)", 202 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n202/1757\nRM0090 Rev 21\n6.3.21 \nRCC clock control & status register (RCC_CSR)\nAddress offset: 0x74\nReset value: 0x0E00 0000, reset by system reset, except reset flags by power reset only.\nAccess: 0 ≤ wait state ≤ 3, word, half-word and byte access\nWait states are inserted in case of successive accesses to this register.\n \nBits 9:8 RTCSEL[1:0]: RTC clock source selection\nThese bits are set by software to select the clock source for the RTC. Once the RTC clock \nsource has been selected, it cannot be changed anymore unless the Backup domain is \nreset. The BDRST bit can be used to reset them.\n00: No clock\n01: LSE oscillator clock used as the RTC clock\n10: LSI oscillator clock used as the RTC clock\n11: HSE oscillator clock divided by a programmable prescaler (selection through the \nRTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC \nclock\nBits 7:3 Reserved, must be kept at reset value.\nBit 2 LSEBYP: External low-speed oscillator bypass\nThis bit is set and cleared by software to bypass the oscillator. This bit can be written only \nwhen the LSE clock is disabled.\n0: LSE oscillator not bypassed\n1: LSE oscillator bypassed\nBit 1 LSERDY: External low-speed oscillator ready\nThis bit is set and cleared by hardware to indicate when the external 32 kHz oscillator is \nstable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed \noscillator clock cycles.\n0: LSE clock not ready\n1: LSE clock ready\nBit 0 LSEON: External low-speed oscillator enable\nThis bit is set and cleared by software.\n0: LSE clock OFF\n1: LSE clock ON\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nLPWR\nRSTF\nWWDG\nRSTF\nIWDG\nRSTF\nSFT\nRSTF\nPOR\nRSTF\nPIN\nRSTF\nBORRS\nTF\nRMVF\nReserved\nr\nr\nr\nr\nr\nr\nr\nrt_w\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLSIRDY\nLSION\nr\nrw\n" }, { "page_number": 203, "page_indices": { "start_index": 509746, "end_index": 511542 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 203 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.21 RCC clock control & status register (RCC_CSR)", 202 ] ], "page_content": "RM0090 Rev 21\n203/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n \nBit 31 LPWRRSTF: Low-power reset flag\nThis bit is set by hardware when a Low-power management reset occurs.\nCleared by writing to the RMVF bit.\n0: No Low-power management reset occurred\n1: Low-power management reset occurred\nFor further information on Low-power management reset, refer to Low-power management \nreset.\nBit 30 WWDGRSTF: Window watchdog reset flag\nThis bit is set by hardware when a window watchdog reset occurs.\nCleared by writing to the RMVF bit.\n0: No window watchdog reset occurred\n1: Window watchdog reset occurred\nBit 29 IWDGRSTF: Independent watchdog reset flag\nThis bit is set by hardware when an independent watchdog reset from VDD domain occurs.\nCleared by writing to the RMVF bit.\n0: No watchdog reset occurred\n1: Watchdog reset occurred\nBit 28 SFTRSTF: Software reset flag\nThis bit is set by hardware when a software reset occurs.\nCleared by writing to the RMVF bit.\n0: No software reset occurred\n1: Software reset occurred\nBit 27 PORRSTF: POR/PDR reset flag\nThis bit is set by hardware when a POR/PDR reset occurs.\nCleared by writing to the RMVF bit.\n0: No POR/PDR reset occurred\n1: POR/PDR reset occurred\nBit 26 PINRSTF: PIN reset flag\nThis bit is set by hardware when a reset from the NRST pin occurs.\nCleared by writing to the RMVF bit.\n0: No reset from NRST pin occurred\n1: Reset from NRST pin occurred\nBit 25 BORRSTF: BOR reset flag\nCleared by software by writing the RMVF bit.\nThis bit is set by hardware when a POR/PDR or BOR reset occurs.\n0: No POR/PDR or BOR reset occurred\n1: POR/PDR or BOR reset occurred\nBit 24 RMVF: Remove reset flag\nThis bit is set by software to clear the reset flags.\n0: No effect\n1: Clear the reset flags\n" }, { "page_number": 204, "page_indices": { "start_index": 511542, "end_index": 513295 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 204 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.22 RCC spread spectrum clock generation register (RCC_SSCGR)", 204 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n204/1757\nRM0090 Rev 21\n6.3.22 \nRCC spread spectrum clock generation register (RCC_SSCGR)\nAddress offset: 0x80\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\nThe spread spectrum clock generation is available only for the main PLL.\nThe RCC_SSCGR register must be written either before the main PLL is enabled or after \nthe main PLL disabled.\nNote:\nFor full details about PLL spread spectrum clock generation (SSCG) characteristics, refer to \nthe “Electrical characteristics” section in your device datasheet. \n \n \nBits 23:2 Reserved, must be kept at reset value.\nBit 1 LSIRDY: Internal low-speed oscillator ready\nThis bit is set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is \nstable. After the LSION bit is cleared, LSIRDY goes low after 3 LSI clock cycles.\n0: LSI RC oscillator not ready\n1: LSI RC oscillator ready\nBit 0 LSION: Internal low-speed oscillator enable\nThis bit is set and cleared by software.\n0: LSI RC oscillator OFF\n1: LSI RC oscillator ON\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nSSCG\nEN\nSPR\nEAD\nSEL\nReserved\nINCSTEP\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nINCSTEP\nMODPER\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 SSCGEN: Spread spectrum modulation enable\nThis bit is set and cleared by software.\n0: Spread spectrum modulation DISABLE. (To write after clearing CR[24]=PLLON bit)\n1: Spread spectrum modulation ENABLE. (To write before setting CR[24]=PLLON bit)\nBit 30 SPREADSEL: Spread Select\nThis bit is set and cleared by software.\nTo write before to set CR[24]=PLLON bit.\n0: Center spread\n1: Down spread\n" }, { "page_number": 205, "page_indices": { "start_index": 513295, "end_index": 514481 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 205 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.23 RCC PLLI2S configuration register (RCC_PLLI2SCFGR)", 205 ] ], "page_content": "RM0090 Rev 21\n205/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n6.3.23 \nRCC PLLI2S configuration register (RCC_PLLI2SCFGR)\nAddress offset: 0x84\nReset value: 0x2400 3000\nAccess: no wait state, word, half-word and byte access.\nThis register is used to configure the PLLI2S clock outputs according to the formulas:\nf(VCO clock) = f(PLLI2S clock input) × (PLLI2SN / PLLM)\nf(PLL I2S clock output) = f(VCO clock) / PLLI2SR\n \nBits 29:28 Reserved, must be kept at reset value.\nBits 27:13 INCSTEP: Incrementation step\nThese bits are set and cleared by software. To write before setting CR[24]=PLLON bit.\nConfiguration input for modulation profile amplitude.\nBits 12:0 MODPER: Modulation period\nThese bits are set and cleared by software. To write before setting CR[24]=PLLON bit.\nConfiguration input for modulation profile period.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserv\ned\nPLLI2S\nR2\nPLLI2S\nR1\nPLLI2S\nR0\nPLLI2SQ\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserv\ned\nPLLI2SN\n8\nPLLI2SN\n7\nPLLI2SN\n6\nPLLI2SN\n5\nPLLI2SN\n4\nPLLI2SN\n3\nPLLI2SN\n2\nPLLI2SN\n1\nPLLI2SN\n0\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 206, "page_indices": { "start_index": 514481, "end_index": 515832 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 206 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.23 RCC PLLI2S configuration register (RCC_PLLI2SCFGR)", 205 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n206/1757\nRM0090 Rev 21\nBit 31 Reserved, must be kept at reset value.\nBits 30:28 PLLI2SR: PLLI2S division factor for I2S clocks\nThese bits are set and cleared by software to control the I2S clock frequency. These bits \nshould be written only if the PLLI2S is disabled. The factor must be chosen in accordance \nwith the prescaler values inside the I2S peripherals, to reach 0.3% error when using \nstandard crystals and 0% error with audio crystals. For more information about I2S clock \nfrequency and precision, refer to Section 28.4.4: Clock generator in the I2S chapter.\nCaution: The I2Ss requires a frequency lower than or equal to 192 MHz to work correctly.\nI2S clock frequency = VCO frequency / PLLR with 2 ≤ PLLR ≤ 7\n000: PLLR = 0, wrong configuration\n001: PLLR = 1, wrong configuration\n010: PLLR = 2\n...\n111: PLLR = 7\nBits 27:24 PLLI2SQ: PLLI2S division factor for SAI1 clock\nThese bits are set and cleared by software to control the SAI1 clock frequency.\nThey should be written when the PLLI2S is disabled.\nSAI1 clock frequency = VCO frequency / PLLI2SQ with 2 <= PLLI2SIQ <= 15\n0000: PLLI2SQ = 0, wrong configuration\n0001: PLLI2SQ = 1, wrong configuration\n0010: PLLI2SQ = 2\n0011: PLLI2SQ = 3\n0100: PLLI2SQ = 4\n0101: PLLI2SQ = 5\n...\n1111: PLLI2SQ = 15\n" }, { "page_number": 207, "page_indices": { "start_index": 515832, "end_index": 517084 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 207 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.23 RCC PLLI2S configuration register (RCC_PLLI2SCFGR)", 205 ] ], "page_content": "RM0090 Rev 21\n207/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBits 23:15 Reserved, must be kept at reset value.\nBits 14:6 PLLI2SN: PLLI2S multiplication factor for VCO\nThese bits are set and cleared by software to control the multiplication factor of the VCO. \nThese bits can be written only when PLLI2S is disabled. Only half-word and word accesses \nare allowed to write these bits.\nCaution: The software has to set these bits correctly to ensure that the VCO output \nfrequency is between 100 and 432 MHz. \nVCO output frequency = VCO input frequency × PLLI2SN with 50 ≤ PLLI2SN ≤ 432\n000000000: PLLI2SN = 0, wrong configuration \n000000001: PLLI2SN = 1, wrong configuration\n...\n000110010: PLLI2SN = 50\n...\n001100011: PLLI2SN = 99 \n001100100: PLLI2SN = 100\n001100101: PLLI2SN = 101\n001100110: PLLI2SN = 102\n... \n110110000: PLLI2SN = 432\n110110001: PLLI2SN = 433, wrong configuration\n... \n111111111: PLLI2SN = 511, wrong configuration \nNote: Multiplication factors ranging from 50 and 99 are possible for VCO input frequency \nhigher than 1 MHz. However care must be taken that the minimum VCO output \nfrequency respects the value specified above. \nBits 5:0 Reserved, must be kept at reset value.\n" }, { "page_number": 208, "page_indices": { "start_index": 517084, "end_index": 518650 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 208 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.24 RCC PLL configuration register (RCC_PLLSAICFGR)", 208 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n208/1757\nRM0090 Rev 21\n6.3.24 \nRCC PLL configuration register (RCC_PLLSAICFGR)\nAddress offset: 0x88\nReset value: 0x2400 3000\nAccess: no wait state, word, half-word and byte access.\nThis register is used to configure the PLLSAI clock outputs according to the formulas:\n•\nf(VCO clock) = f(PLLSAI clock input) × (PLLSAIN / PLLM)\n•\nf(PLLSAI1 clock output) = f(VCO clock) / PLLSAIQ\n•\nf(PLL LCD clock output) = f(VCO clock) / PLLSAIR\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPLLSAIR\nPLLSAIQ\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPLLSAIN\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBits 30:28 PLLSAIR: PLLSAI division factor for LCD clock\nSet and reset by software to control the LCD clock frequency.\nThese bits should be written when the PLLSAI is disabled.\nLCD clock frequency = VCO frequency / PLLSAIR with 2 ≤ PLLSAIR ≤ 7\n000: PLLSAIR = 0, wrong configuration\n001: PLLSAIR = 1, wrong configuration\n010: PLLSAIR = 2\n...\n111: PLLSAIR = 7\nBits 27:24 PLLSAIQ: PLLSAI division factor for SAI1 clock\nSet and reset by software to control the frequency of SAI1 clock.\nThese bits should be written when the PLLSAI is disabled.\nSAI1 clock frequency = VCO frequency / PLLSAIQ with 2 ≤ PLLSAIQ ≤15\n0000: PLLSAIQ = 0, wrong configuration\n0001: PLLSAIQ = 1, wrong configuration\n...\n0010: PLLSAIQ = 2\n0011: PLLSAIQ = 3\n0100: PLLSAIQ = 4\n0101: PLLSAIQ = 5\n...\n1111: PLLSAIQ = 15\n" }, { "page_number": 209, "page_indices": { "start_index": 518650, "end_index": 520684 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 209 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.25 RCC Dedicated Clock Configuration Register (RCC_DCKCFGR)", 209 ] ], "page_content": "RM0090 Rev 21\n209/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n \n6.3.25 \nRCC Dedicated Clock Configuration Register (RCC_DCKCFGR)\nAddress offset: 0x8C\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\nThe RCC_DCKCFGR register allows to configure the timer clock prescalers and the PLLSAI \nand PLLI2S output clock dividers for SAI1 and LTDC peripherals according to the following \nformula:\nf(PLLSAIDIVQ clock output) = f(PLLSAI_Q) / PLLSAIDIVQ\nf(PLLSAIDIVR clock output) = f(PLLSAI_R) / PLLSAIDIVR\nf(PLLI2SDIVQ clock output) = f(PLLI2S_Q) / PLLI2SDIVQ\n \n \nBits 23:15 Reserved, must be kept at reset value.\nBits 14:6 PLLSAIN: PLLSAI division factor for VCO\nThese bits are set and cleared by software to control the multiplication factor of the VCO. \nThese bits can be written only when PLLSAI is disabled. Only half-word and word accesses \nare allowed to write these bits.\nCaution: The software has to set these bits correctly to ensure that the VCO output frequency \nis between 100 and 432 MHz. \nVCO output frequency = VCO input frequency × PLLISAIN with 50 ≤ PLLISAIN ≤ 432\n000000000: PLLISAIN = 0, wrong configuration \n000000001: PLLISAIN = 1, wrong configuration\n...\n000110010: PLLISAIN = 50\n...\n001100011: PLLISAIN = 99 \n001100100: PLLISAIN = 100\n001100101: PLLISAIN = 101\n001100110: PLLISAIN = 102\n... \n110110000: PLLISAIN = 432\n110110001: PLLISAIN = 433, wrong configuration\n... \n111111111: PLLISAIN = 511, wrong configuration \nNote: Multiplication factors ranging from 50 and 99 are possible for VCO input frequency \nhigher than 1 MHz. However care must be taken that the minimum VCO output \nfrequency respects the value specified above. \nBits 5:0 Reserved, must be kept at reset value\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTIMPRE\nSAI1BSRC\nSAI1ASRC\nReserved\nPLLSAIDIVR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPLLSAIDIVQ\nReserved\nPLLS2DIVQ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 210, "page_indices": { "start_index": 520684, "end_index": 522794 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 210 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.25 RCC Dedicated Clock Configuration Register (RCC_DCKCFGR)", 209 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n210/1757\nRM0090 Rev 21\nBits 31:25 Reserved, must be kept at reset value.\nBit 24 TIMPRE: Timers clocks prescalers selection\nThis bit is set and reset by software to control the clock frequency of all the timers connected \nto APB1 and APB2 domain.\n0: If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a \ndivision factor of 1, TIMxCLK = PCLKx. Otherwise, the timer clock frequencies are set to \ntwice to the frequency of the APB domain to which the timers are connected:\nTIMxCLK = 2xPCLKx.\n1:If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a \ndivision factor of 1, 2 or 4, TIMxCLK = HCLK. Otherwise, the timer clock frequencies are set \nto four times to the frequency of the APB domain to which the timers are connected:\nTIMxCLK = 4xPCLKx.\nBits 23:22 SAI1BSRC: SAI1-B clock source selection\nThese bits are set and cleared by software to control the SAI1-B clock frequency.\nThey should be written when the PLLSAI and PLLI2S are disabled.\n00: SAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ\n01: SAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ\n10: SAI1-B clock frequency = Alternate function input frequency\n11: wrong configuration\nBits 21:20 SAI1ASRC: SAI1-A clock source selection\nThese bits are set and cleared by software to control the SAI1-A clock frequency.\nThey should be written when the PLLSAI and PLLI2S are disabled.\n00: SAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ\n01: SAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ\n10: SAI1-A clock frequency = Alternate function input frequency\n11: wrong configuration\nBits 19: 18 Reserved, must be kept at reset value.\nBits 17:16 PLLSAIDIVR: division factor for LCD_CLK\nThese bits are set and cleared by software to control the frequency of LCD_CLK.\nThey should be written only if PLLSAI is disabled.\nLCD_CLK frequency = f(PLLSAI_R) / PLLSAIDIVR with 2 ≤ PLLSAIDIVR ≤ 16\n00: PLLSAIDIVR = /2\n01: PLLSAIDIVR = /4\n10: PLLSAIDIVR = /8\n11: PLLSAIDIVR = /16\nBits 15: 13 Reserved, must be kept at reset value.\n" }, { "page_number": 211, "page_indices": { "start_index": 522794, "end_index": 523773 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 211 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.25 RCC Dedicated Clock Configuration Register (RCC_DCKCFGR)", 209 ] ], "page_content": "RM0090 Rev 21\n211/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\nBits 12:8 PLLSAIDIVQ: PLLSAI division factor for SAI1 clock\nThese bits are set and reset by software to control the SAI1 clock frequency.\nThey should be written only if PLLSAI is disabled.\nSAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ with 1 ≤ PLLSAIDIVQ ≤ 31\n00000: PLLSAIDIVQ = /1\n00001: PLLSAIDIVQ = /2\n00010: PLLSAIDIVQ = /3\n00011: PLLSAIDIVQ = /4\n00100: PLLSAIDIVQ = /5\n...\n11111: PLLSAIDIVQ = /32\nBits 7:5 Reserved, must be kept at reset value.\nBits 4:0 PLLI2SDIVQ: PLLI2S division factor for SAI1 clock\nThese bits are set and reset by software to control the SAI1 clock frequency.\nThey should be written only if PLLI2S is disabled.\nSAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ with 1 <= PLLI2SDIVQ <= 31\n00000: PLLI2SDIVQ = /1\n00001: PLLI2SDIVQ = /2\n00010: PLLI2SDIVQ = /3\n00011: PLLI2SDIVQ = /4\n00100: PLLI2SDIVQ = /5\n...\n11111: PLLI2SDIVQ = /32\n" }, { "page_number": 212, "page_indices": { "start_index": 523773, "end_index": 526764 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 212 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.26 RCC register map", 212 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n212/1757\nRM0090 Rev 21\n6.3.26 \nRCC register map\nTable 34 gives the register map and reset values.\n \nTable 34. RCC register map and reset values for STM32F42xxx and STM32F43xxx\nAddr. \noffset\nRegister \nname\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nRCC_CR\nReserved\nPLL SAIRDY\nPLL SAION\nPLL I2SRDY\nPLL I2SON\nPLL RDY\nPLL ON\nReserved\nCSSON\nHSEBYP\nHSERDY\nHSEON\nHSICAL 7\nHSICAL 6\nHSICAL 5\nHSICAL 4\nHSICAL 3\nHSICAL 2\nHSICAL 1\nHSICAL 0\nHSITRIM 4\nHSITRIM 3\nHSITRIM 2\nHSITRIM 1\nHSITRIM 0\nReserved\nHSIRDY\nHSION\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nX\nX\nX\nX\nX\nX\nX\nX\n1\n0\n0\n0\n0\n0\n1\n1\n0x04\nRCC_\nPLLCFGR\nReserved\nPLLQ 3\nPLLQ 2\nPLLQ 1\nPLLQ 0\nReserved\nPLLSRC\nReserved\nPLLP 1\nPLLP 0\nReserved\nPLLN 8\nPLLN 7\nPLLN 6\nPLLN 5\nPLLN 4\nPLLN 3\nPLLN 2\nPLLN 1\nPLLN 0\nPLLM 5\nPLLM 4\nPLLM 3\nPLLM 2\nPLLM 1\nPLLM 0\nReset value\n0\n1\n0\n0\n0\n0\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0x08\nRCC_CFGR\nMCO2 1\nMCO2 0\nMCO2PRE2\nMCO2PRE1\nMCO2PRE0\nMCO1PRE2\nMCO1PRE1\nMCO1PRE0\nI2SSRC\nMCO1 1\nMCO1 0\nRTCPRE 4\nRTCPRE 3\nRTCPRE 2\nRTCPRE 1\nRTCPRE 0\nPPRE2 2\nPPRE2 1\n PPRE2 0\n PPRE1 2\nPPRE1 1\nPPRE1 0\nReserved\nHPRE 3\nHPRE 2\nHPRE 1\nHPRE 0\nSWS 1\nSWS 0\nSW 1\nSW 0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nRCC_CIR\nReserved\nCSSC\nPLLSAIRDYC\nPLLI2SRDYC\nPLLRDYC\nHSERDYC\nHSIRDYC\nLSERDYC\nLSIRDYC\nReserved\nPLLSAIRDYIE\nPLLI2SRDYIE\nPLLRDYIE\nHSERDYIE\nHSIRDYIE\nLSERDYIE\nLSIRDYIE\nCSSF\nPLLSAIRDYF\nPLLI2SRDYF\nPLLRDYF\nHSERDYF\nHSIRDYF\nLSERDYF\nLSIRDYF\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nRCC_\nAHB1RSTR\nReserved\nOTGHSRST\nReserved\nETHMACRST\nReserved\nDMA2DRST\nDMA2RST\nDMA1RST\nReserved\nCRCRST\nReserved\nGPIOKRST\nGPIOJRST\nGPIOIRST\nGPIOHRST\nGPIOGRST\nGPIOFRST\nGPIOERST\nGPIODRST\nGPIOCRST\nGPIOBRST\nGPIOARST\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nRCC_\nAHB2RSTR\nReserved\nOTGFSRS\nRNGRST\nHSAHRST\nCRYPRST\nReserved\nDCMIRST\nReset value\n0\n0\n0\n0\n0\n0x18\nRCC_\nAHB3RSTR\nReserved\nFMCRS\nReset value\n0\n0x1C\nReserved \nReserved\n0x20\nRCC_\nAPB1RSTR\nUART8RST\nUART7RST\nDACRST\nPWRRST\nReserved\nCAN2RST\nCAN1RST\nReserved\nI2C3RST\nI2C2RST\nI2C1RST\nUART5RST\nUART4RST\nUART3RST\nUART2RST\nReserved\nSPI3RST\nSPI2RST\nReserved\nWWDGRST\nReserved\nTIM14RST\nTIM13RST\nTIM12RST\nTIM7RST\nTIM6RST\nTIM5RST\nTIM4RST\nTIM3RST\nTIM2RST\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x24\nRCC_\nAPB2RSTR\nReserved\nLTDCRST\nReserved\nSAI1RST\nSPI6RST\nSPI5RST\nReserved\nTIM11RST\nTIM10RST\nTIM9RST\nReserved\nSYSCFGRST\nSP45RST\nSPI1RST\nSDIORST\nReserved\nADCRST\nReserved\nUSART6RST\nUSART1RST\nReserved\nTIM8RST\nTIM1RST\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nReserved\nReserved\n0x2C\nReserved\nReserved\n0x30\nRCC_\nAHB1ENR\nReserved\nOTGHSULPIEN\nOTGHSEN\nETHMACPTPEN\nETHMACRXEN\nETHMACTXEN\nETHMACEN\nReserved\nDMA2DEN\nDMA2EN\nDMA1EN\nCCMDATARAMEN\nReserved\nBKPSRAMEN\nReserved\nCRCEN\nReserved\nGPIOKEN\nGPIOJEN\nGPIOIEN\nGPIOHEN\nGPIOGEN\nGPIOFEN\nGPIOEEN\nGPIODEN\nGPIOCEN\nGPIOBEN\nGPIOAEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n" }, { "page_number": 213, "page_indices": { "start_index": 526764, "end_index": 529257 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 213 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.26 RCC register map", 212 ] ], "page_content": "RM0090 Rev 21\n213/1757\nRM0090\nReset and clock control for STM32F42xxx and STM32F43xxx (RCC)\n214\n0x34\nRCC_\nAHB2ENR\nReserved\nOTGFSEN\nRNGEN\nHASHEN\nCRYPEN\nReserved\nDCMIEN\nReset value\n0\n0\n0\n0\n0\n0x38\nRCC_\nAHB3ENR\nReserved\nFMCEN\nReset value\n0\n0x3C\nReserved\nReserved\n0x40\nRCC_\nAPB1ENR\nUART8EN\nUART7EN\nDACEN\nPWREN\nReserved\nCAN2EN\nCAN1EN\nReserved\nI2C3EN\nI2C2EN\nI2C1EN\nUART5EN\nUART4EN\nUSART3EN\nUSART2EN\nReserved\nSPI3EN\nSPI2EN\nReserved\nWWDGEN\nReserved\nTIM14EN\nTIM13EN\nTIM12EN\nTIM7EN\nTIM6EN\nTIM5EN\nTIM4EN\nTIM3EN\nTIM2EN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x44\nRCC_\nAPB2ENR\nReserved\nLTDCEN\nReserved\nSAI1EN\nSPI6EN\nSPI5EN\nReserved\nTIM11EN\nTIM10EN\nTIM9EN\nReserved\nSYSCFGEN\nSPI4EN\nSPI1EN\nSDIOEN\nADC3EN\nADC2EN\nADC1EN\nReserved\nUSART6EN\nUSART1EN\nReserved\nTIM8EN\nTIM1EN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x48\nReserved\nReserved\n0x4C\nReserved\nReserved\n0x50\nRCC_\nAHB1LPENR\nReserved\nOTGHSULPILPEN\nOTGHSLPEN\nETHMACPTPLPEN\nETHMACRXLPEN\nETHMACTXLPEN\nETHMACLPEN\nReserved\nDMA2DLPEN\nDMA2LPEN\nDMA1LPEN\nReserved\nSRAM3LPEN\nBKPSRAMLPEN\nSRAM2LPEN\nSRAM1LPEN\nFLITFLPEN\nReserved\nCRCLPEN\nReserved\nGPIOKLPEN\nGPIOJLPEN\nGPIOILPEN\nGPIOHLPEN\nGPIOGLPEN\nGPIOFLPEN\nGPIOELPEN\nGPIODLPEN\nGPIOCLPEN\nGPIOBLPEN\nGPIOALPEN\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x54\nRCC_\nAHB2LPENR\nReserved\nOTGFSLPEN\nRNGLPEN\nHASHLPEN\nCRYPLPEN\nReserved\nDCMILPEN\nReset value\n1\n1\n1\n1\n1\n0x58\nRCC_\nAHB3LPENR\nReserved\nFMCLPEN\nReset value\n1\n0x5C\nReserved\nReserved\n0x60\nRCC_\nAPB1LPENR\nUART8LPEN\nUART7LPEN\nDACLPEN\nPWRLPEN\nReserved\nCAN2LPEN\nCAN1LPEN\nReserved\nI2C3LPEN\nI2C2LPEN\nI2C1LPEN\nUART5LPEN\nUART4LPEN\nUSART3LPEN\nUSART2LPEN\nReserved\nSPI3LPEN\nSPI2LPEN\nReserved\nWWDGLPEN\nReserved\nTIM14LPEN\nTIM13LPEN\nTIM12LPEN\nTIM7LPEN\nTIM6LPEN\nTIM5LPEN\nTIM4LPEN\nTIM3LPEN\nTIM2LPEN\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x64\nRCC_\nAPB2LPENR\nReserved\nLTDCLPEN\nReserved\nSAI1LPEN\nSPI6LPEN\nSPI5LPEN\nReserved\nTIM11LPEN\nTIM10LPEN\nTIM9LPEN\nReserved\nSYSCFGLPEN\nSPI4LPEN\nSPI1LPEN\nSDIOLPEN\nADC3LPEN\nADC2LPEN\nADC1LPEN\nReserved\nUSART6LPEN\nUSART1LPEN\nReserved\nTIM8LPEN\nTIM1LPEN\nReset value\n1\n1\n0\n1\n1\n0\n1\n1\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x68\nReserved\nReserved\n0x6C\nReserved\nReserved\n0x70\nRCC_BDCR\nReserved\nBDRST\nRTCEN\nReserved\nRTCSEL 1\nRTCSEL 0\nReserved\nLSEBYP\nLSERDY\nLSEON\nReset value\n0\n0\n0\n0\n0\n0\n0\nTable 34. RCC register map and reset values for STM32F42xxx and STM32F43xxx (continued) \nAddr. \noffset\nRegister \nname\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 214, "page_indices": { "start_index": 529257, "end_index": 530342 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 214 }, "toc_details": [ [ 1, "6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)", 152 ], [ 2, "6.3 RCC registers", 163 ], [ 3, "6.3.26 RCC register map", 212 ] ], "page_content": "Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nRM0090\n214/1757\nRM0090 Rev 21\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x74\nRCC_CSR\nLPWRRSTF\nWWDGRSTF\nWDGRSTF\nSFTRSTF\nPORRSTF\nPADRSTF\nBORRSTF\nRMVF\nReserved\nLSIRDY\nLSION\nReset value\n0\n0\n0\n0\n1\n1\n1\n1\n0\n0\n0x78\nReserved\nReserved\n0x7C\nReserved\nReserved\n0x80\nRCC_SSCGR\nSSCGEN\nSPREADSEL\nReserved\nINCSTEP\nMODPER\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x84\nRCC_\nPLLI2SCFGR\nReserved\nPLLI2SRx\nPLLI2SQ\nReserved\nPLLI2SNx\nReserved\nReset value\n0\n1\n0\n0\n1\n0\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\n0x88\nRCC_\nPLLSAICFGR\nReserved\nPLLSAIR\nPLLSAIQ\nReserved\nPLLSAIN\nReserved\nReset value\n0\n1\n0\n0\n1\n0\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\n0x8C\nRCC_\nDCKCFGR\nReserved\nTIMPRE\nSAI1BSCR\nSAI1ASCR\nReserved\nPLLSAIDIVR\nReserved\n0\n0\n0\n0\n0\nReserved\nPLLI2SDIVQ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 34. RCC register map and reset values for STM32F42xxx and STM32F43xxx (continued) \nAddr. \noffset\nRegister \nname\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 215, "page_indices": { "start_index": 530342, "end_index": 531510 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 215 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.1 Reset", 215 ], [ 3, "7.1.1 System reset", 215 ], [ 4, "Software reset", 215 ] ], "page_content": "RM0090 Rev 21\n215/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n7 \nReset and clock control for \nSTM32F405xx/07xx and STM32F415xx/17xx(RCC)\n7.1 \nReset\nThere are three types of reset, defined as system Reset, power Reset and backup domain \nReset. \n7.1.1 \nSystem reset\nA system reset sets all registers to their reset values unless specified otherwise in the \nregister description (see Figure 9).\nA system reset is generated when one of the following events occurs:\n1.\nA low level on the NRST pin (external reset)\n2. \nWindow watchdog end of count condition (WWDG reset)\n3. \nIndependent watchdog end of count condition (IWDG reset)\n4. \nA software reset (SW reset) (see Software reset)\n5. \nLow-power management reset (see Low-power management reset)\nSoftware reset\nThe reset source can be identified by checking the reset flags in the RCC clock control & \nstatus register (RCC_CSR).\nThe SYSRESETREQ bit in Cortex®-M4 with FPU Application Interrupt and Reset Control \nRegister must be set to force a software reset on the device. Refer to the Cortex®-M4 with \nFPU technical reference manual for more details.\n" }, { "page_number": 216, "page_indices": { "start_index": 531510, "end_index": 533633 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 216 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.1 Reset", 215 ], [ 3, "7.1.1 System reset", 215 ], [ 4, "Low-power management reset", 216 ], [ 3, "7.1.2 Power reset", 216 ], [ 3, "7.1.3 Backup domain reset", 216 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n216/1757\nRM0090 Rev 21\nLow-power management reset\nThere are two ways of generating a low-power management reset:\n1.\nReset generated when entering the Standby mode:\nThis type of reset is enabled by resetting the nRST_STDBY bit in the user option bytes. \nIn this case, whenever a Standby mode entry sequence is successfully executed, the \ndevice is reset instead of entering the Standby mode.\n2. \nReset when entering the Stop mode:\nThis type of reset is enabled by resetting the nRST_STOP bit in the user option bytes. \nIn this case, whenever a Stop mode entry sequence is successfully executed, the \ndevice is reset instead of entering the Stop mode.\n7.1.2 \nPower reset\nA power reset is generated when one of the following events occurs: \n1.\nPower-on/power-down reset (POR/PDR reset) or brownout (BOR) reset\n2. \nWhen exiting the Standby mode\nA power reset sets all registers to their reset values except the Backup domain (see \nFigure 9)\nThese sources act on the NRST pin and it is always kept low during the delay phase. The \nRESET service routine vector is fixed at address 0x0000_0004 in the memory map.\nThe system reset signal provided to the device is output on the NRST pin. The pulse \ngenerator guarantees a minimum reset pulse duration of 20 µs for each internal reset \nsource. In case of an external reset, the reset pulse is generated while the NRST pin is \nasserted low.\nFigure 20. Simplified diagram of the reset circuit\nThe Backup domain has two specific resets that affect only the Backup domain (see \nFigure 9).\n7.1.3 \nBackup domain reset\nThe backup domain reset sets all RTC registers, the RCC_BDCR register, and the BRE bit \nof the PWR_CSR register to their reset values. The BKPSRAM is not affected by this reset. \nThe only way of resetting the BKPSRAM is through the Flash interface by requesting a \nprotection level change from 1 to 0.\nNRST\nRPU\nVDD/VDDA\nWWDG reset\nIWDG reset\nPulse\ngenerator\nPower reset\nExternal\nreset\n(min 20 μs)\nSystem reset\nFilter\nSoftware reset\nLow-power management reset\nai16095c\n" }, { "page_number": 217, "page_indices": { "start_index": 533633, "end_index": 534698 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 217 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.2 Clocks", 217 ] ], "page_content": "RM0090 Rev 21\n217/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nA backup domain reset is generated when one of the following events occurs:\n1.\nSoftware reset, triggered by setting the BDRST bit in the RCC Backup domain control \nregister (RCC_BDCR). \n2. \nVDD or VBAT power on, if both supplies have previously been powered off.\nNote:\nThe DBP bit of the PWR_CR register must be set to generate a backup domain reset.\n7.2 \nClocks\nThree different clock sources can be used to drive the system clock (SYSCLK):\n•\nHSI oscillator clock\n•\nHSE oscillator clock\n•\nMain PLL (PLL) clock\nThe devices have the two following secondary clock sources:\n•\n32 kHz low-speed internal RC (LSI RC) which drives the independent watchdog and, \noptionally, the RTC used for Auto-wakeup from the Stop/Standby mode.\n•\n32.768 kHz low-speed external crystal (LSE crystal) which optionally drives the RTC \nclock (RTCCLK)\nEach clock source can be switched on or off independently when it is not used, to optimize \npower consumption.\n" }, { "page_number": 218, "page_indices": { "start_index": 534698, "end_index": 536459 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 218 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.2 Clocks", 217 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n218/1757\nRM0090 Rev 21\nFigure 21. Clock tree\n1.\nFor full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in \nthe device datasheet.\nThe clock controller provides a high degree of flexibility to the application in the choice of the \nexternal crystal or the oscillator to run the core and peripherals at the highest frequency \nand, guarantee the appropriate frequency for peripherals that need a specific clock like \nEthernet, USB OTG FS and HS, I2S and SDIO.\nai16088e\nMII_RMII_SEL in SYSCFG_PMC to Ethernet MAC\nLSE\nETH_MII_TX_CLK_MII\nOTG_HS_ULPI_CK\nPLLI2SCLK\nFCLK Cortex free-\nrunning clock\nAPBx peripheral clocks\nAPBx timer clocks\n48 MHz\nclocks\nUSBHS\nULPI clock\nEthernet PTP clock\nMCO1\nMCO2\nETH_MII_RX_\nCLK_MII\nOSC32_IN\nOSC32_OUT\nto Independent watchdog\nLSE\nLSI\nto RTC\nRTCCLK\nRTCSEL[1:0] \nIWDGCLK\nOSC_IN\nOSC_OUT\nPLLCLK\nHSI\nHSI\nHSE\nSW\nSYSCLK\n168 MHz \nmax \nHCLK \nto AHB bus, core, memory and DMA\n168 MHz max.\nto Cortex System timer\nClock \nenable\nPLL48CK\nI2S clocks\nMACRMIICLK\nMACTXCLK\nMACRXCLK\nPeripheral \nclock enable\nWatchdog \nenable\nRTC \nenable\nPeripheral \nclock enable\n/2to31\nPLLI2S\nSYSCLK\nExt. clock \nI2SSRC\nHSE_RTC\nHSE\nI2S_CKIN\nUSB2.0 PHY\n24 to 60 \nMHz\nPHY Ethernet \n25 to 50 MHz\n/2,20\nPeripheral \nclock enable\nPeripheral \nclock enable\nPeripheral clock \nenable\nPeripheral \nclock enable\n4-26 MHz \nHSE OSC\n/M\n/1 to 5\n/1 to 5\n16 MHz \nHSI RC\nAHB \nPRESC\n/1,2,..512\nPeripheral \nclock enable\n/Q\n/P\n/R\nPLL\nVCO\n/Q\n/P\nPeripheral \nclock enable\n/8\nLSE RC\n32.768 kHz\nAPB \nPRESC\n/1,2,4,8,16\nPeripheral \nclock enable\nif (APBx presc = 1x1\n else x2 \nVCO\nxN\nxN\n/R\nLSE RC\n32 kHz\n" }, { "page_number": 219, "page_indices": { "start_index": 536459, "end_index": 538985 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 219 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.2 Clocks", 217 ], [ 3, "7.2.1 HSE clock", 219 ] ], "page_content": "RM0090 Rev 21\n219/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nSeveral prescalers are used to configure the AHB frequency, the high-speed APB (APB2) \nand the low-speed APB (APB1) domains. The maximum frequency of the AHB domain is \n168 MHz. The maximum allowed frequency of the high-speed APB2 domain is 84 MHz. The \nmaximum allowed frequency of the low-speed APB1 domain is 42 MHz\nAll peripheral clocks are derived from the system clock (SYSCLK) except for:\n•\nThe USB OTG FS clock (48 MHz), the random analog generator (RNG) clock \n(≤48 MHz) and the SDIO clock (≤ 48 MHz) which are coming from a specific output of \nPLL (PLL48CLK)\n•\nThe I2S clock\nTo achieve high-quality audio performance, the I2S clock can be derived either from a \nspecific PLL (PLLI2S) or from an external clock mapped on the I2S_CKIN pin. For \nmore information about I2S clock frequency and precision, refer to Section 28.4.4: \nClock generator.\n•\nThe USB OTG HS (60 MHz) clock which is provided from the external PHY\n•\nThe Ethernet MAC clocks (TX, RX and RMII) which are provided from the external \nPHY. For further information on the Ethernet configuration, please refer to \nSection 33.4.4: MII/RMII selection in the Ethernet peripheral description. When the \nEthernet is used, the AHB clock frequency must be at least 25 MHz.\nThe RCC feeds the external clock of the Cortex System Timer (SysTick) with the AHB clock \n(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock \n(HCLK), configurable in the SysTick control and status register.\nThe timer clock frequencies are automatically set by hardware. There are two cases:\n1.\nIf the APB prescaler is 1, the timer clock frequencies are set to the same frequency as \nthat of the APB domain to which the timers are connected.\n2. \nOtherwise, they are set to twice (×2) the frequency of the APB domain to which the \ntimers are connected.\nFCLK acts as Cortex®-M4 with FPU free-running clock. For more details, refer to the \nCortex®-M4 with FPU technical reference manual.\n7.2.1 \nHSE clock\nThe high speed external clock signal (HSE) can be generated from two possible clock \nsources:\n•\nHSE external crystal/ceramic resonator\n•\nHSE external user clock\nThe resonator and the load capacitors have to be placed as close as possible to the \noscillator pins in order to minimize output distortion and startup stabilization time. The \nloading capacitance values must be adjusted according to the selected oscillator.\n" }, { "page_number": 220, "page_indices": { "start_index": 538985, "end_index": 540764 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 220 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.2 Clocks", 217 ], [ 3, "7.2.1 HSE clock", 219 ], [ 4, "External source (HSE bypass)", 220 ], [ 4, "External crystal/ceramic resonator (HSE crystal)", 220 ], [ 3, "7.2.2 HSI clock", 220 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n220/1757\nRM0090 Rev 21\n \nExternal source (HSE bypass)\nIn this mode, an external clock source must be provided. You select this mode by setting the \nHSEBYP and HSEON bits in the RCC clock control register (RCC_CR). The external clock \nsignal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the \nOSC_OUT pin should be left HI-Z. See Figure 22.\nExternal crystal/ceramic resonator (HSE crystal)\nThe HSE has the advantage of producing a very accurate rate on the main clock.\nThe associated hardware configuration is shown in Figure 22. Refer to the electrical \ncharacteristics section of the datasheet for more details.\nThe HSERDY flag in the RCC clock control register (RCC_CR) indicates if the high-speed \nexternal oscillator is stable or not. At startup, the clock is not released until this bit is set by \nhardware. An interrupt can be generated if enabled in the RCC clock interrupt register \n(RCC_CIR).\nThe HSE Crystal can be switched on and off using the HSEON bit in the RCC clock control \nregister (RCC_CR).\n7.2.2 \nHSI clock\nThe HSI clock signal is generated from an internal 16 MHz RC oscillator and can be used \ndirectly as a system clock, or used as PLL input.\nThe HSI RC oscillator has the advantage of providing a clock source at low cost (no external \ncomponents). It also has a faster startup time than the HSE crystal oscillator however, even \nwith calibration the frequency is less accurate than an external crystal oscillator or ceramic \nresonator. \nFigure 22. HSE/ LSE clock sources\nHardware configuration\nExternal clock\nCrystal/ceramic \nresonators\nOSC_OUT\nExternal\nsource\n(HI-Z)\nOSC_IN\nOSC_OUT\nLoad\ncapacitors\nCL2\nCL1\n" }, { "page_number": 221, "page_indices": { "start_index": 540764, "end_index": 543668 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 221 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.2 Clocks", 217 ], [ 3, "7.2.2 HSI clock", 220 ], [ 4, "Calibration", 221 ], [ 3, "7.2.3 PLL configuration", 221 ], [ 3, "7.2.4 LSE clock", 221 ] ], "page_content": "RM0090 Rev 21\n221/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nCalibration\nRC oscillator frequencies can vary from one chip to another due to manufacturing process \nvariations, this is why each device is factory calibrated by ST for 1% accuracy at TA= 25 °C.\nAfter reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the RCC clock \ncontrol register (RCC_CR). \nIf the application is subject to voltage or temperature variations this may affect the RC \noscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0] \nbits in the RCC clock control register (RCC_CR).\nThe HSIRDY flag in the RCC clock control register (RCC_CR) indicates if the HSI RC is \nstable or not. At startup, the HSI RC output clock is not released until this bit is set by \nhardware. \nThe HSI RC can be switched on and off using the HSION bit in the RCC clock control \nregister (RCC_CR).\nThe HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal \noscillator fails. Refer to Section 7.2.7: Clock security system (CSS) on page 222.\n7.2.3 \nPLL configuration\nThe STM32F4xx devices feature two PLLs:\n•\nA main PLL (PLL) clocked by the HSE or HSI oscillator and featuring two different \noutput clocks:\n–\nThe first output is used to generate the high speed system clock (up to 168 MHz)\n–\nThe second output is used to generate the clock for the USB OTG FS (48 MHz), \nthe random analog generator (≤48 MHz) and the SDIO (≤ 48 MHz). \n•\nA dedicated PLL (PLLI2S) used to generate an accurate clock to achieve high-quality \naudio performance on the I2S interface. \nSince the main-PLL configuration parameters cannot be changed once PLL is enabled, it is \nrecommended to configure PLL before enabling it (selection of the HSI or HSE oscillator as \nPLL clock source, and configuration of division factors M, N, P, and Q). \nThe PLLI2S uses the same input clock as PLL (PLLM[5:0] and PLLSRC bits are common to \nboth PLLs). However, the PLLI2S has dedicated enable/disable and division factors (N and \nR) configuration bits. Once the PLLI2S is enabled, the configuration parameters cannot be \nchanged.\nThe two PLLs are disabled by hardware when entering Stop and Standby modes, or when \nan HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock. RCC \nPLL configuration register (RCC_PLLCFGR) and RCC clock configuration register \n(RCC_CFGR) can be used to configure PLL and PLLI2S, respectively.\n7.2.4 \nLSE clock\nThe LSE clock is generated from a 32.768 kHz low-speed external crystal or ceramic \nresonator. It has the advantage providing a low-power but highly accurate clock source to \nthe real-time clock peripheral (RTC) for clock/calendar or other timing functions. \nThe LSE oscillator is switched on and off using the LSEON bit in RCC Backup domain \ncontrol register (RCC_BDCR). \n" }, { "page_number": 222, "page_indices": { "start_index": 543668, "end_index": 546865 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 222 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.2 Clocks", 217 ], [ 3, "7.2.4 LSE clock", 221 ], [ 4, "External source (LSE bypass)", 222 ], [ 3, "7.2.5 LSI clock", 222 ], [ 3, "7.2.6 System clock (SYSCLK) selection", 222 ], [ 3, "7.2.7 Clock security system (CSS)", 222 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n222/1757\nRM0090 Rev 21\nThe LSERDY flag in the RCC Backup domain control register (RCC_BDCR) indicates if the \nLSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released \nuntil this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock \ninterrupt register (RCC_CIR).\nExternal source (LSE bypass)\nIn this mode, an external clock source must be provided. It must have a frequency up to \n1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the RCC Backup \ndomain control register (RCC_BDCR). The external clock signal (square, sinus or triangle) \nwith ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be \nleft HI-Z. See Figure 22.\n7.2.5 \nLSI clock\nThe LSI RC acts as an low-power clock source that can be kept running in Stop and \nStandby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The \nclock frequency is around 32 kHz. For more details, refer to the electrical characteristics \nsection of the datasheets.\nThe LSI RC can be switched on and off using the LSION bit in the RCC clock control & \nstatus register (RCC_CSR).\nThe LSIRDY flag in the RCC clock control & status register (RCC_CSR) indicates if the low-\nspeed internal oscillator is stable or not. At startup, the clock is not released until this bit is \nset by hardware. An interrupt can be generated if enabled in the RCC clock interrupt register \n(RCC_CIR).\n7.2.6 \nSystem clock (SYSCLK) selection\nAfter a system reset, the HSI oscillator is selected as the system clock. When a clock source \nis used directly or through PLL as the system clock, it is not possible to stop it.\nA switch from one clock source to another occurs only if the target clock source is ready \n(clock stable after startup delay or PLL locked). If a clock source that is not yet ready is \nselected, the switch occurs when the clock source is ready. Status bits in the RCC clock \ncontrol register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently \nused as the system clock.\n7.2.7 \nClock security system (CSS)\nThe clock security system can be activated by software. In this case, the clock detector is \nenabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.\nIf a failure is detected on the HSE clock, this oscillator is automatically disabled, a clock \nfailure event is sent to the break inputs of advanced-control timers TIM1 and TIM8, and an \ninterrupt is generated to inform the software about the failure (clock security system \ninterrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the \nCortex®-M4 with FPU NMI (non-maskable interrupt) exception vector.\nNote:\nWhen the CSS is enabled, if the HSE clock happens to fail, the CSS generates an interrupt, \nwhich causes the automatic generation of an NMI. The NMI is executed indefinitely unless \nthe CSS interrupt pending bit is cleared. As a consequence, the application has to clear the \nCSS interrupt in the NMI ISR by setting the CSSC bit in the Clock interrupt register \n(RCC_CIR).\n" }, { "page_number": 223, "page_indices": { "start_index": 546865, "end_index": 549684 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 223 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.2 Clocks", 217 ], [ 3, "7.2.8 RTC/AWU clock", 223 ], [ 3, "7.2.9 Watchdog clock", 223 ] ], "page_content": "RM0090 Rev 21\n223/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nIf the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that \nit is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is \ndetected, then the system clock switches to the HSI oscillator and the HSE oscillator is \ndisabled. \nIf the HSE oscillator clock was the clock source of PLL used as the system clock when the \nfailure occurred, PLL is also disabled. In this case, if the PLLI2S was enabled, it is also \ndisabled when the HSE fails. \n7.2.8 \nRTC/AWU clock\nOnce the RTCCLK clock source has been selected, the only possible way of modifying the \nselection is to reset the power domain.\nThe RTCCLK clock source can be either the HSE 1 MHz (HSE divided by a programmable \nprescaler), the LSE or the LSI clock. This is selected by programming the RTCSEL[1:0] bits \nin the RCC Backup domain control register (RCC_BDCR) and the RTCPRE[4:0] bits in RCC \nclock configuration register (RCC_CFGR). This selection cannot be modified without \nresetting the Backup domain.\nIf the LSE is selected as the RTC clock, the RTC operates normally if the backup or the \nsystem supply disappears. If the LSI is selected as the AWU clock, the AWU state is not \nguaranteed if the system supply disappears. If the HSE oscillator divided by a value \nbetween 2 and 31 is used as the RTC clock, the RTC state is not guaranteed if the backup \nor the system supply disappears.\nThe LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. As a \nconsequence:\n•\nIf LSE is selected as the RTC clock:\n–\nThe RTC continues to work even if the VDD supply is switched off, provided the \nVBAT supply is maintained. \n•\nIf LSI is selected as the Auto-wakeup unit (AWU) clock:\n–\nThe AWU state is not guaranteed if the VDD supply is powered off. Refer to \nSection 7.2.5: LSI clock on page 222 for more details on LSI calibration.\n•\nIf the HSE clock is used as the RTC clock:\n–\nThe RTC state is not guaranteed if the VDD supply is powered off or if the internal \nvoltage regulator is powered off (removing power from the 1.2 V domain).\nNote:\nTo read the RTC calendar register when the APB1 clock frequency is less than seven times \nthe RTC clock frequency (fAPB1 < 7xfRTCLCK), the software must read the calendar time and \ndate registers twice. The data are correct if the second read access to RTC_TR gives the \nsame result than the first one. Otherwise a third read access must be performed.\n7.2.9 \nWatchdog clock\nIf the independent watchdog (IWDG) is started by either hardware option or software \naccess, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator \ntemporization, the clock is provided to the IWDG.\n" }, { "page_number": 224, "page_indices": { "start_index": 549684, "end_index": 551921 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 224 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.2 Clocks", 217 ], [ 3, "7.2.10 Clock-out capability", 224 ], [ 3, "7.2.11 Internal/external clock measurement using TIM5/TIM11", 224 ], [ 4, "Internal/external clock measurement using TIM5 channel4", 224 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n224/1757\nRM0090 Rev 21\n7.2.10 \nClock-out capability\nTwo microcontroller clock output (MCO) pins are available:\n•\nMCO1\nYou can output four different clock sources onto the MCO1 pin (PA8) using the \nconfigurable prescaler (from 1 to 5):\n–\nHSI clock\n–\nLSE clock\n–\nHSE clock\n–\nPLL clock\nThe desired clock source is selected using the MCO1PRE[2:0] and MCO1[1:0] bits in \nthe RCC clock configuration register (RCC_CFGR).\n•\nMCO2\nYou can output four different clock sources onto the MCO2 pin (PC9) using the \nconfigurable prescaler (from 1 to 5):\n–\nHSE clock\n–\nPLL clock\n–\nSystem clock (SYSCLK)\n–\nPLLI2S clock\nThe desired clock source is selected using the MCO2PRE[2:0] and MCO2 bits in the \nRCC clock configuration register (RCC_CFGR).\nFor the different MCO pins, the corresponding GPIO port has to be programmed in alternate \nfunction mode.\nThe selected clock to output onto MCO must not exceed 100 MHz (the maximum I/O \nspeed).\n7.2.11 \nInternal/external clock measurement using TIM5/TIM11\nIt is possible to indirectly measure the frequencies of all on-board clock source generators \nby means of the input capture of TIM5 channel4 and TIM11 channel1 as shown in Figure 23 \nand Figure 24.\nInternal/external clock measurement using TIM5 channel4\nTIM5 has an input multiplexer which allows choosing whether the input capture is triggered \nby the I/O or by an internal clock. This selection is performed through the TI4_RMP [1:0] bits \nin the TIM5_OR register.\nThe primary purpose of having the LSE connected to the channel4 input capture is to be \nable to precisely measure the HSI (this requires to have the HSI used as the system clock \nsource). The number of HSI clock counts between consecutive edges of the LSE signal \nprovides a measurement of the internal clock period. Taking advantage of the high precision \nof LSE crystals (typically a few tens of ppm) we can determine the internal clock frequency \nwith the same resolution, and trim the source to compensate for manufacturing-process \nand/or temperature- and voltage-related frequency deviations.\nThe HSI oscillator has dedicated, user-accessible calibration bits for this purpose.\n" }, { "page_number": 225, "page_indices": { "start_index": 551921, "end_index": 554189 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 225 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.2 Clocks", 217 ], [ 3, "7.2.11 Internal/external clock measurement using TIM5/TIM11", 224 ], [ 4, "Internal/external clock measurement using TIM11 channel1", 225 ] ], "page_content": "RM0090 Rev 21\n225/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nThe basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the \nprecision is therefore tightly linked to the ratio between the two clock sources. The greater \nthe ratio, the better the measurement.\nIt is also possible to measure the LSI frequency: this is useful for applications that do not \nhave a crystal. The ultralow-power LSI oscillator has a large manufacturing process \ndeviation: by measuring it versus the HSI clock source, it is possible to determine its \nfrequency with the precision of the HSI. The measured value can be used to have more \naccurate RTC time base timeouts (when LSI is used as the RTC clock source) and/or an \nIWDG timeout with an acceptable accuracy.\nUse the following procedure to measure the LSI frequency:\n1.\nEnable the TIM5 timer and configure channel4 in Input capture mode.\n2. \nSet the TI4_RMP bits in the TIM5_OR register to 0x01 to connect the LSI clock \ninternally to TIM5 channel4 input capture for calibration purposes.\n3. \nMeasure the LSI clock frequency using the TIM5 capture/compare 4 event or interrupt.\n4. \nUse the measured LSI frequency to update the prescaler of the RTC depending on the \ndesired time base and/or to compute the IWDG timeout.\nFigure 23. Frequency measurement with TIM5 in Input capture mode\nInternal/external clock measurement using TIM11 channel1\nTIM11 has an input multiplexer which allows choosing whether the input capture is triggered \nby the I/O or by an internal clock. This selection is performed through TI1_RMP [1:0] bits in \nthe TIM11_OR register. The HSE_RTC clock (HSE divided by a programmable prescaler) is \nconnected to channel 1 input capture to have a rough indication of the external crystal \nfrequency. This requires that the HSI is the system clock source. This can be useful for \ninstance to ensure compliance with the IEC 60730/IEC 61335 standards which require to be \nable to determine harmonic or subharmonic frequencies (–50/+100% deviations). \nFigure 24. Frequency measurement with TIM11 in Input capture mode\nTIM5\nTI4\nTI4_RMP[1:0]\nGPIO\nRTC_WakeUp_IT\nLSE\nLSI\nai17741V2\nTIM11\nTI1\nTI1_RMP[1:0]\nGPIO\nHSE_RTC(1 MHz)\nai18433\n" }, { "page_number": 226, "page_indices": { "start_index": 554189, "end_index": 556060 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 226 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.1 RCC clock control register (RCC_CR)", 226 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n226/1757\nRM0090 Rev 21\n7.3 \nRCC registers\nRefer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in \nregister descriptions.\n7.3.1 \nRCC clock control register (RCC_CR)\nAddress offset: 0x00\nReset value: 0x0000 XX83 where X is undefined.\nAccess: no wait state, word, half-word and byte access\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPLLI2S\nRDY\nPLLI2S\nON\nPLLRD\nY\nPLLON\nReserved\nCSS \nON\nHSE \nBYP\nHSE\nRDY\nHSE \nON\nr\nrw\nr\nrw\nrw\nrw\nr\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nHSICAL[7:0]\nHSITRIM[4:0]\nRes.\nHSI \nRDY\nHSION\nr\nr\nr\nr\nr\nr\nr\nr\nrw\nrw\nrw\nrw\nrw\nr\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBit 27 PLLI2SRDY: PLLI2S clock ready flag\nSet by hardware to indicate that the PLLI2S is locked.\n0: PLLI2S unlocked\n1: PLLI2S locked\nBit 26 PLLI2SON: PLLI2S enable\nSet and cleared by software to enable PLLI2S.\nCleared by hardware when entering Stop or Standby mode. \n0: PLLI2S OFF\n1: PLLI2S ON\nBit 25 PLLRDY: Main PLL (PLL) clock ready flag\nSet by hardware to indicate that PLL is locked.\n0: PLL unlocked\n1: PLL locked\nBit 24 PLLON: Main PLL (PLL) enable\nSet and cleared by software to enable PLL.\nCleared by hardware when entering Stop or Standby mode. This bit cannot be reset if PLL \nclock is used as the system clock.\n0: PLL OFF\n1: PLL ON\nBits 23:20 Reserved, must be kept at reset value.\nBit 19 CSSON: Clock security system enable\nSet and cleared by software to enable the clock security system. When CSSON is set, the \nclock detector is enabled by hardware when the HSE oscillator is ready, and disabled by \nhardware if an oscillator failure is detected.\n0: Clock security system OFF (Clock detector OFF)\n1: Clock security system ON (Clock detector ON if HSE oscillator is stable, OFF if not)\n" }, { "page_number": 227, "page_indices": { "start_index": 556060, "end_index": 558134 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 227 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.1 RCC clock control register (RCC_CR)", 226 ] ], "page_content": "RM0090 Rev 21\n227/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 18 HSEBYP: HSE clock bypass\nSet and cleared by software to bypass the oscillator with an external clock. The external \nclock must be enabled with the HSEON bit, to be used by the device.\nThe HSEBYP bit can be written only if the HSE oscillator is disabled.\n0: HSE oscillator not bypassed\n1: HSE oscillator bypassed with an external clock\nBit 17 HSERDY: HSE clock ready flag\nSet by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is cleared, \nHSERDY goes low after 6 HSE oscillator clock cycles.\n0: HSE oscillator not ready\n1: HSE oscillator ready\nBit 16 HSEON: HSE clock enable\nSet and cleared by software.\nCleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This \nbit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.\n0: HSE oscillator OFF\n1: HSE oscillator ON\nBits 15:8 HSICAL[7:0]: Internal high-speed clock calibration\nThese bits are initialized automatically at startup.\nBits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming\nThese bits provide an additional user-programmable trimming value that is added to the \nHSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature \nthat influence the frequency of the internal HSI RC.\nBit 2 Reserved, must be kept at reset value.\nBit 1 HSIRDY: Internal high-speed clock ready flag\nSet by hardware to indicate that the HSI oscillator is stable. After the HSION bit is cleared, \nHSIRDY goes low after 6 HSI clock cycles.\n0: HSI oscillator not ready\n1: HSI oscillator ready\nBit 0 HSION: Internal high-speed clock enable\nSet and cleared by software.\nSet by hardware to force the HSI oscillator ON when leaving the Stop or Standby mode or in \ncase of a failure of the HSE oscillator used directly or indirectly as the system clock. This bit \ncannot be cleared if the HSI is used directly or indirectly as the system clock.\n0: HSI oscillator OFF\n1: HSI oscillator ON\n" }, { "page_number": 228, "page_indices": { "start_index": 558134, "end_index": 560092 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 228 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.2 RCC PLL configuration register (RCC_PLLCFGR)", 228 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n228/1757\nRM0090 Rev 21\n7.3.2 \nRCC PLL configuration register (RCC_PLLCFGR)\nAddress offset: 0x04\nReset value: 0x2400 3010\nAccess: no wait state, word, half-word and byte access.\nThis register is used to configure the PLL clock outputs according to the formulas:\n•\nf(VCO clock) = f(PLL clock input) × (PLLN / PLLM)\n•\nf(PLL general clock output) = f(VCO clock) / PLLP\n•\nf(USB OTG FS, SDIO, RNG clock output) = f(VCO clock) / PLLQ\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPLLQ3\nPLLQ2\nPLLQ1\nPLLQ0\nReserv\ned\nPLLSR\nC\nReserved\nPLLP1\nPLLP0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserv\ned\nPLLN\nPLLM5\nPLLM4\nPLLM3\nPLLM2\nPLLM1\nPLLM0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBits 27:24 PLLQ: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator \nclocks\nSet and cleared by software to control the frequency of USB OTG FS clock, the random \nnumber generator clock and the SDIO clock. These bits should be written only if PLL is \ndisabled.\nCaution: The USB OTG FS requires a 48 MHz clock to work correctly. The SDIO and the \nrandom number generator need a frequency lower than or equal to 48 MHz to work \ncorrectly.\nUSB OTG FS clock frequency = VCO frequency / PLLQ with 2 ≤ PLLQ ≤ 15\n0000: PLLQ = 0, wrong configuration\n0001: PLLQ = 1, wrong configuration\n0010: PLLQ = 2\n0011: PLLQ = 3\n0100: PLLQ = 4\n...\n1111: PLLQ = 15\nBit 23 Reserved, must be kept at reset value.\nBit 22 PLLSRC: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source\nSet and cleared by software to select PLL and PLLI2S clock source. This bit can be written \nonly when PLL and PLLI2S are disabled.\n0: HSI clock selected as PLL and PLLI2S clock entry\n1: HSE oscillator clock selected as PLL and PLLI2S clock entry\nBits 21:18 Reserved, must be kept at reset value.\n" }, { "page_number": 229, "page_indices": { "start_index": 560092, "end_index": 562264 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 229 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.2 RCC PLL configuration register (RCC_PLLCFGR)", 228 ] ], "page_content": "RM0090 Rev 21\n229/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBits 17:16 PLLP: Main PLL (PLL) division factor for main system clock\nSet and cleared by software to control the frequency of the general PLL output clock. These \nbits can be written only if PLL is disabled.\nCaution: The software has to set these bits correctly not to exceed 168 MHz on this domain.\nPLL output clock frequency = VCO frequency / PLLP with PLLP = 2, 4, 6, or 8\n00: PLLP = 2\n01: PLLP = 4\n10: PLLP = 6\n11: PLLP = 8\nBits 14:6 PLLN: Main PLL (PLL) multiplication factor for VCO\nSet and cleared by software to control the multiplication factor of the VCO. These bits can \nbe written only when PLL is disabled. Only half-word and word accesses are allowed to \nwrite these bits.\nCaution: The software has to set these bits correctly to ensure that the VCO output \nfrequency is between 100 and 432 MHz. \nVCO output frequency = VCO input frequency × PLLN with 50 ≤ PLLN ≤ 432\n000000000: PLLN = 0, wrong configuration \n000000001: PLLN = 1, wrong configuration\n...\n000110010: PLLN = 50\n...\n001100011: PLLN = 99\n001100100: PLLN = 100\n... \n110110000: PLLN = 432\n110110001: PLLN = 433, wrong configuration\n... \n111111111: PLLN = 511, wrong configuration \nNote: Multiplication factors ranging from 50 and 99 are possible for VCO input frequency \nhigher than 1 MHz. However care must be taken that the minimum VCO output \nfrequency respects the value specified above. \nBits 5:0 PLLM: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock\nSet and cleared by software to divide the PLL and PLLI2S input clock before the VCO. \nThese bits can be written only when the PLL and PLLI2S are disabled.\nCaution: The software has to set these bits correctly to ensure that the VCO input frequency \nranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit \nPLL jitter. \nVCO input frequency = PLL input clock frequency / PLLM with 2 ≤ PLLM ≤ 63\n000000: PLLM = 0, wrong configuration\n000001: PLLM = 1, wrong configuration\n000010: PLLM = 2\n000011: PLLM = 3\n000100: PLLM = 4\n...\n111110: PLLM = 62\n111111: PLLM = 63\n" }, { "page_number": 230, "page_indices": { "start_index": 562264, "end_index": 564445 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 230 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.3 RCC clock configuration register (RCC_CFGR)", 230 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n230/1757\nRM0090 Rev 21\n7.3.3 \nRCC clock configuration register (RCC_CFGR)\nAddress offset: 0x08\nReset value: 0x0000 0000\nAccess: 0 ≤ wait state ≤ 2, word, half-word and byte access\n1 or 2 wait states inserted only if the access occurs during a clock source switch.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMCO2\nMCO2 PRE[2:0]\nMCO1 PRE[2:0]\nI2SSC\nR\nMCO1\nRTCPRE[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPPRE2[2:0]\nPPRE1[2:0]\nReserved\nHPRE[3:0]\nSWS1\nSWS0\nSW1\nSW0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nr\nr\nrw\nrw\nBits 31:30 MCO2[1:0]: Microcontroller clock output 2\nSet and cleared by software. Clock source selection may generate glitches on MCO2. It is \nhighly recommended to configure these bits only after reset before enabling the external \noscillators and the PLLs.\n00: System clock (SYSCLK) selected\n01: PLLI2S clock selected\n10: HSE oscillator clock selected\n11: PLL clock selected\nBits 27:29 MCO2PRE: MCO2 prescaler\nSet and cleared by software to configure the prescaler of the MCO2. Modification of this \nprescaler may generate glitches on MCO2. It is highly recommended to change this \nprescaler only after reset before enabling the external oscillators and the PLLs.\n0xx: no division\n100: division by 2\n101: division by 3\n110: division by 4\n111: division by 5\nBits 24:26 MCO1PRE: MCO1 prescaler\nSet and cleared by software to configure the prescaler of the MCO1. Modification of this \nprescaler may generate glitches on MCO1. It is highly recommended to change this \nprescaler only after reset before enabling the external oscillators and the PLL.\n0xx: no division\n100: division by 2\n101: division by 3\n110: division by 4\n111: division by 5\nBit 23 I2SSRC: I2S clock selection\nSet and cleared by software. This bit allows to select the I2S clock source between the \nPLLI2S clock and the external clock. It is highly recommended to change this bit only after \nreset and before enabling the I2S module.\n0: PLLI2S clock used as I2S clock source\n1: External clock mapped on the I2S_CKIN pin used as I2S clock source\n" }, { "page_number": 231, "page_indices": { "start_index": 564445, "end_index": 566335 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 231 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.3 RCC clock configuration register (RCC_CFGR)", 230 ] ], "page_content": "RM0090 Rev 21\n231/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBits 22:21 MCO1: Microcontroller clock output 1\nSet and cleared by software. Clock source selection may generate glitches on MCO1. It is \nhighly recommended to configure these bits only after reset before enabling the external \noscillators and PLL.\n00: HSI clock selected\n01: LSE oscillator selected\n10: HSE oscillator clock selected\n11: PLL clock selected\nBits 20:16 RTCPRE: HSE division factor for RTC clock\nSet and cleared by software to divide the HSE clock input clock to generate a 1 MHz clock \nfor RTC.\nCaution: The software has to set these bits correctly to ensure that the clock supplied to the \nRTC is 1 MHz. These bits must be configured if needed before selecting the RTC \nclock source.\n00000: no clock\n00001: no clock\n00010: HSE/2\n00011: HSE/3\n00100: HSE/4\n...\n11110: HSE/30\n11111: HSE/31\nBits 15:13 PPRE2: APB high-speed prescaler (APB2)\nSet and cleared by software to control APB high-speed clock division factor.\nCaution: The software has to set these bits correctly not to exceed 84 MHz on this domain. \nThe clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after \nPPRE2 write.\n0xx: AHB clock not divided\n100: AHB clock divided by 2\n101: AHB clock divided by 4\n110: AHB clock divided by 8\n111: AHB clock divided by 16\nBits 12:10 PPRE1: APB Low speed prescaler (APB1)\nSet and cleared by software to control APB low-speed clock division factor.\nCaution: The software has to set these bits correctly not to exceed 42 MHz on this domain. \nThe clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after \nPPRE1 write.\n0xx: AHB clock not divided\n100: AHB clock divided by 2\n101: AHB clock divided by 4\n110: AHB clock divided by 8\n111: AHB clock divided by 16\nBits 9:8 Reserved, must be kept at reset value.\n" }, { "page_number": 232, "page_indices": { "start_index": 566335, "end_index": 568247 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 232 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.4 RCC clock interrupt register (RCC_CIR)", 232 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n232/1757\nRM0090 Rev 21\n7.3.4 \nRCC clock interrupt register (RCC_CIR)\nAddress offset: 0x0C\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n \nBits 7:4 HPRE: AHB prescaler\nSet and cleared by software to control AHB clock division factor.\nCaution: The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after \nHPRE write.\nCaution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.\n0xxx: system clock not divided\n1000: system clock divided by 2\n1001: system clock divided by 4\n1010: system clock divided by 8\n1011: system clock divided by 16\n1100: system clock divided by 64\n1101: system clock divided by 128\n1110: system clock divided by 256\n1111: system clock divided by 512\nBits 3:2 SWS: System clock switch status\nSet and cleared by hardware to indicate which clock source is used as the system clock.\n00: HSI oscillator used as the system clock\n01: HSE oscillator used as the system clock\n10: PLL used as the system clock\n11: not applicable\nBits 1:0 SW: System clock switch\nSet and cleared by software to select the system clock source.\nSet by hardware to force the HSI selection when leaving the Stop or Standby mode or in \ncase of failure of the HSE oscillator used directly or indirectly as the system clock.\n00: HSI oscillator selected as system clock\n01: HSE oscillator selected as system clock\n10: PLL selected as system clock\n11: not allowed\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nCSSC\nReserv\ned\nPLLI2S \nRDYC\nPLL \nRDYC\nHSE \nRDYC\nHSI \nRDYC\nLSE \nRDYC\nLSI \nRDYC\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPLLI2S \nRDYIE\nPLL \nRDYIE\nHSE \nRDYIE\nHSI \nRDYIE\nLSE \nRDYIE\nLSI \nRDYIE\nCSSF\nReserv\ned\nPLLI2S\nRDYF\nPLL \nRDYF\nHSE \nRDYF\nHSI \nRDYF\nLSE \nRDYF\nLSI \nRDYF\nrw\nrw\nrw\nrw\nrw\nrw\nr\nr\nr\nr\nr\nr\nr\n" }, { "page_number": 233, "page_indices": { "start_index": 568247, "end_index": 570057 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 233 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.4 RCC clock interrupt register (RCC_CIR)", 232 ] ], "page_content": "RM0090 Rev 21\n233/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n \nBits 31:24 Reserved, must be kept at reset value.\nBit 23 CSSC: Clock security system interrupt clear\nThis bit is set by software to clear the CSSF flag.\n0: No effect\n1: Clear CSSF flag\nBits 22 Reserved, must be kept at reset value.\nBit 21 PLLI2SRDYC: PLLI2S ready interrupt clear\nThis bit is set by software to clear the PLLI2SRDYF flag.\n0: No effect\n1: PLLI2SRDYF cleared\nBit 20 PLLRDYC: Main PLL(PLL) ready interrupt clear\nThis bit is set by software to clear the PLLRDYF flag.\n0: No effect\n1: PLLRDYF cleared\nBit 19 HSERDYC: HSE ready interrupt clear\nThis bit is set by software to clear the HSERDYF flag.\n0: No effect\n1: HSERDYF cleared\nBit 18 HSIRDYC: HSI ready interrupt clear\nThis bit is set software to clear the HSIRDYF flag.\n0: No effect\n1: HSIRDYF cleared\nBit 17 LSERDYC: LSE ready interrupt clear\nThis bit is set by software to clear the LSERDYF flag.\n0: No effect\n1: LSERDYF cleared\nBit 16 LSIRDYC: LSI ready interrupt clear\nThis bit is set by software to clear the LSIRDYF flag.\n0: No effect\n1: LSIRDYF cleared\nBits 15:12 Reserved, must be kept at reset value.\nBit 13 PLLI2SRDYIE: PLLI2S ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by PLLI2S lock.\n0: PLLI2S lock interrupt disabled\n1: PLLI2S lock interrupt enabled\nBit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by PLL lock.\n0: PLL lock interrupt disabled\n1: PLL lock interrupt enabled\nBit 11 HSERDYIE: HSE ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by the HSE oscillator \nstabilization.\n0: HSE ready interrupt disabled\n1: HSE ready interrupt enabled\n" }, { "page_number": 234, "page_indices": { "start_index": 570057, "end_index": 571889 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 234 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.4 RCC clock interrupt register (RCC_CIR)", 232 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n234/1757\nRM0090 Rev 21\nBit 10 HSIRDYIE: HSI ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by the HSI oscillator \nstabilization.\n0: HSI ready interrupt disabled\n1: HSI ready interrupt enabled\nBit 9 LSERDYIE: LSE ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by the LSE oscillator \nstabilization.\n0: LSE ready interrupt disabled\n1: LSE ready interrupt enabled\nBit 8 LSIRDYIE: LSI ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by LSI oscillator \nstabilization.\n0: LSI ready interrupt disabled\n1: LSI ready interrupt enabled\nBit 7 CSSF: Clock security system interrupt flag\nSet by hardware when a failure is detected in the HSE oscillator.\nCleared by software setting the CSSC bit.\n0: No clock security interrupt caused by HSE clock failure\n1: Clock security interrupt caused by HSE clock failure\nBits 6 Reserved, must be kept at reset value.\nBit 5 PLLI2SRDYF: PLLI2S ready interrupt flag\nSet by hardware when the PLLI2S locks and PLLI2SRDYIE is set.\nCleared by software setting the PLLRI2SDYC bit.\n0: No clock ready interrupt caused by PLLI2S lock\n1: Clock ready interrupt caused by PLLI2S lock\nBit 4 PLLRDYF: Main PLL (PLL) ready interrupt flag\nSet by hardware when PLL locks and PLLRDYIE is set.\nCleared by software setting the PLLRDYC bit.\n0: No clock ready interrupt caused by PLL lock\n1: Clock ready interrupt caused by PLL lock\nBit 3 HSERDYF: HSE ready interrupt flag\nSet by hardware when External High Speed clock becomes stable and HSERDYIE is set.\nCleared by software setting the HSERDYC bit.\n0: No clock ready interrupt caused by the HSE oscillator\n1: Clock ready interrupt caused by the HSE oscillator\n" }, { "page_number": 235, "page_indices": { "start_index": 571889, "end_index": 573779 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 235 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)", 235 ] ], "page_content": "RM0090 Rev 21\n235/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n7.3.5 \nRCC AHB1 peripheral reset register (RCC_AHB1RSTR)\nAddress offset: 0x10\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \nBit 2 HSIRDYF: HSI ready interrupt flag\nSet by hardware when the Internal High Speed clock becomes stable and HSIRDYIE is \nset.\nCleared by software setting the HSIRDYC bit.\n0: No clock ready interrupt caused by the HSI oscillator\n1: Clock ready interrupt caused by the HSI oscillator\nBit 1 LSERDYF: LSE ready interrupt flag\nSet by hardware when the External Low Speed clock becomes stable and LSERDYIE is \nset.\nCleared by software setting the LSERDYC bit.\n0: No clock ready interrupt caused by the LSE oscillator\n1: Clock ready interrupt caused by the LSE oscillator\nBit 0 LSIRDYF: LSI ready interrupt flag\nSet by hardware when the internal low speed clock becomes stable and LSIRDYIE is set.\nCleared by software setting the LSIRDYC bit.\n0: No clock ready interrupt caused by the LSI oscillator\n1: Clock ready interrupt caused by the LSI oscillator\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nOTGH\nS\nRST\nReserved\nETHMAC\nRST\nReserved\nDMA2\nRST\nDMA1\nRST\nReserved\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCRCR\nST\nReserved\nGPIOI\nRST\nGPIOH\nRST\nGPIOGG\nRST\nGPIOF\nRST\nGPIOE\nRST\nGPIOD\nRST\nGPIOC\nRST\nGPIOB\nRST\nGPIOA\nRST\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBit 29 OTGHSRST: USB OTG HS module reset\nSet and cleared by software.\n0: does not reset the USB OTG HS module\n1: resets the USB OTG HS module\nBits 28:26 Reserved, must be kept at reset value.\nBit 25 ETHMACRST: Ethernet MAC reset\nSet and cleared by software.\n0: does not reset Ethernet MAC\n1: resets Ethernet MAC\nBits 24:23 Reserved, must be kept at reset value.\n" }, { "page_number": 236, "page_indices": { "start_index": 573779, "end_index": 574936 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 236 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)", 235 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n236/1757\nRM0090 Rev 21\nBit 22 DMA2RST: DMA2 reset\nSet and cleared by software.\n0: does not reset DMA2\n1: resets DMA2\nBit 21 DMA1RST: DMA1 reset\nSet and cleared by software.\n0: does not reset DMA1\n1: resets DMA1\nBits 20:13 Reserved, must be kept at reset value.\nBit 12 CRCRST: CRC reset\nSet and cleared by software.\n0: does not reset CRC\n1: resets CRC\nBits 11:9 Reserved, must be kept at reset value.\nBit 8 GPIOIRST: IO port I reset\nSet and cleared by software.\n0: does not reset IO port I\n1: resets IO port I\nBit 7 GPIOHRST: IO port H reset\nSet and cleared by software.\n0: does not reset IO port H\n1: resets IO port H\nBits 6 GPIOGRST: IO port G reset\nSet and cleared by software.\n0: does not reset IO port G\n1: resets IO port G\nBit 5 GPIOFRST: IO port F reset\nSet and cleared by software.\n0: does not reset IO port F\n1: resets IO port F\nBit 4 GPIOERST: IO port E reset\nSet and cleared by software.\n0: does not reset IO port E\n1: resets IO port E\nBit 3 GPIODRST: IO port D reset\nSet and cleared by software.\n0: does not reset IO port D\n1: resets IO port D\n" }, { "page_number": 237, "page_indices": { "start_index": 574936, "end_index": 575391 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 237 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)", 235 ] ], "page_content": "RM0090 Rev 21\n237/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 2 GPIOCRST: IO port C reset\nSet and cleared by software.\n0: does not reset IO port C\n1: resets IO port C\nBit 1 GPIOBRST: IO port B reset\nSet and cleared by software.\n0: does not reset IO port B\n1:resets IO port B\nBit 0 GPIOARST: IO port A reset\nSet and cleared by software.\n0: does not reset IO port A\n1: resets IO port A\n" }, { "page_number": 238, "page_indices": { "start_index": 575391, "end_index": 576692 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 238 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR)", 238 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n238/1757\nRM0090 Rev 21\n7.3.6 \nRCC AHB2 peripheral reset register (RCC_AHB2RSTR)\nAddress offset: 0x14\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOTGFS\nRST\nRNG\nRST\nHASH\nRST\nCRYP\nRST\nReserved\nDCMI\nRST\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBit 7 OTGFSRST: USB OTG FS module reset\nSet and cleared by software.\n0: does not reset the USB OTG FS module\n1: resets the USB OTG FS module\nBit 6 RNGRST: Random number generator module reset\nSet and cleared by software.\n0: does not reset the random number generator module\n1: resets the random number generator module\nBit 5 HASHRST: Hash module reset\nSet and cleared by software.\n0: does not reset the HASH module\n1: resets the HASH module\nBit 4 CRYPRST: Cryptographic module reset\nSet and cleared by software.\n0: does not reset the cryptographic module\n1: resets the cryptographic module\nBits 3:1 Reserved, must be kept at reset value.\nBit 0 DCMIRST: Camera interface reset\nSet and cleared by software.\n0: does not reset the Camera interface\n1: resets the Camera interface \n" }, { "page_number": 239, "page_indices": { "start_index": 576692, "end_index": 578266 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 239 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.7 RCC AHB3 peripheral reset register (RCC_AHB3RSTR)", 239 ], [ 3, "7.3.8 RCC APB1 peripheral reset register (RCC_APB1RSTR)", 239 ] ], "page_content": "RM0090 Rev 21\n239/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n7.3.7 \nRCC AHB3 peripheral reset register (RCC_AHB3RSTR)\nAddress offset: 0x18\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n7.3.8 \nRCC APB1 peripheral reset register (RCC_APB1RSTR)\nAddress offset: 0x20\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFSMCRST\nrw\nBits 31:1 Reserved, must be kept at reset value.\nBit 0 FSMCRST: Flexible static memory controller module reset\nSet and cleared by software.\n0: does not reset the FSMC module\n1: resets the FSMC module\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nDACRST\nPWR\nRST\nReser-\nved\nCAN2\nRST\nCAN1\nRST\nReser-\nved\nI2C3\nRST\nI2C2\nRST\nI2C1\nRST\nUART5 \nRST\nUART4\nRST\nUART3\nRST\nUART2\nRST\nReser-\nved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSPI3\nRST\nSPI2\nRST\nReserved\nWWDG\nRST\nReserved\nTIM14\nRST\nTIM13\nRST\nTIM12\nRST\nTIM7\nRST\nTIM6\nRST\nTIM5\nRST\nTIM4\nRST\nTIM3\nRST\nTIM2\nRST\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBit 29 DACRST: DAC reset\nSet and cleared by software.\n0: does not reset the DAC interface\n1: resets the DAC interface\nBit 28 PWRRST: Power interface reset\nSet and cleared by software.\n0: does not reset the power interface\n1: resets the power interface\nBit 27 Reserved, must be kept at reset value.\n" }, { "page_number": 240, "page_indices": { "start_index": 578266, "end_index": 579544 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 240 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.8 RCC APB1 peripheral reset register (RCC_APB1RSTR)", 239 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n240/1757\nRM0090 Rev 21\nBit 26 CAN2RST: CAN2 reset\nSet and cleared by software.\n0: does not reset CAN2\n1: resets CAN2\nBit 25 CAN1RST: CAN1 reset\nSet and cleared by software.\n0: does not reset CAN1\n1: resets CAN1\nBit 24 Reserved, must be kept at reset value.\nBit 23 I2C3RST: I2C3 reset\nSet and cleared by software.\n0: does not reset I2C3\n1: resets I2C3\nBit 22 I2C2RST: I2C2 reset\nSet and cleared by software.\n0: does not reset I2C2\n1: resets I2C2\nBit 21 I2C1RST: I2C1 reset\nSet and cleared by software.\n0: does not reset I2C1\n1: resets I2C1\nBit 20 UART5RST: UART5 reset\nSet and cleared by software.\n0: does not reset UART5\n1: resets UART5\nBit 19 UART4RST: USART4 reset\nSet and cleared by software.\n0: does not reset UART4\n1: resets UART4\nBit 18 USART3RST: USART3 reset\nSet and cleared by software.\n0: does not reset USART3\n1: resets USART3\nBit 17 USART2RST: USART2 reset\nSet and cleared by software.\n0: does not reset USART2\n1: resets USART2\nBit 16 Reserved, must be kept at reset value.\nBit 15 SPI3RST: SPI3 reset\nSet and cleared by software.\n0: does not reset SPI3\n1: resets SPI3\nBit 14 SPI2RST: SPI2 reset\nSet and cleared by software.\n0: does not reset SPI2\n1: resets SPI2\n" }, { "page_number": 241, "page_indices": { "start_index": 579544, "end_index": 580756 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 241 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.8 RCC APB1 peripheral reset register (RCC_APB1RSTR)", 239 ] ], "page_content": "RM0090 Rev 21\n241/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBits 13:12 Reserved, must be kept at reset value.\nBit 11 WWDGRST: Window watchdog reset\nSet and cleared by software.\n0: does not reset the window watchdog\n1: resets the window watchdog\nBits 10:9 Reserved, must be kept at reset value.\nBit 8 TIM14RST: TIM14 reset\nSet and cleared by software.\n0: does not reset TIM14\n1: resets TIM14\nBit 7 TIM13RST: TIM13 reset\nSet and cleared by software.\n0: does not reset TIM13\n1: resets TIM13\nBit 6 TIM12RST: TIM12 reset\nSet and cleared by software.\n0: does not reset TIM12\n1: resets TIM12\nBit 5 TIM7RST: TIM7 reset\nSet and cleared by software.\n0: does not reset TIM7\n1: resets TIM7\nBit 4 TIM6RST: TIM6 reset\nSet and cleared by software.\n0: does not reset TIM6\n1: resets TIM6\nBit 3 TIM5RST: TIM5 reset\nSet and cleared by software.\n0: does not reset TIM5\n1: resets TIM5\nBit 2 TIM4RST: TIM4 reset\nSet and cleared by software.\n0: does not reset TIM4\n1: resets TIM4\nBit 1 TIM3RST: TIM3 reset\nSet and cleared by software.\n0: does not reset TIM3\n1: resets TIM3\nBit 0 TIM2RST: TIM2 reset\nSet and cleared by software.\n0: does not reset TIM2\n1: resets TIM2\n" }, { "page_number": 242, "page_indices": { "start_index": 580756, "end_index": 582222 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 242 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR)", 242 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n242/1757\nRM0090 Rev 21\n7.3.9 \nRCC APB2 peripheral reset register (RCC_APB2RSTR)\nAddress offset: 0x24\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTIM11\nRST\nTIM10\nRST\nTIM9\nRST\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReser-\nved\nSYSCF\nG RST\nReser-\nved\nSPI1\nRST\nSDIO\nRST\nReserved\nADC\nRST\nReserved\nUSART\n6\nRST\nUSART\n1\nRST\nReserved\nTIM8\nRST\nTIM1\nRST\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:19 Reserved, must be kept at reset value.\nBit 18 TIM11RST: TIM11 reset\nSet and cleared by software.\n0: does not reset TIM11\n1: resets TIM14\nBit 17 TIM10RST: TIM10 reset\nSet and cleared by software.\n0: does not reset TIM10\n1: resets TIM10\nBit 16 TIM9RST: TIM9 reset\nSet and cleared by software.\n0: does not reset TIM9\n1: resets TIM9\nBit 15 Reserved, must be kept at reset value.\nBit 14 SYSCFGRST: System configuration controller reset\nSet and cleared by software.\n0: does not reset the System configuration controller\n1: resets the System configuration controller\nBit 13 Reserved, must be kept at reset value.\nBit 12 SPI1RST: SPI1 reset\nSet and cleared by software.\n0: does not reset SPI1\n1: resets SPI1\nBit 11 SDIORST: SDIO reset\nSet and cleared by software.\n0: does not reset the SDIO module\n1: resets the SDIO module\nBits 10:9 Reserved, must be kept at reset value.\n" }, { "page_number": 243, "page_indices": { "start_index": 582222, "end_index": 582983 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 243 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR)", 242 ] ], "page_content": "RM0090 Rev 21\n243/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 8 ADCRST: ADC interface reset (common to all ADCs)\nSet and cleared by software.\n0: does not reset the ADC interface\n1: resets the ADC interface\nBits 7:6 Reserved, must be kept at reset value.\nBit 5 USART6RST: USART6 reset\nSet and cleared by software.\n0: does not reset USART6\n1: resets USART6\nBit 4\nUSART1RST: USART1 reset\nSet and cleared by software.\n0: does not reset USART1\n1: resets USART1\nBits 3:2 Reserved, must be kept at reset value.\nBit 1 TIM8RST: TIM8 reset\nSet and cleared by software.\n0: does not reset TIM8\n1: resets TIM8\nBit 0 TIM1RST: TIM1 reset\nSet and cleared by software.\n0: does not reset TIM1\n1: resets TIM1\n" }, { "page_number": 244, "page_indices": { "start_index": 582983, "end_index": 584811 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 244 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.10 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)", 244 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n244/1757\nRM0090 Rev 21\n7.3.10 \nRCC AHB1 peripheral clock enable register (RCC_AHB1ENR)\nAddress offset: 0x30\nReset value: 0x0010 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReser-\nved\nOTGH\nS \nULPIE\nN\nOTGH\nSEN\nETHM\nACPTP\nEN\nETHM\nACRXE\nN\nETHM\nACTXE\nN\nETHMA\nCEN\nReserved\nDMA2E\nN\nDMA1E\nN\nCCMDAT\nARAMEN\nRes.\nBKPSR\nAMEN\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCRCE\nN\nReserved\nGPIOIE\nN\nGPIOH\nEN\nGPIOG\nEN\nGPIOFE\nN\nGPIOEEN\nGPIOD\nEN\nGPIOC\nEN\nGPIO\nBEN\nGPIO\nAEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBit 30 OTGHSULPIEN: USB OTG HSULPI clock enable\nSet and cleared by software. This bit must be cleared when the OTG_HS is used in FS \nmode.\n0: USB OTG HS ULPI clock disabled\n1: USB OTG HS ULPI clock enabled\nBit 29 OTGHSEN: USB OTG HS clock enable\nSet and cleared by software.\n0: USB OTG HS clock disabled\n1: USB OTG HS clock enabled\nBit 28 ETHMACPTPEN: Ethernet PTP clock enable\nSet and cleared by software.\n0: Ethernet PTP clock disabled\n1: Ethernet PTP clock enabled\nBit 27 ETHMACRXEN: Ethernet Reception clock enable\nSet and cleared by software.\n0: Ethernet Reception clock disabled\n1: Ethernet Reception clock enabled\nBit 26 ETHMACTXEN: Ethernet Transmission clock enable\nSet and cleared by software.\n0: Ethernet Transmission clock disabled\n1: Ethernet Transmission clock enabled\nBit 25 ETHMACEN: Ethernet MAC clock enable\nSet and cleared by software.\n0: Ethernet MAC clock disabled\n1: Ethernet MAC clock enabled\nBits 24:23 Reserved, must be kept at reset value.\nBit 22 DMA2EN: DMA2 clock enable\nSet and cleared by software.\n0: DMA2 clock disabled\n1: DMA2 clock enabled\n" }, { "page_number": 245, "page_indices": { "start_index": 584811, "end_index": 586326 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 245 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.10 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)", 244 ] ], "page_content": "RM0090 Rev 21\n245/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 21 DMA1EN: DMA1 clock enable\nSet and cleared by software.\n0: DMA1 clock disabled\n1: DMA1 clock enabled\nBit 20 CCMDATARAMEN: CCM data RAM clock enable\nSet and cleared by software. \n0: CCM data RAM clock disabled\n1: CCM data RAM clock enabled\nBit 19 Reserved, must be kept at reset value.\nBit 18 BKPSRAMEN: Backup SRAM interface clock enable\nSet and cleared by software.\n0: Backup SRAM interface clock disabled\n1: Backup SRAM interface clock enabled\nBits 17:13 Reserved, must be kept at reset value.\nBit 12 CRCEN: CRC clock enable\nSet and cleared by software.\n0: CRC clock disabled\n1: CRC clock enabled\nBits 11:9 Reserved, must be kept at reset value.\nBit 8 GPIOIEN: IO port I clock enable\nSet and cleared by software.\n0: IO port I clock disabled\n1: IO port I clock enabled\nBit 7 GPIOHEN: IO port H clock enable\nSet and cleared by software.\n0: IO port H clock disabled\n1: IO port H clock enabled\nBit 6 GPIOGEN: IO port G clock enable\nSet and cleared by software.\n0: IO port G clock disabled\n1: IO port G clock enabled\nBit 5 GPIOFEN: IO port F clock enable\nSet and cleared by software.\n0: IO port F clock disabled\n1: IO port F clock enabled\nBit 4 GPIOEEN: IO port E clock enable\nSet and cleared by software.\n0: IO port E clock disabled\n1: IO port E clock enabled\nBit 3 GPIODEN: IO port D clock enable\nSet and cleared by software.\n0: IO port D clock disabled\n1: IO port D clock enabled\n" }, { "page_number": 246, "page_indices": { "start_index": 586326, "end_index": 587637 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 246 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.11 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)", 246 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n246/1757\nRM0090 Rev 21\n7.3.11 \nRCC AHB2 peripheral clock enable register (RCC_AHB2ENR)\nAddress offset: 0x34\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \nBit 2 GPIOCEN: IO port C clock enable\nSet and cleared by software.\n0: IO port C clock disabled\n1: IO port C clock enabled\nBit 1 GPIOBEN: IO port B clock enable\nSet and cleared by software.\n0: IO port B clock disabled\n1: IO port B clock enabled\nBit 0 GPIOAEN: IO port A clock enable\nSet and cleared by software.\n0: IO port A clock disabled\n1: IO port A clock enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOTGFS\nEN\nRNG\nEN\nHASH\nEN\nCRYP\nEN\nReserved\nDCMI\nEN\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBit 7 OTGFSEN: USB OTG FS clock enable\nSet and cleared by software.\n0: USB OTG FS clock disabled\n1: USB OTG FS clock enabled\nBit 6 RNGEN: Random number generator clock enable\nSet and cleared by software.\n0: Random number generator clock disabled\n1: Random number generator clock enabled\nBit 5 HASHEN: Hash modules clock enable\nSet and cleared by software.\n0: Hash modules clock disabled\n1: Hash modules clock enabled\n" }, { "page_number": 247, "page_indices": { "start_index": 587637, "end_index": 589195 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 247 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.12 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)", 247 ], [ 3, "7.3.13 RCC APB1 peripheral clock enable register (RCC_APB1ENR)", 247 ] ], "page_content": "RM0090 Rev 21\n247/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n7.3.12 \nRCC AHB3 peripheral clock enable register (RCC_AHB3ENR)\nAddress offset: 0x38\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \n7.3.13 \nRCC APB1 peripheral clock enable register\n(RCC_APB1ENR)\nAddress offset: 0x40\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \nBit 4 CRYPEN: Cryptographic modules clock enable\nSet and cleared by software.\n0: cryptographic module clock disabled\n1: cryptographic module clock enabled\nBits 3:1 Reserved, must be kept at reset value.\nBit 0 DCMIEN: Camera interface enable\nSet and cleared by software.\n0: Camera interface clock disabled\n1: Camera interface clock enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFSMCEN\nrw\nBits 31:1 Reserved, must be kept at reset value.\nBit 0 FSMCEN: Flexible static memory controller module clock enable\nSet and cleared by software.\n0: FSMC module clock disabled\n1: FSMC module clock enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nDAC\nEN\nPWR\nEN\nReser-\nved\nCAN2\nEN\nCAN1\nEN\nReser-\nved\nI2C3\nEN\nI2C2\nEN\nI2C1\nEN\nUART5\nEN\nUART4\nEN\nUSART\n3\nEN\nUSART\n2\nEN\nReser-\nved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSPI3\nEN\nSPI2\nEN\nReserved\nWWDG\nEN\nReserved\nTIM14\nEN\nTIM13\nEN\nTIM12\nEN\nTIM7\nEN\nTIM6 \nEN\nTIM5\nEN\nTIM4\nEN\nTIM3\nEN\nTIM2\nEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 248, "page_indices": { "start_index": 589195, "end_index": 590620 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 248 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.13 RCC APB1 peripheral clock enable register (RCC_APB1ENR)", 247 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n248/1757\nRM0090 Rev 21\n \nBits 31:30 Reserved, must be kept at reset value.\nBit 29 DACEN: DAC interface clock enable\nSet and cleared by software.\n0: DAC interface clock disabled\n1: DAC interface clock enable\nBit 28 PWREN: Power interface clock enable\nSet and cleared by software.\n0: Power interface clock disabled\n1: Power interface clock enable\nBit 27 Reserved, must be kept at reset value.\nBit 26 CAN2EN: CAN 2 clock enable\nSet and cleared by software.\n0: CAN 2 clock disabled\n1: CAN 2 clock enabled\nBit 25 CAN1EN: CAN 1 clock enable\nSet and cleared by software.\n0: CAN 1 clock disabled\n1: CAN 1 clock enabled\nBit 24 Reserved, must be kept at reset value.\nBit 23 I2C3EN: I2C3 clock enable\nSet and cleared by software.\n0: I2C3 clock disabled\n1: I2C3 clock enabled\nBit 22 I2C2EN: I2C2 clock enable\nSet and cleared by software.\n0: I2C2 clock disabled\n1: I2C2 clock enabled\nBit 21 I2C1EN: I2C1 clock enable\nSet and cleared by software.\n0: I2C1 clock disabled\n1: I2C1 clock enabled\nBit 20 UART5EN: UART5 clock enable\nSet and cleared by software.\n0: UART5 clock disabled\n1: UART5 clock enabled\nBit 19 UART4EN: UART4 clock enable\nSet and cleared by software.\n0: UART4 clock disabled\n1: UART4 clock enabled\nBit 18 USART3EN: USART3 clock enable\nSet and cleared by software.\n0: USART3 clock disabled\n1: USART3 clock enabled\n" }, { "page_number": 249, "page_indices": { "start_index": 590620, "end_index": 592011 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 249 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.13 RCC APB1 peripheral clock enable register (RCC_APB1ENR)", 247 ] ], "page_content": "RM0090 Rev 21\n249/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 17 USART2EN: USART2 clock enable\nSet and cleared by software.\n0: USART2 clock disabled\n1: USART2 clock enabled\nBit 16 Reserved, must be kept at reset value.\nBit 15 SPI3EN: SPI3 clock enable\nSet and cleared by software.\n0: SPI3 clock disabled\n1: SPI3 clock enabled\nBit 14 SPI2EN: SPI2 clock enable\nSet and cleared by software.\n0: SPI2 clock disabled\n1: SPI2 clock enabled\nBits 13:12 Reserved, must be kept at reset value.\nBit 11 WWDGEN: Window watchdog clock enable\nSet and cleared by software.\n0: Window watchdog clock disabled\n1: Window watchdog clock enabled\nBits 10:9 Reserved, must be kept at reset value.\nBit 8 TIM14EN: TIM14 clock enable\nSet and cleared by software.\n0: TIM14 clock disabled\n1: TIM14 clock enabled\nBit 7 TIM13EN: TIM13 clock enable\nSet and cleared by software.\n0: TIM13 clock disabled\n1: TIM13 clock enabled\nBit 6 TIM12EN: TIM12 clock enable\nSet and cleared by software.\n0: TIM12 clock disabled\n1: TIM12 clock enabled\nBit 5 TIM7EN: TIM7 clock enable\nSet and cleared by software.\n0: TIM7 clock disabled\n1: TIM7 clock enabled\nBit 4 TIM6EN: TIM6 clock enable\nSet and cleared by software.\n0: TIM6 clock disabled\n1: TIM6 clock enabled\nBit 3 TIM5EN: TIM5 clock enable\nSet and cleared by software.\n0: TIM5 clock disabled\n1: TIM5 clock enabled\n" }, { "page_number": 250, "page_indices": { "start_index": 592011, "end_index": 593364 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 250 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.14 RCC APB2 peripheral clock enable register (RCC_APB2ENR)", 250 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n250/1757\nRM0090 Rev 21\n \n7.3.14 \nRCC APB2 peripheral clock enable register (RCC_APB2ENR)\nAddress offset: 0x44\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\n \n \nBit 2 TIM4EN: TIM4 clock enable\nSet and cleared by software.\n0: TIM4 clock disabled\n1: TIM4 clock enabled\nBit 1 TIM3EN: TIM3 clock enable\nSet and cleared by software.\n0: TIM3 clock disabled\n1: TIM3 clock enabled\nBit 0 TIM2EN: TIM2 clock enable\nSet and cleared by software.\n0: TIM2 clock disabled\n1: TIM2 clock enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTIM11\nEN\nTIM10\nEN\nTIM9\nEN\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReser-\nved\nSYSCF\nG EN\nReser-\nved\nSPI1\nEN\nSDIO\nEN\nADC3\nEN\nADC2\nEN\nADC1\nEN\nReserved\nUSART\n6\nEN\nUSART\n1\nEN\nReserved\nTIM8\nEN\nTIM1\nEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:19 Reserved, must be kept at reset value.\nBit 18 TIM11EN: TIM11 clock enable\nSet and cleared by software.\n0: TIM11 clock disabled\n1: TIM11 clock enabled\nBit 17 TIM10EN: TIM10 clock enable\nSet and cleared by software.\n0: TIM10 clock disabled\n1: TIM10 clock enabled\nBit 16 TIM9EN: TIM9 clock enable\nSet and cleared by software.\n0: TIM9 clock disabled\n1: TIM9 clock enabled\nBit 15 Reserved, must be kept at reset value.\n" }, { "page_number": 251, "page_indices": { "start_index": 593364, "end_index": 594815 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 251 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.14 RCC APB2 peripheral clock enable register (RCC_APB2ENR)", 250 ] ], "page_content": "RM0090 Rev 21\n251/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 14 SYSCFGEN: System configuration controller clock enable\nSet and cleared by software.\n0: System configuration controller clock disabled\n1: System configuration controller clock enabled\nBit 13 Reserved, must be kept at reset value.\nBit 12 SPI1EN: SPI1 clock enable\nSet and cleared by software.\n0: SPI1 clock disabled\n1: SPI1 clock enabled\nBit 11 SDIOEN: SDIO clock enable\nSet and cleared by software.\n0: SDIO module clock disabled\n1: SDIO module clock enabled\nBit 10 ADC3EN: ADC3 clock enable\nSet and cleared by software.\n0: ADC3 clock disabled\n1: ADC3 clock disabled\nBit 9\nADC2EN: ADC2 clock enable\nSet and cleared by software.\n0: ADC2 clock disabled\n1: ADC2 clock disabled\nBit 8\nADC1EN: ADC1 clock enable\nSet and cleared by software.\n0: ADC1 clock disabled\n1: ADC1 clock disabled\nBits 7:6 Reserved, must be kept at reset value.\nBit 5 USART6EN: USART6 clock enable\nSet and cleared by software.\n0: USART6 clock disabled\n1: USART6 clock enabled\nBit 4 USART1EN: USART1 clock enable\nSet and cleared by software.\n0: USART1 clock disabled\n1: USART1 clock enabled\nBits 3:2 Reserved, must be kept at reset value.\nBit 1 TIM8EN: TIM8 clock enable\nSet and cleared by software.\n0: TIM8 clock disabled\n1: TIM8 clock enabled\nBit 0 TIM1EN: TIM1 clock enable\nSet and cleared by software.\n0: TIM1 clock disabled\n1: TIM1 clock enabled\n" }, { "page_number": 252, "page_indices": { "start_index": 594815, "end_index": 596950 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 252 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.15 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR)", 252 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n252/1757\nRM0090 Rev 21\n7.3.15 \nRCC AHB1 peripheral clock enable in low power mode register\n(RCC_AHB1LPENR)\nAddress offset: 0x50\nReset value: 0x7E67 91FF\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReser\n-ved\nOTGHS\nULPILPE\nN\nOTGH\nS\nLPEN\nETHPT\nP\nLPEN\nETHRX\nLPEN\nETHTX\nLPEN\nETHMA\nC\nLPEN\nReserved\nDMA2\nLPEN\nDMA1\nLPEN\nReserved\nBKPSRA\nM\nLPEN\nSRAM\n2\nLPEN\nSRAM\n1\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFLITF\nLPEN\nReserved\nCRC\nLPEN\nReserved\nGPIOI\nLPEN\nGPIOH\nLPEN\nGPIOG\nG\nLPEN\nGPIO\nF\nLPEN\nGPIOE\nLPEN\nGPIOD\nLPEN\nGPIOC\nLPEN\nGPIOB\nLPEN\nGPIOA\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBit 30 OTGHSULPILPEN: USB OTG HS ULPI clock enable during Sleep mode\nSet and cleared by software. This bit must be cleared when the OTG_HS is used in FS \nmode.\n0: USB OTG HS ULPI clock disabled during Sleep mode\n1: USB OTG HS ULPI clock enabled during Sleep mode\nBit 29 OTGHSLPEN: USB OTG HS clock enable during Sleep mode\nSet and cleared by software.\n0: USB OTG HS clock disabled during Sleep mode\n1: USB OTG HS clock enabled during Sleep mode\nBit 28 ETHMACPTPLPEN: Ethernet PTP clock enable during Sleep mode\nSet and cleared by software.\n0: Ethernet PTP clock disabled during Sleep mode\n1: Ethernet PTP clock enabled during Sleep mode\nBit 27 ETHMACRXLPEN: Ethernet reception clock enable during Sleep mode\nSet and cleared by software.\n0: Ethernet reception clock disabled during Sleep mode\n1: Ethernet reception clock enabled during Sleep mode\nBit 26 ETHMACTXLPEN: Ethernet transmission clock enable during Sleep mode\nSet and cleared by software.\n0: Ethernet transmission clock disabled during sleep mode\n1: Ethernet transmission clock enabled during sleep mode\nBit 25 ETHMACLPEN: Ethernet MAC clock enable during Sleep mode\nSet and cleared by software.\n0: Ethernet MAC clock disabled during Sleep mode\n1: Ethernet MAC clock enabled during Sleep mode\nBits 24:23 Reserved, must be kept at reset value.\n" }, { "page_number": 253, "page_indices": { "start_index": 596950, "end_index": 599061 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 253 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.15 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR)", 252 ] ], "page_content": "RM0090 Rev 21\n253/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 22 DMA2LPEN: DMA2 clock enable during Sleep mode\nSet and cleared by software.\n0: DMA2 clock disabled during Sleep mode\n1: DMA2 clock enabled during Sleep mode\nBit 21 DMA1LPEN: DMA1 clock enable during Sleep mode\nSet and cleared by software.\n0: DMA1 clock disabled during Sleep mode\n1: DMA1 clock enabled during Sleep mode\nBits 20:19 Reserved, must be kept at reset value.\nBit 18 BKPSRAMLPEN: Backup SRAM interface clock enable during Sleep mode\nSet and cleared by software.\n0: Backup SRAM interface clock disabled during Sleep mode\n1: Backup SRAM interface clock enabled during Sleep mode\nBit 17 SRAM2LPEN: SRAM 2 interface clock enable during Sleep mode\nSet and cleared by software.\n0: SRAM 2 interface clock disabled during Sleep mode\n1: SRAM 2 interface clock enabled during Sleep mode\nBit 16 SRAM1LPEN: SRAM 1interface clock enable during Sleep mode\nSet and cleared by software.\n0: SRAM 1 interface clock disabled during Sleep mode\n1: SRAM 1 interface clock enabled during Sleep mode\nBit 15 FLITFLPEN: Flash interface clock enable during Sleep mode\nSet and cleared by software.\n0: Flash interface clock disabled during Sleep mode\n1: Flash interface clock enabled during Sleep mode\nBits 14:13 Reserved, must be kept at reset value.\nBit 12 CRCLPEN: CRC clock enable during Sleep mode\nSet and cleared by software.\n0: CRC clock disabled during Sleep mode\n1: CRC clock enabled during Sleep mode\nBits 11:9 Reserved, must be kept at reset value.\nBit 8 GPIOILPEN: IO port I clock enable during Sleep mode\nSet and cleared by software.\n0: IO port I clock disabled during Sleep mode\n1: IO port I clock enabled during Sleep mode\nBit 7\nGPIOHLPEN: IO port H clock enable during Sleep mode\nSet and cleared by software.\n0: IO port H clock disabled during Sleep mode\n1: IO port H clock enabled during Sleep mode\nBits 6 GPIOGLPEN: IO port G clock enable during Sleep mode\nSet and cleared by software.\n0: IO port G clock disabled during Sleep mode\n1: IO port G clock enabled during Sleep mode\n" }, { "page_number": 254, "page_indices": { "start_index": 599061, "end_index": 600628 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 254 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.16 RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR)", 254 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n254/1757\nRM0090 Rev 21\n7.3.16 \nRCC AHB2 peripheral clock enable in low power mode register\n(RCC_AHB2LPENR)\nAddress offset: 0x54\nReset value: 0x0000 00F1\nAccess: no wait state, word, half-word and byte access.\n \nBit 5 GPIOFLPEN: IO port F clock enable during Sleep mode\nSet and cleared by software.\n0: IO port F clock disabled during Sleep mode\n1: IO port F clock enabled during Sleep mode\nBit 4 GPIOELPEN: IO port E clock enable during Sleep mode\nSet and cleared by software.\n0: IO port E clock disabled during Sleep mode\n1: IO port E clock enabled during Sleep mode\nBit 3 GPIODLPEN: IO port D clock enable during Sleep mode\nSet and cleared by software.\n0: IO port D clock disabled during Sleep mode\n1: IO port D clock enabled during Sleep mode\nBit 2 GPIOCLPEN: IO port C clock enable during Sleep mode\nSet and cleared by software.\n0: IO port C clock disabled during Sleep mode\n1: IO port C clock enabled during Sleep mode\nBit 1 GPIOBLPEN: IO port B clock enable during Sleep mode\nSet and cleared by software.\n0: IO port B clock disabled during Sleep mode\n1: IO port B clock enabled during Sleep mode\nBit 0 GPIOALPEN: IO port A clock enable during sleep mode\nSet and cleared by software.\n0: IO port A clock disabled during Sleep mode\n1: IO port A clock enabled during Sleep mode\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOTGFS\nLPEN\nRNG\nLPEN\nHASH\nLPEN\nCRYP\nLPEN\nReserved\nDCMI\nLPEN\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 255, "page_indices": { "start_index": 600628, "end_index": 602434 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 255 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.17 RCC AHB3 peripheral clock enable in low power mode register (RCC_AHB3LPENR)", 255 ] ], "page_content": "RM0090 Rev 21\n255/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n \n7.3.17 \nRCC AHB3 peripheral clock enable in low power mode register\n(RCC_AHB3LPENR)\nAddress offset: 0x58\nReset value: 0x0000 0001\nAccess: no wait state, word, half-word and byte access.\n \n \nBits 31:8 Reserved, must be kept at reset value.\nBit 7 OTGFSLPEN: USB OTG FS clock enable during Sleep mode\nSet and cleared by software.\n0: USB OTG FS clock disabled during Sleep mode\n1: USB OTG FS clock enabled during Sleep mode\nBit 6 RNGLPEN: Random number generator clock enable during Sleep mode\nSet and cleared by software.\n0: Random number generator clock disabled during Sleep mode\n1: Random number generator clock enabled during Sleep mode\nBit 5 HASHLPEN: Hash modules clock enable during Sleep mode\nSet and cleared by software.\n0: Hash modules clock disabled during Sleep mode\n1: Hash modules clock enabled during Sleep mode\nBit 4 CRYPLPEN: Cryptography modules clock enable during Sleep mode\nSet and cleared by software.\n0: cryptography modules clock disabled during Sleep mode\n1: cryptography modules clock enabled during Sleep mode\nBits 3:1 Reserved, must be kept at reset value.\nBit 0 DCMILPEN: Camera interface enable during Sleep mode\nSet and cleared by software.\n0: Camera interface clock disabled during Sleep mode\n1: Camera interface clock enabled during Sleep mode\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFSMC\nLPEN\nrw\nBits 31:1Reserved, must be kept at reset value.\nBit 0\nFSMCLPEN: Flexible static memory controller module clock enable during Sleep mode\nSet and cleared by software.\n0: FSMC module clock disabled during Sleep mode\n1: FSMC module clock enabled during Sleep mode\n" }, { "page_number": 256, "page_indices": { "start_index": 602434, "end_index": 604403 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 256 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.18 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR)", 256 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n256/1757\nRM0090 Rev 21\n7.3.18 \nRCC APB1 peripheral clock enable in low power mode register\n(RCC_APB1LPENR)\nAddress offset: 0x60\nReset value: 0x36FE C9FF\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nDAC\nLPEN\nPWR\nLPEN\nRESER\nVED\nCAN2\nLPEN\nCAN1\nLPEN\nReser-\nved\nI2C3\nLPEN\nI2C2\nLPEN\nI2C1\nLPEN\nUART5\nLPEN\nUART4\nLPEN\nUSART\n3\nLPEN\nUSART\n2\nLPEN\nReser-\nved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSPI3\nLPEN\nSPI2\nLPEN\nReserved\nWWDG\nLPEN\nReserved\nTIM14\nLPEN\nTIM13\nLPEN\nTIM12\nLPEN\nTIM7\nLPEN\nTIM6 \nLPEN\nTIM5\nLPEN\nTIM4\nLPEN\nTIM3\nLPEN\nTIM2\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBit 29 DACLPEN: DAC interface clock enable during Sleep mode\nSet and cleared by software.\n0: DAC interface clock disabled during Sleep mode\n1: DAC interface clock enabled during Sleep mode\nBit 28 PWRLPEN: Power interface clock enable during Sleep mode\nSet and cleared by software.\n0: Power interface clock disabled during Sleep mode\n1: Power interface clock enabled during Sleep mode\nBit 27 Reserved, must be kept at reset value.\nBit 26 CAN2LPEN: CAN 2 clock enable during Sleep mode\nSet and cleared by software.\n0: CAN 2 clock disabled during sleep mode\n1: CAN 2 clock enabled during sleep mode\nBit 25 CAN1LPEN: CAN 1 clock enable during Sleep mode\nSet and cleared by software.\n0: CAN 1 clock disabled during Sleep mode\n1: CAN 1 clock enabled during Sleep mode\nBit 24 Reserved, must be kept at reset value.\nBit 23 I2C3LPEN: I2C3 clock enable during Sleep mode\nSet and cleared by software.\n0: I2C3 clock disabled during Sleep mode\n1: I2C3 clock enabled during Sleep mode\nBit 22 I2C2LPEN: I2C2 clock enable during Sleep mode\nSet and cleared by software.\n0: I2C2 clock disabled during Sleep mode\n1: I2C2 clock enabled during Sleep mode\n" }, { "page_number": 257, "page_indices": { "start_index": 604403, "end_index": 606370 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 257 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.18 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR)", 256 ] ], "page_content": "RM0090 Rev 21\n257/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 21 I2C1LPEN: I2C1 clock enable during Sleep mode\nSet and cleared by software.\n0: I2C1 clock disabled during Sleep mode\n1: I2C1 clock enabled during Sleep mode\nBit 20 UART5LPEN: UART5 clock enable during Sleep mode\nSet and cleared by software.\n0: UART5 clock disabled during Sleep mode\n1: UART5 clock enabled during Sleep mode\nBit 19 UART4LPEN: UART4 clock enable during Sleep mode\nSet and cleared by software.\n0: UART4 clock disabled during Sleep mode\n1: UART4 clock enabled during Sleep mode\nBit 18\nUSART3LPEN: USART3 clock enable during Sleep mode\nSet and cleared by software.\n0: USART3 clock disabled during Sleep mode\n1: USART3 clock enabled during Sleep mode\nBit 17 USART2LPEN: USART2 clock enable during Sleep mode\nSet and cleared by software.\n0: USART2 clock disabled during Sleep mode\n1: USART2 clock enabled during Sleep mode\nBit 16 Reserved, must be kept at reset value.\nBit 15 SPI3LPEN: SPI3 clock enable during Sleep mode\nSet and cleared by software.\n0: SPI3 clock disabled during Sleep mode\n1: SPI3 clock enabled during Sleep mode\nBit 14 SPI2LPEN: SPI2 clock enable during Sleep mode\nSet and cleared by software.\n0: SPI2 clock disabled during Sleep mode\n1: SPI2 clock enabled during Sleep mode\nBits 13:12 Reserved, must be kept at reset value.\nBit 11 WWDGLPEN: Window watchdog clock enable during Sleep mode\nSet and cleared by software.\n0: Window watchdog clock disabled during sleep mode\n1: Window watchdog clock enabled during sleep mode\nBits 10:9 Reserved, must be kept at reset value.\nBit 8 TIM14LPEN: TIM14 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM14 clock disabled during Sleep mode\n1: TIM14 clock enabled during Sleep mode\nBit 7 TIM13LPEN: TIM13 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM13 clock disabled during Sleep mode\n1: TIM13 clock enabled during Sleep mode\n" }, { "page_number": 258, "page_indices": { "start_index": 606370, "end_index": 607633 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 258 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.18 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR)", 256 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n258/1757\nRM0090 Rev 21\nBit 6 TIM12LPEN: TIM12 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM12 clock disabled during Sleep mode\n1: TIM12 clock enabled during Sleep mode\nBit 5 TIM7LPEN: TIM7 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM7 clock disabled during Sleep mode\n1: TIM7 clock enabled during Sleep mode\nBit 4 TIM6LPEN: TIM6 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM6 clock disabled during Sleep mode\n1: TIM6 clock enabled during Sleep mode\nBit 3 TIM5LPEN: TIM5 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM5 clock disabled during Sleep mode\n1: TIM5 clock enabled during Sleep mode\nBit 2 TIM4LPEN: TIM4 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM4 clock disabled during Sleep mode\n1: TIM4 clock enabled during Sleep mode\nBit 1 TIM3LPEN: TIM3 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM3 clock disabled during Sleep mode\n1: TIM3 clock enabled during Sleep mode\nBit 0\nTIM2LPEN: TIM2 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM2 clock disabled during Sleep mode\n1: TIM2 clock enabled during Sleep mode\n" }, { "page_number": 259, "page_indices": { "start_index": 607633, "end_index": 609511 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 259 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.19 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR)", 259 ] ], "page_content": "RM0090 Rev 21\n259/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n7.3.19 \nRCC APB2 peripheral clock enabled in low power mode \n register (RCC_APB2LPENR)\nAddress offset: 0x64\nReset value: 0x0007 5F33\nAccess: no wait state, word, half-word and byte access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTIM11\nLPEN\nTIM10\nLPEN\nTIM9\nLPEN\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReser-\nved\nSYSC\nFG\nLPEN\nReser-\nved\nSPI1\nLPEN\nSDIO\nLPEN\nADC3\nLPEN\nADC2\nLPEN\nADC1\nLPEN\nReserved\nUSART\n6\nLPEN\nUSART\n1\nLPEN\nReserved\nTIM8\nLPEN\nTIM1\nLPEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:19 Reserved, must be kept at reset value.\nBit 18 TIM11LPEN: TIM11 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM11 clock disabled during Sleep mode\n1: TIM11 clock enabled during Sleep mode\nBit 17 TIM10LPEN: TIM10 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM10 clock disabled during Sleep mode\n1: TIM10 clock enabled during Sleep mode\nBit 16 TIM9LPEN: TIM9 clock enable during sleep mode\nSet and cleared by software.\n0: TIM9 clock disabled during Sleep mode\n1: TIM9 clock enabled during Sleep mode\nBit 15 Reserved, must be kept at reset value.\nBit 14 SYSCFGLPEN: System configuration controller clock enable during Sleep mode\nSet and cleared by software.\n0: System configuration controller clock disabled during Sleep mode\n1: System configuration controller clock enabled during Sleep mode\nBit 13 Reserved, must be kept at reset value.\nBit 12 SPI1LPEN: SPI1 clock enable during Sleep mode\nSet and cleared by software.\n0: SPI1 clock disabled during Sleep mode\n1: SPI1 clock enabled during Sleep mode\nBit 11 SDIOLPEN: SDIO clock enable during Sleep mode\nSet and cleared by software.\n0: SDIO module clock disabled during Sleep mode\n1: SDIO module clock enabled during Sleep mode\n" }, { "page_number": 260, "page_indices": { "start_index": 609511, "end_index": 610889 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 260 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.19 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR)", 259 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n260/1757\nRM0090 Rev 21\nBit 10 ADC3LPEN: ADC 3 clock enable during Sleep mode\nSet and cleared by software.\n0: ADC 3 clock disabled during Sleep mode\n1: ADC 3 clock disabled during Sleep mode\nBit 9 ADC2LPEN: ADC2 clock enable during Sleep mode\nSet and cleared by software.\n0: ADC2 clock disabled during Sleep mode\n1: ADC2 clock disabled during Sleep mode\nBit 8 ADC1LPEN: ADC1 clock enable during Sleep mode\nSet and cleared by software.\n0: ADC1 clock disabled during Sleep mode\n1: ADC1 clock disabled during Sleep mode\nBits 7:6 Reserved, must be kept at reset value.\nBit 5 USART6LPEN: USART6 clock enable during Sleep mode\nSet and cleared by software.\n0: USART6 clock disabled during Sleep mode\n1: USART6 clock enabled during Sleep mode\nBit 4 USART1LPEN: USART1 clock enable during Sleep mode\nSet and cleared by software.\n0: USART1 clock disabled during Sleep mode\n1: USART1 clock enabled during Sleep mode\nBits 3:2 Reserved, must be kept at reset value.\nBit 1 TIM8LPEN: TIM8 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM8 clock disabled during Sleep mode\n1: TIM8 clock enabled during Sleep mode\nBit 0 TIM1LPEN: TIM1 clock enable during Sleep mode\nSet and cleared by software.\n0: TIM1 clock disabled during Sleep mode\n1: TIM1 clock enabled during Sleep mode\n" }, { "page_number": 261, "page_indices": { "start_index": 610889, "end_index": 613255 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 261 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.20 RCC Backup domain control register (RCC_BDCR)", 261 ] ], "page_content": "RM0090 Rev 21\n261/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n7.3.20 \nRCC Backup domain control register (RCC_BDCR)\nAddress offset: 0x70\nReset value: 0x0000 0000, reset by Backup domain reset.\nAccess: 0 ≤ wait state ≤ 3, word, half-word and byte access\nWait states are inserted in case of successive accesses to this register.\nThe LSEON, LSEBYP, RTCSEL and RTCEN bits in the RCC Backup domain control \nregister (RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are \nwrite-protected and the DBP bit in the PWR power control register (PWR_CR) for \nSTM32F405xx/07xx and STM32F415xx/17xx has to be set before these can be modified. \nRefer to Section 7.1.1: System reset on page 215 for further information. These bits are only \nreset after a Backup domain Reset (see Section 7.1.3: Backup domain reset). Any internal \nor external Reset has no effect on these bits.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nBDRST\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRTCEN\nReserved\nRTCSEL[1:0]\nReserved\nLSEBY\nP\nLSERD\nY\nLSEON\nrw\nrw\nrw\nrw\nr\nrw\nBits 31:17 Reserved, must be kept at reset value.\nBit 16 BDRST: Backup domain software reset\nSet and cleared by software.\n0: Reset not activated\n1: Resets the entire Backup domain\nNote: The BKPSRAM is not affected by this reset, the only way of resetting the BKPSRAM is \nthrough the Flash interface when a protection level change from level 1 to level 0 is \nrequested.\nThe backup domain software reset does not take effect until the DBP bit of the \nPWR_CR register is set.\nBit 15 RTCEN: RTC clock enable\nSet and cleared by software.\n0: RTC clock disabled\n1: RTC clock enabled\nBits 14:10 Reserved, must be kept at reset value.\nBits 9:8 RTCSEL[1:0]: RTC clock source selection\nSet by software to select the clock source for the RTC. Once the RTC clock source has been \nselected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit \ncan be used to reset them.\n00: No clock\n01: LSE oscillator clock used as the RTC clock\n10: LSI oscillator clock used as the RTC clock\n11: HSE oscillator clock divided by a programmable prescaler (selection through the \nRTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC \nclock\nBits 7:3 Reserved, must be kept at reset value.\n" }, { "page_number": 262, "page_indices": { "start_index": 613255, "end_index": 615255 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 262 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.21 RCC clock control & status register (RCC_CSR)", 262 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n262/1757\nRM0090 Rev 21\n7.3.21 \nRCC clock control & status register (RCC_CSR)\nAddress offset: 0x74\nReset value: 0x0E00 0000, reset by system reset, except reset flags by power reset only.\nAccess: 0 ≤ wait state ≤ 3, word, half-word and byte access\nWait states are inserted in case of successive accesses to this register.\n \n \nBit 2 LSEBYP: External low-speed oscillator bypass\nSet and cleared by software to bypass the oscillator. This bit can be written only when the \nLSE clock is disabled.\n0: LSE oscillator not bypassed\n1: LSE oscillator bypassed\nBit 1 LSERDY: External low-speed oscillator ready\nSet and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After \nthe LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock \ncycles.\n0: LSE clock not ready\n1: LSE clock ready\nBit 0 LSEON: External low-speed oscillator enable\nSet and cleared by software.\n0: LSE clock OFF\n1: LSE clock ON\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nLPWR\nRSTF\nWWDG\nRSTF\nIWDG\nRSTF\nSFT\nRSTF\nPOR\nRSTF\nPIN\nRSTF\nBORRS\nTF\nRMVF\nReserved\nr\nr\nr\nr\nr\nr\nr\nrt_w\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLSIRDY\nLSION\nr\nrw\nBit 31 LPWRRSTF: Low-power reset flag\nSet by hardware when a Low-power management reset occurs.\nCleared by writing to the RMVF bit.\n0: No Low-power management reset occurred\n1: Low-power management reset occurred\nFor further information on Low-power management reset, refer to Low-power management \nreset.\nBit 30 WWDGRSTF: Window watchdog reset flag\nSet by hardware when a window watchdog reset occurs.\nCleared by writing to the RMVF bit.\n0: No window watchdog reset occurred\n1: Window watchdog reset occurred\nBit 29 IWDGRSTF: Independent watchdog reset flag\nSet by hardware when an independent watchdog reset from VDD domain occurs.\nCleared by writing to the RMVF bit.\n0: No watchdog reset occurred\n1: Watchdog reset occurred\n" }, { "page_number": 263, "page_indices": { "start_index": 615255, "end_index": 616677 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 263 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.21 RCC clock control & status register (RCC_CSR)", 262 ] ], "page_content": "RM0090 Rev 21\n263/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nBit 28 SFTRSTF: Software reset flag\nSet by hardware when a software reset occurs.\nCleared by writing to the RMVF bit.\n0: No software reset occurred\n1: Software reset occurred\nBit 27 PORRSTF: POR/PDR reset flag\nSet by hardware when a POR/PDR reset occurs.\nCleared by writing to the RMVF bit.\n0: No POR/PDR reset occurred\n1: POR/PDR reset occurred\nBit 26 PINRSTF: PIN reset flag\nSet by hardware when a reset from the NRST pin occurs.\nCleared by writing to the RMVF bit.\n0: No reset from NRST pin occurred\n1: Reset from NRST pin occurred\nBit 25 BORRSTF: BOR reset flag\nCleared by software by writing the RMVF bit.\nSet by hardware when a POR/PDR or BOR reset occurs.\n0: No POR/PDR or BOR reset occurred\n1: POR/PDR or BOR reset occurred\nBit 24 RMVF: Remove reset flag\nSet by software to clear the reset flags.\n0: No effect\n1: Clear the reset flags\nBits 23:2 Reserved, must be kept at reset value.\nBit 1 LSIRDY: Internal low-speed oscillator ready\nSet and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable. \nAfter the LSION bit is cleared, LSIRDY goes low after 3 LSI clock cycles.\n0: LSI RC oscillator not ready\n1: LSI RC oscillator ready\nBit 0 LSION: Internal low-speed oscillator enable\nSet and cleared by software.\n0: LSI RC oscillator OFF\n1: LSI RC oscillator ON\n" }, { "page_number": 264, "page_indices": { "start_index": 616677, "end_index": 618314 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 264 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.22 RCC spread spectrum clock generation register (RCC_SSCGR)", 264 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n264/1757\nRM0090 Rev 21\n7.3.22 \nRCC spread spectrum clock generation register (RCC_SSCGR)\nAddress offset: 0x80\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access.\nThe spread spectrum clock generation is available only for the main PLL.\nThe RCC_SSCGR register must be written either before the main PLL is enabled or after \nthe main PLL disabled.\nNote:\nFor full details about PLL spread spectrum clock generation (SSCG) characteristics, refer to \nthe “Electrical characteristics” section in your device datasheet. \n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nSSCG\nEN\nSPR\nEAD\nSEL\nReserved\nINCSTEP\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nINCSTEP\nMODPER\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 SSCGEN: Spread spectrum modulation enable\nSet and cleared by software.\n0: Spread spectrum modulation DISABLE. (To write after clearing CR[24]=PLLON bit)\n1: Spread spectrum modulation ENABLE. (To write before setting CR[24]=PLLON bit)\nBit 30 SPREADSEL: Spread Select\nSet and cleared by software.\nTo write before to set CR[24]=PLLON bit.\n0: Center spread\n1: Down spread\nBits 29:28 Reserved, must be kept at reset value.\nBits 27:13 INCSTEP: Incrementation step\nSet and cleared by software. To write before setting CR[24]=PLLON bit.\nConfiguration input for modulation profile amplitude.\nBits 12:0 MODPER: Modulation period\nSet and cleared by software. To write before setting CR[24]=PLLON bit.\nConfiguration input for modulation profile period.\n" }, { "page_number": 265, "page_indices": { "start_index": 618314, "end_index": 619885 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 265 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.23 RCC PLLI2S configuration register (RCC_PLLI2SCFGR)", 265 ] ], "page_content": "RM0090 Rev 21\n265/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n7.3.23 \nRCC PLLI2S configuration register (RCC_PLLI2SCFGR)\nAddress offset: 0x84\nReset value: 0x2000 3000\nAccess: no wait state, word, half-word and byte access.\nThis register is used to configure the PLLI2S clock outputs according to the formulas:\n•\nf(VCO clock) = f(PLLI2S clock input) × (PLLI2SN / PLLM)\n•\nf(PLL I2S clock output) = f(VCO clock) / PLLI2SR\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserv\ned\nPLLI2S\nR2\nPLLI2S\nR1\nPLLI2S\nR0\nReserved\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserv\ned\nPLLI2SN\n8\nPLLI2SN\n7\nPLLI2SN\n6\nPLLI2SN\n5\nPLLI2SN\n4\nPLLI2SN\n3\nPLLI2SN\n2\nPLLI2SN\n1\nPLLI2SN\n0\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBits 30:28 PLLI2SR: PLLI2S division factor for I2S clocks\nSet and cleared by software to control the I2S clock frequency. These bits should be written \nonly if the PLLI2S is disabled. The factor must be chosen in accordance with the prescaler \nvalues inside the I2S peripherals, to reach 0.3% error when using standard crystals and 0% \nerror with audio crystals. For more information about I2S clock frequency and precision, \nrefer to Section 28.4.4: Clock generator in the I2S chapter.\nCaution: The I2Ss requires a frequency lower than or equal to 192 MHz to work correctly.\nI2S clock frequency = VCO frequency / PLLR with 2 ≤ PLLR ≤ 7\n000: PLLR = 0, wrong configuration\n001: PLLR = 1, wrong configuration\n010: PLLR = 2\n...\n111: PLLR = 7\n" }, { "page_number": 266, "page_indices": { "start_index": 619885, "end_index": 621142 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 266 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.23 RCC PLLI2S configuration register (RCC_PLLI2SCFGR)", 265 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n266/1757\nRM0090 Rev 21\nBits 27:15 Reserved, must be kept at reset value.\nBits 14:6 PLLI2SN: PLLI2S multiplication factor for VCO\nThese bits are set and cleared by software to control the multiplication factor of the VCO. \nThese bits can be written only when PLLI2S is disabled. Only half-word and word accesses \nare allowed to write these bits.\nCaution: The software has to set these bits correctly to ensure that the VCO output \nfrequency is between 100 and 432 MHz. \nVCO output frequency = VCO input frequency × PLLI2SN with 50 ≤ PLLI2SN ≤ 432\n000000000: PLLI2SN = 0, wrong configuration \n000000001: PLLI2SN = 1, wrong configuration\n...\n000110010: PLLI2SN = 50\n...\n001100011: PLLI2SN = 99 \n001100100: PLLI2SN = 100\n001100101: PLLI2SN = 101\n001100110: PLLI2SN = 102\n... \n110110000: PLLI2SN = 432\n110110001: PLLI2SN = 433, wrong configuration\n... \n111111111: PLLI2SN = 511, wrong configuration \nNote: Multiplication factors ranging from 50 and 99 are possible for VCO input frequency \nhigher than 1 MHz. However care must be taken that the minimum VCO output \nfrequency respects the value specified above. \nBits 5:0 Reserved, must be kept at reset value.\n" }, { "page_number": 267, "page_indices": { "start_index": 621142, "end_index": 623924 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 267 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.24 RCC register map", 267 ] ], "page_content": "RM0090 Rev 21\n267/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\n7.3.24 \nRCC register map\nTable 35 gives the register map and reset values.\n \nTable 35. RCC register map and reset values \nAddr. \noffset\nRegister \nname\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nRCC_CR\nReserved\nPLL I2SRDY\nPLL I2SON\nPLL RDY\nPLL ON\nReserved\nCSSON\nHSEBYP\nHSERDY\nHSEON\nHSICAL 7\nHSICAL 6\nHSICAL 5\nHSICAL 4\nHSICAL 3\nHSICAL 2\nHSICAL 1\nHSICAL 0\nHSITRIM 4\nHSITRIM 3\nHSITRIM 2\nHSITRIM 1\nHSITRIM 0\nReserved\nHSIRDY\nHSION\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\nX\nX\nX\nX\nX\nX\nX\nX\n1\n0\n0\n0\n0\n0\n1\n1\n0x04\nRCC_\nPLLCFGR\nReserved\nPLLQ 3\nPLLQ 2\nPLLQ 1\nPLLQ 0\nReserved\nPLLSRC\nReserved\nPLLP 1\nPLLP 0\nReserved\nPLLN 8\nPLLN 7\nPLLN 6\nPLLN 5\nPLLN 4\nPLLN 3\nPLLN 2\nPLLN 1\nPLLN 0\nPLLM 5\nPLLM 4\nPLLM 3\nPLLM 2\nPLLM 1\nPLLM 0\nReset value\n0\n1\n0\n0\n0\n0\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0x08\nRCC_CFGR\nMCO2 1\nMCO2 0\nMCO2PRE2\nMCO2PRE1\nMCO2PRE0\nMCO1PRE2\nMCO1PRE1\nMCO1PRE0\nI2SSRC\nMCO1 1\nMCO1 0\nRTCPRE 4\nRTCPRE 3\nRTCPRE 2\nRTCPRE 1\nRTCPRE 0\nPPRE2 2\nPPRE2 1\n PPRE2 0\n PPRE1 2\nPPRE1 1\nPPRE1 0\nReserved\nHPRE 3\nHPRE 2\nHPRE 1\nHPRE 0\nSWS 1\nSWS 0\nSW 1\nSW 0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nRCC_CIR\nReserved\nCSSC\nReserved\nPLLI2SRDYC\nPLLRDYC\nHSERDYC\nHSIRDYC\nLSERDYC\nLSIRDYC\nReserved\nPLLI2SRDYIE\nPLLRDYIE\nHSERDYIE\nHSIRDYIE\nLSERDYIE\nLSIRDYIE\nCSSF\nReserved\nPLLI2SRDYF\nPLLRDYF\nHSERDYF\nHSIRDYF\nLSERDYF\nLSIRDYF\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nRCC_\nAHB1RSTR\nReserved\nOTGHSRST\nReserved\nETHMACRST\nReserved\nDMA2RST\nDMA1RST\nReserved\nCRCRST\nReserved\nGPIOIRST\nGPIOHRST\nGPIOGRST\nGPIOFRST\nGPIOERST\nGPIODRST\nGPIOCRST\nGPIOBRST\nGPIOARST\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nRCC_\nAHB2RSTR\nReserved\nOTGFSRS\nRNGRST\nHSAHRST\nCRYPRST\nReserved\nDCMIRST\nReset value\n0x18\nRCC_\nAHB3RSTR\nReserved\nFSMCRST\nReset value\n0\n0x1C\nReserved\nReserved\n0x20\nRCC_\nAPB1RSTR\nReserved\nDACRST\nPWRRST\nReserved\nCAN2RST\nCAN1RST\nReserved\nI2C3RST\nI2C2RST\nI2C1RST\nUART5RST\nUART4RST\nUART3RST\nUART2RST\nReserved\nSPI3RST\nSPI2RST\nReserved\nWWDGRST\nReserved\nTIM14RST\nTIM13RST\nTIM12RST\nTIM7RST\nTIM6RST\nTIM5RST\nTIM4RST\nTIM3RST\nTIM2RST\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x24\nRCC_\nAPB2RSTR\nReserved\nTIM11RST\nTIM10RST\nTIM9RST\nReserved\nSYSCFGRST\nReserved\nSPI1RST\nSDIORST\nReserved\nADCRST\nReserved\nUSART6RST\nUSART1RST\nReserved\nTIM8RST\nTIM1RST\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nReserved\nReserved\n0x2C\nReserved\nReserved\n0x30\nRCC_\nAHB1ENR\nReserved\nOTGHSULPIEN\nOTGHSEN\nETHMACPTPEN\nETHMACRXEN\nETHMACTXEN\nETHMACEN\nReserved\nDMA2EN\nDMA1EN\nCCMDATARAMEN\nReserved\nBKPSRAMEN\nReserved\nCRCEN\nReserved\nGPIOIEN\nGPIOHEN\nGPIOGEN\nGPIOFEN\nGPIOEEN\nGPIODEN\nGPIOCEN\nGPIOBEN\nGPIOAEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n" }, { "page_number": 268, "page_indices": { "start_index": 623924, "end_index": 626200 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 268 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.24 RCC register map", 267 ] ], "page_content": "Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\nRM0090\n268/1757\nRM0090 Rev 21\n0x34\nRCC_\nAHB2ENR\nReserved\nOTGFSEN\nRNGEN\nHASHEN\nCRYPEN\nReserved\nDCMIEN\nReset value\n0\n0\n0\n0\n0\n0x38\nRCC_\nAHB3ENR\nReserved\nFSMCEN\nReset value\n0\n0x3C\nReserved\nReserved\n0x40\nRCC_\nAPB1ENR\nReserved\nDACEN\nPWREN\nReserved\nCAN2EN\nCAN1EN\nReserved\nI2C3EN\nI2C2EN\nI2C1EN\nUART5EN\nUART4EN\nUSART3EN\nUSART2EN\nReserved\nSPI3EN\nSPI2EN\nReserved\nWWDGEN\nReserved\nTIM14EN\nTIM13EN\nTIM12EN\nTIM7EN\nTIM6EN\nTIM5EN\nTIM4EN\nTIM3EN\nTIM2EN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x44\nRCC_\nAPB2ENR\nReserved\nTIM11EN\nTIM10EN\nTIM9EN\nReserved\nSYSCFGEN\nReserved\nSPI1EN\nSDIOEN\nADC3EN\nADC2EN\nADC1EN\nReserved\nUSART6EN\nUSART1EN\nReserved\nTIM8EN\nTIM1EN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x48\nReserved\nReserved\n0x4C\nReserved\nReserved\n0x50\nRCC_\nAHB1LPENR\nReserved\nOTGHSULPILPEN\nOTGHSLPEN\nETHMACPTPLPEN\nETHMACRXLPEN\nETHMACTXLPEN\nETHMACLPEN\nReserved\nDMA2LPEN\nDMA1LPEN\nReserved\nBKPSRAMLPEN\nSRAM2LPEN\nSRAM1LPEN\nFLITFLPEN\nReserved\nCRCLPEN\nReserved\nGPIOILPEN\nGPIOHLPEN\nGPIOGLPEN\nGPIOFLPEN\nGPIOELPEN\nGPIODLPEN\nGPIOCLPEN\nGPIOBLPEN\nGPIOALPEN\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x54\nRCC_\nAHB2LPENR\nReserved\nOTGFSLPEN\nRNGLPEN\nHASHLPEN\nCRYPLPEN\nReserved\nDCMILPEN\nReset value\n1\n1\n1\n1\n1\n0x58\nRCC_\nAHB3LPENR\nReserved\nFSMCLPEN\nReset value\n1\n0x5C\nReserved\nReserved\n0x60\nRCC_\nAPB1LPENR\nReserved\nDACLPEN\nPWRLPEN\nReserved\nCAN2LPEN\nCAN1LPEN\nReserved\nI2C3LPEN\nI2C2LPEN\nI2C1LPEN\nUART5LPEN\nUART4LPEN\nUSART3LPEN\nUSART2LPEN\nReserved\nSPI3LPEN\nSPI2LPEN\nReserved\nWWDGLPEN\nReserved\nTIM14LPEN\nTIM13LPEN\nTIM12LPEN\nTIM7LPEN\nTIM6LPEN\nTIM5LPEN\nTIM4LPEN\nTIM3LPEN\nTIM2LPEN\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x64\nRCC_\nAPB2LPENR\nReserved\nTIM11LPEN\nTIM10LPEN\nTIM9LPEN\nReserved\nSYSCFGLPEN\nReserved\nSPI1LPEN\nSDIOLPEN\nADC3LPEN\nADC2LPEN\nADC1LPEN\nReserved\nUSART6LPEN\nUSART1LPEN\nReserved\nTIM8LPEN\nTIM1LPEN\nReset value\n1\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x68\nReserved\nReserved\n0x6C\nReserved\nReserved\n0x70\nRCC_BDCR\nReserved\nBDRST\nRTCEN\nReserved\nRTCSEL 1\nRTCSEL 0\nReserved\nLSEBYP\nLSERDY\nLSEON\nReset value\n0\n0\n0\n0\n0\n0\n0\nTable 35. RCC register map and reset values (continued)\nAddr. \noffset\nRegister \nname\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 269, "page_indices": { "start_index": 626200, "end_index": 626977 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 269 }, "toc_details": [ [ 1, "7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)", 215 ], [ 2, "7.3 RCC registers", 226 ], [ 3, "7.3.24 RCC register map", 267 ] ], "page_content": "RM0090 Rev 21\n269/1757\nRM0090\nReset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)\n269\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x74\nRCC_CSR\nLPWRRSTF\nWWDGRSTF\nWDGRSTF\nSFTRSTF\nPORRSTF\nPADRSTF\nBORRSTF\nRMVF\nReserved\nLSIRDY\nLSION\nReset value\n0\n0\n0\n0\n1\n1\n1\n1\n0\n0\n0x78\nReserved\nReserved\n0x7C\nReserved\nReserved\n0x80\nRCC_SSCGR\nSSCGEN\nSPREADSEL\nReserved\nINCSTEP\nMODPER\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x84\nRCC_\nPLLI2SCFGR\nReserved\nPLLI2SRx\nReserved\nPLLI2SNx\nReserved\nReset value\n0\n1\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\nTable 35. RCC register map and reset values (continued)\nAddr. \noffset\nRegister \nname\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 270, "page_indices": { "start_index": 626977, "end_index": 628887 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 270 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.1 GPIO introduction", 270 ], [ 2, "8.2 GPIO main features", 270 ], [ 2, "8.3 GPIO functional description", 270 ] ], "page_content": "General-purpose I/Os (GPIO)\nRM0090\n270/1757\nRM0090 Rev 21\n8 \nGeneral-purpose I/Os (GPIO)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n8.1 \nGPIO introduction\nEach general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, \nGPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers \n(GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking \nregister (GPIOx_LCKR) and two 32-bit alternate function selection register (GPIOx_AFRH \nand GPIOx_AFRL).\n8.2 \nGPIO main features\n•\nUp to 16 I/Os under control\n•\nOutput states: push-pull or open drain + pull-up/down\n•\nOutput data from output data register (GPIOx_ODR) or peripheral (alternate function \noutput)\n•\nSpeed selection for each I/O\n•\nInput states: floating, pull-up/down, analog\n•\nInput data to input data register (GPIOx_IDR) or peripheral (alternate function input)\n•\nBit set and reset register (GPIOx_BSRR) for bitwise write access to GPIOx_ODR\n•\nLocking mechanism (GPIOx_LCKR) provided to freeze the I/O configuration\n•\nAnalog function\n•\nAlternate function input/output selection registers (at most 16 AFs per I/O)\n•\nFast toggle capable of changing every two clock cycles\n•\nHighly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several \nperipheral functions\n8.3 \nGPIO functional description\nSubject to the specific hardware characteristics of each I/O port listed in the datasheet, each \nport bit of the general-purpose I/O (GPIO) ports can be individually configured by software in \nseveral modes:\n•\nInput floating \n•\nInput pull-up\n•\nInput-pull-down\n•\nAnalog\n•\nOutput open-drain with pull-up or pull-down capability\n•\nOutput push-pull with pull-up or pull-down capability\n•\nAlternate function push-pull with pull-up or pull-down capability\n•\nAlternate function open-drain with pull-up or pull-down capability\n" }, { "page_number": 271, "page_indices": { "start_index": 628887, "end_index": 630329 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 271 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.3 GPIO functional description", 270 ] ], "page_content": "RM0090 Rev 21\n271/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\nEach I/O port bit is freely programmable, however the I/O port registers have to be \naccessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is \nto allow atomic read/modify accesses to any of the GPIO registers. In this way, there is no \nrisk of an IRQ occurring between the read and the modify access.\nFigure 25 shows the basic structure of a 5 V tolerant I/O port bit. Table 40 gives the possible \nport bit configurations.\nFigure 25. Basic structure of a five-volt tolerant I/O port bit\n1.\nVDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD.\n \nTable 36. Port bit configuration table(1)\nMODER(i)\n[1:0]\nOTYPER(i)\nOSPEEDR(i)\n[B:A]\nPUPDR(i)\n[1:0]\nI/O configuration\n01\n0\nSPEED\n[B:A]\n0\n0\nGP output\nPP\n0\n0\n1\nGP output\nPP + PU\n0\n1\n0\nGP output\nPP + PD\n0\n1\n1\nReserved \n1\n0\n0\nGP output\nOD \n1\n0\n1\nGP output\nOD + PU\n1\n1\n0\nGP output\nOD + PD\n1\n1\n1\nReserved (GP output OD)\nAlternate function output\nAlternate function input\nPush-pull,\nopen-drain or\ndisabled\nOutput data register\nRead/write\nFrom on-chip \nperipheral\nTo on-chip \nperipheral\nOutput\ncontrol\nAnalog\non/off\nPull\nPull\non/off\nI/O pin\nVDD\nVDD\nVSS\nVSS\nTTL Schmitt \n trigger\nVSS\nVDD_FT\n(1)\nProtection\ndiode\nProtection\ndiode\non/off\nInput driver\nOutput driver\ndown\nup\nP-MOS\nN-MOS\nRead\nBit set/reset registers\nWrite\nAnalog\nInput data register\nai15939b\n" }, { "page_number": 272, "page_indices": { "start_index": 630329, "end_index": 631823 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 272 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.3 GPIO functional description", 270 ], [ 3, "8.3.1 General-purpose I/O (GPIO)", 272 ] ], "page_content": "General-purpose I/Os (GPIO)\nRM0090\n272/1757\nRM0090 Rev 21\n8.3.1 \nGeneral-purpose I/O (GPIO)\nDuring and just after reset, the alternate functions are not active and the I/O ports are \nconfigured in input floating mode.\nThe debug pins are in AF pull-up/pull-down after reset:\n•\nPA15: JTDI in pull-up\n•\nPA14: JTCK/SWCLK in pull-down\n•\nPA13: JTMS/SWDAT in pull-up\n•\nPB4: NJTRST in pull-up\n•\nPB3: JTDO in floating state\nWhen the pin is configured as output, the value written to the output data register \n(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull \nmode or open-drain mode (only the N-MOS is activated when 0 is output).\nThe input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB1 \nclock cycle.\nAll GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or \nnot depending on the value in the GPIOx_PUPDR register.\n10\n0\nSPEED\n[B:A]\n0\n0\nAF\nPP\n0\n0\n1\nAF\nPP + PU\n0\n1\n0\nAF\nPP + PD\n0\n1\n1\nReserved\n1\n0\n0\nAF\nOD\n1\n0\n1\nAF\nOD + PU\n1\n1\n0\nAF\nOD + PD\n1\n1\n1\nReserved\n00\nx\nx\nx\n0\n0\nInput\nFloating\nx\nx\nx\n0\n1\nInput\nPU\nx\nx\nx\n1\n0\nInput\nPD\nx\nx\nx\n1\n1\nReserved (input floating)\n11\nx\nx\nx\n0\n0\nInput/output\nAnalog\nx\nx\nx\n0\n1\nReserved\nx\nx\nx\n1\n0\nx\nx\nx\n1\n1\n1.\nGP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate \nfunction.\nTable 36. Port bit configuration table(1) (continued)\nMODER(i)\n[1:0]\nOTYPER(i)\nOSPEEDR(i)\n[B:A]\nPUPDR(i)\n[1:0]\nI/O configuration\n" }, { "page_number": 273, "page_indices": { "start_index": 631823, "end_index": 633577 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 273 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.3 GPIO functional description", 270 ], [ 3, "8.3.2 I/O pin multiplexer and mapping", 273 ] ], "page_content": "RM0090 Rev 21\n273/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\n8.3.2 \nI/O pin multiplexer and mapping\nThe microcontroller I/O pins are connected to onboard peripherals/modules through a \nmultiplexer that allows only one peripheral’s alternate function (AF) connected to an I/O pin \nat a time. In this way, there can be no conflict between peripherals sharing the same I/O pin.\nEach I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that can \nbe configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) \nregisters:\n•\nAfter reset all I/Os are connected to the system’s alternate function 0 (AF0)\n•\nThe peripherals’ alternate functions are mapped from AF1 to AF13\n•\nCortex®-M4 with FPU EVENTOUT is mapped on AF15\nThis structure is shown in Figure 26 below.\nIn addition to this flexible I/O multiplexing architecture, each peripheral has alternate \nfunctions mapped onto different I/O pins to optimize the number of peripherals available in \nsmaller packages.\nTo use an I/O in a given configuration, proceed as follows:\n•\nSystem function\nConnect the I/O to AF0 and configure it depending on the function used:\n–\nJTAG/SWD, after each device reset these pins are assigned as dedicated pins \nimmediately usable by the debugger host (not controlled by the GPIO controller)\n–\nRTC_REFIN: this pin should be configured in Input floating mode\n–\nMCO1 and MCO2: these pins have to be configured in alternate function mode.\nNote:\nThe user can disable some or all of the JTAG/SWD pins and so release the associated pins \nfor GPIO usage (released pins highlighted in gray in the table).\nFor more details refer to Section 7.2.10: Clock-out capability and Section 6.2.10: Clock-out \ncapability.\n" }, { "page_number": 274, "page_indices": { "start_index": 633577, "end_index": 634889 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 274 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.3 GPIO functional description", 270 ], [ 3, "8.3.2 I/O pin multiplexer and mapping", 273 ] ], "page_content": "General-purpose I/Os (GPIO)\nRM0090\n274/1757\nRM0090 Rev 21\n \n•\nGPIO\nConfigure the desired I/O as output or input in the GPIOx_MODER register.\n•\nPeripheral alternate function\nFor the ADC and DAC, configure the desired I/O as analog in the GPIOx_MODER \nregister.\nFor other peripherals:\n–\nConfigure the desired I/O as an alternate function in the GPIOx_MODER register\n–\nSelect the type, pull-up/pull-down and output speed via the GPIOx_OTYPER, \nGPIOx_PUPDR and GPIOx_OSPEEDR registers, respectively\n–\nConnect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register\n•\nEVENTOUT\nConfigure the I/O pin used to output the Cortex®-M4 with FPU EVENTOUT signal by \nconnecting it to AF15\nNote:\nEVENTOUT is not mapped onto the following I/O pins: PC13, PC14, PC15, PH0, PH1 and \nPI8.\nRefer to the “Alternate function mapping” table in the datasheets for the detailed mapping of \nthe system and peripherals’ alternate function I/O pins.\nTable 37. Flexible SWJ-DP pin assignment\nAvailable debug ports\nSWJ I/O pin assigned\nPA13 /\nJTMS/\nSWDIO\nPA14 /\nJTCK/\nSWCLK\nPA15 /\nJTDI\nPB3 / \nJTDO\nPB4/\nNJTRST\nFull SWJ (JTAG-DP + SW-DP) - Reset state\nX\nX\nX\nX\nX\nFull SWJ (JTAG-DP + SW-DP) but without \nNJTRST\nX\nX\nX\nX\nJTAG-DP Disabled and SW-DP Enabled\nX\nX\nJTAG-DP Disabled and SW-DP Disabled\nReleased\n" }, { "page_number": 275, "page_indices": { "start_index": 634889, "end_index": 635835 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 275 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.3 GPIO functional description", 270 ], [ 3, "8.3.2 I/O pin multiplexer and mapping", 273 ] ], "page_content": "RM0090 Rev 21\n275/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\nFigure 26. Selecting an alternate function on STM32F405xx/07xx and \nSTM32F415xx/17xx \n1.\nConfigured in FS.\nai17538\nFor pins 0 to 7, the GPIOx_AFRL[31:0] register selects the dedicated alternate function \nAF0 (system)\nAF1 (TIM1/TIM2)\nAF2 (TIM3..5)\nAF3 (TIM8..11)\nAF4 (I2C1..3)\nAF5 (SPI1/SPI2)\nAF6 (SPI3)\nAF7 (USART1..3)\nAF8 (USART4..6)\nAF9 (CAN1/CAN2, TIM12..14)\nAF10 (OTG_FS, OTG_HS)\nAF11 (ETH)\nAF12 (FSMC, SDIO, OTG_HS(1))\nAF13 (DCMI)\nAF14\nAF15 (EVENTOUT)\nPin x (x = 0..7)\nAFRL[31:0]\nFor pins 8 to 15, the GPIOx_AFRH[31:0] register selects the dedicated alternate function \nAF0 (system)\nAF1 (TIM1/TIM2)\nAF2 (TIM3..5)\nAF3 (TIM8..11)\nAF4 (I2C1..3)\nAF5 (SPI1/SPI2)\nAF6 (SPI3)\nAF7 (USART1..3)\nAF8 (USART4..6)\nAF9 (CAN1/CAN2, TIM12..14)\nAF10 (OTG_FS, OTG_HS)\nAF11 (ETH)\nAF12 (FSMC, SDIO, OTG_HS(1))\nAF13 (DCMI)\nAF14\nAF15 (EVENTOUT)\nPin x (x = 8..15)\nAFRH[31:0]\n1\n1\n" }, { "page_number": 276, "page_indices": { "start_index": 635835, "end_index": 636813 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 276 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.3 GPIO functional description", 270 ], [ 3, "8.3.2 I/O pin multiplexer and mapping", 273 ] ], "page_content": "General-purpose I/Os (GPIO)\nRM0090\n276/1757\nRM0090 Rev 21\nFigure 27. Selecting an alternate function on STM32F42xxx and STM32F43xxx \n1.\nConfigured in FS.\nMS60208V1\nFor pins 0 to 7, the GPIOx_AFRL[31:0] register selects the dedicated alternate function \nAF0 (system)\nAF1 (TIM1/TIM2)\nAF2 (TIM3..5)\nAF3 (TIM8..11)\nAF4 (I2C1..3)\nAF5 (SPI1/2/3/4/5/6)\nAF6 (SPI2/3/SAI1)\nAF7 (USART1..3)\nAF8 (USART4..8)\nAF9 (CAN1/CAN2, LTDC, TIM12..14)\nAF10 (OTG_FS, OTG_HS)\nAF11 (ETH)\nAF12 (FMC, SDIO, OTG_HS(1))\nAF13 (DCMI)\nAF14 (LTDC)\nAF15 (EVENTOUT)\nPin x (x = 0..7)\nAFRL[31:0]\nFor pins 8 to 15, the GPIOx_AFRH[31:0] register selects the dedicated alternate function \nAF0 (system)\nAF1 (TIM1/TIM2)\nAF2 (TIM3..5)\nAF3 (TIM8..11)\nAF4 (I2C1..3)\nAF5 (SPI1/2/4/5/6)\nAF6 (SPI2/3/SAI1)\nAF7 (USART1..3)\nAF8 (USART4..8)\nAF9 (CAN1/CAN2, TIM12..14)\nAF10 (OTG_FS, OTG_HS)\nAF11 (ETH)\nAF12 (FMC, SDIO, OTG_HS(1))\nAF13 (DCMI)\nAF14 (LTDC)\nAF15 (EVENTOUT)\nPin x (x = 8..15)\nAFRH[31:0]\n1\n1\n" }, { "page_number": 277, "page_indices": { "start_index": 636813, "end_index": 639893 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 277 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.3 GPIO functional description", 270 ], [ 3, "8.3.3 I/O port control registers", 277 ], [ 3, "8.3.4 I/O port data registers", 277 ], [ 3, "8.3.5 I/O data bitwise handling", 277 ], [ 3, "8.3.6 GPIO locking mechanism", 277 ] ], "page_content": "RM0090 Rev 21\n277/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\n8.3.3 \nI/O port control registers\nEach of the GPIOs has four 32-bit memory-mapped control registers (GPIOx_MODER, \nGPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. \nThe GPIOx_MODER register is used to select the I/O direction (input, output, AF, analog). \nThe GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type \n(push-pull or open-drain) and speed (the I/O speed pins are directly connected to the \ncorresponding GPIOx_OSPEEDR register bits whatever the I/O direction). The \nGPIOx_PUPDR register is used to select the pull-up/pull-down whatever the I/O direction.\n8.3.4 \nI/O port data registers\nEach GPIO has two 16-bit memory-mapped data registers: input and output data registers \n(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write \naccessible. The data input through the I/O are stored into the input data register \n(GPIOx_IDR), a read-only register.\nSee Section 8.4.5: GPIO port input data register (GPIOx_IDR) (x = A..I/J/K) and \nSection 8.4.6: GPIO port output data register (GPIOx_ODR) (x = A..I/J/K) for the register \ndescriptions.\n8.3.5 \nI/O data bitwise handling\nThe bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to \nset and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset \nregister has twice the size of GPIOx_ODR.\nTo each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BSRR(i) and \nBSRR(i+SIZE). When written to 1, bit BSRR(i) sets the corresponding ODR(i) bit. When \nwritten to 1, bit BSRR(i+SIZE) resets the ODR(i) corresponding bit.\nWriting any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in \nGPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set \naction takes priority.\nUsing the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a \n“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always \nbe accessed directly. The GPIOx_BSRR register provides a way of performing atomic \nbitwise handling.\nThere is no need for the software to disable interrupts when programming the GPIOx_ODR \nat bit level: it is possible to modify one or more bits in a single atomic AHB1 write access.\n8.3.6 \nGPIO locking mechanism\nIt is possible to freeze the GPIO control registers by applying a specific write sequence to \nthe GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER, \nGPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\nTo write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When \nthe right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used \nto lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must \nbe the same). When the LOCK sequence has been applied to a port bit, the value of the port \nbit can no longer be modified until the next MCU or peripheral reset. Each GPIOx_LCKR bit \n" }, { "page_number": 278, "page_indices": { "start_index": 639893, "end_index": 642169 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 278 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.3 GPIO functional description", 270 ], [ 3, "8.3.7 I/O alternate function input/output", 278 ], [ 3, "8.3.8 External interrupt/wake-up lines", 278 ], [ 3, "8.3.9 Input configuration", 278 ] ], "page_content": "General-purpose I/Os (GPIO)\nRM0090\n278/1757\nRM0090 Rev 21\nfreezes the corresponding bit in the control registers (GPIOx_MODER, GPIOx_OTYPER, \nGPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH).\nThe LOCK sequence (refer to Section 8.4.8: GPIO port configuration lock register \n(GPIOx_LCKR) (x = A..I/J/K)) can only be performed using a word (32-bit long) access to \nthe GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same \ntime as the [15:0] bits.\nFor more details refer to LCKR register description in Section 8.4.8: GPIO port configuration \nlock register (GPIOx_LCKR) (x = A..I/J/K).\n8.3.7 \nI/O alternate function input/output\nTwo registers are provided to select one out of the sixteen alternate function inputs/outputs \navailable for each I/O. With these registers, you can connect an alternate function to some \nother pin as required by your application.\nThis means that a number of possible peripheral functions are multiplexed on each GPIO \nusing the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can \nthus select any one of the possible functions for each I/O. The AF selection signal being \ncommon to the alternate function input and alternate function output, a single channel is \nselected for the alternate function input/output of one I/O.\nTo know which functions are multiplexed on each GPIO pin, refer to the datasheets.\nNote:\nThe application is allowed to select one of the possible peripheral functions for each I/O at a \ntime.\n8.3.8 \nExternal interrupt/wake-up lines\nAll ports have external interrupt capability. To use external interrupt lines, the port must be \nconfigured in input mode, refer to Section 12.2: External interrupt/event controller (EXTI) \nand Section 12.2.3: Wake-up event management.\n8.3.9 \nInput configuration\nWhen the I/O port is programmed as Input:\n•\nthe output buffer is disabled\n•\nthe Schmitt trigger input is activated\n•\nthe pull-up and pull-down resistors are activated depending on the value in the \nGPIOx_PUPDR register\n•\nThe data present on the I/O pin are sampled into the input data register every AHB1 \nclock cycle\n•\nA read access to the input data register provides the I/O State\nFigure 28 shows the input configuration of the I/O port bit.\n" }, { "page_number": 279, "page_indices": { "start_index": 642169, "end_index": 643392 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 279 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.3 GPIO functional description", 270 ], [ 3, "8.3.10 Output configuration", 279 ] ], "page_content": "RM0090 Rev 21\n279/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\nFigure 28. Input floating/pull up/pull down configurations\n8.3.10 \nOutput configuration\nWhen the I/O port is programmed as output:\n•\nThe output buffer is enabled:\n–\nOpen drain mode: A “0” in the Output register activates the N-MOS whereas a “1” \nin the Output register leaves the port in Hi-Z (the P-MOS is never activated)\n–\nPush-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in \nthe Output register activates the P-MOS\n•\nThe Schmitt trigger input is activated\n•\nThe weak pull-up and pull-down resistors are activated or not depending on the value \nin the GPIOx_PUPDR register\n•\nThe data present on the I/O pin are sampled into the input data register every AHB1 \nclock cycle\n•\nA read access to the input data register gets the I/O state\n•\nA read access to the output data register gets the last written value\nFigure 29 shows the output configuration of the I/O port bit.\non/off\npull\npull\non/off\nI/O pin\nVDD\nVSS\nTTL Schmitt \n trigger\nVSS\nVDD\nprotection\ndiode\nprotection\ndiode\non\ninput driver\noutput driver\ndown\nup\nInput data register\nOutput data register\nRead/write\nRead\nBit set/reset registers\nWrite\nai15940b\n" }, { "page_number": 280, "page_indices": { "start_index": 643392, "end_index": 644896 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 280 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.3 GPIO functional description", 270 ], [ 3, "8.3.11 Alternate function configuration", 280 ] ], "page_content": "General-purpose I/Os (GPIO)\nRM0090\n280/1757\nRM0090 Rev 21\nFigure 29. Output configuration\n8.3.11 \nAlternate function configuration\nWhen the I/O port is programmed as alternate function:\n•\nThe output buffer can be configured as open-drain or push-pull\n•\nThe output buffer is driven by the signal coming from the peripheral (transmitter enable \nand data)\n•\nThe Schmitt trigger input is activated\n•\nThe weak pull-up and pull-down resistors are activated or not depending on the value \nin the GPIOx_PUPDR register\n•\nThe data present on the I/O pin are sampled into the input data register every AHB1 \nclock cycle\n•\nA read access to the input data register gets the I/O state\nFigure 30 shows the Alternate function configuration of the I/O port bit.\nFigure 30. Alternate function configuration\nPush-pull or\nOpen-drain\nOutput\ncontrol\nVDD\nVSS\nTTL Schmitt \n trigger\non\nInput driver\nOutput driver\nP-MOS\nN-MOS\nInput data register\nOutput data register\nRead/write\nRead\nBit set/reset registers\nWrite\non/off\npull\npull\non/off\nVDD\nVSS\nVSS\nVDD\nprotection\ndiode\nprotection\ndiode\ndown\nup\nI/O pin\nai15941b\nAlternate function output\nAlternate function input\npush-pull or\nopen-drain\nFrom on-chip \nperipheral\nTo on-chip \nperipheral\nOutput\ncontrol\nVDD\nVSS\nTTL Schmitt \n trigger\non\nInput driver\nOutput driver\nP-MOS\nN-MOS\nInput data register\nOutput data register\nRead/write\nRead\nBit set/reset registers\nWrite\non/off\non/off\nVDD\nVSS\nVSS\nVDD\nprotection\ndiode\nprotection\ndiode\nPull\nPull\nI/O pin\ndown\nup\nai15942b\n" }, { "page_number": 281, "page_indices": { "start_index": 644896, "end_index": 646998 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 281 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.3 GPIO functional description", 270 ], [ 3, "8.3.12 Analog configuration", 281 ], [ 3, "8.3.13 Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins", 281 ], [ 3, "8.3.14 Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins", 281 ] ], "page_content": "RM0090 Rev 21\n281/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\n8.3.12 \nAnalog configuration\nWhen the I/O port is programmed as analog configuration:\n•\nThe output buffer is disabled\n•\nThe Schmitt trigger input is deactivated, providing zero consumption for every analog \nvalue of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).\n•\nThe weak pull-up and pull-down resistors are disabled\n•\nRead access to the input data register gets the value “0”\nNote:\nIn the analog configuration, the I/O pins cannot be 5 Volt tolerant.\nFigure 31 shows the high-impedance, analog-input configuration of the I/O port bit.\nFigure 31. High impedance-analog configuration\n8.3.13 \nUsing the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15\nport pins\nThe LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose \nPC14 and PC15 I/Os, respectively, when the LSE oscillator is off. The PC14 and PC15 I/Os \nare only configured as LSE oscillator pins OSC32_IN and OSC32_OUT when the LSE \noscillator is ON. This is done by setting the LSEON bit in the RCC_BDCR register. The LSE \nhas priority over the GPIO function.\nNote:\nThe PC14/PC15 GPIO functionality is lost when the 1.2 V domain is powered off (by the \ndevice entering the standby mode) or when the backup domain is supplied by VBAT (VDD no \nmore supplied). In this case the I/Os are set in analog input mode.\n8.3.14 \nUsing the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins\nThe HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 \nI/Os, respectively, when the HSE oscillator is OFF. (after reset, the HSE oscillator is off). The \nPH0/PH1 I/Os are only configured as OSC_IN/OSC_OUT HSE oscillator pins when the \nHSE oscillator is ON. This is done by setting the HSEON bit in the RCC_CR register. The \nHSE has priority over the GPIO function.\nFrom on-chip \nperipheral\nTo on-chip \nperipheral\nAnalog\n trigger\noff\nInput driver\n0\nInput data register\nOutput data register\nRead/write\nRead\nBit set/reset registers\nWrite\nAnalog\nVSS\nVDD\nprotection\ndiode\nprotection\ndiode\nI/O pin\nai15943\nTTL Schmitt \n" }, { "page_number": 282, "page_indices": { "start_index": 646998, "end_index": 649031 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 282 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.3 GPIO functional description", 270 ], [ 3, "8.3.15 Selection of RTC_AF1 and RTC_AF2 alternate functions", 282 ] ], "page_content": "General-purpose I/Os (GPIO)\nRM0090\n282/1757\nRM0090 Rev 21\n8.3.15 \nSelection of RTC_AF1 and RTC_AF2 alternate functions\nThe STM32F4xx feature two GPIO pins RTC_AF1 and RTC_AF2 that can be used for the \ndetection of a tamper or time stamp event, or RTC_ALARM, or RTC_CALIB RTC outputs.\n•\nThe RTC_AF1 (PC13) can be used for the following purposes:\nRTC_ALARM output: this output can be RTC Alarm A, RTC Alarm B or RTC Wake-up \ndepending on the OSEL[1:0] bits in the RTC_CR register\n•\nRTC_CALIB output: this feature is enabled by setting the COE[23] in the RTC_CR \nregister\n•\nRTC_TAMP1: tamper event detection\n•\nRTC_TS: time stamp event detection\nThe RTC_AF2 (PI8) can be used for the following purposes:\n•\nRTC_TAMP1: tamper event detection\n•\nRTC_TAMP2: tamper event detection\n•\nRTC_TS: time stamp event detection\nThe selection of the corresponding pin is performed through the RTC_TAFCR register as \nfollows:\n•\nTAMP1INSEL is used to select which pin is used as the RTC_TAMP1 tamper input\n•\nTSINSEL is used to select which pin is used as the RTC_TS time stamp input\n•\nALARMOUTTYPE is used to select whether the RTC_ALARM is output in push-pull or \nopen-drain mode\nThe output mechanism follows the priority order listed in Table 38 and Table 39.\n \nTable 38. RTC_AF1 pin(1)\nPin \nconfiguration \nand function\nRTC_ALARM \nenabled\nRTC_CALIB \nenabled\nTamper \nenabled\nTime \nstamp \nenabled\nTAMP1INSEL \nTAMPER1 \npin selection\nTSINSEL \nTIMESTAMP \npin \nselection\nALARMOUTTYPE \nRTC_ALARM \nconfiguration\nAlarm out \noutput OD\n1\nDon’t care\nDon’t \ncare\nDon’t \ncare\nDon’t care\nDon’t care\n0\nAlarm out \noutput PP\n1\nDon’t care\nDon’t \ncare\nDon’t \ncare\nDon’t care\nDon’t care\n1\nCalibration \nout output PP\n0\n1\nDon’t \ncare\nDon’t \ncare\nDon’t care\nDon’t care\nDon’t care\nTAMPER1 \ninput floating\n0\n0\n1\n0\n0\nDon’t care\nDon’t care\nTIMESTAMP \nand \nTAMPER1 \ninput floating\n0\n0\n1\n1\n0\n0\nDon’t care\nTIMESTAMP \ninput floating\n0\n0\n0\n1\nDon’t care\n0\nDon’t care\nStandard \nGPIO\n0\n0\n0\n0\nDon’t care\nDon’t care\nDon’t care\n1.\nOD: open drain; PP: push-pull.\n" }, { "page_number": 283, "page_indices": { "start_index": 649031, "end_index": 649527 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 283 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.3 GPIO functional description", 270 ], [ 3, "8.3.15 Selection of RTC_AF1 and RTC_AF2 alternate functions", 282 ] ], "page_content": "RM0090 Rev 21\n283/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\nTable 39. RTC_AF2 pin\nPin configuration and function\nTamper \nenabled\n Time \nstamp \nenabled\nTAMP1INSEL \nTAMPER1 \npin selection\nTSINSEL \nTIMESTAMP \npin \nselection\nALARMOUTTYPE \nRTC_ALARM \nconfiguration\nTAMPER1 input floating\n1\n0\n1\nDon’t care\nDon’t care\nTIMESTAMP and TAMPER1 input \nfloating\n1\n1\n1\n1\nDon’t care\nTIMESTAMP input floating\n0\n1\nDon’t care\n1\nDon’t care\nStandard GPIO\n0\n0\nDon’t care\nDon’t care\nDon’t care\n" }, { "page_number": 284, "page_indices": { "start_index": 649527, "end_index": 651279 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 284 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.4 GPIO registers", 284 ], [ 3, "8.4.1 GPIO port mode register (GPIOx_MODER) (x = A..I/J/K)", 284 ], [ 3, "8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..I/J/K)", 284 ] ], "page_content": "General-purpose I/Os (GPIO)\nRM0090\n284/1757\nRM0090 Rev 21\n8.4 \nGPIO registers\nThis section gives a detailed description of the GPIO registers.\nFor a summary of register bits, register address offsets and reset values, refer to Table 40.\nThe GPIO registers can be accessed by byte (8 bits), half-words (16 bits) or words (32 bits). \n8.4.1 \nGPIO port mode register (GPIOx_MODER) (x = A..I/J/K)\nAddress offset: 0x00\nReset values:\n•\n0xA800 0000 for port A\n•\n0x0000 0280 for port B\n•\n0x0000 0000 for other ports\n \n \n8.4.2 \nGPIO port output type register (GPIOx_OTYPER) \n(x = A..I/J/K)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMODER15[1:0]\nMODER14[1:0]\nMODER13[1:0]\nMODER12[1:0]\nMODER11[1:0]\nMODER10[1:0]\nMODER9[1:0]\nMODER8[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMODER7[1:0]\nMODER6[1:0]\nMODER5[1:0]\nMODER4[1:0]\nMODER3[1:0]\nMODER2[1:0]\nMODER1[1:0]\nMODER0[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 2y:2y+1 MODERy[1:0]: Port x configuration bits (y = 0..15)\nThese bits are written by software to configure the I/O direction mode.\n00: Input (reset state)\n01: General purpose output mode\n10: Alternate function mode\n11: Analog mode\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOT15\nOT14\nOT13\nOT12\nOT11\nOT10\nOT9\nOT8\nOT7\nOT6\nOT5\nOT4\nOT3\nOT2\nOT1\nOT0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 OTy: Port x configuration bits (y = 0..15)\nThese bits are written by software to configure the output type of the I/O port.\n0: Output push-pull (reset state)\n1: Output open-drain\n" }, { "page_number": 285, "page_indices": { "start_index": 651279, "end_index": 652876 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 285 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.4 GPIO registers", 284 ], [ 3, "8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..I/J/K)", 285 ], [ 3, "8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..I/J/K)", 285 ] ], "page_content": "RM0090 Rev 21\n285/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\n8.4.3 \nGPIO port output speed register (GPIOx_OSPEEDR)\n(x = A..I/J/K)\nAddress offset: 0x08\nReset values:\n•\n0x0C00 0000 for port A\n•\n0x0000 00C0 for port B\n•\n0x0000 0000 for other ports\n \n \n8.4.4 \nGPIO port pull-up/pull-down register (GPIOx_PUPDR)\n(x = A..I/J/K)\nAddress offset: 0x0C\nReset values:\n•\n0x6400 0000 for port A\n•\n0x0000 0100 for port B\n•\n0x0000 0000 for other ports\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nOSPEEDR15\n[1:0]\nOSPEEDR14\n[1:0]\nOSPEEDR13\n[1:0]\nOSPEEDR12\n[1:0]\nOSPEEDR11\n[1:0]\nOSPEEDR10\n[1:0]\nOSPEEDR9\n[1:0]\nOSPEEDR8\n[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOSPEEDR7[1:0]\nOSPEEDR6[1:0]\nOSPEEDR5[1:0]\nOSPEEDR4[1:0]\nOSPEEDR3[1:0]\nOSPEEDR2[1:0]\nOSPEEDR1\n[1:0]\nOSPEEDR0\n1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 2y:2y+1 OSPEEDRy[1:0]: Port x configuration bits (y = 0..15)\nThese bits are written by software to configure the I/O output speed.\n00: Low speed\n01: Medium speed\n10: High speed\n11: Very high speed\nNote: Refer to the product datasheets for the values of OSPEEDRy bits versus VDD \nrange and external load.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nPUPDR15[1:0]\nPUPDR14[1:0]\nPUPDR13[1:0]\nPUPDR12[1:0]\nPUPDR11[1:0]\nPUPDR10[1:0]\nPUPDR9[1:0]\nPUPDR8[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPUPDR7[1:0]\nPUPDR6[1:0]\nPUPDR5[1:0]\nPUPDR4[1:0]\nPUPDR3[1:0]\nPUPDR2[1:0]\nPUPDR1[1:0]\nPUPDR0[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 286, "page_indices": { "start_index": 652876, "end_index": 654397 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 286 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.4 GPIO registers", 284 ], [ 3, "8.4.5 GPIO port input data register (GPIOx_IDR) (x = A..I/J/K)", 286 ], [ 3, "8.4.6 GPIO port output data register (GPIOx_ODR) (x = A..I/J/K)", 286 ] ], "page_content": "General-purpose I/Os (GPIO)\nRM0090\n286/1757\nRM0090 Rev 21\n \n8.4.5 \nGPIO port input data register (GPIOx_IDR) (x = A..I/J/K)\nAddress offset: 0x10\nReset value: 0x0000 XXXX (where X means undefined)\n \n \n8.4.6 \nGPIO port output data register (GPIOx_ODR) (x = A..I/J/K)\nAddress offset: 0x14\nReset value: 0x0000 0000\n \n \nBits 2y:2y+1 PUPDRy[1:0]: Port x configuration bits (y = 0..15)\nThese bits are written by software to configure the I/O pull-up or pull-down\n00: No pull-up, pull-down\n01: Pull-up\n10: Pull-down\n11: Reserved\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nIDR15\nIDR14\nIDR13\nIDR12\nIDR11\nIDR10\nIDR9\nIDR8\nIDR7\nIDR6\nIDR5\nIDR4\nIDR3\nIDR2\nIDR1\nIDR0\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 IDRy: Port input data (y = 0..15)\nThese bits are read-only and can be accessed in word mode only. They contain the input \nvalue of the corresponding I/O port.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nODR15\nODR14\nODR13\nODR12\nODR11\nODR10\nODR9\nODR8\nODR7\nODR6\nODR5\nODR4\nODR3\nODR2\nODR1\nODR0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 ODRy: Port output data (y = 0..15)\nThese bits can be read and written by software.\nNote: For atomic bit set/reset, the ODR bits can be individually set and reset by writing to the \nGPIOx_BSRR register (x = A..I/J/K).\n" }, { "page_number": 287, "page_indices": { "start_index": 654397, "end_index": 656537 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 287 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.4 GPIO registers", 284 ], [ 3, "8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..I/J/K)", 287 ], [ 3, "8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..I/J/K)", 287 ] ], "page_content": "RM0090 Rev 21\n287/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\n8.4.7 \nGPIO port bit set/reset register (GPIOx_BSRR) (x = A..I/J/K)\nAddress offset: 0x18\nReset value: 0x0000 0000\n \n \n8.4.8 \nGPIO port configuration lock register (GPIOx_LCKR)\n(x = A..I/J/K)\nThis register is used to lock the configuration of the port bits when a correct write sequence \nis applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the \nGPIO. During the write sequence, the value of LCKR[15:0] must not change. When the \nLOCK sequence has been applied on a port bit, the value of this port bit can no longer be \nmodified until the next MCU or peripheral reset.\nNote:\nA specific write sequence is used to write to the GPIOx_LCKR register. Only word access \n(32-bit long) is allowed during this write sequence.\nEach lock bit freezes a specific configuration register (control and alternate function \nregisters).\nAddress offset: 0x1C\nReset value: 0x0000 0000\nAccess: 32-bit word only, read/write register\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nBR15\nBR14\nBR13\nBR12\nBR11\nBR10\nBR9\nBR8\nBR7\nBR6\nBR5\nBR4\nBR3\nBR2\nBR1\nBR0\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nBS15\nBS14\nBS13\nBS12\nBS11\nBS10\nBS9\nBS8\nBS7\nBS6\nBS5\nBS4\nBS3\nBS2\nBS1\nBS0\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBits 31:16 BRy: Port x reset bit y (y = 0..15)\nThese bits are write-only and can be accessed in word, half-word or byte mode. A read to \nthese bits returns the value 0x0000.\n0: No action on the corresponding ODRx bit\n1: Resets the corresponding ODRx bit\nNote: If both BSx and BRx are set, BSx has priority.\nBits 15:0 BSy: Port x set bit y (y= 0..15)\nThese bits are write-only and can be accessed in word, half-word or byte mode. A read to \nthese bits returns the value 0x0000.\n0: No action on the corresponding ODRx bit\n1: Sets the corresponding ODRx bit\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nLCKK\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nLCK15\nLCK14\nLCK13\nLCK12\nLCK11\nLCK10\nLCK9\nLCK8\nLCK7\nLCK6\nLCK5\nLCK4\nLCK3\nLCK2\nLCK1\nLCK0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 288, "page_indices": { "start_index": 656537, "end_index": 658350 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 288 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.4 GPIO registers", 284 ], [ 3, "8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..I/J/K)", 288 ] ], "page_content": "General-purpose I/Os (GPIO)\nRM0090\n288/1757\nRM0090 Rev 21\n \n8.4.9 \nGPIO alternate function low register (GPIOx_AFRL) (x = A..I/J/K)\nAddress offset: 0x20\nReset value: 0x0000 0000\n \n \nBits 31:17 Reserved, must be kept at reset value.\nBit 16 LCKK[16]: Lock key\nThis bit can be read any time. It can only be modified using the lock key write sequence.\n0: Port configuration lock key not active\n1: Port configuration lock key active. The GPIOx_LCKR register is locked until an MCU reset \nor a peripheral reset occurs.\nLOCK key write sequence:\nWR LCKR[16] = ‘1’ + LCKR[15:0]\nWR LCKR[16] = ‘0’ + LCKR[15:0]\nWR LCKR[16] = ‘1’ + LCKR[15:0]\nRD LCKR\nRD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active)\nNote: During the LOCK key write sequence, the value of LCK[15:0] must not change.\nAny error in the lock sequence aborts the lock.\nAfter the first lock sequence on any bit of the port, any read access on the LCKK bit \nreturns ‘1’ until the next CPU reset.\nBits 15:0 LCKy: Port x lock bit y (y= 0..15)\nThese bits are read/write but can only be written when the LCKK bit is ‘0.\n0: Port configuration not locked\n1: Port configuration locked\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nAFRL7[3:0]\nAFRL6[3:0]\nAFRL5[3:0]\nAFRL4[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nAFRL3[3:0]\nAFRL2[3:0]\nAFRL1[3:0]\nAFRL0[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 AFRLy: Alternate function selection for port x bit y (y = 0..7)\nThese bits are written by software to configure alternate function I/Os\nAFRLy selection:\n0000: AF0\n0001: AF1\n0010: AF2\n0011: AF3\n0100: AF4\n0101: AF5\n0110: AF6\n0111: AF7\n1000: AF8\n1001: AF9\n1010: AF10\n1011: AF11\n1100: AF12\n1101: AF13\n1110: AF14\n1111: AF15\n" }, { "page_number": 289, "page_indices": { "start_index": 658350, "end_index": 659178 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 289 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.4 GPIO registers", 284 ], [ 3, "8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..I/J)", 289 ] ], "page_content": "RM0090 Rev 21\n289/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\n8.4.10 \nGPIO alternate function high register (GPIOx_AFRH)\n(x = A..I/J)\nAddress offset: 0x24\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nAFRH15[3:0]\nAFRH14[3:0]\nAFRH13[3:0]\nAFRH12[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nAFRH11[3:0]\nAFRH10[3:0]\nAFRH9[3:0]\nAFRH8[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 AFRHy: Alternate function selection for port x bit y (y = 8..15)\nThese bits are written by software to configure alternate function I/Os\nAFRHy selection:\n0000: AF0\n0001: AF1\n0010: AF2\n0011: AF3\n0100: AF4\n0101: AF5\n0110: AF6\n0111: AF7\n1000: AF8\n1001: AF9\n1010: AF10\n1011: AF11\n1100: AF12\n1101: AF13\n1110: AF14\n1111: AF15\n" }, { "page_number": 290, "page_indices": { "start_index": 659178, "end_index": 661841 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 290 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.4 GPIO registers", 284 ], [ 3, "8.4.11 GPIO register map", 290 ] ], "page_content": "General-purpose I/Os (GPIO)\nRM0090\n290/1757\nRM0090 Rev 21\n8.4.11 \nGPIO register map\nThe following table gives the GPIO register map and the reset values. \n \nTable 40. GPIO register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nGPIOA_\nMODER\nMODER15[1:0]\nMODER14[1:0]\nMODER13[1:0]\nMODER12[1:0]\nMODER11[1:0]\nMODER10[1:0]\nMODER9[1:0]\nMODER8[1:0]\nMODER7[1:0]\nMODER6[1:0]\nMODER5[1:0]\nMODER4[1:0]\nMODER3[1:0]\nMODER2[1:0]\nMODER1[1:0]\nMODER0[1:0]\nReset value\n1\n0\n1\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00\nGPIOB_\nMODER\nMODER15[1:0]\nMODER14[1:0]\nMODER13[1:0]\nMODER12[1:0]\nMODER11[1:0]\nMODER10[1:0]\nMODER9[1:0]\nMODER8[1:0]\nMODER7[1:0]\nMODER6[1:0]\nMODER5[1:0]\nMODER4[1:0]\nMODER3[1:0]\nMODER2[1:0]\nMODER1[1:0]\nMODER0[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0x00\nGPIOx_MODER \n(where x = \nC..I/J/K)\nMODER15[1:0]\nMODER14[1:0]\nMODER13[1:0]\nMODER12[1:0]\nMODER11[1:0]\nMODER10[1:0]\nMODER9[1:0]\nMODER8[1:0]\nMODER7[1:0]\nMODER6[1:0]\nMODER5[1:0]\nMODER4[1:0]\nMODER3[1:0]\nMODER2[1:0]\nMODER1[1:0]\nMODER0[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nGPIOx_\nOTYPER\n(where x = \nA..I/J/K)\nReserved\nOT15\nOT14\nOT13\nOT12\nOT11\nOT10\nOT9\nOT8\nOT7\nOT6\nOT5\nOT4\nOT3\nOT2\nOT1\nOT0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nGPIOx_\nOSPEEDR \n(where x = \nA..I/J/K except \nB)\nOSPEEDR15[1:0]\nOSPEEDR14[1:0]\nOSPEEDR13[1:0]\nOSPEEDR12[1:0]\nOSPEEDR11[1:0]\nOSPEEDR10[1:0]\nOSPEEDR9[1:0]\nOSPEEDR8[1:0]\nOSPEEDR7[1:0]\nOSPEEDR6[1:0]\nOSPEEDR5[1:0]\nOSPEEDR4[1:0]\nOSPEEDR3[1:0]\nOSPEEDR2[1:0]\nOSPEEDR1[1:0]\nOSPEEDR0[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nGPIOB_\nOSPEEDR\nOSPEEDR15[1:0]\nOSPEEDR14[1:0]\nOSPEEDR13[1:0]\nOSPEEDR12[1:0]\nOSPEEDR11[1:0]\nOSPEEDR10[1:0]\nOSPEEDR9[1:0]\nOSPEEDR8[1:0]\nOSPEEDR7[1:0]\nOSPEEDR6[1:0]\nOSPEEDR5[1:0]\nOSPEEDR4[1:0]\nOSPEEDR3[1:0]\nOSPEEDR2[1:0]\nOSPEEDR1[1:0]\nOSPEEDR0[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\n0x0C\nGPIOA_PUPDR\nPUPDR15[1:0]\nPUPDR14[1:0]\nPUPDR13[1:0]\nPUPDR12[1:0]\nPUPDR11[1:0]\nPUPDR10[1:0]\nPUPDR9[1:0]\nPUPDR8[1:0]\nPUPDR7[1:0]\nPUPDR6[1:0]\nPUPDR5[1:0]\nPUPDR4[1:0]\nPUPDR3[1:0]\nPUPDR2[1:0]\nPUPDR1[1:0]\nPUPDR0[1:0]\nReset value\n0\n1\n1\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nGPIOB_PUPDR\nPUPDR15[1:0]\nPUPDR14[1:0]\nPUPDR13[1:0]\nPUPDR12[1:0]\nPUPDR11[1:0]\nPUPDR10[1:0]\nPUPDR9[1:0]\nPUPDR8[1:0]\nPUPDR7[1:0]\nPUPDR6[1:0]\nPUPDR5[1:0]\nPUPDR4[1:0]\nPUPDR3[1:0]\nPUPDR2[1:0]\nPUPDR1[1:0]\nPUPDR0[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n" }, { "page_number": 291, "page_indices": { "start_index": 661841, "end_index": 663672 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 291 }, "toc_details": [ [ 1, "8 General-purpose I/Os (GPIO)", 270 ], [ 2, "8.4 GPIO registers", 284 ], [ 3, "8.4.11 GPIO register map", 290 ] ], "page_content": "RM0090 Rev 21\n291/1757\nRM0090\nGeneral-purpose I/Os (GPIO)\n291\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x0C\nGPIOx_PUPDR \n(where x = \nC..I/J/K)\nPUPDR15[1:0]\nPUPDR14[1:0]\nPUPDR13[1:0]\nPUPDR12[1:0]\nPUPDR11[1:0]\nPUPDR10[1:0]\nPUPDR9[1:0]\nPUPDR8[1:0]\nPUPDR7[1:0]\nPUPDR6[1:0]\nPUPDR5[1:0]\nPUPDR4[1:0]\nPUPDR3[1:0]\nPUPDR2[1:0]\nPUPDR1[1:0]\nPUPDR0[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nGPIOx_IDR \n(where x = \nA..I/J/K)\nReserved\nIDR15\nIDR14\nIDR13\nIDR12\nIDR11\nIDR10\nIDR9\nIDR8\nIDR7\nIDR6\nIDR5\nIDR4\nIDR3\nIDR2\nIDR1\nIDR0\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x14\nGPIOx_ODR \n(where x = \nA..I/J/K)\nReserved\nODR15\nODR14\nODR13\nODR12\nODR11\nODR10\nODR9\nODR8\nODR7\nODR6\nODR5\nODR4\nODR3\nODR2\nODR1\nODR0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x18\nGPIOx_BSRR \n(where x = \nA..I/J/K)\nBR15\nBR14\nBR13\nBR12\nBR11\nBR10\nBR9\nBR8\nBR7\nBR6\nBR5\nBR4\nBR3\nBR2\nBR1\nBR0\nBS15\nBS14\nBS13\nBS12\nBS11\nBS10\nBS9\nBS8\nBS7\nBS6\nBS5\nBS4\nBS3\nBS2\nBS1\nBS0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nGPIOx_LCKR \n(where x = \nA..I/J/K)\nReserved\nLCKK\nLCK15\nLCK14\nLCK13\nLCK12\nLCK11\nLCK10\nLCK9\nLCK8\nLCK7\nLCK6\nLCK5\nLCK4\nLCK3\nLCK2\nLCK1\nLCK0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nGPIOx_AFRL \n(where x = \nA..I/J/K)\nAFRL7[3:0]\nAFRL6[3:0]\nAFRL5[3:0]\nAFRL4[3:0]\nAFRL3[3:0]\nAFRL2[3:0]\nAFRL1[3:0]\nAFRL0[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x24\nGPIOx_AFRH \n(where x = \nA..I/J)\nAFRH15[3:0]\nAFRH14[3:0]\nAFRH13[3:0]\nAFRH12[3:0]\nAFRH11[3:0]\nAFRH10[3:0]\nAFRH9[3:0]\nAFRH8[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 40. GPIO register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 292, "page_indices": { "start_index": 663672, "end_index": 665684 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 292 }, "toc_details": [ [ 1, "9 System configuration controller (SYSCFG)", 292 ], [ 2, "9.1 I/O compensation cell", 292 ], [ 2, "9.2 SYSCFG registers for STM32F405xx/07xx and STM32F415xx/17xx", 292 ], [ 3, "9.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP)", 292 ] ], "page_content": "System configuration controller (SYSCFG)\nRM0090\n292/1757\nRM0090 Rev 21\n9 \nSystem configuration controller (SYSCFG)\nThe system configuration controller is mainly used to remap the memory accessible in the \ncode area, select the Ethernet PHY interface and manage the external interrupt line \nconnection to the GPIOs.\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n9.1 \nI/O compensation cell\nBy default the I/O compensation cell is not used. However when the I/O output buffer speed \nis configured in 50 MHz or 100 MHz mode, it is recommended to use the compensation cell \nfor slew rate control on I/O tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power \nsupply.\nWhen the compensation cell is enabled, a READY flag is set to indicate that the \ncompensation cell is ready and can be used. The I/O compensation cell can be used only \nwhen the supply voltage ranges from 2.4 to 3.6 V.\n9.2 \nSYSCFG registers for STM32F405xx/07xx and \nSTM32F415xx/17xx\n9.2.1 \nSYSCFG memory remap register (SYSCFG_MEMRMP)\nThis register is used for specific configurations on memory remap:\n•\nTwo bits are used to configure the type of memory accessible at address 0x0000 0000. \nThese bits are used to select the physical remap by software and so, bypass the BOOT \npins.\n•\nAfter reset these bits take the value selected by the BOOT pins. When booting from \nmain Flash memory with BOOT pins set to 10 [(BOOT1,BOOT0) = (1,0)] this register \ntakes the value 0x00.\nWhen the FSMC is remapped at address 0x0000 0000, only the first two regions of Bank 1 \nmemory controller (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) can be remapped. In remap \nmode, the CPU can access the external memory via ICode bus instead of System bus \nwhich boosts up the performance. \nAddress offset: 0x00\nReset value: 0x0000 000X (X is the memory mode selected by the BOOT pins)\n )\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMEM_MODE\nrw\nrw\n" }, { "page_number": 293, "page_indices": { "start_index": 665684, "end_index": 667034 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 293 }, "toc_details": [ [ 1, "9 System configuration controller (SYSCFG)", 292 ], [ 2, "9.2 SYSCFG registers for STM32F405xx/07xx and STM32F415xx/17xx", 292 ], [ 3, "9.2.2 SYSCFG peripheral mode configuration register (SYSCFG_PMC)", 293 ] ], "page_content": "RM0090 Rev 21\n293/1757\nRM0090\nSystem configuration controller (SYSCFG)\n304\n \n9.2.2 \nSYSCFG peripheral mode configuration register (SYSCFG_PMC)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n \nBits 31:2 Reserved, must be kept at reset value.\nBits 1:0 MEM_MODE: Memory mapping selection\nSet and cleared by software. This bit controls the memory internal mapping at \naddress 0x0000 0000. After reset these bits take the value selected by the Boot \npins (except for FSMC).\n00: Main Flash memory mapped at 0x0000 0000\n01: System Flash memory mapped at 0x0000 0000\n10: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000\n11: Embedded SRAM (SRAM1) mapped at 0x0000 0000\nNote: Refer to Section 2.3: Memory map for details about the memory mapping at \naddress 0x0000 0000.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nMII_RMII\n_SEL\nReserved\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBits 31:24 Reserved, must be kept at reset value.\nBit 23 MII_RMII_SEL: Ethernet PHY interface selection\nSet and Cleared by software.These bits control the PHY interface for the \nEthernet MAC.\n0: MII interface is selected\n1: RMII PHY interface is selected\nNote: This configuration must be done while the MAC is under reset and before \nenabling the MAC clocks.\nBits 22:0 Reserved, must be kept at reset value.\n" }, { "page_number": 294, "page_indices": { "start_index": 667034, "end_index": 668122 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 294 }, "toc_details": [ [ 1, "9 System configuration controller (SYSCFG)", 292 ], [ 2, "9.2 SYSCFG registers for STM32F405xx/07xx and STM32F415xx/17xx", 292 ], [ 3, "9.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)", 294 ], [ 3, "9.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)", 294 ] ], "page_content": "System configuration controller (SYSCFG)\nRM0090\n294/1757\nRM0090 Rev 21\n9.2.3 \nSYSCFG external interrupt configuration register 1\n(SYSCFG_EXTICR1)\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n \n9.2.4 \nSYSCFG external interrupt configuration register 2\n(SYSCFG_EXTICR2)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXTI3[3:0]\nEXTI2[3:0]\nEXTI1[3:0]\nEXTI0[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3)\nThese bits are written by software to select the source input for the EXTIx \nexternal interrupt. \n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n0111: PH[x] pin\n1000: PI[x] pin\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXTI7[3:0]\nEXTI6[3:0]\nEXTI5[3:0]\nEXTI4[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 295, "page_indices": { "start_index": 668122, "end_index": 669256 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 295 }, "toc_details": [ [ 1, "9 System configuration controller (SYSCFG)", 292 ], [ 2, "9.2 SYSCFG registers for STM32F405xx/07xx and STM32F415xx/17xx", 292 ], [ 3, "9.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)", 295 ] ], "page_content": "RM0090 Rev 21\n295/1757\nRM0090\nSystem configuration controller (SYSCFG)\n304\n \n9.2.5 \nSYSCFG external interrupt configuration register 3\n(SYSCFG_EXTICR3)\nAddress offset: 0x10\nReset value: 0x0000 0000\n \n \nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7)\nThese bits are written by software to select the source input for the EXTIx \nexternal interrupt.\n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n0111: PH[x] pin\n1000: PI[x] pin\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXTI11[3:0]\nEXTI10[3:0]\nEXTI9[3:0]\nEXTI8[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x = 8 to 11)\nThese bits are written by software to select the source input for the EXTIx external \ninterrupt.\n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n0111: PH[x] pin\n1000: PI[x] pin\n" }, { "page_number": 296, "page_indices": { "start_index": 669256, "end_index": 670609 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 296 }, "toc_details": [ [ 1, "9 System configuration controller (SYSCFG)", 292 ], [ 2, "9.2 SYSCFG registers for STM32F405xx/07xx and STM32F415xx/17xx", 292 ], [ 3, "9.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)", 296 ], [ 3, "9.2.7 Compensation cell control register (SYSCFG_CMPCR)", 296 ] ], "page_content": "System configuration controller (SYSCFG)\nRM0090\n296/1757\nRM0090 Rev 21\n9.2.6 \nSYSCFG external interrupt configuration register 4\n(SYSCFG_EXTICR4)\nAddress offset: 0x14\nReset value: 0x0000 0000\n \n9.2.7 \nCompensation cell control register (SYSCFG_CMPCR)\nAddress offset: 0x20\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXTI15[3:0]\nEXTI14[3:0]\nEXTI13[3:0]\nEXTI12[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15)\nThese bits are written by software to select the source input for the EXTIx external \ninterrupt.\n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n0111: PH[x] pin\nNote: PI[15:12] are not used.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nREADY\nReserved\nCMP_PD\nr\nrw\nBits 31:9 Reserved, must be kept at reset value.\nBit 8 READY: Compensation cell ready flag\n0: I/O compensation cell not ready\n1: O compensation cell ready\nBits 7:2 Reserved, must be kept at reset value.\nBit 0 CMP_PD: Compensation cell power-down\n0: I/O compensation cell power-down mode\n1: I/O compensation cell enabled\n" }, { "page_number": 297, "page_indices": { "start_index": 670609, "end_index": 672435 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 297 }, "toc_details": [ [ 1, "9 System configuration controller (SYSCFG)", 292 ], [ 2, "9.2 SYSCFG registers for STM32F405xx/07xx and STM32F415xx/17xx", 292 ], [ 3, "9.2.8 SYSCFG register maps for STM32F405xx/07xx and STM32F415xx/17xx", 297 ], [ 2, "9.3 SYSCFG registers for STM32F42xxx and STM32F43xxx", 297 ], [ 3, "9.3.1 SYSCFG memory remap register (SYSCFG_MEMRMP)", 297 ] ], "page_content": "RM0090 Rev 21\n297/1757\nRM0090\nSystem configuration controller (SYSCFG)\n304\n9.2.8 \nSYSCFG register maps for \nSTM32F405xx/07xx and STM32F415xx/17xx\nThe following table gives the SYSCFG register map and the reset values.\n \nRefer to Section 2.3: Memory map for the register boundary addresses.\n9.3 \nSYSCFG registers for STM32F42xxx and STM32F43xxx\n9.3.1 \nSYSCFG memory remap register (SYSCFG_MEMRMP)\nThis register is used for specific configurations on memory remap:\n•\nThree bits are used to configure the type of memory accessible at address \n0x0000 0000. These bits are used to select the physical remap by software and so, \nbypass the BOOT pins.\n•\nAfter reset these bits take the value selected by the BOOT pins. When booting from \nmain Flash memory with BOOT pins set to 10 [(BOOT1,BOOT0) = (1,0)] this register \ntakes the value 0x00.\n•\nOther bits are used to swap FMC SDRAM Bank 1/2 with FMC Bank 3/4 and configure \nthe Flash Bank 1/2 mapping\nTable 41. SYSCFG register map and reset values\n(STM32F405xx/07xx and STM32F415xx/17xx)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nSYSCFG_\nMEMRMP\nReserved\nMEM_MODE\nReset value\nx\nx\n0x04\nSYSCFG_PMC\nReserved\nMII_RMII_SEL\nReserved\nReserved\nReset value\n0\n0x08\nSYSCFG_EXTICR1\nReserved\nEXTI3[3:0]\nEXTI2[3:0]\nEXTI1[3:0]\nEXTI0[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nSYSCFG_EXTICR2\nReserved\nEXTI7[3:0]\nEXTI6[3:0]\nEXTI5[3:0]\nEXTI4[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nSYSCFG_EXTICR3\nReserved\nEXTI11[3:0]\nEXTI10[3:0]\nEXTI9[3:0]\nEXTI8[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nSYSCFG_EXTICR4\nReserved\nEXTI15[3:0]\nEXTI14[3:0]\nEXTI13[3:0]\nEXTI12[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nSYSCFG_CMPCR\nReserved\nREADY\nReserved\nCMP_PD\nReset value\n0\n0\n" }, { "page_number": 298, "page_indices": { "start_index": 672435, "end_index": 674032 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 298 }, "toc_details": [ [ 1, "9 System configuration controller (SYSCFG)", 292 ], [ 2, "9.3 SYSCFG registers for STM32F42xxx and STM32F43xxx", 297 ], [ 3, "9.3.1 SYSCFG memory remap register (SYSCFG_MEMRMP)", 297 ] ], "page_content": "System configuration controller (SYSCFG)\nRM0090\n298/1757\nRM0090 Rev 21\nThere are two possible FMC remap at address 0x0000 0000:\n•\nFMC Bank 1 (NOR/PSRAM 1 and 2) remap:\nOnly the first two regions of Bank 1 memory controller (Bank1 NOR/PSRAM 1 and \nNOR/PSRAM 2) can be remapped.\n•\nFMC SDRAM Bank 1 remap.\nIn remap mode at address 0x0000 0000, the CPU can access the external memory via \nICode bus instead of System bus which boosts up the performance.\nAddress offset: 0x00\nReset value: 0x0000 000X (X is the memory mode selected by the BOOT pins)\nNote:\nBooting from NOR Flash memory or SDRAM is not allowed. The regions can only be \nmapped at 0x0000 0000 through software remap.\n )\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSWP_FMC\nRes.\nFB_\nMODE\nReserved\nMEM_MODE[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:10 SWP_FMC: FMC memory mapping swap\nSet and cleared by software. These bits are used to swap the FMC SDRAM \nBank 1/2 and FMC Bank 3/4 (SDRAM Bank 1/2 and NAND Bank 2/PCCARD \nBank) in order to enable the code execution from SDRAM Banks without a \nphysical remapping at 0x0000 0000 address.\n00: No FMC memory mapping swap\n01: SDRAM banks and NAND Bank 2/PCCARD mapping are swapped. SDRAM \nBank 1 and 2 are mapped at NAND Bank 2 (0x8000 0000) and PCCARD Bank \n(0x9000 0000) address, respectively. NAND Bank 2 and PCCARD Bank are \nmapped at 0xC000 0000 and 0xD000 0000, respectively. \n10: Reserved\n11: Reserved\nBit 9 Reserved, must be kept at reset value.\n" }, { "page_number": 299, "page_indices": { "start_index": 674032, "end_index": 675819 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 299 }, "toc_details": [ [ 1, "9 System configuration controller (SYSCFG)", 292 ], [ 2, "9.3 SYSCFG registers for STM32F42xxx and STM32F43xxx", 297 ], [ 3, "9.3.2 SYSCFG peripheral mode configuration register (SYSCFG_PMC)", 299 ] ], "page_content": "RM0090 Rev 21\n299/1757\nRM0090\nSystem configuration controller (SYSCFG)\n304\n9.3.2 \nSYSCFG peripheral mode configuration register (SYSCFG_PMC)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n \nBit 8 FB_MODE: Flash Bank mode selection\nSet and cleared by software. This bit controls the Flash Bank 1/2 mapping.\n0: Flash Bank 1 is mapped at 0x0800 0000 (and aliased at 0x0000 0000) and \nFlash Bank 2 is mapped at 0x0810 0000 (and aliased at 0x0010 0000)\n1: Flash Bank 2 is mapped at 0x0800 0000 (and aliased at 0x0000 0000) and \nFlash Bank 1 is mapped at 0x0810 0000 (and aliased at 0x0010 0000)\nBits 7:3 Reserved, must be kept at reset value.\nBits 2:0 MEM_MODE: Memory mapping selection\nSet and cleared by software. This bit controls the memory internal mapping at \naddress 0x0000 0000. After reset these bits take the value selected by the Boot \npins (except for FMC).\n000: Main Flash memory mapped at 0x0000 0000\n001: System Flash memory mapped at 0x0000 0000\n010: FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000\n011: Embedded SRAM (SRAM1) mapped at 0x0000 0000\n100: FMC/SDRAM Bank 1 mapped at 0x0000 0000\nOther configurations are reserved\nNote: Refer to Section 2.3: Memory map for details about the memory mapping at \naddress 0x0000 0000.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nMII_RMII\n_SEL\nReserved\nADCxDC2\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBits 31:24 Reserved, must be kept at reset value.\nBit 23 MII_RMII_SEL: Ethernet PHY interface selection\nSet and Cleared by software.These bits control the PHY interface for the \nEthernet MAC.\n0: MII interface is selected\n1: RMII PHY interface is selected\nNote: This configuration must be done while the MAC is under reset and before \nenabling the MAC clocks.\n" }, { "page_number": 300, "page_indices": { "start_index": 675819, "end_index": 677107 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 300 }, "toc_details": [ [ 1, "9 System configuration controller (SYSCFG)", 292 ], [ 2, "9.3 SYSCFG registers for STM32F42xxx and STM32F43xxx", 297 ], [ 3, "9.3.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)", 300 ] ], "page_content": "System configuration controller (SYSCFG)\nRM0090\n300/1757\nRM0090 Rev 21\n9.3.3 \nSYSCFG external interrupt configuration register 1\n(SYSCFG_EXTICR1)\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n \nBits 22:19 Reserved, must be kept at reset value.\nBits 18:16 ADCxDC2:\n0: No effect. \n1: Refer to AN4073 on how to use this bit. \nNote: These bits can be set only if the following conditions are met:\n- ADC clock higher or equal to 30 MHz.\n- Only one ADCxDC2 bit must be selected if ADC conversions do not start \nat the same time and the sampling times differ. \n- These bits must not be set when the ADCDC1 bit is set in PWR_CR \nregister.\nBits 15:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXTI3[3:0]\nEXTI2[3:0]\nEXTI1[3:0]\nEXTI0[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3)\nThese bits are written by software to select the source input for the EXTIx \nexternal interrupt. \n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n0111: PH[x] pin\n1000: PI[x] pin\n1001: PJ[x] pin\n1010: PK[x] pin\n" }, { "page_number": 301, "page_indices": { "start_index": 677107, "end_index": 678232 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 301 }, "toc_details": [ [ 1, "9 System configuration controller (SYSCFG)", 292 ], [ 2, "9.3 SYSCFG registers for STM32F42xxx and STM32F43xxx", 297 ], [ 3, "9.3.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)", 301 ], [ 3, "9.3.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)", 301 ] ], "page_content": "RM0090 Rev 21\n301/1757\nRM0090\nSystem configuration controller (SYSCFG)\n304\n9.3.4 \nSYSCFG external interrupt configuration register 2\n(SYSCFG_EXTICR2)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n \n \n9.3.5 \nSYSCFG external interrupt configuration register 3\n(SYSCFG_EXTICR3)\nAddress offset: 0x10\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXTI7[3:0]\nEXTI6[3:0]\nEXTI5[3:0]\nEXTI4[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7)\nThese bits are written by software to select the source input for the EXTIx \nexternal interrupt.\n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n0111: PH[x] pin\n1000: PI[x] pin\n1001: PJ[x] pin\n1010: PK[x] pin\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXTI11[3:0]\nEXTI10[3:0]\nEXTI9[3:0]\nEXTI8[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 302, "page_indices": { "start_index": 678232, "end_index": 679447 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 302 }, "toc_details": [ [ 1, "9 System configuration controller (SYSCFG)", 292 ], [ 2, "9.3 SYSCFG registers for STM32F42xxx and STM32F43xxx", 297 ], [ 3, "9.3.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)", 302 ] ], "page_content": "System configuration controller (SYSCFG)\nRM0090\n302/1757\nRM0090 Rev 21\n \n9.3.6 \nSYSCFG external interrupt configuration register 4\n(SYSCFG_EXTICR4)\nAddress offset: 0x14\nReset value: 0x0000 0000\n \nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x = 8 to 11)\nThese bits are written by software to select the source input for the EXTIx \nexternal interrupt.\n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n0111: PH[x] pin\n1000: PI[x] pin\n1001: PJ[x] pin\nNote: PK[11:8] are not used.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXTI15[3:0]\nEXTI14[3:0]\nEXTI13[3:0]\nEXTI12[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15)\nThese bits are written by software to select the source input for the EXTIx external \ninterrupt.\n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n0111: PH[x] pin\n1000: PI[x] pin\n1001: PJ[x] pin\nNote: PK[15:12] are not used.\n" }, { "page_number": 303, "page_indices": { "start_index": 679447, "end_index": 680118 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 303 }, "toc_details": [ [ 1, "9 System configuration controller (SYSCFG)", 292 ], [ 2, "9.3 SYSCFG registers for STM32F42xxx and STM32F43xxx", 297 ], [ 3, "9.3.7 Compensation cell control register (SYSCFG_CMPCR)", 303 ] ], "page_content": "RM0090 Rev 21\n303/1757\nRM0090\nSystem configuration controller (SYSCFG)\n304\n9.3.7 \nCompensation cell control register (SYSCFG_CMPCR)\nAddress offset: 0x20\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nREADY\nReserved\nCMP_PD\nr\nrw\nBits 31:9 Reserved, must be kept at reset value.\nBit 8 READY: Compensation cell ready flag\n0: I/O compensation cell not ready\n1: O compensation cell ready\nBits 7:2 Reserved, must be kept at reset value.\nBit 0 CMP_PD: Compensation cell power-down\n0: I/O compensation cell power-down mode\n1: I/O compensation cell enabled\n" }, { "page_number": 304, "page_indices": { "start_index": 680118, "end_index": 681338 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 304 }, "toc_details": [ [ 1, "9 System configuration controller (SYSCFG)", 292 ], [ 2, "9.3 SYSCFG registers for STM32F42xxx and STM32F43xxx", 297 ], [ 3, "9.3.8 SYSCFG register maps for STM32F42xxx and STM32F43xxx", 304 ] ], "page_content": "System configuration controller (SYSCFG)\nRM0090\n304/1757\nRM0090 Rev 21\n9.3.8 \nSYSCFG register maps for STM32F42xxx and STM32F43xxx\nThe following table gives the SYSCFG register map and the reset values.\n \nRefer to Section 2.3: Memory map for the register boundary addresses.\nTable 42. SYSCFG register map and reset values (STM32F42xxx and STM32F43xxx)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nSYSCFG_\nMEMRMP\nReserved\nSWP_FMC\nReserved\nFB_MODE\nReserved\nMEM_\nMODE\nReset value\n0\n0\n0\nx\nx\nx\n0x04\nSYSCFG_PMC\nReserved\nMII_RMII_SEL\nReserved\nADC3DC2\nADC2DC2\nADC1DC2\nReserved\nReset value\n0\n0\n0\n0\n0x08\nSYSCFG_EXTICR1\nReserved\nEXTI3[3:0]\nEXTI2[3:0]\nEXTI1[3:0]\nEXTI0[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nSYSCFG_EXTICR2\nReserved\nEXTI7[3:0]\nEXTI6[3:0]\nEXTI5[3:0]\nEXTI4[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nSYSCFG_EXTICR3\nReserved\nEXTI11[3:0]\nEXTI10[3:0]\nEXTI9[3:0]\nEXTI8[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nSYSCFG_EXTICR4\nReserved\nEXTI15[3:0]\nEXTI14[3:0]\nEXTI13[3:0]\nEXTI12[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nSYSCFG_CMPCR\nReserved\nREADY\nReserved\nCMP_PD\nReset value\n0\n0\n" }, { "page_number": 305, "page_indices": { "start_index": 681338, "end_index": 683040 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 305 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.1 DMA introduction", 305 ], [ 2, "10.2 DMA main features", 305 ] ], "page_content": "RM0090 Rev 21\n305/1757\nRM0090\nDMA controller (DMA)\n341\n10 \nDMA controller (DMA)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n10.1 \nDMA introduction\nDirect memory access (DMA) is used in order to provide high-speed data transfer between \nperipherals and memory and between memory and memory. Data can be quickly moved by \nDMA without any CPU action. This keeps CPU resources free for other operations.\nThe DMA controller combines a powerful dual AHB master bus architecture with \nindependent FIFO to optimize the bandwidth of the system, based on a complex bus matrix \narchitecture.\nThe two DMA controllers have 16 streams in total (8 for each controller), each dedicated to \nmanaging memory access requests from one or more peripherals. Each stream can have \nup to 8 channels (requests) in total. And each has an arbiter for handling the priority \nbetween DMA requests.\n10.2 \nDMA main features\nThe main DMA features are:\n•\nDual AHB master bus architecture, one dedicated to memory accesses and one \ndedicated to peripheral accesses\n•\nAHB slave programming interface supporting only 32-bit accesses\n•\n8 streams for each DMA controller, up to 8 channels (requests) per stream\n•\nFour-word depth 32 first-in, first-out memory buffers (FIFOs) per stream, that can be \nused in FIFO mode or direct mode:\n–\nFIFO mode: with threshold level software selectable between 1/4, 1/2 or 3/4 of the \nFIFO size\n–\nDirect mode \nEach DMA request immediately initiates a transfer from/to the memory. When it is \nconfigured in direct mode (FIFO disabled), to transfer data in memory-to-\nperipheral mode, the DMA preloads only one data from the memory to the internal \n" }, { "page_number": 306, "page_indices": { "start_index": 683040, "end_index": 685195 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 306 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.2 DMA main features", 305 ] ], "page_content": "DMA controller (DMA)\nRM0090\n306/1757\nRM0090 Rev 21\nFIFO to ensure an immediate data transfer as soon as a DMA request is triggered \nby a peripheral.\n•\nEach stream can be configured by hardware to be:\n–\na regular channel that supports peripheral-to-memory, memory-to-peripheral and \nmemory-to-memory transfers\n–\na double buffer channel that also supports double buffering on the memory side\n•\nEach of the 8 streams are connected to dedicated hardware DMA channels (requests)\n•\nPriorities between DMA stream requests are software-programmable (4 levels \nconsisting of very high, high, medium, low) or hardware in case of equality (request 0 \nhas priority over request 1, etc.)\n•\nEach stream also supports software trigger for memory-to-memory transfers (only \navailable for the DMA2 controller)\n•\nEach stream request can be selected among up to 8 possible channel requests. This \nselection is software-configurable and allows several peripherals to initiate DMA \nrequests\n•\nThe number of data items to be transferred can be managed either by the DMA \ncontroller or by the peripheral:\n–\nDMA flow controller: the number of data items to be transferred is software-\nprogrammable from 1 to 65535\n–\nPeripheral flow controller: the number of data items to be transferred is unknown \nand controlled by the source or the destination peripheral that signals the end of \nthe transfer by hardware\n•\nIndependent source and destination transfer width (byte, half-word, word): when the \ndata widths of the source and destination are not equal, the DMA automatically \npacks/unpacks the necessary transfers to optimize the bandwidth. This feature is only \navailable in FIFO mode\n•\nIncrementing or non-incrementing addressing for source and destination\n•\nSupports incremental burst transfers of 4, 8 or 16 beats. The size of the burst is \nsoftware-configurable, usually equal to half the FIFO size of the peripheral\n•\nEach stream supports circular buffer management\n•\n5 event flags (DMA Half Transfer, DMA Transfer complete, DMA Transfer Error, DMA \nFIFO Error, Direct Mode Error) logically ORed together in a single interrupt request for \neach stream\n" }, { "page_number": 307, "page_indices": { "start_index": 685195, "end_index": 686600 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 307 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.1 General description", 307 ] ], "page_content": "RM0090 Rev 21\n307/1757\nRM0090\nDMA controller (DMA)\n341\n10.3 \nDMA functional description\n10.3.1 \nGeneral description\nFigure 32 shows the block diagram of a DMA.\nFigure 32. DMA block diagram\nThe DMA controller performs direct memory transfer: as an AHB master, it can take the \ncontrol of the AHB bus matrix to initiate AHB transactions.\nIt can carry out the following transactions:\n•\nperipheral-to-memory\n•\nmemory-to-peripheral\n•\nmemory-to-memory\nThe DMA controller provides two AHB master ports: the AHB memory port, intended to be \nconnected to memories and the AHB peripheral port, intended to be connected to \nperipherals. However, to allow memory-to-memory transfers, the AHB peripheral port must \nalso have access to the memories.\nThe AHB slave port is used to program the DMA controller (it supports only 32-bit \naccesses).\nAHB master\nMemory port\nFIFO \nAHB master\nPeripheral port\nSTREAM 0\nFIFO \nSTREAM 1\nSTREAM 0\nSTREAM 1\nFIFO \nSTREAM 2\nSTREAM 2\nFIFO \nSTREAM 7\nSTREAM 7\nREQ_STREAM0\nREQ_STR0_CH0\nREQ_STR0_CH1\nDMA controller\nFIFO \nSTREAM 3\nSTREAM 3\nFIFO \nSTREAM 4\nSTREAM 4\nFIFO \nSTREAM 5\nSTREAM 5\nFIFO \nSTREAM 6\nSTREAM 6\nArbiter\nREQ_STREAM1\nREQ_STREAM2\nREQ_STREAM3\nREQ_STREAM4\nREQ_STREAM5\nREQ_STREAM6\nREQ_STREAM7\nREQ_STR0_CH7\nREQ_STR1_CH0\nREQ_STR1_CH1\nREQ_STR1_CH7\nREQ_STR7_CH0\nREQ_STR7_CH1\nREQ_STR7_CH7\nAHB slave\nprogramming\ninterface\nProgramming port\nChannel\nselection\nai15945\n" }, { "page_number": 308, "page_indices": { "start_index": 686600, "end_index": 687503 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 308 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.1 General description", 307 ] ], "page_content": "DMA controller (DMA)\nRM0090\n308/1757\nRM0090 Rev 21\nSee Figure 33 and Figure 34 for the implementation of the system of two DMA controllers.\nFigure 33. System implementation of the two DMA controllers \n(STM32F405xx/07xx and STM32F415xx/17xx)\n1.\nThe DMA1 controller AHB peripheral port is not connected to the bus matrix like DMA2 controller. As a result, only DMA2 \nstreams are able to perform memory-to-memory transfers.\nMS19927V2\nDMA controller 1\nAHB periph\nArbiter\nAHB memory\nFIFO\nDMA controller 2\nAHB memory\nBus matrix \n(AHB \nArbiter\nAHB periph\nMAPPING\nFIFO\nExternal memory\nFlash\nmemory\n112 KB SRAM\nAHB2 peripherals\nmultilayer)\nAHB-APB \nbridge2\n(dual AHB)\nAPB2\nAPB2\nAHB-APB \nbridge1\n(dual AHB)\nAPB1\nAPB1\nperipherals\nAHB slave\nAHB slave\nport\nport\nport\nport\ncontroller (FSMC)\nDMA request\nperipherals\n16 KB SRAM\nAHB1 peripherals\nTo AHB2\nperipherals\nTo AHB2\nperipherals\nDCODE\nICODE\n" }, { "page_number": 309, "page_indices": { "start_index": 687503, "end_index": 688989 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 309 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.2 DMA transactions", 309 ] ], "page_content": "RM0090 Rev 21\n309/1757\nRM0090\nDMA controller (DMA)\n341\nFigure 34. System implementation of the two DMA controllers\n(STM32F42xxx and STM32F43xxx) \n1.\nThe DMA1 controller AHB peripheral port is not connected to the bus matrix like in the case of the DMA2 \ncontroller, thus only DMA2 streams are able to perform memory-to-memory transfers.\n10.3.2 \nDMA transactions\nA DMA transaction consists of a sequence of a given number of data transfers. The number \nof data items to be transferred and their width (8-bit, 16-bit or 32-bit) are software-\nprogrammable.\nEach DMA transfer consists of three operations:\n•\nA loading from the peripheral data register or a location in memory, addressed through \nthe DMA_SxPAR or DMA_SxM0AR register\n•\nA storage of the data loaded to the peripheral data register or a location in memory \naddressed through the DMA_SxPAR or DMA_SxM0AR register\n•\nA post-decrement of the DMA_SxNDTR register, which contains the number of \ntransactions that still have to be performed\nMS30438V1\nDMA controller 1\nAHB periph\nArbiter\nAHB memory\nFIFO\nDMA controller 2\nAHB memory\nBus Matrix\n(AHB multilayer)\n \nArbiter\nAHB periph\nMAPPING\nFIFO\nExternal memory\nFlash\nmemory\n112 KB SRAM\nAHB2 peripherals\nAHB-APB \nbridge2\n(dual AHB)\nAPB2\nAPB2\nAHB-APB \nbridge1\n(dual AHB)\nAPB1\nAPB1\nperipherals\nAHB slave\nAHB slave\nport\nport\nport\nport\ncontroller (FMC)\nDMA request\nperipherals\n16 KB SRAM\nAHB1 peripherals\nTo AHB2\nperipherals\nTo AHB2\nperipherals\nDCODE\nICODE\n64 KB SRAM\n" }, { "page_number": 310, "page_indices": { "start_index": 688989, "end_index": 690916 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 310 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.3 Channel selection", 310 ] ], "page_content": "DMA controller (DMA)\nRM0090\n310/1757\nRM0090 Rev 21\nAfter an event, the peripheral sends a request signal to the DMA controller. The DMA \ncontroller serves the request depending on the channel priorities. As soon as the DMA \ncontroller accesses the peripheral, an Acknowledge signal is sent to the peripheral by the \nDMA controller. The peripheral releases its request as soon as it gets the Acknowledge \nsignal from the DMA controller. Once the request has been deasserted by the peripheral, \nthe DMA controller releases the Acknowledge signal. If there are more requests, the \nperipheral can initiate the next transaction.\n10.3.3 \nChannel selection\nEach stream is associated with a DMA request that can be selected out of 8 possible \nchannel requests. The selection is controlled by the CHSEL[2:0] bits in the DMA_SxCR \nregister.\nFigure 35. Channel selection\nThe 8 requests from the peripherals (TIM, ADC, SPI, I2C, etc.) are independently connected \nto each channel and their connection depends on the product implementation.\nSee the following table(s) for examples of DMA request mappings.\n \nREQ_STREAMx\nREQ_STRx_CH7\nCHSEL[2:0]\n31\n27\n25\n0\nDMA_SxCR\nai15947b\nREQ_STRx_CH6\nREQ_STRx_CH5\nREQ_STRx_CH4\nREQ_STRx_CH3\nREQ_STRx_CH2\nREQ_STRx_CH1\nREQ_STRx_CH0\nTable 43. DMA1 request mapping\nPeripheral \nrequests\nStream 0\nStream 1\nStream 2\nStream 3 \nStream 4\nStream 5\nStream 6\nStream 7\nChannel 0\nSPI3_RX\n-\nSPI3_RX\nSPI2_RX\nSPI2_TX\nSPI3_TX\n-\nSPI3_TX\nChannel 1\nI2C1_RX\n-\nTIM7_UP\n-\nTIM7_UP\nI2C1_RX\nI2C1_TX\nI2C1_TX\nChannel 2\nTIM4_CH1\n-\nI2S3_EXT_\nRX\nTIM4_CH2\nI2S2_EXT_\nTX\nI2S3_EXT_\nTX\nTIM4_UP\nTIM4_CH3\nChannel 3\nI2S3_EXT_\nRX\nTIM2_UP\nTIM2_CH3\nI2C3_RX\nI2S2_EXT_\nRX\nI2C3_TX\nTIM2_CH1\nTIM2_CH2\nTIM2_CH4\nTIM2_UP\nTIM2_CH4\nChannel 4\nUART5_RX\nUSART3_RX\nUART4_RX\nUSART3_TX\nUART4_TX\nUSART2_RX\nUSART2_TX\nUART5_TX\nChannel 5\nUART8_TX(1)\nUART7_TX(1)\nTIM3_CH4\nTIM3_UP\nUART7_RX(1)\nTIM3_CH1\nTIM3_TRIG\nTIM3_CH2\nUART8_RX(1)\nTIM3_CH3\n" }, { "page_number": 311, "page_indices": { "start_index": 690916, "end_index": 692847 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 311 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.4 Arbiter", 311 ] ], "page_content": "RM0090 Rev 21\n311/1757\nRM0090\nDMA controller (DMA)\n341\n \n \n \n10.3.4 \nArbiter\nAn arbiter manages the 8 DMA stream requests based on their priority for each of the two \nAHB master ports (memory and peripheral ports) and launches the peripheral/memory \naccess sequences.\nPriorities are managed in two stages:\n•\nSoftware: each stream priority can be configured in the DMA_SxCR register. There are \nfour levels:\n–\nVery high priority\n–\nHigh priority\n–\nMedium priority\n–\nLow priority\n•\nHardware: If two requests have the same software priority level, the stream with the \nlower number takes priority over the stream with the higher number. For example, \nStream 2 takes priority over Stream 4.\nChannel 6\nTIM5_CH3\nTIM5_UP\nTIM5_CH4\nTIM5_TRIG\nTIM5_CH1\nTIM5_CH4\nTIM5_TRIG\nTIM5_CH2\n-\nTIM5_UP\n-\nChannel 7\n-\nTIM6_UP\nI2C2_RX\nI2C2_RX\nUSART3_TX\nDAC1\nDAC2\nI2C2_TX\n1.\nThese requests are available on STM32F42xxx and STM32F43xxx only. \nTable 43. DMA1 request mapping (continued)\nPeripheral \nrequests\nStream 0\nStream 1\nStream 2\nStream 3 \nStream 4\nStream 5\nStream 6\nStream 7\nTable 44. DMA2 request mapping\nPeripheral \nrequests\nStream 0\nStream 1\nStream 2\nStream 3\nStream 4\nStream 5\nStream 6\nStream 7\nChannel 0\nADC1\n-SAI1_A(1)\nTIM8_CH1\nTIM8_CH2\nTIM8_CH3\n-SAI1_A(1)\nADC1\nSAI1_B(1)-\nTIM1_CH1\nTIM1_CH2\nTIM1_CH3\n-\nChannel 1\n-\nDCMI\nADC2\nADC2\nSAI1_B(1)-\n-SPI6_TX(1)\nSPI6_RX(1)-\nDCMI\nChannel 2\nADC3\nADC3\n-\nSPI5_RX(1)-\n-SPI5_TX(1)\nCRYP_OUT\nCRYP_IN\nHASH_IN\nChannel 3\nSPI1_RX\n-\nSPI1_RX\nSPI1_TX\n-\nSPI1_TX\n-\n-\nChannel 4\nSPI4_RX(1)-\n-SPI4_TX(1)\nUSART1_RX\nSDIO\n-\nUSART1_RX\nSDIO\nUSART1_TX\nChannel 5\n-\nUSART6_RX\nUSART6_RX\nSPI4_RX(1)-\n-SPI4_TX(1)\n-\nUSART6_TX\nUSART6_TX\nChannel 6\nTIM1_TRIG\nTIM1_CH1\nTIM1_CH2\nTIM1_CH1\nTIM1_CH4\nTIM1_TRIG\nTIM1_COM\nTIM1_UP\nTIM1_CH3\n-\nChannel 7\n-\nTIM8_UP\nTIM8_CH1\nTIM8_CH2\nTIM8_CH3\nSPI5_RX(1)-\nSPI5_TX(1)-\nTIM8_CH4\nTIM8_TRIG\nTIM8_COM\n1.\nThese requests are available on STM32F42xxx and STM32F43xxx. \n" }, { "page_number": 312, "page_indices": { "start_index": 692847, "end_index": 695331 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 312 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.5 DMA streams", 312 ], [ 3, "10.3.6 Source, destination and transfer modes", 312 ], [ 4, "Peripheral-to-memory mode", 312 ] ], "page_content": "DMA controller (DMA)\nRM0090\n312/1757\nRM0090 Rev 21\n10.3.5 \nDMA streams\nEach of the 8 DMA controller streams provides a unidirectional transfer link between a \nsource and a destination.\nEach stream can be configured to perform:\n•\nRegular type transactions: memory-to-peripherals, peripherals-to-memory or memory-\nto-memory transfers\n•\nDouble-buffer type transactions: double buffer transfers using two memory pointers for \nthe memory (while the DMA is reading/writing from/to a buffer, the application can \nwrite/read to/from the other buffer).\nThe amount of data to be transferred (up to 65535) is programmable and related to the \nsource width of the peripheral that requests the DMA transfer connected to the peripheral \nAHB port. The register that contains the amount of data items to be transferred is \ndecremented after each transaction.\n10.3.6 \nSource, destination and transfer modes\nBoth source and destination transfers can address peripherals and memories in the entire \n4 GB area, at addresses comprised between 0x0000 0000 and 0xFFFF FFFF.\nThe direction is configured using the DIR[1:0] bits in the DMA_SxCR register and offers \nthree possibilities: memory-to-peripheral, peripheral-to-memory or memory-to-memory \ntransfers. Table 45 describes the corresponding source and destination addresses.\n \nWhen the data width (programmed in the PSIZE or MSIZE bits in the DMA_SxCR register) \nis a half-word or a word, respectively, the peripheral or memory address written into the \nDMA_SxPAR or DMA_SxM0AR/M1AR registers has to be aligned on a word or half-word \naddress boundary, respectively.\nPeripheral-to-memory mode\nFigure 36 describes this mode.\nWhen this mode is enabled (by setting the bit EN in the DMA_SxCR register), each time a \nperipheral request occurs, the stream initiates a transfer from the source to fill the FIFO.\nWhen the threshold level of the FIFO is reached, the contents of the FIFO are drained and \nstored into the destination.\nThe transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral \nrequests the end of transfers (in case of a peripheral flow controller) or when the EN bit in \nthe DMA_SxCR register is cleared by software.\nTable 45. Source and destination address\nBits DIR[1:0] of the \nDMA_SxCR register\nDirection\nSource address\nDestination address\n00\nPeripheral-to-memory\nDMA_SxPAR\nDMA_SxM0AR\n01\nMemory-to-peripheral\nDMA_SxM0AR\nDMA_SxPAR\n10\nMemory-to-memory\nDMA_SxPAR\nDMA_SxM0AR\n11\nreserved\n-\n-\n" }, { "page_number": 313, "page_indices": { "start_index": 695331, "end_index": 697257 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 313 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.6 Source, destination and transfer modes", 312 ], [ 4, "Memory-to-peripheral mode", 313 ] ], "page_content": "RM0090 Rev 21\n313/1757\nRM0090\nDMA controller (DMA)\n341\nIn direct mode (when the DMDIS value in the DMA_SxFCR register is ‘0’), the threshold \nlevel of the FIFO is not used: after each single data transfer from the peripheral to the FIFO, \nthe corresponding data are immediately drained and stored into the destination.\nThe stream has access to the AHB source or destination port only if the arbitration of the \ncorresponding stream is won. This arbitration is performed using the priority defined for \neach stream using the PL[1:0] bits in the DMA_SxCR register.\nFigure 36. Peripheral-to-memory mode\n1.\nFor double-buffer mode.\nMemory-to-peripheral mode\nFigure 37 describes this mode.\nWhen this mode is enabled (by setting the EN bit in the DMA_SxCR register), the stream \nimmediately initiates transfers from the source to entirely fill the FIFO.\nEach time a peripheral request occurs, the contents of the FIFO are drained and stored into \nthe destination. When the level of the FIFO is lower than or equal to the predefined \nthreshold level, the FIFO is fully reloaded with data from the memory.\nThe transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral \nrequests the end of transfers (in case of a peripheral flow controller) or when the EN bit in \nthe DMA_SxCR register is cleared by software.\nIn direct mode (when the DMDIS value in the DMA_SxFCR register is '0'), the threshold \nlevel of the FIFO is not used. Once the stream is enabled, the DMA preloads the first data to \ntransfer into an internal FIFO. As soon as the peripheral requests a data transfer, the DMA \ntransfers the preloaded value into the configured destination. It then reloads again the \nPeripheral bus\nREQ_STREAMx\nArbiter\nFIFO\nAHB peripheral\nport\nMemory bus\nMemory\ndestination\nFIFO\nlevel\nPeripheral\nsource\nDMA_SxPAR\nPeripheral DMA request\nDMA controller\nDMA_SxM0AR\nDMA_SxM1AR(1)\nAHB memory\nport\nMS47543V1\n" }, { "page_number": 314, "page_indices": { "start_index": 697257, "end_index": 698972 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 314 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.6 Source, destination and transfer modes", 312 ], [ 4, "Memory-to-memory mode", 314 ] ], "page_content": "DMA controller (DMA)\nRM0090\n314/1757\nRM0090 Rev 21\nempty internal FIFO with the next data to be transfer. The preloaded data size corresponds \nto the value of the PSIZE bitfield in the DMA_SxCR register. \nThe stream has access to the AHB source or destination port only if the arbitration of the \ncorresponding stream is won. This arbitration is performed using the priority defined for \neach stream using the PL[1:0] bits in the DMA_SxCR register.\nFigure 37. Memory-to-peripheral mode\n1.\nFor double-buffer mode.\nMemory-to-memory mode\nThe DMA channels can also work without being triggered by a request from a peripheral. \nThis is the memory-to-memory mode, described in Figure 38.\nWhen the stream is enabled by setting the Enable bit (EN) in the DMA_SxCR register, the \nstream immediately starts to fill the FIFO up to the threshold level. When the threshold level \nis reached, the FIFO contents are drained and stored into the destination.\nThe transfer stops once the DMA_SxNDTR register reaches zero or when the EN bit in the \nDMA_SxCR register is cleared by software.\nThe stream has access to the AHB source or destination port only if the arbitration of the \ncorresponding stream is won. This arbitration is performed using the priority defined for \neach stream using the PL[1:0] bits in the DMA_SxCR register.\nNote:\nWhen memory-to-memory mode is used, the Circular and direct modes are not allowed.\nOnly the DMA2 controller is able to perform memory-to-memory transfers.\nPeripheral bus\nMemory bus\nREQ_STREAMx\nArbiter\nDMA_SxM1AR(1)\nFIFO\nAHB memory\nport\nAHB peripheral\nport\nDMA_SxPAR\nFIFO\nlevel\nDMA controller\nDMA_SxM0AR\nsource\ndestination\nPeripheral\nMemory\nPeripheral DMA request\nai15949\n" }, { "page_number": 315, "page_indices": { "start_index": 698972, "end_index": 700602 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 315 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.7 Pointer incrementation", 315 ] ], "page_content": "RM0090 Rev 21\n315/1757\nRM0090\nDMA controller (DMA)\n341\nFigure 38. Memory-to-memory mode\n1.\nFor double-buffer mode.\n10.3.7 \nPointer incrementation\nPeripheral and memory pointers can optionally be automatically post-incremented or kept \nconstant after each transfer depending on the PINC and MINC bits in the DMA_SxCR \nregister.\nDisabling the Increment mode is useful when the peripheral source or destination data are \naccessed through a single register.\nIf the Increment mode is enabled, the address of the next transfer is the address of the \nprevious one incremented by 1 (for bytes), 2 (for half-words) or 4 (for words) depending on \nthe data width programmed in the PSIZE or MSIZE bits in the DMA_SxCR register.\nIn order to optimize the packing operation, it is possible to fix the increment offset size for \nthe peripheral address whatever the size of the data transferred on the AHB peripheral port. \nThe PINCOS bit in the DMA_SxCR register is used to align the increment offset size with \nthe data size on the peripheral AHB port, or on a 32-bit address (the address is then \nincremented by 4). The PINCOS bit has an impact on the AHB peripheral port only.\nIf PINCOS bit is set, the address of the next transfer is the address of the previous one \nincremented by 4 (automatically aligned on a 32-bit address) whatever the PSIZE value. \nThe AHB memory port, however, is not impacted by this operation.\nMemory bus\nPeripheral bus\nStream enable\nArbiter\nDMA_SxM1AR(1)\nFIFO\nAHB memory\nport\nAHB peripheral\nport\nDMA_SxPAR\nFIFO\nlevel\nDMA controller\nDMA_SxM0AR\ndestination\nsource\nMemory 1\nMemory 2\nFIFO\nai15950\n" }, { "page_number": 316, "page_indices": { "start_index": 700602, "end_index": 703707 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 316 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.8 Circular mode", 316 ], [ 3, "10.3.9 Double buffer mode", 316 ] ], "page_content": "DMA controller (DMA)\nRM0090\n316/1757\nRM0090 Rev 21\n10.3.8 \nCircular mode\nThe Circular mode is available to handle circular buffers and continuous data flows (e.g. \nADC scan mode). This feature can be enabled using the CIRC bit in the DMA_SxCR \nregister.\nWhen the circular mode is activated, the number of data items to be transferred is \nautomatically reloaded with the initial value programmed during the stream configuration \nphase, and the DMA requests continue to be served.\nNote:\nIn the circular mode, it is mandatory to respect the following rule in case of a burst mode \nconfigured for memory:\nDMA_SxNDTR = Multiple of ((Mburst beat) × (Msize)/(Psize)), where:\n–\n(Mburst beat) = 4, 8 or 16 (depending on the MBURST bits in the DMA_SxCR \nregister)\n–\n((Msize)/(Psize)) = 1, 2, 4, 1/2 or 1/4 (Msize and Psize represent the MSIZE and \nPSIZE bits in the DMA_SxCR register. They are byte dependent)\n–\nDMA_SxNDTR = Number of data items to transfer on the AHB peripheral port\nFor example: Mburst beat = 8 (INCR8), MSIZE = ‘00’ (byte) and PSIZE = ‘01’ (half-word), in \nthis case: DMA_SxNDTR must be a multiple of (8 × 1/2 = 4).\nIf this formula is not respected, the DMA behavior and data integrity are not guaranteed.\nNDTR must also be a multiple of the Peripheral burst size multiplied by the peripheral data \nsize, otherwise this could result in a bad DMA behavior.\n10.3.9 \nDouble buffer mode\nThis mode is available for all the DMA1 and DMA2 streams.\nThe Double buffer mode is enabled by setting the DBM bit in the DMA_SxCR register.\nA double-buffer stream works as a regular (single buffer) stream with the difference that it \nhas two memory pointers. When the Double buffer mode is enabled, the Circular mode is \nautomatically enabled (CIRC bit in DMA_SxCR is don’t care) and at each end of transaction, \nthe memory pointers are swapped.\nIn this mode, the DMA controller swaps from one memory target to another at each end of \ntransaction. This allows the software to process one memory area while the second memory \narea is being filled/used by the DMA transfer. The double-buffer stream can work in both \ndirections (the memory can be either the source or the destination) as described in \nTable 46: Source and destination address registers in Double buffer mode (DBM=1).\nNote:\nIn Double buffer mode, it is possible to update the base address for the AHB memory port \non-the-fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled, by respecting the \nfollowing conditions:\n•\nWhen the CT bit is ‘0’ in the DMA_SxCR register, the DMA_SxM1AR register can be \nwritten. Attempting to write to this register while CT = '1' sets an error flag (TEIF) and \nthe stream is automatically disabled.\n•\nWhen the CT bit is ‘1’ in the DMA_SxCR register, the DMA_SxM0AR register can be \nwritten. Attempting to write to this register while CT = '0', sets an error flag (TEIF) and \nthe stream is automatically disabled.\nTo avoid any error condition, it is advised to change the base address as soon as the TCIF \nflag is asserted because, at this point, the targeted memory must have changed from \n" }, { "page_number": 317, "page_indices": { "start_index": 703707, "end_index": 706440 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 317 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.10 Programmable data width, packing/unpacking, endianess", 317 ] ], "page_content": "RM0090 Rev 21\n317/1757\nRM0090\nDMA controller (DMA)\n341\nmemory 0 to 1 (or from 1 to 0) depending on the value of CT in the DMA_SxCR register in \naccordance with one of the two above conditions.\nFor all the other modes (except the Double buffer mode), the memory address registers are \nwrite-protected as soon as the stream is enabled.\n \n10.3.10 \nProgrammable data width, packing/unpacking, endianess\nThe number of data items to be transferred has to be programmed into DMA_SxNDTR \n(number of data items to transfer bit, NDT) before enabling the stream (except when the \nflow controller is the peripheral, PFCTRL bit in DMA_SxCR is set).\nWhen using the internal FIFO, the data widths of the source and destination data are \nprogrammable through the PSIZE and MSIZE bits in the DMA_SxCR register (can be 8-, \n16- or 32-bit).\nWhen PSIZE and MSIZE are not equal:\n•\nThe data width of the number of data items to transfer, configured in the DMA_SxNDTR \nregister is equal to the width of the peripheral bus (configured by the PSIZE bits in the \nDMA_SxCR register). For instance, in case of peripheral-to-memory, memory-to-\nperipheral or memory-to-memory transfers and if the PSIZE[1:0] bits are configured for \nhalf-word, the number of bytes to be transferred is equal to 2 × NDT.\n•\nThe DMA controller only copes with little-endian addressing for both source and \ndestination. This is described in Table 47: Packing/unpacking & endian behavior (bit \nPINC = MINC = 1).\nThis packing/unpacking procedure may present a risk of data corruption when the operation \nis interrupted before the data are completely packed/unpacked. So, to ensure data \ncoherence, the stream may be configured to generate burst transfers: in this case, each \ngroup of transfers belonging to a burst are indivisible (refer to Section 10.3.11: Single and \nburst transfers).\nIn direct mode (DMDIS = 0 in the DMA_SxFCR register), the packing/unpacking of data is \nnot possible. In this case, it is not allowed to have different source and destination transfer \ndata widths: both are equal and defined by the PSIZE bits in the DMA_SxCR MSIZE bits are \ndon’t care).\nTable 46. Source and destination address registers in Double buffer mode (DBM=1)\nBits DIR[1:0] of the \nDMA_SxCR register\nDirection\nSource address\nDestination address\n00\nPeripheral-to-memory\nDMA_SxPAR\nDMA_SxM0AR / \nDMA_SxM1AR\n01\nMemory-to-peripheral\nDMA_SxM0AR / \nDMA_SxM1AR\nDMA_SxPAR\n10\nNot allowed(1)\n1.\nWhen the Double buffer mode is enabled, the Circular mode is automatically enabled. Since the memory-\nto-memory mode is not compatible with the Circular mode, when the Double buffer mode is enabled, it is \nnot allowed to configure the memory-to-memory mode.\n11\nReserved\n-\n-\n" }, { "page_number": 318, "page_indices": { "start_index": 706440, "end_index": 708475 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 318 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.10 Programmable data width, packing/unpacking, endianess", 317 ] ], "page_content": "DMA controller (DMA)\nRM0090\n318/1757\nRM0090 Rev 21\n \nNote:\nPeripheral port may be the source or the destination (it could also be the memory source in \nthe case of memory-to-memory transfer).\nPSIZE, MSIZE and NDT[15:0] have to be configured so as to ensure that the last transfer is \nnot incomplete. This can occur when the data width of the peripheral port (PSIZE bits) is \nlower than the data width of the memory port (MSIZE bits). This constraint is summarized in \nTable 48.\nTable 47. Packing/unpacking & endian behavior (bit PINC = MINC = 1)\nAHB \nmemory \nport \nwidth\nAHB \nperipheral \nport width\nNumber \nof data \nitems to \ntransfer \n(NDT)\n-\nMemory \ntransfer \nnumber\nMemory port \naddress / byte \nlane\nPeripher\nal \ntransfer \nnumber\nPeripheral port address / byte lane\n-\nPINCOS = 1\nPINCOS = 0\n8\n8\n4\n-\n1\n2\n3\n4\n0x0 / B0[7:0]\n0x1 / B1[7:0]\n0x2 / B2[7:0]\n0x3 / B3[7:0]\n1\n2\n3\n4\n0x0 / B0[7:0]\n0x4 / B1[7:0]\n0x8 / B2[7:0]\n0xC / B3[7:0]\n0x0 / B0[7:0]\n0x1 / B1[7:0]\n0x2 / B2[7:0]\n0x3 / B3[7:0]\n8\n16\n2\n-\n1\n2\n3\n4\n0x0 / B0[7:0]\n0x1 / B1[7:0]\n0x2 / B2[7:0]\n0x3 / B3[7:0]\n1\n2\n0x0 / B1|B0[15:0]\n0x4 / B3|B2[15:0]\n0x0 / B1|B0[15:0]\n0x2 / B3|B2[15:0]\n8\n32\n1\n-\n1\n2\n3\n4\n0x0 / B0[7:0]\n0x1 / B1[7:0]\n0x2 / B2[7:0]\n0x3 / B3[7:0]\n1\n0x0 / B3|B2|B1|B0[31:0]\n0x0 / B3|B2|B1|B0[31:0]\n16\n8\n4\n-\n1\n2\n0x0 / B1|B0[15:0]\n0x2 / B3|B2[15:0]\n1\n2\n3\n4\n0x0 / B0[7:0]\n0x4 / B1[7:0]\n0x8 / B2[7:0]\n0xC / B3[7:0]\n0x0 / B0[7:0]\n0x1 / B1[7:0]\n0x2 / B2[7:0]\n0x3 / B3[7:0]\n16\n16\n2\n-\n1\n2\n0x0 / B1|B0[15:0]\n0x2 / B1|B0[15:0]\n1\n2\n0x0 / B1|B0[15:0]\n0x4 / B3|B2[15:0]\n0x0 / B1|B0[15:0]\n0x2 / B3|B2[15:0]\n16\n32\n1\n-\n1\n2\n0x0 / B1|B0[15:0]\n0x2 / B3|B2[15:0]\n1\n0x0 / B3|B2|B1|B0[31:0]\n0x0 / B3|B2|B1|B0[31:0]\n32\n8\n4\n-\n1\n0x0 / B3|B2|B1|B0[31:0]\n1\n2\n3\n4\n0x0 / B0[7:0]\n0x4 / B1[7:0]\n0x8 / B2[7:0]\n0xC / B3[7:0]\n0x0 / B0[7:0]\n0x1 / B1[7:0]\n0x2 / B2[7:0]\n0x3 / B3[7:0]\n32\n16\n2\n-\n1\n0x0 /B3|B2|B1|B0[31:0]\n1\n2 \n0x0 / B1|B0[15:0]\n0x4 / B3|B2[15:0]\n0x0 / B1|B0[15:0]\n0x2 / B3|B2[15:0]\n32\n32\n1\n- 1\n0x0 /B3|B2|B1|B0 [31:0]\n1\n0x0 /B3|B2|B1|B0 [31:0]\n0x0 / B3|B2|B1|B0[31:0]\n" }, { "page_number": 319, "page_indices": { "start_index": 708475, "end_index": 710833 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 319 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.11 Single and burst transfers", 319 ] ], "page_content": "RM0090 Rev 21\n319/1757\nRM0090\nDMA controller (DMA)\n341\n \n10.3.11 \nSingle and burst transfers\nThe DMA controller can generate single transfers or incremental burst transfers of 4, 8 or 16 \nbeats. \nThe size of the burst is configured by software independently for the two AHB ports by using \nthe MBURST[1:0] and PBURST[1:0] bits in the DMA_SxCR register.\nThe burst size indicates the number of beats in the burst, not the number of bytes \ntransferred.\nTo ensure data coherence, each group of transfers that form a burst are indivisible: AHB \ntransfers are locked and the arbiter of the AHB bus matrix does not degrant the DMA master \nduring the sequence of the burst transfer.\nDepending on the single or burst configuration, each DMA request initiates a different \nnumber of transfers on the AHB peripheral port:\n•\nWhen the AHB peripheral port is configured for single transfers, each DMA request \ngenerates a data transfer of a byte, half-word or word depending on the PSIZE[1:0] bits \nin the DMA_SxCR register\n•\nWhen the AHB peripheral port is configured for burst transfers, each DMA request \ngenerates 4,8 or 16 beats of byte, half word or word transfers depending on the \nPBURST[1:0] and PSIZE[1:0] bits in the DMA_SxCR register.\nThe same as above has to be considered for the AHB memory port considering the \nMBURST and MSIZE bits.\nIn direct mode, the stream can only generate single transfers and the MBURST[1:0] and \nPBURST[1:0] bits are forced by hardware.\nThe address pointers (DMA_SxPAR or DMA_SxM0AR registers) must be chosen so as to \nensure that all transfers within a burst block are aligned on the address boundary equal to \nthe size of the transfer.\nThe burst configuration has to be selected in order to respect the AHB protocol, where \nbursts must not cross the 1 KB address boundary because the minimum address space that \ncan be allocated to a single slave is 1 KB. This means that the 1 KB address boundary \nshould not be crossed by a burst block transfer, otherwise an AHB error would be \ngenerated, that is not reported by the DMA registers.\nTable 48. Restriction on NDT versus PSIZE and MSIZE\nPSIZE[1:0] of DMA_SxCR\nMSIZE[1:0] of DMA_SxCR\nNDT[15:0] of DMA_SxNDTR\n00 (8-bit)\n01 (16-bit)\nmust be a multiple of 2\n00 (8-bit)\n10 (32-bit)\nmust be a multiple of 4\n01 (16-bit)\n10 (32-bit)\nmust be a multiple of 2\n" }, { "page_number": 320, "page_indices": { "start_index": 710833, "end_index": 712462 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 320 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.12 FIFO", 320 ], [ 4, "FIFO structure", 320 ] ], "page_content": "DMA controller (DMA)\nRM0090\n320/1757\nRM0090 Rev 21\n10.3.12 \nFIFO\nFIFO structure\nThe FIFO is used to temporarily store data coming from the source before transmitting them \nto the destination.\nEach stream has an independent 4-word FIFO and the threshold level is software-\nconfigurable between 1/4, 1/2, 3/4 or full.\nTo enable the use of the FIFO threshold level, the direct mode must be disabled by setting \nthe DMDIS bit in the DMA_SxFCR register.\nThe structure of the FIFO differs depending on the source and destination data widths, and \nis described in Figure 39: FIFO structure.\nFigure 39. FIFO structure \nSource: byte\n4 words\nbyte lane 0\nbyte lane 1\nbyte lane 2\nbyte lane 3\n1/4\n1/2\n3/4\nFull\nEmpty\nB0\nB1\nB2\nB3\nB4\nB5\nB6\nB7\nB8\nB9\nB10\nB 11\nB12\nB13\nB14\nB15\nDestination: word\nSource: byte\nDestination: half-word\n4 words\nbyte lane 0\nbyte lane 1\nbyte lane 2\nbyte lane 3\n1/4\n1/2\n3/4\nFull\nEmpty\nB0\nB1\nB2\nB3\nB4\nB5\nB6\nB7\nB8\nB9\nB10\nB 11\nB12\nB13\nB14\nB15\nW0\nW1\nW2\nW3\nH0\nH1\nH2\nH3\nH4\nH5\nH6\nH7\nSource: half-word\nDestination: word\n4 words\nbyte lane 0\nbyte lane 1\nbyte lane 2\nbyte lane 3\n1/4\n1/2\n3/4\nFull\nEmpty\nH0\nW0\nW1\nW2\nW3\nH1\nH2\nH3\nH4\nH5\nH6\nH7\nB15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0\nB15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0\nH7 H6 H5 H4 H3 H2 H1 H0\nH7, H6, H5, H4, H3, H2, H1, H0\nW3, W2, W1, W0\nW3, W2, W1, W0\nSource: half-word\n4-words\nbyte lane 0\nbyte lane 1\nbyte lane 2\nbyte lane 3\n1/4\n1/2\n3/4\nFull\nEmpty\nDestination: byte\nH7 H6 H5 H4 H3 H2 H1 H0\nB0\nB1\nB2\nB3\nB4\nB5\nB6\nB7\nB8\nB9\nB10\nB 11\nB12\nB13\nB14\nB15\nH0\nH1\nH2\nH3\nH4\nH5\nH6\nH7\nB15 B14 B13 B12 B11 B10 B9 B8 \nB7 B6 B5 B4 B3 B2 B1 B0\nai15951\n" }, { "page_number": 321, "page_indices": { "start_index": 712462, "end_index": 714906 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 321 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.12 FIFO", 320 ], [ 4, "FIFO threshold and burst configuration", 321 ] ], "page_content": "RM0090 Rev 21\n321/1757\nRM0090\nDMA controller (DMA)\n341\nFIFO threshold and burst configuration\nCaution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR \nregister) and the size of the memory burst (MBURST[1:0] of the DMA_SxCR register): The \ncontent pointed by the FIFO threshold must exactly match to an integer number of memory \nburst transfers. If this is not in the case, a FIFO error (flag FEIFx of the DMA_HISR or \nDMA_LISR register) is generated when the stream is enabled, then the stream is \nautomatically disabled. The allowed and forbidden configurations are described in the \nTable 49: FIFO threshold configurations.\n \nIn all cases, the burst size multiplied by the data size must not exceed the FIFO size (data \nsize can be: 1 (byte), 2 (half-word) or 4 (word)).\nIncomplete Burst transfer at the end of a DMA transfer may happen if one of the following \nconditions occurs:\n•\nFor the AHB peripheral port configuration: the total number of data items (set in the \nDMA_SxNDTR register) is not a multiple of the burst size multiplied by the data size\n•\nFor the AHB memory port configuration: the number of remaining data items in the \nFIFO to be transferred to the memory is not a multiple of the burst size multiplied by the \ndata size\nIn such cases, the remaining data to be transferred is managed in single mode by the DMA, \neven if a burst transaction was requested during the DMA stream configuration.\nNote:\nWhen burst transfers are requested on the peripheral AHB port and the FIFO is used \n(DMDIS = 1 in the DMA_SxCR register), it is mandatory to respect the following rule to \navoid permanent underrun or overrun conditions, depending on the DMA stream direction:\nIf (PBURST × PSIZE) = FIFO_SIZE (4 words), FIFO_Threshold = 3/4 is forbidden with \nPSIZE = 1, 2 or 4 and PBURST = 4, 8 or 16.\nThis rule ensures that enough FIFO space at a time is free to serve the request from the \nperipheral.\nTable 49. FIFO threshold configurations\nMSIZE\nFIFO level\nMBURST = INCR4\nMBURST = INCR8\nMBURST = INCR16\nByte\n1/4\n1 burst of 4 beats\nforbidden\nforbidden\n1/2\n2 bursts of 4 beats\n1 burst of 8 beats\n3/4\n3 bursts of 4 beats\nforbidden\nFull\n4 bursts of 4 beats\n2 bursts of 8 beats\n1 burst of 16 beats\nHalf-word\n1/4\nforbidden\nforbidden\nforbidden\n1/2\n1 burst of 4 beats\n3/4\nforbidden\nFull\n2 bursts of 4 beats\n1 burst of 8 beats\nWord\n1/4\nforbidden\nforbidden\n1/2\n3/4\nFull\n1 burst of 4 beats\n" }, { "page_number": 322, "page_indices": { "start_index": 714906, "end_index": 717836 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 322 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.12 FIFO", 320 ], [ 4, "FIFO flush", 322 ], [ 4, "Direct mode", 322 ], [ 3, "10.3.13 DMA transfer completion", 322 ] ], "page_content": "DMA controller (DMA)\nRM0090\n322/1757\nRM0090 Rev 21\nFIFO flush\nThe FIFO can be flushed when the stream is disabled by resetting the EN bit in the \nDMA_SxCR register and when the stream is configured to manage peripheral-to-memory or \nmemory-to-memory transfers: If some data are still present in the FIFO when the stream is \ndisabled, the DMA controller continues transferring the remaining data to the destination \n(even though stream is effectively disabled). When this flush is completed, the transfer \ncomplete status bit (TCIFx) in the DMA_LISR or DMA_HISR register is set.\nThe remaining data counter DMA_SxNDTR keeps the value in this case to indicate how \nmany data items are currently available in the destination memory.\nNote that during the FIFO flush operation, if the number of remaining data items in the FIFO \nto be transferred to memory (in bytes) is less than the memory data width (for example 2 \nbytes in FIFO while MSIZE is configured to word), data is sent with the data width set in the \nMSIZE bit in the DMA_SxCR register. This means that memory is written with an undesired \nvalue. The software may read the DMA_SxNDTR register to determine the memory area \nthat contains the good data (start address and last address).\nIf the number of remaining data items in the FIFO is lower than a burst size (if the MBURST \nbits in DMA_SxCR register are set to configure the stream to manage burst on the AHB \nmemory port), single transactions are generated to complete the FIFO flush.\nDirect mode\nBy default, the FIFO operates in direct mode (DMDIS bit in the DMA_SxFCR is reset) and \nthe FIFO threshold level is not used. This mode is useful when the system requires an \nimmediate and single transfer to or from the memory after each DMA request.\nWhen the DMA is configured in direct mode (FIFO disabled), to transfer data in memory-to-\nperipheral mode, the DMA preloads one data from the memory to the internal FIFO to \nensure an immediate data transfer as soon as a DMA request is triggered by a peripheral.\nTo avoid saturating the FIFO, it is recommended to configure the corresponding stream with \na high priority.\nThis mode is restricted to transfers where:\n•\nThe source and destination transfer widths are equal and both defined by the \nPSIZE[1:0] bits in DMA_SxCR (MSIZE[1:0] bits are don’t care)\n•\nBurst transfers are not possible (PBURST[1:0] and MBURST[1:0] bits in DMA_SxCR \nare don’t care)\nDirect mode must not be used when implementing memory-to-memory transfers.\n10.3.13 \nDMA transfer completion\nDifferent events can generate an end of transfer by setting the TCIFx bit in the DMA_LISR \nor DMA_HISR status register:\n•\nIn DMA flow controller mode:\n–\nThe DMA_SxNDTR counter has reached zero in the memory-to-peripheral mode\n–\nThe stream is disabled before the end of transfer (by clearing the EN bit in the \nDMA_SxCR register) and (when transfers are peripheral-to-memory or memory-\n" }, { "page_number": 323, "page_indices": { "start_index": 717836, "end_index": 720899 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 323 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.14 DMA transfer suspension", 323 ] ], "page_content": "RM0090 Rev 21\n323/1757\nRM0090\nDMA controller (DMA)\n341\nto-memory) all the remaining data have been flushed from the FIFO into the \nmemory\n•\nIn Peripheral flow controller mode:\n–\nThe last external burst or single request has been generated from the peripheral \nand (when the DMA is operating in peripheral-to-memory mode) the remaining \ndata have been transferred from the FIFO into the memory\n–\nThe stream is disabled by software, and (when the DMA is operating in peripheral-\nto-memory mode) the remaining data have been transferred from the FIFO into \nthe memory\nNote:\nThe transfer completion is dependent on the remaining data in FIFO to be transferred into \nmemory only in the case of peripheral-to-memory mode. This condition is not applicable in \nmemory-to-peripheral mode.\nIf the stream is configured in noncircular mode, after the end of the transfer (that is when the \nnumber of data to be transferred reaches zero), the DMA is stopped (EN bit in DMA_SxCR \nregister is cleared by Hardware) and no DMA request is served unless the software \nreprograms the stream and re-enables it (by setting the EN bit in the DMA_SxCR register).\n10.3.14 \nDMA transfer suspension\nAt any time, a DMA transfer can be suspended to be restarted later on or to be definitively \ndisabled before the end of the DMA transfer.\nThere are two cases:\n•\nThe stream disables the transfer with no later-on restart from the point where it was \nstopped. There is no particular action to do, except to clear the EN bit in the \nDMA_SxCR register to disable the stream. The stream may take time to be disabled \n(ongoing transfer is completed first). The transfer complete interrupt flag (TCIF in the \nDMA_LISR or DMA_HISR register) is set in order to indicate the end of transfer. The \nvalue of the EN bit in DMA_SxCR is now ‘0’ to confirm the stream interruption. The \nDMA_SxNDTR register contains the number of remaining data items at the moment \nwhen the stream was stopped so that the software can determine how many data items \nhave been transferred before the stream was interrupted.\n•\nThe stream suspends the transfer before the number of remaining data items to be \ntransferred in the DMA_SxNDTR register reaches 0. The aim is to restart the transfer \nlater by re-enabling the stream. In order to restart from the point where the transfer was \nstopped, the software has to read the DMA_SxNDTR register after disabling the stream \nby writing the EN bit in DMA_SxCR register (and then checking that it is at ‘0’) to know \nthe number of data items already collected. Then:\n–\nThe peripheral and/or memory addresses have to be updated in order to adjust \nthe address pointers\n–\nThe SxNDTR register has to be updated with the remaining number of data items \nto be transferred (the value read when the stream was disabled)\n–\nThe stream may then be re-enabled to restart the transfer from the point it was \nstopped\nNote:\nNote that a Transfer complete interrupt flag (TCIF in DMA_LISR or DMA_HISR) is set to \nindicate the end of transfer due to the stream interruption.\n" }, { "page_number": 324, "page_indices": { "start_index": 720899, "end_index": 723762 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 324 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.15 Flow controller", 324 ] ], "page_content": "DMA controller (DMA)\nRM0090\n324/1757\nRM0090 Rev 21\n10.3.15 \nFlow controller\nThe entity that controls the number of data to be transferred is known as the flow controller. \nThis flow controller is configured independently for each stream using the PFCTRL bit in the \nDMA_SxCR register.\nThe flow controller can be:\n•\nThe DMA controller: in this case, the number of data items to be transferred is \nprogrammed by software into the DMA_SxNDTR register before the DMA stream is \nenabled.\n•\nThe peripheral source or destination: this is the case when the number of data items to \nbe transferred is unknown. The peripheral indicates by hardware to the DMA controller \nwhen the last data are being transferred. This feature is only supported for peripherals \nwhich are able to signal the end of the transfer, that is:\n–\nSDIO\nWhen the peripheral flow controller is used for a given stream, the value written into the \nDMA_SxNDTR has no effect on the DMA transfer. Actually, whatever the value written, it is \nforced by hardware to 0xFFFF as soon as the stream is enabled, to respect the following \nschemes:\n•\nAnticipated stream interruption: EN bit in DMA_SxCR register is reset to 0 by the \nsoftware to stop the stream before the last data hardware signal (single or burst) is sent \nby the peripheral. In such a case, the stream is switched off and the FIFO flush is \ntriggered in the case of a peripheral-to-memory DMA transfer. The TCIFx flag of the \ncorresponding stream is set in the status register to indicate the DMA completion. To \nknow the number of data items transferred during the DMA transfer, read the \nDMA_SxNDTR register and apply the following formula:\n–\nNumber_of_data_transferred = 0xFFFF – DMA_SxNDTR\n•\nNormal stream interruption due to the reception of a last data hardware signal: the \nstream is automatically interrupted when the peripheral requests the last transfer \n(single or burst) and when this transfer is complete. the TCIFx flag of the corresponding \nstream is set in the status register to indicate the DMA transfer completion. To know the \nnumber of data items transferred, read the DMA_SxNDTR register and apply the same \nformula as above.\n•\nThe DMA_SxNDTR register reaches 0: the TCIFx flag of the corresponding stream is \nset in the status register to indicate the forced DMA transfer completion. The stream is \nautomatically switched off even though the last data hardware signal (single or burst) \nhas not been yet asserted. The already transferred data are not lost. This means that a \nmaximum of 65535 data items can be managed by the DMA in a single transaction, \neven in peripheral flow control mode.\nNote:\nWhen configured in memory-to-memory mode, the DMA is always the flow controller and \nthe PFCTRL bit is forced to 0 by hardware.\nThe Circular mode is forbidden in the peripheral flow controller mode.\n" }, { "page_number": 325, "page_indices": { "start_index": 723762, "end_index": 726512 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 325 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.16 Summary of the possible DMA configurations", 325 ], [ 3, "10.3.17 Stream configuration procedure", 325 ] ], "page_content": "RM0090 Rev 21\n325/1757\nRM0090\nDMA controller (DMA)\n341\n10.3.16 \nSummary of the possible DMA configurations\nTable 50 summarizes the different possible DMA configurations.\n \n10.3.17 \nStream configuration procedure\nThe following sequence should be followed to configure a DMA stream x (where x is the \nstream number):\n1.\nIf the stream is enabled, disable it by resetting the EN bit in the DMA_SxCR register, \nthen read this bit in order to confirm that there is no ongoing stream operation. Writing \nthis bit to 0 is not immediately effective since it is actually written to 0 once all the \ncurrent transfers have finished. When the EN bit is read as 0, this means that the \nstream is ready to be configured. It is therefore necessary to wait for the EN bit to be \ncleared before starting any stream configuration. All the stream dedicated bits set in the \nstatus register (DMA_LISR and DMA_HISR) from the previous data block DMA \ntransfer should be cleared before the stream can be re-enabled.\n2. \nSet the peripheral port register address in the DMA_SxPAR register. The data are \nmoved from/ to this address to/ from the peripheral port after the peripheral event.\n3. \nSet the memory address in the DMA_SxMA0R register (and in the DMA_SxMA1R \nregister in the case of a double buffer mode). The data are written to or read from this \nmemory after the peripheral event.\n4. \nConfigure the total number of data items to be transferred in the DMA_SxNDTR \nregister. After each peripheral event or each beat of the burst, this value is \ndecremented.\n5. \nSelect the DMA channel (request) using CHSEL[2:0] in the DMA_SxCR register.\n6. \nIf the peripheral is intended to be the flow controller and if it supports this feature, set \nthe PFCTRL bit in the DMA_SxCR register.\n7. \nConfigure the stream priority using the PL[1:0] bits in the DMA_SxCR register.\n8. \nConfigure the FIFO usage (enable or disable, threshold in transmission and reception)\n9. \nConfigure the data transfer direction, peripheral and memory incremented/fixed mode, \nsingle or burst transactions, peripheral and memory data widths, Circular mode, \nTable 50. Possible DMA configurations\nDMA transfer \nmode\nSource\nDestination\nFlow \ncontroller\nCircular \nmode\nTransfer \ntype\nDirect \nmode\nDouble \nbuffer mode\nPeripheral-to-\nmemory\nAHB\nperipheral port\nAHB\nmemory port\nDMA\npossible\nsingle\npossible\npossible\nburst\nforbidden\nPeripheral\nforbidden\nsingle\npossible\nforbidden\nburst\nforbidden\nMemory-to-\nperipheral\nAHB \nmemory port\nAHB \nperipheral port\nDMA\npossible\nsingle\npossible\npossible\nburst\nforbidden\nPeripheral\nforbidden\nsingle\npossible\nforbidden\nburst\nforbidden\nMemory-to-\nmemory\nAHB\nperipheral port\nAHB \nmemory port\nDMA only \nforbidden\nsingle\nforbidden\nforbidden\nburst\n" }, { "page_number": 326, "page_indices": { "start_index": 726512, "end_index": 729546 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 326 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.3 DMA functional description", 307 ], [ 3, "10.3.18 Error management", 326 ] ], "page_content": "DMA controller (DMA)\nRM0090\n326/1757\nRM0090 Rev 21\nDouble buffer mode and interrupts after half and/or full transfer, and/or errors in the \nDMA_SxCR register.\n10. Activate the stream by setting the EN bit in the DMA_SxCR register.\nAs soon as the stream is enabled, it can serve any DMA request from the peripheral \nconnected to the stream.\nOnce half the data have been transferred on the AHB destination port, the half-transfer flag \n(HTIF) is set and an interrupt is generated if the half-transfer interrupt enable bit (HTIE) is \nset. At the end of the transfer, the transfer complete flag (TCIF) is set and an interrupt is \ngenerated if the transfer complete interrupt enable bit (TCIE) is set.\nWarning:\nTo switch off a peripheral connected to a DMA stream \nrequest, it is mandatory to, first, switch off the DMA stream to \nwhich the peripheral is connected, then to wait for EN bit = 0. \nOnly then can the peripheral be safely disabled.\n10.3.18 \nError management\nThe DMA controller can detect the following errors:\n•\nTransfer error: the transfer error interrupt flag (TEIFx) is set when:\n–\nA bus error occurs during a DMA read or a write access\n–\nA write access is requested by software on a memory address register in Double \nbuffer mode whereas the stream is enabled and the current target memory is the \none impacted by the write into the memory address register (refer to \nSection 10.3.9: Double buffer mode)\n•\nFIFO error: the FIFO error interrupt flag (FEIFx) is set if:\n–\nA FIFO underrun condition is detected\n–\nA FIFO overrun condition is detected (no detection in memory-to-memory mode \nbecause requests and transfers are internally managed by the DMA)\n–\nThe stream is enabled while the FIFO threshold level is not compatible with the \nsize of the memory burst (refer to Table 49: FIFO threshold configurations)\n•\nDirect mode error: the direct mode error interrupt flag (DMEIFx) can only be set in the \nperipheral-to-memory mode while operating in direct mode and when the MINC bit in \nthe DMA_SxCR register is cleared. This flag is set when a DMA request occurs while \nthe previous data have not yet been fully transferred into the memory (because the \nmemory bus was not granted). In this case, the flag indicates that 2 data items were be \ntransferred successively to the same destination address, which could be an issue if \nthe destination is not able to manage this situation\nIn direct mode, the FIFO error flag can also be set under the following conditions:\n•\nIn the peripheral-to-memory mode, the FIFO can be saturated (overrun) if the memory \nbus is not granted for several peripheral requests\n•\nIn the memory-to-peripheral mode, an underrun condition may occur if the memory bus \nhas not been granted before a peripheral request occurs\nIf the TEIFx or the FEIFx flag is set due to incompatibility between burst size and FIFO \nthreshold level, the faulty stream is automatically disabled through a hardware clear of its \nEN bit in the corresponding stream configuration register (DMA_SxCR).\n" }, { "page_number": 327, "page_indices": { "start_index": 729546, "end_index": 731221 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 327 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.4 DMA interrupts", 327 ] ], "page_content": "RM0090 Rev 21\n327/1757\nRM0090\nDMA controller (DMA)\n341\nIf the DMEIFx or the FEIFx flag is set due to an overrun or underrun condition, the faulty \nstream is not automatically disabled and it is up to the software to disable or not the stream \nby resetting the EN bit in the DMA_SxCR register. This is because there is no data loss \nwhen this kind of errors occur.\nWhen the stream's error interrupt flag (TEIF, FEIF, DMEIF) in the DMA_LISR or DMA_HISR \nregister is set, an interrupt is generated if the corresponding interrupt enable bit (TEIE, \nFEIE, DMIE) in the DMA_SxCR or DMA_SxFCR register is set.\nNote:\nWhen a FIFO overrun or underrun condition occurs, the data are not lost because the \nperipheral request is not acknowledged by the stream until the overrun or underrun \ncondition is cleared. If this acknowledge takes too much time, the peripheral itself may \ndetect an overrun or underrun condition of its internal buffer and data might be lost.\n10.4 \nDMA interrupts\nFor each DMA stream, an interrupt can be produced on the following events:\n•\nHalf-transfer reached\n•\nTransfer complete\n•\nTransfer error\n•\nFifo error (overrun, underrun or FIFO level error)\n•\nDirect mode error\nSeparate interrupt enable control bits are available for flexibility as shown in Table 51.\n \nNote:\nBefore setting an Enable control bit to ‘1’, the corresponding event flag should be cleared, \notherwise an interrupt is immediately generated.\nTable 51. DMA interrupt requests\nInterrupt event\nEvent flag\nEnable control bit\nHalf-transfer\nHTIF\nHTIE\nTransfer complete\nTCIF\nTCIE\nTransfer error\nTEIF\nTEIE\nFIFO overrun/underrun\nFEIF\nFEIE\nDirect mode error\nDMEIF\nDMEIE\n" }, { "page_number": 328, "page_indices": { "start_index": 731221, "end_index": 733279 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 328 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.5 DMA registers", 328 ], [ 3, "10.5.1 DMA low interrupt status register (DMA_LISR)", 328 ] ], "page_content": "DMA controller (DMA)\nRM0090\n328/1757\nRM0090 Rev 21\n10.5 \nDMA registers\nThe DMA registers have to be accessed by words (32 bits). \n10.5.1 \nDMA low interrupt status register (DMA_LISR)\nAddress offset: 0x00\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTCIF3\nHTIF3\nTEIF3\nDMEIF3\nReserv\ned\nFEIF3\nTCIF2\nHTIF2\nTEIF2\nDMEIF2\nReserv\ned\nFEIF2\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTCIF1\nHTIF1\nTEIF1\nDMEIF1\nReserv\ned\nFEIF1\nTCIF0\nHTIF0\nTEIF0\nDMEIF0\nReserv\ned\nFEIF0\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:28, 15:12 Reserved, must be kept at reset value.\nBits 27, 21, 11, 5 TCIFx: Stream x transfer complete interrupt flag (x = 3..0)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_LIFCR register.\n0: No transfer complete event on stream x\n1: A transfer complete event occurred on stream x\nBits 26, 20, 10, 4 HTIFx: Stream x half transfer interrupt flag (x=3..0)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_LIFCR register.\n0: No half transfer event on stream x\n1: A half transfer event occurred on stream x\nBits 25, 19, 9, 3 TEIFx: Stream x transfer error interrupt flag (x=3..0)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_LIFCR register.\n0: No transfer error on stream x\n1: A transfer error occurred on stream x\nBits 24, 18, 8, 2 DMEIFx: Stream x direct mode error interrupt flag (x=3..0)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_LIFCR register.\n0: No Direct Mode Error on stream x\n1: A Direct Mode Error occurred on stream x\nBits 23, 17, 7, 1 Reserved, must be kept at reset value.\nBits 22, 16, 6, 0 FEIFx: Stream x FIFO error interrupt flag (x=3..0)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_LIFCR register.\n0: No FIFO Error event on stream x\n1: A FIFO Error event occurred on stream x\n" }, { "page_number": 329, "page_indices": { "start_index": 733279, "end_index": 735255 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 329 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.5 DMA registers", 328 ], [ 3, "10.5.2 DMA high interrupt status register (DMA_HISR)", 329 ] ], "page_content": "RM0090 Rev 21\n329/1757\nRM0090\nDMA controller (DMA)\n341\n10.5.2 \nDMA high interrupt status register (DMA_HISR)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTCIF7\nHTIF7\nTEIF7\nDMEIF7\nReserv\ned\nFEIF7\nTCIF6\nHTIF6\nTEIF6\nDMEIF6\nReserv\ned\nFEIF6\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTCIF5\nHTIF5\nTEIF5\nDMEIF5\nReserv\ned\nFEIF5\nTCIF4\nHTIF4\nTEIF4\nDMEIF4\nReserv\ned\nFEIF4\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:28, 15:12 Reserved, must be kept at reset value.\nBits 27, 21, 11, 5 TCIFx: Stream x transfer complete interrupt flag (x=7..4)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_HIFCR register.\n0: No transfer complete event on stream x\n1: A transfer complete event occurred on stream x\nBits 26, 20, 10, 4 HTIFx: Stream x half transfer interrupt flag (x=7..4)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_HIFCR register.\n0: No half transfer event on stream x\n1: A half transfer event occurred on stream x\nBits 25, 19, 9, 3 TEIFx: Stream x transfer error interrupt flag (x=7..4)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_HIFCR register.\n0: No transfer error on stream x\n1: A transfer error occurred on stream x\nBits 24, 18, 8, 2 DMEIFx: Stream x direct mode error interrupt flag (x=7..4)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_HIFCR register.\n0: No Direct mode error on stream x\n1: A Direct mode error occurred on stream x\nBits 23, 17, 7, 1 Reserved, must be kept at reset value.\nBits 22, 16, 6, 0 FEIFx: Stream x FIFO error interrupt flag (x=7..4)\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the \nDMA_HIFCR register.\n0: No FIFO error event on stream x\n1: A FIFO error event occurred on stream x\n" }, { "page_number": 330, "page_indices": { "start_index": 735255, "end_index": 737716 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 330 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.5 DMA registers", 328 ], [ 3, "10.5.3 DMA low interrupt flag clear register (DMA_LIFCR)", 330 ], [ 3, "10.5.4 DMA high interrupt flag clear register (DMA_HIFCR)", 330 ] ], "page_content": "DMA controller (DMA)\nRM0090\n330/1757\nRM0090 Rev 21\n10.5.3 \nDMA low interrupt flag clear register (DMA_LIFCR)\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n \n10.5.4 \nDMA high interrupt flag clear register (DMA_HIFCR)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nCTCIF3 CHTIF3 CTEIF3 CDMEIF3\nReserved\nCFEIF3\nCTCIF2\nCHTIF2\nCTEIF2\nCDMEIF2\nReserved\nCFEIF2\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCTCIF1 CHTIF1 CTEIF1 CDMEIF1\nReserved\nCFEIF1\nCTCIF0\nCHTIF0\nCTEIF0\nCDMEIF0\nReserved\nCFEIF0\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBits 31:28, 15:12 Reserved, must be kept at reset value.\nBits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 3..0)\nWriting 1 to this bit clears the corresponding TCIFx flag in the DMA_LISR register\nBits 26, 20, 10, 4 CHTIFx: Stream x clear half transfer interrupt flag (x = 3..0)\nWriting 1 to this bit clears the corresponding HTIFx flag in the DMA_LISR register\nBits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 3..0)\nWriting 1 to this bit clears the corresponding TEIFx flag in the DMA_LISR register\nBits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 3..0)\nWriting 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR register\nBits 23, 17, 7, 1 Reserved, must be kept at reset value.\nBits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 3..0)\nWriting 1 to this bit clears the corresponding CFEIFx flag in the DMA_LISR register\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nCTCIF7 CHTIF7 CTEIF7 CDMEIF7\nReserved\nCFEIF7\nCTCIF6\nCHTIF6\nCTEIF6\nCDMEIF6\nReserved\nCFEIF6\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCTCIF5 CHTIF5 CTEIF5 CDMEIF5\nReserved\nCFEIF5\nCTCIF4\nCHTIF4\nCTEIF4\nCDMEIF4\nReserved\nCFEIF4\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBits 31:28, 15:12 Reserved, must be kept at reset value.\nBits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 7..4)\nWriting 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register\nBits 26, 20, 10, 4 CHTIFx: Stream x clear half transfer interrupt flag (x = 7..4)\nWriting 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register\nBits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 7..4)\nWriting 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register\n" }, { "page_number": 331, "page_indices": { "start_index": 737716, "end_index": 739901 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 331 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.5 DMA registers", 328 ], [ 3, "10.5.5 DMA stream x configuration register (DMA_SxCR) (x = 0..7)", 331 ] ], "page_content": "RM0090 Rev 21\n331/1757\nRM0090\nDMA controller (DMA)\n341\n10.5.5 \nDMA stream x configuration register (DMA_SxCR) (x = 0..7)\nThis register is used to configure the concerned stream.\nAddress offset: 0x10 + 0x18 × stream number\nReset value: 0x0000 0000\n \nBits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 7..4)\nWriting 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register\nBits 23, 17, 7, 1 Reserved, must be kept at reset value.\nBits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 7..4)\nWriting 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nCHSEL[2:0]\nMBURST [1:0]\nPBURST[1:0]\nReser-\nved\nCT\nDBM\nPL[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBits 27:25 CHSEL[2:0]: Channel selection\nThese bits are set and cleared by software.\n000: channel 0 selected\n001: channel 1 selected\n010: channel 2 selected\n011: channel 3 selected\n100: channel 4 selected\n101: channel 5 selected\n110: channel 6 selected\n111: channel 7 selected\nThese bits are protected and can be written only if EN is ‘0’\nBits 24:23 MBURST: Memory burst transfer configuration\nThese bits are set and cleared by software.\n00: single transfer\n01: INCR4 (incremental burst of 4 beats)\n10: INCR8 (incremental burst of 8 beats)\n11: INCR16 (incremental burst of 16 beats)\nThese bits are protected and can be written only if EN is ‘0’\nIn direct mode, these bits are forced to 0x0 by hardware as soon as bit EN= '1'.\nBits 22:21 PBURST[1:0]: Peripheral burst transfer configuration\nThese bits are set and cleared by software.\n00: single transfer\n01: INCR4 (incremental burst of 4 beats)\n10: INCR8 (incremental burst of 8 beats)\n11: INCR16 (incremental burst of 16 beats)\nThese bits are protected and can be written only if EN is ‘0’\nIn direct mode, these bits are forced to 0x0 by hardware.\nBit 20 Reserved, must be kept at reset value.\n" }, { "page_number": 332, "page_indices": { "start_index": 739901, "end_index": 742225 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 332 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.5 DMA registers", 328 ], [ 3, "10.5.5 DMA stream x configuration register (DMA_SxCR) (x = 0..7)", 331 ] ], "page_content": "DMA controller (DMA)\nRM0090\n332/1757\nRM0090 Rev 21\nBit 19 CT: Current target (only in double buffer mode)\nThis bits is set and cleared by hardware. It can also be written by software.\n0: The current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer)\n1: The current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer)\nThis bit can be written only if EN is ‘0’ to indicate the target memory area of the first transfer. \nOnce the stream is enabled, this bit operates as a status flag indicating which memory area \nis the current target.\nBit 18 DBM: Double buffer mode\nThis bits is set and cleared by software.\n0: No buffer switching at the end of transfer\n1: Memory target switched at the end of the DMA transfer\nThis bit is protected and can be written only if EN is ‘0’.\nBits 17:16 PL[1:0]: Priority level\nThese bits are set and cleared by software.\n00: Low\n01: Medium\n10: High\n11: Very high\nThese bits are protected and can be written only if EN is ‘0’.\nBit 15 PINCOS: Peripheral increment offset size\nThis bit is set and cleared by software\n0: The offset size for the peripheral address calculation is linked to the PSIZE\n1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment).\nThis bit has no meaning if bit PINC = '0'.\nThis bit is protected and can be written only if EN = '0'.\nThis bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct \nmode is selected or if PBURST are different from “00”.\nBits 14:13 MSIZE[1:0]: Memory data size\nThese bits are set and cleared by software.\n00: byte (8-bit)\n01: half-word (16-bit)\n10: word (32-bit)\n11: reserved\nThese bits are protected and can be written only if EN is ‘0’.\nIn direct mode, MSIZE is forced by hardware to the same value as PSIZE as soon as bit EN \n= '1'.\nBits 12:11 PSIZE[1:0]: Peripheral data size\nThese bits are set and cleared by software.\n00: Byte (8-bit)\n01: Half-word (16-bit)\n10: Word (32-bit)\n11: reserved\nThese bits are protected and can be written only if EN is ‘0’\nBit 10 MINC: Memory increment mode\nThis bit is set and cleared by software.\n0: Memory address pointer is fixed\n1: Memory address pointer is incremented after each data transfer (increment is done \naccording to MSIZE)\nThis bit is protected and can be written only if EN is ‘0’.\n" }, { "page_number": 333, "page_indices": { "start_index": 742225, "end_index": 744124 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 333 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.5 DMA registers", 328 ], [ 3, "10.5.5 DMA stream x configuration register (DMA_SxCR) (x = 0..7)", 331 ] ], "page_content": "RM0090 Rev 21\n333/1757\nRM0090\nDMA controller (DMA)\n341\nBit 9 PINC: Peripheral increment mode\nThis bit is set and cleared by software.\n0: Peripheral address pointer is fixed\n1: Peripheral address pointer is incremented after each data transfer (increment is done \naccording to PSIZE)\nThis bit is protected and can be written only if EN is ‘0’.\nBit 8 CIRC: Circular mode\nThis bit is set and cleared by software and can be cleared by hardware.\n0: Circular mode disabled\n1: Circular mode enabled\nWhen the peripheral is the flow controller (bit PFCTRL=1) and the stream is enabled (bit \nEN=1), then this bit is automatically forced by hardware to 0. \nIt is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is \nenabled (bit EN ='1').\nBits 7:6 DIR[1:0]: Data transfer direction\nThese bits are set and cleared by software.\n00: Peripheral-to-memory\n01: Memory-to-peripheral\n10: Memory-to-memory\n11: reserved\nThese bits are protected and can be written only if EN is ‘0’.\nBit 5 PFCTRL: Peripheral flow controller\nThis bit is set and cleared by software.\n0: The DMA is the flow controller\n1: The peripheral is the flow controller\nThis bit is protected and can be written only if EN is ‘0’.\nWhen the memory-to-memory mode is selected (bits DIR[1:0]=10), then this bit is \nautomatically forced to 0 by hardware.\nBit 4 TCIE: Transfer complete interrupt enable\nThis bit is set and cleared by software.\n0: TC interrupt disabled\n1: TC interrupt enabled\nBit 3 HTIE: Half transfer interrupt enable\nThis bit is set and cleared by software.\n0: HT interrupt disabled\n1: HT interrupt enabled\nBit 2 TEIE: Transfer error interrupt enable\nThis bit is set and cleared by software.\n0: TE interrupt disabled\n1: TE interrupt enabled\nBit 1 DMEIE: Direct mode error interrupt enable\nThis bit is set and cleared by software.\n0: DME interrupt disabled\n1: DME interrupt enabled\n" }, { "page_number": 334, "page_indices": { "start_index": 744124, "end_index": 746014 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 334 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.5 DMA registers", 328 ], [ 3, "10.5.6 DMA stream x number of data register (DMA_SxNDTR) (x = 0..7)", 334 ] ], "page_content": "DMA controller (DMA)\nRM0090\n334/1757\nRM0090 Rev 21\n10.5.6 \nDMA stream x number of data register (DMA_SxNDTR) (x = 0..7)\nAddress offset: 0x14 + 0x18 × stream number\nReset value: 0x0000 0000\n \n \nBit 0 EN: Stream enable / flag stream ready when read low\nThis bit is set and cleared by software.\n0: Stream disabled\n1: Stream enabled\nThis bit may be cleared by hardware:\n–\non a DMA end of transfer (stream ready to be configured)\n–\nif a transfer error occurs on the AHB master buses\n–\nwhen the FIFO threshold on memory AHB port is not compatible with the size of the \nburst\nWhen this bit is read as 0, the software is allowed to program the Configuration and FIFO \nbits registers. It is forbidden to write these registers when the EN bit is read as 1.\nNote: Before setting EN bit to '1' to start a new transfer, the event flags corresponding to the \nstream in DMA_LISR or DMA_HISR register must be cleared. \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nNDT[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 NDT[15:0]: Number of data items to transfer\nNumber of data items to be transferred (0 up to 65535). This register can be written only \nwhen the stream is disabled. When the stream is enabled, this register is read-only, \nindicating the remaining data items to be transmitted. This register decrements after each \nDMA transfer.\nOnce the transfer has completed, this register can either stay at zero (when the stream is in \nnormal mode) or be reloaded automatically with the previously programmed value in the \nfollowing cases:\n–\nwhen the stream is configured in Circular mode.\n–\nwhen the stream is enabled again by setting EN bit to '1'\nIf the value of this register is zero, no transaction can be served even if the stream is \nenabled.\n" }, { "page_number": 335, "page_indices": { "start_index": 746014, "end_index": 747755 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 335 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.5 DMA registers", 328 ], [ 3, "10.5.7 DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7)", 335 ], [ 3, "10.5.8 DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7)", 335 ], [ 3, "10.5.9 DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7)", 335 ] ], "page_content": "RM0090 Rev 21\n335/1757\nRM0090\nDMA controller (DMA)\n341\n10.5.7 \nDMA stream x peripheral address register (DMA_SxPAR) (x = 0..7)\nAddress offset: 0x18 + 0x18 × stream number\nReset value: 0x0000 0000\n \n \n10.5.8 \nDMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7)\nAddress offset: 0x1C + 0x18 × stream number\nReset value: 0x0000 0000\n \n \n10.5.9 \nDMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7)\nAddress offset: 0x20 + 0x18 × stream number\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nPAR[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPAR[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 PAR[31:0]: Peripheral address\nBase address of the peripheral data register from/to which the data are read/written.\nThese bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR register.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nM0A[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nM0A[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 M0A[31:0]: Memory 0 address\nBase address of Memory area 0 from/to which the data are read/written.\nThese bits are write-protected. They can be written only if:\n–\nthe stream is disabled (bit EN= '0' in the DMA_SxCR register) or\n–\nthe stream is enabled (EN=’1’ in DMA_SxCR register) and bit CT = '1' in the \nDMA_SxCR register (in Double buffer mode).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nM1A[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nM1A[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 336, "page_indices": { "start_index": 747755, "end_index": 748785 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 336 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.5 DMA registers", 328 ], [ 3, "10.5.10 DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7)", 336 ] ], "page_content": "DMA controller (DMA)\nRM0090\n336/1757\nRM0090 Rev 21\n \n10.5.10 \nDMA stream x FIFO control register (DMA_SxFCR) (x = 0..7)\nAddress offset: 0x24 + 0x18 × stream number\nReset value: 0x0000 0021\nBits 31:0 M1A[31:0]: Memory 1 address (used in case of Double buffer mode)\nBase address of Memory area 1 from/to which the data are read/written.\nThis register is used only for the Double buffer mode.\nThese bits are write-protected. They can be written only if:\n–\nthe stream is disabled (bit EN= '0' in the DMA_SxCR register) or\n–\nthe stream is enabled (EN=’1’ in DMA_SxCR register) and bit CT = '0' in the \nDMA_SxCR register.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFEIE\nReser\nved\nFS[2:0]\nDMDIS\nFTH[1:0]\nrw\nr\nr\nr\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBit 7 FEIE: FIFO error interrupt enable\nThis bit is set and cleared by software.\n0: FE interrupt disabled\n1: FE interrupt enabled\nBit 6 Reserved, must be kept at reset value.\n" }, { "page_number": 337, "page_indices": { "start_index": 748785, "end_index": 749881 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 337 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.5 DMA registers", 328 ], [ 3, "10.5.10 DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7)", 336 ] ], "page_content": "RM0090 Rev 21\n337/1757\nRM0090\nDMA controller (DMA)\n341\nBits 5:3 FS[2:0]: FIFO status\nThese bits are read-only.\n000: 0 < fifo_level < 1/4 \n001: 1/4 ≤ fifo_level < 1/2 \n010: 1/2 ≤ fifo_level < 3/4\n011: 3/4 ≤ fifo_level < full\n100: FIFO is empty\n101: FIFO is full\nothers: no meaning\nThese bits are not relevant in the direct mode (DMDIS bit is zero).\nBit 2 DMDIS: Direct mode disable\nThis bit is set and cleared by software. It can be set by hardware.\n0: Direct mode enabled\n1: Direct mode disabled\nThis bit is protected and can be written only if EN is ‘0’.\nThis bit is set by hardware if the memory-to-memory mode is selected (DIR bit in \nDMA_SxCR are “10”) and the EN bit in the DMA_SxCR register is ‘1’ because the direct \nmode is not allowed in the memory-to-memory configuration.\nBits 1:0 FTH[1:0]: FIFO threshold selection\nThese bits are set and cleared by software.\n00: 1/4 full FIFO\n01: 1/2 full FIFO\n10: 3/4 full FIFO\n11: full FIFO\nThese bits are not used in the direct mode when the DMIS value is zero.\nThese bits are protected and can be written only if EN is ‘0’.\n" }, { "page_number": 338, "page_indices": { "start_index": 749881, "end_index": 752234 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 338 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.5 DMA registers", 328 ], [ 3, "10.5.11 DMA register map", 338 ] ], "page_content": "DMA controller (DMA)\nRM0090\n338/1757\nRM0090 Rev 21\n10.5.11 \nDMA register map\nTable 52 summarizes the DMA registers.\nTable 52. DMA register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x0000\nDMA_LISR\nReserved\nTCIF3\nHTIF3\nTEIF3\nDMEIF3\nReserved\nFEIF3\nTCIF2\nHTIF2\nTEIF2\nDMEIF2\nReserved\nFEIF2\nReserved\nTCIF1\nHTIF1\nTEIF1\nDMEIF1\nReserved\nFEIF1\nTCIF0\nHTIF0\nTEIF0\nDMEIF0\nReserved\nFEIF0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0004\nDMA_HISR\nReserved\nTCIF7\nHTIF7\nTEIF7\nDMEIF7\nReserved\nFEIF7\nTCIF6\nHTIF6\nTEIF6\nDMEIF6\nReserved\nFEIF6\nReserved\nTCIF5\nHTIF5\nTEIF5\nDMEIF5\nReserved\nFEIF5\nTCIF4\nHTIF4\nTEIF4\nDMEIF4\nReserved\nFEIF4\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0008\nDMA_LIFCR\nReserved\nCTCIF3\nCHTIF3\nTEIF3\nCDMEIF3\nReserved\nCFEIF3\nCTCIF2\nCHTIF2\nCTEIF2\nCDMEIF2\nReserved\nCFEIF2\nReserved\nCTCIF1\nCHTIF1\nCTEIF1\nCDMEIF1\nReserved\nCFEIF1\nCTCIF0\nCHTIF0\nCTEIF0\nCDMEIF0\nReserved\nCFEIF0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\nReserved\n0\n0\n0\n0\n0\nReserved\n0\n0\n0\n0\n0\nReserved\n0\n0x000C\nDMA_HIFCR\nReserved\nCTCIF7\nCHTIF7\nCTEIF7\nCDMEIF7\nReserved\nCFEIF7\nCTCIF6\nCHTIF6\nCTEIF6\nCDMEIF6\n-\nCFEIF6\nReserved\nCTCIF5\nCHTIF5\nCTEIF5\nCDMEIF5\n-\nCFEIF5\nCTCIF4\nCHTIF4\nCTEIF4\nCDMEIF4\n-\nCFEIF4\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n-\n0\n0\n0\n0\n0\n-\n0\n0\n0\n0\n0\n-\n0\n0x0010\nDMA_S0CR\nReserved\nCHSEL[2:0]\nMBURST[1:0] \nPBURST[1:0] \nReserved\nCT\nDBM\nPL[1:0]\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0014\nDMA_S0NDTR\nReserved\nNDT[15:.]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0018\nDMA_S0PAR\nPA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x001C\nDMA_S0M0AR\nM0A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0020\nDMA_S0M1AR\nM1A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0024\nDMA_S0FCR\nReserved\nFEIE\nReserved\nFS[2:0]\nDMDIS\nFTH\n[1:0]\nReset value\n0\n1\n0\n0\n0\n0\n1\n0x0028\nDMA_S1CR\nReserved\nCHSEL\n[2:0]\nMBURST[1:]\nPBURST[1:0]\nReserved\nCT\nDBM\nPL[1:0]\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x002C\nDMA_S1NDTR\nReserved\nNDT[15:.]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n" }, { "page_number": 339, "page_indices": { "start_index": 752234, "end_index": 754107 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 339 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.5 DMA registers", 328 ], [ 3, "10.5.11 DMA register map", 338 ] ], "page_content": "RM0090 Rev 21\n339/1757\nRM0090\nDMA controller (DMA)\n341\n0x0030\nDMA_S1PAR\nPA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0034\nDMA_S1M0AR\nM0A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0038\nDMA_S1M1AR\nM1A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x003C\nDMA_S1FCR\nReserved\nFEIE\nReserved\nFS[2:0]\nDMDIS\nFTH\n[1:0]\nReset value\n0\n1\n0\n0\n0\n0\n1\n0x0040\nDMA_S2CR\nReserved\nCHSEL\n[2:0]\nMBURST[1:0]\nPBURST[1:0]\nReserved\nCT\nDBM\nPL[1:0]\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR\n[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0044\nDMA_S2NDTR\nReserved\nNDT[15:.]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0048\nDMA_S2PAR\nPA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x004C\nDMA_S2M0AR\nM0A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0050\nDMA_S2M1AR\nM1A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0054\nDMA_S2FCR\nReserved\nFEIE\nReserved\nFS[2:0]\nDMDIS\nFTH\n[1:0]\nReset value\n0\n1\n0\n0\n0\n0\n1\n0x0058\nDMA_S3CR\nReserved\nCHSEL[2:0]\nMBURST[1:0]\nPBURST[1:0]\nReserved\nCT\nDBM\nPL[1:0]\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x005C\nDMA_S3NDTR\nReserved\nNDT[15:.]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0060\nDMA_S3PAR\nPA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0064\nDMA_S3M0AR\nM0A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 52. DMA register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 340, "page_indices": { "start_index": 754107, "end_index": 756380 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 340 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.5 DMA registers", 328 ], [ 3, "10.5.11 DMA register map", 338 ] ], "page_content": "DMA controller (DMA)\nRM0090\n340/1757\nRM0090 Rev 21\n0x0068\nDMA_S3M1AR\nM1A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x006C\nDMA_S3FCR\nReserved\nFEIE\nReserved\nFS[2:0]\nDMDIS\nFTH\n[1:0]\nReset value\n0\n1\n0\n0\n0\n0\n1\n0x0070\nDMA_S4CR\nReserved\nCHSEL[2:0]\nMBURST[1:0]\nPBURST[1:0]\nReserved\nCT\nDBM\nPL[1:0]\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR\n[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0074\nDMA_S4NDTR\nReserved\nNDT[15:.]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0078\nDMA_S4PAR\nPA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x007C\nDMA_S4M0AR\nM0A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0080\nDMA_S4M1AR\nM1A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0084\nDMA_S4FCR\nReserved\nFEIE\nReserved\nFS[2:0]\nDMDIS\nFTH\n[1:0]\nReset value\n0\n1\n0\n0\n0\n0\n1\n0x0088\nDMA_S5CR\nReserved\nCHSEL[2:0]\nMBURST[1:0]\nPBURST[1:0]\nReserved\nCT\nDBM\nPL[1:0]\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x008C\nDMA_S5NDTR\nReserved\nNDT[15:.]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0090\nDMA_S5PAR\nPA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0094\nDMA_S5M0AR\nM0A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0098\nDMA_S5M1AR\nM1A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x009C\nDMA_S5FCR\nReserved\nFEIE\nReserved\nFS[2:0]\nDMDIS\nFTH\n[1:0]\nReset value\n0\n1\n0\n0\n0\n0\n1\n0x00A0\nDMA_S6CR\nReserved\nCHSEL[2:0]\nMBURST[1:0]\nPBURST[1:0]\nReserved\nCT\nDBM\nPL[1:0]\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00A4\nDMA_S6NDTR\nReserved\nNDT[15:.]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00A8\nDMA_S6PAR\nPA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 52. DMA register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 341, "page_indices": { "start_index": 756380, "end_index": 757698 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 341 }, "toc_details": [ [ 1, "10 DMA controller (DMA)", 305 ], [ 2, "10.5 DMA registers", 328 ], [ 3, "10.5.11 DMA register map", 338 ] ], "page_content": "RM0090 Rev 21\n341/1757\nRM0090\nDMA controller (DMA)\n341\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x00AC\nDMA_S6M0AR\nM0A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00B0\nDMA_S6M1AR\nM1A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00B4\nDMA_S6FCR\nReserved\nFEIE\nReserved\nFS[2:0]\nDMDIS\nFTH\n[1:0]\nReset value\n0\n1\n0\n0\n0\n0\n1\n0x00B8\nDMA_S7CR\nReserved\nCHSEL[2:0]\nMBURST[1:0]\nPBURST[1:0]\nReserved\nCT\nDBM\nPL[1:0]\nPINCOS\nMSIZE[1:0]\nPSIZE[1:0]\nMINC\nPINC\nCIRC\nDIR[1:0]\nPFCTRL\nTCIE\nHTIE\nTEIE\nDMEIE\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n-\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00BC\nDMA_S7NDTR\nReserved\nNDT[15:.]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00C0\nDMA_S7PAR\nPA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00C4\nDMA_S7M0AR\nM0A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00C8\nDMA_S7M1AR\nM1A[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00CC\nDMA_S7FCR\nReserved\nFEIE\nReserved\nFS[2:0]\nDMDIS\nFTH\n[1:0]\nReset value\n0\n1\n0\n0\n0\n0\n1\nTable 52. DMA register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 342, "page_indices": { "start_index": 757698, "end_index": 758673 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 342 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.1 DMA2D introduction", 342 ] ], "page_content": "Chrom-Art Accelerator™ controller (DMA2D)\nRM0090\n342/1757\nRM0090 Rev 21\n11 \nChrom-Art Accelerator™ controller (DMA2D)\n11.1 \nDMA2D introduction\nThe Chrom-Art Accelerator™ (DMA2D) is a specialized DMA dedicated to image \nmanipulation. It can perform the following operations:\n•\nFilling a part or the whole of a destination image with a specific color\n•\nCopying a part or the whole of a source image into a part or the whole of a destination \nimage\n•\nCopying a part or the whole of a source image into a part or the whole of a destination \nimage with a pixel format conversion\n•\nBlending a part and/or two complete source images with different pixel format and copy \nthe result into a part or the whole of a destination image with a different color format.\nAll the classical color coding schemes are supported from 4-bit up to 32-bit per pixel with \nindexed or direct color mode. The DMA2D has its own dedicated memories for CLUTs (color \nlook-up tables).\n" }, { "page_number": 343, "page_indices": { "start_index": 758673, "end_index": 760751 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 343 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.2 DMA2D main features", 343 ], [ 2, "11.3 DMA2D functional description", 343 ], [ 3, "11.3.1 General description", 343 ] ], "page_content": "RM0090 Rev 21\n343/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.2 \nDMA2D main features\nThe main DMA2D features are:\n•\nSingle AHB master bus architecture.\n•\nAHB slave programming interface supporting 8/16/32-bit accesses (except for CLUT \naccesses which are 32-bit).\n•\nUser programmable working area size\n•\nUser programmable offset for sources and destination areas\n•\nUser programmable sources and destination addresses on the whole memory space\n•\nUp to 2 sources with blending operation\n•\nAlpha value can be modified (source value, fixed value or modulated value)\n•\nUser programmable source and destination color format\n•\nUp to 11 color formats supported from 4-bit up to 32-bit per pixel with indirect or direct \ncolor coding\n•\n2 internal memories for CLUT storage in indirect color mode\n•\nAutomatic CLUT loading or CLUT programming via the CPU\n•\nUser programmable CLUT size\n•\nInternal timer to control AHB bandwidth\n•\n4 operating modes: register-to-memory, memory-to-memory, memory-to-memory with \npixel format conversion, and memory-to-memory with pixel format conversion and \nblending\n•\nArea filling with a fixed color\n•\nCopy from an area to another\n•\nCopy with pixel format conversion between source and destination images\n•\nCopy from two sources with independent color format and blending\n•\nAbort and suspend of DMA2D operations\n•\nWatermark interrupt on a user programmable destination line\n•\nInterrupt generation on bus error or access conflict\n•\nInterrupt generation on process completion\n11.3 \nDMA2D functional description\n11.3.1 \nGeneral description\nThe DMA2D controller performs direct memory transfer. As an AHB master, it can take the \ncontrol of the AHB bus matrix to initiate AHB transactions.\nThe DMA2D can operate in the following modes: \n•\nRegister-to-memory\n•\nMemory-to-memory\n•\nMemory-to-memory with Pixel Format Conversion\n•\nMemory-to-memory with Pixel Format Conversion and Blending\nThe AHB slave port is used to program the DMA2D controller.\nThe block diagram of the DMA2D is shown in Figure 40: DMA2D block diagram. \n" }, { "page_number": 344, "page_indices": { "start_index": 760751, "end_index": 761775 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 344 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.3 DMA2D functional description", 343 ], [ 3, "11.3.2 DMA2D control", 344 ], [ 3, "11.3.3 DMA2D foreground and background FIFOs", 344 ] ], "page_content": "Chrom-Art Accelerator™ controller (DMA2D)\nRM0090\n344/1757\nRM0090 Rev 21\nFigure 40. DMA2D block diagram\n11.3.2 \nDMA2D control\nThe DMA2D controller is configured through the DMA2D Control Register (DMA2D_CR) \nwhich allows selecting: \nThe user application can perform the following operations:\n•\nSelect the operating mode\n•\nEnable/disable the DMA2D interrupt\n•\nStart/suspend/abort ongoing data transfers\n11.3.3 \nDMA2D foreground and background FIFOs\nThe DMA2D foreground (FG) FG FIFO and background (BG) FIFO fetch the input data to \nbe copied and/or processed.\nThe FIFOs fetch the pixels according to the color format defined in their respective pixel \nformat converter (PFC).\nMS30439V1\nBG PFC\n32\nAHB SLAVE\nAHB MASTER\n256x32-bit\nRAM\nCLUT itf\n256x32-bit\nRAM\nCLUT itf\nExpander\nExpander\n32\nRGB\nα 8\nColor mode\nX\n8-bit α\nα mode\nα 32\nBG\nFIFO\nFG PFC\n32\nExpander\nExpander\n32\nRGB\nα 8\nColor mode\nX\n8-bit α\nα mode\nα 32\nFG\nFIFO\nBLENDER\n32\n32\nα\nRed\nGreen\nBlue\n32\nOUT PFC\nColor mode\nConverter\n32/24/16\nOUT \nFIFO\nColor\n" }, { "page_number": 345, "page_indices": { "start_index": 761775, "end_index": 763370 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 345 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.3 DMA2D functional description", 343 ], [ 3, "11.3.4 DMA2D foreground and background pixel format converter (PFC)", 345 ] ], "page_content": "RM0090 Rev 21\n345/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\nThey are programmed through a set of control registers:\n•\nDMA2D foreground memory address register (DMA2D_FGMAR)\n•\nDMA2D foreground offset register (DMA2D_FGOR)\n•\nDMA2D background memory address register (DMA2D_BGMAR)\n•\nDMA2D background offset register (DMA2D_BGBOR)\n•\nDMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR)\nWhen the DMA2D operates in register-to-memory mode, none of the FIFOs is activated.\nWhen the DMA2D operates in memory-to-memory mode (no pixel format conversion nor \nblending operation), only the FG FIFO is activated and acts as a buffer.\nWhen the DMA2D operates in memory-to-memory operation with pixel format conversion \n(no blending operation), the BG FIFO is not activated.\n11.3.4 \nDMA2D foreground and background pixel format converter (PFC)\nDMA2D foreground pixel format converter (PFC) and background pixel format converter \nperform the pixel format conversion to generate a 32-bit per pixel value. The PFC can also \nmodify the alpha channel.\nThe first stage of the converter converts the color format. The original color format of the \nforeground pixel and background pixels are configured through the CM[3:0] bits of the \nDMA2D_FGPFCCR and DMA2D_BGPFCCR, respectively.\nThe supported input formats are given in Table 53: Supported color mode in input.\n \nTable 53. Supported color mode in input\nCM[3:0]\nColor mode\n0000\nARGB8888\n0001\nRGB888\n0010\nRGB565\n0011\nARGB1555\n0100\nARGB4444\n0101\nL8\n0110\nAL44\n0111\nAL88\n1000\nL4\n1001\nA8\n1010\nA4\n" }, { "page_number": 346, "page_indices": { "start_index": 763370, "end_index": 765567 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 346 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.3 DMA2D functional description", 343 ], [ 3, "11.3.4 DMA2D foreground and background pixel format converter (PFC)", 345 ] ], "page_content": "Chrom-Art Accelerator™ controller (DMA2D)\nRM0090\n346/1757\nRM0090 Rev 21\nThe color format are coded as follows: \n•\nAlpha value field: transparency\n0xFF value corresponds to an opaque pixel and 0x00 to a transparent one. \n•\nR field for Red\n•\nG field for Green\n•\nB field for Blue\n•\nL field: luminance\nThis field is the index to a CLUT to retrieve the three/four RGB/ARGB components.\nIf the original format was direct color mode, then the extension to 8-bit per channel is \nperformed by copying the MSBs into the LSBs. This ensures a perfect linearity of the \nconversion.\nIf the original format does not include an alpha channel, the alpha value is automatically set \nto 0xFF (opaque).\nIf the original format is indirect color mode, a CLUT is required and each pixel format \nconverter is associated with a 256 entry 32-bit CLUT.\nFor the specific alpha mode A4 and A8, no color information is stored nor indexed. The color \nto be used for the image generation is fixed and is defined in the DMA2D_FGCOLR for \nforeground pixels and in the DMA2D_BGCOLR register for background pixels. \nThe order of the fields in the system memory is defined in Table 54: Data order in memory.\n \nThe 24-bit RGB888 aligned on 32-bit is supported through the ARGB8888 mode.\nOnce the 32-bit value is generated, the alpha channel can be modified according to the \nAM[1:0] field of the DMA2D_FGPFCCR/DMA2D_BGPFCCR registers as shown in \nTable 55: Alpha mode configuration.\nTable 54. Data order in memory\nColor Mode\n@ + 3\n@ + 2\n@ + 1\n@ + 0\nARGB8888\nA0[7:0]\nR0[7:0]\nG0[7:0]\nB0[7:0]\nRGB888\nB1[7:0]\nR0[7:0]\nG0[7:0]\nB0[7:0]\nG2[7:0]\nB2[7:0]\nR1[7:0]\nG1[7:0]\nR3[7:0]\nG3[7:0]\nB3[7:0]\nR2[7:0]\nRGB565\nR1[4:0]G1[5:3]\nG1[2:0]B1[4:0]\nR0[4:0]G0[5:3]\nG0[2:0]B0[4:0]\nARGB1555\nA1[0]R1[4:0]G1[4:3]\nG1[2:0]B1[4:0]\nA0[0]R0[4:0]G0[4:3]\nG0[2:0]B0[4:0]\nARGB4444\nA1[3:0]R1[3:0]\nG1[3:0]B1[3:0]\nA0[3:0]R0[3:0]\nG0[3:0]B0[3:0]\nL8\nL3[7:0]\nL2[7:0]\nL1[7:0]\nL0[7:0]\nAL44\nA3[3:0]L3[3:0]\nA2[3:0]L2[3:0]\nA1[3:0]L1[3:0]\nA0[3:0]L0[3:0]\nAL88\nA1[7:0]\nL1[7:0]\nA0[7:0]\nL0[7:0]\nL4\nL7[3:0]L6[3:0]\nL5[3:0]L4[3:0]\nL3[3:0]L2[3:0]\nL1[3:0]L0[3:0]\nA8\nA3[7:0]\nA2[7:0]\nA1[7:0]\nA0[7:0]\nA4\nA7[3:0]A6[3:0]\nA5[3:0]A4[3:0]\nA3[3:0]A2[3:0]\nA1[3:0]A0[3:0]\n" }, { "page_number": 347, "page_indices": { "start_index": 765567, "end_index": 767762 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 347 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.3 DMA2D functional description", 343 ], [ 3, "11.3.5 DMA2D foreground and background CLUT interface", 347 ] ], "page_content": "RM0090 Rev 21\n347/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\nThe alpha channel can be:\n•\nkept as it is (no modification),\n•\nreplaced by the ALPHA[7:0] value of DMA2D_FGPFCCR/DMA2D_BGPFCCR,\n•\nor replaced by the original alpha value multiplied by the ALPHA[7:0] value of \nDMA2D_FGPFCCR/DMA2D_BGPFCCR divided by 255.\n \n11.3.5 \nDMA2D foreground and background CLUT interface\nThe CLUT interface manages the CLUT memory access and the automatic loading of the \nCLUT.\nThree kinds of accesses are possible:\n•\nCLUT read by the PFC during pixel format conversion operation\n•\nCLUT accessed through the AHB slave port when the CPU is reading or writing data \ninto the CLUT\n•\nCLUT written through the AHB master port when an automatic loading of the CLUT is \nperformed\nThe CLUT memory loading can be done in two different ways:\n•\nAutomatic loading\nThe following sequence should be followed to load the CLUT: \na) \nProgram the CLUT address into the DMA2D_FGCMAR register (foreground \nCLUT) or DMA2D_BGCMAR register (background CLUT)\nb) \nProgram the CLUT size in the CS[7:0] field of the DMA2D_FGPFCCR register \n(foreground CLUT) or DMA2D_BGPFCCR register (background CLUT). \nc) \nSet the START bit of the DMA2D_FGPFCCR register (foreground CLUT) or \nDMA2D_BGPFCCR register (background CLUT) to start the transfer. During this \nautomatic loading process, the CLUT is not accessible by the CPU. If a conflict \noccurs, a CLUT access error interrupt is raised assuming CAEIE is set to ‘1’ in \nDMA2D_CR. \n•\nManual loading\nThe application has to program the CLUT manually through the DMA2D AHB slave \nport to which the local CLUT memory is mapped.The foreground CLUT is located at \naddress offset 0x0400 and the background CLUT at address offset 0x0800.\nThe CLUT format can be 24 or 32 bits. It is configured through the CCM bit of the \nDMA2D_FGPFCCR register (foreground CLUT) or DMA2D_BGPFCCR register \n(background CLUT) as shown in Table 56: Supported CLUT color mode.\nTable 55. Alpha mode configuration\nAM[1:0]\nAlpha mode\n00\nNo modification\n01\nReplaced by value in DMA2D_xxPFCCR\n10\nReplaced by original value multiplied by the value in DMA2D_xxPFCCR / 255\n11\nReserved\n" }, { "page_number": 348, "page_indices": { "start_index": 767762, "end_index": 769100 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 348 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.3 DMA2D functional description", 343 ], [ 3, "11.3.6 DMA2D blender", 348 ], [ 3, "11.3.7 DMA2D output PFC", 348 ] ], "page_content": "Chrom-Art Accelerator™ controller (DMA2D)\nRM0090\n348/1757\nRM0090 Rev 21\n \nThe way the CLUT data are organized in the system memory is specified in Table 57: CLUT \ndata order in memory.\n \n11.3.6 \nDMA2D blender\nThe DMA2D blender blends the source pixels by pair to compute the resulting pixel.\nThe blending is performed according to the following equation:\nNo configuration register is required by the blender. The blender usage depends on the \nDMA2D operating mode defined in MODE[1:0] field of the DMA2D_CR register.\n11.3.7 \nDMA2D output PFC\nThe output PFC performs the pixel format conversion from 32 bits to the output format \ndefined in the CM[2:0] field of the DMA2D output pixel format converter configuration \nregister (DMA2D_OPFCCR).\nThe supported output formats are given in Table 58: Supported color mode in output\nTable 56. Supported CLUT color mode\nCCM\nCLUT color mode\n0\n32-bit ARGB8888\n1\n24-bit RGB888\nTable 57. CLUT data order in memory\nCLUT Color Mode\n@ + 3\n@ + 2\n@ + 1\n@ + 0\nARGB8888\nA0[7:0]\nR0[7:0]\nG0[7:0]\nB0[7:0]\nRGB888\nB1[7:0]\nR0[7:0]\nG0[7:0]\nB0[7:0]\nG2[7:0]\nB2[7:0]\nR1[7:0]\nG1[7:0]\nR3[7:0]\nG3[7:0]\nB3[7:0]\nR2[7:0]\nCOUT =\nwith αMult = \nCFG.αFG + CBG.αBG - CBG.αMult\nαOUT\n255\nαFG . αBG\nwith C = R or G or B\nαOUT = αFG + αBG - αMult \nDivision is rounded to the nearest lower integer\n" }, { "page_number": 349, "page_indices": { "start_index": 769100, "end_index": 770874 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 349 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.3 DMA2D functional description", 343 ], [ 3, "11.3.8 DMA2D output FIFO", 349 ], [ 3, "11.3.9 DMA2D AHB master port timer", 349 ] ], "page_content": "RM0090 Rev 21\n349/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n \n11.3.8 \nDMA2D output FIFO\nThe output FIFO programs the pixels according to the color format defined in the output \nPFC.\nThe destination area is defined through a set of control registers: \n•\nDMA2D output memory address register (DMA2D_OMAR)\n•\nDMA2D output offset register (DMA2D_OOR)\n•\nDMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR)\nIf the DMA2D operates in register-to-memory mode, the configured output rectangle is filled \nby the color specified in the DMA2D output color register (DMA2D_OCOLR) which contains \na fixed 32-bit, 24-bit or 16-bit value. The format is selected by the CM[2:0] field of the \nDMA2D_OPFCCR register.\nThe data are stored into the memory in the order defined in Table 59: Data order in memory\n \nThe RGB888 aligned on 32-bit is supported through the ARGB8888 mode.\n11.3.9 \nDMA2D AHB master port timer\nAn 8-bit timer is embedded into the AHB master port to provide an optional limitation of the \nbandwidth on the crossbar.\nThis timer is clocked by the AHB clock and counts a dead time between two consecutive \naccesses. This limits the bandwidth usage.\nTable 58. Supported color mode in output\nCM[2:0]\nColor mode\n000\nARGB8888\n001\nRGB888\n010\nRGB565\n011\nARGB1555\n100\nARGB4444\nTable 59. Data order in memory\nColor Mode\n@ + 3\n@ + 2\n@ + 1\n@ + 0\nARGB8888\nA0[7:0]\nR0[7:0]\nG0[7:0]\nB0[7:0]\nRGB888\nB1[7:0]\nR0[7:0]\nG0[7:0]\nB0[7:0]\nG2[7:0]\nB2[7:0]\nR1[7:0]\nG1[7:0]\nR3[7:0]\nG3[7:0]\nB3[7:0]\nR2[7:0]\nRGB565\nR1[4:0]G1[5:3]\nG1[2:0]B1[4:0]\nR0[4:0]G0[5:3]\nG0[2:0]B0[4:0]\nARGB1555\nA1[0]R1[4:0]G1[4:3]\nG1[2:0]B1[4:0]\nA0[0]R0[4:0]G0[4:3]\nG0[2:0]B0[4:0]\nARGB4444\nA1[3:0]R1[3:0]\nG1[3:0]B1[3:0]\nA0[3:0]R0[3:0]\nG0[3:0]B0[3:0]\n" }, { "page_number": 350, "page_indices": { "start_index": 770874, "end_index": 773140 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 350 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.3 DMA2D functional description", 343 ], [ 3, "11.3.10 DMA2D transactions", 350 ], [ 3, "11.3.11 DMA2D configuration", 350 ], [ 4, "Register-to-memory", 350 ], [ 4, "Memory-to-memory", 350 ] ], "page_content": "Chrom-Art Accelerator™ controller (DMA2D)\nRM0090\n350/1757\nRM0090 Rev 21\nThe timer enabling and the dead time value are configured through the AHB master port \ntimer configuration register (DMA2D_AMPTCR).\n11.3.10 \nDMA2D transactions\nDMA2D transactions consist of a sequence of a given number of data transfers. The \nnumber of data and the width can be programmed by software.\nEach DMA2D data transfer is composed of up to 4 steps: \n1.\nData loading from the memory location pointed by the DMA2D_FGMAR register and \npixel format conversion as defined in DMA2D_FGCR.\n2. \nData loading from a memory location pointed by the DMA2D_BGMAR register and \npixel format conversion as defined in DMA2D_BGCR.\n3. \nBlending of all retrieved pixels according to the alpha channels resulting of the PFC \noperation on alpha values.\n4. \nPixel format conversion of the resulting pixels according to the DMA2D_OCR register \nand programming of the data to the memory location addressed through the \nDMA2D_OMAR register.\n11.3.11 \nDMA2D configuration\nBoth source and destination data transfers can target peripherals and memories in the \nwhole 4 Gbyte memory area, at addresses ranging between 0x0000 0000 and \n0xFFFF FFFF. \nThe DMA2D can operate in any of the four following modes selected through MODE[1:0] \nbits of the DMA2D_CR register:\n•\nRegister-to-memory \n•\nMemory-to-memory \n•\nMemory-to-memory with PFC\n•\nMemory-to-memory with PFC and blending\nRegister-to-memory\nThe register-to-memory mode is used to fill a user defined area with a predefined color.\nThe color format is set in the DMA2D_OPFCCR.\nThe DMA2D does not perform any data fetching from any source. It just writes the color \ndefined in the DMA2D_OCOLR register to the area located at the address pointed by the \nDMA2D_OMAR and defined in the DMA2D_NLR and DMA2D_OOR.\nMemory-to-memory \nIn memory-to-memory mode, the DMA2D does not perform any graphical data \ntransformation. The foreground input FIFO acts as a buffer and the data are transferred \nfrom the source memory location defined in DMA2D_FGMAR to the destination memory \nlocation pointed by DMA2D_OMAR.\nThe color mode programmed in the CM[3:0] bits of the DMA2D_FGPFCCR register defines \nthe number of bits per pixel for both input and output.\n" }, { "page_number": 351, "page_indices": { "start_index": 773140, "end_index": 775910 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 351 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.3 DMA2D functional description", 343 ], [ 3, "11.3.11 DMA2D configuration", 350 ], [ 4, "Memory-to-memory with PFC", 351 ] ], "page_content": "RM0090 Rev 21\n351/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\nThe size of the area to be transferred is defined by the DMA2D_NLR and DMA2D_FGOR \nregisters for the source, and by DMA2D_NLR and DMA2D_OOR registers for the \ndestination.\nMemory-to-memory with PFC \nIn this mode, the DMA2D performs a pixel format conversion of the source data and stores \nthem in the destination memory location.\nThe size of the areas to be transferred are defined by the DMA2D_NLR and DMA2D_FGOR \nregisters for the source, and by DMA2D_NLR and DMA2D_OOR registers for the \ndestination.\nData are fetched from the location defined in the DMA2D_FGMAR register and processed \nby the foreground PFC. The original pixel format is configured through the \nDMA2D_FGPFCCR register.\nIf the original pixel format is direct color mode, then the color channels are all expanded to 8 \nbits. \nIf the pixel format is indirect color mode, the associated CLUT has to be loaded into the \nCLUT memory. \nThe CLUT loading can be done automatically by following the sequence below: \n1.\nSet the CLUT address into the DMA2D_FGCMAR.\n2. \nSet the CLUT size in the CS[7:0] bits of the DMA2D_FGPFCCR register.\n3. \nSet the CLUT format (24 or 32 bits) in the CCM bit of the DMA2D_FGPFCCR register.\n4. \nStart the CLUT loading by setting the START bit of the DMA2D_FGPFCCR register. \nOnce the CLUT loading is complete, the CTCIF flag of the DMA2D_IFR register is raised, \nand an interrupt is generated if the CTCIE bit is set in DMA2D_CR. The automatic CLUT \nloading process can not work in parallel with classical DMA2D transfers.\nThe CLUT can also be filled by the CPU or by any other master through the APB port. The \naccess to the CLUT is not possible when a DMA2D transfer is ongoing and uses the CLUT \n(indirect color format).\nIn parallel to the color conversion process, the alpha value can be added or changed \ndepending on the value programmed in the DMA2D_FGPFCCR register. If the original \nimage does not have an alpha channel, a default alpha value of 0xFF is automatically added \nto obtain a fully opaque pixel. The alpha value can be modified according to the AM[1:0] bits \nof the DMA2D_FGPFCCR register:\n•\nIt can be unchanged.\n•\nIt can be replaced by the value defined in the ALPHA[7:0] value of the \nDMA2D_FGPFCCR register.\n•\nIt can be replaced by the original value multiplied by the ALPHA[7:0] value of the \nDMA2D_FGPFCCR register divided by 255.\nThe resulting 32-bit data are encoded by the OUT PFC into the format specified by the \nCM[2:0] field of the DMA2D_OPFCCR register. The output pixel format cannot be the \nindirect mode since no CLUT generation process is supported. \nThe processed data are written into the destination memory location pointed by \nDMA2D_OMAR.\n" }, { "page_number": 352, "page_indices": { "start_index": 775910, "end_index": 777207 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 352 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.3 DMA2D functional description", 343 ], [ 3, "11.3.11 DMA2D configuration", 350 ], [ 4, "Memory-to-memory with PFC and blending", 352 ], [ 4, "Configuration error detection", 352 ] ], "page_content": "Chrom-Art Accelerator™ controller (DMA2D)\nRM0090\n352/1757\nRM0090 Rev 21\nMemory-to-memory with PFC and blending\nIn this mode, 2 sources are fetched in the foreground FIFO and background FIFO from the \nmemory locations defined by DMA2D_FGMAR and DMA2D_BGMAR.\nThe two pixel format converters have to be configured as described in the memory-to-\nmemory mode. Their configurations can be different as each pixel format converter are \nindependent and have their own CLUT memory.\nOnce each pixel has been converted into 32 bits by their respective PFCs, they are blended \naccording to the equation below:\nThe resulting 32-bit pixel value is encoded by the output PFC according to the specified \noutput format, and the data are written into the destination memory location pointed by \nDMA2D_OMAR.\nConfiguration error detection\nThe DMA2D checks that the configuration is correct before any transfer. The configuration \nerror interrupt flag is set by hardware when a wrong configuration is detected when a new \ntransfer/automatic loading starts. An interrupt is then generated if the CEIE bit of the \nDMA2D_CR is set.\nCOUT =\nwith αMult = \nCFG.αFG + CBG.αBG - CBG.αMult\nαOUT\n255\nαFG . αBG\nwith C = R or G or B\nαOUT = αFG + αBG - αMult \nDivision are rounded to the nearest lower integer\n" }, { "page_number": 353, "page_indices": { "start_index": 777207, "end_index": 779629 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 353 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.3 DMA2D functional description", 343 ], [ 3, "11.3.12 DMA2D transfer control (start, suspend, abort and completion)", 353 ] ], "page_content": "RM0090 Rev 21\n353/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\nThe wrong configurations that can be detected are listed below:\n•\nForeground CLUT automatic loading: MA bits of DMA2D_FGCMAR not aligned with \nCCM of DMA2D_FGPFCCR.\n•\nBackground CLUT automatic loading: MA of DMA2D_BGCMAR not aligned with CCM \nof DMA2D_BGPFCCR\n•\nMemory transfer (except in register-to-memory mode): MA of DMA2D_FGMAR not \naligned with CM of DMA2D_FGPFCCR\n•\nMemory transfer (except in register-to-memory mode): CM in DMA2D_FGPFCCR are \ninvalid \n•\nMemory transfer (except in register-to-memory mode): PL bits of DMA2D_NLR odd \nwhile CM of DMA2D_FGPFCCR is A4 or L4 \n•\nMemory transfer (except in register-to-memory mode): LO bits in DMA2D_FGOR odd \nwhile CM of DMA2D_FGPFCCR is A4 or L4\n•\nMemory transfer (only in blending mode): MA bits in DMA2D_BGMAR are not aligned \nwith the CM of DMA2D_BGPFCCR \n•\nMemory transfer: CM of DMA2D_BGPFCCR invalid (only in blending mode)\n•\nMemory transfer (only in blending mode): PL bits of DMA2D_NLR odd while CM of \nDMA2D_BGPFCCR is A4 or L4 \n•\nMemory transfer (only in blending mode): LO bits of DMA2D_BGOR odd while CM of \nDMA2D_BGPFCCR is A4 or L4 \n•\nMemory transfer (except in memory to memory mode): MA bits in DMA2D_OMAR are \nnot aligned with CM bits in DMA2D_OPFCCR.\n•\nMemory transfer (except in memory to memory mode): CM bits in DMA2D_OPFCCR \ninvalid \n•\nMemory transfer: NL bits in DMA2D_NLR = 0 \n•\nMemory transfer: PL bits in DMA2D_NLR = 0\n11.3.12 \nDMA2D transfer control (start, suspend, abort and completion)\nOnce the DMA2D is configured, the transfer can be launched by setting the START bit of the \nDMA2D_CR register. Once the transfer is completed, the START bit is automatically reset \nand the TCIF flag of the DMA2D_ISR register is raised. An interrupt can be generated if the \nTCIE bit of the DMA2D_CR is set.\nThe user application can suspend the DMA2D at any time by setting the SUSP bit of the \nDMA2D_CR register. The transaction can then be aborted by setting the ABORT bit of the \nDMA2D_CR register or can be restarted by resetting the SUSP bit of the DMA2D_CR \nregister.\nThe user application can abort at any time an ongoing transaction by setting the ABORT bit \nof the DMA2D_CR register. In this case, the TCIF flag is not raised.\nAutomatic CLUT transfers can also be aborted or suspended by using the ABORT or the \nSUSP bit of the DMA2D_CR register.\n" }, { "page_number": 354, "page_indices": { "start_index": 779629, "end_index": 781538 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 354 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.3 DMA2D functional description", 343 ], [ 3, "11.3.13 Watermark", 354 ], [ 3, "11.3.14 Error management", 354 ], [ 3, "11.3.15 AHB dead time", 354 ], [ 2, "11.4 DMA2D interrupts", 354 ] ], "page_content": "Chrom-Art Accelerator™ controller (DMA2D)\nRM0090\n354/1757\nRM0090 Rev 21\n11.3.13 \nWatermark\nA watermark can be programmed to generate an interrupt when the last pixel of a given line \nhas been written to the destination memory area.\nThe line number is defined in the LW[15:0] field of the DMA2D_LWR register.\nWhen the last pixel of this line has been transferred, the TWIF flag of the DMA2D_ISR \nregister is raised and an interrupt is generated if the TWIE bit of the DMA2D_CR is set.\n11.3.14 \nError management\nTwo kind of errors can be triggered:\n•\nAHB master port errors signalled by the TEIF flag of the DMA2D_ISR register.\n•\nConflicts caused by CLUT access (CPU trying to access the CLUT while a CLUT \nloading or a DMA2D transfer is ongoing) signalled by the CAEIF flag of the \nDMA2D_ISR register.\nBoth flags are associated to their own interrupt enable flag in the DMA2D_CR register to \ngenerate an interrupt if need be (TEIE and CAEIE).\n11.3.15 \nAHB dead time\nTo limit the AHB bandwidth usage, a dead time between two consecutive AHB accesses \ncan be programmed. \nThis feature can be enabled by setting the EN bit in the DMA2D_AMTCR register.\nThe dead time value is stored in the DT[7:0] field of the DMA2D_AMTCR register. This \nvalue represents the guaranteed minimum number of cycles between two consecutive \ntransactions on the AHB bus.\nThe update of the dead time value while the DMA2D is running is taken into account for the \nnext AHB transfer.\n11.4 \nDMA2D interrupts\nAn interrupt can be generated on the following events: \n•\nConfiguration error\n•\nCLUT transfer complete\n•\nCLUT access error\n•\nTransfer watermark reached \n•\nTransfer complete\n•\nTransfer error\nSeparate interrupt enable bits are available for flexibility.\n \nTable 60. DMA2D interrupt requests\nInterrupt event\nEvent flag\nEnable control bit\nConfiguration error\nCEIF\nCEIE\nCLUT transfer complete\nCTCIF\nCTCIE\n" }, { "page_number": 355, "page_indices": { "start_index": 781538, "end_index": 783036 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 355 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.1 DMA2D control register (DMA2D_CR)", 355 ] ], "page_content": "RM0090 Rev 21\n355/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.5 \nDMA2D registers\n11.5.1 \nDMA2D control register (DMA2D_CR)\nAddress offset: 0x0000\nReset value: 0x0000 0000\n \nCLUT access error\nCAEIF\nCAEIE\nTransfer watermark\nTWF\nTWIE\nTransfer complete\nTCIF\nTCIE\nTransfer error\nTEIF\nTEIE\nTable 60. DMA2D interrupt requests (continued)\nInterrupt event\nEvent flag\nEnable control bit\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nMODE\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCEIE\nCTCIE CAEIE\nTWIE\nTCIE\nTEIE\nReserved\nABORT\nSUSP\nSTART\nrw\nrw\nrw\nrw\nrw\nrw\nrs\nrw\nrs\nBits 31:18 Reserved, must be kept at reset value\nBits 17:16 MODE: DMA2D mode\nThis bit is set and cleared by software. It cannot be modified while a transfer is ongoing.\n00: Memory-to-memory (FG fetch only)\n01: Memory-to-memory with PFC (FG fetch only with FG PFC active)\n10: Memory-to-memory with blending (FG and BG fetch with PFC and blending)\n11: Register-to-memory (no FG nor BG, only output stage active)\nBits 15:14 Reserved, must be kept at reset value\nBit 13 CEIE: Configuration Error Interrupt Enable\nThis bit is set and cleared by software.\n0: CE interrupt disable\n1: CE interrupt enable\nBit 12 CTCIE: CLUT transfer complete interrupt enable\nThis bit is set and cleared by software.\n0: CTC interrupt disable\n1: CTC interrupt enable\nBit 11 CAEIE: CLUT access error interrupt enable\nThis bit is set and cleared by software.\n0: CAE interrupt disable\n1: CAE interrupt enable\n" }, { "page_number": 356, "page_indices": { "start_index": 783036, "end_index": 784537 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 356 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.1 DMA2D control register (DMA2D_CR)", 355 ] ], "page_content": "Chrom-Art Accelerator™ controller (DMA2D)\nRM0090\n356/1757\nRM0090 Rev 21\nBit 10 TWIE: Transfer watermark interrupt enable\nThis bit is set and cleared by software.\n0: TW interrupt disable\n1: TW interrupt enable\nBit 9 TCIE: Transfer complete interrupt enable\nThis bit is set and cleared by software.\n0: TC interrupt disable\n1: TC interrupt enable\nBit 8 TEIE: Transfer error interrupt enable\nThis bit is set and cleared by software.\n0: TE interrupt disable\n1: TE interrupt enable\nBits 7:3 Reserved, must be kept at reset value\nBit 2 ABORT: Abort\nThis bit can be used to abort the current transfer. This bit is set by software and is \nautomatically reset by hardware when the START bit is reset.\n0: No transfer abort requested\n1: Transfer abort requested\nBit 1 SUSP: Suspend\nThis bit can be used to suspend the current transfer. This bit is set and reset by \nsoftware. It is automatically reset by hardware when the START bit is reset.\n0: Transfer not suspended\n1: Transfer suspended\nBit 0 START: Start\nThis bit can be used to launch the DMA2D according to the parameters loaded in the \nvarious configuration registers. This bit is automatically reset by the following events:\n–\nAt the end of the transfer \n–\nWhen the data transfer is aborted by the user application by setting the ABORT \nbit in DMA2D_CR\n–\nWhen a data transfer error occurs\n–\nWhen the data transfer has not started due to a configuration error or another \ntransfer operation already ongoing (automatic CLUT loading).\n" }, { "page_number": 357, "page_indices": { "start_index": 784537, "end_index": 785859 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 357 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.2 DMA2D Interrupt Status Register (DMA2D_ISR)", 357 ] ], "page_content": "RM0090 Rev 21\n357/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.5.2 \nDMA2D Interrupt Status Register (DMA2D_ISR)\nAddress offset: 0x0004\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCEIF\nCTCIF\nCAEIF\nTWIF\nTCIF\nTEIF\nr\nr\nr\nr\nr\nr\nBits 31:6 Reserved, must be kept at reset value\nBit 5 CEIF: Configuration error interrupt flag\nThis bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or \nDMA2D_BGPFCCR is set and a wrong configuration has been programmed.\nBit 4 CTCIF: CLUT transfer complete interrupt flag\nThis bit is set when the CLUT copy from a system memory area to the internal DMA2D \nmemory is complete.\nBit 3 CAEIF: CLUT access error interrupt flag\nThis bit is set when the CPU accesses the CLUT while the CLUT is being automatically \ncopied from a system memory to the internal DMA2D.\nBit 2 TWIF: Transfer watermark interrupt flag\nThis bit is set when the last pixel of the watermarked line has been transferred.\nBit 1 TCIF: Transfer complete interrupt flag\nThis bit is set when a DMA2D transfer operation is complete (data transfer only).\nBit 0 TEIF: Transfer error interrupt flag\nThis bit is set when an error occurs during a DMA transfer (data transfer or automatic \nCLUT loading).\n" }, { "page_number": 358, "page_indices": { "start_index": 785859, "end_index": 787053 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 358 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.3 DMA2D interrupt flag clear register (DMA2D_IFCR)", 358 ] ], "page_content": "Chrom-Art Accelerator™ controller (DMA2D)\nRM0090\n358/1757\nRM0090 Rev 21\n11.5.3 \nDMA2D interrupt flag clear register (DMA2D_IFCR)\nAddress offset: 0x0008\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCCEIF\nCCTCIF CAECIF\nCTWIF\nCTCIF\nCTEIF\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nBits 31:6 Reserved, must be kept at reset value\nBit 5 CCEIF: Clear configuration error interrupt flag\nProgramming this bit to 1 clears the CEIF flag in the DMA2D_ISR register\nBit 4 CCTCIF: Clear CLUT transfer complete interrupt flag\nProgramming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register\nBit 3 CAECIF: Clear CLUT access error interrupt flag\nProgramming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register\nBit 2 CTWIF: Clear transfer watermark interrupt flag\nProgramming this bit to 1 clears the TWIF flag in the DMA2D_ISR register\nBit 1 CTCIF: Clear transfer complete interrupt flag\nProgramming this bit to 1 clears the TCIF flag in the DMA2D_ISR register\nBit 0 CTEIF: Clear Transfer error interrupt flag\nProgramming this bit to 1 clears the TEIF flag in the DMA2D_ISR register\n" }, { "page_number": 359, "page_indices": { "start_index": 787053, "end_index": 788643 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 359 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.4 DMA2D foreground memory address register (DMA2D_FGMAR)", 359 ], [ 3, "11.5.5 DMA2D foreground offset register (DMA2D_FGOR)", 359 ] ], "page_content": "RM0090 Rev 21\n359/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.5.4 \nDMA2D foreground memory address register (DMA2D_FGMAR)\nAddress offset: 0x000C\nReset value: 0x0000 0000\n \n11.5.5 \nDMA2D foreground offset register (DMA2D_FGOR)\nAddress offset: 0x0010\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMA[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMA[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 MA[31: 0]: Memory address\nAddress of the data used for the foreground image. This register can only be written \nwhen data transfers are disabled. Once the data transfer has started, this register is \nread-only.\nThe address alignment must match the image format selected e.g. a 32-bit per pixel \nformat must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-\nbit per pixel format must be 8-bit aligned.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLO[13:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:14 Reserved, must be kept at reset value\nBits 13:0 LO[13: 0]: Line offset\nLine offset used for the foreground expressed in pixel. This value is used to generate \nthe address. It is added at the end of each line to determine the starting address of the \nnext line.\nThese bits can only be written when data transfers are disabled. Once a data transfer \nhas started, they become read-only.\nIf the image format is 4-bit per pixel, the line offset must be even.\n" }, { "page_number": 360, "page_indices": { "start_index": 788643, "end_index": 790237 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 360 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.6 DMA2D background memory address register (DMA2D_BGMAR)", 360 ], [ 3, "11.5.7 DMA2D background offset register (DMA2D_BGOR)", 360 ] ], "page_content": "Chrom-Art Accelerator™ controller (DMA2D)\nRM0090\n360/1757\nRM0090 Rev 21\n11.5.6 \nDMA2D background memory address register (DMA2D_BGMAR)\nAddress offset: 0x0014\nReset value: 0x0000 0000\n \n11.5.7 \nDMA2D background offset register (DMA2D_BGOR)\nAddress offset: 0x0018\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMA[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMA[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31: 0 MA[31: 0]: Memory address\nAddress of the data used for the background image. This register can only be written \nwhen data transfers are disabled. Once a data transfer has started, this register is read-\nonly.\nThe address alignment must match the image format selected e.g. a 32-bit per pixel \nformat must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-\nbit per pixel format must be 8-bit aligned.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLO[13:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:14 Reserved, must be kept at reset value\nBits 13:0 LO[13: 0]: Line offset\nLine offset used for the background image (expressed in pixel). This value is used for \nthe address generation. It is added at the end of each line to determine the starting \naddress of the next line.\nThese bits can only be written when data transfers are disabled. Once data transfer has \nstarted, they become read-only.\nIf the image format is 4-bit per pixel, the line offset must be even.\n" }, { "page_number": 361, "page_indices": { "start_index": 790237, "end_index": 791867 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 361 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR)", 361 ] ], "page_content": "RM0090 Rev 21\n361/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.5.8 \nDMA2D foreground PFC control register (DMA2D_FGPFCCR)\nAddress offset: 0x001C\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nALPHA[7:0]\nReserved\nAM[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCS[7:0]\nReserved\nSTART\nCCM\nCM[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrs\nrw\nrw\nrw\nrw\nrw\nBits 31:24 ALPHA[7: 0]: Alpha value\nThese bits define a fixed alpha channel value which can replace the original alpha value \nor be multiplied by the original alpha value according to the alpha mode selected \nthrough the AM[1:0] bits. \nThese bits can only be written when data transfers are disabled. Once a transfer has \nstarted, they become read-only.\nBits 23:18 Reserved, must be kept at reset value\nBits 17:16 AM[1: 0]: Alpha mode\nThese bits select the alpha channel value to be used for the foreground image. They \ncan only be written data the transfer are disabled. Once the transfer has started, they \nbecome read-only.\n00: No modification of the foreground image alpha channel value\n01: Replace original foreground image alpha channel value by ALPHA[7: 0]\n10: Replace original foreground image alpha channel value by ALPHA[7:0] multiplied \nwith original alpha channel value\nother configurations are meaningless\nBits 15:8 CS[7: 0]: CLUT size\nThese bits define the size of the CLUT used for the foreground image. Once the CLUT \ntransfer has started, this field is read-only.\nThe number of CLUT entries is equal to CS[7:0] + 1.\nBits 7:6 Reserved, must be kept at reset value\n" }, { "page_number": 362, "page_indices": { "start_index": 791867, "end_index": 792974 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 362 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR)", 361 ] ], "page_content": "Chrom-Art Accelerator™ controller (DMA2D)\nRM0090\n362/1757\nRM0090 Rev 21\nBit 5 START: Start\nThis bit can be set to start the automatic loading of the CLUT. It is automatically reset:\n–\nat the end of the transfer \n–\nwhen the transfer is aborted by the user application by setting the ABORT bit in \nDMA2D_CR\n–\nwhen a transfer error occurs\n–\nwhen the transfer has not started due to a configuration error or another \ntransfer operation already ongoing (data transfer or automatic background \nCLUT transfer).\nBit 4 CCM: CLUT color mode\nThis bit defines the color format of the CLUT. It can only be written when the transfer is \ndisabled. Once the CLUT transfer has started, this bit is read-only.\n0: ARGB8888\n1: RGB888\nothers: meaningless\nBits 3:0 CM[3: 0]: Color mode\nThese bits defines the color format of the foreground image. They can only be written \nwhen data transfers are disabled. Once the transfer has started, they are read-only.\n0000: ARGB8888\n0001: RGB888\n0010: RGB565\n0011: ARGB1555\n0100: ARGB4444\n0101: L8\n0110: AL44\n0111: AL88\n1000: L4\n1001: A8\n1010: A4\nothers: meaningless\n" }, { "page_number": 363, "page_indices": { "start_index": 792974, "end_index": 794109 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 363 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.9 DMA2D foreground color register (DMA2D_FGCOLR)", 363 ] ], "page_content": "RM0090 Rev 21\n363/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.5.9 \nDMA2D foreground color register (DMA2D_FGCOLR)\nAddress offset: 0x0020\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nRED[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nGREEN[7:0]\nBLUE[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value\nBits 23:16 RED[7: 0]: Red Value\nThese bits defines the red value for the A4 or A8 mode of the foreground image. They \ncan only be written when data transfers are disabled. Once the transfer has started, \nthey are read-only.\nBits 15:8 GREEN[7: 0]: Green Value\nThese bits defines the green value for the A4 or A8 mode of the foreground image. They \ncan only be written when data transfers are disabled. Once the transfer has started, \nThey are read-only.\nBits 7:0 BLUE[7: 0]: Blue Value\nThese bits defines the blue value for the A4 or A8 mode of the foreground image. They \ncan only be written when data transfers are disabled. Once the transfer has started, \nThey are read-only.\n" }, { "page_number": 364, "page_indices": { "start_index": 794109, "end_index": 795695 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 364 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR)", 364 ] ], "page_content": "Chrom-Art Accelerator™ controller (DMA2D)\nRM0090\n364/1757\nRM0090 Rev 21\n11.5.10 \nDMA2D background PFC control register (DMA2D_BGPFCCR)\nAddress offset: 0x0024\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nALPHA[7:0]\nReserved\nAM[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCS[7:0]\nReserved\nSTART\nCCM\nCM[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrs\nrw\nrw\nrw\nrw\nrw\nBits 31:24 ALPHA[7: 0]: Alpha value\nThese bits define a fixed alpha channel value which can replace the original alpha value \nor be multiplied with the original alpha value according to the alpha mode selected with \nbits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the \ntransfer has started, they are read-only.\nBits 23:18 Reserved, must be kept at reset value\nBits 17:16 AM[1: 0]: Alpha mode\nThese bits define which alpha channel value to be used for the background image. \nThese bits can only be written when data transfers are disabled. Once the transfer has \nstarted, they are read-only.\n00: No modification of the foreground image alpha channel value\n01: Replace original background image alpha channel value by ALPHA[7: 0]\n10: Replace original background image alpha channel value by ALPHA[7:0] multiplied \nwith original alpha channel value\nothers: meaningless\nBits 15:8 CS[7: 0]: CLUT size\nThese bits define the size of the CLUT used for the BG. Once the CLUT transfer has \nstarted, this field is read-only.\nThe number of CLUT entries is equal to CS[7:0] + 1.\nBits 7:6 Reserved, must be kept at reset value\n" }, { "page_number": 365, "page_indices": { "start_index": 795695, "end_index": 796831 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 365 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR)", 364 ] ], "page_content": "RM0090 Rev 21\n365/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\nBit 5 START: Start\nThis bit is set to start the automatic loading of the CLUT. This bit is automatically reset:\n–\nat the end of the transfer \n–\nwhen the transfer is aborted by the user application by setting the ABORT bit in \nthe DMA2D_CR\n–\nwhen a transfer error occurs\n–\nwhen the transfer has not started due to a configuration error or another \ntransfer operation already on going (data transfer or automatic foreground \nCLUT transfer).\nBit 4 CCM: CLUT Color mode\nThese bits define the color format of the CLUT. This register can only be written when \nthe transfer is disabled. Once the CLUT transfer has started, this bit is read-only.\n0: ARGB8888\n1: RGB888\nothers: meaningless\nBits 3:0 CM[3: 0]: Color mode\nThese bits define the color format of the foreground image. These bits can only be \nwritten when data transfers are disabled. Once the transfer has started, they are read-\nonly.\n0000: ARGB8888\n0001: RGB888\n0010: RGB565\n0011: ARGB1555\n0100: ARGB4444\n0101: L8\n0110: AL44\n0111: AL88\n1000: L4\n1001: A8\n1010: A4\nothers: meaningless\n" }, { "page_number": 366, "page_indices": { "start_index": 796831, "end_index": 798613 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 366 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.11 DMA2D background color register (DMA2D_BGCOLR)", 366 ], [ 3, "11.5.12 DMA2D foreground CLUT memory address register (DMA2D_FGCMAR)", 366 ] ], "page_content": "Chrom-Art Accelerator™ controller (DMA2D)\nRM0090\n366/1757\nRM0090 Rev 21\n11.5.11 \nDMA2D background color register (DMA2D_BGCOLR)\nAddress offset: 0x0028\nReset value: 0x0000 0000\n \n11.5.12 \nDMA2D foreground CLUT memory address register\n(DMA2D_FGCMAR)\nAddress offset: 0x002C\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nRED[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nGREEN[7:0]\nBLUE[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value\nBits 23:16 RED[7: 0]: Red Value\nThese bits define the red value for the A4 or A8 mode of the background. These bits \ncan only be written when data transfers are disabled. Once the transfer has started, \nthey are read-only.\nBits 15:8 GREEN[7: 0]: Green Value\nThese bits define the green value for the A4 or A8 mode of the background. These bits \ncan only be written when data transfers are disabled. Once the transfer has started, \nthey are read-only.\nBits 7:0 BLUE[7: 0]: Blue Value\nThese bits define the blue value for the A4 or A8 mode of the background. These bits \ncan only be written when data transfers are disabled. Once the transfer has started, \nthey are read-only.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMA[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMA[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31: 0 MA[31: 0]: Memory Address\nAddress of the data used for the CLUT address dedicated to the foreground image. This \nregister can only be written when no transfer is ongoing. Once the CLUT transfer has \nstarted, this register is read-only.\nIf the foreground CLUT format is 32-bit, the address must be 32-bit aligned.\n" }, { "page_number": 367, "page_indices": { "start_index": 798613, "end_index": 799941 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 367 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.13 DMA2D background CLUT memory address register (DMA2D_BGCMAR)", 367 ], [ 3, "11.5.14 DMA2D output PFC control register (DMA2D_OPFCCR)", 367 ] ], "page_content": "RM0090 Rev 21\n367/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.5.13 \nDMA2D background CLUT memory address register\n(DMA2D_BGCMAR)\nAddress offset: 0x0030\nReset value: 0x0000 0000\n \n11.5.14 \nDMA2D output PFC control register (DMA2D_OPFCCR)\nAddress offset: 0x0034\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMA[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMA[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31: 0 MA[31: 0]: Memory address\nAddress of the data used for the CLUT address dedicated to the background image. \nThis register can only be written when no transfer is on going. Once the CLUT transfer \nhas started, this register is read-only.\nIf the background CLUT format is 32-bit, the address must be 32-bit aligned.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCM[2:0]\nrw\nrw\nrw\nBits 31: 3 Reserved, must be kept at reset value\nBits 2: 0 CM[2: 0]: Color mode\nThese bits define the color format of the output image. These bits can only be written \nwhen data transfers are disabled. Once the transfer has started, they are read-only.\n000: ARGB8888\n001: RGB888\n010: RGB565\n011: ARGB1555\n100: ARGB4444\nothers: meaningless\n" }, { "page_number": 368, "page_indices": { "start_index": 799941, "end_index": 801300 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 368 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.15 DMA2D output color register (DMA2D_OCOLR)", 368 ] ], "page_content": "Chrom-Art Accelerator™ controller (DMA2D)\nRM0090\n368/1757\nRM0090 Rev 21\n11.5.15 \nDMA2D output color register (DMA2D_OCOLR)\nAddress offset: 0x0038\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nALPHA[7:0]\nRED[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nGREEN[7:0]\nBLUE[7:0]\nRED[4:0]\nGREEN[5:0]\nBLUE[4:0]\nA\nRED[4:0]\nGREEN[4:0]\nBLUE[4:0]\nALPHA[3:0]\nRED[3:0]\nGREEN[3:0]\nBLUE[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 ALPHA[7: 0]: Alpha Channel Value\nThese bits define the alpha channel of the output color. These bits can only be written \nwhen data transfers are disabled. Once the transfer has started, they are read-only.\nBits 23:16 RED[7: 0]: Red Value\nThese bits define the red value of the output image. These bits can only be written when \ndata transfers are disabled. Once the transfer has started, they are read-only.\nBits 15:8 GREEN[7: 0]: Green Value\nThese bits define the green value of the output image. These bits can only be written \nwhen data transfers are disabled. Once the transfer has started, they are read-only.\nBits 7:0 BLUE[7: 0]: Blue Value\nThese bits define the blue value of the output image. These bits can only be written \nwhen data transfers are disabled. Once the transfer has started, they are read-only.\n" }, { "page_number": 369, "page_indices": { "start_index": 801300, "end_index": 802084 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 369 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.16 DMA2D output memory address register (DMA2D_OMAR)", 369 ] ], "page_content": "RM0090 Rev 21\n369/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.5.16 \nDMA2D output memory address register (DMA2D_OMAR)\nAddress offset: 0x003C\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMA[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMA[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31: 0 MA[31: 0]: Memory Address\nAddress of the data used for the output FIFO. These bits can only be written when data \ntransfers are disabled. Once the transfer has started, they are read-only.\nThe address alignment must match the image format selected e.g. a 32-bit per pixel \nformat must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned.\n" }, { "page_number": 370, "page_indices": { "start_index": 802084, "end_index": 803690 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 370 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.17 DMA2D output offset register (DMA2D_OOR)", 370 ], [ 3, "11.5.18 DMA2D number of line register (DMA2D_NLR)", 370 ] ], "page_content": "Chrom-Art Accelerator™ controller (DMA2D)\nRM0090\n370/1757\nRM0090 Rev 21\n11.5.17 \nDMA2D output offset register (DMA2D_OOR)\nAddress offset: 0x0040\nReset value: 0x0000 0000\n \n11.5.18 \nDMA2D number of line register (DMA2D_NLR)\nAddress offset: 0x0044\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLO[13:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:14 Reserved, must be kept at reset value\nBits 13:0 LO[13: 0]: Line Offset\nLine offset used for the output (expressed in pixels). This value is used for the address \ngeneration. It is added at the end of each line to determine the starting address of the \nnext line. These bits can only be written when data transfers are disabled. Once the \ntransfer has started, they are read-only.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPL[13:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nNL[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value\nBits 29:16 PL[13: 0]: Pixel per lines\nNumber of pixels per lines of the area to be transferred. These bits can only be written \nwhen data transfers are disabled. Once the transfer has started, they are read-only.\nIf any of the input image format is 4-bit per pixel, pixel per lines must be even.\nBits 15:0 NL[15: 0]: Number of lines\nNumber of lines of the area to be transferred. These bits can only be written when data \ntransfers are disabled. Once the transfer has started, they are read-only.\n" }, { "page_number": 371, "page_indices": { "start_index": 803690, "end_index": 805014 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 371 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.19 DMA2D line watermark register (DMA2D_LWR)", 371 ], [ 3, "11.5.20 DMA2D AHB master timer configuration register (DMA2D_AMTCR)", 371 ] ], "page_content": "RM0090 Rev 21\n371/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n11.5.19 \nDMA2D line watermark register (DMA2D_LWR)\nAddress offset: 0x0048\nReset value: 0x0000 0000\n \n11.5.20 \nDMA2D AHB master timer configuration register (DMA2D_AMTCR)\nAddress offset: 0x004C\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nLW[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value\nBits 15:0 LW[15:0]: Line watermark \nThese bits allow to configure the line watermark for interrupt generation. \nAn interrupt is raised when the last pixel of the watermarked line has been transferred. \nThese bits can only be written when data transfers are disabled. Once the transfer has \nstarted, they are read-only.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDT[7:0]\nReserved\nEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved\nBits 15:8 DT[7: 0]: Dead Time\nDead time value in the AHB clock cycle inserted between two consecutive accesses on \nthe AHB master port. These bits represent the minimum guaranteed number of cycles \nbetween two consecutive AHB accesses.\nBits 7:1 Reserved\nBit 0 EN: Enable\nEnables the dead time functionality.\n" }, { "page_number": 372, "page_indices": { "start_index": 805014, "end_index": 807270 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 372 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.21 DMA2D register map", 372 ] ], "page_content": "Chrom-Art Accelerator™ controller (DMA2D)\nRM0090\n372/1757\nRM0090 Rev 21\n11.5.21 \nDMA2D register map\nThe following table summarizes the DMA2D registers. Refer to Section 2.3: Memory map \nfor the DMA2D register base address.\n \nTable 61. DMA2D register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x0000\nDMA2D_CR\nReserved\nMODE[1:0]\nReserved\nCEIE\nCTCIE\nCAEIE\nTWIE\nTCIE\nTEIE\nReserved\nABORT\nSUSP\nSTART\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0004\nDMA2D_ISR\nReserved\nCEIF\nCTCIF\nCAEIF\nTWIF\nTCIF\nTEIF\nReset value\n0\n0\n0\n0\n0\n0\n0x0008\nDMA2D_IFCR\nReserved\nCCEIF\nCCTCIF\nCAECIF\nCTWIF\nCTCIF\nCTEIF\nReset value\n0\n0\n0\n0\n0\n0\n0x000C\nDMA2D_FGMAR\nMA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0010\nDMA2D_FGOR\nReserved\nLO[13:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0014\nDMA2D_BGMAR\nMA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0018\nDMA2D_BGOR\nReserved\nLO[13:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x001C\nDMA2D_FGPFCCR\nALPHA[7:0]\nReserved\nAM[1:0]\nCS[7:0]\nRes\nSTART\nCCM\nCM[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0020\nDMA2D_FGCOLR\nAPLHA[7:0]\nRED[7:0]\nGREEN[7:0]\nBLUE[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0024\nDMA2D_BGPFCCR\nALPHA[7:0]\nReserved\nAM[1:0]\nCS[7:0]\nRes\nSTART\nCCM\nCM[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0028\nDMA2D_BGCOLR\nAPLHA[7:0]\nRED[7:0]\nGREEN[7:0]\nBLUE[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x002C\nDMA2D_FGCMAR\nMA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0030\nDMA2D_BGCMAR\nMA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0034\nDMA2D_OPFCCR\nReserved\nCM[2:0]\nReset value\n0\n0\n0\n0x0038\nDMA2D_OCOLR\nAPLHA[7:0]\nRED[7:0]\nGREEN[7:0]\nBLUE[7:0]\nReserved\nRED[4:0]\nGREEN[6:0]\nBLUE[4:0]\nReserved\nA\nRED[4:0]\nGREEN[4:0]\nBLUE[4:0]\nReserved\nALPHA[3:0]\nRED[3:0]\nGREEN[3:0]\nBLUE[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x003C\nDMA2D_OMAR\nMA[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n" }, { "page_number": 373, "page_indices": { "start_index": 807270, "end_index": 808243 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 373 }, "toc_details": [ [ 1, "11 Chrom-Art Accelerator™ controller (DMA2D)", 342 ], [ 2, "11.5 DMA2D registers", 355 ], [ 3, "11.5.21 DMA2D register map", 372 ] ], "page_content": "RM0090 Rev 21\n373/1757\nRM0090\nChrom-Art Accelerator™ controller (DMA2D)\n373\n0x0040\nDMA2D_OOR\nReserved\nLO[13:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0044\nDMA2D_NLR\nRes\nPL[13:0]\nNL[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0048\nDMA2D_LWR\nReserved\nLW[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x004C\nDMA2D_AMTCR\nReserved\nDT[7:0]\nReserved\nEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0050-\nOx03FF\n-\nReserved\n0x0400-\n0x07FF\nDMA2D_FGCLUT\nAPLHA[7:0][255:0]\nRED[7:0][255:0]\nGREEN[7:0][255:0]\nBLUE[7:0][255:0]\nReset value\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\n0x0800-\n0x0BFF\nDMA2D_BGCLUT\nAPLHA[7:0][255:0]\nRED[7:0][255:0]\nGREEN[7:0][255:0]\nBLUE[7:0][255:0]\nReset value\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nTable 61. DMA2D register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 374, "page_indices": { "start_index": 808243, "end_index": 810217 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 374 }, "toc_details": [ [ 1, "12 Interrupts and events", 374 ], [ 2, "12.1 Nested vectored interrupt controller (NVIC)", 374 ], [ 3, "12.1.1 NVIC features", 374 ], [ 3, "12.1.2 SysTick calibration value register", 374 ], [ 3, "12.1.3 Interrupt and exception vectors", 374 ], [ 2, "12.2 External interrupt/event controller (EXTI)", 374 ] ], "page_content": "Interrupts and events\nRM0090\n374/1757\nRM0090 Rev 21\n12 \nInterrupts and events\nThis Section applies to the whole STM32F4xx family, unless otherwise specified.\n12.1 \nNested vectored interrupt controller (NVIC)\n12.1.1 \nNVIC features\nThe nested vector interrupt controller NVIC includes the following features:\n•\n82 maskable interrupt channels for STM32F405xx/07xx and STM32F415xx/17xx, and \nup to 91 maskable interrupt channels for STM32F42xxx and STM32F43xxx (not \nincluding the 16 interrupt lines of Cortex®-M4 with FPU)\n•\n16 programmable priority levels (4 bits of interrupt priority are used)\n•\nlow-latency exception and interrupt handling\n•\npower management control\n•\nimplementation of system control registers\nThe NVIC and the processor core interface are closely coupled, which enables low latency \ninterrupt processing and efficient processing of late arriving interrupts.\nAll interrupts including the core exceptions are managed by the NVIC. For more information \non exceptions and NVIC programming, refer to programming manual PM0214.\n12.1.2 \nSysTick calibration value register\nThe SysTick calibration value is fixed to 18750, which gives a reference time base of 1 ms \nwith the SysTick clock set to 18.75 MHz (HCLK/8, with HCLK set to 150 MHz). \n12.1.3 \nInterrupt and exception vectors\nSee Table 62 and Table 63, for the vector table for the STM32F405xx/07xx and \nSTM32F415xx/17xx and STM32F42xxx and STM32F43xxx devices.\n12.2 \nExternal interrupt/event controller (EXTI)\nThe external interrupt/event controller consists of up to 23 edge detectors for generating \nevent/interrupt requests. Each input line can be independently configured to select the type \n(interrupt or event) and the corresponding trigger event (rising or falling or both). Each line \ncan also masked independently. A pending register maintains the status line of the interrupt \nrequests.\nThe grey rows in the following tables describe the vectors without specific position.\n" }, { "page_number": 375, "page_indices": { "start_index": 810217, "end_index": 811926 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 375 }, "toc_details": [ [ 1, "12 Interrupts and events", 374 ], [ 2, "12.2 External interrupt/event controller (EXTI)", 374 ] ], "page_content": "RM0090 Rev 21\n375/1757\nRM0090\nInterrupts and events\n390\n Table 62. Vector table for STM32F405xx/07xx and STM32F415xx/17xx\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\n-\n-\n-\n-\nReserved\n0x0000 0000\n-\n-3\nfixed\nReset\nReset\n0x0000 0004\n-\n-2\nfixed\nNMI\nNon maskable interrupt. The RCC \nClock Security System (CSS) is linked \nto the NMI vector.\n0x0000 0008\n-\n-1\nfixed\nHardFault\nAll class of fault\n0x0000 000C\n-\n0\nsettable\nMemManage\nMemory management\n0x0000 0010\n-\n1\nsettable\nBusFault\nPre-fetch fault, memory access fault\n0x0000 0014\n-\n2\nsettable\nUsageFault\nUndefined instruction or illegal state\n0x0000 0018\n-\n-\n-\n-\nReserved\n0x0000 001C - 0x0000 \n002B\n-\n3\nsettable\nSVCall\nSystem service call via SWI \ninstruction\n0x0000 002C\n-\n4\nsettable\nDebug Monitor\nDebug Monitor\n0x0000 0030\n-\n-\n-\n-\nReserved\n0x0000 0034\n-\n5\nsettable\nPendSV\nPendable request for system service\n0x0000 0038\n-\n6\nsettable\nSysTick\nSystem tick timer\n0x0000 003C\n0\n7\nsettable\nWWDG\nWindow Watchdog interrupt\n0x0000 0040\n1\n8\nsettable\nPVD\nPVD through EXTI line detection \ninterrupt\n0x0000 0044\n2\n9\nsettable\nTAMP_STAMP\nTamper and TimeStamp interrupts \nthrough the EXTI line\n0x0000 0048\n3\n10\nsettable\nRTC_WKUP\nRTC Wake-up interrupt through the \nEXTI line\n0x0000 004C\n4\n11\nsettable\nFLASH\nFlash global interrupt\n0x0000 0050\n5\n12\nsettable\nRCC\nRCC global interrupt\n0x0000 0054\n6\n13\nsettable\nEXTI0\nEXTI Line0 interrupt\n0x0000 0058\n7\n14\nsettable\nEXTI1\nEXTI Line1 interrupt\n0x0000 005C\n8\n15\nsettable\nEXTI2\nEXTI Line2 interrupt\n0x0000 0060\n9\n16\nsettable\nEXTI3\nEXTI Line3 interrupt\n0x0000 0064\n10\n17\nsettable\nEXTI4\nEXTI Line4 interrupt\n0x0000 0068\n11\n18\nsettable\nDMA1_Stream0\nDMA1 Stream0 global interrupt \n0x0000 006C\n" }, { "page_number": 376, "page_indices": { "start_index": 811926, "end_index": 813940 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 376 }, "toc_details": [ [ 1, "12 Interrupts and events", 374 ], [ 2, "12.2 External interrupt/event controller (EXTI)", 374 ] ], "page_content": "Interrupts and events\nRM0090\n376/1757\nRM0090 Rev 21\n12\n19\nsettable\nDMA1_Stream1\nDMA1 Stream1 global interrupt\n0x0000 0070\n13\n20\nsettable\nDMA1_Stream2\nDMA1 Stream2 global interrupt\n0x0000 0074\n14\n21\nsettable\nDMA1_Stream3\nDMA1 Stream3 global interrupt\n0x0000 0078\n15\n22\nsettable\nDMA1_Stream4\nDMA1 Stream4 global interrupt\n0x0000 007C\n16\n23\nsettable\nDMA1_Stream5\nDMA1 Stream5 global interrupt\n0x0000 0080\n17\n24\nsettable\nDMA1_Stream6\nDMA1 Stream6 global interrupt\n0x0000 0084\n18\n25\nsettable\nADC\nADC1, ADC2 and ADC3 global \ninterrupts\n0x0000 0088\n19\n26\nsettable\nCAN1_TX\nCAN1 TX interrupts\n0x0000 008C\n20\n27\nsettable\nCAN1_RX0\nCAN1 RX0 interrupts\n0x0000 0090\n21\n28\nsettable\nCAN1_RX1\nCAN1 RX1 interrupt\n0x0000 0094\n22\n29\nsettable\nCAN1_SCE\nCAN1 SCE interrupt\n0x0000 0098\n23\n30\nsettable\nEXTI9_5\nEXTI Line[9:5] interrupts\n0x0000 009C\n24\n31\nsettable\nTIM1_BRK_TIM9\nTIM1 Break interrupt and TIM9 global \ninterrupt\n0x0000 00A0\n25\n32\nsettable\nTIM1_UP_TIM10\nTIM1 Update interrupt and TIM10 \nglobal interrupt\n0x0000 00A4\n26\n33\nsettable\nTIM1_TRG_COM_TIM11\nTIM1 Trigger and Commutation \ninterrupts and TIM11 global interrupt\n0x0000 00A8\n27\n34\nsettable\nTIM1_CC\nTIM1 Capture Compare interrupt\n0x0000 00AC\n28\n35\nsettable\nTIM2\nTIM2 global interrupt\n0x0000 00B0\n29\n36\nsettable\nTIM3\nTIM3 global interrupt\n0x0000 00B4\n30\n37\nsettable\nTIM4\nTIM4 global interrupt\n0x0000 00B8\n31\n38\nsettable\nI2C1_EV\nI2C1 event interrupt\n0x0000 00BC\n32\n39\nsettable\nI2C1_ER\nI2C1 error interrupt\n0x0000 00C0\n33\n40\nsettable\nI2C2_EV\nI2C2 event interrupt\n0x0000 00C4\n34\n41\nsettable\nI2C2_ER\nI2C2 error interrupt\n0x0000 00C8\n35\n42\nsettable\nSPI1\nSPI1 global interrupt\n0x0000 00CC\n36\n43\nsettable\nSPI2\nSPI2 global interrupt\n0x0000 00D0\n37\n44\nsettable\nUSART1\nUSART1 global interrupt\n0x0000 00D4\n38\n45\nsettable\nUSART2\nUSART2 global interrupt\n0x0000 00D8\n39\n46\nsettable\nUSART3\nUSART3 global interrupt\n0x0000 00DC\nTable 62. Vector table for STM32F405xx/07xx and STM32F415xx/17xx (continued)\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\n" }, { "page_number": 377, "page_indices": { "start_index": 813940, "end_index": 815920 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 377 }, "toc_details": [ [ 1, "12 Interrupts and events", 374 ], [ 2, "12.2 External interrupt/event controller (EXTI)", 374 ] ], "page_content": "RM0090 Rev 21\n377/1757\nRM0090\nInterrupts and events\n390\n40\n47\nsettable\nEXTI15_10\nEXTI Line[15:10] interrupts\n0x0000 00E0\n41\n48\nsettable\nRTC_Alarm\nRTC Alarms (A and B) through EXTI \nline interrupt\n0x0000 00E4\n42\n49\nsettable\nOTG_FS_WKUP\nUSB On-The-Go FS Wake-up through \nEXTI line interrupt\n0x0000 00E8\n43\n50\nsettable\nTIM8_BRK_TIM12\nTIM8 Break interrupt and TIM12 \nglobal interrupt\n0x0000 00EC\n44\n51\nsettable\nTIM8_UP_TIM13\nTIM8 Update interrupt and TIM13 \nglobal interrupt\n0x0000 00F0\n45\n52\nsettable\nTIM8_TRG_COM_TIM14 TIM8 Trigger and Commutation \ninterrupts and TIM14 global interrupt\n0x0000 00F4\n46\n53\nsettable\nTIM8_CC\nTIM8 Capture Compare interrupt\n0x0000 00F8\n47\n54\nsettable\nDMA1_Stream7\nDMA1 Stream7 global interrupt \n0x0000 00FC\n48\n55\nsettable\nFSMC\nFSMC global interrupt\n0x0000 0100\n49\n56\nsettable\nSDIO\nSDIO global interrupt\n0x0000 0104\n50\n57\nsettable\nTIM5\nTIM5 global interrupt\n0x0000 0108\n51\n58\nsettable\nSPI3\nSPI3 global interrupt\n0x0000 010C\n52\n59\nsettable\nUART4\nUART4 global interrupt\n0x0000 0110\n53\n60\nsettable\nUART5\nUART5 global interrupt\n0x0000 0114\n54\n61\nsettable\nTIM6_DAC\nTIM6 global interrupt,\nDAC1 and DAC2 underrun error \ninterrupts\n0x0000 0118\n55\n62\nsettable\nTIM7\nTIM7 global interrupt\n0x0000 011C\n56\n63\nsettable\nDMA2_Stream0\nDMA2 Stream0 global interrupt \n0x0000 0120\n57\n64\nsettable\nDMA2_Stream1\nDMA2 Stream1 global interrupt\n0x0000 0124\n58\n65\nsettable\nDMA2_Stream2\nDMA2 Stream2 global interrupt\n0x0000 0128\n59\n66\nsettable\nDMA2_Stream3\nDMA2 Stream3 global interrupt\n0x0000 012C\n60\n67\nsettable\nDMA2_Stream4\nDMA2 Stream4 global interrupt\n0x0000 0130\n61\n68\nsettable\nETH\nEthernet global interrupt \n0x0000 0134\n62\n69\nsettable\nETH_WKUP\nEthernet Wake-up through EXTI line \ninterrupt\n0x0000 0138\n63\n70\nsettable\nCAN2_TX\nCAN2 TX interrupts\n0x0000 013C\n64\n71\nsettable\nCAN2_RX0\nCAN2 RX0 interrupts\n0x0000 0140\nTable 62. Vector table for STM32F405xx/07xx and STM32F415xx/17xx (continued)\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\n" }, { "page_number": 378, "page_indices": { "start_index": 815920, "end_index": 817543 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 378 }, "toc_details": [ [ 1, "12 Interrupts and events", 374 ], [ 2, "12.2 External interrupt/event controller (EXTI)", 374 ] ], "page_content": "Interrupts and events\nRM0090\n378/1757\nRM0090 Rev 21\n \n65\n72\nsettable\nCAN2_RX1\nCAN2 RX1 interrupt\n0x0000 0144\n66\n73\nsettable\nCAN2_SCE\nCAN2 SCE interrupt\n0x0000 0148\n67\n74\nsettable\nOTG_FS\nUSB On The Go FS global interrupt\n0x0000 014C\n68\n75\nsettable\nDMA2_Stream5\nDMA2 Stream5 global interrupt \n0x0000 0150\n69\n76\nsettable\nDMA2_Stream6\nDMA2 Stream6 global interrupt \n0x0000 0154\n70\n77\nsettable\nDMA2_Stream7\nDMA2 Stream7 global interrupt \n0x0000 0158\n71\n78\nsettable\nUSART6\nUSART6 global interrupt \n0x0000 015C\n72\n79\nsettable\nI2C3_EV\nI2C3 event interrupt\n0x0000 0160\n73\n80\nsettable\nI2C3_ER\nI2C3 error interrupt\n0x0000 0164\n74\n81\nsettable\nOTG_HS_EP1_OUT\nUSB On The Go HS End Point 1 Out \nglobal interrupt \n0x0000 0168\n75\n82\nsettable\nOTG_HS_EP1_IN\nUSB On The Go HS End Point 1 In \nglobal interrupt \n0x0000 016C\n76\n83\nsettable\nOTG_HS_WKUP\nUSB On The Go HS Wake-up through \nEXTI interrupt \n0x0000 0170\n77\n84\nsettable\nOTG_HS\nUSB On The Go HS global interrupt \n0x0000 0174\n78\n85\nsettable\nDCMI\nDCMI global interrupt \n0x0000 0178\n79\n86\nsettable\nCRYP\nCRYP crypto global interrupt\n0x0000 017C\n80\n87\nsettable\nHASH_RNG\nHash and Rng global interrupt \n0x0000 0180\n81\n88\nsettable\nFPU\nFPU global interrupt\n0x0000 0184\nTable 62. Vector table for STM32F405xx/07xx and STM32F415xx/17xx (continued)\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\nTable 63. Vector table for STM32F42xxx and STM32F43xxx\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\n-\n-\n-\n-\nReserved\n0x0000 0000\n-\n-3\nfixed\nReset\nReset\n0x0000 0004\n-\n-2\nfixed\nNMI\nNon maskable interrupt, Clock Security \nSystem\n0x0000 0008\n" }, { "page_number": 379, "page_indices": { "start_index": 817543, "end_index": 819479 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 379 }, "toc_details": [ [ 1, "12 Interrupts and events", 374 ], [ 2, "12.2 External interrupt/event controller (EXTI)", 374 ] ], "page_content": "RM0090 Rev 21\n379/1757\nRM0090\nInterrupts and events\n390\n-\n-1\nfixed\nHardFault\nAll class of fault\n0x0000 000C\n-\n0\nsettable\nMemManage\nMemory management\n0x0000 0010\n-\n1\nsettable\nBusFault\nPre-fetch fault, memory access fault\n0x0000 0014\n-\n2\nsettable\nUsageFault\nUndefined instruction or illegal state\n0x0000 0018\n-\n-\n-\n-\nReserved\n0x0000 001C - \n0x0000 002B\n-\n3\nsettable\nSVCall\nSystem Service call via SWI instruction\n0x0000 002C\n-\n4\nsettable\nDebug Monitor\nDebug Monitor\n0x0000 0030\n-\n-\n-\nReserved\n0x0000 0034\n-\n5\nsettable\nPendSV\nPendable request for system service\n0x0000 0038\n-\n6\nsettable\nSystick\nSystem tick timer\n0x0000 003C\n0\n7\nsettable\nWWDG\nWindow Watchdog interrupt\n0x0000 0040\n1\n8\nsettable\nPVD\nPVD through EXTI line detection interrupt\n0x0000 0044\n2\n9\nsettable\nTAMP_STAMP\nTamper and TimeStamp interrupts through \nthe EXTI line\n0x0000 0048\n3\n10\nsettable\nRTC_WKUP\nRTC Wake-up interrupt through the EXTI \nline\n0x0000 004C\n4\n11\nsettable\nFLASH\nFlash global interrupt\n0x0000 0050\n5\n12\nsettable\nRCC\nRCC global interrupt\n0x0000 0054\n6\n13\nsettable\nEXTI0\nEXTI Line0 interrupt\n0x0000 0058\n7\n14\nsettable\nEXTI1\nEXTI Line1 interrupt\n0x0000 005C\n8\n15\nsettable\nEXTI2\nEXTI Line2 interrupt\n0x0000 0060\n9\n16\nsettable\nEXTI3\nEXTI Line3 interrupt\n0x0000 0064\n10\n17\nsettable\nEXTI4\nEXTI Line4 interrupt\n0x0000 0068\n11\n18\nsettable\nDMA1_Stream0\nDMA1 Stream0 global interrupt \n0x0000 006C\n12\n19\nsettable\nDMA1_Stream1\nDMA1 Stream1 global interrupt\n0x0000 0070\n13\n20\nsettable\nDMA1_Stream2\nDMA1 Stream2 global interrupt\n0x0000 0074\n14\n21\nsettable\nDMA1_Stream3\nDMA1 Stream3 global interrupt\n0x0000 0078\n15\n22\nsettable\nDMA1_Stream4\nDMA1 Stream4 global interrupt\n0x0000 007C\n16\n23\nsettable\nDMA1_Stream5\nDMA1 Stream5 global interrupt\n0x0000 0080\n17\n24\nsettable\nDMA1_Stream6\nDMA1 Stream6 global interrupt\n0x0000 0084\nTable 63. Vector table for STM32F42xxx and STM32F43xxx (continued)\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\n" }, { "page_number": 380, "page_indices": { "start_index": 819479, "end_index": 821398 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 380 }, "toc_details": [ [ 1, "12 Interrupts and events", 374 ], [ 2, "12.2 External interrupt/event controller (EXTI)", 374 ] ], "page_content": "Interrupts and events\nRM0090\n380/1757\nRM0090 Rev 21\n18\n25\nsettable\nADC\nADC1, ADC2 and ADC3 global interrupts\n0x0000 0088\n19\n26\nsettable\nCAN1_TX\nCAN1 TX interrupts\n0x0000 008C\n20\n27\nsettable\nCAN1_RX0\nCAN1 RX0 interrupts\n0x0000 0090\n21\n28\nsettable\nCAN1_RX1\nCAN1 RX1 interrupt\n0x0000 0094\n22\n29\nsettable\nCAN1_SCE\nCAN1 SCE interrupt\n0x0000 0098\n23\n30\nsettable\nEXTI9_5\nEXTI Line[9:5] interrupts\n0x0000 009C\n24\n31\nsettable\nTIM1_BRK_TIM9\nTIM1 Break interrupt and TIM9 global \ninterrupt\n0x0000 00A0\n25\n32\nsettable\nTIM1_UP_TIM10\nTIM1 Update interrupt and TIM10 global \ninterrupt\n0x0000 00A4\n26\n33\nsettable\nTIM1_TRG_COM_TIM11\nTIM1 Trigger and Commutation interrupts \nand TIM11 global interrupt\n0x0000 00A8\n27\n34\nsettable\nTIM1_CC\nTIM1 Capture Compare interrupt\n0x0000 00AC\n28\n35\nsettable\nTIM2\nTIM2 global interrupt\n0x0000 00B0\n29\n36\nsettable\nTIM3\nTIM3 global interrupt\n0x0000 00B4\n30\n37\nsettable\nTIM4\nTIM4 global interrupt\n0x0000 00B8\n31\n38\nsettable\nI2C1_EV\nI2C1 event interrupt\n0x0000 00BC\n32\n39\nsettable\nI2C1_ER\nI2C1 error interrupt\n0x0000 00C0\n33\n40\nsettable\nI2C2_EV\nI2C2 event interrupt\n0x0000 00C4\n34\n41\nsettable\nI2C2_ER\nI2C2 error interrupt\n0x0000 00C8\n35\n42\nsettable\nSPI1\nSPI1 global interrupt\n0x0000 00CC\n36\n43\nsettable\nSPI2\nSPI2 global interrupt\n0x0000 00D0\n37\n44\nsettable\nUSART1\nUSART1 global interrupt\n0x0000 00D4\n38\n45\nsettable\nUSART2\nUSART2 global interrupt\n0x0000 00D8\n39\n46\nsettable\nUSART3\nUSART3 global interrupt\n0x0000 00DC\n40\n47\nsettable\nEXTI15_10\nEXTI Line[15:10] interrupts\n0x0000 00E0\n41\n48\nsettable\nRTC_Alarm\nRTC Alarms (A and B) through EXTI line \ninterrupt\n0x0000 00E4\n42\n49\nsettable\nOTG_FS_WKUP\nUSB On-The-Go FS Wake-up through EXTI \nline interrupt\n0x0000 00E8\n43\n50\nsettable\nTIM8_BRK_TIM12\nTIM8 Break interrupt and TIM12 global \ninterrupt\n0x0000 00EC\nTable 63. Vector table for STM32F42xxx and STM32F43xxx (continued)\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\n" }, { "page_number": 381, "page_indices": { "start_index": 821398, "end_index": 823482 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 381 }, "toc_details": [ [ 1, "12 Interrupts and events", 374 ], [ 2, "12.2 External interrupt/event controller (EXTI)", 374 ] ], "page_content": "RM0090 Rev 21\n381/1757\nRM0090\nInterrupts and events\n390\n44\n51\nsettable\nTIM8_UP_TIM13\nTIM8 Update interrupt and TIM13 global \ninterrupt\n0x0000 00F0\n45\n52\nsettable\nTIM8_TRG_COM_TIM1\n4\nTIM8 Trigger and Commutation interrupts \nand TIM14 global interrupt\n0x0000 00F4\n46\n53\nsettable\nTIM8_CC\nTIM8 Capture Compare interrupt\n0x0000 00F8\n47\n54\nsettable\nDMA1_Stream7\nDMA1 Stream7 global interrupt \n0x0000 00FC\n48\n55\nsettable\nFSMC\nFSMC global interrupt\n0x0000 0100\n49\n56\nsettable\nSDIO\nSDIO global interrupt\n0x0000 0104\n50\n57\nsettable\nTIM5\nTIM5 global interrupt\n0x0000 0108\n51\n58\nsettable\nSPI3\nSPI3 global interrupt\n0x0000 010C\n52\n59\nsettable\nUART4\nUART4 global interrupt\n0x0000 0110\n53\n60\nsettable\nUART5\nUART5 global interrupt\n0x0000 0114\n54\n61\nsettable\nTIM6_DAC\nTIM6 global interrupt,\nDAC1 and DAC2 underrun error interrupts\n0x0000 0118\n55\n62\nsettable\nTIM7\nTIM7 global interrupt\n0x0000 011C\n56\n63\nsettable\nDMA2_Stream0\nDMA2 Stream0 global interrupt \n0x0000 0120\n57\n64\nsettable\nDMA2_Stream1\nDMA2 Stream1 global interrupt\n0x0000 0124\n58\n65\nsettable\nDMA2_Stream2\nDMA2 Stream2 global interrupt\n0x0000 0128\n59\n66\nsettable\nDMA2_Stream3\nDMA2 Stream3 global interrupt\n0x0000 012C\n60\n67\nsettable\nDMA2_Stream4\nDMA2 Stream4 global interrupt\n0x0000 0130\n61\n68\nsettable\nETH\nEthernet global interrupt \n0x0000 0134\n62\n69\nsettable\nETH_WKUP\nEthernet Wake-up through EXTI line \ninterrupt\n0x0000 0138\n63\n70\nsettable\nCAN2_TX\nCAN2 TX interrupts\n0x0000 013C\n64\n71\nsettable\nCAN2_RX0\nCAN2 RX0 interrupts\n0x0000 0140\n65\n72\nsettable\nCAN2_RX1\nCAN2 RX1 interrupt\n0x0000 0144\n66\n73\nsettable\nCAN2_SCE\nCAN2 SCE interrupt\n0x0000 0148\n67\n74\nsettable\nOTG_FS\nUSB On The Go FS global interrupt\n0x0000 014C\n68\n75\nsettable\nDMA2_Stream5\nDMA2 Stream5 global interrupt \n0x0000 0150\n69\n76\nsettable\nDMA2_Stream6\nDMA2 Stream6 global interrupt \n0x0000 0154\n70\n77\nsettable\nDMA2_Stream7\nDMA2 Stream7 global interrupt \n0x0000 0158\n71\n78\nsettable\nUSART6\nUSART6 global interrupt \n0x0000 015C\nTable 63. Vector table for STM32F42xxx and STM32F43xxx (continued)\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\n" }, { "page_number": 382, "page_indices": { "start_index": 823482, "end_index": 825335 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 382 }, "toc_details": [ [ 1, "12 Interrupts and events", 374 ], [ 2, "12.2 External interrupt/event controller (EXTI)", 374 ], [ 3, "12.2.1 EXTI main features", 382 ] ], "page_content": "Interrupts and events\nRM0090\n382/1757\nRM0090 Rev 21\n12.2.1 \nEXTI main features\nThe main features of the EXTI controller are the following:\n•\nindependent trigger and mask on each interrupt/event line\n•\ndedicated status bit for each interrupt line \n•\ngeneration of up to 23 software event/interrupt requests\n•\ndetection of external signals with a pulse width lower than the APB2 clock period. Refer \nto the electrical characteristics section of the STM32F4xx datasheets for details on this \nparameter.\n72\n79\nsettable\nI2C3_EV\nI2C3 event interrupt\n0x0000 0160\n73\n80\nsettable\nI2C3_ER\nI2C3 error interrupt\n0x0000 0164\n74\n81\nsettable\nOTG_HS_EP1_OUT\nUSB On The Go HS End Point 1 Out global \ninterrupt \n0x0000 0168\n75\n82\nsettable\nOTG_HS_EP1_IN\nUSB On The Go HS End Point 1 In global \ninterrupt \n0x0000 016C\n76\n83\nsettable\nOTG_HS_WKUP\nUSB On The Go HS Wake-up through EXTI \ninterrupt \n0x0000 0170\n77\n84\nsettable\nOTG_HS\nUSB On The Go HS global interrupt \n0x0000 0174\n78\n85\nsettable\nDCMI\nDCMI global interrupt \n0x0000 0178\n79\n86\nsettable\nCRYP\nCRYP crypto global interrupt\n0x0000 017C\n80\n87\nsettable\nHASH_RNG\nHash and Rng global interrupt \n0x0000 0180\n81\n88\nSettable\nFPU\nFPU global interrupt\n0x0000 0184\n82\n89\nsettable\nUART7\nUART 7 global interrupt\n0x0000 0188\n83\n90\nsettable\nUART8\nUART 8 global interrupt\n0x0000 018C\n84\n91\nsettable\nSPI4\nSPI 4 global interrupt\n0x0000 0190\n85\n92\nsettable\nSPI5\nSPI 5 global interrupt\n0x0000 0194\n86\n93\nsettable\nSPI6\nSPI 6 global interrupt\n0x0000 0198\n87\n94\nsettable\nSAI1\nSAI1 global interrupt\n0x0000 019C\n88\n95\nsettable\nLCD-TFT\nLTDC global interrupt\n0x0000 01A0\n89\n96\nsettable\nLCD-TFT\nLTDC global Error interrupt\n0x0000 01A4\n90\n97\nsettable\nDMA2D\nDMA2D global interrupt\n0x0000 01A8\nTable 63. Vector table for STM32F42xxx and STM32F43xxx (continued)\nPosition\nPriority\nType of \npriority\nAcronym\nDescription\nAddress\n" }, { "page_number": 383, "page_indices": { "start_index": 825335, "end_index": 827166 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 383 }, "toc_details": [ [ 1, "12 Interrupts and events", 374 ], [ 2, "12.2 External interrupt/event controller (EXTI)", 374 ], [ 3, "12.2.2 EXTI block diagram", 383 ], [ 3, "12.2.3 Wake-up event management", 383 ], [ 3, "12.2.4 Functional description", 383 ] ], "page_content": "RM0090 Rev 21\n383/1757\nRM0090\nInterrupts and events\n390\n12.2.2 \nEXTI block diagram\nFigure 41 shows the block diagram.\nFigure 41. External interrupt/event controller block diagram\n12.2.3 \nWake-up event management\nThe STM32F4xx are able to handle external or internal events in order to wake up the core \n(WFE). The wake-up event can be generated either by:\n•\nenabling an interrupt in the peripheral control register but not in the NVIC, and enabling \nthe SEVONPEND bit in the Cortex®-M4 with FPU System Control register. When the \nMCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC \nIRQ channel pending bit (in the NVIC interrupt clear pending register) have to be \ncleared.\n•\nor configuring an external or internal EXTI line in event mode. When the CPU resumes \nfrom WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC \nIRQ channel pending bit as the pending bit corresponding to the event line is not set.\nTo use an external line as a wake-up event, refer to Section 12.2.4: Functional description.\n12.2.4 \nFunctional description\nTo generate the interrupt, the interrupt line should be configured and enabled. This is done \nby programming the two trigger registers with the desired edge detection and by enabling \nthe interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register. \nWhen the selected edge occurs on the external interrupt line, an interrupt request is \nPeripheral interface\nEdge detect \ncircuit\nAMBA APB bus\nPCLK2\n23\n23\n23\n23\n23\n23\n23\nTo NVIC interrupt\ncontroller\nSoftware \ninterrupt \nevent \nregister\nRising \ntrigger \nselection \nregister\n23\nEvent\nmask\nregister\nPulse \ngenerator\n23\n23\n23\n23\nInput\nline\nPending\nrequest\nregister\n23\nMS32662V1\nInterrupt\nmask\nregister\nFalling\ntrigger \nselection \nregister\n" }, { "page_number": 384, "page_indices": { "start_index": 827166, "end_index": 828929 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 384 }, "toc_details": [ [ 1, "12 Interrupts and events", 374 ], [ 2, "12.2 External interrupt/event controller (EXTI)", 374 ], [ 3, "12.2.4 Functional description", 383 ], [ 4, "Hardware interrupt selection", 384 ], [ 4, "Hardware event selection", 384 ], [ 4, "Software interrupt/event selection", 384 ] ], "page_content": "Interrupts and events\nRM0090\n384/1757\nRM0090 Rev 21\ngenerated. The pending bit corresponding to the interrupt line is also set. This request is \nreset by writing a ‘1’ in the pending register.\nTo generate the event, the event line should be configured and enabled. This is done by \nprogramming the two trigger registers with the desired edge detection and by enabling the \nevent request by writing a ‘1’ to the corresponding bit in the event mask register. When the \nselected edge occurs on the event line, an event pulse is generated. The pending bit \ncorresponding to the event line is not set.\nAn interrupt/event request can also be generated by software by writing a ‘1’ in the software \ninterrupt/event register.\nHardware interrupt selection\nTo configure the 23 lines as interrupt sources, use the following procedure:\n•\nConfigure the mask bits of the 23 interrupt lines (EXTI_IMR)\n•\nConfigure the Trigger selection bits of the interrupt lines (EXTI_RTSR and EXTI_FTSR)\n•\nConfigure the enable and mask bits that control the NVIC IRQ channel mapped to the \nexternal interrupt controller (EXTI) so that an interrupt coming from one of the 23 lines \ncan be correctly acknowledged.\nHardware event selection\nTo configure the 23 lines as event sources, use the following procedure:\n•\nConfigure the mask bits of the 23 event lines (EXTI_EMR)\n•\nConfigure the Trigger selection bits of the event lines (EXTI_RTSR and EXTI_FTSR)\nSoftware interrupt/event selection\nThe 23 lines can be configured as software interrupt/event lines. The following is the \nprocedure to generate a software interrupt.\n•\nConfigure the mask bits of the 23 interrupt/event lines (EXTI_IMR, EXTI_EMR)\n•\nSet the required bit in the software interrupt register (EXTI_SWIER)\n" }, { "page_number": 385, "page_indices": { "start_index": 828929, "end_index": 829608 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 385 }, "toc_details": [ [ 1, "12 Interrupts and events", 374 ], [ 2, "12.2 External interrupt/event controller (EXTI)", 374 ], [ 3, "12.2.5 External interrupt/event line mapping", 385 ] ], "page_content": "RM0090 Rev 21\n385/1757\nRM0090\nInterrupts and events\n390\n12.2.5 \nExternal interrupt/event line mapping\nUp to 140 GPIOs (STM32F405xx/07xx and STM32F415xx/17xx), 168 GPIOs \n(STM32F42xxx and STM32F43xxx) are connected to the 16 external interrupt/event lines in \nthe following manner:\nFigure 42. External interrupt/event GPIO mapping\n(STM32F405xx/07xx and STM32F415xx/17xx)\nPA0\nPB0\nPC0\nPD0\nPE0\nPF0\nPG0\nPH0\nPI0\nPA1\nPB1\nPC1\nPD1\nPE1\nPF1\nPG1\nPH1\nPI1\nPA15\nPB15\nPC15\nPD15\nPE15\nPF15\nPG15\nPH15\nEXTI0\nEXTI1\nEXTI15\nEXTI15[3:0] bits in the SYSCFG_EXTICR4 register\n. . .\nEXTI1[3:0] bits in the SYSCFG_EXTICR1 register\nEXTI0[3:0] bits in the SYSCFG_EXTICR1 register\nai15897\n" }, { "page_number": 386, "page_indices": { "start_index": 829608, "end_index": 830532 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 386 }, "toc_details": [ [ 1, "12 Interrupts and events", 374 ], [ 2, "12.2 External interrupt/event controller (EXTI)", 374 ], [ 3, "12.2.5 External interrupt/event line mapping", 385 ] ], "page_content": "Interrupts and events\nRM0090\n386/1757\nRM0090 Rev 21\nFigure 43. External interrupt/event GPIO mapping (STM32F42xxx and STM32F43xxx)\nThe seven other EXTI lines are connected as follows:\n•\nEXTI line 16 is connected to the PVD output\n•\nEXTI line 17 is connected to the RTC Alarm event\n•\nEXTI line 18 is connected to the USB OTG FS Wake-up event\n•\nEXTI line 19 is connected to the Ethernet Wake-up event\n•\nEXTI line 20 is connected to the USB OTG HS (configured in FS) Wake-up event\n•\nEXTI line 21 is connected to the RTC Tamper and TimeStamp events\n•\nEXTI line 22 is connected to the RTC Wake-up event\nPA0\nPB0\nPC0\nPD0\nPE0\nPF0\nPG0\nPH0\nPI0\nPA1\nPB1\nPC1\nPD1\nPE1\nPF1\nPG1\nPH1\nPI1\nPA15\nPB15\nPC15\nPD15\nPE15\nPF15\nPG15\nPH15\nEXTI0\nEXTI1\nEXTI15\nEXTI15[3:0] bits in the SYSCFG_EXTICR4 register\nEXTI1[3:0] bits in the SYSCFG_EXTICR1 register\nEXTI0[3:0] bits in the SYSCFG_EXTICR1 register\nMS30440V1\nPJ0\nPK0\nPJ1\nPK1\nPJ15\n" }, { "page_number": 387, "page_indices": { "start_index": 830532, "end_index": 831849 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 387 }, "toc_details": [ [ 1, "12 Interrupts and events", 374 ], [ 2, "12.3 EXTI registers", 387 ], [ 3, "12.3.1 Interrupt mask register (EXTI_IMR)", 387 ], [ 3, "12.3.2 Event mask register (EXTI_EMR)", 387 ] ], "page_content": "RM0090 Rev 21\n387/1757\nRM0090\nInterrupts and events\n390\n12.3 \nEXTI registers\nRefer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in \nregister descriptions.\n12.3.1 \nInterrupt mask register (EXTI_IMR)\nAddress offset: 0x00\nReset value: 0x0000 0000\n \n \n12.3.2 \nEvent mask register (EXTI_EMR)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nMR22\nMR21\nMR20\nMR19\nMR18\nMR17\nMR16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMR15\nMR14\nMR13\nMR12\nMR11\nMR10\nMR9\nMR8\nMR7\nMR6\nMR5\nMR4\nMR3\nMR2\nMR1\nMR0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:23 Reserved, must be kept at reset value.\nBits 22:0 MRx: Interrupt mask on line x\n0: Interrupt request from line x is masked\n1: Interrupt request from line x is not masked\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nMR22\nMR21\nMR20\nMR19\nMR18\nMR17\nMR16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMR15\nMR14\nMR13\nMR12\nMR11\nMR10\nMR9\nMR8\nMR7\nMR6\nMR5\nMR4\nMR3\nMR2\nMR1\nMR0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:23 Reserved, must be kept at reset value.\nBits 22:0 MRx: Event mask on line x\n0: Event request from line x is masked\n1: Event request from line x is not masked\n" }, { "page_number": 388, "page_indices": { "start_index": 831849, "end_index": 833912 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 388 }, "toc_details": [ [ 1, "12 Interrupts and events", 374 ], [ 2, "12.3 EXTI registers", 387 ], [ 3, "12.3.3 Rising trigger selection register (EXTI_RTSR)", 388 ], [ 3, "12.3.4 Falling trigger selection register (EXTI_FTSR)", 388 ] ], "page_content": "Interrupts and events\nRM0090\n388/1757\nRM0090 Rev 21\n12.3.3 \nRising trigger selection register (EXTI_RTSR)\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n \nNote:\nThe external wake-up lines are edge triggered, no glitch must be generated on these lines.\nIf a rising edge occurs on the external interrupt line while writing to the EXTI_RTSR register, \nthe pending bit is be set.\nRising and falling edge triggers can be set for the same interrupt line. In this configuration, \nboth generate a trigger condition.\n12.3.4 \nFalling trigger selection register (EXTI_FTSR)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n \n \nNote:\nThe external wake-up lines are edge triggered, no glitch must be generated on these lines.\nIf a falling edge occurs on the external interrupt line while writing to the EXTI_FTSR register, \nthe pending bit is not set.\nRising and falling edge triggers can be set for the same interrupt line. In this configuration, \nboth generate a trigger condition.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTR22\nTR21\nTR20\nTR19\nTR18\nTR17\nTR16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTR15\nTR14\nTR13\nTR12\nTR11\nTR10\nTR9\nTR8\nTR7\nTR6\nTR5\nTR4\nTR3\nTR2\nTR1\nTR0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:23 Reserved, must be kept at reset value.\nBits 22:0 TRx: Rising trigger event configuration bit of line x\n0: Rising trigger disabled (for Event and Interrupt) for input line\n1: Rising trigger enabled (for Event and Interrupt) for input line\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTR22\nTR21\nTR20\nTR19\nTR18\nTR17\nTR16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTR15\nTR14\nTR13\nTR12\nTR11\nTR10\nTR9\nTR8\nTR7\nTR6\nTR5\nTR4\nTR3\nTR2\nTR1\nTR0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:23 Reserved, must be kept at reset value.\nBits 22:0 TRx: Falling trigger event configuration bit of line x\n0: Falling trigger disabled (for Event and Interrupt) for input line\n1: Falling trigger enabled (for Event and Interrupt) for input line.\n" }, { "page_number": 389, "page_indices": { "start_index": 833912, "end_index": 835603 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 389 }, "toc_details": [ [ 1, "12 Interrupts and events", 374 ], [ 2, "12.3 EXTI registers", 387 ], [ 3, "12.3.5 Software interrupt event register (EXTI_SWIER)", 389 ], [ 3, "12.3.6 Pending register (EXTI_PR)", 389 ] ], "page_content": "RM0090 Rev 21\n389/1757\nRM0090\nInterrupts and events\n390\n12.3.5 \nSoftware interrupt event register (EXTI_SWIER)\nAddress offset: 0x10\nReset value: 0x0000 0000\n \n \n12.3.6 \nPending register (EXTI_PR)\nAddress offset: 0x14\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nSWIER\n22\nSWIER\n21\nSWIER\n20\nSWIER\n19\nSWIER\n18\nSWIER\n17\nSWIER\n16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSWIER\n15\nSWIER\n14\nSWIER\n13\nSWIER\n12\nSWIER\n11\nSWIER\n10\nSWIER\n9\nSWIER\n8\nSWIER\n7\nSWIER\n6\nSWIER\n5\nSWIER\n4\nSWIER\n3\nSWIER\n2\nSWIER\n1\nSWIER\n0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:23 Reserved, must be kept at reset value.\nBits 22:0 SWIERx: Software Interrupt on line x\nIf interrupt are enabled on line x in the EXTI_IMR register, writing '1' to SWIERx bit when it is \nset at '0' sets the corresponding pending bit in the EXTI_PR register, thus resulting in an \ninterrupt request generation. \nThis bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to the bit).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPR22\nPR21\nPR20\nPR19\nPR18\nPR17\nPR16\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPR15\nPR14\nPR13\nPR12\nPR11\nPR10\nPR9\nPR8\nPR7\nPR6\nPR5\nPR4\nPR3\nPR2\nPR1\nPR0\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nBits 31:23 Reserved, must be kept at reset value.\nBits 22:0 PRx: Pending bit\n0: No trigger request occurred\n1: selected trigger request occurred\nThis bit is set when the selected edge event arrives on the external interrupt line. \nThis bit is cleared by programming it to ‘1’. \n" }, { "page_number": 390, "page_indices": { "start_index": 835603, "end_index": 836576 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 390 }, "toc_details": [ [ 1, "12 Interrupts and events", 374 ], [ 2, "12.3 EXTI registers", 387 ], [ 3, "12.3.7 EXTI register map", 390 ] ], "page_content": "Interrupts and events\nRM0090\n390/1757\nRM0090 Rev 21\n12.3.7 \nEXTI register map\nTable 65 gives the EXTI register map and the reset values.\n \n \nRefer to Section 2.3: Memory map for the register boundary addresses.\nTable 64. External interrupt/event controller register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nEXTI_IMR\nReserved\nMR[22:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nEXTI_EMR\nReserved\nMR[22:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nEXTI_RTSR\nReserved\nTR[22:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nEXTI_FTSR\nReserved\nTR[22:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nEXTI_SWIER\nReserved\nSWIER[22:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nEXTI_PR\nReserved\nPR[22:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n" }, { "page_number": 391, "page_indices": { "start_index": 836576, "end_index": 838406 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 391 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.1 ADC introduction", 391 ], [ 2, "13.2 ADC main features", 391 ] ], "page_content": "RM0090 Rev 21\n391/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13 \nAnalog-to-digital converter (ADC)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n13.1 \nADC introduction\nThe 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 \nmultiplexed channels allowing it to measure signals from 16 external sources, two internal \nsources, and the VBAT channel. The A/D conversion of the channels can be performed in \nsingle, continuous, scan or discontinuous mode. The result of the ADC is stored into a left- \nor right-aligned 16-bit data register.\nThe analog watchdog feature allows the application to detect if the input voltage goes \nbeyond the user-defined, higher or lower thresholds.\n13.2 \nADC main features\n•\n12-bit, 10-bit, 8-bit or 6-bit configurable resolution\n•\nInterrupt generation at the end of conversion, end of injected conversion, and in case of \nanalog watchdog or overrun events\n•\nSingle and continuous conversion modes\n•\nScan mode for automatic conversion of channel 0 to channel ‘n’\n•\nData alignment with in-built data coherency\n•\nChannel-wise programmable sampling time\n•\nExternal trigger option with configurable polarity for both regular and injected \nconversions\n•\nDiscontinuous mode\n•\nDual/Triple mode (on devices with 2 ADCs or more)\n•\nConfigurable DMA data storage in Dual/Triple ADC mode\n•\nConfigurable delay between conversions in Dual/Triple interleaved mode\n•\nADC conversion type (refer to the datasheets)\n•\nADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at slower \nspeed\n•\nADC input range: VREF– ≤ VIN ≤ VREF+\n•\nDMA request generation during regular channel conversion\nFigure 44 shows the block diagram of the ADC.\nNote:\nVREF–, if available (depending on package), must be tied to VSSA.\n" }, { "page_number": 392, "page_indices": { "start_index": 838406, "end_index": 839654 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 392 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.3 ADC functional description", 392 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n392/1757\nRM0090 Rev 21\n13.3 \nADC functional description\nFigure 44 shows a single ADC block diagram and Table 66 gives the ADC pin description.\nFigure 44. Single ADC block diagram\nADCx_IN0\nADCx_IN1\nAnalog to digital\nconverter\nADCx_IN15\nAnalog\nmux\nADCCLK\nADC Interrupt to NVIC\nGPIO\nports \nAnalog watchdog\nAddress/data bus\nLower threshold (12 bits)\nCompare result \nHigher threshold (12 bits)\nFlags\nenable bits\nEOC\nAWD\nAnalog watchdog event\nVDDA\nVSSA\nVREF+\nVREF-\nInterrupt\nEXTI_11\nTIM3_CH2\nFrom ADC prescaler\n (16 bits)\nEnd of conversion \n channels\nInjected\n channels\nEnd of injected conversion \nJEOC\nEOCIE\nAWDIE \nJEOCIE\nup to 4\nup to 16\nRegular data register\n (4 x 16 bits)\nInjected data registers\nRegular\nStart trigger\n(regular group)\nEXTSEL[3:0] bits\nEXTEN\nTIM3_CH4\nEXTI_15\nTIM1_TRGO\nTIM2_CH1\nTIM2_TRGO\nStart trigger\n(injected group)\nJEXTSEL[3:0] bits\nTIM1_CH4\nJEXTEN\n[1:0] bits\n[1:0] bits\nDMA request\nTemp. sensor\nVREFINT\nOVR OVRIE\nDMA overrun\nVBAT\nTIM5_CH4\nTIM5_TRGO\nTIM4_CH2\nTIM4_CH3\nTIM4_TRGO\nTIM4_CH1\nTIM8_CH3\nTIM8_CH4\nTIM8_CH2\nTIM2_CH3\nTIM2_CH4\nTIM1_CH2\nTIM1_CH3\nTIM2_CH2\nTIM1_CH1\nTIM5_CH1\nTIM5_CH2\nTIM3_CH1\nTIM3_TRGO\nTIM4_CH4\nTIM2_TRGO\nTIM8_CH1\nTIM8_TRGO\nTIM5_CH3\nai16046\n" }, { "page_number": 393, "page_indices": { "start_index": 839654, "end_index": 842136 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 393 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.3 ADC functional description", 392 ], [ 3, "13.3.1 ADC on-off control", 393 ], [ 3, "13.3.2 ADC clock", 393 ], [ 3, "13.3.3 Channel selection", 393 ] ], "page_content": "RM0090 Rev 21\n393/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n \n13.3.1 \nADC on-off control\nThe ADC is powered on by setting the ADON bit in the ADC_CR2 register. When the ADON \nbit is set for the first time, it wakes up the ADC from the Power-down mode.\nConversion starts when either the SWSTART or the JSWSTART bit is set.\nYou can stop conversion and put the ADC in power down mode by clearing the ADON bit. In \nthis mode the ADC consumes almost no power (only a few µA). \n13.3.2 \nADC clock\nThe ADC features two clock schemes: \n•\nClock for the analog circuitry: ADCCLK, common to all ADCs\nThis clock is generated from the APB2 clock divided by a programmable prescaler that \nallows the ADC to work at fPCLK2/2, /4, /6 or /8. Refer to the datasheets for the \nmaximum value of ADCCLK. \n•\nClock for the digital interface (used for registers read/write access) \nThis clock is equal to the APB2 clock. The digital interface clock can be \nenabled/disabled individually for each ADC through the RCC APB2 peripheral clock \nenable register (RCC_APB2ENR).\n13.3.3 \nChannel selection\nThere are 16 multiplexed channels. It is possible to organize the conversions in two groups: \nregular and injected. A group consists of a sequence of conversions that can be done on \nany channel and in any order. For instance, it is possible to implement the conversion \nsequence in the following order: ADC_IN3, ADC_IN8, ADC_IN2, ADC_IN2, ADC_IN0, \nADC_IN2, ADC_IN2, ADC_IN15.\n•\nA regular group is composed of up to 16 conversions. The regular channels and their \norder in the conversion sequence must be selected in the ADC_SQRx registers. The \ntotal number of conversions in the regular group must be written in the L[3:0] bits in the \nADC_SQR1 register.\n•\nAn injected group is composed of up to 4 conversions. The injected channels and \ntheir order in the conversion sequence must be selected in the ADC_JSQR register. \nTable 66. ADC pins\nName\nSignal type\nRemarks\nVREF+\nInput, analog reference \npositive\nThe higher/positive reference voltage for the ADC,\n1.8 V ≤ VREF+ ≤ VDDA\nVDDA\nInput, analog supply\nAnalog power supply equal to VDD and \n2.4 V ≤ VDDA ≤ VDD (3.6 V) for full speed\n1.8 V ≤ VDDA ≤ VDD (3.6 V) for reduced speed\nVREF–\nInput, analog reference \nnegative\nThe lower/negative reference voltage for the ADC, \nVREF– = VSSA\nVSSA\nInput, analog supply \nground\nGround for analog power supply equal to VSS\nADCx_IN[15:0]\nAnalog input signals\n16 analog input channels\n" }, { "page_number": 394, "page_indices": { "start_index": 842136, "end_index": 844183 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 394 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.3 ADC functional description", 392 ], [ 3, "13.3.3 Channel selection", 393 ], [ 4, "Temperature sensor, VREFINT and VBAT internal channels", 394 ], [ 3, "13.3.4 Single conversion mode", 394 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n394/1757\nRM0090 Rev 21\nThe total number of conversions in the injected group must be written in the L[1:0] bits \nin the ADC_JSQR register.\nIf the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current \nconversion is reset and a new start pulse is sent to the ADC to convert the newly chosen \ngroup.\nTemperature sensor, VREFINT and VBAT internal channels\n•\nFor the STM32F40x and STM32F41x devices, the temperature sensor is internally \nconnected to channel ADC1_IN16. \nThe internal reference voltage VREFINT is connected to ADC1_IN17. \n•\nFor the STM32F42x and STM32F43x devices, the temperature sensor is internally \nconnected to ADC1_IN18 channel which is shared with VBAT. Only one conversion, \ntemperature sensor or VBAT, must be selected at a time. When the temperature sensor \nand VBAT conversion are set simultaneously, only the VBAT conversion is performed. \nThe internal reference voltage VREFINT is connected to ADC1_IN17.\nThe VBAT channel (connected to channel ADC1_IN18) can also be converted as an injected \nor regular channel.\nNote:\nThe temperature sensor, VREFINT and the VBAT channel are available only on the master \nADC1 peripheral.\n13.3.4 \nSingle conversion mode\nIn Single conversion mode the ADC does one conversion. This mode is started with the \nCONT bit at 0 by either:\n•\nsetting the SWSTART bit in the ADC_CR2 register (for a regular channel only)\n•\nsetting the JSWSTART bit (for an injected channel)\n•\nexternal trigger (for a regular or injected channel)\nOnce the conversion of the selected channel is complete:\n•\nIf a regular channel was converted:\n–\nThe converted data are stored into the 16-bit ADC_DR register\n–\nThe EOC (end of conversion) flag is set\n–\nAn interrupt is generated if the EOCIE bit is set\n•\nIf an injected channel was converted:\n–\nThe converted data are stored into the 16-bit ADC_JDR1 register\n–\nThe JEOC (end of conversion injected) flag is set\n–\nAn interrupt is generated if the JEOCIE bit is set\nThen the ADC stops.\n" }, { "page_number": 395, "page_indices": { "start_index": 844183, "end_index": 846209 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 395 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.3 ADC functional description", 392 ], [ 3, "13.3.5 Continuous conversion mode", 395 ], [ 3, "13.3.6 Timing diagram", 395 ], [ 3, "13.3.7 Analog watchdog", 395 ] ], "page_content": "RM0090 Rev 21\n395/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.3.5 \nContinuous conversion mode\nIn continuous conversion mode, the ADC starts a new conversion as soon as it finishes one. \nThis mode is started with the CONT bit at 1 either by external trigger or by setting the \nSWSTART bit in the ADC_CR2 register (for regular channels only).\nAfter each conversion:\n•\nIf a regular group of channels was converted:\n–\nThe last converted data are stored into the 16-bit ADC_DR register\n–\nThe EOC (end of conversion) flag is set\n–\nAn interrupt is generated if the EOCIE bit is set\nNote:\nInjected channels cannot be converted continuously. The only exception is when an injected \nchannel is configured to be converted automatically after regular channels in continuous \nmode (using JAUTO bit), refer to Auto-injection section).\n13.3.6 \nTiming diagram\nAs shown in Figure 45, the ADC needs a stabilization time of tSTAB before it starts \nconverting accurately. After the start of the ADC conversion and after 15 clock cycles, the \nEOC flag is set and the 16-bit ADC data register contains the result of the conversion.\nFigure 45. Timing diagram \n13.3.7 \nAnalog watchdog\nThe AWD analog watchdog status bit is set if the analog voltage converted by the ADC is \nbelow a lower threshold or above a higher threshold. These thresholds are programmed in \nthe 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can \nbe enabled by using the AWDIE bit in the ADC_CR1 register.\nThe threshold value is independent of the alignment selected by the ALIGN bit in the \nADC_CR2 register. The analog voltage is compared to the lower and higher thresholds \nbefore alignment.\nTable 67 shows how the ADC_CR1 register should be configured to enable the analog \nwatchdog on one or more channels.\nADC_CLK\nEOC\nNext ADC conversion\nADC conversion\nConversion time \ntSTAB\nADC\nSoftware clears the EOC bit\n \n(total conv. time)\nStart 1st conversion\nStart next conversion\nai16047b\nADON\nSWSTART/\nJSWSTART\n" }, { "page_number": 396, "page_indices": { "start_index": 846209, "end_index": 847982 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 396 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.3 ADC functional description", 392 ], [ 3, "13.3.8 Scan mode", 396 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n396/1757\nRM0090 Rev 21\nFigure 46. Analog watchdog’s guarded area\n \n13.3.8 \nScan mode\nThis mode is used to scan a group of analog channels.\nThe Scan mode is selected by setting the SCAN bit in the ADC_CR1 register. Once this bit \nhas been set, the ADC scans all the channels selected in the ADC_SQRx registers (for \nregular channels) or in the ADC_JSQR register (for injected channels). A single conversion \nis performed for each channel of the group. After each end of conversion, the next channel \nin the group is converted automatically. If the CONT bit is set, regular channel conversion \ndoes not stop at the last selected channel in the group but continues again from the first \nselected channel.\nIf the DMA bit is set, the direct memory access (DMA) controller is used to transfer the data \nconverted from the regular group of channels (stored in the ADC_DR register) to SRAM \nafter each regular channel conversion.\nThe EOC bit is set in the ADC_SR register:\n•\nAt the end of each regular group sequence if the EOCS bit is cleared to 0\n•\nAt the end of each regular channel conversion if the EOCS bit is set to 1\nThe data converted from an injected channel are always stored into the ADC_JDRx \nregisters.\nTable 67. Analog watchdog channel selection\nChannels guarded by the analog \nwatchdog\nADC_CR1 register control bits (x = don’t care)\nAWDSGL bit\nAWDEN bit\nJAWDEN bit\nNone\nx\n0\n0\nAll injected channels\n0\n0\n1\nAll regular channels\n0\n1\n0\nAll regular and injected channels\n0\n1\n1\nSingle(1) injected channel\n1.\nSelected by the AWDCH[4:0] bits\n1\n0\n1\nSingle(1) regular channel\n1\n1\n0\nSingle (1) regular or injected channel\n1\n1\n1\nAnalog voltage\nHigher threshold\nLower threshold\nGuarde d area\nHTR\nLTR\nai16048\n" }, { "page_number": 397, "page_indices": { "start_index": 847982, "end_index": 850033 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 397 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.3 ADC functional description", 392 ], [ 3, "13.3.9 Injected channel management", 397 ], [ 4, "Triggered injection", 397 ], [ 4, "Auto-injection", 397 ] ], "page_content": "RM0090 Rev 21\n397/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.3.9 \nInjected channel management\nTriggered injection\nTo use triggered injection, the JAUTO bit must be cleared in the ADC_CR1 register.\n1.\nStart the conversion of a group of regular channels either by external trigger or by \nsetting the SWSTART bit in the ADC_CR2 register.\n2. \nIf an external injected trigger occurs or if the JSWSTART bit is set during the \nconversion of a regular group of channels, the current conversion is reset and the \ninjected channel sequence switches to Scan-once mode.\n3. \nThen, the regular conversion of the regular group of channels is resumed from the last \ninterrupted regular conversion.\nIf a regular event occurs during an injected conversion, the injected conversion is not \ninterrupted but the regular sequence is executed at the end of the injected sequence. \nFigure 47 shows the corresponding timing diagram.\nNote:\nWhen using triggered injection, one must ensure that the interval between trigger events is \nlonger than the injection sequence. For instance, if the sequence length is 30 ADC clock \ncycles (that is two conversions with a sampling time of 3 clock periods), the minimum \ninterval between triggers must be 31 ADC clock cycles.\nAuto-injection\nIf the JAUTO bit is set, then the channels in the injected group are automatically converted \nafter the regular group of channels. This can be used to convert a sequence of up to 20 \nconversions programmed in the ADC_SQRx and ADC_JSQR registers.\nIn this mode, external trigger on injected channels must be disabled.\nIf the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected \nchannels are continuously converted.\nNote:\nIt is not possible to use both the auto-injected and discontinuous modes simultaneously.\nFigure 47. Injected conversion latency\n1.\nThe maximum latency value can be found in the electrical characteristics of the STM32F40x and \nSTM32F41x datasheets.\nADCCLK\nInjection event\nReset ADC\nSOC\nmax latency (1)\nai16049\n" }, { "page_number": 398, "page_indices": { "start_index": 850033, "end_index": 852512 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 398 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.3 ADC functional description", 392 ], [ 3, "13.3.10 Discontinuous mode", 398 ], [ 4, "Regular group", 398 ], [ 4, "Injected group", 398 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n398/1757\nRM0090 Rev 21\n13.3.10 \nDiscontinuous mode\nRegular group\nThis mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to \nconvert a short sequence of n conversions (n ≤ 8) that is part of the sequence of conversions \nselected in the ADC_SQRx registers. The value of n is specified by writing to the \nDISCNUM[2:0] bits in the ADC_CR1 register.\nWhen an external trigger occurs, it starts the next n conversions selected in the ADC_SQRx \nregisters until all the conversions in the sequence are done. The total sequence length is \ndefined by the L[3:0] bits in the ADC_SQR1 register.\nExample:\n•\nn = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10\n•\n1st trigger: sequence converted 0, 1, 2. An EOC event is generated at each \nconversion.\n•\n2nd trigger: sequence converted 3, 6, 7. An EOC event is generated at each \nconversion\n•\n3rd trigger: sequence converted 9, 10.An EOC event is generated at each conversion\n•\n4th trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion\nNote:\nWhen a regular group is converted in discontinuous mode, no rollover occurs.\nWhen all subgroups are converted, the next trigger starts the conversion of the first \nsubgroup. In the example above, the 4th trigger reconverts the channels 0, 1 and 2 in the \n1st subgroup.\nInjected group\nThis mode is enabled by setting the JDISCEN bit in the ADC_CR1 register. It can be used to \nconvert the sequence selected in the ADC_JSQR register, channel by channel, after an \nexternal trigger event.\nWhen an external trigger occurs, it starts the next channel conversions selected in the \nADC_JSQR registers until all the conversions in the sequence are done. The total sequence \nlength is defined by the JL[1:0] bits in the ADC_JSQR register.\nExample:\nn = 1, channels to be converted = 1, 2, 3\n1st trigger: channel 1 converted \n2nd trigger: channel 2 converted \n3rd trigger: channel 3 converted and JEOC event generated\n4th trigger: channel 1\nNote:\nWhen all injected channels are converted, the next trigger starts the conversion of the first \ninjected channel. In the example above, the 4th trigger reconverts the 1st injected channel \n1.\nIt is not possible to use both the auto-injected and discontinuous modes simultaneously.\nDiscontinuous mode must not be set for regular and injected groups at the same time. \nDiscontinuous mode must be enabled only for the conversion of one group.\n" }, { "page_number": 399, "page_indices": { "start_index": 852512, "end_index": 853917 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 399 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.4 Data alignment", 399 ] ], "page_content": "RM0090 Rev 21\n399/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.4 \nData alignment\nThe ALIGN bit in the ADC_CR2 register selects the alignment of the data stored after \nconversion. Data can be right- or left-aligned as shown in Figure 48 and Figure 49.\nThe converted data value from the injected group of channels is decreased by the user-\ndefined offset written in the ADC_JOFRx registers so the result can be a negative value. \nThe SEXT bit represents the extended sign value.\nFor channels in a regular group, no offset is subtracted so only twelve bits are significant.\nFigure 48. Right alignment of 12-bit data\nFigure 49. Left alignment of 12-bit data\nSpecial case: when left-aligned, the data are aligned on a half-word basis except when the \nresolution is set to 6-bit. in that case, the data are aligned on a byte basis as shown in \nFigure 50.\nFigure 50. Left alignment of 6-bit data\nD7\nD8\n D9\nD6\nD5\n D4\nD3\n D2\n D1\n D0\n D10\n D11\n SEXT\n SEXT\n SEXT\n SEXT\nD7\nD8\n D10\n D11\n Injected group\n Regular group\n0\n0\n0\n0\n D9\nD6\nD5\n D4\nD3\n D2\n D1\n D0\nai16050\nD4\nD5\n D6 \nD3\nD2\n D1\nD0\n 0 0 0\n D7\n D8\nD9\n D10\n D11\n SEXT\n Injected group\n Regular group\nai16051\nD11\nD10\nD9\nD8\nD7\nD6\nD5\nD4\nD3\nD2\nD1\nD0\n0\n0\n0\n0\nD4\nD5\n SEXT\n SEXT\nSEXT\nSEXT\n SEXT\n SEXT\n Injected group\n Regular group\nai16052\n0\n0\n0\n0\n0\n0\nD5\nD4\nD3\nD2\nD1\nD0\n0\n0\n0\n0\n SEXT\n SEXT\nD3\nD2\nD1\nD0\n0\n SEXT\n" }, { "page_number": 400, "page_indices": { "start_index": 853917, "end_index": 855460 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 400 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.5 Channel-wise programmable sampling time", 400 ], [ 2, "13.6 Conversion on external trigger and trigger polarity", 400 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n400/1757\nRM0090 Rev 21\n13.5 \nChannel-wise programmable sampling time\nThe ADC samples the input voltage for a number of ADCCLK cycles that can be modified \nusing the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can \nbe sampled with a different sampling time.\nThe total conversion time is calculated as follows:\nTconv = Sampling time + 12 cycles\nExample:\nWith ADCCLK = 30 MHz and sampling time = 3 cycles:\nTconv = 3 + 12 = 15 cycles = 0.5 µs with APB2 at 60 MHz\n13.6 \nConversion on external trigger and trigger polarity\nConversion can be triggered by an external event (e.g. timer capture, EXTI line). If the \nEXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected \nconversion) are different from “0b00”, then external events are able to trigger a conversion \nwith the selected polarity. Table 68 provides the correspondence between the EXTEN[1:0] \nand JEXTEN[1:0] values and the trigger polarity.\n \nNote:\nThe polarity of the external trigger can be changed on the fly.\nThe EXTSEL[3:0] and JEXTSEL[3:0] control bits are used to select which out of 16 possible \nevents can trigger conversion for the regular and injected groups.\nTable 69 gives the possible external trigger for regular conversion.\nTable 68. Configuring the trigger polarity\nSource\nEXTEN[1:0] / JEXTEN[1:0]\nTrigger detection disabled\n00\nDetection on the rising edge\n01\nDetection on the falling edge\n10\nDetection on both the rising and falling edges\n11\n" }, { "page_number": 401, "page_indices": { "start_index": 855460, "end_index": 856074 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 401 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.6 Conversion on external trigger and trigger polarity", 400 ] ], "page_content": "RM0090 Rev 21\n401/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n \nTable 70 gives the possible external trigger for injected conversion.\nTable 69. External trigger for regular channels\nSource\nType\nEXTSEL[3:0]\nTIM1_CH1 event \nInternal signal from on-chip \ntimers\n0000\nTIM1_CH2 event\n0001\nTIM1_CH3 event\n0010\nTIM2_CH2 event\n0011\nTIM2_CH3 event\n0100\nTIM2_CH4 event\n0101\nTIM2_TRGO event\n0110\nTIM3_CH1 event\n0111\nTIM3_TRGO event\n1000\nTIM4_CH4 event\n1001\nTIM5_CH1 event \n1010\nTIM5_CH2 event\n1011\nTIM5_CH3 event\n1100\nTIM8_CH1 event\n1101\nTIM8_TRGO event\n1110\nEXTI line11\nExternal pin\n1111\n" }, { "page_number": 402, "page_indices": { "start_index": 856074, "end_index": 857481 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 402 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.7 Fast conversion mode", 402 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n402/1757\nRM0090 Rev 21\n \nSoftware source trigger events can be generated by setting SWSTART (for regular \nconversion) or JSWSTART (for injected conversion) in ADC_CR2.\nA regular group conversion can be interrupted by an injected trigger.\nNote:\nThe trigger selection can be changed on the fly. However, when the selection changes, \nthere is a time frame of 1 APB clock cycle during which the trigger detection is disabled. \nThis is to avoid spurious detection during transitions.\n13.7 \nFast conversion mode\nIt is possible to perform faster conversion by reducing the ADC resolution. The RES bits are \nused to select the number of bits available in the data register. The minimum conversion \ntime for each resolution is then as follows:\n•\n12 bits: 3 + 12 = 15 ADCCLK cycles\n•\n10 bits: 3 + 10 = 13 ADCCLK cycles\n•\n8 bits: 3 + 8 = 11 ADCCLK cycles\n•\n6 bits: 3 + 6 = 9 ADCCLK cycles\nTable 70. External trigger for injected channels\nSource\nConnection type\nJEXTSEL[3:0]\nTIM1_CH4 event \nInternal signal from on-chip \ntimers\n0000\nTIM1_TRGO event\n0001\nTIM2_CH1 event\n0010\nTIM2_TRGO event\n0011\nTIM3_CH2 event\n0100\nTIM3_CH4 event\n0101\nTIM4_CH1 event \n0110\nTIM4_CH2 event\n0111\nTIM4_CH3 event\n1000\nTIM4_TRGO event\n1001\nTIM5_CH4 event\n1010\nTIM5_TRGO event\n1011\nTIM8_CH2 event\n1100\nTIM8_CH3 event\n1101\nTIM8_CH4 event\n1110\nEXTI line15\nExternal pin\n1111\n" }, { "page_number": 403, "page_indices": { "start_index": 857481, "end_index": 860472 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 403 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.8 Data management", 403 ], [ 3, "13.8.1 Using the DMA", 403 ], [ 3, "13.8.2 Managing a sequence of conversions without using the DMA", 403 ] ], "page_content": "RM0090 Rev 21\n403/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.8 \nData management\n13.8.1 \nUsing the DMA\nSince converted regular channel values are stored into a unique data register, it is useful to \nuse DMA for conversion of more than one regular channel. This avoids the loss of the data \nalready stored in the ADC_DR register.\nWhen the DMA mode is enabled (DMA bit set to 1 in the ADC_CR2 register), after each \nconversion of a regular channel, a DMA request is generated. This allows the transfer of the \nconverted data from the ADC_DR register to the destination location selected by the \nsoftware.\nDespite this, if data are lost (overrun), the OVR bit in the ADC_SR register is set and an \ninterrupt is generated (if the OVRIE enable bit is set). DMA transfers are then disabled and \nDMA requests are no longer accepted. In this case, if a DMA request is made, the regular \nconversion in progress is aborted and further regular triggers are ignored. It is then \nnecessary to clear the OVR flag and the DMAEN bit in the used DMA stream, and to re-\ninitialize both the DMA and the ADC to have the wanted converted channel data transferred \nto the right memory location. Only then can the conversion be resumed and the data \ntransfer, enabled again. Injected channel conversions are not impacted by overrun errors.\nWhen OVR = 1 in DMA mode, the DMA requests are blocked after the last valid data have \nbeen transferred, which means that all the data transferred to the RAM can be considered \nas valid.\nAt the end of the last DMA transfer (number of transfers configured in the DMA controller’s \nDMA_SxNDTR register):\n•\nNo new DMA request is issued to the DMA controller if the DDS bit is cleared to 0 in the \nADC_CR2 register (this avoids generating an overrun error). However the DMA bit is \nnot cleared by hardware. It must be written to 0, then to 1 to start a new transfer.\n•\nRequests can continue to be generated if the DDS bit is set to 1. This allows \nconfiguring the DMA in double-buffer circular mode.\nTo recover the ADC from OVR state when the DMA is used, follow the steps below:\n1.\nReinitialize the DMA (adjust destination address and NDTR counter)\n2. \nClear the ADC OVR bit in ADC_SR register\n3. \nTrigger the ADC to start the conversion.\n13.8.2 \nManaging a sequence of conversions without using the DMA\nIf the conversions are slow enough, the conversion sequence can be handled by the \nsoftware. In this case the EOCS bit must be set in the ADC_CR2 register for the EOC status \nbit to be set at the end of each conversion, and not only at the end of the sequence. When \nEOCS = 1, overrun detection is automatically enabled. Thus, each time a conversion is \ncomplete, EOC is set and the ADC_DR register can be read. The overrun management is \nthe same as when the DMA is used.\nTo recover the ADC from OVR state when the EOCS is set, follow the steps below:\n1.\nClear the ADC OVR bit in ADC_SR register\n2. \nTrigger the ADC to start the conversion.\n" }, { "page_number": 404, "page_indices": { "start_index": 860472, "end_index": 862049 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 404 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.8 Data management", 403 ], [ 3, "13.8.3 Conversions without DMA and without overrun detection", 404 ], [ 2, "13.9 Multi ADC mode", 404 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n404/1757\nRM0090 Rev 21\n13.8.3 \nConversions without DMA and without overrun detection\nIt may be useful to let the ADC convert one or more channels without reading the data each \ntime (if there is an analog watchdog for instance). For that, the DMA must be disabled \n(DMA = 0) and the EOC bit must be set at the end of a sequence only (EOCS = 0). In this \nconfiguration, overrun detection is disabled.\n13.9 \nMulti ADC mode\nIn devices with two ADCs or more, the Dual (with two ADCs) and Triple (with three ADCs) \nADC modes can be used (see Figure 51).\nIn multi ADC mode, the start of conversion is triggered alternately or simultaneously by the \nADC1 master to the ADC2 and ADC3 slaves, depending on the mode selected by the \nMULTI[4:0] bits in the ADC_CCR register.\nNote:\nIn multi ADC mode, when configuring conversion trigger by an external event, the \napplication must set trigger by the master only and disable trigger by slaves to prevent \nspurious triggers that would start unwanted slave conversions.\nThe four possible modes below are implemented:\n•\nInjected simultaneous mode\n•\nRegular simultaneous mode\n•\nInterleaved mode\n•\nAlternate trigger mode\nIt is also possible to use the previous modes combined in the following ways:\n•\nInjected simultaneous mode + Regular simultaneous mode\n•\nRegular simultaneous mode + Alternate trigger mode\nNote:\nIn multi ADC mode, the converted data can be read on the multi-mode data register \n(ADC_CDR). The status bits can be read in the multi-mode status register (ADC_CSR).\n" }, { "page_number": 405, "page_indices": { "start_index": 862049, "end_index": 863342 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 405 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.9 Multi ADC mode", 404 ] ], "page_content": "RM0090 Rev 21\n405/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\nFigure 51. Multi ADC block diagram(1)\n1.\nAlthough external triggers are present on ADC2 and ADC3 they are not shown in this diagram.\n2.\nIn the Dual ADC mode, the ADC3 slave part is not present.\n3.\nIn Triple ADC mode, the ADC common data register (ADC_CDR) contains the ADC1, ADC2 and ADC3’s \nregular converted data. All 32 register bits are used according to a selected storage order.\nIn Dual ADC mode, the ADC common data register (ADC_CDR) contains both the ADC1 and ADC2’s \nregular converted data. All 32 register bits are used.\nADCx_IN0\nADCx_IN1\nADCx_IN15\nGPIO\nPorts \nAddress/data bus\nEXTI_11\nEXTI_15\nInjected data registers\n (4 x 16 bits)\nRegular\n channels\nInjected\n channels\nADC3(2) (Slave)\n (12 bits)\nInjected data registers\n (4 x 16 bits)\nRegular\n channels\nInjected\n channels\nADC1 (Master)\nDual/Triple\ninternal triggers \nStart trigger mux\n \n(regular group)\n(injected group)\nStart trigger mux\n control\nTemp. sensor\nVREFINT\nRegular data register\n (16 bits)\nRegular data register\n (16 bits)\nCommon regular data register\n (32 bits)(3)\nVBAT\nCommon part\n mode\nADC2 (Slave)\n (12 bits)\nInjected data registers\n (4 x 16 bits)\nRegular\n channels\nInjected\n channels\nRegular data register\n (16 bits)\nai16053\n" }, { "page_number": 406, "page_indices": { "start_index": 863342, "end_index": 866014 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 406 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.9 Multi ADC mode", 404 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n406/1757\nRM0090 Rev 21\n•\nDMA requests in Multi ADC mode:\nIn Multi ADC mode the DMA may be configured to transfer converted data in three \ndifferent modes. In all cases, the DMA streams to use are those connected to the ADC:\n–\nDMA mode 1: On each DMA request (one data item is available), a half-word \nrepresenting an ADC-converted data item is transferred.\nIn Triple ADC mode, ADC1 data are transferred on the first request, ADC2 data \nare transferred on the second request and ADC3 data are transferred on the third \nrequest; the sequence is repeated. So the DMA first transfers ADC1 data followed \nby ADC2 data followed by ADC3 data and so on.\nDMA mode 1 is used in regular simultaneous triple mode only.\nExample:\nRegular simultaneous triple mode: 3 consecutive DMA requests are generated \n(one for each converted data item)\n1st request: ADC_CDR[31:0] = ADC1_DR[15:0]\n2nd request: ADC_CDR[31:0] = ADC2_DR[15:0]\n3rd request: ADC_CDR[31:0] = ADC3_DR[15:0]\n4th request: ADC_CDR[31:0] = ADC1_DR[15:0]\n–\nDMA mode 2: On each DMA request (two data items are available) two half-\nwords representing two ADC-converted data items are transferred as a word.\nIn Dual ADC mode, both ADC2 and ADC1 data are transferred on the first request \n(ADC2 data take the upper half-word and ADC1 data take the lower half-word) and \nso on.\nIn Triple ADC mode, three DMA requests are generated. On the first request, both \nADC2 and ADC1 data are transferred (ADC2 data take the upper half-word and \nADC1 data take the lower half-word). On the second request, both ADC1 and \nADC3 data are transferred (ADC1 data take the upper half-word and ADC3 data \ntake the lower half-word).On the third request, both ADC3 and ADC2 data are \ntransferred (ADC3 data take the upper half-word and ADC2 data take the lower \nhalf-word) and so on.\nDMA mode 2 is used in interleaved mode and in regular simultaneous mode (for \nDual ADC mode only).\nExample:\na) \nInterleaved dual mode: a DMA request is generated each time 2 data items are \navailable:\n1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0] \n2nd request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0] \nb) \nInterleaved triple mode: a DMA request is generated each time 2 data items are \navailable\n1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0] \n2nd request: ADC_CDR[31:0] = ADC1_DR[15:0] | ADC3_DR[15:0] \n3rd request: ADC_CDR[31:0] = ADC3_DR[15:0] | ADC2_DR[15:0] \n4th request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]\n–\nDMA mode 3: This mode is similar to the DMA mode 2. The only differences are \nthat the on each DMA request (two data items are available) two bytes \n" }, { "page_number": 407, "page_indices": { "start_index": 866014, "end_index": 868246 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 407 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.9 Multi ADC mode", 404 ], [ 3, "13.9.1 Injected simultaneous mode", 407 ] ], "page_content": "RM0090 Rev 21\n407/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\nrepresenting two ADC converted data items are transferred as a half-word. The \ndata transfer order is similar to that of the DMA mode 2.\nDMA mode 3 is used in interleaved mode in 6-bit and 8-bit resolutions (dual and \ntriple mode).\nExample:\na) \nInterleaved dual mode: a DMA request is generated each time 2 data items are \navailable\n1st request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]\n2nd request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]\nb) \nInterleaved triple mode: a DMA request is generated each time 2 data items are \navailable\n1st request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]\n2nd request: ADC_CDR[15:0] = ADC1_DR[7:0] | ADC3_DR[7:0]\n3rd request: ADC_CDR[15:0] = ADC3_DR[7:0] | ADC2_DR[7:0]\n4th request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]\nOverrun detection: If an overrun is detected on one of the concerned ADCs (ADC1 and \nADC2 in dual and triple modes, ADC3 in triple mode only), the DMA requests are no longer \nissued to ensure that all the data transferred to the RAM are valid. It may happen that the \nEOC bit corresponding to one ADC remains set because the data register of this ADC \ncontains valid data.\n13.9.1 \nInjected simultaneous mode\nThis mode converts an injected group of channels. The external trigger source comes from \nthe injected group multiplexer of ADC1 (selected by the JEXTSEL[3:0] bits in the ADC1_CR2 \nregister). A simultaneous trigger is provided to ADC2 and ADC3.\nNote:\nDo not convert the same channel on the two/three ADCs (no overlapping sampling times for \nthe two/three ADCs when converting the same channel).\nIn simultaneous mode, one must convert sequences with the same length or ensure that the \ninterval between triggers is longer than the longer of the 2 sequences (Dual ADC mode) /3 \nsequences (Triple ADC mode). Otherwise, the ADC with the shortest sequence may restart \nwhile the ADC with the longest sequence is completing the previous conversions.\nRegular conversions can be performed on one or all ADCs. In that case, they are \nindependent of each other and are interrupted when an injected event occurs. They are \nresumed at the end of the injected conversion group.\n" }, { "page_number": 408, "page_indices": { "start_index": 868246, "end_index": 870208 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 408 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.9 Multi ADC mode", 404 ], [ 3, "13.9.1 Injected simultaneous mode", 407 ], [ 4, "Dual ADC mode", 408 ], [ 4, "Triple ADC mode", 408 ], [ 3, "13.9.2 Regular simultaneous mode", 408 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n408/1757\nRM0090 Rev 21\nDual ADC mode\nAt the end of conversion event on ADC1 or ADC2:\n•\nThe converted data are stored into the ADC_JDRx registers of each ADC interface.\n•\nA JEOC interrupt is generated (if enabled on one of the two ADC interfaces) when the \nADC1/ADC2’s injected channels have all been converted.\nFigure 52. Injected simultaneous mode on 4 channels: dual ADC mode\nTriple ADC mode\nAt the end of conversion event on ADC1, ADC2 or ADC3:\n•\nThe converted data are stored into the ADC_JDRx registers of each ADC interface.\n•\nA JEOC interrupt is generated (if enabled on one of the three ADC interfaces) when the \nADC1/ADC2/ADC3’s injected channels have all been converted.\nFigure 53. Injected simultaneous mode on 4 channels: triple ADC mode\n13.9.2 \nRegular simultaneous mode\nThis mode is performed on a regular group of channels. The external trigger source comes \nfrom the regular group multiplexer of ADC1 (selected by the EXTSEL[3:0] bits in the \nADC1_CR2 register). A simultaneous trigger is provided to ADC2 and ADC3.\nNote:\nDo not convert the same channel on the two/three ADCs (no overlapping sampling times for \nthe two/three ADCs when converting the same channel).\nIn regular simultaneous mode, one must convert sequences with the same length or ensure \nthat the interval between triggers is longer than the long conversion time of the 2 sequences \n(Dual ADC mode) /3 sequences (Triple ADC mode). Otherwise, the ADC with the shortest \nsequence may restart while the ADC with the longest sequence is completing the previous \nconversions.\nInjected conversions must be disabled.\nCH0\nCH1\nCH2\nCH3\nCH15\nCH14\nCH13\nCH12\nADC1\nADC2\nTrigger\nEnd of conversion on ADC1 and ADC2\nConversion\nSampling\nCH15\nCH0\n...\n...\nai16054\nCH0\nCH1\nCH2\nCH3\nCH15\nCH14\nCH13\nCH12\nADC1\nADC2\nTrigger\nEnd of conversion on ADC1, ADC2 and ADC3\nConversion\nSampling\nCH15\nCH0\n...\n...\nai16055\nCH10\nCH12\nCH8\nCH5\nADC3\nCH2\n...\n" }, { "page_number": 409, "page_indices": { "start_index": 870208, "end_index": 871828 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 409 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.9 Multi ADC mode", 404 ], [ 3, "13.9.2 Regular simultaneous mode", 408 ], [ 4, "Dual ADC mode", 409 ], [ 4, "Triple ADC mode", 409 ] ], "page_content": "RM0090 Rev 21\n409/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\nDual ADC mode\nAt the end of conversion event on ADC1 or ADC2:\n•\nA 32-bit DMA transfer request is generated (if DMA[1:0] bits in the ADC_CCR register \nare equal to 0b10). This request transfers the ADC2 converted data stored in the upper \nhalf-word of the ADC_CDR 32-bit register to the SRAM and then the ADC1 converted \ndata stored in the lower half-word of ADC_CDR to the SRAM.\n•\nAn EOC interrupt is generated (if enabled on one of the two ADC interfaces) when the \nADC1/ADC2’s regular channels have all been converted.\nFigure 54. Regular simultaneous mode on 16 channels: dual ADC mode\nTriple ADC mode\nAt the end of conversion event on ADC1, ADC2 or ADC3:\n•\nThree 32-bit DMA transfer requests are generated (if DMA[1:0] bits in the ADC_CCR \nregister are equal to 0b01). Three transfers then take place from the ADC_CDR 32-bit \nregister to SRAM: first the ADC1 converted data, then the ADC2 converted data and \nfinally the ADC3 converted data. The process is repeated for each new three \nconversions.\n•\nAn EOC interrupt is generated (if enabled on one of the three ADC interfaces) when the \nADC1/ADC2/ADC3’s regular channels are have all been converted.\nFigure 55. Regular simultaneous mode on 16 channels: triple ADC mode\nCH0\nCH1\nCH2\nCH3\nCH15\nCH14\nCH13\nCH12\nADC1\nADC2\nTrigger\nEnd of conversion on ADC1 and ADC2\nConversion\nSampling\nCH15\nCH0\n...\n...\nai16054\nCH0\nCH1\nCH2\nCH3\nCH15\nCH14\nCH13\nCH12\nADC1\nADC2\nTrigger\nEnd of conversion on ADC1, ADC2 and ADC3\nConversion\nSampling\nCH15\nCH0\n...\n...\nai16055\nCH10\nCH12\nCH8\nCH5\nADC3\nCH2\n...\n" }, { "page_number": 410, "page_indices": { "start_index": 871828, "end_index": 874201 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 410 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.9 Multi ADC mode", 404 ], [ 3, "13.9.3 Interleaved mode", 410 ], [ 4, "Dual ADC mode", 410 ], [ 4, "Triple ADC mode", 410 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n410/1757\nRM0090 Rev 21\n13.9.3 \nInterleaved mode\nThis mode can be started only on a regular group (usually one channel). The external \ntrigger source comes from the regular channel multiplexer of ADC1.\nDual ADC mode\nAfter an external trigger occurs:\n•\nADC1 starts immediately\n•\nADC2 starts after a delay of several ADC clock cycles\nThe minimum delay which separates 2 conversions in interleaved mode is configured in the \nDELAY bits in the ADC_CCR register. However, an ADC cannot start a conversion if the \ncomplementary ADC is still sampling its input (only one ADC can sample the input signal at \na given time). In this case, the delay becomes the sampling time + 2 ADC clock cycles. For \ninstance, if DELAY = 5 clock cycles and the sampling takes 15 clock cycles on both ADCs, \nthen 17 clock cycles separate conversions on ADC1 and ADC2).\nIf the CONT bit is set on both ADC1 and ADC2, the selected regular channels of both ADCs \nare continuously converted.\nNote:\nIf the conversion sequence is interrupted (for instance when DMA end of transfer occurs), \nthe multi-ADC sequencer must be reset by configuring it in independent mode first (bits \nDUAL[4:0] = 00000) before reprogramming the interleaved mode.\nAfter an EOC interrupt is generated by ADC2 (if enabled through the EOCIE bit) a 32-bit \nDMA transfer request is generated (if the DMA[1:0] bits in ADC_CCR are equal to 0b10). \nThis request first transfers the ADC2 converted data stored in the upper half-word of the \nADC_CDR 32-bit register into SRAM, then the ADC1 converted data stored in the register’s \nlower half-word into SRAM.\nFigure 56. Interleaved mode on 1 channel in continuous conversion mode: dual ADC \nmode\nTriple ADC mode\nAfter an external trigger occurs:\n•\nADC1 starts immediately and\n•\nADC2 starts after a delay of several ADC clock cycles\n•\nADC3 starts after a delay of several ADC clock cycles referred to the ADC2 conversion\nThe minimum delay which separates 2 conversions in interleaved mode is configured in the \nDELAY bits in the ADC_CCR register. However, an ADC cannot start a conversion if the \ncomplementary ADC is still sampling its input (only one ADC can sample the input signal at \nCH0\nCH0\nADC1\nADC2\nTrigger\nEnd of conversion on ADC2\nCH0\nCH0\n...\n...\n8 ADCCLK\ncycles\nEnd of conversion on ADC1\nConversion\nSampling\nai16056\n" }, { "page_number": 411, "page_indices": { "start_index": 874201, "end_index": 876214 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 411 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.9 Multi ADC mode", 404 ], [ 3, "13.9.4 Alternate trigger mode", 411 ] ], "page_content": "RM0090 Rev 21\n411/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\na given time). In this case, the delay becomes the sampling time + 2 ADC clock cycles. For \ninstance, if DELAY = 5 clock cycles and the sampling takes 15 clock cycles on the three \nADCs, then 17 clock cycles separate the conversions on ADC1, ADC2 and ADC3).\nIf the CONT bit is set on ADC1, ADC2 and ADC3, the selected regular channels of all ADCs \nare continuously converted.\nNote:\nIf the conversion sequence is interrupted (for instance when DMA end of transfer occurs), \nthe multi-ADC sequencer must be reset by configuring it in independent mode first (bits \nDUAL[4:0] = 00000) before reprogramming the interleaved mode.\nIn this mode a DMA request is generated each time 2 data items are available, (if the \nDMA[1:0] bits in the ADC_CCR register are equal to 0b10). The request first transfers the \nfirst converted data stored in the lower half-word of the ADC_CDR 32-bit register to SRAM, \nthen it transfers the second converted data stored in ADC_CDR’s upper half-word to SRAM. \nThe sequence is the following:\n•\n1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0] \n•\n2nd request: ADC_CDR[31:0] = ADC1_DR[15:0] | ADC3_DR[15:0] \n•\n3rd request: ADC_CDR[31:0] = ADC3_DR[15:0] | ADC2_DR[15:0] \n•\n4th request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0], ...\nFigure 57. Interleaved mode on 1 channel in continuous conversion mode: triple ADC \nmode\n13.9.4 \nAlternate trigger mode\nThis mode can be started only on an injected group. The source of external trigger comes \nfrom the injected group multiplexer of ADC1.\nNote:\nRegular conversions can be enabled on one or all ADCs. In this case the regular \nconversions are independent of each other. A regular conversion is interrupted when the \nADC1\nADC2\nTrigger\nEnd of conversion on ADC3\n...\n...\n6 ADCCLK\ncycles\nEnd of conversion on ADC1\n...\nADC3\nEnd of conversion on ADC2\nDMA request every 2 conversions\nCH0\nConversion\nSampling\nai16058\nCH0\nCH0\nCH0\nCH0\nCH0\nCH0\nCH0\nCH0\n" }, { "page_number": 412, "page_indices": { "start_index": 876214, "end_index": 878336 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 412 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.9 Multi ADC mode", 404 ], [ 3, "13.9.4 Alternate trigger mode", 411 ], [ 4, "Dual ADC mode", 412 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n412/1757\nRM0090 Rev 21\nADC has to perform an injected conversion. It is resumed when the injected conversion is \nfinished.\nIf the conversion sequence is interrupted (for instance when DMA end of transfer occurs), \nthe multi-ADC sequencer must be reset by configuring it in independent mode first (bits \nDUAL[4:0] = 00000) before reprogramming the interleaved mode.\nThe time interval between 2 trigger events must be greater than or equal to 1 ADC clock \nperiod. The minimum time interval between 2 trigger events that start conversions on the \nsame ADC is the same as in the single ADC mode.\nDual ADC mode\n•\nWhen the 1st trigger occurs, all injected ADC1 channels in the group are converted\n•\nWhen the 2nd trigger occurs, all injected ADC2 channels in the group are converted\n•\nand so on\nA JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group \nhave been converted.\nA JEOC interrupt, if enabled, is generated after all injected ADC2 channels in the group \nhave been converted.\nIf another external trigger occurs after all injected channels in the group have been \nconverted then the alternate trigger process restarts by converting the injected ADC1 \nchannels in the group.\nFigure 58. Alternate trigger: injected group of each ADC\nIf the injected discontinuous mode is enabled for both ADC1 and ADC2:\n•\nWhen the 1st trigger occurs, the first injected ADC1 channel is converted.\n•\nWhen the 2nd trigger occurs, the first injected ADC2 channel are converted \n•\nand so on\nA JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group \nhave been converted.\nA JEOC interrupt, if enabled, is generated after all injected ADC2 channels in the group \nhave been converted.\nIf another external trigger occurs after all injected channels in the group have been \nconverted then the alternate trigger process restarts.\nADC1\nADC2\n1st trigger\n2nd trigger\n3rd trigger\n4th trigger\n(n)th trigger\n(n+1)th trigger\nEOC, JEOC\non ADC1\nEOC, JEOC\non ADC1\n. . .\nEOC, JEOC\non ADC2\nEOC, JEOC\non ADC2\nConversion\nSampling\nai16059\n" }, { "page_number": 413, "page_indices": { "start_index": 878336, "end_index": 880223 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 413 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.9 Multi ADC mode", 404 ], [ 3, "13.9.4 Alternate trigger mode", 411 ], [ 4, "Triple ADC mode", 413 ], [ 3, "13.9.5 Combined regular/injected simultaneous mode", 413 ] ], "page_content": "RM0090 Rev 21\n413/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\nFigure 59. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode\nTriple ADC mode\n•\nWhen the 1st trigger occurs, all injected ADC1 channels in the group are converted.\n•\nWhen the 2nd trigger occurs, all injected ADC2 channels in the group are converted.\n•\nWhen the 3rd trigger occurs, all injected ADC3 channels in the group are converted.\n•\nand so on\nA JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group \nhave been converted.\nA JEOC interrupt, if enabled, is generated after all injected ADC2 channels in the group \nhave been converted.\nA JEOC interrupt, if enabled, is generated after all injected ADC3 channels in the group \nhave been converted.\nIf another external trigger occurs after all injected channels in the group have been \nconverted then the alternate trigger process restarts by converting the injected ADC1 \nchannels in the group.\nFigure 60. Alternate trigger: injected group of each ADC\n13.9.5 \nCombined regular/injected simultaneous mode\nIt is possible to interrupt the simultaneous conversion of a regular group to start the \nsimultaneous conversion of an injected group.\nNote:\nIn combined regular/injected simultaneous mode, one must convert sequences with the \nsame length or ensure that the interval between triggers is longer than the long conversion \ntime of the 2 sequences (Dual ADC mode) /3 sequences (Triple ADC mode). Otherwise, the \nADC1\nADC2\n1st trigger\nConversion\nSampling\n2nd trigger\n3rd trigger\n4th trigger\n5th trigger\n6th trigger\n7th trigger\n8th trigger\nJEOC on ADC2\nJEOC on ADC1\nai16060\nADC1\nADC2\n1st trigger\nConversion\nSampling\n2nd trigger\n4th trigger\n3rd trigger\n(n)th trigger\n(n+1)th trigger\nEOC, JEOC\non ADC1\nEOC, JEOC\non ADC1\n. . .\nEOC, JEOC\non ADC2\nEOC, JEOC\non ADC3\n5th trigger\n(n+2)th trigger\nai16061\n" }, { "page_number": 414, "page_indices": { "start_index": 880223, "end_index": 882077 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 414 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.9 Multi ADC mode", 404 ], [ 3, "13.9.6 Combined regular simultaneous + alternate trigger mode", 414 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n414/1757\nRM0090 Rev 21\nADC with the shortest sequence may restart while the ADC with the longest sequence is \ncompleting the previous conversions.\n13.9.6 \nCombined regular simultaneous + alternate trigger mode\nIt is possible to interrupt the simultaneous conversion of a regular group to start the alternate \ntrigger conversion of an injected group. Figure 61 shows the behavior of an alternate trigger \ninterrupting a simultaneous regular conversion.\nThe injected alternate conversion is immediately started after the injected event. If regular \nconversion is already running, in order to ensure synchronization after the injected \nconversion, the regular conversion of all (master/slave) ADCs is stopped and resumed \nsynchronously at the end of the injected conversion.\nNote:\nIn combined regular simultaneous + alternate trigger mode, one must convert sequences \nwith the same length or ensure that the interval between triggers is longer than the long \nconversion time of the 2 sequences (Dual ADC mode) /3 sequences (Triple ADC mode). \nOtherwise, the ADC with the shortest sequence may restart while the ADC with the longest \nsequence is completing the previous conversions.\nIf the conversion sequence is interrupted (for instance when DMA end of transfer occurs), \nthe multi-ADC sequencer must be reset by configuring it in independent mode first (bits \nDUAL[4:0] = 00000) before reprogramming the interleaved mode.\nFigure 61. Alternate + regular simultaneous\nIf a trigger occurs during an injected conversion that has interrupted a regular conversion, it \nis ignored. Figure 62 shows the behavior in this case (2nd trigger is ignored).\nADC1 reg\nCH0\nCH1\nCH2\nCH0\nCH2\nCH3\nCH0\nADC1 inj\nADC2 reg\nADC2 inj\n1st trigger\n2nd trigger\nsynchro not lost\nCH3\nCH5\nCH6\nCH6\nCH7\nCH3\nCH4\nCH7\nCH8\nai16062\n" }, { "page_number": 415, "page_indices": { "start_index": 882077, "end_index": 883468 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 415 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.10 Temperature sensor", 415 ], [ 3, "Main features", 415 ] ], "page_content": "RM0090 Rev 21\n415/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\nFigure 62. Case of trigger occurring during injected conversion\n13.10 \nTemperature sensor\nThe temperature sensor can be used to measure the junction temperature (TJ) of the \ndevice.\n•\nOn STM32F40x and STM32F41x devices, the temperature sensor is internally \nconnected to ADC1_IN16 channel which is used to convert the sensor output voltage \nto a digital value.\n•\nOn STM32F42x and STM32F43x devices, the temperature sensor is internally \nconnected to the same input channel, ADC1_IN18, as VBAT: ADC1_IN18 is used to \nconvert the sensor output voltage or VBAT into a digital value. Only one conversion, \ntemperature sensor or VBAT, must be selected at a time. When the temperature sensor \nand the VBAT conversion are set simultaneously, only the VBAT conversion is \nperformed.\nFigure 63 shows the block diagram of the temperature sensor.\nWhen not in use, the sensor can be put in power down mode.\nNote:\nThe TSVREFE bit must be set to enable the conversion of both internal channels: the \nADC1_IN16 or ADC1_IN18 (temperature sensor) and the ADC1_IN17 (VREFINT). \nMain features\n•\nSupported temperature range: –40 to 125 °C\n•\nPrecision: ±1.5 °C \nADC1 reg\nCH0\nCH1\nCH2\nCH0\nCH2\nCH3\nCH0\nADC1 inj\nADC2 reg\nADC2 inj\n1st trigger\n2nd trigger\nCH3\nCH5\nCH6\nCH6\nCH7\nCH3\nCH4\nCH7\nCH8\nai16063\nCH0\n2nd trigger\n3rd trigger\n" }, { "page_number": 416, "page_indices": { "start_index": 883468, "end_index": 885142 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 416 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.10 Temperature sensor", 415 ], [ 3, "Reading the temperature", 416 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n416/1757\nRM0090 Rev 21\nFigure 63. Temperature sensor and VREFINT channel block diagram \n1.\nVSENSE is input to ADC1_IN16 for the STM23F40x and STM32F41x devices and to ADC1_IN18 for the \nSTM32F42x and STM32F43x devices.\nReading the temperature\nTo use the sensor:\n3. \nSelect ADC1_IN16 or ADC1_IN18 input channel. \n4. \nSelect a sampling time greater than the minimum sampling time specified in the \ndatasheet.\n5. \nSet the TSVREFE bit in the ADC_CCR register to wake up the temperature sensor \nfrom power down mode\n6. \nStart the ADC conversion by setting the SWSTART bit (or by external trigger)\n7. \nRead the resulting VSENSE data in the ADC data register\n8. \nCalculate the temperature using the following formula:\nTemperature (in °C) = {(VSENSE – V25) / Avg_Slope} + 25\nWhere:\n–\nV25 = VSENSE value for 25° C\n–\nAvg_Slope = average slope of the temperature vs. VSENSE curve (given in mV/°C \nor µV/°C)\nRefer to the datasheet’s electrical characteristics section for the actual values of V25 \nand Avg_Slope.\nNote:\nThe sensor has a startup time after waking from power down mode before it can output \nVSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize \nthe delay, the ADON and TSVREFE bits should be set at the same time.\nThe temperature sensor output voltage changes linearly with temperature. The offset of this \nlinear function depends on each chip due to process variation (up to 45 °C from one chip to \nanother).\nMS31830V1\nTemperature \nsensor\nVSENSE\nTSVREFE control bit\nADC1 \nAddress/data bus\n \nVREFINT\nADC1_IN16/\nADC1_IN18(1)\nInternal\npower block\nADC1_IN17\nconverted data\n" }, { "page_number": 417, "page_indices": { "start_index": 885142, "end_index": 886980 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 417 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.11 Battery charge monitoring", 417 ], [ 2, "13.12 ADC interrupts", 417 ] ], "page_content": "RM0090 Rev 21\n417/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\nThe internal temperature sensor is more suited for applications that detect temperature \nvariations instead of absolute temperatures. If accurate temperature reading is required, an \nexternal temperature sensor should be used.\n13.11 \nBattery charge monitoring\nThe VBATE bit in the ADC_CCR register is used to switch to the battery voltage. As the \nVBAT voltage could be higher than VDDA, to ensure the correct operation of the ADC, the \nVBAT pin is internally connected to a bridge divider.\nWhen the VBATE is set, the bridge is automatically enabled to connect:\n•\nVBAT/2 to the ADC1_IN18 input channel, on STM32F40xx and STM32F41xx devices\n•\nVBAT/4 to the ADC1_IN18 input channel, on STM32F42xx and STM32F43xx devices\nNote:\nOn STM32F42xx and STM32F43xx devices, VBAT and temperature sensor are connected \nto the same ADC internal channel (ADC1_IN18). Only one conversion, either temperature \nsensor or VBAT, must be selected at a time. When both conversion are enabled \nsimultaneously, only the VBAT conversion is performed.\n13.12 \nADC interrupts\nAn interrupt can be produced on the end of conversion for regular and injected groups, \nwhen the analog watchdog status bit is set and when the overrun status bit is set. Separate \ninterrupt enable bits are available for flexibility.\nTwo other flags are present in the ADC_SR register, but there is no interrupt associated with \nthem:\n•\nJSTRT (Start of conversion for channels of an injected group)\n•\nSTRT (Start of conversion for channels of a regular group)\n \nTable 71. ADC interrupts\nInterrupt event\nEvent flag\nEnable control bit\nEnd of conversion of a regular group\nEOC\nEOCIE\nEnd of conversion of an injected group\nJEOC\nJEOCIE\nAnalog watchdog status bit is set\nAWD\nAWDIE\nOverrun\nOVR\nOVRIE\n" }, { "page_number": 418, "page_indices": { "start_index": 886980, "end_index": 889215 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 418 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.1 ADC status register (ADC_SR)", 418 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n418/1757\nRM0090 Rev 21\n13.13 \nADC registers\nRefer to Section 1.1: List of abbreviations for registers for registers for a list of abbreviations \nused in register descriptions.\nThe peripheral registers must be written at word level (32 bits). Read accesses can be done \nby bytes (8 bits), half-words (16 bits) or words (32 bits). \n13.13.1 \nADC status register (ADC_SR)\nAddress offset: 0x00\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOVR\nSTRT\nJSTRT\nJEOC \nEOC\nAWD\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nBits 31:6 Reserved, must be kept at reset value.\nBit 5 OVR: Overrun\nThis bit is set by hardware when data are lost (either in single mode or in dual/triple mode). It \nis cleared by software. Overrun detection is enabled only when DMA = 1 or EOCS = 1.\n0: No overrun occurred\n1: Overrun has occurred\nBit 4 STRT: Regular channel start flag\nThis bit is set by hardware when regular channel conversion starts. It is cleared by software.\n0: No regular channel conversion started\n1: Regular channel conversion has started\nBit 3 JSTRT: Injected channel start flag\nThis bit is set by hardware when injected group conversion starts. It is cleared by software.\n0: No injected group conversion started\n1: Injected group conversion has started\nBit 2 JEOC: Injected channel end of conversion\nThis bit is set by hardware at the end of the conversion of all injected channels in the group. \nIt is cleared by software.\n0: Conversion is not complete\n1: Conversion complete\nBit 1 EOC: Regular channel end of conversion\nThis bit is set by hardware at the end of the conversion of a regular group of channels. It is \ncleared by software or by reading the ADC_DR register.\n0: Conversion not complete (EOCS=0), or sequence of conversions not complete (EOCS=1)\n1: Conversion complete (EOCS=0), or sequence of conversions complete (EOCS=1)\nBit 0 AWD: Analog watchdog flag\nThis bit is set by hardware when the converted voltage crosses the values programmed in \nthe ADC_LTR and ADC_HTR registers. It is cleared by software.\n0: No analog watchdog event occurred\n1: Analog watchdog event occurred\n" }, { "page_number": 419, "page_indices": { "start_index": 889215, "end_index": 891170 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 419 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.2 ADC control register 1 (ADC_CR1)", 419 ] ], "page_content": "RM0090 Rev 21\n419/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.13.2 \nADC control register 1 (ADC_CR1)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nOVRIE\nRES\nAWDEN\nJAWDEN\nReserved\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDISCNUM[2:0]\nJDISCE\nN\nDISC \nEN\nJAUTO AWDSG\nL\nSCAN\nJEOCIE\nAWDIE\nEOCIE\nAWDCH[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:27 Reserved, must be kept at reset value.\nBit 26 OVRIE: Overrun interrupt enable\nThis bit is set and cleared by software to enable/disable the Overrun interrupt. \n0: Overrun interrupt disabled\n1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.\nBits 25:24 RES[1:0]: Resolution\nThese bits are written by software to select the resolution of the conversion.\n00: 12-bit (15 ADCCLK cycles)\n01: 10-bit (13 ADCCLK cycles)\n10: 8-bit (11 ADCCLK cycles)\n11: 6-bit (9 ADCCLK cycles)\nBit 23 AWDEN: Analog watchdog enable on regular channels\nThis bit is set and cleared by software.\n0: Analog watchdog disabled on regular channels\n1: Analog watchdog enabled on regular channels\nBit 22 JAWDEN: Analog watchdog enable on injected channels\nThis bit is set and cleared by software.\n0: Analog watchdog disabled on injected channels\n1: Analog watchdog enabled on injected channels\nBits 21:16 Reserved, must be kept at reset value.\nBits 15:13 DISCNUM[2:0]: Discontinuous mode channel count\nThese bits are written by software to define the number of regular channels to be converted \nin discontinuous mode, after receiving an external trigger.\n000: 1 channel\n001: 2 channels\n...\n111: 8 channels\nBit 12 JDISCEN: Discontinuous mode on injected channels\nThis bit is set and cleared by software to enable/disable discontinuous mode on the injected \nchannels of a group.\n0: Discontinuous mode on injected channels disabled\n1: Discontinuous mode on injected channels enabled\n" }, { "page_number": 420, "page_indices": { "start_index": 891170, "end_index": 893745 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 420 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.2 ADC control register 1 (ADC_CR1)", 419 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n420/1757\nRM0090 Rev 21\nBit 11 DISCEN: Discontinuous mode on regular channels\nThis bit is set and cleared by software to enable/disable Discontinuous mode on regular \nchannels.\n0: Discontinuous mode on regular channels disabled\n1: Discontinuous mode on regular channels enabled\nBit 10 JAUTO: Automatic injected group conversion\nThis bit is set and cleared by software to enable/disable automatic injected group conversion \nafter regular group conversion.\n0: Automatic injected group conversion disabled\n1: Automatic injected group conversion enabled\nBit 9 AWDSGL: Enable the watchdog on a single channel in scan mode\nThis bit is set and cleared by software to enable/disable the analog watchdog on the channel \nidentified by the AWDCH[4:0] bits.\n0: Analog watchdog enabled on all channels\n1: Analog watchdog enabled on a single channel\nBit 8 SCAN: Scan mode\nThis bit is set and cleared by software to enable/disable the Scan mode. In Scan mode, the \ninputs selected through the ADC_SQRx or ADC_JSQRx registers are converted.\n0: Scan mode disabled\n1: Scan mode enabled\nNote: An EOC interrupt is generated if the EOCIE bit is set:\n–\nAt the end of each regular group sequence if the EOCS bit is cleared to 0\n–\nAt the end of each regular channel conversion if the EOCS bit is set to 1\nNote: A JEOC interrupt is generated only on the end of conversion of the last channel if the \nJEOCIE bit is set.\nBit 7 JEOCIE: Interrupt enable for injected channels\nThis bit is set and cleared by software to enable/disable the end of conversion interrupt for \ninjected channels.\n0: JEOC interrupt disabled\n1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.\nBit 6 AWDIE: Analog watchdog interrupt enable\nThis bit is set and cleared by software to enable/disable the analog watchdog interrupt.\n0: Analog watchdog interrupt disabled\n1: Analog watchdog interrupt enabled\nBit 5 EOCIE: Interrupt enable for EOC\nThis bit is set and cleared by software to enable/disable the end of conversion interrupt.\n0: EOC interrupt disabled\n1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.\nBits 4:0 AWDCH[4:0]: Analog watchdog channel select bits\nThese bits are set and cleared by software. They select the input channel to be guarded by \nthe analog watchdog.\nNote: 00000: ADC analog input Channel0\n00001: ADC analog input Channel1\n...\n01111: ADC analog input Channel15\n10000: ADC analog input Channel16\n10001: ADC analog input Channel17\n10010: ADC analog input Channel18\nOther values reserved\n" }, { "page_number": 421, "page_indices": { "start_index": 893745, "end_index": 895506 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 421 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.3 ADC control register 2 (ADC_CR2)", 421 ] ], "page_content": "RM0090 Rev 21\n421/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.13.3 \nADC control register 2 (ADC_CR2)\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nreserved\nSWST\nART\nEXTEN\nEXTSEL[3:0]\nreserved\nJSWST\nART\nJEXTEN\nJEXTSEL[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nreserved\nALIGN\nEOCS\nDDS\nDMA\nReserved\nCONT\nADON\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBit 30 SWSTART: Start conversion of regular channels\nThis bit is set by software to start conversion and cleared by hardware as soon as the \nconversion starts.\n0: Reset state\n1: Starts conversion of regular channels\nNote: This bit can be set only when ADON = 1 otherwise no conversion is launched.\nBits 29:28 EXTEN: External trigger enable for regular channels\nThese bits are set and cleared by software to select the external trigger polarity and enable \nthe trigger of a regular group.\n00: Trigger detection disabled\n01: Trigger detection on the rising edge\n10: Trigger detection on the falling edge\n11: Trigger detection on both the rising and falling edges\nBits 27:24 EXTSEL[3:0]: External event select for regular group\nThese bits select the external event used to trigger the start of conversion of a regular group:\n0000: Timer 1 CC1 event\n0001: Timer 1 CC2 event\n0010: Timer 1 CC3 event\n0011: Timer 2 CC2 event\n0100: Timer 2 CC3 event\n0101: Timer 2 CC4 event\n0110: Timer 2 TRGO event\n0111: Timer 3 CC1 event\n1000: Timer 3 TRGO event\n1001: Timer 4 CC4 event\n1010: Timer 5 CC1 event\n1011: Timer 5 CC2 event\n1100: Timer 5 CC3 event\n1101: Timer 8 CC1 event\n1110: Timer 8 TRGO event\n1111: EXTI line11\nBit 23 Reserved, must be kept at reset value.\n" }, { "page_number": 422, "page_indices": { "start_index": 895506, "end_index": 897725 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 422 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.3 ADC control register 2 (ADC_CR2)", 421 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n422/1757\nRM0090 Rev 21\nBit 22 JSWSTART: Start conversion of injected channels\nThis bit is set by software and cleared by hardware as soon as the conversion starts.\n0: Reset state\n1: Starts conversion of injected channels\nNote: This bit can be set only when ADON = 1 otherwise no conversion is launched.\nBits 21:20 JEXTEN: External trigger enable for injected channels\nThese bits are set and cleared by software to select the external trigger polarity and enable \nthe trigger of an injected group.\n00: Trigger detection disabled\n01: Trigger detection on the rising edge\n10: Trigger detection on the falling edge\n11: Trigger detection on both the rising and falling edges\nBits 19:16 JEXTSEL[3:0]: External event select for injected group\nThese bits select the external event used to trigger the start of conversion of an injected \ngroup.\n0000: Timer 1 CC4 event\n0001: Timer 1 TRGO event\n0010: Timer 2 CC1 event\n0011: Timer 2 TRGO event\n0100: Timer 3 CC2 event\n0101: Timer 3 CC4 event\n0110: Timer 4 CC1 event\n0111: Timer 4 CC2 event\n1000: Timer 4 CC3 event\n1001: Timer 4 TRGO event\n1010: Timer 5 CC4 event\n1011: Timer 5 TRGO event\n1100: Timer 8 CC2 event\n1101: Timer 8 CC3 event\n1110: Timer 8 CC4 event\n1111: EXTI line15\nBits 15:12 Reserved, must be kept at reset value.\nBit 11 ALIGN: Data alignment\nThis bit is set and cleared by software. Refer to Figure 48 and Figure 49.\n0: Right alignment\n1: Left alignment\nBit 10 EOCS: End of conversion selection\nThis bit is set and cleared by software.\n0: The EOC bit is set at the end of each sequence of regular conversions. Overrun detection \nis enabled only if DMA=1.\n1: The EOC bit is set at the end of each regular conversion. Overrun detection is enabled.\nBit 9 DDS: DMA disable selection (for single ADC mode)\nThis bit is set and cleared by software.\n0: No new DMA request is issued after the last transfer (as configured in the DMA controller)\n1: DMA requests are issued as long as data are converted and DMA=1\nBit 8 DMA: Direct memory access mode (for single ADC mode)\nThis bit is set and cleared by software. Refer to the DMA controller chapter for more details.\n0: DMA mode disabled\n1: DMA mode enabled\n" }, { "page_number": 423, "page_indices": { "start_index": 897725, "end_index": 899412 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 423 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.4 ADC sample time register 1 (ADC_SMPR1)", 423 ], [ 3, "13.13.5 ADC sample time register 2 (ADC_SMPR2)", 423 ] ], "page_content": "RM0090 Rev 21\n423/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.13.4 \nADC sample time register 1 (ADC_SMPR1)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n \n \n13.13.5 \nADC sample time register 2 (ADC_SMPR2)\nAddress offset: 0x10\nReset value: 0x0000 0000\n \nBits 7:2 Reserved, must be kept at reset value.\nBit 1 CONT: Continuous conversion\nThis bit is set and cleared by software. If it is set, conversion takes place continuously until it \nis cleared.\n0: Single conversion mode\n1: Continuous conversion mode \nBit 0 ADON: A/D Converter ON / OFF\nThis bit is set and cleared by software.\nNote: 0: Disable ADC conversion and go to power down mode\n1: Enable ADC\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nSMP18[2:0]\nSMP17[2:0]\nSMP16[2:0]\nSMP15[2:1]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSMP15_0\nSMP14[2:0]\nSMP13[2:0]\nSMP12[2:0]\nSMP11[2:0]\nSMP10[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31: 27 Reserved, must be kept at reset value.\nBits 26:0 SMPx[2:0]: Channel x sampling time selection\nThese bits are written by software to select the sampling time individually for each channel. \nDuring sampling cycles, the channel selection bits must remain unchanged.\nNote: 000: 3 cycles\n001: 15 cycles\n010: 28 cycles\n011: 56 cycles\n100: 84 cycles\n101: 112 cycles\n110: 144 cycles\n111: 480 cycles\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nSMP9[2:0]\nSMP8[2:0]\nSMP7[2:0]\nSMP6[2:0]\nSMP5[2:1]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSMP\n5_0\nSMP4[2:0]\nSMP3[2:0]\nSMP2[2:0]\nSMP1[2:0]\nSMP0[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 424, "page_indices": { "start_index": 899412, "end_index": 900990 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 424 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)", 424 ], [ 3, "13.13.7 ADC watchdog higher threshold register (ADC_HTR)", 424 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n424/1757\nRM0090 Rev 21\n \n13.13.6 \nADC injected channel data offset register x (ADC_JOFRx) (x=1..4)\nAddress offset: 0x14-0x20\nReset value: 0x0000 0000\n \n \n13.13.7 \nADC watchdog higher threshold register (ADC_HTR)\nAddress offset: 0x24\nReset value: 0x0000 0FFF\n \n \nBits 31:30 Reserved, must be kept at reset value.\nBits 29:0 SMPx[2:0]: Channel x sampling time selection\nThese bits are written by software to select the sampling time individually for each channel. \nDuring sample cycles, the channel selection bits must remain unchanged.\nNote: 000: 3 cycles\n001: 15 cycles\n010: 28 cycles\n011: 56 cycles\n100: 84 cycles\n101: 112 cycles\n110: 144 cycles\n111: 480 cycles\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nJOFFSETx[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 JOFFSETx[11:0]: Data offset for injected channel x\nThese bits are written by software to define the offset to be subtracted from the raw \nconverted data when converting injected channels. The conversion result can be read from \nin the ADC_JDRx registers.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nHT[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 HT[11:0]: Analog watchdog higher threshold\nThese bits are written by software to define the higher threshold for the analog watchdog.\n" }, { "page_number": 425, "page_indices": { "start_index": 900990, "end_index": 902942 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 425 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.8 ADC watchdog lower threshold register (ADC_LTR)", 425 ], [ 3, "13.13.9 ADC regular sequence register 1 (ADC_SQR1)", 425 ] ], "page_content": "RM0090 Rev 21\n425/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\nNote:\nThe software can write to these registers when an ADC conversion is ongoing. The \nprogrammed value is effective when the next conversion is complete. Writing to this register \nis performed with a write delay that can create uncertainty on the effective time at which the \nnew value is programmed.\n13.13.8 \nADC watchdog lower threshold register (ADC_LTR)\nAddress offset: 0x28\nReset value: 0x0000 0000\n \n \nNote:\nThe software can write to these registers when an ADC conversion is ongoing. The \nprogrammed value is effective when the next conversion is complete. Writing to this register \nis performed with a write delay that can create uncertainty on the effective time at which the \nnew value is programmed.\n13.13.9 \nADC regular sequence register 1 (ADC_SQR1)\nAddress offset: 0x2C\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLT[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 LT[11:0]: Analog watchdog lower threshold\nThese bits are written by software to define the lower threshold for the analog watchdog.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nL[3:0]\nSQ16[4:1]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSQ16_0\nSQ15[4:0]\nSQ14[4:0]\nSQ13[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value.\nBits 23:20 L[3:0]: Regular channel sequence length\nThese bits are written by software to define the total number of conversions in the regular \nchannel conversion sequence.\n0000: 1 conversion\n0001: 2 conversions\n...\n1111: 16 conversions\nBits 19:15 SQ16[4:0]: 16th conversion in regular sequence\nThese bits are written by software with the channel number (0..18) assigned as the 16th in \nthe conversion sequence.\n" }, { "page_number": 426, "page_indices": { "start_index": 902942, "end_index": 904722 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 426 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.10 ADC regular sequence register 2 (ADC_SQR2)", 426 ], [ 3, "13.13.11 ADC regular sequence register 3 (ADC_SQR3)", 426 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n426/1757\nRM0090 Rev 21\n13.13.10 ADC regular sequence register 2 (ADC_SQR2)\nAddress offset: 0x30\nReset value: 0x0000 0000\n \n \n13.13.11 ADC regular sequence register 3 (ADC_SQR3)\nAddress offset: 0x34\nReset value: 0x0000 0000\n \n \nBits 14:10 SQ15[4:0]: 15th conversion in regular sequence\nBits 9:5 SQ14[4:0]: 14th conversion in regular sequence\nBits 4:0 SQ13[4:0]: 13th conversion in regular sequence\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nSQ12[4:0]\nSQ11[4:0]\nSQ10[4:1]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSQ10_0\nSQ9[4:0]\nSQ8[4:0]\nSQ7[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBits 29:26 SQ12[4:0]: 12th conversion in regular sequence\nThese bits are written by software with the channel number (0..18) assigned as the 12th in \nthe sequence to be converted. \nBits 24:20 SQ11[4:0]: 11th conversion in regular sequence\nBits 19:15 SQ10[4:0]: 10th conversion in regular sequence\nBits 14:10 SQ9[4:0]: 9th conversion in regular sequence\nBits 9:5 SQ8[4:0]: 8th conversion in regular sequence\nBits 4:0 SQ7[4:0]: 7th conversion in regular sequence\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nSQ6[4:0]\nSQ5[4:0]\nSQ4[4:1]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSQ4_0\nSQ3[4:0]\nSQ2[4:0]\nSQ1[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBits 29:25 SQ6[4:0]: 6th conversion in regular sequence\nThese bits are written by software with the channel number (0..18) assigned as the 6th in the \nsequence to be converted.\nBits 24:20 SQ5[4:0]: 5th conversion in regular sequence\n" }, { "page_number": 427, "page_indices": { "start_index": 904722, "end_index": 906674 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 427 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.12 ADC injected sequence register (ADC_JSQR)", 427 ] ], "page_content": "RM0090 Rev 21\n427/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.13.12 ADC injected sequence register (ADC_JSQR)\nAddress offset: 0x38\nReset value: 0x0000 0000\n \n \nNote:\nWhen JL[1:0]=3 (4 injected conversions in the sequencer), the ADC converts the channels \nin the following order: JSQ1[4:0], JSQ2[4:0], JSQ3[4:0], and JSQ4[4:0].\nWhen JL=2 (3 injected conversions in the sequencer), the ADC converts the channels in the \nfollowing order: JSQ2[4:0], JSQ3[4:0], and JSQ4[4:0].\nWhen JL=1 (2 injected conversions in the sequencer), the ADC converts the channels in \nstarting from JSQ3[4:0], and then JSQ4[4:0].\nWhen JL=0 (1 injected conversion in the sequencer), the ADC converts only JSQ4[4:0] \nchannel.\nBits 19:15 SQ4[4:0]: 4th conversion in regular sequence\nBits 14:10 SQ3[4:0]: 3rd conversion in regular sequence\nBits 9:5 SQ2[4:0]: 2nd conversion in regular sequence\nBits 4:0 SQ1[4:0]: 1st conversion in regular sequence\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nJL[1:0]\nJSQ4[4:1]\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nJSQ4[0]\nJSQ3[4:0]\nJSQ2[4:0]\nJSQ1[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:22 Reserved, must be kept at reset value.\nBits 21:20 JL[1:0]: Injected sequence length\nThese bits are written by software to define the total number of conversions in the injected \nchannel conversion sequence.\n00: 1 conversion\n01: 2 conversions\n10: 3 conversions\n11: 4 conversions\nBits 19:15 JSQ4[4:0]: 4th conversion in injected sequence (when JL[1:0]=3, see note below)\nThese bits are written by software with the channel number (0..18) assigned as the 4th in the \nsequence to be converted.\nBits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence (when JL[1:0]=3, see note below)\nBits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence (when JL[1:0]=3, see note below)\nBits 4:0 JSQ1[4:0]: 1st conversion in injected sequence (when JL[1:0]=3, see note below)\n" }, { "page_number": 428, "page_indices": { "start_index": 906674, "end_index": 907774 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 428 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4)", 428 ], [ 3, "13.13.14 ADC regular data register (ADC_DR)", 428 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n428/1757\nRM0090 Rev 21\n13.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4)\nAddress offset: 0x3C - 0x48\nReset value: 0x0000 0000\n \n \n13.13.14 ADC regular data register (ADC_DR)\nAddress offset: 0x4C\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nJDATA[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 JDATA[15:0]: Injected data\nThese bits are read-only. They contain the conversion result from injected channel x. The \ndata are left -or right-aligned as shown in Figure 48 and Figure 49.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATA[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 DATA[15:0]: Regular data\nThese bits are read-only. They contain the conversion result from the regular \nchannels. The data are left- or right-aligned as shown in Figure 48 and \nFigure 49.\n" }, { "page_number": 429, "page_indices": { "start_index": 907774, "end_index": 909923 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 429 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.15 ADC Common status register (ADC_CSR)", 429 ] ], "page_content": "RM0090 Rev 21\n429/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.13.15 ADC Common status register (ADC_CSR)\nAddress offset: 0x00 (this offset address is relative to ADC1 base address + 0x300)\nReset value: 0x0000 0000\nThis register provides an image of the status bits of the different ADCs. Nevertheless it is \nread-only and does not allow to clear the different status bits. Instead each status bit must \nbe cleared by writing it to 0 in the corresponding ADC_SR register.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nOVR3\nSTRT3\nJSTRT3 JEOC 3\nEOC3\nAWD3\nADC3\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOVR2\nSTRT2\nJSTRT\n2\nJEOC2 EOC2\nAWD2\nReserved\nOVR1\nSTRT1\nJSTRT1 JEOC 1\nEOC1\nAWD1\nADC2\nADC1\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:22 Reserved, must be kept at reset value.\nBit 21 OVR3: Overrun flag of ADC3\nThis bit is a copy of the OVR bit in the ADC3_SR register.\nBit 20 STRT3: Regular channel Start flag of ADC3\nThis bit is a copy of the STRT bit in the ADC3_SR register.\nBit 19 JSTRT3: Injected channel Start flag of ADC3\nThis bit is a copy of the JSTRT bit in the ADC3_SR register.\nBit 18 JEOC3: Injected channel end of conversion of ADC3\nThis bit is a copy of the JEOC bit in the ADC3_SR register.\nBit 17 EOC3: End of conversion of ADC3\nThis bit is a copy of the EOC bit in the ADC3_SR register.\nBit 16 AWD3: Analog watchdog flag of ADC3\nThis bit is a copy of the AWD bit in the ADC3_SR register.\nBits 15:14 Reserved, must be kept at reset value.\nBit 13 OVR2: Overrun flag of ADC2\nThis bit is a copy of the OVR bit in the ADC2_SR register.\nBit 12 STRT2: Regular channel Start flag of ADC2\nThis bit is a copy of the STRT bit in the ADC2_SR register.\nBit 11 JSTRT2: Injected channel Start flag of ADC2\nThis bit is a copy of the JSTRT bit in the ADC2_SR register.\nBit 10 JEOC2: Injected channel end of conversion of ADC2\nThis bit is a copy of the JEOC bit in the ADC2_SR register.\nBit 9 EOC2: End of conversion of ADC2\nThis bit is a copy of the EOC bit in the ADC2_SR register.\nBit 8 AWD2: Analog watchdog flag of ADC2\nThis bit is a copy of the AWD bit in the ADC2_SR register.\n" }, { "page_number": 430, "page_indices": { "start_index": 909923, "end_index": 911740 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 430 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.16 ADC common control register (ADC_CCR)", 430 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n430/1757\nRM0090 Rev 21\n13.13.16 ADC common control register (ADC_CCR)\nAddress offset: 0x04 (this offset address is relative to ADC1 base address + 0x300)\nReset value: 0x0000 0000\n \n \nBits 7:6 Reserved, must be kept at reset value.\nBit 5 OVR1: Overrun flag of ADC1\nThis bit is a copy of the OVR bit in the ADC1_SR register.\nBit 4 STRT1: Regular channel Start flag of ADC1\nThis bit is a copy of the STRT bit in the ADC1_SR register.\nBit 3 JSTRT1: Injected channel Start flag of ADC1\nThis bit is a copy of the JSTRT bit in the ADC1_SR register.\nBit 2 JEOC1: Injected channel end of conversion of ADC1\nThis bit is a copy of the JEOC bit in the ADC1_SR register.\nBit 1 EOC1: End of conversion of ADC1\nThis bit is a copy of the EOC bit in the ADC1_SR register.\nBit 0 AWD1: Analog watchdog flag of ADC1\nThis bit is a copy of the AWD bit in the ADC1_SR register.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTSVREFE VBATE\nReserved\nADCPRE\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDMA[1:0]\nDDS\nRes.\nDELAY[3:0]\nReserved\nMULTI[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value.\nBit 23 TSVREFE: Temperature sensor and VREFINT enable\nThis bit is set and cleared by software to enable/disable the temperature sensor and the \nVREFINT channel.\n0: Temperature sensor and VREFINT channel disabled\n1: Temperature sensor and VREFINT channel enabled\nNote: On STM32F42x and STM32F43x devices, VBATE must be disabled when TSVREFE is \nset. If both bits are set, only the VBAT conversion is performed.\nBit 22 VBATE: VBAT enable\nThis bit is set and cleared by software to enable/disable the VBAT channel.\n0: VBAT channel disabled\n1: VBAT channel enabled\nBits 21:18 Reserved, must be kept at reset value.\n" }, { "page_number": 431, "page_indices": { "start_index": 911740, "end_index": 912956 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 431 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.16 ADC common control register (ADC_CCR)", 430 ] ], "page_content": "RM0090 Rev 21\n431/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\nBits 17:16 ADCPRE: ADC prescaler\nSet and cleared by software to select the frequency of the clock to the ADC. The clock is \ncommon for all the ADCs.\nNote: 00: PCLK2 divided by 2\n01: PCLK2 divided by 4\n10: PCLK2 divided by 6\n11: PCLK2 divided by 8\nBits 15:14 DMA: Direct memory access mode for multi ADC mode\nThis bit-field is set and cleared by software. Refer to the DMA controller section for more \ndetails.\n00: DMA mode disabled\n01: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)\n10: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)\n11: DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2)\nBit 13 DDS: DMA disable selection (for multi-ADC mode)\nThis bit is set and cleared by software.\n0: No new DMA request is issued after the last transfer (as configured in the DMA \ncontroller). DMA bits are not cleared by hardware, however they must have been cleared \nand set to the wanted mode by software before new DMA requests can be generated.\n1: DMA requests are issued as long as data are converted and DMA = 01, 10 or 11.\nBit 12 Reserved, must be kept at reset value.\n" }, { "page_number": 432, "page_indices": { "start_index": 912956, "end_index": 914440 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 432 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.16 ADC common control register (ADC_CCR)", 430 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n432/1757\nRM0090 Rev 21\nBit 11:8 DELAY: Delay between 2 sampling phases\nSet and cleared by software. These bits are used in dual or triple interleaved modes.\n0000: 5 * TADCCLK\n0001: 6 * TADCCLK\n0010: 7 * TADCCLK\n...\n1111: 20 * TADCCLK\nBits 7:5 Reserved, must be kept at reset value.\nBits 4:0 MULTI[4:0]: Multi ADC mode selection\nThese bits are written by software to select the operating mode.\n– All the ADCs independent:\n00000: Independent mode\n– 00001 to 01001: Dual mode, ADC1 and ADC2 working together, ADC3 is independent\n00001: Combined regular simultaneous + injected simultaneous mode\n00010: Combined regular simultaneous + alternate trigger mode\n00011: Reserved\n00101: Injected simultaneous mode only\n00110: Regular simultaneous mode only\n00111: interleaved mode only\n01001: Alternate trigger mode only\n– 10001 to 11001: Triple mode: ADC1, 2 and 3 working together\n10001: Combined regular simultaneous + injected simultaneous mode\n10010: Combined regular simultaneous + alternate trigger mode\n10011: Reserved\n10101: Injected simultaneous mode only\n10110: Regular simultaneous mode only\n10111: interleaved mode only\n11001: Alternate trigger mode only\nAll other combinations are reserved and must not be programmed\nNote: In multi mode, a change of channel configuration generates an abort that can cause a \nloss of synchronization. It is recommended to disable the multi ADC mode before any \nconfiguration change.\n" }, { "page_number": 433, "page_indices": { "start_index": 914440, "end_index": 915752 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 433 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.17 ADC common regular data register for dual and triple modes (ADC_CDR)", 433 ], [ 3, "13.13.18 ADC register map", 433 ] ], "page_content": "RM0090 Rev 21\n433/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n13.13.17 ADC common regular data register for dual and triple modes\n(ADC_CDR)\nAddress offset: 0x08 (this offset address is relative to ADC1 base address + 0x300)\nReset value: 0x0000 0000\n \n \n13.13.18 ADC register map\nThe following table summarizes the ADC registers.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATA2[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATA1[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 DATA2[15:0]: 2nd data item of a pair of regular conversions\n– In dual mode, these bits contain the regular data of ADC2. Refer to Dual ADC mode.\n– In triple mode, these bits contain alternatively the regular data of ADC2, ADC1 and ADC3. \nRefer to Triple ADC mode.\nBits 15:0 DATA1[15:0]: 1st data item of a pair of regular conversions\n– In dual mode, these bits contain the regular data of ADC1. Refer to Dual ADC mode\n– In triple mode, these bits contain alternatively the regular data of ADC1, ADC3 and ADC2. \nRefer to Triple ADC mode.\nTable 72. ADC global register map\nOffset\nRegister\n0x000 - 0x04C\nADC1\n0x050 - 0x0FC\nReserved\n0x100 - 0x14C\nADC2\n0x118 - 0x1FC\nReserved\n0x200 - 0x24C\nADC3\n0x250 - 0x2FC\nReserved\n0x300 - 0x308\nCommon registers\n" }, { "page_number": 434, "page_indices": { "start_index": 915752, "end_index": 918052 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 434 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.18 ADC register map", 433 ] ], "page_content": "Analog-to-digital converter (ADC)\nRM0090\n434/1757\nRM0090 Rev 21\n \nTable 73. ADC register map and reset values for each ADC\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nADC_SR\nReserved\nOVR\nSTRT\nJSTRT\nJEOC\nEOC\nAWD\nReset value\n0\n0\n0\n0\n0\n0\n0x04\nADC_CR1\nReserved\nOVRIE\nRES[1:0]\nAWDEN\nJAWDEN\nReserved\nDISC \nNUM [2:0]\nJDISCEN\nDISCEN\nJAUTO\nAWD SGL\nSCAN\nJEOCIE\nAWDIE\nEOCIE\nAWDCH[4:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nADC_CR2\nRe\nse\nrv\ned\nSWSTART\nEXTEN[1:0]\nEXTSEL [3:0]\nRe\nse\nrv\ned\nJSWSTART\nJEXTEN[1:0]\nJEXTSEL \n[3:0]\nReserved\nALIGN\nEOCS\nDDS\nDMA\nReserved\nCONT\nADON\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nADC_SMPR1\nSample time bits SMPx_x\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nADC_SMPR2\nSample time bits SMPx_x\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nADC_JOFR1\nReserved\nJOFFSET1[11:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x18\nADC_JOFR2\nReserved\nJOFFSET2[11:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nADC_JOFR3\nReserved\nJOFFSET3[11:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nADC_JOFR4\nReserved\nJOFFSET4[11:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x24\nADC_HTR\nReserved\nHT[11:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x28\nADC_LTR\nReserved\nLT[11:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x2C\nADC_SQR1\nReserved\nL[3:0]\nRegular channel sequence SQx_x bits\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x30\nADC_SQR2\nReserved\nRegular channel sequence SQx_x bits\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x34\nADC_SQR3\nReserved\nRegular channel sequence SQx_x bits\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x38\nADC_JSQR\nReserved\nJL[1:0]\nInjected channel sequence JSQx_x bits\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x3C\nADC_JDR1\nReserved\nJDATA[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x40\nADC_JDR2\nReserved\nJDATA[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x44\nADC_JDR3\nReserved\nJDATA[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x48\nADC_JDR4\nReserved\nJDATA[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x4C\nADC_DR\nReserved\nRegular DATA[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n" }, { "page_number": 435, "page_indices": { "start_index": 918052, "end_index": 918863 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 435 }, "toc_details": [ [ 1, "13 Analog-to-digital converter (ADC)", 391 ], [ 2, "13.13 ADC registers", 418 ], [ 3, "13.13.18 ADC register map", 433 ] ], "page_content": "RM0090 Rev 21\n435/1757\nRM0090\nAnalog-to-digital converter (ADC)\n435\n \nRefer to Section 2.3: Memory map for the register boundary addresses.\nTable 74. ADC register map and reset values (common ADC registers)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nADC_CSR\nReserved\nOVR\nSTRT\nJSTRT\nJEOC\nEOC\nAWD\nReserved\nOVR\nSTRT\nJSTRT\nJEOC\nEOC\nAWD\nReserved\nOVR\nSTRT\nJSTRT\nJEOC\nEOC\nAWD\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nADC3\nADC2\nADC1\n0x04\nADC_CCR\nReserved\nTSVREFE\nVBATE\nReserved\nADCPRE[1:0]\nDMA[1:0]\nDDS\nReserved\nDELAY [3:0]\nReserved\nMULTI [4:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nADC_CDR\nRegular DATA2[15:0]\nRegular DATA1[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n" }, { "page_number": 436, "page_indices": { "start_index": 918863, "end_index": 920124 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 436 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.1 DAC introduction", 436 ], [ 2, "14.2 DAC main features", 436 ] ], "page_content": "Digital-to-analog converter (DAC)\nRM0090\n436/1757\nRM0090 Rev 21\n14 \nDigital-to-analog converter (DAC)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n14.1 \nDAC introduction\nThe DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be \nconfigured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In \n12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each \nwith its own converter. In dual DAC channel mode, conversions could be done \nindependently or simultaneously when both channels are grouped together for synchronous \nupdate operations. An input reference pin, VREF+ (shared with ADC) is available for better \nresolution.\n14.2 \nDAC main features\n•\nTwo DAC converters: one output channel each\n•\nLeft or right data alignment in 12-bit mode\n•\nSynchronized update capability\n•\nNoise-wave generation\n•\nTriangular-wave generation\n•\nDual DAC channel for independent or simultaneous conversions\n•\nDMA capability for each channel\n•\nDMA underrun error detection\n•\nExternal triggers for conversion\n•\nInput voltage reference, VREF+\nFigure 64 shows the block diagram of a DAC channel and Table 75 gives the pin \ndescription.\n" }, { "page_number": 437, "page_indices": { "start_index": 920124, "end_index": 921155 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 437 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.2 DAC main features", 436 ] ], "page_content": "RM0090 Rev 21\n437/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\nFigure 64. DAC channel block diagram \n \nNote:\nOnce the DAC channelx is enabled, the corresponding GPIO pin (PA4 or PA5) is \nautomatically connected to the analog converter output (DAC_OUTx). In order to avoid \nparasitic consumption, the PA4 or PA5 pin should first be configured to analog (AIN).\nTable 75. DAC pins\nName\nSignal type\nRemarks\nVREF+\nInput, analog reference \npositive\nThe higher/positive reference voltage for the DAC,\n1.8 V ≤ VREF+ ≤ VDDA\nVDDA\nInput, analog supply\nAnalog power supply\nVSSA\nInput, analog supply ground\nGround for analog power supply\nDAC_OUTx\nAnalog output signal\nDAC channelx analog output\nVDDA\nVSSA\nVREF+\nDAC_OUTx\nControl logicx\nDHRx\n12-bit\n12-bit\nLFSRx\ntrianglex\nDM A requestx\nTSELx[2:0] bits\nTIM4_TRGO\nTIM5_TRGO\nTIM6_TRGO\nTIM7_TRGO\nTIM2_TRGO\nTIM8_TRGO\nEXTI_9\nDMAENx\nTENx\nMAMPx[3:0] bits\nWAVENx[1:0] bits\nSWTRIGx\nDORx\nDigital-to-analog\nconverterx\n12-bit\nDAC control register\nai14708b\nTrigger selectorx\n" }, { "page_number": 438, "page_indices": { "start_index": 921155, "end_index": 922839 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 438 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.3 DAC functional description", 438 ], [ 3, "14.3.1 DAC channel enable", 438 ], [ 3, "14.3.2 DAC output buffer enable", 438 ], [ 3, "14.3.3 DAC data format", 438 ] ], "page_content": "Digital-to-analog converter (DAC)\nRM0090\n438/1757\nRM0090 Rev 21\n14.3 \nDAC functional description\n14.3.1 \nDAC channel enable\nEach DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR \nregister. The DAC channel is then enabled after a startup time tWAKEUP.\nNote:\nThe ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital \ninterface is enabled even if the ENx bit is reset.\n14.3.2 \nDAC output buffer enable\nThe DAC integrates two output buffers that can be used to reduce the output impedance, \nand to drive external loads directly without having to add an external operational amplifier. \nEach DAC channel output buffer can be enabled and disabled using the corresponding \nBOFFx bit in the DAC_CR register.\n14.3.3 \nDAC data format\nDepending on the selected configuration mode, the data have to be written into the specified \nregister as described below:\n•\nSingle DAC channelx, there are three possibilities:\n–\n8-bit right alignment: the software has to load data into the DAC_DHR8Rx [7:0] \nbits (stored into the DHRx[11:4] bits)\n–\n12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4] \nbits (stored into the DHRx[11:0] bits)\n–\n12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0] \nbits (stored into the DHRx[11:0] bits)\nDepending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and \nstored into the corresponding DHRx (data holding registerx, which are internal non-memory-\nmapped registers). The DHRx register is then loaded into the DORx register either \nautomatically, by software trigger or by an external event trigger.\n" }, { "page_number": 439, "page_indices": { "start_index": 922839, "end_index": 925007 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 439 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.3 DAC functional description", 438 ], [ 3, "14.3.4 DAC conversion", 439 ] ], "page_content": "RM0090 Rev 21\n439/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\nFigure 65. Data registers in single DAC channel mode \n•\nDual DAC channels, there are three possibilities:\n–\n8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD \n[7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded \ninto the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits)\n–\n12-bit left alignment: data for DAC channel1 to be loaded into the DAC_DHR12LD \n[15:4] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be \nloaded into the DAC_DHR12LD [31:20] bits (stored into the DHR2[11:0] bits)\n–\n12-bit right alignment: data for DAC channel1 to be loaded into the \nDAC_DHR12RD [11:0] bits (stored into the DHR1[11:0] bits) and data for DAC \nchannel2 to be loaded into the DAC_DHR12LD [27:16] bits (stored into the \nDHR2[11:0] bits)\nDepending on the loaded DAC_DHRyyyD register, the data written by the user is shifted \nand stored into DHR1 and DHR2 (data holding registers, which are internal non-memory-\nmapped registers). The DHR1 and DHR2 registers are then loaded into the DOR1 and \nDOR2 registers, respectively, either automatically, by software trigger or by an external \nevent trigger.\nFigure 66. Data registers in dual DAC channel mode\n14.3.4 \nDAC conversion\nThe DAC_DORx cannot be written directly and any data transfer to the DAC channelx must \nbe performed by loading the DAC_DHRx register (write to DAC_DHR8Rx, DAC_DHR12Lx, \nDAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12LD).\nData stored in the DAC_DHRx register are automatically transferred to the DAC_DORx \nregister after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR \nregister is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR \nregister is set) and a trigger occurs, the transfer is performed three APB1 clock cycles later.\n31\n24\n15\n7\n0\n8-bit right aligned\n12-bit left aligned\n12-bit right aligned\nai14710b\n31\n24\n15\n7\n0\n8-bit right aligned\n12-bit left aligned\n12-bit right aligned\nai14709\n31\n24\n15\n7\n0\n8-bit right aligned\n12-bit left aligned\n12-bit right aligned\nai14709b\n" }, { "page_number": 440, "page_indices": { "start_index": 925007, "end_index": 926568 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 440 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.3 DAC functional description", 438 ], [ 3, "14.3.5 DAC output voltage", 440 ], [ 3, "14.3.6 DAC trigger selection", 440 ] ], "page_content": "Digital-to-analog converter (DAC)\nRM0090\n440/1757\nRM0090 Rev 21\nWhen DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage \nbecomes available after a time tSETTLING that depends on the power supply voltage and the \nanalog output load.\nFigure 67. Timing diagram for conversion with trigger disabled TEN = 0\n14.3.5 \nDAC output voltage\nDigital inputs are converted to output voltages on a linear conversion between 0 and VREF+.\nThe analog output voltages on each DAC channel pin are determined by the following \nequation:\n14.3.6 \nDAC trigger selection\nIf the TENx control bit is set, conversion can then be triggered by an external event (timer \ncounter, external interrupt line). The TSELx[2:0] control bits determine which out of eight \npossible events trigger conversion as shown in Table 76.\n \nEach time a DAC interface detects a rising edge on the selected timer TRGO output, or on \nthe selected external interrupt line 9, the last data stored into the DAC_DHRx register are \ntransferred into the DAC_DORx register. The DAC_DORx register is updated three APB1 \ncycles after the trigger occurs.\nAPB1_CLK\n0x1AC\n0x1AC\ntSETTLING\nDHR\nDOR\nOutput voltage\navailable on DAC_OUT pin\nai14711c\nDACoutput \nVREF\nDOR\n4096\n-------------\n×\n=\nTable 76. External triggers\nSource\nType\nTSEL[2:0]\nTimer 6 TRGO event\nInternal signal from on-chip \ntimers\n000\nTimer 8 TRGO event\n001\nTimer 7 TRGO event\n010\nTimer 5 TRGO event\n011\nTimer 2 TRGO event\n100\nTimer 4 TRGO event\n101\nEXTI line9\nExternal pin\n110\nSWTRIG\nSoftware control bit\n111\n" }, { "page_number": 441, "page_indices": { "start_index": 926568, "end_index": 929008 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 441 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.3 DAC functional description", 438 ], [ 3, "14.3.7 DMA request", 441 ], [ 4, "DMA underrun", 441 ], [ 3, "14.3.8 Noise generation", 441 ] ], "page_content": "RM0090 Rev 21\n441/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\nIf the software trigger is selected, the conversion starts once the SWTRIG bit is set. \nSWTRIG is reset by hardware once the DAC_DORx register has been loaded with the \nDAC_DHRx register contents.\nNote:\nTSELx[2:0] bit cannot be changed when the ENx bit is set.\nWhen software trigger is selected, the transfer from the DAC_DHRx register to the \nDAC_DORx register takes only one APB1 clock cycle.\n14.3.7 \nDMA request\nEach DAC channel has a DMA capability. Two DMA channels are used to service DAC \nchannel DMA requests.\nA DAC DMA request is generated when an external trigger (but not a software trigger) \noccurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred \ninto the DAC_DORx register.\nIn dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one \nDMA request is needed, the user should set only the corresponding DMAENx bit. In this \nway, the application can manage both DAC channels in dual mode by using one DMA \nrequest and a unique DMA channel.\nDMA underrun\nThe DAC DMA request is not queued so that if a second external trigger arrives before the \nacknowledgement for the first external trigger is received (first request), then no new \nrequest is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register \nis set, reporting the error condition. DMA data transfers are then disabled and no further \nDMA request is treated. The DAC channelx continues to convert old data.\nThe software should clear the DMAUDRx flag by writing “1”, clear the DMAEN bit of the \nused DMA stream and re-initialize both DMA and DAC channelx to restart the transfer \ncorrectly. The software should modify the DAC trigger conversion frequency or lighten the \nDMA workload to avoid a new DMA underrun. Finally, the DAC conversion could be \nresumed by enabling both DMA data transfer and conversion trigger.\nFor each DAC channelx, an interrupt is also generated if its corresponding DMAUDRIEx bit \nin the DAC_CR register is enabled.\n14.3.8 \nNoise generation\nIn order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift \nregister) is available. DAC noise generation is selected by setting WAVEx[1:0] to “01”. The \npreloaded value in LFSR is 0xAAA. This register is updated three APB1 clock cycles after \neach trigger event, following a specific calculation algorithm.\n" }, { "page_number": 442, "page_indices": { "start_index": 929008, "end_index": 930554 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 442 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.3 DAC functional description", 438 ], [ 3, "14.3.9 Triangle-wave generation", 442 ] ], "page_content": "Digital-to-analog converter (DAC)\nRM0090\n442/1757\nRM0090 Rev 21\nFigure 68. DAC LFSR register calculation algorithm\nThe LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in \nthe DAC_CR register, is added up to the DAC_DHRx contents without overflow and this \nvalue is then stored into the DAC_DORx register.\nIf LFSR is 0x0000, a ‘1 is injected into it (antilock-up mechanism).\nIt is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.\nFigure 69. DAC conversion (SW trigger enabled) with LFSR wave generation\nNote:\nThe DAC trigger must be enabled for noise generation by setting the TENx bit in the \nDAC_CR register.\n14.3.9 \nTriangle-wave generation\nIt is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. \nDAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is \nconfigured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter \nis incremented three APB1 clock cycles after each trigger event. The value of this counter is \nthen added to the DAC_DHRx register without overflow and the sum is stored into the \nDAC_DORx register. The triangle counter is incremented as long as it is less than the \nmaximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is \nreached, the counter is decremented down to 0, then incremented again and so on.\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n12\nNOR\nX12\nX0\nX\nX4\nX6\nXOR\nai14713c\nAPB1_CLK\n0x00\n0xAAA\nDHR\nDOR\nai14714b\n0xD55\nSWTRIG\n" }, { "page_number": 443, "page_indices": { "start_index": 930554, "end_index": 931749 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 443 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.4 Dual DAC channel conversion", 443 ] ], "page_content": "RM0090 Rev 21\n443/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\nIt is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits.\nFigure 70. DAC triangle wave generation\nFigure 71. DAC conversion (SW trigger enabled) with triangle wave generation\nNote:\nThe DAC trigger must be enabled for noise generation by setting the TENx bit in the \nDAC_CR register.\nThe MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot \nbe changed.\n14.4 \nDual DAC channel conversion\nTo efficiently use the bus bandwidth in applications that require the two DAC channels at the \nsame time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A \nunique register access is then required to drive both DAC channels at the same time.\nEleven possible conversion modes are possible using the two DAC channels and these dual \nregisters. All the conversion modes can nevertheless be obtained using separate DHRx \nregisters if needed.\nAll modes are described in the paragraphs below.\nMAMPx[3:0] max amplitude\n+ DAC_DHRx base value\nDAC_DHRx base value\nIncrementation\nai14715c\nDecrementation\n0\nAPB1_CLK\n0x00\n0xAAA\nDHR\nDOR\nai14714b\n0xD55\nSWTRIG\n" }, { "page_number": 444, "page_indices": { "start_index": 931749, "end_index": 934431 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 444 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.4 Dual DAC channel conversion", 443 ], [ 3, "14.4.1 Independent trigger without wave generation", 444 ], [ 3, "14.4.2 Independent trigger with single LFSR generation", 444 ], [ 3, "14.4.3 Independent trigger with different LFSR generation", 444 ] ], "page_content": "Digital-to-analog converter (DAC)\nRM0090\n444/1757\nRM0090 Rev 21\n14.4.1 \nIndependent trigger without wave generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure different trigger sources by setting different values in the TSEL1[2:0] and \nTSEL2[2:0] bits\n•\nLoad the dual DAC channel data into the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nWhen a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1 \n(three APB1 clock cycles later).\nWhen a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2 \n(three APB1 clock cycles later). \n14.4.2 \nIndependent trigger with single LFSR generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure different trigger sources by setting different values in the TSEL1[2:0] and \nTSEL2[2:0] bits\n•\nConfigure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask \nvalue in the MAMPx[3:0] bits\n•\nLoad the dual DAC channel data into the desired DHR register (DHR12RD, DHR12LD \nor DHR8RD)\nWhen a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to \nthe DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles \nlater). Then the LFSR1 counter is updated.\nWhen a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to \nthe DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles \nlater). Then the LFSR2 counter is updated.\n14.4.3 \nIndependent trigger with different LFSR generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure different trigger sources by setting different values in the TSEL1[2:0] and \nTSEL2[2:0] bits\n•\nConfigure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR masks \nvalues in the MAMP1[3:0] and MAMP2[3:0] bits\n•\nLoad the dual DAC channel data into the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nWhen a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by \nMAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 \n(three APB1 clock cycles later). Then the LFSR1 counter is updated.\nWhen a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by \nMAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 \n(three APB1 clock cycles later). Then the LFSR2 counter is updated.\n" }, { "page_number": 445, "page_indices": { "start_index": 934431, "end_index": 937054 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 445 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.4 Dual DAC channel conversion", 443 ], [ 3, "14.4.4 Independent trigger with single triangle generation", 445 ], [ 3, "14.4.5 Independent trigger with different triangle generation", 445 ], [ 3, "14.4.6 Simultaneous software start", 445 ] ], "page_content": "RM0090 Rev 21\n445/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\n14.4.4 \nIndependent trigger with single triangle generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure different trigger sources by setting different values in the TSEL1[2:0] and \nTSEL2[2:0] bits\n•\nConfigure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum \namplitude value in the MAMPx[3:0] bits\n•\nLoad the dual DAC channel data into the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nWhen a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same \ntriangle amplitude, is added to the DHR1 register and the sum is transferred into \nDAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then \nupdated.\nWhen a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same \ntriangle amplitude, is added to the DHR2 register and the sum is transferred into \nDAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then \nupdated.\n14.4.5 \nIndependent trigger with different triangle generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure different trigger sources by setting different values in the TSEL1[2:0] and \nTSEL2[2:0] bits\n•\nConfigure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum \namplitude values in the MAMP1[3:0] and MAMP2[3:0] bits\n•\nLoad the dual DAC channel data into the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nWhen a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with a triangle \namplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is \ntransferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle \ncounter is then updated.\nWhen a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle \namplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is \ntransferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle \ncounter is then updated.\n14.4.6 \nSimultaneous software start\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nLoad the dual DAC channel data to the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nIn this configuration, one APB1 clock cycle later, the DHR1 and DHR2 registers are \ntransferred into DAC_DOR1 and DAC_DOR2, respectively.\n" }, { "page_number": 446, "page_indices": { "start_index": 937054, "end_index": 939633 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 446 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.4 Dual DAC channel conversion", 443 ], [ 3, "14.4.7 Simultaneous trigger without wave generation", 446 ], [ 3, "14.4.8 Simultaneous trigger with single LFSR generation", 446 ], [ 3, "14.4.9 Simultaneous trigger with different LFSR generation", 446 ] ], "page_content": "Digital-to-analog converter (DAC)\nRM0090\n446/1757\nRM0090 Rev 21\n14.4.7 \nSimultaneous trigger without wave generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure the same trigger source for both DAC channels by setting the same value in \nthe TSEL1[2:0] and TSEL2[2:0] bits\n•\nLoad the dual DAC channel data to the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nWhen a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and \nDAC_DOR2, respectively (after three APB1 clock cycles).\n14.4.8 \nSimultaneous trigger with single LFSR generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure the same trigger source for both DAC channels by setting the same value in \nthe TSEL1[2:0] and TSEL2[2:0] bits\n•\nConfigure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask \nvalue in the MAMPx[3:0] bits\n•\nLoad the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or \nDHR8RD)\nWhen a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 \nregister and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The \nLFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask, \nis added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 \nclock cycles later). The LFSR2 counter is then updated.\n14.4.9 \nSimultaneous trigger with different LFSR generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure the same trigger source for both DAC channels by setting the same value in \nthe TSEL1[2:0] and TSEL2[2:0] bits\n•\nConfigure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR mask \nvalues using the MAMP1[3:0] and MAMP2[3:0] bits\n•\nLoad the dual DAC channel data into the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nWhen a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is \nadded to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock \ncycles later). The LFSR1 counter is then updated.\nAt the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to \nthe DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles \nlater). The LFSR2 counter is then updated.\n" }, { "page_number": 447, "page_indices": { "start_index": 939633, "end_index": 941873 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 447 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.4 Dual DAC channel conversion", 443 ], [ 3, "14.4.10 Simultaneous trigger with single triangle generation", 447 ], [ 3, "14.4.11 Simultaneous trigger with different triangle generation", 447 ] ], "page_content": "RM0090 Rev 21\n447/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\n14.4.10 \nSimultaneous trigger with single triangle generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure the same trigger source for both DAC channels by setting the same value in \nthe TSEL1[2:0] and TSEL2[2:0] bits\n•\nConfigure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum \namplitude value using the MAMPx[3:0] bits\n•\nLoad the dual DAC channel data into the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nWhen a trigger arrives, the DAC channel1 triangle counter, with the same triangle \namplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three \nAPB1 clock cycles later). The DAC channel1 triangle counter is then updated.\nAt the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is \nadded to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock \ncycles later). The DAC channel2 triangle counter is then updated.\n14.4.11 \nSimultaneous trigger with different triangle generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n•\nSet the two DAC channel trigger enable bits TEN1 and TEN2\n•\nConfigure the same trigger source for both DAC channels by setting the same value in \nthe TSEL1[2:0] and TSEL2[2:0] bits\n•\nConfigure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum \namplitude values in the MAMP1[3:0] and MAMP2[3:0] bits\n•\nLoad the dual DAC channel data into the desired DHR register (DAC_DHR12RD, \nDAC_DHR12LD or DAC_DHR8RD)\nWhen a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude \nconfigured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into \nDAC_DOR1 (three APB1 clock cycles later). Then the DAC channel1 triangle counter is \nupdated.\nAt the same time, the DAC channel2 triangle counter, with a triangle amplitude configured \nby MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 \n(three APB1 clock cycles later). Then the DAC channel2 triangle counter is updated.\n" }, { "page_number": 448, "page_indices": { "start_index": 941873, "end_index": 944204 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 448 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.5 DAC registers", 448 ], [ 3, "14.5.1 DAC control register (DAC_CR)", 448 ] ], "page_content": "Digital-to-analog converter (DAC)\nRM0090\n448/1757\nRM0090 Rev 21\n14.5 \nDAC registers\nRefer to Section 1.1: List of abbreviations for registers for registers for a list of abbreviations \nused in register descriptions.\nThe peripheral registers have to be accessed by words (32 bits).\n14.5.1 \nDAC control register (DAC_CR)\nAddress offset: 0x00\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nDMAU\nDRIE2\nDMA \nEN2\nMAMP2[3:0]\nWAVE2[1:0]\nTSEL2[2:0]\nTEN2\nBOFF2\nEN2\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDMAU\nDRIE1\nDMA \nEN1\nMAMP1[3:0]\nWAVE1[1:0]\nTSEL1[2:0]\nTEN1\nBOFF1\nEN1\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBits 29 DMAUDRIE2: DAC channel2 DMA underrun interrupt enable\nThis bit is set and cleared by software.\n0: DAC channel2 DMA underrun interrupt disabled\n1: DAC channel2 DMA underrun interrupt enabled\nBit 28 DMAEN2: DAC channel2 DMA enable\nThis bit is set and cleared by software.\n0: DAC channel2 DMA mode disabled\n1: DAC channel2 DMA mode enabled\nBits 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector\nThese bits are written by software to select mask in wave generation mode or amplitude in \ntriangle generation mode.\n0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1\n0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3\n0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7\n0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15\n0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31\n0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63\n0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127\n0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255\n1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511\n1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023\n1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047\n≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095\nBits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable\nThese bits are set/reset by software.\n00: wave generation disabled \n01: Noise wave generation enabled \n1x: Triangle wave generation enabled\nNote: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)\n" }, { "page_number": 449, "page_indices": { "start_index": 944204, "end_index": 945972 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 449 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.5 DAC registers", 448 ], [ 3, "14.5.1 DAC control register (DAC_CR)", 448 ] ], "page_content": "RM0090 Rev 21\n449/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\nBits 21:19 TSEL2[2:0]: DAC channel2 trigger selection\nThese bits select the external event used to trigger DAC channel2\n000: Timer 6 TRGO event\n001: Timer 8 TRGO event\n010: Timer 7 TRGO event\n011: Timer 5 TRGO event\n100: Timer 2 TRGO event\n101: Timer 4 TRGO event\n110: External line9\n111: Software trigger \nNote: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).\nBit 18 TEN2: DAC channel2 trigger enable\nThis bit is set and cleared by software to enable/disable DAC channel2 trigger \n0: DAC channel2 trigger disabled and data written into the DAC_DHRx register are \ntransferred one APB1 clock cycle later to the DAC_DOR2 register\n1: DAC channel2 trigger enabled and data from the DAC_DHRx register are transferred \nthree APB1 clock cycles later to the DAC_DOR2 register\nNote: When software trigger is selected, the transfer from the DAC_DHRx register to the \nDAC_DOR2 register takes only one APB1 clock cycle.\nBit 17 BOFF2: DAC channel2 output buffer disable\nThis bit is set and cleared by software to enable/disable DAC channel2 output buffer.\n0: DAC channel2 output buffer enabled\n1: DAC channel2 output buffer disabled\nBit 16 EN2: DAC channel2 enable\nThis bit is set and cleared by software to enable/disable DAC channel2.\n0: DAC channel2 disabled\n1: DAC channel2 enabled\nBits 15:14 Reserved, must be kept at reset value.\nBit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable\nThis bit is set and cleared by software. \n0: DAC channel1 DMA Underrun Interrupt disabled\n1: DAC channel1 DMA Underrun Interrupt enabled\nBit 12 DMAEN1: DAC channel1 DMA enable\nThis bit is set and cleared by software.\n0: DAC channel1 DMA mode disabled\n1: DAC channel1 DMA mode enabled\n" }, { "page_number": 450, "page_indices": { "start_index": 945972, "end_index": 948553 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 450 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.5 DAC registers", 448 ], [ 3, "14.5.1 DAC control register (DAC_CR)", 448 ] ], "page_content": "Digital-to-analog converter (DAC)\nRM0090\n450/1757\nRM0090 Rev 21\nBits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector\nThese bits are written by software to select mask in wave generation mode or amplitude in \ntriangle generation mode.\n0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1\n0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3\n0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7\n0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15\n0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31\n0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63\n0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127\n0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255\n1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511\n1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023\n1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047\n≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095\nBits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable\nThese bits are set and cleared by software.\n00: wave generation disabled\n01: Noise wave generation enabled\n1x: Triangle wave generation enabled\nNote: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).\nBits 5:3 TSEL1[2:0]: DAC channel1 trigger selection\nThese bits select the external event used to trigger DAC channel1.\n000: Timer 6 TRGO event\n001: Timer 8 TRGO event\n010: Timer 7 TRGO event\n011: Timer 5 TRGO event\n100: Timer 2 TRGO event\n101: Timer 4 TRGO event\n110: External line9\n111: Software trigger\nNote: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).\nBit 2 TEN1: DAC channel1 trigger enable\nThis bit is set and cleared by software to enable/disable DAC channel1 trigger.\n0: DAC channel1 trigger disabled and data written into the DAC_DHRx register are \ntransferred one APB1 clock cycle later to the DAC_DOR1 register\n1: DAC channel1 trigger enabled and data from the DAC_DHRx register are transferred \nthree APB1 clock cycles later to the DAC_DOR1 register\nNote: When software trigger is selected, the transfer from the DAC_DHRx register to the \nDAC_DOR1 register takes only one APB1 clock cycle.\nBit 1 BOFF1: DAC channel1 output buffer disable\nThis bit is set and cleared by software to enable/disable DAC channel1 output buffer.\n0: DAC channel1 output buffer enabled\n1: DAC channel1 output buffer disabled\nBit 0 EN1: DAC channel1 enable\nThis bit is set and cleared by software to enable/disable DAC channel1.\n0: DAC channel1 disabled\n1: DAC channel1 enabled\n" }, { "page_number": 451, "page_indices": { "start_index": 948553, "end_index": 950064 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 451 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.5 DAC registers", 448 ], [ 3, "14.5.2 DAC software trigger register (DAC_SWTRIGR)", 451 ], [ 3, "14.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1)", 451 ] ], "page_content": "RM0090 Rev 21\n451/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\n14.5.2 \nDAC software trigger register (DAC_SWTRIGR)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n14.5.3 \nDAC channel1 12-bit right-aligned data holding register\n(DAC_DHR12R1)\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSWTRIG2 SWTRIG1\nw\nw\nBits 31:2 Reserved, must be kept at reset value.\nBit 1 SWTRIG2: DAC channel2 software trigger\nThis bit is set and cleared by software to enable/disable the software trigger.\n0: Software trigger disabled\n1: Software trigger enabled\nNote: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 \nregister value has been loaded into the DAC_DOR2 register.\nBit 0 SWTRIG1: DAC channel1 software trigger\nThis bit is set and cleared by software to enable/disable the software trigger.\n0: Software trigger disabled\n1: Software trigger enabled\nNote: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 \nregister value has been loaded into the DAC_DOR1 register.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDACC1DHR[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data \nThese bits are written by software which specifies 12-bit data for DAC channel1.\n" }, { "page_number": 452, "page_indices": { "start_index": 950064, "end_index": 951156 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 452 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.5 DAC registers", 448 ], [ 3, "14.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)", 452 ], [ 3, "14.5.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)", 452 ] ], "page_content": "Digital-to-analog converter (DAC)\nRM0090\n452/1757\nRM0090 Rev 21\n14.5.4 \nDAC channel1 12-bit left aligned data holding register\n(DAC_DHR12L1)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n \n \n14.5.5 \nDAC channel1 8-bit right aligned data holding register\n(DAC_DHR8R1)\nAddress offset: 0x10\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDACC1DHR[11:0]\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data\nThese bits are written by software which specifies 12-bit data for DAC channel1.\nBits 3:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDACC1DHR[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data\nThese bits are written by software which specifies 8-bit data for DAC channel1.\n" }, { "page_number": 453, "page_indices": { "start_index": 951156, "end_index": 952707 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 453 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.5 DAC registers", 448 ], [ 3, "14.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)", 453 ], [ 3, "14.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)", 453 ], [ 3, "14.5.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)", 453 ] ], "page_content": "RM0090 Rev 21\n453/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\n14.5.6 \nDAC channel2 12-bit right aligned data holding register\n(DAC_DHR12R2)\nAddress offset: 0x14\nReset value: 0x0000 0000\n \n14.5.7 \nDAC channel2 12-bit left aligned data holding register \n(DAC_DHR12L2)\nAddress offset: 0x18\nReset value: 0x0000 0000\n14.5.8 \nDAC channel2 8-bit right-aligned data holding register\n(DAC_DHR8R2)\nAddress offset: 0x1C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDACC2DHR[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data\nThese bits are written by software which specifies 12-bit data for DAC channel2.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDACC2DHR[11:0]\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data \nThese bits are written by software which specify 12-bit data for DAC channel2.\nBits 3:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDACC2DHR[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data\nThese bits are written by software which specifies 8-bit data for DAC channel2.\n" }, { "page_number": 454, "page_indices": { "start_index": 952707, "end_index": 954237 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 454 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.5 DAC registers", 448 ], [ 3, "14.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD)", 454 ], [ 3, "14.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD)", 454 ] ], "page_content": "Digital-to-analog converter (DAC)\nRM0090\n454/1757\nRM0090 Rev 21\n14.5.9 \nDual DAC 12-bit right-aligned data holding register\n(DAC_DHR12RD)\nAddress offset: 0x20\nReset value: 0x0000 0000\n14.5.10 \nDUAL DAC 12-bit left aligned data holding register\n(DAC_DHR12LD)\nAddress offset: 0x24\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nDACC2DHR[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDACC1DHR[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data\nThese bits are written by software which specifies 12-bit data for DAC channel2.\nBits 15:12 Reserved, must be kept at reset value.\nBits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data\nThese bits are written by software which specifies 12-bit data for DAC channel1.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDACC2DHR[11:0]\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDACC1DHR[11:0]\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data\nThese bits are written by software which specifies 12-bit data for DAC channel2.\nBits 19:16 Reserved, must be kept at reset value.\nBits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data\nThese bits are written by software which specifies 12-bit data for DAC channel1.\nBits 3:0 Reserved, must be kept at reset value.\n" }, { "page_number": 455, "page_indices": { "start_index": 954237, "end_index": 955828 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 455 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.5 DAC registers", 448 ], [ 3, "14.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD)", 455 ], [ 3, "14.5.12 DAC channel1 data output register (DAC_DOR1)", 455 ], [ 3, "14.5.13 DAC channel2 data output register (DAC_DOR2)", 455 ] ], "page_content": "RM0090 Rev 21\n455/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\n14.5.11 \nDUAL DAC 8-bit right aligned data holding register\n(DAC_DHR8RD)\nAddress offset: 0x28\nReset value: 0x0000 0000\n \n14.5.12 \nDAC channel1 data output register (DAC_DOR1)\nAddress offset: 0x2C\nReset value: 0x0000 0000\n \n \n14.5.13 \nDAC channel2 data output register (DAC_DOR2)\nAddress offset: 0x30\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDACC2DHR[7:0]\nDACC1DHR[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data\nThese bits are written by software which specifies 8-bit data for DAC channel2.\nBits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data \nThese bits are written by software which specifies 8-bit data for DAC channel1.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDACC1DOR[11:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:12 Reserved, must be kept at reset value.\nBit 11:0 DACC1DOR[11:0]: DAC channel1 data output\nThese bits are read-only, they contain data output for DAC channel1.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDACC2DOR[11:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 DACC2DOR[11:0]: DAC channel2 data output\nThese bits are read-only, they contain data output for DAC channel2.\n" }, { "page_number": 456, "page_indices": { "start_index": 955828, "end_index": 957694 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 456 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.5 DAC registers", 448 ], [ 3, "14.5.14 DAC status register (DAC_SR)", 456 ], [ 3, "14.5.15 DAC register map", 456 ] ], "page_content": "Digital-to-analog converter (DAC)\nRM0090\n456/1757\nRM0090 Rev 21\n14.5.14 \nDAC status register (DAC_SR)\nAddress offset: 0x34\nReset value: 0x0000 0000\n \n \n14.5.15 \nDAC register map\nTable 77 summarizes the DAC registers. \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved \nDMAUDR2\nReserved \nrc_w1\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved \nDMAUDR1\nReserved \nrc_w1\nBits 31:30 Reserved, must be kept at reset value.\nBit 29 DMAUDR2: DAC channel2 DMA underrun flag\nThis bit is set by hardware and cleared by software (by writing it to 1).\n0: No DMA underrun error condition occurred for DAC channel2\n1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is \ndriving DAC channel2 conversion at a frequency higher than the DMA service capability rate)\nBits 28:14 Reserved, must be kept at reset value.\nBit 13 DMAUDR1: DAC channel1 DMA underrun flag\nThis bit is set by hardware and cleared by software (by writing it to 1).\n0: No DMA underrun error condition occurred for DAC channel1\n1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is \ndriving DAC channel1 conversion at a frequency higher than the DMA service capability rate)\nBits 12:0 Reserved, must be kept at reset value.\nTable 77. DAC register map\nOffset Register\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nDAC_CR\nReserved\nDMAUDRIE2\nDMAEN2\nMAMP2[3:0]\nWAVE\n2[2:0]\nTSEL2[2:0]\nTEN2\nBOFF2\nEN2\nReserved\nDMAUDRIE1\nDMAEN1\nMAMP1[3:0]\nWAVE\n1[2:0]\nTSEL1[2\n:0]\nTEN1\nBOFF1\nEN1\n0x04\nDAC_\nSWTRIGR\nReserved\nSWTRIG2\nSWTRIG1\n0x08\nDAC_\nDHR12R1\nReserved\nDACC1DHR[11:0]\n0x0C\nDAC_\nDHR12L1\nReserved\nDACC1DHR[11:0]\nReserved\n0x10\nDAC_\nDHR8R1\nReserved\nDACC1DHR[7:0]\n0x14\nDAC_\nDHR12R2\nReserved\nDACC2DHR[11:0]\n0x18\nDAC_\nDHR12L2\nReserved\nDACC2DHR[11:0]\nReserved\n" }, { "page_number": 457, "page_indices": { "start_index": 957694, "end_index": 958354 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 457 }, "toc_details": [ [ 1, "14 Digital-to-analog converter (DAC)", 436 ], [ 2, "14.5 DAC registers", 448 ], [ 3, "14.5.15 DAC register map", 456 ] ], "page_content": "RM0090 Rev 21\n457/1757\nRM0090\nDigital-to-analog converter (DAC)\n457\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x1C\nDAC_\nDHR8R2\nReserved\nDACC2DHR[7:0]\n0x20\nDAC_\nDHR12RD\nReserved\nDACC2DHR[11:0]\nReserved\nDACC1DHR[11:0]\n0x24\nDAC_\nDHR12LD\nDACC2DHR[11:0]\nReserved\nDACC1DHR[11:0]\nReserved\n0x28\nDAC_\nDHR8RD\nReserved\nDACC2DHR[7:0]\nDACC1DHR[7:0]\n0x2C\nDAC_\nDOR1\nReserved\nDACC1DOR[11:0]\n0x30\nDAC_\nDOR2\nReserved\nDACC2DOR[11:0]\n0x34\nDAC_SR\nReserved\nDMAUDR2\nReserved\nDMAUDR1\nReserved\nTable 77. DAC register map (continued)\nOffset Register\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 458, "page_indices": { "start_index": 958354, "end_index": 959941 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 458 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.1 DCMI introduction", 458 ], [ 2, "15.2 DCMI main features", 458 ], [ 2, "15.3 DCMI pins", 458 ], [ 2, "15.4 DCMI clocks", 458 ] ], "page_content": "Digital camera interface (DCMI)\nRM0090\n458/1757\nRM0090 Rev 21\n15 \nDigital camera interface (DCMI)\nThis section applies to all STM32F4xx devices, unless otherwise specified.\n15.1 \nDCMI introduction\nThe digital camera is a synchronous parallel interface able to receive a high-speed data flow \nfrom an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data \nformats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).\nThis interface is for use with black & white cameras, X24 and X5 cameras, and it is \nassumed that all pre-processing like resizing is performed in the camera module.\n15.2 \nDCMI main features\n•\n8-, 10-, 12- or 14-bit parallel interface\n•\nEmbedded/external line and frame synchronization\n•\nContinuous or snapshot mode\n•\nCrop feature\n•\nSupports the following data formats:\n–\n8/10/12/14- bit progressive video: either monochrome or raw bayer\n–\nYCbCr 4:2:2 progressive video\n–\nRGB 565 progressive video\n–\nCompressed data: JPEG\n15.3 \nDCMI pins\nTable 78 shows the DCMI pins.\n \n15.4 \nDCMI clocks\nThe digital camera interface uses two clock domains PIXCLK and HCLK. The signals \ngenerated with PIXCLK are sampled on the rising edge of HCLK once they are stable. An \nenable signal is generated in the HCLK domain, to indicate that data coming from the \ncamera are stable and can be sampled. The minimum PIXCLK period must be higher than \n2.5 HCLK periods.\nTable 78. DCMI pins\nName\nSignal type\nD[0:13]\nData inputs\nHSYNC\nHorizontal synchronization input\nVSYNC\nVertical synchronization input\nPIXCLK\nPixel clock input\n" }, { "page_number": 459, "page_indices": { "start_index": 959941, "end_index": 961242 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 459 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.5 DCMI functional overview", 459 ] ], "page_content": "RM0090 Rev 21\n459/1757\nRM0090\nDigital camera interface (DCMI)\n482\n15.5 \nDCMI functional overview\nThe digital camera interface is a synchronous parallel interface that can receive high-speed \n(up to 54 Mbytes/s) data flows. It consists of up to 14 data lines (D13-D0) and a pixel clock \nline (PIXCLK). The pixel clock has a programmable polarity, so that data can be captured on \neither the rising or the falling edge of the pixel clock.\nThe data are packed into a 32-bit data register (DCMI_DR) and then transferred through a \ngeneral-purpose DMA channel. The image buffer is managed by the DMA, not by the \ncamera interface.\nThe data received from the camera can be organized in lines/frames (raw YUB/RGB/Bayer \nmodes) or can be a sequence of JPEG images. To enable JPEG image reception, the JPEG \nbit (bit 3 of DCMI_CR register) must be set.\nThe data flow is synchronized either by hardware using the optional HSYNC (horizontal \nsynchronization) and VSYNC (vertical synchronization) signals or by synchronization codes \nembedded in the data flow.\nFigure 72 shows the DCMI block diagram.\nFigure 72. DCMI block diagram\nDMA\ninterface\nControl/Status\nregister\nAHB\ninterface\nFIFO/\nData\nformatter\nData\nextraction\nSynchronizer DCMI_PIXCLK\nDCMI_D[0:13], DCMI_HSYNC, DCMI_VSYNC\nai15604b\n" }, { "page_number": 460, "page_indices": { "start_index": 961242, "end_index": 962525 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 460 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.5 DCMI functional overview", 459 ], [ 3, "15.5.1 DMA interface", 460 ], [ 3, "15.5.2 DCMI physical interface", 460 ] ], "page_content": "Digital camera interface (DCMI)\nRM0090\n460/1757\nRM0090 Rev 21\nFigure 73. Top-level block diagram\n15.5.1 \nDMA interface\nThe DMA interface is active when the CAPTURE bit in the DCMI_CR register is set. A DMA \nrequest is generated each time the camera interface receives a complete 32-bit data block \nin its register.\n15.5.2 \nDCMI physical interface\nThe interface is composed of 11/13/15/17 inputs. Only the Slave mode is supported.\nThe camera interface can capture 8-bit, 10-bit, 12-bit or 14-bit data depending on the \nEDM[1:0] bits in the DCMI_CR register. If less than 14 bits are used, the unused data pins \nmust not be assigned to DCMI interface through GPIO alternate functions.\n \nThe data are synchronous with PIXCLK and change on the rising/falling edge of the pixel \nclock depending on the polarity.\nThe HSYNC signal indicates the start/end of a line.\nThe VSYNC signal indicates the start/end of a frame\nDCMI\nInterrupt\ncontroller\nDCMI_IT\nExternal\ninterface\nDCMI_D[0:13]\nDCMI_PIXCLK\nDCMI_HSYNC\nDCMI_VSYNC\nDMA_REQ\nHCLK\nai15603b\nTable 79. DCMI signals\nSignal name\nSignal description\n8 bits\n10 bits\n12 bits\n14 bits\nD[0..7]\nD[0..9]\nD[0..11]\nD[0..13]\nData\nPIXCLK\nPixel clock\nHSYNC\nHorizontal synchronization / Data valid\nVSYNC\nVertical synchronization\n" }, { "page_number": 461, "page_indices": { "start_index": 962525, "end_index": 964310 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 461 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.5 DCMI functional overview", 459 ], [ 3, "15.5.2 DCMI physical interface", 460 ], [ 4, "8-bit data", 461 ], [ 4, "10-bit data", 461 ] ], "page_content": "RM0090 Rev 21\n461/1757\nRM0090\nDigital camera interface (DCMI)\n482\nFigure 74. DCMI signal waveforms\n1.\nThe capture edge of DCMI_PIXCLK is the falling edge, the active state of DCMI_HSYNC and \nDCMI_VSYNC is 1.\n1.\nDCMI_HSYNC and DCMI_VSYNC can change states at the same time.\n8-bit data\nWhen EDM[1:0] in DCMI_CR are programmed to “00” the interface captures 8 LSB’s at its \ninput (D[0:7]) and stores them as 8-bit data. The D[13:8] inputs are ignored. In this case, to \ncapture a 32-bit word, the camera interface takes four pixel clock cycles.\nThe first captured data byte is placed in the LSB position in the 32-bit word and the 4th \ncaptured data byte is placed in the MSB position in the 32-bit word. Table 80 gives an \nexample of the positioning of captured data bytes in two 32-bit words.\n \n10-bit data\nWhen EDM[1:0] in DCMI_CR are programmed to “01”, the camera interface captures 10-bit \ndata at its input D[0..9] and stores them as the 10 least significant bits of a 16-bit word. The \nremaining most significant bits in the DCMI_DR register (bits 11 to 15) are cleared to zero. \nSo, in this case, a 32-bit data word is made up every two pixel clock cycles.\nThe first captured data are placed in the LSB position in the 32-bit word and the 2nd \ncaptured data are placed in the MSB position in the 32-bit word as shown in Table 81.\n \nTable 80. Positioning of captured data bytes in 32-bit words (8-bit width)\nByte address\n31:24\n23:16\n15:8\n7:0\n0\nDn+3[7:0]\nDn+2[7:0]\nDn+1[7:0]\nDn[7:0]\n4\nDn+7[7:0]\nDn+6[7:0]\nDn+5[7:0]\nDn+4[7:0]\nTable 81. Positioning of captured data bytes in 32-bit words (10-bit width)\nByte address\n31:26\n25:16\n15:10\n9:0\n0\n0\nDn+1[9:0]\n0\nDn[9:0]\n4\n0\nDn+3[9:0]\n0\nDn+2[9:0]\nDCMI_PIXCLK\nDCMI_DR[0:13]\nDCMI_HSYNC\nDCMI_VSYNC\nai15606b\n" }, { "page_number": 462, "page_indices": { "start_index": 964310, "end_index": 966453 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 462 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.5 DCMI functional overview", 459 ], [ 3, "15.5.2 DCMI physical interface", 460 ], [ 4, "12-bit data", 462 ], [ 4, "14-bit data", 462 ], [ 3, "15.5.3 Synchronization", 462 ] ], "page_content": "Digital camera interface (DCMI)\nRM0090\n462/1757\nRM0090 Rev 21\n12-bit data\nWhen EDM[1:0] in DCMI_CR are programmed to “10”, the camera interface captures the \n12-bit data at its input D[0..11] and stores them as the 12 least significant bits of a 16-bit \nword. The remaining most significant bits are cleared to zero. So, in this case a 32-bit data \nword is made up every two pixel clock cycles.\nThe first captured data are placed in the LSB position in the 32-bit word and the 2nd \ncaptured data are placed in the MSB position in the 32-bit word as shown in Table 82.\n \n14-bit data\nWhen EDM[1:0] in DCMI_CR are programmed to “11”, the camera interface captures the \n14-bit data at its input D[0..13] and stores them as the 14 least significant bits of a 16-bit \nword. The remaining most significant bits are cleared to zero. So, in this case a 32-bit data \nword is made up every two pixel clock cycles.\nThe first captured data are placed in the LSB position in the 32-bit word and the 2nd \ncaptured data are placed in the MSB position in the 32-bit word as shown in Table 83.\n \n15.5.3 \nSynchronization\nThe digital camera interface supports embedded or hardware (HSYNC & VSYNC) \nsynchronization. When embedded synchronization is used, it is up to the digital camera \nmodule to make sure that the 0x00 and 0xFF values are used ONLY for synchronization \n(not in data). Embedded synchronization codes are supported only for the 8-bit parallel data \ninterface width (that is, in the DCMI_CR register, the EDM[1:0] bits should be cleared to \n“00”).\nFor compressed data, the DCMI supports only the hardware synchronization mode. In this \ncase, VSYNC is used as a start/end of the image, and HSYNC is used as a Data Valid \nsignal. Figure 75 shows the corresponding timing diagram.\nTable 82. Positioning of captured data bytes in 32-bit words (12-bit width)\nByte address\n31:28\n27:16\n15:12\n11:0\n0\n0\nDn+1[11:0]\n0\nDn[11:0]\n4\n0\nDn+3[11:0]\n0\nDn+2[11:0]\nTable 83. Positioning of captured data bytes in 32-bit words (14-bit width)\nByte address\n31:30\n29:16\n15:14\n13:0\n0\n0\nDn+1[13:0]\n0\nDn[13:0]\n4\n0\nDn+3[13:0]\n0\nDn+2[13:0]\n" }, { "page_number": 463, "page_indices": { "start_index": 966453, "end_index": 966839 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 463 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.5 DCMI functional overview", 459 ], [ 3, "15.5.3 Synchronization", 462 ] ], "page_content": "RM0090 Rev 21\n463/1757\nRM0090\nDigital camera interface (DCMI)\n482\nFigure 75. Timing diagram\nai15944b\nBeginning of JPEG stream\nJPEG data\nDCMI_HSYNC\nJPEG packet data \nDCMI_VSYNC\nPadding data \nat the end of the JPEG stream\nProgrammable\nJPEG packet size\nEnd of JPEG stream\nPacket dispatching depends on the image content.\nThis results in a variable blanking duration.\n" }, { "page_number": 464, "page_indices": { "start_index": 966839, "end_index": 969495 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 464 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.5 DCMI functional overview", 459 ], [ 3, "15.5.3 Synchronization", 462 ], [ 4, "Hardware synchronization mode", 464 ], [ 4, "Embedded data synchronization mode", 464 ] ], "page_content": "Digital camera interface (DCMI)\nRM0090\n464/1757\nRM0090 Rev 21\nHardware synchronization mode\nIn hardware synchronisation mode, the two synchronization signals (HSYNC/VSYNC) are \nused.\nDepending on the camera module/mode, data may be transmitted during horizontal/vertical \nsynchronisation periods. The HSYNC/VSYNC signals act like blanking signals since all the \ndata received during HSYNC/VSYNC active periods are ignored.\nIn order to correctly transfer images into the DMA/RAM buffer, data transfer is synchronized \nwith the VSYNC signal. When the hardware synchronisation mode is selected, and capture \nis enabled (CAPTURE bit set in DCMI_CR), data transfer is synchronized with the \ndeactivation of the VSYNC signal (next start of frame).\nTransfer can then be continuous, with successive frames transferred by DMA to successive \nbuffers or the same/circular buffer. To allow the DMA management of successive frames, a \nVSIF (Vertical synchronization interrupt flag) is activated at the end of each frame.\nEmbedded data synchronization mode\nIn this synchronisation mode, the data flow is synchronised using 32-bit codes embedded in \nthe data flow. These codes use the 0x00/0xFF values that are not used in data anymore. \nThere are 4 types of codes, all with a 0xFF0000XY format. The embedded synchronization \ncodes are supported only in 8-bit parallel data width capture (in the DCMI_CR register, the \nEDM[1:0] bits should be programmed to “00”). For other data widths, this mode generates \nunpredictable results and must not be used.\nNote:\nCamera modules can have 8 such codes (in interleaved mode). For this reason, the \ninterleaved mode is not supported by the camera interface (otherwise, every other half-\nframe would be discarded).\n•\nMode 2\nFour embedded codes signal the following events\n–\nFrame start (FS)\n–\nFrame end (FE)\n–\nLine start (LS)\n–\nLine end (LE)\nThe XY values in the 0xFF0000XY format of the four codes are programmable (see \nSection 15.8.7: DCMI embedded synchronization code register (DCMI_ESCR)).\nA 0xFF value programmed as a “frame end” means that all the unused codes are \ninterpreted as valid frame end codes. \nIn this mode, once the camera interface has been enabled, the frame capture starts \nafter the first occurrence of the frame end (FE) code followed by a frame start (FS) \ncode.\n•\nMode 1\nAn alternative coding is the camera mode 1. This mode is ITU656 compatible.\nThe codes signal another set of events:\n–\nSAV (active line) - line start \n–\nEAV (active line) - line end\n–\nSAV (blanking) - end of line during interframe blanking period\n–\nEAV (blanking) - end of line during interframe blanking period\n" }, { "page_number": 465, "page_indices": { "start_index": 969495, "end_index": 971124 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 465 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.5 DCMI functional overview", 459 ], [ 3, "15.5.3 Synchronization", 462 ], [ 4, "Example", 465 ], [ 3, "15.5.4 Capture modes", 465 ], [ 4, "Snapshot mode (single frame)", 465 ] ], "page_content": "RM0090 Rev 21\n465/1757\nRM0090\nDigital camera interface (DCMI)\n482\nThis mode can be supported by programming the following codes:\n•\nFS ≤ 0xFF\n•\nFE ≤ 0xFF\n•\nLS ≤ SAV (active)\n•\nLE ≤ EAV (active)\nAn embedded unmask code is also implemented for frame/line start and frame/line end \ncodes. Using it, it is possible to compare only the selected unmasked bits with the \nprogrammed code. You can therefore select a bit to compare in the embedded code and \ndetect a frame/line start or frame/line end. This means that there can be different codes for \nthe frame/line start and frame/line end with the unmasked bit position remaining the same.\nExample\nFS = 0xA5\nUnmask code for FS = 0x10\nIn this case the frame start code is embedded in the bit 4 of the frame start code.\n15.5.4 \nCapture modes\nThis interface supports two types of capture: snapshot (single frame) and continuous grab.\nSnapshot mode (single frame)\nIn this mode, a single frame is captured (CM = ‘1’ in the DCMI_CR register). After the \nCAPTURE bit is set in DCMI_CR, the interface waits for the detection of a start of frame \nbefore sampling the data. The camera interface is automatically disabled (CAPTURE bit \ncleared in DCMI_CR) after receiving the first complete frame. An interrupt is generated \n(IT_FRAME) if it is enabled.\nIn case of an overrun, the frame is lost and the CAPTURE bit is cleared.\nFigure 76. Frame capture waveforms in Snapshot mode\n1.\nHere, the active state of DCMI_HSYNC and DCMI_VSYNC is 1.\n2.\nDCMI_HSYNC and DCMI_VSYNC can change states at the same time.\nDCMI_HSYNC\nDCMI_VSYNC\nFrame 1 captured\nFrame 2\nnot captured\nai15832b\n" }, { "page_number": 466, "page_indices": { "start_index": 971124, "end_index": 972869 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 466 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.5 DCMI functional overview", 459 ], [ 3, "15.5.4 Capture modes", 465 ], [ 4, "Continuous grab mode", 466 ], [ 3, "15.5.5 Crop feature", 466 ] ], "page_content": "Digital camera interface (DCMI)\nRM0090\n466/1757\nRM0090 Rev 21\nContinuous grab mode\nIn this mode (CM bit = ‘0’ in DCMI_CR), once the CAPTURE bit has been set in DCMI_CR, \nthe grabbing process starts on the next VSYNC or embedded frame start depending on the \nmode. The process continues until the CAPTURE bit is cleared in DCMI_CR. Once the \nCAPTURE bit has been cleared, the grabbing process continues until the end of the current \nframe.\nFigure 77. Frame capture waveforms in continuous grab mode\n1.\nHere, the active state of DCMI_HSYNC and DCMI_VSYNC is 1.\n2.\nDCMI_HSYNC and DCMI_VSYNC can change states at the same time.\nIn continuous grab mode, you can configure the FCRC bits in DCMI_CR to grab all pictures, \nevery second picture or one out of four pictures to decrease the frame capture rate.\nNote:\nIn the hardware synchronization mode (ESS = ‘0’ in DCMI_CR), the IT_VSYNC interrupt is \ngenerated (if enabled) even when CAPTURE = ‘0’ in DCMI_CR so, to reduce the frame \ncapture rate even further, the IT_VSYNC interrupt can be used to count the number of \nframes between 2 captures in conjunction with the Snapshot mode. This is not allowed by \nembedded data synchronization mode.\n15.5.5 \nCrop feature\nWith the crop feature, the camera interface can select a rectangular window from the \nreceived image. The start (upper left corner) coordinates and size (horizontal dimension in \nnumber of pixel clocks and vertical dimension in number of lines) are specified using two 32-\nbit registers (DCMI_CWSTRT and DCMI_CWSIZE). The size of the window is specified in \nnumber of pixel clocks (horizontal dimension) and in number of lines (vertical dimension).\nDCMI_HSYNC\nDCMI_VSYNC\nFrame 1 captured\nFrame 2 captured\nai15833b\n" }, { "page_number": 467, "page_indices": { "start_index": 972869, "end_index": 973984 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 467 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.5 DCMI functional overview", 459 ], [ 3, "15.5.5 Crop feature", 466 ] ], "page_content": "RM0090 Rev 21\n467/1757\nRM0090\nDigital camera interface (DCMI)\n482\nFigure 78. Coordinates and size of the window after cropping\nThese registers specify the coordinates of the starting point of the capture window as a line \nnumber (in the frame, starting from 0) and a number of pixel clocks (on the line, starting from \n0), and the size of the window as a line number and a number of pixel clocks. The CAPCNT \nvalue can only be a multiple of 4 (two least significant bits are forced to 0) to allow the \ncorrect transfer of data through the DMA.\nIf the VSYNC signal goes active before the number of lines is specified in the \nDCMI_CWSIZE register, then the capture stops and an IT_FRAME interrupt is generated \nwhen enabled.\nFigure 79. Data capture waveforms\n1.\nHere, the active state of DCMI_HSYNC and DCMI_VSYNC is 1.\n2.\nDCMI_HSYNC and DCMI_VSYNC can change states at the same time.\nCAPCNT bit in DCMI_CSIZE\nHOFFCNT bit in DCMI_CSTRT\nai15834\nVST bit in DCMI_CSTRT\nVLINE bit in DCMI_CSIZE\nDCMI_HSYNC\nDCMI_VSYNC\nai15835\nCAPCNT\nHOFFCNT\nData not captured in this phase\nData captured in this phase\n" }, { "page_number": 468, "page_indices": { "start_index": 973984, "end_index": 976126 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 468 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.5 DCMI functional overview", 459 ], [ 3, "15.5.6 JPEG format", 468 ], [ 3, "15.5.7 FIFO", 468 ], [ 2, "15.6 Data format description", 468 ], [ 3, "15.6.1 Data formats", 468 ] ], "page_content": "Digital camera interface (DCMI)\nRM0090\n468/1757\nRM0090 Rev 21\n15.5.6 \nJPEG format\nTo allow JPEG image reception, it is necessary to set the JPEG bit in the DCMI_CR register. \nJPEG images are not stored as lines and frames, so the VSYNC signal is used to start the \ncapture while HSYNC serves as a data enable signal. The number of bytes in a line may not \nbe a multiple of 4, you should therefore be careful when handling this case since a DMA \nrequest is generated each time a complete 32-bit word has been constructed from the \ncaptured data. When an end of frame is detected and the 32-bit word to be transferred has \nnot been completely received, the remaining data are padded with ‘0s’ and a DMA request \nis generated.\nThe crop feature and embedded synchronization codes cannot be used in the JPEG format.\n15.5.7 \nFIFO\nA four-word FIFO is implemented to manage data rate transfers on the AHB. The DCMI \nfeatures a simple FIFO controller with a read pointer incremented each time the camera \ninterface reads from the AHB, and a write pointer incremented each time the camera \ninterface writes to the FIFO. There is no overrun protection to prevent the data from being \noverwritten if the AHB interface does not sustain the data transfer rate.\nIn case of overrun or errors in the synchronization signals, the FIFO is reset and the DCMI \ninterface waits for a new start of frame.\n15.6 \nData format description\n15.6.1 \nData formats\nThree types of data are supported:\n•\n8-bit progressive video: either monochrome or raw Bayer format\n•\nYCbCr 4:2:2 progressive video\n•\nRGB565 progressive video. A pixel coded in 16 bits (5 bits for blue, 5 bits for red, 6 bits \nfor green) takes two clock cycles to be transferred.\nCompressed data: JPEG\nFor B&W, YCbCr or RGB data, the maximum input size is 2048 × 2048 pixels. No limit in \nJPEG compressed mode.\nFor monochrome, RGB & YCbCr, the frame buffer is stored in raster mode. 32-bit words are \nused. Only the little endian format is supported.\nFigure 80. Pixel raster scan order\nPixel raster\nscan order\n(increasing\naddresses)\nWord0 Word1 Word2\nPixel row 0\nPixel row n – 1\nai15848\n" }, { "page_number": 469, "page_indices": { "start_index": 976126, "end_index": 977828 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 469 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.6 Data format description", 468 ], [ 3, "15.6.2 Monochrome format", 469 ], [ 3, "15.6.3 RGB format", 469 ], [ 3, "15.6.4 YCbCr format", 469 ] ], "page_content": "RM0090 Rev 21\n469/1757\nRM0090\nDigital camera interface (DCMI)\n482\n15.6.2 \nMonochrome format\nCharacteristics:\n•\nRaster format\n•\n8 bits per pixel\nTable 84 shows how the data are stored.\n \n15.6.3 \nRGB format\nCharacteristics:\n•\nRaster format\n•\nRGB\n•\nInterleaved: one buffer: R, G & B interleaved: BRGBRGBRG, etc.\n•\nOptimized for display output\nThe RGB planar format is compatible with standard OS frame buffer display formats.\nOnly 16 BPP (bits per pixel): RGB565 (2 pixels per 32-bit word) is supported.\nThe 24 BPP (palletized format) and grayscale formats are not supported. Pixels are stored \nin a raster scan order, that is from top to bottom for pixel rows, and from left to right within a \npixel row. Pixel components are R (red), G (green) and B (blue). All components have the \nsame spatial resolution (4:4:4 format). A frame is stored in a single part, with the \ncomponents interleaved on a pixel basis.\nTable 85 shows how the data are stored.\n \n15.6.4 \nYCbCr format\nCharacteristics:\n•\nRaster format\n•\nYCbCr 4:2:2\n•\nInterleaved: one Buffer: Y, Cb & Cr interleaved: CbYCrYCbYCr, etc.\nPixel components are Y (luminance or “luma”), Cb and Cr (chrominance or “chroma” blue \nand red). Each component is encoded in 8 bits. Luma and chroma are stored together \n(interleaved) as shown in Table 86.\nTable 84. Data storage in monochrome progressive video format\nByte address\n31:24\n23:16\n15:8\n7:0\n0\nn + 3\nn + 2\nn + 1\nn\n4\nn + 7\nn + 6\nn + 5\nn + 4\nTable 85. Data storage in RGB progressive video format\nByte address\n31:27\n26:21\n20:16\n15:11\n10:5\n4:0\n0\nRed n + 1\nGreen n + 1\nBlue n + 1\nRed n\nGreen n\nBlue n\n4\nRed n + 4\nGreen n + 3\nBlue n + 3\nRed n + 2\nGreen n + 2\nBlue n + 2\n" }, { "page_number": 470, "page_indices": { "start_index": 977828, "end_index": 979345 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 470 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.7 DCMI interrupts", 470 ], [ 2, "15.8 DCMI register description", 470 ], [ 3, "15.8.1 DCMI control register 1 (DCMI_CR)", 470 ] ], "page_content": "Digital camera interface (DCMI)\nRM0090\n470/1757\nRM0090 Rev 21\n \n15.7 \nDCMI interrupts\nFive interrupts are generated. All interrupts are maskable by software. The global interrupt \n(IT_DCMI) is the OR of all the individual interrupts. Table 87 gives the list of all interrupts.\n \n15.8 \nDCMI register description\nAll DCMI registers have to be accessed as 32-bit words, otherwise a bus error occurs.\n15.8.1 \nDCMI control register 1 (DCMI_CR)\nAddress offset: 0x00\nReset value: 0x0000 0x0000\n \n \nTable 86. Data storage in YCbCr progressive video format\nByte address\n31:24\n23:16\n15:8\n7:0\n0\nY n + 1\nCr n\nY n\nCb n\n4\nY n + 3\nCr n + 2\nY n + 2\nCb n + 2\nTable 87. DCMI interrupts\nInterrupt name\nInterrupt event\nIT_LINE\nIndicates the end of line\nIT_FRAME\nIndicates the end of frame capture\nIT_OVR\nindicates the overrun of data reception\nIT_VSYNC\nIndicates the synchronization frame\nIT_ERR\nIndicates the detection of an error in the embedded synchronization frame \ndetection\nIT_DCMI\nLogic OR of the previous interrupts\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nENABLE\nReserved\nEDM\nFCRC\nVSPOL\nHSPOL\nPCKPOL\nESS\nJPEG\nCROP\nCM\nCAPTURE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31:15 Reserved, must be kept at reset value.\nBit 14 ENABLE: DCMI enable\n0: DCMI disabled\n1: DCMI enabled\nNote: The DCMI configuration registers should be programmed correctly before \nenabling this Bit\nBit 13: 12 Reserved, must be kept at reset value.\n" }, { "page_number": 471, "page_indices": { "start_index": 979345, "end_index": 981503 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 471 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.8 DCMI register description", 470 ], [ 3, "15.8.1 DCMI control register 1 (DCMI_CR)", 470 ] ], "page_content": "RM0090 Rev 21\n471/1757\nRM0090\nDigital camera interface (DCMI)\n482\nBits 11:10 EDM[1:0]: Extended data mode\n00: Interface captures 8-bit data on every pixel clock\n01: Interface captures 10-bit data on every pixel clock\n10: Interface captures 12-bit data on every pixel clock\n11: Interface captures 14-bit data on every pixel clock\nBits 9:8 FCRC[1:0]: Frame capture rate control\nThese bits define the frequency of frame capture. They are meaningful only in \nContinuous grab mode. They are ignored in snapshot mode.\n00: All frames are captured\n01: Every alternate frame captured (50% bandwidth reduction)\n10: One frame in 4 frames captured (75% bandwidth reduction)\n11: reserved\nBit 7 VSPOL: Vertical synchronization polarity\nThis bit indicates the level on the VSYNC pin when the data are not valid on the \nparallel interface.\n0: VSYNC active low\n1: VSYNC active high\nBit 6 HSPOL: Horizontal synchronization polarity\nThis bit indicates the level on the HSYNC pin when the data are not valid on the \nparallel interface.\n0: HSYNC active low\n1: HSYNC active high\nBit 5 PCKPOL: Pixel clock polarity\nThis bit configures the capture edge of the pixel clock\n0: Falling edge active.\n1: Rising edge active.\nBit 4 ESS: Embedded synchronization select\n0: Hardware synchronization data capture (frame/line start/stop) is synchronized \nwith the HSYNC/VSYNC signals.\n1: Embedded synchronization data capture is synchronized with synchronization \ncodes embedded in the data flow.\nNote: Valid only for 8-bit parallel data. HSPOL/VSPOL are ignored when the ESS \nbit is set.\nThis bit is disabled in JPEG mode.\nBit 3 JPEG: JPEG format\n0: Uncompressed video format\n1: This bit is used for JPEG data transfers. The HSYNC signal is used as data \nenable. The crop and embedded synchronization features (ESS bit) cannot be \nused in this mode.\nBits 2 CROP: Crop feature\n0: The full image is captured. In this case the total number of bytes in an image \nframe should be a multiple of 4\n1: Only the data inside the window specified by the crop register are captured. If \nthe size of the crop window exceeds the picture size, then only the picture size is \ncaptured.\n" }, { "page_number": 472, "page_indices": { "start_index": 981503, "end_index": 982599 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 472 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.8 DCMI register description", 470 ], [ 3, "15.8.1 DCMI control register 1 (DCMI_CR)", 470 ] ], "page_content": "Digital camera interface (DCMI)\nRM0090\n472/1757\nRM0090 Rev 21\nBit 1 CM: Capture mode\n0: Continuous grab mode - The received data are transferred into the destination \nmemory through the DMA. The buffer location and mode (linear or circular \nbuffer) is controlled through the system DMA.\n1: Snapshot mode (single frame) - Once activated, the interface waits for the \nstart of frame and then transfers a single frame through the DMA. At the end of \nthe frame, the CAPTURE bit is automatically reset.\nBit 0 CAPTURE: Capture enable\n0: Capture disabled.\n1: Capture enabled.\nThe camera interface waits for the first start of frame, then a DMA request is \ngenerated to transfer the received data into the destination memory.\nIn snapshot mode, the CAPTURE bit is automatically cleared at the end of the \n1st frame received.\nIn continuous grab mode, if the software clears this bit while a capture is \nongoing, the bit is effectively cleared after the frame end.\nNote: The DMA controller and all DCMI configuration registers should be \nprogrammed correctly before enabling this bit.\n" }, { "page_number": 473, "page_indices": { "start_index": 982599, "end_index": 983734 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 473 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.8 DCMI register description", 470 ], [ 3, "15.8.2 DCMI status register (DCMI_SR)", 473 ] ], "page_content": "RM0090 Rev 21\n473/1757\nRM0090\nDigital camera interface (DCMI)\n482\n15.8.2 \nDCMI status register (DCMI_SR)\nAddress offset: 0x04\nReset value: 0x0000 0x0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFNE\nVSYNC\nHSYNC\nr\nr\nr\nBits 31:3 Reserved, must be kept at reset value.\nBit 2 FNE: FIFO not empty\nThis bit gives the status of the FIFO\n1: FIFO contains valid data\n0: FIFO empty\nBit 1 VSYNC\nThis bit gives the state of the VSYNC pin with the correct programmed polarity.\nWhen embedded synchronization codes are used, the meaning of this bit is the \nfollowing:\n0: active frame\n1: synchronization between frames\nIn case of embedded synchronization, this bit is meaningful only if the \nCAPTURE bit in DCMI_CR is set.\nBit 0 HSYNC\nThis bit gives the state of the HSYNC pin with the correct programmed polarity.\nWhen embedded synchronization codes are used, the meaning of this bit is the \nfollowing:\n0: active line\n1: synchronization between lines\nIn case of embedded synchronization, this bit is meaningful only if the \nCAPTURE bit in DCMI_CR is set.\n" }, { "page_number": 474, "page_indices": { "start_index": 983734, "end_index": 985979 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 474 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.8 DCMI register description", 470 ], [ 3, "15.8.3 DCMI raw interrupt status register (DCMI_RIS)", 474 ] ], "page_content": "Digital camera interface (DCMI)\nRM0090\n474/1757\nRM0090 Rev 21\n15.8.3 \nDCMI raw interrupt status register (DCMI_RIS)\nAddress offset: 0x08\nReset value: 0x0000 0x0000\n \nDCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this \nregister returns the status of the corresponding interrupt before masking with the DCMI_IER \nregister value.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLINE_RIS\nVSYNC_RIS\nERR_RIS\nOVR_RIS\nFRAME_RIS\nr\nr\nr\nr\nr\nBits 31:5 Reserved, must be kept at reset value.\nBit 4 LINE_RIS: Line raw interrupt status\nThis bit gets set when the HSYNC signal changes from the inactive state to the \nactive state. It goes high even if the line is not valid.\nIn the case of embedded synchronization, this bit is set only if the CAPTURE bit \nin DCMI_CR is set.\nIt is cleared by writing a ‘1’ to the LINE_ISC bit in DCMI_ICR.\nBit 3 VSYNC_RIS: VSYNC raw interrupt status\nThis bit is set when the VSYNC signal changes from the inactive state to the \nactive state.\nIn the case of embedded synchronization, this bit is set only if the CAPTURE bit \nis set in DCMI_CR.\nIt is cleared by writing a ‘1’ to the VSYNC_ISC bit in DCMI_ICR.\nBit 2 ERR_RIS: Synchronization error raw interrupt status\n0: No synchronization error detected\n1: Embedded synchronization characters are not received in the correct order.\nThis bit is valid only in the embedded synchronization mode. It is cleared by \nwriting a ‘1’ to the ERR_ISC bit in DCMI_ICR.\nNote: This bit is available only in embedded synchronization mode.\nBit 1 OVR_RIS: Overrun raw interrupt status\n0: No data buffer overrun occurred\n1: A data buffer overrun occurred and the data FIFO is corrupted.\nThis bit is cleared by writing a ‘1’ to the OVR_ISC bit in DCMI_ICR.\nBit 0 FRAME_RIS: Capture complete raw interrupt status\n0: No new capture \n1: A frame has been captured.\nThis bit is set when a frame or window has been captured.\nIn case of a cropped window, this bit is set at the end of line of the last line in the \ncrop. It is set even if the captured frame is empty (e.g. window cropped outside \nthe frame).\nThis bit is cleared by writing a ‘1’ to the FRAME_ISC bit in DCMI_ICR.\n" }, { "page_number": 475, "page_indices": { "start_index": 985979, "end_index": 987560 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 475 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.8 DCMI register description", 470 ], [ 3, "15.8.4 DCMI interrupt enable register (DCMI_IER)", 475 ] ], "page_content": "RM0090 Rev 21\n475/1757\nRM0090\nDigital camera interface (DCMI)\n482\n15.8.4 \nDCMI interrupt enable register (DCMI_IER)\nAddress offset: 0x0C\nReset value: 0x0000 0x0000\n \nThe DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set, \nthe corresponding interrupt is enabled. This register is accessible in both read and write.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLINE_IE\nVSYNC_IE\nERR_IE\nOVR_IE\nFRAME_IE\nrw\nrw\nrw\nrw\nrw\nBits 31:5 Reserved, must be kept at reset value.\nBit 4 LINE_IE: Line interrupt enable\n0: No interrupt generation when the line is received\n1: An Interrupt is generated when a line has been completely received\nBit 3 VSYNC_IE: VSYNC interrupt enable\n0: No interrupt generation\n1: An interrupt is generated on each VSYNC transition from the inactive to the \nactive state\nThe active state of the VSYNC signal is defined by the VSPOL bit.\nBit 2 ERR_IE: Synchronization error interrupt enable\n0: No interrupt generation\n1: An interrupt is generated if the embedded synchronization codes are not \nreceived in the correct order.\nNote: This bit is available only in embedded synchronization mode.\nBit 1 OVR_IE: Overrun interrupt enable\n0: No interrupt generation\n1: An interrupt is generated if the DMA was not able to transfer the last data \nbefore new data (32-bit) are received.\nBit 0 FRAME_IE: Capture complete interrupt enable\n0: No interrupt generation\n1: An interrupt is generated at the end of each received frame/crop window (in \ncrop mode).\n" }, { "page_number": 476, "page_indices": { "start_index": 987560, "end_index": 989894 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 476 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.8 DCMI register description", 470 ], [ 3, "15.8.5 DCMI masked interrupt status register (DCMI_MIS)", 476 ] ], "page_content": "Digital camera interface (DCMI)\nRM0090\n476/1757\nRM0090 Rev 21\n15.8.5 \nDCMI masked interrupt status register (DCMI_MIS)\nThis DCMI_MIS register is a read-only register. When read, it returns the current masked \nstatus value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in \nthis register is set if the corresponding enable bit in DCMI_IER is set and the corresponding \nbit in DCMI_RIS is set.\nAddress offset: 0x10\nReset value: 0x0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLINE_MIS\nVSYNC_MIS\nERR_MIS\nOVR_MIS\nFRAME_MIS\nr\nr\nr\nr\nr\nBits 31:5 Reserved, must be kept at reset value.\nBit 4 LINE_MIS: Line masked interrupt status\nThis bit gives the status of the masked line interrupt\n0: No interrupt generation when the line is received\n1: An Interrupt is generated when a line has been completely received and the \nLINE_IE bit is set in DCMI_IER.\nBit 3 VSYNC_MIS: VSYNC masked interrupt status\nThis bit gives the status of the masked VSYNC interrupt\n0: No interrupt is generated on VSYNC transitions\n1: An interrupt is generated on each VSYNC transition from the inactive to the \nactive state and the VSYNC_IE bit is set in DCMI_IER.\nThe active state of the VSYNC signal is defined by the VSPOL bit.\nBit 2 ERR_MIS: Synchronization error masked interrupt status\nThis bit gives the status of the masked synchronization error interrupt\n0: No interrupt is generated on a synchronization error\n1: An interrupt is generated if the embedded synchronization codes are not \nreceived in the correct order and the ERR_IE bit in DCMI_IER is set.\nNote: This bit is available only in embedded synchronization mode.\nBit 1 OVR_MIS: Overrun masked interrupt status\nThis bit gives the status of the masked overflow interrupt\n0: No interrupt is generated on overrun\n1: An interrupt is generated if the DMA was not able to transfer the last data \nbefore new data (32-bit) are received and the OVR_IE bit is set in DCMI_IER.\nBit 0 FRAME_MIS: Capture complete masked interrupt status\nThis bit gives the status of the masked capture complete interrupt\n0: No interrupt is generated after a complete capture\n1: An interrupt is generated at the end of each received frame/crop window (in \ncrop mode) and the FRAME_IE bit is set in DCMI_IER.\n" }, { "page_number": 477, "page_indices": { "start_index": 989894, "end_index": 991131 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 477 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.8 DCMI register description", 470 ], [ 3, "15.8.6 DCMI interrupt clear register (DCMI_ICR)", 477 ] ], "page_content": "RM0090 Rev 21\n477/1757\nRM0090\nDigital camera interface (DCMI)\n482\n15.8.6 \nDCMI interrupt clear register (DCMI_ICR)\nAddress offset: 0x14\nReset value: 0x0000 0x0000\n \nThe DCMI_ICR register is write-only. Writing a ‘1’ into a bit of this register clears the \ncorresponding bit in the DCMI_RIS and DCMI_MIS registers. Writing a ‘0’ has no effect.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLINE_ISC\nVSYNC_ISC\nERR_ISC\nOVR_ISC\nFRAME_ISC\nw\nw\nw\nw\nw\nBits 15:5 Reserved, must be kept at reset value.\nBit 4 LINE_ISC: line interrupt status clear\nWriting a ‘1’ into this bit clears LINE_RIS in the DCMI_RIS register\nBit 3 VSYNC_ISC: Vertical synch interrupt status clear\nWriting a ‘1’ into this bit clears the VSYNC_RIS bit in DCMI_RIS\nBit 2 ERR_ISC: Synchronization error interrupt status clear\nWriting a ‘1’ into this bit clears the ERR_RIS bit in DCMI_RIS\nNote: This bit is available only in embedded synchronization mode.\nBit 1 OVR_ISC: Overrun interrupt status clear\nWriting a ‘1’ into this bit clears the OVR_RIS bit in DCMI_RIS\nBits 0 FRAME_ISC: Capture complete interrupt status clear\nWriting a ‘1’ into this bit clears the FRAME_RIS bit in DCMI_RIS\n" }, { "page_number": 478, "page_indices": { "start_index": 991131, "end_index": 992480 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 478 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.8 DCMI register description", 470 ], [ 3, "15.8.7 DCMI embedded synchronization code register (DCMI_ESCR)", 478 ] ], "page_content": "Digital camera interface (DCMI)\nRM0090\n478/1757\nRM0090 Rev 21\n15.8.7 \nDCMI embedded synchronization code register (DCMI_ESCR)\nAddress offset: 0x18\nReset value: 0x0000 0x0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFEC\nLEC\nLSC\nFSC\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 FEC: Frame end delimiter code\nThis byte specifies the code of the frame end delimiter. The code consists of 4 \nbytes in the form of 0xFF, 0x00, 0x00, FEC.\nIf FEC is programmed to 0xFF, all the unused codes (0xFF0000XY) are \ninterpreted as frame end delimiters.\nBits 23:16 LEC: Line end delimiter code\nThis byte specifies the code of the line end delimiter. The code consists of 4 \nbytes in the form of 0xFF, 0x00, 0x00, LEC.\nBits 15:8 LSC: Line start delimiter code\nThis byte specifies the code of the line start delimiter. The code consists of 4 \nbytes in the form of 0xFF, 0x00, 0x00, LSC.\nBits 7:0 FSC: Frame start delimiter code\nThis byte specifies the code of the frame start delimiter. The code consists of 4 \nbytes in the form of 0xFF, 0x00, 0x00, FSC.\nIf FSC is programmed to 0xFF, no frame start delimiter is detected. But, the 1st \noccurrence of LSC after an FEC code is interpreted as a start of frame delimiter.\n" }, { "page_number": 479, "page_indices": { "start_index": 992480, "end_index": 994443 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 479 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.8 DCMI register description", 470 ], [ 3, "15.8.8 DCMI embedded synchronization unmask register (DCMI_ESUR)", 479 ] ], "page_content": "RM0090 Rev 21\n479/1757\nRM0090\nDigital camera interface (DCMI)\n482\n15.8.8 \nDCMI embedded synchronization unmask register (DCMI_ESUR)\nAddress offset: 0x1C\nReset value: 0x0000 0x0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFEU\nLEU\nLSU\nFSU\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 FEU: Frame end delimiter unmask\nThis byte specifies the mask to be applied to the code of the frame end delimiter.\n0: The corresponding bit in the FEC byte in DCMI_ESCR is masked while \ncomparing the frame end delimiter with the received data.\n1: The corresponding bit in the FEC byte in DCMI_ESCR is compared while \ncomparing the frame end delimiter with the received data\nBits 23:16 LEU: Line end delimiter unmask\nThis byte specifies the mask to be applied to the code of the line end delimiter.\n0: The corresponding bit in the LEC byte in DCMI_ESCR is masked while \ncomparing the line end delimiter with the received data\n1: The corresponding bit in the LEC byte in DCMI_ESCR is compared while \ncomparing the line end delimiter with the received data\nBits 15:8 LSU: Line start delimiter unmask\nThis byte specifies the mask to be applied to the code of the line start delimiter.\n0: The corresponding bit in the LSC byte in DCMI_ESCR is masked while \ncomparing the line start delimiter with the received data\n1: The corresponding bit in the LSC byte in DCMI_ESCR is compared while \ncomparing the line start delimiter with the received data\nBits 7:0 FSU: Frame start delimiter unmask\nThis byte specifies the mask to be applied to the code of the frame start \ndelimiter.\n0: The corresponding bit in the FSC byte in DCMI_ESCR is masked while \ncomparing the frame start delimiter with the received data\n1: The corresponding bit in the FSC byte in DCMI_ESCR is compared while \ncomparing the frame start delimiter with the received data\n" }, { "page_number": 480, "page_indices": { "start_index": 994443, "end_index": 996162 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 480 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.8 DCMI register description", 470 ], [ 3, "15.8.9 DCMI crop window start (DCMI_CWSTRT)", 480 ], [ 3, "15.8.10 DCMI crop window size (DCMI_CWSIZE)", 480 ] ], "page_content": "Digital camera interface (DCMI)\nRM0090\n480/1757\nRM0090 Rev 21\n15.8.9 \nDCMI crop window start (DCMI_CWSTRT)\nAddress offset: 0x20\nReset value: 0x0000 0x0000\n \n \n15.8.10 \nDCMI crop window size (DCMI_CWSIZE)\nAddress offset: 0x24\nReset value: 0x0000 0x0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nVST[12:0\nReserv\ned\nHOFFCNT[13:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:29 Reserved, must be kept at reset value.\nBits 28:16 VST[12:0]: Vertical start line count\nThe image capture starts with this line number. Previous line data are ignored.\n0x0000 => line 1\n0x0001 => line 2\n0x0002 => line 3\n....\nBits 15:14 Reserved, must be kept at reset value.\nBit 13:0 HOFFCNT[13:0]: Horizontal offset count\nThis value gives the number of pixel clocks to count before starting a capture.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nVLINE13:0]\nReserved\nCAPCNT[13:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBitst 29:16 VLINE[13:0]: Vertical line count\nThis value gives the number of lines to be captured from the starting point.\n0x0000 => 1 line\n0x0001 => 2 lines\n0x0002 => 3 lines\n....\nBits 15:14 Reserved, must be kept at reset value.\nBits 13:0 CAPCNT[13:0]: Capture count\nThis value gives the number of pixel clocks to be captured from the starting \npoint on the same line. It value should corresponds to word-aligned data for \ndifferent widths of parallel interfaces.\n0x0000 => 1 pixel\n0x0001 => 2 pixels\n0x0002 => 3 pixels\n....\n" }, { "page_number": 481, "page_indices": { "start_index": 996162, "end_index": 997512 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 481 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.8 DCMI register description", 470 ], [ 3, "15.8.11 DCMI data register (DCMI_DR)", 481 ], [ 3, "15.8.12 DCMI register map", 481 ] ], "page_content": "RM0090 Rev 21\n481/1757\nRM0090\nDigital camera interface (DCMI)\n482\n15.8.11 \nDCMI data register (DCMI_DR)\nAddress offset: 0x28\nReset value: 0x0000 0x0000\n \n \nThe digital camera Interface packages all the received data in 32-bit format before \nrequesting a DMA transfer. A 4-word deep FIFO is available to leave enough time for DMA \ntransfers and avoid DMA overrun conditions.\n15.8.12 \nDCMI register map\nTable 88 summarizes the DCMI registers.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nByte3\nByte2\nByte1\nByte0\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:24 Data byte 3\nBits 23:16 Data byte 2\nBits 15:8 Data byte 1\nBits 7:0 Data byte 0\nTable 88. DCMI register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nDCMI_CR\nReserved\nENABLE\nReserved\nEDM\nFCR\nC\nVSPOL\nHSPOL\nPCKPOL\nESS\nJPEG\nCROP\nCM\nCAPTURE\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nDCMI_SR\nReserved\nFNE\nVSYNC\nHSYNC\nReset value\n0\n0\n0\n0x08\nDCMI_RIS\nReserved\nLINE_RIS\nVSYNC_RIS\nERR_RIS\nOVR_RIS\nFRAME_RIS\nReset value\n0\n0\n0\n0\n0\n0x0C\nDCMI_IER\nReserved\nLINE_IE\nVSYNC_IE\nERR_IE\nOVR_IE\nFRAME_IE\nReset value\n0\n0\n0\n0\n0\n0x10\nDCMI_MIS\nReserved\nLINE_MIS\nVSYNC_MIS\nERR_MIS\nOVR_MIS\nFRAME_MIS\nReset value\n0\n0\n0\n0\n0\n" }, { "page_number": 482, "page_indices": { "start_index": 997512, "end_index": 998496 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 482 }, "toc_details": [ [ 1, "15 Digital camera interface (DCMI)", 458 ], [ 2, "15.8 DCMI register description", 470 ], [ 3, "15.8.12 DCMI register map", 481 ] ], "page_content": "Digital camera interface (DCMI)\nRM0090\n482/1757\nRM0090 Rev 21\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x14\nDCMI_ICR\nReserved\nLINE_ISC\nVSYNC_ISC\nERR_ISC\nOVR_ISC\nFRAME_ISC\nReset value\n0\n0\n0\n0\n0\n0x18\nDCMI_ESCR\nFEC\nLEC\nLSC\nFSC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nDCMI_ESUR\nFEU\nLEU\nLSU\nFSU\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nDCMI_CWSTR\nT\nReserve\nd\nVST[12:0\nReserved\nHOFFCNT[13:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x24\nDCMI_CWSIZ\nE\nReserved\nVLINE13:0]\nReserved\nCAPCNT[13:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nDCMI_DR\nByte3\nByte2\nByte1\nByte0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 88. DCMI register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 483, "page_indices": { "start_index": 998496, "end_index": 999967 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 483 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.1 Introduction", 483 ], [ 2, "16.2 LTDC main features", 483 ] ], "page_content": "RM0090 Rev 21\n483/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16 \nLCD-TFT controller (LTDC)\nThis section applies only to STM32F429xx/439xx devices.\n16.1 \nIntroduction\nThe LCD-TFT (Liquid Crystal Display - Thin Film Transistor) display controller provides a \nparallel digital RGB (Red, Green, Blue) and signals for horizontal, vertical synchronisation, \nPixel Clock and Data Enable as output to interface directly to a variety of LCD and TFT \npanels.\n16.2 \nLTDC main features\n•\n24-bit RGB Parallel Pixel Output; 8 bits-per-pixel (RGB888)\n•\n2 display layers with dedicated FIFO (64x32-bit)\n•\nColor Look-Up Table (CLUT) up to 256 color (256x24-bit) per layer\n•\nSupports up to XGA (1024x768) resolution\n•\nProgrammable timings for different display panels\n•\nProgrammable Background color\n•\nProgrammable polarity for HSync, VSync and Data Enable\n•\nUp to 8 Input color formats selectable per layer\n–\nARGB8888\n–\nRGB888\n–\nRGB565\n–\nARGB1555\n–\nARGB4444\n–\nL8 (8-bit Luminance or CLUT)\n–\nAL44 (4-bit alpha + 4-bit luminance)\n–\nAL88 (8-bit alpha + 8-bit luminance)\n•\nPseudo-random dithering output for low bits per channel\n–\nDither width 2-bits for Red, Green, Blue\n•\nFlexible blending between two layers using alpha value (per pixel or constant)\n•\nColor Keying (transparency color) \n•\nProgrammable Window position and size \n•\nSupports thin film transistor (TFT) color displays \n•\nAHB master interface with burst of 16 words\n•\nUp to 4 programmable interrupt events\n" }, { "page_number": 484, "page_indices": { "start_index": 999967, "end_index": 1001475 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 484 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.3 LTDC functional description", 484 ], [ 3, "16.3.1 LTDC block diagram", 484 ], [ 3, "16.3.2 LTDC reset and clocks", 484 ] ], "page_content": "LCD-TFT controller (LTDC)\nRM0090\n484/1757\nRM0090 Rev 21\n16.3 \nLTDC functional description\n16.3.1 \nLTDC block diagram \nThe block diagram of the LTDC is shown in Figure 81: LTDC block diagram. \nFigure 81. LTDC block diagram\nLayer FIFO: One FIFO 64x32 bit per layer.\nPFC: Pixel Format Convertor performing the pixel format conversion from the selected input \npixel format of a layer to words.\nAHB interface: For data transfer from memories to the FIFO.\nBlending, Dithering unit and Timings Generator: Refer to Section 16.4.1 and Section 16.4.2.\n16.3.2 \nLTDC reset and clocks\nThe LCD-TFT controller peripheral uses 3 clock domains:\n•\nThe AHB clock domain (HCLK) is used for data transfer from the memories to the \nLayer FIFO and frame buffer configuration register\n•\nThe APB2 clock domain (PCLK2) is used for global configuration register and interrupt \nregisters\n•\nThe Pixel Clock domain (LCD_CLK) is used to generate LCD-TFT interface signals, \npixel data generation and layer configuration. The LCD_CLK output should be \nconfigured following the panel requirements. The LCD_CLK is configured through the \nPLLSAI (refer to RCC section). \nTable 89 summarizes the clock domain for each register. \nMSv19675V1\nLCD-TFT\npanel\nLCD_HSYNC\nLCD_VSYNC\nLCD_DE\nLCD_CLK\nLCD_R[7:0]\nLCD_G[7:0]\nLCD_B[7:0]\nPixel clock domain\nDithering \nunit\nBlending \nunit\nPFC\nPFC\nLayer1 \nFIFO\nLayer1 \nFIFO\nAHB \ninterface\nTiming \ngenerator\nConfiguration \nand status \nregisters\nAHB clock domain\nAPB2 clock domain\nInterrupts\n" }, { "page_number": 485, "page_indices": { "start_index": 1001475, "end_index": 1002598 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 485 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.3 LTDC functional description", 484 ], [ 3, "16.3.2 LTDC reset and clocks", 484 ] ], "page_content": "RM0090 Rev 21\n485/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n \nCare must be taken when accessing the LTDC registers since the APB2 bus is stalling when \nthe following operations are ongoing:\n•\nRegister write access and update for 6 xPCKL2 period + 5x LCD_CLK period (5x \nHCLK period for register on AHB clock domain)\n•\nRegister read access for 7xPCKL2 period + 5x LCD_CLK period (5x HCLK period for \nregister on AHB clock domain).\nFor registers on PCLK2 clock domain, APB2 bus is stalling during the register write access \nfor 6 xPCKL2 period and 7xPCKL2 period for read access. \nThe LCD controller can be reset by setting the corresponding bit in the RCC_APB2RSTR \nregister. It resets the three clock domains.\nTable 89. LTDC registers versus clock domain\nLTDC registers\nClock domain\nLTDC_LxCR\nHCLK\nLTDC_LxCFBAR\nLTDC_LxCFBLR\nLTDC_LxCFBLNR\nLTDC_SRCR\nPCLK2\nLTDC_IER\nLTDC_ISR\nLTDC_ICR\nLTDC_SSCR\nPixel Clock (LCD_CLK)\nLTDC_BPCR\nLTDC_AWCR\nLTDC_TWCR\nLTDC_GCR\nLTDC_BCCR\nLTDC_LIPCR\nLTDC_CPSR\nLTDC_CDSR\nLTDC_LxWHPCR\nLTDC_LxWVPCR\nLTDC_LxCKCR\nLTDC_LxPFCR\nLTDC_LxCACR\nLTDC_LxDCCR\nLTDC_LxBFCR\nLTDC_LxCLUTWR\n" }, { "page_number": 486, "page_indices": { "start_index": 1002598, "end_index": 1004203 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 486 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.3 LTDC functional description", 484 ], [ 3, "16.3.3 LCD-TFT pins and signal interface", 486 ], [ 2, "16.4 LTDC programmable parameters", 486 ], [ 3, "16.4.1 LTDC Global configuration parameters", 486 ], [ 4, "Synchronous Timings:", 486 ] ], "page_content": "LCD-TFT controller (LTDC)\nRM0090\n486/1757\nRM0090 Rev 21\n16.3.3 \nLCD-TFT pins and signal interface\nThe Table below summarizes the LTDC signal interface: \n \nThe LCD-TFT controller pins must be configured by the user application. The unused pins \ncan be used for other purposes. \nFor LTDC outputs up to 24-bit (RGB888), if less than 8bpp are used to output for example \nRGB565 or RGB666 to interface on 16b-bit or 18-bit displays, the RGB display data lines \nmust be connected to the MSB of the LCD-TFT controller RGB data lines. As an example, in \nthe case of an LCD-TFT controller interfacing with a RGB565 16-bit display, the LCD display \nR[4:0], G[5:0] and B[4:0] data lines pins must be connected to LCD-TFT controller \nLCD_R[7:3], LCD_G[7:2] and LCD_B[7:3].\n16.4 \nLTDC programmable parameters\nThe LCD-TFT controller provides flexible configurable parameters. It can be enabled or \ndisabled through the LTDC_GCR register.\n16.4.1 \nLTDC Global configuration parameters\nSynchronous Timings:\nFigure 82 presents the configurable timing parameters generated by the Synchronous \nTimings Generator block presented in the block diagram Figure 81. It generates the \nHorizontal and Vertical Synchronization timings panel signals, the Pixel Clock and the Data \nEnable signals.\nTable 90. LCD-TFT pins and signal interface\nLCD-TFT \nsignals \nI/O \nDescription\nLCD_CLK\nO\nClock Output\nLCD_HSYNC\nO\nHorizontal Synchronization\nLCD_VSYNC\nO\nVertical Synchronization\nLCD_DE\nO\nNot Data Enable\nLCD_R[7:0]\nO\nData: 8-bit Red data\nLCD_G[7:0]\nO\nData: 8-bit Green data\nLCD_B[7:0]\nO\nData: 8-bit Blue data\n" }, { "page_number": 487, "page_indices": { "start_index": 1004203, "end_index": 1006027 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 487 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.4 LTDC programmable parameters", 486 ], [ 3, "16.4.1 LTDC Global configuration parameters", 486 ], [ 4, "Synchronous Timings:", 486 ] ], "page_content": "RM0090 Rev 21\n487/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\nFigure 82. LCD-TFT Synchronous timings\nNote:\nThe HBP and HFP are respectively the Horizontal back porch and front porch period.\nThe VBP and the VFP are respectively the Vertical back porch and front porch period.\nThe LCD-TFT programmable synchronous timings are: \n–\nHSYNC and VSYNC Width: Horizontal and Vertical Synchronization width \nconfigured by programming a value of HSYNC Width - 1 and VSYNC Width - 1 in \nthe LTDC_SSCR register.\n–\nHBP and VBP: Horizontal and Vertical Synchronization back porch width \nconfigured by programming the accumulated value HSYNC Width + HBP - 1 and \nthe accumulated value VSYNC Width + VBP - 1 in the LTDC_BPCR register.\n–\nActive Width and Active Height: The Active Width and Active Height are \nconfigured by programming the accumulated value HSYNC Width + HBP + \nActive Width - 1 and the accumulated value VSYNC Width + VBP + Active \nHeight - 1 in the LTDC_AWCR register (only up to 1024x768 is supported).\n–\nTotal Width: The Total width is configured by programming the accumulated value \nHSYNC Width + HBP + Active Width + HFP - 1 in the LTDC_TWCR register. The \nHFP is the Horizontal front porch period.\n–\nTotal Height: The Total Height is configured by programming the accumulated \nvalue VSYNC Height + VBP + Active Height + VFP - 1 in the LTDC_TWCR \nregister. The VFP is the Vertical front porch period.\nNote:\nWhen the LTDC is enabled, the timings generated start with X/Y=0/0 position as the first \nhorizontal synchronization pixel in the vertical synchronization area and following the back \nporch, active data display area and the front porch.\nMSv19674V1\nTotal width\nActive width\nHFP\nHBP\nHSYNC\n width\nVSYNC width\nVBP\nVFP\nActive height\nTotal height\nActive display area\nData1, Line1\nData(n), Line(n)\n" }, { "page_number": 488, "page_indices": { "start_index": 1006027, "end_index": 1008707 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 488 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.4 LTDC programmable parameters", 486 ], [ 3, "16.4.1 LTDC Global configuration parameters", 486 ], [ 4, "Example of Synchronous timings configuration", 488 ], [ 4, "Programmable polarity", 488 ], [ 4, "Background Color", 488 ], [ 4, "Dithering", 488 ] ], "page_content": "LCD-TFT controller (LTDC)\nRM0090\n488/1757\nRM0090 Rev 21\nWhen the LTDC is disabled, the timing generator block is reset to X=Total Width - 1, \nY=Total Height - 1 and held the last pixel before the vertical synchronization phase and the \nFIFO are flushed. Therefore only blanking data is output continuously.\nExample of Synchronous timings configuration\nTFT-LCD timings (should be extracted from Panel datasheet):\n•\nHorizontal and Vertical Synchronization width: 0x8 pixels and 0x4 lines\n•\nHorizontal and Vertical back porch: 0x7 pixels and 0x2 lines\n•\nActive Width and Active Height: 0x280 pixels, 0x1E0 lines (640x480)\n•\nHorizontal front porch: 0x6 pixels\n•\nVertical front porch: 0x2 lines\nThe programmed values in the LTDC timings registers are:\n•\nLTDC_SSCR register: to be programmed to 0x00070003. (HSW[11:0] is 0x7 and \nVSH[10:0] is 0x3)\n•\nLTDC_BPCR register: to be programmed to 0x000E0005. (AHBP[11:0] is 0xE(0x8 + \n0x6) and AVBP[10:0] is 0x5(0x4 + 0x1)) \n•\nLTDC_AWCR register: to be programmed to 0x028E01E5. (AAW[11:0] is 0x28E(0x8 \n+0x7 +0x27F) and AAH[10:0] is 0x1E5(0x4 +0x2 + 0x1DF)\n•\nLTDC_TWCR register: to be programmed to 0x00000294. (TOTALW[11:0] is \n0x294(0x8 +0x7 +0x280 + 0x5)\n•\nLTDC_THCR register: to be programmed to 0x000001E7. (TOTALH[10:0] is \n0x1E7(0x4 +0x2 + 0x1E0 + 1)\nProgrammable polarity\nThe Horizontal and Vertical Synchronization, Data Enable and Pixel Clock output signals \npolarity can be programmed to active high or active low through the LTDC_GCR register.\nBackground Color \nA constant background color (RGB888) can programmed through the LTDC_BCCR \nregister. It is used for blending with the bottom layer.\nDithering\nThe Dithering pseudo-random technique using an LFSR is used to add a small random \nvalue (threshold) to each pixel color channel (R, G or B) value, thus rounding up the MSB in \nsome cases when displaying a 24-bit data on 18-bit display. Thus the Dithering technique is \nused to round data which is different from one frame to the other.\nThe Dither pseudo-random technique is the same as comparing LSBs against a threshold \nvalue and adding a 1 to the MSB part only, if the LSB part is >= the threshold. The LSBs are \ntypically dropped once dithering was applied.\nThe width of the added pseudo-random value is 2 bits for each color channel; 2 bits for Red, \n2 bits for Green and 2 bits for Blue.\nOnce the LCD-TFT controller is enabled, the LFSR starts running with the first active pixel \nand it is kept running even during blanking periods and when dithering is switched off. If the \nLTDC is disabled, the LFSR is reset.\nThe Dithering can be switched On and Off on the fly through the LTDC_GCR register.\n" }, { "page_number": 489, "page_indices": { "start_index": 1008707, "end_index": 1010822 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 489 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.4 LTDC programmable parameters", 486 ], [ 3, "16.4.1 LTDC Global configuration parameters", 486 ], [ 4, "Reload Shadow registers", 489 ], [ 4, "Interrupt generation event", 489 ], [ 3, "16.4.2 Layer programmable parameters", 489 ], [ 4, "Windowing", 489 ] ], "page_content": "RM0090 Rev 21\n489/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\nReload Shadow registers\nSome configuration registers are shadowed. The shadow registers values can be reloaded \nimmediately to the active registers when writing to these registers or at the beginning of the \nvertical blanking period following the configuration in the LTDC_SRCR register. If the \nimmediate reload configuration is selected, the reload should be only activated when all new \nregisters have been written.\nThe shadow registers should not be modified again before the reload has been done. \nReading from the shadow registers returns the actual active value. The new written value \ncan only be read after the reload has taken place. \nA register reload interrupt can be generated if enabled in the LTDC_IER register. \nThe shadowed registers are all the Layer 1 and Layer 2 registers except the \nLTDC_LxCLUTWR register.\nInterrupt generation event\nRefer to Section 16.5: LTDC interrupts for interrupt configuration. \n16.4.2 \nLayer programmable parameters\nUp to two layers can be enabled, disabled and configured separately. The layer display \norder is fixed and it is bottom up. If two layers are enabled, the Layer2 is the top displayed \nwindow. \nWindowing\nEvery layer can be positioned and resized and it must be inside the Active Display area.\nThe window position and size are configured through the top-left and bottom-right X/Y \npositions and the Internal timing generator which includes the synchronous, back porch size \nand the active data area. Refer to LTDC_LxWHPCR and LTDC_WVPCR registers.\nThe programmable layer position and size defines the first/last visible pixel of a line and the \nfirst/last visible line in the window. It allows to display either the full image frame or only a \npart of the image frame. Refer to Figure 83\n•\nThe first and the last visible pixel in the layer are set by configuring the WHSTPOS[11:0] \nand WHSPPOS[11:0] in the LTDC_LxWHPCR register.\n•\nThe first and the last visible lines in the layer are set by configuring the WVSTPOS[10:0] \nand WVSPPOS[10:0] in the LTDC_LxWVPCR register.\n" }, { "page_number": 490, "page_indices": { "start_index": 1010822, "end_index": 1012237 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 490 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.4 LTDC programmable parameters", 486 ], [ 3, "16.4.2 Layer programmable parameters", 489 ], [ 4, "Pixel input Format", 490 ] ], "page_content": "LCD-TFT controller (LTDC)\nRM0090\n490/1757\nRM0090 Rev 21\nFigure 83. Layer window programmable parameters:\nPixel input Format\nThe programmable pixel format is used for the data stored in the frame buffer of a layer.\nUp to 8 input pixel formats can be configured for every layer through the LTDC_LxPFCR \nregister \nThe pixel data is read from the frame buffer and then transformed to the internal 8888 \n(ARGB) format as follows:\n•\nComponents which have a width of less than 8 bits get expanded to 8 bits by bit \nreplication. The selected bit range is concatenated multiple times until it is longer than \n8 bits. Of the resulting vector, the 8 MSB bits are chosen. Example: 5 bits of an \nRGB565 red channel become (bit positions): 43210432 (the 3 LSBs are filled with the 3 \nMSBs of the 5 bits)\nThe figure below describes the pixel data mapping depending on the selected format.\nTable 91. Pixel Data mapping versus Color Format\nARGB8888\n@+3\nAx[7:0]\n@+2\nRx[7:0]\n@+1\nGx[7:0]\n@\nBx[7:0]\n@+7\nAx+1[7:0]\n@+6\nRx+1[7:0]\n@+5\nGx+1[7:0]\n@+4\nBx+1[7:0]\nRGB888\n@+3\nBx+1[7:0]\n@+2\nRx[7:0]\n@+1\nGx[7:0]\n@\nBx[7:0]\n@+7\nGx+2[7:0]\n@+6\nBx+2[7:0]\n@+5\nRx+1[7:0]\n@+4\nGx+1[7:0]\nRGB565\n@+3\nRx+1[4:0] Gx+1[5:3]\n@+2\nGx+1[2:0] Bx+1[4:0]\n@+1\nRx[4:0] Gx[5:3]\n@\nGx[2:0] Bx[4:0]\nMSv19676V3\nActive data area\nWVSPPOS bits in \nLTDC_LxWVPCR\nWindow\nWHSPPOS bits in \nLTDC_LxWHPCR\nWHSTPOS bits in \nLTDC_LxWHPCR\nWVSTPOS bits in \nLTDC_LxWVPCR\n" }, { "page_number": 491, "page_indices": { "start_index": 1012237, "end_index": 1013733 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 491 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.4 LTDC programmable parameters", 486 ], [ 3, "16.4.2 Layer programmable parameters", 489 ], [ 4, "Color Look-Up Table (CLUT)", 491 ] ], "page_content": "RM0090 Rev 21\n491/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\nColor Look-Up Table (CLUT)\nThe CLUT can be enabled at run-time for every layer through the LTDC_LxCR register and \nit is only useful in case of indexed color when using the L8, AL44 and AL88 input pixel \nformat. \nFirst, the CLUT has to be loaded with the R, G and B values that replace the original R, G, B \nvalues of that pixel (indexed color). Each color (RGB value) has its own address which is the \nposition within the CLUT.\n@+7\nRx+3[4:0] Gx+3[5:3]\n@+6\nGx+3[2:0] Bx+3[4:0]\n@+5\nRx+2[4:0] Gx+2[5:3]\n@+4\nGx+2[2:0] Bx+2[4:0]\nARGB1555\n@+3\nAx+1[0]Rx+1[4:0]\nGx+1[4:3]\n@+2\nGx+1[2:0] Bx+1[4:0]\n@+1\nAx[0] Rx[4:0] Gx[4:3]\n@\nGx[2:0] Bx[4:0]\n@+7\nAx+3[0]Rx+3[4:0]\nGx+3[4:3]\n@+6\nGx+3[2:0] Bx+3[4:0]\n@+5\nAx+2[0]Rx+2[4:0]Gx+2[4:\n3]\n@+4\nGx+2[2:0] Bx+2[4:0]\nARGB4444\n@+3\nAx+1[3:0]Rx+1[3:0]\n@+2\nGx+1[3:0] Bx+1[3:0]\n@+1\nAx[3:0] Rx[3:0]\n@\nGx[3:0] Bx[3:0]\n@+7\nAx+3[3:0]Rx+3[3:0]\n@+6\nGx+3[3:0] Bx+3[3:0]\n@+5\nAx+2[3:0]Rx+2[3:0]\n@+4\nGx+2[3:0] Bx+2[3:0]\nL8\n@+3\nLx+3[7:0]\n@+2\nLx+2[7:0]\n@+1\nLx+1[7:0]\n@\nLx[7:0]\n@+7\nLx+7[7:0]\n@+6\nLx+6[7:0]\n@+5\nLx+5[7:0]\n@+4\nLx+4[7:0]\nAL44\n@+3\nAx+3[3:0] Lx+3[3:0]\n@+2\nAx+2[3:0] Lx+2[3:0]\n@+1\nAx+1[3:0] Lx+1[3:0]\n@\nAx[3:0] Lx[3:0]\n@+7\nAx+7[3:0] Lx+7[3:0]\n@+6\nAx+6[3:0] Lx+6[3:0]\n@+5\nAx+5[3:0] Lx+5[3:0]\n@+4\nAx+4[3:0] Lx+4[3:0]\nAL88\n@+3\nAx+1[7:0]\n@+2\nLx+1[7:0]\n@+1\nAx[7:0]\n@\nLx[7:0]\n@+7\nAx+3[7:0]\n@+6\nLx+3[7:0]\n@+5\nAx+2[7:0]\n@+4\nLx+2[7:0]\nTable 91. Pixel Data mapping versus Color Format (continued)\nARGB8888\n" }, { "page_number": 492, "page_indices": { "start_index": 1013733, "end_index": 1015863 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 492 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.4 LTDC programmable parameters", 486 ], [ 3, "16.4.2 Layer programmable parameters", 489 ], [ 4, "Color Frame Buffer Address", 492 ], [ 4, "Color Frame Buffer Length", 492 ], [ 4, "Color Frame Buffer Pitch", 492 ], [ 4, "Layer Blending", 492 ] ], "page_content": "LCD-TFT controller (LTDC)\nRM0090\n492/1757\nRM0090 Rev 21\nThe R, G and B values and their own respective address are programmed through the \nLTDC_LxCLUTWR register.\n•\nIn case of L8 and AL88 input pixel format, the CLUT has to be loaded by 256 colors. The \naddress of each color is configured in the CLUTADD bits in the LTDC_LxCLUTWR \nregister.\n•\nIn case of AL44 input pixel format, the CLUT has to be only loaded by 16 colors. The \naddress of each color must be filled by replicating the 4-bit L channel to 8-bit as follows:\n–\nL0 (indexed color 0), at address 0x00\n–\nL1, at address 0x11\n–\nL2, at address 0x22\n–\n.....\n–\nL15, at address 0xFF\nColor Frame Buffer Address\nEvery Layer has a start address for the color frame buffer configured through the \nLTDC_LxCFBAR register.\nWhen a layer is enabled, the data is fetched from the Color Frame Buffer.\nColor Frame Buffer Length\nEvery layer has a total line length setting for the color frame buffer in bytes and a number of \nlines in the frame buffer configurable in the LTDC_LxCFBLR and LTDC_LxCFBLNR \nregister respectively.\nThe line length and the number of lines settings are used to stop the prefetching of data to \nthe layer FIFO at the end of the frame buffer.\n•\nIf it is set to less bytes than required, a FIFO underrun interrupt is generated if it has \nbeen previously enabled.\n•\nIf it is set to more bytes than actually required, the useless data read from the FIFO is \ndiscarded. The useless data is not displayed.\nColor Frame Buffer Pitch\nEvery layer has a configurable pitch for the color frame buffer, which is the distance between \nthe start of one line and the beginning of the next line in bytes. It is configured through the \nLTDC_LxCFBLR register.\nLayer Blending\nThe blending is always active and the two layers can be blended following the blending \nfactors configured through the LTDC_LxBFCR register.\nThe blending order is fixed and it is bottom up. If two layers are enabled, first the Layer1 is \nblended with the Background color, then the Layer2 is blended with the result of blended \ncolor of Layer1 and the background. Refer to Figure 84.\n" }, { "page_number": 493, "page_indices": { "start_index": 1015863, "end_index": 1017852 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 493 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.4 LTDC programmable parameters", 486 ], [ 3, "16.4.2 Layer programmable parameters", 489 ], [ 4, "Default color", 493 ], [ 4, "Color Keying", 493 ], [ 2, "16.5 LTDC interrupts", 493 ] ], "page_content": "RM0090 Rev 21\n493/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\nFigure 84. Blending two layers with background\nDefault color\nEvery layer can have a default color in the format ARGB which is used outside the defined \nlayer window or when a layer is disabled.\nThe default color is configured through the LTDC_LxDCCR register.\nThe blending is always performed between the two layers even when a layer is disabled. To \navoid displaying the default color when a layer is disabled, keep the blending factors of this \nlayer in the LTDC_LxBFCR register to their reset value.\nColor Keying\nA color key (RGB) can be configured to be representative for a transparent pixel.\nIf the Color Keying is enabled, the current pixels (after format conversion and before \nblending) are compared to the color key. If they match for the programmed RGB value, all \nchannels (ARGB) of that pixel are set to 0.\nThe Color Key value can be configured and used at run-time to replace the pixel RGB value.\nThe Color Keying is enabled through the LTDC_LxCKCR register.\n16.5 \nLTDC interrupts\nThe LTDC provides four maskable interrupts logically ORed to two interrupt vectors.\nThe interrupt sources can be enabled or disabled separately through the LTDC_IER \nregister. Setting the appropriate mask bit to 1 enables the corresponding interrupt.\nThe two interrupts are generated on the following events:\n•\nLine interrupt: generated when a programmed line is reached. The line interrupt \nposition is programmed in the LTDC_LIPCR register\n•\nRegister Reload interrupt: generated when the shadow registers reload was performed \nduring the vertical blanking period\n•\nFIFO Underrun interrupt: generated when a pixel is requested from an empty layer \nFIFO\n•\nTransfer Error interrupt: generated when an AHB bus error occurs during data transfer \nThose interrupts events are connected to the NVIC controller as described in the figure \nbelow.\nMS19677V1\nLayer 2\nLayer 1\nBG\nLayer 2\nLayer 1 + BG\nLayer 2 +\nLayer 1 + BG\n" }, { "page_number": 494, "page_indices": { "start_index": 1017852, "end_index": 1018262 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 494 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.5 LTDC interrupts", 493 ] ], "page_content": "LCD-TFT controller (LTDC)\nRM0090\n494/1757\nRM0090 Rev 21\nFigure 85. Interrupt events\n \nTable 92. LTDC interrupt requests\nInterrupt event\nEvent flag\nEnable Control bit\nLine \nLIF\nLIE\nRegister Reload \nRRIF\nRRIEN\nFIFO Underrun\nFUDERRIF\nFUDERRIE\nTransfer Error \nTERRIF\nTERRIE\nLine\nRegister reload\nLTDC global interrupt\nMS19678V1\nFIFO underrun\nTransfer error\nLTDC global error interrupt\n" }, { "page_number": 495, "page_indices": { "start_index": 1018262, "end_index": 1020441 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 495 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.6 LTDC programming procedure", 495 ] ], "page_content": "RM0090 Rev 21\n495/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.6 \nLTDC programming procedure\n•\nEnable the LTDC clock in the RCC register\n•\nConfigure the required Pixel clock following the panel datasheet\n•\nConfigure the Synchronous timings: VSYNC, HSYNC, Vertical and Horizontal back \nporch, active data area and the front porch timings following the panel datasheet as \ndescribed in the Section 16.4.1: LTDC Global configuration parameters\n•\nConfigure the synchronous signals and clock polarity in the LTDC_GCR register\n•\nIf needed, configure the background color in the LTDC_BCCR register\n•\nConfigure the needed interrupts in the LTDC_IER and LTDC_LIPCR register\n•\nConfigure the Layer1/2 parameters by programming:\n–\nThe Layer window horizontal and vertical position in the LTDC_LxWHPCR and \nLTDC_WVPCR registers. The layer window must be in the active data area.\n–\nThe pixel input format in the LTDC_LxPFCR register\n–\nThe color frame buffer start address in the LTDC_LxCFBAR register\n–\nThe line length and pitch of the color frame buffer in the LTDC_LxCFBLR register\n–\nThe number of lines of the color frame buffer in the LTDC_LxCFBLNR register\n–\nif needed, load the CLUT with the RGB values and its address in the \nLTDC_LxCLUTWR register\n–\nIf needed, configure the default color and the blending factors respectively in the \nLTDC_LxDCCR and LTDC_LxBFCR registers\n•\nEnable Layer1/2 and if needed the CLUT in the LTDC_LxCR register\n•\nIf needed, dithering and color keying can be enabled respectively in the LTDC_GCR \nand LTDC_LxCKCR registers. It can be also enabled on the fly.\n•\nReload the shadow registers to active register through the LTDC_SRCR register.\n•\nEnable the LCD-TFT controller in the LTDC_GCR register.\n•\nAll layer parameters can be modified on the fly except the CLUT. The new configuration \nhas to be either reloaded immediately or during vertical blanking period by configuring \nthe LTDC_SRCR register.\nNote:\nAll layer’s registers are shadowed. Once a register is written, it should not be modified again \nbefore the reload has been done. Thus, a new write to the same register overrides the \nprevious configuration if not yet reloaded.\n" }, { "page_number": 496, "page_indices": { "start_index": 1020441, "end_index": 1022210 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 496 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.1 LTDC Synchronization Size Configuration Register (LTDC_SSCR)", 496 ], [ 3, "16.7.2 LTDC Back Porch Configuration Register (LTDC_BPCR)", 496 ] ], "page_content": "LCD-TFT controller (LTDC)\nRM0090\n496/1757\nRM0090 Rev 21\n16.7 \nLTDC registers\n16.7.1 \nLTDC Synchronization Size Configuration Register (LTDC_SSCR)\nThis register defines the number of Horizontal Synchronization pixels minus 1 and the \nnumber of Vertical Synchronization lines minus 1. Refer to Figure 82 and Section 16.4: \nLTDC programmable parameters for an example of configuration.\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n16.7.2 \nLTDC Back Porch Configuration Register (LTDC_BPCR)\nThis register defines the accumulated number of Horizontal Synchronization and back porch \npixels minus 1 (HSYNC Width + HBP- 1) and the accumulated number of Vertical \nSynchronization and back porch lines minus 1 (VSYNC Height + VBP - 1). Refer to \nFigure 82 and Section 16.4: LTDC programmable parameters for an example of \nconfiguration.\nAddress offset: 0x0C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nHSW[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nVSH[10:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value\nBits 27:16 HSW[11:0]: Horizontal Synchronization Width (in units of pixel clock period)\nThese bits define the number of Horizontal Synchronization pixel minus 1.\nBits 15:11 Reserved, must be kept at reset value\nBits 10:0 VSH[10:0]: Vertical Synchronization Height (in units of horizontal scan line)\nThese bits define the vertical Synchronization height minus 1. It represents the \nnumber\nof horizontal synchronization lines.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nAHBP[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nAVBP[10:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 497, "page_indices": { "start_index": 1022210, "end_index": 1024651 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 497 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.3 LTDC Active Width Configuration Register (LTDC_AWCR)", 497 ] ], "page_content": "RM0090 Rev 21\n497/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.7.3 \nLTDC Active Width Configuration Register (LTDC_AWCR)\nThis register defines the accumulated number of Horizontal Synchronization, back porch \nand Active pixels minus 1 (HSYNC width + HBP + Active Width - 1) and the accumulated \nnumber of Vertical Synchronization, back porch lines and Active lines minus 1 (VSYNC \nHeight+ BVBP + Active Height - 1). Refer to Figure 82 and Section 16.4: LTDC \nprogrammable parameters for an example of configuration.\nAddress offset: 0x10\nReset value: 0x0000 0000\nBits 31:28 Reserved, must be kept at reset value\nBits 27:16 AHBP[11:0]: Accumulated Horizontal back porch (in units of pixel clock period)\nThese bits define the Accumulated Horizontal back porch width which includes the \nHorizontal Synchronization and Horizontal back porch pixels minus 1.\nThe Horizontal back porch is the period between Horizontal Synchronization going \ninactive and the start of the active display part of the next scan line.\nBits 15:11 Reserved, must be kept at reset value\nBits 10:0 AVBP[10:0]: Accumulated Vertical back porch (in units of horizontal scan line)\nThese bits define the accumulated Vertical back porch width which includes the Vertical \nSynchronization and Vertical back porch lines minus 1.\nThe Vertical back porch is the number of horizontal scan lines at a start of frame to the \nstart of the first active scan line of the next frame.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nAAW[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nAAH[10:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value\nBits 27:16 AAW[11:0]: Accumulated Active Width (in units of pixel clock period)\nThese bits define the Accumulated Active Width which includes the Horizontal \nSynchronization, Horizontal back porch and Active pixels minus 1.\nThe Active Width is the number of pixels in active display area of the panel scan line. The \nmaximum Active Width supported is 0x400.\nBits 15:11 Reserved, must be kept at reset value\nBits 10:0 AAH[10:0]: Accumulated Active Height (in units of horizontal scan line)\nThese bits define the Accumulated Height which includes the Vertical Synchronization, \nVertical back porch and the Active Height lines minus 1. The Active Height is the number \nof active lines in the panel. The maximum Active Height supported is 0x300.\n" }, { "page_number": 498, "page_indices": { "start_index": 1024651, "end_index": 1026461 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 498 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.4 LTDC Total Width Configuration Register (LTDC_TWCR)", 498 ], [ 3, "16.7.5 LTDC Global Control Register (LTDC_GCR)", 498 ] ], "page_content": "LCD-TFT controller (LTDC)\nRM0090\n498/1757\nRM0090 Rev 21\n16.7.4 \nLTDC Total Width Configuration Register (LTDC_TWCR)\nThis register defines the accumulated number of Horizontal Synchronization, back porch, \nActive and front porch pixels minus 1 (HSYNC Width + HBP + Active Width + HFP - 1) and \nthe accumulated number of Vertical Synchronization, back porch lines, Active and Front \nlines minus 1 (VSYNC Height+ BVBP + Active Height + VFP - 1). Refer to Figure 82 and \nSection 16.4: LTDC programmable parameters for an example of configuration.\nAddress offset: 0x14\nReset value: 0x0000 0000\n16.7.5 \nLTDC Global Control Register (LTDC_GCR)\nThis register defines the global configuration of the LCD-TFT controller. \nAddress offset: 0x18\nReset value: 0x0000 2220\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nTOTALW[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n16\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTOTALH[10:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value\nBits 27:16 TOTALW[11:0]: Total Width (in units of pixel clock period)\nThese bits defines the accumulated Total Width which includes the Horizontal \nSynchronization, Horizontal back porch, Active Width and Horizontal front porch pixels \nminus 1.\nBits 15:11 Reserved, must be kept at reset value\nBits 10:0 TOTALH[10:0]: Total Height (in units of horizontal scan line)\nThese bits defines the accumulated Height which includes the Vertical Synchronization, \nVertical back porch, the Active Height and Vertical front porch Height lines minus 1.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nHSPOL\nVSPOL\nDEPOL PCPOL\nReserved\nDEN\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserve\nd\nDRW[2:0]\nReser\nved\nDGW[2:0]\nReser\nved\nDBW[2:0]\nReserved\nLTDCEN\nr\nr\nr\nr\nr\nr\nr\nr\nr\nrw\n" }, { "page_number": 499, "page_indices": { "start_index": 1026461, "end_index": 1027883 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 499 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.5 LTDC Global Control Register (LTDC_GCR)", 498 ] ], "page_content": "RM0090 Rev 21\n499/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\nBit 31 HSPOL: Horizontal Synchronization Polarity\nThis bit is set and cleared by software.\n0: Horizontal Synchronization polarity is active low\n1: Horizontal Synchronization polarity is active high\nBit 30 VSPOL: Vertical Synchronization Polarity\nThis bit is set and cleared by software.\n0: Vertical Synchronization is active low \n1: Vertical Synchronization is active high\nBit 29 DEPOL: Data Enable Polarity\nThis bit is set and cleared by software.\n0: Data Enable polarity is active low\n1: Data Enable polarity is active high\nBit 28 PCPOL: Pixel Clock Polarity\nThis bit is set and cleared by software.\n0: input pixel clock\n1: inverted input pixel clock\nBits 27:17 Reserved, must be kept at reset value\nBit 16 DEN: Dither Enable \nThis bit is set and cleared by software.\n0: Dither disable\n1: Dither enable\nBit 15 Reserved, must be kept at reset value\nBits 14:12 DRW[2:0]: Dither Red Width \nThese bits return the Dither Red Bits \nBit 11 Reserved, must be kept at reset value\nBits 10:8 DGW[2:0]: Dither Green Width \nThese bits return the Dither Green Bits \nBit 7 Reserved, must be kept at reset value\nBits 6:4 DBW[2:0]: Dither Blue Width \nThese bits return the Dither Blue Bits \nBits 3:1 Reserved, must be kept at reset value\nBit 0 LTDCEN: LCD-TFT controller enable bit \nThis bit is set and cleared by software.\n0: LTDC disable\n1: LTDC enable\n" }, { "page_number": 500, "page_indices": { "start_index": 1027883, "end_index": 1029430 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 500 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.6 LTDC Shadow Reload Configuration Register (LTDC_SRCR)", 500 ], [ 3, "16.7.7 LTDC Background Color Configuration Register (LTDC_BCCR)", 500 ] ], "page_content": "LCD-TFT controller (LTDC)\nRM0090\n500/1757\nRM0090 Rev 21\n16.7.6 \nLTDC Shadow Reload Configuration Register (LTDC_SRCR)\nThis register allows to reload either immediately or during the vertical blanking period, the \nshadow registers values to the active registers. The shadow registers are all Layer1 and \nLayer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR.\nAddress offset: 0x24\nReset value: 0x0000 0000\nNote:\nThe shadow registers read back the active values. Until the reload has been done, the 'old' \nvalue is read.\n16.7.7 \nLTDC Background Color Configuration Register (LTDC_BCCR)\nThis register defines the background color (RGB888).\nAddress offset: 0x2C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nVBR\nIMR\nrw\nrw\nBits 31:2 Reserved, must be kept at reset value\nBit 1 VBR: Vertical Blanking Reload\nThis bit is set by software and cleared only by hardware after reload. (it cannot be cleared \nthrough register write once it is set) \n0: No effect\n1: The shadow registers are reloaded during the vertical blanking period (at the \nbeginning of the first line after the Active Display Area)\nBit 0 IMR: Immediate Reload\nThis bit is set by software and cleared only by hardware after reload.\n0: No effect\n1: The shadow registers are reloaded immediately\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nBCRED[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nBCGREEN[7:0]\nBCBLUE[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 501, "page_indices": { "start_index": 1029430, "end_index": 1030842 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 501 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.8 LTDC Interrupt Enable Register (LTDC_IER)", 501 ] ], "page_content": "RM0090 Rev 21\n501/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.7.8 \nLTDC Interrupt Enable Register (LTDC_IER)\nThis register determines which status flags generate an interrupt request by setting the \ncorresponding bit to 1.\nAddress offset: 0x34\nReset value: 0x0000 0000\nBits 31:24 Reserved, must be kept at reset value\nBits 23:16 BCRED[7:0]: Background Color Red value\nThese bits configure the background red value\nBits 15:8 BCGREEN[7:0]: Background Color Green value\nThese bits configure the background green value\nBits 7:0 BCBLUE[7:0]: Background Color Blue value\nThese bits configure the background blue value\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRRIE\nTERRIE\nFUIE\nLIE\nrw\nrw\nrw\nrw\nBits 31:4 Reserved, must be kept at reset value\nBit 3 RRIE: Register Reload interrupt enable\nThis bit is set and cleared by software\n0: Register Reload interrupt disable\n1: Register Reload interrupt enable\nBit 2 TERRIE: Transfer Error Interrupt Enable\nThis bit is set and cleared by software\n0: Transfer Error interrupt disable\n1: Transfer Error interrupt enable\nBit 1 FUIE: FIFO Underrun Interrupt Enable \nThis bit is set and cleared by software\n0: FIFO Underrun interrupt disable\n1: FIFO Underrun Interrupt enable\nBit 0 LIE: Line Interrupt Enable\nThis bit is set and cleared by software\n0: Line interrupt disable\n1: Line Interrupt enable\n" }, { "page_number": 502, "page_indices": { "start_index": 1030842, "end_index": 1032173 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 502 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.9 LTDC Interrupt Status Register (LTDC_ISR)", 502 ], [ 3, "16.7.10 LTDC Interrupt Clear Register (LTDC_ICR)", 502 ] ], "page_content": "LCD-TFT controller (LTDC)\nRM0090\n502/1757\nRM0090 Rev 21\n16.7.9 \nLTDC Interrupt Status Register (LTDC_ISR)\nThis register returns the interrupt status flag\nAddress offset: 0x38\nReset value: 0x0000 0000\n16.7.10 \nLTDC Interrupt Clear Register (LTDC_ICR)\nAddress offset: 0x3C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRRIF\nTERRIF\nFUIF\nLIF\nr\nr\nr\nr\nBits 31:24 Reserved, must be kept at reset value\nBit 3 RRIF: Register Reload Interrupt Flag\n0: No Register Reload interrupt generated\n1: Register Reload interrupt generated when a vertical blanking reload occurs (and the \nfirst line after the active area is reached)\nBit 2 TERRIF: Transfer Error interrupt flag\n0: No Transfer Error interrupt generated\n1: Transfer Error interrupt generated when a Bus error occurs\nBit 1 FUIF: FIFO Underrun Interrupt flag \n0: NO FIFO Underrun interrupt generated.\n1: A FIFO underrun interrupt is generated, if one of the layer FIFOs is empty and pixel \ndata is read from the FIFO\nBit 0 LIF: Line Interrupt flag\n0: No Line interrupt generated\n1: A Line interrupt is generated, when a programmed line is reached\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCRRIF\nCTERRIF\nCFUIF\nCLIF\nw\nw\nw\nw\n" }, { "page_number": 503, "page_indices": { "start_index": 1032173, "end_index": 1033606 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 503 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.11 LTDC Line Interrupt Position Configuration Register (LTDC_LIPCR)", 503 ], [ 3, "16.7.12 LTDC Current Position Status Register (LTDC_CPSR)", 503 ] ], "page_content": "RM0090 Rev 21\n503/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.7.11 \nLTDC Line Interrupt Position Configuration Register (LTDC_LIPCR)\nThis register defines the position of the line interrupt. The line value to be programmed \ndepends on the timings parameters. Refer to Figure 82.\nAddress offset: 0x40\nReset value: 0x0000 0000\n16.7.12 \nLTDC Current Position Status Register (LTDC_CPSR)\nAddress offset: 0x44\nReset value: 0x0000 0000\nBits 31:24 Reserved, must be kept at reset value\nBit 3 CRRIF: Clears Register Reload Interrupt Flag \n0: No effect\n1: Clears the RRIF flag in the LTDC_ISR register\nBit 2 CTERRIF: Clears the Transfer Error Interrupt Flag \n0: No effect\n1: Clears the TERRIF flag in the LTDC_ISR register.\nBit 1 CFUIF: Clears the FIFO Underrun Interrupt flag \n0: No effect\n1: Clears the FUDERRIF flag in the LTDC_ISR register.\nBit 0 CLIF: Clears the Line Interrupt Flag \n0: No effect\n1: Clears the LIF flag in the LTDC_ISR register.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLIPOS[10:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:11 Reserved, must be kept at reset value\nBits 10:0 LIPOS[10:0]: Line Interrupt Position\nThese bits configure the line interrupt position\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCXPOS[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCYPOS{15;0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n" }, { "page_number": 504, "page_indices": { "start_index": 1033606, "end_index": 1034968 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 504 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.13 LTDC Current Display Status Register (LTDC_CDSR)", 504 ] ], "page_content": "LCD-TFT controller (LTDC)\nRM0090\n504/1757\nRM0090 Rev 21\n16.7.13 \nLTDC Current Display Status Register (LTDC_CDSR)\nThis register returns the status of the current display phase which is controlled by the \nHSYNC, VSYNC, and Horizontal/Vertical DE signals.\nExample: if the current display phase is the vertical synchronization, the VSYNCS bit is set \n(active high). If the current display phase is the horizontal synchronization, the HSYNCS bit \nis active high.\nAddress offset: 0x48\nReset value: 0x0000 000F\nNote:\nThe returned status does not depend on the configured polarity in the LTDC_GCR register, \ninstead it returns the current active display phase.\nBits 31:16: CXPOS[15:0]: Current X Position \nThese bits return the current X position \nBits 15:0 CYPOS[15:0]: Current Y Position \nThese bits return the current Y position\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nHSYNC\nS\nVSYNC\nS\nHDES\nVDES\nr\nr\nr\nr\nBits 31:24 Reserved, must be kept at reset value\nBit 3 HSYNCS: Horizontal Synchronization display Status\n0: Active low \n1: Active high\nBit 2 VSYNCS: Vertical Synchronization display Status\n0: Active low \n1: Active high\nBit 1 HDES: Horizontal Data Enable display Status\n0: Active low \n1: Active high\nBit 0 VDES: Vertical Data Enable display Status\n0: Active low \n1: Active high\n" }, { "page_number": 505, "page_indices": { "start_index": 1034968, "end_index": 1035952 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 505 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.14 LTDC Layerx Control Register (LTDC_LxCR) (where x=1..2)", 505 ] ], "page_content": "RM0090 Rev 21\n505/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.7.14 \nLTDC Layerx Control Register (LTDC_LxCR) (where x=1..2) \nAddress offset: 0x84 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCLUTEN\nReserved\nCOLKEN\nLEN\nrw\nrw\nrw\nBits 31:5 Reserved, must be kept at reset value\nBit 4 CLUTEN: Color Look-Up Table Enable\nThis bit is set and cleared by software.\n0: Color Look-Up Table disable\n1: Color Look-Up Table enable\nThe CLUT is only meaningful for L8, AL44 and AL88 pixel format. Refer to Color Look-Up \nTable (CLUT) on page 491\nBit 3 Reserved, must be kept at reset value\nBit 2 Reserved, must be kept at reset value\nBit 1 COLKEN: Color Keying Enable\nThis bit is set and cleared by software.\n0: Color Keying disable\n1: Color Keying enable\nBit 0 LEN: Layer Enable\nThis bit is set and cleared by software.\n0: Layer disable\n1: Layer enable\n" }, { "page_number": 506, "page_indices": { "start_index": 1035952, "end_index": 1037791 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 506 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.15 LTDC Layerx Window Horizontal Position Configuration Register (LTDC_LxWHPCR) (where x=1..2)", 506 ] ], "page_content": "LCD-TFT controller (LTDC)\nRM0090\n506/1757\nRM0090 Rev 21\n16.7.15 \nLTDC Layerx Window Horizontal Position Configuration Register\n(LTDC_LxWHPCR) (where x=1..2)\nThis register defines the Horizontal Position (first and last pixel) of the layer 1 or 2 window.\nThe first visible pixel of a line is the programmed value of AHBP[10:0] bits + 1 in the \nLTDC_BPCR register.\nThe last visible pixel of a line is the programmed value of AAW[10:0] bits in the \nLTDC_AWCR register. \nAddress offset: 0x88 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\n \nExample: \nThe LTDC_BPCR register is configured to 0x000E0005(AHBP[11:0] is 0xE) and the \nLTDC_AWCR register is configured to 0x028E01E5(AAW[11:0] is 0x28E). To configure the \nhorizontal position of a window size of 630x460, with horizontal start offset of 5 pixels in the \nActive data area.\n1.\nLayer window first pixel: WHSTPOS[11:0] should be programmed to 0x14 (0xE+1+0x5)\n2. \nLayer window last pixel: WHSPPOS[11:0] should be programmed to 0x28A\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nWHSPPOS[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nWHSTPOS[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value\nBits 27:16 WHSPPOS[11:0]: Window Horizontal Stop Position\nThese bits configure the last visible pixel of a line of the layer window.\nThe following condition must be respected: \nWHSPPOS[11:0] ≥ AHBP[10:0] bits + 1 (programmed in LTDC_BPCR register)\nBits 15:12 Reserved, must be kept at reset value\nBits 11:0 WHSTPOS[11:0]: Window Horizontal Start Position\nThese bits configure the first visible pixel of a line of the layer window.\nThe following condition must be respected: \nWHSTPOS[11:0] must be ≤ AAW[10:0] bits (programmed in the LTDC_AWCR \nregister).\n" }, { "page_number": 507, "page_indices": { "start_index": 1037791, "end_index": 1039603 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 507 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.16 LTDC Layerx Window Vertical Position Configuration Register (LTDC_LxWVPCR) (where x=1..2)", 507 ] ], "page_content": "RM0090 Rev 21\n507/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.7.16 \nLTDC Layerx Window Vertical Position Configuration Register\n(LTDC_LxWVPCR) (where x=1..2)\nThis register defines the vertical position (first and last line) of the layer1 or 2 window. \nThe first visible line of a frame is the programmed value of AVBP[10:0] bits + 1 in the \nregister LTDC_BPCR register. \nThe last visible line of a frame is the programmed value of AAH[10:0] bits in the \nLTDC_AWCR register.\nAddress offset: 0x8C + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\nExample:\nThe LTDC_BPCR register is configured to 0x000E0005 (AVBP[10:0] is 0x5) and the \nLTDC_AWCR register is configured to 0x028E01E5 (AAH[10:0] is 0x1E5). To configure the \nvertical position of a window size of 630x460, with vertical start offset of 8 lines in the Active \ndata area:\n1.\nLayer window first line: WVSTPOS[10:0] should be programmed to 0xE (0x5 + 1 + 0x8)\n2. \nLayer window last line: WVSPPOS[10:0] should be programmed to 0x1DA\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nWVSPPOS[10:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nWVSTPOS[10:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:27 Reserved, must be kept at reset value\nBits 26:16 WVSPPOS[10:0]: Window Vertical Stop Position\nThese bits configures the last visible line of the layer window. \nThe following condition must be respected: \nWHSPPOS[11:0] must be ≥ AVBP[10:0] bits + 1 (programmed in LTDC_BPCR \nregister)\nBits 15:11 Reserved, must be kept at reset value\nBits 10:0 WVSTPOS[10:0]: Window Vertical Start Position\nThese bits configure the first visible line of the layer window.\nThe following condition must be respected: \nWHSTPOS[11:0] must be ≤ AAH[10:0] bits (programmed in the LTDC_AWCR register) \n" }, { "page_number": 508, "page_indices": { "start_index": 1039603, "end_index": 1040799 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 508 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.17 LTDC Layerx Color Keying Configuration Register (LTDC_LxCKCR) (where x=1..2)", 508 ], [ 3, "16.7.18 LTDC Layerx Pixel Format Configuration Register (LTDC_LxPFCR) (where x=1..2)", 508 ] ], "page_content": "LCD-TFT controller (LTDC)\nRM0090\n508/1757\nRM0090 Rev 21\n16.7.17 \nLTDC Layerx Color Keying Configuration Register (LTDC_LxCKCR)\n(where x=1..2)\nThis register defines the color key value (RGB), which is used by the Color Keying.\nAddress offset: 0x90 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\n16.7.18 \nLTDC Layerx Pixel Format Configuration Register (LTDC_LxPFCR)\n(where x=1..2)\nThis register defines the pixel format which is used for the stored data in the frame buffer of \na layer. The pixel data is read from the frame buffer and then transformed to the internal \nformat 8888 (ARGB).\nAddress offset: 0x94 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nCKRED[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCKGREEN[7:0]\nCKBLUE[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value\nBits 23:16 CKRED[7:0]: Color Key Red value\nBits 15:8 CKGREEN[7:0]: Color Key Green value\nBits 7:0 CKBLUE[7:0]: Color Key Blue value \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPF[2:0]\nrw\nrw\nrw\n" }, { "page_number": 509, "page_indices": { "start_index": 1040799, "end_index": 1042326 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 509 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.19 LTDC Layerx Constant Alpha Configuration Register (LTDC_LxCACR) (where x=1..2)", 509 ], [ 3, "16.7.20 LTDC Layerx Default Color Configuration Register (LTDC_LxDCCR) (where x=1..2)", 509 ] ], "page_content": "RM0090 Rev 21\n509/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.7.19 \nLTDC Layerx Constant Alpha Configuration Register (LTDC_LxCACR)\n(where x=1..2)\nThis register defines the constant alpha value (divided by 255 by Hardware), which is used \nin the alpha blending. Refer to LTDC_LxBFCR register.\nAddress offset: 0x98 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: (Layerx -1) 0x0000 00FF\n16.7.20 \nLTDC Layerx Default Color Configuration Register (LTDC_LxDCCR)\n(where x=1..2)\nThis register defines the default color of a layer in the format ARGB. The default color is \nused outside the defined layer window or when a layer is disabled. The reset value of \n0x00000000 defines a transparent black color.\nAddress offset: 0x9C + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\nBits 31:3 Reserved, must be kept at reset value\nBits 2:0 PF[2:0]: Pixel Format \nThese bits configures the Pixel format\n000: ARGB8888\n001: RGB888\n010: RGB565\n011: ARGB1555\n100: ARGB4444\n101: L8 (8-Bit Luminance)\n110: AL44 (4-Bit Alpha, 4-Bit Luminance)\n111: AL88 (8-Bit Alpha, 8-Bit Luminance)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCONSTA[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value\nBits 7:0 CONSTA[7:0]: Constant Alpha\nThese bits configure the Constant Alpha used for blending. The Constant Alpha is divided \nby 255 by hardware.\nExample: if the programmed Constant Alpha is 0xFF, the Constant Alpha value is \n255/255=1\n" }, { "page_number": 510, "page_indices": { "start_index": 1042326, "end_index": 1042942 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 510 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.20 LTDC Layerx Default Color Configuration Register (LTDC_LxDCCR) (where x=1..2)", 509 ] ], "page_content": "LCD-TFT controller (LTDC)\nRM0090\n510/1757\nRM0090 Rev 21\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDCALPHA[7:0]\nDCRED[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDCGREEN[7:0]\nDCBLUE[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 DCALPHA[7:0]: Default Color Alpha\nThese bits configure the default alpha value\nBits 23:16 DCRED[7:0]: Default Color Red\nThese bits configure the default red value\nBits 15:8 DCGREEN[7:0]: Default Color Green\nThese bits configure the default green value\nBits 7:0 DCBLUE[7:0]: Default Color Blue \nThese bits configure the default blue value\n" }, { "page_number": 511, "page_indices": { "start_index": 1042942, "end_index": 1044128 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 511 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.21 LTDC Layerx Blending Factors Configuration Register (LTDC_LxBFCR) (where x=1..2)", 511 ] ], "page_content": "RM0090 Rev 21\n511/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.7.21 \nLTDC Layerx Blending Factors Configuration Register (LTDC_LxBFCR)\n(where x=1..2)\nThis register defines the blending factors F1 and F2.\nThe general blending formula is: BC = BF1 x C + BF2 x Cs\n•\nBC = Blended color\n•\nBF1 = Blend Factor 1\n•\nC = Current layer color\n•\nBF2 = Blend Factor 2\n•\nCs = subjacent layers blended color\nAddress offset: 0xA0 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0607\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBF1[2:0]\nReserved\nBF2[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:11 Reserved, must be kept at reset value\nBits 10:8 BF1[2:0]: Blending Factor 1\nThese bits select the blending factor F1\n000: Reserved\n001: Reserved\n010: Reserved\n011: Reserved\n100: Constant Alpha\n101: Reserved\n110: Pixel Alpha x Constant Alpha\n111:Reserved\nBits 7:3 Reserved, must be kept at reset value\nBits 2:0 BF2[2:0]: Blending Factor 2 \nThese bits select the blending factor F2\n000: Reserved\n001: Reserved\n010: Reserved\n011: Reserved\n100: Reserved\n101: 1 - Constant Alpha\n110: Reserved\n111: 1 - (Pixel Alpha x Constant Alpha)\n" }, { "page_number": 512, "page_indices": { "start_index": 1044128, "end_index": 1045858 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 512 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.22 LTDC Layerx Color Frame Buffer Address Register (LTDC_LxCFBAR) (where x=1..2)", 512 ], [ 3, "16.7.23 LTDC Layerx Color Frame Buffer Length Register (LTDC_LxCFBLR) (where x=1..2)", 512 ] ], "page_content": "LCD-TFT controller (LTDC)\nRM0090\n512/1757\nRM0090 Rev 21\nNote:\nThe Constant Alpha value, is the programmed value in the LxCACR register divided by 255 \nby hardware.\nExample: Only layer1 is enabled, BF1 configured to Constant Alpha\nBF2 configured to 1 - Constant Alpha\nConstant Alpha: The Constant Alpha programmed in the LxCACR register is 240 (0xF0). \nThus, the Constant Alpha value is 240/255 = 0.94\nC: Current Layer Color is 128\nCs: Background color is 48\nLayer1 is blended with the background color. \nBC = Constant Alpha x C + (1 - Constant Alpha) x Cs = 0.94 x 128 + (1- 0.94) x 48 = 123.\n16.7.22 \nLTDC Layerx Color Frame Buffer Address Register (LTDC_LxCFBAR)\n(where x=1..2)\nThis register defines the color frame buffer start address which has to point to the address \nwhere the pixel data of the top left pixel of a layer is stored in the frame buffer.\nAddress offset: 0xAC + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\n16.7.23 \nLTDC Layerx Color Frame Buffer Length Register (LTDC_LxCFBLR)\n(where x=1..2)\nThis register defines the color frame buffer line length and pitch.\nAddress offset: 0xB0 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCFBADD[31:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCFBADD[31:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 CFBADD[31:0]: Color Frame Buffer Start Address\nThese bits defines the color frame buffer start address.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nCFBP[12:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCFBLL[12:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 513, "page_indices": { "start_index": 1045858, "end_index": 1047823 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 513 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.24 LTDC Layerx ColorFrame Buffer Line Number Register (LTDC_LxCFBLNR) (where x=1..2)", 513 ] ], "page_content": "RM0090 Rev 21\n513/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\nExample:\n•\nA frame buffer having the format RGB565 (2 bytes per pixel) and a width of 256 pixels \n(total number of bytes per line is 256x2=512 bytes), where pitch = line length requires a \nvalue of 0x02000203 to be written into this register.\n•\nA frame buffer having the format RGB888 (3 bytes per pixel) and a width of 320 pixels \n(total number of bytes per line is 320x3=960), where pitch = line length requires a value \nof 0x03C003C3 to be written into this register.\n16.7.24 \nLTDC Layerx ColorFrame Buffer Line Number Register\n(LTDC_LxCFBLNR) (where x=1..2)\nThis register defines the number of lines in the color frame buffer.\nAddress offset: 0xB4 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\nNote:\nThe number of lines and line length settings define how much data is fetched per frame for \nevery layer. If it is configured to less bytes than required, a FIFO underrun interrupt is \ngenerated if enabled.\nThe start address and pitch settings on the other hand define the correct start of every line in \nmemory.\nBits 31:29 Reserved, must be kept at reset valuer\nBits 28:16 CFBP[12:0]: Color Frame Buffer Pitch in bytes \nThese bits define the pitch which is the increment from the start of one line of pixels to the \nstart of the next line in bytes.\nBits 15:13 Reserved, must be kept at reset value\nBits 12:0 CFBLL[12:0]: Color Frame Buffer Line Length\nThese bits define the length of one line of pixels in bytes + 3.\nThe line length is computed as follows: Active high width x number of bytes per pixel + 3.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCFBLNBR[10:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:11 Reserved, must be kept at reset value\nBits 10:0 CFBLNBR[10:0]: Frame Buffer Line Number \nThese bits define the number of lines in the frame buffer which corresponds to the Active \nhigh width.\n" }, { "page_number": 514, "page_indices": { "start_index": 1047823, "end_index": 1048879 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 514 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.25 LTDC Layerx CLUT Write Register (LTDC_LxCLUTWR) (where x=1..2)", 514 ] ], "page_content": "LCD-TFT controller (LTDC)\nRM0090\n514/1757\nRM0090 Rev 21\n16.7.25 \nLTDC Layerx CLUT Write Register (LTDC_LxCLUTWR) \n(where x=1..2)\nThis register defines the CLUT address and the RGB value.\nAddress offset: 0xC4 + 0x80 x (Layerx -1), Layerx = 1 or 2\nReset value: 0x0000 0000\n \nNote:\nThe CLUT write register should only be configured during blanking period or if the layer is \ndisabled. The CLUT can be enabled or disabled in the LTDC_LxCR register.\nThe CLUT is only meaningful for L8, AL44 and AL88 pixel format.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCLUTADD[7:0]\nRED[7:0]\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nGREEN[7:0]\nBLUE[7:0]\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBits 31:24 CLUTADD[7:0]: CLUT Address\nThese bits configure the CLUT address (color position within the CLUT) of each RGB \nvalue\nBits 23:16 RED[7:0]: Red value\nThese bits configure the red value\nBits 15:8 GREEN[7:0]: Green value\nThese bits configure the green value\nBits 7:0 BLUE[7:0]: Blue value\nThese bits configure the blue value\n" }, { "page_number": 515, "page_indices": { "start_index": 1048879, "end_index": 1050703 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 515 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.26 LTDC register map", 515 ] ], "page_content": "RM0090 Rev 21\n515/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n16.7.26 \nLTDC register map\nThe following table summarizes the LTDC registers. Refer to the register boundary \naddresses table for the LTDC register base address.\n \nTable 93. LTDC register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x0008\nLTDC_SSCR\nReserved\nHSW[9:0]\nReserved\nVSH[10:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x000C\nLTDC_BPCR\nReserved\nAHBP[11:0]\nReserved\nAVBP[10:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0010\nLTDC_AWCR\nReserved\nAAV[11:0]\nReserved\nAAH[10:0]\nReset value\n0\n9\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0014\nLTDC_TWCR\nReserved\nTOTALW[11:0]\nReserved\nTOTALH[10:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0018\nLTDC_GCR\nHSPOL\nVSPOL\nDEPOL\nPCPOL\nReserve\nDEN\nReserved\nDRW[2:0]\nReserved\nDGW[2:0]\nReserved\nDBW[2:0]\nReserved\nLTDCEN\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n1\n0\n0\n1\n0\n0\n0x0024\nLTDC_SRCR\nReserved\nVBR\nIMR\nReset value\n0\n0\n0x002C\nLTDC_BCCR\nReserved\nBC[23:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0034\nLTDC_IER\nReserved\nRRIE\nTERRIE\nFUIE\nLIE\nReset value\n0\n0\n0\n0\n0x0038\nLTDC_ISR\nReserved\nRRIF\nTERRIF\nFUIF\nLIF\nReset value\n0\n0\n0\n0\n0x003C\nLTDC_ICR\nReserved\nCRRIF\nCTERRIF\nCFUIF\nCLIF\nReset value\n0\n0\n0\n0\n0x0040\nLTDC_LIPCR\nReserved\nLIPOS[10:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0044\nLTDC_CPSR\nCXPOS[15:0]\nCYPOS[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0048\nLTDC_CDSR\nReserved\nHSYNCS\nVSYNCS\nHDES\nVDES\nReset value\n1\n1\n1\n1\n0x0084\nLTDC_L1CR\nReserved\nCLUTEN\nReserved\nCOLKEN\nLEN\nReset value\n0\n0\n0\n0x0088\nLTDC_L1WHPCR\nReserved\nWHSPPOS[11:0]\nReserved\nWHSTPOS[11:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n" }, { "page_number": 516, "page_indices": { "start_index": 1050703, "end_index": 1053005 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 516 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.26 LTDC register map", 515 ] ], "page_content": "LCD-TFT controller (LTDC)\nRM0090\n516/1757\nRM0090 Rev 21\n0x008C\nLTDC_L1WVPCR\nReserved\nWVSPPOS[10:0]\nReserved\nWVSTPOS[10:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0090\nLTDC_L1CKCR\nReserved\nCKRED[7:0]\nCKGREEN[7:0]\nCKBLUE[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0094\nLTDC_L1PFCR\nReserved\nPF[2:0]\nReset value\n0\n0\n0\n0x0098\nLTDC_L1CACR\nReserved\nCONSTA[7:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n0x009C\nLTDC_L1DCCR\nDCALPHA[7:0]\nDCRED[7:0]\nDCGREEN[7:0]\nDCBLUE[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00A0\nLTDC_L1BFCR\nReserved\nBF1[2:0]\nReserved\nBF2[2:0]\nReset value\n1\n1\n0\n1\n1\n1\n0x00AC\nLTDC_L1CFBAR\nCFBADD[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00B0\nLTDC_L1CFBLR\nReserved\nCFBP[12:0]\nReserved\nCFBLL[12:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00B4\nLTDC_L1CFBLNR\nReserved\nCFBLNBR[10:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00C4\nLTDC_L1CLUTWR\nCLUTADD[7:0]\nRED[7:0]\nGREEN[7:0]\nBLUE[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0104\nLTDC_L2CR\nReserved\nCLUTEN\nReserved\nCOLKEN\nLEN\nReset value\n0\n0\n0\n0x0108\nLTDC_L2WHPCR\nReserved\nWHSPPOS[11:0]\nReserved\nWHSTPOS[11:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x010C\nLTDC_L2WVPCR\nReserved\nWVSPPOS[10:0]\nReserved\nWVSTPOS[10:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0110\nLTDC_L2CKCR\nReserved\nCKRED[7:0]\nCKGREEN[7:0]\nCKBLUE[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0114\nLTDC_L2PFCR\nReserved\nPF[2:0]\nReset value\n0\n0\n0\n0x0118\nLTDC_L2CACR\nReserved\nCONSTA[7:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n0x011C\nLTDC_L2DCCR\nDCALPHA[7:0]\nDCRED[7:0]\nDCGREEN[7:0]\nDCBLUE[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0120\nLTDC_L2BFCR\nReserved\nBF1[2:0]\nReserved\nBF2[2:0]\nReset value\n1\n1\n0\n1\n1\n1\n0x012C\nLTDC_L2CFBAR\nCFBADD[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0130\nLTDC_L2CFBLR\nReserved\nCFBP[12:0]\nReserved\nCFBLL[12:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 93. LTDC register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 517, "page_indices": { "start_index": 1053005, "end_index": 1053474 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 517 }, "toc_details": [ [ 1, "16 LCD-TFT controller (LTDC)", 483 ], [ 2, "16.7 LTDC registers", 496 ], [ 3, "16.7.26 LTDC register map", 515 ] ], "page_content": "RM0090 Rev 21\n517/1757\nRM0090\nLCD-TFT controller (LTDC)\n517\n \n0x0134\nLTDC_L2CFBLNR\nReserved\nCFBLNBR[10:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0144\nLTDC_L2CLUTWR\nCLUTADD[7:0]\nRED[7:0]\nGREEN[7:0]\nBLUE[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 93. LTDC register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 518, "page_indices": { "start_index": 1053474, "end_index": 1054425 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 518 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.1 TIM1 and TIM8 introduction", 518 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n518/1757\nRM0090 Rev 21\n17 \nAdvanced-control timers (TIM1 and TIM8)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n17.1 \nTIM1 and TIM8 introduction\nThe advanced-control timers (TIM1 and TIM8) consist of a 16-bit auto-reload counter driven \nby a programmable prescaler.\nIt may be used for a variety of purposes, including measuring the pulse lengths of input \nsignals (input capture) or generating output waveforms (output compare, PWM, \ncomplementary PWM with dead-time insertion).\nPulse lengths and waveform periods can be modulated from a few microseconds to several \nmilliseconds using the timer prescaler and the RCC clock controller prescalers.\nThe advanced-control (TIM1 and TIM8) and general-purpose (TIMx) timers are completely \nindependent, and do not share any resources. They can be synchronized together as \ndescribed in Section 17.3.20.\n" }, { "page_number": 519, "page_indices": { "start_index": 1054425, "end_index": 1055742 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 519 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.2 TIM1 and TIM8 main features", 519 ] ], "page_content": "RM0090 Rev 21\n519/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.2 \nTIM1 and TIM8 main features\nTIM1 and TIM8 timer features include:\n•\n16-bit up, down, up/down auto-reload counter.\n•\n16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock \nfrequency either by any factor between 1 and 65536.\n•\nUp to 4 independent channels for:\n–\nInput capture\n–\nOutput compare\n–\nPWM generation (Edge and Center-aligned mode)\n–\nOne-pulse mode output\n•\nComplementary outputs with programmable dead-time\n•\nSynchronization circuit to control the timer with external signals and to interconnect \nseveral timers together.\n•\nRepetition counter to update the timer registers only after a given number of cycles of \nthe counter.\n•\nBreak input to put the timer’s output signals in reset state or in a known state.\n•\nInterrupt/DMA generation on the following events:\n–\nUpdate: counter overflow/underflow, counter initialization (by software or \ninternal/external trigger)\n–\nTrigger event (counter start, stop, initialization or count by internal/external trigger)\n–\nInput capture\n–\nOutput compare\n–\nBreak input\n•\nSupports incremental (quadrature) encoder and hall-sensor circuitry for positioning \npurposes\n•\nTrigger input for external clock or cycle-by-cycle current management\n" }, { "page_number": 520, "page_indices": { "start_index": 1055742, "end_index": 1057148 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 520 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.2 TIM1 and TIM8 main features", 519 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n520/1757\nRM0090 Rev 21\nFigure 86. Advanced-control timer block diagram\nMS39906V3\nInterrupt & DMA output\nEvent\nPolarity selection\nInput filter & \nEdge detector\nInput filter & \nEdge detector\nInput filter & \nEdge detector\nInput filter & \nEdge detector\nTRC\nTRC\nTRC\nTRC\nTI4FP4\nTI4FP3\nTI3FP4\nTI3FP3\nPrescaler\nIC3\nIC4\nIC2\nIC1\nPrescaler\nPrescaler\nPrescaler\nTI2FP2\nTI2FP1\nTI1FP1\nTI1FP2\nTI1\nTI2\nTI3\nTI4\nBRK\nClock failure event from clock controller\nCSS (Clock Security System)\nIC1PS\nIC2PS\nIC3PS\nIC4PS\nBI\nCapture/Compare \n4 Register\nU\nCapture/Compare \n3 Register\nU\nU\nCapture/Compare \n2 Register\nCapture/Compare \n1 Register\nU\nCC1I\nCC2I\nCC3I\nCC4I\nCC1I\nCC2I\nCC3I\nCC4I\nOC1REF\nOC2REF\nOC3REF\nOC4REF\nDTG\nDTG\nDTG\nOC4\nOC3N\nOC3\nOC2N\nOC2\nOC1N\nOC1\nDTG[7:0] registers\nCNT\n(counter)\nPSC\n(prescaler)\nCK_CNT\nCK_PSC\nRepetition counter\nREP Register\nUI\nPolarity selection,\nEdge detector and Prescaler\nInput filter\nTrigger \ncontroller\nSlave mode \ncontroller\nEncoder \ninterface\nReset, \nEnable, \nUp/Down, \nCount\nTo other timers\nTo DAC and ADC\nTRGO\nTRGI\nTGI\nInternal clock (CK_INT)\nETRF\nETRP\nETR\nCK_TIM18 from RCC\nTI1FP1\nTI2FP2\nTIMx_ETR\nTIMx_CH1\nTIMx_CH2\nTIMx_CH3\nTIMx_CH4\nTIMx_BKIN\nTIMx_CH1\nTIMx_CH1N\nTIMx_CH3\nTIMx_CH3N\nTIMx_CH2\nTIMx_CH4\nTIMx_CH2N\nU\nU\nOutput \ncontrol\nAutoReload \nRegister\nU\nITR0\nITR1\nITR2\nITR3\nTIF_ED\nOutput \ncontrol\nOutput \ncontrol\nOutput \ncontrol\nTRC\n" }, { "page_number": 521, "page_indices": { "start_index": 1057148, "end_index": 1059251 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 521 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.1 Time-base unit", 521 ], [ 4, "Prescaler description", 521 ] ], "page_content": "RM0090 Rev 21\n521/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.3 \nTIM1 and TIM8 functional description\n17.3.1 \nTime-base unit\nThe main block of the programmable advanced-control timer is a 16-bit counter with its \nrelated auto-reload register. The counter can count up, down or both up and down. The \ncounter clock can be divided by a prescaler. \nThe counter, the auto-reload register and the prescaler register can be written or read by \nsoftware. This is true even when the counter is running.\nThe time-base unit includes:\n•\nCounter register (TIMx_CNT)\n•\nPrescaler register (TIMx_PSC)\n•\nAuto-reload register (TIMx_ARR)\n•\nRepetition counter register (TIMx_RCR)\nThe auto-reload register is preloaded. Writing to or reading from the auto-reload register \naccesses the preload register. The content of the preload register are transferred into the \nshadow register permanently or at each update event (UEV), depending on the auto-reload \npreload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter \nreaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the \nTIMx_CR1 register. It can also be generated by software. The generation of the update \nevent is described in detailed for each configuration.\nThe counter is clocked by the prescaler output CK_CNT, which is enabled only when the \ncounter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller \ndescription to get more details on counter enabling). \nNote that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 \nregister.\nPrescaler description\nThe prescaler can divide the counter clock frequency by any factor between 1 and 65536. It \nis based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). \nIt can be changed on the fly as this control register is buffered. The new prescaler ratio is \ntaken into account at the next update event.\nFigure 87 and Figure 88 give some examples of the counter behavior when the prescaler \nratio is changed on the fly:\n" }, { "page_number": 522, "page_indices": { "start_index": 1059251, "end_index": 1059953 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 522 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.1 Time-base unit", 521 ], [ 4, "Prescaler description", 521 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n522/1757\nRM0090 Rev 21\nFigure 87. Counter timing diagram with prescaler division change from 1 to 2\nFigure 88. Counter timing diagram with prescaler division change from 1 to 4\nCK_PSC\n00\nCEN\n \nTimerclock = CK_CNT\n \n \nCounter register\nUpdate event (UEV)\n0\nPrescaler control register\n1\n0\nWrite a new value in TIMx_PSC\nPrescaler buffer\n1\n0\nPrescaler counter\n0\n1\n0\n1\n0\n1\n0\n1\n01\n02\n03\nFA\nFB\nF7\nF8\nF9\nFC\nMS31076V2\n0\n3\n0\n0\n1\n2\n3\n0\n1\n2\n3\nMS31077V2\nCK_PSC\nCEN\n \nTimerclock = CK_CNT\n \n \nCounter register\nUpdate event (UEV)\nPrescaler control register\nWrite a new value in TIMx_PSC\nPrescaler buffer\nPrescaler counter\n00\n01\nFA\nFB\nF7\nF8\nF9\nFC\n3\n0\n" }, { "page_number": 523, "page_indices": { "start_index": 1059953, "end_index": 1062099 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 523 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.2 Counter modes", 523 ], [ 4, "Upcounting mode", 523 ] ], "page_content": "RM0090 Rev 21\n523/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.3.2 \nCounter modes\nUpcounting mode\nIn upcounting mode, the counter counts from 0 to the auto-reload value (content of the \nTIMx_ARR register), then restarts from 0 and generates a counter overflow event.\nIf the repetition counter is used, the update event (UEV) is generated after upcounting is \nrepeated for the number of times programmed in the repetition counter register plus one \n(TIMx_RCR+1). Else the update event is generated at each counter overflow.\nSetting the UG bit in the TIMx_EGR register (by software or by using the slave mode \ncontroller) also generates an update event.\nThe UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 \nregister. This is to avoid updating the shadow registers while writing new values in the \npreload registers. Then no update event occurs until the UDIS bit has been written to 0. \nHowever, the counter restarts from 0, as well as the counter of the prescaler (but the \nprescale rate does not change). In addition, if the URS bit (update request selection) in \nTIMx_CR1 register is set, setting the UG bit generates an update event UEV but without \nsetting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating \nboth update and capture interrupts when clearing the counter on the capture event.\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in \nTIMx_SR register) is set (depending on the URS bit):\n•\nThe repetition counter is reloaded with the content of TIMx_RCR register,\n•\nThe auto-reload shadow register is updated with the preload value (TIMx_ARR),\n•\nThe buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC \nregister).\nThe following figures show some examples of the counter behavior for different clock \nfrequencies when TIMx_ARR=0x36.\nFigure 89. Counter timing diagram, internal clock divided by 1\n00\n02\n03\n04\n05\n06\n07\n33\n34\n35\n36\n31\nMS31078V3\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n01\n32\n" }, { "page_number": 524, "page_indices": { "start_index": 1062099, "end_index": 1062812 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 524 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.2 Counter modes", 523 ], [ 4, "Upcounting mode", 523 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n524/1757\nRM0090 Rev 21\nFigure 90. Counter timing diagram, internal clock divided by 2\nFigure 91. Counter timing diagram, internal clock divided by 4\nFigure 92. Counter timing diagram, internal clock divided by N\nMS31079V3\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n0034\n0035\n0036\n0000\n0001\n0002\n0003\nMS31080V3\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n0000\n0001\n0035\n0036\nMS31081V3\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n1F\n20\n" }, { "page_number": 525, "page_indices": { "start_index": 1062812, "end_index": 1063569 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 525 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.2 Counter modes", 523 ], [ 4, "Upcounting mode", 523 ] ], "page_content": "RM0090 Rev 21\n525/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 93. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not \npreloaded)\nFigure 94. Counter timing diagram, update event when ARPE=1 (TIMx_ARR \npreloaded)\nFF\n36\nMS31082V3\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n02\n03\n04\n05\n06\n07\n32\n33\n34\n35\n36\n31\n01\nCEN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\nMS31083V2\nF5\n36\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag\n (UIF)\n00\n02\n03\n04\n05\n06\n07\nF1\nF2\nF3\nF4\nF5\nF0\n01\nCEN\nAuto-reload preload\nregister\nWrite a new value in TIMx_ARR\nAuto-reload shadow\nregister\nF5\n36\n" }, { "page_number": 526, "page_indices": { "start_index": 1063569, "end_index": 1065670 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 526 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.2 Counter modes", 523 ], [ 4, "Downcounting mode", 526 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n526/1757\nRM0090 Rev 21\nDowncounting mode\nIn downcounting mode, the counter counts from the auto-reload value (content of the \nTIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a \ncounter underflow event.\nIf the repetition counter is used, the update event (UEV) is generated after downcounting is \nrepeated for the number of times programmed in the repetition counter register plus one \n(TIMx_RCR+1). Else the update event is generated at each counter underflow.\nSetting the UG bit in the TIMx_EGR register (by software or by using the slave mode \ncontroller) also generates an update event.\nThe UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 \nregister. This is to avoid updating the shadow registers while writing new values in the \npreload registers. Then no update event occurs until UDIS bit has been written to 0. \nHowever, the counter restarts from the current auto-reload value, whereas the counter of the \nprescaler restarts from 0 (but the prescale rate doesn’t change). \nIn addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the \nUG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or \nDMA request is sent). This is to avoid generating both update and capture interrupts when \nclearing the counter on the capture event.\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in \nTIMx_SR register) is set (depending on the URS bit):\n•\nThe repetition counter is reloaded with the content of TIMx_RCR register\n•\nThe buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC \nregister)\n•\nThe auto-reload active register is updated with the preload value (content of the \nTIMx_ARR register). Note that the auto-reload is updated before the counter is \nreloaded, so that the next period is the expected one\nThe following figures show some examples of the counter behavior for different clock \nfrequencies when TIMx_ARR=0x36.\n" }, { "page_number": 527, "page_indices": { "start_index": 1065670, "end_index": 1066234 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 527 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.2 Counter modes", 523 ], [ 4, "Downcounting mode", 526 ] ], "page_content": "RM0090 Rev 21\n527/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 95. Counter timing diagram, internal clock divided by 1\nFigure 96. Counter timing diagram, internal clock divided by 2\n36\n34\n33\n32\n31\n30\n2F\n04\n03\n02\n01\n00\n05\nMS31184V1\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow \n(cnt_udf)\nUpdate interrupt flag\n (UIF)\n35\nMS31185V1\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow\nUpdate interrupt flag\n (UIF)\n0002\n0001\n0000\n0036\n0035\n0034\n0033\n" }, { "page_number": 528, "page_indices": { "start_index": 1066234, "end_index": 1066730 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 528 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.2 Counter modes", 523 ], [ 4, "Downcounting mode", 526 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n528/1757\nRM0090 Rev 21\nFigure 97. Counter timing diagram, internal clock divided by 4\nFigure 98. Counter timing diagram, internal clock divided by N\nMS40510V1\n0036\n0035\n0001\n0000\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow\nUpdate interrupt flag (UIF)\nCNT_EN\n00\n1F\n20\nMS31187V1\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow\nUpdate interrupt flag\n (UIF)\n36\n" }, { "page_number": 529, "page_indices": { "start_index": 1066730, "end_index": 1068980 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 529 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.2 Counter modes", 523 ], [ 4, "Center-aligned mode (up/down counting)", 529 ] ], "page_content": "RM0090 Rev 21\n529/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 99. Counter timing diagram, update event when repetition counter is not used\nCenter-aligned mode (up/down counting)\nIn center-aligned mode, the counter counts from 0 to the auto-reload value (content of the \nTIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-\nreload value down to 1 and generates a counter underflow event. Then it restarts counting \nfrom 0.\nCenter-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to \n'00'. The Output compare interrupt flag of channels configured in output is set when: the \ncounter counts down (Center aligned mode 1, CMS = \"01\"), the counter counts up (Center \naligned mode 2, CMS = \"10\") the counter counts up and down (Center aligned mode 3, \nCMS = \"11\").\nIn this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated \nby hardware and gives the current direction of the counter.\nThe update event can be generated at each counter overflow and at each counter underflow \nor by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode \ncontroller) also generates an update event. In this case, the counter restarts counting from \n0, as well as the counter of the prescaler.\nThe UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1 \nregister. This is to avoid updating the shadow registers while writing new values in the \npreload registers. Then no update event occurs until UDIS bit has been written to 0. \nHowever, the counter continues counting up and down, based on the current auto-reload \nvalue. \nIn addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the \nUG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or \nDMA request is sent). This is to avoid generating both update and capture interrupts when \nclearing the counter on the capture event.\nFF\n36\nMS31188V1\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow\nUpdate interrupt flag\n (UIF)\n00\n02\n03\n04\n05\n30\n2F\n32\n33\n34\n35\n36\n31\n01\nCEN\nAuto-reload preload\nregister\nWrite a new value in TIMx_ARR\n" }, { "page_number": 530, "page_indices": { "start_index": 1068980, "end_index": 1070395 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 530 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.2 Counter modes", 523 ], [ 4, "Center-aligned mode (up/down counting)", 529 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n530/1757\nRM0090 Rev 21\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in \nTIMx_SR register) is set (depending on the URS bit):\n•\nThe repetition counter is reloaded with the content of TIMx_RCR register\n•\nThe buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC \nregister)\n•\nThe auto-reload active register is updated with the preload value (content of the \nTIMx_ARR register). Note that if the update source is a counter overflow, the auto-\nreload is updated before the counter is reloaded, so that the next period is the expected \none (the counter is loaded with the new value).\nThe following figures show some examples of the counter behavior for different clock \nfrequencies.\nFigure 100. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6\n1.\nHere, center-aligned mode 1 is used (for more details refer to Section 17.4: TIM1 and TIM8 registers).\nFigure 101. Counter timing diagram, internal clock divided by 2\n \nMS31189V2\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\nCEN\nCounter underflow\n00\n02\n03\n04\n05\n06\n01\n02\n03\n04\n01\n05\n03\n04\nMS31190V2\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nCNT_EN\nCounter underflow\n0003\n0002\n0001\n0000\n0001\n0002\n0003\n" }, { "page_number": 531, "page_indices": { "start_index": 1070395, "end_index": 1070973 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 531 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.2 Counter modes", 523 ], [ 4, "Center-aligned mode (up/down counting)", 529 ] ], "page_content": "RM0090 Rev 21\n531/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 102. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36\n1.\nCenter-aligned mode 2 or 3 is used with an UIF on overflow.\nFigure 103. Counter timing diagram, internal clock divided by N\n0034\n0035\nMS31191V2\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\nCNT_EN\n0036\n0035\nMS31192V2\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nCounter underflow\n00\n1F\n20\n01\n" }, { "page_number": 532, "page_indices": { "start_index": 1070973, "end_index": 1072361 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 532 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.3 Repetition counter", 532 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n532/1757\nRM0090 Rev 21\nFigure 104. Counter timing diagram, update event with ARPE=1 (counter underflow)\nFigure 105. Counter timing diagram, Update event with ARPE=1 (counter overflow)\n17.3.3 \nRepetition counter\nSection 17.3.1: Time-base unit describes how the update event (UEV) is generated with \nrespect to the counter overflows/underflows. It is actually generated only when the repetition \ncounter has reached zero. This can be useful when generating PWM signals.\nThis means that data are transferred from the preload registers to the shadow registers \n(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx \ncapture/compare registers in compare mode) every N+1 counter overflows or underflows, \nwhere N is the value in the TIMx_RCR repetition counter register.\nMS31193V3\nCK_PSC\nTimer clock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\nCEN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\nAuto-reload active register\nFD\n36\n00\n02\n03\n04\n05\n06 07\n01\n06\n05\n04\n03\n02\n01\nFD\n36\nMS31194V2\nFD\n36\nCK_PSC\nTimer clock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n36\n34\n33\n32\n31\n30\n2F\nF8\nF9\nFA\nFB FC\nF7\n35\nCEN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\nAuto-reload active register\nFD\n36\n" }, { "page_number": 533, "page_indices": { "start_index": 1072361, "end_index": 1073900 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 533 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.3 Repetition counter", 532 ] ], "page_content": "RM0090 Rev 21\n533/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nThe repetition counter is decremented:\n•\nAt each counter overflow in upcounting mode,\n•\nAt each counter underflow in downcounting mode,\n•\nAt each counter overflow and at each counter underflow in center-aligned mode. \nAlthough this limits the maximum number of repetition to 128 PWM cycles, it makes it \npossible to update the duty cycle twice per PWM period. When refreshing compare \nregisters only once per PWM period in center-aligned mode, maximum resolution is \n2xTck, due to the symmetry of the pattern.\nThe repetition counter is an auto-reload type; the repetition rate is maintained as defined by \nthe TIMx_RCR register value (refer to Figure 106). When the update event is generated by \nsoftware (by setting the UG bit in TIMx_EGR register) or by hardware through the slave \nmode controller, it occurs immediately whatever the value of the repetition counter is and the \nrepetition counter is reloaded with the content of the TIMx_RCR register.\nIn center-aligned mode, for odd values of RCR, the update event occurs either on the \noverflow or on the underflow depending on when the RCR register was written and when \nthe counter was started. If the RCR was written before starting the counter, the UEV occurs \non the overflow. If the RCR was written after starting the counter, the UEV occurs on the \nunderflow. For example for RCR = 3, the UEV is generated on each 4th overflow or \nunderflow event depending on when RCR was written.\n" }, { "page_number": 534, "page_indices": { "start_index": 1073900, "end_index": 1074505 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 534 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.3 Repetition counter", 532 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n534/1757\nRM0090 Rev 21\nFigure 106. Update rate examples depending on mode and TIMx_RCR register \nsettings\nMSv31195V1\nUEV\nUEV\nUEV\nUEV\nUEV\nCounter-aligned mode\nEdge-aligned mode\nUpcounting\nDowncounting\n(by SW)\n(by SW)\n(by SW)\nTIMx_RCR = 3\nand\nre-synchronization\nTIMx_RCR = 3\nTIMx_RCR = 2\nTIMx_RCR = 1\nTIMx_RCR = 0\nCounter\nTIMx_CNT\nUEV\nUpdate event: Preload registers transferred to active registers and update interrupt generated\nUpdate Event if the repetition counter underflow occurs when the counter is equal to the auto-reload value.\n" }, { "page_number": 535, "page_indices": { "start_index": 1074505, "end_index": 1075907 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 535 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.4 Clock selection", 535 ], [ 4, "Internal clock source (CK_INT)", 535 ], [ 4, "External clock source mode 1", 535 ] ], "page_content": "RM0090 Rev 21\n535/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.3.4 \nClock selection\nThe counter clock can be provided by the following clock sources:\n•\nInternal clock (CK_INT)\n•\nExternal clock mode1: external input pin\n•\nExternal clock mode2: external trigger input ETR\n•\nInternal trigger inputs (ITRx): using one timer as prescaler for another timer, for \nexample, the user can configure Timer 1 to act as a prescaler for Timer 2. Refer to \nUsing one timer as prescaler for another timer for more details.\nInternal clock source (CK_INT)\nIf the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 \nregister) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed \nonly by software (except UG which remains cleared automatically). As soon as the CEN bit \nis written to 1, the prescaler is clocked by the internal clock CK_INT.\nFigure 107 shows the behavior of the control circuit and the upcounter in normal mode, \nwithout prescaler.\nFigure 107. Control circuit in normal mode, internal clock divided by 1\nExternal clock source mode 1\nThis mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at \neach rising or falling edge on a selected input.\nInternal clock\nCounter clock = CK_CNT = CK_PSC\nCounter register\nCEN=CNT_EN\nUG\nCNT_INIT\nMS31085V2\n00\n02\n03\n04\n05\n06\n07\n3 2\n33\n34\n35 36\n31\n01\n" }, { "page_number": 536, "page_indices": { "start_index": 1075907, "end_index": 1077417 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 536 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.4 Clock selection", 535 ], [ 4, "External clock source mode 1", 535 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n536/1757\nRM0090 Rev 21\nFigure 108. TI2 external clock connection example\nFor example, to configure the upcounter to count in response to a rising edge on the TI2 \ninput, use the following procedure:\n1.\nConfigure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in \nthe TIMx_CCMR1 register.\n2. \nConfigure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 \nregister (if no filter is needed, keep IC2F=0000).\n3. \nSelect rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER \nregister.\n4. \nConfigure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR \nregister. \n5. \nSelect TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register.\n6. \nEnable the counter by writing CEN=1 in the TIMx_CR1 register.\nNote:\nThe capture prescaler is not used for triggering, so the user does not need to configure it. \nWhen a rising edge occurs on TI2, the counter counts once and the TIF flag is set.\nThe delay between the rising edge on TI2 and the actual clock of the counter is due to the \nresynchronization circuit on TI2 input.\nExternal clock\nmode 1 \nInternal clock\nmode\nTRGI\nCK_INT\nCK_PSC\nTIMx_SMCR\nSMS[2:0]\nITRx\nTI1_ED\nTI1FP1\nTI2FP2\nTIMx_SMCR\nTS[2:0]\nTI2\n0\n1\nTIMx_CCER\nCC2P\nFilter\nICF[3:0]\nTIMx_CCMR1\nEdge\ndetector\nTI2F_Rising\nTI2F_Falling\n110\n0xx\n100\n101\nMS31196V1\n(internal clock)\nTI1F\nor\nTI2F\nor\nor\nEncoder\nmode \nETRF\n111\nExternal clock\nmode 2 \nETRF\nECE\n" }, { "page_number": 537, "page_indices": { "start_index": 1077417, "end_index": 1078247 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 537 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.4 Clock selection", 535 ], [ 4, "External clock source mode 2", 537 ] ], "page_content": "RM0090 Rev 21\n537/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 109. Control circuit in external clock mode 1\nExternal clock source mode 2 \nThis mode is selected by writing ECE=1 in the TIMx_SMCR register.\nThe counter can count at each rising or falling edge on the external trigger input ETR.\nFigure 110 gives an overview of the external trigger input block.\nFigure 110. External trigger input block\nCounter clock = CK_CNT = CK_PSC\nCounter register\n35\n36\n34\nTI2\nCNT_EN\nTIF\nWrite TIF=0\nMS31087V2\nExternal clock\nmode 1 \nInternal clock\nmode\nTRGI\nCK_INT\nCK_PSC\nTIMx_SMCR\nSMS[2:0]\nMS33116V1\n(internal clock)\nTI1F\nor\nTI2F\nor\nor\nEncoder\nmode \nExternal clock\nmode 2 \nETRF\nECE\n0\n1\nTIMx_SMCR\nETP\nETR pin\nETR\nDivider\n/1, /2, /4, /8\nFilter\ndowncounter\nf\nETRP\nTIMx_SMCR\nETPS[1:0]\nTIMx_SMCR\nETF[3:0]\nDTS\n" }, { "page_number": 538, "page_indices": { "start_index": 1078247, "end_index": 1079837 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 538 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.5 Capture/compare channels", 538 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n538/1757\nRM0090 Rev 21\nFor example, to configure the upcounter to count each 2 rising edges on ETR, use the \nfollowing procedure:\n1.\nAs no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.\n2. \nSet the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register \n3. \nSelect rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR \nregister\n4. \nEnable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.\n5. \nEnable the counter by writing CEN=1 in the TIMx_CR1 register.\nThe counter counts once each 2 ETR rising edges.\nThe delay between the rising edge on ETR and the actual clock of the counter is due to the \nresynchronization circuit on the ETRP signal.\nFigure 111. Control circuit in external clock mode 2\n17.3.5 \nCapture/compare channels\nEach Capture/Compare channel is built around a capture/compare register (including a \nshadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and \nan output stage (with comparator and output control).\nFigure 112 to Figure 115 give an overview of one Capture/Compare channel.\nThe input stage samples the corresponding TIx input to generate a filtered signal TIxF. \nThen, an edge detector with polarity selection generates a signal (TIxFPx) which can be \nused as trigger input by the slave mode controller or as the capture command. It is \nprescaled before the capture register (ICxPS).\nMS33111V2\n34\n35\n36\nfCK_INT\nCNT_EN\nETR\nETRP\nETRF\nCounter clock = \nCK_INT =CK_PSC\nCounter register\n" }, { "page_number": 539, "page_indices": { "start_index": 1079837, "end_index": 1081000 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 539 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.5 Capture/compare channels", 538 ] ], "page_content": "RM0090 Rev 21\n539/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 112. Capture/compare channel (example: channel 1 input stage)\nThe output stage generates an intermediate waveform that is then used for reference: \nOCxRef (active high). The polarity acts at the end of the chain.\nFigure 113. Capture/compare channel 1 main circuit\n0\n1\nDivider\n/1, /2, /4, /8\nICPS[1:0]\nTI1F_ED\nTo the slave mode controller\nTI1FP1\n11\n01\nCC1S[1:0]\nIC1\nTI2FP1\nTRC\n(from slave mode\ncontroller)\n10\nIC1PS\n0\n1\nMS33115V1\nTI1\nTIMx_CCER\nCC1P/CC1NP\nFilter\ndowncounter\nICF[3:0]\nTIMx_CCMR1\nEdge\ndetector\nTI1F_Rising\nTI1F_Falling\nTIMx_CCMR1\nTIMx_CCER\nTI2F_Rising\n(from channel 2)\nTI2F_Falling\n(from channel 2)\nTI1F\nf\nCC1E\nDTS\nMS31089V3\nCC1E\nCapture/compare shadow register\nComparator\nCapture/compare preload register\nCounter\nIC1PS\nCC1S[0]\nCC1S[1]\nCapture\nInput \nmode\nS\nR\nRead CCR1H\nRead CCR1L\nread_in_progress\ncapture_transfer\nCC1S[0]\nCC1S[1]\nS\nR\nwrite CCR1H\nwrite CCR1L\nwrite_in_progress\nOutput \nmode\nUEV\nOC1PE\n(from time \nbase unit)\ncompare_transfer\nAPB Bus\n8\n8\nhigh\nlow\n(if 16-bit)\nMCU-peripheral interface\nTIMx_CCMR1\nOC1PE\nCNT>CCR1\nCNT=CCR1\nTIMx_EGR\nCC1G\n" }, { "page_number": 540, "page_indices": { "start_index": 1081000, "end_index": 1082208 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 540 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.5 Capture/compare channels", 538 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n540/1757\nRM0090 Rev 21\nFigure 114. Output stage of capture/compare channel (channel 1 to 3)\nFigure 115. Output stage of capture/compare channel (channel 4)\nThe capture/compare block is made of one preload register and one shadow register. Write \nand read always access the preload register. \nIn capture mode, captures are actually done in the shadow register, which is copied into the \npreload register. \nIn compare mode, the content of the preload register is copied into the shadow register \nwhich is compared to the counter.\nMS35909V1\nOutput\nmode\ncontroller\nCNT>CCR1\nCNT=CCR1\nTIM1_CCMR1\nOC1M[3:0]\nOC1REF\nOC1CE\nDead-time\ngenerator\nOC1_DT\nOC1N_DT\nDTG[7:0]\nTIM1_BDTR\n‘0’\n‘0’\nCC1E\nTIM1_CCER\nCC1NE\n0\n1\nCC1P\nTIM1_CCER\n0\n1\nCC1NP\nTIM1_CCER\nOC1\nOutput\nenable\ncircuit\nOC1N\nCC1E TIM1_CCER\nCC1NE\nOSSI\nTIM1_BDTR\nMOE\nOSSR\n0x\n10\n11\n11\n01\nx0\nOutput\nselector\nOCxREF\nOC1REFC\nTo the master mode\ncontroller\nOutput\nenable\ncircuit\nOC5REF\n(1)\nETRF\nMS37370V1\nOutput \nmode \ncontroller\nTIM1_CCMR2\nOC1M[3:0]\nOC4REF\n0\n1\nCC4P\nTIM1_CCER\nOC4\nTo the master \nmode controller\nOutput \nenable \ncircuit\nETR\nCNT>CCR4\nCNT>CCR4\nTIM1_CCER\nTIM1_BDTR\nTIM1_CR2\nOSSI\nMOE\nCC4E\nOIS4\n" }, { "page_number": 541, "page_indices": { "start_index": 1082208, "end_index": 1085214 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 541 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.6 Input capture mode", 541 ] ], "page_content": "RM0090 Rev 21\n541/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.3.6 \nInput capture mode\nIn Input capture mode, the Capture/Compare registers (TIMx_CCRx) are used to latch the \nvalue of the counter after a transition detected by the corresponding ICx signal. When a \ncapture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or \na DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was \nalready high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be \ncleared by software by writing it to ‘0’ or by reading the captured data stored in the \nTIMx_CCRx register. CCxOF is cleared when written to ‘0’.\nThe following example shows how to capture the counter value in TIMx_CCR1 when TI1 \ninput rises. To do this, use the following procedure:\n•\nSelect the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S \nbits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, \nthe channel is configured in input and the TIMx_CCR1 register becomes read-only.\n•\nProgram the needed input filter duration with respect to the signal connected to the \ntimer (by programming ICxF bits in the TIMx_CCMRx register if the input is a TIx input). \nLet’s imagine that, when toggling, the input signal is not stable during at must five \ninternal clock cycles. We must program a filter duration longer than these five clock \ncycles. We can validate a transition on TI1 when 8 consecutive samples with the new \nlevel have been detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in \nthe TIMx_CCMR1 register.\n•\nSelect the edge of the active transition on the TI1 channel by writing CC1P and CC1NP \nbits to 0 in the TIMx_CCER register (rising edge in this case).\n•\nProgram the input prescaler. In our example, we wish the capture to be performed at \neach valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the \nTIMx_CCMR1 register).\n•\nEnable capture from the counter into the capture register by setting the CC1E bit in the \nTIMx_CCER register.\n•\nIf needed, enable the related interrupt request by setting the CC1IE bit in the \nTIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the \nTIMx_DIER register.\nWhen an input capture occurs:\n•\nThe TIMx_CCR1 register gets the value of the counter on the active transition.\n•\nCC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures \noccurred whereas the flag was not cleared.\n•\nAn interrupt is generated depending on the CC1IE bit.\n•\nA DMA request is generated depending on the CC1DE bit.\nIn order to handle the overcapture, it is recommended to read the data before the \novercapture flag. This is to avoid missing an overcapture which could happen after reading \nthe flag and before reading the data.\nNote:\nIC interrupt and/or DMA requests can be generated by software by setting the \ncorresponding CCxG bit in the TIMx_EGR register.\n" }, { "page_number": 542, "page_indices": { "start_index": 1085214, "end_index": 1087207 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 542 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.7 PWM input mode", 542 ], [ 3, "17.3.8 Forced output mode", 542 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n542/1757\nRM0090 Rev 21\n17.3.7 \nPWM input mode\nThis mode is a particular case of input capture mode. The procedure is the same except:\n•\nTwo ICx signals are mapped on the same TIx input.\n•\nThese 2 ICx signals are active on edges with opposite polarity.\n•\nOne of the two TIxFP signals is selected as trigger input and the slave mode controller \nis configured in reset mode.\nFor example, user can measure the period (in TIMx_CCR1 register) and the duty cycle (in \nTIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending \non CK_INT frequency and prescaler value):\n•\nSelect the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 \nregister (TI1 selected).\n•\nSelect the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter \nclear): write the CC1P and CC1NP bits to ‘0’ (active on rising edge).\n•\nSelect the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 \nregister (TI1 selected).\n•\nSelect the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P \nbit to '1' and the CC2NP bit to '0' (active on falling edge).\n•\nSelect the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register \n(TI1FP1 selected).\n•\nConfigure the slave mode controller in reset mode: write the SMS bits to 100 in the \nTIMx_SMCR register.\n•\nEnable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.\nFigure 116. PWM input mode timing\n17.3.8 \nForced output mode\nIn output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal \n(OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, \nindependently of any comparison between the output compare register and the counter.\nTo force an output compare signal (OCXREF/OCx) to its active level, the user just needs to \nwrite 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is \n" }, { "page_number": 543, "page_indices": { "start_index": 1087207, "end_index": 1089871 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 543 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.9 Output compare mode", 543 ] ], "page_content": "RM0090 Rev 21\n543/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nforced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity \nbit.\nFor example: CCxP=0 (OCx active high) => OCx is forced to high level.\nThe OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx \nregister.\nAnyway, the comparison between the TIMx_CCRx shadow register and the counter is still \nperformed and allows the flag to be set. Interrupt and DMA requests can be sent \naccordingly. This is described in the output compare mode section below.\n17.3.9 \nOutput compare mode\nThis function is used to control an output waveform or indicating when a period of time has \nelapsed.\nWhen a match is found between the capture/compare register and the counter, the output \ncompare function: \n•\nAssigns the corresponding output pin to a programmable value defined by the output \ncompare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP \nbit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set \nactive (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.\n•\nSets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).\n•\nGenerates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the \nTIMx_DIER register).\n•\nSends a DMA request if the corresponding enable bit is set (CCxDE bit in the \nTIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request \nselection).\nThe TIMx_CCRx registers can be programmed with or without preload registers using the \nOCxPE bit in the TIMx_CCMRx register.\nIn output compare mode, the update event UEV has no effect on OCxREF and OCx output. \nThe timing resolution is one count of the counter. Output compare mode can also be used to \noutput a single pulse (in One Pulse mode).\nProcedure:\n1.\nSelect the counter clock (internal, external, prescaler).\n2. \nWrite the desired data in the TIMx_ARR and TIMx_CCRx registers.\n3. \nSet the CCxIE bit if an interrupt request is to be generated.\n4. \nSelect the output mode. For example:\n–\nWrite OCxM = 011 to toggle OCx output pin when CNT matches CCRx\n–\nWrite OCxPE = 0 to disable preload register\n–\nWrite CCxP = 0 to select active high polarity\n–\nWrite CCxE = 1 to enable the output\n5. \nEnable the counter by setting the CEN bit in the TIMx_CR1 register.\nThe TIMx_CCRx register can be updated at any time by software to control the output \nwaveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx \nshadow register is updated only at the next update event UEV). An example is given in \nFigure 117.\n" }, { "page_number": 544, "page_indices": { "start_index": 1089871, "end_index": 1091958 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 544 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.10 PWM mode", 544 ], [ 4, "PWM edge-aligned mode", 544 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n544/1757\nRM0090 Rev 21\nFigure 117. Output compare mode, toggle on OC1.\n17.3.10 \nPWM mode\nPulse Width Modulation mode allows generating a signal with a frequency determined by \nthe value of the TIMx_ARR register and a duty cycle determined by the value of the \nTIMx_CCRx register.\nThe PWM mode can be selected independently on each channel (one PWM per OCx \noutput) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the \nTIMx_CCMRx register. The corresponding preload register must be enabled by setting the \nOCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in \nupcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.\nAs the preload registers are transferred to the shadow registers only when an update event \noccurs, before starting the counter, the user must initialize all the registers by setting the UG \nbit in the TIMx_EGR register.\nOCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It \ncan be programmed as active high or active low. OCx output is enabled by a combination of \nthe CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers). \nRefer to the TIMx_CCER register description for more details.\nIn PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine \nwhether TIMx_CCRx ≤TIMx_CNT or TIMx_CNT ≤TIMx_CCRx (depending on the direction \nof the counter). \nThe timer is able to generate PWM in edge-aligned mode or center-aligned mode \ndepending on the CMS bits in the TIMx_CR1 register.\nPWM edge-aligned mode\n•\nUpcounting configuration\nUpcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to \nUpcounting mode.\nIn the following example, we consider PWM mode 1. The reference PWM signal \nOCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the \nMS31092V2\nOC1REF= OC1\nTIM1_CNT\nB200\nB201\n0039\nTIM1_CCR1\n003A\nWrite B201h in the CC1R register\nMatch detected on CCR1\nInterrupt generated if enabled\n003B\nB201\n003A\n" }, { "page_number": 545, "page_indices": { "start_index": 1091958, "end_index": 1093248 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 545 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.10 PWM mode", 544 ], [ 4, "PWM center-aligned mode", 545 ] ], "page_content": "RM0090 Rev 21\n545/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\ncompare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) \nthen OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. \nFigure 118 shows some edge-aligned PWM waveforms in an example where \nTIMx_ARR=8.\nFigure 118. Edge-aligned PWM waveforms (ARR=8)\n•\nDowncounting configuration\nDowncounting is active when DIR bit in TIMx_CR1 register is high. Refer to \nDowncounting mode\nIn PWM mode 1, the reference signal OCxRef is low as long as \nTIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is \ngreater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM \nis not possible in this mode.\nPWM center-aligned mode\nCenter-aligned mode is active when the CMS bits in TIMx_CR1 register are different from \n‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals). \nThe compare flag is set when the counter counts up, when it counts down or both when it \ncounts up and down depending on the CMS bits configuration. The direction bit (DIR) in the \nMS31093V1\nCounter register\n‘1’\n0\n1\n2\n3\n4\n5\n6\n7\n8\n0\n1\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nCCRx=4\nCCRx=8\nCCRx>8\nCCRx=0\n‘0’\n" }, { "page_number": 546, "page_indices": { "start_index": 1093248, "end_index": 1094258 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 546 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.10 PWM mode", 544 ], [ 4, "PWM center-aligned mode", 545 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n546/1757\nRM0090 Rev 21\nTIMx_CR1 register is updated by hardware and must not be changed by software. Refer to \nCenter-aligned mode (up/down counting).\nFigure 119 shows some center-aligned PWM waveforms in an example where:\n•\nTIMx_ARR=8,\n•\nPWM mode is the PWM mode 1,\n•\nThe flag is set when the counter counts down corresponding to the center-aligned \nmode 1 selected for CMS=01 in TIMx_CR1 register.\nFigure 119. Center-aligned PWM waveforms (ARR=8)\nHints on using center-aligned mode:\n•\nWhen starting in center-aligned mode, the current up-down configuration is used. It \nmeans that the counter counts up or down depending on the value written in the DIR bit \nCCxIF\n0\n1\n2\n3\n4\n5\n6\n7\n8\n7\n6\n5\n4\n3\n2\n1\n0\n1\nCounter register\nCCRx = 4\nOCxREF\nCMS=01\nCMS=10\nCMS=11\nCCxIF\nCCRx = 7\nOCxREF\nCMS=10 or 11\nCCxIF\nCCRx = 8\nOCxREF\nCMS=01\nCMS=10\nCMS=11\n'1'\nCCxIF\nCCRx > 8\nOCxREF\nCMS=01\nCMS=10\nCMS=11\n'1'\nCCxIF\nCCRx = 0\nOCxREF\nCMS=01\nCMS=10\nCMS=11\n'0'\nai14681b\n" }, { "page_number": 547, "page_indices": { "start_index": 1094258, "end_index": 1097093 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 547 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.11 Complementary outputs and dead-time insertion", 547 ] ], "page_content": "RM0090 Rev 21\n547/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nin the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the \nsame time by the software.\n•\nWriting to the counter while running in center-aligned mode is not recommended as it \ncan lead to unexpected results. In particular:\n–\nThe direction is not updated if the user writes a value in the counter greater than \nthe auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was \ncounting up, it continues to count up.\n–\nThe direction is updated if the user writes 0 or write the TIMx_ARR value in the \ncounter but no Update Event UEV is generated.\n•\nThe safest way to use center-aligned mode is to generate an update by software \n(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to \nwrite the counter while it is running.\n17.3.11 \nComplementary outputs and dead-time insertion\nThe advanced-control timers (TIM1 and TIM8) can output two complementary signals and \nmanage the switching-off and the switching-on instants of the outputs.\nThis time is generally known as dead-time and it has to be adjust it depending on the \ndevices connected to the outputs and their characteristics (intrinsic delays of level-shifters, \ndelays due to power switches...)\nUser can select the polarity of the outputs (main output OCx or complementary OCxN) \nindependently for each output. This is done by writing to the CCxP and CCxNP bits in the \nTIMx_CCER register.\nThe complementary signals OCx and OCxN are activated by a combination of several \ncontrol bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx, \nOISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to Table 96 \nfor more details. In particular, the dead-time is activated when switching to the IDLE state \n(MOE falling down to 0).\nDead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the \nbreak circuit is present. DTG[7:0] bits of the TIMx_BDTR register are used to control the \ndead-time generation for all channels. From a reference waveform OCxREF, it generates 2 \noutputs OCx and OCxN. If OCx and OCxN are active high:\n•\nThe OCx output signal is the same as the reference signal except for the rising edge, \nwhich is delayed relative to the reference rising edge.\n•\nThe OCxN output signal is the opposite of the reference signal except for the rising \nedge, which is delayed relative to the reference falling edge.\nIf the delay is greater than the width of the active output (OCx or OCxN) then the \ncorresponding pulse is not generated.\nThe following figures show the relationships between the output signals of the dead-time \ngenerator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1, \nCCxE=1 and CCxNE=1 in these examples)\n" }, { "page_number": 548, "page_indices": { "start_index": 1097093, "end_index": 1098123 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 548 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.11 Complementary outputs and dead-time insertion", 547 ], [ 4, "Re-directing OCxREF to OCx or OCxN", 548 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n548/1757\nRM0090 Rev 21\nFigure 120. Complementary output with dead-time insertion.\nFigure 121. Dead-time waveforms with delay greater than the negative pulse.\nFigure 122. Dead-time waveforms with delay greater than the positive pulse.\nThe dead-time delay is the same for each of the channels and is programmable with the \nDTG bits in the TIMx_BDTR register. Refer to Section 17.4.18: TIM1 and TIM8 break and \ndead-time register (TIMx_BDTR) for delay calculation.\nRe-directing OCxREF to OCx or OCxN\nIn output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx \noutput or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER \nregister.\nThis allows the user to send a specific waveform (such as PWM or static active level) on \none output while the complementary remains at its inactive level. Other possibilities are to \ndelay\ndelay\nOCxREF\nOCx\nOCxN\nMS31095V1\nMS31096V1\ndelay\nOCxREF\nOCx\nOCxN\nMS31097V1\ndelay\nOCxREF\nOCx\nOCxN\n" }, { "page_number": 549, "page_indices": { "start_index": 1098123, "end_index": 1101284 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 549 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.12 Using the break function", 549 ] ], "page_content": "RM0090 Rev 21\n549/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nhave both outputs at inactive level or both outputs active and complementary with \ndead-time.\nNote:\nWhen only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes \nactive as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the \nother hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes \nactive when OCxREF is high whereas OCxN is complemented and becomes active when \nOCxREF is low.\n17.3.12 \nUsing the break function\nWhen using the break function, the output enable signals and inactive levels are modified \naccording to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register, \nOISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs \ncannot be set both to active level at a given time. Refer to Table 96 for more details.\nThe break source can be either the break input pin or a clock failure event, generated by the \nClock Security System (CSS), from the Reset Clock Controller. For further information on \nthe Clock Security System, refer to Section 7.2.7: Clock security system (CSS).\nWhen exiting from reset, the break circuit is disabled and the MOE bit is low. User can \nenable the break function by setting the BKE bit in the TIMx_BDTR register. The break input \npolarity can be selected by configuring the BKP bit in the same register. BKE and BKP can \nbe modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB \nclock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1 \nAPB clock period to correctly read back the bit after the write operation.\nBecause MOE falling edge can be asynchronous, a resynchronization circuit has been \ninserted between the actual signal (acting on the outputs) and the synchronous control bit \n(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous \nand the synchronous signals. In particular, if MOE is written to 1 whereas it was low, a delay \n(dummy instruction) must be inserted before reading it correctly. This is because the user \nwrites an asynchronous signal, but reads a synchronous signal.\nWhen a break occurs (selected level on the break input):\n•\nThe MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state \nor in reset state (selected by the OSSI bit). This feature functions even if the MCU \noscillator is off.\n•\nEach output channel is driven with the level programmed in the OISx bit in the \nTIMx_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable \noutput else the enable output remains high.\n•\nWhen complementary outputs are used: \n–\nThe outputs are first put in reset state inactive state (depending on the polarity). \nThis is done asynchronously so that it works even if no clock is provided to the \ntimer. \n–\nIf the timer clock is still present, then the dead-time generator is reactivated in \norder to drive the outputs with the level programmed in the OISx and OISxN bits \nafter a dead-time. Even in this case, OCx and OCxN cannot be driven to their \n" }, { "page_number": 550, "page_indices": { "start_index": 1101284, "end_index": 1103419 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 550 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.12 Using the break function", 549 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n550/1757\nRM0090 Rev 21\nactive level together. Note that because of the resynchronization on MOE, the \ndead-time duration is a bit longer than usual (around 2 ck_tim clock cycles).\n–\nIf OSSI=0 then the timer releases the enable outputs else the enable outputs \nremain or become high as soon as one of the CCxE or CCxNE bits is high.\n•\nThe break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be \ngenerated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if \nthe BDE bit in the TIMx_DIER register is set.\n•\nIf the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again \nat the next update event UEV. This can be used to perform a regulation, for instance. \nElse, MOE remains low until it is written to ‘1’ again. In this case, it can be used for \nsecurity and the break input can be connected to an alarm from power drivers, thermal \nsensors or any security components.\nNote:\nThe break inputs is acting on level. Thus, the MOE cannot be set while the break input is \nactive (neither automatically nor by software). In the meantime, the status flag BIF cannot \nbe cleared.\nThe break can be generated by the BRK input which has a programmable polarity and an \nenable bit BKE in the TIMx_BDTR register.\nThere are two solutions to generate a break:\n•\nBy using the BRK input which has a programmable polarity and an enable bit BKE in \nthe TIMx_BDTR register\n•\nBy software through the BG bit of the TIMx_EGR register.\nIn addition to the break input and the output management, a write protection has been \nimplemented inside the break circuit to safeguard the application. It allows freezing the \nconfiguration of several parameters (dead-time duration, OCx/OCxN polarities and state \nwhen disabled, OCxM configurations, break enable and polarity). The user can choose from \nthree levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to \nSection 17.4.18: TIM1 and TIM8 break and dead-time register (TIMx_BDTR). The LOCK \nbits can be written only once after an MCU reset.\n" }, { "page_number": 551, "page_indices": { "start_index": 1103419, "end_index": 1104219 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 551 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.12 Using the break function", 549 ] ], "page_content": "RM0090 Rev 21\n551/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 123 shows an example of behavior of the outputs in response to a break.\nFigure 123. Output behavior in response to a break.\ndelay\ndelay\ndelay\ndelay\ndelay\ndelay\ndelay\ndelay\nOCxREF\nOCx\n(OCxN not implemented, CCxP=0, OISx=1)\nOCx\n(OCxN not implemented, CCxP=0, OISx=0)\nOCx\n(OCxN not implemented, CCxP=1, OISx=1)\nOCx\n(OCxN not implemented, CCxP=1, OISx=0)\nOCx\nOCxN\n(CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1)\nOCx\nOCxN\n(CCxE=1, CCxP=0, OISx=1, CCxNE=1, CCxNP=1, OISxN=1)\nOCx\nOCxN\n(CCxE=1, CCxP=0, OISx=0, CCxNE=0, CCxNP=0, OISxN=1)\nOCx\nOCxN\n(CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0)\nOCx\nOCxN\n(CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1)\nMS31098V1\nBREAK (MOE ) \n" }, { "page_number": 552, "page_indices": { "start_index": 1104219, "end_index": 1105658 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 552 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.13 Clearing the OCxREF signal on an external event", 552 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n552/1757\nRM0090 Rev 21\n17.3.13 \nClearing the OCxREF signal on an external event\nThe OCxREF signal for a given channel can be driven Low by applying a High level to the \nETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The \nOCxREF signal remains Low until the next update event, UEV, occurs. \nThis function can only be used in output compare and PWM modes, and does not work in \nforced mode.\nFor example, the ETR signal can be connected to the output of a comparator to be used for \ncurrent handling. In this case, the ETR must be configured as follow:\n1.\nThe External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR \nregister set to ‘00’.\n2. \nThe external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to \n‘0’.\n3. \nThe External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be \nconfigured according to the user needs.\nFigure 124 shows the behavior of the OCxREF signal when the ETRF Input becomes High, \nfor both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in \nPWM mode.\nFigure 124. Clearing TIMx OCxREF\nNote:\nIn case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at \nthe next counter overflow.\nMSv35889V1\n(CCRx)\nCounter (CNT)\nETRF\nOCxREF (OCxCE = ‘0’)\nOCxREF (OCxCE = ‘1’)\nETRF becomes high\nETRF still high\n" }, { "page_number": 553, "page_indices": { "start_index": 1105658, "end_index": 1106669 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 553 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.14 6-step PWM generation", 553 ] ], "page_content": "RM0090 Rev 21\n553/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.3.14 \n6-step PWM generation\nWhen complementary outputs are used on a channel, preload bits are available on the \nOCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the \nCOM commutation event. The user can thus program in advance the configuration for the \nnext step and change the configuration of all the channels at the same time. COM can be \ngenerated by software by setting the COM bit in the TIMx_EGR register or by hardware (on \nTRGI rising edge).\nA flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can \ngenerate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request \n(if the COMDE bit is set in the TIMx_DIER register).\nFigure 125 describes the behavior of the OCx and OCxN outputs when a COM event \noccurs, in 3 different examples of programmed configurations.\nFigure 125. 6-step generation, COM example (OSSR=1)\n" }, { "page_number": 554, "page_indices": { "start_index": 1106669, "end_index": 1108272 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 554 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.15 One-pulse mode", 554 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n554/1757\nRM0090 Rev 21\n17.3.15 \nOne-pulse mode\nOne-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to \nbe started in response to a stimulus and to generate a pulse with a programmable length \nafter a programmable delay.\nStarting the counter can be controlled through the slave mode controller. Generating the \nwaveform can be done in output compare mode or PWM mode. Select One-pulse mode by \nsetting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at \nthe next update event UEV.\nA pulse can be correctly generated only if the compare value is different from the counter \ninitial value. Before starting (when the timer is waiting for the trigger), the configuration must \nbe:\n•\nIn upcounting: CNT < CCRx ≤ARR (in particular, 0 < CCRx)\n•\nIn downcounting: CNT > CCRx\nFigure 126. Example of one pulse mode.\nFor example the user may want to generate a positive pulse on OC1 with a length of tPULSE \nand after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.\nLet’s use TI2FP2 as trigger 1:\n•\nMap TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.\n•\nTI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER \nregister.\n•\nConfigure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in \nthe TIMx_SMCR register.\n•\nTI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register \n(trigger mode).\nMS31099V2\nTI2\nOC1REF\nCounter\nt\n0\nTIM1_ARR\nTIM1_CCR1\nOC1\ntDELAY\ntPULSE\n" }, { "page_number": 555, "page_indices": { "start_index": 1108272, "end_index": 1111846 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 555 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.16 Encoder interface mode", 555 ] ], "page_content": "RM0090 Rev 21\n555/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nThe OPM waveform is defined by writing the compare registers (taking into account the \nclock frequency and the counter prescaler).\n•\nThe tDELAY is defined by the value written in the TIMx_CCR1 register.\n•\nThe tPULSE is defined by the difference between the auto-reload value and the compare \nvalue (TIMx_ARR - TIMx_CCR1).\n•\nLet us say the user wants to build a waveform with a transition from ‘0’ to ‘1’ when a \ncompare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the \nauto-reload value. To do this, enable PWM mode 2 by writing OC1M=111 in the \nTIMx_CCMR1 register. The user can optionally enable the preload registers by writing \nOC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this \ncase the compare value must be written in the TIMx_CCR1 register, the auto-reload \nvalue in the TIMx_ARR register, generate an update by setting the UG bit and wait for \nexternal trigger event on TI2. CC1P is written to ‘0’ in this example.\nIn our example, the DIR and CMS bits in the TIMx_CR1 register should be low.\nThe user only wants one pulse (Single mode), so '1’ must be written in the OPM bit in the \nTIMx_CR1 register to stop the counter at the next update event (when the counter rolls over \nfrom the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', \nso the Repetitive mode is selected.\nParticular case: OCx fast enable:\nIn One-pulse mode, the edge detection on TIx input set the CEN bit which enables the \ncounter. Then the comparison between the counter and the compare value makes the \noutput toggle. But several clock cycles are needed for these operations and it limits the \nminimum delay tDELAY min we can get.\nIf the user wants to output a waveform with the minimum delay, the OCxFE bit in the \nTIMx_CCMRx register must be set. Then OCxRef (and OCx) are forced in response to the \nstimulus, without taking in account the comparison. Its new level is the same as if a compare \nmatch had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 \nmode.\n17.3.16 \nEncoder interface mode\nTo select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the \ncounter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and \nSMS=’011’ if it is counting on both TI1 and TI2 edges.\nSelect the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER \nregister. When needed, the user can program the input filter as well. CC1NP and CC2NP \nmust be kept low.\nThe two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to \nTable 94. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 \nafter input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted, \nTI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in \nTIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated \nand generates count pulses as well as the direction signal. Depending on the sequence the \ncounter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware \naccordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever \nthe counter is counting on TI1 only, TI2 only or both TI1 and TI2.\nEncoder interface mode acts simply as an external clock with direction selection. This \nmeans that the counter just counts continuously between 0 and the auto-reload value in the \n" }, { "page_number": 556, "page_indices": { "start_index": 1111846, "end_index": 1114260 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 556 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.16 Encoder interface mode", 555 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n556/1757\nRM0090 Rev 21\nTIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So user must \nconfigure TIMx_ARR before starting. in the same way, the capture, compare, prescaler, \nrepetition counter, trigger output features continue to work as normal. Encoder mode and \nExternal clock mode 2 are not compatible and must not be selected together. \nIn this mode, the counter is modified automatically following the speed and the direction of \nthe incremental encoder and its content, therefore, always represents the encoder’s \nposition. The count direction correspond to the rotation direction of the connected sensor. \nTable 94 summarizes the possible combinations, assuming TI1 and TI2 do not switch at the \nsame time.\n \nAn external incremental encoder can be connected directly to the MCU without external \ninterface logic. However, comparators are normally be used to convert the encoder’s \ndifferential outputs to digital signals. This greatly increases noise immunity. The third \nencoder output which indicate the mechanical zero position, may be connected to an \nexternal interrupt input and trigger a counter reset.\nFigure 127 gives an example of counter operation, showing count signal generation and \ndirection control. It also shows how input jitter is compensated where both edges are \nselected. This might occur if the sensor is positioned near to one of the switching points. For \nthis example we assume that the configuration is the following:\n•\nCC1S=’01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1).\n•\nCC2S=’01’ (TIMx_CCMR1 register, TI1FP2 mapped on TI2).\n•\nCC1P=’0’, CC1NP=’0’, and IC1F = ‘0000’ (TIMx_CCER register, TI1FP1 non-inverted, \nTI1FP1=TI1).\n•\nCC2P=’0’, CC2NP=’0’, and IC2F = ‘0000’ (TIMx_CCER register, TI1FP2 non-inverted, \nTI1FP2= TI2).\n•\nSMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling \nedges).\n•\nCEN=’1’ (TIMx_CR1 register, Counter enabled).\nTable 94. Counting direction versus encoder signals\nActive\nedge\nLevel on opposite signal\n(TI1FP1 for TI2, TI2FP2 for TI1)\nTI1FP1 signal\nTI2FP2 signal\nRising\nFalling\nRising\nFalling\nCounting on \nTI1 only\nHigh\nDown\nUp\nNo Count\nNo Count\nLow\nUp\nDown\nNo Count\nNo Count\nCounting on \nTI2 only\nHigh\nNo Count\nNo Count\nUp\nDown\nLow\nNo Count\nNo Count\nDown\nUp\nCounting on \nTI1 and TI2\nHigh\nDown\nUp\nUp\nDown\nLow\nUp\nDown\nDown\nUp\n" }, { "page_number": 557, "page_indices": { "start_index": 1114260, "end_index": 1115542 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 557 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.16 Encoder interface mode", 555 ] ], "page_content": "RM0090 Rev 21\n557/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 127. Example of counter operation in encoder interface mode.\nFigure 128 gives an example of counter behavior when TI1FP1 polarity is inverted (same \nconfiguration as above except CC1P=’1’).\nFigure 128. Example of encoder interface mode with TI1FP1 polarity inverted.\nThe timer, when configured in Encoder Interface mode provides information on the sensor’s \ncurrent position.The user can obtain dynamic information (speed, acceleration, \ndeceleration) by measuring the period between two encoder events using a second timer \nconfigured in capture mode. The output of the encoder which indicates the mechanical zero \ncan be used for this purpose. Depending on the time between two events, the counter can \nalso be read at regular times. This can be done by latching the counter value into a third \ninput capture register if available (then the capture signal must be periodic and can be \ngenerated by another timer). when available, it is also possible to read its value through a \nDMA request generated by a real-time clock.\nTI1\nbackward\njitter\njitter\nup\ndown\nup\nTI2\nCounter\nforward\nforward\nMS33107V1\nTI1\nbackward\njitter\njitter\nup\ndown\nTI2\nCounter\nforward\nforward\nMS33108V1\ndown\n" }, { "page_number": 558, "page_indices": { "start_index": 1115542, "end_index": 1118914 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 558 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.17 Timer input XOR function", 558 ], [ 3, "17.3.18 Interfacing with Hall sensors", 558 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n558/1757\nRM0090 Rev 21\n17.3.17 \nTimer input XOR function \nThe TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to \nthe output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and \nTIMx_CH3.\nThe XOR output can be used with all the timer input functions such as trigger or input \ncapture. An example of this feature used to interface Hall sensors is given in \nSection 17.3.18.\n17.3.18 \nInterfacing with Hall sensors\nThis is done using the advanced-control timers (TIM1 or TIM8) to generate PWM signals to \ndrive the motor and another timer TIMx (TIM2, TIM3, TIM4 or TIM5) referred to as \n“interfacing timer” in Figure 129. The “interfacing timer” captures the 3 timer input pins \n(TIMx_CH1, TIMx_CH2, and TIMx_CH3) connected through a XOR to the TI1 input channel \n(selected by setting the TI1S bit in the TIMx_CR2 register).\nThe slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus, \neach time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a \ntime base triggered by any change on the Hall inputs.\nOn the “interfacing timer”, capture/compare channel 1 is configured in capture mode, \ncapture signal is TRC (see Figure 112). The captured value, which corresponds to the time \nelapsed between 2 changes on the inputs, gives information about motor speed.\nThe “interfacing timer” can be used in output mode to generate a pulse which changes the \nconfiguration of the channels of the advanced-control timer (TIM1 or TIM8) (by triggering a \nCOM event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this, \nthe interfacing timer channel must be programmed so that a positive pulse is generated \nafter a programmed delay (in output compare or PWM mode). This pulse is sent to the \nadvanced-control timer (TIM1 or TIM8) through the TRGO output.\nExample: the user wants to change the PWM configuration of the advanced-control timer \nTIM1 after a programmed delay each time a change occurs on the Hall inputs connected to \none of the TIMx timers.\n•\nConfigure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the \nTIMx_CR2 register to ‘1’,\n•\nProgram the time base: write the TIMx_ARR to the max value (the counter must be \ncleared by the TI1 change. Set the prescaler to get a maximum counter period longer \nthan the time between 2 changes on the sensors,\n•\nProgram channel 1 in capture mode (TRC selected): write the CC1S bits in the \nTIMx_CCMR1 register to ‘11’. The user can also program the digital filter if needed,\n•\nProgram channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to ‘111’ \nand the CC2S bits to ‘00’ in the TIMx_CCMR1 register,\n•\nSelect OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 \nregister to ‘101’,\nIn the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the \ntimer is programmed to generate PWM signals, the capture/compare control signals are \npreloaded (CCPC=1 in the TIMx_CR2 register) and the COM event is controlled by the \ntrigger input (CCUS=1 in the TIMx_CR2 register). The PWM control bits (CCxE, OCxM) are \nwritten after a COM event for the next step (this can be done in an interrupt subroutine \ngenerated by the rising edge of OC2REF).\n" }, { "page_number": 559, "page_indices": { "start_index": 1118914, "end_index": 1119299 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 559 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.18 Interfacing with Hall sensors", 558 ] ], "page_content": "RM0090 Rev 21\n559/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nFigure 129 describes this example.\nFigure 129. Example of Hall sensor interface\nai17335b\nCounter (CNT)\nTRGO=OC2REF\n(CCR2)\nOC1\nOC1N\nCOM \nWrite CCxE, CCxNE\nTIH1\nTIH2\nTIH3\nCCR1\nOC2\nOC2N\nOC3\nOC3N\nC796\nand OCxM for next step\nInterfacing timer\nAdvanced-control timers \nC7A3\nC7A8\nC794\nC7A5\nC7AB\n" }, { "page_number": 560, "page_indices": { "start_index": 1119299, "end_index": 1121334 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 560 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.19 TIMx and external trigger synchronization", 560 ], [ 4, "Slave mode: Reset mode", 560 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n560/1757\nRM0090 Rev 21\n17.3.19 \nTIMx and external trigger synchronization\nThe TIMx timer can be synchronized with an external trigger in several modes: Reset mode, \nGated mode and Trigger mode.\nSlave mode: Reset mode\nThe counter and its prescaler can be reinitialized in response to an event on a trigger input. \nMoreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is \ngenerated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.\nIn the following example, the upcounter is cleared in response to a rising edge on TI1 input:\n•\nConfigure the channel 1 to detect rising edges on TI1. Configure the input filter duration \n(in this example, we don’t need any filter, so we keep IC1F=0000). The capture \nprescaler is not used for triggering, so there’s no need to configure it. The CC1S bits \nselect the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write \nCC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect \nrising edges only).\n•\nConfigure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select \nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\n•\nStart the counter by writing CEN=1 in the TIMx_CR1 register.\nThe counter starts counting on the internal clock, then behaves normally until TI1 rising \nedge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the \ntrigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA \nrequest can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).\nThe following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. \nThe delay between the rising edge on TI1 and the actual reset of the counter is due to the \nresynchronization circuit on TI1 input.\nFigure 130. Control circuit in reset mode\nMS31401V3\nUG\nTI1\n00\nCounter clock = CK_CNT = CK_PSC\nCounter register\n01\n02\n03\n00\n01\n02\n03\n32\n33\n34\n35\n36\n31\n30\nTIF\n" }, { "page_number": 561, "page_indices": { "start_index": 1121334, "end_index": 1122829 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 561 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.19 TIMx and external trigger synchronization", 560 ], [ 4, "Slave mode: Gated mode", 561 ] ], "page_content": "RM0090 Rev 21\n561/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nSlave mode: Gated mode\nThe counter can be enabled depending on the level of a selected input.\nIn the following example, the upcounter counts only when TI1 input is low:\n•\nConfigure the channel 1 to detect low levels on TI1. Configure the input filter duration \n(in this example, we don’t need any filter, so we keep IC1F=0000). The capture \nprescaler is not used for triggering, so the user does not need to configure it. The \nCC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register. \nWrite CC1P=1 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and \ndetect low level only).\n•\nConfigure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select \nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\n•\nEnable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the \ncounter doesn’t start if CEN=0, whatever is the trigger input level).\nThe counter starts counting on the internal clock as long as TI1 is low and stops as soon as \nTI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts \nor stops.\nThe delay between the rising edge on TI1 and the actual stop of the counter is due to the \nresynchronization circuit on TI1 input.\nFigure 131. Control circuit in gated mode\nMS31402V3\nTI1\nCNT_EN\nWrite TIF=0\nCounter clock = ck_cnt = ck_psc\nCounter register\nTIF\n37 38\n32\n33\n34\n35\n36\n31\n30\n" }, { "page_number": 562, "page_indices": { "start_index": 1122829, "end_index": 1125143 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 562 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.19 TIMx and external trigger synchronization", 560 ], [ 4, "Slave mode: Trigger mode", 562 ], [ 4, "Slave mode: external clock mode 2 + trigger mode", 562 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n562/1757\nRM0090 Rev 21\nSlave mode: Trigger mode\nThe counter can start in response to an event on a selected input.\nIn the following example, the upcounter starts in response to a rising edge on TI2 input:\n•\nConfigure the channel 2 to detect rising edges on TI2. Configure the input filter duration \n(in this example, we don’t need any filter, so we keep IC2F=0000). The capture \nprescaler is not used for triggering, so there’s no need to configure it. The CC2S bits \nare configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 \nregister. Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity \n(and detect low level only).\n•\nConfigure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select \nTI2 as the input source by writing TS=110 in TIMx_SMCR register.\nWhen a rising edge occurs on TI2, the counter starts counting on the internal clock and the \nTIF flag is set.\nThe delay between the rising edge on TI2 and the actual start of the counter is due to the \nresynchronization circuit on TI2 input.\nFigure 132. Control circuit in trigger mode\nSlave mode: external clock mode 2 + trigger mode\nThe external clock mode 2 can be used in addition to another slave mode (except external \nclock mode 1 and encoder mode). In this case, the ETR signal is used as external clock \ninput, and another input can be selected as trigger input (in reset mode, gated mode or \ntrigger mode). It is recommended not to select ETR as TRGI through the TS bits of \nTIMx_SMCR register.\nIn the following example, the upcounter is incremented at each rising edge of the ETR \nsignal as soon as a rising edge of TI1 occurs:\n1.\nConfigure the external trigger input circuit by programming the TIMx_SMCR register as \nfollows:\n–\nETF = 0000: no filter \n–\nETPS = 00: prescaler disabled\n–\nETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock \nmode 2.\n2. \nConfigure the channel 1 as follows, to detect rising edges on TI: \n–\nIC1F=0000: no filter. \n–\nThe capture prescaler is not used for triggering and does not need to be \nconfigured.\n–\nCC1S=01 in TIMx_CCMR1 register to select only the input capture source\nMS31403V2\nTI2\nCNT_EN\nCounter clock = ck_cnt = ck_psc\nCounter register\nTIF\n37\n38\n34\n35\n36\n" }, { "page_number": 563, "page_indices": { "start_index": 1125143, "end_index": 1126910 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 563 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.3 TIM1 and TIM8 functional description", 521 ], [ 3, "17.3.20 Timer synchronization", 563 ], [ 3, "17.3.21 Debug mode", 563 ] ], "page_content": "RM0090 Rev 21\n563/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n–\nCC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and \ndetect rising edge only).\n3. \nConfigure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select \nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\nA rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on \nETR rising edges.\nThe delay between the rising edge of the ETR signal and the actual reset of the counter is \ndue to the resynchronization circuit on ETRP input. \nFigure 133. Control circuit in external clock mode 2 + trigger mode\n17.3.20 \nTimer synchronization\nThe TIM timers are linked together internally for timer synchronization or chaining. Refer to \nSection 18.3.15: Timer synchronization for details.\nNote:\nThe clock of the slave timer must be enabled prior to receive events from the master timer, \nand must not be changed on-the-fly while triggers are received from the master timer.\n17.3.21 \nDebug mode\nWhen the microcontroller enters debug mode (Cortex®-M4 with FPU core halted), the TIMx \ncounter either continues to work normally or stops, depending on DBG_TIMx_STOP \nconfiguration bit in DBG module. For more details, refer to Section 38.16.2: Debug support \nfor timers, watchdog, bxCAN and I2C.\nFor safety purposes, when the counter is stopped (DBG_TIMx_STOP = 1 in \nDBGMCU_APBx_FZ register), the outputs are disabled (as if the MOE bit was reset). The \noutputs can either be forced to an inactive state (OSSI bit = 1), or have their control taken \nover by the GPIO controller (OSSI bit = 0) to force them to Hi-Z.\nMS33110V1\n34\n35\n36\nTIF\nCounter register\nCounter clock = CK_CNT = CK_PSC\nETR\nCEN/CNT_EN\nTI1\n" }, { "page_number": 564, "page_indices": { "start_index": 1126910, "end_index": 1129255 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 564 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.1 TIM1 and TIM8 control register 1 (TIMx_CR1)", 564 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n564/1757\nRM0090 Rev 21\n17.4 \nTIM1 and TIM8 registers\nRefer to Section 2.2 for a list of abbreviations used in register descriptions.\nThe peripheral registers must be written by half-words (16 bits) or words (32 bits). Read \naccesses can be done by bytes (8 bits), half-word (16 bits) or words (32 bits).\n17.4.1 \nTIM1 and TIM8 control register 1 (TIMx_CR1)\nAddress offset: 0x00\nReset value: 0x0000\n \n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCKD[1:0]\nARPE\nCMS[1:0]\nDIR\nOPM\nURS\nUDIS\nCEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:10 Reserved, must be kept at reset value.\nBits 9:8 CKD[1:0]: Clock division\nThis bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the \ndead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters \n(ETR, TIx),\n00: tDTS=tCK_INT\n01: tDTS=2*tCK_INT\n10: tDTS=4*tCK_INT\n11: Reserved, do not program this value\nBit 7 ARPE: Auto-reload preload enable\n0: TIMx_ARR register is not buffered\n1: TIMx_ARR register is buffered\nBits 6:5 CMS[1:0]: Center-aligned mode selection\n00: Edge-aligned mode. The counter counts up or down depending on the direction bit \n(DIR).\n01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare \ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set \nonly when the counter is counting down.\n10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare \ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set \nonly when the counter is counting up.\n11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare \ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set \nboth when the counter is counting up or down.\nNote: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as \nthe counter is enabled (CEN=1)\nBit 4 DIR: Direction\n0: Counter used as upcounter\n1: Counter used as downcounter\nNote: This bit is read only when the timer is configured in Center-aligned mode or Encoder \nmode.\nBit 3 OPM: One pulse mode\n0: Counter is not stopped at update event\n1: Counter stops counting at the next update event (clearing the bit CEN)\n" }, { "page_number": 565, "page_indices": { "start_index": 1129255, "end_index": 1131264 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 565 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.2 TIM1 and TIM8 control register 2 (TIMx_CR2)", 565 ] ], "page_content": "RM0090 Rev 21\n565/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.4.2 \nTIM1 and TIM8 control register 2 (TIMx_CR2)\nAddress offset: 0x04\nReset value: 0x0000\n \n \nBit 2 URS: Update request source\nThis bit is set and cleared by software to select the UEV event sources.\n0: Any of the following events generate an update interrupt or DMA request if enabled. \nThese events can be: \n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\n1: Only counter overflow/underflow generates an update interrupt or DMA request if \nenabled.\nBit 1 UDIS: Update disable\nThis bit is set and cleared by software to enable/disable UEV event generation.\n0: UEV enabled. The Update (UEV) event is generated by one of the following events:\n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\nBuffered registers are then loaded with their preload values.\n1: UEV disabled. The Update event is not generated, shadow registers keep their value \n(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is \nset or if a hardware reset is received from the slave mode controller.\nBit 0 CEN: Counter enable\n0: Counter disabled\n1: Counter enabled\nNote: External clock, gated mode and encoder mode can work only if the CEN bit has been \npreviously set by software. However trigger mode can set the CEN bit automatically by \nhardware.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nOIS4\nOIS3N\nOIS3\nOIS2N\nOIS2\nOIS1N\nOIS1\nTI1S\nMMS[2:0]\nCCDS\nCCUS\nRes.\nCCPC\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 Reserved, must be kept at reset value.\nBit 14 OIS4: Output Idle state 4 (OC4 output)\nrefer to OIS1 bit\nBit 13 OIS3N: Output Idle state 3 (OC3N output)\nrefer to OIS1N bit\nBit 12 OIS3: Output Idle state 3 (OC3 output)\nrefer to OIS1 bit\nBit 11 OIS2N: Output Idle state 2 (OC2N output)\nrefer to OIS1N bit\nBit 10 OIS2: Output Idle state 2 (OC2 output)\nrefer to OIS1 bit\n" }, { "page_number": 566, "page_indices": { "start_index": 1131264, "end_index": 1133921 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 566 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.2 TIM1 and TIM8 control register 2 (TIMx_CR2)", 565 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n566/1757\nRM0090 Rev 21\nBit 9 OIS1N: Output Idle state 1 (OC1N output)\n0: OC1N=0 after a dead-time when MOE=0\n1: OC1N=1 after a dead-time when MOE=0\nNote: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed \n(LOCK bits in TIMx_BDTR register).\nBit 8 OIS1: Output Idle state 1 (OC1 output)\n0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0\n1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0\nNote: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed \n(LOCK bits in TIMx_BDTR register).\nBit 7 TI1S: TI1 selection\n0: The TIMx_CH1 pin is connected to TI1 input\n1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)\nBits 6:4 MMS[2:0]: Master mode selection\nThese bits allow to select the information to be sent in master mode to slave timers for \nsynchronization (TRGO). The combination is as follows:\n000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the \nreset is generated by the trigger input (slave mode controller configured in reset mode) then \nthe signal on TRGO is delayed compared to the actual reset.\n001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is \nuseful to start several timers at the same time or to control a window in which a slave timer is \nenable. The Counter Enable signal is generated by a logic OR between CEN control bit and \nthe trigger input when configured in gated mode. When the Counter Enable signal is \ncontrolled by the trigger input, there is a delay on TRGO, except if the master/slave mode is \nselected (see the MSM bit description in TIMx_SMCR register).\n010: Update - The update event is selected as trigger output (TRGO). For instance a master \ntimer can then be used as a prescaler for a slave timer.\n011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be \nset (even if it was already high), as soon as a capture or a compare match occurred. \n(TRGO).\n100: Compare - OC1REF signal is used as trigger output (TRGO)\n101: Compare - OC2REF signal is used as trigger output (TRGO)\n110: Compare - OC3REF signal is used as trigger output (TRGO)\n111: Compare - OC4REF signal is used as trigger output (TRGO)\nNote: The clock of the slave timer and ADC must be enabled prior to receiving events from \nthe master timer, and must not be changed on-the-fly while triggers are received from \nthe master timer.\nBit 3 CCDS: Capture/compare DMA selection\n0: CCx DMA request sent when CCx event occurs\n1: CCx DMA requests sent when update event occurs\n" }, { "page_number": 567, "page_indices": { "start_index": 1133921, "end_index": 1134807 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 567 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.2 TIM1 and TIM8 control register 2 (TIMx_CR2)", 565 ] ], "page_content": "RM0090 Rev 21\n567/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nBit 2 CCUS: Capture/compare control update selection\n0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting \nthe COMG bit only\n1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting \nthe COMG bit or when an rising edge occurs on TRGI\nNote: This bit acts only on channels that have a complementary output.\nBit 1 Reserved, must be kept at reset value.\nBit 0 CCPC: Capture/compare preloaded control\n0: CCxE, CCxNE and OCxM bits are not preloaded\n1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated \nonly when a commutation event (COM) occurs (COMG bit set or rising edge detected on \nTRGI, depending on the CCUS bit).\nNote: This bit acts only on channels that have a complementary output.\n" }, { "page_number": 568, "page_indices": { "start_index": 1134807, "end_index": 1136420 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 568 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.3 TIM1 and TIM8 slave mode control register (TIMx_SMCR)", 568 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n568/1757\nRM0090 Rev 21\n17.4.3 \nTIM1 and TIM8 slave mode control register (TIMx_SMCR)\nAddress offset: 0x08\nReset value: 0x0000\n \n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nETP\nECE\nETPS[1:0]\nETF[3:0]\nMSM\nTS[2:0]\nRes.\nSMS[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nRes.\nrw\nrw\nrw\nBit 15 ETP: External trigger polarity\nThis bit selects whether ETR or ETR is used for trigger operations\n0: ETR is non-inverted, active at high level or rising edge.\n1: ETR is inverted, active at low level or falling edge.\nBit 14 ECE: External clock enable\nThis bit enables External clock mode 2.\n0: External clock mode 2 disabled\n1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF \nsignal.\nNote: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with \nTRGI connected to ETRF (SMS=111 and TS=111).\n2: It is possible to simultaneously use external clock mode 2 with the following slave \nmodes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be \nconnected to ETRF in this case (TS bits must not be 111).\n3: If external clock mode 1 and external clock mode 2 are enabled at the same time, \nthe external clock input is ETRF.\nBits 13:12 ETPS[1:0]: External trigger prescaler\nExternal trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A \nprescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external \nclocks.\n00: Prescaler OFF\n01: ETRP frequency divided by 2\n10: ETRP frequency divided by 4\n11: ETRP frequency divided by 8\n" }, { "page_number": 569, "page_indices": { "start_index": 1136420, "end_index": 1138189 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 569 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.3 TIM1 and TIM8 slave mode control register (TIMx_SMCR)", 568 ] ], "page_content": "RM0090 Rev 21\n569/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nBits 11:8 ETF[3:0]: External trigger filter\nThis bit-field then defines the frequency used to sample ETRP signal and the length of the \ndigital filter applied to ETRP. The digital filter is made of an event counter in which N \nconsecutive events are needed to validate a transition on the output:\n0000: No filter, sampling is done at fDTS\n0001: fSAMPLING=fCK_INT, N=2\n0010: fSAMPLING=fCK_INT, N=4\n0011: fSAMPLING=fCK_INT, N=8\n0100: fSAMPLING=fDTS/2, N=6\n0101: fSAMPLING=fDTS/2, N=8\n0110: fSAMPLING=fDTS/4, N=6\n0111: fSAMPLING=fDTS/4, N=8\n1000: fSAMPLING=fDTS/8, N=6\n1001: fSAMPLING=fDTS/8, N=8\n1010: fSAMPLING=fDTS/16, N=5\n1011: fSAMPLING=fDTS/16, N=6\n1100: fSAMPLING=fDTS/16, N=8\n1101: fSAMPLING=fDTS/32, N=5\n1110: fSAMPLING=fDTS/32, N=6\n1111: fSAMPLING=fDTS/32, N=8\nBit 7 MSM: Master/slave mode\n0: No action\n1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect \nsynchronization between the current timer and its slaves (through TRGO). It is useful if we \nwant to synchronize several timers on a single external event.\nBits 6:4 TS[2:0]: Trigger selection\nThis bit-field selects the trigger input to be used to synchronize the counter.\n000: Internal Trigger 0 (ITR0) \n001: Internal Trigger 1 (ITR1)\n010: Internal Trigger 2 (ITR2)\n011: Internal Trigger 3 (ITR3)\n100: TI1 Edge Detector (TI1F_ED)\n101: Filtered Timer Input 1 (TI1FP1)\n110: Filtered Timer Input 2 (TI2FP2)\n111: External Trigger input (ETRF)\nSee Table 95 for more details on ITRx meaning for each Timer.\nNote: These bits must be changed only when they are not used (e.g. when SMS=000) to \navoid wrong edge detections at the transition.\nBit 3 Reserved, must be kept at reset value.\n" }, { "page_number": 570, "page_indices": { "start_index": 1138189, "end_index": 1140644 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 570 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.4 TIM1 and TIM8 DMA/interrupt enable register (TIMx_DIER)", 570 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n570/1757\nRM0090 Rev 21\n \n17.4.4 \nTIM1 and TIM8 DMA/interrupt enable register (TIMx_DIER)\nAddress offset: 0x0C\nReset value: 0x0000\n \nBits 2:0 SMS: Slave mode selection\nWhen external signals are selected the active edge of the trigger signal (TRGI) is linked to \nthe polarity selected on the external input (see Input Control register and Control register \ndescription.\n000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal \nclock.\n001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 \nlevel.\n010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 \nlevel.\n011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges \ndepending on the level of the other input.\n100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter \nand generates an update of the registers.\n101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The \ncounter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of \nthe counter are controlled.\n110: Trigger mode - The counter starts at a rising edge of the trigger TRGI (but it is not \nreset). Only the start of the counter is controlled.\n111: External Clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.\nNote: The gated mode must not be used if TI1F_ED is selected as the trigger input \n(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the \ngated mode checks the level of the trigger signal.\nThe clock of the slave timer must be enabled prior to receiving events from the master \ntimer, and must not be changed on-the-fly while triggers are received from the master \ntimer.\nTable 95. TIMx Internal trigger connection\nSlave TIM\nITR0 (TS = 000)\nITR1 (TS = 001)\nITR2 (TS = 010)\nITR3 (TS = 011)\nTIM1\nTIM5_TRGO\nTIM2_TRGO\nTIM3_TRGO\nTIM4_TRGO\nTIM8\nTIM1_TRGO\nTIM2_TRGO\nTIM4_TRGO\nTIM5_TRGO\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nTDE\nCOMDE CC4DE CC3DE CC2DE CC1DE\nUDE\nBIE\nTIE\nCOMIE\nCC4IE\nCC3IE\nCC2IE\nCC1IE\nUIE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 Reserved, must be kept at reset value.\nBit 14 TDE: Trigger DMA request enable\n0: Trigger DMA request disabled\n1: Trigger DMA request enabled\nBit 13 COMDE: COM DMA request enable\n0: COM DMA request disabled\n1: COM DMA request enabled\n" }, { "page_number": 571, "page_indices": { "start_index": 1140644, "end_index": 1142018 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 571 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.4 TIM1 and TIM8 DMA/interrupt enable register (TIMx_DIER)", 570 ] ], "page_content": "RM0090 Rev 21\n571/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nBit 12 CC4DE: Capture/Compare 4 DMA request enable\n0: CC4 DMA request disabled\n1: CC4 DMA request enabled\nBit 11 CC3DE: Capture/Compare 3 DMA request enable\n0: CC3 DMA request disabled\n1: CC3 DMA request enabled\nBit 10 CC2DE: Capture/Compare 2 DMA request enable\n0: CC2 DMA request disabled\n1: CC2 DMA request enabled\nBit 9 CC1DE: Capture/Compare 1 DMA request enable\n0: CC1 DMA request disabled\n1: CC1 DMA request enabled\nBit 8 UDE: Update DMA request enable\n0: Update DMA request disabled\n1: Update DMA request enabled\nBit 7 BIE: Break interrupt enable\n0: Break interrupt disabled\n1: Break interrupt enabled\nBit 6 TIE: Trigger interrupt enable\n0: Trigger interrupt disabled\n1: Trigger interrupt enabled\nBit 5 COMIE: COM interrupt enable\n0: COM interrupt disabled\n1: COM interrupt enabled\nBit 4 CC4IE: Capture/Compare 4 interrupt enable\n0: CC4 interrupt disabled\n1: CC4 interrupt enabled\nBit 3 CC3IE: Capture/Compare 3 interrupt enable\n0: CC3 interrupt disabled\n1: CC3 interrupt enabled\nBit 2 CC2IE: Capture/Compare 2 interrupt enable\n0: CC2 interrupt disabled\n1: CC2 interrupt enabled\nBit 1 CC1IE: Capture/Compare 1 interrupt enable\n0: CC1 interrupt disabled\n1: CC1 interrupt enabled\nBit 0 UIE: Update interrupt enable\n0: Update interrupt disabled\n1: Update interrupt enabled\n" }, { "page_number": 572, "page_indices": { "start_index": 1142018, "end_index": 1144034 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 572 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.5 TIM1 and TIM8 status register (TIMx_SR)", 572 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n572/1757\nRM0090 Rev 21\n17.4.5 \nTIM1 and TIM8 status register (TIMx_SR)\nAddress offset: 0x10\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCC4OF CC3OF CC2OF CC1OF\nRes.\nBIF\nTIF\nCOMIF\nCC4IF\nCC3IF\nCC2IF\nCC1IF\nUIF\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nRes.\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nBits 15:13 Reserved, must be kept at reset value.\nBit 12 CC4OF: Capture/Compare 4 overcapture flag\nrefer to CC1OF description\nBit 11 CC3OF: Capture/Compare 3 overcapture flag\nrefer to CC1OF description\nBit 10 CC2OF: Capture/Compare 2 overcapture flag\nrefer to CC1OF description\nBit 9 CC1OF: Capture/Compare 1 overcapture flag\nThis flag is set by hardware only when the corresponding channel is configured in input \ncapture mode. It is cleared by software by writing it to ‘0’.\n0: No overcapture has been detected.\n1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was \nalready set\nBit 8 Reserved, must be kept at reset value.\nBit 7 BIF: Break interrupt flag\nThis flag is set by hardware as soon as the break input goes active. It can be cleared by \nsoftware if the break input is not active.\n0: No break event occurred.\n1: An active level has been detected on the break input.\nBit 6 TIF: Trigger interrupt flag\nThis flag is set by hardware on trigger event (active edge detected on TRGI input when the \nslave mode controller is enabled in all modes but gated mode. It is set when the counter \nstarts or stops when gated mode is selected. It is cleared by software.\n0: No trigger event occurred.\n1: Trigger interrupt pending.\nBit 5 COMIF: COM interrupt flag\nThis flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, \nCCxNE, OCxM - have been updated). It is cleared by software.\n0: No COM event occurred.\n1: COM interrupt pending.\nBit 4 CC4IF: Capture/Compare 4 interrupt flag\nrefer to CC1IF description\nBit 3 CC3IF: Capture/Compare 3 interrupt flag\nrefer to CC1IF description\n" }, { "page_number": 573, "page_indices": { "start_index": 1144034, "end_index": 1146544 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 573 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.6 TIM1 and TIM8 event generation register (TIMx_EGR)", 573 ] ], "page_content": "RM0090 Rev 21\n573/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.4.6 \nTIM1 and TIM8 event generation register (TIMx_EGR)\nAddress offset: 0x14\nReset value: 0x0000\n \nBit 2 CC2IF: Capture/Compare 2 interrupt flag\nrefer to CC1IF description\nBit 1 CC1IF: Capture/Compare 1 interrupt flag\nIf channel CC1 is configured as output:\nThis flag is set by hardware when the counter matches the compare value, with some \nexception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register \ndescription). It is cleared by software.\n0: No match.\n1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. \nWhen the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF \nbit goes high on the counter overflow (in upcounting and up/down-counting modes) or \nunderflow (in downcounting mode)\nIf channel CC1 is configured as input:\nThis bit is set by hardware on a capture. It is cleared by software or by reading the \nTIMx_CCR1 register.\n0: No input capture occurred\n1: The counter value has been captured in TIMx_CCR1 register (An edge has been \ndetected on IC1 which matches the selected polarity)\nBit 0 UIF: Update interrupt flag\nThis bit is set by hardware on an update event. It is cleared by software.\n0: No update occurred.\n1: Update interrupt pending. This bit is set by hardware when the registers are updated:\n– At overflow or underflow regarding the repetition counter value (update if repetition counter \n= 0) and if the UDIS=0 in the TIMx_CR1 register.\n– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and \nUDIS=0 in the TIMx_CR1 register.\n– When CNT is reinitialized by a trigger event (refer to Section 17.4.3: TIM1 and TIM8 slave \nmode control register (TIMx_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBG\nTG\nCOMG\nCC4G\nCC3G\nCC2G\nCC1G\nUG\nw\nw\nw\nw\nw\nw\nw\nw\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 BG: Break generation\nThis bit is set by software in order to generate an event, it is automatically cleared by \nhardware.\n0: No action\n1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or \nDMA transfer can occur if enabled.\nBit 6 TG: Trigger generation\nThis bit is set by software in order to generate an event, it is automatically cleared by \nhardware.\n0: No action\n1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if \nenabled.\n" }, { "page_number": 574, "page_indices": { "start_index": 1146544, "end_index": 1148137 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 574 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.6 TIM1 and TIM8 event generation register (TIMx_EGR)", 573 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n574/1757\nRM0090 Rev 21\nBit 5 COMG: Capture/Compare control update generation\nThis bit can be set by software, it is automatically cleared by hardware\n0: No action\n1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits\nNote: This bit acts only on channels having a complementary output.\nBit 4 CC4G: Capture/Compare 4 generation\nrefer to CC1G description\nBit 3 CC3G: Capture/Compare 3 generation\nrefer to CC1G description\nBit 2 CC2G: Capture/Compare 2 generation\nrefer to CC1G description\nBit 1 CC1G: Capture/Compare 1 generation\nThis bit is set by software in order to generate an event, it is automatically cleared by \nhardware.\n0: No action\n1: A capture/compare event is generated on channel 1:\nIf channel CC1 is configured as output:\nCC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.\nIf channel CC1 is configured as input:\nThe current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, \nthe corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the \nCC1IF flag was already high.\nBit 0 UG: Update generation\nThis bit can be set by software, it is automatically cleared by hardware.\n0: No action\n1: Reinitialize the counter and generates an update of the registers. Note that the prescaler \ncounter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if \nthe center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload \nvalue (TIMx_ARR) if DIR=1 (downcounting).\n" }, { "page_number": 575, "page_indices": { "start_index": 1148137, "end_index": 1150048 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 575 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.7 TIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1)", 575 ], [ 4, "Output compare mode:", 575 ] ], "page_content": "RM0090 Rev 21\n575/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.4.7 \nTIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1)\nAddress offset: 0x18\nReset value: 0x0000\nThe channels can be used in input (capture mode) or in output (compare mode). The \ndirection of a channel is defined by configuring the corresponding CCxS bits. All the other \nbits of this register have a different function in input and in output mode. For a given bit, \nOCxx describes its function when the channel is configured in output, ICxx describes its \nfunction when the channel is configured in input. So the user must take care that the same \nbit can have a different meaning for the input stage and for the output stage.\n \nOutput compare mode:\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOC2\nCE\nOC2M[2:0]\nOC2\nPE\nOC2\nFE\nCC2S[1:0]\nOC1\nCE\nOC1M[2:0]\nOC1\nPE\nOC1\nFE\nCC1S[1:0]\nIC2F[3:0]\nIC2PSC[1:0]\nIC1F[3:0]\nIC1PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 OC2CE: Output compare 2 clear enable\nBits 14:12 OC2M[2:0]: Output compare 2 mode\nBit 11 OC2PE: Output compare 2 preload enable\nBit 10 OC2FE: Output compare 2 fast enable\nBits 9:8 CC2S[1:0]: Capture/Compare 2 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC2 channel is configured as output\n01: CC2 channel is configured as input, IC2 is mapped on TI2\n10: CC2 channel is configured as input, IC2 is mapped on TI1\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through the TS bit (TIMx_SMCR register)\nNote: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).\nBit 7 OC1CE: Output compare 1 clear enable\nOC1CE: Output compare 1 Clear Enable\n0: OC1Ref is not affected by the ETRF Input\n1: OC1Ref is cleared as soon as a High level is detected on ETRF input\n" }, { "page_number": 576, "page_indices": { "start_index": 1150048, "end_index": 1153698 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 576 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.7 TIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1)", 575 ], [ 4, "Output compare mode:", 575 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n576/1757\nRM0090 Rev 21\nBits 6:4 OC1M: Output compare 1 mode\nThese bits define the behavior of the output reference signal OC1REF from which OC1 and \nOC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends \non CC1P and CC1NP bits.\n000: Frozen - The comparison between the output compare register TIMx_CCR1 and the \ncounter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing \nbase).\n001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter \nTIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).\n010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the \ncounter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).\n011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.\n100: Force inactive level - OC1REF is forced low.\n101: Force active level - OC1REF is forced high.\n110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (OC1REF=’1’).\n111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 else \ninactive.\nNote: 1: These bits can not be modified as long as LOCK level 3 has been programmed \n(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in \noutput).\n2: In PWM mode 1 or 2, the OCREF level changes only when the result of the \ncomparison changes or when the output compare mode switches from “frozen” mode \nto “PWM” mode.\n3: On channels having a complementary output, this bit field is preloaded. If the CCPC \nbit is set in the TIMx_CR2 register then the OC1M active bits take the new value from \nthe preloaded bits only when a COM event is generated.\nBit 3 OC1PE: Output compare 1 preload enable\n0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the \nnew value is taken in account immediately.\n1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload \nregister. TIMx_CCR1 preload value is loaded in the active register at each update event.\nNote: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK \nbits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).\nBit 2 OC1FE: Output compare 1 fast enable\nThis bit is used to accelerate the effect of an event on the trigger in input on the CC output.\n0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is \nON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is \n5 clock cycles.\n1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is \nset to the compare level independently from the result of the comparison. Delay to sample \nthe trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if \nthe channel is configured in PWM1 or PWM2 mode.\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: CC1 channel is configured as input, IC1 is mapped on TI2\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).\n" }, { "page_number": 577, "page_indices": { "start_index": 1153698, "end_index": 1156252 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 577 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.7 TIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1)", 575 ], [ 4, "Input capture mode", 577 ], [ 3, "17.4.8 TIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2)", 577 ] ], "page_content": "RM0090 Rev 21\n577/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nInput capture mode\n \n17.4.8 \nTIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2)\nAddress offset: 0x1C\nBits 15:12 IC2F: Input capture 2 filter\nBits 11:10 IC2PSC[1:0]: Input capture 2 prescaler\nBits 9:8 CC2S: Capture/Compare 2 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC2 channel is configured as output\n01: CC2 channel is configured as input, IC2 is mapped on TI2\n10: CC2 channel is configured as input, IC2 is mapped on TI1\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an \ninternal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).\nBits 7:4 IC1F[3:0]: Input capture 1 filter\nThis bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied \nto TI1. The digital filter is made of an event counter in which N consecutive events are needed to \nvalidate a transition on the output:\n0000: No filter, sampling is done at fDTS\n0001: fSAMPLING=fCK_INT, N=2\n0010: fSAMPLING=fCK_INT, N=4\n0011: fSAMPLING=fCK_INT, N=8\n0100: fSAMPLING=fDTS/2, N=6\n0101: fSAMPLING=fDTS/2, N=8\n0110: fSAMPLING=fDTS/4, N=6\n0111: fSAMPLING=fDTS/4, N=8\n1000: fSAMPLING=fDTS/8, N=6\n1001: fSAMPLING=fDTS/8, N=8\n1010: fSAMPLING=fDTS/16, N=5\n1011: fSAMPLING=fDTS/16, N=6\n1100: fSAMPLING=fDTS/16, N=8\n1101: fSAMPLING=fDTS/32, N=5\n1110: fSAMPLING=fDTS/32, N=6\n1111: fSAMPLING=fDTS/32, N=8\nBits 3:2 IC1PSC: Input capture 1 prescaler\nThis bit-field defines the ratio of the prescaler acting on CC1 input (IC1).\nThe prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).\n00: no prescaler, capture is done each time an edge is detected on the capture input\n01: capture is done once every 2 events\n10: capture is done once every 4 events\n11: capture is done once every 8 events\nBits 1:0 CC1S: Capture/Compare 1 Selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: CC1 channel is configured as input, IC1 is mapped on TI2\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an \ninternal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).\n" }, { "page_number": 578, "page_indices": { "start_index": 1156252, "end_index": 1158095 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 578 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.8 TIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2)", 577 ], [ 4, "Output compare mode", 578 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n578/1757\nRM0090 Rev 21\nReset value: 0x0000\nRefer to the above CCMR1 register description.\nOutput compare mode\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOC4\nCE\nOC4M[2:0]\nOC4\nPE\nOC4\nFE\nCC4S[1:0]\nOC3\nCE.\nOC3M[2:0]\nOC3\nPE\nOC3\nFE\nCC3S[1:0]\nIC4F[3:0]\nIC4PSC[1:0]\nIC3F[3:0]\nIC3PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 OC4CE: Output compare 4 clear enable\nBits 14:12 OC4M: Output compare 4 mode\nBit 11 OC4PE: Output compare 4 preload enable\nBit 10 OC4FE: Output compare 4 fast enable\nBits 9:8 CC4S: Capture/Compare 4 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC4 channel is configured as output\n01: CC4 channel is configured as input, IC4 is mapped on TI4\n10: CC4 channel is configured as input, IC4 is mapped on TI3\n11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).\nBit 7 OC3CE: Output compare 3 clear enable\nBits 6:4 OC3M: Output compare 3 mode\nBit 3 OC3PE: Output compare 3 preload enable\nBit 2 OC3FE: Output compare 3 fast enable\nBits 1:0 CC3S: Capture/Compare 3 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC3 channel is configured as output\n01: CC3 channel is configured as input, IC3 is mapped on TI3\n10: CC3 channel is configured as input, IC3 is mapped on TI4\n11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).\n" }, { "page_number": 579, "page_indices": { "start_index": 1158095, "end_index": 1160302 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 579 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.8 TIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2)", 577 ], [ 4, "Input capture mode", 579 ], [ 3, "17.4.9 TIM1 and TIM8 capture/compare enable register (TIMx_CCER)", 579 ] ], "page_content": "RM0090 Rev 21\n579/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nInput capture mode\n \n17.4.9 \nTIM1 and TIM8 capture/compare enable register (TIMx_CCER)\nAddress offset: 0x20\nReset value: 0x0000\n \nBits 15:12 IC4F: Input capture 4 filter\nBits 11:10 IC4PSC: Input capture 4 prescaler\nBits 9:8 CC4S: Capture/Compare 4 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC4 channel is configured as output\n01: CC4 channel is configured as input, IC4 is mapped on TI4\n10: CC4 channel is configured as input, IC4 is mapped on TI3\n11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).\nBits 7:4 IC3F: Input capture 3 filter\nBits 3:2 IC3PSC: Input capture 3 prescaler\nBits 1:0 CC3S: Capture/compare 3 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC3 channel is configured as output\n01: CC3 channel is configured as input, IC3 is mapped on TI3\n10: CC3 channel is configured as input, IC3 is mapped on TI4\n11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCC4NP\nRes.\nCC4P\nCC4E\nCC3NP CC3NE\nCC3P\nCC3E\nCC2NP CC2NE\nCC2P\nCC2E\nCC1NP CC1NE\nCC1P\nCC1E\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 CC4NP: Capture/Compare 4 complementary output polarity\nrefer to CC1NP description\nBit 14 Reserved, must be kept at reset value.\nBit 13 CC4P: Capture/Compare 4 output polarity\nrefer to CC1P description\nBit 12 CC4E: Capture/Compare 4 output enable\nrefer to CC1E description\nBit 11 CC3NP: Capture/Compare 3 complementary output polarity\nrefer to CC1NP description\nBit 10 CC3NE: Capture/Compare 3 complementary output enable\nrefer to CC1NE description\nBit 9 CC3P: Capture/Compare 3 output polarity\nrefer to CC1P description\n" }, { "page_number": 580, "page_indices": { "start_index": 1160302, "end_index": 1161986 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 580 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.9 TIM1 and TIM8 capture/compare enable register (TIMx_CCER)", 579 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n580/1757\nRM0090 Rev 21\nBit 8 CC3E: Capture/Compare 3 output enable\nrefer to CC1E description\nBit 7 CC2NP: Capture/Compare 2 complementary output polarity\nrefer to CC1NP description\nBit 6 CC2NE: Capture/Compare 2 complementary output enable\nrefer to CC1NE description\nBit 5 CC2P: Capture/Compare 2 output polarity\nrefer to CC1P description\nBit 4 CC2E: Capture/Compare 2 output enable\nrefer to CC1E description\nBit 3 CC1NP: Capture/Compare 1 complementary output polarity\nCC1 channel configured as output:\n0: OC1N active high.\n1: OC1N active low.\nCC1 channel configured as input:\nThis bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer \nto CC1P description.\nNote: On channels having a complementary output, this bit is preloaded. If the CCPC bit is \nset in the TIMx_CR2 register then the CC1NP active bit takes the new value from the \npreloaded bit only when a Commutation event is generated.\nNote: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits \nin TIMx_BDTR register) and CC1S=”00” (the channel is configured in output).\nBit 2 CC1NE: Capture/Compare 1 complementary output enable\n0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N \nand CC1E bits.\n1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, \nOSSR, OIS1, OIS1N and CC1E bits.\nNote: On channels having a complementary output, this bit is preloaded. If the CCPC bit is \nset in the TIMx_CR2 register then the CC1NE active bit takes the new value from the \npreloaded bit only when a Commutation event is generated.\n" }, { "page_number": 581, "page_indices": { "start_index": 1161986, "end_index": 1164201 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 581 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.9 TIM1 and TIM8 capture/compare enable register (TIMx_CCER)", 579 ] ], "page_content": "RM0090 Rev 21\n581/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nBit 1 CC1P: Capture/Compare 1 output polarity\nCC1 channel configured as output:\n0: OC1 active high\n1: OC1 active low\nCC1 channel configured as input:\nCC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture \noperations.\n00: non-inverted/rising edge\nThe circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external \nclock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder \nmode).\n01: inverted/falling edge\nThe circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external \nclock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder \nmode).\n10: reserved, do not use this configuration.\n11: non-inverted/both edges\nThe circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations \nin reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated \nmode). This configuration must not be used in encoder mode.\nNote: On channels having a complementary output, this bit is preloaded. If the CCPC bit is \nset in the TIMx_CR2 register then the CC1P active bit takes the new value from the \npreloaded bit only when a Commutation event is generated.\nNote: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits \nin TIMx_BDTR register).\nBit 0 CC1E: Capture/Compare 1 output enable\nCC1 channel configured as output:\n0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N \nand CC1NE bits.\n1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, \nOSSR, OIS1, OIS1N and CC1NE bits.\nCC1 channel configured as input:\nThis bit determines if a capture of the counter value can actually be done into the input \ncapture/compare register 1 (TIMx_CCR1) or not.\n0: Capture disabled.\n1: Capture enabled.\nNote: On channels having a complementary output, this bit is preloaded. If the CCPC bit is \nset in the TIMx_CR2 register then the CC1E active bit takes the new value from the \npreloaded bit only when a Commutation event is generated.\n" }, { "page_number": 582, "page_indices": { "start_index": 1164201, "end_index": 1166194 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 582 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.9 TIM1 and TIM8 capture/compare enable register (TIMx_CCER)", 579 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n582/1757\nRM0090 Rev 21\n \nNote:\nThe state of the external I/O pins connected to the complementary OCx and OCxN channels \ndepends on the OCx and OCxN channel state and the GPIO registers.\nTable 96. Output control bits for complementary OCx and OCxN channels with\nbreak feature\nControl bits\nOutput states(1)\nMOE \nbit\nOSSI \nbit\nOSSR \nbit\nCCxE \nbit\nCCxNE \nbit\nOCx output state\nOCxN output state\n1\nX\n0\n0\n0\nOutput Disabled (not driven by \nthe timer), OCx=0, OCx_EN=0\nOutput Disabled (not driven by the \ntimer), OCxN=0, OCxN_EN=0\n0\n0\n1\nOutput Disabled (not driven by \nthe timer), OCx=0, OCx_EN=0\nOCxREF + Polarity OCxN=OCxREF \nxor CCxNP, OCxN_EN=1\n0\n1\n0\nOCxREF + Polarity\nOCx=OCxREF xor CCxP,\nOCx_EN=1\nOutput Disabled (not driven by the \ntimer)\nOCxN=0, OCxN_EN=0\n0\n1\n1\nOCREF + Polarity + dead-time\nOCx_EN=1\nComplementary to OCREF (not \nOCREF) + Polarity + dead-time\nOCxN_EN=1\n1\n0\n0\nOutput Disabled (not driven by \nthe timer)\nOCx=CCxP, OCx_EN=0\nOutput Disabled (not driven by the \ntimer)\nOCxN=CCxNP, OCxN_EN=0\n1\n0\n1\nOff-State (output enabled with \ninactive state)\nOCx=CCxP, OCx_EN=1\nOCxREF + Polarity\nOCxN=OCxREF xor CCxNP, \nOCxN_EN=1\n1\n1\n0\nOCxREF + Polarity\nOCx=OCxREF xor CCxP,\nOCx_EN=1\nOff-State (output enabled with \ninactive state)\nOCxN=CCxNP, OCxN_EN=1\n1\n1\n1\nOCREF + Polarity + dead-time\nOCx_EN=1\nComplementary to OCREF (not \nOCREF) + Polarity + dead-time\nOCxN_EN=1\n0\n0\nX\nX\nX\nOutput disabled (not driven by the timer anymore). The output state is \ndefined by the GPIO controller and can be High, Low or Hi-Z.\n1\n0\n0\n0\n1\nOff-State (output enabled with inactive state)\nAsynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP, \nOCxN_EN=1\nThen if the clock is present: OCx=OISx and OCxN=OISxN after a \ndead-time, assuming that OISx and OISxN do not correspond to OCX \nand OCxN both in active state\n1\n0\n1\n1\n1.\nWhen both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept \ncleared.\n" }, { "page_number": 583, "page_indices": { "start_index": 1166194, "end_index": 1167504 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 583 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.10 TIM1 and TIM8 counter (TIMx_CNT)", 583 ], [ 3, "17.4.11 TIM1 and TIM8 prescaler (TIMx_PSC)", 583 ], [ 3, "17.4.12 TIM1 and TIM8 auto-reload register (TIMx_ARR)", 583 ] ], "page_content": "RM0090 Rev 21\n583/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.4.10 \nTIM1 and TIM8 counter (TIMx_CNT)\nAddress offset: 0x24\nReset value: 0x0000\n \n17.4.11 \nTIM1 and TIM8 prescaler (TIMx_PSC)\nAddress offset: 0x28\nReset value: 0x0000\n \n17.4.12 \nTIM1 and TIM8 auto-reload register (TIMx_ARR)\nAddress offset: 0x2C\nReset value: 0xFFFF\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCNT[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CNT[15:0]: Counter value\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPSC[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 PSC[15:0]: Prescaler value\nThe counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1).\nPSC contains the value to be loaded in the active prescaler register at each update event \n(including when the counter is cleared through UG bit of TIMx_EGR register or through \ntrigger controller when configured in “reset mode”).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nARR[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 ARR[15:0]: Auto-reload value\nARR is the value to be loaded in the actual auto-reload register.\nRefer to Section 17.3.1: Time-base unit for more details about ARR update and behavior.\nThe counter is blocked while the auto-reload value is null.\n" }, { "page_number": 584, "page_indices": { "start_index": 1167504, "end_index": 1169537 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 584 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.13 TIM1 and TIM8 repetition counter register (TIMx_RCR)", 584 ], [ 3, "17.4.14 TIM1 and TIM8 capture/compare register 1 (TIMx_CCR1)", 584 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n584/1757\nRM0090 Rev 21\n17.4.13 \nTIM1 and TIM8 repetition counter register (TIMx_RCR)\nAddress offset: 0x30\nReset value: 0x0000\n \n17.4.14 \nTIM1 and TIM8 capture/compare register 1 (TIMx_CCR1)\nAddress offset: 0x34\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nREP[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value.\nBits 7:0 REP[7:0]: Repetition counter value\nThese bits allow the user to set-up the update rate of the compare registers (i.e. periodic \ntransfers from preload to active registers) when preload registers are enable, as well as the \nupdate interrupt generation rate, if this interrupt is enable.\nEach time the REP_CNT related downcounter reaches zero, an update event is generated \nand it restarts counting from REP value. As REP_CNT is reloaded with REP value only at \nthe repetition update event U_RC, any write to the TIMx_RCR register is not taken in \naccount until the next repetition update event.\nIt means in PWM mode (REP+1) corresponds to:\n–\nthe number of PWM periods in edge-aligned mode\n–\nthe number of half PWM period in center-aligned mode.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR1[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 15:0 CCR1[15:0]: Capture/Compare 1 value\nIf channel CC1 is configured as output:\nCCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register \n(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when \nan update event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signaled on OC1 output.\nIf channel CC1 is configured as input:\nCCR1 is the counter value transferred by the last input capture 1 event (IC1). The \nTIMx_CCR1 register is read-only and cannot be programmed.\n" }, { "page_number": 585, "page_indices": { "start_index": 1169537, "end_index": 1171525 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 585 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.15 TIM1 and TIM8 capture/compare register 2 (TIMx_CCR2)", 585 ], [ 3, "17.4.16 TIM1 and TIM8 capture/compare register 3 (TIMx_CCR3)", 585 ] ], "page_content": "RM0090 Rev 21\n585/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.4.15 \nTIM1 and TIM8 capture/compare register 2 (TIMx_CCR2)\nAddress offset: 0x38\nReset value: 0x0000\n \n17.4.16 \nTIM1 and TIM8 capture/compare register 3 (TIMx_CCR3)\nAddress offset: 0x3C\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR2[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 15:0 CCR2[15:0]: Capture/Compare 2 value\nIf channel CC2 is configured as output:\nCCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register \n(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when \nan update event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signalled on OC2 output.\nIf channel CC2 is configured as input:\nCCR2 is the counter value transferred by the last input capture 2 event (IC2). The \nTIMx_CCR2 register is read-only and cannot be programmed.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR3[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 15:0 CCR3[15:0]: Capture/Compare value\nIf channel CC3 is configured as output:\nCCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register \n(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when \nan update event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signalled on OC3 output.\nIf channel CC3 is configured as input:\nCCR3 is the counter value transferred by the last input capture 3 event (IC3). The \nTIMx_CCR3 register is read-only and cannot be programmed.\n" }, { "page_number": 586, "page_indices": { "start_index": 1171525, "end_index": 1173869 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 586 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.17 TIM1 and TIM8 capture/compare register 4 (TIMx_CCR4)", 586 ], [ 3, "17.4.18 TIM1 and TIM8 break and dead-time register (TIMx_BDTR)", 586 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n586/1757\nRM0090 Rev 21\n17.4.17 \nTIM1 and TIM8 capture/compare register 4 (TIMx_CCR4)\nAddress offset: 0x40\nReset value: 0x0000\n \n17.4.18 \nTIM1 and TIM8 break and dead-time register (TIMx_BDTR)\nAddress offset: 0x44\nReset value: 0x0000\nNote:\nAs the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on \nthe LOCK configuration, it can be necessary to configure all of them during the first write \naccess to the TIMx_BDTR register.\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR4[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 15:0 CCR4[15:0]: Capture/Compare value\nIf channel CC4 is configured as output:\nCCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register \n(bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when \nan update event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signalled on OC4 output.\nIf channel CC4 is configured as input:\nCCR4 is the counter value transferred by the last input capture 4 event (IC4). The \nTIMx_CCR3 register is read-only and cannot be programmed.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMOE\nAOE\nBKP\nBKE\nOSSR\nOSSI\nLOCK[1:0]\nDTG[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 MOE: Main output enable\nThis bit is cleared asynchronously by hardware as soon as the break input is active. It is set \nby software or automatically depending on the AOE bit. It is acting only on the channels \nwhich are configured in output.\n0: OC and OCN outputs are disabled or forced to idle state.\n1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in \nTIMx_CCER register).\nSee OC/OCN enable description for more details (Section 17.4.9: TIM1 and TIM8 \ncapture/compare enable register (TIMx_CCER)).\nBit 14 AOE: Automatic output enable\n0: MOE can be set only by software\n1: MOE can be set by software or automatically at the next update event (if the break input is \nnot be active)\nNote: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits \nin TIMx_BDTR register).\n" }, { "page_number": 587, "page_indices": { "start_index": 1173869, "end_index": 1176759 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 587 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.18 TIM1 and TIM8 break and dead-time register (TIMx_BDTR)", 586 ] ], "page_content": "RM0090 Rev 21\n587/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nBit 13 BKP: Break polarity\n0: Break input BRK is active low\n1: Break input BRK is active high\nNote: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits \nin TIMx_BDTR register).\nNote: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.\nBit 12 BKE: Break enable\n0: Break inputs (BRK and CSS clock failure event) disabled\n1; Break inputs (BRK and CSS clock failure event) enabled\nNote: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in \nTIMx_BDTR register).\nNote: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.\nBit 11 OSSR: Off-state selection for Run mode\nThis bit is used when MOE=1 on channels having a complementary output which are \nconfigured as outputs. OSSR is not implemented if no complementary output is implemented \nin the timer.\nSee OC/OCN enable description for more details (Section 17.4.9: TIM1 and TIM8 \ncapture/compare enable register (TIMx_CCER)).\n0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).\n1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 \nor CCxNE=1. Then, OC/OCN enable output signal=1\nNote: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK \nbits in TIMx_BDTR register).\nBit 10 OSSI: Off-state selection for Idle mode\nThis bit is used when MOE=0 on channels configured as outputs.\nSee OC/OCN enable description for more details (Section 17.4.9: TIM1 and TIM8 \ncapture/compare enable register (TIMx_CCER)).\n0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).\n1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or \nCCxNE=1. OC/OCN enable output signal=1)\nNote: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK \nbits in TIMx_BDTR register).\nBits 9:8 LOCK[1:0]: Lock configuration\nThese bits offer a write protection against software errors.\n00: LOCK OFF - No bit is write protected.\n01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 \nregister and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.\n10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER \nregister, as long as the related channel is configured in output through the CCxS bits) as well \nas OSSR and OSSI bits can no longer be written.\n11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in \nTIMx_CCMRx registers, as long as the related channel is configured in output through the \nCCxS bits) can no longer be written.\nNote: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register \nhas been written, their content is frozen until the next reset.\n" }, { "page_number": 588, "page_indices": { "start_index": 1176759, "end_index": 1178667 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 588 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.19 TIM1 and TIM8 DMA control register (TIMx_DCR)", 588 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n588/1757\nRM0090 Rev 21\n17.4.19 \nTIM1 and TIM8 DMA control register (TIMx_DCR)\nAddress offset: 0x48\nReset value: 0x0000\n \nBits 7:0 DTG[7:0]: Dead-time generator setup\nThis bit-field defines the duration of the dead-time inserted between the complementary \noutputs. DT correspond to this duration.\nDTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS.\nDTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS.\nDTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS.\nDTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS.\nExample if TDTS=125ns (8MHz), dead-time possible values are:\n0 to 15875 ns by 125 ns steps,\n16 us to 31750 ns by 250 ns steps,\n32 us to 63us by 1 us steps,\n64 us to 126 us by 2 us steps\nNote: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed \n(LOCK bits in TIMx_BDTR register).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDBL[4:0]\nReserved\nDBA[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:13 Reserved, must be kept at reset value.\nBits 12:8 DBL[4:0]: DMA burst length\nThis 5-bit vector defines the number of DMA transfers (the timer detects a burst transfer \nwhen a read or a write access to the TIMx_DMAR register address is performed). \nthe TIMx_DMAR address)\n00000: 1 transfer\n00001: 2 transfers\n00010: 3 transfers\n...\n10001: 18 transfers\nBits 7:5 Reserved, must be kept at reset value.\nBits 4:0 DBA[4:0]: DMA base address\nThis 5-bits vector defines the base-address for DMA transfers (when read/write access are \ndone through the TIMx_DMAR address). DBA is defined as an offset starting from the \naddress of the TIMx_CR1 register.\nExample:\n00000: TIMx_CR1,\n00001: TIMx_CR2,\n00010: TIMx_SMCR,\n...\nExample: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In \nthis case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.\n" }, { "page_number": 589, "page_indices": { "start_index": 1178667, "end_index": 1180957 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 589 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.20 TIM1 and TIM8 DMA address for full transfer (TIMx_DMAR)", 589 ], [ 4, "Example of how to use the DMA burst feature", 589 ] ], "page_content": "RM0090 Rev 21\n589/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\n17.4.20 \nTIM1 and TIM8 DMA address for full transfer (TIMx_DMAR)\nAddress offset: 0x4C\nReset value: 0x0000 0000\n \nExample of how to use the DMA burst feature\nIn this example the timer DMA burst feature is used to update the contents of the CCRx \nregisters (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers. \nThis is done in the following steps:\n1.\nConfigure the corresponding DMA channel as follows: \n–\nDMA channel peripheral address is the DMAR register address \n–\nDMA channel memory address is the address of the buffer in the RAM containing \nthe data to be transferred by DMA into CCRx registers. \n–\nNumber of data to transfer = 3 (See note below). \n–\nCircular mode disabled. \n2. \nConfigure the DCR register by configuring the DBA and DBL bit fields as follows: \nDBL = 3 transfers, DBA = 0xE. \n3. \nEnable the TIMx update DMA request (set the UDE bit in the DIER register). \n4. \nEnable TIMx \n5. \nEnable the DMA channel\nNote:\nThis example is for the case where every CCRx register to be updated once. If every CCRx \nregister is to be updated twice for example, the number of data to transfer should be 6. Let's \ntake the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and \ndata6. The data is transferred to the CCRx registers as follows: on the first update DMA \nrequest, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to \nCCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is \ntransferred to CCR3 and data6 is transferred to CCR4. \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDMAB[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDMAB[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 DMAB[31:0]: DMA register for burst accesses\nA read or write operation to the DMAR register accesses the register located at the address\n(TIMx_CR1 address) + (DBA + DMA index) x 4 \nwhere TIMx_CR1 address is the address of the control register 1, DBA is the DMA base \naddress configured in TIMx_DCR register, DMA index is automatically controlled by the \nDMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).\n" }, { "page_number": 590, "page_indices": { "start_index": 1180957, "end_index": 1183054 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 590 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.21 TIM1 and TIM8 register map", 590 ] ], "page_content": "Advanced-control timers (TIM1 and TIM8)\nRM0090\n590/1757\nRM0090 Rev 21\n17.4.21 \nTIM1 and TIM8 register map\nTIM1 and TIM8 registers are mapped as 16-bit addressable registers as described in the \ntable below:\n \nTable 97. TIM1 and TIM8 register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nTIMx_CR1\nReserved\nCKD \n[1:0]\nARPE\nCMS\n[1:0]\nDIR\nOPM\nURS\nUDIS\nCEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nTIMx_CR2\nReserved\nOIS4\nOIS3N\nOIS3\nOIS2N\nOIS2\nOIS1N\nOIS1\nTI1S\nMMS[2:0]\nCCDS\nCCUS\nReserved\nCCPC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nTIMx_SMCR\nReserved\nETP\nECE\nETP\nS \n[1:0]\nETF[3:0]\nMSM\nTS[2:0]\nReserved\nSMS[2:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nTIMx_DIER\nReserved\nTDE\nCOMDE\nCC4DE\nCC3DE\nCC2DE\nCC1DE\nUDE\nBIE\nTIE\nCOMIE\nCC4IE\nCC3IE\nCC2IE\nCC1IE\nUIE\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nTIMx_SR\nReserved\nCC4OF\nCC3OF\nCC2OF\nCC1OF\nReserved\nBIF\nTIF\nCOMIF\nCC4IF\nCC3IF\nCC2IF\nCC1IF\nUIF\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nTIMx_EGR\nReserved\nBG\nTG\nCOMG\nCC4G\nCC3G\nCC2G\nCC1G\nUG\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x18\nTIMx_CCMR1\nOutput compare \nmode\nReserved\nOC2CE\nOC2M\n[2:0]\nOC2PE\nOC2FE\nCC2S \n[1:0]\nOC1CE\nOC1M\n[2:0]\nOC1PE\nOC1FE\nCC1\nS \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTIMx_CCMR1\nInput capture \nmode\nReserved\nIC2F[3:0]\nIC2\nPSC\n[1:0]\nCC2S \n[1:0]\nIC1F[3:0]\nIC1\nPSC\n[1:0]\nCC1\nS \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nTIMx_CCMR2\nOutput compare \nmode\nReserved\nOC4CE\nOC4M\n[2:0]\nOC4PE\nOC4FE\nCC4S \n[1:0]\nOC3CE\nOC3M\n[2:0]\nOC3PE\nOC3FE\nCC3\nS \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTIMx_CCMR2\nInput capture \nmode\nReserved\nIC4F[3:0]\nIC4\nPSC\n[1:0]\nCC4S \n[1:0]\nIC3F[3:0]\nIC3\nPSC\n[1:0]\nCC3\nS \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nTIMx_CCER\nReserved\nCC4NP\nReserved\nCC4P\nCC4E\nCC3NP\nCC3NE\nCC3P\nCC3E\nCC2NP\nCC2NE\nCC2P\nCC2E\nCC1NP\nCC1NE\nCC1P\nCC1E\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x24\nTIMx_CNT\nReserved\nCNT[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nTIMx_PSC\nReserved\nPSC[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n" }, { "page_number": 591, "page_indices": { "start_index": 1183054, "end_index": 1184139 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 591 }, "toc_details": [ [ 1, "17 Advanced-control timers (TIM1 and TIM8)", 518 ], [ 2, "17.4 TIM1 and TIM8 registers", 564 ], [ 3, "17.4.21 TIM1 and TIM8 register map", 590 ] ], "page_content": "RM0090 Rev 21\n591/1757\nRM0090\nAdvanced-control timers (TIM1 and TIM8)\n591\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x2C\nTIMx_ARR\nReserved\nARR[15:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x30\nTIMx_RCR\nReserved\nREP[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x34\nTIMx_CCR1\nReserved\nCCR1[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x38\nTIMx_CCR2\nReserved\nCCR2[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x3C\nTIMx_CCR3\nReserved\nCCR3[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x40\nTIMx_CCR4\nReserved\nCCR4[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x44\nTIMx_BDTR\nReserved\nMOE\nAOE\nBKP\nBKE\nOSSR\nOSSI\nLOCK \n[1:0]\nDT[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x48\nTIMx_DCR\nReserved\nDBL[4:0]\nReserved\nDBA[4:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x4C\nTIMx_DMAR\nDMAB[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 97. TIM1 and TIM8 register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 592, "page_indices": { "start_index": 1184139, "end_index": 1185979 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 592 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.1 TIM2 to TIM5 introduction", 592 ], [ 2, "18.2 TIM2 to TIM5 main features", 592 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n592/1757\nRM0090 Rev 21\n18 \nGeneral-purpose timers (TIM2 to TIM5)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n18.1 \nTIM2 to TIM5 introduction\nThe general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a \nprogrammable prescaler.\nThey may be used for a variety of purposes, including measuring the pulse lengths of input \nsignals (input capture) or generating output waveforms (output compare and PWM).\nPulse lengths and waveform periods can be modulated from a few microseconds to several \nmilliseconds using the timer prescaler and the RCC clock controller prescalers.\nThe timers are completely independent, and do not share any resources. They can be \nsynchronized together as described in Section 18.3.15.\n18.2 \nTIM2 to TIM5 main features\nGeneral-purpose TIMx timer features include:\n•\n16-bit (TIM3 and TIM4) or 32-bit (TIM2 and TIM5) up, down, up/down auto-reload \ncounter.\n•\n16-bit programmable prescaler used to divide (also “on the fly”) the counter clock \nfrequency by any factor between 1 and 65536.\n•\nUp to four independent channels for:\n–\nInput capture\n–\nOutput compare\n–\nPWM generation (Edge- and Center-aligned modes)\n–\nOne-pulse mode output\n•\nSynchronization circuit to control the timer with external signals and to interconnect \nseveral timers.\n•\nInterrupt/DMA generation on the following events:\n–\nUpdate: counter overflow/underflow, counter initialization (by software or \ninternal/external trigger)\n–\nTrigger event (counter start, stop, initialization or count by internal/external trigger)\n–\nInput capture\n–\nOutput compare\n•\nSupports incremental (quadrature) encoder and hall-sensor circuitry for positioning \npurposes\n•\nTrigger input for external clock or cycle-by-cycle current management\n" }, { "page_number": 593, "page_indices": { "start_index": 1185979, "end_index": 1187288 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 593 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.2 TIM2 to TIM5 main features", 592 ] ], "page_content": "RM0090 Rev 21\n593/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFigure 134. General-purpose timer block diagram\nU\nU\nU\nCC1I\nCC2I\nTrigger\ncontroller\n+/-\nStop, clear or up/down\nTI1FP1\nTI2FP2\nITR0\nITR1\nITR2\nTRGI\nOutput\ncontrol\nTRGO\nOC1REF\nOC2REF\nU\nUI\nReset, enable, up, count\nCK_PSC\nIC1\nIC2\nIC2PS\nIC1PS\nTI1FP1\nTGI\nTRC\nTRC\nITR\nTRC\nTI1F_ED\nCC1I\nCC2I\nTI1FP2\nTI2FP1\nTI2FP2\nTI1\nTI2\nTIMx_CH1\nTIMx_CH2\nOC1\nOC2\nTIMx_CH2\nTIMx_CH1\nto other timers\nto DAC/ADC\nSlave \ncontroller \nmode\nPSC\nprescaler\nCNT counter\nInternal clock (CK_INT)\nCK_CNT\nTIMxCLK from RCC\nITR3\nMS19673V1\nXOR\nInput filter & \nedge detector\n \nCapture/Compare 1 register\nNotes:\nReg\nPreload registers transferred\nto active registers on U event\naccording to control bit\nEvent\nInterrupt & DMA output\nAuto-reload register\nCapture/Compare 2 register\nPrescaler\nPrescaler\nInput filter & \nedge detector\nOutput\ncontrol\nU\nU\nCC3I\nCC4I\nOutput\ncontrol\nOC3REF\nOC4REF\nIC3\nIC4\nIC4PS\nIC3PS\nTI4FP3\nTI4FP4\nTIMx_CH3\nTIMx_CH4\nOC3\nOC4\nTIMx_CH4\nTIMx_CH3\nInput filter & \nedge detector\n \nCapture/Compare 3 register\nCapture/Compare 4 register\nPrescaler\nPrescaler\nInput filter & \nedge detector\nOutput\ncontrol\nTRC\nTI3FP3\nTI3FP4\nTRC\nCC3I\nCC4I\nTI3\nTI4\nEncoder\ninterface\nTIMx_ETR\nInput filter\nPolarity selection & edge\ndetector & prescaler\nETR\nETRP\nETRF\nETRF\n" }, { "page_number": 594, "page_indices": { "start_index": 1187288, "end_index": 1189291 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 594 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.1 Time-base unit", 594 ], [ 4, "Prescaler description", 594 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n594/1757\nRM0090 Rev 21\n18.3 \nTIM2 to TIM5 functional description\n18.3.1 \nTime-base unit\nThe main block of the programmable timer is a 16-bit/32-bit counter with its related auto-\nreload register. The counter can count up. The counter clock can be divided by a prescaler. \nThe counter, the auto-reload register and the prescaler register can be written or read by \nsoftware. This is true even when the counter is running.\nThe time-base unit includes:\n•\nCounter register (TIMx_CNT)\n•\nPrescaler register (TIMx_PSC):\n•\nAuto-Reload register (TIMx_ARR)\nThe auto-reload register is preloaded. Writing to or reading from the auto-reload register \naccesses the preload register. The content of the preload register are transferred into the \nshadow register permanently or at each update event (UEV), depending on the auto-reload \npreload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter \nreaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the \nTIMx_CR1 register. It can also be generated by software. The generation of the update \nevent is described in detail for each configuration.\nThe counter is clocked by the prescaler output CK_CNT, which is enabled only when the \ncounter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller \ndescription to get more details on counter enabling).\nNote that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN. \nPrescaler description\nThe prescaler can divide the counter clock frequency by any factor between 1 and 65536. It \nis based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC \nregister). It can be changed on the fly as this control register is buffered. The new prescaler \nratio is taken into account at the next update event.\nFigure 135 and Figure 136 give some examples of the counter behavior when the prescaler \nratio is changed on the fly:\n" }, { "page_number": 595, "page_indices": { "start_index": 1189291, "end_index": 1190722 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 595 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.2 Counter modes", 595 ], [ 4, "Upcounting mode", 595 ] ], "page_content": "RM0090 Rev 21\n595/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFigure 135. Counter timing diagram with prescaler division change from 1 to 2\nFigure 136. Counter timing diagram with prescaler division change from 1 to 4\n18.3.2 \nCounter modes\nUpcounting mode\nIn upcounting mode, the counter counts from 0 to the auto-reload value (content of the \nTIMx_ARR register), then restarts from 0 and generates a counter overflow event.\nAn Update event can be generated at each counter overflow or by setting the UG bit in the \nTIMx_EGR register (by software or by using the slave mode controller). \nThe UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. \nThis is to avoid updating the shadow registers while writing new values in the preload \nregisters. Then no update event occurs until the UDIS bit has been written to 0. However, \nthe counter restarts from 0, as well as the counter of the prescaler (but the prescale rate \nMS35833V1\nCK_PSC\n00\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\n0\nPrescaler control register\n1\n0\nWrite a new value in TIMx_PSC\nPrescaler buffer\n1\n0\nPrescaler counter\n0\n1\n0\n1\n0\n1\n0\n1\n01\n02\n03\nFA FB\nF7\nF8\nF9\nFC\nMS35834V1\n0\n3\n0\n0\n1\n2\n3\n0\n1\n2\n3\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nPrescaler control register\nWrite a new value in TIMx_PSC\nPrescaler buffer\nPrescaler counter\n00\n01\nFA FB\nF7\nF8\nF9\nFC\n3\n0\n" }, { "page_number": 596, "page_indices": { "start_index": 1190722, "end_index": 1192052 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 596 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.2 Counter modes", 595 ], [ 4, "Upcounting mode", 595 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n596/1757\nRM0090 Rev 21\ndoes not change). In addition, if the URS bit (update request selection) in TIMx_CR1 \nregister is set, setting the UG bit generates an update event UEV but without setting the UIF \nflag (thus no interrupt or DMA request is sent). This is to avoid generating both update and \ncapture interrupts when clearing the counter on the capture event.\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in \nTIMx_SR register) is set (depending on the URS bit):\n•\nThe buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC \nregister)\n•\nThe auto-reload shadow register is updated with the preload value (TIMx_ARR)\nThe following figures show some examples of the counter behavior for different clock \nfrequencies when TIMx_ARR=0x36.\nFigure 137. Counter timing diagram, internal clock divided by 1\nFigure 138. Counter timing diagram, internal clock divided by 2\n00\n02\n03\n04\n05\n06\n07\n33\n34\n35\n36\n31\nMS35836V1\nCK_INT\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n01\n32\nMS35835V1\nCK_INT\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n0034\n0035\n0036\n0000\n0001\n0002\n0003\n" }, { "page_number": 597, "page_indices": { "start_index": 1192052, "end_index": 1192548 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 597 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.2 Counter modes", 595 ], [ 4, "Upcounting mode", 595 ] ], "page_content": "RM0090 Rev 21\n597/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFigure 139. Counter timing diagram, internal clock divided by 4\nFigure 140. Counter timing diagram, internal clock divided by N\n0000\n0001\n0035\n0036\nMSv37301V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\nCNT_EN\nMSv37302V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n1F\n20\n" }, { "page_number": 598, "page_indices": { "start_index": 1192548, "end_index": 1193854 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 598 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.2 Counter modes", 595 ], [ 4, "Downcounting mode", 598 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n598/1757\nRM0090 Rev 21\nFigure 141. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not \npreloaded)\nFigure 142. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR \npreloaded)\nDowncounting mode\nIn downcounting mode, the counter counts from the auto-reload value (content of the \nTIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a \ncounter underflow event.\nAn Update event can be generate at each counter underflow or by setting the UG bit in the \nTIMx_EGR register (by software or by using the slave mode controller) \nThe UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 \nregister. This is to avoid updating the shadow registers while writing new values in the \nFF\n36\nMSv37303V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n02 03\n04 05 06 07\n32\n33 34 35 36\n31\n01\nCNT_EN\nAuto-reload register\nWrite a new value in TIMx_ARR\nMSv37304V1\nF5\n36\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n02 03 04\n05 06\n07\nF1 F2 F3 F4 F5\nF0\n01\nCNT_EN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\nAuto-reload shadow register\nF5\n36\n" }, { "page_number": 599, "page_indices": { "start_index": 1193854, "end_index": 1195350 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 599 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.2 Counter modes", 595 ], [ 4, "Downcounting mode", 598 ] ], "page_content": "RM0090 Rev 21\n599/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\npreload registers. Then no update event occurs until UDIS bit has been written to 0. \nHowever, the counter restarts from the current auto-reload value, whereas the counter of the \nprescaler restarts from 0 (but the prescale rate does not change). \nIn addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the \nUG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or \nDMA request is sent). This is to avoid generating both update and capture interrupts when \nclearing the counter on the capture event.\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in \nTIMx_SR register) is set (depending on the URS bit):\n•\nThe buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC \nregister).\n•\nThe auto-reload active register is updated with the preload value (content of the \nTIMx_ARR register). Note that the auto-reload is updated before the counter is \nreloaded, so that the next period is the expected one.\nThe following figures show some examples of the counter behavior for different clock \nfrequencies when TIMx_ARR=0x36.\nFigure 143. Counter timing diagram, internal clock divided by 1\n36\n34\n33\n32\n31\n30\n2F\n04\n03 02\n01\n00\n05\nMSv37305V1\nCK_INT\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow (cnt_udf) \nUpdate interrupt flag (UIF)\n35\n" }, { "page_number": 600, "page_indices": { "start_index": 1195350, "end_index": 1196070 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 600 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.2 Counter modes", 595 ], [ 4, "Downcounting mode", 598 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n600/1757\nRM0090 Rev 21\nFigure 144. Counter timing diagram, internal clock divided by 2\nFigure 145. Counter timing diagram, internal clock divided by 4\nFigure 146. Counter timing diagram, internal clock divided by N\nMSv37306V1\nCK_INT\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow\nUpdate interrupt flag (UIF)\n0002\n0001\n0000\n0036\n0035\n0034\n0033\nMS40511V1\n0036\n0035\n0001\n0000\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow\nUpdate interrupt flag (UIF)\nCNT_EN\nMS37340V1\n00\n1F\n20\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n36\n" }, { "page_number": 601, "page_indices": { "start_index": 1196070, "end_index": 1198282 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 601 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.2 Counter modes", 595 ], [ 4, "Center-aligned mode (up/down counting)", 601 ] ], "page_content": "RM0090 Rev 21\n601/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFigure 147. Counter timing diagram, Update event\nCenter-aligned mode (up/down counting)\nIn center-aligned mode, the counter counts from 0 to the auto-reload value (content of the \nTIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-\nreload value down to 1 and generates a counter underflow event. Then it restarts counting \nfrom 0.\nCenter-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to \n'00'. The Output compare interrupt flag of channels configured in output is set when: the \ncounter counts down (Center aligned mode 1, CMS = \"01\"), the counter counts up (Center \naligned mode 2, CMS = \"10\") the counter counts up and down (Center aligned mode 3, \nCMS = \"11\").\nIn this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated \nby hardware and gives the current direction of the counter.\nThe update event can be generated at each counter overflow and at each counter underflow \nor by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode \ncontroller) also generates an update event. In this case, the counter restarts counting from \n0, as well as the counter of the prescaler.\nThe UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 \nregister. This is to avoid updating the shadow registers while writing new values in the \npreload registers. Then no update event occurs until the UDIS bit has been written to 0. \nHowever, the counter continues counting up and down, based on the current auto-reload \nvalue.\nIn addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the \nUG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or \nDMA request is sent). This is to avoid generating both update and capture interrupt when \nclearing the counter on the capture event.\nMS37341V1\nFF\n36\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n01\nCNT_EN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\n00\n36\n05\n04\n03\n02\n35 34\n33\n32\n31 30\n2F\n" }, { "page_number": 602, "page_indices": { "start_index": 1198282, "end_index": 1199632 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 602 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.2 Counter modes", 595 ], [ 4, "Center-aligned mode (up/down counting)", 601 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n602/1757\nRM0090 Rev 21\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in \nTIMx_SR register) is set (depending on the URS bit):\n•\nThe buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC \nregister).\n•\nThe auto-reload active register is updated with the preload value (content of the \nTIMx_ARR register). Note that if the update source is a counter overflow, the auto-\nreload is updated before the counter is reloaded, so that the next period is the expected \none (the counter is loaded with the new value).\nThe following figures show some examples of the counter behavior for different clock \nfrequencies.\nFigure 148. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6\n1.\nHere, center-aligned mode 1 is used, for more details refer to Section 18.4.1: TIMx control register 1 (TIMx_CR1).\nFigure 149. Counter timing diagram, internal clock divided by 2\nMS37342V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\nCNT_EN\nCounter underflow\n00\n02\n03\n04\n05 06\n01\n02 03 04\n01\n05\n03\n04\nMS37343V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nCNT_EN\nCounter underflow\n0003\n0002\n0001\n0000\n0001\n0002\n0003\n" }, { "page_number": 603, "page_indices": { "start_index": 1199632, "end_index": 1200218 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 603 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.2 Counter modes", 595 ], [ 4, "Center-aligned mode (up/down counting)", 601 ] ], "page_content": "RM0090 Rev 21\n603/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFigure 150. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36\n1.\nCenter-aligned mode 2 or 3 is used with an UIF on overflow.\nFigure 151. Counter timing diagram, internal clock divided by N\nMS37344V1\n0034\n0035\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow (cnt_ovf)\nUpdate interrupt flag (UIF)\nCNT_EN\n0036\n0035\nMS37345V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nCounter underflow\n00\n1F\n20\n01\n" }, { "page_number": 604, "page_indices": { "start_index": 1200218, "end_index": 1201003 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 604 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.2 Counter modes", 595 ], [ 4, "Center-aligned mode (up/down counting)", 601 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n604/1757\nRM0090 Rev 21\nFigure 152. Counter timing diagram, Update event with ARPE=1 (counter underflow)\nFigure 153. Counter timing diagram, Update event with ARPE=1 (counter overflow)\nMS37360V1\nFD\n36\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter underflow\nUpdate interrupt flag (UIF)\n00\n02 03 04 05 06\n07\n01\nCNT_EN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\n06\n05\n04 03 02 01\nFD\n36\nAuto-reload active register\nMS37361V1\nFD\n36\nCK_INT\nTimer clock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n36\n34 33 32\n31 30 2F\nF8\nF9 FA FB FC\nF7\n35\nCNT_EN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\nAuto-reload active register\nFD\n36\n" }, { "page_number": 605, "page_indices": { "start_index": 1201003, "end_index": 1202472 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 605 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.3 Clock selection", 605 ], [ 4, "Internal clock source (CK_INT)", 605 ], [ 4, "External clock source mode 1", 605 ] ], "page_content": "RM0090 Rev 21\n605/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n18.3.3 \nClock selection\nThe counter clock can be provided by the following clock sources:\n•\nInternal clock (CK_INT)\n•\nExternal clock mode1: external input pin (TIx)\n•\nExternal clock mode2: external trigger input (ETR) available on TIM2, TIM3 and TIM4 \nonly.\n•\nInternal trigger inputs (ITRx): using one timer as prescaler for another timer, for \nexample, Timer3 can be configured to act as a prescaler for Timer 2. Refer to Using \none timer as prescaler for another timer for more details.\nInternal clock source (CK_INT)\nIf the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the \nCEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual \ncontrol bits and can be changed only by software (except UG which remains cleared \nautomatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal \nclock CK_INT.\nFigure 154 shows the behavior of the control circuit and the upcounter in normal mode, \nwithout prescaler.\nFigure 154. Control circuit in normal mode, internal clock divided by 1\nExternal clock source mode 1\nThis mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at \neach rising or falling edge on a selected input.\nInternal clock\nCounter clock = CK_CNT = CK_PSC\nCounter register\nCEN=CNT_EN\nUG\nCNT_INIT\nMS31085V2\n00\n02\n03\n04\n05\n06\n07\n3 2\n33\n34\n35 36\n31\n01\n" }, { "page_number": 606, "page_indices": { "start_index": 1202472, "end_index": 1203962 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 606 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.3 Clock selection", 605 ], [ 4, "External clock source mode 1", 605 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n606/1757\nRM0090 Rev 21\nFigure 155. TI2 external clock connection example\nFor example, to configure the upcounter to count in response to a rising edge on the TI2 \ninput, use the following procedure:\n1.\nConfigure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the \nTIMx_CCMR1 register.\n2. \nConfigure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 \nregister (if no filter is needed, keep IC2F=0000).\nNote:\nThe capture prescaler is not used for triggering, so there’s no need to configure it.\n3. \nSelect rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER \nregister.\n4. \nConfigure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR \nregister. \n5. \nSelect TI2 as the input source by writing TS=110 in the TIMx_SMCR register.\n6. \nEnable the counter by writing CEN=1 in the TIMx_CR1 register.\nWhen a rising edge occurs on TI2, the counter counts once and the TIF flag is set.\nThe delay between the rising edge on TI2 and the actual clock of the counter is due to the \nresynchronization circuit on TI2 input.\nExternal clock\nmode 1 \nInternal clock\nmode\nTRGI\nCK_INT\nCK_PSC\nTIMx_SMCR\nSMS[2:0]\nITRx\nTI1_ED\nTI1FP1\nTI2FP2\nTIMx_SMCR\nTS[2:0]\nTI2\n0\n1\nTIMx_CCER\nCC2P\nFilter\nICF[3:0]\nTIMx_CCMR1\nEdge\ndetector\nTI2F_Rising\nTI2F_Falling\n110\n0xx\n100\n101\nMS31196V1\n(internal clock)\nTI1F\nor\nTI2F\nor\nor\nEncoder\nmode \nETRF\n111\nExternal clock\nmode 2 \nETRF\nECE\n" }, { "page_number": 607, "page_indices": { "start_index": 1203962, "end_index": 1205346 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 607 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.3 Clock selection", 605 ], [ 4, "External clock source mode 2", 607 ] ], "page_content": "RM0090 Rev 21\n607/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFigure 156. Control circuit in external clock mode 1\nExternal clock source mode 2\nThis mode is selected by writing ECE=1 in the TIMx_SMCR register.\nThe counter can count at each rising or falling edge on the external trigger input ETR.\nFigure 157 gives an overview of the external trigger input block.\nFigure 157. External trigger input block\nFor example, to configure the upcounter to count each 2 rising edges on ETR, use the \nfollowing procedure:\n1.\nAs no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.\n2. \nSet the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register \n3. \nSelect rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR \nregister\n4. \nEnable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.\n5. \nEnable the counter by writing CEN=1 in the TIMx_CR1 register.\nThe counter counts once each 2 ETR rising edges.\nCounter clock = CK_CNT = CK_PSC\nCounter register\n35\n36\n34\nTI2\nCNT_EN\nTIF\nWrite TIF=0\nMS31087V2\nMS37365V1\nTRGI\nCK_INT\nTIMx_SMCR\nSMS[2:0]\n(internal clock)\nTI1F\nor\nTI2F\nor\nor\nEncoder\nmode \nETRF\nECE\n0\n1\nTIMx_SMCR\nETP\nETR pin\nETR\nDivider\n/1, /2, /4, /8\nFilter\ndowncounter\nCK_INT\nETRP\nTIMx_SMCR\nETPS[1:0]\nTIMx_SMCR\nETF[3:0]\nExternal clock \nmode 1\nExternal clock \nmode 2\nInternal clock \nmode\nCK_PSC\n" }, { "page_number": 608, "page_indices": { "start_index": 1205346, "end_index": 1206887 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 608 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.4 Capture/compare channels", 608 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n608/1757\nRM0090 Rev 21\nThe delay between the rising edge on ETR and the actual clock of the counter is due to the \nresynchronization circuit on the ETRP signal.\nFigure 158. Control circuit in external clock mode 2\n18.3.4 \nCapture/compare channels\nEach Capture/Compare channel (see Figure 159) is built around a capture/compare register \n(including a shadow register), an input stage for capture (with digital filter, multiplexing and \nprescaler) and an output stage (with comparator and output control).\nThe input stage samples the corresponding TIx input to generate a filtered signal TIxF. \nThen, an edge detector with polarity selection generates a signal (TIxFPx) which can be \nused as trigger input by the slave mode controller or as the capture command. It is \nprescaled before the capture register (ICxPS).\nFigure 159. Capture/compare channel (example: channel 1 input stage)\nThe output stage generates an intermediate waveform which is then used for reference: \nOCxRef (active high). The polarity acts at the end of the chain.\nMS37362V1\n34\n35\n36\nCNT_EN\nETR\nETRP\nETRF\nCounter clock = CK_INT =CK_PSC\nCounter register\nCK_INT\nTI1\nTIMx_CCER\nCC1P/CC1NP\ndivider\n/1, /2, /4, /8\nICPS[1:0]\nTI1F_ED\nfilter\nICF[3:0]\ndowncounter\nTIMx_CCMR1\nEdge\nDetector\nTI1F_Rising\nTI1F_Falling\nto the slave mode controller\nTI1FP1\n11\n01\nTIMx_CCMR1\nCC1S[1:0]\nIC1\nTI2FP1\nTRC\n(from channel 2)\n(from slave mode\ncontroller)\n10\nfDTS\nTIMx_CCER\nCC1E\nIC1PS\nTI1F\nTI2F_rising\nTI2F_falling\n(from channel 2)\n" }, { "page_number": 609, "page_indices": { "start_index": 1206887, "end_index": 1208097 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 609 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.4 Capture/compare channels", 608 ] ], "page_content": "RM0090 Rev 21\n609/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFigure 160. Capture/compare channel 1 main circuit\nFigure 161. Output stage of capture/compare channel (channel 1)\nThe capture/compare block is made of one preload register and one shadow register. Write \nand read always access the preload register. \nIn capture mode, captures are actually done in the shadow register, which is copied into the \npreload register. \nIn compare mode, the content of the preload register is copied into the shadow register \nwhich is compared to the counter.\nCC1E\nCapture/compare shadow register\nComparator\nCapture/compare preload register\nCounter\nIC1PS\nCC1S[0]\nCC1S[1]\nCapture\nInput \nmode\nS\nR\nRead CCR1H\nRead CCR1L\nread_in_progress\ncapture_transfer\nCC1S[0]\nCC1S[1]\nS\nR\nwrite CCR1H\nwrite CCR1L\nwrite_in_progress\nOutput \nmode\nUEV\nOC1PE\n(from time\nbase unit)\ncompare_transfer\nAPB Bus\n8\n8\nhigh\nlow\n(if 16-bit)\nMCU-peripheral interface\nTIMx_CCMR1\nOC1PE\nCNT>CCR1\nCNT=CCR1\nTIMx_EGR\nCC1G\nMS33144V1\nOutput mode\nTIMx_CNT > TIMx_CCR1\ncontroller\nTIMx_CCMR1\nOC1M[2:0]\noc1ref\n0\n1\nTIMx_CCER\nOutput\nEnable\nCircuit\nOC1\nTIMx_CCER\nTo the master mode\ncontroller\nETRF\nai17187b\nCC1P\nCC1E\nTIMx_CNT = TIMx_CCR1\n" }, { "page_number": 610, "page_indices": { "start_index": 1208097, "end_index": 1211114 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 610 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.5 Input capture mode", 610 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n610/1757\nRM0090 Rev 21\n18.3.5 \nInput capture mode\nIn Input capture mode, the Capture/Compare registers (TIMx_CCRx) are used to latch the \nvalue of the counter after a transition detected by the corresponding ICx signal. When a \ncapture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or \na DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was \nalready high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be \ncleared by software by writing it to 0 or by reading the captured data stored in the \nTIMx_CCRx register. CCxOF is cleared when written to 0.\nThe following example shows how to capture the counter value in TIMx_CCR1 when TI1 \ninput rises. To do this, use the following procedure:\n•\nSelect the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S \nbits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, \nthe channel is configured in input and the TIMx_CCR1 register becomes read-only.\n•\nProgram the needed input filter duration with respect to the signal connected to the \ntimer (by programming the ICxF bits in the TIMx_CCMRx register if the input is one of \nthe TIx inputs). Let’s imagine that, when toggling, the input signal is not stable during at \nmust five internal clock cycles. We must program a filter duration longer than these five \nclock cycles. We can validate a transition on TI1 when eight consecutive samples with \nthe new level have been detected (sampled at fDTS frequency). Then write IC1F bits to \n0011 in the TIMx_CCMR1 register.\n•\nSelect the edge of the active transition on the TI1 channel by writing the CC1P and \nCC1NP bits to 00 in the TIMx_CCER register (rising edge in this case).\n•\nProgram the input prescaler. In our example, we wish the capture to be performed at \neach valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the \nTIMx_CCMR1 register).\n•\nEnable capture from the counter into the capture register by setting the CC1E bit in the \nTIMx_CCER register.\n•\nIf needed, enable the related interrupt request by setting the CC1IE bit in the \nTIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the \nTIMx_DIER register.\nWhen an input capture occurs:\n•\nThe TIMx_CCR1 register gets the value of the counter on the active transition.\n•\nCC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures \noccurred whereas the flag was not cleared.\n•\nAn interrupt is generated depending on the CC1IE bit.\n•\nA DMA request is generated depending on the CC1DE bit.\nIn order to handle the overcapture, it is recommended to read the data before the \novercapture flag. This is to avoid missing an overcapture which could happen after reading \nthe flag and before reading the data.\nNote:\nIC interrupt and/or DMA requests can be generated by software by setting the \ncorresponding CCxG bit in the TIMx_EGR register.\n" }, { "page_number": 611, "page_indices": { "start_index": 1211114, "end_index": 1212848 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 611 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.6 PWM input mode", 611 ] ], "page_content": "RM0090 Rev 21\n611/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n18.3.6 \nPWM input mode\nThis mode is a particular case of input capture mode. The procedure is the same except:\n•\nTwo ICx signals are mapped on the same TIx input.\n•\nThese 2 ICx signals are active on edges with opposite polarity.\n•\nOne of the two TIxFP signals is selected as trigger input and the slave mode controller \nis configured in reset mode.\nFor example, the user can measure the period (in TIMx_CCR1 register) and the duty cycle \n(in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure \n(depending on CK_INT frequency and prescaler value):\n•\nSelect the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 \nregister (TI1 selected).\n•\nSelect the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter \nclear): write the CC1P to ‘0’ and the CC1NP bit to ‘0’ (active on rising edge).\n•\nSelect the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 \nregister (TI1 selected).\n•\nSelect the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P \nbit to ‘1’ and the CC2NP bit to ’0’(active on falling edge).\n•\nSelect the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register \n(TI1FP1 selected).\n•\nConfigure the slave mode controller in reset mode: write the SMS bits to 100 in the \nTIMx_SMCR register.\n•\nEnable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register.\nFigure 162. PWM input mode timing\nTI1\nTIMx_CNT\n0000\n0001\n0002\n0003\n0004\n0000\n0004\nTIMx_CCR1\nTIMx_CCR2\n0004\n0002\nIC1 capture\nIC2 capture\nreset counter\nIC2 capture\npu\nl se wid th\n \nIC1 capture\nperiod\nmeasurement\nmeasurement\nai15413\n" }, { "page_number": 612, "page_indices": { "start_index": 1212848, "end_index": 1215661 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 612 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.7 Forced output mode", 612 ], [ 3, "18.3.8 Output compare mode", 612 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n612/1757\nRM0090 Rev 21\n18.3.7 \nForced output mode\nIn output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal \n(OCxREF and then OCx) can be forced to active or inactive level directly by software, \nindependently of any comparison between the output compare register and the counter.\nTo force an output compare signal (ocxref/OCx) to its active level, the user just needs to \nwrite 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is \nforced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity \nbit.\ne.g.: CCxP=0 (OCx active high) => OCx is forced to high level.\nocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx \nregister.\nAnyway, the comparison between the TIMx_CCRx shadow register and the counter is still \nperformed and allows the flag to be set. Interrupt and DMA requests can be sent \naccordingly. This is described in the next section.\n18.3.8 \nOutput compare mode\nThis function is used to control an output waveform or indicating when a period of time has \nelapsed.\nWhen a match is found between the capture/compare register and the counter, the output \ncompare function: \n•\nAssigns the corresponding output pin to a programmable value defined by the output \ncompare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP \nbit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set \nactive (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.\n•\nSets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).\n•\nGenerates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the \nTIMx_DIER register).\n•\nSends a DMA request if the corresponding enable bit is set (CCxDE bit in the \nTIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request \nselection).\nThe TIMx_CCRx registers can be programmed with or without preload registers using the \nOCxPE bit in the TIMx_CCMRx register.\nIn output compare mode, the update event UEV has no effect on ocxref and OCx output. \nThe timing resolution is one count of the counter. Output compare mode can also be used to \noutput a single pulse (in One-pulse mode).\nProcedure:\n1.\nSelect the counter clock (internal, external, prescaler).\n2. \nWrite the desired data in the TIMx_ARR and TIMx_CCRx registers.\n3. \nSet the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be \ngenerated.\n4. \nSelect the output mode. For example, the user must write OCxM=011, OCxPE=0, \nCCxP=0 and CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx \npreload is not used, OCx is enabled and active high.\n5. \nEnable the counter by setting the CEN bit in the TIMx_CR1 register.\n" }, { "page_number": 613, "page_indices": { "start_index": 1215661, "end_index": 1217948 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 613 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.9 PWM mode", 613 ] ], "page_content": "RM0090 Rev 21\n613/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nThe TIMx_CCRx register can be updated at any time by software to control the output \nwaveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx \nshadow register is updated only at the next update event UEV). An example is given in \nFigure 163.\nFigure 163. Output compare mode, toggle on OC1\n18.3.9 \nPWM mode\nPulse width modulation mode allows generating a signal with a frequency determined by the \nvalue of the TIMx_ARR register and a duty cycle determined by the value of the \nTIMx_CCRx register.\nThe PWM mode can be selected independently on each channel (one PWM per OCx \noutput) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the \nTIMx_CCMRx register. The user must enable the corresponding preload register by setting \nthe OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register \nby setting the ARPE bit in the TIMx_CR1 register.\nAs the preload registers are transferred to the shadow registers only when an update event \noccurs, before starting the counter, the user has to initialize all the registers by setting the \nUG bit in the TIMx_EGR register.\nOCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It \ncan be programmed as active high or active low. OCx output is enabled by the CCxE bit in \nthe TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.\nIn PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine \nwhether TIMx_CCRx≤TIMx_CNT or TIMx_CNT≤TIMx_CCRx (depending on the direction of \nthe counter). However, to comply with the ETRF (OCREF can be cleared by an external \nevent through the ETR signal until the next PWM period), the OCREF signal is asserted \nonly:\n•\nWhen the result of the comparison changes, or\n•\nWhen the output compare mode (OCxM bits in TIMx_CCMRx register) switches from \nthe “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes \n(OCxM=‘110 or ‘111).\nThis forces the PWM by software while the timer is running.\nMS37363V1\nOC1REF = OC1\nTIMx_CNT\nB200\nB201\n0039\nTIMx_CCR1\n003A\nWrite B201h in the CC1R register\nMatch detected on CCR1\nInterrupt generated if enabled\n003B\nB201\n003A\n" }, { "page_number": 614, "page_indices": { "start_index": 1217948, "end_index": 1219565 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 614 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.9 PWM mode", 613 ], [ 4, "PWM edge-aligned mode", 614 ], [ 4, "Upcounting configuration", 614 ], [ 4, "Downcounting configuration", 614 ], [ 4, "PWM center-aligned mode", 614 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n614/1757\nRM0090 Rev 21\nThe timer is able to generate PWM in edge-aligned mode or center-aligned mode \ndepending on the CMS bits in the TIMx_CR1 register.\nPWM edge-aligned mode\nUpcounting configuration\nUpcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting \nmode.\nIn the following example, we consider PWM mode 1. The reference PWM signal OCxREF is \nhigh as long as TIMx_CNT TIMx_CCRx else \nit becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in \nTIMx_ARR, then ocxref is held at ‘1. 0% PWM is not possible in this mode.\nPWM center-aligned mode\nCenter-aligned mode is active when the CMS bits in TIMx_CR1 register are different from \n‘00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The \ncompare flag is set when the counter counts up, when it counts down or both when it counts \nMS31093V1\nCounter register\n‘1’\n0\n1\n2\n3\n4\n5\n6\n7\n8\n0\n1\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nCCRx=4\nCCRx=8\nCCRx>8\nCCRx=0\n‘0’\n" }, { "page_number": 615, "page_indices": { "start_index": 1219565, "end_index": 1220662 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 615 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.9 PWM mode", 613 ], [ 4, "PWM center-aligned mode", 614 ] ], "page_content": "RM0090 Rev 21\n615/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nup and down depending on the CMS bits configuration. The direction bit (DIR) in the \nTIMx_CR1 register is updated by hardware and must not be changed by software. Refer to \nCenter-aligned mode (up/down counting).\nFigure 165 shows some center-aligned PWM waveforms in an example where:\n•\nTIMx_ARR=8,\n•\nPWM mode is the PWM mode 1,\n•\nThe flag is set when the counter counts down corresponding to the center-aligned \nmode 1 selected for CMS=01 in TIMx_CR1 register.\nFigure 165. Center-aligned PWM waveforms (ARR=8)\nHints on using center-aligned mode:\n•\nWhen starting in center-aligned mode, the current up-down configuration is used. It \nmeans that the counter counts up or down depending on the value written in the DIR bit \nCCxIF\n0\n1\n2\n3\n4\n5\n6\n7\n8\n7\n6\n5\n4\n3\n2\n1\n0\n1\nCounter register\nCCRx = 4\nOCxREF\nCMS=01\nCMS=10\nCMS=11\nCCxIF\nCCRx = 7\nOCxREF\nCMS=10 or 11\nCCxIF\nCCRx = 8\nOCxREF\nCMS=01\nCMS=10\nCMS=11\n'1'\nCCxIF\nCCRx > 8\nOCxREF\nCMS=01\nCMS=10\nCMS=11\n'1'\nCCxIF\nCCRx = 0\nOCxREF\nCMS=01\nCMS=10\nCMS=11\n'0'\nai14681b\n" }, { "page_number": 616, "page_indices": { "start_index": 1220662, "end_index": 1222643 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 616 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.10 One-pulse mode", 616 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n616/1757\nRM0090 Rev 21\nin the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the \nsame time by the software.\n•\nWriting to the counter while running in center-aligned mode is not recommended as it \ncan lead to unexpected results. In particular:\n–\nThe direction is not updated if the user writes a value in the counter that is greater \nthan the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter \nwas counting up, it continues to count up.\n–\nThe direction is updated if the user writes 0 or write the TIMx_ARR value in the \ncounter but no Update Event UEV is generated.\n•\nThe safest way to use center-aligned mode is to generate an update by software \n(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to \nwrite the counter while it is running.\n18.3.10 \nOne-pulse mode\nOne-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to \nbe started in response to a stimulus and to generate a pulse with a programmable length \nafter a programmable delay.\nStarting the counter can be controlled through the slave mode controller. Generating the \nwaveform can be done in output compare mode or PWM mode. Select One-pulse mode by \nsetting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at \nthe next update event UEV.\nA pulse can be correctly generated only if the compare value is different from the counter \ninitial value. Before starting (when the timer is waiting for the trigger), the configuration must \nbe:\n•\nIn upcounting: CNTCCRx.\nFigure 166. Example of one-pulse mode\nFor example the user may want to generate a positive pulse on OC1 with a length of tPULSE \nand after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.\nMS31099V1\nTI2\nOC1REF\nCounter\nt\n0\nTIM1_ARR\nTIM1_CCR1\nOC1\ntDELAY\ntPULSE\n" }, { "page_number": 617, "page_indices": { "start_index": 1222643, "end_index": 1225710 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 617 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.10 One-pulse mode", 616 ], [ 4, "Particular case: OCx fast enable:", 617 ], [ 3, "18.3.11 Clearing the OCxREF signal on an external event", 617 ] ], "page_content": "RM0090 Rev 21\n617/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nLet’s use TI2FP2 as trigger 1:\n•\nMap TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register.\n•\nTI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER \nregister.\n•\nConfigure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in \nthe TIMx_SMCR register.\n•\nTI2FP2 is used to start the counter by writing SMS to ‘110 in the TIMx_SMCR register \n(trigger mode).\nThe OPM waveform is defined by writing the compare registers (taking into account the \nclock frequency and the counter prescaler).\n•\nThe tDELAY is defined by the value written in the TIMx_CCR1 register.\n•\nThe tPULSE is defined by the difference between the auto-reload value and the compare \nvalue (TIMx_ARR - TIMx_CCR + 1).\n•\nLet us say user wants to build a waveform with a transition from ‘0 to ‘1 when a \ncompare match occurs and a transition from ‘1 to ‘0 when the counter reaches the \nauto-reload value. To do this enable PWM mode 2 by writing OC1M=111 in the \nTIMx_CCMR1 register. The user can optionally enable the preload registers by writing \nOC1PE=1 in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this \ncase write the compare value in the TIMx_CCR1 register, the auto-reload value in the \nTIMx_ARR register, generate an update by setting the UG bit and wait for external \ntrigger event on TI2. CC1P is written to ‘0 in this example.\nIn our example, the DIR and CMS bits in the TIMx_CR1 register should be low.\nUser only wants one pulse (Single mode), so write '1 in the OPM bit in the TIMx_CR1 \nregister to stop the counter at the next update event (when the counter rolls over from the \nauto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the \nRepetitive mode is selected.\nParticular case: OCx fast enable:\nIn One-pulse mode, the edge detection on TIx input set the CEN bit which enables the \ncounter. Then the comparison between the counter and the compare value makes the \noutput toggle. But several clock cycles are needed for these operations and it limits the \nminimum delay tDELAY min we can get.\nTo output a waveform with the minimum delay, the user can set the OCxFE bit in the \nTIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus, \nwithout taking in account the comparison. Its new level is the same as if a compare match \nhad occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.\n18.3.11 \nClearing the OCxREF signal on an external event\nThe OCxREF signal for a given channel can be driven Low by applying a High level to the \nETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to '1'). The \nOCxREF signal remains Low until the next update event, UEV, occurs. \nThis function can only be used in output compare and PWM modes, and does not work in \nforced mode. \nFor example, the ETR signal can be connected to the output of a comparator to be used for \ncurrent handling. In this case, ETR must be configured as follows:\n" }, { "page_number": 618, "page_indices": { "start_index": 1225710, "end_index": 1228196 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 618 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.12 Encoder interface mode", 618 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n618/1757\nRM0090 Rev 21\n1.\nThe external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR \nregister are cleared to 00.\n2. \nThe external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is \ncleared to 0.\n3. \nThe external trigger polarity (ETP) and the external trigger filter (ETF) can be \nconfigured according to the application’s needs.\nFigure 167 shows the behavior of the OCxREF signal when the ETRF input becomes high, \nfor both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in \nPWM mode.\nFigure 167. Clearing TIMx OCxREF\n1.\nIn case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the next counter \noverflow.\n18.3.12 \nEncoder interface mode\nTo select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter \nis counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if \nit is counting on both TI1 and TI2 edges.\nSelect the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER \nregister. When needed, program the input filter as well.\nThe two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to \nTable 98. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 \nafter input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted, \nTI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in \nTIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated \nand generates count pulses as well as the direction signal. Depending on the sequence the \ncounter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware \naccordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever \nthe counter is counting on TI1 only, TI2 only or both TI1 and TI2.\nEncoder interface mode acts simply as an external clock with direction selection. This \nmeans that the counter just counts continuously between 0 and the auto-reload value in the \nTIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So the user \nmust configure TIMx_ARR before starting. In the same way, the capture, compare, \nprescaler, trigger output features continue to work as normal. \nMS37368V1\n(CCRx)\nCounter (CNT)\nETRF\nOCxREF (OCxCE = ‘0’)\nOCxREF (OCxCE = ‘1’)\nETRF becomes high\nETRF still high\n" }, { "page_number": 619, "page_indices": { "start_index": 1228196, "end_index": 1230266 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 619 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.12 Encoder interface mode", 618 ] ], "page_content": "RM0090 Rev 21\n619/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nIn this mode, the counter is modified automatically following the speed and the direction of \nthe incremental encoder and its content, therefore, always represents the encoder’s \nposition. The count direction correspond to the rotation direction of the connected sensor. \nThe table summarizes the possible combinations, assuming TI1 and TI2 do not switch at the \nsame time.\n \nAn external incremental encoder can be connected directly to the MCU without external \ninterface logic. However, comparators are normally be used to convert the encoder’s \ndifferential outputs to digital signals. This greatly increases noise immunity. The third \nencoder output which indicate the mechanical zero position, may be connected to an \nexternal interrupt input and trigger a counter reset.\nFigure 168 gives an example of counter operation, showing count signal generation and \ndirection control. It also shows how input jitter is compensated where both edges are \nselected. This might occur if the sensor is positioned near to one of the switching points. For \nthis example we assume that the configuration is the following:\n•\nCC1S= ‘01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1)\n•\nCC2S= ‘01’ (TIMx_CCMR1 register, TI2FP2 mapped on TI2)\n•\nCC1P= ‘0’, CC1NP = ‘0’, IC1F =’0000’ (TIMx_CCER register, TI1FP1 noninverted, \nTI1FP1=TI1)\n•\nCC2P= ‘0’, CC2NP = ‘0’, IC2F =’0000’ (TIMx_CCER register, TI2FP2 noninverted, \nTI2FP2=TI2)\n•\nSMS= ‘011’ (TIMx_SMCR register, both inputs are active on both rising and falling \nedges)\n•\nCEN = 1 (TIMx_CR1 register, Counter is enabled)\nTable 98. Counting direction versus encoder signals\nActive edge\nLevel on opposite \nsignal (TI1FP1 for \nTI2, TI2FP2 for TI1)\nTI1FP1 signal\nTI2FP2 signal\nRising\nFalling\nRising\nFalling\nCounting on \nTI1 only\nHigh\nDown\nUp\nNo Count\nNo Count\nLow\nUp\nDown\nNo Count\nNo Count\nCounting on \nTI2 only\nHigh\nNo Count\nNo Count\nUp\nDown\nLow\nNo Count\nNo Count\nDown\nUp\nCounting on \nTI1 and TI2\nHigh\nDown\nUp\nUp\nDown\nLow\nUp\nDown\nDown\nUp\n" }, { "page_number": 620, "page_indices": { "start_index": 1230266, "end_index": 1231545 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 620 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.12 Encoder interface mode", 618 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n620/1757\nRM0090 Rev 21\nFigure 168. Example of counter operation in encoder interface mode \nFigure 169 gives an example of counter behavior when TI1FP1 polarity is inverted (same \nconfiguration as above except CC1P=1).\nFigure 169. Example of encoder interface mode with TI1FP1 polarity inverted \nThe timer, when configured in Encoder Interface mode provides information on the sensor’s \ncurrent position. The user can obtain dynamic information (speed, acceleration, \ndeceleration) by measuring the period between two encoder events using a second timer \nconfigured in capture mode. The output of the encoder which indicates the mechanical zero \ncan be used for this purpose. Depending on the time between two events, the counter can \nalso be read at regular times. The user can do this by latching the counter value into a third \ninput capture register if available (then the capture signal must be periodic and can be \ngenerated by another timer). when available, it is also possible to read its value through a \nDMA request generated by a Real-Time clock.\nTI1\nbackward\njitter\njitter\nup\ndown\nup\nTI2\nCounter\nforward\nforward\nMS33107V1\nTI1\nbackward\njitter\njitter\nup\ndown\nTI2\nCounter\nforward\nforward\nMS33108V1\ndown\n" }, { "page_number": 621, "page_indices": { "start_index": 1231545, "end_index": 1233876 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 621 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.13 Timer input XOR function", 621 ], [ 3, "18.3.14 Timers and external trigger synchronization", 621 ], [ 4, "Slave mode: Reset mode", 621 ] ], "page_content": "RM0090 Rev 21\n621/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n18.3.13 \nTimer input XOR function\nThe TI1S bit in the TIM_CR2 register, allows the input filter of channel 1 to be connected to \nthe output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3.\nThe XOR output can be used with all the timer input functions such as trigger or input \ncapture.\n18.3.14 \nTimers and external trigger synchronization\nThe TIMx Timers can be synchronized with an external trigger in several modes: Reset \nmode, Gated mode and Trigger mode.\nSlave mode: Reset mode\nThe counter and its prescaler can be reinitialized in response to an event on a trigger input. \nMoreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is \ngenerated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.\nIn the following example, the upcounter is cleared in response to a rising edge on TI1 input:\n•\nConfigure the channel 1 to detect rising edges on TI1. Configure the input filter duration \n(in this example, no need of any filter, IC1F=0000 kept). The capture prescaler is not \nused for triggering, so the user does not need to configure it. The CC1S bits select the \ninput capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=0 and \nCC1NP=0 in TIMx_CCER register to validate the polarity (and detect rising edges \nonly).\n•\nConfigure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select \nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\n•\nStart the counter by writing CEN=1 in the TIMx_CR1 register.\nThe counter starts counting on the internal clock, then behaves normally until TI1 rising \nedge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the \ntrigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA \nrequest can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).\nFigure 170 shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay \nbetween the rising edge on TI1 and the actual reset of the counter is due to the \nresynchronization circuit on TI1 input.\nFigure 170. Control circuit in reset mode\nMS37384V1\n00\nCounter clock = CK_CNT = CK_PSC\nCounter register\n01 02 03 00\n01 02 03\n32 33 34 35 36\nUG\nTI1\n31\n30\nTIF\n" }, { "page_number": 622, "page_indices": { "start_index": 1233876, "end_index": 1236277 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 622 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.14 Timers and external trigger synchronization", 621 ], [ 4, "Slave mode: Gated mode", 622 ], [ 4, "Slave mode: Trigger mode", 622 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n622/1757\nRM0090 Rev 21\nSlave mode: Gated mode\nThe counter can be enabled depending on the level of a selected input.\nIn the following example, the upcounter counts only when TI1 input is low:\n•\nConfigure the channel 1 to detect low levels on TI1. Configure the input filter duration \n(in this example, no need of any filter, IC1F=0000 kept). The capture prescaler is not \nused for triggering, so the user does not need to configure it. The CC1S bits select the \ninput capture source only, CC1S=01 in TIMx_CCMR1 register. Write CC1P=1 in \nTIMx_CCER register to validate the polarity (and detect low level only).\n•\nConfigure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select \nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\n•\nEnable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the \ncounter does not start if CEN=0, whatever is the trigger input level).\nThe counter starts counting on the internal clock as long as TI1 is low and stops as soon as \nTI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts \nor stops.\nThe delay between the rising edge on TI1 and the actual stop of the counter is due to the \nresynchronization circuit on TI1 input.\nFigure 171. Control circuit in gated mode\n1.\nThe configuration “CCxP=CCxNP=1” (detection of both rising and falling edges) does not have any effect \nin gated mode because gated mode acts on a level and not on an edge.\nSlave mode: Trigger mode\nThe counter can start in response to an event on a selected input.\nIn the following example, the upcounter starts in response to a rising edge on TI2 input:\n•\nConfigure the channel 2 to detect rising edges on TI2. Configure the input filter duration \n(in this example, no need of any filter, IC2F=0000 kept). The capture prescaler is not \nused for triggering, so the user does not need to configure it. CC2S bits are selecting \nthe input capture source only, CC2S=01 in TIMx_CCMR1 register. Write CC2P=1 in \nTIMx_CCER register to validate the polarity (and detect low level only).\n•\nConfigure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select \nTI2 as the input source by writing TS=110 in TIMx_SMCR register.\nMS40512V1\nTI1\nCNT_EN\nWrite TIF=0\n37\nCounter clock = CK_CNT = CK_PSC\nCounter register\n38\n32\n33\n34\n35\n36\n31\n30\nTIF\n" }, { "page_number": 623, "page_indices": { "start_index": 1236277, "end_index": 1238321 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 623 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.14 Timers and external trigger synchronization", 621 ], [ 4, "Slave mode: External Clock mode 2 + trigger mode", 623 ] ], "page_content": "RM0090 Rev 21\n623/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nWhen a rising edge occurs on TI2, the counter starts counting on the internal clock and the \nTIF flag is set.\nThe delay between the rising edge on TI2 and the actual start of the counter is due to the \nresynchronization circuit on TI2 input.\nFigure 172. Control circuit in trigger mode\nSlave mode: External Clock mode 2 + trigger mode\nThe external clock mode 2 can be used in addition to another slave mode (except external \nclock mode 1 and encoder mode). In this case, the ETR signal is used as external clock \ninput, and another input can be selected as trigger input when operating in reset mode, \ngated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS \nbits of TIMx_SMCR register.\nIn the following example, the upcounter is incremented at each rising edge of the ETR \nsignal as soon as a rising edge of TI1 occurs:\n1.\nConfigure the external trigger input circuit by programming the TIMx_SMCR register as \nfollows:\n–\nETF = 0000: no filter \n–\nETPS = 00: prescaler disabled\n–\nETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock \nmode 2.\n2. \nConfigure the channel 1 as follows, to detect rising edges on TI: \n–\nIC1F = 0000: no filter. \n–\nThe capture prescaler is not used for triggering and does not need to be \nconfigured.\n–\nCC1S = 01 in TIMx_CCMR1 register to select only the input capture source\n–\nCC1P = 0 in TIMx_CCER register to validate the polarity (and detect rising edge \nonly).\n3. \nConfigure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select \nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\nA rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on \nETR rising edges.\nThe delay between the rising edge of the ETR signal and the actual reset of the counter is \ndue to the resynchronization circuit on ETRP input. \nMS37386V1\nTI2\nCNT_EN\nCounter register\nTIF\n37 38\n34\n35 36\nCounter clock = CK_CNT = CK_PSC\n" }, { "page_number": 624, "page_indices": { "start_index": 1238321, "end_index": 1239360 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 624 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.15 Timer synchronization", 624 ], [ 4, "Using one timer as prescaler for another timer", 624 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n624/1757\nRM0090 Rev 21\nFigure 173. Control circuit in external clock mode 2 + trigger mode\n18.3.15 \nTimer synchronization\nThe TIMx timers are linked together internally for timer synchronization or chaining. When \none Timer is configured in Master mode, it can reset, start, stop or clock the counter of \nanother Timer configured in Slave mode.\nFigure 174 presents an overview of the trigger selection and the master mode selection \nblocks.\nNote:\nThe clock of the slave timer must be enabled prior to receiving events from the master timer, \nand must not be changed on-the-fly while triggers are received from the master timer.\nUsing one timer as prescaler for another timer\nFigure 174. Master/Slave timer example\nMS33110V1\n34\n35\n36\nTIF\nCounter register\nCounter clock = CK_CNT = CK_PSC\nETR\nCEN/CNT_EN\nTI1\nMS37387V1\nCounter\nMaster \nmode \ncontrol \nUEV\nPrescaler\nClock\nCounter\nPrescaler\nCK_PSC\nTRGO1\nMMS\nSMS\nTS\nInput trigger \nselection\nTIM1\nTIM2\nSlave \nmode \ncontrol \nITR0\n" }, { "page_number": 625, "page_indices": { "start_index": 1239360, "end_index": 1241900 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 625 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.15 Timer synchronization", 624 ], [ 4, "Using one timer to enable another timer", 625 ] ], "page_content": "RM0090 Rev 21\n625/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFor example, the user can configure Timer 1 to act as a prescaler for Timer 2 (see \nFigure 174). To do this:\n•\nConfigure Timer 1 in master mode so that it outputs a periodic trigger signal on each \nupdate event UEV. If you write MMS=010 in the TIM1_CR2 register, a rising edge is \noutput on TRGO1 each time an update event is generated.\n•\nTo connect the TRGO1 output of Timer 1 to Timer 2, Timer 2 must be configured in \nslave mode using ITR0 as internal trigger. You select this through the TS bits in the \nTIM2_SMCR register (writing TS=000).\n•\nThen you put the slave mode controller in external clock mode 1 (write SMS=111 in the \nTIM2_SMCR register). This causes Timer 2 to be clocked by the rising edge of the \nperiodic Timer 1 trigger signal (which correspond to the timer 1 counter overflow).\n•\nFinally both timers must be enabled by setting their respective CEN bits (TIMx_CR1 \nregister).\nNote:\nIf OCx is selected on Timer 1 as trigger output (MMS=1xx), its rising edge is used to clock \nthe counter of timer 2.\nUsing one timer to enable another timer\nIn this example, we control the enable of Timer 2 with the output compare 1 of Timer 1. \nRefer to Figure 174 for connections. Timer 2 counts on the divided internal clock only when \nOC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the \nprescaler compared to CK_INT (fCK_CNT = fCK_INT/3).\n•\nConfigure Timer 1 master mode to send its Output compare 1 Reference (OC1REF) \nsignal as trigger output (MMS=100 in the TIM1_CR2 register).\n•\nConfigure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).\n•\nConfigure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR \nregister).\n•\nConfigure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).\n•\nEnable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).\n•\nStart Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).\nNote:\nThe counter 2 clock is not synchronized with counter 1, this mode only affects the Timer 2 \ncounter enable signal.\nFigure 175. Gating timer 2 with OC1REF of timer 1\nIn the example in Figure 175, the Timer 2 counter and prescaler are not initialized before \nbeing started. So they start counting from their current value. It is possible to start from a \ngiven value by resetting both timers before starting Timer 1. You can then write any value \nMS37388V1\nCK_INT\nFC\nFD\nFE\nFF\n00\n01\nTIMER1-OC1REF\nTIMER1-CNT\n3046\n3045\n3047\n3048\nTIMER2-CNT\nTIMER2-TIF\nWrite TIF = 0 \n" }, { "page_number": 626, "page_indices": { "start_index": 1241900, "end_index": 1243377 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 626 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.15 Timer synchronization", 624 ], [ 4, "Using one timer to enable another timer", 625 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n626/1757\nRM0090 Rev 21\nyou want in the timer counters. The timers can easily be reset by software using the UG bit \nin the TIMx_EGR registers.\nIn the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts \nfrom 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both \ntimers. Timer 2 stops when Timer 1 is disabled by writing ‘0 to the CEN bit in the TIM1_CR1 \nregister:\n•\nConfigure Timer 1 master mode to send its Output compare 1 Reference (OC1REF) \nsignal as trigger output (MMS=100 in the TIM1_CR2 register).\n•\nConfigure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).\n•\nConfigure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR \nregister).\n•\nConfigure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).\n•\nReset Timer 1 by writing ‘1 in UG bit (TIM1_EGR register).\n•\nReset Timer 2 by writing ‘1 in UG bit (TIM2_EGR register).\n•\nInitialize Timer 2 to 0xE7 by writing ‘0xE7’ in the timer 2 counter (TIM2_CNTL).\n•\nEnable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).\n•\nStart Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).\n•\nStop Timer 1 by writing ‘0 in the CEN bit (TIM1_CR1 register).\nFigure 176. Gating timer 2 with Enable of timer 1\nMS37389V1\nCK_INT\n75\n00\nE7\nTIMER1-CNT_INIT\nTIMER1-CNT\nAB\nTIMER2-CNT\nTIMER2-CNT_INIT\nWrite TIF = 0 \n01\n02\nE9\nE8\n00\nTIMER1-CEN=CNT_EN\nTIMER2-write CNT\nTIMER2-TIF\n" }, { "page_number": 627, "page_indices": { "start_index": 1243377, "end_index": 1244876 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 627 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.15 Timer synchronization", 624 ], [ 4, "Using one timer to start another timer", 627 ] ], "page_content": "RM0090 Rev 21\n627/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nUsing one timer to start another timer\nIn this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to \nFigure 174 for connections. Timer 2 starts counting from its current value (which can be \nnonzero) on the divided internal clock as soon as the update event is generated by Timer 1. \nWhen Timer 2 receives the trigger signal its CEN bit is automatically set and the counter \ncounts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock \nfrequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).\n•\nConfigure Timer 1 master mode to send its Update Event (UEV) as trigger output \n(MMS=010 in the TIM1_CR2 register).\n•\nConfigure the Timer 1 period (TIM1_ARR registers).\n•\nConfigure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR \nregister).\n•\nConfigure Timer 2 in trigger mode (SMS=110 in TIM2_SMCR register).\n•\nStart Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).\nFigure 177. Triggering timer 2 with update of timer 1\nAs in the previous example, the user can initialize both counters before starting counting. \nFigure 178 shows the behavior with the same configuration as in Figure 177 but in trigger \nmode instead of gated mode (SMS=110 in the TIM2_SMCR register).\nMS37390V1\nWrite TIF = 0 \nCK_INT\nTIMER2-CNT\nFD\nTIMER1-CNT\nTIMER2-CEN=CNT_EN\nTIMER2-TIF\nFE\nFF\n00\n01\n02\n46\n47\n48\n45\nTIMER1-UEV\n" }, { "page_number": 628, "page_indices": { "start_index": 1244876, "end_index": 1246563 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 628 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.15 Timer synchronization", 624 ], [ 4, "Starting 2 timers synchronously in response to an external trigger", 628 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n628/1757\nRM0090 Rev 21\nFigure 178. Triggering timer 2 with Enable of timer 1\nStarting 2 timers synchronously in response to an external trigger\nIn this example, we set the enable of timer 1 when its TI1 input rises, and the enable of \nTimer 2 with the enable of Timer 1. Refer to Figure 174 for connections. To ensure the \ncounters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect \nto TI1, master with respect to Timer 2):\n•\nConfigure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the \nTIM1_CR2 register).\n•\nConfigure Timer 1 slave mode to get the input trigger from TI1 (TS=100 in the \nTIM1_SMCR register).\n•\nConfigure Timer 1 in trigger mode (SMS=110 in the TIM1_SMCR register).\n•\nConfigure the Timer 1 in Master/Slave mode by writing MSM=1 (TIM1_SMCR register).\n•\nConfigure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR \nregister).\n•\nConfigure Timer 2 in trigger mode (SMS=110 in the TIM2_SMCR register).\nWhen a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on \nthe internal clock and both TIF flags are set.\nNote:\nIn this example both timers are initialized before starting (by setting their respective UG \nbits). Both counters starts from 0, but you can easily insert an offset between them by \nwriting any of the counter registers (TIMx_CNT). You can see that the master/slave mode \ninsert a delay between CNT_EN and CK_PSC on timer 1.\nMS37391V1\nWrite TIF = 0 \nCK_INT\nTIMER2-CNT\nTIMER1-CNT_INIT\nTIMER1-CEN=CNT_EN\nTIMER2-TIF\nE7\n02\n00\n01\nE9\n75\nCD\n00\nE8\nEA\nTIMER1-CNT\nTIMER2-CNT_INIT\nTIMER2-write CNT\n" }, { "page_number": 629, "page_indices": { "start_index": 1246563, "end_index": 1247235 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 629 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.3 TIM2 to TIM5 functional description", 594 ], [ 3, "18.3.16 Debug mode", 629 ] ], "page_content": "RM0090 Rev 21\n629/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nFigure 179. Triggering timer 1 and 2 with timer 1 TI1 input\n18.3.16 \nDebug mode\nWhen the microcontroller enters debug mode (Cortex®-M4 with FPU core - halted), the \nTIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP \nconfiguration bit in DBGMCU module. For more details, refer to Section 38.16.2: Debug \nsupport for timers, watchdog, bxCAN and I2C.\nMS37392V1\nCK_INT\nTIMER2-CNT\nTIMER1-CEN=CNT_EN\nTIMER2-TIF\n01\nTIMER1-CNT\n02 03 04 05 06 07 08 09\n00\nTIMER2-CEN=CNT_EN\nTIMER1-TIF\nTIMER1-CK_PSC\nTIMER1-TI1\nTIMER2-CK_PSC\n01 02 03 04 05 06 07 08 09\n00\n" }, { "page_number": 630, "page_indices": { "start_index": 1247235, "end_index": 1249555 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 630 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.1 TIMx control register 1 (TIMx_CR1)", 630 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n630/1757\nRM0090 Rev 21\n18.4 \nTIM2 to TIM5 registers\nRefer to Section 2.2 for a list of abbreviations used in register descriptions.\nThe 32-bit peripheral registers have to be written by words (32 bits). All other peripheral \nregisters have to be written by half-words (16 bits) or words (32 bits). Read accesses can be \ndone by bytes (8 bits), half-words (16 bits) or words (32 bits). \n18.4.1 \nTIMx control register 1 (TIMx_CR1)\nAddress offset: 0x00\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCKD[1:0]\nARPE\nCMS\nDIR\nOPM\nURS\nUDIS\nCEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:10 Reserved, must be kept at reset value.\nBits 9:8 CKD: Clock division\nThis bit-field indicates the division ratio between the timer clock (CK_INT) frequency and \nsampling clock used by the digital filters (ETR, TIx),\n00: tDTS = tCK_INT\n01: tDTS = 2 × tCK_INT\n10: tDTS = 4 × tCK_INT\n11: Reserved\nBit 7 ARPE: Auto-reload preload enable\n0: TIMx_ARR register is not buffered\n1: TIMx_ARR register is buffered\nBits 6:5 CMS: Center-aligned mode selection\n00: Edge-aligned mode. The counter counts up or down depending on the direction bit \n(DIR).\n01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare \ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set \nonly when the counter is counting down.\n10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare \ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set \nonly when the counter is counting up.\n11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare \ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set \nboth when the counter is counting up or down.\nNote: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as \nthe counter is enabled (CEN=1)\nBit 4 DIR: Direction\n0: Counter used as upcounter\n1: Counter used as downcounter\nNote: This bit is read only when the timer is configured in Center-aligned mode or Encoder \nmode.\nBit 3 OPM: One-pulse mode\n0: Counter is not stopped at update event\n1: Counter stops counting at the next update event (clearing the bit CEN)\n" }, { "page_number": 631, "page_indices": { "start_index": 1249555, "end_index": 1250998 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 631 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.1 TIMx control register 1 (TIMx_CR1)", 630 ] ], "page_content": "RM0090 Rev 21\n631/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nBit 2 URS: Update request source\nThis bit is set and cleared by software to select the UEV event sources.\n0: Any of the following events generate an update interrupt or DMA request if enabled. \nThese events can be: \n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\n1: Only counter overflow/underflow generates an update interrupt or DMA request if \nenabled.\nBit 1 UDIS: Update disable\nThis bit is set and cleared by software to enable/disable UEV event generation.\n0: UEV enabled. The Update (UEV) event is generated by one of the following events:\n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\nBuffered registers are then loaded with their preload values.\n1: UEV disabled. The Update event is not generated, shadow registers keep their value \n(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is \nset or if a hardware reset is received from the slave mode controller.\nBit 0 CEN: Counter enable\n0: Counter disabled\n1: Counter enabled\nNote: External clock, gated mode and encoder mode can work only if the CEN bit has been \npreviously set by software. However trigger mode can set the CEN bit automatically by \nhardware. \nCEN is cleared automatically in one-pulse mode, when an update event occurs.\n" }, { "page_number": 632, "page_indices": { "start_index": 1250998, "end_index": 1253402 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 632 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.2 TIMx control register 2 (TIMx_CR2)", 632 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n632/1757\nRM0090 Rev 21\n18.4.2 \nTIMx control register 2 (TIMx_CR2)\nAddress offset: 0x04\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTI1S\nMMS[2:0]\nCCDS\nReserved\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 TI1S: TI1 selection\n0: The TIMx_CH1 pin is connected to TI1 input\n1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) \nBits 6:4 MMS[2:0]: Master mode selection\nThese bits can be used to select the information to be sent in master mode to slave timers \nfor synchronization (TRGO). The combination is as follows:\n000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the \nreset is generated by the trigger input (slave mode controller configured in reset mode) then \nthe signal on TRGO is delayed compared to the actual reset.\n001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is \nuseful to start several timers at the same time or to control a window in which a slave timer is \nenabled. The Counter Enable signal is generated by a logic OR between CEN control bit \nand the trigger input when configured in gated mode. \nWhen the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, \nexcept if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR \nregister).\n010: Update - The update event is selected as trigger output (TRGO). For instance a master \ntimer can then be used as a prescaler for a slave timer.\n011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be \nset (even if it was already high), as soon as a capture or a compare match occurred. \n(TRGO)\n100: Compare - OC1REF signal is used as trigger output (TRGO)\n101: Compare - OC2REF signal is used as trigger output (TRGO)\n110: Compare - OC3REF signal is used as trigger output (TRGO)\n111: Compare - OC4REF signal is used as trigger output (TRGO)\nNote: The clock of the slave timer and ADC must be enabled prior to receiving events from \nthe master timer, and must not be changed on-the-fly while triggers are received from \nthe master timer.\nBit 3 CCDS: Capture/compare DMA selection\n0: CCx DMA request sent when CCx event occurs\n1: CCx DMA requests sent when update event occurs\nBits 2:0 Reserved, must be kept at reset value.\n" }, { "page_number": 633, "page_indices": { "start_index": 1253402, "end_index": 1255776 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 633 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.3 TIMx slave mode control register (TIMx_SMCR)", 633 ] ], "page_content": "RM0090 Rev 21\n633/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n18.4.3 \nTIMx slave mode control register (TIMx_SMCR)\nAddress offset: 0x08\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nETP\nECE\nETPS[1:0]\nETF[3:0]\nMSM\nTS[2:0]\nRes.\nSMS[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 ETP: External trigger polarity\nThis bit selects whether ETR or ETR is used for trigger operations\n0: ETR is noninverted, active at high level or rising edge\n1: ETR is inverted, active at low level or falling edge\nBit 14 ECE: External clock enable\nThis bit enables External clock mode 2.\n0: External clock mode 2 disabled\n1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF \nsignal.\n1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI \nconnected to ETRF (SMS=111 and TS=111).\n2: It is possible to simultaneously use external clock mode 2 with the following slave modes: \nreset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to \nETRF in this case (TS bits must not be 111).\n3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the \nexternal clock input is ETRF.\nBits 13:12 ETPS: External trigger prescaler\nExternal trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A \nprescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external \nclocks.\n00: Prescaler OFF\n01: ETRP frequency divided by 2\n10: ETRP frequency divided by 4\n11: ETRP frequency divided by 8\nBits 11:8 ETF[3:0]: External trigger filter\nThis bit-field then defines the frequency used to sample ETRP signal and the length of the \ndigital filter applied to ETRP. The digital filter is made of an event counter in which N \nconsecutive events are needed to validate a transition on the output:\n0000: No filter, sampling is done at fDTS\n0001: fSAMPLING=fCK_INT, N=2\n0010: fSAMPLING=fCK_INT, N=4\n0011: fSAMPLING=fCK_INT, N=8\n0100: fSAMPLING=fDTS/2, N=6\n0101: fSAMPLING=fDTS/2, N=8\n0110: fSAMPLING=fDTS/4, N=6\n0111: fSAMPLING=fDTS/4, N=8\n1000: fSAMPLING=fDTS/8, N=6\n1001: fSAMPLING=fDTS/8, N=8\n1010: fSAMPLING=fDTS/16, N=5\n1011: fSAMPLING=fDTS/16, N=6\n1100: fSAMPLING=fDTS/16, N=8\n1101: fSAMPLING=fDTS/32, N=5\n1110: fSAMPLING=fDTS/32, N=6\n1111: fSAMPLING=fDTS/32, N=8\n" }, { "page_number": 634, "page_indices": { "start_index": 1255776, "end_index": 1258447 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 634 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.3 TIMx slave mode control register (TIMx_SMCR)", 633 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n634/1757\nRM0090 Rev 21\n \nBit 7 MSM: Master/Slave mode\n0: No action\n1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect \nsynchronization between the current timer and its slaves (through TRGO). It is useful if we \nwant to synchronize several timers on a single external event.\nBits 6:4 TS: Trigger selection\nThis bit-field selects the trigger input to be used to synchronize the counter.\n000: Internal Trigger 0 (ITR0)\n001: Internal Trigger 1 (ITR1). \n010: Internal Trigger 2 (ITR2). \n011: Internal Trigger 3 (ITR3).\n100: TI1 Edge Detector (TI1F_ED)\n101: Filtered Timer Input 1 (TI1FP1)\n110: Filtered Timer Input 2 (TI2FP2)\n111: External Trigger input (ETRF)\nSee Table 99: TIMx internal trigger connection on page 635 for more details on ITRx \nmeaning for each Timer.\nNote: These bits must be changed only when they are not used (e.g. when SMS=000) to \navoid wrong edge detections at the transition.\nBit 3 Reserved, must be kept at reset value.\nBits 2:0 SMS: Slave mode selection\nWhen external signals are selected the active edge of the trigger signal (TRGI) is linked to \nthe polarity selected on the external input (see Input Control register and Control register \ndescription.\n000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal \nclock.\n001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 \nlevel.\n010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 \nlevel.\n011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges \ndepending on the level of the other input.\n100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter \nand generates an update of the registers.\n101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The \ncounter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of \nthe counter are controlled.\n110: Trigger mode - The counter starts at a rising edge of the trigger TRGI (but it is not \nreset). Only the start of the counter is controlled.\n111: External Clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.\nNote: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100). \nIndeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode \nchecks the level of the trigger signal.\nThe clock of the slave timer must be enabled prior to receiving events from the master \ntimer, and must not be changed on-the-fly while triggers are received from the master \ntimer.\n" }, { "page_number": 635, "page_indices": { "start_index": 1258447, "end_index": 1260113 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 635 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)", 635 ] ], "page_content": "RM0090 Rev 21\n635/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n \n18.4.4 \nTIMx DMA/Interrupt enable register (TIMx_DIER)\nAddress offset: 0x0C\nReset value: 0x0000\n \nTable 99. TIMx internal trigger connection\nSlave TIM\nITR0 (TS = 000)\nITR1 (TS = 001)\nITR2 (TS = 010)\nITR3 (TS = 011)\nTIM2\nTIM1_TRGO\nTIM8_TRGO\nTIM3_TRGO\nTIM4_TRGO\nTIM3\nTIM1_TRGO\nTIM2_TRGO\nTIM5_TRGO\nTIM4_TRGO\nTIM4\nTIM1_TRGO\nTIM2_TRGO\nTIM3_TRGO\nTIM8_TRGO\nTIM5\nTIM2_TRGO\nTIM3_TRGO\nTIM4_TRGO\nTIM8_TRGO\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nTDE\nRes\nCC4DE CC3DE CC2DE CC1DE\nUDE\nRes.\nTIE\nRes\nCC4IE\nCC3IE\nCC2IE\nCC1IE\nUIE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15\nReserved, must be kept at reset value.\nBit 14 TDE: Trigger DMA request enable\n0: Trigger DMA request disabled.\n1: Trigger DMA request enabled.\nBit 13\nReserved, always read as 0\nBit 12 CC4DE: Capture/Compare 4 DMA request enable\n0: CC4 DMA request disabled.\n1: CC4 DMA request enabled.\nBit 11 CC3DE: Capture/Compare 3 DMA request enable\n0: CC3 DMA request disabled.\n1: CC3 DMA request enabled.\nBit 10 CC2DE: Capture/Compare 2 DMA request enable\n0: CC2 DMA request disabled.\n1: CC2 DMA request enabled.\nBit 9 CC1DE: Capture/Compare 1 DMA request enable\n0: CC1 DMA request disabled.\n1: CC1 DMA request enabled.\nBit 8 UDE: Update DMA request enable\n0: Update DMA request disabled.\n1: Update DMA request enabled.\nBit 7\nReserved, must be kept at reset value.\nBit 6 TIE: Trigger interrupt enable\n0: Trigger interrupt disabled.\n1: Trigger interrupt enabled.\nBit 5\nReserved, must be kept at reset value.\nBit 4 CC4IE: Capture/Compare 4 interrupt enable\n0: CC4 interrupt disabled.\n1: CC4 interrupt enabled.\n" }, { "page_number": 636, "page_indices": { "start_index": 1260113, "end_index": 1261977 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 636 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.5 TIMx status register (TIMx_SR)", 636 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n636/1757\nRM0090 Rev 21\n18.4.5 \nTIMx status register (TIMx_SR)\nAddress offset: 0x10\nReset value: 0x0000\n \nBit 3 CC3IE: Capture/Compare 3 interrupt enable\n0: CC3 interrupt disabled\n1: CC3 interrupt enabled\nBit 2 CC2IE: Capture/Compare 2 interrupt enable\n0: CC2 interrupt disabled\n1: CC2 interrupt enabled\nBit 1 CC1IE: Capture/Compare 1 interrupt enable\n0: CC1 interrupt disabled\n1: CC1 interrupt enabled\nBit 0 UIE: Update interrupt enable\n0: Update interrupt disabled\n1: Update interrupt enabled\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCC4OF CC3OF CC2OF CC1OF\nReserved\nTIF\nRes\nCC4IF\nCC3IF\nCC2IF\nCC1IF\nUIF\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nBits 15:13\nReserved, must be kept at reset value.\nBit 12 CC4OF: Capture/Compare 4 overcapture flag\nrefer to CC1OF description\nBit 11 CC3OF: Capture/Compare 3 overcapture flag\nrefer to CC1OF description\nBit 10 CC2OF: Capture/compare 2 overcapture flag\nrefer to CC1OF description\nBit 9 CC1OF: Capture/Compare 1 overcapture flag\nThis flag is set by hardware only when the corresponding channel is configured in input \ncapture mode. It is cleared by software by writing it to ‘0.\n0: No overcapture has been detected\n1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was \nalready set\nBits 8:7\nReserved, must be kept at reset value.\nBit 6 TIF: Trigger interrupt flag\nThis flag is set by hardware on trigger event (active edge detected on TRGI input when the \nslave mode controller is enabled in all modes but gated mode. It is set when the counter \nstarts or stops when gated mode is selected. It is cleared by software.\n0: No trigger event occurred\n1: Trigger interrupt pending\nBit 5\nReserved, must be kept at reset value.\nBit 4 CC4IF: Capture/Compare 4 interrupt flag\nrefer to CC1IF description\n" }, { "page_number": 637, "page_indices": { "start_index": 1261977, "end_index": 1263699 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 637 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.5 TIMx status register (TIMx_SR)", 636 ] ], "page_content": "RM0090 Rev 21\n637/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nBit 3 CC3IF: Capture/Compare 3 interrupt flag\nrefer to CC1IF description\nBit 2 CC2IF: Capture/Compare 2 interrupt flag\nrefer to CC1IF description\nBit 1 CC1IF: Capture/compare 1 interrupt flag\nIf channel CC1 is configured as output:\nThis flag is set by hardware when the counter matches the compare value, with some \nexception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register \ndescription). It is cleared by software.\n0: No match\n1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. \nWhen the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit \ngoes high on the counter overflow (in upcounting and up/down-counting modes) or underflow \n(in downcounting mode)\nIf channel CC1 is configured as input:\nThis bit is set by hardware on a capture. It is cleared by software or by reading the \nTIMx_CCR1 register.\n0: No input capture occurred\n1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected \non IC1 which matches the selected polarity)\nBit 0 UIF: Update interrupt flag\n″\nThis bit is set by hardware on an update event. It is cleared by software.\n0: No update occurred.\n1: Update interrupt pending. This bit is set by hardware when the registers are updated:\n″\nAt overflow or underflow (for TIM2 to TIM5) and if UDIS=0 in the TIMx_CR1 register.\n″\nWhen CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 \nand UDIS=0 in the TIMx_CR1 register.\nWhen CNT is reinitialized by a trigger event (refer to the synchro control register description), \nif URS=0 and UDIS=0 in the TIMx_CR1 register.\n" }, { "page_number": 638, "page_indices": { "start_index": 1263699, "end_index": 1265541 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 638 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.6 TIMx event generation register (TIMx_EGR)", 638 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n638/1757\nRM0090 Rev 21\n18.4.6 \nTIMx event generation register (TIMx_EGR)\nAddress offset: 0x14\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTG\nRes.\nCC4G\nCC3G\nCC2G\nCC1G\nUG\nw\nw\nw\nw\nw\nw\nBits 15:7 Reserved, must be kept at reset value.\nBit 6 TG: Trigger generation\nThis bit is set by software in order to generate an event, it is automatically cleared by \nhardware.\n0: No action\n1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if \nenabled.\nBit 5 Reserved, must be kept at reset value.\nBit 4 CC4G: Capture/compare 4 generation\nrefer to CC1G description\nBit 3 CC3G: Capture/compare 3 generation\nrefer to CC1G description\nBit 2 CC2G: Capture/compare 2 generation\nrefer to CC1G description\nBit 1 CC1G: Capture/compare 1 generation\nThis bit is set by software in order to generate an event, it is automatically cleared by \nhardware.\n0: No action\n1: A capture/compare event is generated on channel 1:\nIf channel CC1 is configured as output:\nCC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.\nIf channel CC1 is configured as input:\nThe current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, \nthe corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the \nCC1IF flag was already high.\nBit 0 UG: Update generation\nThis bit can be set by software, it is automatically cleared by hardware.\n0: No action\n1: Re-initialize the counter and generates an update of the registers. Note that the prescaler \ncounter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if \nthe center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload \nvalue (TIMx_ARR) if DIR=1 (downcounting).\n" }, { "page_number": 639, "page_indices": { "start_index": 1265541, "end_index": 1267415 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 639 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)", 639 ], [ 4, "Output compare mode", 639 ] ], "page_content": "RM0090 Rev 21\n639/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n18.4.7 \nTIMx capture/compare mode register 1 (TIMx_CCMR1)\nAddress offset: 0x18\nReset value: 0x0000\nThe channels can be used in input (capture mode) or in output (compare mode). The \ndirection of a channel is defined by configuring the corresponding CCxS bits. All the other \nbits of this register have a different function in input and in output mode. For a given bit, \nOCxx describes its function when the channel is configured in output, ICxx describes its \nfunction when the channel is configured in input. Take care that the same bit can have a \ndifferent meaning for the input stage and for the output stage.\n \nOutput compare mode\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOC2CE\nOC2M[2:0]\nOC2PE OC2FE\nCC2S[1:0]\nOC1CE\nOC1M[2:0]\nOC1PE OC1FE\nCC1S[1:0]\nIC2F[3:0]\nIC2PSC[1:0]\nIC1F[3:0]\nIC1PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 OC2CE: Output compare 2 clear enable\nBits 14:12 OC2M[2:0]: Output compare 2 mode\nBit 11 OC2PE: Output compare 2 preload enable\nBit 10 OC2FE: Output compare 2 fast enable\nBits 9:8 CC2S[1:0]: Capture/Compare 2 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC2 channel is configured as output\n01: CC2 channel is configured as input, IC2 is mapped on TI2\n10: CC2 channel is configured as input, IC2 is mapped on TI1\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through the TS bit (TIMx_SMCR register)\nNote: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).\nBit 7 OC1CE: Output compare 1 clear enable\nOC1CE: Output compare 1 Clear Enable\n0: OC1Ref is not affected by the ETRF input\n1: OC1Ref is cleared as soon as a High level is detected on ETRF input\n" }, { "page_number": 640, "page_indices": { "start_index": 1267415, "end_index": 1270659 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 640 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)", 639 ], [ 4, "Output compare mode", 639 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n640/1757\nRM0090 Rev 21\nBits 6:4 OC1M: Output compare 1 mode\nThese bits define the behavior of the output reference signal OC1REF from which OC1 and \nOC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends \non CC1P and CC1NP bits.\n000: Frozen - The comparison between the output compare register TIMx_CCR1 and the \ncounter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing \nbase).\n001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter \nTIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).\n010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the \ncounter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).\n011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.\n100: Force inactive level - OC1REF is forced low.\n101: Force active level - OC1REF is forced high.\n110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (OC1REF=1).\n111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 else \ninactive.\nNote: In PWM mode 1 or 2, the OCREF level changes only when the result of the \ncomparison changes or when the output compare mode switches from “frozen” mode \nto “PWM” mode.\nBit 3 OC1PE: Output compare 1 preload enable\n0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the \nnew value is taken in account immediately.\n1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload \nregister. TIMx_CCR1 preload value is loaded in the active register at each update event.\nNote: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK \nbits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output).\nBit 2 OC1FE: Output compare 1 fast enable\nThis bit is used to accelerate the effect of an event on the trigger in input on the CC output.\n0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is \nON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is \n5 clock cycles.\n1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC \nis set to the compare level independently from the result of the comparison. Delay to sample \nthe trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if \nthe channel is configured in PWM1 or PWM2 mode.\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC1 channel is configured as output.\n01: CC1 channel is configured as input, IC1 is mapped on TI1.\n10: CC1 channel is configured as input, IC1 is mapped on TI2.\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\n" }, { "page_number": 641, "page_indices": { "start_index": 1270659, "end_index": 1273105 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 641 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)", 639 ], [ 4, "Input capture mode", 641 ] ], "page_content": "RM0090 Rev 21\n641/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nInput capture mode\nBits 15:12 IC2F: Input capture 2 filter\nBits 11:10 IC2PSC[1:0]: Input capture 2 prescaler\nBits 9:8 CC2S: Capture/compare 2 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC2 channel is configured as output.\n01: CC2 channel is configured as input, IC2 is mapped on TI2.\n10: CC2 channel is configured as input, IC2 is mapped on TI1.\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).\nBits 7:4 IC1F: Input capture 1 filter\nThis bit-field defines the frequency used to sample TI1 input and the length of the digital filter \napplied to TI1. The digital filter is made of an event counter in which N consecutive events \nare needed to validate a transition on the output:\n0000: No filter, sampling is done at fDTS\n0001: fSAMPLING=fCK_INT, N=2\n0010: fSAMPLING=fCK_INT, N=4\n0011: fSAMPLING=fCK_INT, N=8\n0100: fSAMPLING=fDTS/2, N=6\n0101: fSAMPLING=fDTS/2, N=8\n0110: fSAMPLING=fDTS/4, N=6\n0111: fSAMPLING=fDTS/4, N=8\n1000: fSAMPLING=fDTS/8, N=6\n1001: fSAMPLING=fDTS/8, N=8\n1010: fSAMPLING=fDTS/16, N=5\n1011: fSAMPLING=fDTS/16, N=6\n1100: fSAMPLING=fDTS/16, N=8\n1101: fSAMPLING=fDTS/32, N=5\n1110: fSAMPLING=fDTS/32, N=6\n1111: fSAMPLING=fDTS/32, N=8\nBits 3:2 IC1PSC: Input capture 1 prescaler\nThis bit-field defines the ratio of the prescaler acting on CC1 input (IC1).\nThe prescaler is reset as soon as CC1E=0 (TIMx_CCER register).\n00: no prescaler, capture is done each time an edge is detected on the capture input\n01: capture is done once every 2 events\n10: capture is done once every 4 events\n11: capture is done once every 8 events\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: CC1 channel is configured as input, IC1 is mapped on TI2\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\n" }, { "page_number": 642, "page_indices": { "start_index": 1273105, "end_index": 1275004 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 642 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)", 642 ], [ 4, "Output compare mode", 642 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n642/1757\nRM0090 Rev 21\n18.4.8 \nTIMx capture/compare mode register 2 (TIMx_CCMR2)\nAddress offset: 0x1C\nReset value: 0x0000\nRefer to the above CCMR1 register description.\nOutput compare mode\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOC4CE\nOC4M[2:0]\nOC4PE OC4FE\nCC4S[1:0]\nOC3CE\nOC3M[2:0]\nOC3PE OC3FE\nCC3S[1:0]\nIC4F[3:0]\nIC4PSC[1:0]\nIC3F[3:0]\nIC3PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 OC4CE: Output compare 4 clear enable\nBits 14:12 OC4M: Output compare 4 mode\nBit 11 OC4PE: Output compare 4 preload enable\nBit 10 OC4FE: Output compare 4 fast enable\nBits 9:8 CC4S: Capture/Compare 4 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC4 channel is configured as output\n01: CC4 channel is configured as input, IC4 is mapped on TI4\n10: CC4 channel is configured as input, IC4 is mapped on TI3\n11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).\nBit 7 OC3CE: Output compare 3 clear enable\nBits 6:4 OC3M: Output compare 3 mode\nBit 3 OC3PE: Output compare 3 preload enable\nBit 2 OC3FE: Output compare 3 fast enable\nBits 1:0 CC3S: Capture/Compare 3 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC3 channel is configured as output\n01: CC3 channel is configured as input, IC3 is mapped on TI3\n10: CC3 channel is configured as input, IC3 is mapped on TI4\n11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).\n" }, { "page_number": 643, "page_indices": { "start_index": 1275004, "end_index": 1277120 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 643 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)", 642 ], [ 4, "Input capture mode", 643 ], [ 3, "18.4.9 TIMx capture/compare enable register (TIMx_CCER)", 643 ] ], "page_content": "RM0090 Rev 21\n643/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nInput capture mode\n18.4.9 \nTIMx capture/compare enable register (TIMx_CCER)\nAddress offset: 0x20\nReset value: 0x0000\n \n \nBits 15:12 IC4F: Input capture 4 filter\nBits 11:10 IC4PSC: Input capture 4 prescaler\nBits 9:8 CC4S: Capture/Compare 4 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC4 channel is configured as output\n01: CC4 channel is configured as input, IC4 is mapped on TI4\n10: CC4 channel is configured as input, IC4 is mapped on TI3\n11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).\nBits 7:4 IC3F: Input capture 3 filter\nBits 3:2 IC3PSC: Input capture 3 prescaler\nBits 1:0 CC3S: Capture/Compare 3 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC3 channel is configured as output\n01: CC3 channel is configured as input, IC3 is mapped on TI3\n10: CC3 channel is configured as input, IC3 is mapped on TI4\n11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCC4NP\nRes.\nCC4P\nCC4E\nCC3NP\nRes.\nCC3P\nCC3E\nCC2NP\nRes.\nCC2P\nCC2E\nCC1NP\nRes.\nCC1P\nCC1E\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 CC4NP: Capture/Compare 4 output Polarity.\nRefer to CC1NP description\nBit 14\nReserved, must be kept at reset value.\nBit 13 CC4P: Capture/Compare 4 output Polarity.\nrefer to CC1P description\nBit 12 CC4E: Capture/Compare 4 output enable.\nrefer to CC1E description\nBit 11 CC3NP: Capture/Compare 3 output Polarity.\nrefer to CC1NP description\nBit 10\nReserved, must be kept at reset value.\nBit 9 CC3P: Capture/Compare 3 output Polarity.\nrefer to CC1P description\n" }, { "page_number": 644, "page_indices": { "start_index": 1277120, "end_index": 1279308 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 644 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.9 TIMx capture/compare enable register (TIMx_CCER)", 643 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n644/1757\nRM0090 Rev 21\n \nBit 8 CC3E: Capture/Compare 3 output enable.\nrefer to CC1E description\nBit 7 CC2NP: Capture/Compare 2 output Polarity.\nrefer to CC1NP description\nBit 6\nReserved, must be kept at reset value.\nBit 5 CC2P: Capture/Compare 2 output Polarity.\nrefer to CC1P description\nBit 4 CC2E: Capture/Compare 2 output enable.\nrefer to CC1E description\nBit 3 CC1NP: Capture/Compare 1 output Polarity.\nCC1 channel configured as output:\nCC1NP must be kept cleared in this case.\nCC1 channel configured as input:\nThis bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P \ndescription.\nBit 2\nReserved, must be kept at reset value.\nBit 1 CC1P: Capture/Compare 1 output Polarity.\nCC1 channel configured as output:\n0: OC1 active high\n1: OC1 active low\nCC1 channel configured as input:\nCC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.\n00: noninverted/rising edge\nCircuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger \nmode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).\n01: inverted/falling edge\nCircuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger \nmode), TIxFP1 is inverted (trigger in gated mode, encoder mode).\n10: reserved, do not use this configuration.\n11: noninverted/both edges\nCircuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external \nclock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration \nmust not be used for encoder mode.\nBit 0 CC1E: Capture/Compare 1 output enable.\nCC1 channel configured as output:\n0: Off - OC1 is not active\n1: On - OC1 signal is output on the corresponding output pin\nCC1 channel configured as input:\nThis bit determines if a capture of the counter value can actually be done into the input \ncapture/compare register 1 (TIMx_CCR1) or not.\n0: Capture disabled\n1: Capture enabled\nTable 100. Output control bit for standard OCx channels\nCCxE bit\nOCx output state\n0\nOutput Disabled (OCx=0, OCx_EN=0)\n1\nOCx=OCxREF + Polarity, OCx_EN=1\n" }, { "page_number": 645, "page_indices": { "start_index": 1279308, "end_index": 1280801 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 645 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.10 TIMx counter (TIMx_CNT)", 645 ], [ 3, "18.4.11 TIMx prescaler (TIMx_PSC)", 645 ], [ 3, "18.4.12 TIMx auto-reload register (TIMx_ARR)", 645 ] ], "page_content": "RM0090 Rev 21\n645/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\nNote:\nThe state of the external IO pins connected to the standard OCx channels depends on the \nOCx channel state and the GPIO registers.\n18.4.10 \nTIMx counter (TIMx_CNT)\nAddress offset: 0x24\nReset value: 0x0000 0000\n \n18.4.11 \nTIMx prescaler (TIMx_PSC)\nAddress offset: 0x28\nReset value: 0x0000\n \n18.4.12 \nTIMx auto-reload register (TIMx_ARR)\nAddress offset: 0x2C\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCNT[31:16] (depending on timers)\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCNT[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 CNT[31:16]: High counter value (on TIM2 and TIM5).\nBits 15:0 CNT[15:0]: Counter value\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPSC[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 PSC[15:0]: Prescaler value\nThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).\nPSC contains the value to be loaded in the active prescaler register at each update event \n(including when the counter is cleared through UG bit of TIMx_EGR register or through \ntrigger controller when configured in “reset mode”).\nReset value: 0xFFFF FFFF\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nARR[31:16] (depending on timers)\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nARR[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 646, "page_indices": { "start_index": 1280801, "end_index": 1282843 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 646 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.13 TIMx capture/compare register 1 (TIMx_CCR1)", 646 ], [ 3, "18.4.14 TIMx capture/compare register 2 (TIMx_CCR2)", 646 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n646/1757\nRM0090 Rev 21\n \n18.4.13 \nTIMx capture/compare register 1 (TIMx_CCR1)\nAddress offset: 0x34\nReset value: 0x0000 0000\n \n18.4.14 \nTIMx capture/compare register 2 (TIMx_CCR2)\nAddress offset: 0x38\nReset value: 0x0000 0000\nBits 31:16 ARR[31:16]: High auto-reload value (on TIM2 and TIM5).\nBits 15:0\nARR[15:0]: Auto-reload value\nARR is the value to be loaded in the actual auto-reload register.\nRefer to the Section 18.3.1: Time-base unit for more details about ARR update and \nbehavior.\nThe counter is blocked while the auto-reload value is null.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCCR1[31:16] (depending on timers)\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR1[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 31:16 CCR1[31:16]: High Capture/Compare 1 value (on TIM2 and TIM5).\nBits 15:0 CCR1[15:0]: Low Capture/Compare 1 value\nIf channel CC1 is configured as output:\nCCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register \n(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when \nan update event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signaled on OC1 output.\nIf channel CC1is configured as input:\nCCR1 is the counter value transferred by the last input capture 1 event (IC1). The \nTIMx_CCR1 register is read-only and cannot be programmed.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCCR2[31:16] (depending on timers)\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR2[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\n" }, { "page_number": 647, "page_indices": { "start_index": 1282843, "end_index": 1285328 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 647 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.15 TIMx capture/compare register 3 (TIMx_CCR3)", 647 ], [ 3, "18.4.16 TIMx capture/compare register 4 (TIMx_CCR4)", 647 ] ], "page_content": "RM0090 Rev 21\n647/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n \n18.4.15 \nTIMx capture/compare register 3 (TIMx_CCR3)\nAddress offset: 0x3C\nReset value: 0x0000 0000\n \n18.4.16 \nTIMx capture/compare register 4 (TIMx_CCR4)\nAddress offset: 0x40\nReset value: 0x0000 0000\nBits 31:16 CCR2[31:16]: High Capture/Compare 2 value (on TIM2 and TIM5).\nBits 15:0 CCR2[15:0]: Low Capture/Compare 2 value\nIf channel CC2 is configured as output:\nCCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR register (bit \nOC2PE). Else the preload value is copied in the active capture/compare 2 register when an \nupdate event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signalled on OC2 output.\nIf channel CC2 is configured as input:\nCCR2 is the counter value transferred by the last input capture 2 event (IC2). The \nTIMx_CCR2 register is read-only and cannot be programmed.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCCR3[31:16] (depending on timers)\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR3[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2 and TIM5).\nBits 15:0 CCR3[15:0]: Low Capture/Compare value\nIf channel CC3 is configured as output:\nCCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR register (bit \nOC3PE). Else the preload value is copied in the active capture/compare 3 register when an \nupdate event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signaled on OC3 output.\nIf channel CC3 is configured as input:\nCCR3 is the counter value transferred by the last input capture 3 event (IC3). The \nTIMx_CCR3 register is read-only and cannot be programmed.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCCR4[31:16] (depending on timers)\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR4[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\n" }, { "page_number": 648, "page_indices": { "start_index": 1285328, "end_index": 1287309 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 648 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.17 TIMx DMA control register (TIMx_DCR)", 648 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n648/1757\nRM0090 Rev 21\n \n18.4.17 \nTIMx DMA control register (TIMx_DCR)\nAddress offset: 0x48\nReset value: 0x0000\n \nBits 31:16 CCR4[31:16]: High Capture/Compare 4 value (on TIM2 and TIM5).\nBits 15:0 CCR4[15:0]: Low Capture/Compare value\n1.\nif CC4 channel is configured as output (CC4S bits):\nCCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR register \n(bit OC4PE). Else the preload value is copied in the active capture/compare 4 register \nwhen an update event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signalled on OC4 output.\n2. \nif CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register):\nCCR4 is the counter value transferred by the last input capture 4 event (IC4). The \nTIMx_CCR4 register is read-only and cannot be programmed.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDBL[4:0]\nReserved\nDBA[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:13 Reserved, must be kept at reset value.\nBits 12:8 DBL[4:0]: DMA burst length\nThis 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer \nwhen a read or a write access is done to the TIMx_DMAR address).\n00000: 1 transfer,\n00001: 2 transfers,\n00010: 3 transfers,\n...\n10001: 18 transfers.\nBits 7:5 Reserved, must be kept at reset value.\nBits 4:0 DBA[4:0]: DMA base address\nThis 5-bit vector defines the base-address for DMA transfers (when read/write access are \ndone through the TIMx_DMAR address). DBA is defined as an offset starting from the \naddress of the TIMx_CR1 register.\nExample:\n00000: TIMx_CR1,\n00001: TIMx_CR2,\n00010: TIMx_SMCR,\n...\nExample: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this \ncase the transfer is done to/from 7 registers starting from the TIMx_CR1 address.\n" }, { "page_number": 649, "page_indices": { "start_index": 1287309, "end_index": 1289637 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 649 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.18 TIMx DMA address for full transfer (TIMx_DMAR)", 649 ], [ 4, "Example of how to use the DMA burst feature", 649 ], [ 3, "18.4.19 TIM2 option register (TIM2_OR)", 649 ] ], "page_content": "RM0090 Rev 21\n649/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n18.4.18 \nTIMx DMA address for full transfer (TIMx_DMAR)\nAddress offset: 0x4C\nReset value: 0x0000\n \nExample of how to use the DMA burst feature\nIn this example the timer DMA burst feature is used to update the contents of the CCRx \nregisters (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers. \nThis is done in the following steps:\n1.\nConfigure the corresponding DMA channel as follows: \n–\nDMA channel peripheral address is the DMAR register address \n–\nDMA channel memory address is the address of the buffer in the RAM containing \nthe data to be transferred by DMA into CCRx registers. \n–\nNumber of data to transfer = 3 (See note below). \n–\nCircular mode disabled. \n2. \nConfigure the DCR register by configuring the DBA and DBL bit fields as follows: \nDBL = 3 transfers, DBA = 0xE. \n3. \nEnable the TIMx update DMA request (set the UDE bit in the DIER register). \n4. \nEnable TIMx \n5. \nEnable the DMA channel\nNote:\nThis example is for the case where every CCRx register to be updated once. If every CCRx \nregister is to be updated twice for example, the number of data to transfer should be 6. Let's \ntake the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and \ndata6. The data is transferred to the CCRx registers as follows: on the first update DMA \nrequest, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to \nCCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is \ntransferred to CCR3 and data6 is transferred to CCR4. \n18.4.19 \nTIM2 option register (TIM2_OR)\nAddress offset: 0x50\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDMAB[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 DMAB[15:0]: DMA register for burst accesses\nA read or write operation to the DMAR register accesses the register located at the address\n(TIMx_CR1 address) + (DBA + DMA index) x 4 \nwhere TIMx_CR1 address is the address of the control register 1, DBA is the DMA base \naddress configured in TIMx_DCR register, DMA index is automatically controlled by the \nDMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nITR1_RMP\nReserved\nrw\nrw\n" }, { "page_number": 650, "page_indices": { "start_index": 1289637, "end_index": 1290812 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 650 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.20 TIM5 option register (TIM5_OR)", 650 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n650/1757\nRM0090 Rev 21\n \n18.4.20 \nTIM5 option register (TIM5_OR)\nAddress offset: 0x50\nReset value: 0x0000\n \nBits 15:12 Reserved, must be kept at reset value.\nBits 11:10 ITR1_RMP: Internal trigger 1 remap\nSet and cleared by software.\n00: TIM8_TRGOUT\n01: PTP trigger output is connected to TIM2_ITR1\n10: OTG FS SOF is connected to the TIM2_ITR1 input\n11: OTG HS SOF is connected to the TIM2_ITR1 input\nBits 9:0 Reserved, must be kept at reset value.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTI4_RMP\nReserved\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value.\nBits 7:6 TI4_RMP: Timer Input 4 remap\nSet and cleared by software.\n00: TIM5 Channel4 is connected to the GPIO: Refer to the Alternate function mapping table \nin the datasheets.\n01: the LSI internal clock is connected to the TIM5_CH4 input for calibration purposes\n10: the LSE internal clock is connected to the TIM5_CH4 input for calibration purposes\n11: the RTC wake-up interrupt is connected to TIM5_CH4 input for calibration purposes. \nWake-up interrupt should be enabled. \nBits 5:0 Reserved, must be kept at reset value.\n" }, { "page_number": 651, "page_indices": { "start_index": 1290812, "end_index": 1292875 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 651 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.21 TIMx register map", 651 ] ], "page_content": "RM0090 Rev 21\n651/1757\nRM0090\nGeneral-purpose timers (TIM2 to TIM5)\n652\n18.4.21 \nTIMx register map\nTIMx registers are mapped as described in the table below: \n \nTable 101. TIM2 to TIM5 register map and reset values \nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nTIMx_CR1\nReserved\nCKD \n[1:0]\nARPE\nCMS\n[1:0]\nDIR\nOPM\nURS\nUDIS\nCEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nTIMx_CR2\nReserved\nTI1S\nMMS[2:0]\nCCDS\nReserved\nReset value\n0\n0\n0\n0\n0\n0x08\nTIMx_SMCR\nReserved\nETP\nECE\nETPS \n[1:0]\nETF[3:0]\nMSM\nTS[2:0]\nReserved\nSMS[2:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nTIMx_DIER\nReserved\nTDE\nCOMDE\nCC4DE\nCC3DE\nCC2DE\nCC1DE\nUDE\nReserved\nTIE\nReserved\nCC4IE\nCC3IE\nCC2IE\nCC1IE\nUIE\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nTIMx_SR\nReserved\nCC4OF\nCC3OF\nCC2OF\nCC1OF\nReserved\nTIF\nReserved\nCC4IF\nCC3IF\nCC2IF\nCC1IF\nUIF\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nTIMx_EGR\nReserved\nTG\nReserved\nCC4G\nCC3G\nCC2G\nCC1G\nUG\nReset value\n0\n0\n0\n0\n0\n0\n0x18\nTIMx_CCMR1\nOutput Compare \nmode\nReserved\nOC2CE\nOC2M\n[2:0]\nOC2PE\nOC2FE\nCC2S \n[1:0]\nOC1CE\nOC1M\n[2:0]\nOC1PE\nOC1FE\nCC1S \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTIMx_CCMR1\nInput Capture \nmode\nReserved\nIC2F[3:0]\nIC2\nPSC\n[1:0]\nCC2S \n[1:0]\nIC1F[3:0]\nIC1\nPSC\n[1:0]\nCC1S \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nTIMx_CCMR2\nOutput Compare \nmode\nReserved\nOC4CE\nOC4M\n[2:0]\nOC4PE\nOC4FE\nCC4S \n[1:0]\nOC3CE\nOC3M\n[2:0]\nOC3PE\nOC3FE\nCC3S \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTIMx_CCMR2\nInput Capture \nmode\nReserved\nIC4F[3:0]\nIC4\nPSC\n[1:0]\nCC4S \n[1:0]\nIC3F[3:0]\nIC3\nPSC\n[1:0]\nCC3S \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nTIMx_CCER\nReserved\nCC4NP\nReserved\nCC4P\nCC4E\nCC3NP\nReserved\nCC3P\nCC3E\nCC2NP\nReserved\nCC2P\nCC2E\nCC1NP\nReserved\nCC1P\nCC1E\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x24\nTIMx_CNT\nCNT[31:16]\n(TIM2 and TIM5 only, reserved on the other timers)\nCNT[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nTIMx_PSC\nReserved\nPSC[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n" }, { "page_number": 652, "page_indices": { "start_index": 1292875, "end_index": 1294346 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 652 }, "toc_details": [ [ 1, "18 General-purpose timers (TIM2 to TIM5)", 592 ], [ 2, "18.4 TIM2 to TIM5 registers", 630 ], [ 3, "18.4.21 TIMx register map", 651 ] ], "page_content": "General-purpose timers (TIM2 to TIM5)\nRM0090\n652/1757\nRM0090 Rev 21\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x2C\nTIMx_ARR\nARR[31:16]\n(TIM2 and TIM5 only, reserved on the other timers)\nARR[15:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x30\nReserved\n0x34\nTIMx_CCR1\nCCR1[31:16]\n(TIM2 and TIM5 only, reserved on the other timers)\nCCR1[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x38\nTIMx_CCR2\nCCR2[31:16]\n(TIM2 and TIM5 only, reserved on the other timers)\nCCR2[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x3C\nTIMx_CCR3\nCCR3[31:16]\n(TIM2 and TIM5 only, reserved on the other timers)\nCCR3[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x40\nTIMx_CCR4\nCCR4[31:16]\n(TIM2 and TIM5 only, reserved on the other timers)\nCCR4[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x44\nReserved\n0x48\nTIMx_DCR\nReserved\nDBL[4:0]\nReserved\nDBA[4:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x4C\nTIMx_DMAR\nReserved\nDMAB[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x50\nTIM2_OR\nReserved\nReserved\nITR1_\nRMP\nReserved\nReset value\n0\n0\n0x50\nTIM5_OR\nReserved\nReserved\nIT4_\nRMP\nReserved\nReset value\n0\n0\nTable 101. TIM2 to TIM5 register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 653, "page_indices": { "start_index": 1294346, "end_index": 1296003 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 653 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.1 TIM9 to TIM14 introduction", 653 ], [ 2, "19.2 TIM9 to TIM14 main features", 653 ], [ 3, "19.2.1 TIM9/TIM12 main features", 653 ] ], "page_content": "RM0090 Rev 21\n653/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19 \nGeneral-purpose timers (TIM9 to TIM14)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n19.1 \nTIM9 to TIM14 introduction\nThe TIM9 to TIM14 general-purpose timers consist of a 16-bit auto-reload counter driven by \na programmable prescaler.\nThey may be used for a variety of purposes, including measuring the pulse lengths of input \nsignals (input capture) or generating output waveforms (output compare, PWM).\nPulse lengths and waveform periods can be modulated from a few microseconds to several \nmilliseconds using the timer prescaler and the RCC clock controller prescalers.\nThe TIM9 to TIM14 timers are completely independent, and do not share any resources. \nThey can be synchronized together as described in Section 19.3.12.\n19.2 \nTIM9 to TIM14 main features\n19.2.1 \nTIM9/TIM12 main features\nThe features of the TIM9 to TIM14 general-purpose timers include:\n•\n16-bit auto-reload upcounter\n•\n16-bit programmable prescaler used to divide the counter clock frequency by any factor \nbetween 1 and 65536 (can be changed “on the fly”)\n•\nUp to 2 independent channels for:\n–\nInput capture\n–\nOutput compare\n–\nPWM generation (edge-aligned mode)\n–\nOne-pulse mode output\n•\nSynchronization circuit to control the timer with external signals and to interconnect \nseveral timers together\n•\nInterrupt generation on the following events:\n–\nUpdate: counter overflow, counter initialization (by software or internal trigger)\n–\nTrigger event (counter start, stop, initialization or count by internal trigger)\n–\nInput capture\n–\nOutput compare\n" }, { "page_number": 654, "page_indices": { "start_index": 1296003, "end_index": 1297391 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 654 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.2 TIM9 to TIM14 main features", 653 ], [ 3, "19.2.2 TIM10/TIM11 and TIM13/TIM14 main features", 654 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n654/1757\nRM0090 Rev 21\nFigure 180. General-purpose timer block diagram (TIM9 and TIM12) \n19.2.2 \nTIM10/TIM11 and TIM13/TIM14 main features\nThe features of general-purpose timers TIM10/TIM11 and TIM13/TIM14 include:\n•\n16-bit auto-reload upcounter\n•\n16-bit programmable prescaler used to divide the counter clock frequency by any factor \nbetween 1 and 65536 (can be changed “on the fly”)\n•\nindependent channel for:\n–\nInput capture\n–\nOutput compare\n–\nPWM generation (edge-aligned mode)\n–\nOne-pulse mode output\n•\nInterrupt generation on the following events:\n–\nUpdate: counter overflow, counter initialization (by software)\n–\nInput capture\n–\nOutput compare\nU\nU\nU\nCC1I\nCC2I\nTrigger\ncontroller\n+/-\nStop, Clear\nTI1FP1\nTI2FP2\nITR0\nITR1\nITR2\nTRGI\nOutput\ncontrol\nOC1REF\nOC2REF\nU\nUI\nReset, enable, up, count\nCK_PSC\nIC1\nIC2\nIC2PS\nIC1PS\nTI1FP1\nTGI\nTRC\nTRC\nITR\nTRC\nTI1F_ED\nCC1I\nCC2I\nTI1FP2\nTI2FP1\nTI2FP2\nTI1\nTI2\nTIMx_CH1\nTIMx_CH2\nOC1\nOC2\nTIMx_CH1\nTIMx_CH2\nSlave \ncontroller \nmode\nPSC\nprescaler\nCNT counter\nInternal clock (CK_INT)\nCK_CNT\nITR3\nai17190b\nInput filter & \nedge detector\nCapture/Compare 1 register\nNotes:\nReg\nPreload registers transferred\nto active registers on U event\naccording to control bit\nEvent\nInterrupt\nAuto-reload register\nCapture/Compare 2 register\nPrescaler\nPrescaler\nInput filter & \nedge detector\nOutput\ncontrol\n" }, { "page_number": 655, "page_indices": { "start_index": 1297391, "end_index": 1297973 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 655 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.2 TIM9 to TIM14 main features", 653 ], [ 3, "19.2.2 TIM10/TIM11 and TIM13/TIM14 main features", 654 ] ], "page_content": "RM0090 Rev 21\n655/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\nFigure 181. General-purpose timer block diagram (TIM10/11/13/14)\nAutoreload register\nCapture/Compare 1 register\nU\nU\nCC1I\nStop, Clear \noutput\ncontrol\nOC1\nOC1REF\nU\nUI\nIC1\nPrescaler\nInput filter &\nedge detector\nIC1PS\nTI1FP1\nReg\nevent\nNotes: \nPreload registers transferred\nto active registers on U event \naccording to control bit\ninterrupt & DMA output\nCC1I\nTI1\nTIMx_CH1\nprescaler\ncounter\n+/-\nCK_PSC\nPSC\nCNT\nCK_CNT\nInternal clock (CK_INT)\nai17725c\nTrigger\nController\nEnable\ncounter\nTIMx_CH1\n" }, { "page_number": 656, "page_indices": { "start_index": 1297973, "end_index": 1299939 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 656 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.1 Time-base unit", 656 ], [ 4, "Prescaler description", 656 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n656/1757\nRM0090 Rev 21\n19.3 \nTIM9 to TIM14 functional description\n19.3.1 \nTime-base unit\nThe main block of the timer is a 16-bit counter with its related auto-reload register. The \ncounters counts up. \nThe counter clock can be divided by a prescaler.\nThe counter, the auto-reload register and the prescaler register can be written or read by \nsoftware. This is true even when the counter is running.\nThe time-base unit includes:\n•\nCounter register (TIMx_CNT)\n•\nPrescaler register (TIMx_PSC)\n•\nAuto-reload register (TIMx_ARR)\nThe auto-reload register is preloaded. Writing to or reading from the auto-reload register \naccesses the preload register. The content of the preload register are transferred into the \nshadow register permanently or at each update event (UEV), depending on the auto-reload \npreload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter \nreaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be \ngenerated by software. The generation of the update event is described in details for each \nconfiguration.\nThe counter is clocked by the prescaler output CK_CNT, which is enabled only when the \ncounter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller \ndescription to get more details on counter enabling). \nNote that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 \nregister.\nPrescaler description\nThe prescaler can divide the counter clock frequency by any factor between 1 and 65536. It \nis based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). \nIt can be changed on the fly as this control register is buffered. The new prescaler ratio is \ntaken into account at the next update event.\nFigure 182 and Figure 183 give some examples of the counter behavior when the prescaler \nratio is changed on the fly.\n" }, { "page_number": 657, "page_indices": { "start_index": 1299939, "end_index": 1300646 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 657 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.1 Time-base unit", 656 ], [ 4, "Prescaler description", 656 ] ], "page_content": "RM0090 Rev 21\n657/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\nFigure 182. Counter timing diagram with prescaler division change from 1 to 2\nFigure 183. Counter timing diagram with prescaler division change from 1 to 4\nCK_PSC\n00\nCEN\n \nTimerclock = CK_CNT\n \n \nCounter register\nUpdate event (UEV)\n0\nPrescaler control register\n1\n0\nWrite a new value in TIMx_PSC\nPrescaler buffer\n1\n0\nPrescaler counter\n0\n1\n0\n1\n0\n1\n0\n1\n01\n02\n03\nFA\nFB\nF7\nF8\nF9\nFC\nMS31076V2\n0\n3\n0\n0\n1\n2\n3\n0\n1\n2\n3\nMS31077V2\nCK_PSC\nCEN\n \nTimerclock = CK_CNT\n \n \nCounter register\nUpdate event (UEV)\nPrescaler control register\nWrite a new value in TIMx_PSC\nPrescaler buffer\nPrescaler counter\n00\n01\nFA\nFB\nF7\nF8\nF9\nFC\n3\n0\n" }, { "page_number": 658, "page_indices": { "start_index": 1300646, "end_index": 1302459 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 658 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.2 Counter modes", 658 ], [ 4, "Upcounting mode", 658 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n658/1757\nRM0090 Rev 21\n19.3.2 \nCounter modes\nUpcounting mode\nIn upcounting mode, the counter counts from 0 to the auto-reload value (content of the \nTIMx_ARR register), then restarts from 0 and generates a counter overflow event.\nSetting the UG bit in the TIMx_EGR register (by software or by using the slave mode \ncontroller on TIM9 and TIM12) also generates an update event.\nThe UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 \nregister. This is to avoid updating the shadow registers while writing new values in the \npreload registers. Then no update event occurs until the UDIS bit has been written to 0. \nHowever, the counter restarts from 0, as well as the counter of the prescaler (but the \nprescale rate does not change). In addition, if the URS bit (update request selection) in \nTIMx_CR1 register is set, setting the UG bit generates an update event UEV but without \nsetting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and \ncapture interrupts when clearing the counter on the capture event.\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in \nTIMx_SR register) is set (depending on the URS bit):\n•\nThe auto-reload shadow register is updated with the preload value (TIMx_ARR),\n•\nThe buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC \nregister).\nThe following figures show some examples of the counter behavior for different clock \nfrequencies when TIMx_ARR=0x36.\nFigure 184. Counter timing diagram, internal clock divided by 1\n00\n02\n03\n04\n05\n06\n07\n33\n34\n35\n36\n31\nMS31078V3\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n01\n32\n" }, { "page_number": 659, "page_indices": { "start_index": 1302459, "end_index": 1303178 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 659 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.2 Counter modes", 658 ], [ 4, "Upcounting mode", 658 ] ], "page_content": "RM0090 Rev 21\n659/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\nFigure 185. Counter timing diagram, internal clock divided by 2\nFigure 186. Counter timing diagram, internal clock divided by 4\nFigure 187. Counter timing diagram, internal clock divided by N\nMS31079V3\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n0034\n0035\n0036\n0000\n0001\n0002\n0003\nMS31080V3\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n0000\n0001\n0035\n0036\nMS31081V3\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n1F\n20\n" }, { "page_number": 660, "page_indices": { "start_index": 1303178, "end_index": 1303932 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 660 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.2 Counter modes", 658 ], [ 4, "Upcounting mode", 658 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n660/1757\nRM0090 Rev 21\nFigure 188. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not \npreloaded)\nFigure 189. Counter timing diagram, update event when ARPE=1 (TIMx_ARR \npreloaded)\nFF\n36\nMS31082V3\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n02\n03\n04\n05\n06\n07\n32\n33\n34\n35\n36\n31\n01\nCEN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\nMS31083V2\nF5\n36\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag\n (UIF)\n00\n02\n03\n04\n05\n06\n07\nF1\nF2\nF3\nF4\nF5\nF0\n01\nCEN\nAuto-reload preload\nregister\nWrite a new value in TIMx_ARR\nAuto-reload shadow\nregister\nF5\n36\n" }, { "page_number": 661, "page_indices": { "start_index": 1303932, "end_index": 1305418 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 661 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.3 Clock selection", 661 ], [ 4, "Internal clock source (CK_INT)", 661 ], [ 4, "External clock source mode 1(TIM9 and TIM12)", 661 ] ], "page_content": "RM0090 Rev 21\n661/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.3.3 \nClock selection\nThe counter clock can be provided by the following clock sources:\n•\nInternal clock (CK_INT)\n•\nExternal clock mode1 (for TIM9 and TIM12): external input pin (TIx) \n•\nInternal trigger inputs (ITRx) (for TIM9 and TIM12): connecting the trigger output from \nanother timer. Refer to Using one timer as prescaler for another timer for more details.\nInternal clock source (CK_INT)\nThe internal clock source is the default clock source for TIM10/TIM11 and TIM13/TIM14. \nFor TIM9 and TIM12, the internal clock source is selected when the slave mode controller is \ndisabled (SMS=’000’). The CEN bit in the TIMx_CR1 register and the UG bit in the \nTIMx_EGR register are then used as control bits and can be changed only by software \n(except for UG which remains cleared). As soon as the CEN bit is programmed to 1, the \nprescaler is clocked by the internal clock CK_INT. \nFigure 190 shows the behavior of the control circuit and of the upcounter in normal mode, \nwithout prescaler.\nFigure 190. Control circuit in normal mode, internal clock divided by 1\nExternal clock source mode 1(TIM9 and TIM12)\nThis mode is selected when SMS=’111’ in the TIMx_SMCR register. The counter can count \nat each rising or falling edge on a selected input.\nInternal clock\nCounter clock = CK_CNT = CK_PSC\nCounter register\nCEN=CNT_EN\nUG\nCNT_INIT\nMS31085V2\n00\n02\n03\n04\n05\n06\n07\n3 2\n33\n34\n35 36\n31\n01\n" }, { "page_number": 662, "page_indices": { "start_index": 1305418, "end_index": 1307022 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 662 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.3 Clock selection", 661 ], [ 4, "External clock source mode 1(TIM9 and TIM12)", 661 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n662/1757\nRM0090 Rev 21\nFigure 191. TI2 external clock connection example\nFor example, to configure the upcounter to count in response to a rising edge on the TI2 \ninput, use the following procedure:\n1.\nConfigure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in \nthe TIMx_CCMR1 register.\n2. \nConfigure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 \nregister (if no filter is needed, keep IC2F=’0000’).\n3. \nSelect the rising edge polarity by writing CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER \nregister.\n4. \nConfigure the timer in external clock mode 1 by writing SMS=’111’ in the TIMx_SMCR \nregister. \n5. \nSelect TI2 as the trigger input source by writing TS=’110’ in the TIMx_SMCR register.\n6. \nEnable the counter by writing CEN=’1’ in the TIMx_CR1 register.\nNote:\nThe capture prescaler is not used for triggering, so no need to configure it.\nWhen a rising edge occurs on TI2, the counter counts once and the TIF flag is set.\nThe delay between the rising edge on TI2 and the actual clock of the counter is due to the \nresynchronization circuit on TI2 input.\nFigure 192. Control circuit in external clock mode 1\nExternal clock \nmode 1\nInternal clock\nmode\nTRGI\nCK_INT\nCK_PSC\nTIMx_SMCR\nSMS[2:0]\nITRx\nTI1_ED\nTI1FP1\nTI2FP2\nTIMx_SMCR\nTS[2:0]\nTI2\n0\n1\nTIMx_CCER\nCC2P\nFilter\nICF[3:0]\nTIMx_CCMR1\nEdge\ndetector\nTI2F_Rising\nTI2F_Falling\n110\n0xx\n100\n101\nMS37337V1\n(internal clock)\nTI1F\nor\nTI2F\nor\nor\nCounter clock = CK_CNT = CK_PSC\nCounter register\n35\n36\n34\nTI2\nCNT_EN\nTIF\nWrite TIF = 0\nMS31087V3\n" }, { "page_number": 663, "page_indices": { "start_index": 1307022, "end_index": 1308355 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 663 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.4 Capture/compare channels", 663 ] ], "page_content": "RM0090 Rev 21\n663/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.3.4 \nCapture/compare channels\nEach Capture/Compare channel is built around a capture/compare register (including a \nshadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and \nan output stage (with comparator and output control).\nFigure 193 to Figure 195 give an overview of a capture/compare channel.\nThe input stage samples the corresponding TIx input to generate a filtered signal TIxF. \nThen, an edge detector with polarity selection generates a signal (TIxFPx) which can be \nused as trigger input by the slave mode controller or as the capture command. It is \nprescaled before the capture register (ICxPS).\nFigure 193. Capture/compare channel (example: channel 1 input stage)\nThe output stage generates an intermediate waveform which is then used for reference: \nOCxRef (active high). The polarity acts at the end of the chain.\n0\n1\nDivider\n/1, /2, /4, /8\nICPS[1:0]\nTI1F_ED\nTo the slave mode controller\nTI1FP1\n11\n01\nCC1S[1:0]\nIC1\nTI2FP1\nTRC\n(from slave mode\ncontroller)\n10\nIC1PS\n0\n1\nMS33115V1\nTI1\nTIMx_CCER\nCC1P/CC1NP\nFilter\ndowncounter\nICF[3:0]\nTIMx_CCMR1\nEdge\ndetector\nTI1F_Rising\nTI1F_Falling\nTIMx_CCMR1\nTIMx_CCER\nTI2F_Rising\n(from channel 2)\nTI2F_Falling\n(from channel 2)\nTI1F\nf\nCC1E\nDTS\n" }, { "page_number": 664, "page_indices": { "start_index": 1308355, "end_index": 1310018 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 664 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.5 Input capture mode", 664 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n664/1757\nRM0090 Rev 21\nFigure 194. Capture/compare channel 1 main circuit\nFigure 195. Output stage of capture/compare channel (channel 1)\nThe capture/compare block is made of one preload register and one shadow register. Write \nand read always access the preload register. \nIn capture mode, captures are actually done in the shadow register, which is copied into the \npreload register. \nIn compare mode, the content of the preload register is copied into the shadow register \nwhich is compared to the counter.\n19.3.5 \nInput capture mode\nIn Input capture mode, the Capture/Compare registers (TIMx_CCRx) are used to latch the \nvalue of the counter after a transition detected by the corresponding ICx signal. When a \ncapture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or \na DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was \nalready high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be \nMS31089V3\nCC1E\nCapture/compare shadow register\nComparator\nCapture/compare preload register\nCounter\nIC1PS\nCC1S[0]\nCC1S[1]\nCapture\nInput \nmode\nS\nR\nRead CCR1H\nRead CCR1L\nread_in_progress\ncapture_transfer\nCC1S[0]\nCC1S[1]\nS\nR\nwrite CCR1H\nwrite CCR1L\nwrite_in_progress\nOutput \nmode\nUEV\nOC1PE\n(from time \nbase unit)\ncompare_transfer\nAPB Bus\n8\n8\nhigh\nlow\n(if 16-bit)\nMCU-peripheral interface\nTIMx_CCMR1\nOC1PE\nCNT>CCR1\nCNT=CCR1\nTIMx_EGR\nCC1G\nai17720\nOutput \nmode\ncontroller\nCNT > CCR2\nCNT = CCR2\nTIMx_CCMR1\nOC2M[2:0]\n0\n1\nCC1P\nTIMx_CCER\nOutput\nenable\ncircuit\nOC1\nCC1E TIMx_CCER\nTo the master \nmode controller\nOC1_REF\n" }, { "page_number": 665, "page_indices": { "start_index": 1310018, "end_index": 1312459 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 665 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.5 Input capture mode", 664 ] ], "page_content": "RM0090 Rev 21\n665/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\ncleared by software by writing it to ‘0’ or by reading the captured data stored in the \nTIMx_CCRx register. CCxOF is cleared when the user writes it to ‘0’.\nThe following example shows how to capture the counter value in TIMx_CCR1 when TI1 \ninput rises. To do this, use the following procedure:\n1.\nSelect the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S \nbits to ‘01’ in the TIMx_CCMR1 register. As soon as CC1S becomes different from ‘00’, \nthe channel is configured in input mode and the TIMx_CCR1 register becomes read-\nonly.\n2. \nProgram the needed input filter duration with respect to the signal connected to the \ntimer (by programming the ICxF bits in the TIMx_CCMRx register if the input is one of \nthe TIx inputs). Let us imagine that, when toggling, the input signal is not stable during \nat least five internal clock cycles. We must program a filter duration longer than these 5 \nclock cycles. We can validate a transition on TI1 when eight consecutive samples with \nthe new level have been detected (sampled at fDTS frequency). Then write IC1F bits to \n‘0011’ in the TIMx_CCMR1 register.\n3. \nSelect the edge of the active transition on the TI1 channel by programming CC1P and \nCC1NP bits to ‘00’ in the TIMx_CCER register (rising edge in this case).\n4. \nProgram the input prescaler. In our example, we wish the capture to be performed at \neach valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the \nTIMx_CCMR1 register).\n5. \nEnable capture from the counter into the capture register by setting the CC1E bit in the \nTIMx_CCER register.\n6. \nIf needed, enable the related interrupt request by setting the CC1IE bit in the \nTIMx_DIER register.\nWhen an input capture occurs:\n•\nThe TIMx_CCR1 register gets the value of the counter on the active transition.\n•\nCC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures \noccurred whereas the flag was not cleared.\n•\nAn interrupt is generated depending on the CC1IE bit.\nIn order to handle the overcapture, it is recommended to read the data before the \novercapture flag. This is to avoid missing an overcapture which could happen after reading \nthe flag and before reading the data.\nNote:\nIC interrupt requests can be generated by software by setting the corresponding CCxG bit in \nthe TIMx_EGR register.\n" }, { "page_number": 666, "page_indices": { "start_index": 1312459, "end_index": 1314388 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 666 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.6 PWM input mode (only for TIM9/12)", 666 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n666/1757\nRM0090 Rev 21\n19.3.6 \nPWM input mode (only for TIM9/12)\nThis mode is a particular case of input capture mode. The procedure is the same except:\n•\nTwo ICx signals are mapped on the same TIx input.\n•\nThese 2 ICx signals are active on edges with opposite polarity.\n•\nOne of the two TIxFP signals is selected as trigger input and the slave mode controller \nis configured in reset mode.\nFor example, the user can measure the period (in TIMx_CCR1 register) and the duty cycle \n(in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure \n(depending on CK_INT frequency and prescaler value):\n1.\nSelect the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1 \nregister (TI1 selected).\n2. \nSelect the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter \nclear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge).\n3. \nSelect the active input for TIMx_CCR2: write the CC2S bits to ‘10’ in the TIMx_CCMR1 \nregister (TI1 selected).\n4. \nSelect the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P \nbit to '1' and the CC2NP bit to '0' (active on falling edge).\n5. \nSelect the valid trigger input: write the TS bits to ‘101’ in the TIMx_SMCR register \n(TI1FP1 selected).\n6. \nConfigure the slave mode controller in reset mode: write the SMS bits to ‘100’ in the \nTIMx_SMCR register.\n7. \nEnable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.\nFigure 196. PWM input mode timing\n1.\nThe PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only \nTI1FP1 and TI2FP2 are connected to the slave mode controller.\nTI1\nTIMx_CNT\n0000\n0001\n0002\n0003\n0004\n0000\n0004\nTIMx_CCR1\nTIMx_CCR2\n0004\n0002\nIC1 capture\nIC2 capture\nreset counter\nIC2 capture\npu\nl se wid th\n \nIC1 capture\nperiod\nmeasurement\nmeasurement\nai15413\n" }, { "page_number": 667, "page_indices": { "start_index": 1314388, "end_index": 1317098 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 667 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.7 Forced output mode", 667 ], [ 3, "19.3.8 Output compare mode", 667 ] ], "page_content": "RM0090 Rev 21\n667/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.3.7 \nForced output mode\nIn output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal \n(OCxREF and then OCx) can be forced to active or inactive level directly by software, \nindependently of any comparison between the output compare register and the counter.\nTo force an output compare signal (OCXREF/OCx) to its active level, the user just needs to \nwrite ‘101’ in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is \nforced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity \nbit.\nFor example: CCxP=’0’ (OCx active high) => OCx is forced to high level.\nThe OCxREF signal can be forced low by writing the OCxM bits to ‘100’ in the \nTIMx_CCMRx register.\nAnyway, the comparison between the TIMx_CCRx shadow register and the counter is still \nperformed and allows the flag to be set. Interrupt requests can be sent accordingly. This is \ndescribed in the output compare mode section below.\n19.3.8 \nOutput compare mode\nThis function is used to control an output waveform or indicating when a period of time has \nelapsed.\nWhen a match is found between the capture/compare register and the counter, the output \ncompare function: \n1.\nAssigns the corresponding output pin to a programmable value defined by the output \ncompare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP \nbit in the TIMx_CCER register). The output pin can keep its level (OCXM=’000’), be set \nactive (OCxM=’001’), be set inactive (OCxM=’010’) or can toggle (OCxM=’011’) on \nmatch.\n2. \nSets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).\n3. \nGenerates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the \nTIMx_DIER register).\nThe TIMx_CCRx registers can be programmed with or without preload registers using the \nOCxPE bit in the TIMx_CCMRx register.\nIn output compare mode, the update event UEV has no effect on OCxREF and OCx output. \nThe timing resolution is one count of the counter. Output compare mode can also be used to \noutput a single pulse (in One-pulse mode).\nProcedure:\n1.\nSelect the counter clock (internal, external, prescaler).\n2. \nWrite the desired data in the TIMx_ARR and TIMx_CCRx registers.\n3. \nSet the CCxIE bit if an interrupt request is to be generated.\n4. \nSelect the output mode. For example:\n–\nWrite OCxM = ‘011’ to toggle OCx output pin when CNT matches CCRx\n–\nWrite OCxPE = ‘0’ to disable preload register\n–\nWrite CCxP = ‘0’ to select active high polarity\n–\nWrite CCxE = ‘1’ to enable the output\n5. \nEnable the counter by setting the CEN bit in the TIMx_CR1 register.\n" }, { "page_number": 668, "page_indices": { "start_index": 1317098, "end_index": 1319158 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 668 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.9 PWM mode", 668 ], [ 4, "PWM edge-aligned mode", 668 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n668/1757\nRM0090 Rev 21\nThe TIMx_CCRx register can be updated at any time by software to control the output \nwaveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx \nshadow register is updated only at the next update event UEV). An example is given in \nFigure 197.\nFigure 197. Output compare mode, toggle on OC1.\n19.3.9 \nPWM mode\nPulse Width Modulation mode allows the user to generate a signal with a frequency \ndetermined by the value of the TIMx_ARR register and a duty cycle determined by the value \nof the TIMx_CCRx register.\nThe PWM mode can be selected independently on each channel (one PWM per OCx \noutput) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the \nTIMx_CCMRx register. Enable the corresponding preload register by setting the OCxPE bit \nin the TIMx_CCMRx register, and eventually the auto-reload preload register by setting the \nARPE bit in the TIMx_CR1 register.\nAs the preload registers are transferred to the shadow registers only when an update event \noccurs, before starting the counter, the user has to initialize all the registers by setting the \nUG bit in the TIMx_EGR register.\nThe OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. \nIt can be programmed as active high or active low. The OCx output is enabled by the CCxE \nbit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more \ndetails.\nIn PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine \nwhether TIMx_CNT ≤TIMx_CCRx.\nThe timer is able to generate PWM in edge-aligned mode only since the counter is \nupcounting.\nPWM edge-aligned mode\nIn the following example, we consider PWM mode 1. The reference PWM signal OCxREF is \nhigh as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in \nMS31092V2\nOC1REF= OC1\nTIM1_CNT\nB200\nB201\n0039\nTIM1_CCR1\n003A\nWrite B201h in the CC1R register\nMatch detected on CCR1\nInterrupt generated if enabled\n003B\nB201\n003A\n" }, { "page_number": 669, "page_indices": { "start_index": 1319158, "end_index": 1320436 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 669 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.10 One-pulse mode", 669 ] ], "page_content": "RM0090 Rev 21\n669/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\nTIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at \n‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 198 shows some edge-\naligned PWM waveforms in an example where TIMx_ARR=8.\nFigure 198. Edge-aligned PWM waveforms (ARR=8)\n19.3.10 \nOne-pulse mode\nOne-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to \nbe started in response to a stimulus and to generate a pulse with a programmable length \nafter a programmable delay.\nStarting the counter can be controlled through the slave mode controller. Generating the \nwaveform can be done in output compare mode or PWM mode. Select One-pulse mode by \nsetting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at \nthe next update event UEV.\nA pulse can be correctly generated only if the compare value is different from the counter \ninitial value. Before starting (when the timer is waiting for the trigger), the configuration must \nbe as follows:\nCNT < CCRx≤ARR (in particular, 0 < CCRx)\nMS31093V1\nCounter register\n‘1’\n0\n1\n2\n3\n4\n5\n6\n7\n8\n0\n1\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nOCXREF\nCCxIF\nCCRx=4\nCCRx=8\nCCRx>8\nCCRx=0\n‘0’\n" }, { "page_number": 670, "page_indices": { "start_index": 1320436, "end_index": 1322522 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 670 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.10 One-pulse mode", 669 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n670/1757\nRM0090 Rev 21\nFigure 199. Example of one pulse mode.\nFor example the user may want to generate a positive pulse on OC1 with a length of tPULSE \nand after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.\nUse TI2FP2 as trigger 1:\n1.\nMap TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.\n2. \nTI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP = ‘0’ in the TIMx_CCER \nregister.\n3. \nConfigure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in \nthe TIMx_SMCR register.\n4. \nTI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register \n(trigger mode).\nThe OPM waveform is defined by writing the compare registers (taking into account the \nclock frequency and the counter prescaler).\n•\nThe tDELAY is defined by the value written in the TIMx_CCR1 register.\n•\nThe tPULSE is defined by the difference between the auto-reload value and the compare \nvalue (TIMx_ARR - TIMx_CCR1).\n•\nLet us say the user wants to build a waveform with a transition from ‘0’ to ‘1’ when a \ncompare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the \nauto-reload value. To do this enable PWM mode 2 by writing OC1M=’111’ in the \nTIMx_CCMR1 register. The user can optionally enable the preload registers by writing \nOC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this \ncase the user has to write the compare value in the TIMx_CCR1 register, the auto-\nreload value in the TIMx_ARR register, generate an update by setting the UG bit and \nwait for external trigger event on TI2. CC1P is written to ‘0’ in this example.\nThe user only wants one pulse (Single mode), so write '1 in the OPM bit in the TIMx_CR1 \nregister to stop the counter at the next update event (when the counter rolls over from the \nauto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the \nRepetitive mode is selected.\nMS31099V1\nTI2\nOC1REF\nCounter\nt\n0\nTIM1_ARR\nTIM1_CCR1\nOC1\ntDELAY\ntPULSE\n" }, { "page_number": 671, "page_indices": { "start_index": 1322522, "end_index": 1325063 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 671 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.11 TIM9/12 external trigger synchronization", 671 ], [ 4, "Slave mode: Reset mode", 671 ] ], "page_content": "RM0090 Rev 21\n671/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\nParticular case: OCx fast enable\nIn One-pulse mode, the edge detection on TIx input set the CEN bit which enables the \ncounter. Then the comparison between the counter and the compare value makes the \noutput toggle. But several clock cycles are needed for these operations and it limits the \nminimum delay tDELAY min we can get.\nIf the user wants to output a waveform with the minimum delay, set the OCxFE bit in the \nTIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, \nwithout taking in account the comparison. Its new level is the same as if a compare match \nhad occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.\n19.3.11 \nTIM9/12 external trigger synchronization\nThe TIM9/12 timers can be synchronized with an external trigger in several modes: Reset \nmode, Gated mode and Trigger mode.\nSlave mode: Reset mode\nThe counter and its prescaler can be reinitialized in response to an event on a trigger input. \nMoreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is \ngenerated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.\nIn the following example, the upcounter is cleared in response to a rising edge on TI1 input:\n1.\nConfigure the channel 1 to detect rising edges on TI1. Configure the input filter duration \n(in this example, no need of any filter, IC1F = 0000 kept). The capture prescaler is not \nused for triggering, so there’s no need to configure it. The CC1S bits select the input \ncapture source only, CC1S = ‘01’ in the TIMx_CCMR1 register. Program CC1P and \nCC1NP to ‘00’ in TIMx_CCER register to validate the polarity (and detect rising edges \nonly).\n2. \nConfigure the timer in reset mode by writing SMS=’100’ in TIMx_SMCR register. Select \nTI1 as the input source by writing TS=’101’ in TIMx_SMCR register.\n3. \nStart the counter by writing CEN=’1’ in the TIMx_CR1 register.\nThe counter starts counting on the internal clock, then behaves normally until TI1 rising \nedge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the \ntrigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request can be sent if \nenabled (depending on the TIE bit in TIMx_DIER register).\nThe following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. \nThe delay between the rising edge on TI1 and the actual reset of the counter is due to the \nresynchronization circuit on TI1 input.\n" }, { "page_number": 672, "page_indices": { "start_index": 1325063, "end_index": 1326561 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 672 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.11 TIM9/12 external trigger synchronization", 671 ], [ 4, "Slave mode: Gated mode", 672 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n672/1757\nRM0090 Rev 21\nFigure 200. Control circuit in reset mode\nSlave mode: Gated mode\nThe counter can be enabled depending on the level of a selected input.\nIn the following example, the upcounter counts only when TI1 input is low:\n1.\nConfigure the channel 1 to detect low levels on TI1. Configure the input filter duration \n(in this example, no need of any filter, IC1F=’0000’ kept). The capture prescaler is not \nused for triggering, so there’s no need to configure it. The CC1S bits select the input \ncapture source only, CC1S=’01’ in TIMx_CCMR1 register. Program CC1P=’1’ and \nCC1NP= ‘0’ in TIMx_CCER register to validate the polarity (and detect low level only).\n2. \nConfigure the timer in gated mode by writing SMS=’101’ in TIMx_SMCR register. \nSelect TI1 as the input source by writing TS=’101’ in TIMx_SMCR register.\n3. \nEnable the counter by writing CEN=’1’ in the TIMx_CR1 register (in gated mode, the \ncounter does not start if CEN=’0’, whatever is the trigger input level).\nThe counter starts counting on the internal clock as long as TI1 is low and stops as soon as \nTI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts \nor stops.\nThe delay between the rising edge on TI1 and the actual stop of the counter is due to the \nresynchronization circuit on TI1 input.\nMS31401V2\n00\nCounter clock = ck_cnt = ck_psc\nCounter register\n01 02 03\n00\n01 02 03\n32\n33\n34\n35\n36\nUG\nTI1\n31\n30\nTIF\n" }, { "page_number": 673, "page_indices": { "start_index": 1326561, "end_index": 1327983 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 673 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.11 TIM9/12 external trigger synchronization", 671 ], [ 4, "Slave mode: Trigger mode", 673 ] ], "page_content": "RM0090 Rev 21\n673/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\nFigure 201. Control circuit in gated mode\nSlave mode: Trigger mode\nThe counter can start in response to an event on a selected input.\nIn the following example, the upcounter starts in response to a rising edge on TI2 input:\n1.\nConfigure the channel 2 to detect rising edges on TI2. Configure the input filter duration \n(in this example, no need of any filter, IC2F=’0000’ kept). The capture prescaler is not \nused for triggering, so there’s no need to configure it. The CC2S bits are configured to \nselect the input capture source only, CC2S=’01’ in TIMx_CCMR1 register. Program \nCC2P=’1’ and CC2NP=’0’ in TIMx_CCER register to validate the polarity (and detect \nlow level only).\n2. \nConfigure the timer in trigger mode by writing SMS=’110’ in TIMx_SMCR register. \nSelect TI2 as the input source by writing TS=’110’ in TIMx_SMCR register.\nWhen a rising edge occurs on TI2, the counter starts counting on the internal clock and the \nTIF flag is set.\nThe delay between the rising edge on TI2 and the actual start of the counter is due to the \nresynchronization circuit on TI2 input.\nFigure 202. Control circuit in trigger mode\nMS31402V1\nTI1\ncnt_en\nWrite TIF=0\n37\nCounter clock = ck_cnt = ck_psc\nCounter register\n38\n32\n33\n34\n35\n36\n31\n30\nTIF\nMS31403V1\nTI2\ncnt_en\n37\nCounter clock = ck_cnt = ck_psc\nCounter register\n38\n34\n35\n36\nTIF\n" }, { "page_number": 674, "page_indices": { "start_index": 1327983, "end_index": 1328764 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 674 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.3 TIM9 to TIM14 functional description", 656 ], [ 3, "19.3.12 Timer synchronization (TIM9/12)", 674 ], [ 3, "19.3.13 Debug mode", 674 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n674/1757\nRM0090 Rev 21\n19.3.12 \nTimer synchronization (TIM9/12)\nThe TIM timers are linked together internally for timer synchronization or chaining. Refer to \nSection 18.3.15: Timer synchronization for details.\nNote:\nThe clock of the slave timer must be enabled prior to receive events from the master timer, \nand must not be changed on-the-fly while triggers are received from the master timer.\n19.3.13 \nDebug mode\nWhen the microcontroller enters debug mode (Cortex®-M4 with FPU core halted), the TIMx \ncounter either continues to work normally or stops, depending on DBG_TIMx_STOP \nconfiguration bit in DBG module. For more details, refer to Section 38.16.2: Debug support \nfor timers, watchdog, bxCAN and I2C.\n" }, { "page_number": 675, "page_indices": { "start_index": 1328764, "end_index": 1330831 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 675 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.4 TIM9 and TIM12 registers", 675 ], [ 3, "19.4.1 TIM9/12 control register 1 (TIMx_CR1)", 675 ] ], "page_content": "RM0090 Rev 21\n675/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.4 \nTIM9 and TIM12 registers\nRefer to Section 2.2 for a list of abbreviations used in register descriptions.\nThe peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read \naccesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). \n19.4.1 \nTIM9/12 control register 1 (TIMx_CR1)\nAddress offset: 0x00\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCKD[1:0]\nARPE\nReserved\nOPM\nURS\nUDIS\nCEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:10 Reserved, must be kept at reset value.\nBits 9:8 CKD: Clock division\nThis bit-field indicates the division ratio between the timer clock (CK_INT) frequency and \nsampling clock used by the digital filters (TIx),\n00: tDTS = tCK_INT\n01: tDTS = 2 × tCK_INT\n10: tDTS = 4 × tCK_INT\n11: Reserved\nBit 7 ARPE: Auto-reload preload enable\n0: TIMx_ARR register is not buffered.\n1: TIMx_ARR register is buffered.\nBits 6:4 Reserved, must be kept at reset value.\nBit 3 OPM: One-pulse mode\n0: Counter is not stopped on the update event\n1: Counter stops counting on the next update event (clearing the CEN bit).\nBit 2 URS: Update request source\nThis bit is set and cleared by software to select the UEV event sources.\n0: Any of the following events generates an update interrupt if enabled:\n–\nCounter overflow\n–\nSetting the UG bit\n1: Only counter overflow generates an update interrupt if enabled.\nBit 1 UDIS: Update disable\nThis bit is set and cleared by software to enable/disable update event (UEV) generation.\n0: UEV enabled. An UEV is generated by one of the following events:\n–\nCounter overflow\n–\nSetting the UG bit\nBuffered registers are then loaded with their preload values.\n1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, \nCCRx). The counter and the prescaler are reinitialized if the UG bit is set.\nBit 0 CEN: Counter enable\n0: Counter disabled\n1: Counter enabled\nCEN is cleared automatically in one-pulse mode, when an update event occurs.\n" }, { "page_number": 676, "page_indices": { "start_index": 1330831, "end_index": 1332024 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 676 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.4 TIM9 and TIM12 registers", 675 ], [ 3, "19.4.2 TIM9/12 slave mode control register (TIMx_SMCR)", 676 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n676/1757\nRM0090 Rev 21\n19.4.2 \nTIM9/12 slave mode control register (TIMx_SMCR)\nAddress offset: 0x08\nReset value: 0x0000\n \n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMSM\nTS[2:0]\nRes.\nSMS[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 MSM: Master/Slave mode\n0: No action\n1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect \nsynchronization between the current timer and its slaves (through TRGO). It is useful in \norder to synchronize several timers on a single external event.\nBits 6:4 TS: Trigger selection\nThis bit field selects the trigger input to be used to synchronize the counter.\n000: Internal Trigger 0 (ITR0)\n001: Internal Trigger 1 (ITR1)\n010: Internal Trigger 2 (ITR2)\n011: Internal Trigger 3 (ITR3)\n100: TI1 Edge Detector (TI1F_ED)\n101: Filtered Timer Input 1 (TI1FP1)\n110: Filtered Timer Input 2 (TI2FP2)\n111: Reserved.\nSee Table 102 for more details on the meaning of ITRx for each timer.\nNote: These bits must be changed only when they are not used (e.g. when SMS=’000’) to \navoid wrong edge detections at the transition.\n" }, { "page_number": 677, "page_indices": { "start_index": 1332024, "end_index": 1334122 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 677 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.4 TIM9 and TIM12 registers", 675 ], [ 3, "19.4.3 TIM9/12 Interrupt enable register (TIMx_DIER)", 677 ] ], "page_content": "RM0090 Rev 21\n677/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n \n19.4.3 \nTIM9/12 Interrupt enable register (TIMx_DIER)\nAddress offset: 0x0C\nReset value: 0x0000\n \nBit 3 Reserved, must be kept at reset value.\nBits 2:0 SMS: Slave mode selection\nWhen external signals are selected, the active edge of the trigger signal (TRGI) is linked to \nthe polarity selected on the external input (see Input control register and Control register \ndescriptions.\n000: Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal \nclock\n001: Reserved\n010: Reserved\n011: Reserved\n100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter \nand generates an update of the registers\n101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The \ncounter stops (but is not reset) as soon as the trigger becomes low. Counter starts and stops \nare both controlled\n110: Trigger mode - The counter starts on a rising edge of the trigger TRGI (but it is not \nreset). Only the start of the counter is controlled\n111: External clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter\nNote: The Gated mode must not be used if TI1F_ED is selected as the trigger input \n(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the \nGated mode checks the level of the trigger signal.\nNote: The clock of the slave timer must be enabled prior to receive events from the master \ntimer, and must not be changed on-the-fly while triggers are received from the master \ntimer.\nTable 102. TIMx internal trigger connection\nSlave TIM\nITR0 (TS = 000)\nITR1 (TS = 001)\nITR2 (TS = 010)\nITR3 (TS = 011)\nTIM9\nTIM2_TRGO\nTIM3_TRGO\nTIM10_OC\nTIM11_OC\nTIM12\nTIM4_TRGO\nTIM5_TRGO\nTIM13_OC\nTIM14_OC\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTIE\nRes\nCC2IE\nCC1IE\nUIE\nrw\nrw\nrw\nrw\nBits 15:7\nReserved, must be kept at reset value.\nBit 6 TIE: Trigger interrupt enable\n0: Trigger interrupt disabled.\n1: Trigger interrupt enabled.\nBit 5:3\nReserved, must be kept at reset value.\n" }, { "page_number": 678, "page_indices": { "start_index": 1334122, "end_index": 1334509 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 678 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.4 TIM9 and TIM12 registers", 675 ], [ 3, "19.4.3 TIM9/12 Interrupt enable register (TIMx_DIER)", 677 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n678/1757\nRM0090 Rev 21\nBit 2 CC2IE: Capture/Compare 2 interrupt enable\n0: CC2 interrupt disabled.\n1: CC2 interrupt enabled.\nBit 1 CC1IE: Capture/Compare 1 interrupt enable\n0: CC1 interrupt disabled.\n1: CC1 interrupt enabled.\nBit 0 UIE: Update interrupt enable\n0: Update interrupt disabled.\n1: Update interrupt enabled.\n" }, { "page_number": 679, "page_indices": { "start_index": 1334509, "end_index": 1336525 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 679 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.4 TIM9 and TIM12 registers", 675 ], [ 3, "19.4.4 TIM9/12 status register (TIMx_SR)", 679 ] ], "page_content": "RM0090 Rev 21\n679/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.4.4 \nTIM9/12 status register (TIMx_SR)\nAddress offset: 0x10\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCC2OF CC1OF\nReserved\nTIF\nReserved\nCC2IF\nCC1IF\nUIF\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nBits 15:11\nReserved, must be kept at reset value.\nBit 10 CC2OF: Capture/compare 2 overcapture flag\nrefer to CC1OF description\nBit 9 CC1OF: Capture/Compare 1 overcapture flag\nThis flag is set by hardware only when the corresponding channel is configured in input \ncapture mode. It is cleared by software by writing it to ‘0’.\n0: No overcapture has been detected.\n1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was \nalready set\nBits 8:7\nReserved, must be kept at reset value.\nBit 6 TIF: Trigger interrupt flag\nThis flag is set by hardware on trigger event (active edge detected on TRGI input when the \nslave mode controller is enabled in all modes but gated mode. It is set when the counter \nstarts or stops when gated mode is selected. It is cleared by software.\n0: No trigger event occurred.\n1: Trigger interrupt pending.\nBits 5:3\nReserved, must be kept at reset value.\nBit 2 CC2IF: Capture/Compare 2 interrupt flag\nrefer to CC1IF description\nBit 1 CC1IF: Capture/compare 1 interrupt flag\nIf channel CC1 is configured as output:\nThis flag is set by hardware when the counter matches the compare value. It is cleared by \nsoftware.\n0: No match.\n1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. \nWhen the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF \nbit goes high on the counter overflow.\nIf channel CC1 is configured as input:\nThis bit is set by hardware on a capture. It is cleared by software or by reading the \nTIMx_CCR1 register.\n0: No input capture occurred.\n1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected \non IC1 which matches the selected polarity).\n" }, { "page_number": 680, "page_indices": { "start_index": 1336525, "end_index": 1338587 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 680 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.4 TIM9 and TIM12 registers", 675 ], [ 3, "19.4.5 TIM9/12 event generation register (TIMx_EGR)", 680 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n680/1757\nRM0090 Rev 21\n19.4.5 \nTIM9/12 event generation register (TIMx_EGR)\nAddress offset: 0x14\nReset value: 0x0000\n \nBit 0 UIF: Update interrupt flag\nThis bit is set by hardware on an update event. It is cleared by software.\n0: No update occurred.\n1: Update interrupt pending. This bit is set by hardware when the registers are updated:\n– At overflow and if UDIS=’0’ in the TIMx_CR1 register.\n– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and \nUDIS=’0’ in the TIMx_CR1 register.\n– When CNT is reinitialized by a trigger event (refer to the synchro control register \ndescription), if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTG\nReserved\nCC2G\nCC1G\nUG\nw\nw\nw\nw\nBits 15:7 Reserved, must be kept at reset value.\nBit 6 TG: Trigger generation\nThis bit is set by software in order to generate an event, it is automatically cleared by \nhardware.\n0: No action\n1: The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled\nBits 5:3 Reserved, must be kept at reset value.\nBit 2 CC2G: Capture/compare 2 generation\nrefer to CC1G description\nBit 1 CC1G: Capture/compare 1 generation\nThis bit is set by software to generate an event, it is automatically cleared by hardware.\n0: No action\n1: A capture/compare event is generated on channel 1:\nIf channel CC1 is configured as output:\nthe CC1IF flag is set, the corresponding interrupt is sent if enabled.\nIf channel CC1 is configured as input:\nThe current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the \ncorresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was \nalready high.\nBit 0 UG: Update generation\nThis bit can be set by software, it is automatically cleared by hardware.\n0: No action\n1: Re-initializes the counter and generates an update of the registers. The prescaler counter \nis also cleared and the prescaler ratio is not affected. The counter is cleared.\n" }, { "page_number": 681, "page_indices": { "start_index": 1338587, "end_index": 1340304 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 681 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.4 TIM9 and TIM12 registers", 675 ], [ 3, "19.4.6 TIM9/12 capture/compare mode register 1 (TIMx_CCMR1)", 681 ], [ 4, "Output compare mode", 681 ] ], "page_content": "RM0090 Rev 21\n681/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.4.6 \nTIM9/12 capture/compare mode register 1 (TIMx_CCMR1)\nAddress offset: 0x18\nReset value: 0x0000\nThe channels can be used in input (capture mode) or in output (compare mode). The \ndirection of a channel is defined by configuring the corresponding CCxS bits. All the other \nbits in this register have different functions in input and output modes. For a given bit, OCxx \ndescribes its function when the channel is configured in output mode, ICxx describes its \nfunction when the channel is configured in input mode. Take care that the same bit can have \ndifferent meanings for the input stage and the output stage.\nOutput compare mode\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nOC2M[2:0]\nOC2PE OC2FE\nCC2S[1:0]\nRes.\nOC1M[2:0]\nOC1PE OC1FE\nCC1S[1:0]\nIC2F[3:0]\nIC2PSC[1:0]\nIC1F[3:0]\nIC1PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15\nReserved, must be kept at reset value.\nBits 14:12 OC2M[2:0]: Output compare 2 mode\nBit 11 OC2PE: Output compare 2 preload enable\nBit 10 OC2FE: Output compare 2 fast enable\nBits 9:8 CC2S[1:0]: Capture/Compare 2 selection\nThis bitfield defines the direction of the channel (input/output) as well as the used input. \n00: CC2 channel is configured as output\n01: CC2 channel is configured as input, IC2 is mapped on TI2\n10: CC2 channel is configured as input, IC2 is mapped on TI1\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an \ninternal trigger input is selected through the TS bit (TIMx_SMCR register\nNote: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).\nBit 7\nReserved, must be kept at reset value.\n" }, { "page_number": 682, "page_indices": { "start_index": 1340304, "end_index": 1343449 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 682 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.4 TIM9 and TIM12 registers", 675 ], [ 3, "19.4.6 TIM9/12 capture/compare mode register 1 (TIMx_CCMR1)", 681 ], [ 4, "Output compare mode", 681 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n682/1757\nRM0090 Rev 21\nBits 6:4 OC1M: Output compare 1 mode\nThese bits define the behavior of the output reference signal OC1REF from which OC1 and \nOC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N \ndepend on the CC1P and CC1NP bits, respectively.\n000: Frozen - The comparison between the output compare register TIMx_CCR1 and the \ncounter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing \nbase).\n001: Set channel 1 to active level on match. The OC1REF signal is forced high when the \nTIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1).\n010: Set channel 1 to inactive level on match. The OC1REF signal is forced low when the \nTIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1).\n011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1\n100: Force inactive level - OC1REF is forced low\n101: Force active level - OC1REF is forced high\n110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1, else it is active (OC1REF=’1’)\n111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 \nelse it is inactive.\nNote: In PWM mode 1 or 2, the OCREF level changes only when the result of the \ncomparison changes or when the output compare mode switches from “frozen” mode \nto “PWM” mode.\nBit 3 OC1PE: Output compare 1 preload enable\n0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the \nnew value is taken into account immediately\n1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload \nregister. TIMx_CCR1 preload value is loaded into the active register at each update event\nBit 2 OC1FE: Output compare 1 fast enable\nThis bit is used to accelerate the effect of an event on the trigger in input on the CC output.\n0: CC1 behaves normally depending on the counter and CCR1 values even when the \ntrigger is ON. The minimum delay to activate the CC1 output when an edge occurs on the \ntrigger input is 5 clock cycles\n1: An active edge on the trigger input acts like a compare match on the CC1 output. Then, \nOC is set to the compare level independently of the result of the comparison. Delay to \nsample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE \nacts only if the channel is configured in PWM1 or PWM2 mode.\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bitfield defines the direction of the channel (input/output) as well as the used input. \n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: CC1 channel is configured as input, IC1 is mapped on TI2\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode works only if an \ninternal trigger input is selected through the TS bit (TIMx_SMCR register)\nNote: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\n" }, { "page_number": 683, "page_indices": { "start_index": 1343449, "end_index": 1345907 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 683 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.4 TIM9 and TIM12 registers", 675 ], [ 3, "19.4.6 TIM9/12 capture/compare mode register 1 (TIMx_CCMR1)", 681 ], [ 4, "Input capture mode", 683 ] ], "page_content": "RM0090 Rev 21\n683/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\nInput capture mode\nBits 15:12 IC2F: Input capture 2 filter\nBits 11:10 IC2PSC[1:0]: Input capture 2 prescaler\nBits 9:8 CC2S: Capture/compare 2 selection\nThis bitfield defines the direction of the channel (input/output) as well as the used input. \n00: CC2 channel is configured as output\n01: CC2 channel is configured as input, IC2 is mapped on TI2\n10: CC2 channel is configured as input, IC2 is mapped on TI1\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an \ninternal trigger input is selected through the TS bit (TIMx_SMCR register)\nNote: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).\nBits 7:4 IC1F: Input capture 1 filter\nThis bitfield defines the frequency used to sample the TI1 input and the length of the digital \nfilter applied to TI1. The digital filter is made of an event counter in which N consecutive \nevents are needed to validate a transition on the output:\n0000: No filter, sampling is done at fDTS\n0001: fSAMPLING=fCK_INT, N=2\n0010: fSAMPLING=fCK_INT, N=4\n0011: fSAMPLING=fCK_INT, N=8 \n0100: fSAMPLING=fDTS/2, N=6\n0101: fSAMPLING=fDTS/2, N=8\n0110: fSAMPLING=fDTS/4, N=6\n0111: fSAMPLING=fDTS/4, N=8\n1000: fSAMPLING=fDTS/8, N=6\n1001: fSAMPLING=fDTS/8, N=8\n1010: fSAMPLING=fDTS/16, N=5\n1011: fSAMPLING=fDTS/16, N=6\n1100: fSAMPLING=fDTS/16, N=8\n1101: fSAMPLING=fDTS/32, N=5\n1110: fSAMPLING=fDTS/32, N=6\n1111: fSAMPLING=fDTS/32, N=8\nBits 3:2 IC1PSC: Input capture 1 prescaler\nThis bitfield defines the ratio of the prescaler acting on the CC1 input (IC1).\nThe prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).\n00: no prescaler, capture is done each time an edge is detected on the capture input\n01: capture is done once every 2 events\n10: capture is done once every 4 events\n11: capture is done once every 8 events\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bitfield defines the direction of the channel (input/output) as well as the used input. \n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: CC1 channel is configured as input, IC1 is mapped on TI2\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if \nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\n" }, { "page_number": 684, "page_indices": { "start_index": 1345907, "end_index": 1348140 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 684 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.4 TIM9 and TIM12 registers", 675 ], [ 3, "19.4.7 TIM9/12 capture/compare enable register (TIMx_CCER)", 684 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n684/1757\nRM0090 Rev 21\n19.4.7 \nTIM9/12 capture/compare enable register (TIMx_CCER)\nAddress offset: 0x20\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCC2NP\nRes.\nCC2P\nCC2E\nCC1NP\nRes.\nCC1P\nCC1E\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 CC2NP: Capture/Compare 2 output Polarity\nrefer to CC1NP description \nBits 6 Reserved, must be kept at reset value.\nBit 5 CC2P: Capture/Compare 2 output Polarity\nrefer to CC1P description\nBit 4 CC2E: Capture/Compare 2 output enable\nrefer to CC1E description\nBit 3 CC1NP: Capture/Compare 1 complementary output Polarity\nCC1 channel configured as output: CC1NP must be kept cleared\nCC1 channel configured as input: CC1NP is used in conjunction with CC1P to define \nTI1FP1/TI2FP1 polarity (refer to CC1P description).\nBit 2 Reserved, must be kept at reset value.\nBit 1 CC1P: Capture/Compare 1 output Polarity.\nCC1 channel configured as output:\n0: OC1 active high.\n1: OC1 active low.\nCC1 channel configured as input:\nCC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.\n00: noninverted/rising edge\nCircuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger \nmode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).\n01: inverted/falling edge\nCircuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger \nmode), TIxFP1 is inverted (trigger in gated mode, encoder mode).\n10: reserved, do not use this configuration.\nNote: 11: noninverted/both edges\nCircuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, \nexternal clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This \nconfiguration must not be used for encoder mode.\nBit 0 CC1E: Capture/Compare 1 output enable.\nCC1 channel configured as output:\n0: Off - OC1 is not active. \n1: On - OC1 signal is output on the corresponding output pin. \nCC1 channel configured as input:\nThis bit determines if a capture of the counter value can actually be done into the input \ncapture/compare register 1 (TIMx_CCR1) or not.\n0: Capture disabled.\n1: Capture enabled.\n" }, { "page_number": 685, "page_indices": { "start_index": 1348140, "end_index": 1349751 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 685 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.4 TIM9 and TIM12 registers", 675 ], [ 3, "19.4.8 TIM9/12 counter (TIMx_CNT)", 685 ], [ 3, "19.4.9 TIM9/12 prescaler (TIMx_PSC)", 685 ], [ 3, "19.4.10 TIM9/12 auto-reload register (TIMx_ARR)", 685 ] ], "page_content": "RM0090 Rev 21\n685/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n \nNote:\nThe states of the external I/O pins connected to the standard OCx channels depend on the \nstate of the OCx channel and on the GPIO registers.\n19.4.8 \nTIM9/12 counter (TIMx_CNT)\nAddress offset: 0x24\nReset value: 0x0000 \n \n19.4.9 \nTIM9/12 prescaler (TIMx_PSC)\nAddress offset: 0x28\nReset value: 0x0000\n \n19.4.10 \nTIM9/12 auto-reload register (TIMx_ARR)\nAddress offset: 0x2C\nReset value: 0xFFFF\n \nTable 103. Output control bit for standard OCx channels\nCCxE bit\nOCx output state\n0\nOutput disabled (OCx=’0’, OCx_EN=’0’)\n1\nOCx=OCxREF + Polarity, OCx_EN=’1’\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCNT[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CNT[15:0]: Counter value\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPSC[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 PSC[15:0]: Prescaler value\nThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).\nPSC contains the value to be loaded in the active prescaler register at each update event \n(including when the counter is cleared through UG bit of TIMx_EGR register or through \ntrigger controller when configured in “reset mode”).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nARR[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 ARR[15:0]: Auto-reload value\nARR is the value to be loaded into the actual auto-reload register.\nRefer to the Section 19.3.1: Time-base unit for more details about ARR update and \nbehavior.\nThe counter is blocked while the auto-reload value is null.\n" }, { "page_number": 686, "page_indices": { "start_index": 1349751, "end_index": 1351738 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 686 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.4 TIM9 and TIM12 registers", 675 ], [ 3, "19.4.11 TIM9/12 capture/compare register 1 (TIMx_CCR1)", 686 ], [ 3, "19.4.12 TIM9/12 capture/compare register 2 (TIMx_CCR2)", 686 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n686/1757\nRM0090 Rev 21\n19.4.11 \nTIM9/12 capture/compare register 1 (TIMx_CCR1)\nAddress offset: 0x34\nReset value: 0x0000\n \n19.4.12 \nTIM9/12 capture/compare register 2 (TIMx_CCR2)\nAddress offset: 0x38\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR1[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 15:0 CCR1[15:0]: Capture/Compare 1 value\nIf channel CC1 is configured as output:\nCCR1 is the value to be loaded into the actual capture/compare 1 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register \n(OC1PE bit). Else the preload value is copied into the active capture/compare 1 register \nwhen an update event occurs.\nThe active capture/compare register contains the value to be compared to the TIMx_CNT \ncounter and signaled on the OC1 output.\nIf channel CC1is configured as input:\nCCR1 is the counter value transferred by the last input capture 1 event (IC1). The \nTIMx_CCR1 register is read-only and cannot be programmed.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR2[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 15:0 CCR2[15:0]: Capture/Compare 2 value\nIf channel CC2 is configured as output:\nCCR2 is the value to be loaded into the actual capture/compare 2 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register \n(OC2PE bit). Else the preload value is copied into the active capture/compare 2 register \nwhen an update event occurs.\nThe active capture/compare register contains the value to be compared to the TIMx_CNT \ncounter and signalled on the OC2 output.\nIf channel CC2 is configured as input:\nCCR2 is the counter value transferred by the last input capture 2 event (IC2). The \nTIMx_CCR2 register is read-only and cannot be programmed.\n" }, { "page_number": 687, "page_indices": { "start_index": 1351738, "end_index": 1353338 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 687 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.4 TIM9 and TIM12 registers", 675 ], [ 3, "19.4.13 TIM9/12 register map", 687 ] ], "page_content": "RM0090 Rev 21\n687/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.4.13 \nTIM9/12 register map\nTIM9/12 registers are mapped as 16-bit addressable registers as described below. The \nreserved memory areas are highlighted in gray in the table.\n \nTable 104. TIM9/12 register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nTIMx_CR1\nReserved\nCKD \n[1:0]\nARPE\nReserved\nOPM\nURS\nUDIS\nCEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0x08\nTIMx_SMCR\nReserved\nMSM\nTS[2:0]\nReserved\nSMS[2:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0x0C\nTIMx_DIER\nReserved\nTIE\nReserved\nCC2IE\nCC1IE\nUIE\nReset value\n0\n0\n0\n0\n0x10\nTIMx_SR\nReserved\nCC2OF\nCC1OF\nReserved\nTIF\nReserved\nCC2IF\nCC1IF\nUIF\nReset value\n0\n0\n0\n0\n0\n0\n0x14\nTIMx_EGR\nReserved\nTG\nReserved\nCC2G\nCC1G\nUG\nReset value\n0\n0\n0\n0\n0x18\nTIMx_CCMR1\nOutput compare \nmode\nReserved\nOC2M\n[2:0]\nOC2PE\nOC2FE\nCC2S \n[1:0]\nReserved\nOC1M\n[2:0]\nOC1PE\nOC1FE\nCC1\nS \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTIMx_CCMR1\nInput capture \nmode\nReserved\nIC2F[3:0]\nIC2\nPSC\n[1:0]\nCC2S \n[1:0]\nIC1F[3:0]\nIC1\nPSC\n[1:0]\nCC1\nS \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nReserved\n0x20\nTIMx_CCER\nReserved\nCC2NP\nReserved\nCC2P\nCC2E\nCC1NP\nReserved\nCC1P\nCC1E\nReset value\n0\n0\n0\n0\n0\n0\n0x24\nTIMx_CNT\nReserved\nCNT[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nTIMx_PSC\nReserved\nPSC[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x2C\nTIMx_ARR\nReserved\nARR[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x30\nReserved\n0x34\nTIMx_CCR1\nReserved\nCCR1[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n" }, { "page_number": 688, "page_indices": { "start_index": 1353338, "end_index": 1353763 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 688 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.4 TIM9 and TIM12 registers", 675 ], [ 3, "19.4.13 TIM9/12 register map", 687 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n688/1757\nRM0090 Rev 21\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x38\nTIMx_CCR2\nReserved\nCCR2[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x3C to\n0x4C\nReserved\nTable 104. TIM9/12 register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 689, "page_indices": { "start_index": 1353763, "end_index": 1355678 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 689 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.5 TIM10/11/13/14 registers", 689 ], [ 3, "19.5.1 TIM10/11/13/14 control register 1 (TIMx_CR1)", 689 ] ], "page_content": "RM0090 Rev 21\n689/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.5 \nTIM10/11/13/14 registers\nThe peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read \naccesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). \n19.5.1 \nTIM10/11/13/14 control register 1 (TIMx_CR1)\nAddress offset: 0x00\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCKD[1:0]\nARPE\nReserved\nOPM\nURS\nUDIS\nCEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:10 Reserved, must be kept at reset value.\nBits 9:8 CKD: Clock division\nThis bit-field indicates the division ratio between the timer clock (CK_INT) frequency and \nsampling clock used by the digital filters (TIx),\n00: tDTS = tCK_INT\n01: tDTS = 2 × tCK_INT\n10: tDTS = 4 × tCK_INT\n11: Reserved\nBit 7 ARPE: Auto-reload preload enable\n0: TIMx_ARR register is not buffered\n1: TIMx_ARR register is buffered\nBits 6:4 Reserved, must be kept at reset value.\nBit 3 OPM: One-pulse mode\n0: Counter is not stopped on the update event\n1: Counter stops counting on the next update event (clearing the CEN bit).\nBit 2 URS: Update request source\nThis bit is set and cleared by software to select the update interrupt (UEV) sources.\n0: Any of the following events generate an UEV if enabled: \n–\nCounter overflow\n–\nSetting the UG bit\n1: Only counter overflow generates an UEV if enabled.\nBit 1 UDIS: Update disable\nThis bit is set and cleared by software to enable/disable update interrupt (UEV) event \ngeneration.\n0: UEV enabled. An UEV is generated by one of the following events:\n–\nCounter overflow\n–\nSetting the UG bit. \nBuffered registers are then loaded with their preload values.\n1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, \nCCRx). The counter and the prescaler are reinitialized if the UG bit is set.\nBit 0 CEN: Counter enable\n0: Counter disabled\n1: Counter enabled\n" }, { "page_number": 690, "page_indices": { "start_index": 1355678, "end_index": 1357524 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 690 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.5 TIM10/11/13/14 registers", 689 ], [ 3, "19.5.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER)", 690 ], [ 3, "19.5.3 TIM10/11/13/14 status register (TIMx_SR)", 690 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n690/1757\nRM0090 Rev 21\n19.5.2 \nTIM10/11/13/14 Interrupt enable register (TIMx_DIER)\nAddress offset: 0x0C\nReset value: 0x0000\n \n19.5.3 \nTIM10/11/13/14 status register (TIMx_SR)\nAddress offset: 0x10\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCC1IE\nUIE\nrw\nrw\nBits 15:2\nReserved, must be kept at reset value.\nBit 1 CC1IE: Capture/Compare 1 interrupt enable\n0: CC1 interrupt disabled\n1: CC1 interrupt enabled\nBit 0 UIE: Update interrupt enable\n0: Update interrupt disabled\n1: Update interrupt enabled\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCC1OF\nReserved\nCC1IF\nUIF\nrc_w0\nrc_w0\nrc_w0\nBits 15:10\nReserved, must be kept at reset value.\nBit 9 CC1OF: Capture/Compare 1 overcapture flag\nThis flag is set by hardware only when the corresponding channel is configured in input \ncapture mode. It is cleared by software by writing it to ‘0’.\n0: No overcapture has been detected.\n1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was \nalready set\nBits 8:2\nReserved, must be kept at reset value.\nBit 1 CC1IF: Capture/compare 1 interrupt flag\nIf channel CC1 is configured as output:\nThis flag is set by hardware when the counter matches the compare value. It is cleared by \nsoftware.\n0: No match.\n1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. \nWhen the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit \ngoes high on the counter overflow.\nIf channel CC1 is configured as input:\nThis bit is set by hardware on a capture. It is cleared by software or by reading the \nTIMx_CCR1 register.\n0: No input capture occurred.\n1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected \non IC1 which matches the selected polarity).\n" }, { "page_number": 691, "page_indices": { "start_index": 1357524, "end_index": 1359863 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 691 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.5 TIM10/11/13/14 registers", 689 ], [ 3, "19.5.4 TIM10/11/13/14 event generation register (TIMx_EGR)", 691 ], [ 3, "19.5.5 TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1)", 691 ] ], "page_content": "RM0090 Rev 21\n691/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.5.4 \nTIM10/11/13/14 event generation register (TIMx_EGR)\nAddress offset: 0x14\nReset value: 0x0000\n \n19.5.5 \nTIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1)\nAddress offset: 0x18\nReset value: 0x0000\nThe channels can be used in input (capture mode) or in output (compare mode). The \ndirection of a channel is defined by configuring the corresponding CCxS bits. All the other \nbits of this register have a different function in input and in output mode. For a given bit, \nOCxx describes its function when the channel is configured in output, ICxx describes its \nfunction when the channel is configured in input. So take care that the same bit can have a \ndifferent meaning for the input stage and for the output stage.\nBit 0 UIF: Update interrupt flag\nThis bit is set by hardware on an update event. It is cleared by software.\n0: No update occurred.\n1: Update interrupt pending. This bit is set by hardware when the registers are updated:\n–\nAt overflow and if UDIS=’0’ in the TIMx_CR1 register.\n–\nWhen CNT is reinitialized by software using the UG bit in TIMx_EGR register, if \nURS=’0’ and UDIS=’0’ in the TIMx_CR1 register.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCC1G\nUG\nw\nw\nBits 15:2 Reserved, must be kept at reset value.\nBit 1 CC1G: Capture/compare 1 generation\nThis bit is set by software in order to generate an event, it is automatically cleared by \nhardware.\n0: No action\n1: A capture/compare event is generated on channel 1:\nIf channel CC1 is configured as output:\nCC1IF flag is set, Corresponding interrupt or is sent if enabled.\nIf channel CC1 is configured as input:\nThe current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, \nthe corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was \nalready high.\nBit 0 UG: Update generation\nThis bit can be set by software, it is automatically cleared by hardware.\n0: No action\n1: Re-initialize the counter and generates an update of the registers. Note that the prescaler \ncounter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared. \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOC1M[2:0]\nOC1PE OC1FE\nCC1S[1:0]\nReserved\nIC1F[3:0]\nIC1PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 692, "page_indices": { "start_index": 1359863, "end_index": 1362489 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 692 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.5 TIM10/11/13/14 registers", 689 ], [ 3, "19.5.5 TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1)", 691 ], [ 4, "Output compare mode", 692 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n692/1757\nRM0090 Rev 21\nOutput compare mode\nBits 15:7\nReserved, must be kept at reset value.\nBits 6:4 OC1M: Output compare 1 mode\nThese bits define the behavior of the output reference signal OC1REF from which OC1 is \nderived. OC1REF is active high whereas OC1 active level depends on CC1P bit. \n000: Frozen. The comparison between the output compare register TIMx_CCR1 and the \ncounter TIMx_CNT has no effect on the outputs. \n001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter \nTIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). \n010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the \ncounter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). \n011: Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1. \n100: Force inactive level - OC1REF is forced low. \n101: Force active level - OC1REF is forced high.\n110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive.\n111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active.\nNote: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison \nchanges or when the output compare mode switches from frozen to PWM mode. \nBit 3 OC1PE: Output compare 1 preload enable\n0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the \nnew value is taken in account immediately. \n1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload \nregister. TIMx_CCR1 preload value is loaded in the active register at each update event.\nBit 2 OC1FE: Output compare 1 fast enable\nThis bit is used to accelerate the effect of an event on the trigger in input on the CC output.\n0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is \nON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is \n5 clock cycles.\n1: An active edge on the trigger input acts like a compare match on CC1 output. OC is then \nset to the compare level independently of the result of the comparison. Delay to sample the \ntrigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the \nchannel is configured in PWM1 or PWM2 mode.\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC1 channel is configured as output.\n01: CC1 channel is configured as input, IC1 is mapped on TI1.\n10: \n11: \nNote: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\n" }, { "page_number": 693, "page_indices": { "start_index": 1362489, "end_index": 1364154 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 693 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.5 TIM10/11/13/14 registers", 689 ], [ 3, "19.5.5 TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1)", 691 ], [ 4, "Input capture mode", 693 ] ], "page_content": "RM0090 Rev 21\n693/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\nInput capture mode\n \nBits 15:8\nReserved, must be kept at reset value.\nBits 7:4 IC1F: Input capture 1 filter\nThis bit-field defines the frequency used to sample TI1 input and the length of the digital filter \napplied to TI1. The digital filter is made of an event counter in which N consecutive events \nare needed to validate a transition on the output:\n0000: No filter, sampling is done at fDTS\n0001: fSAMPLING=fCK_INT, N=2\n0010: fSAMPLING=fCK_INT, N=4\n0011: fSAMPLING=fCK_INT, N=8\n0100: fSAMPLING=fDTS/2, N=6\n0101: fSAMPLING=fDTS/2, N=8\n0110: fSAMPLING=fDTS/4, N=6\n0111: fSAMPLING=fDTS/4, N=8\n1000: fSAMPLING=fDTS/8, N=6\n1001: fSAMPLING=fDTS/8, N=8\n1010: fSAMPLING=fDTS/16, N=5\n1011: fSAMPLING=fDTS/16, N=6\n1100: fSAMPLING=fDTS/16, N=8\n1101: fSAMPLING=fDTS/32, N=5\n1110: fSAMPLING=fDTS/32, N=6\n1111: fSAMPLING=fDTS/32, N=8\nBits 3:2 IC1PSC: Input capture 1 prescaler\nThis bit-field defines the ratio of the prescaler acting on CC1 input (IC1).\nThe prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).\n00: no prescaler, capture is done each time an edge is detected on the capture input\n01: capture is done once every 2 events\n10: capture is done once every 4 events\n11: capture is done once every 8 events\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input. \n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: Reserved\n11: Reserved\nNote: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\n" }, { "page_number": 694, "page_indices": { "start_index": 1364154, "end_index": 1366104 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 694 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.5 TIM10/11/13/14 registers", 689 ], [ 3, "19.5.6 TIM10/11/13/14 capture/compare enable register (TIMx_CCER)", 694 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n694/1757\nRM0090 Rev 21\n19.5.6 \nTIM10/11/13/14 capture/compare enable register (TIMx_CCER)\nAddress offset: 0x20\nReset value: 0x0000\n \n \nNote:\nThe state of the external I/O pins connected to the standard OCx channels depends on the \nOCx channel state and the GPIO registers.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCC1NP\nRes.\nCC1P\nCC1E\nrw\nrw\nrw\nBits 15:4 Reserved, must be kept at reset value.\nBit 3 CC1NP: Capture/Compare 1 complementary output Polarity. \nCC1 channel configured as output: CC1NP must be kept cleared. \nCC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define \nTI1FP1 polarity (refer to CC1P description).\nBit 2 Reserved, must be kept at reset value. \nBit 1 CC1P: Capture/Compare 1 output Polarity.\nCC1 channel configured as output:\n0: OC1 active high\n1: OC1 active low\nCC1 channel configured as input:\nThe CC1P bit selects TI1FP1 and TI2FP1 polarity for trigger or capture operations.\n00: noninverted/rising edge\nCircuit is sensitive to TI1FP1 rising edge (capture mode), TI1FP1 is not inverted. \n01: inverted/falling edge\nCircuit is sensitive to TI1FP1 falling edge (capture mode), TI1FP1 is inverted.\n10: reserved, do not use this configuration. \n11: noninverted/both edges\nCircuit is sensitive to both TI1FP1 rising and falling edges (capture mode), TI1FP1 is not \ninverted. \nBit 0 CC1E: Capture/Compare 1 output enable.\nCC1 channel configured as output:\n0: Off - OC1 is not active\n1: On - OC1 signal is output on the corresponding output pin\nCC1 channel configured as input:\nThis bit determines if a capture of the counter value can actually be done into the input \ncapture/compare register 1 (TIMx_CCR1) or not.\n0: Capture disabled\n1: Capture enabled\nTable 105. Output control bit for standard OCx channels\nCCxE bit\nOCx output state\n0\nOutput Disabled (OCx=’0’, OCx_EN=’0’)\n1\nOCx=OCxREF + Polarity, OCx_EN=’1’\n" }, { "page_number": 695, "page_indices": { "start_index": 1366104, "end_index": 1367411 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 695 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.5 TIM10/11/13/14 registers", 689 ], [ 3, "19.5.7 TIM10/11/13/14 counter (TIMx_CNT)", 695 ], [ 3, "19.5.8 TIM10/11/13/14 prescaler (TIMx_PSC)", 695 ], [ 3, "19.5.9 TIM10/11/13/14 auto-reload register (TIMx_ARR)", 695 ] ], "page_content": "RM0090 Rev 21\n695/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.5.7 \nTIM10/11/13/14 counter (TIMx_CNT)\nAddress offset: 0x24\nReset value: 0x0000\n \n19.5.8 \nTIM10/11/13/14 prescaler (TIMx_PSC)\nAddress offset: 0x28\nReset value: 0x0000\n \n19.5.9 \nTIM10/11/13/14 auto-reload register (TIMx_ARR)\nAddress offset: 0x2C\nReset value: 0xFFFF\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCNT[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CNT[15:0]: Counter value\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPSC[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 PSC[15:0]: Prescaler value\nThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).\nPSC contains the value to be loaded in the active prescaler register at each update event \n(including when the counter is cleared through UG bit of TIMx_EGR register or through \ntrigger controller when configured in “reset mode”).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nARR[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 ARR[15:0]: Auto-reload value\nARR is the value to be loaded in the actual auto-reload register.\nRefer to Section 19.3.1: Time-base unit for more details about ARR update and behavior.\nThe counter is blocked while the auto-reload value is null.\n" }, { "page_number": 696, "page_indices": { "start_index": 1367411, "end_index": 1368990 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 696 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.5 TIM10/11/13/14 registers", 689 ], [ 3, "19.5.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1)", 696 ], [ 3, "19.5.11 TIM11 option register 1 (TIM11_OR)", 696 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n696/1757\nRM0090 Rev 21\n19.5.10 \nTIM10/11/13/14 capture/compare register 1 (TIMx_CCR1)\nAddress offset: 0x34\nReset value: 0x0000\n \n \n19.5.11 \nTIM11 option register 1 (TIM11_OR)\nAddress offset: 0x50\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCCR1[15:0]\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nrw/ro\nBits 15:0 CCR1[15:0]: Capture/Compare 1 value\nIf channel CC1 is configured as output:\nCCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit \nOC1PE). Else the preload value is copied in the active capture/compare 1 register when an \nupdate event occurs.\nThe active capture/compare register contains the value to be compared to the counter \nTIMx_CNT and signaled on OC1 output.\nIf channel CC1is configured as input:\nCCR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 \nregister is read-only and cannot be programmed.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTI1_RMP[1:0]\nrw\nBits 15:2\nReserved, must be kept at reset value.\nBits 1:0\nTI1_RMP[1:0]: TIM11 Input 1 remapping capability\nSet and cleared by software.\n00,01,11: TIM11 Channel1 is connected to the GPIO (refer to the Alternate function mapping \ntable in the datasheets).\n10: HSE_RTC clock (HSE divided by programmable prescaler) is connected to the \nTIM11_CH1 input for measurement purposes\n" }, { "page_number": 697, "page_indices": { "start_index": 1368990, "end_index": 1370300 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 697 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.5 TIM10/11/13/14 registers", 689 ], [ 3, "19.5.12 TIM10/11/13/14 register map", 697 ] ], "page_content": "RM0090 Rev 21\n697/1757\nRM0090\nGeneral-purpose timers (TIM9 to TIM14)\n698\n19.5.12 \nTIM10/11/13/14 register map\nTIMx registers are mapped as 16-bit addressable registers as described in the table below. \nTable 106. TIM10/11/13/14 register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nTIMx_CR1\nReserved\nCKD \n[1:0]\nARPE\nReserve\nd\nOPM\nURS\nUDIS\nCEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0x08\nTIMx_SMCR\nReserved\nReset value\n0x0C\nTIMx_DIER\nReserved\nCC1IE\nUIE\nReset value\n0\n0\n0x10\nTIMx_SR\nReserved\nCC1OF\nReserved\nCC1IF\nUIF\nReset value\n0\n0\n0\n0x14\nTIMx_EGR\nReserved\nCC1G\nUG\nReset value\n0\n0\n0x18\nTIMx_CCMR1\nOutput compare \nmode\nReserved\nOC1M\n[2:0]\nOC1PE\nOC1FE\nCC1S \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\nTIMx_CCMR1\nInput capture \nmode\nReserved\nIC1F[3:0]\nIC1\nPSC\n[1:0]\nCC1S \n[1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nReserved\n0x20\nTIMx_CCER\nReserved\nCC1NP\nReserved\nCC1P\nCC1E\nReset value\n0\n0\n0\n0x24\nTIMx_CNT\nReserved\nCNT[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nTIMx_PSC\nReserved\nPSC[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x2C\nTIMx_ARR\nReserved\nARR[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x30\nReserved\n0x34\nTIMx_CCR1\nReserved\nCCR1[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x38 to\n0x4C\nReserved\n" }, { "page_number": 698, "page_indices": { "start_index": 1370300, "end_index": 1370677 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 698 }, "toc_details": [ [ 1, "19 General-purpose timers (TIM9 to TIM14)", 653 ], [ 2, "19.5 TIM10/11/13/14 registers", 689 ], [ 3, "19.5.12 TIM10/11/13/14 register map", 697 ] ], "page_content": "General-purpose timers (TIM9 to TIM14)\nRM0090\n698/1757\nRM0090 Rev 21\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x50\nTIMx_OR\nReserved\nTI1_RMP\nReset value\n0\n0\nTable 106. TIM10/11/13/14 register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 699, "page_indices": { "start_index": 1370677, "end_index": 1372059 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 699 }, "toc_details": [ [ 1, "20 Basic timers (TIM6 and TIM7)", 699 ], [ 2, "20.1 TIM6 and TIM7 introduction", 699 ], [ 2, "20.2 TIM6 and TIM7 main features", 699 ] ], "page_content": "RM0090 Rev 21\n699/1757\nRM0090\nBasic timers (TIM6 and TIM7)\n710\n20 \nBasic timers (TIM6 and TIM7)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n20.1 \nTIM6 and TIM7 introduction\nThe basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a \nprogrammable prescaler.\nThey may be used as generic timers for time-base generation but they are also specifically \nused to drive the digital-to-analog converter (DAC). In fact, the timers are internally \nconnected to the DAC and are able to drive it through their trigger outputs.\nThe timers are completely independent, and do not share any resources. \n20.2 \nTIM6 and TIM7 main features\nBasic timer (TIM6 and TIM7) features include:\n•\n16-bit auto-reload upcounter\n•\n16-bit programmable prescaler used to divide (also “on the fly”) the counter clock \nfrequency by any factor between 1 and 65536\n•\nSynchronization circuit to trigger the DAC\n•\nInterrupt/DMA generation on the update event: counter overflow\nFigure 203. Basic timer block diagram\nU\nTrigger\ncontroller\nStop, Clear or up\nTRGO\nU\nUI\nReset, Enable, Count,\nevent\nPreload registers transferred \nto active registers on U event according to control bit\ninterrupt & DMA output\nto DAC \nCOUNTER\nCK_PSC\nCNT\nCK_CNT\nController\nInternal clock (CK_INT)\nTIMxCLK from RCC\n±\nPrescaler\nPSC\nAuto-reload Register\nFlag\nai14749b\n" }, { "page_number": 700, "page_indices": { "start_index": 1372059, "end_index": 1373931 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 700 }, "toc_details": [ [ 1, "20 Basic timers (TIM6 and TIM7)", 699 ], [ 2, "20.3 TIM6 and TIM7 functional description", 700 ], [ 3, "20.3.1 Time-base unit", 700 ], [ 4, "Prescaler description", 700 ] ], "page_content": "Basic timers (TIM6 and TIM7)\nRM0090\n700/1757\nRM0090 Rev 21\n20.3 \nTIM6 and TIM7 functional description\n20.3.1 \nTime-base unit\nThe main block of the programmable timer is a 16-bit upcounter with its related auto-reload \nregister. The counter clock can be divided by a prescaler. \nThe counter, the auto-reload register and the prescaler register can be written or read by \nsoftware. This is true even when the counter is running.\nThe time-base unit includes:\n•\nCounter register (TIMx_CNT)\n•\nPrescaler register (TIMx_PSC)\n•\nAuto-Reload register (TIMx_ARR)\nThe auto-reload register is preloaded. The preload register is accessed each time an \nattempt is made to write or read the auto-reload register. The contents of the preload \nregister are transferred into the shadow register permanently or at each update event UEV, \ndepending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The \nupdate event is sent when the counter reaches the overflow value and if the UDIS bit equals \n0 in the TIMx_CR1 register. It can also be generated by software. The generation of the \nupdate event is described in detail for each configuration.\nThe counter is clocked by the prescaler output CK_CNT, which is enabled only when the \ncounter enable bit (CEN) in the TIMx_CR1 register is set. \nNote that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN. \nPrescaler description\nThe prescaler can divide the counter clock frequency by any factor between 1 and 65536. It \nis based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). \nIt can be changed on the fly as the TIMx_PSC control register is buffered. The new \nprescaler ratio is taken into account at the next update event.\nFigure 204 and Figure 205 give some examples of the counter behavior when the prescaler \nratio is changed on the fly.\n" }, { "page_number": 701, "page_indices": { "start_index": 1373931, "end_index": 1374622 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 701 }, "toc_details": [ [ 1, "20 Basic timers (TIM6 and TIM7)", 699 ], [ 2, "20.3 TIM6 and TIM7 functional description", 700 ], [ 3, "20.3.1 Time-base unit", 700 ], [ 4, "Prescaler description", 700 ] ], "page_content": "RM0090 Rev 21\n701/1757\nRM0090\nBasic timers (TIM6 and TIM7)\n710\nFigure 204. Counter timing diagram with prescaler division change from 1 to 2\nFigure 205. Counter timing diagram with prescaler division change from 1 to 4\nCK_PSC\n00\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\n0\nPrescaler control register\n1\n0\nWrite a new value in TIMx_PSC\nPrescaler buffer\n1\n0\nPrescaler counter\n0\n1\n0\n1\n0\n1\n0\n1\n01\n02\n03\nFA\nFB\nF7\nF8\nF9\nFC\nMS31076V3\n0\n3\n0\n0\n1\n2\n3\n0\n1\n2\n3\nMS31077V3\nCK_PSC\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nPrescaler control register\nWrite a new value in TIMx_PSC\nPrescaler buffer\nPrescaler counter\n00\n01\nFA FB\nF7\nF8\nF9\nFC\n3\n0\n" }, { "page_number": 702, "page_indices": { "start_index": 1374622, "end_index": 1376306 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 702 }, "toc_details": [ [ 1, "20 Basic timers (TIM6 and TIM7)", 699 ], [ 2, "20.3 TIM6 and TIM7 functional description", 700 ], [ 3, "20.3.2 Counting mode", 702 ] ], "page_content": "Basic timers (TIM6 and TIM7)\nRM0090\n702/1757\nRM0090 Rev 21\n20.3.2 \nCounting mode\nThe counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), \nthen restarts from 0 and generates a counter overflow event.\nAn update event can be generate at each counter overflow or by setting the UG bit in the \nTIMx_EGR register (by software or by using the slave mode controller). \nThe UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 \nregister. This avoids updating the shadow registers while writing new values into the preload \nregisters. In this way, no update event occurs until the UDIS bit has been written to 0, \nhowever, the counter and the prescaler counter both restart from 0 (but the prescale rate \ndoes not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 \nregister is set, setting the UG bit generates an update event UEV, but the UIF flag is not set \n(so no interrupt or DMA request is sent). \nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in \nthe TIMx_SR register) is set (depending on the URS bit):\n•\nThe buffer of the prescaler is reloaded with the preload value (contents of the \nTIMx_PSC register)\n•\nThe auto-reload shadow register is updated with the preload value (TIMx_ARR)\nThe following figures show some examples of the counter behavior for different clock \nfrequencies when TIMx_ARR = 0x36.\nFigure 206. Counter timing diagram, internal clock divided by 1\nMS37364V1\n00\n02\n03\n04\n05\n06\n07\n33\n34\n35\n36\n31\nCK_INT\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n01\n32\n" }, { "page_number": 703, "page_indices": { "start_index": 1376306, "end_index": 1377017 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 703 }, "toc_details": [ [ 1, "20 Basic timers (TIM6 and TIM7)", 699 ], [ 2, "20.3 TIM6 and TIM7 functional description", 700 ], [ 3, "20.3.2 Counting mode", 702 ] ], "page_content": "RM0090 Rev 21\n703/1757\nRM0090\nBasic timers (TIM6 and TIM7)\n710\nFigure 207. Counter timing diagram, internal clock divided by 2\nFigure 208. Counter timing diagram, internal clock divided by 4\nFigure 209. Counter timing diagram, internal clock divided by N\nMS35835V1\nCK_INT\nCNT_EN\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n0034\n0035\n0036\n0000\n0001\n0002\n0003\n0000\n0001\n0035\n0036\nMSv37301V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\nCNT_EN\nMSv37302V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n1F\n20\n" }, { "page_number": 704, "page_indices": { "start_index": 1377017, "end_index": 1378239 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 704 }, "toc_details": [ [ 1, "20 Basic timers (TIM6 and TIM7)", 699 ], [ 2, "20.3 TIM6 and TIM7 functional description", 700 ], [ 3, "20.3.3 Clock source", 704 ] ], "page_content": "Basic timers (TIM6 and TIM7)\nRM0090\n704/1757\nRM0090 Rev 21\nFigure 210. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not\npreloaded)\nFigure 211. Counter timing diagram, update event when ARPE=1 (TIMx_ARR\npreloaded)\n20.3.3 \nClock source\nThe counter clock is provided by the Internal clock (CK_INT) source.\nThe CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual \ncontrol bits and can be changed only by software (except for UG that remains cleared \nautomatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal \nclock CK_INT.\nFigure 212 shows the behavior of the control circuit and the upcounter in normal mode, \nwithout prescaler.\nFF\n36\nMSv37303V1\nCK_INT\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n02 03\n04 05 06 07\n32\n33 34 35 36\n31\n01\nCNT_EN\nAuto-reload register\nWrite a new value in TIMx_ARR\nMSv37304V1\nF5\n36\nCK_PSC\nTimerclock = CK_CNT\nCounter register\nUpdate event (UEV)\nCounter overflow\nUpdate interrupt flag (UIF)\n00\n02 03 04\n05 06\n07\nF1 F2 F3 F4 F5\nF0\n01\nCNT_EN\nAuto-reload preload register\nWrite a new value in TIMx_ARR\nAuto-reload shadow register\nF5\n36\n" }, { "page_number": 705, "page_indices": { "start_index": 1378239, "end_index": 1379699 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 705 }, "toc_details": [ [ 1, "20 Basic timers (TIM6 and TIM7)", 699 ], [ 2, "20.3 TIM6 and TIM7 functional description", 700 ], [ 3, "20.3.4 Debug mode", 705 ], [ 2, "20.4 TIM6 and TIM7 registers", 705 ], [ 3, "20.4.1 TIM6 and TIM7 control register 1 (TIMx_CR1)", 705 ] ], "page_content": "RM0090 Rev 21\n705/1757\nRM0090\nBasic timers (TIM6 and TIM7)\n710\nFigure 212. Control circuit in normal mode, internal clock divided by 1\n20.3.4 \nDebug mode\nWhen the microcontroller enters the debug mode (Cortex®-M4 with FPU core - halted), the \nTIMx counter either continues to work normally or stops, depending on the \nDBG_TIMx_STOP configuration bit in the DBG module. For more details, refer to \nSection 38.16.2: Debug support for timers, watchdog, bxCAN and I2C.\n20.4 \nTIM6 and TIM7 registers\nRefer to Section 2.2 for a list of abbreviations used in register descriptions.\nThe peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read \naccesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). \n20.4.1 \nTIM6 and TIM7 control register 1 (TIMx_CR1)\nAddress offset: 0x00\nReset value: 0x0000\n \nInternal clock\nCounter clock = CK_CNT = CK_PSC\nCounter register\nCEN=CNT_EN\nUG\nCNT_INIT\nMS31085V2\n00\n02\n03\n04\n05\n06\n07\n3 2\n33\n34\n35 36\n31\n01\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nARPE\nReserved\nOPM\nURS\nUDIS\nCEN\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 ARPE: Auto-reload preload enable\n0: TIMx_ARR register is not buffered.\n1: TIMx_ARR register is buffered.\nBits 6:4 Reserved, must be kept at reset value.\nBit 3 OPM: One-pulse mode\n0: Counter is not stopped at update event\n1: Counter stops counting at the next update event (clearing the CEN bit).\n" }, { "page_number": 706, "page_indices": { "start_index": 1379699, "end_index": 1381089 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 706 }, "toc_details": [ [ 1, "20 Basic timers (TIM6 and TIM7)", 699 ], [ 2, "20.4 TIM6 and TIM7 registers", 705 ], [ 3, "20.4.1 TIM6 and TIM7 control register 1 (TIMx_CR1)", 705 ] ], "page_content": "Basic timers (TIM6 and TIM7)\nRM0090\n706/1757\nRM0090 Rev 21\nBit 2 URS: Update request source\nThis bit is set and cleared by software to select the UEV event sources.\n0: Any of the following events generates an update interrupt or DMA request if enabled. \nThese events can be: \n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\n1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.\nBit 1 UDIS: Update disable\nThis bit is set and cleared by software to enable/disable UEV event generation.\n0: UEV enabled. The Update (UEV) event is generated by one of the following events:\n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\nBuffered registers are then loaded with their preload values.\n1: UEV disabled. The Update event is not generated, shadow registers keep their value \n(ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if \na hardware reset is received from the slave mode controller.\nBit 0 CEN: Counter enable\n0: Counter disabled\n1: Counter enabled\nNote: Gated mode can work only if the CEN bit has been previously set by software. However \ntrigger mode can set the CEN bit automatically by hardware. \nCEN is cleared automatically in one-pulse mode, when an update event occurs.\n" }, { "page_number": 707, "page_indices": { "start_index": 1381089, "end_index": 1383233 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 707 }, "toc_details": [ [ 1, "20 Basic timers (TIM6 and TIM7)", 699 ], [ 2, "20.4 TIM6 and TIM7 registers", 705 ], [ 3, "20.4.2 TIM6 and TIM7 control register 2 (TIMx_CR2)", 707 ], [ 3, "20.4.3 TIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER)", 707 ] ], "page_content": "RM0090 Rev 21\n707/1757\nRM0090\nBasic timers (TIM6 and TIM7)\n710\n20.4.2 \nTIM6 and TIM7 control register 2 (TIMx_CR2)\nAddress offset: 0x04\nReset value: 0x0000\n \n20.4.3 \nTIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER)\nAddress offset: 0x0C\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMMS[2:0]\nReserved\nrw\nrw\nrw\nBits 15:7 Reserved, must be kept at reset value.\nBits 6:4 MMS[2:0]: Master mode selection\nThese bits are used to select the information to be sent in master mode to slave timers for \nsynchronization (TRGO). The combination is as follows:\n000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If \nreset is generated by the trigger input (slave mode controller configured in reset mode) then \nthe signal on TRGO is delayed compared to the actual reset.\n001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is \nuseful to start several timers at the same time or to control a window in which a slave timer \nis enabled. The Counter Enable signal is generated by a logic OR between CEN control bit \nand the trigger input when configured in gated mode. \nWhen the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, \nexcept if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR \nregister).\n010: Update - The update event is selected as a trigger output (TRGO). For instance a \nmaster timer can then be used as a prescaler for a slave timer.\nNote: The clock of the slave timer and ADC must be enabled prior to receiving events from \nthe master timer, and must not be changed on-the-fly while triggers are received from \nthe master timer.\nBits 3:0 Reserved, must be kept at reset value.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nUDE\nReserved\nUIE\nrw\nrw\nBits 15:9 Reserved, must be kept at reset value.\nBit 8 UDE: Update DMA request enable\n0: Update DMA request disabled.\n1: Update DMA request enabled.\nBits 7:1 Reserved, must be kept at reset value.\nBit 0 UIE: Update interrupt enable\n0: Update interrupt disabled.\n1: Update interrupt enabled.\n" }, { "page_number": 708, "page_indices": { "start_index": 1383233, "end_index": 1384661 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 708 }, "toc_details": [ [ 1, "20 Basic timers (TIM6 and TIM7)", 699 ], [ 2, "20.4 TIM6 and TIM7 registers", 705 ], [ 3, "20.4.4 TIM6 and TIM7 status register (TIMx_SR)", 708 ], [ 3, "20.4.5 TIM6 and TIM7 event generation register (TIMx_EGR)", 708 ], [ 3, "20.4.6 TIM6 and TIM7 counter (TIMx_CNT)", 708 ] ], "page_content": "Basic timers (TIM6 and TIM7)\nRM0090\n708/1757\nRM0090 Rev 21\n20.4.4 \nTIM6 and TIM7 status register (TIMx_SR)\nAddress offset: 0x10\nReset value: 0x0000\n \n20.4.5 \nTIM6 and TIM7 event generation register (TIMx_EGR)\nAddress offset: 0x14\nReset value: 0x0000\n \n20.4.6 \nTIM6 and TIM7 counter (TIMx_CNT)\nAddress offset: 0x24\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nUIF\nrc_w0\nBits 15:1 Reserved, must be kept at reset value.\nBit 0 UIF: Update interrupt flag\nThis bit is set by hardware on an update event. It is cleared by software.\n0: No update occurred.\n1: Update interrupt pending. This bit is set by hardware when the registers are updated:\n– At overflow or underflow and if UDIS = 0 in the TIMx_CR1 register.\n– When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 \nand UDIS = 0 in the TIMx_CR1 register.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nUG\nw\nBits 15:1 Reserved, must be kept at reset value.\nBit 0 UG: Update generation\nThis bit can be set by software, it is automatically cleared by hardware.\n0: No action.\n1: Re-initializes the timer counter and generates an update of the registers. Note that the \nprescaler counter is cleared too (but the prescaler ratio is not affected).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCNT[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0\nCNT[15:0]: Counter value\n" }, { "page_number": 709, "page_indices": { "start_index": 1384661, "end_index": 1385734 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 709 }, "toc_details": [ [ 1, "20 Basic timers (TIM6 and TIM7)", 699 ], [ 2, "20.4 TIM6 and TIM7 registers", 705 ], [ 3, "20.4.7 TIM6 and TIM7 prescaler (TIMx_PSC)", 709 ], [ 3, "20.4.8 TIM6 and TIM7 auto-reload register (TIMx_ARR)", 709 ] ], "page_content": "RM0090 Rev 21\n709/1757\nRM0090\nBasic timers (TIM6 and TIM7)\n710\n20.4.7 \nTIM6 and TIM7 prescaler (TIMx_PSC)\nAddress offset: 0x28\nReset value: 0x0000\n \n20.4.8 \nTIM6 and TIM7 auto-reload register (TIMx_ARR)\nAddress offset: 0x2C\nReset value: 0xFFFF\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPSC[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 PSC[15:0]: Prescaler value\nThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).\nPSC contains the value to be loaded in the active prescaler register at each update event \n(including when the counter is cleared through UG bit of TIMx_EGR register or through \ntrigger controller when configured in “reset mode”).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nARR[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 ARR[15:0]: Auto-reload value\nARR is the value to be loaded into the actual auto-reload register.\nRefer to Section 20.3.1: Time-base unit for more details about ARR update and behavior.\nThe counter is blocked while the auto-reload value is null.\n" }, { "page_number": 710, "page_indices": { "start_index": 1385734, "end_index": 1386739 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 710 }, "toc_details": [ [ 1, "20 Basic timers (TIM6 and TIM7)", 699 ], [ 2, "20.4 TIM6 and TIM7 registers", 705 ], [ 3, "20.4.9 TIM6 and TIM7 register map", 710 ] ], "page_content": "Basic timers (TIM6 and TIM7)\nRM0090\n710/1757\nRM0090 Rev 21\n20.4.9 \nTIM6 and TIM7 register map\nTIMx registers are mapped as 16-bit addressable registers as described in the table below. \n \nRefer to Section 2.3: Memory map for the register boundary addresses. \nTable 107. TIM6 and TIM7 register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nTIMx_CR1\nReserved\nARPE\nReserved\nOPM\nURS\nUDIS\nCEN\nReset value\n0\n0\n0\n0\n0\n0x04\nTIMx_CR2\nReserved\nMMS[2:0]\nReserved\nReset value\n0\n0\n0\n0x08\nReserved\n0x0C\nTIMx_DIER\nReserved\nUDE\nReserved\nUIE\nReset value\n0\n0\n0x10\nTIMx_SR\nReserved\nUIF\nReset value\n0\n0x14\nTIMx_EGR\nReserved\nUG\nReset value\n0\n0x18\nReserved\n0x1C\nReserved\n0x20\nReserved\n0x24\nTIMx_CNT\nReserved\nCNT[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nTIMx_PSC\nReserved\nPSC[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x2C\nTIMx_ARR\nReserved\nARR[15:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n" }, { "page_number": 711, "page_indices": { "start_index": 1386739, "end_index": 1389243 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 711 }, "toc_details": [ [ 1, "21 Independent watchdog (IWDG)", 711 ], [ 2, "21.1 IWDG introduction", 711 ], [ 2, "21.2 IWDG main features", 711 ], [ 2, "21.3 IWDG functional description", 711 ], [ 3, "21.3.1 Hardware watchdog", 711 ], [ 3, "21.3.2 Register access protection", 711 ] ], "page_content": "RM0090 Rev 21\n711/1757\nRM0090\nIndependent watchdog (IWDG)\n715\n21 \nIndependent watchdog (IWDG)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n21.1 \nIWDG introduction\nThe devices have two embedded watchdog peripherals which offer a combination of high \nsafety level, timing accuracy and flexibility of use. Both watchdog peripherals (Independent \nand Window) serve to detect and resolve malfunctions due to software failure, and to trigger \nsystem reset or an interrupt (window watchdog only) when the counter reaches a given \ntimeout value.\nThe independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI) \nand thus stays active even if the main clock fails. The window watchdog (WWDG) clock is \nprescaled from the APB1 clock and has a configurable time-window that can be \nprogrammed to detect abnormally late or early application behavior.\nThe IWDG is best suited to applications which require the watchdog to run as a totally \nindependent process outside the main application, but have lower timing accuracy \nconstraints. The WWDG is best suited to applications which require the watchdog to react \nwithin an accurate timing window. For further information on the window watchdog, refer to \nSection 22 on page 716.\n21.2 \nIWDG main features\n•\nFree-running downcounter\n•\nclocked from an independent RC oscillator (can operate in Standby and Stop modes)\n•\nReset (if watchdog activated) when the downcounter value of 0x000 is reached\n21.3 \nIWDG functional description\nFigure 213 shows the functional blocks of the independent watchdog module. \nWhen the independent watchdog is started by writing the value 0xCCCC in the Key register \n(IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it \nreaches the end of count value (0x000) a reset signal is generated (IWDG reset).\nWhenever the key value 0xAAAA is written in the IWDG_KR register, the IWDG_RLR value \nis reloaded in the counter and the watchdog reset is prevented.\n21.3.1 \nHardware watchdog\nIf the “Hardware watchdog” feature is enabled through the device option bits, the watchdog \nis automatically enabled at power-on, and generates a reset unless the Key register is \nwritten by the software before the counter reaches end of count.\n21.3.2 \nRegister access protection\nWrite access to the IWDG_PR and IWDG_RLR registers is protected. To modify them, first \nwrite the code 0x5555 in the IWDG_KR register. A write access to this register with a \n" }, { "page_number": 712, "page_indices": { "start_index": 1389243, "end_index": 1390766 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 712 }, "toc_details": [ [ 1, "21 Independent watchdog (IWDG)", 711 ], [ 2, "21.3 IWDG functional description", 711 ], [ 3, "21.3.3 Debug mode", 712 ] ], "page_content": "Independent watchdog (IWDG)\nRM0090\n712/1757\nRM0090 Rev 21\ndifferent value breaks the sequence and register access is protected again. This implies that \nit is the case of the reload operation (writing 0xAAAA).\nA status register is available to indicate that an update of the prescaler or the down-counter \nreload value is on going.\n21.3.3 \nDebug mode\nWhen the microcontroller enters debug mode (Cortex®-M4 with FPU core halted), the IWDG \ncounter either continues to work normally or stops, depending on DBG_IWDG_STOP \nconfiguration bit in DBG module. For more details, refer to Section 38.16.2: Debug support \nfor timers, watchdog, bxCAN and I2C.\nFigure 213. Independent watchdog block diagram\nNote:\nThe watchdog function is implemented in the VDD voltage domain, still functional in Stop and \nStandby modes.\n \nIWDG reset\nprescaler\nIWDG_PR\nPrescaler register\nIWDG_RLR\nReload register\n8-bit\nLSI\n(40 kHz) \nIWDG_KR\nKey register\n \nCORE\n VDD voltage domain\nIWDG_SR\nStatus register\n \nMS19944V2\n12-bit reload value\n12-bit downcounter\n \nTable 108. Min/max IWDG timeout period (in ms) at 32 kHz (LSI)(1)\n1.\nThese timings are given for a 32 kHz clock but the microcontroller internal RC frequency can vary. Refer to \nthe LSI oscillator characteristics table in the device datasheet for maximum and minimum values.\nPrescaler divider\nPR[2:0] bits\nMin timeout RL[11:0]= 0x000\nMax timeout RL[11:0]= 0xFFF\n/4\n0\n0.125\n512\n/8\n1\n0.25\n1024\n/16\n2\n0.5\n2048\n/32\n3\n1\n4096\n/64\n4\n2\n8192\n/128\n5\n4\n16384\n/256\n6\n8\n32768\n" }, { "page_number": 713, "page_indices": { "start_index": 1390766, "end_index": 1392722 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 713 }, "toc_details": [ [ 1, "21 Independent watchdog (IWDG)", 711 ], [ 2, "21.4 IWDG registers", 713 ], [ 3, "21.4.1 Key register (IWDG_KR)", 713 ], [ 3, "21.4.2 Prescaler register (IWDG_PR)", 713 ] ], "page_content": "RM0090 Rev 21\n713/1757\nRM0090\nIndependent watchdog (IWDG)\n715\n21.4 \nIWDG registers\nRefer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.\nThe peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).\n21.4.1 \nKey register (IWDG_KR)\nAddress offset: 0x00\nReset value: 0x0000 0000 (reset by Standby mode)\n \n21.4.2 \nPrescaler register (IWDG_PR)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nKEY[15:0]\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 KEY[15:0]: Key value (write only, read 0000h)\nThese bits must be written by software at regular intervals with the key value AAAAh, \notherwise the watchdog generates a reset when the counter reaches 0. \nWriting the key value 5555h to enable access to the IWDG_PR and IWDG_RLR registers \n(see Section 21.3.2)\nWriting the key value CCCCh starts the watchdog (except if the hardware watchdog option is \nselected)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPR[2:0]\nrw\nrw\nrw\nBits 31:3 Reserved, must be kept at reset value.\nBits 2:0 PR[2:0]: Prescaler divider \nThese bits are write access protected seeSection 21.3.2. They are written by software to \nselect the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in \norder to be able to change the prescaler divider.\n000: divider /4\n001: divider /8\n010: divider /16\n011: divider /32\n100: divider /64\n101: divider /128\n110: divider /256\n111: divider /256\nNote: Reading this register returns the prescaler value from the VDD voltage domain. This \nvalue may not be up to date/valid if a write operation to this register is ongoing. For this \nreason the value read from this register is valid only when the PVU bit in the IWDG_SR \nregister is reset.\n" }, { "page_number": 714, "page_indices": { "start_index": 1392722, "end_index": 1395333 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 714 }, "toc_details": [ [ 1, "21 Independent watchdog (IWDG)", 711 ], [ 2, "21.4 IWDG registers", 713 ], [ 3, "21.4.3 Reload register (IWDG_RLR)", 714 ], [ 3, "21.4.4 Status register (IWDG_SR)", 714 ] ], "page_content": "Independent watchdog (IWDG)\nRM0090\n714/1757\nRM0090 Rev 21\n21.4.3 \nReload register (IWDG_RLR)\nAddress offset: 0x08\nReset value: 0x0000 0FFF (reset by Standby mode)\n \n21.4.4 \nStatus register (IWDG_SR)\nAddress offset: 0x0C\nReset value: 0x0000 0000 (not reset by Standby mode)\n \n \nNote:\nIf several reload values or prescaler values are used by application, it is mandatory to wait \nuntil RVU bit is reset before changing the reload value and to wait until PVU bit is reset \nbefore changing the prescaler value. However, after updating the prescaler and/or the \nreload value it is not necessary to wait until RVU or PVU is reset before continuing code \nexecution (even in case of low-power mode entry, the write operation is taken into account \nand completes)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRL[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits11:0 RL[11:0]: Watchdog counter reload value \nThese bits are write access protected see Section 21.3.2. They are written by software to \ndefine the value to be loaded in the watchdog counter each time the value AAAAh is written \nin the IWDG_KR register. The watchdog counter counts down from this value. The timeout \nperiod is a function of this value and the clock prescaler. Refer to Table 108. \nThe RVU bit in the IWDG_SR register must be reset in order to be able to change the reload \nvalue.\nNote: Reading this register returns the reload value from the VDD voltage domain. This value \nmay not be up to date/valid if a write operation to this register is ongoing on this \nregister. For this reason the value read from this register is valid only when the RVU bit \nin the IWDG_SR register is reset.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRVU PVU\nr\nr\nBits 31:2 Reserved, must be kept at reset value.\nBit 1 RVU: Watchdog counter reload value update \nThis bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset \nby hardware when the reload value update operation is completed in the VDD voltage domain \n(takes up to 5 RC 40 kHz cycles).\nReload value can be updated only when RVU bit is reset.\nBit 0 PVU: Watchdog prescaler value update\nThis bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is \nreset by hardware when the prescaler update operation is completed in the VDD voltage \ndomain (takes up to 5 RC 40 kHz cycles).\nPrescaler value can be updated only when PVU bit is reset.\n" }, { "page_number": 715, "page_indices": { "start_index": 1395333, "end_index": 1395976 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 715 }, "toc_details": [ [ 1, "21 Independent watchdog (IWDG)", 711 ], [ 2, "21.4 IWDG registers", 713 ], [ 3, "21.4.5 IWDG register map", 715 ] ], "page_content": "RM0090 Rev 21\n715/1757\nRM0090\nIndependent watchdog (IWDG)\n715\n21.4.5 \nIWDG register map\nThe following table gives the IWDG register map and reset values. \n \nRefer to Section 2.3: Memory map for the register boundary addresses.\nTable 109. IWDG register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nIWDG_KR\nReserved\nKEY[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nIWDG_PR\nReserved\nPR[2:0]\nReset value\n0\n0\n0\n0x08\nIWDG_RLR\nReserved\nRL[11:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x0C\nIWDG_SR\nReserved\nRVU\nPVU\nReset value\n0\n0\n" }, { "page_number": 716, "page_indices": { "start_index": 1395976, "end_index": 1397584 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 716 }, "toc_details": [ [ 1, "22 Window watchdog (WWDG)", 716 ], [ 2, "22.1 WWDG introduction", 716 ], [ 2, "22.2 WWDG main features", 716 ], [ 2, "22.3 WWDG functional description", 716 ] ], "page_content": "Window watchdog (WWDG)\nRM0090\n716/1757\nRM0090 Rev 21\n22 \nWindow watchdog (WWDG)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n22.1 \nWWDG introduction\nThe window watchdog is used to detect the occurrence of a software fault, usually \ngenerated by external interference or by unforeseen logical conditions, which causes the \napplication program to abandon its normal sequence. The watchdog circuit generates an \nMCU reset on expiry of a programmed time period, unless the program refreshes the \ncontents of the downcounter before the T6 bit becomes cleared. An MCU reset is also \ngenerated if the 7-bit downcounter value (in the control register) is refreshed before the \ndowncounter has reached the window register value. This implies that the counter must be \nrefreshed in a limited window.\n22.2 \nWWDG main features\n•\nProgrammable free-running downcounter \n•\nConditional reset\n–\nReset (if watchdog activated) when the downcounter value becomes less than \n0x40\n–\nReset (if watchdog activated) if the downcounter is reloaded outside the window \n(see Figure 215)\n•\nEarly wake-up interrupt (EWI): triggered (if enabled and the watchdog activated) when \nthe downcounter is equal to 0x40. \n22.3 \nWWDG functional description\nIf the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the \n7-bit downcounter (T[6:0] bits) rolls over from 0x40 to 0x3F (T6 becomes cleared), it initiates \na reset. If the software reloads the counter while the counter is greater than the value stored \nin the window register, then a reset is generated.\n" }, { "page_number": 717, "page_indices": { "start_index": 1397584, "end_index": 1399825 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 717 }, "toc_details": [ [ 1, "22 Window watchdog (WWDG)", 716 ], [ 2, "22.3 WWDG functional description", 716 ], [ 3, "Enabling the watchdog", 717 ], [ 3, "Controlling the downcounter", 717 ], [ 3, "Advanced watchdog interrupt feature", 717 ] ], "page_content": "RM0090 Rev 21\n717/1757\nRM0090\nWindow watchdog (WWDG)\n722\nFigure 214. Watchdog block diagram\nThe application program must write in the WWDG_CR register at regular intervals during \nnormal operation to prevent an MCU reset. This operation must occur only when the counter \nvalue is lower than the window register value. The value to be stored in the WWDG_CR \nregister must be between 0xFF and 0xC0.\nEnabling the watchdog\nThe watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the \nWWDG_CR register, then it cannot be disabled again except by a reset.\nControlling the downcounter\nThis downcounter is free-running, counting down even if the watchdog is disabled. When \nthe watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset. \nThe T[5:0] bits contain the number of increments which represents the time delay before the \nwatchdog produces a reset. The timing varies between a minimum and a maximum value \ndue to the unknown status of the prescaler when writing to the WWDG_CR register (see \nFigure 215). The Configuration register (WWDG_CFR) contains the high limit of the window: \nTo prevent a reset, the downcounter must be reloaded when its value is lower than the \nwindow register value and greater than 0x3F. Figure 215 describes the window watchdog \nprocess.\nNote:\nThe T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is \ncleared).\nAdvanced watchdog interrupt feature \nThe Early Wake-up Interrupt (EWI) can be used if specific safety operations or data logging \nmust be performed before the actual reset is generated. The EWI interrupt is enabled by \nsetting the EWI bit in the WWDG_CFR register. When the downcounter reaches the value \n0x40, an EWI interrupt is generated and the corresponding interrupt service routine (ISR) \ncan be used to trigger specific actions (such as communications or data logging), before \nresetting the device. \n06Y\u0016\u001a\u0015\u0015\u00199\u0015\n5(6(7\n\u001a\u0010ELW\u0003GRZQFRXQWHU\u0003\u000b&17\f\n:DWFKGRJ\u0003FRQILJXUDWLRQ\u0003UHJLVWHU\u0003\u000b::'*B&)5\f\nFRPSDUDWRU\n7\u0019\u001d\u0013\u0003!\u0003:\u0019\u001d\u0013\n \u0014\u0003ZKHQ\n:ULWH\u0003::'*B&5\n3&/.\u0014\n\u000bIURP\u00035&&\u0003FORFN\u0003FRQWUROOHU\f\n:'*\u0003SUHVFDOHU\n\u000b:'*7%\f\n\u0010\n:\u0019\n:\u0014\n:\u0015\n:\u0016\n:\u0017\n:\u0018\n:\u0013\n\u0012\u0017\u0013\u001c\u0019\n:'*$\n7\u0019\n:DWFKGRJ\u0003FRQWURO\u0003UHJLVWHU\u0003\u000b::'*B&5\f\n7\u0014\n7\u0015\n7\u0016\n7\u0017\n7\u0018\n7\u0013\n" }, { "page_number": 718, "page_indices": { "start_index": 1399825, "end_index": 1400983 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 718 }, "toc_details": [ [ 1, "22 Window watchdog (WWDG)", 716 ], [ 2, "22.4 How to program the watchdog timeout", 718 ] ], "page_content": "Window watchdog (WWDG)\nRM0090\n718/1757\nRM0090 Rev 21\nIn some applications, the EWI interrupt can be used to manage a software system check \nand/or system recovery/graceful degradation, without generating a WWDG reset. In this \ncase, the corresponding interrupt service routine (ISR) should reload the WWDG counter to \navoid the WWDG reset, then trigger the required actions. \nThe EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register. \nNote:\nWhen the EWI interrupt cannot be served (due to a system lock in a higher priority task), the \nWWDG reset is eventually generated. \n22.4 \nHow to program the watchdog timeout\nWarning:\nWhen writing to the WWDG_CR register, always write 1 in the \nT6 bit to avoid generating an immediate reset. \nFigure 215. Window watchdog timing diagram\nThe formula to calculate the WWDG timeout value is given by:\nwhere:\ntWWDG: WWDG timeout\ntPCLK1: APB1 clock period measured in ms\n4096: value corresponding to internal divider\nai17101c\nW[6:0]\nT[6:0] CNT downcounter\nRefresh not allowed\n0x3F\nRefresh allowed\nTime\nT6 bit\nRESET\ntWWDG\ntPCLK1\n4096\n×\n2WDGTB[1:0]\n×\nT[5:0]\n1\n+\n(\n)\n×\n=\nms\n(\n)\n" }, { "page_number": 719, "page_indices": { "start_index": 1400983, "end_index": 1401832 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 719 }, "toc_details": [ [ 1, "22 Window watchdog (WWDG)", 716 ], [ 2, "22.5 Debug mode", 719 ] ], "page_content": "RM0090 Rev 21\n719/1757\nRM0090\nWindow watchdog (WWDG)\n722\nAs an example, let us assume APB1 frequency is equal to 24 MHz, WDGTB[1:0] is set to 3 \nand T[5:0] is set to 63: \nRefer to Table 110 for the minimum and maximum values of the tWWDG.\n \n22.5 \nDebug mode\nWhen the microcontroller enters debug mode (Cortex®-M4 with FPU core halted), the \nWWDG counter either continues to work normally or stops, depending on \nDBG_WWDG_STOP configuration bit in DBG module. For more details, refer to \nSection 38.16.2: Debug support for timers, watchdog, bxCAN and I2C.\nTable 110. Minimum and maximum timeout values at 30 MHz (fPCLK1)\nPrescaler\nWDGTB\nMin timeout (µs)\nT[5:0] = 0x00\nMax timeout (ms)\nT[5:0] = 0x3F\n1\n0\n136.53\n8.74\n2\n1\n273.07\n17.48\n4\n2\n546.13\n34.95\n8\n3\n1092.27\n69.91\ntWWDG\n1\n24000\n⁄\n4096\n×\n23\n×\n63\n1\n+\n(\n)\n×\n21.85ms\n=\n=\n" }, { "page_number": 720, "page_indices": { "start_index": 1401832, "end_index": 1402810 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 720 }, "toc_details": [ [ 1, "22 Window watchdog (WWDG)", 716 ], [ 2, "22.6 WWDG registers", 720 ], [ 3, "22.6.1 Control register (WWDG_CR)", 720 ] ], "page_content": "Window watchdog (WWDG)\nRM0090\n720/1757\nRM0090 Rev 21\n22.6 \nWWDG registers\nRefer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.\nThe peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).\n22.6.1 \nControl register (WWDG_CR)\nAddress offset: 0x00\nReset value: 0x0000 007F\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nWDGA\nT[6:0]\nrs\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBit 7 WDGA: Activation bit \nThis bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the \nwatchdog can generate a reset.\n0: Watchdog disabled\n1: Watchdog enabled\nBits 6:0 T[6:0]: 7-bit counter (MSB to LSB)\nThese bits contain the value of the watchdog counter. It is decremented every (4096 x \n2WDGTB[1:0]) PCLK1 cycles. A reset is produced when it rolls over from 0x40 to 0x3F (T6 \nbecomes cleared).\n" }, { "page_number": 721, "page_indices": { "start_index": 1402810, "end_index": 1404238 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 721 }, "toc_details": [ [ 1, "22 Window watchdog (WWDG)", 716 ], [ 2, "22.6 WWDG registers", 720 ], [ 3, "22.6.2 Configuration register (WWDG_CFR)", 721 ], [ 3, "22.6.3 Status register (WWDG_SR)", 721 ] ], "page_content": "RM0090 Rev 21\n721/1757\nRM0090\nWindow watchdog (WWDG)\n722\n22.6.2 \nConfiguration register (WWDG_CFR)\nAddress offset: 0x04\nReset value: 0x0000 007F\n \n \n22.6.3 \nStatus register (WWDG_SR)\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nEWI\nWDGTB[1:0]\nW[6:0]\nrs\nrw\nrw\nBit 31:10 Reserved, must be kept at reset value.\nBit 9 EWI: Early wake-up interrupt\nWhen set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is \nonly cleared by hardware after a reset. \nBits 8:7 WDGTB[1:0]: Timer base\nThe time base of the prescaler can be modified as follows:\n00: CK Counter Clock (PCLK1 div 4096) div 1\n01: CK Counter Clock (PCLK1 div 4096) div 2\n10: CK Counter Clock (PCLK1 div 4096) div 4\n11: CK Counter Clock (PCLK1 div 4096) div 8\nBits 6:0 W[6:0]: 7-bit window value\nThese bits contain the window value to be compared to the downcounter.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nEWIF\nrc_w0\nBits 31:1 Reserved, must be kept at reset value.\nBit 0 EWIF: Early wake-up interrupt flag\nThis bit is set by hardware when the counter has reached the value 0x40. It must be cleared \nby software by writing ‘0’. A write of ‘1’ has no effect. This bit is also set if the interrupt is not \nenabled. \n" }, { "page_number": 722, "page_indices": { "start_index": 1404238, "end_index": 1404817 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 722 }, "toc_details": [ [ 1, "22 Window watchdog (WWDG)", 716 ], [ 2, "22.6 WWDG registers", 720 ], [ 3, "22.6.4 WWDG register map", 722 ] ], "page_content": "Window watchdog (WWDG)\nRM0090\n722/1757\nRM0090 Rev 21\n22.6.4 \nWWDG register map\nThe following table gives the WWDG register map and reset values. \n \nRefer to Section 2.3: Memory map for the register boundary addresses.\nTable 111. WWDG register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nWWDG_CR\nReserved\nWDGA\nT[6:0]\nReset value\n0\n1\n1\n1\n1\n1\n1\n1\n0x04\nWWDG_CFR\nReserved\nEWI\nWDGTB1\nWDGTB0\nW[6:0]\nReset value\n0\n0\n0\n1\n1\n1\n1\n1\n1\n1\n0x08\nWWDG_SR\nReserved\nEWIF\nReset value\n0\n" }, { "page_number": 723, "page_indices": { "start_index": 1404817, "end_index": 1406671 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 723 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.1 CRYP introduction", 723 ], [ 2, "23.2 CRYP main features", 723 ] ], "page_content": "RM0090 Rev 21\n723/1757\nRM0090\nCryptographic processor (CRYP)\n769\n23 \nCryptographic processor (CRYP)\nThis section applies to STM32F415/417xx and STM32F43xxx devices.\n23.1 \nCRYP introduction\nThe cryptographic processor can be used to both encipher and decipher data using the \nDES, Triple-DES or AES (128, 192, or 256) algorithms. It is a fully compliant implementation \nof the following standards:\n•\nThe data encryption standard (DES) and Triple-DES (TDES) as defined by Federal \nInformation Processing Standards Publication (FIPS PUB 46-3, 1999 October 25). It \nfollows the American National Standards Institute (ANSI) X9.52 standard.\n•\nThe advanced encryption standard (AES) as defined by Federal Information \nProcessing Standards Publication (FIPS PUB 197, 2001 November 26)\nThe CRYP processor performs data encryption and decryption using DES and TDES \nalgorithms in Electronic codebook (ECB) or Cipher block chaining (CBC) mode.\nThe CRYP peripheral is a 32-bit AHB2 peripheral. It supports DMA transfer for incoming and \nprocessed data, and has input and output FIFOs (each 8 words deep).\n23.2 \nCRYP main features\n•\nSuitable for AES, DES and TDES enciphering and deciphering operations\n•\nAES\n–\nSupports the ECB, CBC, CTR, CCM and GCM chaining algorithms (CCM and \nGCM are available on STM32F42xxx and STM32F43xxx only)\n–\nSupports 128-, 192- and 256-bit keys\n–\n4 × 32-bit initialization vectors (IV) used in the CBC, CTR, CCM and GCM modes\n \n \nTable 112. Number of cycles required to process each 128-bit block\n(STM32F415/417xx)\nAlgorithm / Key size\nECB\nCBC\nCTR\n128b\n14\n14\n14\n192b\n16\n16\n16\n256b\n18\n18\n18\nTable 113. Number of cycles required to process each 128-bit block\n(STM32F43xxx)\nAlgorithm / \nKey size\nECB\nCBC\nCTR\nGCM\nCCM\nInit\nHeader\nPayload\nTag\nInit\nHeader\nPayload\nTag\n128b\n14\n14\n14\n24\n10\n14\n14\n12\n14\n25\n14\n" }, { "page_number": 724, "page_indices": { "start_index": 1406671, "end_index": 1407614 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 724 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.2 CRYP main features", 723 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n724/1757\nRM0090 Rev 21\n•\nDES/TDES\n–\nDirect implementation of simple DES algorithms (a single key, K1, is used)\n–\nSupports the ECB and CBC chaining algorithms\n–\nSupports 64-, 128- and 192-bit keys (including parity)\n–\n2 × 32-bit initialization vectors (IV) used in the CBC mode\n–\n16 HCLK cycles to process one 64-bit block in DES\n–\n48 HCLK cycles to process one 64-bit block in TDES\n•\nCommon to DES/TDES and AES\n–\nIN and OUT FIFO (each with an 8-word depth, a 32-bit width, corresponding to 4 \nDES blocks or 2 AES blocks)\n–\nAutomatic data flow control with support of direct memory access (DMA) (using 2 \nchannels, one for incoming data the other for processed data)\n–\nData swapping logic to support 1-, 8-, 16- or 32-bit data\n192b\n16\n16\n16\n28\n10\n16\n16\n14\n16\n29\n16\n256b\n18\n18\n18\n32\n10\n18\n18\n16\n18\n33\n18\nTable 113. Number of cycles required to process each 128-bit block\n(STM32F43xxx)\n" }, { "page_number": 725, "page_indices": { "start_index": 1407614, "end_index": 1408698 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 725 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ] ], "page_content": "RM0090 Rev 21\n725/1757\nRM0090\nCryptographic processor (CRYP)\n769\n23.3 \nCRYP functional description\nThe cryptographic processor implements a Triple-DES (TDES, that also supports DES) core \nand an AES cryptographic core. Section 23.3.1 and Section 23.3.2 provide details on these \ncores.\nSince the TDES and the AES algorithms use block ciphers, incomplete input data blocks \nhave to be padded prior to encryption (extra bits should be appended to the trailing end of \nthe data string). After decryption, the padding has to be discarded. The hardware does not \nmanage the padding operation, the software has to handle it.\nFigure 216 shows the block diagram of the cryptographic processor.\nFigure 216. Block diagram (STM32F415/417xx)\n32-bit AHB2 bus\n \nProcessor core\nDES/TDES/AES\nCRYP_DIN\nswappi ng\nswappin g\n8 × 32-bit\nIN FIFO\n8 × 32-bit\nOUT FIFO\nCRYP_CR\nCRYP_K0...K3\nCRYP_IV0...IV1\nIV0...IV127\nk255...k0\nCRYP_IMSCR\nCRYP_RIS\nCRYP_MISR\nCRYP_DMACR\nCRYP_SR\nStatus\nDMA control register\nInterrupt registers\nControl register\nInitialization vectors\nKey\nai16068b\nCRYP_DOUT\n" }, { "page_number": 726, "page_indices": { "start_index": 1408698, "end_index": 1410063 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 726 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.1 DES/TDES cryptographic core", 726 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n726/1757\nRM0090 Rev 21\nFigure 217. Block diagram (STM32F43xxx)\n23.3.1 \nDES/TDES cryptographic core\nThe DES/Triple-DES cryptographic core consists of three components:\n•\nThe DES algorithm (DEA)\n•\nMultiple keys (1 for the DES algorithm, 1 to 3 for the TDES algorithm)\n•\nThe initialization vector (used in the CBC mode)\nThe basic processing involved in the TDES is as follows: an input block is read in the DEA \nand encrypted using the first key, K1 (K0 is not used in TDES mode). The output is then \ndecrypted using the second key, K2, and encrypted using the third key, K3. The key \ndepends on the algorithm which is used: \n•\nDES mode: Key = [K1]\n•\nTDES mode: Key = [K3 K2 K1]\nwhere Kx=[KxR KxL], R = right, L = left\nAccording to the mode implemented, the resultant output block is used to calculate the \nciphertext.\nNote that the outputs of the intermediate DEA stages is never revealed outside the \ncryptographic boundary.\n32-bit AHB2 bus\nProcessor core\nDES/TDES/AES\nCRYP_DIN\nCRYP_DOUT\nswappi ng\nswappin g\n8 × 32-bit\nIN FIFO\n8 × 32-bit\nOUT FIFO\nCRYP_CR\nCRYP_K0...K3\nCRYP_IV0...IV1\nIV0...IV127\nk255...k0\nCRYP_IMSCR\nCRYP_RIS\nCRYP_MISR\nCRYP_DMACR\nCRYP_SR\nStatus\nDMA control register\nInterrupt registers\nControl register\nInitialization vectors\nKey\nMS30441V1\nCRYP_CSGCMCCM0..7\nContext swapping\nCRYP_CSGCM0..7\n" }, { "page_number": 727, "page_indices": { "start_index": 1410063, "end_index": 1412799 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 727 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.1 DES/TDES cryptographic core", 726 ], [ 4, "DES and TDES Electronic codebook (DES/TDES-ECB) mode", 727 ] ], "page_content": "RM0090 Rev 21\n727/1757\nRM0090\nCryptographic processor (CRYP)\n769\nThe TDES allows three different keying options:\n•\nThree independent keys\nThe first option specifies that all the keys are independent, that is, K1, K2 and K3 are \nindependent. FIPS PUB 46-3 – 1999 (and ANSI X9.52 – 1998) refers to this option as \nthe Keying Option 1 and, to the TDES as 3-key TDES.\n•\nTwo independent keys\nThe second option specifies that K1 and K2 are independent and K3 is equal to K1, \nthat is, K1 and K2 are independent, K3 = K1. FIPS PUB 46-3 – 1999 (and ANSI X9.52 \n– 1998) refers to this second option as the Keying Option 2 and, to the TDES as 2-key \nTDES.\n•\nThree equal keys\nThe third option specifies that K1, K2 and K3 are equal, that is, K1 = K2 = K3. FIPS \nPUB 46-3 – 1999 (and ANSI X9.52 – 1998) refers to the third option as the Keying \nOption 3. This “1-key” TDES is equivalent to single DES.\nFIPS PUB 46-3 – 1999 (and ANSI X9.52-1998) provides a thorough explanation of the \nprocessing involved in the four operation modes supplied by the TDEA (TDES algorithm): \nTDES-ECB encryption, TDES-ECB decryption, TDES-CBC encryption and TDES-CBC \ndecryption.\nThis reference manual only gives a brief explanation of each mode.\nDES and TDES Electronic codebook (DES/TDES-ECB) mode\n•\nDES/TDES-ECB mode encryption\nFigure 218 illustrates the encryption in DES and TDES Electronic codebook \n(DES/TDES-ECB) mode. A 64-bit plaintext data block (P) is used after bit/byte/half-\nword swapping (refer to Section 23.3.3: Data type on page 742) as the input block (I). \nThe input block is processed through the DEA in the encrypt state using K1. The output \nof this process is fed back directly to the input of the DEA where the DES is performed \nin the decrypt state using K2. The output of this process is fed back directly to the input \nof the DEA where the DES is performed in the encrypt state using K3. The resultant 64-\nbit output block (O) is used, after bit/byte/half-word swapping, as ciphertext (C) and it is \npushed into the OUT FIFO.\n•\nDES/TDES-ECB mode decryption\nFigure 219 illustrates the DES/TDES-ECB decryption. A 64-bit ciphertext block (C) is \nused, after bit/byte/half-word swapping, as the input block (I). The keying sequence is \nreversed compared to that used in the encryption process. The input block is \nprocessed through the DEA in the decrypt state using K3. The output of this process is \nfed back directly to the input of the DEA where the DES is performed in the encrypt \nstate using K2. The new result is directly fed to the input of the DEA where the DES is \nperformed in the decrypt state using K1. The resultant 64-bit output block (O), after \nbit/byte/half-word swapping, produces the plaintext (P).\n" }, { "page_number": 728, "page_indices": { "start_index": 1412799, "end_index": 1413480 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 728 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.1 DES/TDES cryptographic core", 726 ], [ 4, "DES and TDES Electronic codebook (DES/TDES-ECB) mode", 727 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n728/1757\nRM0090 Rev 21\nFigure 218. DES/TDES-ECB mode encryption\n1.\nK: key; C: cipher text; I: input block; O: output block; P: plain text.\nFigure 219. DES/TDES-ECB mode decryption\n1.\nK: key; C: cipher text; I: input block; O: output block; P: plain text.\nIN FIFO\nDEA, encrypt\nK1\nP, 64 bits\nDEA, decrypt\nK2\nDEA, encrypt\nK3\nOUT FIFO\nplaintext P\nciphertext C\n64\n64\n64\nswapping\nO, 64 bits\nC, 64 bits\nswapping\nDATATYPE\nDATATYPE\nai16069b\nIN FIFO\nC, 64 bits\nOUT FIFO\nciphertext C\nplaintext P\nDEA, decrypt\nK3\nDEA, encrypt\nK2\nDEA, decrypt\nK1\n64\n64\n64\nI, 64 bits\nswapping\nO, 64 bits\nDATATYPE\nDATATYPE\nP, 64 bits\nswapping\nMS19021V1\n" }, { "page_number": 729, "page_indices": { "start_index": 1413480, "end_index": 1416373 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 729 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.1 DES/TDES cryptographic core", 726 ], [ 4, "DES and TDES Cipher block chaining (DES/TDES-CBC) mode", 729 ] ], "page_content": "RM0090 Rev 21\n729/1757\nRM0090\nCryptographic processor (CRYP)\n769\nDES and TDES Cipher block chaining (DES/TDES-CBC) mode\n•\nDES/TDES-CBC mode encryption\nFigure 220 illustrates the DES and Triple-DES Cipher block chaining (DES/TDES-\nCBC) mode encryption. This mode begins by dividing a plaintext message into 64-bit \ndata blocks. In TCBC encryption, the first input block (I1), obtained after bit/byte/half-\nword swapping (refer to Section 23.3.3: Data type on page 742), is formed by \nexclusive-ORing the first plaintext data block (P1) with a 64-bit initialization vector IV (I1 \n= IV ⊕ P1). The input block is processed through the DEA in the encrypt state using K1. \nThe output of this process is fed back directly to the input of the DEA, which performs \nthe DES in the decrypt state using K2. The output of this process is fed directly to the \ninput of the DEA, which performs the DES in the encrypt state using K3. The resultant \n64-bit output block (O1) is used directly as the ciphertext (C1), that is, C1 = O1. This first \nciphertext block is then exclusive-ORed with the second plaintext data block to produce \nthe second input block, (I2) = (C1 ⊕ P2). Note that I2 and P2 now refer to the second \nblock. The second input block is processed through the TDEA to produce the second \nciphertext block. This encryption process continues to “chain” successive cipher and \nplaintext blocks together until the last plaintext block in the message is encrypted. If the \nmessage does not consist of an integral number of data blocks, then the final partial \ndata block should be encrypted in a manner specified for the application.\n•\nDES/TDES-CBC mode decryption\nIn DES/TDES-CBC decryption (see Figure 221), the first ciphertext block (C1) is used \ndirectly as the input block (I1). The keying sequence is reversed compared to that used \nfor the encrypt process. The input block is processed through the DEA in the decrypt \nstate using K3. The output of this process is fed directly to the input of the DEA where \nthe DES is processed in the encrypt state using K2. This resulting value is directly fed \nto the input of the DEA where the DES is processed in the decrypt state using K1. The \nresulting output block is exclusive-ORed with the IV (which must be the same as that \nused during encryption) to produce the first plaintext block (P1 = O1 ⊕ IV). The second \nciphertext block is then used as the next input block and is processed through the \nTDEA. The resulting output block is exclusive-ORed with the first ciphertext block to \nproduce the second plaintext data block (P2 = O2 ⊕ C1). (Note that P2 and O2 refer to \nthe second block of data.) The TCBC decryption process continues in this manner until \nthe last complete ciphertext block has been decrypted. Ciphertext representing a \npartial data block must be decrypted in a manner specified for the application.\n" }, { "page_number": 730, "page_indices": { "start_index": 1416373, "end_index": 1417015 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 730 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.1 DES/TDES cryptographic core", 726 ], [ 4, "DES and TDES Cipher block chaining (DES/TDES-CBC) mode", 729 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n730/1757\nRM0090 Rev 21\nFigure 220. DES/TDES-CBC mode encryption\n1.\nK: key; C: cipher text; I: input block; O: output block; Ps: plain text before swapping (when decoding) or \nafter swapping (when encoding); P: plain text; IV: initialization vectors.\nIN FIFO\nDEA, encrypt\nK1\nP, 64 bits\nDEA, decrypt\nK2\nDEA, encrypt\nK3\nOUT FIFO\nO, 64 bits\nplaintext P\nciphertext C\n64\n64\n64\nPs, 64 bits\nswapping\n+\nIV0(L/R)\n64\nI, 64 bits\n(before CRYP\nis enabled)\nO is written back\ninto IV at the\nsame time as it\nis pushed into\nthe OUT FIFO\nswapping\nC, 64 bits\nDATATYPE\nDATATYPE\nAHB2 data write\nai16070b\n" }, { "page_number": 731, "page_indices": { "start_index": 1417015, "end_index": 1418652 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 731 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.2 AES cryptographic core", 731 ] ], "page_content": "RM0090 Rev 21\n731/1757\nRM0090\nCryptographic processor (CRYP)\n769\nFigure 221. DES/TDES-CBC mode decryption\n1.\nK: key; C: cipher text; I: input block; O: output block; Ps: plain text before swapping (when decoding) or \nafter swapping (when encoding); P: plain text; IV: initialization vectors.\n23.3.2 \nAES cryptographic core\nThe AES cryptographic core consists of three components:\n•\nThe AES algorithm (AEA: advanced encryption algorithm)\n•\nMultiple keys\n•\nInitialization vector(s) or Nonce\nThe AES utilizes keys of 3 possible lengths: 128, 192 or 256 bits and, depending on the \noperation mode used, zero or one 128-bit initialization vector (IV).\nThe basic processing involved in the AES is as follows: an input block of 128 bits is read \nfrom the input FIFO and sent to the AEA to be encrypted using the key (K0...3). The key \nformat depends on the key size: \n•\nIf Key size = 128: Key = [K3 K2]\n•\nIf Key size = 192: Key = [K3 K2 K1]\n•\nIf Key size = 256: Key = [K3 K2 K1 K0]\nwhere Kx=[KxR KxL],R=right, L=left\nAccording to the mode implemented, the resultant output block is used to calculate the \nciphertext.\nFIPS PUB 197 (November 26, 2001) provides a thorough explanation of the processing \ninvolved in the four operation modes supplied by the AES core: AES-ECB encryption, AES-\nIN FIFO\nI, 64 bits\nOUT FIFO\nPs, 64 bits\nciphertext C\nplaintext P\nP, 64 bits\nswapping\nDEA, decrypt\nK3\nDEA, encrypt\nK2\nDEA, decrypt\nK1\n64\n64\n64\n+\nIV0(L/R)\n64\nAHB2 data write\n(before CRYP\nis enabled)\nO, 64 bits\nI is written back\ninto IV at the\nsame time as P\nis pushed into\n the OUT FIFO\nC, 64 bits\nswapping\nDATATYPE\nDATATYPE\nMS19022V1\n" }, { "page_number": 732, "page_indices": { "start_index": 1418652, "end_index": 1420652 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 732 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.2 AES cryptographic core", 731 ], [ 4, "AES Electronic codebook (AES-ECB) mode", 732 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n732/1757\nRM0090 Rev 21\nECB decryption, AES-CBC encryption and AES-CBC decryption.This reference manual \nonly gives a brief explanation of each mode.\nAES Electronic codebook (AES-ECB) mode\n•\nAES-ECB mode encryption\nFigure 222 illustrates the AES Electronic codebook (AES-ECB) mode encryption.\nIn AES-ECB encryption, a 128- bit plaintext data block (P) is used after bit/byte/half-\nword swapping (refer to Section 23.3.3: Data type on page 742) as the input block (I). \nThe input block is processed through the AEA in the encrypt state using the 128, 192 or \n256-bit key. The resultant 128-bit output block (O) is used after bit/byte/half-word \nswapping as ciphertext (C). It is then pushed into the OUT FIFO.\n•\nAES-ECB mode decryption\nFigure 223 illustrates the AES Electronic codebook (AES-ECB) mode encryption.\nTo perform an AES decryption in the ECB mode, the secret key has to be prepared (it is \nnecessary to execute the complete key schedule for encryption) by collecting the last \nround key, and using it as the first round key for the decryption of the ciphertext. This \npreparation function is computed by the AES core. Refer to Section 23.3.6: Procedure \nto perform an encryption or a decryption for more details on how to prepare the key.\nIn AES-ECB decryption, a 128-bit ciphertext block (C) is used after bit/byte/half-word \nswapping as the input block (I). The keying sequence is reversed compared to that of \nthe encryption process. The resultant 128-bit output block (O), after bit/byte or half-\nword swapping, produces the plaintext (P).\nFigure 222. AES-ECB mode encryption\n1.\nK: key; C: cipher text; I: input block; O: output block; P: plain text.\n2.\nIf Key size = 128: Key = [K3 K2]. \nIf Key size = 192: Key = [K3 K2 K1]\nIf Key size = 256: Key = [K3 K2 K1 K0].\nIN FIFO\nAEA, encrypt\nK0...3(1)\nP, 128 bits\nOUT FIFO\nplaintext P\nciphertext C\n128/192\nI, 128 bits\nswapping\nC, 128 bits\nswapping\nDATATYPE\nDATATYPE\nor 256\nai16071b\n" }, { "page_number": 733, "page_indices": { "start_index": 1420652, "end_index": 1423344 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 733 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.2 AES cryptographic core", 731 ], [ 4, "AES Cipher block chaining (AES-CBC) mode", 733 ] ], "page_content": "RM0090 Rev 21\n733/1757\nRM0090\nCryptographic processor (CRYP)\n769\nFigure 223. AES-ECB mode decryption\n1.\nK: key; C: cipher text; I: input block; O: output block; P: plain text.\n2.\nIf Key size = 128 => Key = [K3 K2]. \nIf Key size = 192 => Key = [K3 K2 K1]\nIf Key size = 256 => Key = [K3 K2 K1 K0].\nAES Cipher block chaining (AES-CBC) mode\n•\nAES-CBC mode encryption\nThe AES Cipher block chaining (AES-CBC) mode decryption is shown on Figure 224.\nIn AES-CBC encryption, the first input block (I1) obtained after bit/byte/half-word \nswapping (refer to Section 23.3.3: Data type on page 742) is formed by exclusive-\nORing the first plaintext data block (P1) with a 128-bit initialization vector IV (I1 = IV ⊕ \nP1). The input block is processed through the AEA in the encrypt state using the 128-, \n192- or 256-bit key (K0...K3). The resultant 128-bit output block (O1) is used directly as \nciphertext (C1), that is, C1 = O1. This first ciphertext block is then exclusive-ORed with \nthe second plaintext data block to produce the second input block, (I2) = (C1 ⊕ P2). \nNote that I2 and P2 now refer to the second block. The second input block is processed \nthrough the AEA to produce the second ciphertext block. This encryption process \ncontinues to “chain” successive cipher and plaintext blocks together until the last \nplaintext block in the message is encrypted. If the message does not consist of an \nintegral number of data blocks, then the final partial data block should be encrypted in a \nmanner specified for the application.\nIn the CBC mode, like in the ECB mode, the secret key must be prepared to perform an \nAES decryption. Refer to Section 23.3.6: Procedure to perform an encryption or a \ndecryption on page 747 for more details on how to prepare the key.\n•\nAES-CBC mode decryption\nIn AES-CBC decryption (see Figure 225), the first 128-bit ciphertext block (C1) is used \ndirectly as the input block (I1). The input block is processed through the AEA in the \ndecrypt state using the 128-, 192- or 256-bit key. The resulting output block is \nexclusive-ORed with the 128-bit initialization vector IV (which must be the same as that \nused during encryption) to produce the first plaintext block (P1 = O1 ⊕ IV). The second \nciphertext block is then used as the next input block and is processed through the AEA. \nThe resulting output block is exclusive-ORed with the first ciphertext block to produce \nthe second plaintext data block (P2 = O2 ⊕ C1). (Note that P2 and O2 refer to the second \nIN FIFO\nC, 128 bits\nOUT FIFO\nciphertext C\nplaintext P\nAEA, decrypt\nI, 128 bits\nswapping\nO, 128 bits\nDATATYPE\nDATATYPE\nP, 128 bits\nswapping\nK0...3(1)\n128/192\nor 256\nMS19023V1\n" }, { "page_number": 734, "page_indices": { "start_index": 1423344, "end_index": 1424374 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 734 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.2 AES cryptographic core", 731 ], [ 4, "AES Cipher block chaining (AES-CBC) mode", 733 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n734/1757\nRM0090 Rev 21\nblock of data.) The AES-CBC decryption process continues in this manner until the last \ncomplete ciphertext block has been decrypted. Ciphertext representing a partial data \nblock must be decrypted in a manner specified for the application.\nFigure 224. AES-CBC mode encryption\n1.\nK: key; C: cipher text; I: input block; O: output block; Ps: plain text before swapping (when decoding) or \nafter swapping (when encoding); P: plain text; IV: Initialization vectors.\n2.\nIVx=[IVxR IVxL], R=right, L=left.\n3.\nIf Key size = 128 => Key = [K3 K2]. \nIf Key size = 192 => Key = [K3 K2 K1]\nIf Key size = 256 => Key = [K3 K2 K1 K0].\nIN FIFO\nAEA, encrypt\nP, 128 bits\nOUT FIFO\nO, 128 bits\nplaintext P\nciphertext C\nswapping\n+\nIV=[IV1 IV0](2)\n128\nI, 128 bits\nAHB2 data write\n(before CRYP\nis enabled)\nO is written\nback into IV\nat the same time\nas it is pushed\ninto the OUT FIFO\nswapping\nC, 128 bits\nDATATYPE\nDATATYPE\nK0...3(3)\n128, 192\nor 256\nPs, 128 bits\nai16072b\n" }, { "page_number": 735, "page_indices": { "start_index": 1424374, "end_index": 1426296 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 735 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.2 AES cryptographic core", 731 ], [ 4, "AES counter mode (AES-CTR) mode", 735 ] ], "page_content": "RM0090 Rev 21\n735/1757\nRM0090\nCryptographic processor (CRYP)\n769\nFigure 225. AES-CBC mode decryption\n1.\nK: key; C: cipher text; I: input block; O: output block; Ps: plain text before swapping (when decoding) or \nafter swapping (when encoding); P: plain text; IV: Initialization vectors.\n2.\nIVx=[IVxR IVxL], R=right, L=left.\n3.\nIf Key size = 128 => Key = [K3 K2]. \nIf Key size = 192 => Key = [K3 K2 K1]\nIf Key size = 256 => Key = [K3 K2 K1 K0].\nAES counter mode (AES-CTR) mode\nThe AES counter mode uses the AES block as a key stream generator. The generated keys \nare then XORed with the plaintext to obtain the cipher. For this reason, it makes no sense to \nspeak of different CTR encryption/decryption, since the two operations are exactly the \nsame.\nIn fact, given:\n•\nPlaintext: P[0], P[1], ..., P[n] (128 bits each)\n•\nA key K to be used (the size does not matter)\n•\nAn initial counter block (call it ICB but it has the same functionality as the IV of CBC)\nThe cipher is computed as follows:\nC[i] = enck(iv[i]) xor P[i], where:\niv[0] = ICB and iv[i+1] = func(iv[i]), where func is an update function \napplied to the previous iv block; func is basically an increment of one of the fields \ncomposing the iv block.\nGiven that the ICB for decryption is the same as the one for encryption, the key stream \ngenerated during decryption is the same as the one generated during encryption. Then, the \nciphertext is XORed with the key stream in order to retrieve the original plaintext. The \ndecryption operation therefore acts exactly in the same way as the encryption operation.\nIN FIFO\nI, 128 bits\nOUT FIFO\nciphertext C\nplaintext P\nP, 128 bits\nswapping\nAEA, decrypt\nK0...3(3)\n128, 192\n+\n128\nAHB2 data write\n(before CRYP\nis enabled)\nO, 128 bits\nI is written\nback into IV\nat the same time\nas P is pushed\ninto the OUT FIFO\nC, 128 bits\nswapping\nDATATYPE\nDATATYPE\nor 256\nPs, 128 bits\nMS19024V1\nIV=[IV1 IV0](2)\n" }, { "page_number": 736, "page_indices": { "start_index": 1426296, "end_index": 1427101 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 736 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.2 AES cryptographic core", 731 ], [ 4, "AES counter mode (AES-CTR) mode", 735 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n736/1757\nRM0090 Rev 21\nFigure 226 and Figure 227 illustrate AES-CTR encryption and decryption, respectively. \nFigure 226. AES-CTR mode encryption\n1.\nK: key; C: cipher text; I: input Block; o: output block; Ps: plain text before swapping (when decoding) or \nafter swapping (when encoding); Cs: cipher text after swapping (when decoding) or before swapping (when \nencoding); P: plain text; IV: Initialization vectors.\nIN FIFO\nAEA, encrypt\nP, 128 bits\nOUT FIFO\nCs, 128 bit\nplaintext P\nciphertext C\nswapping\n+\nIV0...1(L/R)\nO, 128 bits\nI, 128 bits\nAHB2 data write\n(before CRYP\nis enabled)\n(I + 1) is written\nback into IV\nat same time\nthan C is pushed\nin OUT FIFO\nswapping\nC, 128 bits\nDATATYPE\nDATATYPE\nK0...3\n128, 192\nor 256\nPs, 128 bits\n+1\nai16073b\n" }, { "page_number": 737, "page_indices": { "start_index": 1427101, "end_index": 1428647 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 737 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.2 AES cryptographic core", 731 ], [ 4, "AES counter mode (AES-CTR) mode", 735 ] ], "page_content": "RM0090 Rev 21\n737/1757\nRM0090\nCryptographic processor (CRYP)\n769\nFigure 227. AES-CTR mode decryption\n1.\nK: key; C: cipher text; I: input Block; o: output block; Ps: plain text before swapping (when decoding) or \nafter swapping (when encoding); Cs: cipher text after swapping (when decoding) or before swapping (when \nencoding); P: plain text; IV: Initialization vectors.\nFigure 228 shows the structure of the IV block as defined by the standard [2]. It is composed \nof three distinct fields.\nFigure 228. Initial counter block structure for the Counter mode\n•\nNonce is a 32-bit, single-use value. A new nonce should be assigned to each different \ncommunication.\n•\nThe initialization vector (IV) is a 64-bit value and the standard specifies that the \nencryptor must choose IV so as to ensure that a given value is used only once for a \ngiven key\n•\nThe counter is a 32-bit big-endian integer that is incremented each time a block has \nbeen encrypted. The initial value of the counter should be set to ‘1’.\nThe block increments the least significant 32 bits, while it leaves the other (most significant) \n96 bits unchanged.\nIN FIFO\nAEA, encrypt\nC, 128 bits\nOUT FIFO\nPs, 128 bits\nciphertext P\nplaintext C\nswapping\n+\nIV0...1(L/R)\nI, 128 bits\nAHB2 data write\n(before CRYP\nis enabled)\n(I + 1) is written\nback into IV\nat same time\nthan P is pushed\nin OUT FIFO\nswapping\nP, 128 bits\nDATATYPE\nDATATYPE\nK0...3\n128, 192\nor 256\nCs, 128 bits\n+1\nO, 128 bits\nMS19025V1\nNonce\n32 bits\nInitialization vector (IV)\n64 bits\nCounter\n32 bits\nai16074\n" }, { "page_number": 738, "page_indices": { "start_index": 1428647, "end_index": 1429926 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 738 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.2 AES cryptographic core", 731 ], [ 4, "AES Galois/counter mode (GCM)", 738 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n738/1757\nRM0090 Rev 21\nAES Galois/counter mode (GCM)\nThe AES Galois/counter mode (GCM) allows encrypting and authenticating the plaintext, \nand generating the correspondent ciphertext and tag (also known as message \nauthentication code or message integrity check). This algorithm is based on AES counter \nmode to ensure confidentiality. It uses a multiplier over a fixed finite field to generate the tag. \nAn initialization vector is required at the beginning of the algorithm.\nThe message to be processed is split into 2 parts: \n•\nThe header (also knows as additional authentication data): data which is authenticated \nbut no protected (such as information for routing the packet)\n•\nThe payload (also knows as plaintext or ciphertext): the message itself which is \nauthenticated and encrypted.\nNote:\nThe header must precede the payload and the two parts cannot be mixed together.\nThe GCM standard requires to pass, at the end of the message, a specific 128-bit block \ncomposed of the size of the header (64 bits) and the size of the payload (64 bits). During the \ncomputation, the header blocks must be distinguished from the payload blocks. \nIn GCM mode, four steps are required to perform an encryption/decryption: \n" }, { "page_number": 739, "page_indices": { "start_index": 1429926, "end_index": 1432122 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 739 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.2 AES cryptographic core", 731 ], [ 4, "AES Galois/counter mode (GCM)", 738 ] ], "page_content": "RM0090 Rev 21\n739/1757\nRM0090\nCryptographic processor (CRYP)\n769\n1.\nGCM init phase\nDuring this first step, the HASH key is calculated and saved internally to be used for \nprocessing all the blocks. It is recommended to follow the sequence below:\na) \nMake sure that the cryptographic processor is disabled by clearing the CRYPEN \nbit in the CRYP_CR register.\nb) \nSelect the GCM chaining mode by programming ALGOMODE bits to ‘01000’ in \nCRYP_CR.\nc) \nConfigure GCM_CCMPH bits to ‘00’ in CRYP_CR to start the GCM Init phase.\nd) \nInitialize the key registers (128,192 and 256 bits) in CRYP_KEYRx as well as the \ninitialization vector (IV).\ne) \nSet CRYPEN bit to ‘1’ to start the calculation of the HASH key.\nf) \nWait for the CRYPEN bit to be cleared to ‘0’ before moving on to the next phase.\ng) \nSet the CRYPEN bit to ‘1’.\n2. \nGCM header phase\nThis step must be performed after the GCM Init phase:\nh) \nSet the GCM_CCMPH bits to ‘01’ in CRYP_CR to indicate that the header phase \nhas started.\ni) \nWrite the header data. Three methods can be used:\n–\nProgram the data by blocks of 32 bits into the CRYP_DIN register, and use the \nIFNF flag to determine if the input FIFO can receive data. The size of the header \nmust be a multiple of 128 bits (4 words). \n–\nProgram the data into the CRYP_DIN register by blocks of 8 words, and use the \nIFEM flag to determine if the input FIFO can receive data (IFEM=’1’). The size of \nthe header must be a multiple of 128 bits (4 words). \n–\nUse the DMA.\nj) \nOnce all header data have been supplied, wait until the BUSY bit is cleared in the \nCRYP_SR register. \n3. \nGCM payload phase (encryption/decryption)\nThis step must be performed after the GCM header phase:\nk) \nConfigure GCM_CCMPH to ‘10’ in the CRYP_CR register.\nl) \nSelect the algorithm direction (encryption or decryption) by using the ALGODIR bit \nin CRYP_CR.\nm) Program the payload message into the CRYP_DIN register, and use the IFNF flag \nto determine if the input FIFO can receive data. Alternatively, the data could be \nprogrammed into the CRYP_DIN register by blocks of 8 words and the IFEM flag \nused to determine if the input FIFO can receive data (IFEM=’1’). In parallel, the \n" }, { "page_number": 740, "page_indices": { "start_index": 1432122, "end_index": 1435170 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 740 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.2 AES cryptographic core", 731 ], [ 4, "AES Galois message authentication code (GMAC)", 740 ], [ 4, "AES combined cipher machine (CCM)", 740 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n740/1757\nRM0090 Rev 21\nOFNE/OFFU flag of the CRYP_DOUT register can be monitored to check if the \noutput FIFO is not empty.\nn) \nRepeat the previous step until all payload blocks have been encrypted or \ndecrypted. Alternatively, DMA could be used.\n4. \nGCM final phase\nThis step generates the authentication tag:\no) \nConfigure GCM_CCMPH[1:0] to ‘11’ in CRYP_CR.\np) \nWrite the input into the CRYP_DIN register 4 times. The input must contain the \nnumber of bits in the header (64 bits) concatenated with the number of bits in the \npayload (64 bits).\nq) \nWait till the OFNE flag (FIFO output not empty) is set to ‘1’ in the CRYP_SR \nregister.\nr) \nRead the CRYP_DOUT register 4 times: the output corresponds to the \nauthentication tag. \ns) \nDisable the cryptographic processor (CRYPEN bit in CRYP_CR = ‘0’)\nNote:\nWhen a decryption is performed, it is not required to compute the key at the beginning. At \nthe end of the decryption, the generated tag should be compared with the expected tag \npassed with the message. In addition, the ALGODIR bit (algorithm direction) must be set to ‘1’.\nNo need to disable/enable CRYP processor when moving from header phase to tag phase. \nAES Galois message authentication code (GMAC)\nThe cryptographic processor also supports GMAC to authenticate the plaintext. It uses the \nGCM algorithm and a multiplier over a fixed finite field to generate the corresponding tag.\nAn initialization vector is required at the beginning of the algorithm.\nActually, the GMAC algorithm corresponds to the GCM algorithm applied on a message \ncomposed of the header only. As a consequence, the payload phase is not required.\nAES combined cipher machine (CCM)\nThe CCM algorithm allows encrypting and authenticating the plaintext, as well as generating \nthe corresponding ciphertext and tag (also known as message authentication code or \nmessage integrity check). This algorithm is based on AES counter mode to ensure \nconfidentiality. It uses the AES CBC mode to generate a 128-bit tag.\nThe CCM standard (RFC 3610 Counter with CBC-MAC (CCM) dated September 2003) \ndefines particular encoding rules for the first authentication block (called B0 in the standard). \nIn particular, the first block includes flags, a nonce and the payload length expressed in \nbytes. The CCM standard specifies another format, called A or counter, for \nencryption/decryption. The counter is incremented during the payload phase and its 32 LSB \nbits are initialized to ‘1’ during the tag generation (called A0 packet in the CCM standard).\nNote:\nThe hardware does not perform the formatting operation of the B0 packet. It should be \nhandled by the software.\nAs for the GCM algorithm, the message to be processed is split into 2 parts: \n•\nThe header (also knows as additional authentication data): data which is authenticated \nbut no protected (such as information for routing the packet)\n•\nThe payload (also knows as plaintext or ciphertext): the message itself which is \nauthenticated and encrypted. \n" }, { "page_number": 741, "page_indices": { "start_index": 1435170, "end_index": 1437183 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 741 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.2 AES cryptographic core", 731 ], [ 4, "AES combined cipher machine (CCM)", 740 ] ], "page_content": "RM0090 Rev 21\n741/1757\nRM0090\nCryptographic processor (CRYP)\n769\nNote:\nThe header part must precede the payload and the two parts cannot be mixed together.\nIn CCM mode, 4 steps are required to perform and encryption or decryption: \n1.\nCCM init phase\nIn this first step, the B0 packet of the CCM message (1st packet) is programmed into \nthe CRYP_DIN register. During this phase, the CRYP_DOUT register does not contain \nany output data.\nThe following sequence must be followed: \na) \nMake sure that the cryptographic processor is disabled by clearing the CRYPEN \nbit in the CRYP_CR register.\nb) \nSelect the CCM chaining mode by programming the ALGOMODE bits to ‘01001’ \nin the CRYP_CR register.\nc) \nConfigure the GCM_CCMPH bits to ‘00’ in CRYP_CR to start the CCM Init phase.\nd) \nInitialize the key registers (128,192 and 256 bits) in CRYP_KEYRx as well as the \ninitialization vector (IV).\ne) \nSet the CRYPEN bit to ‘1’ in CRYP_CR. \nf) \nProgram the B0 packet into the input data register.\ng) \nWait for the CRYPEN bit to be cleared before moving on to the next phase.\nh) \nSet CRYPEN to ‘1’.\n2. \nCCM header phase\nThis step must be performed after the CCM Init phase. The sequence is identical for \nencryption and decryption. \nDuring this phase, the CRYP_DOUT register does not contain any output data. \nThis phase can be skipped if there is no additional authenticated data.\nThe following sequence must be followed: \ni) \nSet the GCM_CCMPH bit to ’01’ in CRYP_CR to indicate that the header phase \nhas started.\nj) \nThree methods can be used:\n–\nProgram the header data by blocks of 32 bits into the CRYP_DIN register, and use \nthe IFNF flag to determine if the input FIFO can receive data. The size of the \nheader must be a multiple of 128 bits (4 words). \n–\nProgram the header data into the CRYP_DIN register by blocks of 8 words, and \nuse the IFEM flag to determine if the input FIFO can receive data (IFEM=’1’). The \nsize of the header must be a multiple of 128 bits (4 words). \n–\nUse the DMA.\n" }, { "page_number": 742, "page_indices": { "start_index": 1437183, "end_index": 1439949 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 742 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.3 Data type", 742 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n742/1757\nRM0090 Rev 21\nNote:\nThe first block B1 must be formatted with the header length. This task should be handled by \nsoftware.\nk) \nOnce all header data have been supplied, wait until the BUSY flag is cleared.\n3. \nCCM payload phase (encryption/decryption)\nThis step must be performed after the CCM header phase. During this phase, the \nencrypted/decrypted payload is stored in the CRYP_DOUT register.\nThe following sequence must be followed: \nl) \nConfigure GCM_CCMPH bits to ‘10’ in CRYP_CR.\nm) Select the algorithm direction (encryption or decryption) by using the ALGODIR bit \nin CRYP_CR.\nn) \nProgram the payload message into the CRYP_DIN register, and use the IFNF flag \nto determine if the input FIFO can receive data. Alternatively, the data could be \nprogrammed into the CRYP_DIN register by blocks of 8 words and the IFEM flag \nused to determine if the input FIFO can receive data (IFEM=’1’). In parallel, the \nOFNE/OFFU flag of the CRYP_DOUT register can be monitored to check if the \noutput FIFO is not empty.\no) \nRepeat the previous step until all payload blocks have been encrypted or \ndecrypted. Alternatively, DMA could be used.\n4. \nCCM final phase\nThis step generates the authentication tag. During this phase, the authentication tag of \nthe message is generated and stored in the CRYP_DOUT register.\np) \nConfigure GCM_CCMPH[1:0] bits to ‘11’ in CRYP_CR.\nq) \nLoad the A0 initialized counter, and program the 128-bit A0 value by writing 4 \ntimes 32 bits into the CRYP_DIN register.\nr) \nWait till the OFNE flag (FIFO output not empty) is set to ‘1’ in the CRYP_SR \nregister.\ns) \nRead the CRYP_DOUT register 4 times: the output corresponds to the encrypted \nauthentication tag. \nt) \nDisable the cryptographic processor (CRYPEN bit in CRYP_CR = ‘0’)\nNote:\nThe hardware does not perform the formatting of the original B0 and B1 packets and the tag \ncomparison between encryption and decryption. They have to be handled by software.\nThe cryptographic processor does not need to be disabled/enabled when moving from the \nheader phase to the tag phase.\nAES cipher message authentication code (CMAC)\nThe CMAC algorithm allows authenticating the plaintext, and generating the corresponding \ntag. The CMAC sequence is identical to the CCM one, except that the payload phase is \nskipped. \n23.3.3 \nData type\nData enter the CRYP processor 32 bits (word) at a time as they are written into the \nCRYP_DIN register. The principle of the DES is that streams of data are processed 64 bits \nby 64 bits and, for each 64-bit block, the bits are numbered from M1 to M64, with M1 the left-\nmost bit and M64 the right-most bit of the block. The same principle is used for the AES, but \nwith a 128-bit block size.\n" }, { "page_number": 743, "page_indices": { "start_index": 1439949, "end_index": 1442142 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 743 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.3 Data type", 742 ] ], "page_content": "RM0090 Rev 21\n743/1757\nRM0090\nCryptographic processor (CRYP)\n769\nThe system memory organization is little-endian: whatever the data type (bit, byte, 16-bit \nhalf-word, 32-bit word) used, the least-significant data occupy the lowest address locations. \nA bit, byte, or half-word swapping operation (depending on the kind of data to be encrypted) \ntherefore has to be performed on the data read from the IN FIFO before they enter the \nCRYP processor. The same swapping operation should be performed on the CRYP data \nbefore they are written into the OUT FIFO. For example, the operation would be byte \nswapping for an ASCII text stream.\nThe kind of data to be processed is configured with the DATATYPE bitfield in the CRYP \ncontrol register (CRYP_CR).\n \nFigure 229 shows how the 64-bit data block M1...64 is constructed from two consecutive 32-\nbit words popped off the IN FIFO by the CRYP processor, according to the DATATYPE \nvalue. The same schematic can easily be extended to form the 128-bit block for the AES \nTable 114. Data types\nDATATYPE in \nCRYP_CR\nSwapping performed\nSystem memory data\n(plaintext or cypher)\n00b\nNo swapping\nExample: TDES block value 0xABCD77206973FE01 is \nrepresented in system memory as:\n01b\nHalf-word (16-bit) \nswapping\nExample: TDES block value 0xABCD77206973FE01 is \nrepresented in system memory as:\n10b\nByte (8-bit) swapping\nExample: TDES block value 0xABCD77206973FE01 is \nrepresented in system memory as:\n11b\nBit swapping\nTDES block value 0x4E6F772069732074 is represented in system \nmemory as:\n \n0xABCD7720 6973FE01 \nTDES block size = 64bit = 2x 32 bit \n0xABCD7720 \n0x6973FE01 \n@ \n@+4 \nsystem memory \n0xABCD 7720 6973 FE01 \nTDES block size = 64bit = 2x 32 bit \n0x7720 ABCD \n0xFE01 6973 \n@ \n@+4 \nsystem memory \n \n0xAB CD 77 20 69 73 FE 01 \nTDES block size = 64bit = 2x 32 bit \n0x 20 77 CD AB \n0x 01 FE 73 69 \n@ \n@+4 \nsystem memory \n \n0x4E 6F 77 20 69 73 20 74 \n0x04 EE F6 72 \n0x2E 04 CE 96 \n@ \n@+4 \n0000 0100 1110 1110 1111 0110 0111 0010 \n0100 1110 0110 1111 \n0111 0111 0010 0000 \n0110 1001 0111 0011 \n0010 0000 0111 0100 \n0010 1110 0000 0100 1100 1110 1001 0110 \n@ \n@+4 \nsystem memory\n \nTDES Bloc size = 64bit = 2x 32 bit \n" }, { "page_number": 744, "page_indices": { "start_index": 1442142, "end_index": 1443943 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 744 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.3 Data type", 742 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n744/1757\nRM0090 Rev 21\ncryptographic algorithm (for the AES, the block length is four 32-bit words, but swapping \nonly takes place at word level, so it is identical to the one described here for the TDES).\nNote:\nThe same swapping is performed between the IN FIFO and the CRYP data block, and \nbetween the CRYP data block and the OUT FIFO.\nFigure 229. 64-bit block construction according to DATATYPE\nByte 0,3\nByte 0,2\nByte 0,1\nByte 0,0\nM25...32\nM17...24\nM9...16\nM1...8\nIN FIFO\nbit string\nM1\nM2\nM30\nM31 M32\nbit swapping operation\nIN FIFO\nbit string\nbyte swapping operation\nByte 0,0\nByte 0,1\nByte 0,2\nByte 0,3\nbits 7...0\nbits 7...0\nbits 7...0\nbits 7...0\nIN FIFO\nbit string\nhald-word swapping operation\nHalf-word 0,0\nbits 15...0\nDATATYPE = 11b\nDATATYPE = 10b\nDATATYPE = 01b\nHalf-word 0,1\nbits 15...0\nHalf-word 0,0\nM1...16\nHalf-word 0,1\nM17...32\nM33\nM34 M62\nM63\nM64\nbit 0\nbit 1\nbit 2\nbit 30\nbit 31\nbit 0\nbit 1\nbit 2\nbit 30\nbit 31\nfirst word written into the CRYP_DIN register\nsecond word written into the CRYP_DIN register\nByte 1,0\nByte 1,1\nByte 1,2\nByte 1,3\nbits 7...0\nbits 7...0\nbits 7...0\nbits 7...0\nfirst word written into the CRYP_DIN register\nsecond word written into the CRYP_DIN register\nByte 1,3\nByte 1,2\nByte 1,1\nByte 1,0\nM57...64\nM49...56\nM41...48\nM33...40\n(bit ordering within byte is unchanged)\nHalf-word 1,0\nbits 15...0\nHalf-word 1,1\nbits 15...0\nfirst word written into the CRYP_DIN register\nsecond word written into the CRYP_DIN register\nHalf-word 1,0\nM33...48\nHalf-word 1,1\nM49...64\nIN FIFO\nbit string\nNo swapping operation\nDATATYPE = 00b\nWord 0\nbits 31...0\nWord 0\nM1...32\nWord 1\nbits 31...0\nfirst word written into the CRYP_DIN register\nsecond word written into the CRYP_DIN register\nWord 1\nM33...64\nai16075\n" }, { "page_number": 745, "page_indices": { "start_index": 1443943, "end_index": 1446764 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 745 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.4 Initialization vectors - CRYP_IV0...1(L/R)", 745 ] ], "page_content": "RM0090 Rev 21\n745/1757\nRM0090\nCryptographic processor (CRYP)\n769\n23.3.4 \nInitialization vectors - CRYP_IV0...1(L/R)\nInitialization vectors are considered as two 64-bit data items. They therefore do not have the \nsame data format and representation in system memory as plaintext or cypher data, and \nthey are not affected by the DATATYPE value.\nInitialization vectors are defined by two consecutive 32-bit words, CRYP_IVL (left part, \nnoted as bits IV1...32) and CRYP_IVR (right part, noted as bits IV33...64). \nDuring the DES or TDES CBC encryption, the CRYP_IV0(L/R) bits are XORed with the 64-\nbit data block popped off the IN FIFO after swapping (according to the DATATYPE value), \nthat is, with the M1...64 bits of the data block. When the output of the DEA3 block is \navailable, it is copied back into the CRYP_IV0(L/R) vector, and this new content is XORed \nwith the next 64-bit data block popped off the IN FIFO, and so on.\nDuring the DES or TDES CBC decryption, the CRYP_IV0(L/R) bits are XORed with the 64-\nbit data block (that is, with the M1...64 bits) delivered by the TDEA1 block before swapping \n(according to the DATATYPE value), and pushed into the OUT FIFO. When the XORed \nresult is swapped and pushed into the OUT FIFO, the CRYP_IV0(L/R) value is replaced by \nthe output of the IN FIFO, then the IN FIFO is popped, and a new 64-bit data block can be \nprocessed.\nDuring the AES CBC encryption, the CRYP_IV0...1(L/R) bits are XORed with the 128-bit \ndata block popped off the IN FIFO after swapping (according to the DATATYPE value). \nWhen the output of the AES core is available, it is copied back into the CRYP_IV0...1(L/R) \nvector, and this new content is XORed with the next 128-bit data block popped off the IN \nFIFO, and so on.\nDuring the AES CBC decryption, the CRYP_IV0...1(L/R) bits are XORed with the 128-bit \ndata block delivered by the AES core before swapping (according to the DATATYPE value) \nand pushed into the OUT FIFO. When the XORed result is swapped and pushed into the \nOUT FIFO, the CRYP_IV0...1(L/R) value is replaced by the output of the IN FIFO, then the \nIN FIFO is popped, and a new 128-bit data block can be processed.\nDuring the AES CTR encryption or decryption, the CRYP_IV0...1(L/R) bits are encrypted by \nthe AES core. Then the result of the encryption is XORed with the 128-bit data block popped \noff the IN FIFO after swapping (according to the DATATYPE value). When the XORed result \nis swapped and pushed into the OUT FIFO, the counter part of the CRYP_IV0...1(L/R) value \n(32 LSB) is incremented.\nAny write operation to the CRYP_IV0...1(L/R) registers when bit BUSY = 1b in the \nCRYP_SR register is disregarded (CRYP_IV0...1(L/R) register content not modified). Thus, \nyou must check that bit BUSY = 0b before modifying initialization vectors.\n" }, { "page_number": 746, "page_indices": { "start_index": 1446764, "end_index": 1448634 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 746 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.5 CRYP busy state", 746 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n746/1757\nRM0090 Rev 21\nFigure 230. Initialization vectors use in the TDES-CBC encryption\n23.3.5 \nCRYP busy state\nWhen there is enough data in the input FIFO (at least 2 words for the DES or TDES \nalgorithm mode, 4 words for the AES algorithm mode) and enough free-space in the output \nFIFO (at least 2 (DES/TDES) or 4 (AES) word locations), and when the bit CRYPEN = 1 in \nthe CRYP_CR register, then the cryptographic processor automatically starts an encryption \nor decryption process (according to the value of the ALGODIR bit in the CRYP_CR \nregister).\nThis process takes 48 AHB2 clock cycles for the Triple-DES algorithm, 16 AHB2 clock \ncycles for the simple DES algorithm, and 14, 16 or 18 AHB2 clock cycles for the AES with \nkey lengths of 128, 192 or 256 bits, respectively. During the whole process, the BUSY bit in \nthe CRYP_SR register is set to ‘1’. At the end of the process, two (DES/TDES) or four (AES) \nwords are written by the CRYP Core into the output FIFO, and the BUSY bit is cleared. In \nCRYP_IVL\nbit string\nM1 M2 M30 M31 M32\nTDES-CBC encryption example, DATATYPE = 11b\nM33 M34 M62 M63 M64\nbit 0\nbit 1\nbit 2\nbit 30\nbit 31\nbit 0\nbit 1\nbit 2\nbit 30\nbit 31\nfirst word written into the CRYP_DIN register\nsecond word written into the CRYP_DIN register\nIV1\nCRYP_IVR\n0\n1\n2\n30\n31\n0\n1\n2\n30\n31\nDEA Encrypt, \nK1\nDEA Decrypt, \nK2\nDEA Encrypt, \nK3\nCRYP_IVL\nCRYP_IVR\n0\n1\n2\n30\n31\n0\n1\n2\n30\n31\nCRYP result is copied\nback to the CRYP_IVL/R\nregisters after cyphering\nOUT FIFO\nFirst word from the OUT FIFO contains the left part of the cyphertext block (O1...32)\nSecond word from OUT FIFO contains the right part of cyphertext block (O33...64)\nIV2\nIV30 IV31 IV32 IV33 IV34\nIV62 IV63 IV64\nI1\nI2\nI30\nI33\nI34\nI62\nI63\nI64\nI31\nI32\nIV1\nIV2\nIV30 IV31 IV32 IV33 IV34\nIV62 IV63 IV64\nai16076\n" }, { "page_number": 747, "page_indices": { "start_index": 1448634, "end_index": 1451650 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 747 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.6 Procedure to perform an encryption or a decryption", 747 ], [ 4, "Initialization", 747 ], [ 4, "Processing when the DMA is used to transfer the data from/to the memory", 747 ] ], "page_content": "RM0090 Rev 21\n747/1757\nRM0090\nCryptographic processor (CRYP)\n769\nthe CBC, CTR mode, the initialization vectors CRYP_IVx(L/R)R (x = 0..3) are updated as \nwell.\nA write operation to the key registers (CRYP_Kx(L/R)R, x = 0..3), the initialization registers \n(CRYP_IVx(L/R)R, x = 0..3), or to bits [9:2] in the CRYP_CR register are ignored when the \ncryptographic processor is busy (bit BUSY = 1b in the CRYP_SR register), and the registers \nare not modified. It is thus not possible to modify the configuration of the cryptographic \nprocessor while it is processing a block of data. It is however possible to clear the CRYPEN \nbit while BUSY = 1, in which case the ongoing DES, TDES or AES processing is completed \nand the two/four word results are written into the output FIFO, and then, only then, the \nBUSY bit is cleared.\nNote:\nWhen a block is being processed in the DES or TDES mode, if the output FIFO becomes full \nand if the input FIFO contains at least one new block, then the new block is popped off the \ninput FIFO and the BUSY bit remains high until there is enough space to store this new \nblock into the output FIFO.\n23.3.6 \nProcedure to perform an encryption or a decryption\nInitialization\n1.\nInitialize the peripheral (the order of operations is not important except for the key \npreparation for AES-ECB or AES-CBC decryption. The key size and the key value \nmust be entered before preparing the key and the algorithm must be configured once \nthe key has been prepared):\na) \nConfigure the key size (128-, 192- or 256-bit, in the AES only) with the KEYSIZE \nbits in the CRYP_CR register\nb) \nWrite the symmetric key into the CRYP_KxL/R registers (2 to 8 registers to be \nwritten depending on the algorithm)\nc) \nConfigure the data type (1-, 8-, 16- or 32-bit), with the DATATYPE bits in the \nCRYP_CR register\nd) \nIn case of decryption in AES-ECB or AES-CBC, you must prepare the key: \nconfigure the key preparation mode by setting the ALGOMODE bits to ‘111’ in the \nCRYP_CR register. Then write the CRYPEN bit to ‘1’: the BUSY bit is set. Wait \nuntil BUSY returns to 0 (CRYPEN is automatically cleared as well): the key is \nprepared for decryption\ne) \nConfigure the algorithm and chaining (the DES/TDES in ECB/CBC, the AES in \nECB/CBC/CTR/GCM/CCM) with the ALGOMODE bits in the CRYP_CR register\nf) \nConfigure the direction (encryption/decryption), with the ALGODIR bit in the \nCRYP_CR register\ng) \nWrite the initialization vectors into the CRYP_IVxL/R register (in CBC or CTR \nmodes only)\n2. \nFlush the IN and OUT FIFOs by writing the FFLUSH bit to 1 in the CRYP_CR register\nProcessing when the DMA is used to transfer the data from/to the memory\n1.\nConfigure the DMA controller to transfer the input data from the memory. The transfer \nlength is the length of the message. As message padding is not managed by the \nperipheral, the message length must be an entire number of blocks. The data are \ntransferred in burst mode. The burst length is 4 words in the AES and 2 or 4 words in \n" }, { "page_number": 748, "page_indices": { "start_index": 1451650, "end_index": 1453958 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 748 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.6 Procedure to perform an encryption or a decryption", 747 ], [ 4, "Processing when the data are transferred by the CPU during interrupts", 748 ], [ 4, "Processing without using the DMA nor interrupts", 748 ], [ 3, "23.3.7 Context swapping", 748 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n748/1757\nRM0090 Rev 21\nthe DES/TDES. The DMA should be configured to set an interrupt on transfer \ncompletion of the output data to indicate that the processing is finished.\n2. \nEnable the cryptographic processor by writing the CRYPEN bit to 1. Enable the DMA \nrequests by setting the DIEN and DOEN bits in the CRYP_DMACR register.\n3. \nAll the transfers and processing are managed by the DMA and the cryptographic \nprocessor. The DMA interrupt indicates that the processing is complete. Both FIFOs \nare normally empty and BUSY = 0.\nProcessing when the data are transferred by the CPU during interrupts\n1.\nEnable the interrupts by setting the INIM and OUTIM bits in the CRYP_IMSCR register.\n2. \nEnable the cryptographic processor by setting the CRYPEN bit in the CRYP_CR \nregister.\n3. \nIn the interrupt managing the input data: load the input message into the IN FIFO. You \ncan load 2 or 4 words at a time, or load data until the FIFO is full. When the last word of \nthe message has been entered into the FIFO, disable the interrupt by clearing the INIM \nbit.\n4. \nIn the interrupt managing the output data: read the output message from the OUT \nFIFO. You can read 1 block (2 or 4 words) at a time or read data until the FIFO is \nempty. When the last word has been read, INIM=0, BUSY=0 and both FIFOs are empty \n(IFEM=1 and OFNE=0). You can disable the interrupt by clearing the OUTIM bit and, \nthe peripheral by clearing the CRYPEN bit.\nProcessing without using the DMA nor interrupts\n1.\nEnable the cryptographic processor by setting the CRYPEN bit in the CRYP_CR \nregister.\n2. \nWrite the first blocks in the input FIFO (2 to 8 words).\n3. \nRepeat the following sequence until the complete message has been processed:\na) \nWait for OFNE=1, then read the OUT-FIFO (1 block or until the FIFO is empty)\nb) \nWait for IFNF=1, then write the IN FIFO (1 block or until the FIFO is full)\n4. \nAt the end of the processing, BUSY=0 and both FIFOs are empty (IFEM=1 and \nOFNE=0). You can disable the peripheral by clearing the CRYPEN bit.\n23.3.7 \nContext swapping\nIf a context switching is needed because a new task launched by the OS requires this \nresource, the following tasks have to be performed for full context restoration (example \nwhen the DMA is used):\n" }, { "page_number": 749, "page_indices": { "start_index": 1453958, "end_index": 1456513 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 749 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.3 CRYP functional description", 725 ], [ 3, "23.3.7 Context swapping", 748 ], [ 4, "Case of the AES and DES", 749 ], [ 4, "Case of the TDES", 749 ] ], "page_content": "RM0090 Rev 21\n749/1757\nRM0090\nCryptographic processor (CRYP)\n769\nCase of the AES and DES\n1.\nContext saving\na) \nStop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR \nregister.\nb) \nWait until both the IN and OUT FIFOs are empty (IFEM=1 and OFNE=0 in the \nCRYP_SR register) and the BUSY bit is cleared.\nc) \nStop DMA transfers on the OUT FIFO by writing the DOEN bit to 0 in the \nCRYP_DMACR register and clear the CRYPEN bit.\nd) \nSave the current configuration (bits [9:2] and bits 19 in the CRYP_CR register) \nand, if not in ECB mode, the initialization vectors. The key value must already be \navailable in the memory. When needed, save the DMA status (pointers for IN and \nOUT messages, number of remaining bytes, etc.). \nAdditional bits should be saved when GCM/GMAC or CCM/CMAC algorithms are \nused:\n–\nbits [17:16] in the CRYP_CR register\n–\ncontext swap registers:\nCRYP_CSGCMCCM0..7 for GCM/GMAC or CCM/CMAC algorithm\nCRYP_CSGCM0..7 for GCM/GMAC algorithm.\n2. \nConfigure and execute the other processing.\n3. \nContext restoration\na) \nConfigure the processor as in Section 23.3.6: Procedure to perform an encryption \nor a decryption on page 747, Initialization with the saved configuration. For the \nAES-ECB or AES-CBC decryption, the key must be prepared again.\nb) \nIf needed, reconfigure the DMA controller to transfer the rest of the message.\nc) \nEnable the processor by setting the CRYPEN bit and, the DMA requests by setting \nthe DIEN and DOEN bits.\nCase of the TDES\nContext swapping can be done in the TDES in the same way as in the AES. But as the input \nFIFO can contain up to 4 unprocessed blocks and as the processing duration per block is \nhigher, it can be faster in certain cases to interrupt the processing without waiting for the IN \nFIFO to be empty.\n1.\nContext saving\na) \nStop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR \nregister.\nb) \nDisable the processor by clearing the CRYPEN bit (the processing stops at the \nend of the current block).\nc) \nWait until the OUT FIFO is empty (OFNE=0 in the CRYP_SR register) and the \nBUSY bit is cleared.\nd) \nStop DMA transfers on the OUT FIFO by writing the DOEN bit to 0 in the \nCRYP_DMACR register.\ne) \nSave the current configuration (bits [9:2] and bits 19 in the CRYP_CR register) \nand, if not in ECB mode, the initialization vectors. The key value must already be \navailable in the memory. When needed, save the DMA status (pointers for IN and \nOUT messages, number of remaining bytes, etc.). Read back the data loaded in \n" }, { "page_number": 750, "page_indices": { "start_index": 1456513, "end_index": 1459113 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 750 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.4 CRYP interrupts", 750 ], [ 3, "Output FIFO service interrupt - OUTMIS", 750 ], [ 3, "Input FIFO service interrupt - INMIS", 750 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n750/1757\nRM0090 Rev 21\nthe IN FIFO that have not been processed and save them in the memory until the \nFIFO is empty.\nNote:\nIn GCM/GMAC or CCM/CMAC mode, bits [17:16] of the CRYP_CR register should also be \nsaved.\n2. \nConfigure and execute the other processing.\n3. \nContext restoration\na) \nConfigure the processor as in Section 23.3.6: Procedure to perform an encryption \nor a decryption on page 747, Initialization with the saved configuration. For the \nAES-ECB or AES-CBC decryption, the key must be prepared again.\nb) \nWrite the data that were saved during context saving into the IN FIFO.\nc) \nIf needed, reconfigure the DMA controller to transfer the rest of the message.\nd) \nEnable the processor by setting the CRYPEN bit and, the DMA requests by setting \nthe DIEN and DOEN bits.\n23.4 \nCRYP interrupts\nThere are two individual maskable interrupt sources generated by the CRYP. These two \nsources are combined into a single interrupt signal, which is the only interrupt signal from \nthe CRYP that drives the NVIC (nested vectored interrupt controller). This combined \ninterrupt, which is an OR function of the individual masked sources, is asserted if any of the \nindividual interrupts listed below is asserted and enabled.\nYou can enable or disable the interrupt sources individually by changing the mask bits in the \nCRYP_IMSCR register. Setting the appropriate mask bit to ‘1’ enables the interrupt.\nThe status of the individual interrupt sources can be read either from the CRYP_RISR \nregister, for raw interrupt status, or from the CRYP_MISR register, for the masked interrupt \nstatus.\nOutput FIFO service interrupt - OUTMIS\nThe output FIFO service interrupt is asserted when there is one or more (32-bit word) data \nitems in the output FIFO. This interrupt is cleared by reading data from the output FIFO until \nthere is no valid (32-bit) word left (that is, the interrupt follows the state of the OFNE (output \nFIFO not empty) flag).\nThe output FIFO service interrupt OUTMIS is NOT enabled with the CRYP enable bit. \nConsequently, disabling the CRYP does not force the OUTMIS signal low if the output FIFO \nis not empty.\nInput FIFO service interrupt - INMIS\nThe input FIFO service interrupt is asserted when there are less than four words in the input \nFIFO. It is cleared by performing write operations to the input FIFO until it holds four or more \nwords.\nThe input FIFO service interrupt INMIS is enabled with the CRYP enable bit. Consequently, \nwhen CRYP is disabled, the INMIS signal is low even if the input FIFO is empty.\n" }, { "page_number": 751, "page_indices": { "start_index": 1459113, "end_index": 1461214 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 751 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.5 CRYP DMA interface", 751 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.1 CRYP control register (CRYP_CR) for STM32F415/417xx", 751 ] ], "page_content": "RM0090 Rev 21\n751/1757\nRM0090\nCryptographic processor (CRYP)\n769\nFigure 231. CRYP interrupt mapping diagram\n23.5 \nCRYP DMA interface\nThe cryptographic processor provides an interface to connect to the DMA controller. The \nDMA operation is controlled through the CRYP DMA control register, CRYP_DMACR.\nThe burst and single transfer request signals are not mutually exclusive. They can both be \nasserted at the same time. For example, when there are 6 words available in the OUT FIFO, \nthe burst transfer request and the single transfer request are asserted. After a burst transfer \nof 4 words, the single transfer request only is asserted to transfer the last 2 available words. \nThis is useful for situations where the number of words left to be received in the stream is \nless than a burst.\nEach request signal remains asserted until the relevant DMA clear signal is asserted. After \nthe request clear signal is deasserted, a request signal can become active again, depending \non the above described conditions. All request signals are deasserted if the CRYP \nperipheral is disabled or the DMA enable bit is cleared (DIEN bit for the IN FIFO and DOEN \nbit for the OUT FIFO in the CRYP_DMACR register).\nNote:\nThe DMA controller must be configured to perform burst of 4 words or less. Otherwise some \ndata could be lost.\nIn order to let the DMA controller empty the OUT FIFO before filling up the IN FIFO, the \nOUTDMA channel should have a higher priority than the INDMA channel.\n23.6 \nCRYP registers\nThe cryptographic core is associated with several control and status registers, eight key \nregisters and four initialization vectors registers.\n23.6.1 \nCRYP control register (CRYP_CR) for STM32F415/417xx\nAddress offset: 0x00\nReset value: 0x0000 0000\n \nINRIS\nINIM\nCRYPEN\nINMIS\nIN FIFO Interrupt - INMIS\nOUTRIS\nOUTIM\nOUTMIS\nOUT FIFO Interrupt - OUTMIS\nGlobal Interrupt\nai16077\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCRYPEN FFLUSH\nReserved\nKEYSIZE\nDATATYPE\nALGOMODE[2:0]\nALGODIR\nRes.\nRes.\nrw\nw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 752, "page_indices": { "start_index": 1461214, "end_index": 1463127 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 752 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.1 CRYP control register (CRYP_CR) for STM32F415/417xx", 751 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n752/1757\nRM0090 Rev 21\n \nBits 31:18 Reserved, must be kept at reset value\nBits 17:16 Reserved, must be kept at reset value\nBit 15 CRYPEN: Cryptographic processor enable\n0: CRYP processor is disabled\n1: CRYP processor is enabled\nNote: The CRYPEN bit is automatically cleared by hardware when the key \npreparation process ends (ALGOMODE=111b) or GCM_CCM init Phase\nBit 14 FFLUSH: FIFO flush\nWhen CRYPEN = 0, writing this bit to 1 flushes the IN and OUT FIFOs (that is \nread and write pointers of the FIFOs are reset. Writing this bit to 0 has no effect.\nWhen CRYPEN = 1, writing this bit to 0 or 1 has no effect.\nReading this bit always returns 0.\nBits 13:10 Reserved, must be kept at reset value\nBits 9:8 KEYSIZE[1:0]: Key size selection (AES mode only)\nThis bitfield defines the bit-length of the key used for the AES cryptographic core. \nThis bitfield is ‘don’t care’ in the DES or TDES modes.\n00: 128 bit key length\n01: 192 bit key length\n10: 256 bit key length\n11: Reserved, do not use this value\nBits 7:6 DATATYPE[1:0]: Data type selection\nThis bitfield defines the format of data entered in the CRYP_DIN register (refer to \nSection 23.3.3: Data type).\n00: 32-bit data. No swapping of each word. First word pushed into the IN FIFO \n(or popped off the OUT FIFO) forms bits 1...32 of the data block, the second \nword forms bits 33...64.\n01: 16-bit data, or half-word. Each word pushed into the IN FIFO (or popped off \nthe OUT FIFO) is considered as 2 half-words, which are swapped with each \nother.\n10: 8-bit data, or bytes. Each word pushed into the IN FIFO (or popped off the \nOUT FIFO) is considered as 4 bytes, which are swapped with each other.\n11: bit data, or bit-string. Each word pushed into the IN FIFO (or popped off the \nOUT FIFO) is considered as 32 bits (1st bit of the string at position 0), which are \nswapped with each other.\n" }, { "page_number": 753, "page_indices": { "start_index": 1463127, "end_index": 1466096 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 753 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.2 CRYP control register (CRYP_CR) for STM32F415/417xx", 753 ] ], "page_content": "RM0090 Rev 21\n753/1757\nRM0090\nCryptographic processor (CRYP)\n769\nNote:\nWriting to the KEYSIZE, DATATYPE, ALGOMODE and ALGODIR bits while BUSY=1 has \nno effect. These bits can only be configured when BUSY=0.\nThe FFLUSH bit has to be set only when BUSY=0. If not, the FIFO is flushed, but the block \nbeing processed may be pushed into the output FIFO just after the flush operation, resulting \nin a nonempty FIFO condition.\n23.6.2 \nCRYP control register (CRYP_CR) for STM32F415/417xx\nAddress offset: 0x00\nReset value: 0x0000 0000\n Bits 5:3 ALGOMODE[2:0]: Algorithm mode\n000: TDES-ECB (triple-DES Electronic codebook): no feedback between blocks \nof data. Initialization vectors (CRYP_IV0(L/R)) are not used, three key vectors \n(K1, K2, and K3) are used (K0 is not used).\n001: TDES-CBC (triple-DES Cipher block chaining): output block is XORed with \nthe subsequent input block before its entry into the algorithm. Initialization \nvectors (CRYP_IV0L/R) must be initialized, three key vectors (K1, K2, and K3) \nare used (K0 is not used).\n010: DES-ECB (simple DES Electronic codebook): no feedback between blocks \nof data. Initialization vectors (CRYP_IV0L/R) are not used, only one key vector \n(K1) is used (K0, K2, K3 are not used).\n011: DES-CBC (simple DES Cipher block chaining): output block is XORed with \nthe subsequent input block before its entry into the algorithm. Initialization \nvectors (CRYP_IV0L/R) must be initialized. Only one key vector (K1) is used \n(K0, K2, K3 are not used).\n100: AES-ECB (AES Electronic codebook): no feedback between blocks of data. \nInitialization vectors (CRYP_IV0L/R...1L/R) are not used. All four key vectors \n(K0...K3) are used.\n101: AES-CBC (AES Cipher block chaining): output block is XORed with the \nsubsequent input block before its entry into the algorithm. Initialization vectors \n(CRYP_IV0L/R...1L/R) must be initialized. All four key vectors (K0...K3) are \nused.\n110: AES-CTR (AES counter mode): output block is XORed with the subsequent \ninput block before its entry into the algorithm. Initialization vectors \n(CRYP_IV0L/R...1L/R) must be initialized. All four key vectors (K0...K3) are \nused. CTR decryption does not differ from CTR encryption, since the core \nalways encrypts the current counter block to produce the key stream that is \nXORed with the plaintext or cipher in input. Thus, ALGODIR is don’t care when \nALGOMODE = 110b, and the key must NOT be unrolled (prepared) for \ndecryption.\n111: AES key preparation for decryption mode. Writing this value when CRYPEN \n= 1 immediately starts an AES round for key preparation. The secret key must \nhave previously been loaded into the K0...K3 registers. The BUSY bit in the \nCRYP_SR register is set during the key preparation. After key processing, the \nresulting key is copied back into the K0...K3 registers, and the BUSY bit is \ncleared.\nBit 2 ALGODIR: Algorithm direction\n0: Encrypt\n1: Decrypt\nBits 1:0 Reserved, must be kept at reset value\n" }, { "page_number": 754, "page_indices": { "start_index": 1466096, "end_index": 1468411 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 754 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.2 CRYP control register (CRYP_CR) for STM32F415/417xx", 753 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n754/1757\nRM0090 Rev 21\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nALGO\nMODE\n[3]\nRes.\nGCM_CCMPH\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCRYPEN FFLUSH\nReserved\nKEYSIZE\nDATATYPE\nALGOMODE[2:0]\nALGODIR\nReserved\nrw\nw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:20 Reserved, forced by hardware to 0.\nBit 18 Reserved, forced by hardware to 0.\nBits 17:16 GCM_CCMPH[1:0]: no effect if “GCM or CCM algorithm” is not set\n00: GCM_CCM init Phase\n01: GCM_CCM header phase\n10: GCM_CCM payload phase\n11: GCM_CCM final phase\nBit 15 CRYPEN: Cryptographic processor enable\n0: CRYP processor is disabled\n1: CRYP processor is enabled\nNote: The CRYPEN bit is automatically cleared by hardware when the key \npreparation process ends (ALGOMODE=111b) or GCM_CCM init Phase\nBit 14 FFLUSH: FIFO flush\nWhen CRYPEN = 0, writing this bit to 1 flushes the IN and OUT FIFOs (that is \nread and write pointers of the FIFOs are reset. Writing this bit to 0 has no effect.\nWhen CRYPEN = 1, writing this bit to 0 or 1 has no effect.\nReading this bit always returns 0.\nBits 13:10 Reserved, forced by hardware to 0.\nBits 9:8 KEYSIZE[1:0]: Key size selection (AES mode only)\nThis bitfield defines the bit-length of the key used for the AES cryptographic core. \nThis bitfield is ‘don’t care’ in the DES or TDES modes.\n00: 128 bit key length\n01: 192 bit key length\n10: 256 bit key length\n11: Reserved, do not use this value\nBits 7:6 DATATYPE[1:0]: Data type selection\nThis bitfield defines the format of data entered in the CRYP_DIN register (refer to \nSection 23.3.3: Data type).\n00: 32-bit data. No swapping of each word. First word pushed into the IN FIFO \n(or popped off the OUT FIFO) forms bits 1...32 of the data block, the second \nword forms bits 33...64.\n01: 16-bit data, or half-word. Each word pushed into the IN FIFO (or popped off \nthe OUT FIFO) is considered as 2 half-words, which are swapped with each \nother.\n10: 8-bit data, or bytes. Each word pushed into the IN FIFO (or popped off the \nOUT FIFO) is considered as 4 bytes, which are swapped with each other.\n11: bit data, or bit-string. Each word pushed into the IN FIFO (or popped off the \nOUT FIFO) is considered as 32 bits (1st bit of the string at position 0), which are \nswapped with each other.\n" }, { "page_number": 755, "page_indices": { "start_index": 1468411, "end_index": 1471462 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 755 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.2 CRYP control register (CRYP_CR) for STM32F415/417xx", 753 ] ], "page_content": "RM0090 Rev 21\n755/1757\nRM0090\nCryptographic processor (CRYP)\n769\nNote:\nWriting to the KEYSIZE, DATATYPE, ALGOMODE and ALGODIR bits while BUSY=1 has \nno effect. These bits can only be configured when BUSY=0.\nThe FFLUSH bit has to be set only when BUSY=0. If not, the FIFO is flushed, but the block \nbeing processed may be pushed into the output FIFO just after the flush operation, resulting \nin a nonempty FIFO condition.\nBits 19 and 5:3 ALGOMODE[3:0]: Algorithm mode\n0000: TDES-ECB (triple-DES Electronic codebook): no feedback between \nblocks of data. Initialization vectors (CRYP_IV0(L/R)) are not used, three key \nvectors (K1, K2, and K3) are used (K0 is not used).\n0001: TDES-CBC (triple-DES Cipher block chaining): output block is XORed \nwith the subsequent input block before its entry into the algorithm. Initialization \nvectors (CRYP_IV0L/R) must be initialized, three key vectors (K1, K2, and K3) \nare used (K0 is not used).\n0010: DES-ECB (simple DES Electronic codebook): no feedback between \nblocks of data. Initialization vectors (CRYP_IV0L/R) are not used, only one key \nvector (K1) is used (K0, K2, K3 are not used).\n0011: DES-CBC (simple DES Cipher block chaining): output block is XORed with \nthe subsequent input block before its entry into the algorithm. Initialization \nvectors (CRYP_IV0L/R) must be initialized. Only one key vector (K1) is used \n(K0, K2, K3 are not used).\n0100: AES-ECB (AES Electronic codebook): no feedback between blocks of \ndata. Initialization vectors (CRYP_IV0L/R...1L/R) are not used. All four key \nvectors (K0...K3) are used.\n0101: AES-CBC (AES Cipher block chaining): output block is XORed with the \nsubsequent input block before its entry into the algorithm. Initialization vectors \n(CRYP_IV0L/R...1L/R) must be initialized. All four key vectors (K0...K3) are \nused.\n0110: AES-CTR (AES Counter mode): output block is XORed with the \nsubsequent input block before its entry into the algorithm. Initialization vectors \n(CRYP_IV0L/R...1L/R) must be initialized. All four key vectors (K0...K3) are \nused. CTR decryption does not differ from CTR encryption, since the core \nalways encrypts the current counter block to produce the key stream that is \nXORed with the plaintext or cipher in input. Thus, ALGODIR is don’t care when \nALGOMODE = 110b, and the key must NOT be unrolled (prepared) for \ndecryption.\n0111: AES key preparation for decryption mode. Writing this value when \nCRYPEN = 1 immediately starts an AES round for key preparation. The secret \nkey must have previously been loaded into the K0...K3 registers. The BUSY bit \nin the CRYP_SR register is set during the key preparation. After key processing, \nthe resulting key is copied back into the K0...K3 registers, and the BUSY bit is \ncleared.\n1000: Galois Counter Mode (GCM). This algorithm mode is also used for the \nGMAC algorithm.\n1001: Counter with CBC-MAC (CCM). This algorithm mode is also used for the \nCMAC algorithm.\nBit 2 ALGODIR: Algorithm direction\n0: Encrypt\n1: Decrypt\nBits 1:0 Reserved, must be kept to 0.\n" }, { "page_number": 756, "page_indices": { "start_index": 1471462, "end_index": 1472636 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 756 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.3 CRYP status register (CRYP_SR)", 756 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n756/1757\nRM0090 Rev 21\n23.6.3 \nCRYP status register (CRYP_SR)\nAddress offset: 0x04\nReset value: 0x0000 0003\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBUSY\nOFFU\nOFNE\nIFNF\nIFEM\nr\nr\nr\nr\nr\nBits 31:5 Reserved, must be kept at reset value\nBit 4 BUSY: Busy bit\n0: The CRYP Core is not processing any data. The reason is either that:\n–\nthe CRYP core is disabled (CRYPEN=0 in the CRYP_CR register) and \nthe last processing has completed, or\n–\nThe CRYP core is waiting for enough data in the input FIFO or enough \nfree space in the output FIFO (that is in each case at least 2 words in \nthe DES, 4 words in the AES).\n1: The CRYP core is currently processing a block of data or a key preparation \n(for AES decryption).\nBit 3 OFFU: Output FIFO full\n0: Output FIFO is not full\n1: Output FIFO is full\nBit 2 OFNE: Output FIFO not empty\n0: Output FIFO is empty\n1: Output FIFO is not empty\nBit 1 IFNF: Input FIFO not full\n0: Input FIFO is full\n1: Input FIFO is not full\nBit 0 IFEM: Input FIFO empty\n0: Input FIFO is not empty\n1: Input FIFO is empty\n" }, { "page_number": 757, "page_indices": { "start_index": 1472636, "end_index": 1475390 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 757 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.4 CRYP data input register (CRYP_DIN)", 757 ] ], "page_content": "RM0090 Rev 21\n757/1757\nRM0090\nCryptographic processor (CRYP)\n769\n23.6.4 \nCRYP data input register (CRYP_DIN)\nAddress offset: 0x08\nReset value: 0x0000 0000\nThe CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter up to \nfour 64-bit (TDES) or two 128-bit (AES) plaintext (when encrypting) or ciphertext (when \ndecrypting) blocks into the input FIFO, one 32-bit word at a time.\nThe first word written into the FIFO is the MSB of the input block. The LSB of the input block \nis written at the end. Disregarding the data swapping, this gives:\n•\nIn the DES/TDES modes: a block is a sequence of bits numbered from bit 1 (leftmost \nbit) to bit 64 (rightmost bit). Bit 1 corresponds to the MSB (bit 31) of the first word \nentered into the FIFO, bit 64 corresponds to the LSB (bit 0) of the second word entered \ninto the FIFO.\n•\nIn the AES mode: a block is a sequence of bits numbered from 0 (leftmost bit) to 127 \n(rightmost bit). Bit 0 corresponds to the MSB (bit 31) of the first word written into the \nFIFO, bit 127 corresponds to the LSB (bit 0) of the 4th word written into the FIFO.\nTo fit different data sizes, the data written in the CRYP_DIN register can be swapped before \nbeing processed by configuring the DATATYPE bits in the CRYP_CR register. Refer to \nSection 23.3.3: Data type on page 742 for more details.\nWhen CRYP_DIN register is written to, the data are pushed into the input FIFO. When at \nleast two 32-bit words in the DES/TDES mode (or four 32-bit words in the AES mode) have \nbeen pushed into the input FIFO, and when at least 2 words are free in the output FIFO, the \nCRYP engine starts an encrypting or decrypting process. This process takes two 32-bit \nwords in the DES/TDES mode (or four 32-bit words in the AES mode) from the input FIFO \nand delivers two 32-bit words (or 4, respectively) to the output FIFO per process round.\nWhen CRYP_DIN register is read:\n•\nIf CRYPEN = 0, the FIFO is popped, and then the data present in the Input FIFO are \nreturned, from the oldest one (first reading) to the newest one (last reading). The IFEM \nflag must be checked before each read operation to make sure that the FIFO is not \nempty.\n•\nif CRYPEN = 1, an undefined value is returned.\nAfter the CRYP_DIN register has been read once or several times, the FIFO must be \nflushed by setting the FFLUSH bit prior to processing new data.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATAIN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATAIN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 DATAIN: Data input\nRead = returns Input FIFO content if CRYPEN = 0, else returns an undefined \nvalue.\nWrite = Input FIFO is written.\n" }, { "page_number": 758, "page_indices": { "start_index": 1475390, "end_index": 1477040 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 758 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.5 CRYP data output register (CRYP_DOUT)", 758 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n758/1757\nRM0090 Rev 21\n23.6.5 \nCRYP data output register (CRYP_DOUT)\nAddress offset: 0x0C\nReset value: 0x0000 0000\nThe CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is \nused to retrieve up to four 64-bit (TDES mode) or two 128-bit (AES mode) ciphertext (when \nencrypting) or plaintext (when decrypting) blocks from the output FIFO, one 32-bit word at a \ntime.\nLike for the input data, the MSB of the output block is the first word read from the output \nFIFO. The LSB of the output block is read at the end. Disregarding data swapping, this \ngives:\n•\nIn the DES/TDES modes: Bit 1 (leftmost bit) corresponds to the MSB (bit 31) of the first \nword read from the FIFO, bit 64 (rightmost bit) corresponds to the LSB (bit 0) of the \nsecond word read from the FIFO.\n•\nIn the AES mode: Bit 0 (leftmost bit) corresponds to the MSB (bit 31) of the first word \nread from the FIFO, bit 127 (rightmost bit) corresponds to the LSB (bit 0) of the 4th \nword read from the FIFO.\nTo fit different data sizes, the data can be swapped after processing by configuring the \nDATATYPE bits in the CRYP_CR register. Refer to Section 23.3.3: Data type on page 742 \nfor more details.\nWhen CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to \nby the read pointer) is returned.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATAOUT\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATAOUT\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 DATAOUT: Data output\nRead = returns output FIFO content.\nWrite = No effect.\n" }, { "page_number": 759, "page_indices": { "start_index": 1477040, "end_index": 1478611 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 759 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.6 CRYP DMA control register (CRYP_DMACR)", 759 ], [ 3, "23.6.7 CRYP interrupt mask set/clear register (CRYP_IMSCR)", 759 ] ], "page_content": "RM0090 Rev 21\n759/1757\nRM0090\nCryptographic processor (CRYP)\n769\n23.6.6 \nCRYP DMA control register (CRYP_DMACR)\nAddress offset: 0x10\nReset value: 0x0000 0000\n \n \n23.6.7 \nCRYP interrupt mask set/clear register (CRYP_IMSCR)\nAddress offset: 0x14\nReset value: 0x0000 0000\nThe CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write \nregister. On a read operation, this register gives the current value of the mask on the \nrelevant interrupt. Writing 1 to the particular bit sets the mask, enabling the interrupt to be \nread. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when \nthe peripheral is reset.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDOEN\nDIEN\nrw\nrw\nBits 31:2 Reserved, must be kept at reset value\nBit 1 DOEN: DMA output enable\n0: DMA for outgoing data transfer is disabled\n1: DMA for outgoing data transfer is enabled\nBit 0 DIEN: DMA input enable\n0: DMA for incoming data transfer is disabled\n1: DMA for incoming data transfer is enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOUTIM\nINIM\nrw\nrw\nBits 31:2 Reserved, must be kept at reset value\nBit 1 OUTIM: Output FIFO service interrupt mask\n0: Output FIFO service interrupt is masked\n1: Output FIFO service interrupt is not masked\nBit 0 INIM: Input FIFO service interrupt mask\n0: Input FIFO service interrupt is masked\n1: Input FIFO service interrupt is not masked\n" }, { "page_number": 760, "page_indices": { "start_index": 1478611, "end_index": 1480045 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 760 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.8 CRYP raw interrupt status register (CRYP_RISR)", 760 ], [ 3, "23.6.9 CRYP masked interrupt status register (CRYP_MISR)", 760 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n760/1757\nRM0090 Rev 21\n23.6.8 \nCRYP raw interrupt status register (CRYP_RISR)\nAddress offset: 0x18\nReset value: 0x0000 0001\nThe CRYP_RISR register is the raw interrupt status register. It is a read-only register. On a \nread, this register gives the current raw status of the corresponding interrupt prior to \nmasking. A write has no effect.\n \n \n23.6.9 \nCRYP masked interrupt status register (CRYP_MISR)\nAddress offset: 0x1C\nReset value: 0x0000 0000\nThe CRYP_MISR register is the masked interrupt status register. It is a read-only register. \nOn a read, this register gives the current masked status of the corresponding interrupt prior \nto masking. A write has no effect.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOUTRIS\nINRIS\nr\nr\nBits 31:2 Reserved, must be kept at reset value\nBit 1 OUTRIS: Output FIFO service raw interrupt status\nGives the raw interrupt state prior to masking of the output FIFO service \ninterrupt.\n0: Raw interrupt not pending\n1: Raw interrupt pending\nBit 0 INRIS: Input FIFO service raw interrupt status\nGives the raw interrupt state prior to masking of the Input FIFO service interrupt.\n0: Raw interrupt not pending\n1: Raw interrupt pending\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOUTMIS\nINMIS\nr\nr\n" }, { "page_number": 761, "page_indices": { "start_index": 1480045, "end_index": 1482241 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 761 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.10 CRYP key registers (CRYP_K0...3(L/R)R)", 761 ], [ 4, "CRYP_K0LR (address offset: 0x20)", 761 ], [ 4, "CRYP_K0RR (address offset: 0x24)", 761 ] ], "page_content": "RM0090 Rev 21\n761/1757\nRM0090\nCryptographic processor (CRYP)\n769\n \n23.6.10 \nCRYP key registers (CRYP_K0...3(L/R)R)\nAddress offset: 0x20 to 0x3C\nReset value: 0x0000 0000\nThese registers contain the cryptographic keys.\nIn the TDES mode, keys are 64-bit binary values (number from left to right, that is the \nleftmost bit is bit 1), named K1, K2 and K3 (K0 is not used), each key consists of 56 \ninformation bits and 8 parity bits. The parity bits are reserved for error detection purposes \nand are not used by the current block. Thus, bits 8, 16, 24, 32, 40, 48, 56 and 64 of each 64-\nbit key value Kx[1:64] are not used.\nIn the AES mode, the key is considered as a single 128-, 192- or 256-bit long bit sequence, \nk0k1k2...k127/191/255 (k0 being the leftmost bit). The AES key is entered into the registers as \nfollows:\n•\nfor AES-128: k0..k127 corresponds to b127..b0 (b255..b128 are not used),\n•\nfor AES-192: k0..k191 corresponds to b191..b0 (b255..b192 are not used),\n•\nfor AES-256: k0..k255 corresponds to b255..b0.\nIn any case b0 is the rightmost bit.\nCRYP_K0LR (address offset: 0x20)\nCRYP_K0RR (address offset: 0x24)\nBits 31:2 Reserved, must be kept at reset value\nBit 1 OUTMIS: Output FIFO service masked interrupt status\nGives the interrupt state after masking of the output FIFO service interrupt.\n0: Interrupt not pending\n1: Interrupt pending\nBit 0 INMIS: Input FIFO service masked interrupt status\nGives the interrupt state after masking of the input FIFO service interrupt.\n0: Interrupt not pending\n1: Interrupt pending when CRYPEN = 1\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nb255\nb254\nb253\nb252\nb251\nb250\nb249\nb248\nb247\nb246\nb245\nb244\nb243\nb242\nb241\nb240\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nb239\nb238\nb237\nb236\nb235\nb234\nb233\nb232\nb231\nb230\nb229\nb228\nb227\nb226\nb225\nb224\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nb223\nb222\nb221\nb220\nb219\nb218\nb217\nb216\nb215\nb214\nb213\nb212\nb211\nb210\nb209\nb208\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nb207\nb206\nb205\nb204\nb203\nb202\nb201\nb200\nb199\nb198\nb197\nb196\nb195\nb194\nb193\nb192\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n" }, { "page_number": 762, "page_indices": { "start_index": 1482241, "end_index": 1484904 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 762 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.10 CRYP key registers (CRYP_K0...3(L/R)R)", 761 ], [ 4, "CRYP_K1LR (address offset: 0x28)", 762 ], [ 4, "CRYP_K1RR (address offset: 0x2C)", 762 ], [ 4, "CRYP_K2LR (address offset: 0x30)", 762 ], [ 4, "CRYP_K2RR (address offset: 0x34)", 762 ], [ 4, "CRYP_K3LR (address offset: 0x38)", 762 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n762/1757\nRM0090 Rev 21\nCRYP_K1LR (address offset: 0x28)\nCRYP_K1RR (address offset: 0x2C)\nCRYP_K2LR (address offset: 0x30)\nCRYP_K2RR (address offset: 0x34)\nCRYP_K3LR (address offset: 0x38)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nk1.1\nb191\nk1.2\nb190\nk1.3\nb189\nk1.4\nb188\nk1.5\nb187\nk1.6\nb186\nk1.7\nb185\nk1.8\nb184\nk1.9\nb183\nk1.10\nb182\nk1.11\nb181\nk1.12\nb180\nk1.13\nb179\nk1.14\nb178\nk1.15\nb177\nk1.16\nb176\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nk1.17\nb175\nk1.18\nb174\nk1.19\nb173\nk1.20\nb172\nk1.21\nb171\nk1.22\nb170\nk1.23\nb169\nk1.24\nb168\nk1.25\nb167\nk1.26\nb166\nk1.27\nb165\nk1.28\nb164\nk1.29\nb163\nk1.30\nb162\nk1.31\nb161\nk1.32\nb160\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nk1.33\nb159\nk1.34\nb158\nk1.35\nb157\nk1.36\nb156\nk1.37\nb155\nk1.38\nb154\nk1.39\nb153\nk1.40\nb152\nk1.41\nb151\nk1.42\nb150\nk1.43\nb149\nk1.44\nb148\nk1.45\nb147\nk1.46\nb146\nk1.47\nb145\nk1.48\nb144\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nk1.49\nb143\nk1.50\nb142\nk1.51\nb141\nk1.52\nb140\nk1.53\nb139\nk1.54\nb138\nk1.55\nb137\nk1.56\nb136\nk1.57\nb135\nk1.58\nb134\nk1.59\nb133\nk1.60\nb132\nk1.61\nb131\nk1.62\nb130\nk1.63\nb129\nk1.64\nb128\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nk2.1\nb127\nk2.2\nb126\nk2.3\nb125\nk2.4\nb124\nk2.5\nb123\nk2.6\nb122\nk2.7\nb121\nk2.8\nb120\nk2.9\nb119\nk2.10\nb118\nk2.11\nb117\nk2.12\nb116\nk2.13\nb115\nk2.14\nb114\nk2.15\nb113\nk2.16\nb112\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nk2.17\nb111\nk2.18\nb110\nk2.19\nb109\nk2.20\nb108\nk2.21\nb107\nk2.22\nb106\nk2.23\nb105\nk2.24\nb104\nk2.25\nb103\nk2.26\nb102\nk2.27\nb101\nk2.28\nb100\nk2.29\nb99\nk2.30\nb98\nk2.31\nb97\nk2.32\nb96\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nk2.33\nb95\nk2.34\nb94\nk2.35\nb93\nk2.36\nb92\nk2.37\nb91\nk2.38\nb90\nk2.39\nb89\nk2.40\nb88\nk2.41\nb87\nk2.42\nb86\nk2.43\nb85\nk2.44\nb84\nk2.45\nb83\nk2.46\nb82\nk2.47\nb81\nk2.48\nb80\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nk2.49\nb79\nk2.50\nb78\nk2.51\nb77\nk2.52\nb76\nk2.53\nb75\nk2.54\nb74\nk2.55\nb73\nk2.56\nb72\nk2.57\nb71\nk2.58\nb70\nk2.59\nb69\nk2.60\nb68\nk2.61\nb67\nk2.62\nb66\nk2.63\nb65\nk2.64\nb64\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nk3.1\nb63\nk3.2\nb62\nk3.3\nb61\nk3.4\nb60\nk3.5\nb59\nk3.6\nb58\nk3.7\nb57\nk3.8\nb56\nk3.9\nb55\nk3.10\nb54\nk3.11\nb53\nk3.12\nb52\nk3.13\nb51\nk3.14\nb50\nk3.15\nb49\nk3.16\nb48\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nk3.17\nb47\nk3.18\nb46\nk3.19\nb45\nk3.20\nb44\nk3.21\nb43\nk3.22\nb42\nk3.23\nb41\nk3.24\nb40\nk3.25\nb39\nk3.26\nb38\nk3.27\nb37\nk3.28\nb36\nk3.29\nb35\nk3.30\nb34\nk3.31\nb33\nk3.32\nb32\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n" }, { "page_number": 763, "page_indices": { "start_index": 1484904, "end_index": 1487172 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 763 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.10 CRYP key registers (CRYP_K0...3(L/R)R)", 761 ], [ 4, "CRYP_K3RR (address offset: 0x3C)", 763 ], [ 3, "23.6.11 CRYP initialization vector registers (CRYP_IV0...1(L/R)R)", 763 ], [ 4, "CRYP_IV0LR (address offset: 0x40)", 763 ], [ 4, "CRYP_IV0RR (address offset: 0x44)", 763 ] ], "page_content": "RM0090 Rev 21\n763/1757\nRM0090\nCryptographic processor (CRYP)\n769\nCRYP_K3RR (address offset: 0x3C)\nNote:\nWrite accesses to these registers are disregarded when the cryptographic processor is busy \n(bit BUSY = 1 in the CRYP_SR register).\n23.6.11 \nCRYP initialization vector registers (CRYP_IV0...1(L/R)R)\nAddress offset: 0x40 to 0x4C\nReset value: 0x0000 0000\nThe CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization \nvector (64 bits for DES/TDES and 128 bits for AES) and are used in the CBC (Cipher block \nchaining) and Counter (CTR) modes. After each computation round of the TDES or AES \nCore, the CRYP_IV0...1(L/R)R registers are updated as described in Section : DES and \nTDES Cipher block chaining (DES/TDES-CBC) mode on page 729, Section : AES Cipher \nblock chaining (AES-CBC) mode on page 733 and Section : AES counter mode (AES-CTR) \nmode on page 735.\nIV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of \nthe initialization vector. IV1(L/R)R is used only in the AES.\nCRYP_IV0LR (address offset: 0x40)\nCRYP_IV0RR (address offset: 0x44)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nk3.33\nb31\nk3.34\nb30\nk3.35\nb29\nk3.36\nb28\nk3.37\nb27\nk3.38\nb26\nk3.39\nb25\nk3.40\nb24\nk3.41\nb23\nk3.42\nb22\nk3.43\nb21\nk3.44\nb20\nk3.45\nb19\nk3.46\nb18\nk3.47\nb17\nk3.48\nb16\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nk3.49\nb15\nk3.50\nb14\nk3.51\nb13\nk3.52\nb12\nk3.53\nb11\nk3.54\nb10\nk3.55\nb9\nk3.56\nb8\nk3.57\nb7\nk3.58\nb6\nk3.59\nb5\nk3.60\nb4\nk3.61\nb3\nk3.62\nb2\nk3.63\nb1\nk3.64\nb0\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nIV0\nIV1\nIV2\nIV3\nIV4\nIV5\nIV6\nIV7\nIV8\nIV9\nIV10\nIV11\nIV12\nIV13\nIV14\nIV15\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nIV16\nIV17\nIV18\nIV19\nIV20\nIV21\nIV22\nIV23\nIV24\nIV25\nIV26\nIV27\nIV28\nIV29\nIV30\nIV31\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nIV32\nIV33\nIV34\nIV35\nIV36\nIV37\nIV38\nIV39\nIV40\nIV41\nIV42\nIV43\nIV44\nIV45\nIV46\nIV47\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nIV48\nIV49\nIV50\nIV51\nIV52\nIV53\nIV54\nIV55\nIV56\nIV57\nIV58\nIV59\nIV60\nIV61\nIV62\nIV63\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 764, "page_indices": { "start_index": 1487172, "end_index": 1488218 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 764 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.11 CRYP initialization vector registers (CRYP_IV0...1(L/R)R)", 763 ], [ 4, "CRYP_IV1LR (address offset: 0x48)", 764 ], [ 4, "CRYP_IV1RR (address offset: 0x4C)", 764 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n764/1757\nRM0090 Rev 21\nCRYP_IV1LR (address offset: 0x48)\nCRYP_IV1RR (address offset: 0x4C)\nNote:\nIn DES/3DES modes, only CRYP_IV0(L/R) is used.\nWrite access to these registers are disregarded when the cryptographic processor is busy \n(bit BUSY = 1 in the CRYP_SR register).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nIV64\nIV65\nIV66\nIV67\nIV68\nIV69\nIV70\nIV71\nIV72\nIV73\nIV74\nIV75\nIV76\nIV77\nIV78\nIV79\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nIV80\nIV81\nIV82\nIV83\nIV84\nIV85\nIV86\nIV87\nIV88\nIV89\nIV90\nIV91\nIV92\nIV93\nIV94\nIV95\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nIV96\nIV97\nIV98\nIV99\nIV100\nIV101\nIV102\nIV103\nIV104\nIV105\nIV106\nIV107\nIV108\nIV109\nIV110\nIV111\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nIV112\nIV113\nIV114\nIV115\nIV116\nIV117\nIV118\nIV119\nIV120\nIV121\nIV122\nIV123\nIV124\nIV125\nIV126\nIV127\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 765, "page_indices": { "start_index": 1488218, "end_index": 1489941 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 765 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.12 CRYP context swap registers (CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R) for STM32F42xxx and STM32F43xxx", 765 ], [ 4, "CRYP_CSGCMCCMxR: where x=[7:0]", 765 ], [ 4, "CRYP_CSGCMxR: where x=[7:0]", 765 ] ], "page_content": "RM0090 Rev 21\n765/1757\nRM0090\nCryptographic processor (CRYP)\n769\n23.6.12 \nCRYP context swap registers (CRYP_CSGCMCCM0..7R and\nCRYP_CSGCM0..7R) for STM32F42xxx and STM32F43xxx\nAddress offset: \n•\nCRYP_CSGCMCCM0..7: 0x050 to 0x06C: used for GCM/GMAC or CCM/CMAC \nalogrithm only\n•\nCRYP_CSGCM0..7: 0x070 to 0x08C: used for GCM/GMAC algorithm only\nReset value: 0x0000 0000\nThese registers contain the complete internal register states of the CRYP processor when \nthe GCM/GMAC or CCM/CMAC algorithm is selected. They are useful when a context swap \nhas to be performed because a high-priority task needs the cryptographic processor while it \nis already in use by another task. \nWhen such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in \nGCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM/CMAC mode) registers have to \nbe read and the values retrieved have to be saved in the system memory space. The \ncryptographic processor can then be used by the preemptive task, and when the \ncryptographic computation is complete, the saved context can be read from memory and \nwritten back into the corresponding context swap registers.\nNote:\nThese registers are used only when GCM/GMAC or CCM/CMAC algorithm mode is \nselected.\nCRYP_CSGCMCCMxR: where x=[7:0]\nCRYP_CSGCMxR: where x=[7:0]\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCRYP_CSGCMCCMxR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCRYP_CSGCMCCMxR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCRYP_CSGCMxR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCRYP_CSGCMxR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 766, "page_indices": { "start_index": 1489941, "end_index": 1491287 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 766 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.13 CRYP register map", 766 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n766/1757\nRM0090 Rev 21\n23.6.13 \nCRYP register map\n Table 115. CRYP register map and reset values for STM32F415/417xx\nOffset\nRegister \nname and \nreset value\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\n0x00\nCRYP_CR\nReserved\nCRYPEN\nFFLUSH\nReserved\nKEYSIZE\nDATATYPE\nALOMODE[2:0]\nALGODIR\nRes.\nReset value\n0 0\n0 0 0 0 0 0 0 0\n0x04\nCRYP_SR\nReserved\nBUSY\nOFFU\nOFNE\nIFNF\nIFEM\nReset value\n0 0 0 1 1\n0x08\nCRYP_DIN\nDATAIN\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0\n0x0C\nCRYP_DOUT\nDATAOUT\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0\n0x10\nCRYP_DMAC\nR\nReserved\nDOEN\nDIEN\nReset value\n0 0\n0x14\nCRYP_IMSC\nR\nReserved\nOUTIM\nINIM\nReset value\n0 0\n0x18\nCRYP_RISR\nReserved\nOUTRIS\nINRIS\nReset value\n0 1\n0x1C\nCRYP_MISR\nReserved\nOUTMIS\nIN%IS\nReset value\n0 0\n0x20\nCRYP_K0LR\nCRYP_K0LR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x24\nCRYP_K0RR\nCRYP_K0RR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n...\n0x38\nCRYP_K3LR\nCRYP_K3LR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x3C\nCRYP_K3RR\nCRYP_K3RR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x40\nCRYP_IV0LR\nCRYP_IV0LR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n" }, { "page_number": 767, "page_indices": { "start_index": 1491287, "end_index": 1492582 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 767 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.13 CRYP register map", 766 ] ], "page_content": "RM0090 Rev 21\n767/1757\nRM0090\nCryptographic processor (CRYP)\n769\n \n0x44\nCRYP_IV0RR\nCRYP_IV0RR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x48\nCRYP_IV1LR\nCRYP_IV1LR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x4C\nCRYP_IV1RR\nCRYP_IV1RR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nTable 115. CRYP register map and reset values for STM32F415/417xx (continued)\nOffset\nRegister \nname and \nreset value\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTable 116. CRYP register map and reset values for STM32F43xxx\nOffset\nRegister \nname\nreset value\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\n0x00\nCRYP_CR\nReserved\nALGOMODE[3]\nRes.\nGCM_CCMPH\nCRYPEN\nFFLUSH\nReserved\nKEYSIZE\nDATATYPE\nALOMODE[2:0]\nALGODIR\nRes..\nReset value\n0 0 0 0\n0 0 0 0 0 0 0 0\n0x04\nCRYP_SR\nReserved\nBUSY\nOFFU\nOFNE\nIFNF\nIFEM\nReset value\n0 0 0 1 1\n0x08\nCRYP_DIN\nDATAIN\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0\n0x0C\nCRYP_DOUT\nDATAOUT\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0\n0x10\nCRYP_DMAC\nR\nReserved\nDOEN\nDIEN\nReset value\n0 0\n0x14\nCRYP_IMSC\nR\nReserved\nOUTIM\nINIM\nReset value\n0 0\n0x18\nCRYP_RISR\nReserved\nOUTRIS\nINRIS\nReset value\n0 1\n" }, { "page_number": 768, "page_indices": { "start_index": 1492582, "end_index": 1494195 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 768 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.13 CRYP register map", 766 ] ], "page_content": "Cryptographic processor (CRYP)\nRM0090\n768/1757\nRM0090 Rev 21\n0x1C\nCRYP_MISR\nReserved\nOUTMIS\nIN%IS\nReset value\n0 0\n0x20\nCRYP_K0LR\nCRYP_K0LR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x24\nCRYP_K0RR\nCRYP_K0RR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n...\n...\n0x38\nCRYP_K3LR\nCRYP_K3LR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x3C\nCRYP_K3RR\nCRYP_K3RR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x40\nCRYP_IV0LR\nCRYP_IV0LR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x44\nCRYP_IV0RR\nCRYP_IV0RR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x48\nCRYP_IV1LR\nCRYP_IV1LR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x4C\nCRYP_IV1RR\nCRYP_IV1RR\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x50\nCRYP_\nCSGCMCCM\nR\nCRYP_CSGCMCCM0R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x54\nCRYP_\nCSGCMCCM\n1R\nCRYP_CSGCMCCM1R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x58\nCRYP_\nCSGCMCCM\n2R\nCRYP_CSGCMCCM2R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x5C\nCRYP_\nCSGCMCCM\n3R\nCRYP_CSGCMCCM3R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nTable 116. CRYP register map and reset values for STM32F43xxx (continued)\nOffset\nRegister \nname\nreset value\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 769, "page_indices": { "start_index": 1494195, "end_index": 1495870 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 769 }, "toc_details": [ [ 1, "23 Cryptographic processor (CRYP)", 723 ], [ 2, "23.6 CRYP registers", 751 ], [ 3, "23.6.13 CRYP register map", 766 ] ], "page_content": "RM0090 Rev 21\n769/1757\nRM0090\nCryptographic processor (CRYP)\n769\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x60\nCRYP_\nCSGCMCCM\n4R\nCRYP_CSGCMCCM4R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x64\nCRYP_\nCSGCMCCM\n5R\nCRYP_CSGCMCCM5R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x68\nCRYP_\nCSGCMCCM\n6R\nCRYP_CSGCMCCM6R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x6C\nCRYP_\nCSGCMCCM\n7R\nCRYP_CSGCMCCM7R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x70\nCRYP_CSGC\nM0R\nCRYP_CSGCM0R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x74\nCRYP_CSGC\nM1R\nCRYP_CSGCM1R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x78\nCRYP_CSGC\nM2R\nCRYP_CSGCM2R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x7C\nCRYP_CSGC\nM3R\nCRYP_CSGCM3R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x80\nCRYP_CSGC\nM4R\nCRYP_CSGCM4R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x84\nCRYP_CSGC\nM5R\nCRYP_CSGCM5R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x88\nCRYP_CSGC\nM6R\nCRYP_CSGCM6R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x8C\nCRYP_CSGC\nM7R\nCRYP_CSGCM7R\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nTable 116. CRYP register map and reset values for STM32F43xxx (continued)\nOffset\nRegister \nname\nreset value\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 770, "page_indices": { "start_index": 1495870, "end_index": 1497376 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 770 }, "toc_details": [ [ 1, "24 Random number generator (RNG)", 770 ], [ 2, "24.1 RNG introduction", 770 ], [ 2, "24.2 RNG main features", 770 ], [ 2, "24.3 RNG functional description", 770 ] ], "page_content": "Random number generator (RNG)\nRM0090\n770/1757\nRM0090 Rev 21\n24 \nRandom number generator (RNG)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n24.1 \nRNG introduction\nThe RNG processor is a random number generator, based on a continuous analog noise, \nthat provides a random 32-bit value to the host when read. \nThe RNG passed the FIPS PUB 140-2 (2001 October 10) tests with a success ratio of 99%.\n24.2 \nRNG main features\n•\nIt delivers 32-bit random numbers, produced by an analog generator\n•\n40 periods of the RNG_CLK clock signal between two consecutive random numbers\n•\nMonitoring of the RNG entropy to flag abnormal behavior (generation of stable values, \nor of a stable sequence of values)\n•\nIt can be disabled to reduce power consumption\n24.3 \nRNG functional description\nFigure 232 shows the RNG block diagram.\nFigure 232. Block diagram\n1.\nFor more details about RNG Clock (RNG_CLK) source, please refer to Section 6: Reset and clock control \nfor STM32F42xxx and STM32F43xxx (RCC) and Section 7: Reset and clock control for \nSTM32F405xx/07xx and STM32F415xx/17xx(RCC).\nThe random number generator implements an analog circuit. This circuit generates seeds \nthat feed a linear feedback shift register (RNG_LFSR) in order to produce 32-bit random \nnumbers.\n32-bit AHB bus\nRNG_DR\nRNG _CR\nRNG _SR\nStatus register\nControl register\nfault detector\nLFSR\nAnalog seed\nRNG_CLK\nClock checker &\ndata register\n Shift Register\nfeed a Linear Feedback\nai16080\n" }, { "page_number": 771, "page_indices": { "start_index": 1497376, "end_index": 1500219 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 771 }, "toc_details": [ [ 1, "24 Random number generator (RNG)", 770 ], [ 2, "24.3 RNG functional description", 770 ], [ 3, "24.3.1 Operation", 771 ], [ 3, "24.3.2 Error management", 771 ], [ 4, "If the CEIS bit is read as ‘1’ (clock error)", 771 ], [ 4, "If the SEIS bit is read as ‘1’ (seed error)", 771 ], [ 2, "24.4 RNG registers", 771 ] ], "page_content": "RM0090 Rev 21\n771/1757\nRM0090\nRandom number generator (RNG)\n774\nThe analog circuit is made of several ring oscillators whose outputs are XORed to generate \nthe seeds. The RNG_LFSR is clocked by a dedicated clock (RNG_CLK) at a constant \nfrequency, so that the quality of the random number is independent of the HCLK frequency. \nThe contents of the RNG_LFSR are transferred into the data register (RNG_DR) when a \nsignificant number of seeds have been introduced into the RNG_LFSR.\nIn parallel, the analog seed and the dedicated RNG_CLK clock are monitored. Status bits (in \nthe RNG_SR register) indicate when an abnormal sequence occurs on the seed or when \nthe frequency of the RNG_CLK clock is too low. An interrupt can be generated when an \nerror is detected.\n24.3.1 \nOperation\nTo run the RNG, follow the steps below:\n1.\nEnable the interrupt if needed (to do so, set the IE bit in the RNG_CR register). An \ninterrupt is generated when a random number is ready or when an error occurs.\n2. \nEnable the random number generation by setting the RNGEN bit in the RNG_CR \nregister. This activates the analog part, the RNG_LFSR and the error detector.\n3. \nAt each interrupt, check that no error occurred (the SEIS and CEIS bits should be ‘0’ in \nthe RNG_SR register) and that a random number is ready (the DRDY bit is ‘1’ in the \nRNG_SR register). The contents of the RNG_DR register can then be read.\nAs required by the FIPS PUB (Federal Information Processing Standard Publication) 140-2, \nthe first random number generated after setting the RNGEN bit should not be used, but \nsaved for comparison with the next generated random number. Each subsequent generated \nrandom number has to be compared with the previously generated number. The test fails if \nany two compared numbers are equal (continuous random number generator test).\n24.3.2 \nError management\nIf the CEIS bit is read as ‘1’ (clock error)\nIn the case of a clock, the RNG is no more able to generate random numbers because the \nRNG_CLK clock is not correct. Check that the clock controller is correctly configured to \nprovide the RNG clock and clear the CEIS bit. The RNG can work when the CECS bit is ‘0’. \nThe clock error has no impact on the previously generated random numbers, and the \nRNG_DR register contents can be used.\nIf the SEIS bit is read as ‘1’ (seed error)\nIn the case of a seed error, the generation of random numbers is interrupted for as long as \nthe SECS bit is ‘1’. If a number is available in the RNG_DR register, it must not be used \nbecause it may not have enough entropy.\nWhat you should do is clear the SEIS bit, then clear and set the RNGEN bit to reinitialize \nand restart the RNG.\n24.4 \nRNG registers\nThe RNG is associated with a control register, a data register and a status register. They \nhave to be accessed by words (32 bits).\n" }, { "page_number": 772, "page_indices": { "start_index": 1500219, "end_index": 1501950 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 772 }, "toc_details": [ [ 1, "24 Random number generator (RNG)", 770 ], [ 2, "24.4 RNG registers", 771 ], [ 3, "24.4.1 RNG control register (RNG_CR)", 772 ], [ 3, "24.4.2 RNG status register (RNG_SR)", 772 ] ], "page_content": "Random number generator (RNG)\nRM0090\n772/1757\nRM0090 Rev 21\n24.4.1 \nRNG control register (RNG_CR)\nAddress offset: 0x00\nReset value: 0x0000 0000\n \n \n24.4.2 \nRNG status register (RNG_SR)\nAddress offset: 0x04\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nIE\nRNGEN\nReserved\nrw\nrw\nBits 31:4 Reserved, must be kept at reset value\nBit 3 IE: Interrupt enable\n0: RNG Interrupt is disabled\n1: RNG Interrupt is enabled. An interrupt is pending as soon as DRDY=1 or SEIS=1 or \nCEIS=1 in the RNG_SR register.\nBit 2 RNGEN: Random number generator enable\n0: Random number generator is disabled\n1: random Number Generator is enabled.\nBits 1:0 Reserved, must be kept at reset value\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSEIS\nCEIS\nReserved\nSECS\nCECS\nDRDY\nrc_w0\nrc_w0\nr\nr\nr\nBits 31:3 Reserved, must be kept at reset value\nBit 6 SEIS: Seed error interrupt status\nThis bit is set at the same time as SECS, it is cleared by writing it to 0.\n0: No faulty sequence detected\n1: One of the following faulty sequences has been detected:\n–\nMore than 64 consecutive bits at the same value (0 or 1)\n–\nMore than 32 consecutive alternances of 0 and 1 (0101010101...01)\nAn interrupt is pending if IE = 1 in the RNG_CR register.\nBit 5 CEIS: Clock error interrupt status\nThis bit is set at the same time as CECS, it is cleared by writing it to 0.\n0: The RNG_CLK clock was correctly detected\n1: The RNG_CLK was not correctly detected (fRNG_CLK< fHCLK/16)\nAn interrupt is pending if IE = 1 in the RNG_CR register.\nBits 4:3 Reserved, must be kept at reset value\n" }, { "page_number": 773, "page_indices": { "start_index": 1501950, "end_index": 1503594 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 773 }, "toc_details": [ [ 1, "24 Random number generator (RNG)", 770 ], [ 2, "24.4 RNG registers", 771 ], [ 3, "24.4.3 RNG data register (RNG_DR)", 773 ] ], "page_content": "RM0090 Rev 21\n773/1757\nRM0090\nRandom number generator (RNG)\n774\n24.4.3 \nRNG data register (RNG_DR)\nAddress offset: 0x08\nReset value: 0x0000 0000\nThe RNG_DR register is a read-only register that delivers a 32-bit random value when read. \nAfter being read, this register delivers a new random value after a maximum time of 40 \nperiods of the RNG_CLK clock. The software must check that the DRDY bit is set before \nreading the RNDATA value.\n \n \nBit 2 SECS: Seed error current status\n0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a \nfaulty sequence was detected and the situation has been recovered.\n1: One of the following faulty sequences has been detected:\n–\nMore than 64 consecutive bits at the same value (0 or 1)\n–\nMore than 32 consecutive alternances of 0 and 1 (0101010101...01)\nBit 1 CECS: Clock error current status\n0: The RNG_CLK clock has been correctly detected. If the CEIS bit is set, this means that a \nclock error was detected and the situation has been recovered\n1: The RNG_CLK was not correctly detected (fRNG_CLK< fHCLK/16).\nBit 0 DRDY: Data ready\n0: The RNG_DR register is not yet valid, no random data is available\n1: The RNG_DR register contains valid random data\nNote: An interrupt is pending if IE = 1 in the RNG_CR register.\nOnce the RNG_DR register has been read, this bit returns to 0 until a new valid value is \ncomputed.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nRNDATA\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRNDATA\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 RNDATA: Random data\n32-bit random data.\n" }, { "page_number": 774, "page_indices": { "start_index": 1503594, "end_index": 1504091 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 774 }, "toc_details": [ [ 1, "24 Random number generator (RNG)", 770 ], [ 2, "24.4 RNG registers", 771 ], [ 3, "24.4.4 RNG register map", 774 ] ], "page_content": "Random number generator (RNG)\nRM0090\n774/1757\nRM0090 Rev 21\n24.4.4 \nRNG register map\nTable 117 gives the RNG register map and reset values.\n \nTable 117. RNG register map and reset map\nOffset\nRegister \nname\nreset value\nRegister size\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nRNG_CR\n0x0000000\nReserved\nIE\nRNGEN\nReserved\n0x04\nRNG_SR\n0x0000000\nReserved\nSEIS\nCEIS\nReserved\nSECS\nCECS\nDRDY\n0x08\nRNG_DR\n0x0000000\nRNDATA[31:0]\n" }, { "page_number": 775, "page_indices": { "start_index": 1504091, "end_index": 1506778 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 775 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.1 HASH introduction", 775 ], [ 2, "25.2 HASH main features", 775 ] ], "page_content": "RM0090 Rev 21\n775/1757\nRM0090\nHash processor (HASH)\n800\n25 \nHash processor (HASH)\nThis section applies to STM32F415/417xx and STM32F43xxx devices.\n25.1 \nHASH introduction\nThe hash processor is a fully compliant implementation of the secure hash algorithm \n(SHA-1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and \nthe HMAC (keyed-hash message authentication code) algorithm suitable for a variety of \napplications. It computes a message digest (160 bits for the SHA-1 algorithm, 256 bits for \nthe SHA-256 algorithm and 224 bits for the SHA-224 algorithm,128 bits for the MD5 \nalgorithm) for messages of up to (264 – 1) bits, while HMAC algorithms provide a way of \nauthenticating messages by means of hash functions. HMAC algorithms consist in calling \nthe SHA-1, SHA-224, SHA-256 or MD5 hash function twice.\n25.2 \nHASH main features\n•\nSuitable for data authentication applications, compliant with:\n–\nFIPS PUB 180-2 (Federal Information Processing Standards Publication 180-2)\n–\nSecure Hash Standard specifications (SHA-1, SHA-224 and SHA-256) \n–\nIETF RFC 1321 (Internet Engineering Task Force Request For Comments number \n1321) specifications (MD5)\n•\nFast computation of SHA-1, SHA-224 and SHA-256, and MD5 (SHA-224 and SHA-256 \nare available on STM32F43xxx only)\n•\nAHB slave peripheral\n•\n32-bit data words for input data, supporting word, half-word, byte and bit bit-string \nrepresentations, with little-endian data representation only.\n•\nAutomatic swapping to comply with the big-endian SHA1, SHA-224 and SHA-256 \ncomputation standard with little-endian input bit-string representation\n•\nAutomatic padding to complete the input bit string to fit modulo 512 (16 × 32 bits) \nmessage digest computing\n•\n5× 32-bit words (H0 to H5) on STM32F415/417xx and 8 × 32-bit words (H0 to H7) on \nSTM32F43xxx for output message digest, reload able to continue interrupted message \ndigest computation.\n•\nCorresponding 32-bit words of the digest from consecutive message blocks are added \nto each other to form the digest of the whole message\n•\nAutomatic data flow control with support for direct memory access (DMA)\nNote:\nPadding, as defined in the SHA-1, SHA-224 and SHA-256 algorithm, consists in adding a bit \nat bx1 followed by N bits at bx0 to get a total length congruent to 448 modulo 512. After this, \nthe message is completed with a 64-bit integer which is the binary representation of the \noriginal message length.\nFor this hash processor, the quanta for entering the message is a 32-bit word, so an \nadditional information must be provided at the end of the message entry, which is the \nnumber of valid bits in the last 32-bit word entered.\n" }, { "page_number": 776, "page_indices": { "start_index": 1506778, "end_index": 1507426 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 776 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.3 HASH functional description", 776 ] ], "page_content": "Hash processor (HASH)\nRM0090\n776/1757\nRM0090 Rev 21\n25.3 \nHASH functional description\nFigure 1 shows the block diagram of the hash processor.\nFigure 233. Block diagram for STM32F415/417xx\n32-bit AHB2 bus\nHash / HMAC\nSHA-1 / MD5\nHASH_DIN\nswa ppin g\n16 × 32-bit\nIN FIFO\nHASH_CR\nHASH_H0...H4\nHASH_CSR0..50\ncontext\ndigest\nHASH_IMR\nHASH_SR\nInterrupt registers\nControl register\nContext swapping\nMessage digest\nprocessor core\nHASH_ST R\nStart register\nIN FIFO full\nwrite into HASH_DIN\nControl and status\nregisters\nData\nregister\nor write DCAL bit to 1\nor 1 complete block\nor DCAL written to 1\nIN buffer\ntransferred by the DMA\nai16081\n" }, { "page_number": 777, "page_indices": { "start_index": 1507426, "end_index": 1509825 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 777 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.3 HASH functional description", 776 ] ], "page_content": "RM0090 Rev 21\n777/1757\nRM0090\nHash processor (HASH)\n800\nFigure 234. Block diagram for STM32F43xxx\nThe FIPS PUB 180-2 standard and the IETF RFC 1321 publication specify the SHA-1, SHA-\n224 and SHA-256 and MD5 secure hash algorithms, respectively, for computing a \ncondensed representation of a message or data file. When a message of any length below \n264 bits is provided on input, the SHA-1, SHA-224 and SHA-256 and MD5 produce \nrespective a 160-bit, 224 bit, 256 bit and 128-bit output string, respectively, called a \nmessage digest. The message digest can then be processed with a digital signature \nalgorithm in order to generate or verify the signature for the message. Signing the message \ndigest rather than the message often improves the efficiency of the process because the \nmessage digest is usually much smaller in size than the message. The verifier of a digital \nsignature has to use the same hash algorithm as the one used by the creator of the digital \nsignature.\nThe SHA-1, SHA-224 and SHA-256 and MD5 are qualified as “secure” because it is \ncomputationally infeasible to find a message that corresponds to a given message digest, or \nto find two different messages that produce the same message digest. Any change to a \nmessage in transit, with very high probability, results in a different message digest, and the \nsignature fails to verify. For more detail on the SHA-1 or SHA-224 and SHA-256 algorithm, \nplease refer to the FIPS PUB 180-2 (Federal Information Processing Standards Publication \n180-2), 2002 august 1.\nThe current implementation of this standard works with little-endian input data convention. \nFor example, the C string “abc” must be represented in memory as the 24-bit hexadecimal \nvalue 0x434241.\nA message or data file to be processed by the hash processor should be considered a bit \nstring. The length of the message is the number of bits in the message (the empty message \n32-bit AHB2 bus\nHash / HMAC\nSHA-1, SHA-224, SHA-256 and MD5\nHASH_DIN\nswa ppin g\n16 × 32-bit\nIN FIFO\nHASH_CR\nHASH_H0...H7\nHASH_CSR0..53\ncontext\ndigest\nHASH_IMR\nHASH_SR\nInterrupt registers\nControl register\nContext swapping\nMessage digest\nprocessor core\nHASH_ST R\nStart register\nIN FIFO full\nwrite into HASH_DIN\nControl and status\nregisters\nData\nregister\nor write DCAL bit to 1\nor 1 complete block\nor DCAL written to 1\nIN buffer\ntransferred by the DMA\nMS30442V1\n" }, { "page_number": 778, "page_indices": { "start_index": 1509825, "end_index": 1511835 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 778 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.3 HASH functional description", 776 ], [ 3, "25.3.1 Duration of the processing", 778 ], [ 3, "25.3.2 Data type", 778 ] ], "page_content": "Hash processor (HASH)\nRM0090\n778/1757\nRM0090 Rev 21\nhas length 0). You can consider that 32 bits of this bit string forms a 32-bit word. Note that \nthe FIPS PUB 180-1 standard uses the convention that bit strings grow from left to right, and \nbits can be grouped as bytes (8 bits) or words (32 bits) (but some implementations also use \nhalf-words (16 bits), and implicitly, uses the big-endian byte (half-word) ordering. This \nconvention is mainly important for padding (see Section 1.3.4: Message padding on \npage 12).\n25.3.1 \nDuration of the processing\nThe computation of an intermediate block of a message takes:\n•\n66 HCLK clock cycles in SHA-1\n•\n50 HCLK clock cycles in SHA-224\n•\n50 HCLK clock cycles in SHA-256\n•\n50 HCLK clock cycles in MD5\nto which you must add the time needed to load the 16 words of the block into the processor \n(at least 16 clock cycles for a 512-bit block).\nThe time needed to process the last block of a message (or of a key in HMAC) can be \nlonger. This time depends on the length of the last block and the size of the key (in HMAC \nmode). Compared to the processing of an intermediate block, it can be increased by a factor \nof:\n•\n1 to 2.5 for a hash message\n•\naround 2.5 for an HMAC input-key\n•\n1 to 2.5 for an HMAC message\n•\naround 2.5 for an HMAC output key in case of a short key\n•\n3.5 to 5 for an HMAC output key in case of a long key\n25.3.2 \nData type\nData are entered into the hash processor 32 bits (word) at a time, by writing them into the \nHASH_DIN register. But the original bit-string can be organized in bytes, half-words or \nwords, or even be represented as bits. As the system memory organization is little-endian \nand SHA1, SHA-224 and SHA-256 computation is big-endian, depending on the way the \noriginal bit string is grouped, a bit, byte, or half-word swapping operation is performed \nautomatically by the hash processor.\nThe kind of data to be processed is configured with the DATATYPE bitfield in the HASH \ncontrol register (HASH_CR).\n" }, { "page_number": 779, "page_indices": { "start_index": 1511835, "end_index": 1513475 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 779 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.3 HASH functional description", 776 ], [ 3, "25.3.2 Data type", 778 ] ], "page_content": "RM0090 Rev 21\n779/1757\nRM0090\nHash processor (HASH)\n800\nFigure 235. Bit, byte and half-word swapping\nB y t e 3\nB y t e 2\nB y t e 1\nB y t e 0\nbi t s 7 . . . 0\nb i t s 7 .. . 0\nb i t s 7 .. . 0\nbi t s 7 . . . 0\nH A S H_D I N\nbit string organization in\nbi t 0 bi t 1\n bi t 2 9 b i t 3 0 b i t 3 1\nBit s w a p pi n g ope r a t i o n\nb i t- s tr i n g g r o ws\ni n t hi s di rect io n\nas d e f i n e d b y\nFIPS PUB 1 80 - 2 s t d .\nbi t 0\nbi t 1\nbi t 2\nbi t 3 0\nb i t 3 1\nH A S H_D I N\nB y t e s w a p ping ope r a t i o n\nb i t- s tr i n g g r o ws\ni n t hi s di rect io n\nas d e f i n e d b y\nFIPS PUB 1 80 - 2 s t d .\nB y t e 0\nB y t e 1\nB y t e 2\nB y t e 3\nbi t s 7 . . . 0\nb i t s 7 .. . 0\nb i t s 7 .. . 0\nbi t s 7 . . . 0\nHA S H_ D I N\nH a l f - w o r d s w a pping o p er a t io n\nb i t-str in g g r o ws\ni n t h is d i rect i o n\na s d e fi n e d b y\nF I PS PUB 18 0 - 2 s t d .\nHalf-wo r d 0\nbi t s 15 . . . 0\nD A T A TYPE = bx 1 1\nD A T A T YPE = bx 10\nD A T A T YPE = bx 01\nHalf-wo r d 1\nbi t s 15 . . . 0\nHalf-wor d 0\nbi t s 15 .. . 0\nHalf-wor d 1\nbi t s 15 .. . 0\n“1” “0s”\np ad d ing is perfo r m ed\non this side of the\nbit s t ri n g.\nai16082b\nHash processor: Big-Endian\nBits entred with little-Endian format\nA-In case of binary data hash, all bits should be swapped as below \nB-In case of byte data hash, all bytes should be swapped as below \nC-In case of half-word hash, all half-word should be swapped as below \nBytes entred with little-Endian format\nBit string organization in\nHash processor: Big-Endian\nhalf word entred with little-Endian format\nBit string organization in\nHash processor: Big-Endian\n" }, { "page_number": 780, "page_indices": { "start_index": 1513475, "end_index": 1516856 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 780 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.3 HASH functional description", 776 ], [ 3, "25.3.3 Message digest computing", 780 ] ], "page_content": "Hash processor (HASH)\nRM0090\n780/1757\nRM0090 Rev 21\nThe least significant bit of the message has to be at position 0 (right) in the first word \nentered into the hash processor, the 32nd bit of the bit string has to be at position 0 in the \nsecond word entered into the hash processor and so on.\n25.3.3 \nMessage digest computing\nThe HASH sequentially processes blocks of 512 bits when computing the message digest. \nThus, each time 16 × 32-bit words (= 512 bits) have been written by the DMA or the CPU, \ninto the hash processor, the HASH automatically starts computing the message digest. This \noperation is known as a partial digest computation.\nThe message to be processed is entered into the peripheral by 32-bit words written into the \nHASH_DIN register. The current contents of the HASH_DIN register are transferred to the \ninput FIFO (IN FIFO) each time the register is written with new data. HASH_DIN and the \ninput FIFO form a FIFO of a 17-word length (named the IN buffer).\nThe processing of a block can start only once the last value of the block has entered the IN \nFIFO. The peripheral must get the information as to whether the HASH_DIN register \ncontains the last bits of the message or not. Two cases may occur:\n•\nWhen the DMA is not used:\n–\nIn case of a partial digest computation, this is done by writing an additional word \ninto the HASH_DIN register (actually the first word of the next block). Then the \nsoftware must wait until the processor is ready again (when DINIS=1) before \nwriting new data into HASH_DIN.\n–\nIn case of a final digest computation (last block entered), this is done by writing the \nDCAL bit to 1.\n•\nWhen the DMA is used:\nThe contents of the HASH_DIN register are interpreted automatically with the \ninformation sent by the DMA controller.\n–\nIn case of a single DMA transfer: Multiple DMA transfer (MDMAT) bit should be \ncleared on STM32F43xxx. When the last block has been transferred to the \nHASH_DIN register via DMA channel, DCAL bit is set to automatically to 1 in the \nHASH_STR register in order to launch the final digest calculation.\n–\nIn case of a multiple DMA transfer (available only on STM32F43xxx): Multiple \nDMA transfer (MDMAT) bit should be set to 1 by software so DCAL bit does not \nget set automatically by HW, in this case the final digest calculation for hash and \nfor each phases for HMAC (for more details about HMAC phases please refer to \nHMAC operation section) is not launched a the end of the DMA transfer request, \nallowing the processor to receive a new DMA transfer. During the last DMA \ntransfer, Multiple DMA transfer (MDMAT) bit should be cleared by software in \norder to set automatically DCAL bit at the end of the last bloc and lunch the final \ndigest.\n–\nThe contents of the HASH_DIN register are interpreted automatically with the \ninformation sent by the DMA controller.\nThis process —data entering + partial digest computation— continues until the last bits of \nthe original message are written to the HASH_DIN register. As the length (number of bits) of \na message can be any integer value, the last word written into the HASH processor may \nhave a valid number of bits between 1 and 32. This number of valid bits in the last word, \nNBLW, has to be written into the HASH_STR register, so that message padding is correctly \nperformed before the final message digest computation.\n" }, { "page_number": 781, "page_indices": { "start_index": 1516856, "end_index": 1519758 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 781 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.3 HASH functional description", 776 ], [ 3, "25.3.4 Message padding", 781 ] ], "page_content": "RM0090 Rev 21\n781/1757\nRM0090\nHash processor (HASH)\n800\nOnce this is done, writing into HASH_STR with bit DCAL = 1 starts the processing of the last \nentered block of message by the hash processor. This processing consists in:\n•\nAutomatically performing the message padding operation: the purpose of this operation \nis to make the total length of a padded message a multiple of 512. The HASH \nsequentially processes blocks of 512 bits when computing the message digest\n•\nComputing the final message digest\nWhen the DMA is enabled, it provides the information to the hash processor when it is \ntransferring the last data word. Then the padding and digest computation are performed \nautomatically as if DCAL had been written to 1.\n25.3.4 \nMessage padding\nMessage padding consists in appending a “1” followed by m “0”s followed by a 64-bit integer \nto the end of the original message to produce a padded message block of length 512. The \n“1” is added to the last word written into the HASH_DIN register at the bit position defined by \nthe NBLW bitfield, and the remaining upper bits are cleared (“0”s).\nExample: let us assume that the original message is the ASCII binary-coded form of “abc”, \nof length L = 24:\nbyte 0\nbyte 1\nbyte 2\nbyte 3\n01100001 01100010 01100011 UUUUUUUU\n<-- 1st word written to HASH_DIN --> \nNBLW has to be loaded with the value 24: a “1” is appended at bit location 24 in the bit string \n(starting counting from left to right in the above bit string), which corresponds to bit 31 in the \nHASH_DIN register (little-endian convention):\n01100001 01100010 01100011 1UUUUUUU\nSince L = 24, the number of bits in the above bit string is 25, and 423 “0”s are appended, \nmaking now 448. This gives (in hexadecimal, big-endian format):\n61626380 00000000 00000000 00000000\n00000000 00000000 00000000 00000000\n00000000 00000000 00000000 00000000\n00000000 00000000\nThe L value, in two-word representation (that is 00000000 00000018) is appended. Hence \nthe final padded message in hexadecimal:\n61626380 00000000 00000000 00000000\n00000000 00000000 00000000 00000000\n00000000 00000000 00000000 00000000\n00000000 00000000 00000000 00000028\nIf the HASH is programmed to use the little-endian byte input format, the above message \nhas to be entered by doing the following steps:\n1.\n0xUU636261 is written into the HASH_DIN register (where ‘U’ means don’t care)\n2. \n0x18 is written into the HASH_STR register (the number of valid bits in the last word \nwritten into the HASH_DIN register is 24, as the original message length is 24 bits)\n3. \n0x10 is written into the HASH_STR register to start the message padding and digest \ncomputation. When NBLW ≠ 0x00, the message padding puts a “1” into the HASH_DIN \nregister at the bit position defined by the NBLW value, and inserts “0”s at bit locations \n[31:(NBLW+1)]. When NBLW == 0x00, the message padding inserts one new word with \n" }, { "page_number": 782, "page_indices": { "start_index": 1519758, "end_index": 1522414 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 782 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.3 HASH functional description", 776 ], [ 3, "25.3.5 Hash operation", 782 ], [ 3, "25.3.6 HMAC operation", 782 ] ], "page_content": "Hash processor (HASH)\nRM0090\n782/1757\nRM0090 Rev 21\nvalue 0x0000 0001. Then an all zero word (0x0000 0000) is added and the message \nlength in a two-word representation, to get a block of 16 x 32-bit words.\n4. \nThe HASH computing is performed, and the message digest is then available in the \nHASH_Hx registers (x = 0...4) for the SHA-1 algorithm. For example:\nH0 = 0xA9993E36\nH1 = 0x4706816A\nH2 = 0xBA3E2571\nH3 = 0x7850C26C\nH4 = 0x9CD0D89D\n25.3.5 \nHash operation\nThe hash function (SHA-1, SHA-224, SHA-256 and MD5) is selected when the INIT bit is \nwritten to ‘1’ in the HASH_CR register while the MODE bit is at ‘0’ in HASH_CR. The \nalgorithm (SHA-1, SHA-224,SHA-256 or MD5) is selected at the same time (that is when the \nINIT bit is set) using the ALGO bits.\nThe message can then be sent by writing it word by word into the HASH_DIN register. When \na block of 512 bits —that is 16 words— has been written, a partial digest computation starts \nupon writing the first data of the next block. The hash processor remains busy for 66 cycles \nfor the SHA-1 algorithm, or 50 cycles for the MD5 algorithm, SHA-224 algorithm and SHA-\n256 algorithm.\nThe process can then be repeated until the last word of the message. If DMA transfers are \nused, refer to the Procedure where the data are loaded by DMA section. Otherwise, if the \nmessage length is not an exact multiple of 512 bits, then the HASH_STR register has to be \nwritten to launch the computation of the final digest.\nOnce computed, the digest can be read from the HASH_H0...HASH_H4 registers (for the \nMD5 algorithm, HASH_H4 is not relevant) on STM32F415/417xx, and from the \nHASH_H0...HASH_H7 registers on STM32F43xxx where:\nHASH_H4..HASH_H7 are not relevant when the MD5 algorithm is selected,\nHASH_H5.. HASH_H7 are not relevant when the SHA-1algorithm is selected,\nHASH_H7 is not relevant when the SHA-224 algorithm is selected.\n25.3.6 \nHMAC operation\nThe HMAC algorithm is used for message authentication, by irreversibly binding the \nmessage being processed to a key chosen by the user. For HMAC specifications, refer to \n“HMAC: keyed-hashing for message authentication, H. Krawczyk, M. Bellare, R. Canetti, \nFebruary 1997.\nBasically, the algorithm consists of two nested hash operations:\nHMAC(message) = Hash[((key | pad) XOR 0x5C) \n| Hash(((key | pad) XOR 0x36) | message)]\nwhere:\n•\npad is a sequence of zeroes needed to extend the key to the length of the underlying \nhash function data block (that is 512 bits for both the SHA-1, SHA224, SHA-256 and \nMD5 hash algorithms)\n•\n| represents the concatenation operator\nTo compute the HMAC, four different phases are required:\n" }, { "page_number": 783, "page_indices": { "start_index": 1522414, "end_index": 1524462 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 783 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.3 HASH functional description", 776 ], [ 3, "25.3.7 Context swapping", 783 ] ], "page_content": "RM0090 Rev 21\n783/1757\nRM0090\nHash processor (HASH)\n800\n1.\nThe block is initialized by writing the INIT bit to ‘1’ with the MODE bit at ‘1’ and the \nALGO bits set to the value corresponding to the desired algorithm. The LKEY bit must \nalso be set during this phase if the key being used is longer than 64 bytes (in this case, \nthe HMAC specifications specify that the hash of the key should be used in place of the \nreal key).\n2. \nThe key (to be used for the inner hash function) is then given to the core. This \noperation follows the same mechanism as the one used to send the message in the \nhash operation (that is, by writing into HASH_DIN and, finally, into HASH_STR).\n3. \nOnce the last word has been entered and computation has started, the hash processor \nelaborates the key. It is then ready to accept the message text using the same \nmechanism as the one used to send the message in the hash operation.\n4. \nAfter the first hash round, the hash processor returns “ready” to indicate that it is ready \nto receive the key to be used for the outer hash function (normally, this key is the same \nas the one used for the inner hash function). When the last word of the key is entered \nand computation starts, the HMAC result is made available in the \nHASH_H0...HASH_H4 registers on STM32F415/417xx and on HASH_H0...HASH_H7 \nregisters on STM32F43xxx. \nNote:\n1\nThe computation latency of the HMAC primitive depends on the lengths of the keys and \nmessage. You could the HMAC as two nested underlying hash functions with the same key \nlength (long or short).\n25.3.7 \nContext swapping\nIt is possible to interrupt a hash/HMAC process to perform another processing with a higher \npriority, and to complete the interrupted process later on, when the higher-priority task is \ncomplete. To do so, the context of the interrupted task must be saved from the hash \nregisters to memory, and then be restored from memory to the hash registers.\nThe procedures where the data flow is controlled by software or by DMA are described \nbelow.\n" }, { "page_number": 784, "page_indices": { "start_index": 1524462, "end_index": 1527019 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 784 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.3 HASH functional description", 776 ], [ 3, "25.3.7 Context swapping", 783 ], [ 4, "Procedure where the data are loaded by software", 784 ], [ 4, "Procedure where the data are loaded by DMA", 784 ] ], "page_content": "Hash processor (HASH)\nRM0090\n784/1757\nRM0090 Rev 21\nProcedure where the data are loaded by software\nThe context can be saved only when no block is currently being processed. That is, you \nmust wait for DINIS = 1 (the last block has been processed and the input FIFO is empty) or \nNBW ≠0 (the FIFO is not full and no processing is ongoing).\n•\nContext saving:\nStore the contents of the following registers into memory:\n–\nHASH_IMR\n–\nHASH_STR\n–\nHASH_CR\n–\nHASH_CSR0 to HASH_CSR50 on STM32F415/417xx, and HASH_CSR0 to \nHASH_CSR53 on STM32F43xxx.\n•\nContext restoring:\nThe context can be restored when the high-priority task is complete. Please follow the \norder of the sequence below.\na) \nWrite the following registers with the values saved in memory: HASH_IMR, \nHASH_STR and HASH_CR\nb) \nInitialize the hash processor by setting the INIT bit in the HASH_CR register\nc) \nWrite the HASH_CSR0 to HASH_CSR50 (STM32F415/417xx), and HASH_CSR0 \nto HASH_CSR53 (STM32F43xxx) registers with the values saved in memory\nYou can now restart the processing from the point where it has been interrupted.\nProcedure where the data are loaded by DMA\nIn this case it is not possible to predict if a DMA transfer is in progress or if the process is \nongoing. Thus, you must stop the DMA transfers, then wait until the HASH is ready in order \nto interrupt the processing of a message.\n•\nInterrupting a processing:\n–\nClear the DMAE bit to disable the DMA interface\n–\nWait until the current DMA transfer is complete (wait for DMAES = 0 in the \nHASH_SR register). Note that the block may or not have been totally transferred \nto the HASH.\n–\nDisable the corresponding channel in the DMA controller\n–\nWait until the hash processor is ready (no block is being processed), that is wait \nfor DINIS = 1\n•\nThe context saving and context restoring phases are the same as above (see \nProcedure where the data are loaded by software).\nReconfigure the DMA controller so that it transfers the end of the message. You can now \nrestart the processing from the point where it was interrupted by setting the DMAE bit.\nNote:\nIf context swapping does not involve HMAC operations, the HASH_CSR38 to \nHASH_CSR50 (STM32F415/417xx) and HASH_CSR38 to HASH_CSR53 (STM32F43xxx) \nregisters do not have to be saved and restored.\nIf context swapping occurs between two blocks (the last block was completely processed \nand the next block has not yet been pushed into the IN FIFO, NBW = 000 in the HASH_CR \nregister), the HASH_CSR22 to HASH_CSR37 registers do not have to be saved and \nrestored.\n" }, { "page_number": 785, "page_indices": { "start_index": 1527019, "end_index": 1528555 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 785 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.3 HASH functional description", 776 ], [ 3, "25.3.8 HASH interrupt", 785 ], [ 2, "25.4 HASH registers", 785 ], [ 3, "25.4.1 HASH control register (HASH_CR) for STM32F415/417xx", 785 ] ], "page_content": "RM0090 Rev 21\n785/1757\nRM0090\nHash processor (HASH)\n800\n25.3.8 \nHASH interrupt\nThere are two individual maskable interrupt sources generated by the HASH processor. \nThey are connected to the same interrupt vector.\nYou can enable or disable the interrupt sources individually by changing the mask bits in the \nHASH_IMR register. Setting the appropriate mask bit to 1 enables the interrupt.\nThe status of the individual interrupt sources can be read from the HASH_SR register.\nFigure 236. HASH interrupt mapping diagram\n25.4 \nHASH registers\nThe HASH core is associated with several control and status registers and five message \ndigest registers.\nAll these registers are accessible through word accesses only, else an AHB error is \ngenerated.\n25.4.1 \nHASH control register (HASH_CR) for STM32F415/417xx\nAddress offset: 0x00\nReset value: 0x0000 0000\n \n \nDCIS\nDCIM\nDINIS\nDINIM\nHASH interrupt to NVIC\nai16086\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nLKEY\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDINNE\nNBW\nALGO[0]\nMODE\nDATATYPE\nDMAE\nINIT\nReserved\nr\nr\nr\nr\nr\nrw\nrw\nrw\nrw\nrw\nw\nBits 31:17 Reserved, forced by hardware to 0.\nBit 16 LKEY: Long key selection\nThis bit selects between short key (≤ 64 bytes) or long key (> 64 bytes) in HMAC \nmode\n0: Short key (≤ 64 bytes)\n1: Long key (> 64 bytes)\nNote: This selection is only taken into account when the INIT bit is set and MODE \n= 1. Changing this bit during a computation has no effect.\nBits 15:13 Reserved, forced by hardware to 0.\n" }, { "page_number": 786, "page_indices": { "start_index": 1528555, "end_index": 1531277 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 786 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.4 HASH registers", 785 ], [ 3, "25.4.1 HASH control register (HASH_CR) for STM32F415/417xx", 785 ] ], "page_content": "Hash processor (HASH)\nRM0090\n786/1757\nRM0090 Rev 21\nBit 12 DINNE: DIN not empty\nThis bit is set when the HASH_DIN register holds valid data (that is after being \nwritten at least once). It is cleared when either the INIT bit (initialization) or the \nDCAL bit (completion of the previous message processing) is written to 1.\n0: No data are present in the data input buffer\n1: The input buffer contains at least one word of data\nBits 11:8 NBW: Number of words already pushed\nThis bitfield reflects the number of words in the message that have already been \npushed into the IN FIFO.\nNBW increments (+1) when a write access is performed to the HASH_DIN \nregister while DINNE = 1.\nIt goes to 0000 when the INIT bit is written to 1 or when a digest calculation \nstarts (DCAL written to 1 or DMA end of transfer).\n″\nIf the DMA is not used:\n0000 and DINNE=0: no word has been pushed into the DIN buffer (the buffer is \nempty, both the HASH_DIN register and the IN FIFO are empty)\n0000 and DINNE=1: 1 word has been pushed into the DIN buffer (The \nHASH_DIN register contains 1 word, the IN FIFO is empty)\n0001: 2 words have been pushed into the DIN buffer (the HASH_DIN register \nand the IN FIFO contain 1 word each)\n...\n1111: 16 words have been pushed into the DIN buffer\n″\nIf the DMA is used, NBW is the exact number of words that have been \npushed into the IN FIFO.\nBit 7 ALGO[1:0]: Algorithm selection\nThese bits selects the SHA-1 or the MD5 algorithm:\n0: SHA-1 algorithm selected\n1: MD5 algorithm selected\nNote: This selection is only taken into account when the INIT bit is set. Changing \nthis bit during a computation has no effect.\nBit 6 MODE: Mode selection\nThis bit selects the HASH or HMAC mode for the selected algorithm:\n0: Hash mode selected\n1: HMAC mode selected. LKEY must be set if the key being used is longer than \n64 bytes.\nNote: This selection is only taken into account when the INIT bit is set. Changing \nthis bit during a computation has no effect.\nBits 5:4 DATATYPE: Data type selection\nDefines the format of the data entered into the HASH_DIN register:\n00: 32-bit data. The data written into HASH_DIN are directly used by the HASH \nprocessing, without reordering.\n01: 16-bit data, or half-word. The data written into HASH_DIN are considered as \n2 half-words, and are swapped before being used by the HASH processing.\n10: 8-bit data, or bytes. The data written into HASH_DIN are considered as 4 \nbytes, and are swapped before being used by the HASH processing.\n11: bit data, or bit-string. The data written into HASH_DIN are considered as 32 \nbits (1st bit of the sting at position 0), and are swapped before being used by the \nHASH processing (1st bit of the string at position 31).\n" }, { "page_number": 787, "page_indices": { "start_index": 1531277, "end_index": 1532260 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 787 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.4 HASH registers", 785 ], [ 3, "25.4.1 HASH control register (HASH_CR) for STM32F415/417xx", 785 ] ], "page_content": "RM0090 Rev 21\n787/1757\nRM0090\nHash processor (HASH)\n800\nBit 3 DMAE: DMA enable\n0: DMA transfers disabled\n1: DMA transfers enabled. A DMA request is sent as soon as the HASH core is \nready to receive data.\nNote: 1: This bit is cleared by hardware when the DMA asserts the DMA terminal \ncount signal (while transferring the last data of the message). This bit is not \ncleared when the INIT bit is written to 1.\n2: If this bit is written to 0 while a DMA transfer has already been requested \nto the DMA, DMAE is cleared but the current transfer is not aborted. \nInstead, the DMA interface remains internally enabled until the transfer is \ncomplete or INIT is written to 1.\nBit 2 INIT: Initialize message digest calculation\nWriting this bit to 1 resets the hash processor core, so that the HASH is ready to \ncompute the message digest of a new message.\nWriting this bit to 0 has no effect.\nReading this bit always return 0.\nBits 1:0 Reserved, must be kept cleared.\n" }, { "page_number": 788, "page_indices": { "start_index": 1532260, "end_index": 1533738 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 788 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.4 HASH registers", 785 ], [ 3, "25.4.2 HASH control register (HASH_CR) for STM32F43xxx", 788 ] ], "page_content": "Hash processor (HASH)\nRM0090\n788/1757\nRM0090 Rev 21\n25.4.2 \nHASH control register (HASH_CR) for STM32F43xxx\nAddress offset: 0x00\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nALGO[1]\nReserved\nLKEY\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMDMAT\nDINNE\nNBW\nALGO[0]\nMODE\nDATATYPE\nDMAE\nINIT\nReserved\nrw\nr\nr\nr\nr\nr\nrw\nrw\nrw\nrw\nrw\nw\nBits 31:19 Reserved, forced by hardware to 0.\nBit 17 Reserved, forced by hardware to 0.\nBit 16 LKEY: Long key selection\nThis bit selects between short key (≤ 64 bytes) or long key (> 64 bytes) in HMAC \nmode\n0: Short key (≤ 64 bytes)\n1: Long key (> 64 bytes)\nNote: This selection is only taken into account when the INIT bit is set and MODE \n= 1. Changing this bit during a computation has no effect.\nBits 15:14 Reserved, forced by hardware to 0.\nBit 13 MDMAT: Multiple DMA Transfers \nThis bit is set when hashing large files when multiple DMA transfers are needed. \n0: DCAL is automatically set at the end of a DMA transfer.\n1: DCAL is not automatically set at the end of a DMA transfer.\nBit 12 DINNE: DIN not empty\nThis bit is set when the HASH_DIN register holds valid data (that is after being \nwritten at least once). It is cleared when either the INIT bit (initialization) or the \nDCAL bit (completion of the previous message processing) is written to 1.\n0: No data are present in the data input buffer\n1: The input buffer contains at least one word of data\n" }, { "page_number": 789, "page_indices": { "start_index": 1533738, "end_index": 1536179 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 789 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.4 HASH registers", 785 ], [ 3, "25.4.2 HASH control register (HASH_CR) for STM32F43xxx", 788 ] ], "page_content": "RM0090 Rev 21\n789/1757\nRM0090\nHash processor (HASH)\n800\nBits 11:8 NBW: Number of words already pushed\nThis bitfield reflects the number of words in the message that have already been \npushed into the IN FIFO.\nNBW increments (+1) when a write access is performed to the HASH_DIN \nregister while DINNE = 1.\nIt goes to 0000 when the INIT bit is written to 1 or when a digest calculation \nstarts (DCAL written to 1 or DMA end of transfer).\n″\nIf the DMA is not used:\n0000 and DINNE=0: no word has been pushed into the DIN buffer (the buffer is \nempty, both the HASH_DIN register and the IN FIFO are empty)\n0000 and DINNE=1: 1 word has been pushed into the DIN buffer (The \nHASH_DIN register contains 1 word, the IN FIFO is empty)\n0001: 2 words have been pushed into the DIN buffer (the HASH_DIN register \nand the IN FIFO contain 1 word each)\n...\n1111: 16 words have been pushed into the DIN buffer\n″\nIf the DMA is used, NBW is the exact number of words that have been \npushed into the IN FIFO.\nBit 18 and bit 7 ALGO[1:0]: Algorithm selection\nThese bits selects the SHA-1, SHA-224, SHA256 or the MD5 algorithm:\n00: SHA-1 algorithm selected\n01: MD5 algorithm selected\n10: SHA224 algorithm selected\n11: SHA256 algorithm selected\nNote: This selection is only taken into account when the INIT bit is set. Changing \nthis bit during a computation has no effect.\nBit 6 MODE: Mode selection\nThis bit selects the HASH or HMAC mode for the selected algorithm:\n0: Hash mode selected\n1: HMAC mode selected. LKEY must be set if the key being used is longer than \n64 bytes.\nNote: This selection is only taken into account when the INIT bit is set. Changing \nthis bit during a computation has no effect.\nBits 5:4 DATATYPE: Data type selection\nDefines the format of the data entered into the HASH_DIN register:\n00: 32-bit data. The data written into HASH_DIN are directly used by the HASH \nprocessing, without reordering.\n01: 16-bit data, or half-word. The data written into HASH_DIN are considered as \n2 half-words, and are swapped before being used by the HASH processing.\n10: 8-bit data, or bytes. The data written into HASH_DIN are considered as 4 \nbytes, and are swapped before being used by the HASH processing.\n11: bit data, or bit-string. The data written into HASH_DIN are considered as 32 \nbits (1st bit of the sting at position 0), and are swapped before being used by the \nHASH processing (1st bit of the string at position 31).\n" }, { "page_number": 790, "page_indices": { "start_index": 1536179, "end_index": 1537158 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 790 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.4 HASH registers", 785 ], [ 3, "25.4.2 HASH control register (HASH_CR) for STM32F43xxx", 788 ] ], "page_content": "Hash processor (HASH)\nRM0090\n790/1757\nRM0090 Rev 21\nBit 3 DMAE: DMA enable\n0: DMA transfers disabled\n1: DMA transfers enabled. A DMA request is sent as soon as the HASH core is \nready to receive data.\nNote: 1: This bit is cleared by hardware when the DMA asserts the DMA terminal \ncount signal (while transferring the last data of the message). This bit is not \ncleared when the INIT bit is written to 1.\n2: If this bit is written to 0 while a DMA transfer has already been requested \nto the DMA, DMAE is cleared but the current transfer is not aborted. \nInstead, the DMA interface remains internally enabled until the transfer is \ncomplete or INIT is written to 1.\nBit 2 INIT: Initialize message digest calculation\nWriting this bit to 1 resets the hash processor core, so that the HASH is ready to \ncompute the message digest of a new message.\nWriting this bit to 0 has no effect.\nReading this bit always return 0.\nBits 1:0 Reserved, must be kept cleared.\n" }, { "page_number": 791, "page_indices": { "start_index": 1537158, "end_index": 1539044 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 791 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.4 HASH registers", 785 ], [ 3, "25.4.3 HASH data input register (HASH_DIN)", 791 ] ], "page_content": "RM0090 Rev 21\n791/1757\nRM0090\nHash processor (HASH)\n800\n25.4.3 \nHASH data input register (HASH_DIN)\nAddress offset: 0x04\nReset value: 0x0000 0000\nHASH_DIN is the data input register. It is 32-bit wide. It is used to enter the message by \nblocks of 512 bits. When the HASH_DIN register is written to, the value presented on the \nAHB databus is ‘pushed’ into the HASH core and the register takes the new value presented \non the AHB databus. The DATATYPE bits must previously have been configured in the \nHASH_CR register to get a correct message representation.\nWhen a block of 16 words has been written to the HASH_DIN register, an intermediate \ndigest calculation is launched:\n•\nby writing new data into the HASH_DIN register (the first word of the next block) if the \nDMA is not used (intermediate digest calculation)\n•\nautomatically if the DMA is used\nWhen the last block has been written to the HASH_DIN register, the final digest calculation \n(including padding) is launched:\n•\nby writing the DCAL bit to 1 in the HASH_STR register (final digest calculation)\n•\nautomatically if the DMA is used and MDMAT bit is set to ‘0’.\nWhen a digest calculation (intermediate or final) is in progress, any new write access to the \nHASH_DIN register is extended (by wait-state insertion on the AHB bus) until the HASH \ncalculation completes.\nWhen the HASH_DIN register is read, the last word written in this location is accessed (zero \nafter reset).\n .\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATAIN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATAIN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 DATAIN: Data input\nRead = returns the current register content.\nWrite = the current register content is pushed into the IN FIFO, and the register \ntakes the new value presented on the AHB databus.\n" }, { "page_number": 792, "page_indices": { "start_index": 1539044, "end_index": 1541280 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 792 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.4 HASH registers", 785 ], [ 3, "25.4.4 HASH start register (HASH_STR)", 792 ] ], "page_content": "Hash processor (HASH)\nRM0090\n792/1757\nRM0090 Rev 21\n25.4.4 \nHASH start register (HASH_STR)\nAddress offset: 0x08\nReset value: 0x0000 0000\nThe HASH_STR register has two functions:\n•\nIt is used to define the number of valid bits in the last word of the message entered in \nthe hash processor (that is the number of valid least significant bits in the last data \nwritten into the HASH_DIN register)\n•\nIt is used to start the processing of the last block in the message by writing the DCAL \nbit to 1\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDCAL\nReserved\nNBLW\nw\nrw\nrw\nrw\nrw\nrw\nBits 31:9 Reserved, forced by hardware to 0.\nBit 8 DCAL: Digest calculation\nWriting this bit to 1 starts the message padding, using the previously written \nvalue of NBLW, and starts the calculation of the final message digest with all data \nwords written to the IN FIFO since the INIT bit was last written to 1.\nReading this bit returns 0.\nNote \nBits 7:5 Reserved, forced by hardware to 0.\nBits 4:0 NBLW: Number of valid bits in the last word of the message in the bit string \norganization of hash processor \nWhen these bits are written and DCAL is at ‘0’, they take the value on the AHB \ndatabus:\n0x00: All 32 bits of the last data written in the bit string organization of hash \nprocessor (after data swapping) are valid.\n0x01: Only bit [31] of the last data written in the bit string organization of hash \nprocessor (after data swapping) are valid\n0x02: Only bits [31:30] of the last data written in the bit string organization of \nhash processor (after data swapping) are valid\n0x03: Only bits [31:29] of the last data written in the bit string organization of \nhash processor (after data swapping) are valid\n...\n0x1F: Only bits [0] of the last data written in the bit string organization of hash \nprocessor (after data swapping) are valid\nWhen these bits are written and DCAL is at ‘1’, the bitfield is not changed.\nReading them returns the last value written to NBLW.\nNote: These bits must be configured before setting the DCAL bit, else they are not \ntaken into account. Especially, it is not possible to configure NBLW and set \nDCAL at the same time.\n" }, { "page_number": 793, "page_indices": { "start_index": 1541280, "end_index": 1542975 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 793 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.4 HASH registers", 785 ], [ 3, "25.4.5 HASH digest registers (HASH_HR0..4/5/6/7)", 793 ], [ 4, "HASH_HR0", 793 ], [ 4, "HASH_HR1", 793 ], [ 4, "HASH_HR2", 793 ] ], "page_content": "RM0090 Rev 21\n793/1757\nRM0090\nHash processor (HASH)\n800\n25.4.5 \nHASH digest registers (HASH_HR0..4/5/6/7)\nAddress offset: 0x0C to 0x1C (STM32F415/417xx), plus 0x310 to 0x32C (STM32F43xxx)\nReset value: 0x0000 0000\nThese registers contain the message digest result named as:\n1.\nH0, H1, H2, H3 and H4, respectively, in the SHA1 algorithm description\nNote that in this case, the HASH_H5 to HASH_H7 register is not used, and is read as \nzero.\n2. \nA, B, C and D, respectively, in the MD5 algorithm description\nNote that in this case, the HASH_H4 to HASH_H7 register is not used, and is read as \nzero.\n3. \nH0 to H6, respectively, in the SHA224 algorithm description,\nNote that in this case, the HASH_H7 register is not used, and is read as zero.\n4. \nH0 to H7, respectively, in the SHA256 algorithm description,\nIf a read access to one of these registers occurs while the HASH core is calculating an \nintermediate digest or a final message digest (that is when the DCAL bit has been written to \n1), then the read is stalled until the completion of the HASH calculation.\nNote:\nH0, H1, H2, H3 and H4 mapping are duplicated in two region.\nHASH_HR0\nAddress offset: 0x0C and 0x310\n \nHASH_HR1\nAddress offset: 0x10 and 0x314\n \nHASH_HR2\nAddress offset: 0x14 and 0x318\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nH0\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nH0\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nH1\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nH1\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nH2\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n" }, { "page_number": 794, "page_indices": { "start_index": 1542975, "end_index": 1543959 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 794 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.4 HASH registers", 785 ], [ 3, "25.4.5 HASH digest registers (HASH_HR0..4/5/6/7)", 793 ], [ 4, "HASH_HR3", 794 ], [ 4, "HASH_HR4", 794 ], [ 4, "HASH_HR5", 794 ], [ 4, "HASH_HR6", 794 ], [ 4, "HASH_HR7", 794 ] ], "page_content": "Hash processor (HASH)\nRM0090\n794/1757\nRM0090 Rev 21\nHASH_HR3\nAddress offset: 0x18 and 0x31C\n \nHASH_HR4\nAddress offset: 0x1C and 0x320\n \nHASH_HR5\nAddress offset: 0x324\n \nHASH_HR6\nAddress offset: 0x328\n \nHASH_HR7\nAddress offset: 0x32C\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nH2\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nH3\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nH3\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nH4\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nH4\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nH5\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nH5\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nH6\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nH6\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n" }, { "page_number": 795, "page_indices": { "start_index": 1543959, "end_index": 1544892 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 795 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.4 HASH registers", 785 ], [ 3, "25.4.6 HASH interrupt enable register (HASH_IMR)", 795 ] ], "page_content": "RM0090 Rev 21\n795/1757\nRM0090\nHash processor (HASH)\n800\n \nNote:\nWhen starting a digest computation for a new bit stream (by writing the INIT bit to 1), these \nregisters assume their reset values.\n25.4.6 \nHASH interrupt enable register (HASH_IMR)\nAddress offset: 0x20\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nH7\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nH7\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDCIE\nDINIE\nrw\nrw\nBits 31:2 Reserved, forced by hardware to 0.\nBit 1 DCIE: Digest calculation completion interrupt enable\n0: Digest calculation completion interrupt disabled\n1: Digest calculation completion interrupt enabled.\nBit 0 DINIE: Data input interrupt enable\n0: Data input interrupt disabled\n1: Data input interrupt enabled\n" }, { "page_number": 796, "page_indices": { "start_index": 1544892, "end_index": 1546549 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 796 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.4 HASH registers", 785 ], [ 3, "25.4.7 HASH status register (HASH_SR)", 796 ] ], "page_content": "Hash processor (HASH)\nRM0090\n796/1757\nRM0090 Rev 21\n25.4.7 \nHASH status register (HASH_SR)\nAddress offset: 0x24\nReset value: 0x0000 0001\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBUSY\nDMAS\nDCIS\nDINIS\nr\nr\nrc_w0\nrc_w0\nBits 31:4 Reserved, forced by hardware to 0.\nBit 3 BUSY: Busy bit\n0: No block is currently being processed\n1: The hash core is processing a block of data\nBit 2 DMAS: DMA Status\nThis bit provides information on the DMA interface activity. It is set with DMAE \nand cleared when DMAE=0 and no DMA transfer is ongoing. No interrupt is \nassociated with this bit.\n0: DMA interface is disabled (DMAE=0) and no transfer is ongoing\n1: DMA interface is enabled (DMAE=1) or a transfer is ongoing\nBit 1 DCIS: Digest calculation completion interrupt status\nThis bit is set by hardware when a digest becomes ready (the whole message \nhas been processed). It is cleared by writing it to 0 or by writing the INIT bit to 1 \nin the HASH_CR register.\n0: No digest available in the HASH_Hx registers\n1: Digest calculation complete, a digest is available in the HASH_Hx registers. \nAn interrupt is generated if the DCIE bit is set in the HASH_IMR register.\nBit 0 DINIS: Data input interrupt status\nThis bit is set by hardware when the input buffer is ready to get a new block (16 \nlocations are free). It is cleared by writing it to 0 or by writing the HASH_DIN \nregister.\n0: Less than 16 locations are free in the input buffer\n1: A new block can be entered into the input buffer. An interrupt is generated if \nthe DINIE bit is set in the HASH_IMR register.\n" }, { "page_number": 797, "page_indices": { "start_index": 1546549, "end_index": 1547883 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 797 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.4 HASH registers", 785 ], [ 3, "25.4.8 HASH context swap registers (HASH_CSRx)", 797 ], [ 4, "HASH_CSRx", 797 ] ], "page_content": "RM0090 Rev 21\n797/1757\nRM0090\nHash processor (HASH)\n800\n25.4.8 \nHASH context swap registers (HASH_CSRx)\nAddress offset: 0x0F8 to 0x1C0\n•\nFor HASH_CSR0 register: Reset value is 0x0000 0002.\n•\nFor others registers: Reset value is 0x0000 0000 , except for STM32F43xxx devices \nwhere the HASH_CSR2 register reset value is 0x2000 0000\nAdditional registers are available from 0x1C1 to 0x1CC on STM32F43xxx:\n•\nReset value: 0x0000 0000.\nThese registers contain the complete internal register states of the hash processor, and are \nuseful when a context swap has to be done because a high-priority task has to use the hash \nprocessor while it is already in use by another task.\nWhen such an event occurs, the HASH_CSRx registers have to be read and the read \nvalues have to be saved somewhere in the system memory space. Then the hash \nprocessor can be used by the preemptive task, and when hash computation is finished, the \nsaved context can be read from memory and written back into these HASH_CSRx registers.\nHASH_CSRx\nAddress offset: 0x0F8 to 0x1C0 on STM32F415/417xx \nAddress offset: 0x0F8 to 0x1CC on STM32F43xxx\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nCSx\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCSx\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 798, "page_indices": { "start_index": 1547883, "end_index": 1549572 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 798 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.4 HASH registers", 785 ], [ 3, "25.4.9 HASH register map", 798 ] ], "page_content": "Hash processor (HASH)\nRM0090\n798/1757\nRM0090 Rev 21\n25.4.9 \nHASH register map\nTable 9 gives the summary HASH register map and reset values.\n \nTable 118. HASH register map and reset values on STM32F415/417xx\nOffset\nRegister name\nreset value\nRegister size\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nHASH_CR\nReserved\nLKEY\nReserved\nDINNE\nNBW\nALGO[0]\nMODE\nDATATYPE\nDMAE\nINIT\nReserved\nReset value\n0\n0 0 0 0 0 0 0 0 0 0 0\n0x04\nHASH_DIN\nDATAIN\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x08\nHASH_STR\nReserved\nDCAL\nReserved\nNBLW\nReset value\n0\n0 0 0 0 0\n0x0C \nHASH_HR0\nH0\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x10 \nHASH_HR1\nH1\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x14 \nHASH_HR2\nH2\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x18\nHASH_HR3\nH3\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x1C\nHASH_HR4\nH4\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x20\nHASH_IMR\nReserved\nDCIE\nDINIE\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x24\nHASH_SR\nReserved\nBUSY\nDMAS\nDCIS\nDINIS\nReset value\n0 0 0 1\n0xF8\nHASH_CSR0\nCSR0\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0\n...\n...\n0x1C0 HASH_CSR50\nCSR50\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nReserved\n0x310\nHASH_HR0\nH0\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x314\nHASH_HR1\nH1\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n" }, { "page_number": 799, "page_indices": { "start_index": 1549572, "end_index": 1551290 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 799 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.4 HASH registers", 785 ], [ 3, "25.4.9 HASH register map", 798 ] ], "page_content": "RM0090 Rev 21\n799/1757\nRM0090\nHash processor (HASH)\n800\n0x318\nHASH_HR2\nH2\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x31C\nHASH_HR3\nH3\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x320\nHASH_HR4\nH4\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nTable 119. HASH register map and reset values on STM32F43xxx\nOffset\nRegister name\nreset value\nRegister size\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nHASH_CR\nReserved\nALGO[1]\nReserved\nLKEY\nReserved\nMDMAT\nDINNE\nNBW\nALGO[0]\nMODE\nDATATYPE\nDMAE\nINIT\nReserved\nReset value\n0\n0\n0 0 0 0 0 0 0 0 0 0 0 0\n0x04\nHASH_DIN\nDATAIN\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x08\nHASH_STR\nReserved\nDCAL\nReserved\nNBLW\nReset value\n0\n0 0 0 0 0\n0x0C \nHASH_HR0\nH0\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x10 \nHASH_HR1\nH1\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x14 \nHASH_HR2\nH2\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x18\nHASH_HR3\nH3\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x1C\nHASH_HR4\nH4\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x20\nHASH_IMR\nReserved\nDCIE\nDINIE\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x24\nHASH_SR\nReserved\nBUSY\nDMAS\nDCIS\nDINIS\nReset value\n0 0 0 1\nTable 118. HASH register map and reset values on STM32F415/417xx (continued)\nOffset\nRegister name\nreset value\nRegister size\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 800, "page_indices": { "start_index": 1551290, "end_index": 1552534 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 800 }, "toc_details": [ [ 1, "25 Hash processor (HASH)", 775 ], [ 2, "25.4 HASH registers", 785 ], [ 3, "25.4.9 HASH register map", 798 ] ], "page_content": "Hash processor (HASH)\nRM0090\n800/1757\nRM0090 Rev 21\n0xF8\nHASH_CSR0\nCSR0\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0\n...\n...\n0x1CC\nHASH_CSR53\nCSR53\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nReserved\n0x310\nHASH_HR0\nH0\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x314\nHASH_HR1\nH1\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x318\nHASH_HR2\nH2\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x31C\nHASH_HR3\nH3\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x320\nHASH_HR4\nH4\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x324\nHASH_HR5\nH5\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x328\nHASH_HR6\nH6\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x32C\nHASH_HR7\nH7\nReset value\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nTable 119. HASH register map and reset values on STM32F43xxx (continued)\nOffset\nRegister name\nreset value\nRegister size\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 801, "page_indices": { "start_index": 1552534, "end_index": 1553908 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 801 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.1 Introduction", 801 ] ], "page_content": "RM0090 Rev 21\n801/1757\nRM0090\nReal-time clock (RTC)\n841\n26 \nReal-time clock (RTC)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n26.1 \nIntroduction\nThe real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-\nof-day clock/calendar, two programmable alarm interrupts, and a periodic programmable \nwake-up flag with interrupt capability. The RTC also includes an automatic wake-up unit to \nmanage low-power modes.\nTwo 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day \nof week), date (day of month), month, and year, expressed in binary coded decimal format \n(BCD). The sub-seconds value is also available in binary format.\nCompensations for 28-, 29- (leap year), 30-, and 31-day months are performed \nautomatically. Daylight saving time compensation can also be performed. \nAdditional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, \nhours, day, and date.\nA digital calibration feature is available to compensate for any deviation in crystal oscillator \naccuracy.\nAfter backup domain reset, all RTC registers are protected against possible parasitic write \naccesses.\nAs long as the supply voltage remains in the operating range, the RTC never stops, \nregardless of the device status (Run mode, low-power mode or under reset).\n" }, { "page_number": 802, "page_indices": { "start_index": 1553908, "end_index": 1556069 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 802 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.2 RTC main features", 802 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n802/1757\nRM0090 Rev 21\n26.2 \nRTC main features\nThe RTC unit main features are the following (see Figure 237: RTC block diagram):\n•\nCalendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of \nweek), date (day of month), month, and year.\n•\nDaylight saving compensation programmable by software.\n•\nTwo programmable alarms with interrupt function. The alarms can be triggered by any \ncombination of the calendar fields.\n•\nAutomatic wake-up unit generating a periodic flag that triggers an automatic wake-up \ninterrupt.\n•\nReference clock detection: a more precise second source clock (50 or 60 Hz) can be \nused to enhance the calendar precision.\n•\nAccurate synchronization with an external clock using the subsecond shift feature.\n•\nMaskable interrupts/events:\n–\nAlarm A\n–\nAlarm B\n–\nWake-up interrupt\n–\nTimestamp\n–\nTamper detection\n•\nDigital calibration circuit (periodic counter correction) \n–\n5 ppm accuracy \n–\n0.95 ppm accuracy, obtained in a calibration window of several seconds\n•\nTimestamp function for event saving (1 event)\n•\nTamper detection:\n–\n2 tamper events with configurable filter and internal pull-up.\n•\n20 backup registers (80 bytes). The backup registers are reset when a tamper \ndetection event occurs.\n•\nAlternate function output (RTC_OUT) which selects one of the following two outputs: \n–\nRTC_CALIB: 512 Hz or 1 Hz clock output (with an LSE frequency of 32.768 kHz).\nThis output is enabled by setting the COE bit in the RTC_CR register. It is routed \nto the device RTC_AF1 function. \n–\nRTC_ALARM (Alarm A, Alarm B or wake-up). \nThis output is selected by configuring the OSEL[1:0] bits in the RTC_CR register. \nIt is routed to the device RTC_AF1 function.\n•\nRTC alternate function inputs:\n–\nRTC_TS: timestamp event detection. It is routed to the device RTC_AF1 and \nRTC_AF2 functions. \n–\nRTC_TAMP1: TAMPER1 event detection. It is routed to the device RTC_AF1 and \nRTC_AF2 functions. \n–\nRTC_TAMP2: TAMPER2 event detection. \n–\nRTC_REFIN: reference clock input (usually the mains, 50 or 60 Hz).\nRefer to Section 8.3.15: Selection of RTC_AF1 and RTC_AF2 alternate functions. \n" }, { "page_number": 803, "page_indices": { "start_index": 1556069, "end_index": 1556947 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 803 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.2 RTC main features", 802 ] ], "page_content": "RM0090 Rev 21\n803/1757\nRM0090\nReal-time clock (RTC)\n841\nFigure 237. RTC block diagram \n1.\nOn STM32F4xx devices, the RTC_AF1 and RTC_AF2 alternate functions are connected to PC13 and PI8, \nrespectively.\nMS30216V7\nCalendar\nRTC_ALARM\nRTCCLK\nDivided HSE\nLSE (32.768 Hz)\nLSI\nSynchronous \n15-bit prescaler \n(default = 256)\nALRAF\nRTC_PRER\nBackup registers \nand RTC tamper \ncontrol register\nTAMPxF\nTime stamp \nregisters\nTSF\nOutput \ncontrol\nRTC_OUT\ncalibration\nRTC_TAMP2\n=\nSmooth\nck_spre\n(default 1 Hz)\nRTC_REFIN\nRTC_TAMP1\nRTC_TS\nAsynchronous \n7-bit prescaler \n(default = 128)\nRTC_PRER\nRTC_CALR\nShadow registers \nRTC_TR,\nRTC_DR\nAlarm A\nRTC_ALRMAR\nRTC_ALRMASSR \nck_apre\n(default 256 Hz\nRTC_CALIB\nShadow register \nRTC_SSR\nAlarm B\n=\nALRBF\nWUCKSEL[1:0]\nPrescaler\n1, 2, 4, 8, 16\n16-bit wakeup\nauto reload timer\nRTC_WUTR\nRTC_TAMP3\nWUTF\nOSEL[1:0]\nRTC_ALRMBR\nRTC_ALRMBSSR \n" }, { "page_number": 804, "page_indices": { "start_index": 1556947, "end_index": 1559134 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 804 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.3 RTC functional description", 804 ], [ 3, "26.3.1 Clock and prescalers", 804 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n804/1757\nRM0090 Rev 21\n26.3 \nRTC functional description\n26.3.1 \nClock and prescalers\nThe RTC clock source (RTCCLK) is selected through the clock controller among the LSE \nclock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock \nsource configuration, refer to Section 7: Reset and clock control for STM32F405xx/07xx \nand STM32F415xx/17xx(RCC) and Section 6: Reset and clock control for STM32F42xxx \nand STM32F43xxx (RCC).\nA programmable prescaler stage generates a 1 Hz clock which is used to update the \ncalendar. To minimize power consumption, the prescaler is split into 2 programmable \nprescalers (see Figure 237: RTC block diagram):\n•\nA 7-bit asynchronous prescaler configured through the PREDIV_A bits of the \nRTC_PRER register. \n•\n A 15-bit synchronous prescaler configured through the PREDIV_S bits of the \nRTC_PRER register. \nNote:\nWhen both prescalers are used, it is recommended to configure the asynchronous prescaler \nto a high value to minimize consumption.\nThe asynchronous prescaler division factor is set to 128, and the synchronous division \nfactor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency \nof 32.768 kHz. \nThe minimum division factor is 1 and the maximum division factor is 222. \nThis corresponds to a maximum input frequency of around 4 MHz. \nfck_apre is given by the following formula:\nThe ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it \nreaches 0, RTC_SSR is reloaded with the content of PREDIV_S. \nfck_spre is given by the following formula:\nThe ck_spre clock can be used either to update the calendar or as timebase for the 16-bit \nwake-up auto-reload timer. To obtain short timeout periods, the 16-bit wake-up auto-reload \ntimer can also run with the RTCCLK divided by the programmable 4-bit asynchronous \nprescaler (see Section 26.3.4: Periodic auto-wakeup for details).\nfCK_APRE\nfRTCCLK\nPREDIV_A\n1\n+\n--------------------------------------\n=\nfCK_SPRE\nfRTCCLK\nPREDIV_S\n1\n+\n(\n)\nPREDIV_A\n1\n+\n(\n)\n×\n-----------------------------------------------------------------------------------------------\n=\n" }, { "page_number": 805, "page_indices": { "start_index": 1559134, "end_index": 1561736 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 805 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.3 RTC functional description", 804 ], [ 3, "26.3.2 Real-time clock and calendar", 805 ], [ 3, "26.3.3 Programmable alarms", 805 ], [ 3, "26.3.4 Periodic auto-wakeup", 805 ] ], "page_content": "RM0090 Rev 21\n805/1757\nRM0090\nReal-time clock (RTC)\n841\n26.3.2 \nReal-time clock and calendar\nThe RTC calendar time and date registers are accessed through shadow registers which \nare synchronized with PCLK1 (APB1 clock). They can also be accessed directly in order to \navoid waiting for the synchronization duration.\n•\nRTC_SSR for the subseconds \n•\nRTC_TR for the time\n•\nRTC_DR for the date\nEvery two RTCCLK periods, the current calendar value is copied into the shadow registers, \nand the RSF bit of RTC_ISR register is set (see Section 26.6.4). The copy is not performed \nin Stop and Standby mode. When exiting these modes, the shadow registers are updated \nafter up to 2 RTCCLK periods.\nWhen the application reads the calendar registers, it accesses the content of the shadow \nregisters.t is possible to make a direct access to the calendar registers by setting the \nBYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user \naccesses the shadow registers.\nWhen reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD=0 mode, the \nfrequency of the APB clock (fAPB) must be at least 7 times the frequency of the RTC clock \n(fRTCCLK).\nThe shadow registers are reset by system reset. \n26.3.3 \nProgrammable alarms\nThe RTC unit provides two programmable alarms, Alarm A and Alarm B.\nThe programmable alarm functions are enabled through the ALRAIE and ALRBIE bits in the \nRTC_CR register. The ALRAF and ALRBF flags are set to 1 if the calendar subseconds, \nseconds, minutes, hours, date or day match the values programmed in the alarm registers \nRTC_ALRMASSR/RTC_ALRMAR and RTC_ALRMBSSR/RTC_ALRMBR, respectively. \nEach calendar field can be independently selected through the MSKx bits of the \nRTC_ALRMAR and RTC_ALRMBR registers, and through the MASKSSx bits of the \nRTC_ALRMASSR and RTC_ALRMBSSR registers. The alarm interrupts are enabled \nthrough the ALRAIE and ALRBIE bits in the RTC_CR register.\nAlarm A and Alarm B (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the \nRTC_ALARM output. RTC_ALARM polarity can be configured through bit POL in the \nRTC_CR register.\nCaution:\nIf the seconds field is selected (MSK0 bit reset in RTC_ALRMAR or RTC_ALRMBR), the \nsynchronous prescaler division factor set in the RTC_PRER register must be at least 3 to \nensure correct behavior.\n26.3.4 \nPeriodic auto-wakeup \nThe periodic wake-up flag is generated by a 16-bit programmable auto-reload down-\ncounter. The wake-up timer range can be extended to 17 bits.\nThe wake-up function is enabled through the WUTE bit in the RTC_CR register.\n" }, { "page_number": 806, "page_indices": { "start_index": 1561736, "end_index": 1564337 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 806 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.3 RTC functional description", 804 ], [ 3, "26.3.5 RTC initialization and configuration", 806 ], [ 4, "RTC register access", 806 ], [ 4, "RTC register write protection", 806 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n806/1757\nRM0090 Rev 21\nThe wake-up timer clock input can be:\n•\nRTC clock (RTCCLK) divided by 2, 4, 8, or 16.\nWhen RTCCLK is LSE(32.768kHz), this allows configuring the wake-up interrupt period \nfrom 122 µs to 32 s, with a resolution down to 61µs.\n•\nck_spre (usually 1 Hz internal clock)\nWhen ck_spre frequency is 1Hz, this allows achieving a wake-up time from 1 s to \naround 36 hours with one-second resolution. This large programmable time range is \ndivided in 2 parts:\n–\nfrom 1s to 18 hours when WUCKSEL [2:1] = 10\n–\nand from around 18h to 36h when WUCKSEL[2:1] = 11. In this last case 216 is \nadded to the 16-bit counter current value.When the initialization sequence is \ncomplete (see Programming the wake-up timer on page 808), the timer starts \ncounting down.When the wake-up function is enabled, the down-counting remains \nactive in low-power modes. In addition, when it reaches 0, the WUTF flag is set in \nthe RTC_ISR register, and the wake-up counter is automatically reloaded with its \nreload value (RTC_WUTR register value).\nThe WUTF flag must then be cleared by software.\nWhen the periodic wake-up interrupt is enabled by setting the WUTIE bit in the RTC_CR2 \nregister, it can exit the device from low-power modes.\nThe periodic wake-up flag can be routed to the RTC_ALARM output provided it has been \nenabled through bits OSEL[1:0] of RTC_CR register. RTC_ALARM polarity can be \nconfigured through the POL bit in the RTC_CR register.\nSystem reset, as well as low-power modes (Sleep, Stop and Standby) have no influence on \nthe wake-up timer.\n26.3.5 \nRTC initialization and configuration\nRTC register access\nThe RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC \nregister accesses except on read accesses to calendar shadow registers when \nBYPSHAD=0.\nRTC register write protection\nAfter system reset, the RTC registers are protected against parasitic write access with the \nDBP bit of the PWR power control register (PWR_CR). The DBP bit must be set to enable \nRTC registers write access.\nAfter backup domain reset, all the RTC registers are write-protected. Writing to the RTC \nregisters is enabled by writing a key into the Write Protection register, RTC_WPR.\nThe following steps are required to unlock the write protection on all the RTC registers \nexcept for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR.\n1.\nWrite ‘0xCA’ into the RTC_WPR register.\n2. \nWrite ‘0x53’ into the RTC_WPR register.\nWriting a wrong key reactivates the write protection.\nThe protection mechanism is not affected by system reset.\n" }, { "page_number": 807, "page_indices": { "start_index": 1564337, "end_index": 1567140 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 807 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.3 RTC functional description", 804 ], [ 3, "26.3.5 RTC initialization and configuration", 806 ], [ 4, "Calendar initialization and configuration", 807 ], [ 4, "Daylight saving time", 807 ], [ 4, "Programming the alarm", 807 ] ], "page_content": "RM0090 Rev 21\n807/1757\nRM0090\nReal-time clock (RTC)\n841\nCalendar initialization and configuration\nTo program the initial time and date calendar values, including the time format and the \nprescaler configuration, the following sequence is required:\n1.\nSet INIT bit to 1 in the RTC_ISR register to enter initialization mode. In this mode, the \ncalendar counter is stopped and its value can be updated.\n2. \nPoll INITF bit of in the RTC_ISR register. The initialization phase mode is entered when \nINITF is set to 1. It takes from 1 to 2 RTCCLK clock cycles (due to clock \nsynchronization). \n3. \nTo generate a 1 Hz clock for the calendar counter, program first the synchronous \nprescaler factor in RTC_PRER register, and then program the asynchronous prescaler \nfactor. Even if only one of the two fields needs to be changed, 2 separate write \naccesses must be performed to the RTC_PRER register.\n4. \nLoad the initial time and date values in the shadow registers (RTC_TR and RTC_DR), \nand configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR \nregister.\n5. \nExit the initialization mode by clearing the INIT bit. The actual calendar counter value is \nthen automatically loaded and the counting restarts after 4 RTCCLK clock cycles.\nWhen the initialization sequence is complete, the calendar starts counting.\nNote:\nAfter a system reset, the application can read the INITS flag in the RTC_ISR register to \ncheck if the calendar has been initialized or not. If this flag equals 0, the calendar has not \nbeen initialized since the year field is set at its backup domain reset default value (0x00).\nTo read the calendar after initialization, the software must first check that the RSF flag is set \nin the RTC_ISR register.\nDaylight saving time\nThe daylight saving time management is performed through bits SUB1H, ADD1H, and BKP \nof the RTC_CR register.\nUsing SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one \nsingle operation without going through the initialization procedure.\nIn addition, the software can use the BKP bit to memorize this operation.\nProgramming the alarm\nA similar procedure must be followed to program or update the programmable alarm (Alarm \nA or Alarm B):\n1.\nClear ALRAE or ALRBIE in RTC_CR to disable Alarm A or Alarm B.\n2. \nPoll ALRAWF or ALRBWF in RTC_ISR until it is set to make sure the access to alarm \nregisters is allowed. This takes 1 to 2 RTCCLK clock cycles (due to clock \nsynchronization). \n3. \nProgram the Alarm A or Alarm B registers (RTC_ALRMASSR/RTC_ALRMAR or \nRTC_ALRMBSSR/RTC_ALRMBR).\n4. \nSet ALRAE or ALRBIE in the RTC_CR register to enable Alarm A or Alarm B again.\nNote:\nEach change of the RTC_CR register is taken into account after 1 to 2 RTCCLK clock cycles \ndue to clock synchronization.\n" }, { "page_number": 808, "page_indices": { "start_index": 1567140, "end_index": 1570144 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 808 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.3 RTC functional description", 804 ], [ 3, "26.3.5 RTC initialization and configuration", 806 ], [ 4, "Programming the wake-up timer", 808 ], [ 3, "26.3.6 Reading the calendar", 808 ], [ 4, "When BYPSHAD control bit is cleared in the RTC_CR register", 808 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n808/1757\nRM0090 Rev 21\nProgramming the wake-up timer\nThe following sequence is required to configure or change the wake-up timer auto-reload \nvalue (WUT[15:0] in RTC_WUTR):\n1.\nClear WUTE in RTC_CR to disable the wake-up timer.\n2. \nPoll WUTWF until it is set in RTC_ISR to make sure the access to wake-up auto-reload \ncounter and to WUCKSEL[2:0] bits is allowed. It takes 1 to 2 RTCCLK clock cycles \n(due to clock synchronization).\n3. \nProgram the wake-up auto-reload value WUT[15:0], and the wake-up clock selection \n(WUCKSEL[2:0] bits in RTC_CR).Set WUTE in RTC_CR to enable the timer again. \nThe wake-up timer restarts down-counting. The WUTWF bit is cleared up to 2 RTCCLK \nclocks cycles after WUTE is cleared, due to clock synchronization.\n26.3.6 \nReading the calendar\nWhen BYPSHAD control bit is cleared in the RTC_CR register\nTo read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB1 \nclock frequency (fPCLK1) must be equal to or greater than seven times the fRTCCLK RTC \nclock frequency. This ensures a secure behavior of the synchronization mechanism.\nIf the APB1 clock frequency is less than seven times the RTC clock frequency, the software \nmust read the calendar time and date registers twice. If the second read of the RTC_TR \ngives the same result as the first read, this ensures that the data is correct. Otherwise a third \nread access must be done. In any case the APB1 clock frequency must never be lower than \nthe RTC clock frequency.\nThe RSF bit is set in RTC_ISR register each time the calendar registers are copied into the \nRTC_SSR, RTC_TR and RTC_DR shadow registers. The copy is performed every two \nRTCCLK cycles. To ensure consistency between the 3 values, reading either RTC_SSR or \nRTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is \nread. In case the software makes read accesses to the calendar in a time interval smaller \nthan 1 RTCCLK periods: RSF must be cleared by software after the first calendar read, and \nthen the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR \nand RTC_DR registers.\nAfter waking up from low-power mode (Stop or Standby), RSF must be cleared by software. \nThe software must then wait until it is set again before reading the RTC_SSR, RTC_TR and \nRTC_DR registers.\nThe RSF bit must be cleared after wake-up and not before entering low-power mode.\nNote:\nAfter a system reset, the software must wait until RSF is set before reading the RTC_SSR, \nRTC_TR and RTC_DR registers. Indeed, a system reset resets the shadow registers to \ntheir default values. \nAfter an initialization (refer to Calendar initialization and configuration on page 807): the \nsoftware must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR \nregisters.\nAfter synchronization (refer to Section 26.3.8: RTC synchronization): the software must wait \nuntil RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers.\n" }, { "page_number": 809, "page_indices": { "start_index": 1570144, "end_index": 1573349 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 809 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.3 RTC functional description", 804 ], [ 3, "26.3.6 Reading the calendar", 808 ], [ 4, "When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow registers)", 809 ], [ 3, "26.3.7 Resetting the RTC", 809 ], [ 3, "26.3.8 RTC synchronization", 809 ] ], "page_content": "RM0090 Rev 21\n809/1757\nRM0090\nReal-time clock (RTC)\n841\nWhen the BYPSHAD control bit is set in the RTC_CR register (bypass shadow \nregisters)\nReading the calendar registers gives the values from the calendar counters directly, thus \neliminating the need to wait for the RSF bit to be set. This is especially useful after exiting \nfrom low-power modes (STOP or Standby), since the shadow registers are not updated \nduring these modes.\nWhen the BYPSHAD bit is set to 1, the results of the different registers might not be \ncoherent with each other if an RTCCLK edge occurs between two read accesses to the \nregisters. Additionally, the value of one of the registers may be incorrect if an RTCCLK edge \noccurs during the read operation. The software must read all the registers twice, and then \ncompare the results to confirm that the data is coherent and correct. Alternatively, the \nsoftware can just compare the two results of the least-significant calendar register.\nNote:\nWhile BYPSHAD=1, instructions which read the calendar registers require one extra APB \ncycle to complete.\n26.3.7 \nResetting the RTC\nThe calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the \nRTC status register (RTC_ISR) are reset to their default values by all available system reset \nsources.\nOn the contrary, the following registers are resetted to their default values by a backup \ndomain reset and are not affected by a system reset: the RTC current calendar registers, \nthe RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC \ncalibration registers (RTC_CALIBR or RTC_CALR), the RTC shift register (RTC_SHIFTR), \nthe RTC timestamp registers (RTC_TSSSR, RTC_TSTR and RTC_TSDR), the RTC tamper \nand alternate function configuration register (RTC_TAFCR), the RTC backup registers \n(RTC_BKPxR), the wake-up timer register (RTC_WUTR), the Alarm A and Alarm B \nregisters (RTC_ALRMASSR/RTC_ALRMAR and RTC_ALRMBSSR/RTC_ALRMBR). \nIn addition, when the RTC is clocked by the LSE, it goes on running under system reset if \nthe reset source is different from a backup domain reset one. Refer to section RTC clock of \nthe Reset and clock controller for details about the list of the RTC clock sources that are not \naffected by system reset.\nWhen a backup domain reset occurs, the RTC is stopped and all the RTC registers are set \nto their reset values.\n26.3.8 \nRTC synchronization \nThe RTC can be synchronized to a remote clock with a high degree of precision. After \nreading the sub-second field (RTC_SSR or RTC_TSSSR), a calculation can be made of the \nprecise offset between the times being maintained by the remote clock and the RTC. The \nRTC can then be adjusted to eliminate this offset by “shifting” its clock by a fraction of a \nsecond using RTC_SHIFTR.\nRTC_SSR contains the value of the synchronous prescaler counter. This allows one to \ncalculate the exact time being maintained by the RTC down to a resolution of \n1 / (PREDIV_S + 1) seconds. As a consequence, the resolution can be improved by \nincreasing the synchronous prescaler value (PREDIV_S[14:0]. The maximum resolution \nallowed (30.52 μs with a 32768 Hz clock) is obtained with PREDIV_S set to 0x7FFF.\n" }, { "page_number": 810, "page_indices": { "start_index": 1573349, "end_index": 1576681 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 810 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.3 RTC functional description", 804 ], [ 3, "26.3.9 RTC reference clock detection", 810 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n810/1757\nRM0090 Rev 21\nHowever, increasing PREDIV_S means that PREDIV_A must be decreased in order to \nmaintain the synchronous prescaler output at 1 Hz. In this way, the frequency of the \nasynchronous prescaler output increases, which may increase the RTC dynamic \nconsumption.\nThe RTC can be finely adjusted using the RTC shift control register (RTC_SHIFTR). Writing \nto RTC_SHIFTR can shift (either delay or advance) the clock by up to a second with a \nresolution of 1 / (PREDIV_S + 1) seconds. The shift operation consists of adding the \nSUBFS[14:0] value to the synchronous prescaler counter SS[15:0]: this delays the clock. If \nat the same time the ADD1S bit is set, this results in adding one second and at the same \ntime subtracting a fraction of second, so this advances the clock.\nCaution:\nBefore initiating a shift operation, the user must check that SS[15] = 0 in order to ensure that \nno overflow occurs.\nAs soon as a shift operation is initiated by a write to the RTC_SHIFTR register, the SHPF \nflag is set by hardware to indicate that a shift operation is pending. This bit is cleared by \nhardware as soon as the shift operation has completed. \nCaution:\nThis synchronization feature is not compatible with the reference clock detection feature: \nfirmware must not write to RTC_SHIFTR when REFCKON=1.\n26.3.9 \nRTC reference clock detection\nThe RTC calendar update can be synchronized to a reference clock RTC_REFIN, usually \nthe mains (50 or 60 Hz). The RTC_REFIN reference clock should have a higher precision \nthan the 32.768 kHz LSE clock. When the RTC_REFIN detection is enabled (REFCKON bit \nof RTC_CR set to 1), the calendar is still clocked by the LSE, and RTC_REFIN is used to \ncompensate for the imprecision of the calendar update frequency (1 Hz). \nEach 1 Hz clock edge is compared to the nearest reference clock edge (if one is found \nwithin a given time window). In most cases, the two clock edges are properly aligned. When \nthe 1 Hz clock becomes misaligned due to the imprecision of the LSE clock, the RTC shifts \nthe 1 Hz clock a bit so that future 1 Hz clock edges are aligned. Thanks to this mechanism, \nthe calendar becomes as precise as the reference clock. \nThe RTC detects if the reference clock source is present by using the 256 Hz clock \n(ck_apre) generated from the 32.768 kHz quartz. The detection is performed during a time \nwindow around each of the calendar updates (every 1 s). The window equals 7 ck_apre \nperiods when detecting the first reference clock edge. A smaller window of 3 ck_apre \nperiods is used for subsequent calendar updates. \nEach time the reference clock is detected in the window, the synchronous prescaler which \noutputs the ck_spre clock is forced to reload. This has no effect when the reference clock \nand the 1 Hz clock are aligned because the prescaler is being reloaded at the same \nmoment. When the clocks are not aligned, the reload shifts future 1 Hz clock edges a little \nfor them to be aligned with the reference clock. \nIf the reference clock halts (no reference clock edge occurred during the 3 ck_apre window), \nthe calendar is updated continuously based solely on the LSE clock. The RTC then waits for \nthe reference clock using a large 7 ck_apre period detection window centered on the \nck_spre edge.\n" }, { "page_number": 811, "page_indices": { "start_index": 1576681, "end_index": 1579759 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 811 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.3 RTC functional description", 804 ], [ 3, "26.3.10 RTC coarse digital calibration", 811 ], [ 4, "Case of RTCCLK=32.768 kHz and PREDIV_A+1=128", 811 ] ], "page_content": "RM0090 Rev 21\n811/1757\nRM0090\nReal-time clock (RTC)\n841\nWhen the reference clock detection is enabled, PREDIV_A and PREDIV_S must be set to \ntheir default values:\n•\nPREDIV_A = 0x007F\n•\nPREDIV_S = 0x00FF\nNote:\nThe reference clock detection is not available in Standby mode.\nCaution:\nThe reference clock detection feature cannot be used in conjunction with the coarse digital \ncalibration: RTC_CALIBR must be kept at 0x0000 0000 when REFCKON=1.\n26.3.10 \nRTC coarse digital calibration\nTwo digital calibration methods are available: coarse and smooth calibration. To perform \ncoarse calibration refer to Section 26.6.7: RTC calibration register (RTC_CALIBR).\n The two calibration methods are not intended to be used together, the application must \nselect one of the two methods. Coarse calibration is provided for compatibly reasons. To \nperform smooth calibration refer to Section 26.3.11: RTC smooth digital calibration and the \nSection 26.6.16: RTC calibration register (RTC_CALR)\nThe coarse digital calibration can be used to compensate crystal inaccuracy by adding \n(positive calibration) or masking (negative calibration) clock cycles at the output of the \nasynchronous prescaler (ck_apre).\nPositive and negative calibration are selected by setting the DCS bit in RTC_CALIBR \nregister to ‘0’ and ‘1’, respectively.\nWhen positive calibration is enabled (DCS = ‘0’), 2 ck_apre cycles are added every minute \n(around 15360 ck_apre cycles) for 2xDC minutes. This causes the calendar to be updated \nsooner, thereby adjusting the effective RTC frequency to be a bit higher.\nWhen negative calibration is enabled (DCS = ‘1’), 1 ck_apre cycle is removed every minute \n(around 15360 ck_apre cycles) for 2xDC minutes. This causes the calendar to be updated \nlater, thereby adjusting the effective RTC frequency to be a bit lower.\nDC is configured through bits DC[4:0] of RTC_CALIBR register. This number ranges from 0 \nto 31 corresponding to a time interval (2xDC) ranging from 0 to 62.\nThe coarse digital calibration can be configured only in initialization mode, and starts when \nthe INIT bit is cleared. The full calibration cycle lasts 64 minutes. The first 2xDC minutes of \nthe 64 -minute cycle are modified as just described.\nNegative calibration can be performed with a resolution of about 2 ppm while positive \ncalibration can be performed with a resolution of about 4 ppm. The maximum calibration \nranges from -63 ppm to 126 ppm.\nThe calibration can be performed either on the LSE or on the HSE clock.\nCaution:\nDigital calibration may not work correctly if PREDIV_A < 6.\nCase of RTCCLK=32.768 kHz and PREDIV_A+1=128\nThe following description assumes that ck_apre frequency is 256 Hz obtained with an LSE \nclock nominal frequency of 32.768 kHz, and PREDIV_A set to 127 (default value). \nThe ck_spre clock frequency is only modified during the first 2xDC minutes of the 64-minute \ncycle. For example, when DC equals 1, only the first 2 minutes are modified. This means \nthat the first 2xDC minutes of each 64-minute cycle have, once per minute, one second \n" }, { "page_number": 812, "page_indices": { "start_index": 1579759, "end_index": 1583042 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 812 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.3 RTC functional description", 804 ], [ 3, "26.3.11 RTC smooth digital calibration", 812 ], [ 4, "Calibration when PREDIV_A<3", 812 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n812/1757\nRM0090 Rev 21\neither shortened by 256 or lengthened by 128 RTCCLK cycles, given that each ck_apre \ncycle represents 128 RTCCLK cycles (with PREDIV_A+1=128).\nTherefore each calibration step has the effect of adding 512 or subtracting 256 oscillator \ncycles for every 125829120 RTCCLK cycles (64min x 60 s/min x 32768 cycles/s). This is \nequivalent to +4.069 ppm or -2.035 ppm per calibration step. As a result, the calibration \nresolution is +10.5 or -5.27 seconds per month, and the total calibration ranges from +5.45 \nto -2.72 minutes per month.\nIn order to measure the clock deviation, a 512 Hz clock is output for calibration.Refer to \nSection 26.3.14: Calibration clock output.\n26.3.11 \nRTC smooth digital calibration \n RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a range \nfrom -487.1 ppm to +488.5 ppm. The correction of the frequency is performed using series \nof small adjustments (adding and/or subtracting individual RTCCLK pulses). These \nadjustments are fairly well distributed so that the RTC is well calibrated even when observed \nover short durations of time.\nThe smooth digital calibration is performed during a cycle of about 220 RTCCLK pulses, or \n32 seconds when the input frequency is 32768 Hz. This cycle is maintained by a 20-bit \ncounter, cal_cnt[19:0], clocked by RTCCLK.\nThe smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles \nto be masked during the 32-second cycle:\n•\nSetting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32-\nsecond cycle.\n•\nSetting CALM[1] to 1 causes two additional cycles to be masked\n•\nSetting CALM[2] to 1 causes four additional cycles to be masked\n•\nand so on up to CALM[8] set to 1 which causes 256 clocks to be masked.\nNote:\nCALM[8:0] (RTC_CALRx) specifies the number of RTCCLK pulses to be masked during the \n32-second cycle. Setting the bit CALM[0] to ‘1’ causes exactly one pulse to be masked \nduring the 32-second cycle at the moment when cal_cnt[19:0] is 0x80000; CALM[1]=1 \ncauses two other cycles to be masked (when cal_cnt is 0x40000 and 0xC0000); CALM[2]=1 \ncauses four other cycles to be masked (cal_cnt = 0x20000/0x60000/0xA0000/ 0xE0000); \nand so on up to CALM[8]=1 which causes 256 clocks to be masked (cal_cnt = 0xXX800).\nWhile CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine \nresolution, the bit CALP can be used to increase the frequency by 488.5 ppm. Setting CALP \nto ‘1’ effectively inserts an extra RTCCLK pulse every 211 RTCCLK cycles, which means \nthat 512 clocks are added during every 32-second cycle.\nUsing CALM together with CALP, an offset ranging from -511 to +512 RTCCLK cycles can \nbe added during the 32-second cycle, which translates to a calibration range of -487.1 ppm \nto +488.5 ppm with a resolution of about 0.954 ppm.\nThe formula to calculate the effective calibrated frequency (FCAL) given the input frequency \n(FRTCCLK) is as follows:\nFCAL = FRTCCLK x [1 + (CALP x 512 - CALM) / (220 + CALM - CALP x 512)]\nCalibration when PREDIV_A<3\nThe CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in \nRTC_PRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are \n" }, { "page_number": 813, "page_indices": { "start_index": 1583042, "end_index": 1586151 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 813 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.3 RTC functional description", 804 ], [ 3, "26.3.11 RTC smooth digital calibration", 812 ], [ 4, "Verifying the RTC calibration", 813 ], [ 4, "Re-calibration on-the-fly", 813 ] ], "page_content": "RM0090 Rev 21\n813/1757\nRM0090\nReal-time clock (RTC)\n841\nset to a value less than 3, CALP is ignored and the calibration operates as if CALP was \nequal to 0.\nTo perform a calibration with PREDIV_A less than 3, the synchronous prescaler value \n(PREDIV_S) should be reduced so that each second is accelerated by 8 RTCCLK clock \ncycles, which is equivalent to adding 256 clock cycles every 32 seconds. As a result, \nbetween 255 and 256 clock pulses (corresponding to a calibration range from 243.3 to \n244.1 ppm) can effectively be added during each 32-second cycle using only the CALM bits.\nWith a nominal RTCCLK frequency of 32768 Hz, when PREDIV_A equals 1 (division factor \nof 2), PREDIV_S should be set to 16379 rather than 16383 (4 less). The only other \ninteresting case is when PREDIV_A equals 0, PREDIV_S should be set to 32759 rather \nthan 32767 (8 less).\nIf PREDIV_S is reduced in this way, the formula given the effective frequency of the\ncalibrated input clock is as follows:\nFCAL = FRTCCLK x [1 + (256 - CALM) / (220 + CALM - 256)]\nIn this case, CALM[7:0] equals 0x100 (the midpoint of the CALM range) is the correct \nsetting if RTCCLK is exactly 32768.00 Hz.\nVerifying the RTC calibration\nRTC precision is performed by measuring the precise frequency of RTCCLK and calculating \nthe correct CALM value and CALP values. An optional 1 Hz output is provided to allow \napplications to measure and verify the RTC precision.\nMeasuring the precise frequency of the RTC over a limited interval can result in a \nmeasurement error of up to 2 RTCCLK clock cycles over the measurement period, \ndepending on how the digital calibration cycle is aligned with the measurement period.\nHowever, this measurement error can be eliminated if the measurement period is the same \nlength as the calibration cycle period. In this case, the only error observed is the error due to \nthe resolution of the digital calibration.\n•\nBy default, the calibration cycle period is 32 seconds. \nUsing this mode and measuring the accuracy of the 1 Hz output over exactly 32 \nseconds guarantees that the measure is within 0.477 ppm (0.5 RTCCLK cycles over 32 \nseconds, due to the limitation of the calibration resolution). \n•\nCALW16 bit of the RTC_CALR register can be set to 1 to force a 16- second calibration \ncycle period.\nIn this case, the RTC precision can be measured during 16 seconds with a maximum \nerror of 0.954 ppm (0.5 RTCCLK cycles over 16 seconds). However, since the \ncalibration resolution is reduced, the long term RTC precision is also reduced to 0.954 \nppm: CALM[0] bit is stuck at 0 when CALW16 is set to 1.\n•\nCALW8 bit of the RTC_CALR register can be set to 1 to force a 8- second calibration \ncycle period.\nIn this case, the RTC precision can be measured during 8 seconds with a maximum \nerror of 1.907 ppm (0.5 RTCCLK cycles over 8s). The long term RTC precision is also \nreduced to 1.907 ppm: CALM[1:0] bits are stuck at 00 when CALW8 is set to 1.\nRe-calibration on-the-fly\nThe calibration register (RTC_CALR) can be updated on-the-fly while RTC_ISR/INITF=0, by \nusing the follow process:\n" }, { "page_number": 814, "page_indices": { "start_index": 1586151, "end_index": 1589043 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 814 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.3 RTC functional description", 804 ], [ 3, "26.3.12 Timestamp function", 814 ], [ 4, "TIMESTAMP alternate function", 814 ], [ 3, "26.3.13 Tamper detection", 814 ], [ 4, "RTC backup registers", 814 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n814/1757\nRM0090 Rev 21\n1.\nPoll the RTC_ISR/RECALPF (re-calibration pending flag).\n2. \nIf it is set to 0, write a new value to RTC_CALR, if necessary. RECALPF is then \nautomatically set to 1\n3. \nWithin three ck_apre cycles after the write operation to RTC_CALR, the new calibration \nsettings take effect.\n26.3.12 \nTimestamp function\nTimestamp is enabled by setting the TSE bit of RTC_CR register to 1.\nThe calendar is saved in the timestamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) \nwhen a timestamp event is detected on the pin to which the TIMESTAMP alternate function \nis mapped. When a timestamp event occurs, the timestamp flag bit (TSF) in RTC_ISR \nregister is set. \nBy setting the TSIE bit in the RTC_CR register, an interrupt is generated when a timestamp \nevent occurs. \nIf a new timestamp event is detected while the timestamp flag (TSF) is already set, the \ntimestamp overflow flag (TSOVF) flag is set and the timestamp registers (RTC_TSTR and \nRTC_TSDR) maintain the results of the previous event.\nNote:\nTSF is set 2 ck_apre cycles after the timestamp event occurs due to synchronization \nprocess.\nThere is no delay in the setting of TSOVF. This means that if two timestamp events are \nclose together, TSOVF can be seen as '1' while TSF is still '0'. As a consequence, it is \nrecommended to poll TSOVF only after TSF has been set.\nCaution:\nIf a timestamp event occurs immediately after the TSF bit is supposed to be cleared, then \nboth TSF and TSOVF bits are set. To avoid masking a timestamp event occurring at the \nsame moment, the application must not write ‘0’ into TSF bit unless it has already read it to \n‘1’.\nOptionally, a tamper event can cause a timestamp to be recorded. See the description of the \nTAMPTS control bit in Section 26.6.17: RTC tamper and alternate function configuration \nregister (RTC_TAFCR). If the timestamp event is on the same pin as a tamper event \nconfigured in filtered mode (TAMPFLT set to a non-zero value), the timestamp on tamper \ndetection event mode must be selected by setting TAMPTS='1' in RTC_TAFCR register.\nTIMESTAMP alternate function\nThe TIMESTAMP alternate function (RTC_TS) can be mapped either to RTC_AF1 or to \nRTC_AF2 depending on the value of the TSINSEL bit in the RTC_TAFCR register (see \nSection 26.6.17: RTC tamper and alternate function configuration register (RTC_TAFCR)). \nMapping the timestamp event on RTC_AF2 is not allowed if RTC_AF1 is used as TAMPER \nin filtered mode (TAMPFLT set to a non-zero value).\n26.3.13 \nTamper detection\nTwo tamper detection inputs are available. They can be configured either for edge detection, \nor for level detection with filtering.\nRTC backup registers\nThe backup registers (RTC_BKPxR) are twenty 32-bit registers for storing 80 bytes of user \napplication data. They are implemented in the backup domain that remains powered-on by \n" }, { "page_number": 815, "page_indices": { "start_index": 1589043, "end_index": 1592122 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 815 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.3 RTC functional description", 804 ], [ 3, "26.3.13 Tamper detection", 814 ], [ 4, "Tamper detection initialization", 815 ], [ 4, "Timestamp on tamper event", 815 ], [ 4, "Edge detection on tamper inputs", 815 ], [ 4, "Level detection with filtering on tamper inputs", 815 ] ], "page_content": "RM0090 Rev 21\n815/1757\nRM0090\nReal-time clock (RTC)\n841\nVBAT when the VDD power is switched off. They are not reset by system reset or when the \ndevice wakes up from Standby mode. They are reset by a backup domain reset\nThe backup registers are reset when a tamper detection event occurs (see Section 26.6.20: \nRTC backup registers (RTC_BKPxR) and Tamper detection initialization on page 815. \nTamper detection initialization\nEach tamper detection input is associated with the TAMP1F/TAMP2F flags in the RTC_ISR2 \nregister. Each input can be enabled by setting the corresponding TAMP1E/TAMP2E bits to 1 \nin the RTC_TAFCR register.\nA tamper detection event resets all backup registers (RTC_BKPxR).\nBy setting the TAMPIE bit in the RTC_TAFCR register, an interrupt is generated when a \ntamper detection event occurs. \nTimestamp on tamper event\nWith TAMPTS set to ‘1 , any tamper event causes a timestamp to occur. In this case, either \nthe TSF bit or the TSOVF bit are set in RTC_ISR, in the same manner as if a normal \ntimestamp event occurs. The affected tamper flag register (TAMP1F, TAMP2F) is set at the \nsame time that TSF or TSOVF is set.\nEdge detection on tamper inputs\nIf the TAMPFLT bits are “00”, the TAMPER pins generate tamper detection events \n(RTC_TAMP[2:1]) when either a rising edge is observed or an falling edge is observed \ndepending on the corresponding TAMPxTRG bit. The internal pull-up resistors on the \nTAMPER inputs are deactivated when edge detection is selected.\nCaution:\nTo avoid losing tamper detection events, the signal used for edge detection is logically \nANDed with TAMPxE in order to detect a tamper detection event in case it occurs before the \nTAMPERx pin is enabled.\n•\nWhen TAMPxTRG = 0: if the TAMPERx alternate function is already high before \ntamper detection is enabled (TAMPxE bit set to 1), a tamper event is detected as soon \nas TAMPERx is enabled, even if there was no rising edge on TAMPERx after TAMPxE \nwas set.\n•\nWhen TAMPxTRG = 1: if the TAMPERx alternate function is already low before tamper \ndetection is enabled, a tamper event is detected as soon as TAMPERx is enabled \n(even if there was no falling edge on TAMPERx after TAMPxE was set.\nAfter a tamper event has been detected and cleared, the TAMPERx alternate function \nshould be disabled and then re-enabled (TAMPxE set to 1) before re-programming the \nbackup registers (RTC_BKPxR). This prevents the application from writing to the backup \nregisters while the TAMPERx value still indicates a tamper detection. This is equivalent to a \nlevel detection on the TAMPERx alternate function.\nNote:\nTamper detection is still active when VDD power is switched off. To avoid unwanted resetting \nof the backup registers, the pin to which the TAMPER alternate function is mapped should \nbe externally tied to the correct level.\nLevel detection with filtering on tamper inputs \nLevel detection with filtering is performed by setting TAMPFLT to a non-zero value. A tamper \ndetection event is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive \n" }, { "page_number": 816, "page_indices": { "start_index": 1592122, "end_index": 1594941 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 816 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.3 RTC functional description", 804 ], [ 3, "26.3.13 Tamper detection", 814 ], [ 4, "TAMPER alternate function detection", 816 ], [ 3, "26.3.14 Calibration clock output", 816 ], [ 4, "Calibration alternate function output", 816 ], [ 3, "26.3.15 Alarm output", 816 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n816/1757\nRM0090 Rev 21\nsamples are observed at the level designated by the TAMPxTRG bits \n(TAMP1TRG/TAMP2TRG).\nThe TAMPER inputs are pre-charged through the I/O internal pull-up resistance before its \nstate is sampled, unless disabled by setting TAMPPUDIS to 1,The duration of the precharge \nis determined by the TAMPPRCH bits, allowing for larger capacitances on the tamper \ninputs.\nThe trade-off between tamper detection latency and power consumption through the pull-up \ncan be optimized by using TAMPFREQ to determine the frequency of the sampling for level \ndetection. \nNote:\nRefer to the datasheets for the electrical characteristics of the pull-up resistors.\nTAMPER alternate function detection\nThe TAMPER1 alternate function (RTC_TAMP1) can be mapped either to RTC_AF1(PC13) \nor RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in RTC_TAFCR register (see \nSection 26.6.17: RTC tamper and alternate function configuration register (RTC_TAFCR)). \nTAMPE bit must be cleared when TAMP1INSEL is modified to avoid unwanted setting of \nTAMPF. \nThe TAMPER 2 alternate function corresponds to RTC_TAMP2 pin.\n26.3.14 \nCalibration clock output\nWhen the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the \nRTC_CALIB device output. If the COSEL bit in the RTC_CR register is reset and \nPREDIV_A = 0x7F, the RTC_CALIB frequency is fRTCCLK/64. This corresponds to a \ncalibration output at 512 Hz for an RTCCLK frequency at 32.768 kHz. \nThe RTC_CALIB output is not impacted by the calibration value programmed in \nRTC_CALIBR register. The RTC_CALIB duty cycle is irregular: there is a light jitter on falling \nedges. It is therefore recommended to use rising edges.\nIf COSEL is set and (PREDIV_S+1) is a non-zero multiple of 256 (i.e: PREDIV_S[7:0] = \n0xFF), the RTC_CALIB frequency is fRTCCLK/(256 * (PREDIV_A+1)). This corresponds to a \ncalibration output at 1 Hz for prescaler default values (PREDIV_A = 0x7F, PREDIV_S = \n0xFF), with an RTCCLK frequency at 32.768 kHz. The 1 Hz output is affected when a shift \noperation is on going and may toggle during the shift operation (SHPF=1). \nCalibration alternate function output\nWhen the COE bit in the RTC_CR register is set to 1, the calibration alternate function \n(RTC_CALIB) is enabled on RTC_AF1.\nNote:\nWhen RTC_CALIB or RTC_ALARM is selected, RTC_AF1 is automatically configured in \noutput alternate function.\n26.3.15 \nAlarm output\nThree functions can be selected on Alarm output: ALRAF, ALRBF and WUTF. These \nfunctions reflect the contents of the corresponding flags in the RTC_ISR register. \nThe OSEL[1:0] control bits in the RTC_CR register are used to activate the alarm alternate \nfunction output (RTC_ALARM) in RTC_AF1, and to select the function which is output on \nRTC_ALARM.\n" }, { "page_number": 817, "page_indices": { "start_index": 1594941, "end_index": 1597128 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 817 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.3 RTC functional description", 804 ], [ 3, "26.3.15 Alarm output", 816 ], [ 4, "Alarm alternate function output", 817 ], [ 2, "26.4 RTC and low-power modes", 817 ], [ 2, "26.5 RTC interrupts", 817 ] ], "page_content": "RM0090 Rev 21\n817/1757\nRM0090\nReal-time clock (RTC)\n841\nThe polarity of the output is determined by the POL control bit in RTC_CR so that the \nopposite of the selected flag bit is output when POL is set to 1.\nAlarm alternate function output\nRTC_ALARM can be configured in output open drain or output push-pull using the control \nbit ALARMOUTTYPE in the RTC_TAFCR register.\nNote:\nOnce RTC_ALARM is enabled, it has priority over RTC_CALIB (COE bit is don't care on \nRTC_AF1).\nWhen RTC_CALIB or RTC_ALARM is selected, RTC_AF1 is automatically configured in \noutput alternate function.\n26.4 \nRTC and low-power modes\n \n26.5 \nRTC interrupts\nAll RTC interrupts are connected to the EXTI controller.\nTo enable the RTC Alarm interrupt, the following sequence is required:\n1.\nConfigure and enable the EXTI Line 17 in interrupt mode and select the rising edge \nsensitivity.\n2. \nConfigure and enable the RTC_Alarm IRQ channel in the NVIC.\n3. \nConfigure the RTC to generate RTC alarms (Alarm A or Alarm B).\nTo enable the RTC Wake-up interrupt, the following sequence is required:\n1.\nConfigure and enable the EXTI Line 22 in interrupt mode and select the rising edge \nsensitivity.\n2. \nConfigure and enable the RTC_WKUP IRQ channel in the NVIC.\n3. \nConfigure the RTC to generate the RTC wake-up timer event.\nTo enable the RTC Tamper interrupt, the following sequence is required:\n1.\nConfigure and enable the EXTI Line 21 in interrupt mode and select the rising edge \nsensitivity.\n2. \nConfigure and Enable the TAMP_STAMP IRQ channel in the NVIC.\n3. \nConfigure the RTC to detect the RTC tamper event.\nTo enable the RTC TimeStamp interrupt, the following sequence is required:\nTable 120. Effect of low-power modes on RTC\nMode \nDescription \nSleep\nNo effect \nRTC interrupts cause the device to exit the Sleep mode.\nStop\nThe RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC \ntamper event, RTC time stamp event, and RTC Wake-up cause the device to exit the Stop \nmode.\nStandby\nThe RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC \ntamper event, RTC time stamp event, and RTC Wake-up cause the device to exit the \nStandby mode.\n" }, { "page_number": 818, "page_indices": { "start_index": 1597128, "end_index": 1598003 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 818 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.5 RTC interrupts", 817 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n818/1757\nRM0090 Rev 21\n1.\nConfigure and enable the EXTI Line 21 in interrupt mode and select the rising edge \nsensitivity.\n2. \nConfigure and Enable the TAMP_STAMP IRQ channel in the NVIC.\n3. \nConfigure the RTC to detect the RTC timestamp event.\n \nTable 121. Interrupt control bits\nInterrupt event\nEvent flag\nEnable \ncontrol \nbit\nExit the \nSleep \nmode\nExit the \nStop \nmode\nExit the \nStandby \nmode\nAlarm A\nALRAF\nALRAIE\nyes\nyes(1)\n1.\nWake-up from STOP and Standby modes is possible only when the RTC clock source is LSE or LSI.\nyes(1)\nAlarm B\nALRBF\nALRBIE\nyes\nyes(1)\nyes(1)\nWake-up\nWUTF\nWUTIE\nyes\nyes(1)\nyes(1)\nTimeStamp\nTSF\nTSIE\nyes\nyes(1)\nyes(1)\nTamper1 detection\nTAMP1F\nTAMPIE\nyes\nyes(1)\nyes(1)\nTamper2 detection(2)\n2.\nIf RTC_TAMPER2 pin is present. Refer to device datasheet pinout.\nTAMP2F\nTAMPIE\nyes\nyes(1)\nyes(1)\n" }, { "page_number": 819, "page_indices": { "start_index": 1598003, "end_index": 1599531 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 819 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.1 RTC time register (RTC_TR)", 819 ] ], "page_content": "RM0090 Rev 21\n819/1757\nRM0090\nReal-time clock (RTC)\n841\n26.6 \nRTC registers\nRefer to Section 1.1: List of abbreviations for registers for registers for a list of abbreviations \nused in register descriptions.\nThe peripheral registers have to be accessed by words (32 bits).\n26.6.1 \nRTC time register (RTC_TR)\nThe RTC_TR is the calendar time shadow register. This register must be written in \ninitialization mode only. Refer to Calendar initialization and configuration on page 807 and \nReading the calendar on page 808.\nAddress offset: 0x00\nBackup domain reset value: 0x0000 0000\nSystem reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.\n \n \nNote:\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPM\nHT[1:0]\nHU[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nMNT[2:0]\nMNU[3:0]\nRes.\nST[2:0]\nSU[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31-24 Reserved\nBit 23 Reserved, must be kept at reset value.\nBit 22 PM: AM/PM notation\n0: AM or 24-hour format\n1: PM\nBits 21:20 HT[1:0]: Hour tens in BCD format\nBits 19:16 HU[3:0]: Hour units in BCD format\nBit 15 Reserved, must be kept at reset value.\nBits 14:12 MNT[2:0]: Minute tens in BCD format\nBit 11:8 MNU[3:0]: Minute units in BCD format\nBit 7 Reserved, must be kept at reset value.\nBits 6:4 ST[2:0]: Second tens in BCD format\nBits 3:0 SU[3:0]: Second units in BCD format\n" }, { "page_number": 820, "page_indices": { "start_index": 1599531, "end_index": 1600752 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 820 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.2 RTC date register (RTC_DR)", 820 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n820/1757\nRM0090 Rev 21\n26.6.2 \nRTC date register (RTC_DR)\nThe RTC_DR is the calendar date shadow register. This register must be written in \ninitialization mode only. Refer to Calendar initialization and configuration on page 807 and \nReading the calendar on page 808.\nAddress offset: 0x04\nBackup domain reset value: 0x0000 2101\nSystem reset: 0x0000 2101 when BYPSHAD = 0. Not affected when BYPSHAD = 1.\n \n \nNote:\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nYT[3:0]\nYU[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nWDU[2:0]\nMT\nMU[3:0]\nReserved\nDT[1:0]\nDU[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31-24 Reserved\nBits 23:20 YT[3:0]: Year tens in BCD format\nBits 19:16 YU[3:0]: Year units in BCD format\nBits 15:13 WDU[2:0]: Week day units\n000: forbidden\n001: Monday\n...\n111: Sunday\nBit 12 MT: Month tens in BCD format\nBits 11:8 MU: Month units in BCD format\nBits 7:6 Reserved, must be kept at reset value.\nBits 5:4 DT[1:0]: Date tens in BCD format\nBits 3:0 DU[3:0]: Date units in BCD format\n" }, { "page_number": 821, "page_indices": { "start_index": 1600752, "end_index": 1602745 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 821 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.3 RTC control register (RTC_CR)", 821 ] ], "page_content": "RM0090 Rev 21\n821/1757\nRM0090\nReal-time clock (RTC)\n841\n26.6.3 \nRTC control register (RTC_CR)\nAddress offset: 0x08\nBackup domain reset value: 0x0000 0000 \nSystem reset: not affected\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nCOE\nOSEL[1:0]\nPOL\nCOSEL\nBKP\nSUB1H ADD1H\nrw\nrw\nrw\nrw\nrw\nrw\nw\nw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTSIE\nWUTIE\nALRBIE ALRAIE\nTSE\nWUTE\nALRBE\nALRAE\nDCE\nFMT\nBYPS\nHAD\nREFCKON TSEDGE\nWUCKSEL[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value.\nBit 23 COE: Calibration output enable\nThis bit enables the RTC_CALIB output\n0: Calibration output disabled\n1: Calibration output enabled\nBits 22:21 OSEL[1:0]: Output selection\nThese bits are used to select the flag to be routed to RTC_ALARM output\n00: Output disabled\n01: Alarm A output enabled\n10:Alarm B output enabled\n11: Wake-up output enabled\nBit 20 POL: Output polarity\nThis bit is used to configure the polarity of RTC_ALARM output\n0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])\n1: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]).\nBit 19 COSEL: Calibration output selection\nWhen COE=1, this bit selects which signal is output on RTC_CALIB.\n0: Calibration output is 512 Hz\n1: Calibration output is 1 Hz\nThese frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default \nvalues (PREDIV_A=127 and PREDIV_S=255). Refer to Section 26.3.14: Calibration clock \noutput\nBit 18 BKP: Backup\nThis bit can be written by the user to memorize whether the daylight saving time change has \nbeen performed or not.\nBit 17 SUB1H: Subtract 1 hour (winter time change)\nWhen this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the \ncurrent hour is not 0. This bit is always read as 0.\nSetting this bit has no effect when current hour is 0.\n0: No effect\n1: Subtracts 1 hour to the current time. This can be used for winter time change.\n" }, { "page_number": 822, "page_indices": { "start_index": 1602745, "end_index": 1604499 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 822 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.3 RTC control register (RTC_CR)", 821 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n822/1757\nRM0090 Rev 21\nBit 16 ADD1H: Add 1 hour (summer time change)\nWhen this bit is set, 1 hour is added to the calendar time. This bit is always read as 0.\n0: No effect\n1: Adds 1 hour to the current time. This can be used for summer time change outside \ninitialization mode.\nBit 15 TSIE: Timestamp interrupt enable\n0: Timestamp Interrupt disable\n1: Timestamp Interrupt enable\nBit 14 WUTIE: Wake-up timer interrupt enable\n0: Wake-up timer interrupt disabled\n1: Wake-up timer interrupt enabled\nBit 13 ALRBIE: Alarm B interrupt enable\n0: Alarm B Interrupt disable\n1: Alarm B Interrupt enable\nBit 12 ALRAIE: Alarm A interrupt enable\n0: Alarm A interrupt disabled\n1: Alarm A interrupt enabled\nBit 11 TSE: Time stamp enable\n0: Time stamp disable\n1: Time stamp enable\nBit 10 WUTE: Wake-up timer enable\n0: Wake-up timer disabled\n1: Wake-up timer enabled\nNote: When the wake-up timer is disabled, wait for WUTWF=1 before enabling it again.\nBit 9 ALRBE: Alarm B enable\n0: Alarm B disabled\n1: Alarm B enabled\nBit 8 ALRAE: Alarm A enable\n0: Alarm A disabled\n1: Alarm A enabled\nBit 7 DCE: Coarse digital calibration enable\n0: Digital calibration disabled\n1: Digital calibration enabled\nPREDIV_A must be 6 or greater\nBit 6 FMT: Hour format\n0: 24 hour/day format\n1: AM/PM hour format\nBit 5 BYPSHAD: Bypass the shadow registers\n0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from \nthe shadow registers, which are updated once every two RTCCLK cycles.\n1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken \ndirectly from the calendar counters.\nNote: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, \nBYPSHAD must be set to ‘1’.\n" }, { "page_number": 823, "page_indices": { "start_index": 1604499, "end_index": 1606463 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 823 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.4 RTC initialization and status register (RTC_ISR)", 823 ] ], "page_content": "RM0090 Rev 21\n823/1757\nRM0090\nReal-time clock (RTC)\n841\nNote:\nWUT = Wake-up unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when \nWUCKSEL[2:1 = 11]. \nBits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1).\nBits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR \nWUTWF bit = 1.\nIt is recommended not to change the hour during the calendar hour increment as it could \nmask the incrementation of the calendar hour.\nADD1H and SUB1H changes are effective in the next second.\nTo avoid spuriously setting of TSF, TSE must be reset when TSEDGE is changed. \nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806.\n26.6.4 \nRTC initialization and status register (RTC_ISR)\nAddress offset: 0x0C\nBackup domain reset value: 0x0000 0007\nSystem reset value: Not affected except INIT, INITF and RSF which are cleared to 0.\n \nBit 4 REFCKON: Reference clock detection enable (50 or 60 Hz)\n0: Reference clock detection disabled\n1: Reference clock detection enabled\nNote: PREDIV_S must be 0x00FF.\nBit 3 TSEDGE: Timestamp event active edge\n0: TIMESTAMP rising edge generates a timestamp event\n1: TIMESTAMP falling edge generates a timestamp event\nTSE must be reset when TSEDGE is changed to avoid unwanted TSF setting\nBits 2:0 WUCKSEL[2:0]: Wake-up clock selection\n000: RTC/16 clock is selected\n001: RTC/8 clock is selected\n010: RTC/4 clock is selected\n011: RTC/2 clock is selected\n10x: ck_spre (usually 1 Hz) clock is selected\n11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value \n(see note below)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nRECAL \nPF\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nTAMP \n2F\nTAMP \n1F\nTSOVF\nTSF\nWUTF\nALRBF\nALRAF\nINIT\nINITF\nRSF\nINITS\nSHPF\nWUT \nWF\nALRB \nWF\nALRA \nWF\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrw\nr\nrc_w0\nr\nr\nr\nr\nr\n" }, { "page_number": 824, "page_indices": { "start_index": 1606463, "end_index": 1608874 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 824 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.4 RTC initialization and status register (RTC_ISR)", 823 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n824/1757\nRM0090 Rev 21\nBits 31:17 Reserved \nBit 16 RECALPF: Recalibration pending Flag\nThe RECALPF status flag is automatically set to ‘1’ when software writes to the RTC_CALR \nregister, indicating that the RTC_CALR register is blocked. When the new calibration \nsettings are taken into account, this bit returns to ‘0’. Refer to Section : Re-calibration on-the-\nfly.\nBit 15 Reserved, must be kept at reset value.\nBit 14 TAMP2F: TAMPER2 detection flag\nThis flag is set by hardware when a tamper detection event is detected on tamper input 2.\nIt is cleared by software writing 0.\nBit 13 TAMP1F: Tamper detection flag\nThis flag is set by hardware when a tamper detection event is detected.\nIt is cleared by software writing 0.\nBit 12 TSOVF: Timestamp overflow flag\nThis flag is set by hardware when a timestamp event occurs while TSF is already set.\nThis flag is cleared by software by writing 0. It is recommended to check and then clear \nTSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a \ntimestamp event occurs immediately before the TSF bit is cleared.\nBit 11 TSF: Timestamp flag\nThis flag is set by hardware when a timestamp event occurs.\nThis flag is cleared by software by writing 0.\nBit 10 WUTF: Wake-up timer flag\nThis flag is set by hardware when the wake-up auto-reload counter reaches 0.\nThis flag is cleared by software by writing 0.\nThis flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 \nagain.\nBit 9 ALRBF: Alarm B flag\nThis flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the \nAlarm B register (RTC_ALRMBR).\nThis flag is cleared by software by writing 0.\nBit 8 ALRAF: Alarm A flag\nThis flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the \nAlarm A register (RTC_ALRMAR).\nThis flag is cleared by software by writing 0.\nBit 7 INIT: Initialization mode\n0: Free running mode\n1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and \nprescaler register (RTC_PRER). Counters are stopped and start counting from the new \nvalue when INIT is reset.\nBit 6 INITF: Initialization flag\nWhen this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler \nregisters can be updated.\n0: Calendar registers update is not allowed\n1: Calendar registers update is allowed.\n" }, { "page_number": 825, "page_indices": { "start_index": 1608874, "end_index": 1611114 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 825 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.4 RTC initialization and status register (RTC_ISR)", 823 ] ], "page_content": "RM0090 Rev 21\n825/1757\nRM0090\nReal-time clock (RTC)\n841\nNote:\nThe ALRAF, ALRBF, WUTF and TSF bits are cleared 2 APB clock cycles after programming \nthem to 0.\nThis register is write protected (except for RTC_ISR[13:8] bits). The write access procedure \nis described in RTC register write protection on page 806.\nBit 5 RSF: Registers synchronization flag\nThis bit is set by hardware each time the calendar registers are copied into the shadow \nregisters (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in \ninitialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow \nregister mode (BYPSHAD=1). This bit can also be cleared by software.\n0: Calendar shadow registers not yet synchronized\n1: Calendar shadow registers synchronized\nBit 4 INITS: Initialization status flag\nThis bit is set by hardware when the calendar year field is different from 0 (backup domain \nreset value state).\n0: Calendar has not been initialized\n1: Calendar has been initialized\nBit 3 SHPF: Shift operation pending \n0: No shift operation is pending\n1: A shift operation is pending\nThis flag is set by hardware as soon as a shift operation is initiated by a write to the \nRTC_SHIFTR. It is cleared by hardware when the corresponding shift operation has been \nexecuted. Writing to SHPF has no effect.\nBit 2 WUTWF: Wake-up timer write flag\nThis bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in \nRTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The \nwake-up timer values can be changed when WUTE bit is cleared and WUTWF is set.\n0: Wake-up timer configuration update not allowed\n1: Wake-up timer configuration update allowed\nBit 1 ALRBWF: Alarm B write flag\nThis bit is set by hardware when Alarm B values can be changed, after the ALRBIE bit has \nbeen set to 0 in RTC_CR.\nIt is cleared by hardware in initialization mode.\n0: Alarm B update not allowed\n1: Alarm B update allowed.\nBit 0 ALRAWF: Alarm A write flag\nThis bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has \nbeen set to 0 in RTC_CR.\nIt is cleared by hardware in initialization mode.\n0: Alarm A update not allowed\n1: Alarm A update allowed\n" }, { "page_number": 826, "page_indices": { "start_index": 1611114, "end_index": 1612557 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 826 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.5 RTC prescaler register (RTC_PRER)", 826 ], [ 3, "26.6.6 RTC wake-up timer register (RTC_WUTR)", 826 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n826/1757\nRM0090 Rev 21\n26.6.5 \nRTC prescaler register (RTC_PRER)\nAddress offset: 0x10\nBackup domain reset value: 0x007F 00FF\nSystem reset: not affected\n \n \nNote:\nThis register must be written in initialization mode only. The initialization must be performed \nin two separate write accesses. Refer to Calendar initialization and configuration on \npage 807\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806.\n26.6.6 \nRTC wake-up timer register (RTC_WUTR)\nAddress offset: 0x14\nBackup domain reset value: 0x0000 FFFF\nSystem reset: not affected\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nPREDIV_A[6:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nPREDIV_S[14:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved\nBit 23 Reserved, must be kept at reset value.\nBits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor\nThis is the asynchronous division factor: \nck_apre frequency = RTCCLK frequency/(PREDIV_A+1)\nBit 15 Reserved, must be kept at reset value.\nBits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor\nThis is the synchronous division factor: \nck_spre frequency = ck_apre frequency/(PREDIV_S+1)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nWUT[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 827, "page_indices": { "start_index": 1612557, "end_index": 1614363 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 827 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.7 RTC calibration register (RTC_CALIBR)", 827 ] ], "page_content": "RM0090 Rev 21\n827/1757\nRM0090\nReal-time clock (RTC)\n841\n \nNote:\nThis register can be written only when WUTWF is set to 1 in RTC_ISR.\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806.\n26.6.7 \nRTC calibration register (RTC_CALIBR)\nAddress offset: 0x18\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected\n \n \nBits 31:16 Reserved\nBits 15:0 WUT[15:0]: Wake-up auto-reload value bits\nWhen the wake-up timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] \n+ 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the \nRTC_CR register\nWhen WUCKSEL[2] = 1, the wake-up timer becomes 17-bits and WUCKSEL[1] effectively \nbecomes WUT[16] the most-significant bit to be reloaded into the timer.\nNote: The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting \nWUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden. \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDCS\nReserved\nDC[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved\nBit 7 DCS: Digital calibration sign\n0: Positive calibration: calendar update frequency is increased\n1: Negative calibration: calendar update frequency is decreased\nBits 6:5 Reserved, must be kept at reset value.\nBits 4:0 DC[4:0]: Digital calibration\nDCS = 0 (positive calibration)\n00000: + 0 ppm\n00001: + 4 ppm (rounded value)\n00010: + 8 ppm (rounded value)\n..\n11111: + 126 ppm (rounded value)\nDCS = 1 (negative calibration)\n00000: − 0 ppm\n00001: − 2 ppm (rounded value)\n00010: − 4 ppm (rounded value)\n..\n11111: − 63 ppm (rounded value)\nRefer to Case of RTCCLK=32.768 kHz and PREDIV_A+1=128 on page 811 for the exact \nstep value.\n" }, { "page_number": 828, "page_indices": { "start_index": 1614363, "end_index": 1616082 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 828 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.8 RTC alarm A register (RTC_ALRMAR)", 828 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n828/1757\nRM0090 Rev 21\nNote:\nThis register can be written in initialization mode only (RTC_ISR/INITF = ‘1’).\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806.\n26.6.8 \nRTC alarm A register (RTC_ALRMAR)\nAddress offset: 0x1C\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMSK4\nWDSEL\nDT[1:0]\nDU[3:0]\nMSK3\n PM\nHT[1:0]\nHU[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMSK2\n MNT[2:0]\nMNU[3:0]\nMSK1\n ST[2:0]\nSU[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 MSK4: Alarm A date mask\n0: Alarm A set if the date/day match\n1: Date/day don’t care in Alarm A comparison\nBit 30 WDSEL: Week day selection\n0: DU[3:0] represents the date units\n1: DU[3:0] represents the week day. DT[1:0] is don’t care.\nBits 29:28 DT[1:0]: Date tens in BCD format.\nBits 27:24 DU[3:0]: Date units or day in BCD format.\nBit 23 MSK3: Alarm A hours mask\n0: Alarm A set if the hours match\n1: Hours don’t care in Alarm A comparison\nBit 22 PM: AM/PM notation\n0: AM or 24-hour format\n1: PM\nBits 21:20 HT[1:0]: Hour tens in BCD format.\nBits 19:16 HU[3:0]: Hour units in BCD format.\nBit 15 MSK2: Alarm A minutes mask\n0: Alarm A set if the minutes match\n1: Minutes don’t care in Alarm A comparison\nBits 14:12 MNT[2:0]: Minute tens in BCD format.\nBits 11:8 MNU[3:0]: Minute units in BCD format.\nBit 7 MSK1: Alarm A seconds mask\n0: Alarm A set if the seconds match\n1: Seconds don’t care in Alarm A comparison\nBits 6:4 ST[2:0]: Second tens in BCD format.\nBits 3:0 SU[3:0]: Second units in BCD format.\n" }, { "page_number": 829, "page_indices": { "start_index": 1616082, "end_index": 1617823 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 829 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.9 RTC alarm B register (RTC_ALRMBR)", 829 ] ], "page_content": "RM0090 Rev 21\n829/1757\nRM0090\nReal-time clock (RTC)\n841\nNote:\nThis register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization \nmode.\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806.\n26.6.9 \nRTC alarm B register (RTC_ALRMBR)\nAddress offset: 0x20\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nMSK4\nWDSEL\nDT[1:0]\nDU[3:0]\nMSK3\n PM\nHT[1:0]\nHU[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMSK2\n MNT[2:0]\nMNU[3:0]\nMSK1\n ST[2:0]\nSU[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 MSK4: Alarm B date mask\n0: Alarm B set if the date and day match\n1: Date and day don’t care in Alarm B comparison\nBit 30 WDSEL: Week day selection\n0: DU[3:0] represents the date units\n1: DU[3:0] represents the week day. DT[1:0] is don’t care.\nBits 29:28 DT[1:0]: Date tens in BCD format\nBits 27:24 DU[3:0]: Date units or day in BCD format\nBit 23 MSK3: Alarm B hours mask\n0: Alarm B set if the hours match\n1: Hours don’t care in Alarm B comparison\nBit 22 PM: AM/PM notation\n0: AM or 24-hour format\n1: PM\nBits 21:20 HT[1:0]: Hour tens in BCD format\nBits 19:16 HU[3:0]: Hour units in BCD format\nBit 15 MSK2: Alarm B minutes mask\n0: Alarm B set if the minutes match\n1: Minutes don’t care in Alarm B comparison\nBits 14:12 MNT[2:0]: Minute tens in BCD format\nBits 11:8 MNU[3:0]: Minute units in BCD format\nBit 7 MSK1: Alarm B seconds mask\n0: Alarm B set if the seconds match\n1: Seconds don’t care in Alarm B comparison\nBits 6:4 ST[2:0]: Second tens in BCD format\nBits 3:0 SU[3:0]: Second units in BCD format\n" }, { "page_number": 830, "page_indices": { "start_index": 1617823, "end_index": 1619388 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 830 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.10 RTC write protection register (RTC_WPR)", 830 ], [ 3, "26.6.11 RTC sub second register (RTC_SSR)", 830 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n830/1757\nRM0090 Rev 21\nNote:\nThis register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization \nmode.\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806.\n26.6.10 \nRTC write protection register (RTC_WPR)\nAddress offset: 0x24\nBackup domain reset value: 0x0000 0000\n \n \n26.6.11 \nRTC sub second register (RTC_SSR)\nAddress offset: 0x28\nBackup domain reset value: 0x0000 0000\nSystem reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nKEY\nw\nw\nw\nw\nw\nw\nw\nw\nBits 31:8 Reserved, must be kept at reset value.\nBits 7:0 KEY: Write protection key\nThis byte is written by software.\nReading this byte always returns 0x00.\nRefer to RTC register write protection for a description of how to unlock RTC register write \nprotection.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSS[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 Reserved\nBits 15:0 SS: Sub second value\nSS[15:0] is the value in the synchronous prescaler’s counter. The fraction of a second is \ngiven by the formula below:\nSecond fraction = ( PREDIV_S - SS ) / ( PREDIV_S + 1 )\nNote: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct \ntime/date is one second less than as indicated by RTC_TR/RTC_DR.\n" }, { "page_number": 831, "page_indices": { "start_index": 1619388, "end_index": 1621449 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 831 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.12 RTC shift control register (RTC_SHIFTR)", 831 ], [ 3, "26.6.13 RTC time stamp time register (RTC_TSTR)", 831 ] ], "page_content": "RM0090 Rev 21\n831/1757\nRM0090\nReal-time clock (RTC)\n841\n26.6.12 \nRTC shift control register (RTC_SHIFTR)\nAddress offset: 0x2C\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected\n \n \nNote:\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806\n26.6.13 \nRTC time stamp time register (RTC_TSTR)\nAddress offset: 0x30\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nADD1S\nReserved\nw\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nSUBFS[14:0]\nr\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBit 31 ADD1S: Add one second\n0: No effect\n1: Add one second to the clock/calendar\nThis bit is write only and is always read as zero. Writing to this bit has no effect when a shift \noperation is pending (when SHPF=1, in RTC_ISR).\nThis function is intended to be used with SUBFS (see description below) in order to \neffectively add a fraction of a second to the clock in an atomic operation.\nBits 30:15 Reserved\nBits 14:0 SUBFS: Subtract a fraction of a second\nThese bits are write only and is always read as zero. Writing to this bit has no effect when a \nshift operation is pending (when SHPF=1, in RTC_ISR).\nThe value which is written to SUBFS is added to the synchronous prescaler’s counter. Since \nthis counter counts down, this operation effectively subtracts from (delays) the clock by:\nDelay (seconds) = SUBFS / ( PREDIV_S + 1 )\nA fraction of a second can effectively be added to the clock (advancing the clock) when the \nADD1S function is used in conjunction with SUBFS, effectively advancing the clock by:\nAdvance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) .\nNote: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be \nsure that the shadow registers have been updated with the shifted time.\nRefer to Section 26.3.8: RTC synchronization.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n PM\nHT[1:0]\nHU[3:0]\nr\nr\nr\nr\nr\nr\nr\n" }, { "page_number": 832, "page_indices": { "start_index": 1621449, "end_index": 1622981 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 832 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.14 RTC time stamp date register (RTC_TSDR)", 832 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n832/1757\nRM0090 Rev 21\n \nNote:\nThe content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when \nTSF bit is reset.\n26.6.14 \nRTC time stamp date register (RTC_TSDR)\nAddress offset: 0x34\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected\n \n \nNote:\nThe content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when \nTSF bit is reset.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nMNT[2:0]\nMNU[3:0]\nRes.\nST[2:0]\nSU[3:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:23 Reserved, must be kept at reset value.\nBit 22 PM: AM/PM notation\n0: AM or 24-hour format\n1: PM\nBits 21:20 HT[1:0]: Hour tens in BCD format.\nBits 19:16 HU[3:0]: Hour units in BCD format.\nBit 15\nReserved, must be kept at reset value.\nBits 14:12 MNT[2:0]: Minute tens in BCD format.\nBits 11:8 MNU[3:0]: Minute units in BCD format.\nBit 7 Reserved, must be kept at reset value.\nBits 6:4 ST[2:0]: Second tens in BCD format.\nBits 3:0 SU[3:0]: Second units in BCD format.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nWDU[1:0]\nMT\nMU[3:0]\nReserved\nDT[1:0]\nDU[3:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:13 WDU[1:0]: Week day units\nBit 12 MT: Month tens in BCD format\nBits 11:8 MU[3:0]: Month units in BCD format\nBits 7:6 Reserved, must be kept at reset value.\nBits 5:4 DT[1:0]: Date tens in BCD format\nBit 3:0 DU[3:0]: Date units in BCD format\n" }, { "page_number": 833, "page_indices": { "start_index": 1622981, "end_index": 1624013 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 833 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.15 RTC timestamp sub second register (RTC_TSSSR)", 833 ], [ 3, "26.6.16 RTC calibration register (RTC_CALR)", 833 ] ], "page_content": "RM0090 Rev 21\n833/1757\nRM0090\nReal-time clock (RTC)\n841\n26.6.15 \nRTC timestamp sub second register (RTC_TSSSR)\nAddress offset: 0x38\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected\n \n \nNote:\nThe content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the \nRTC_ISR/TSF bit is reset.\n26.6.16 \nRTC calibration register (RTC_CALR)\nAddress offset: 0x3C\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSS[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 Reserved\nBits 15:0 SS: Sub second value\nSS[15:0] is the value of the synchronous prescaler’s counter when the timestamp event \noccurred. \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCALP\nCALW8 CALW16\nReserved\nCALM[8:0]\nrw\nrw\nrw\nr\nr\nr\nr\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 834, "page_indices": { "start_index": 1624013, "end_index": 1625709 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 834 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.16 RTC calibration register (RTC_CALR)", 833 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n834/1757\nRM0090 Rev 21\n \nNote:\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806\nBits 31:16 Reserved\nBit 15 CALP: Increase frequency of RTC by 488.5 ppm\n0: No RTCCLK pulses are added.\n1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency increased by \n488.5 ppm). \nThis feature is intended to be used in conjunction with CALM, which lowers the frequency of \nthe calendar with a fine resolution. if the input frequency is 32768 Hz, the number of \nRTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - \nCALM.\nRefer to Section 26.3.11: RTC smooth digital calibration.\nBit 14 CALW8: Use an 8-second calibration cycle period\nWhen CALW8 is set to ‘1’, the 8-second calibration cycle period is selected. \nCALM[1:0] are stuck at “00” when CALW8=’1’.\nRefer to Section 26.3.11: RTC smooth digital calibration.\nBit 13 CALW16: Use a 16-second calibration cycle period\nWhen CALW16 is set to ‘1’, the 16-second calibration cycle period is selected. This bit must \nnot be set to ‘1’ if CALW8=1.\nNote: CALM[0] is stuck at ‘0’ when CALW16=’1’.\nRefer to Section 26.3.11: RTC smooth digital calibration.\nBits 12:9 Reserved\nBits 8:0 CALM[8:0]: Calibration minus\nThe frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 \nseconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar \nwith a resolution of 0.9537 ppm.\nTo increase the frequency of the calendar, this feature should be used in conjunction with \nCALP.\nSee Section 26.3.11: RTC smooth digital calibration on page 812.\n" }, { "page_number": 835, "page_indices": { "start_index": 1625709, "end_index": 1627214 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 835 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.17 RTC tamper and alternate function configuration register (RTC_TAFCR)", 835 ] ], "page_content": "RM0090 Rev 21\n835/1757\nRM0090\nReal-time clock (RTC)\n841\n26.6.17 \nRTC tamper and alternate function configuration register\n(RTC_TAFCR)\nAddress offset: 0x40\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nALARMOUT\nTYPE\nTSIN\nSEL\nTAMP1\nINSEL\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTAMP-\nPUDIS\nTAMP-\nPRCH[1:0]\nTAMPFLT[1:0]\nTAMPFREQ[2:0]\nTAMPT\nS\nReserved\nTAMP2\n-TRG\nTAMP2\nE\nTAMPIE\nTAMP1\nTRG\nTAMP1\nE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:19 Reserved. Always read as 0.\nBit 18 ALARMOUTTYPE: RTC_ALARM output type\n0: RTC_ALARM is an open-drain output\n1: RTC_ALARM is a push-pull output\nBit 17 TSINSEL: TIMESTAMP mapping\n0: RTC_AF1 used as TIMESTAMP\n1: RTC_AF2 used as TIMESTAMP\nBit 16 TAMP1INSEL: TAMPER1 mapping\n0: RTC_AF1 used as TAMPER1\n1: RTC_AF2 used as TAMPER1\nNote: TAMP1E must be reset when TAMP1INSEL is changed to avoid unwanted setting of \nTAMP1F.\nBit 15 TAMPPUDIS: TAMPER pull-up disable\nThis bit determines if each of the tamper pins are pre-charged before each sample.\n0: Precharge tamper pins before sampling (enable internal pull-up)\n1: Disable precharge of tamper pins\nNote:\nBits 14:13 TAMPPRCH[1:0]: Tamper precharge duration\nThese bit determines the duration of time during which the pull-up/is activated before each \nsample. TAMPPRCH is valid for each of the tamper inputs.\n0x0: 1 RTCCLK cycle\n0x1: 2 RTCCLK cycles\n0x2: 4 RTCCLK cycles\n0x3: 8 RTCCLK cycles\n" }, { "page_number": 836, "page_indices": { "start_index": 1627214, "end_index": 1629142 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 836 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.17 RTC tamper and alternate function configuration register (RTC_TAFCR)", 835 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n836/1757\nRM0090 Rev 21\nBits 12:11 TAMPFLT[1:0]: Tamper filter count\nThese bits determines the number of consecutive samples at the specified level \n(TAMP*TRG) necessary to activate a Tamper event. TAMPFLT is valid for each of the tamper \ninputs.\n0x0: Tamper is activated on edge of tamper input transitions to the active level (no internal \npull-up on tamper input).\n0x1: Tamper is activated after 2 consecutive samples at the active level.\n0x2: Tamper is activated after 4 consecutive samples at the active level.\n0x3: Tamper is activated after 8 consecutive samples at the active level.\nBits 10:8 TAMPFREQ[2:0]: Tamper sampling frequency\nDetermines the frequency at which each of the tamper inputs are sampled.\n0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)\n0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)\n0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)\n0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)\n0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)\n0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)\n0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)\n0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)\nBit 7 TAMPTS: Activate timestamp on tamper detection event\n0: Tamper detection event does not cause a timestamp to be saved\n1: Save timestamp on tamper detection event\nTAMPTS is valid even if TSE=0 in the RTC_CR register. \nBits 6:5 Reserved. Always read as 0.\nBit 4 TAMP2TRG: Active level for tamper 2\nif TAMPFLT != 00 \n0: TAMPER2 staying low triggers a tamper detection event.\n1: TAMPER2 staying high triggers a tamper detection event.\nif TAMPFLT = 00:\n0: TAMPER2 rising edge triggers a tamper detection event.\n1: TAMPER2 falling edge triggers a tamper detection event.\nBit 3 TAMP2E: Tamper 2 detection enable\n0: Tamper 2 detection disabled\n1: Tamper 2 detection enabled\nBit 2 TAMPIE: Tamper interrupt enable\n0: Tamper interrupt disabled\n1: Tamper interrupt enabled\n" }, { "page_number": 837, "page_indices": { "start_index": 1629142, "end_index": 1631242 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 837 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.18 RTC alarm A sub second register (RTC_ALRMASSR)", 837 ] ], "page_content": "RM0090 Rev 21\n837/1757\nRM0090\nReal-time clock (RTC)\n841\n26.6.18 \nRTC alarm A sub second register (RTC_ALRMASSR)\nAddress offset: 0x44\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected \n \n \nBit 1 TAMP1TRG: Active level for tamper 1\nif TAMPFLT != 00 \n0: TAMPER1 staying low triggers a tamper detection event.\n1: TAMPER1 staying high triggers a tamper detection event.\nif TAMPFLT = 00:\n0: TAMPER1 rising edge triggers a tamper detection event.\n1: TAMPER1 falling edge triggers a tamper detection event.\nCaution: When TAMPFLT = 0, TAMPxE must be reset when TAMPxTRG is changed to avoid \nspuriously setting TAMPxF.\nBit 0 TAMP1E: Tamper 1 detection enable\n0: Tamper 1 detection disabled\n1: Tamper 1 detection enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nMASKSS[3:0]\nReserved\nr\nr\nr\nr\nrw\nrw\nrw\nrw\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSS[14:0]\nr\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nw\nrw\nrw\nBits 31:28 Reserved\nBits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit\n0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is \nincremented (assuming that the rest of the fields match).\n1: SS[14:1] are don’t care in Alarm A comparison. Only SS[0] is compared.\n2: SS[14:2] are don’t care in Alarm A comparison. Only SS[1:0] are compared.\n3: SS[14:3] are don’t care in Alarm A comparison. Only SS[2:0] are compared.\n...\n12: SS[14:12] are don’t care in Alarm A comparison. SS[11:0] are compared.\n13: SS[14:13] are don’t care in Alarm A comparison. SS[12:0] are compared.\n14: SS[14] is don’t care in Alarm A comparison. SS[13:0] are compared.\n15: All 15 SS bits are compared and must match to activate alarm.\nThe overflow bits of the synchronous counter (bits 15) is never compared. This bit can be \ndifferent from 0 only after a shift operation.\nBits 23:15 Reserved\nBits 14:0 SS[14:0]: Sub seconds value\nThis value is compared with the contents of the synchronous prescaler’s counter to \ndetermine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.\n" }, { "page_number": 838, "page_indices": { "start_index": 1631242, "end_index": 1633285 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 838 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.19 RTC alarm B sub second register (RTC_ALRMBSSR)", 838 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n838/1757\nRM0090 Rev 21\nNote:\nThis register can be written only when ALRAE is reset in RTC_CR register, or in initialization \nmode.\nThis register is write protected. The write access procedure is described in RTC register \nwrite protection on page 806\n26.6.19 \nRTC alarm B sub second register (RTC_ALRMBSSR)\nAddress offset: 0x48\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected \n \n \nNote:\nThis register can be written only when ALRBIE is reset in RTC_CR register, or in \ninitialization mode.\nThis register is write protected.The write access procedure is described in Section : RTC \nregister write protection\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nMASKSS[3:0]\nReserved\nr\nr\nr\nr\nrw\nrw\nrw\nrw\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSS[14:0]\nr\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nw\nrw\nrw\nBits 31:28 Reserved\nBits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit\n0x0: No comparison on sub seconds for Alarm B. The alarm is set when the seconds unit is \nincremented (assuming that the rest of the fields match).\n0x1: SS[14:1] are don’t care in Alarm B comparison. Only SS[0] is compared.\n0x2: SS[14:2] are don’t care in Alarm B comparison. Only SS[1:0] are compared.\n0x3: SS[14:3] are don’t care in Alarm B comparison. Only SS[2:0] are compared.\n...\n0xC: SS[14:12] are don’t care in Alarm B comparison. SS[11:0] are compared.\n0xD: SS[14:13] are don’t care in Alarm B comparison. SS[12:0] are compared.\n0xE: SS[14] is don’t care in Alarm B comparison. SS[13:0] are compared.\n0xF: All 15 SS bits are compared and must match to activate alarm.\nThe overflow bits of the synchronous counter (bits 15) is never compared. This bit can be \ndifferent from 0 only after a shift operation.\nBits 23:15 Reserved\nBits 14:0 SS[14:0]: Sub seconds value\nThis value is compared with the contents of the synchronous prescaler’s counter to \ndetermine if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared.\n" }, { "page_number": 839, "page_indices": { "start_index": 1633285, "end_index": 1635141 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 839 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.20 RTC backup registers (RTC_BKPxR)", 839 ], [ 3, "26.6.21 RTC register map", 839 ] ], "page_content": "RM0090 Rev 21\n839/1757\nRM0090\nReal-time clock (RTC)\n841\n26.6.20 \nRTC backup registers (RTC_BKPxR)\nAddress offset: 0x50 to 0x9C\nBackup domain reset value: 0x0000 0000\nSystem reset: not affected \n \n \n26.6.21 \nRTC register map\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nBKP[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nBKP[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nw\nrw\nrw\nBits 31:0 BKP[31:0]\nThe application can write or read data to and from these registers. \nThey are powered-on by VBAT when VDD is switched off, so that they are not reset by \nSystem reset, and their contents remain valid when the device operates in low-power mode. \nThis register is reset on a tamper detection event, as long as TAMPxF=1.\nTable 122. RTC register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nRTC_TR\nReserved\nPM\nHT\n[1:0]\nHU[3:0]\nReserved\nMNT[2:0]\nMNU[3:0]\nReserved\nST[2:0]\nSU[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nRTC_DR\nReserved\nYT[3:0]\nYU[3:0]\nWDU[2:0]\nMT\nMU[3:0]\nReserved\nDT\n[1:0]\nDU[3:0]\nReset value\n0\n0\n1\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n1\n0x08\nRTC_CR\nReserved\nCOE\nOSEL\n[1:0]\nPOL\nCOSEL\nBKP\nSUB1H\nADD1H\nTSIE\nWUTIE\nALRBIE\nALRAIE\nTSE\nWUTE\nALRBE\nALRAE\nDCE\nFMT\nBYPSHAD\nREFCKON\nTSEDGE\nWCKSEL\n[2:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nRTC_ISR\nReserved\nTAMP2F\nTAMP1F\nTSOVF\nTSF\nWUTF\nALRBF\nALRAF\nINIT\nINITF\nRSF\nINITS\nSHPF\nWUTWF\nALRBWF\nALRAWF\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n1\n0x10\nRTC_PRER\nReserved\nPREDIV_A[6:0]\nReserved\nPREDIV_S[14:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n1\n1\n1\n1\n1\n0x14\nRTC_WUTR\nReserved\nWUT[15:0]\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x18\nRTC_CALIBR\nReserved\nDCS\nReserved\nDC[4:0]\nReset value\n0\n0\n0\n0\n0\n0\n" }, { "page_number": 840, "page_indices": { "start_index": 1635141, "end_index": 1636932 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 840 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.21 RTC register map", 839 ] ], "page_content": "Real-time clock (RTC)\nRM0090\n840/1757\nRM0090 Rev 21\n0x1C\nRTC_ALRMAR\nMSK4\nWDSEL\nDT\n[1:0]\nDU[3:0]\nMSK3\nPM\nHT\n[1:0]\nHU[3:0]\nMSK2\nMNT[2:0]\nMNU[3:0]\nMSK1\nST[2:0]\nSU[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nRTC_ALRMBR\nMSK4\nWDSEL\nDT\n[1:0]\nDU[3:0]\nMSK3\nPM\nHT\n[1:0]\nHU[3:0]\nMSK2\nMNT[2:0]\nMNU[3:0]\nMSK2\nST[2:0]\nSU[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x24\nRTC_WPR\nReserved\nKEY[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nRTC_SSR\nReserved\nSS[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x2C\nRTC_SHIFTR\nADD1S\nReserved\nSUBFS[14:0]\nReset value\n0\n0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0x30\nRTC_TSTR\nReserved\nPM\nHT[1:0]\nHU[3:0]\nReserved\nMNT[2:0]\nMNU[3:0]\nReserved\nST[2:0]\nSU[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x38\nRTC_TSSSR\nReserved\nSS[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x3C\nRTC_ CALR\nReserved\nCALP\nCALW8\nCALW16\nReserved\nCALM[8:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x40\nRTC_TAFCR\nReserved\nALARMOUTTYPE\nTSINSEL\nTAMP1INSEL\nTAMPPUDIS\nTAMPPRCH[1:0]\nTAMPFLT[1:0]\nTAMPFREQ[2:0]\nTAMPTS\nReserved\nTAMP2TRG\nTAMP2E\nTAMPIE\nTAMP1ETRG\nTAMP1E\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x44\nRTC_ \nALRMASSR\nReserved\nMASKSS[3:0]\nReserved\nSS[14:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x48\nRTC_ \nALRMBSSR\nReserved\nMASKSS[3:0]\nReserved\nSS[14:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x50\nto 0x9C\nRTC_BKP0R\nBKP[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nto \nRTC_BKP19R\nBKP[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 122. RTC register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 841, "page_indices": { "start_index": 1636932, "end_index": 1637302 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 841 }, "toc_details": [ [ 1, "26 Real-time clock (RTC)", 801 ], [ 2, "26.6 RTC registers", 819 ], [ 3, "26.6.21 RTC register map", 839 ] ], "page_content": "RM0090 Rev 21\n841/1757\nRM0090\nReal-time clock (RTC)\n841\nRefer to Section 2.3: Memory map for the register boundary addresses.\nCaution:\nIn Table 122, the reset value is the value after a backup domain reset. The majority of the \nregisters are not affected by a system reset. For more information, please refer to \nSection 26.3.7: Resetting the RTC.\n" }, { "page_number": 842, "page_indices": { "start_index": 1637302, "end_index": 1639073 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 842 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.1 I2C introduction", 842 ], [ 2, "27.2 I2C main features", 842 ] ], "page_content": "Inter-integrated circuit (I2C) interface\nRM0090\n842/1757\nRM0090 Rev 21\n27 \nInter-integrated circuit (I2C) interface\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n27.1 \nI2C introduction\nI2C (inter-integrated circuit) bus Interface serves as an interface between the microcontroller \nand the serial I2C bus. It provides multimaster capability, and controls all I2C bus-specific \nsequencing, protocol, arbitration and timing. It supports the standard mode (Sm, up to \n100 kHz) and Fm mode (Fm, up to 400 kHz). \nIt may be used for a variety of purposes, including CRC generation and verification, SMBus \n(system management bus) and PMBus (power management bus).\nDepending on specific device implementation DMA capability can be available for reduced \nCPU overload.\n27.2 \nI2C main features\n•\nParallel-bus/I2C protocol converter\n•\nMultimaster capability: the same interface can act as Master or Slave\n•\nI2C Master features:\n–\nClock generation\n–\nStart and Stop generation\n•\nI2C Slave features:\n–\nProgrammable I2C Address detection\n–\nDual Addressing Capability to acknowledge 2 slave addresses\n–\nStop bit detection\n•\nGeneration and detection of 7-bit/10-bit addressing and General Call\n•\nSupports different communication speeds: \n–\nStandard Speed (up to 100 kHz)\n–\nFast Speed (up to 400 kHz)\n•\nAnalog noise filter \n•\nProgrammable digital noise filter for STM32F42xxx and STM32F43xxx\n•\nStatus flags:\n–\nTransmitter/Receiver mode flag\n–\nEnd-of-Byte transmission flag\n–\nI2C busy flag\n•\nError flags:\n–\nArbitration lost condition for master mode\n–\nAcknowledgment failure after address/ data transmission\n–\nDetection of misplaced start or stop condition\n–\nOverrun/Underrun if clock stretching is disabled\n•\n2 Interrupt vectors: \n" }, { "page_number": 843, "page_indices": { "start_index": 1639073, "end_index": 1641247 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 843 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.1 Mode selection", 843 ], [ 4, "Communication flow", 843 ] ], "page_content": "RM0090 Rev 21\n843/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\n–\n1 Interrupt for successful address/ data communication\n–\n1 Interrupt for error condition\n•\nOptional clock stretching\n•\n1-byte buffer with DMA capability\n•\nConfigurable PEC (packet error checking) generation or verification:\n–\nPEC value can be transmitted as last byte in Tx mode\n–\nPEC error checking for last received byte\n•\nSMBus 2.0 Compatibility:\n–\n25 ms clock low timeout delay\n–\n10 ms master cumulative clock low extend time\n–\n25 ms slave cumulative clock low extend time\n–\nHardware PEC generation/verification with ACK control\n–\nAddress Resolution Protocol (ARP) supported\n•\nPMBus Compatibility\nNote:\nSome of the above features may not be available in certain products. The user should refer \nto the product data sheet, to identify the specific features supported by the I2C interface \nimplementation.\n27.3 \nI2C functional description\nIn addition to receiving and transmitting data, this interface converts it from serial to parallel \nformat and vice versa. The interrupts are enabled or disabled by software. The interface is \nconnected to the I2C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected \nwith a standard (up to 100 kHz) or fast (up to 400 kHz) I2C bus. \n27.3.1 \nMode selection\nThe interface can operate in one of the four following modes:\n•\nSlave transmitter\n•\nSlave receiver\n•\nMaster transmitter\n•\nMaster receiver\nBy default, it operates in slave mode. The interface automatically switches from slave to \nmaster, after it generates a START condition and from master to slave, if an arbitration loss \nor a Stop generation occurs, allowing multimaster capability.\nCommunication flow\nIn Master mode, the I2C interface initiates a data transfer and generates the clock signal. A \nserial data transfer always begins with a start condition and ends with a stop condition. Both \nstart and stop conditions are generated in master mode by software.\nIn Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and \nthe General Call address. The General Call address detection may be enabled or disabled \nby software. \n" }, { "page_number": 844, "page_indices": { "start_index": 1641247, "end_index": 1642055 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 844 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.1 Mode selection", 843 ], [ 4, "Communication flow", 843 ] ], "page_content": "Inter-integrated circuit (I2C) interface\nRM0090\n844/1757\nRM0090 Rev 21\nData and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the \nstart condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is \nalways transmitted in Master mode. \nA 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must \nsend an acknowledge bit to the transmitter. Refer to Figure 238.\nFigure 238. I2C bus protocol\nAcknowledge may be enabled or disabled by software. The I2C interface addresses (dual \naddressing 7-bit/ 10-bit and/or general call address) can be selected by software. \nThe block diagram of the I2C interface is shown in Figure 239. \nMS19854V1\nSDA\nSCL\nStart\ncondition\nStop\ncondition\nMSB\nACK\n1\n2\n8\n9\n" }, { "page_number": 845, "page_indices": { "start_index": 1642055, "end_index": 1642526 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 845 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.1 Mode selection", 843 ], [ 4, "Communication flow", 843 ] ], "page_content": "RM0090 Rev 21\n845/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nFigure 239. I2C block diagram for STM32F40x/41x \nData shift register\nComparator\nOwn address register\nClock control \nStatus registers \nControl registers \nControl \nClock\ncontrol\nData\ncontrol\nSCL\nlogic\nDual address register\nData register\nPEC register\nInterrupts\nPEC calculation\nSMBA\nSDA\nRegister (CCR)\n(SR1&SR2)\n(CR1&CR2)\nDMA requests & ACK\nMS30035V1\nNoise\nfilter\nNoise\nfilter\n" }, { "page_number": 846, "page_indices": { "start_index": 1642526, "end_index": 1643862 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 846 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.2 I2C slave mode", 846 ] ], "page_content": "Inter-integrated circuit (I2C) interface\nRM0090\n846/1757\nRM0090 Rev 21\nFigure 240. I2C block diagram for STM32F42x/43x\n1.\nSMBA is an optional signal in SMBus mode. This signal is not applicable if SMBus is disabled.\n27.3.2 \nI2C slave mode\nBy default the I2C interface operates in Slave mode. To switch from default Slave mode to \nMaster mode a Start condition generation is needed.\nThe peripheral input clock must be programmed in the I2C_CR2 register in order to \ngenerate correct timings. The peripheral input clock frequency must be at least:\n•\n2 MHz in Sm mode\n•\n4 MHz in Fm mode \nAs soon as a start condition is detected, the address is received from the SDA line and sent \nto the shift register. Then it is compared with the address of the interface (OAR1) and with \nOAR2 (if ENDUAL=1) or the General Call address (if ENGC = 1). \nNote:\nIn 10-bit addressing mode, the comparison includes the header sequence (11110xx0), \nwhere xx denotes the two most significant bits of the address.\nData shift register\nComparator\nOwn address register\nClock control \nStatus registers \nControl registers \nControl \nClock\ncontrol\nData\ncontrol\nSCL\nlogic\nDual address register\nData register\nPEC register\nInterrupts\nPEC calculation\nSMBA\nSDA\nRegister (CCR)\n(SR1&SR2)\n(CR1&CR2)\nDMA requests & ACK\nMS30035V1\nNoise\nfilter\nNoise\nfilter\n" }, { "page_number": 847, "page_indices": { "start_index": 1643862, "end_index": 1645544 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 847 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.2 I2C slave mode", 846 ], [ 4, "Slave transmitter", 847 ] ], "page_content": "RM0090 Rev 21\n847/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nHeader or address not matched: the interface ignores it and waits for another Start \ncondition.\nHeader matched (10-bit mode only): the interface generates an acknowledge pulse if the \nACK bit is set and waits for the 8-bit slave address.\nAddress matched: the interface generates in sequence:\n•\nAn acknowledge pulse if the ACK bit is set\n•\nThe ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit is \nset. \n•\nIf ENDUAL=1, the software has to read the DUALF bit to check which slave address \nhas been acknowledged.\nIn 10-bit mode, after receiving the address sequence the slave is always in Receiver mode. \nIt enters Transmitter mode on receiving a repeated Start condition followed by the header \nsequence with matching address bits and the least significant bit set (11110xx1).\nThe TRA bit indicates whether the slave is in Receiver or Transmitter mode.\nSlave transmitter\nFollowing the address reception and after clearing ADDR, the slave sends bytes from the \nDR register to the SDA line via the internal shift register.\nThe slave stretches SCL low until ADDR is cleared and DR filled with the data to be sent \n(see Figure 241 Transfer sequencing EV1 EV3).\nWhen the acknowledge pulse is received: \n•\nThe TxE bit is set by hardware with an interrupt if the ITEVFEN and the ITBUFEN bits \nare set.\nIf TxE is set and some data were not written in the I2C_DR register before the end of the \nnext data transmission, the BTF bit is set and the interface waits until BTF is cleared by a \nread to I2C_SR1 followed by a write to the I2C_DR register, stretching SCL low.\n" }, { "page_number": 848, "page_indices": { "start_index": 1645544, "end_index": 1647182 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 848 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.2 I2C slave mode", 846 ], [ 4, "Slave receiver", 848 ] ], "page_content": "Inter-integrated circuit (I2C) interface\nRM0090\n848/1757\nRM0090 Rev 21\nFigure 241. Transfer sequence diagram for slave transmitter\n1.\nThe EV1 and EV3_1 events stretch SCL low until the end of the corresponding software sequence.\n2.\nThe EV3 event stretches SCL low if the software sequence is not completed before the end of the next byte \ntransmission.\nSlave receiver\nFollowing the address reception and after clearing ADDR, the slave receives bytes from the \nSDA line into the DR register via the internal shift register. After each byte the interface \ngenerates in sequence:\n•\nAn acknowledge pulse if the ACK bit is set\n•\nThe RxNE bit is set by hardware and an interrupt is generated if the ITEVFEN and \nITBUFEN bit is set.\nIf RxNE is set and the data in the DR register is not read before the end of the next data \nreception, the BTF bit is set and the interface waits until BTF is cleared by a read from the \nI2C_DR register, stretching SCL low (see Figure 242 Transfer sequencing).\n7-bit slave transmitter\n10-bit slave transmitter\nLegend: S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge,\nEVx= Event (with interrupt if ITEVFEN=1)\nEV1: ADDR=1, cleared by reading SR1 followed by reading SR2\nEV3-1: TxE=1, shift register empty, data register empty, write Data1 in DR.\nEV3: TxE=1, shift register not empty, data register empty, cleared by writing DR\n \nEV3-2: AF=1; AF is cleared by writing ‘0’ in AF bit of SR1 register.\nS\nAddress\nA\nData1\nA\nData2\nA\n.....\nDataN\nNA\nP\nEV1\nEV3-1 EV3\nEV3\nEV3\nEV3-2\nS\nHeader\nA\nAddress\nA\nEV1\nSr\nHeader\nA\nData1\nA\n.... DataN\nNA\nP\nEV1\nEV3_1\nEV3\nEV3\nEV3-2\nai18209\n" }, { "page_number": 849, "page_indices": { "start_index": 1647182, "end_index": 1649530 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 849 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.2 I2C slave mode", 846 ], [ 4, "Closing slave communication", 849 ], [ 3, "27.3.3 I2C master mode", 849 ] ], "page_content": "RM0090 Rev 21\n849/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nFigure 242. Transfer sequence diagram for slave receiver\n1.\nThe EV1 event stretches SCL low until the end of the corresponding software sequence.\n2.\nThe EV2 event stretches SCL low if the software sequence is not completed before the end of the next byte \nreception.\n3.\nAfter checking the SR1 register content, the user should perform the complete clearing sequence for each \nflag found set.\nThus, for ADDR and STOPF flags, the following sequence is required inside the I2C interrupt routine:\nREAD SR1\nif (ADDR == 1) {READ SR1; READ SR2}\nif (STOPF == 1) {READ SR1; WRITE CR1}\nThe purpose is to make sure that both ADDR and STOPF flags are cleared if both are found set.\nClosing slave communication\nAfter the last data byte is transferred a Stop Condition is generated by the master. The \ninterface detects this condition and sets:\n•\nThe STOPF bit and generates an interrupt if the ITEVFEN bit is set.\nThe STOPF bit is cleared by a read of the SR1 register followed by a write to the CR1 \nregister (see EV4 in Figure 242).\n27.3.3 \nI2C master mode\nIn Master mode, the I2C interface initiates a data transfer and generates the clock signal. A \nserial data transfer always begins with a Start condition and ends with a Stop condition. \nMaster mode is selected as soon as the Start condition is generated on the bus with a \nSTART bit.\nThe following is the required sequence in master mode.\n•\nProgram the peripheral input clock in I2C_CR2 register in order to generate correct \ntimings\n•\nConfigure the clock control registers\n•\nConfigure the rise time register\n•\nProgram the I2C_CR1 register to enable the peripheral\n•\nSet the START bit in the I2C_CR1 register to generate a Start condition\nThe peripheral input clock frequency must be at least:\n•\n2 MHz in Sm mode \n•\n4 MHz in Fm mode\n7-bit slave receiver\n10-bit slave receiver\nLegend: S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge, \nEVx= Event (with interrupt if ITEVFEN=1)\nEV1: ADDR=1, cleared by reading SR1 followed by reading SR2\nEV2: RxNE=1 cleared by reading DR register.\nEV4: STOPF=1, cleared by reading SR1 register followed by writing to the CR1 register\nS\nAddress\nA\nData1\nA\nData2\nA\n.....\nDataN\nA\nP\nEV1\nEV2\nEV2\nEV2\nEV4\nS\nHeader\nA\nAddress\nA\nData1\nA\n.....\nDataN\nA\nP\nEV1\nEV2\nEV2\nEV4\nai18208\n" }, { "page_number": 850, "page_indices": { "start_index": 1649530, "end_index": 1652452 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 850 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.3 I2C master mode", 849 ], [ 4, "SCL master clock generation", 850 ], [ 4, "Start condition", 850 ], [ 4, "Slave address transmission", 850 ] ], "page_content": "Inter-integrated circuit (I2C) interface\nRM0090\n850/1757\nRM0090 Rev 21\nSCL master clock generation\nThe CCR bits are used to generate the high and low level of the SCL clock, starting from the \ngeneration of the rising and falling edge (respectively). As a slave may stretch the SCL line, \nthe peripheral checks the SCL input from the bus at the end of the time programmed in \nTRISE bits after rising edge generation. \n•\nIf the SCL line is low, it means that a slave is stretching the bus, and the high level \ncounter stops until the SCL line is detected high. This allows to guarantee the minimum \nHIGH period of the SCL clock parameter. \n•\nIf the SCL line is high, the high level counter keeps on counting.\nIndeed, the feedback loop from the SCL rising edge generation by the peripheral to the SCL \nrising edge detection by the peripheral takes time even if no slave stretches the clock. This \nloopback duration is linked to the SCL rising time (impacting SCL VIH input detection), plus \ndelay due to the noise filter present on the SCL input path, plus delay due to internal SCL \ninput synchronization with APB clock. The maximum time used by the feedback loop is \nprogrammed in the TRISE bits, so that the SCL frequency remains stable whatever the SCL \nrising time.\nStart condition\nSetting the START bit causes the interface to generate a Start condition and to switch to \nMaster mode (MSL bit set) when the BUSY bit is cleared.\nNote:\nIn master mode, setting the START bit causes the interface to generate a ReStart condition \nat the end of the current byte transfer.\nOnce the Start condition is sent:\n•\nThe SB bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.\nThen the master waits for a read of the SR1 register followed by a write in the DR register \nwith the Slave address (see Figure 243 and Figure 244 Transfer sequencing EV5).\nSlave address transmission\nThen the slave address is sent to the SDA line via the internal shift register.\n•\nIn 10-bit addressing mode, sending the header sequence causes the following event:\n–\nThe ADD10 bit is set by hardware and an interrupt is generated if the ITEVFEN bit \nis set. \nThen the master waits for a read of the SR1 register followed by a write in the DR \nregister with the second address byte (see Figure 243 and Figure 244 Transfer \nsequencing). \n–\nThe ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit \nis set. \nThen the master waits for a read of the SR1 register followed by a read of the SR2 \nregister (see Figure 243 and Figure 244 Transfer sequencing).\n•\nIn 7-bit addressing mode, one address byte is sent.\nAs soon as the address byte is sent,\n–\nThe ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit \nis set. \nThen the master waits for a read of the SR1 register followed by a read of the SR2 \nregister (see Figure 243 and Figure 244 Transfer sequencing). \n" }, { "page_number": 851, "page_indices": { "start_index": 1652452, "end_index": 1654330 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 851 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.3 I2C master mode", 849 ], [ 4, "Master transmitter", 851 ] ], "page_content": "RM0090 Rev 21\n851/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nThe master can decide to enter Transmitter or Receiver mode depending on the LSB of the \nslave address sent.\n•\nIn 7-bit addressing mode,\n–\nTo enter Transmitter mode, a master sends the slave address with LSB reset.\n–\nTo enter Receiver mode, a master sends the slave address with LSB set.\n•\nIn 10-bit addressing mode,\n–\nTo enter Transmitter mode, a master sends the header (11110xx0) and then the \nslave address, (where xx denotes the two most significant bits of the address).\n–\nTo enter Receiver mode, a master sends the header (11110xx0) and then the \nslave address. Then it should send a repeated Start condition followed by the \nheader (11110xx1), (where xx denotes the two most significant bits of the \naddress).\nThe TRA bit indicates whether the master is in Receiver or Transmitter mode.\nMaster transmitter\nFollowing the address transmission and after clearing ADDR, the master sends bytes from \nthe DR register to the SDA line via the internal shift register.\nThe master waits until the first data byte is written into I2C_DR (see Figure 243 Transfer \nsequencing EV8_1).\nWhen the acknowledge pulse is received, the TxE bit is set by hardware and an interrupt is \ngenerated if the ITEVFEN and ITBUFEN bits are set.\nIf TxE is set and a data byte was not written in the DR register before the end of the last data \ntransmission, BTF is set and the interface waits until BTF is cleared by a write to I2C_DR, \nstretching SCL low.\nClosing the communication\nAfter the last byte is written to the DR register, the STOP bit is set by software to generate a \nStop condition (see Figure 243 Transfer sequencing EV8_2). The interface automatically \ngoes back to slave mode (MSL bit cleared).\nNote:\nStop condition should be programmed during EV8_2 event, when either TxE or BTF is set.\n" }, { "page_number": 852, "page_indices": { "start_index": 1654330, "end_index": 1657127 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 852 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.3 I2C master mode", 849 ], [ 4, "Master receiver", 852 ] ], "page_content": "Inter-integrated circuit (I2C) interface\nRM0090\n852/1757\nRM0090 Rev 21\nFigure 243. Transfer sequence diagram for master transmitter\n1.\nThe EV5, EV6, EV9, EV8_1 and EV8_2 events stretch SCL low until the end of the corresponding software sequence.\n2.\nThe EV8 event stretches SCL low if the software sequence is not complete before the end of the next byte transmission.\nMaster receiver\nFollowing the address transmission and after clearing ADDR, the I2C interface enters \nMaster Receiver mode. In this mode the interface receives bytes from the SDA line into the \nDR register via the internal shift register. After each byte the interface generates in \nsequence:\n1.\nAn acknowledge pulse if the ACK bit is set\n2. \nThe RxNE bit is set and an interrupt is generated if the ITEVFEN and ITBUFEN bits are \nset (see Figure 244 Transfer sequencing EV7).\nIf the RxNE bit is set and the data in the DR register is not read before the end of the last \ndata reception, the BTF bit is set by hardware and the interface waits until BTF is cleared by \na read in the DR register, stretching SCL low. \nClosing the communication\nThe master sends a NACK for the last byte received from the slave. After receiving this \nNACK, the slave releases the control of the SCL and SDA lines. Then the master can send \na Stop/Restart condition.\n1.\nTo generate the nonacknowledge pulse after the last received data byte, the ACK bit \nmust be cleared just after reading the second last data byte (after second last RxNE \nevent).\n2. \nIn order to generate the Stop/Restart condition, software must set the STOP/START bit \nafter reading the second last data byte (after the second last RxNE event). \n3. \nIn case a single byte has to be received, the Acknowledge disable is made during EV6 \n(before ADDR flag is cleared) and the STOP condition generation is made after EV6.\nAfter the Stop condition generation, the interface goes automatically back to slave mode \n(MSL bit cleared).\n7-bit master transmitter\n10-bit master transmitter\nLegend: S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge, \nEVx= Event (with interrupt if ITEVFEN = 1)\nEV5: SB=1, cleared by reading SR1 register followed by writing DR register with Address.\nEV6: ADDR=1, cleared by reading SR1 register followed by reading SR2.\nEV8_1: TxE=1, shift register empty, data register empty, write Data1 in DR.\nEV8: TxE=1, shift register not empty, data register empty, cleared by writing DR register\n.\nEV8_2: TxE=1, BTF = 1, Program Stop request. TxE and BTF are cleared by hardware by the Stop condition\nEV9: ADD10=1, cleared by reading SR1 register followed by writing DR register.\nS\nAddress\nA\nData1\nA\nData2\nA\n.....\nDataN\nA\nP\nEV5\nEV6\nEV8_1\nEV8\nEV8\nEV8\nEV8_2\nS\nHeader\nA\nAddress\nA\nData1\nA\n.....\nDataN\nA\nP\nEV5\nEV9\nEV6\nEV8_1\nEV8\nEV8\nEV8_2\nai18210\n" }, { "page_number": 853, "page_indices": { "start_index": 1657127, "end_index": 1659233 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 853 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.3 I2C master mode", 849 ], [ 4, "Master receiver", 852 ] ], "page_content": "RM0090 Rev 21\n853/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nFigure 244. Transfer sequence diagram for master receiver \n1.\nIf a single byte is received, it is NA.\n2.\nThe EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence.\n3.\nThe EV7 event stretches SCL low if the software sequence is not completed before the end of the next byte \nreception.\n4.\nThe EV7_1 software sequence must be completed before the ACK pulse of the current byte transfer.\n The procedures described below are recommended if the EV7-1 software sequence is not \ncompleted before the ACK pulse of the current byte transfer.\nThese procedures must be followed to make sure:\n•\nThe ACK bit is set low on time before the end of the last data reception\n•\nThe STOP bit is set high after the last data reception without reception of \nsupplementary data.\nFor 2-byte reception:\n•\nWait until ADDR = 1 (SCL stretched low until the ADDR flag is cleared)\n•\nSet ACK low, set POS high\n•\nClear ADDR flag\n•\nWait until BTF = 1 (Data 1 in DR, Data2 in shift register, SCL stretched low until a data \n1 is read)\n•\nSet STOP high\n•\nRead data 1 and 2\n7-bit master receiver\n10-bit master receiver\nLegend: S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge,\nEVx= Event (with interrupt if ITEVFEN=1)\nEV5: SB=1, cleared by reading SR1 register followed by writing DR register.\nEV6: ADDR=1, cleared by reading SR1 register followed by reading SR2. In 10-bit master receiver mode, this se-\nquence should be followed by writing CR2 with START = 1.\nEV7: RxNE=1 cleared by reading DR register.\nEV7_1: RxNE=1 cleared by reading DR register, program ACK=0 and STOP request\nEV9: ADD10=1, cleared by reading SR1 register followed by writing DR register.\nS\nAddress\nA\nData1\nA(1)\nData2\nA\n.....\nDataN\nNA\nP\nEV5\nEV6\nEV7\nEV7\nEV7_1\nEV7\nS\nHeader\nA\nAddress\nA\nEV5\nEV9\nEV6\nSr\nHeader\nA\nData1\nA(1)\n.....\nEV5\nEV6\nEV7\nData2\nA\nEV7\nDataN\nNA\nP\nEV7_1\nEV7\nai17540d\nIn case of the reception of 1 byte, the Acknowledge disable must be performed during EV6 event, i.e. before clearing ADDR flag.\n" }, { "page_number": 854, "page_indices": { "start_index": 1659233, "end_index": 1661355 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 854 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.4 Error conditions", 854 ], [ 4, "Bus error (BERR)", 854 ], [ 4, "Acknowledge failure (AF)", 854 ], [ 4, "Arbitration lost (ARLO)", 854 ] ], "page_content": "Inter-integrated circuit (I2C) interface\nRM0090\n854/1757\nRM0090 Rev 21\nFor N >2 -byte reception, from N-2 data reception\n•\nWait until BTF = 1 (data N-2 in DR, data N-1 in shift register, SCL stretched low until \ndata N-2 is read)\n•\nSet ACK low\n•\nRead data N-2\n•\nWait until BTF = 1 (data N-1 in DR, data N in shift register, SCL stretched low until a \ndata N-1 is read)\n•\nSet STOP high\n•\nRead data N-1 and N\n27.3.4 \nError conditions\nThe following are the error conditions which may cause communication to fail.\nBus error (BERR)\nThis error occurs when the I2C interface detects an external Stop or Start condition during \nan address or a data transfer. In this case:\n•\nthe BERR bit is set and an interrupt is generated if the ITERREN bit is set\n•\nin Slave mode: data are discarded and the lines are released by hardware:\n–\nin case of a misplaced Start, the slave considers it is a restart and waits for an \naddress, or a Stop condition\n–\nin case of a misplaced Stop, the slave behaves like for a Stop condition and the \nlines are released by hardware\n•\nIn Master mode: the lines are not released and the state of the current transmission is \nnot affected. It is up to the software to abort or not the current transmission\nAcknowledge failure (AF)\nThis error occurs when the interface detects a nonacknowledge bit. In this case:\n•\nthe AF bit is set and an interrupt is generated if the ITERREN bit is set\n•\na transmitter which receives a NACK must reset the communication:\n–\nIf Slave: lines are released by hardware\n–\nIf Master: a Stop or repeated Start condition must be generated by software\nArbitration lost (ARLO)\nThis error occurs when the I2C interface detects an arbitration lost condition. In this case\n•\nthe ARLO bit is set by hardware (and an interrupt is generated if the ITERREN bit is \nset)\n•\nthe I2C Interface goes automatically back to slave mode (the MSL bit is cleared). When \nthe I2C loses the arbitration, it is not able to acknowledge its slave address in the same \ntransfer, but it can acknowledge it after a repeated Start from the winning master.\n•\nlines are released by hardware\n" }, { "page_number": 855, "page_indices": { "start_index": 1661355, "end_index": 1663858 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 855 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.4 Error conditions", 854 ], [ 4, "Overrun/underrun error (OVR)", 855 ], [ 3, "27.3.5 Programmable noise filter", 855 ] ], "page_content": "RM0090 Rev 21\n855/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nOverrun/underrun error (OVR)\nAn overrun error can occur in slave mode when clock stretching is disabled and the I2C \ninterface is receiving data. The interface has received a byte (RxNE=1) and the data in DR \nhas not been read, before the next byte is received by the interface. In this case,\n•\nThe last received byte is lost. \n•\nIn case of Overrun error, software should clear the RxNE bit and the transmitter should \nre-transmit the last received byte.\nUnderrun error can occur in slave mode when clock stretching is disabled and the I2C \ninterface is transmitting data. The interface has not updated the DR with the next byte \n(TxE=1), before the clock comes for the next byte. In this case,\n•\nThe same byte in the DR register is sent again.\n•\nThe user should make sure that data received on the receiver side during an underrun \nerror are discarded and that the next bytes are written within the clock low time \nspecified in the I2C bus standard.\nFor the first byte to be transmitted, the DR must be written after ADDR is cleared and before \nthe first SCL rising edge. If not possible, the receiver must discard the first data.\n27.3.5 \nProgrammable noise filter\nThe programmable noise filter is available on STM32F42xxx and STM32F43xxx devices \nonly.\nIn Fm mode, the I2C standard requires that spikes are suppressed to a length of 50 ns on \nSDA and SCL lines.\nAn analog noise filter is implemented in the SDA and SCL I/Os. This filter is enabled by \ndefault and can be disabled by setting the ANOFF bit in the I2C_FLTR register.\nA digital noise filter can be enabled by configuring the DNF[3:0] bits to a non-zero value. \nThis suppresses the spikes on SDA and SCL inputs with a length of up to DNF[3:0] * \nTPCLK1. \nEnabling the digital noise filter increases the SDA hold time by (DNF[3:0] +1)* TPCLK.\nTo be compliant with the maximum hold time of the I2C-bus specification version 2.1 \n(Thd:dat), the DNF bits must be programmed using the constraints shown in Table 123, and \nassuming that the analog filter is disabled.\nNote:\nDNF[3:0] must only be configured when the I2C is disabled (PE = 0). If the analog filter is \nalso enabled, the digital filter is added to the analog filter.\n \nTable 123. Maximum DNF[3:0] value to be compliant with Thd:dat(max)\nPCLK1 frequency\nMaximum DNF value\nSm mode\nFm mode\n2 <= FPCLK1 <= 5\n2\n0\n5 < FPCLK1 <= 10\n12\n0\n10 < FPCLK1 <= 20\n15\n1\n20 < FPCLK1 <= 30\n15\n7\n" }, { "page_number": 856, "page_indices": { "start_index": 1663858, "end_index": 1666283 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 856 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.6 SDA/SCL line control", 856 ], [ 3, "27.3.7 SMBus", 856 ], [ 4, "Introduction", 856 ], [ 4, "Similarities between SMBus and I2C", 856 ] ], "page_content": "Inter-integrated circuit (I2C) interface\nRM0090\n856/1757\nRM0090 Rev 21\nNote:\nFor each frequency range, the constraint is given based on the worst case which is the \nminimum frequency of the range. Greater DNF values can be used if the system can \nsupport maximum hold time violation.\n27.3.6 \nSDA/SCL line control\n•\nIf clock stretching is enabled:\n–\nTransmitter mode: If TxE=1 and BTF=1: the interface holds the clock line low \nbefore transmission to wait for the microcontroller to write the byte in the Data \nregister (both buffer and shift register are empty).\n–\nReceiver mode: If RxNE=1 and BTF=1: the interface holds the clock line low after \nreception to wait for the microcontroller to read the byte in the Data register (both \nbuffer and shift register are full).\n•\nIf clock stretching is disabled in Slave mode:\n–\nOverrun Error in case of RxNE=1 and no read of DR has been done before the \nnext byte is received. The last received byte is lost.\n–\nUnderrun Error in case TxE=1 and no write into DR has been done before the next \nbyte must be transmitted. The same byte is sent again.\n–\nWrite Collision not managed.\n27.3.7 \nSMBus\nIntroduction\nThe System Management Bus (SMBus) is a two-wire interface through which various \ndevices can communicate with each other and with the rest of the system. It is based on I2C \nprinciples of operation. SMBus provides a control bus for system and power management \nrelated tasks. A system may use SMBus to pass messages to and from devices instead of \ntoggling individual control lines. \nThe System Management Bus Specification refers to three types of devices. A slave is a \ndevice that is receiving or responding to a command. A master is a device that issues \ncommands, generates the clocks, and terminates the transfer. A host is a specialized \nmaster that provides the main interface to the system's CPU. A host must be a master-slave \nand must support the SMBus host notify protocol. Only one host is allowed in a system.\nSimilarities between SMBus and I2C\n•\n2-wire bus protocol (1 Clk, 1 Data) + SMBus Alert line optional\n•\nMaster-slave communication, Master provides clock\n•\nMulti master capability\n•\nSMBus data format similar to I2C 7-bit addressing format (Figure 238).\n30 < FPCLK1 <= 40\n15\n13\n40 < FPCLK1 <= 50\n15\n15\nTable 123. Maximum DNF[3:0] value to be compliant with Thd:dat(max) (continued)\nPCLK1 frequency\nMaximum DNF value\nSm mode\nFm mode\n" }, { "page_number": 857, "page_indices": { "start_index": 1666283, "end_index": 1668561 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 857 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.7 SMBus", 856 ], [ 4, "Differences between SMBus and I2C", 857 ], [ 4, "SMBus application usage", 857 ], [ 4, "Device identification", 857 ], [ 4, "Bus protocols", 857 ], [ 4, "Address resolution protocol (ARP)", 857 ], [ 4, "Unique device identifier (UDID)", 857 ] ], "page_content": "RM0090 Rev 21\n857/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nDifferences between SMBus and I2C\nThe following table describes the differences between SMBus and I2C.\n \nSMBus application usage\nWith System Management Bus, a device can provide manufacturer information, tell the \nsystem what its model/part number is, save its state for a suspend event, report different \ntypes of errors, accept control parameters, and return its status. SMBus provides a control \nbus for system and power management related tasks. \nDevice identification\nAny device that exists on the System Management Bus as a slave has a unique address \ncalled the Slave Address. For the list of reserved slave addresses, refer to the SMBus \nspecification version. 2.0 (http://smbus.org/).\nBus protocols\nThe SMBus specification supports up to nine bus protocols. For more details of these \nprotocols and SMBus address types, refer to SMBus specification version. 2.0. These \nprotocols should be implemented by the user software.\nAddress resolution protocol (ARP)\nSMBus slave address conflicts can be resolved by dynamically assigning a new unique \naddress to each slave device. The Address Resolution Protocol (ARP) has the following \nattributes:\n•\nAddress assignment uses the standard SMBus physical layer arbitration mechanism\n•\nAssigned addresses remain constant while device power is applied; address retention \nthrough device power loss is also allowed\n•\nNo additional SMBus packet overhead is incurred after address assignment. (i.e. \nsubsequent accesses to assigned slave addresses have the same overhead as \naccesses to fixed address devices.)\n•\nAny SMBus master can enumerate the bus\nUnique device identifier (UDID)\nIn order to provide a mechanism to isolate each device for the purpose of address \nassignment, each device must implement a unique device identifier (UDID). \nTable 124. SMBus vs. I2C\nSMBus\nI2C\nMax. speed 100 kHz\nMax. speed 400 kHz\nMin. clock speed 10 kHz\nNo minimum clock speed\n35 ms clock low timeout\nNo timeout\nLogic levels are fixed\nLogic levels are VDD dependent\nDifferent address types (reserved, dynamic etc.)\n7-bit, 10-bit and general call slave address types\nDifferent bus protocols (quick command, process \ncall etc.)\nNo bus protocols\n" }, { "page_number": 858, "page_indices": { "start_index": 1668561, "end_index": 1671413 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 858 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.7 SMBus", 856 ], [ 4, "SMBus alert mode", 858 ], [ 4, "Timeout error", 858 ], [ 4, "How to use the interface in SMBus mode", 858 ] ], "page_content": "Inter-integrated circuit (I2C) interface\nRM0090\n858/1757\nRM0090 Rev 21\nFor the details on 128-bit UDID and more information on ARP, refer to SMBus specification \nversion 2.0.\nSMBus alert mode\nSMBus Alert is an optional signal with an interrupt line for devices that want to trade their \nability to master for a pin. SMBA is a wired-AND signal just as the SCL and SDA signals are. \nSMBA is used in conjunction with the SMBus General Call Address. Messages invoked with \nthe SMBus are two bytes long. \nA slave-only device can signal the host through SMBA that it wants to talk by setting ALERT \nbit in I2C_CR1 register. The host processes the interrupt and simultaneously accesses all \nSMBA devices through the Alert Response Address (known as ARA having a value 0001 \n100X). Only the device(s) which pulled SMBA low acknowledge the Alert Response \nAddress. This status is identified using SMBALERT Status flag in I2C_SR1 register. The \nhost performs a modified Receive Byte operation. The 7 bit device address provided by the \nslave transmit device is placed in the 7 most significant bits of the byte. The eighth bit can \nbe a zero or one.\nIf more than one device pulls SMBA low, the highest priority (lowest address) device wins \ncommunication rights via standard arbitration during the slave address transfer. After \nacknowledging the slave address the device must disengage its SMBA pull-down. If the \nhost still sees SMBA low when the message transfer is complete, it knows to read the ARA \nagain.\nA host which does not implement the SMBA signal may periodically access the ARA.\nFor more details on SMBus Alert mode, refer to SMBus specification version 2.0.\nTimeout error\nThere are differences in the timing specifications between I2C and SMBus.\nSMBus defines a clock low timeout, TIMEOUT of 35 ms. Also SMBus specifies TLOW: \nSEXT as the cumulative clock low extend time for a slave device. SMBus specifies TLOW: \nMEXT as the cumulative clock low extend time for a master device. For more details on \nthese timeouts, refer to SMBus specification version 2.0.\nThe status flag Timeout or Tlow Error in I2C_SR1 shows the status of this feature.\nHow to use the interface in SMBus mode\nTo switch from I2C mode to SMBus mode, the following sequence should be performed.\n•\nSet the SMBus bit in the I2C_CR1 register\n•\nConfigure the SMBTYPE and ENARP bits in the I2C_CR1 register as required for the \napplication \nIf you want to configure the device as a master, follow the Start condition generation \nprocedure in Section 27.3.3. Otherwise, follow the sequence in Section 27.3.2. \nThe application has to control the various SMBus protocols by software.\n•\nSMB Device Default Address acknowledged if ENARP=1 and SMBTYPE=0\n•\nSMB Host Header acknowledged if ENARP=1 and SMBTYPE=1\n•\nSMB Alert Response Address acknowledged if SMBALERT=1\n" }, { "page_number": 859, "page_indices": { "start_index": 1671413, "end_index": 1674719 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 859 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.8 DMA requests", 859 ], [ 4, "Transmission using DMA", 859 ] ], "page_content": "RM0090 Rev 21\n859/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\n27.3.8 \nDMA requests\nDMA requests (when enabled) are generated only for data transfer. DMA requests are \ngenerated by Data register becoming empty in transmission and Data register becoming full \nin reception. The DMA must be initialized and enabled before the I2C data transfer. The \nDMAEN bit must be set in the I2C_CR2 register before the ADDR event. In master mode or \nin slave mode when clock stretching is enabled, the DMAEN bit can also be set during the \nADDR event, before clearing the ADDR flag. The DMA request must be served before the \nend of the current byte transfer. When the number of data transfers which has been \nprogrammed for the corresponding DMA stream is reached, the DMA controller sends an \nEnd of Transfer EOT signal to the I2C interface and generates a Transfer Complete interrupt \nif enabled: \n•\nMaster transmitter: In the interrupt routine after the EOT interrupt, disable DMA \nrequests then wait for a BTF event before programming the Stop condition.\n•\nMaster receiver\n–\nWhen the number of bytes to be received is equal to or greater than two, the DMA \ncontroller sends a hardware signal, EOT_1, corresponding to the last but one data \nbyte (number_of_bytes – 1). If, in the I2C_CR2 register, the LAST bit is set, I2C \nautomatically sends a NACK after the next byte following EOT_1. The user can \ngenerate a Stop condition in the DMA Transfer Complete interrupt routine if \nenabled.\n–\nWhen a single byte must be received: the NACK must be programmed during EV6 \nevent, i.e. program ACK=0 when ADDR=1, before clearing ADDR flag. Then the \nuser can program the STOP condition either after clearing ADDR flag, or in the \nDMA Transfer Complete interrupt routine.\nTransmission using DMA\nDMA mode can be enabled for transmission by setting the DMAEN bit in the I2C_CR2 \nregister. Data are loaded from a Memory area configured using the DMA peripheral (refer to \nthe DMA specification) to the I2C_DR register whenever the TxE bit is set. To map a DMA \nstream x for I2C transmission (where x is the stream number), perform the following \nsequence:\n1.\nSet the I2C_DR register address in the DMA_SxPAR register. The data are moved to \nthis address from the memory after each TxE event.\n2. \nSet the memory address in the DMA_SxMA0R register (and in DMA_SxMA1R register \nin the case of a bouble buffer mode). The data are loaded into I2C_DR from this \nmemory after each TxE event.\n3. \nConfigure the total number of bytes to be transferred in the DMA_SxNDTR register. \nAfter each TxE event, this value is decremented.\n4. \nConfigure the DMA stream priority using the PL[0:1] bits in the DMA_SxCR register\n5. \nSet the DIR bit in the DMA_SxCR register and configure interrupts after half transfer or \nfull transfer depending on application requirements.\n6. \nActivate the stream by setting the EN bit in the DMA_SxCR register.\nWhen the number of data transfers which has been programmed in the DMA Controller \nregisters is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the \nI2C interface and the DMA generates an interrupt, if enabled, on the DMA stream interrupt \nvector.\nNote:\nDo not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for transmission.\n" }, { "page_number": 860, "page_indices": { "start_index": 1674719, "end_index": 1677196 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 860 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.3 I2C functional description", 843 ], [ 3, "27.3.8 DMA requests", 859 ], [ 4, "Reception using DMA", 860 ], [ 3, "27.3.9 Packet error checking", 860 ] ], "page_content": "Inter-integrated circuit (I2C) interface\nRM0090\n860/1757\nRM0090 Rev 21\nReception using DMA\nDMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register. \nData are loaded from the I2C_DR register to a Memory area configured using the DMA \nperipheral (refer to the DMA specification) whenever a data byte is received. To map a DMA \nstream x for I2C reception (where x is the stream number), perform the following sequence:\n1.\nSet the I2C_DR register address in DMA_SxPAR register. The data are moved from \nthis address to the memory after each RxNE event.\n2. \nSet the memory address in the DMA_SxMA0R register (and in DMA_SxMA1R register \nin the case of a bouble buffer mode). The data are loaded from the I2C_DR register to \nthis memory area after each RxNE event.\n3. \nConfigure the total number of bytes to be transferred in the DMA_SxNDTR register. \nAfter each RxNE event, this value is decremented.\n4. \nConfigure the stream priority using the PL[0:1] bits in the DMA_SxCR register\n5. \nReset the DIR bit and configure interrupts in the DMA_SxCR register after half transfer \nor full transfer depending on application requirements.\n6. \nActivate the stream by setting the EN bit in the DMA_SxCR register.\nWhen the number of data transfers which has been programmed in the DMA Controller \nregisters is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the \nI2C interface and DMA generates an interrupt, if enabled, on the DMA stream interrupt \nvector. \nNote:\nDo not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for reception.\n27.3.9 \nPacket error checking\nA PEC calculator has been implemented to improve the reliability of communication. The \nPEC is calculated by using the C(x) = x8 + x2 + x + 1 CRC-8 polynomial serially on each bit.\n•\nPEC calculation is enabled by setting the ENPEC bit in the I2C_CR1 register. PEC is a \nCRC-8 calculated on all message bytes including addresses and R/W bits.\n–\nIn transmission: set the PEC transfer bit in the I2C_CR1 register after the TxE \nevent corresponding to the last byte. The PEC is transferred after the last \ntransmitted byte.\n–\nIn reception: set the PEC bit in the I2C_CR1 register after the RxNE event \ncorresponding to the last byte so that the receiver sends a NACK if the next \nreceived byte is not equal to the internally calculated PEC. In case of Master-\nReceiver, a NACK must follow the PEC whatever the check result. The PEC must \n" }, { "page_number": 861, "page_indices": { "start_index": 1677196, "end_index": 1678997 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 861 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.4 I2C interrupts", 861 ] ], "page_content": "RM0090 Rev 21\n861/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nbe set before the ACK of the CRC reception in slave mode. It must be set when \nthe ACK is set low in master mode.\n•\nA PECERR error flag/interrupt is also available in the I2C_SR1 register.\n•\nIf DMA and PEC calculation are both enabled:-\n–\nIn transmission: when the I2C interface receives an EOT signal from the DMA \ncontroller, it automatically sends a PEC after the last byte.\n–\nIn reception: when the I2C interface receives an EOT_1 signal from the DMA \ncontroller, it automatically considers the next byte as a PEC and checks it. A DMA \nrequest is generated after PEC reception.\n•\nTo allow intermediate PEC transfers, a control bit is available in the I2C_CR2 register \n(LAST bit) to determine if it is really the last DMA transfer or not. If it is the last DMA \nrequest for a master receiver, a NACK is automatically sent after the last received byte.\n•\nPEC calculation is corrupted by an arbitration loss.\n27.4 \nI2C interrupts\nThe table below gives the list of I2C interrupt requests.\n \nNote:\nSB, ADDR, ADD10, STOPF, BTF, RxNE and TxE are logically OR-ed on the same interrupt \nchannel.\nBERR, ARLO, AF, OVR, PECERR, TIMEOUT and SMBALERT are logically OR-ed on the \nsame interrupt channel.\nTable 125. I2C Interrupt requests\nInterrupt event\nEvent flag\nEnable control bit\nStart bit sent (Master)\nSB\nITEVFEN\nAddress sent (Master) or Address matched (Slave)\nADDR\n10-bit header sent (Master)\nADD10\nStop received (Slave)\nSTOPF\nData byte transfer finished\nBTF\nReceive buffer not empty\nRxNE\nITEVFEN and ITBUFEN\nTransmit buffer empty\nTxE\nBus error\nBERR\nITERREN\nArbitration loss (Master)\nARLO\nAcknowledge failure\nAF\nOverrun/Underrun\nOVR\nPEC error\nPECERR\nTimeout/Tlow error\nTIMEOUT\nSMBus Alert\nSMBALERT\n" }, { "page_number": 862, "page_indices": { "start_index": 1678997, "end_index": 1679259 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 862 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.4 I2C interrupts", 861 ] ], "page_content": "Inter-integrated circuit (I2C) interface\nRM0090\n862/1757\nRM0090 Rev 21\nFigure 245. I2C interrupt mapping diagram \nADDR\nSB\nADD10\nRxNE\nTxE\nBTF\nit_event\nARLO\nBERR\nAF\nOVR\nPECERR\nTIMEOUT\nSMBALERT\nITERREN\nit_error\nITEVFEN\nITBUFEN\nSTOPF\nMS42082V1\n" }, { "page_number": 863, "page_indices": { "start_index": 1679259, "end_index": 1681875 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 863 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.5 I2C debug mode", 863 ], [ 2, "27.6 I2C registers", 863 ], [ 3, "27.6.1 I2C Control register 1 (I2C_CR1)", 863 ] ], "page_content": "RM0090 Rev 21\n863/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\n27.5 \nI2C debug mode\nWhen the microcontroller enters the debug mode (Cortex®-M4 with FPU core halted), the \nSMBUS timeout either continues to work normally or stops, depending on the \nDBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details, \nrefer to Section 38.16.2: Debug support for timers, watchdog, bxCAN and I2C.\n27.6 \nI2C registers\nRefer to Section 1.1 for a list of abbreviations used in register descriptions.\nThe peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).\n27.6.1 \nI2C Control register 1 (I2C_CR1)\nAddress offset: 0x00\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSWRST\nRes.\nALERT\nPEC\nPOS\nACK\nSTOP\nSTART\nNO\nSTRETCH\nENGC\nENPEC ENARP\nSMB\nTYPE\nRes.\nSMBU\nS\nPE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 SWRST: Software reset\nWhen set, the I2C is under reset state. Before resetting this bit, make sure the I2C lines are \nreleased and the bus is free.\n0: I2C Peripheral not under reset\n1: I2C Peripheral under reset state\nNote: This bit can be used to reinitialize the peripheral after an error or a locked state. As an \nexample, if the BUSY bit is set and remains locked due to a glitch on the bus, the \nSWRST bit can be used to exit from this state.\nBit 14 Reserved, must be kept at reset value\nBit 13 ALERT: SMBus alert\nThis bit is set and cleared by software, and cleared by hardware when PE=0.\n0: Releases SMBA pin high. Alert Response Address Header followed by NACK.\n1: Drives SMBA pin low. Alert Response Address Header followed by ACK.\nBit 12 PEC: Packet error checking\nThis bit is set and cleared by software, and cleared by hardware when PEC is transferred or \nby a START or Stop condition or when PE=0.\n0: No PEC transfer\n1: PEC transfer (in Tx or Rx mode)\nNote: PEC calculation is corrupted by an arbitration loss.\nBit 11 POS: Acknowledge/PEC Position (for data reception)\nThis bit is set and cleared by software and cleared by hardware when PE=0.\n0: ACK bit controls the (N)ACK of the current byte being received in the shift register. The \nPEC bit indicates that current byte in shift register is a PEC.\n1: ACK bit controls the (N)ACK of the next byte which is received in the shift register. The \nPEC bit indicates that the next byte in the shift register is a PEC\nNote: The POS bit must be used only in 2-byte reception configuration in master mode. It \nmust be configured before data reception starts, as described in the 2-byte reception \nprocedure recommended in Section : Master receiver on page 852.\n" }, { "page_number": 864, "page_indices": { "start_index": 1681875, "end_index": 1683505 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 864 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.6 I2C registers", 863 ], [ 3, "27.6.1 I2C Control register 1 (I2C_CR1)", 863 ] ], "page_content": "Inter-integrated circuit (I2C) interface\nRM0090\n864/1757\nRM0090 Rev 21\nBit 10 ACK: Acknowledge enable\nThis bit is set and cleared by software and cleared by hardware when PE=0.\n0: No acknowledge returned\n1: Acknowledge returned after a byte is received (matched address or data)\nBit 9 STOP: Stop generation\nThe bit is set and cleared by software, cleared by hardware when a Stop condition is \ndetected, set by hardware when a timeout error is detected.\nIn Master mode:\n0: No Stop generation.\n1: Stop generation after the current byte transfer or after the current Start condition is sent.\nIn Slave mode:\n0: No Stop generation.\n1: Release the SCL and SDA lines after the current byte transfer. \nBit 8 START: Start generation\nThis bit is set and cleared by software and cleared by hardware when start is sent or PE=0.\nIn Master mode:\n0: No Start generation\n1: Repeated start generation\nIn Slave mode:\n0: No Start generation\n1: Start generation when the bus is free\nBit 7 NOSTRETCH: Clock stretching disable (Slave mode)\nThis bit is used to disable clock stretching in slave mode when ADDR or BTF flag is set, until \nit is reset by software.\n0: Clock stretching enabled\n1: Clock stretching disabled\nBit 6 ENGC: General call enable\n0: General call disabled. Address 00h is NACKed.\n1: General call enabled. Address 00h is ACKed.\nBit 5 ENPEC: PEC enable\n0: PEC calculation disabled\n1: PEC calculation enabled\nBit 4 ENARP: ARP enable\n0: ARP disable\n1: ARP enable\nSMBus Device default address recognized if SMBTYPE=0\nSMBus Host address recognized if SMBTYPE=1\nBit 3 SMBTYPE: SMBus type\n0: SMBus Device\n1: SMBus Host\n" }, { "page_number": 865, "page_indices": { "start_index": 1683505, "end_index": 1685063 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 865 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.6 I2C registers", 863 ], [ 3, "27.6.2 I2C Control register 2 (I2C_CR2)", 865 ] ], "page_content": "RM0090 Rev 21\n865/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nNote:\nWhen the STOP, START or PEC bit is set, the software must not perform any write access \nto I2C_CR1 before this bit is cleared by hardware. Otherwise there is a risk of setting a \nsecond STOP, START or PEC request.\n27.6.2 \nI2C Control register 2 (I2C_CR2)\nAddress offset: 0x04\nReset value: 0x0000\n \nBit 2 Reserved, must be kept at reset value\nBit 1 SMBUS: SMBus mode\n0: I2C mode\n1: SMBus mode\nBit 0 PE: Peripheral enable\n0: Peripheral disable\n1: Peripheral enable\nNote: If this bit is reset while a communication is on going, the peripheral is disabled at the \nend of the current communication, when back to IDLE state. \nAll bit resets due to PE=0 occur at the end of the communication.\nIn master mode, this bit must not be reset before the end of the communication.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLAST\nDMAEN ITBUFEN ITEVTEN ITERREN\nReserved\nFREQ[5:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:13 Reserved, must be kept at reset value\nBit 12 LAST: DMA last transfer\n0: Next DMA EOT is not the last transfer\n1: Next DMA EOT is the last transfer\nNote: This bit is used in master receiver mode to permit the generation of a NACK on the last \nreceived data.\nBit 11 DMAEN: DMA requests enable\n0: DMA requests disabled\n1: DMA request enabled when TxE=1 or RxNE =1\nBit 10 ITBUFEN: Buffer interrupt enable\n0: TxE = 1 or RxNE = 1 does not generate any interrupt.\n1: TxE = 1 or RxNE = 1 generates Event Interrupt (whatever the state of DMAEN)\n" }, { "page_number": 866, "page_indices": { "start_index": 1685063, "end_index": 1686276 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 866 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.6 I2C registers", 863 ], [ 3, "27.6.2 I2C Control register 2 (I2C_CR2)", 865 ] ], "page_content": "Inter-integrated circuit (I2C) interface\nRM0090\n866/1757\nRM0090 Rev 21\nBit 9 ITEVTEN: Event interrupt enable\n0: Event interrupt disabled\n1: Event interrupt enabled\nThis interrupt is generated when:\n–\nSB = 1 (Master)\n–\nADDR = 1 (Master/Slave)\n–\nADD10= 1 (Master)\n–\nSTOPF = 1 (Slave)\n–\nBTF = 1 with no TxE or RxNE event\n–\nTxE event to 1 if ITBUFEN = 1\n–\nRxNE event to 1if ITBUFEN = 1\nBit 8 ITERREN: Error interrupt enable\n0: Error interrupt disabled\n1: Error interrupt enabled\nThis interrupt is generated when:\n–\nBERR = 1\n–\nARLO = 1\n–\nAF = 1\n–\nOVR = 1\n–\nPECERR = 1\n–\nTIMEOUT = 1\n–\nSMBALERT = 1\nBits 7:6 Reserved, must be kept at reset value\nBits 5:0 FREQ[5:0]: Peripheral clock frequency\nThe FREQ bits must be configured with the APB clock frequency value (I2C peripheral \nconnected to APB). The FREQ field is used by the peripheral to generate data setup and \nhold times compliant with the I2C specifications. The minimum allowed frequency is 2 MHz, \nthe maximum frequency is limited by the maximum APB frequency and cannot exceed \n50 MHz (peripheral intrinsic maximum limit).\n0b000000: Not allowed\n0b000001: Not allowed\n0b000010: 2 MHz\n...\n0b110010: 50 MHz\nHigher than 0b101010: Not allowed\n" }, { "page_number": 867, "page_indices": { "start_index": 1686276, "end_index": 1687583 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 867 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.6 I2C registers", 863 ], [ 3, "27.6.3 I2C Own address register 1 (I2C_OAR1)", 867 ], [ 3, "27.6.4 I2C Own address register 2 (I2C_OAR2)", 867 ] ], "page_content": "RM0090 Rev 21\n867/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\n27.6.3 \nI2C Own address register 1 (I2C_OAR1)\nAddress offset: 0x08\nReset value: 0x0000\n \n27.6.4 \nI2C Own address register 2 (I2C_OAR2)\nAddress offset: 0x0C\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nADD\nMODE\nReserved\nADD[9:8]\nADD[7:1]\nADD0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 ADDMODE Addressing mode (slave mode)\n0: 7-bit slave address (10-bit address not acknowledged)\n1: 10-bit slave address (7-bit address not acknowledged)\nBit 14\nShould always be kept at 1 by software.\nBits 13:10\nReserved, must be kept at reset value\nBits 9:8 ADD[9:8]: Interface address\n7-bit addressing mode: don’t care\n10-bit addressing mode: bits9:8 of address\nBits 7:1 ADD[7:1]: Interface address\nbits 7:1 of address\nBit 0 ADD0: Interface address\n7-bit addressing mode: don’t care\n10-bit addressing mode: bit 0 of address\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nADD2[7:1]\nENDUAL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value\nBits 7:1 ADD2[7:1]: Interface address\nbits 7:1 of address in dual addressing mode\nBit 0 ENDUAL: Dual addressing mode enable\n0: Only OAR1 is recognized in 7-bit addressing mode\n1: Both OAR1 and OAR2 are recognized in 7-bit addressing mode\n" }, { "page_number": 868, "page_indices": { "start_index": 1687583, "end_index": 1689152 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 868 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.6 I2C registers", 863 ], [ 3, "27.6.5 I2C Data register (I2C_DR)", 868 ], [ 3, "27.6.6 I2C Status register 1 (I2C_SR1)", 868 ] ], "page_content": "Inter-integrated circuit (I2C) interface\nRM0090\n868/1757\nRM0090 Rev 21\n27.6.5 \nI2C Data register (I2C_DR)\nAddress offset: 0x10\nReset value: 0x0000\n \n27.6.6 \nI2C Status register 1 (I2C_SR1)\nAddress offset: 0x14\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDR[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value\nBits 7:0 DR[7:0] 8-bit data register\nByte received or to be transmitted to the bus.\n– Transmitter mode: Byte transmission starts automatically when a byte is written in the DR \nregister. A continuous transmit stream can be maintained if the next data to be transmitted is \nput in DR once the transmission is started (TxE=1)\n– Receiver mode: Received byte is copied into DR (RxNE=1). A continuous transmit stream \ncan be maintained if DR is read before the next data byte is received (RxNE=1).\nNote: In slave mode, the address is not copied into DR.\nWrite collision is not managed (DR can be written if TxE=0).\nIf an ARLO event occurs on ACK pulse, the received byte is not copied into DR and so \ncannot be read.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSMB\nALERT\nTIME\nOUT\nRes.\nPEC\nERR\nOVR\nAF\nARLO\nBERR\nTxE\nRxNE\nRes.\nSTOPF\nADD10\nBTF\nADDR\nSB\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nr\nr\nr\nr\nr\nr\nr\nBit 15 SMBALERT: SMBus alert \nIn SMBus host mode:\n0: no SMBALERT\n1: SMBALERT event occurred on pin\nIn SMBus slave mode:\n0: no SMBALERT response address header\n1: SMBALERT response address header to SMBALERT LOW received\n– Cleared by software writing 0, or by hardware when PE=0.\n" }, { "page_number": 869, "page_indices": { "start_index": 1689152, "end_index": 1691531 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 869 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.6 I2C registers", 863 ], [ 3, "27.6.6 I2C Status register 1 (I2C_SR1)", 868 ] ], "page_content": "RM0090 Rev 21\n869/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\nBit 14 TIMEOUT: Timeout or Tlow error \n0: No timeout error\n1: SCL remained LOW for 25 ms (Timeout)\nor\nMaster cumulative clock low extend time more than 10 ms (Tlow:mext)\nor\nSlave cumulative clock low extend time more than 25 ms (Tlow:sext)\n– When set in slave mode: slave resets the communication and lines are released by \nhardware\n– When set in master mode: Stop condition sent by hardware\n– Cleared by software writing 0, or by hardware when PE=0.\nNote: This functionality is available only in SMBus mode.\nBit 13 Reserved, must be kept at reset value\nBit 12 PECERR: PEC Error in reception\n0: no PEC error: receiver returns ACK after PEC reception (if ACK=1)\n1: PEC error: receiver returns NACK after PEC reception (whatever ACK)\n– Cleared by software writing 0, or by hardware when PE=0.\nNote: When the received CRC is wrong, PECERR is not set in slave mode if the PEC control \nbit is not set before the end of the CRC reception. Nevertheless, reading the PEC value \ndetermines whether the received CRC is right or wrong.\nBit 11 OVR: Overrun/Underrun\n0: No overrun/underrun\n1: Overrun or underrun\n– Set by hardware in slave mode when NOSTRETCH=1 and:\n– In reception when a new byte is received (including ACK pulse) and the DR register has not \nbeen read yet. New received byte is lost.\n– In transmission when a new byte should be sent and the DR register has not been written \nyet. The same byte is sent twice.\n– Cleared by software writing 0, or by hardware when PE=0.\nNote: If the DR write occurs very close to SCL rising edge, the sent data is unspecified and a \nhold timing error occurs\nBit 10 AF: Acknowledge failure\n0: No acknowledge failure\n1: Acknowledge failure\n– Set by hardware when no acknowledge is returned. \n– Cleared by software writing 0, or by hardware when PE=0.\nBit 9 ARLO: Arbitration lost (master mode) \n0: No Arbitration Lost detected\n1: Arbitration Lost detected\nSet by hardware when the interface loses the arbitration of the bus to another master\n– Cleared by software writing 0, or by hardware when PE=0.\nAfter an ARLO event the interface switches back automatically to Slave mode (MSL=0). \nNote: In SMBUS, the arbitration on the data in slave mode occurs only during the data phase, \nor the acknowledge transmission (not on the address acknowledge).\n" }, { "page_number": 870, "page_indices": { "start_index": 1691531, "end_index": 1693836 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 870 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.6 I2C registers", 863 ], [ 3, "27.6.6 I2C Status register 1 (I2C_SR1)", 868 ] ], "page_content": "Inter-integrated circuit (I2C) interface\nRM0090\n870/1757\nRM0090 Rev 21\nBit 8 BERR: Bus error \n0: No misplaced Start or Stop condition\n1: Misplaced Start or Stop condition\n– Set by hardware when the interface detects an SDA rising or falling edge while SCL is high, \noccurring in a non-valid position during a byte transfer.\n– Cleared by software writing 0, or by hardware when PE=0.\nBit 7 TxE: Data register empty (transmitters) \n0: Data register not empty\n1: Data register empty\n– Set when DR is empty in transmission. TxE is not set during address phase.\n– Cleared by software writing to the DR register or by hardware after a start or a stop condition \nor when PE=0.\nTxE is not set if either a NACK is received, or if next byte to be transmitted is PEC (PEC=1)\nNote: TxE is not cleared by writing the first data being transmitted, or by writing data when \nBTF is set, as in both cases the data register is still empty.\nBit 6 RxNE: Data register not empty (receivers)\n0: Data register empty\n1: Data register not empty\n– Set when data register is not empty in receiver mode. RxNE is not set during address phase.\n– Cleared by software reading or writing the DR register or by hardware when PE=0.\nRxNE is not set in case of ARLO event.\nNote: RxNE is not cleared by reading data when BTF is set, as the data register is still full.\nBit 5 Reserved, must be kept at reset value\nBit 4 STOPF: Stop detection (slave mode) \n0: No Stop condition detected\n1: Stop condition detected\n– Set by hardware when a Stop condition is detected on the bus by the slave after an \nacknowledge (if ACK=1). \n– Cleared by software reading the SR1 register followed by a write in the CR1 register, or by \nhardware when PE=0\nNote: The STOPF bit is not set after a NACK reception.\nIt is recommended to perform the complete clearing sequence (READ SR1 then \nWRITE CR1) after the STOPF is set. Refer to Figure 242.\nBit 3 ADD10: 10-bit header sent (Master mode) \n0: No ADD10 event occurred.\n1: Master has sent first address byte (header).\n– Set by hardware when the master has sent the first byte in 10-bit address mode. \n– Cleared by software reading the SR1 register followed by a write in the DR register of the \nsecond address byte, or by hardware when PE=0.\nNote: ADD10 bit is not set after a NACK reception\n" }, { "page_number": 871, "page_indices": { "start_index": 1693836, "end_index": 1696186 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 871 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.6 I2C registers", 863 ], [ 3, "27.6.7 I2C Status register 2 (I2C_SR2)", 871 ] ], "page_content": "RM0090 Rev 21\n871/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\n27.6.7 \nI2C Status register 2 (I2C_SR2)\nAddress offset: 0x18\nReset value: 0x0000\nNote:\nReading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was \nset after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found \nset in I2C_SR1 or when the STOPF bit is cleared.\n \nBit 2 BTF: Byte transfer finished\n0: Data byte transfer not done\n1: Data byte transfer succeeded\n– Set by hardware when NOSTRETCH=0 and: \n– In reception when a new byte is received (including ACK pulse) and DR has not been read \nyet (RxNE=1).\n– In transmission when a new byte should be sent and DR has not been written yet (TxE=1). \n– Cleared by software by either a read or write in the DR register or by hardware after a start or \na stop condition in transmission or when PE=0.\nNote: The BTF bit is not set after a NACK reception\nThe BTF bit is not set if next byte to be transmitted is the PEC (TRA=1 in I2C_SR2 \nregister and PEC=1 in I2C_CR1 register)\nBit 1 ADDR: Address sent (master mode)/matched (slave mode)\nThis bit is cleared by software reading SR1 register followed reading SR2, or by hardware \nwhen PE=0.\nAddress matched (Slave)\n0: Address mismatched or not received.\n1: Received address matched.\n– Set by hardware as soon as the received slave address matched with the OAR registers \ncontent or a general call or a SMBus Device Default Address or SMBus Host or SMBus Alert \nis recognized. (when enabled depending on configuration).\nNote: In slave mode, it is recommended to perform the complete clearing sequence (READ \nSR1 then READ SR2) after ADDR is set. Refer to Figure 242.\nAddress sent (Master)\n0: No end of address transmission\n1: End of address transmission\n– For 10-bit addressing, the bit is set after the ACK of the 2nd byte.\n– For 7-bit addressing, the bit is set after the ACK of the byte.\nNote: ADDR is not set after a NACK reception\nBit 0 SB: Start bit (Master mode)\n0: No Start condition\n1: Start condition generated.\n– Set when a Start condition generated.\n– Cleared by software by reading the SR1 register followed by writing the DR register, or by \nhardware when PE=0\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPEC[7:0]\nDUALF\nSMB\nHOST\nSMBDE\nFAULT\nGEN\nCALL\nRes.\nTRA\nBUSY\nMSL\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n" }, { "page_number": 872, "page_indices": { "start_index": 1696186, "end_index": 1698429 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 872 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.6 I2C registers", 863 ], [ 3, "27.6.7 I2C Status register 2 (I2C_SR2)", 871 ] ], "page_content": "Inter-integrated circuit (I2C) interface\nRM0090\n872/1757\nRM0090 Rev 21\n \nNote:\nReading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was \nset after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found \nset in I2C_SR1 or when the STOPF bit is cleared.\nBits 15:8 PEC[7:0] Packet error checking register\nThis register contains the internal PEC when ENPEC=1. \nBit 7 DUALF: Dual flag (Slave mode)\n0: Received address matched with OAR1\n1: Received address matched with OAR2\n– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.\nBit 6 SMBHOST: SMBus host header (Slave mode)\n0: No SMBus Host address\n1: SMBus Host address received when SMBTYPE=1 and ENARP=1.\n– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.\nBit 5 SMBDEFAULT: SMBus device default address (Slave mode) \n0: No SMBus Device Default address\n1: SMBus Device Default address received when ENARP=1\n– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.\nBit 4 GENCALL: General call address (Slave mode) \n0: No General Call\n1: General Call Address received when ENGC=1\n– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.\nBit 3 Reserved, must be kept at reset value\nBit 2 TRA: Transmitter/receiver\n0: Data bytes received\n1: Data bytes transmitted\nThis bit is set depending on the R/W bit of the address byte, at the end of total address \nphase.\nIt is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start \ncondition, loss of bus arbitration (ARLO=1), or when PE=0.\nBit 1 BUSY: Bus busy\n0: No communication on the bus\n1: Communication ongoing on the bus\n– Set by hardware on detection of SDA or SCL low \n– cleared by hardware on detection of a Stop condition. \nIt indicates a communication in progress on the bus. This information is still updated when \nthe interface is disabled (PE=0).\nBit 0 MSL: Master/slave\n0: Slave mode\n1: Master mode\n– Set by hardware as soon as the interface is in Master mode (SB=1). \n– Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration \n(ARLO=1), or by hardware when PE=0. \n" }, { "page_number": 873, "page_indices": { "start_index": 1698429, "end_index": 1700346 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 873 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.6 I2C registers", 863 ], [ 3, "27.6.8 I2C Clock control register (I2C_CCR)", 873 ] ], "page_content": "RM0090 Rev 21\n873/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\n27.6.8 \nI2C Clock control register (I2C_CCR)\nAddress offset: 0x1C\nReset value: 0x0000\nNote:\nfPCLK1 must be at least 2 MHz to achieve Sm mode I²C frequencies. It must be at least 4 \nMHz to achieve Fm mode I²C frequencies. It must be a multiple of 10MHz to reach the \n400 kHz maximum I²C Fm mode clock.\nThe CCR register must be configured only when the I2C is disabled (PE = 0).\n \n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nF/S\nDUTY\nReserved\nCCR[11:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 F/S: I2C master mode selection\n0: Sm mode I2C\n1: Fm mode I2C\nBit 14 DUTY: Fm mode duty cycle \n0: Fm mode tlow/thigh = 2\n1: Fm mode tlow/thigh = 16/9 (see CCR)\nBits 13:12 Reserved, must be kept at reset value\nBits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode) \nControls the SCL clock in master mode.\nSm mode or SMBus:\nThigh = CCR * TPCLK1\nTlow = CCR * TPCLK1\nFm mode:\nIf DUTY = 0:\nThigh = CCR * TPCLK1\nTlow = 2 * CCR * TPCLK1\nIf DUTY = 1: \nThigh = 9 * CCR * TPCLK1\nTlow = 16 * CCR * TPCLK1\nFor instance: in Sm mode, to generate a 100 kHz SCL frequency: \nIf FREQ = 08, TPCLK1 = 125 ns so CCR must be programmed with 0x28\n(0x28 <=> 40d x 125 ns = 5000 ns.)\nNote: The minimum allowed value is 0x04, except in FAST DUTY mode where the minimum \nallowed value is 0x01\nthigh = tr(SCL) + tw(SCLH).\ntlow = tf(SCL) + tw(SCLL).\nWhere the I2C parameters below are part of the I2C standard specification.\n- tr(SCL) = SCL clock rise time from 30% to 70%.\n- tf(SCL) = SCL clock fall time from 70% to 30%.\n- tw(SCLH) = SCL clock high time measure at 70%.\n- tw(SCLL) = SCL clock low time measure at 30%.\nI2C communication speed, fSCL ~ 1/(thigh + tlow). The real frequency may differ due to \nthe analog noise filter input delay.\nThe CCR register must be configured only when the I2C is disabled (PE = 0).\n" }, { "page_number": 874, "page_indices": { "start_index": 1700346, "end_index": 1702536 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 874 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.6 I2C registers", 863 ], [ 3, "27.6.9 I2C TRISE register (I2C_TRISE)", 874 ], [ 3, "27.6.10 I2C FLTR register (I2C_FLTR)", 874 ] ], "page_content": "Inter-integrated circuit (I2C) interface\nRM0090\n874/1757\nRM0090 Rev 21\n27.6.9 \nI2C TRISE register (I2C_TRISE)\nAddress offset: 0x20\nReset value: 0x0002 \n \n27.6.10 \nI2C FLTR register (I2C_FLTR)\nAddress offset: 0x24\nReset value: 0x0000\nThe I2C_FLTR is available on STM32F42xxx and STM32F43xxx only.\n \n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTRISE[5:0]\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:6 Reserved, must be kept at reset value\nBits 5:0 TRISE[5:0]: Maximum rise time in Fm/Sm mode (Master mode)\nThese bits should provide the maximum duration of the SCL feedback loop in master mode. \nThe purpose is to keep a stable SCL frequency whatever the SCL rising edge duration.\nThese bits must be programmed with the maximum SCL rise time given in the I2C bus \nspecification, incremented by 1.\nFor instance: in Sm mode, the maximum allowed SCL rise time is 1000 ns.\nIf, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 0x08 and TPCLK1 = 125 ns \ntherefore the TRISE[5:0] bits must be programmed with 09h.\n(1000 ns / 125 ns = 8 + 1)\nThe filter value can also be added to TRISE[5:0].\nIf the result is not an integer, TRISE[5:0] must be programmed with the integer part, in order \nto respect the tHIGH parameter.\nNote: TRISE[5:0] must be configured only when the I2C is disabled (PE = 0).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nANOFF\nDNF[3:0]\nrw\nrw\nrw\nrw\nrw\nBits 15:5 Reserved, must be kept at reset value\nBit 4 ANOFF: Analog noise filter OFF\n0: Analog noise filter enable\n1: Analog noise filter disable\nNote: ANOFF must be configured only when the I2C is disabled (PE = 0).\nBits 3:0 DNF[3:0]: Digital noise filter\nThese bits are used to configure the digital noise filter on SDA and SCL inputs. The digital filter \nsuppresses the spikes with a length of up to DNF[3:0] * TPCLK1.\n0000: Digital noise filter disable\n0001: Digital noise filter enabled and filtering capability up to 1* TPCLK1.\n...\n1111: Digital noise filter enabled and filtering capability up to 15* TPCLK1.\nNote: DNF[3:0] must be configured only when the I2C is disabled (PE = 0). If the analog filter \nis also enabled, the digital filter is added to the analog filter.\n" }, { "page_number": 875, "page_indices": { "start_index": 1702536, "end_index": 1703938 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 875 }, "toc_details": [ [ 1, "27 Inter-integrated circuit (I2C) interface", 842 ], [ 2, "27.6 I2C registers", 863 ], [ 3, "27.6.11 I2C register map", 875 ] ], "page_content": "RM0090 Rev 21\n875/1757\nRM0090\nInter-integrated circuit (I2C) interface\n875\n27.6.11 \nI2C register map\nThe table below provides the I2C register map and reset values. \n \nRefer to Section 2.3: Memory map for the register boundary addresses table.\nTable 126. I2C register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nI2C_CR1\nReserved\nSWRST\nReserved\nALERT\nPEC\nPOS\nACK\nSTOP\nSTART\nNOSTRETCH\nENGC\nENPEC\nENARP\nSMBTYPE\nReserved\nSMBUS\nPE\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nI2C_CR2\nReserved\nLAST\nDMAEN\nITBUFEN\nITEVTEN\nITERREN\nReserved\nFREQ[5:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nI2C_OAR1\nReserved\nADDMODE\nReserved\nADD[9:8]\nADD[7:1]\nADD0\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nI2C_OAR2\nReserved\nADD2[7:1]\nENDUAL\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nI2C_DR\nReserved\nDR[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nI2C_SR1\nReserved\nSMBALERT\nTIMEOUT\nReserved\nPECERR\nOVR\nAF\nARLO\nBERR\nTxE\nRxNE\nReserved\nSTOPF\nADD10\nBTF\nADDR\nSB\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x18\nI2C_SR2\nReserved\nPEC[7:0]\nDUALF\nSMBHOST\nSMBDEFAUL\nGENCALL\nReserved\nTRA\nBUSY\nMSL\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nI2C_CCR\nReserved\nF/S\nDUTY\nReserved\nCCR[11:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nI2C_TRISE\nReserved\nTRISE[5:0]\nReset value\n0\n0\n0\n0\n1\n0\n0x24\nI2C_FLTR\nReserved\nANOFF\nDNF[3:0]\nReset value\n0\n0\n0\n0\n0\n" }, { "page_number": 876, "page_indices": { "start_index": 1703938, "end_index": 1705915 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 876 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.1 SPI introduction", 876 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n876/1757\nRM0090 Rev 21\n28 \nSerial peripheral interface (SPI)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n28.1 \nSPI introduction\nThe SPI interface provides two main functions, supporting the SPI or the I2S audio protocol. \nBy default, the SPI function is selected. It is possible to switch the interface from SPI to I2S \nby software. \nThe serial peripheral interface (SPI) allows half/ full-duplex, synchronous, serial \ncommunication with external devices. The interface can be configured as the master and in \nthis case it provides the communication clock (SCK) to the external slave device. The \ninterface is also capable of operating in multimaster configuration.\nIt may be used for a variety of purposes, including simplex synchronous transfers on two \nlines with a possible bidirectional data line or reliable communication using CRC checking.\nThe I2S is also a synchronous serial communication interface. It can address four different \naudio standards including the I2S Philips standard, the MSB- and LSB-justified standards, \nand the PCM standard. It can operate as a slave or a master device in full-duplex mode \n(using 4 pins) or in half-duplex mode (using 3 pins). Master clock can be provided by the \ninterface to an external slave component when the I2S is configured as the communication \nmaster.\nWarning:\nSince some SPI1 and SPI3/I2S3 pins may be mapped onto \nsome pins used by the JTAG interface (SPI1_NSS onto JTDI, \nSPI3_NSS/I2S3_WS onto JTDI and SPI3_SCK/I2S3_CK onto \nJTDO), you may either:\n– map SPI/I2S onto other pins\n– disable the JTAG and use the SWD interface prior to \nconfiguring the pins listed as SPI I/Os (when debugging the \napplication) or\n– disable both JTAG/SWD interfaces (for standalone \napplications).\nFor more information on the configuration of the JTAG/SWD \ninterface pins, please refer to Section 8.3.2: I/O pin \nmultiplexer and mapping.\n" }, { "page_number": 877, "page_indices": { "start_index": 1705915, "end_index": 1707084 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 877 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.2 SPI and I2S main features", 877 ], [ 3, "28.2.1 SPI features", 877 ] ], "page_content": "RM0090 Rev 21\n877/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.2 \nSPI and I2S main features\n28.2.1 \nSPI features\n•\nFull-duplex synchronous transfers on three lines\n•\nSimplex synchronous transfers on two lines with or without a bidirectional data line\n•\n8- or 16-bit transfer frame format selection\n•\nMaster or slave operation\n•\nMultimaster mode capability\n•\n8 master mode baud rate prescalers (fPCLK/2 max.)\n•\nSlave mode frequency (fPCLK/2 max)\n•\nFaster communication for both master and slave\n•\nNSS management by hardware or software for both master and slave: dynamic change \nof master/slave operations\n•\nProgrammable clock polarity and phase\n•\nProgrammable data order with MSB-first or LSB-first shifting\n•\nDedicated transmission and reception flags with interrupt capability\n•\nSPI bus busy status flag\n•\nSPI TI mode \n•\nHardware CRC feature for reliable communication:\n–\nCRC value can be transmitted as last byte in Tx mode\n–\nAutomatic CRC error checking for last received byte\n•\nMaster mode fault, overrun and CRC error flags with interrupt capability\n•\n1-byte transmission and reception buffer with DMA capability: Tx and Rx requests\n" }, { "page_number": 878, "page_indices": { "start_index": 1707084, "end_index": 1708587 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 878 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.2 SPI and I2S main features", 877 ], [ 3, "28.2.2 I2S features", 878 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n878/1757\nRM0090 Rev 21\n28.2.2 \nI2S features\n•\nFull duplex communication\n•\nHalf-duplex communication (only transmitter or receiver)\n•\nMaster or slave operations\n•\n8-bit programmable linear prescaler to reach accurate audio sample frequencies (from \n8 kHz to 192 kHz)\n•\nData format may be 16-bit, 24-bit or 32-bit\n•\nPacket frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, 32-bit data \nframe) by audio channel\n•\nProgrammable clock polarity (steady state)\n•\nUnderrun flag in slave transmission mode, overrun flag in reception mode (master and \nslave), and Frame Error flag in reception and transmission mode (slave only)\n•\n16-bit register for transmission and reception with one data register for both channel \nsides\n•\nSupported I2S protocols:\n–\nI2S Phillps standard\n–\nMSB-justified standard (left-justified)\n–\nLSB-justified standard (right-justified)\n–\nPCM standard (with short and long frame synchronization on 16-bit channel frame \nor 16-bit data frame extended to 32-bit channel frame)\n•\nData direction is always MSB first\n•\nDMA capability for transmission and reception (16-bit wide)\n•\nMaster clock may be output to drive an external audio component. Ratio is fixed at \n256 × FS (where FS is the audio sampling frequency)\n•\nBoth I2S (I2S2 and I2S3) have a dedicated PLL (PLLI2S) to generate an even more \naccurate clock.\n•\nI2S (I2S2 and I2S3) clock can be derived from an external clock mapped on the \nI2S_CKIN pin.\n" }, { "page_number": 879, "page_indices": { "start_index": 1708587, "end_index": 1710520 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 879 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.1 General description", 879 ] ], "page_content": "RM0090 Rev 21\n879/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.3 \nSPI functional description\n28.3.1 \nGeneral description\nThe block diagram of the SPI is shown in Figure 246. \nFigure 246. SPI block diagram\nUsually, the SPI is connected to external devices through four pins:\n•\nMISO: Master In / Slave Out data. This pin can be used to transmit data in slave mode \nand receive data in master mode.\n•\nMOSI: Master Out / Slave In data. This pin can be used to transmit data in master \nmode and receive data in slave mode.\n•\nSCK: Serial Clock output for SPI masters and input for SPI slaves.\n•\nNSS: Slave select. This is an optional pin to select a slave device. This pin acts as a \n‘chip select’ to let the SPI master communicate with slaves individually and to avoid \ncontention on the data lines. Slave NSS inputs can be driven by standard IO ports on \nthe master device. The NSS pin may also be used as an output if enabled (SSOE bit) \nand driven low if the SPI is in master configuration. In this manner, all NSS pins from \ndevices connected to the Master NSS pin see a low level and become slaves when \nthey are configured in NSS hardware mode. When configured in master mode with \nNSS configured as an input (MSTR=1 and SSOE=0) and if NSS is pulled low, the SPI \nenters the master mode fault state: the MSTR bit is automatically cleared and the \ndevice is configured in slave mode (refer to Section 28.3.10). \nA basic example of interconnections between a single master and a single slave is \nillustrated in Figure 247.\nMS51604V1\nMOSI\nMISO\nBaud rate generator\nSCK\nMaster control logic\nCommunication control\nSPE\nBR2\nBR1\nBR0\nMSTR\nCPOL\nCPHA\nBR[2:0]\nRXNE\nIE\nLSB\nFIRST\nBIDI\nMODE\nBIDI\nOE\nBSY\nOVR\nMOD\nF\nRXNE\nTXE\nERR\nIE\nTXE\nIE\n0\n0\nDFF\n0\nSSOE\nCRCEN\n0\nRX\nONLY\nCRC\nNext\nCRC\nERR\n0\n1\nNSS\nSPI_CR1\nSPI_CR2\nSPI_SR\nTXDM\nAEN\nRXDM\nAEN\nAddress and data bus\nRead\nRx buffer\nShift register\nLSB first\nTx buffer\nWrite\nSSM\nSSI\n" }, { "page_number": 880, "page_indices": { "start_index": 1710520, "end_index": 1712394 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 880 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.1 General description", 879 ], [ 4, "Slave select (NSS) pin management", 880 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n880/1757\nRM0090 Rev 21\nFigure 247. Single master/ single slave application\n1.\nHere, the NSS pin is configured as an input.\nThe MOSI pins are connected together and the MISO pins are connected together. In this \nway data is transferred serially between master and slave (most significant bit first).\nThe communication is always initiated by the master. When the master device transmits \ndata to a slave device via the MOSI pin, the slave device responds via the MISO pin. This \nimplies full-duplex communication with both data out and data in synchronized with the \nsame clock signal (which is provided by the master device via the SCK pin).\nSlave select (NSS) pin management\nHardware or software slave select management can be set using the SSM bit in the \nSPI_CR1 register.\n•\nSoftware NSS management (SSM = 1)\nThe slave select information is driven internally by the value of the SSI bit in the \nSPI_CR1 register. The external NSS pin remains free for other application uses.\n•\nHardware NSS management (SSM = 0)\nTwo configurations are possible depending on the NSS output configuration (SSOE bit \nin register SPI_CR2).\n–\nNSS output enabled (SSM = 0, SSOE = 1)\nThis configuration is used only when the device operates in master mode. The \nNSS signal is driven low when the master starts the communication and is kept \nlow until the SPI is disabled. \n–\nNSS output disabled (SSM = 0, SSOE = 0)\nThis configuration allows multimaster capability for devices operating in master \nmode. For devices set as slave, the NSS pin acts as a classical NSS input: the \nslave is selected when NSS is low and deselected when NSS high.\n8-bit shift register\nSPI clock\ngenerator\n8-bit shift register\nMISO\nMOSI\nMOSI\nMISO\nSCK\nSCK\nSlave\nMaster\nNSS(1)\nNSS(1)\nVDD\nMSBit\nLSBit\nMSBit\nLSBit\nNot used if NSS is managed\n by software\nai14745\n" }, { "page_number": 881, "page_indices": { "start_index": 1712394, "end_index": 1714208 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 881 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.1 General description", 879 ], [ 4, "Clock phase and clock polarity", 881 ] ], "page_content": "RM0090 Rev 21\n881/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nClock phase and clock polarity\nFour possible timing relationships may be chosen by software, using the CPOL and CPHA \nbits in the SPI_CR1 register. The CPOL (clock polarity) bit controls the steady state value of \nthe clock when no data is being transferred. This bit affects both master and slave modes. If \nCPOL is reset, the SCK pin has a low-level idle state. If CPOL is set, the SCK pin has a \nhigh-level idle state.\nIf the CPHA (clock phase) bit is set, the second edge on the SCK pin (falling edge if the \nCPOL bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data are \nlatched on the occurrence of the second clock transition. If the CPHA bit is reset, the first \nedge on the SCK pin (falling edge if CPOL bit is set, rising edge if CPOL bit is reset) is the \nMSBit capture strobe. Data are latched on the occurrence of the first clock transition.\nThe combination of the CPOL (clock polarity) and CPHA (clock phase) bits selects the data \ncapture clock edge.\nFigure 248, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. \nThe diagram may be interpreted as a master or slave timing diagram where the SCK pin, \nthe MISO pin, the MOSI pin are directly connected between the master and the slave \ndevice.\nNote:\nPrior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit.\nMaster and slave must be programmed with the same timing mode.\nThe idle state of SCK must correspond to the polarity selected in the SPI_CR1 register (by \npulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).\nThe Data Frame Format (8- or 16-bit) is selected through the DFF bit in SPI_CR1 register, \nand determines the data length during transmission/reception.\n" }, { "page_number": 882, "page_indices": { "start_index": 1714208, "end_index": 1714984 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 882 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.1 General description", 879 ], [ 4, "Data frame format", 882 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n882/1757\nRM0090 Rev 21\nFigure 248. Data clock timing diagram\n1.\nThese timings are shown with the LSBFIRST bit reset in the SPI_CR1 register.\nData frame format\nData can be shifted out either MSB-first or LSB-first depending on the value of the \nLSBFIRST bit in the SPI_CR1 register.\nEach data frame is 8 or 16 bits long depending on the size of the data programmed using \nthe DFF bit in the SPI_CR1 register. The selected data frame format is applicable for \ntransmission and/or reception. \nCPOL = 1\nCPOL = 0\nMSBit\nLSBit\nMSBit\nLSBit\nMISO\nMOSI\nNSS\n(to slave)\nCapture strobe\nCPHA =1\nCPOL = 1\nCPOL = 0\nMSBit\nLSBit\nMSBit\nLSBit\nMISO\nMOSI\nNSS\n(to slave)\nCapture strobe\nCPHA =0\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \nai17154d\n" }, { "page_number": 883, "page_indices": { "start_index": 1714984, "end_index": 1717859 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 883 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.2 Configuring the SPI in slave mode", 883 ], [ 4, "Procedure", 883 ], [ 4, "Transmit sequence", 883 ], [ 4, "Receive sequence", 883 ] ], "page_content": "RM0090 Rev 21\n883/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.3.2 \nConfiguring the SPI in slave mode\nIn the slave configuration, the serial clock is received on the SCK pin from the master \ndevice. The value set in the BR[2:0] bits in the SPI_CR1 register, does not affect the data \ntransfer rate.\nNote:\nIt is recommended to enable the SPI slave before the master sends the clock. If not, \nundesired data transmission might occur. The data register of the slave needs to be ready \nbefore the first edge of the communication clock or before the end of the ongoing \ncommunication. It is mandatory to have the polarity of the communication clock set to the \nsteady state value before the slave and the master are enabled.\nFollow the procedure below to configure the SPI in slave mode:\nProcedure\n1.\nSet the DFF bit to define 8- or 16-bit data frame format\n2. \nSelect the CPOL and CPHA bits to define one of the four relationships between the \ndata transfer and the serial clock (see Figure 248). For correct data transfer, the CPOL \nand CPHA bits must be configured in the same way in the slave device and the master \ndevice. This step is not required when the TI mode is selected through the FRF bit in \nthe SPI_CR2 register. \n3. \nThe frame format (MSB-first or LSB-first depending on the value of the LSBFIRST bit in \nthe SPI_CR1 register) must be the same as the master device. This step is not \nrequired when TI mode is selected.\n4. \nIn Hardware mode (refer to Slave select (NSS) pin management), the NSS pin must be \nconnected to a low level signal during the complete byte transmit sequence. In NSS \nsoftware mode, set the SSM bit and clear the SSI bit in the SPI_CR1 register. This step \nis not required when TI mode is selected.\n5. \nSet the FRF bit in the SPI_CR2 register to select the TI mode protocol for serial \ncommunications.\n6. \nClear the MSTR bit and set the SPE bit (both in the SPI_CR1 register) to assign the \npins to alternate functions.\nIn this configuration the MOSI pin is a data input and the MISO pin is a data output.\nTransmit sequence\nThe data byte is parallel-loaded into the Tx buffer during a write cycle.\nThe transmit sequence begins when the slave device receives the clock signal and the most \nsignificant bit of the data on its MOSI pin. The remaining bits (the 7 bits in 8-bit data frame \nformat, and the 15 bits in 16-bit data frame format) are loaded into the shift-register. The \nTXE flag in the SPI_SR register is set on the transfer of data from the Tx Buffer to the shift \nregister and an interrupt is generated if the TXEIE bit in the SPI_CR2 register is set.\nReceive sequence\nFor the receiver, when data transfer is complete:\n•\nThe Data in shift register is transferred to Rx Buffer and the RXNE flag (SPI_SR \nregister) is set\n•\nAn Interrupt is generated if the RXNEIE bit is set in the SPI_CR2 register.\n" }, { "page_number": 884, "page_indices": { "start_index": 1717859, "end_index": 1720266 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 884 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.2 Configuring the SPI in slave mode", 883 ], [ 4, "SPI TI protocol in slave mode", 884 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n884/1757\nRM0090 Rev 21\nAfter the last sampling clock edge the RXNE bit is set, a copy of the data byte received in \nthe shift register is moved to the Rx buffer. When the SPI_DR register is read, the SPI \nperipheral returns this buffered value.\nClearing of the RXNE bit is performed by reading the SPI_DR register.\nSPI TI protocol in slave mode\nIn slave mode, the SPI interface is compatible with the TI protocol. The FRF bit of the \nSPI_CR2 register can be used to configure the slave SPI serial communications to be \ncompliant with this protocol.\nThe clock polarity and phase are forced to conform to the TI protocol requirements whatever \nthe values set in the SPI_CR1 register. NSS management is also specific to the TI protocol \nwhich makes the configuration of NSS management through the SPI_CR1 and SPI_CR2 \nregisters (such as SSM, SSI, SSOE) transparent for the user.\nIn Slave mode (Figure 249: TI mode - Slave mode, single transfer and Figure 250: TI mode \n- Slave mode, continuous transfer), the SPI baud rate prescaler is used to control the \nmoment when the MISO pin state changes to HI-Z. Any baud rate can be used thus allowing \nto determine this moment with optimal flexibility. However, the baud rate is generally set to \nthe external master clock baud rate. The time for the MISO signal to become HI-Z (trelease) \ndepends on internal resynchronizations and on the baud rate value set in through BR[2:0] of \nSPI_CR1 register. It is given by the formula:\nNote:\nThis feature is not available for Motorola SPI communications (FRF bit set to 0).\nTo detect TI frame errors in Slave transmitter only mode by using the Error interrupt (ERRIE \n= 1), the SPI must be configured in 2-line unidirectional mode by setting BIDIMODE and \nBIDIOE to 1 in the SPI_CR1 register. When BIDIMODE is set to 0, OVR is set to 1 because \nthe data register is never read and error interrupt are always generated, while when \nBIDIMODE is set to 1, data are not received and OVR is never set.\nFigure 249. TI mode - Slave mode, single transfer\ntbaud_rate\n2\n----------------------------\n4\ntpclk\n×\n+\ntrelease\ntbaud_rate\n2\n----------------------------\n6\ntpclk\n×\n+\n<\n<\nai18434\nMSBIN\nMOSI\ninput\nNSS\ninput\nSCK\ninput\ntrigger\nedge\nsampling\nedge\ntrigger\nedge\nsampling\nedge\ntrigger\nedge\nsampling\nedge\nDONTCARE\nLSBIN\nDONTCARE\nMISO\noutput\n1 or 0\nMSBOUT\nLSBOUT\ntRelease\n" }, { "page_number": 885, "page_indices": { "start_index": 1720266, "end_index": 1722357 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 885 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.3 Configuring the SPI in master mode", 885 ], [ 4, "Procedure", 885 ], [ 4, "Transmit sequence", 885 ] ], "page_content": "RM0090 Rev 21\n885/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nFigure 250. TI mode - Slave mode, continuous transfer\n28.3.3 \nConfiguring the SPI in master mode\nIn the master configuration, the serial clock is generated on the SCK pin.\nProcedure\n1.\nSelect the BR[2:0] bits to define the serial clock baud rate (see SPI_CR1 register).\n2. \nSelect the CPOL and CPHA bits to define one of the four relationships between the \ndata transfer and the serial clock (see Figure 248). This step is not required when the \nTI mode is selected.\n3. \nSet the DFF bit to define 8- or 16-bit data frame format\n4. \nConfigure the LSBFIRST bit in the SPI_CR1 register to define the frame format. This \nstep is not required when the TI mode is selected.\n5. \nIf the NSS pin is required in input mode, in hardware mode, connect the NSS pin to a \nhigh-level signal during the complete byte transmit sequence. In NSS software mode, \nset the SSM and SSI bits in the SPI_CR1 register. If the NSS pin is required in output \nmode, the SSOE bit only should be set. This step is not required when the TI mode is \nselected.\n6. \nSet the FRF bit in SPI_CR2 to select the TI protocol for serial communications.\n7. \nThe MSTR and SPE bits must be set (they remain set only if the NSS pin is connected \nto a high-level signal).\nIn this configuration the MOSI pin is a data output and the MISO pin is a data input.\nTransmit sequence\nThe transmit sequence begins when a byte is written in the Tx Buffer.\nThe data byte is parallel-loaded into the shift register (from the internal bus) during the first \nbit transmission and then shifted out serially to the MOSI pin MSB first or LSB first \ndepending on the LSBFIRST bit in the SPI_CR1 register. The TXE flag is set on the transfer \nof data from the Tx Buffer to the shift register and an interrupt is generated if the TXEIE bit in \nthe SPI_CR2 register is set.\nai18435\nMSBIN\nMOSI\ninput\nNSS\ninput\nSCK\ninput\ntrigger\nsampling trigger\nsampling trigger\nsampling\nDONTCARE\nLSBIN\nDONTCARE\nMISO\noutput\n1 or 0\nMSBOUT\nLSBOUT\nMSBIN\nLSBIN\nMSBOUT\nLSBOUT\nFRAME 1\nFRAME 2\n" }, { "page_number": 886, "page_indices": { "start_index": 1722357, "end_index": 1724383 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 886 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.3 Configuring the SPI in master mode", 885 ], [ 4, "Receive sequence", 886 ], [ 4, "SPI TI protocol in master mode", 886 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n886/1757\nRM0090 Rev 21\nReceive sequence\nFor the receiver, when data transfer is complete:\n•\nThe data in the shift register is transferred to the RX Buffer and the RXNE flag is set\n•\nAn interrupt is generated if the RXNEIE bit is set in the SPI_CR2 register\nAt the last sampling clock edge the RXNE bit is set, a copy of the data byte received in the \nshift register is moved to the Rx buffer. When the SPI_DR register is read, the SPI \nperipheral returns this buffered value.\nClearing the RXNE bit is performed by reading the SPI_DR register.\nA continuous transmit stream can be maintained if the next data to be transmitted is put in \nthe Tx buffer once the transmission is started. Note that TXE flag should be ‘1 before any \nattempt to write the Tx buffer is made.\nNote:\nWhen a master is communicating with SPI slaves which need to be de-selected between \ntransmissions, the NSS pin must be configured as GPIO or another GPIO must be used and \ntoggled by software. \nSPI TI protocol in master mode\nIn master mode, the SPI interface is compatible with the TI protocol. The FRF bit of the \nSPI_CR2 register can be used to configure the master SPI serial communications to be \ncompliant with this protocol.\nThe clock polarity and phase are forced to conform to the TI protocol requirements whatever \nthe values set in the SPI_CR1 register. NSS management is also specific to the TI protocol \nwhich makes the configuration of NSS management through the SPI_CR1 and SPI_CR2 \nregisters (SSM, SSI, SSOE) transparent for the user.\nFigure 251: TI mode - master mode, single transfer and Figure 252: TI mode - master mode, \ncontinuous transfer) show the SPI master communication waveforms when the TI mode is \nselected in master mode.\nFigure 251. TI mode - master mode, single transfer\nai18436\nMSBIN\nMOSI\ninput\nNSS\noutput\nSCK\noutput\ntrigger\nedge\nsampling\nedge\ntrigger\nedge\nsampling\nedge\ntrigger\nedge\nsampling\nedge\nDONTCARE\nLSBIN\nDONTCARE\nMISO\noutput\n1 or 0\nMSBOUT\nLSBOUT\n" }, { "page_number": 887, "page_indices": { "start_index": 1724383, "end_index": 1726642 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 887 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.4 Configuring the SPI for half-duplex communication", 887 ], [ 4, "1 clock and 1 bidirectional data wire (BIDIMODE = 1)", 887 ], [ 4, "1 clock and 1 unidirectional data wire (BIDIMODE = 0)", 887 ] ], "page_content": "RM0090 Rev 21\n887/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nFigure 252. TI mode - master mode, continuous transfer\n28.3.4 \nConfiguring the SPI for half-duplex communication\nThe SPI is capable of operating in half-duplex mode in 2 configurations.\n•\n1 clock and 1 bidirectional data wire\n•\n1 clock and 1 data wire (receive-only or transmit-only)\n1 clock and 1 bidirectional data wire (BIDIMODE = 1)\nThis mode is enabled by setting the BIDIMODE bit in the SPI_CR1 register. In this mode \nSCK is used for the clock and MOSI in master or MISO in slave mode is used for data \ncommunication. The transfer direction (Input/Output) is selected by the BIDIOE bit in the \nSPI_CR1 register. When this bit is 1, the data line is output otherwise it is input.\n1 clock and 1 unidirectional data wire (BIDIMODE = 0)\nIn this mode, the application can use the SPI either in transmit-only mode or in receive-only \nmode.\n•\nTransmit-only mode is similar to full-duplex mode (BIDIMODE=0, RXONLY=0): the \ndata are transmitted on the transmit pin (MOSI in master mode or MISO in slave mode) \nand the receive pin (MISO in master mode or MOSI in slave mode) can be used as a \ngeneral-purpose IO. In this case, the application just needs to ignore the Rx buffer (if \nthe data register is read, it does not contain the received value).\n•\nIn receive-only mode, the application can disable the SPI output function by setting the \nRXONLY bit in the SPI_CR1 register. In this case, it frees the transmit IO pin (MOSI in \nmaster mode or MISO in slave mode), so it can be used for other purposes.\nTo start the communication in receive-only mode, configure and enable the SPI:\n•\nIn master mode, the communication starts immediately and stops when the SPE bit is \ncleared and the current reception stops. There is no need to read the BSY flag in this \nmode. It is always set when an SPI communication is ongoing.\n•\nIn slave mode, the SPI continues to receive as long as the NSS is pulled down (or the \nSSI bit is cleared in NSS software mode) and the SCK is running.\nai18437\nMSBOUT\nMOSI\noutput\nNSS\noutput\nSCK\noutput\ntrigger\nsampling trigger\nsampling trigger\nsampling\nDONTCARE\nLSBOUT\nDONTCARE\nMISO\nintput\n1 or 0\nMSBIN\nLSBIN\nMSBOUT\nLSBOUT\nMSBIN\nLSBIN\nFRAME 1\nFRAME 2\n" }, { "page_number": 888, "page_indices": { "start_index": 1726642, "end_index": 1729035 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 888 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.5 Data transmission and reception procedures", 888 ], [ 4, "Rx and Tx buffers", 888 ], [ 4, "Start sequence in master mode", 888 ], [ 4, "Start sequence in slave mode", 888 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n888/1757\nRM0090 Rev 21\n28.3.5 \nData transmission and reception procedures\nRx and Tx buffers\nIn reception, data are received and then stored into an internal Rx buffer while In \ntransmission, data are first stored into an internal Tx buffer before being transmitted.\nA read access of the SPI_DR register returns the Rx buffered value whereas a write access \nto the SPI_DR stores the written data into the Tx buffer.\nStart sequence in master mode\n•\nIn full-duplex (BIDIMODE=0 and RXONLY=0)\n–\nThe sequence begins when data are written into the SPI_DR register (Tx buffer).\n–\nThe data are then parallel loaded from the Tx buffer into the 8-bit shift register \nduring the first bit transmission and then shifted out serially to the MOSI pin.\n–\nAt the same time, the received data on the MISO pin is shifted in serially to the 8-\nbit shift register and then parallel loaded into the SPI_DR register (Rx buffer).\n•\nIn unidirectional receive-only mode (BIDIMODE=0 and RXONLY=1)\n–\nThe sequence begins as soon as SPE=1\n–\nOnly the receiver is activated and the received data on the MISO pin are shifted in \nserially to the 8-bit shift register and then parallel loaded into the SPI_DR register \n(Rx buffer).\n•\nIn bidirectional mode, when transmitting (BIDIMODE=1 and BIDIOE=1)\n–\nThe sequence begins when data are written into the SPI_DR register (Tx buffer).\n–\nThe data are then parallel loaded from the Tx buffer into the 8-bit shift register \nduring the first bit transmission and then shifted out serially to the MOSI pin.\n–\nNo data are received.\n•\nIn bidirectional mode, when receiving (BIDIMODE=1 and BIDIOE=0)\n–\nThe sequence begins as soon as SPE=1 and BIDIOE=0.\n–\nThe received data on the MOSI pin are shifted in serially to the 8-bit shift register \nand then parallel loaded into the SPI_DR register (Rx buffer).\n–\nThe transmitter is not activated and no data are shifted out serially to the MOSI \npin.\nStart sequence in slave mode\n•\nIn full-duplex mode (BIDIMODE=0 and RXONLY=0)\n–\nThe sequence begins when the slave device receives the clock signal and the first \nbit of the data on its MOSI pin. The 7 remaining bits are loaded into the shift \nregister.\n–\nAt the same time, the data are parallel loaded from the Tx buffer into the 8-bit shift \nregister during the first bit transmission, and then shifted out serially to the MISO \n" }, { "page_number": 889, "page_indices": { "start_index": 1729035, "end_index": 1731753 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 889 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.5 Data transmission and reception procedures", 888 ], [ 4, "Handling data transmission and reception", 889 ] ], "page_content": "RM0090 Rev 21\n889/1757\nRM0090\nSerial peripheral interface (SPI)\n928\npin. The software must have written the data to be sent before the SPI master \ndevice initiates the transfer.\n•\nIn unidirectional receive-only mode (BIDIMODE=0 and RXONLY=1)\n–\nThe sequence begins when the slave device receives the clock signal and the first \nbit of the data on its MOSI pin. The 7 remaining bits are loaded into the shift \nregister.\n–\nThe transmitter is not activated and no data are shifted out serially to the MISO \npin.\n•\nIn bidirectional mode, when transmitting (BIDIMODE=1 and BIDIOE=1)\n–\nThe sequence begins when the slave device receives the clock signal and the first \nbit in the Tx buffer is transmitted on the MISO pin.\n–\nThe data are then parallel loaded from the Tx buffer into the 8-bit shift register \nduring the first bit transmission and then shifted out serially to the MISO pin. The \nsoftware must have written the data to be sent before the SPI master device \ninitiates the transfer.\n–\nNo data are received.\n•\nIn bidirectional mode, when receiving (BIDIMODE=1 and BIDIOE=0)\n–\nThe sequence begins when the slave device receives the clock signal and the first \nbit of the data on its MISO pin.\n–\nThe received data on the MISO pin are shifted in serially to the 8-bit shift register \nand then parallel loaded into the SPI_DR register (Rx buffer).\n–\nThe transmitter is not activated and no data are shifted out serially to the MISO \npin.\nHandling data transmission and reception\nThe TXE flag (Tx buffer empty) is set when the data are transferred from the Tx buffer to the \nshift register. It indicates that the internal Tx buffer is ready to be loaded with the next data. \nAn interrupt can be generated if the TXEIE bit in the SPI_CR2 register is set. Clearing the \nTXE bit is performed by writing to the SPI_DR register.\nNote:\nThe software must ensure that the TXE flag is set to 1 before attempting to write to the Tx \nbuffer. Otherwise, it overwrites the data previously written to the Tx buffer.\nThe RXNE flag (Rx buffer not empty) is set on the last sampling clock edge, when the data \nare transferred from the shift register to the Rx buffer. It indicates that data are ready to be \nread from the SPI_DR register. An interrupt can be generated if the RXNEIE bit in the \nSPI_CR2 register is set. Clearing the RXNE bit is performed by reading the SPI_DR \nregister.\nFor some configurations, the BSY flag can be used during the last data transfer to wait until \nthe completion of the transfer.\nFull-duplex transmit and receive procedure in master or slave mode (BIDIMODE=0 and \nRXONLY=0)\nThe software has to follow this procedure to transmit and receive data (see Figure 253 and \nFigure 254):\n" }, { "page_number": 890, "page_indices": { "start_index": 1731753, "end_index": 1733551 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 890 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.5 Data transmission and reception procedures", 888 ], [ 4, "Handling data transmission and reception", 889 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n890/1757\nRM0090 Rev 21\n1.\nEnable the SPI by setting the SPE bit to 1.\n2. \nWrite the first data item to be transmitted into the SPI_DR register (this clears the TXE \nflag).\n3. \nWait until TXE=1 and write the second data item to be transmitted. Then wait until \nRXNE=1 and read the SPI_DR to get the first received data item (this clears the RXNE \nbit). Repeat this operation for each data item to be transmitted/received until the n–1 \nreceived data.\n4. \nWait until RXNE=1 and read the last received data.\n5. \nWait until TXE=1 and then wait until BSY=0 before disabling the SPI.\nThis procedure can also be implemented using dedicated interrupt subroutines launched at \neach rising edges of the RXNE or TXE flag.\nFigure 253. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and\nRXONLY=0) in case of continuous transfers\nMISO/MOSI (in)\nTx buffer\nDATA1 = 0xA1\n TXE flag\n0xF2\nBSY flag\n0xF3\nsoftware \nwrites 0xF1 \ninto SPI_DR\nsoftware waits \nuntil TXE=1 and \nwrites 0xF2 into \nSPI_DR\nsoftware waits \nuntil RXNE=1 \nand reads 0xA1 \nfrom SPI_DR\nset by hardware\ncleared by software\nset by hardware\ncleared by software\nset by hardware\nset by hardware\nSCK\nDATA 2 = 0xA2\nDATA 3 = 0xA3\nreset by hardware\nExample in Master mode with CPOL=1, CPHA=1\n0xF1\n RXNE flag\n(write SPI_DR)\nRx buffer\nset by hardware\nMISO/MOSI (out)\nDATA1 = 0xF1\nDATA2 = 0xF2\nDATA3 = 0xF3\n(read SPI_DR)\n0xA1\n0xA2\n0xA3\nsoftware waits \nuntil TXE=1 and \nwrites 0xF3 into \nSPI_DR\nsoftware waits \nuntil RXNE=1 \nand reads 0xA2 \nfrom SPI_ DR\nsoftware waits \nuntil RXNE=1 \nand reads 0xA3 \nfrom SPI_DR\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7\ncleared by software\nai17343\n" }, { "page_number": 891, "page_indices": { "start_index": 1733551, "end_index": 1735893 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 891 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.5 Data transmission and reception procedures", 888 ], [ 4, "Transmit-only procedure (BIDIMODE=0 RXONLY=0)", 891 ] ], "page_content": "RM0090 Rev 21\n891/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nFigure 254. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0,\nRXONLY=0) in case of continuous transfers\nTransmit-only procedure (BIDIMODE=0 RXONLY=0)\nIn this mode, the procedure can be reduced as described below and the BSY bit can be \nused to wait until the completion of the transmission (see Figure 255 and Figure 256).\n1.\nEnable the SPI by setting the SPE bit to 1.\n2. \nWrite the first data item to send into the SPI_DR register (this clears the TXE bit).\n3. \nWait until TXE=1 and write the next data item to be transmitted. Repeat this step for \neach data item to be transmitted.\n4. \nAfter writing the last data item into the SPI_DR register, wait until TXE=1, then wait until \nBSY=0, this indicates that the transmission of the last data is complete.\nThis procedure can be also implemented using dedicated interrupt subroutines launched at \neach rising edge of the TXE flag.\nNote:\nDuring discontinuous communications, there is a 2 APB clock period delay between the \nwrite operation to SPI_DR and the BSY bit setting. As a consequence, in transmit-only \nmode, it is mandatory to wait first until TXE is set and then until BSY is cleared after writing \nthe last data.\nAfter transmitting two data items in transmit-only mode, the OVR flag is set in the SPI_SR \nregister since the received data are never read.\n0xF1\nset by cleared by software\nMISO/MOSI (in)\nTx buffer\nDATA 1 = 0xA1\n TXE flag\n0xF2\nBSY flag\n0xF3\nsoftware \nwrites 0xF1 \ninto SPI_DR\nsoftware waits \nuntil TXE=1 and \nwrites 0xF2 into \nSPI_DR\nsoftware waits \nuntil RXNE=1 \nand reads 0xA1 \nfrom SPI_DR\nset by hardware\ncleared by software\nset by hardware\ncleared by software\nset by hardware\nSCK\nDATA 2 = 0xA2\nDATA 3 = 0xA3\nreset by hardware\nExample in Slave mode with CPOL=1, CPHA=1\n RXNE flag\n(write to SPI_DR)\nRx buffer\nset by hardware\nMISO/MOSI (out)\nDATA 1 = 0xF1\nDATA 2 = 0xF2\nDATA 3 = 0xF3\n(read from SPI_DR)\n0xA1\n0xA2\n0xA3\nsoftware waits \nuntil TXE=1 and \nwrites 0xF3 into \nSPI_DR\nsoftware waits \nuntil RXNE=1 \nand reads 0xA2 \nfrom SPI_ DR\nsoftware waits \nuntil RXNE=1 \nand reads 0xA3 \nfrom SPI_DR\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7\ncleared by software\nai17344\n" }, { "page_number": 892, "page_indices": { "start_index": 1735893, "end_index": 1737742 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 892 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.5 Data transmission and reception procedures", 888 ], [ 4, "Bidirectional transmit procedure (BIDIMODE=1 and BIDIOE=1)", 892 ], [ 4, "Unidirectional receive-only procedure (BIDIMODE=0 and RXONLY=1)", 892 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n892/1757\nRM0090 Rev 21\nFigure 255. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0)\nin case of continuous transfers\nFigure 256. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of \ncontinuous transfers\nBidirectional transmit procedure (BIDIMODE=1 and BIDIOE=1)\nIn this mode, the procedure is similar to the procedure in Transmit-only mode except that \nthe BIDIMODE and BIDIOE bits both have to be set in the SPI_CR2 register before enabling \nthe SPI.\nUnidirectional receive-only procedure (BIDIMODE=0 and RXONLY=1)\nIn this mode, the procedure can be reduced as described below (see Figure 257):\n0xF1\nTx buffer\nTXE flag\n0xF2\nBSY flag\n0xF3\nsoftware writes \n0xF1 into \nSPI_DR\nsoftware waits \nuntil TXE=1 and \nwrites 0xF2 into \nSPI_DR\nset by hardware\ncleared by software\nset by hardware\ncleared by software\nset by hardware\nset by hardware\nSCK\nreset by hardware\nExample in Master mode with CPOL=1, CPHA=1\n(write to SPI_DR)\nMISO/MOSI (out)\nDATA 1 = 0xF1\nDATA 2 = 0xF2\nDATA 3 = 0xF3\nsoftware waits \nuntil TXE=1 and \nwrites 0xF3 into \nSPI_DR\nsoftware waits until BSY=0\nsoftware waits until TXE=1 \nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7\nai17345\n0xF1\nTx buffer\nTXE flag\n0xF2\nBSY flag\n0xF3\nsoftware writes \n0xF1 into \nSPI_DR\nsoftware waits \nuntil TXE=1 and \nwrites 0xF2 into \nSPI_DR\nset by hardware\ncleared by software\nset by hardware\ncleared by software\nset by hardware\nset by hardware\nSCK\nreset by hardware\nExample in slave mode with CPOL=1, CPHA=1\n(write to SPI_DR)\nMISO/MOSI (out)\nDATA 1 = 0xF1\nDATA 2 = 0xF2\nDATA 3 = 0xF3\nsoftware waits \nuntil TXE=1 and \nwrites 0xF3 into \nSPI_DR\nsoftware waits until BSY=0\nsoftware waits until TXE=1 \nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3 b4 b5\nb6\nb7 b0 b1\nb2\nb3 b4 b5\nb6\nb7\nai17346\n" }, { "page_number": 893, "page_indices": { "start_index": 1737742, "end_index": 1740173 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 893 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.5 Data transmission and reception procedures", 888 ], [ 4, "Bidirectional receive procedure (BIDIMODE=1 and BIDIOE=0)", 893 ], [ 4, "Continuous and discontinuous transfers", 893 ] ], "page_content": "RM0090 Rev 21\n893/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n1.\nSet the RXONLY bit in the SPI_CR1 register.\n2. \nEnable the SPI by setting the SPE bit to 1:\na) \nIn master mode, this immediately activates the generation of the SCK clock, and \ndata are serially received until the SPI is disabled (SPE=0).\nb) \nIn slave mode, data are received when the SPI master device drives NSS low and \ngenerates the SCK clock.\n3. \nWait until RXNE=1 and read the SPI_DR register to get the received data (this clears \nthe RXNE bit). Repeat this operation for each data item to be received.\nThis procedure can also be implemented using dedicated interrupt subroutines launched at \neach rising edge of the RXNE flag.\nNote:\nIf it is required to disable the SPI after the last transfer, follow the recommendation \ndescribed in Section 28.3.8.\nFigure 257. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1)\nin case of continuous transfers\nBidirectional receive procedure (BIDIMODE=1 and BIDIOE=0)\nIn this mode, the procedure is similar to the Receive-only mode procedure except that the \nBIDIMODE bit has to be set and the BIDIOE bit cleared in the SPI_CR2 register before \nenabling the SPI.\nContinuous and discontinuous transfers\nWhen transmitting data in master mode, if the software is fast enough to detect each rising \nedge of TXE (or TXE interrupt) and to immediately write to the SPI_DR register before the \nongoing data transfer is complete, the communication is said to be continuous. In this case, \nthere is no discontinuity in the generation of the SPI clock between each data item and the \nBSY bit is never cleared between each data transfer.\nOn the contrary, if the software is not fast enough, this can lead to some discontinuities in \nthe communication. In this case, the BSY bit is cleared between each data transmission \n(see Figure 258).\nIn Master receive-only mode (RXONLY=1), the communication is always continuous and \nthe BSY flag is always read at 1.\nMISO/MOSI (in)\nDATA 1 = 0xA1\nsoftware waits until RXNE=1 \nand reads 0xA1 from SPI_DR\nSCK\nDATA 2 = 0xA2\nDATA 3 = 0xA3\nExample with CPOL=1, CPHA=1, RXONLY=1\n RXNE flag\nRx buffer\nset by hardware\n(read from SPI_DR)\n0xA1\n0xA2\n0xA3\nsoftware waits until RXNE=1 \nand reads 0xA2 from SPI_DR\nsoftware waits until RXNE=1 \nand reads 0xA3 from SPI_DR\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7\ncleared by software\nai17347\n" }, { "page_number": 894, "page_indices": { "start_index": 1740173, "end_index": 1742770 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 894 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.6 CRC calculation", 894 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n894/1757\nRM0090 Rev 21\nIn slave mode, the continuity of the communication is decided by the SPI master device. In \nany case, even if the communication is continuous, the BSY flag goes low between each \ntransfer for a minimum duration of one SPI clock cycle (see Figure 256).\nFigure 258. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) \nin case of discontinuous transfers\n28.3.6 \nCRC calculation\nA CRC calculator has been implemented for communication reliability. Separate CRC \ncalculators are implemented for transmitted data and received data. The CRC is calculated \nusing a programmable polynomial serially on each bit. It is calculated on the sampling clock \nedge defined by the CPHA and CPOL bits in the SPI_CR1 register.\nNote:\nThis SPI offers two kinds of CRC calculation standard which depend directly on the data \nframe format selected for the transmission and/or reception: 8-bit data (CR8) and 16-bit data \n(CRC16).\nCRC calculation is enabled by setting the CRCEN bit in the SPI_CR1 register. This action \nresets the CRC registers (SPI_RXCRCR and SPI_TXCRCR). In full duplex or transmitter \nonly mode, when the transfers are managed by the software (CPU mode), it is necessary to \nwrite the bit CRCNEXT immediately after the last data to be transferred is written to the \nSPI_DR. At the end of this last data transfer, the SPI_TXCRCR value is transmitted.\nIn receive only mode and when the transfers are managed by software (CPU mode), it is \nnecessary to write the CRCNEXT bit after the second last data has been received. The CRC \nis received just after the last data reception and the CRC check is then performed.\nAt the end of data and CRC transfers, the CRCERR flag in the SPI_SR register is set if \ncorruption occurs during the transfer.\nIf data are present in the TX buffer, the CRC value is transmitted only after the transmission \nof the data byte. During CRC transmission, the CRC calculator is switched off and the \nregister value remains unchanged.\nSPI communication using the CRC is possible through the following procedure:\nMOSI (out)\nTx buffer\nDATA 1 = 0xF1\nTXE flag\n0xF1\nBSY flag\n0xF2\nsoftware writes 0xF1 \ninto SPI_DR\nsoftware waits until TXE=1 but is \nlate to write 0xF2 into SPI_DR\nsoftware waits until TXE=1 but \nis late to write 0xF3 into \nSPI_DR\nSCK\n3\nF\nx\n0\n \n=\n \n3\n \nA\nT\nA\nD\n2\nF\nx\n0\n \n=\n \n2\n \nA\nT\nA\nD\nExample with CPOL=1, CPHA=1\n0xF3\nsoftware waits \nuntil TXE=1\nsoftware waits until BSY=0\n(write to SPI_DR)\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7\nai17348\n" }, { "page_number": 895, "page_indices": { "start_index": 1742770, "end_index": 1745889 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 895 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.6 CRC calculation", 894 ] ], "page_content": "RM0090 Rev 21\n895/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n1.\nProgram the CPOL, CPHA, LSBFirst, BR, SSM, SSI and MSTR values.\n2. \nProgram the polynomial in the SPI_CRCPR register.\n3. \nEnable the CRC calculation by setting the CRCEN bit in the SPI_CR1 register. This \nalso clears the SPI_RXCRCR and SPI_TXCRCR registers.\n4. \nEnable the SPI by setting the SPE bit in the SPI_CR1 register.\n5. \nStart the communication and sustain the communication until all but one byte or half-\nword have been transmitted or received.\n–\nIn full duplex or transmitter-only mode, when the transfers are managed by \nsoftware, when writing the last byte or half word to the Tx buffer, set the \nCRCNEXT bit in the SPI_CR1 register to indicate that the CRC is transmitted after \nthe transmission of the last byte.\n–\nIn receiver only mode, set the bit CRCNEXT just after the reception of the second \nto last data to prepare the SPI to enter in CRC Phase at the end of the reception of \nthe last data. CRC calculation is frozen during the CRC transfer. \n6. \nAfter the transfer of the last byte or half word, the SPI enters the CRC transfer and \ncheck phase. In full duplex mode or receiver-only mode, the received CRC is \ncompared to the SPI_RXCRCR value. If the value does not match, the CRCERR flag in \nSPI_SR is set and an interrupt can be generated when the ERRIE bit in the SPI_CR2 \nregister is set.\nNote:\nWhen the SPI is in slave mode, be careful to enable CRC calculation only when the clock is \nstable, that is, when the clock is in the steady state. If not, a wrong CRC calculation may be \ndone. In fact, the CRC is sensitive to the SCK slave input clock as soon as CRCEN is set, \nand this, whatever the value of the SPE bit.\nWith high bitrate frequencies, be careful when transmitting the CRC. As the number of used \nCPU cycles has to be as low as possible in the CRC transfer phase, it is forbidden to call \nsoftware functions in the CRC transmission sequence to avoid errors in the last data and \nCRC reception. In fact, CRCNEXT bit has to be written before the end of the \ntransmission/reception of the last data.\nFor high bit rate frequencies, it is advised to use the DMA mode to avoid the degradation of \nthe SPI speed performance due to CPU accesses impacting the SPI bandwidth.\nWhen the devices are configured as slaves and the NSS hardware mode is used, the NSS \npin needs to be kept low between the data phase and the CRC phase.\nWhen the SPI is configured in slave mode with the CRC feature enabled, CRC calculation \ntakes place even if a high level is applied on the NSS pin. This may happen for example in \ncase of a multislave environment where the communication master addresses slaves \nalternately.\nBetween a slave deselection (high level on NSS) and a new slave selection (low level on \nNSS), the CRC value should be cleared on both master and slave sides in order to \nresynchronize the master and slave for their respective CRC calculation.\nTo clear the CRC, follow the procedure below:\n1.\nDisable SPI (SPE = 0)\n2. \nClear the CRCEN bit\n3. \nSet the CRCEN bit\n4. \nEnable the SPI (SPE = 1)\n" }, { "page_number": 896, "page_indices": { "start_index": 1745889, "end_index": 1747902 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 896 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.7 Status flags", 896 ], [ 4, "Tx buffer empty flag (TXE)", 896 ], [ 4, "Rx buffer not empty (RXNE)", 896 ], [ 4, "BUSY flag", 896 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n896/1757\nRM0090 Rev 21\n28.3.7 \nStatus flags\nFour status flags are provided for the application to completely monitor the state of the SPI \nbus.\nTx buffer empty flag (TXE)\nWhen it is set, this flag indicates that the Tx buffer is empty and the next data to be \ntransmitted can be loaded into the buffer. The TXE flag is cleared when writing to the \nSPI_DR register.\nRx buffer not empty (RXNE)\nWhen set, this flag indicates that there are valid received data in the Rx buffer. It is cleared \nwhen SPI_DR is read.\nBUSY flag\nThis BSY flag is set and cleared by hardware (writing to this flag has no effect). The BSY \nflag indicates the state of the communication layer of the SPI.\nWhen BSY is set, it indicates that the SPI is busy communicating. There is one exception in \nmaster mode / bidirectional receive mode (MSTR=1 and BDM=1 and BDOE=0) where the \nBSY flag is kept low during reception.\nThe BSY flag is useful to detect the end of a transfer if the software wants to disable the SPI \nand enter Halt mode (or disable the peripheral clock). This avoids corrupting the last \ntransfer. For this, the procedure described below must be strictly respected.\nThe BSY flag is also useful to avoid write collisions in a multimaster system.\nThe BSY flag is set when a transfer starts, with the exception of master mode / bidirectional \nreceive mode (MSTR=1 and BDM=1 and BDOE=0).\nIt is cleared:\n•\nwhen a transfer is finished (except in master mode if the communication is continuous)\n•\nwhen the SPI is disabled\n•\nwhen a master mode fault occurs (MODF=1)\nWhen communication is not continuous, the BSY flag is low between each communication.\nWhen communication is continuous:\n•\nin master mode, the BSY flag is kept high during all the transfers\n•\nin slave mode, the BSY flag goes low for one SPI clock cycle between each transfer\nNote:\nDo not use the BSY flag to handle each data transmission or reception. It is better to use the \nTXE and RXNE flags instead.\n" }, { "page_number": 897, "page_indices": { "start_index": 1747902, "end_index": 1750155 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 897 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.8 Disabling the SPI", 897 ], [ 4, "In master or slave full-duplex mode (BIDIMODE=0, RXONLY=0)", 897 ], [ 4, "In master or slave unidirectional transmit-only mode (BIDIMODE=0, RXONLY=0) or bidirectional transmit mode (BIDIMODE=1, BIDIOE=1)", 897 ], [ 4, "In master unidirectional receive-only mode (MSTR=1, BIDIMODE=0, RXONLY=1) or bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0)", 897 ] ], "page_content": "RM0090 Rev 21\n897/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.3.8 \nDisabling the SPI\nWhen a transfer is terminated, the application can stop the communication by disabling the \nSPI peripheral. This is done by clearing the SPE bit.\nFor some configurations, disabling the SPI and entering the Halt mode while a transfer is \nongoing can cause the current transfer to be corrupted and/or the BSY flag might become \nunreliable.\nTo avoid any of those effects, it is recommended to respect the following procedure when \ndisabling the SPI:\nIn master or slave full-duplex mode (BIDIMODE=0, RXONLY=0)\n1.\nWait until RXNE=1 to receive the last data\n2. \nWait until TXE=1\n3. \nThen wait until BSY=0\n4. \nDisable the SPI (SPE=0) and, eventually, enter the Halt mode (or disable the peripheral \nclock)\nIn master or slave unidirectional transmit-only mode (BIDIMODE=0, \nRXONLY=0) or bidirectional transmit mode (BIDIMODE=1, BIDIOE=1)\nAfter the last data is written into the SPI_DR register:\n1.\nWait until TXE=1\n2. \nThen wait until BSY=0\n3. \nDisable the SPI (SPE=0) and, eventually, enter the Halt mode (or disable the peripheral \nclock)\nIn master unidirectional receive-only mode (MSTR=1, BIDIMODE=0, \nRXONLY=1) or bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0)\nThis case must be managed in a particular way to ensure that the SPI does not initiate a \nnew transfer. The sequence below is valid only for SPI Motorola configuration (FRF bit set to \n0):\n1.\nWait for the second to last occurrence of RXNE=1 (n–1)\n2. \nThen wait for one SPI clock cycle (using a software loop) before disabling the SPI \n(SPE=0)\n3. \nThen wait for the last RXNE=1 before entering the Halt mode (or disabling the \nperipheral clock)\nWhen the SPI is configured in TI mode (Bit FRF set to 1), the following procedure has to be \nrespected to avoid generating an undesired pulse on NSS when the SPI is disabled:\n1.\nWait for the second to last occurrence of RXNE = 1 (n-1).\n2. \nDisable the SPI (SPE = 0) in the following window frame using a software loop:\n–\nAfter at least one SPI clock cycle,\n–\nBefore the beginning of the LSB data transfer.\nNote:\nIn master bidirectional receive mode (MSTR=1 and BDM=1 and BDOE=0), the BSY flag is \nkept low during transfers.\n" }, { "page_number": 898, "page_indices": { "start_index": 1750155, "end_index": 1752333 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 898 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.8 Disabling the SPI", 897 ], [ 4, "In slave receive-only mode (MSTR=0, BIDIMODE=0, RXONLY=1) or bidirectional receive mode (MSTR=0, BIDIMODE=1, BIDOE=0)", 898 ], [ 3, "28.3.9 SPI communication using DMA (direct memory addressing)", 898 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n898/1757\nRM0090 Rev 21\nIn slave receive-only mode (MSTR=0, BIDIMODE=0, RXONLY=1) or \nbidirectional receive mode (MSTR=0, BIDIMODE=1, BIDOE=0)\n1.\nYou can disable the SPI (write SPE=1) at any time: the current transfer completes \nbefore the SPI is effectively disabled\n2. \nThen, if you want to enter the Halt mode, you must first wait until BSY = 0 before \nentering the Halt mode (or disabling the peripheral clock).\n28.3.9 \nSPI communication using DMA (direct memory addressing)\nTo operate at its maximum speed, the SPI needs to be fed with the data for transmission \nand the data received on the Rx buffer should be read to avoid overrun. To facilitate the \ntransfers, the SPI features a DMA capability implementing a simple request/acknowledge \nprotocol.\nA DMA access is requested when the enable bit in the SPI_CR2 register is enabled. \nSeparate requests must be issued to the Tx and Rx buffers (see Figure 259 and \nFigure 260):\n•\nIn transmission, a DMA request is issued each time TXE is set to 1. The DMA then \nwrites to the SPI_DR register (this clears the TXE flag).\n•\nIn reception, a DMA request is issued each time RXNE is set to 1. The DMA then reads \nthe SPI_DR register (this clears the RXNE flag).\nWhen the SPI is used only to transmit data, it is possible to enable only the SPI Tx DMA \nchannel. In this case, the OVR flag is set because the data received are not read.\nWhen the SPI is used only to receive data, it is possible to enable only the SPI Rx DMA \nchannel.\nIn transmission mode, when the DMA has written all the data to be transmitted (flag TCIF is \nset in the DMA_ISR register), the BSY flag can be monitored to ensure that the SPI \ncommunication is complete. This is required to avoid corrupting the last transmission before \ndisabling the SPI or entering the Stop mode. The software must first wait until TXE=1 and \nthen until BSY=0.\nNote:\nDuring discontinuous communications, there is a 2 APB clock period delay between the \nwrite operation to SPI_DR and the BSY bit setting. As a consequence, it is mandatory to \nwait first until TXE=1 and then until BSY=0 after writing the last data.\n" }, { "page_number": 899, "page_indices": { "start_index": 1752333, "end_index": 1753872 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 899 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.9 SPI communication using DMA (direct memory addressing)", 898 ] ], "page_content": "RM0090 Rev 21\n899/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nFigure 259. Transmission using DMA\nFigure 260. Reception using DMA\n0xF1\nTx buffer\nTXE flag\n0xF2\nBSY flag\n0xF3\nset by hardware\nclear by DMA write\nset by hardware\ncleared by DMA write\nset by hardware\nset by hardware\nSCK\nreset\nExample with CPOL=1, CPHA=1\n(write to SPI_DR)\nMISO/MOSI (out)\nDATA 1 = 0xF1\nDATA 2 = 0xF2\nDATA 3 = 0xF3\nsoftware configures the \nDMA SPI Tx channel\nto send 3 data items\nand enables the SPI\nDMA writes to SPI_DR\nDMA request\nignored by the DMA because\nDMA TCIF flag\nset by hardware\nclear by software\nDMA writes \nDATA1 into \nSPI_DR\nby hardware\nDMA writes \nDATA2 into \nSPI_DR\nDMA writes \nDATA3 into \nSPI_DR\nsoftware waits until BSY=0\n(DMA transfer complete)\nDMA transfer is \ncomplete (TCIF=1 in \nDMA_ISR)\nsoftware waits \nuntil TXE=1\nDMA transfer is complete\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3\nb4 b5\nb6\nb7\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7\nai17349\nMISO/MOSI (in)\nDATA 1 = 0xA1\nsoftware configures the \nDMA SPI Rx channel\nto receive 3 data items\nand enables the SPI\nSCK\nDATA 2 = 0xA2\nDATA 3 = 0xA3\nExample with CPOL=1, CPHA=1\nRXNE flag\nRx buffer\nset by hardware\n(read from SPI_DR)\n0xA1\n0xA2\n0xA3\nDMA request\nDMA reads \nDATA3 from \nSPI_DR\nflag DMA TCIF\nset by hardware\nclear \nby software\nDMA read from SPI_DR\nThe DMA transfer is \ncomplete (TCIF=1 in \nDMA_ISR)\nDMA reads \nDATA2 from \nSPI_DR\nDMA reads \nDATA1 from \nSPI_DR\n(DMA transfer complete)\nb0 b1\nb2\nb3\nb4 b5\nb6\nb7 b0 b1\nb2\nb3 b4 b5\nb6\nb7 b0 b1\nb2\nb3 b4 b5\nb6\nb7\nclear by DMA read\nai17350\n" }, { "page_number": 900, "page_indices": { "start_index": 1753872, "end_index": 1756458 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 900 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.9 SPI communication using DMA (direct memory addressing)", 898 ], [ 4, "DMA capability with CRC", 900 ], [ 3, "28.3.10 Error flags", 900 ], [ 4, "Master mode fault (MODF)", 900 ], [ 4, "Overrun condition", 900 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n900/1757\nRM0090 Rev 21\nDMA capability with CRC\nWhen SPI communication is enabled with CRC communication and DMA mode, the \ntransmission and reception of the CRC at the end of communication are automatic that is \nwithout using the bit CRCNEXT. After the CRC reception, the CRC must be read in the \nSPI_DR register to clear the RXNE flag.\nAt the end of data and CRC transfers, the CRCERR flag in SPI_SR is set if corruption \noccurs during the transfer.\n28.3.10 \nError flags\nMaster mode fault (MODF)\nMaster mode fault occurs when the master device has its NSS pin pulled low (in NSS \nhardware mode) or SSI bit low (in NSS software mode), this automatically sets the MODF \nbit. Master mode fault affects the SPI peripheral in the following ways:\n•\nThe MODF bit is set and an SPI interrupt is generated if the ERRIE bit is set.\n•\nThe SPE bit is cleared. This blocks all output from the device and disables the SPI \ninterface.\n•\nThe MSTR bit is cleared, thus forcing the device into slave mode.\nUse the following software sequence to clear the MODF bit:\n1.\nMake a read or write access to the SPI_SR register while the MODF bit is set.\n2. \nThen write to the SPI_CR1 register.\nTo avoid any multiple slave conflicts in a system comprising several MCUs, the NSS pin \nmust be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits can \nbe restored to their original state after this clearing sequence.\nAs a security, hardware does not allow the setting of the SPE and MSTR bits while the \nMODF bit is set.\nIn a slave device the MODF bit cannot be set. However, in a multimaster configuration, the \ndevice can be in slave mode with this MODF bit set. In this case, the MODF bit indicates \nthat there might have been a multimaster conflict for system control. An interrupt routine can \nbe used to recover cleanly from this state by performing a reset or returning to a default \nstate.\nOverrun condition\nAn overrun condition occurs when the master device has sent data bytes and the slave \ndevice has not cleared the RXNE bit resulting from the previous data byte transmitted. \nWhen an overrun condition occurs:\n•\nthe OVR bit is set and an interrupt is generated if the ERRIE bit is set.\nIn this case, the receiver buffer contents are not updated with the newly received data from \nthe master device. A read from the SPI_DR register returns this byte. All other subsequently \ntransmitted bytes are lost.\nClearing the OVR bit is done by a read from the SPI_DR register followed by a read access \nto the SPI_SR register.\n" }, { "page_number": 901, "page_indices": { "start_index": 1756458, "end_index": 1758252 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 901 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.3 SPI functional description", 879 ], [ 3, "28.3.10 Error flags", 900 ], [ 4, "CRC error", 901 ], [ 4, "TI mode frame format error", 901 ], [ 3, "28.3.11 SPI interrupts", 901 ] ], "page_content": "RM0090 Rev 21\n901/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nCRC error\nThis flag is used to verify the validity of the value received when the CRCEN bit in the \nSPI_CR1 register is set. The CRCERR flag in the SPI_SR register is set if the value \nreceived in the shift register does not match the receiver SPI_RXCRCR value.\nTI mode frame format error\nA TI mode frame format error is detected when an NSS pulse occurs during an ongoing \ncommunication when the SPI is acting in slave mode and configured to conform to the TI \nmode protocol. When this error occurs, the FRE flag is set in the SPI_SR register. The SPI \nis not disabled when an error occurs, the NSS pulse is ignored, and the SPI waits for the \nnext NSS pulse before starting a new transfer. The data may be corrupted since the error \ndetection may result in the lost of two data bytes.\nThe FRE flag is cleared when SPI_SR register is read. If the bit ERRIE is set, an interrupt is \ngenerated on the NSS error detection. In this case, the SPI should be disabled because \ndata consistency is no more guaranteed and communications should be reinitiated by the \nmaster when the slave SPI is re-enabled.\nFigure 261. TI mode frame format error detection\n28.3.11 \nSPI interrupts\n \nai18438\nMSBIN\nMOSI\ninput\nNSS\noutput\nSCK\noutput\ntrigger\nsampling trigger\nsampling trigger\nsampling\nDONTCARE\nMISO\noutput\n1 or 0\nMSBOUT\nLSBOUT\nMSBIN\nLSBIN\nMSBOUT\nLSBOUT\ntrigger\nsampling trigger samplingtrigger\nsampling trigger\nsampling\nLSBIN\nDONTCARE\nTIFRFE\nTable 127. SPI interrupt requests\nInterrupt event\nEvent flag\nEnable Control bit\nTransmit buffer empty flag\nTXE\nTXEIE\nReceive buffer not empty flag\nRXNE\nRXNEIE\nMaster mode fault event\nMODF\nERRIE\nOverrun error\nOVR\nCRC error flag\nCRCERR\nTI frame format error\nFRE\nERRIE\n" }, { "page_number": 902, "page_indices": { "start_index": 1758252, "end_index": 1759284 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 902 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.1 I2S general description", 902 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n902/1757\nRM0090 Rev 21\n28.4 \nI2S functional description\n28.4.1 \nI2S general description\nThe block diagram of the I2S is shown in Figure 262.\nFigure 262. I2S block diagram \n1.\nI2S2ext_SD and I2S3ext_SD are the extended SD pins that control the I2S full duplex mode.\nThe SPI could function as an audio I2S interface when the I2S capability is enabled (by \nsetting the I2SMOD bit in the SPI_I2SCFGR register). This interface uses almost the same \npins, flags and interrupts as the SPI.\nTx buffer \nShift register\n16-bit\nCommunication\nRx buffer\n16-bit\nMOSI/ SD\nMaster control logic \nMISO/\nI2S2ext_SD/\nI2S3ext_SD(1)\nSPI \nbaud rate generator\nCK\nI2SMOD\nLSB first\nLSB\nFirst\nSPE BR2\nBR1\nBR0\nMSTR CPOL CPHA\nBidi\nmode\nBidi\nOE\nCRC\nEN\nCRC\nNext DFF\nRx\nonly SSM\nSSI\nAddress and data bus\ncontrol\nNSS/WS\nBSY OVR MODF CRC\nERR\nCH\nSIDE TxE RxNE\nI2S clock generator\nMCK\nI2S_CK\nI2S\nMODI2SE\nCH\nDATLEN\nLEN\nCK \nPOL\nI2SCFG\nI2SSTD\nMCKOEODD\nI2SDIV[7:0]\n[1:0]\n[1:0]\n[1:0]\nUDR\nI2SxCLK \nMS19909V1\nFRE\n" }, { "page_number": 903, "page_indices": { "start_index": 1759284, "end_index": 1761537 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 903 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.2 I2S full duplex", 903 ] ], "page_content": "RM0090 Rev 21\n903/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nThe I2S shares three common pins with the SPI:\n•\nSD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time-\nmultiplexed data channels (in half-duplex mode only).\n•\nWS: Word Select (mapped on the NSS pin) is the data control signal output in master \nmode and input in slave mode.\n•\nCK: Serial Clock (mapped on the SCK pin) is the serial clock output in master mode \nand serial clock input in slave mode.\n•\nI2S2ext_SD and I2S3ext_SD: additional pins (mapped on the MISO pin) to control the \nI2S full duplex mode.\nAn additional pin could be used when a master clock output is needed for some external \naudio devices:\n•\nMCK: Master Clock (mapped separately) is used, when the I2S is configured in master \nmode (and when the MCKOE bit in the SPI_I2SPR register is set), to output this \nadditional clock generated at a preconfigured frequency rate equal to 256 × FS, where \nFS is the audio sampling frequency.\nThe I2S uses its own clock generator to produce the communication clock when it is set in \nmaster mode. This clock generator is also the source of the master clock output. Two \nadditional registers are available in I2S mode. One is linked to the clock generator \nconfiguration SPI_I2SPR and the other one is a generic I2S configuration register \nSPI_I2SCFGR (audio standard, slave/master mode, data format, packet frame, clock \npolarity, etc.).\nThe SPI_CR1 register and all CRC registers are not used in the I2S mode. Likewise, the \nSSOE bit in the SPI_CR2 register and the MODF and CRCERR bits in the SPI_SR are not \nused.\nThe I2S uses the same SPI register for data transfer (SPI_DR) in 16-bit wide mode.\n28.4.2 \nI2S full duplex\nTo support I2S full duplex mode, two extra I2S instances called extended I2Ss (I2S2_ext, \nI2S3_ext) are available in addition to I2S2 and I2S3 (see Figure 263). The first I2S full-\nduplex interface is consequently based on I2S2 and I2S2_ext, and the second one on I2S3 \nand I2S3_ext.\nNote:\nI2S2_ext an I2S3_ext are used only in full-duplex mode.\nFigure 263. I2S full duplex block diagram \n1.\nWhere x can be 2 or 3.\nMS19910V1\nSPI/I2Sx \nI2Sx_ext \nSPIx_MOSI/I2Sx_SD(in/out)\nI2S_ WS \nI2Sx_SCK \nI2Sx_extSD(in/out)\n" }, { "page_number": 904, "page_indices": { "start_index": 1761537, "end_index": 1763759 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 904 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.3 Supported audio protocols", 904 ], [ 4, "I2S Philips standard", 904 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n904/1757\nRM0090 Rev 21\nI2Sx can operate in master mode. As a result:\n•\n Only I2Sx can output SCK and WS in half duplex mode\n•\n Only I2Sx can deliver SCK and WS to I2S2_ext and I2S3_ext in full duplex mode.\nThe extended I2Ss (I2Sx_ext) can be used only in full duplex mode. The I2Sx_ext operate \nalways in slave mode.\nBoth I2Sx and I2Sx_ext can be configured as transmitters or receivers.\n28.4.3 \nSupported audio protocols\nThe four-line bus has to handle only audio data generally time-multiplexed on two channels: \nthe right channel and the left channel. However there is only one 16-bit register for the \ntransmission and the reception. So, it is up to the software to write into the data register the \nadequate value corresponding to the considered channel side, or to read the data from the \ndata register and to identify the corresponding channel by checking the CHSIDE bit in the \nSPI_SR register. Channel Left is always sent first followed by the channel right (CHSIDE \nhas no meaning for the PCM protocol).\nFour data and packet frames are available. Data may be sent with a format of:\n•\n16-bit data packed in 16-bit frame\n•\n16-bit data packed in 32-bit frame\n•\n24-bit data packed in 32-bit frame\n•\n32-bit data packed in 32-bit frame\nWhen using 16-bit data extended on 32-bit packet, the first 16 bits (MSB) are the significant \nbits, the 16-bit LSB is forced to 0 without any need for software action or DMA request (only \none read/write operation).\nThe 24-bit and 32-bit data frames need two CPU read or write operations to/from the \nSPI_DR or two DMA operations if the DMA is preferred for the application. For 24-bit data \nframe specifically, the 8 nonsignificant bits are extended to 32 bits with 0-bits (by hardware).\nFor all data formats and communication standards, the most significant bit is always sent \nfirst (MSB first). \nThe I2S interface supports four audio standards, configurable using the I2SSTD[1:0] and \nPCMSYNC bits in the SPI_I2SCFGR register.\nI2S Philips standard\nFor this standard, the WS signal is used to indicate which channel is being transmitted. It is \nactivated one CK clock cycle before the first bit (MSB) is available.\n" }, { "page_number": 905, "page_indices": { "start_index": 1763759, "end_index": 1764788 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 905 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.3 Supported audio protocols", 904 ], [ 4, "I2S Philips standard", 904 ] ], "page_content": "RM0090 Rev 21\n905/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nFigure 264. I2S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0)\nData are latched on the falling edge of CK (for the transmitter) and are read on the rising \nedge (for the receiver). The WS signal is also latched on the falling edge of CK.\nFigure 265. I2S Philips standard waveforms (24-bit frame with CPOL = 0)\nThis mode needs two write or read operations to/from the SPI_DR.\n•\nIn transmission mode:\nif 0x8EAA33 has to be sent (24-bit):\nFigure 266. Transmitting 0x8EAA33\n•\nIn reception mode:\nif data 0x8EAA33 is received:\nMS19591V1\nCK\nWS\nSD\nCan be 16-bit or 32-bit\nMSB\nMSB\nLSB\nChannel left\nChannel \nright\ntransmission\nreception\nMS19592V1\nCK\nWS\nSD\nTransmission\nReception\n24-bit data\nMSB\nLSB\nChannel left 32-bit\nChannel right\n8-bit remaining 0 forced\nMS19593V1\n0x8EAA\n0x33XX\nFirst write to Data register\nSecond write to Data register\nOnly the 8 MSB are sent \nto compare the 24 bits\n8 LSBs have no meaning \nand can be anything\n" }, { "page_number": 906, "page_indices": { "start_index": 1764788, "end_index": 1766407 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 906 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.3 Supported audio protocols", 904 ], [ 4, "MSB justified standard", 906 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n906/1757\nRM0090 Rev 21\nFigure 267. Receiving 0x8EAA33\nFigure 268. I2S Philips standard (16-bit extended to 32-bit packet frame with \nCPOL = 0)\nWhen 16-bit data frame extended to 32-bit channel frame is selected during the I2S \nconfiguration phase, only one access to SPI_DR is required. The 16 remaining bits are \nforced by hardware to 0x0000 to extend the data to 32-bit format.\nIf the data to transmit or the received data are 0x76A3 (0x76A30000 extended to 32-bit), the \noperation shown in Figure 269 is required.\nFigure 269. Example\nFor transmission, each time an MSB is written to SPI_DR, the TXE flag is set and its \ninterrupt, if allowed, is generated to load SPI_DR with the new value to send. This takes \nplace even if 0x0000 have not yet been sent because it is done by hardware.\nFor reception, the RXNE flag is set and its interrupt, if allowed, is generated when the first \n16 MSB half-word is received.\nIn this way, more time is provided between two write or read operations, which prevents \nunderrun or overrun conditions (depending on the direction of the data transfer).\nMSB justified standard\nFor this standard, the WS signal is generated at the same time as the first data bit, which is \nthe MSBit.\nMS19594V1\n0x8EAA\n0x33XX\nFirst read to Data register\nSecond read to Data register\nOnly the 8 MSB are sent \nto compare the 24 bits\n8 LSBs have no meaning \nand can be anything\nMS19599V1\nCK\nWS\nSD\nTransmission\nReception\n16-bit data\nMSB\nLSB\nChannel left 32-bit\nChannel right\n16-bit remaining 0 forced\nMS19595V1\n0x76A3\nOnly one access to SPIx_DR\n" }, { "page_number": 907, "page_indices": { "start_index": 1766407, "end_index": 1767322 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 907 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.3 Supported audio protocols", 904 ], [ 4, "LSB justified standard", 907 ] ], "page_content": "RM0090 Rev 21\n907/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nFigure 270. MSB justified 16-bit or 32-bit full-accuracy length with CPOL = 0\nData are latched on the falling edge of CK (for transmitter) and are read on the rising edge \n(for the receiver).\nFigure 271. MSB justified 24-bit frame length with CPOL = 0\nFigure 272. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0\nLSB justified standard\nThis standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit \nfull-accuracy frame formats).\nMS30100 V1\nCK\nWS\nSD\nTransmission\nReception\n16- or 32 bit data\nMSB\nLSB\nChannel left\nChannel right\nMSB\nMS30101V1\nCK\nWS\nSD\nTransmission\nReception\n24 bit data\nMSB\nLSB\nChannel left 32-bit\nChannel right\n8-bit remaining\n0 forced\nMS30102V1\nCK\nWS\nSD\nTransmission\nReception\n16-bit data\nMSB\nLSB\nChannel left 32-bit\nChannel right\n16-bit remaining\n0 forced\n" }, { "page_number": 908, "page_indices": { "start_index": 1767322, "end_index": 1768350 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 908 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.3 Supported audio protocols", 904 ], [ 4, "LSB justified standard", 907 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n908/1757\nRM0090 Rev 21\nFigure 273. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0\nFigure 274. LSB justified 24-bit frame length with CPOL = 0\n•\nIn transmission mode:\nIf data 0x3478AE have to be transmitted, two write operations to the SPI_DR register \nare required from software or by DMA. The operations are shown below.\nFigure 275. Operations required to transmit 0x3478AE\n•\nIn reception mode:\nIf data 0x3478AE are received, two successive read operations from SPI_DR are \nrequired on each RXNE event.\nMS30103V1\nCK\nWS\nSD\nTransmission\nReception\n16- or 32-bit data\nMSB\nLSB\nChannel left\nChannel right\nMSB\nMS30104V1\nCK\nWS\nSD\nTransmission\nReception\n8-bit data\n0 forced\nMSB\nLSB\nChannel left 32-bit\nChannel right\n24-bit remaining\n0xXX34\n0x78AE\nFirst write to Data register \nconditioned by TXE=1\nSecond write to Data register \nconditioned by TXE=1\nOnly the 8 LSB of the \nhalf-word are significant. \nA field of 0x00 is forced \ninstead of the 8 MSBs.\nMS19596V1\n" }, { "page_number": 909, "page_indices": { "start_index": 1768350, "end_index": 1769975 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 909 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.3 Supported audio protocols", 904 ], [ 4, "LSB justified standard", 907 ] ], "page_content": "RM0090 Rev 21\n909/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nFigure 276. Operations required to receive 0x3478AE\nFigure 277. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0\nWhen 16-bit data frame extended to 32-bit channel frame is selected during the I2S \nconfiguration phase, Only one access to SPI_DR is required. The 16 remaining bits are \nforced by hardware to 0x0000 to extend the data to 32-bit format. In this case it corresponds \nto the half-word MSB.\nIf the data to transmit or the received data are 0x76A3 (0x0000 76A3 extended to 32-bit), \nthe operation shown in Figure 278 is required.\nFigure 278. Example of LSB justified 16-bit extended to 32-bit packet frame\nIn transmission mode, when TXE is asserted, the application has to write the data to be \ntransmitted (in this case 0x76A3). The 0x000 field is transmitted first (extension on 32-bit). \nTXE is asserted again as soon as the effective data (0x76A3) is sent on SD.\nIn reception mode, RXNE is asserted as soon as the significant half-word is received (and \nnot the 0x0000 field).\nIn this way, more time is provided between two write or read operations to prevent underrun \nor overrun conditions.\n0xXX34\n0x78AE\nFirst read from Data register \nconditioned by RXNE=1\nSecond read from Data register \nconditioned by RXNE=1\nOnly the 8 LSB of the \nhalf-word are significant. \nA field of 0x00 is forced \ninstead of the 8 MSBs.\nMS19597V1\nMS30105V1\nCK\nWS\nSD\nTransmission\nReception\n16-bit data\n0 forced\nMSB\nLSB\nChannel left 32-bit\nChannel right\n16-bit remaining\n0x76A3\nOnly one access to the SPIx-DR register\nMS19598V1\n" }, { "page_number": 910, "page_indices": { "start_index": 1769975, "end_index": 1771372 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 910 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.3 Supported audio protocols", 904 ], [ 4, "PCM standard", 910 ], [ 3, "28.4.4 Clock generator", 910 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n910/1757\nRM0090 Rev 21\nPCM standard\nFor the PCM standard, there is no need to use channel-side information. The two PCM \nmodes (short and long frame) are available and configurable using the PCMSYNC bit in \nSPI_I2SCFGR.\nFigure 279. PCM standard waveforms (16-bit)\nFor long frame synchronization, the WS signal assertion time is fixed 13 bits in master \nmode.\nFor short frame synchronization, the WS synchronization signal is only one cycle long.\nFigure 280. PCM standard waveforms (16-bit extended to 32-bit packet frame)\nNote:\nFor both modes (master and slave) and for both synchronizations (short and long), the \nnumber of bits between two consecutive pieces of data (and so two synchronization signals) \nneeds to be specified (DATLEN and CHLEN bits in the SPI_I2SCFGR register) even in \nslave mode.\n28.4.4 \nClock generator\nThe I2S bitrate determines the dataflow on the I2S data line and the I2S clock signal \nfrequency.\nI2S bitrate = number of bits per channel × number of channels × sampling audio frequency\nFor a 16-bit audio, left and right channel, the I2S bitrate is calculated as follows:\nI2S bitrate = 16 × 2 × FS\nIt is I2S bitrate = 32 x 2 x FS if the packet length is 32-bit wide.\nMS30106V1\nCK\nWS\nshort frame\nSD\nWS\nlong frame\n13-bits\nMSB\nLSB MSB\nMS30107V1\nCK\nWS\nshort frame\nSD\nWS\nlong frame\nUp to 13-bits\nMSB\nLSB\n16 bits\n" }, { "page_number": 911, "page_indices": { "start_index": 1771372, "end_index": 1773057 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 911 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.4 Clock generator", 910 ] ], "page_content": "RM0090 Rev 21\n911/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nFigure 281. Audio sampling frequency definition\nWhen the master mode is configured, a specific action needs to be taken to properly \nprogram the linear divider in order to communicate with the desired audio frequency.\nFigure 282. I2S clock generator architecture\n1.\nWhere x could be 2 or 3.\nFigure 281 presents the communication clock architecture. To achieve high-quality audio \nperformance, the I2SxCLK clock source can be either the PLLI2S output (through R division \nfactor) or an external clock (mapped to I2S_CKIN pin).\nThe audio sampling frequency can be 192 kHz, 96 kHz, or 48 kHz. In order to reach the \ndesired frequency, the linear divider needs to be programmed according to the formulas \nbelow:\nWhen the master clock is generated (MCKOE in the SPI_I2SPR register is set):\nFS = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide\nFS = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide\nWhen the master clock is disabled (MCKOE bit cleared):\nFS = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide\nFS = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide\nTable 128 provides example precision values for different clock configurations.\nNote:\nOther configurations are possible that allow optimum clock precision.\nMS30108V1\n16-or 32-bit left \nchannel\n16-or 32-bit \nright channel\n32- or 64-bits\nsampling point\nsampling point\nFS\nFS : audio sampling frequency\nMS30109V1\nMCKOE ODD\n8-bit linear divider \n+ reshaping stage\nDivider by 4\nDiv2\nI²SDIV[7:0]\nI²SMOD\nCHLEN\n0\n1\n0\n1\nMCKOE\nCK\nMCK\nI²SxCLK\n" }, { "page_number": 912, "page_indices": { "start_index": 1773057, "end_index": 1774833 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 912 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.5 I2S master mode", 912 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n912/1757\nRM0090 Rev 21\n \n \n28.4.5 \nI2S master mode\nThe I2S can be configured as follows: \n•\nIn master mode for transmission or reception (half-duplex mode using I2Sx)\n•\nIn master mode transmission and reception (full duplex mode using I2Sx and \nI2Sx_ext).\nThis means that the serial clock is generated on the CK pin as well as the Word Select \nsignal WS. Master clock (MCK) may be output or not, thanks to the MCKOE bit in the \nSPI_I2SPR register.\nTable 128. Audio frequency precision (for PLLM VCO = 1 MHz or 2 MHz)(1)\nMaster \nclock\nTarget fS \n(Hz)\nData \nformat\nPLLI2SN\nPLLI2SR\nI2SDIV\nI2SODD\nReal fS (Hz)\nError\nDisabled\n8000\n16-bit\n192\n2\n187\n1\n8000\n0.0000%\n32-bit\n192\n3\n62\n1\n8000\n0.0000%\n16000\n16-bit\n192\n3\n62\n1\n16000\n0.0000%\n32-bit\n256\n2\n62\n1\n16000\n0.0000%\n32000\n16-bit\n256\n2\n62\n1\n32000\n0.0000%\n32-bit\n256\n5\n12\n1\n32000\n0.0000%\n48000\n16-bit\n192\n5\n12\n1\n48000\n0.0000%\n32-bit\n384\n5\n12\n1\n48000\n0.0000%\n96000\n16-bit\n384\n5\n12\n1\n96000\n0.0000%\n32-bit\n424\n3\n11\n1\n96014.49219\n0.0151%\n22050\n16-bit\n290\n3\n68\n1\n22049.87695\n0.0006%\n32-bit\n302\n2\n53\n1\n22050.23438\n0.0011%\n44100\n16-bit\n302\n2\n53\n1\n44100.46875\n0.0011%\n32-bit\n429\n4\n19\n0\n44099.50781\n0.0011%\n192000\n16-bit\n424\n3\n11\n1\n192028.9844\n0.0151%\n32-bit\n258\n3\n3\n1\n191964.2813\n0.0186%\nEnabled\n8000\ndon't care\n256\n5\n12\n1\n8000\n0.0000%\n16000\ndon't care\n213\n2\n13\n0\n16000.60059\n0.0038%\n32000\ndon't care\n213\n2\n6\n1\n32001.20117\n0.0038%\n48000\ndon't care\n258\n3\n3\n1\n47991.07031\n0.0186%\n96000\ndon't care\n344\n2\n3\n1\n95982.14063\n0.0186%\n22050\ndon't care\n429\n4\n9\n1\n22049.75391\n0.0011%\n44100\ndon't care\n271\n2\n6\n0\n44108.07422\n0.0183%\n1.\nThis table gives only example values for different clock configurations. Other configurations allowing optimum clock \nprecision are possible.\n" }, { "page_number": 913, "page_indices": { "start_index": 1774833, "end_index": 1778054 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 913 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.5 I2S master mode", 912 ], [ 4, "Procedure", 913 ], [ 4, "Transmission sequence", 913 ], [ 4, "Reception sequence", 913 ] ], "page_content": "RM0090 Rev 21\n913/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nProcedure\n1.\nSelect the I2SDIV[7:0] bits in the SPI_I2SPR register to define the serial clock baud \nrate to reach the proper audio sample frequency. The ODD bit in the SPI_I2SPR \nregister also has to be defined.\n2. \nSelect the CKPOL bit to define the steady level for the communication clock. Set the \nMCKOE bit in the SPI_I2SPR register if the master clock MCK needs to be provided to \nthe external DAC/ADC audio component (the I2SDIV and ODD values should be \ncomputed depending on the state of the MCK output, for more details refer to \nSection 28.4.4: Clock generator).\n3. \nSet the I2SMOD bit in SPI_I2SCFGR to activate the I2S functionalities and choose the \nI2S standard through the I2SSTD[1:0] and PCMSYNC bits, the data length through the \nDATLEN[1:0] bits and the number of bits per channel by configuring the CHLEN bit. \nSelect also the I2S master mode and direction (Transmitter or Receiver) through the \nI2SCFG[1:0] bits in the SPI_I2SCFGR register.\n4. \nIf needed, select all the potential interruption sources and the DMA capabilities by \nwriting the SPI_CR2 register.\n5. \nThe I2SE bit in SPI_I2SCFGR register must be set.\nWS and CK are configured in output mode. MCK is also an output, if the MCKOE bit in \nSPI_I2SPR is set.\nTransmission sequence\nThe transmission sequence begins when a half-word is written into the Tx buffer.\nAssumedly, the first data written into the Tx buffer correspond to the channel Left data. \nWhen data are transferred from the Tx buffer to the shift register, TXE is set and data \ncorresponding to the channel Right have to be written into the Tx buffer. The CHSIDE flag \nindicates which channel is to be transmitted. It has a meaning when the TXE flag is set \nbecause the CHSIDE flag is updated when TXE goes high.\nA full frame has to be considered as a Left channel data transmission followed by a Right \nchannel data transmission. It is not possible to have a partial frame where only the left \nchannel is sent.\nThe data half-word is parallel loaded into the 16-bit shift register during the first bit \ntransmission, and then shifted out, serially, to the MOSI/SD pin, MSB first. The TXE flag is \nset after each transfer from the Tx buffer to the shift register and an interrupt is generated if \nthe TXEIE bit in the SPI_CR2 register is set.\nFor more details about the write operations depending on the I2S standard mode selected, \nrefer to Section 28.4.3: Supported audio protocols).\nTo ensure a continuous audio data transmission, it is mandatory to write the SPI_DR with \nthe next data to transmit before the end of the current transmission.\nTo switch off the I2S, by clearing I2SE, it is mandatory to wait for TXE = 1 and BSY = 0.\nReception sequence\nThe operating mode is the same as for the transmission mode except for the point 3 (refer to \nthe procedure described in Section 28.4.5: I2S master mode), where the configuration \nshould set the master reception mode through the I2SCFG[1:0] bits.\nWhatever the data or channel length, the audio data are received by 16-bit packets. This \nmeans that each time the Rx buffer is full, the RXNE flag is set and an interrupt is generated \n" }, { "page_number": 914, "page_indices": { "start_index": 1778054, "end_index": 1780694 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 914 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.6 I2S slave mode", 914 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n914/1757\nRM0090 Rev 21\nif the RXNEIE bit is set in SPI_CR2 register. Depending on the data and channel length \nconfiguration, the audio value received for a right or left channel may result from one or two \nreceptions into the Rx buffer.\nClearing the RXNE bit is performed by reading the SPI_DR register.\nCHSIDE is updated after each reception. It is sensitive to the WS signal generated by the \nI2S cell.\nFor more details about the read operations depending on the I2S standard mode selected, \nrefer to Section 28.4.3: Supported audio protocols.\nIf data are received while the previously received data have not been read yet, an overrun is \ngenerated and the OVR flag is set. If the ERRIE bit is set in the SPI_CR2 register, an \ninterrupt is generated to indicate the error.\nTo switch off the I2S, specific actions are required to ensure that the I2S completes the \ntransfer cycle properly without initiating a new data transfer. The sequence depends on the \nconfiguration of the data and channel lengths, and on the audio protocol mode selected. In \nthe case of:\n•\n16-bit data length extended on 32-bit channel length (DATLEN = 00 and CHLEN = 1) \nusing the LSB justified mode (I2SSTD = 10)\na) \nWait for the second to last RXNE = 1 (n – 1)\nb) \nThen wait 17 I2S clock cycles (using a software loop)\nc) \nDisable the I2S (I2SE = 0)\n•\n16-bit data length extended on 32-bit channel length (DATLEN = 00 and CHLEN = 1) in \nMSB justified, I2S or PCM modes (I2SSTD = 00, I2SSTD = 01 or I2SSTD = 11, \nrespectively)\na) \nWait for the last RXNE\nb) \nThen wait 1 I2S clock cycle (using a software loop)\nc) \nDisable the I2S (I2SE = 0)\n•\nFor all other combinations of DATLEN and CHLEN, whatever the audio mode selected \nthrough the I2SSTD bits, carry out the following sequence to switch off the I2S:\na) \nWait for the second to last RXNE = 1 (n – 1)\nb) \nThen wait one I2S clock cycle (using a software loop)\nc) \nDisable the I2S (I2SE = 0)\nNote:\nThe BSY flag is kept low during transfers.\n28.4.6 \nI2S slave mode\nThe I2S can be configured as follows: \n•\nIn slave mode for transmission or reception (half-duplex mode using I2Sx)\n•\nIn slave mode transmission and reception (full duplex mode using I2Sx and I2Sx_ext).\nThe operating mode is following mainly the same rules as described for the I2S master \nconfiguration. In slave mode, there is no clock to be generated by the I2S interface. The \nclock and WS signals are input from the external master connected to the I2S interface. \nThere is then no need, for the user, to configure the clock.\nThe configuration steps to follow are listed below:\n" }, { "page_number": 915, "page_indices": { "start_index": 1780694, "end_index": 1784157 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 915 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.6 I2S slave mode", 914 ], [ 4, "Transmission sequence", 915 ], [ 4, "Reception sequence", 915 ] ], "page_content": "RM0090 Rev 21\n915/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n1.\nSet the I2SMOD bit in the SPI_I2SCFGR register to reach the I2S functionalities and \nchoose the I2S standard through the I2SSTD[1:0] bits, the data length through the \nDATLEN[1:0] bits and the number of bits per channel for the frame configuring the \nCHLEN bit. Select also the mode (transmission or reception) for the slave through the \nI2SCFG[1:0] bits in SPI_I2SCFGR register.\n2. \nIf needed, select all the potential interrupt sources and the DMA capabilities by writing \nthe SPI_CR2 register.\n3. \nThe I2SE bit in SPI_I2SCFGR register must be set.\nTransmission sequence\nThe transmission sequence begins when the external master device sends the clock and \nwhen the NSS_WS signal requests the transfer of data. The slave has to be enabled before \nthe external master starts the communication. The I2S data register has to be loaded before \nthe master initiates the communication.\nFor the I2S, MSB justified and LSB justified modes, the first data item to be written into the \ndata register corresponds to the data for the left channel. When the communication starts, \nthe data are transferred from the Tx buffer to the shift register. The TXE flag is then set in \norder to request the right channel data to be written into the I2S data register.\nThe CHSIDE flag indicates which channel is to be transmitted. Compared to the master \ntransmission mode, in slave mode, CHSIDE is sensitive to the WS signal coming from the \nexternal master. This means that the slave needs to be ready to transmit the first data \nbefore the clock is generated by the master. WS assertion corresponds to left channel \ntransmitted first.\nNote:\nThe I2SE has to be written at least two PCLK cycles before the first clock of the master \ncomes on the CK line.\nThe data half-word is parallel-loaded into the 16-bit shift register (from the internal bus) \nduring the first bit transmission, and then shifted out serially to the MOSI/SD pin MSB first. \nThe TXE flag is set after each transfer from the Tx buffer to the shift register and an interrupt \nis generated if the TXEIE bit in the SPI_CR2 register is set.\nNote that the TXE flag should be checked to be at 1 before attempting to write the Tx buffer.\nFor more details about the write operations depending on the I2S standard mode selected, \nrefer to Section 28.4.3: Supported audio protocols.\nTo secure a continuous audio data transmission, it is mandatory to write the SPI_DR \nregister with the next data to transmit before the end of the current transmission. An \nunderrun flag is set and an interrupt may be generated if the data are not written into the \nSPI_DR register before the first clock edge of the next data communication. This indicates \nto the software that the transferred data are wrong. If the ERRIE bit is set into the SPI_CR2 \nregister, an interrupt is generated when the UDR flag in the SPI_SR register goes high. In \nthis case, it is mandatory to switch off the I2S and to restart a data transfer starting from the \nleft channel.\nTo switch off the I2S, by clearing the I2SE bit, it is mandatory to wait for TXE = 1 and \nBSY = 0.\nReception sequence\nThe operating mode is the same as for the transmission mode except for the point 1 (refer to \nthe procedure described in Section 28.4.6: I2S slave mode), where the configuration should \nset the master reception mode using the I2SCFG[1:0] bits in the SPI_I2SCFGR register.\n" }, { "page_number": 916, "page_indices": { "start_index": 1784157, "end_index": 1786789 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 916 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.7 Status flags", 916 ], [ 4, "Busy flag (BSY)", 916 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n916/1757\nRM0090 Rev 21\nWhatever the data length or the channel length, the audio data are received by 16-bit \npackets. This means that each time the RX buffer is full, the RXNE flag in the SPI_SR \nregister is set and an interrupt is generated if the RXNEIE bit is set in the SPI_CR2 register. \nDepending on the data length and channel length configuration, the audio value received for \na right or left channel may result from one or two receptions into the RX buffer.\nThe CHSIDE flag is updated each time data are received to be read from SPI_DR. It is \nsensitive to the external WS line managed by the external master component.\nClearing the RXNE bit is performed by reading the SPI_DR register.\nFor more details about the read operations depending the I2S standard mode selected, refer \nto Section 28.4.3: Supported audio protocols.\nIf data are received while the precedent received data have not yet been read, an overrun is \ngenerated and the OVR flag is set. If the bit ERRIE is set in the SPI_CR2 register, an \ninterrupt is generated to indicate the error.\nTo switch off the I2S in reception mode, I2SE has to be cleared immediately after receiving \nthe last RXNE = 1.\nNote:\nThe external master components should have the capability of sending/receiving data in 16-\nbit or 32-bit packets via an audio channel.\n28.4.7 \nStatus flags\nThree status flags are provided for the application to fully monitor the state of the I2S bus.\nBusy flag (BSY)\nThe BSY flag is set and cleared by hardware (writing to this flag has no effect). It indicates \nthe state of the communication layer of the I2S.\nWhen BSY is set, it indicates that the I2S is busy communicating. There is one exception in \nmaster receive mode (I2SCFG = 11) where the BSY flag is kept low during reception.\nThe BSY flag is useful to detect the end of a transfer if the software needs to disable the I2S. \nThis avoids corrupting the last transfer. For this, the procedure described below must be \nstrictly respected.\nThe BSY flag is set when a transfer starts, except when the I2S is in master receiver mode.\nThe BSY flag is cleared:\n•\nwhen a transfer completes (except in master transmit mode, in which the \ncommunication is supposed to be continuous)\n•\nwhen the I2S is disabled\nWhen communication is continuous:\n•\nIn master transmit mode, the BSY flag is kept high during all the transfers\n•\nIn slave mode, the BSY flag goes low for one I2S clock cycle between each transfer\nNote:\nDo not use the BSY flag to handle each data transmission or reception. It is better to use the \nTXE and RXNE flags instead.\n" }, { "page_number": 917, "page_indices": { "start_index": 1786789, "end_index": 1789562 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 917 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.7 Status flags", 916 ], [ 4, "Tx buffer empty flag (TXE)", 917 ], [ 4, "RX buffer not empty (RXNE)", 917 ], [ 4, "Channel Side flag (CHSIDE)", 917 ], [ 3, "28.4.8 Error flags", 917 ], [ 4, "Underrun flag (UDR)", 917 ], [ 4, "Overrun flag (OVR)", 917 ], [ 4, "Frame error flag (FRE)", 917 ] ], "page_content": "RM0090 Rev 21\n917/1757\nRM0090\nSerial peripheral interface (SPI)\n928\nTx buffer empty flag (TXE)\nWhen set, this flag indicates that the Tx buffer is empty and the next data to be transmitted \ncan then be loaded into it. The TXE flag is reset when the Tx buffer already contains data to \nbe transmitted. It is also reset when the I2S is disabled (I2SE bit is reset).\nRX buffer not empty (RXNE)\nWhen set, this flag indicates that there are valid received data in the RX Buffer. It is reset \nwhen SPI_DR register is read.\nChannel Side flag (CHSIDE)\nIn transmission mode, this flag is refreshed when TXE goes high. It indicates the channel \nside to which the data to transfer on SD has to belong. In case of an underrun error event in \nslave transmission mode, this flag is not reliable and I2S needs to be switched off and \nswitched on before resuming the communication.\nIn reception mode, this flag is refreshed when data are received into SPI_DR. It indicates \nfrom which channel side data have been received. Note that in case of error (like OVR) this \nflag becomes meaningless and the I2S should be reset by disabling and then enabling it \n(with configuration if it needs changing).\nThis flag has no meaning in the PCM standard (for both Short and Long frame modes).\nWhen the OVR or UDR flag in the SPI_SR is set and the ERRIE bit in SPI_CR2 is also set, \nan interrupt is generated. This interrupt can be cleared by reading the SPI_SR status \nregister (once the interrupt source has been cleared).\n28.4.8 \nError flags\nThere are three error flags for the I2S cell.\nUnderrun flag (UDR)\nIn slave transmission mode this flag is set when the first clock for data transmission appears \nwhile the software has not yet loaded any value into SPI_DR. It is available when the \nI2SMOD bit in SPI_I2SCFGR is set. An interrupt may be generated if the ERRIE bit in \nSPI_CR2 is set.\nThe UDR bit is cleared by a read operation on the SPI_SR register.\nOverrun flag (OVR)\nThis flag is set when data are received and the previous data have not yet been read from \nSPI_DR. As a result, the incoming data are lost. An interrupt may be generated if the ERRIE \nbit is set in SPI_CR2.\nIn this case, the receive buffer contents are not updated with the newly received data from \nthe transmitter device. A read operation to the SPI_DR register returns the previous \ncorrectly received data. All other subsequently transmitted half-words are lost.\nClearing the OVR bit is done by a read operation on the SPI_DR register followed by a read \naccess to the SPI_SR register.\nFrame error flag (FRE)\nThis flag can be set by hardware only if the I2S is configured in Slave mode. It is set if the \nexternal master is changing the WS line at a moment when the slave is not expected this \n" }, { "page_number": 918, "page_indices": { "start_index": 1789562, "end_index": 1790819 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 918 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.4 I2S functional description", 902 ], [ 3, "28.4.9 I2S interrupts", 918 ], [ 3, "28.4.10 DMA features", 918 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n918/1757\nRM0090 Rev 21\nchange. If the synchronization is lost, to recover from this state and resynchronize the \nexternal master device with the I2S slave device, follow the steps below:\n1.\nDisable the I2S\n2. \nRe-enable it when the correct level is detected on the WS line (WS line is high in I2S \nmode, or low for MSB- or LSB-justified or PCM modes). \nDesynchronization between the master and slave device may be due to noisy environment \non the SCK communication clock or on the WS frame synchronization line. An error interrupt \ncan be generated if the ERRIE bit is set. The desynchronization flag (FRE) is cleared by \nsoftware when the status register is read.\n28.4.9 \nI2S interrupts\nTable 129 provides the list of I2S interrupts.\n \n28.4.10 \nDMA features\nDMA is working in exactly the same way as for the SPI mode. There is no difference on the \nI2S. Only the CRC feature is not available in I2S mode since there is no data transfer \nprotection system.\nTable 129. I2S interrupt requests\nInterrupt event\nEvent flag\nEnable Control bit\nTransmit buffer empty flag\nTXE\nTXEIE\nReceive buffer not empty flag\nRXNE\nRXNEIE\nOverrun error\nOVR\nERRIE\nUnderrun error\nUDR\nFrame error flag\nFRE\nERRIE\n" }, { "page_number": 919, "page_indices": { "start_index": 1790819, "end_index": 1792817 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 919 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.5 SPI and I2S registers", 919 ], [ 3, "28.5.1 SPI control register 1 (SPI_CR1) (not used in I2S mode)", 919 ] ], "page_content": "RM0090 Rev 21\n919/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.5 \nSPI and I2S registers\nThe peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).\n28.5.1 \nSPI control register 1 (SPI_CR1) (not used in I2S mode)\nAddress offset: 0x00\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nBIDI\nMODE\nBIDI\nOE\nCRC\nEN\nCRC\nNEXT\nDFF\nRX\nONLY\nSSM\nSSI\nLSB\nFIRST\nSPE\nBR [2:0]\nMSTR\nCPOL\nCPHA\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 BIDIMODE: Bidirectional data mode enable\n0: 2-line unidirectional data mode selected\n1: 1-line bidirectional data mode selected\nNote: This bit is not used in I2S mode\nBit 14 BIDIOE: Output enable in bidirectional mode\nThis bit combined with the BIDImode bit selects the direction of transfer in bidirectional mode\n0: Output disabled (receive-only mode) \n1: Output enabled (transmit-only mode)\nNote: This bit is not used in I2S mode.\nIn master mode, the MOSI pin is used while the MISO pin is used in slave mode.\nBit 13 CRCEN: Hardware CRC calculation enable\n0: CRC calculation disabled\n1: CRC calculation enabled\nNote: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation. \nIt is not used in I2S mode.\nBit 12 CRCNEXT: CRC transfer next\n0: Data phase (no CRC phase) \n1: Next transfer is CRC (CRC phase)\nNote: When the SPI is configured in full duplex or transmitter only modes, CRCNEXT must be \nwritten as soon as the last data is written to the SPI_DR register. \nWhen the SPI is configured in receiver only mode, CRCNEXT must be set after the \nsecond last data reception. \nThis bit should be kept cleared when the transfers are managed by DMA.\nIt is not used in I2S mode.\nBit 11 DFF: Data frame format\n0: 8-bit data frame format is selected for transmission/reception\n1: 16-bit data frame format is selected for transmission/reception\nNote: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation.\nIt is not used in I2S mode.\n" }, { "page_number": 920, "page_indices": { "start_index": 1792817, "end_index": 1794584 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 920 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.5 SPI and I2S registers", 919 ], [ 3, "28.5.1 SPI control register 1 (SPI_CR1) (not used in I2S mode)", 919 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n920/1757\nRM0090 Rev 21\nBit 10 RXONLY: Receive only\nThis bit combined with the BIDImode bit selects the direction of transfer in 2-line \nunidirectional mode. This bit is also useful in a multislave system in which this particular \nslave is not accessed, the output from the accessed slave is not corrupted.\n0: Full duplex (Transmit and receive)\n1: Output disabled (Receive-only mode)\nNote: This bit is not used in I2S mode\nBit 9 SSM: Software slave management\nWhen the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit.\n0: Software slave management disabled\n1: Software slave management enabled\nNote: This bit is not used in I2S mode and SPI TI mode\nBit 8 SSI: Internal slave select\nThis bit has an effect only when the SSM bit is set. The value of this bit is forced onto the \nNSS pin and the IO value of the NSS pin is ignored.\nNote: This bit is not used in I2S mode and SPI TI mode\nBit 7 LSBFIRST: Frame format\n0: MSB transmitted first\n1: LSB transmitted first\nNote: This bit should not be changed when communication is ongoing.\nIt is not used in I2S mode and SPI TI mode\nBit 6 SPE: SPI enable\n0: Peripheral disabled\n1: Peripheral enabled\nNote: This bit is not used in I2S mode.\nWhen disabling the SPI, follow the procedure described in Section 28.3.8.\nBits 5:3 BR[2:0]: Baud rate control\n000: fPCLK/2\n001: fPCLK/4\n010: fPCLK/8\n011: fPCLK/16\n100: fPCLK/32\n101: fPCLK/64\n110: fPCLK/128\n111: fPCLK/256\nNote: These bits should not be changed when communication is ongoing.\nThey are not used in I2S mode.\nBit 2 MSTR: Master selection \n0: Slave configuration\n1: Master configuration\nNote: This bit should not be changed when communication is ongoing.\nIt is not used in I2S mode.\n" }, { "page_number": 921, "page_indices": { "start_index": 1794584, "end_index": 1796408 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 921 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.5 SPI and I2S registers", 919 ], [ 3, "28.5.2 SPI control register 2 (SPI_CR2)", 921 ] ], "page_content": "RM0090 Rev 21\n921/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.5.2 \nSPI control register 2 (SPI_CR2)\nAddress offset: 0x04\nReset value: 0x0000\n \nBit1 CPOL: Clock polarity \n0: CK to 0 when idle\n1: CK to 1 when idle\nNote: This bit should not be changed when communication is ongoing.\nIt is not used in I2S mode and SPI TI mode.\nBit 0 CPHA: Clock phase \n0: The first clock transition is the first data capture edge\n1: The second clock transition is the first data capture edge\nNote: This bit should not be changed when communication is ongoing.\nIt is not used in I2S mode and SPI TI mode.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTXEIE\nRXNEIE\nERRIE\nFRF\nRes.\nSSOE\nTXDMAEN RXDMAEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 TXEIE: Tx buffer empty interrupt enable\n0: TXE interrupt masked \n1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set.\nBit 6 RXNEIE: RX buffer not empty interrupt enable\n0: RXNE interrupt masked \n1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is \nset.\nBit 5 ERRIE: Error interrupt enable\nThis bit controls the generation of an interrupt when an error condition occurs )(CRCERR, \nOVR, MODF in SPI mode, FRE in TI mode and UDR, OVR, and FRE in I2S mode).\n0: Error interrupt is masked\n1: Error interrupt is enabled\nBit 4 FRF: Frame format\n0: SPI Motorola mode\n1 SPI TI mode \nNote: This bit is not used in I2S mode.\nBit 3 Reserved. Forced to 0 by hardware.\nBit 2 SSOE: SS output enable\n0: SS output is disabled in master mode and the cell can work in multimaster configuration\n1: SS output is enabled in master mode and when the cell is enabled. The cell cannot work \nin a multimaster environment.\nNote: This bit is not used in I2S mode and SPI TI mode.\n" }, { "page_number": 922, "page_indices": { "start_index": 1796408, "end_index": 1798186 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 922 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.5 SPI and I2S registers", 919 ], [ 3, "28.5.3 SPI status register (SPI_SR)", 922 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n922/1757\nRM0090 Rev 21\n28.5.3 \nSPI status register (SPI_SR)\nAddress offset: 0x08\nReset value: 0x0002\n \nBit 1 TXDMAEN: Tx buffer DMA enable\nWhen this bit is set, the DMA request is made whenever the TXE flag is set.\n0: Tx buffer DMA disabled\n1: Tx buffer DMA enabled\nBit 0 RXDMAEN: Rx buffer DMA enable\nWhen this bit is set, the DMA request is made whenever the RXNE flag is set.\n0: Rx buffer DMA disabled\n1: Rx buffer DMA enabled\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFRE\nBSY\nOVR\nMODF\nCRC\nERR\nUDR\nCHSIDE\nTXE\nRXNE\nr\nr\nr\nr\nrc_w0\nr\nr\nr\nr\nBits 15:9 Reserved. Forced to 0 by hardware.\nBit 8 FRE: Frame format error\n0: No frame format error\n1: A frame format error occurred\nThis flag is set by hardware and cleared by software when the SPIx_SR register is read.\nNote: This flag is used when the SPI operates in TI slave mode or I2S slave mode (refer to \nSection 28.3.10).\nBit 7 BSY: Busy flag\n0: SPI (or I2S) not busy\n1: SPI (or I2S) is busy in communication or Tx buffer is not empty\nThis flag is set and cleared by hardware.\nNote: BSY flag must be used with caution: refer to Section 28.3.7 and Section 28.3.8.\nBit 6 OVR: Overrun flag\n0: No overrun occurred\n1: Overrun occurred\nThis flag is set by hardware and reset by a software sequence (see Section 28.3.10).\nBit 5 MODF: Mode fault\n0: No mode fault occurred\n1: Mode fault occurred\nThis flag is set by hardware and reset by a software sequence (see Section 28.3.10).\nNote: This bit is not used in I2S mode\nBit 4 CRCERR: CRC error flag\n0: CRC value received matches the SPI_RXCRCR value\n1: CRC value received does not match the SPI_RXCRCR value\nThis flag is set by hardware and cleared by software writing 0.\nNote: This bit is not used in I2S mode.\n" }, { "page_number": 923, "page_indices": { "start_index": 1798186, "end_index": 1799989 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 923 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.5 SPI and I2S registers", 919 ], [ 3, "28.5.4 SPI data register (SPI_DR)", 923 ] ], "page_content": "RM0090 Rev 21\n923/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.5.4 \nSPI data register (SPI_DR)\nAddress offset: 0x0C\nReset value: 0x0000\n \n \nBit 3 UDR: Underrun flag\n0: No underrun occurred\n1: Underrun occurred\nThis flag is set by hardware and reset by a software sequence. Refer to Section 28.4.8: \nError flags for the software sequence.\nNote: This bit is not used in SPI mode.\nBit 2 CHSIDE: Channel side\n0: Channel Left has to be transmitted or has been received\n1: Channel Right has to be transmitted or has been received\nNote: This bit is not used for SPI mode and is meaningless in PCM mode.\nBit 1 TXE: Transmit buffer empty\n0: Tx buffer not empty\n1: Tx buffer empty\nBit 0 RXNE: Receive buffer not empty\n0: Rx buffer empty\n1: Rx buffer not empty\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDR[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 DR[15:0]: Data register\nData received or to be transmitted.\nThe data register is split into 2 buffers - one for writing (Transmit Buffer) and another one for \nreading (Receive buffer). A write to the data register writes into the Tx buffer and a read \nfrom the data register returns the value held in the Rx buffer.\nNote: These notes apply to SPI mode:\nDepending on the data frame format selection bit (DFF in SPI_CR1 register), the data \nsent or received is either 8-bit or 16-bit. This selection has to be made before enabling \nthe SPI to ensure correct operation. \nFor an 8-bit data frame, the buffers are 8-bit and only the LSB of the register \n(SPI_DR[7:0]) is used for transmission/reception. When in reception mode, the MSB of \nthe register (SPI_DR[15:8]) is forced to 0.\nFor a 16-bit data frame, the buffers are 16-bit and the entire register, SPI_DR[15:0] is \nused for transmission/reception.\n" }, { "page_number": 924, "page_indices": { "start_index": 1799989, "end_index": 1801592 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 924 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.5 SPI and I2S registers", 919 ], [ 3, "28.5.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I2S mode)", 924 ], [ 3, "28.5.6 SPI RX CRC register (SPI_RXCRCR) (not used in I2S mode)", 924 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n924/1757\nRM0090 Rev 21\n28.5.5 \nSPI CRC polynomial register (SPI_CRCPR) (not used in I2S\nmode)\nAddress offset: 0x10\nReset value: 0x0007\n \n28.5.6 \nSPI RX CRC register (SPI_RXCRCR) (not used in I2S mode)\nAddress offset: 0x14\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCRCPOLY[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CRCPOLY[15:0]: CRC polynomial register\nThis register contains the polynomial for the CRC calculation.\nThe CRC polynomial (0007h) is the reset value of this register. Another polynomial can be \nconfigured as required.\nNote: These bits are not used for the I2S mode.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRXCRC[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 15:0 RXCRC[15:0]: Rx CRC register\nWhen CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of \nthe subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1 \nregister is written to 1. The CRC is calculated serially using the polynomial programmed in \nthe SPI_CRCPR register. \nOnly the 8 LSB bits are considered when the data frame format is set to be 8-bit data (DFF \nbit of SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard.\nThe entire 16-bits of this register are considered when a 16-bit data frame format is selected \n(DFF bit of the SPI_CR1 register is set). CRC calculation is done based on any CRC16 \nstandard.\nNote: A read to this register when the BSY Flag is set could return an incorrect value.\nThese bits are not used for I2S mode.\n" }, { "page_number": 925, "page_indices": { "start_index": 1801592, "end_index": 1803474 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 925 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.5 SPI and I2S registers", 919 ], [ 3, "28.5.7 SPI TX CRC register (SPI_TXCRCR) (not used in I2S mode)", 925 ], [ 3, "28.5.8 SPI_I2S configuration register (SPI_I2SCFGR)", 925 ] ], "page_content": "RM0090 Rev 21\n925/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.5.7 \nSPI TX CRC register (SPI_TXCRCR) (not used in I2S mode)\nAddress offset: 0x18\nReset value: 0x0000\n \n28.5.8 \nSPI_I2S configuration register (SPI_I2SCFGR)\nAddress offset: 0x1C\nReset value: 0x0000\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTXCRC[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 15:0 TXCRC[15:0]: Tx CRC register\nWhen CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of \nthe subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 \nis written to 1. The CRC is calculated serially using the polynomial programmed in the \nSPI_CRCPR register.\nOnly the 8 LSB bits are considered when the data frame format is set to be 8-bit data (DFF \nbit of SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard.\nThe entire 16-bits of this register are considered when a 16-bit data frame format is selected \n(DFF bit of the SPI_CR1 register is set). CRC calculation is done based on any CRC16 \nstandard.\nNote: A read to this register when the BSY flag is set could return an incorrect value.\nThese bits are not used for I2S mode.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nI2SMOD\nI2SE\nI2SCFG\nPCMSY\nNC\nRes.\nI2SSTD\nCKPOL\nDATLEN\nCHLEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:12 Reserved, must be kept at reset value.\nBit 11 I2SMOD: I2S mode selection\n0: SPI mode is selected\n1: I2S mode is selected\nNote: This bit should be configured when the SPI or I2S is disabled\nBit 10 I2SE: I2S Enable\n0: I2S peripheral is disabled\n1: I2S peripheral is enabled\nNote: This bit is not used in SPI mode.\nBits 9:8 I2SCFG: I2S configuration mode\n00: Slave - transmit\n01: Slave - receive\n10: Master - transmit\n11: Master - receive\nNote: This bit should be configured when the I2S is disabled.\nIt is not used in SPI mode.\n" }, { "page_number": 926, "page_indices": { "start_index": 1803474, "end_index": 1805011 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 926 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.5 SPI and I2S registers", 919 ], [ 3, "28.5.8 SPI_I2S configuration register (SPI_I2SCFGR)", 925 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n926/1757\nRM0090 Rev 21\nBit 7 PCMSYNC: PCM frame synchronization\n0: Short frame synchronization\n1: Long frame synchronization\nNote: This bit has a meaning only if I2SSTD = 11 (PCM standard is used)\nIt is not used in SPI mode.\nBit 6 Reserved: forced at 0 by hardware\nBits 5:4 I2SSTD: I2S standard selection\n00: I2S Philips standard.\n01: MSB justified standard (left justified)\n10: LSB justified standard (right justified)\n11: PCM standard\nFor more details on I2S standards, refer to Section 28.4.3: Supported audio protocols. Not used \nin SPI mode.\nNote: For correct operation, these bits should be configured when the I2S is disabled.\nBit 3 CKPOL: Steady state clock polarity\n0: I2S clock steady state is low level\n1: I2S clock steady state is high level\nNote: For correct operation, this bit should be configured when the I2S is disabled.\nThis bit is not used in SPI mode\nBits 2:1 DATLEN: Data length to be transferred\n00: 16-bit data length\n01: 24-bit data length\n10: 32-bit data length\n11: Not allowed\nNote: For correct operation, these bits should be configured when the I2S is disabled.\nThis bit is not used in SPI mode.\nBit 0 CHLEN: Channel length (number of bits per audio channel)\n0: 16-bit wide\n1: 32-bit wide\nThe bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to \n32-bit by hardware whatever the value filled in. Not used in SPI mode.\nNote: For correct operation, this bit should be configured when the I2S is disabled.\n" }, { "page_number": 927, "page_indices": { "start_index": 1805011, "end_index": 1806156 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 927 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.5 SPI and I2S registers", 919 ], [ 3, "28.5.9 SPI_I2S prescaler register (SPI_I2SPR)", 927 ] ], "page_content": "RM0090 Rev 21\n927/1757\nRM0090\nSerial peripheral interface (SPI)\n928\n28.5.9 \nSPI_I2S prescaler register (SPI_I2SPR)\nAddress offset: 0x20\nReset value: 0000 0010 (0x0002)\n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMCKOE\nODD\nI2SDIV\nrw\nrw\nrw\nBits 15:10 Reserved, must be kept at reset value.\nBit 9 MCKOE: Master clock output enable\n0: Master clock output is disabled\n1: Master clock output is enabled\nNote: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master \nmode.\nThis bit is not used in SPI mode.\nBit 8 ODD: Odd factor for the prescaler\n0: real divider value is = I2SDIV *2\n1: real divider value is = (I2SDIV * 2)+1\nRefer to Section 28.4.4: Clock generator. Not used in SPI mode.\nNote: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master \nmode.\nBits 7:0 I2SDIV: I2S Linear prescaler\nI2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.\nRefer to Section 28.4.4: Clock generator. Not used in SPI mode.\nNote: These bits should be configured when the I2S is disabled. It is used only when the I2S is in \nmaster mode.\n" }, { "page_number": 928, "page_indices": { "start_index": 1806156, "end_index": 1807421 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 928 }, "toc_details": [ [ 1, "28 Serial peripheral interface (SPI)", 876 ], [ 2, "28.5 SPI and I2S registers", 919 ], [ 3, "28.5.10 SPI register map", 928 ] ], "page_content": "Serial peripheral interface (SPI)\nRM0090\n928/1757\nRM0090 Rev 21\n28.5.10 \nSPI register map\nThe table provides shows the SPI register map and reset values. \n \nRefer to Section 2.3: Memory map for the register boundary addresses.\nTable 130. SPI register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nSPI_CR1\nReserved\nBIDIMODE\nBIDIOE\nCRCEN\nCRCNEXT\nDFF\nRXONLY\nSSM\nSSI\nLSBFIRST\nSPE\nBR [2:0]\nMSTR\nCPOL\nCPHA\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nSPI_CR2\nReserved\nTXEIE\nRXNEIE\nERRIE\nFRF\nReserved\nSSOE\nTXDMAEN\nRXDMAEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0x08\nSPI_SR\nReserved\nFRE\nBSY\nOVR\nMODF\nCRCERR\nUDR\nCHSIDE\nTXE\nRXNE\nReset value\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0x0C\nSPI_DR\nReserved\nDR[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nSPI_CRCPR\nReserved\nCRCPOLY[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n0x14\nSPI_RXCRCR\nReserved\nRxCRC[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x18\nSPI_TXCRCR\nReserved\nTxCRC[15:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nSPI_I2SCFGR\nReserved\nI2SMOD\nI2SE\nI2SCFG\nPCMSYNC\nReserved\nI2SSTD\nCKPOL\nDATLEN\nCHLEN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x20\nSPI_I2SPR\nReserved\nMCKOE\nODD\nI2SDIV\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n" }, { "page_number": 929, "page_indices": { "start_index": 1807421, "end_index": 1808605 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 929 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.1 Introduction", 929 ] ], "page_content": "RM0090 Rev 21\n929/1757\nRM0090\nSerial audio interface (SAI)\n967\n29 \nSerial audio interface (SAI)\nThis section applies to the STM32F42xxx and STM32F43xxx family.\n29.1 \nIntroduction\nThe SAI interface (serial audio interface) offers a wide set of audio protocols due to its \nflexibility and wide range of configurations. Many stereo or mono audio applications may be \ntargeted. I2S standards, LSB or MSB-justified, PCM/DSP, free protocol, and AC’97 \nprotocols may be addressed for example. \nTo bring this level of flexibility and configurability, the SAI contains two audio sub-blocks that \nare fully independent of each other. Each audio sub-block is connected to up to 4 pins (SD, \nSCK, FS, MCLK). Some of these pins can be shared if the two sub-blocks are declared as \nsynchronous to leave some free to be used as general purpose I/Os. The MCLK pin can be \noutput, or not, depending on the application, the decoder requirement and whether the \naudio block is configured as the master.\nThe SAI can work in master or slave configuration. The audio sub-blocks can be either \nreceiver or transmitter and can work synchronously or not (with respect to the other one).\n" }, { "page_number": 930, "page_indices": { "start_index": 1808605, "end_index": 1810309 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 930 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.2 Main features", 930 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n930/1757\nRM0090 Rev 21\n29.2 \nMain features\n•\nTwo independent audio sub-blocks which can be transmitters or receivers with their \nrespective FIFO.\n•\n8-word integrated FIFOs for each audio sub-block.\n•\nSynchronous or asynchronous mode between the audio sub-blocks.\n•\nMaster or slave configuration independent for both audio sub-blocks. \n•\nClock generator for each audio block to target independent audio frequency sampling \nwhen both audio sub-blocks are configured in master mode.\n•\nData size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.\n•\nPeripheral with large configurability and flexibility allowing to target as example the \nfollowing audio protocol: I2S, LSB or MSB-justified, PCM/DSP, free protocol mode, \nAC’97\n•\nUp to 16 slots available with configurable size and with the possibility to select which \nones are active in the audio frame.\n•\nNumber of bits by frame may be configurable.\n•\nFrame synchronization active level configurable (offset, bit length, level).\n•\nFirst active bit position in the slot is configurable.\n•\nLSB first or MSB first for data transfer.\n•\nMute mode.\n•\nStereo/Mono audio frame capability.\n•\nCommunication clock strobing edge configurable (SCK).\n•\nError flags with associated interrupts if enabled respectively.\n–\nOverrun and underrun detection,\n–\nAnticipated frame synchronization signal detection in slave mode,\n–\nLate frame synchronization signal detection in slave mode,\n–\nCodec not ready for the AC’97 mode in reception.\n•\nInterruption sources when enabled:\n–\nErrors,\n–\nFIFO requests.\n•\nDMA interface with 2 dedicated channels to handle access to the dedicated integrated \nFIFO of each SAI audio sub-block.\n" }, { "page_number": 931, "page_indices": { "start_index": 1810309, "end_index": 1812220 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 931 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.3 Functional block diagram", 931 ] ], "page_content": "RM0090 Rev 21\n931/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.3 \nFunctional block diagram\nThe block diagram of the SAI is shown in Figure 283. \nFigure 283. Functional block diagram\nThe SAI is mainly composed of two audio sub-blocks with their own clock generator. Each \naudio block integrates a 32-bit shift register controlled by their own functional state machine. \nData are stored or read from the dedicated FIFO. FIFO may be accessed by the CPU, or by \nDMA in order to leave the CPU free during the communication. Each audio block is \nindependent. They can be synchronous with each other.\nAn I/O line controller manages each dedicated pins for a given audio block in the SAI. If the \ntwo blocks are synchronized, this controller reduces the number of I/Os used, freeing up an \nFS pin, an SCK pin and eventually an MCLK pin, making them general purpose I/Os\nThe functional state machine can be configured to address a wide range of audio protocols. \nSome registers are present to set-up the desired protocols (audio frame waveform \ngenerator). \nThe audio block can be a transmitter or receiver, in master or slave mode. The master mode \nmeans the bit clock SCK and the frame synchronization signal are generated from the SAI, \nwhereas in slave mode, they come from another external or internal master. There is a \nparticular case for which the FS signal direction is not directly linked to the master or slave \nMS30032V1\nFIFO\nFIFO\nAudio block A\n32-bit shift register\nAPB interface\nAPB interface\nSerial Audio Interface\nFIFO ctrl\nFSM\nConfiguration \nregisters and\nStatus register\nAPB\nAPB\nSAI_CK_A\nsynchro\nctrl out\n \nint_sck\nint_FS\nFS_A\nSCK_A\nSD_A\nMCLK_A\nSAI_XCR1\nClock generator\nAudio block A\nFSM\n(SAI)\nAudio block B\nFIFO ctrl\nConfiguration \nregisters and\nStatus register\nClock generator\nAudio block B\nSAI_XCR1\nSAI_CK_B\nI/O line Management\nFS_B\nSCK_B\nSD_B\nMCLK_B\n32-bit shift register\n" }, { "page_number": 932, "page_indices": { "start_index": 1812220, "end_index": 1814808 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 932 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.4 Main SAI modes", 932 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n932/1757\nRM0090 Rev 21\nmode definition. In AC’97 protocol, it is an SAI output even if the SAI (link controller) is set-\nup to consume the SCK clock (and so to be in Slave mode). \n29.4 \nMain SAI modes\nEach audio sub-block of the SAI can be configured to be master or slave via bit MODE[0] in \nthe SAI_xCR1 register of the selected audio block. \nIn master mode:\n•\nThe bit clock is generated by the SAI using the clock generator on pin SCK_A or \nSCK_B (depending which audio block is declared as a master in the SAI). \n•\nThe dedicated pin SCK_x is considered as an output.\nIn slave mode:\n•\nThe slave must be enabled before the master is enabled.\n•\nThe slave audio block’s SCK clock I/O pin is considered input if it is configured in \nasynchronous mode.\n•\nIf the audio block is declared synchronous with the second audio block in the SAI, its \nSCK I/O pin is released to leave it free to be used as a general purpose I/O and is \nconnected internally to the SCK pin of the device with which it is synchronized.\nEach audio sub-block can be independently defined as a transmitter or receiver by bit \nMODE[1] in the SAI_xCR1 register of the relevant audio block. The I/O pin SD is defined \nrespectively as an output or an input.\nIt is possible to declare two master audio blocks in the same SAI with two different MCLK \nand SCK clock frequencies (they have to be declared asynchronous). \nEach of the audio blocks in the SAI are enabled by bit SAIxEN in the SAI_xCR1 register. As \nsoon as this bit is active, the transmitter or the receiver is sensitive to the activity on the \nclock line, data line and synchronization line in slave mode. \nIn master TX mode, enabling the audio block immediately generates the bit clock for the \nexternal slaves even if there is no data in the FIFO, However FS signal generation is \nconditioned by the presence of data in the FIFO. After the FIFO receives the first data to \ntransmit, this data is output to external slaves. If there is no data to transmit in the FIFO, 0 \nvalues are then sent in the audio frame with an underrun flag generation.\nIn slave mode, the audio frame starts when the audio block is enabled and when a start of \nframe is detected.\nIn Slave TX mode, no underrun event is possible on the first frame after the audio block is \nenabled, because the mandatory operating sequence in this case is:\n1.\nWrite into the SAI_xDR (by software or by DMA).\n2. \nWait until the FIFO threshold (FLH) flag is different from 000b (FIFO empty).\n3. \nEnable the audio block in slave transmitter mode.\n" }, { "page_number": 933, "page_indices": { "start_index": 1814808, "end_index": 1816880 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 933 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.5 SAI synchronization mode", 933 ], [ 3, "Internal synchronization", 933 ], [ 2, "29.6 Audio data size", 933 ], [ 2, "29.7 Frame synchronization", 933 ] ], "page_content": "RM0090 Rev 21\n933/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.5 \nSAI synchronization mode\nInternal synchronization\nAn audio block can be declared synchronous with the second audio block. In this case, the \nbit clock and the frame synchronization signals are shared to reduce the number of external \npins used for the communication. The audio block declared as synchronous with the other \none sees its own SCK_x, FS_x, and MCLK_x pins released to bring them back as GPIOs. \nThe one declared asynchronous is the one for which the I/O pins FS_x and SCK_x ad \nMCLK_x (if the audio block is considered as master) are considered.\nTypically, the audio block synchronous mode may be used to configure the SAI in full duplex \nmode. One of the two audio blocks can be configured as master and the other as slave, or \nboth can be slaves; with one block declared as asynchronous (respective bit SYNCEN[1:0] \n= 00 in SAI_xCR1) and the other one declared as synchronous with the other audio block \n(respective bit SYNCEN[1:0] = 01 in the SAI_xCR1).\nNote:\nAPB frequency PCLK must be greater or equal to twice the bit rate clock frequency (due to \ninternal resynchronization stages).\n29.6 \nAudio data size\nThe audio frame can target different data sizes by configuring bit DS[2:0] in the SAI_xCR1 \nregister. The data sizes may be 8-, 10-, 16-, 20-, 24- or 32-bit. During the transfer, either the \nMSB or the LSB of the data are sent first, depending on the configuration of bit LSBFIRST in \nthe SAI_xCR1 register.\n29.7 \nFrame synchronization\nThe FS signal acts as the Frame synchronization signal in the audio frame (start of frame). \nThe shape of this signal is completely configurable in order to target the different audio \nprotocols with their own specificities concerning this Frame synchronization behavior. This \nconfigurability is done using register SAI_xFRCR. Figure 284 gives a view of this flexibility.\nFigure 284. Audio frame\nSlot 0\nFs\nsck\nsd\nFs offset\nFs length = < 256 bits\nFs active length = < 128 bits\nMS30037V1\nSlot 1\nSlot 2\nSlot 3\nSlot n\n…\n…\n" }, { "page_number": 934, "page_indices": { "start_index": 1816880, "end_index": 1820137 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 934 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.7 Frame synchronization", 933 ], [ 3, "29.7.1 Frame length", 934 ], [ 3, "29.7.2 Frame synchronization polarity", 934 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n934/1757\nRM0090 Rev 21\nIn AC’97 mode (bit PRTCFG[1:0] = 10 in the SAI_xCR1 register), the frame synchronization \nshape is forced to be configured to target these protocols. The SAI_xFRCR register value is \nignored.\nEach audio block is independent and so each requires a specific configuration.\n29.7.1 \nFrame length\n•\nMaster mode: The audio frame length can be configured up to 256 bit clock, setting bit \nFRL[7:0] in the SAI_xFRCR register. If the frame length is greater than the number of \ndeclared slots for the frame, the remaining bits to transmit are extended to 0 or the SD \nline is released to HI-z depending the state of bit TRIS in the SAI_xCR2 register (refer \nto Section 29.12.4). In reception mode, the remaining bit is ignored.\n•\nSlave mode: The audio frame length is mainly used in order to specify to the slave the \nnumber of bit clocks per audio frame sent by the external master. It is used mainly to \ndetect from the master, any anticipated or late occurrence of the Frame \nsynchronization signal during an on-going audio frame. An error is generated in such \ncase. For more details please refer to the Section 29.13.\nThe number of bits in the frame is equal to FRL[7:0] + 1. \nThe minimum number of bits to transfer in an audio frame is 8. This is the case when the \ndata size is 8-bit and only one slot is defined in NBSLOT[3:0] in the SAI_xSLOTR register \n(NBSLOT[3:0] = 0000 for slot 0).\nIn master mode:\n•\nIf bit NODIV in the SAI_xCR1 register is cleared, the frame length should be aligned to \na number equal to a power of 2, from 8 to 256. This is to ensure that an audio frame \ncontains an integer number of MCLK pulses per bit clock, which ensures correct \noperation of the external DAC/ADC inside the decoders. If the value set in FRL[7:0] \ndoes not respect this rule, flag WCKCFG is set when the audio block is enabled and an \ninterrupt is generated if bit WCKCFGIE is set in the SAI_xIM register. The SAI is \nautomatically disabled.\n•\nIf bit NODIV in the SAI_xCR1 register is set, the FRL[7:0] bit can take any of the values \nwithout constraint since the input clock of the audio block should be equal to the bit \nclock. There is no MCLK_x clock which can be output. MCLK_x output pad is \nautomatically disabled.\nIn slave mode, there are no constraints for the FRL[7:0] bit configuration in the SAI_xFRCR \nregister.\n29.7.2 \nFrame synchronization polarity\nBit FSPOL in the SAI_xFRCR register sets the active polarity of the FS pin from which a \nframe is started. The start of frame is edge sensitive.\nIn slave mode, the audio block waits for a valid frame to start to transmit or to receive. Start \nof frame is synchronized to this signal. It is effective only if the start of frame is not detected \nduring an on-going communication and assimilated to an anticipated start of frame (refer to \nSection 29.13).\nIn master mode, the frame synchronization is sent continuously each time an audio frame is \ncomplete until the SAIxEN bit in the SAI_xCR1 register is cleared. If no data is present in the \nFIFO at the end of the previous audio frame, an underrun condition is managed as \ndescribed in Section 29.13), but there is no interruption in the audio communication flow.\n" }, { "page_number": 935, "page_indices": { "start_index": 1820137, "end_index": 1822409 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 935 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.7 Frame synchronization", 933 ], [ 3, "29.7.3 Frame synchronization active level length", 935 ], [ 3, "29.7.4 Frame synchronization offset", 935 ], [ 3, "29.7.5 FS signal role", 935 ] ], "page_content": "RM0090 Rev 21\n935/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.7.3 \nFrame synchronization active level length\nBit FSALL[6:0] in the SAI_xFRCR register configures the length of the active level of the \nFrame synchronization signal. The length can be set from 1 to 128 bit clock SCK. \nThe active length may be half of the frame length in I2S, LSB or MSB-justified modes for \ninstance, or one-bit wide for PCM/DSP or free protocol mode, or even 16-bit length in \nAC’97. \n29.7.4 \nFrame synchronization offset\nDepending on the audio protocol targeted in the application, the Frame synchronization \nsignal can be asserted when transmitting the last bit or the first bit of the audio frame (as for \ninstance, respectively, in I2S standard protocol and in MSB-justified protocol). Bit FSOFF in \nthe SAI_xFRCR register makes the choice.\n29.7.5 \nFS signal role\nThe FS signal may have a different meaning depending on the FS function. Bit FSDEF in \nthe SAI_xFRCR register selects which meaning it has. It may be either:\n•\n0: a start of frame, like for instance the PCM/DSP, free protocol, AC’97, audio \nprotocols, \n•\n1: a start of frame and a channel side identification within the audio frame like for the \nI2S, the MSB or LSB-justified protocols. \nWhen the FS signal is considered as a start of frame and channel side identification within \nthe frame, the number of declared slots must be considered to be half of the number for the \nleft channel and half of the number for the right channel. If the number of bit clock on half \naudio frame is greater than the number of slots dedicated to a channel side, if TRIS = 0, 0 is \nsent for transmission for the remaining bit clock in the SAI_xCR2 register, otherwise if TRIS \n= 1, the SD line is released to HI-Z. In reception, the remaining bit clock are not considered \nuntil the channel side changes.\nFigure 285. FS role is start of frame + channel side identification (FSDEF = TRIS = 1)\n1.\nThe frame length should be even.\nsck\nslot\nAudio frame\nFS\nHalf of frame\nAudio frame\nFS\nHalf of frame\nNumber of slots not aligned with the audio frame\nNumber of slots aligned with the audio frame\nMS30038V1\nSlot 0 \nsck\nslot\nSlot 1\nSlot 2\nSlot 3\nSlot 5\nSlot 4\nSlot 0 ON\nSlot 1 OFF\nSlot 2 ON\nSlot 3 ON\nSlot 4 OFF\nSlot 5 ON\n" }, { "page_number": 936, "page_indices": { "start_index": 1822409, "end_index": 1824432 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 936 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.8 Slot configuration", 936 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n936/1757\nRM0090 Rev 21\nIf bit FSDEF in SAI_xFRCR is kept clear, so FS signal is equivalent to a start of frame, and \nif the number of slots defined in bit NBSLOT[3:0] in SAI_xSLOTR multiplied by \nthe number of bits by slot configured in bit SLOTSZ[1:0] in SAI_xSLOTR is less than the \nframe size (bit FRL[7:0] in the SAI_xFRCR register), then, \n•\nif TRIS = 0 in the SAI_xCR2 register, the remaining bit after the last slot is forced to 0 \nuntil the end of frame in case of transmission,\n•\nif TRIS = 1, the line is released to HI-Z during the transfer of these remaining bits. In \nreception mode, these bits are discarded.\nFigure 286. FS role is start of frame (FSDEF = 0)\n29.8 \nSlot configuration\nThe slot is the basic element in the audio frame. The number of slots in the audio frame is \nequal to the configured setting of bit NBSLOT[3:0] in the SAI_xSLOTR register +1. \nThe maximum number of slots per audio frame is fixed at 16. \nFor AC’97 protocol (when bit PRTCFG[1:0] = 10), the number of slots is automatically set to \ntarget the protocol specification, and the value of NBSLOT[3:0] is ignored. \nEach slot can be defined as a valid slot, or not, by setting bit SLOTEN[15:0] in the \nSAI_xSLOTR register. In an audio frame, during the transfer of a non-valid slot, 0 value is \nforced on the data line or the SD data line is released to HI-z (refer to Section 29.12.4) if the \naudio block is transmitter, or the received value from the end of this slot is ignored. \nConsequently, there is no FIFO access and so no request to read or write the FIFO linked to \nthis inactive slot status.\nThe slot size is also configurable as shown in the Figure 287. The size of the slots is \nselected by setting bit SLOTSZ[1:0] in the SAI_xSLOTR register. The size is applied \nidentically for each slot in an audio frame. \nAudio frame\nData = 0 after slot n if TRIS = 0\nSD output released (HI-Z) after slot n if TRIS = 1\nMS30039V1\nsck\nslot\nSlot 0 \nSlot 1 \nSlot 2 \nSlot n\n...\n" }, { "page_number": 937, "page_indices": { "start_index": 1824432, "end_index": 1826031 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 937 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.8 Slot configuration", 936 ] ], "page_content": "RM0090 Rev 21\n937/1757\nRM0090\nSerial audio interface (SAI)\n967\nFigure 287. Slot size configuration with FBOFF = 0 in SAI_xSLOTR\nIt is possible to choose the position of the first data bit to transfer within the slots, this offset \nis configured by bit FBOFF[5:0] in the SAI_xSLOTR register. 0 values are injected in \ntransmitter mode from the beginning of the slot until this offset position is reached. In \nreception, the bit in the offset phase is ignored. This feature targets the LSB justified \nprotocol (if the offset is equal to the slot size minus the data size).\nFigure 288. First bit offset\nIt is mandatory to respect the following conditions in order to avoid bad SAI behavior:\nFBOFF ≤ (SLOTSZ - DS),\nDS ≤ SLOTSZ,\nNBSLOT x SLOTSZ ≤ FRL (frame length),\nThe number of slots should be even when bit FSDEF in the SAI_xFRCR register is set.\nIn AC’97 (bit PRTCFG[1:0] = 10), the slot size is automatically set as defined in \nSection 29.11. \nMS30033V1\n00..00\n00..00\nX..X\nXX..XX\nX: don’t care\nAudio block is transmitter\nSlot size = data size\ndata size\ndata size\ndata size\ndata size\nslotx\nslotx\nslotx\n16-bit\n32-bit\nAudio block is receiver\nSlot size = data size\ndata size\ndata size\ndata size\nslotx\nslotx\nslotx\n16-bit\n32-bit\ndata size\nMS30034V1\nXX .. XX\n00\n00..00\nX: don’t care\nAudio block is transmitter\nSlot size = data size\ndata size\ndata size\ndata size\ndata size\nslotx\nslotx\nslotx\n16-bit\n32-bit\nAudio block is receiver\n00\nFBOFF\nFBOFF = SLOT SZ -DS\nXX\nSlot size = data size\ndata size\ndata size\ndata size\ndata size\nslotx\nslotx\nslotx\n16-bit\n32-bit\nXX\nFBOFF\nFBOFF = SLOT SZ -DS\n" }, { "page_number": 938, "page_indices": { "start_index": 1826031, "end_index": 1827669 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 938 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.9 SAI clock generator", 938 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n938/1757\nRM0090 Rev 21\n29.9 \nSAI clock generator\nEach audio block has its own clock generator to make these two blocks completely \nindependent. There is no difference in terms of functionality between these two clock \ngenerators. They are exactly the same.\nWhen the audio block is defined as Master, the clock generator generates the \ncommunication clock (the bit clock) and the master clock for external decoders. \nWhen the audio block is defined as slave, the clock generator is OFF.\nFigure 289 illustrates the architecture of the audio block clock generator.\nFigure 289. Audio block clock generator overview\nNote:\nIf NoDiv is set to 1, the MCLK_x signal is set at 0 level if this pin is configured as the SAI pin \nin GPIO peripherals.\nThe clock source for the clock generator comes from the product clock controller. The \nSAI_CK_x clock is equivalent to the master clock which may be divided for the external \ndecoders using bit MCKDIV[3:0]: \nMCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2), if MCKDIV[3:0] is not equal to 0000. \nMCLK_x = SAI_CK_x, if MCKDIV[3:0] is equal to 0000.\nMCLK_x signal is used only in free protocol mode.\nThe division must be even in order to keep 50% on the Duty cycle on the MCLK output and \non the SCK_x clock. If bit MCKDIV[3:0] = 0000, division by one is applied to have MCLK_x \n= SAI_CK_x.\nIn the SAI, the single ratio MCLK/FS = 256 is considered. Mostly, three frequency ranges \nare encountered as illustrated in the Table 131.\nMaster clock\ndivider\nBit clock divider \nMCKDIV[3:0]\nSCK_x\nMCLK_x\nNODIV\n0\n1\n0\n1\nNODIV\n0\n1\n0\nNODIV\nSAI_CK_x\nMS30040V1\nFRL[7:0]\n" }, { "page_number": 939, "page_indices": { "start_index": 1827669, "end_index": 1829982 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 939 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.10 Internal FIFOs", 939 ] ], "page_content": "RM0090 Rev 21\n939/1757\nRM0090\nSerial audio interface (SAI)\n967\n \nThe master clock may be generated externally on an I/O pad for external decoders if the \ncorresponding audio block is declared as master with bit NODIV = 0 in the SAI_xCR1 \nregister. In slave, the value set in this last bit is ignored since the clock generator is OFF, \nand the MCLK_x I/O pin is released for use as a general purpose I/O.\nThe bit clock is derived from the master clock. The bit clock divider sets the divider factor \nbetween the bit clock SCK_x and the master clock MCLK_x following the formula:\nSCK_x = MCLK x (FRL[7:0] +1) / 256\nwhere:\n256 is the fixed ratio between MCLK and the audio frequency sampling.\nFRL[7:0] is the number of bit clock - 1 in the audio frame, configured in the SAI_xFRCR \nregister.\nIt is mandatory in master mode that (FRL[7:0] +1) should be equal to a number with a power \nof 2 (refer to Section 29.7) in order to have an even integer number of MCLK_x pulses by bit \nclock. The 50% duty cycle is guaranteed on the bit clock SCK_x.\nThe SAI_CK_x clock can be also equal to the bit clock frequency. In this case, bit NODIV in \nthe SAI_xCR1 register should be set and the value inside the MCKDIV divider and the bit \nclock divider is ignored. In this case, the number of bits per frame is fully configurable \nwithout the need to be equal to a power of two.\nThe bit clock strobing edge on SCK can be configured by bit CKSTR in the SAI_xCR1 \nregister.\n29.10 \nInternal FIFOs\nEach audio block in the SAI has its own FIFO. Depending if the block is defined to be a \ntransmitter or a receiver, the FIFO is written or read, respectively. There is therefore only \none FIFO request linked to FREQ bit in the SAI_xSR register. \nTable 131. Example of possible audio frequency sampling range\nInput SAI_CK_x clock \nfrequency\nMost usual audio frequency \nsampling achievable\nMCKDIV[3:0]\n192 kHz x 256\n192 kHz\n MCKDIV[3:0] = 0000\n96 kHz\n MCKDIV[3:0] = 0001\n48 kHz\n MCKDIV[3:0] = 0010\n16 kHz\n MCKDIV[3:0] = 0100\n8 kHz\n MCKDIV[3:0] = 1000\n44.1 kHz x 256\n44.1 kHz\n MCKDIV[3:0] = 0000\n22.05 kHz\n MCKDIV[3:0] = 0001\n11.025 kHz\n MCKDIV[3:0] = 0010\nSAI_CK_x = MCLK(1)\n1.\nThis may happen when the product clock controller selects an external clock source, instead of PLL clock.\nMCLK\n MCKDIV[3:0] = 0000\n" }, { "page_number": 940, "page_indices": { "start_index": 1829982, "end_index": 1833623 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 940 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.10 Internal FIFOs", 939 ], [ 3, "Interrupt generation in transmitter mode", 940 ], [ 3, "Interrupt generation in reception mode", 940 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n940/1757\nRM0090 Rev 21\nAn interrupt is generated if FREQIE bit is enabled in the SAI_xIM register. This depends on: \n•\nFIFO threshold setting (FLTH bits in SAI_CR2) \n•\nCommunication direction transmitter or receiver (see Section : Interrupt generation in \ntransmitter mode and Section : Interrupt generation in reception mode)\nInterrupt generation in transmitter mode\nThe interrupt generation depends on the FIFO configuration in transmitter mode: \n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO empty \n(FTH[2:0] set to 000b), an interrupt is generated (FREQ bit set by hardware to 1 in \nSAI_XSR register) if no data are available in SAI_xDR register (FLTH[2:0] bits in SAI_xSR \nis less than 001b). This Interrupt (FREQ bit in SAI_XSR register) is cleared by hardware \nwhen the FIFO became not empty (FLTH[2:0] bits in SAI_xSR are different from 000b) i.e \none or more data are stored in the FIFO.\n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO quarter full \n(FTH[2:0] set to 001b), an interrupt is generated (FREQ bit set by hardware to 1 in \nSAI_XSR register) if less than a quarter of the FIFO contains data (FLTH[2:0] bits in \nSAI_xSR are less than 010b). This Interrupt (FREQ bit in SAI_XSR register) is cleared by \nhardware when at least a quarter of the FIFO contains data (FLTH[2:0] bits in SAI_xSR \nare higher or equal to 010b).\n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO half full \n(FTH[2:0] set to 010b), an interrupt is generated (FREQ bit set by hardware to 1 in \nSAI_XSR register) if less than half of the FIFO contains data (FLTH[2:0] bits in SAI_xSR \nare less than 011b). This Interrupt (FREQ bit in SAI_XSR register) is cleared by hardware \nwhen at least half of the FIFO contains data (FLTH[2:0] bits in SAI_xSR are higher or \nequal to 011b).\n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO three quarter \n(FTH[2:0] set to 011b), an interrupt is generated (FREQ bit is set by hardware to 1 in \nSAI_XSR register) if less than three quarters of the FIFO contain data (FLTH[2:0] bits in \nSAI_xSR are less than 100b). This Interrupt (FREQ bit in SAI_XSR register) is cleared by \nhardware when at least three quarters of the FIFO contain data (FLTH[2:0] bits in \nSAI_xSR are higher or equal to 100b).\n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO full (FTH[2:0] \nset to 100b), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_XSR \nregister) if the FIFO is not full (FLTH[2:0] bits in SAI_xSR is less than 101b). This Interrupt \n(FREQ bit in SAI_XSR register) is cleared by hardware when the FIFO is full (FLTH[2:0] \nbits in SAI_xSR is equal to 101b value).\nInterrupt generation in reception mode\nThe interrupt generation depends on the FIFO configuration in reception mode: \n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO empty \n(FTH[2:0] set to 000b), an interrupt is generated (FREQ bit is set by hardware to 1 in \nSAI_XSR register) if at least one data is available in SAI_xDR register(FLTH[2:0] bits in \nSAI_xSR is higher or equal to 001b). This Interrupt (FREQ bit in SAI_XSR register) is \ncleared by hardware when the FIFO became empty (FLTH[2:0] bits in SAI_xSR is equal \nto 000b) i.e no data is stored in FIFO.\n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO quarter fully \n(FTH[2:0] set to 001b), an interrupt is generated (FREQ bit is set by hardware to 1 in \nSAI_XSR register) if at less one quarter of the FIFO data locations are available \n" }, { "page_number": 941, "page_indices": { "start_index": 1833623, "end_index": 1836168 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 941 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.10 Internal FIFOs", 939 ], [ 3, "Interrupt generation in reception mode", 940 ] ], "page_content": "RM0090 Rev 21\n941/1757\nRM0090\nSerial audio interface (SAI)\n967\n(FLTH[2:0] bits in SAI_xSR is higher or equal to 010b). This Interrupt (FREQ bit in \nSAI_XSR register) is cleared by hardware when less than a quarter of the FIFO data \nlocations become available (FLTH[2:0] bits in SAI_xSR is less than 010b).\n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO half fully \n(FTH[2:0] set to 010b value), an interrupt is generated (FREQ bit is set by hardware to 1 \nin SAI_XSR register) if at least half of the FIFO data locations are available (FLTH[2:0] \nbits in SAI_xSR is higher or equal to 011b). This Interrupt (FREQ bit in SAI_XSR register) \nis cleared by hardware when less than half of the FIFO data locations become available \n(FLTH[2:0] bits in SAI_xSR is less than 011b).\n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO three quarter \nfull(FTH[2:0] set to 011b value), an interrupt is generated (FREQ bit is set by hardware to \n1 in SAI_XSR register) if at least three quarters of the FIFO data locations are available \n(FLTH[2:0] bits in SAI_xSR is higher or equal to 100b). This Interrupt (FREQ bit in \nSAI_XSR register) is cleared by hardware when the FIFO has less than three quarters of \nthe FIFO data locations avalable(FLTH[2:0] bits in SAI_xSR is less than 100b).\n•\nWhen the FIFO threshold bits in SAI_XCR2 register are configured as FIFO full(FTH[2:0] \nset to 100b), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_XSR \nregister) if the FIFO is full (FLTH[2:0] bits in SAI_xSR is equal to 101b). This Interrupt \n(FREQ bit in SAI_XSR register) is cleared by hardware when the FIFO is not full \n(FLTH[2:0] bits in SAI_xSR is less than 101b). \nLike interrupt generation, the SAI can use the DMA if DMAEN bit in the SAI_xCR1 register is \nset. The FREQ bit assertion mechanism is the same as the interruption generation \nmechanism described above for FREQIE.\nEach FIFO is an 8-word FIFO. Each read or write operation from/to the FIFO targets one \nword FIFO allocation whatever the access size. Each FIFO word contains one audio frame. \nFIFO pointers are incremented by one word after each access to the SAI_xDR register.\nData should be right aligned when it is written in the SAI_xDR. \nData received are right aligned in the SAI_xDR.\nThe FIFO pointers can be reinitialized when the SAI is disabled by setting bit FFLUSH in the \nSAI_xCR2 register. If FFLUSH is set when the SAI is enabled, the data present in the FIFO \nare lost automatically.\n" }, { "page_number": 942, "page_indices": { "start_index": 1836168, "end_index": 1838185 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 942 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.11 AC’97 link controller", 942 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n942/1757\nRM0090 Rev 21\n29.11 \nAC’97 link controller\nThe SAI is able to work as an AC’97 link controller. In this protocol:\n•\nThe slot number and the slot size are fixed. \n•\nThe frame synchronization signal is perfectly defined and has a fixed shape. \nTo select this protocol, set bit PRTCFG[1:0] in the SAI_xCR1 register to 10. When AC’97 \nmode is selected the data sizes that can be used are 16-bit or 20-bit only, else SAI behavior \nis not guaranteed.\n•\nBits NBSLOT[3:0] and SLOTSZ[1:0] are consequently ignored. \n•\nThe number of slots is fixed at 13 slots. The first one is 16 bits wide and all the others \nare 20 bits wide (data slots).\n•\nBit FBOFF[5:0] in the SAI_xSLOTR register is ignored\n•\nThe SAI_xFRCR register is ignored. \nThe FS signal from the block defined as asynchronous is configured automatically as an \noutput, since the AC’97 controller link drives the FS signal whatever the master or slave \nconfiguration.\nFigure 290 presents an AC’97 audio frame structure.\nFigure 290. AC’97 audio frame\nNote:\nIn AC’97 protocol, bit 2 of the tag is reserved (always 0), so whatever the value written in the \nSAI FIFO, bit 2 of the TAG is forced to 0 level.\nFor more details about TAG representation, please refer to the AC’97 protocol standard.\nOne SAI can be used to target an AC’97 point-to-point communication.\nIn receiver mode, the SAI acting as an AC’97 link controller does not require any FIFO \nrequest and so no data storage in the FIFO when the codec ready bit in the slot 0 is \ndecoded low. If bit CNRDYIE is enabled in the SAI_xIM register, flag CNRDY is set in the \nSAI_xSR register and an interrupt is generated. This flag is dedicated to the AC’97 protocol.\nMS192343V1\nFS\n1\n2\n3\n4\n5\n6\n7\n8\n9\n10\n11\n12\nSDI\nSDO\nTag\nCMD\nADDR\nCMD\nDATA\nLINE1\nDAC\nPCM\nLFRONT\nPCM\nRFRONT\nPCM\nCENTER\nPCM\nLSURR\nPCM\nRSURR\nPCM\nLFE\nLINE2\nDAC\nHSET\nDAC\nIO\nCTRL\nTag\nSTATUS\nADDR\nSTATUS\nDATA\nLINE1\nADC\nPCM\nLEFT\nPCM\nRIGHT\nPCM\nMIC\nRSR\nVD\nRSR\nLVD\nLINE2\nADC\nHSET\nIO\nSTATUS\nRSR\nVD\n" }, { "page_number": 943, "page_indices": { "start_index": 1838185, "end_index": 1841225 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 943 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.12 Specific features", 943 ], [ 3, "29.12.1 Mute mode", 943 ], [ 4, "Transmitter", 943 ], [ 4, "Receiver", 943 ], [ 3, "29.12.2 MONO/STEREO function", 943 ] ], "page_content": "RM0090 Rev 21\n943/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.12 \nSpecific features\nThe SAI has some specific functions which can be useful depending on the audio protocol \nselected. These functions are accessible through specific bits in the SAI_xCR2 register.\n29.12.1 \nMute mode \nMute mode may be used when the audio block is a transmitter or receiver.\nTransmitter\nIn transmitter mode, Mute mode can be selected at anytime. Mute mode is active for entire \naudio frames. The bit MUTE in the SAI_xCR2 register requests Mute mode when it is set \nduring an on-going frame.\nThe mute mode bit is strobed only at the end of the frame. If set at this time, the mute mode \nis active at the beginning of the new audio frame, for a complete frame, until the next end of \nframe, it then strobes the bit to determine if the next frame is still a mute frame.\nIf the number of slots set in bit NBSLOT[3:0] in the SAI_xSLOTR register is lower than or \nequal to two, it is possible to specify if the value sent during the Mute mode is 0 or if it is the \nlast value of each slot. The selection is done via bit MUTEVAL in the SAI_xCR2 register.\nIf the number of slots set in bit NBSLOT[3:0] in the SAI_xSLOTR register is greater than \ntwo, MUTEVAL bit in the SAI_xCR2 has no meaning as 0 values are sent on each bit on \neach slot. \nDuring Mute mode, the FIFO pointers are still incremented, meaning that data which was \npresent in the FIFO and for which the Mute mode is requested is discarded.\nReceiver\nIn receiver mode, it is possible to detect a Mute mode sent from the external transmitter \nwhen all the declared and valid slots of the audio frame receive 0 for a given consecutive \nnumber of audio frames (bit MUTECNT[5:0] in the SAI_xCR2 register). \nWhen the number of MUTE frames is detected, flag MUTEDET in the SAI_xSR register is \nset and an interrupt can be generated if bit MUTEDETIE is set in the SAI_xCR2. \nThe mute frame counter is cleared when the audio block is disabled or when a valid slot \nreceives at least one data in an audio frame. The interrupt is generated just once, when the \ncounter reaches the specified value in bit MUTECNT[5:0]. Then the interrupt event is re-\narmed when the counter is cleared.\n29.12.2 \nMONO/STEREO function\nIn transmission mode, it is possible to address the Mono mode without any data pre-\nprocessing in memory when the number of slot is equal to 2 (NBSLOT[3:0] = 0001 in the \nSAI_xSLOTR). In such a case, the access to and from the FIFO is reduced by two since in \ntransmission, the data for slot 0 is duplicated into data slot 1. \nTo select the Mono feature, set bit MONO in the SAI_xCR1 register.\nIn reception mode, bit MONO can be set and has a meaning only if the number of slots is \nequal to 2 like for the transmission mode. When it is set, only the data of slot 0 are stored in \nthe FIFO. The data belonging to slot 1 are discarded since in this case, it is supposed to be \nthe same as the previous slot. If the data flux in reception is a real stereo audio flow with a \n" }, { "page_number": 944, "page_indices": { "start_index": 1841225, "end_index": 1843356 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 944 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.12 Specific features", 943 ], [ 3, "29.12.3 Companding mode", 944 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n944/1757\nRM0090 Rev 21\ndistinct and different left and right data, bit MONO has no meaning. The conversion from the \noutput stereo file to the equivalent mono file is done by software.\nNote:\nTo enable Mono mode, NBSLOT and SLOTEN must equal two and MONO bit set to 1.\n29.12.3 \nCompanding mode\nTelecommunication applications may require to process the data to transmit or to receive \nwith a data companding algorithm.\nDepending on the COMP[1:0] bit in the SAI_xCR2 register (used only when free protocol \nmode is selected), the software may choose to process or not the data before sending it on \nSD serial output line (compression) or to expand the data after the reception on SD serial \ninput line (expansion) as illustrated in Figure 291. The two companding modes supported \nare the µ-Law and the A-Law log which are a part of the CCITT G.711 recommendation. \nThe companding standard employed in the United States and Japan is the µ-Law and allows \n14 bits of dynamic range (COMP[1:0] = 10 in the SAI_xCR2 register). \nThe European companding standard is A-Law and allows 13 bits of dynamic range \n(COMP[1:0] = 11 in the SAI_xCR2 register).\nCompanding standard (µ-Law or A-Law) can be computed based on 1’s complement or 2’s \ncomplement representation depending on the CPL bit setting in the SAI_xCR2 register.\nThe µ-Law and A-Law formats encode data into 8-bit code elements with MSB alignment. \nCompanded data is always 8 bits wide. For this reason, bit DS[2:0] in the SAI_xCR1 register \nis forced to 010 when the SAI audio block is enabled (bit SAIxEN = 1 in the SAI_xCR1 \nregister) and when the COMP[1:0] bit selects one of these two companding modes.\nIf no companding processing is required, COMP[1:0] bit in the SAI_xCR2 register should be \nkept cleared.\nFigure 291. Data companding hardware in an audio block in the SAI\nNote:\nNot applicable when AC’97 selected.\nexpand\nFIFO \nCOMP[1]\nCOMP[1]\n32-bit shift register\nSD\nReceiver mode (bit MODE[0] = 1 in SAI_xCR1)\nTransmitter mode (bit MODE[0] = 0 in SAI_xCR1)\nMS19244V1\n1\n0\n1\n0\n32-bit shift register\nSD\ncompress\nFIFO \n" }, { "page_number": 945, "page_indices": { "start_index": 1843356, "end_index": 1845011 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 945 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.12 Specific features", 943 ], [ 3, "29.12.4 Output data line management on an inactive slot", 945 ] ], "page_content": "RM0090 Rev 21\n945/1757\nRM0090\nSerial audio interface (SAI)\n967\nExpansion or compression mode is automatically selected by the SAI configuration. \n•\nIf the SAI audio block is configured to be a transmitter, and if the COMP[1] bit is set in \nthe SAI_xCR2 register, the compression mode is applied. \n•\nIf the SAI audio block is declared as a receiver, the expansion algorithm is applied.\n29.12.4 \nOutput data line management on an inactive slot \nIn transmitter mode, it is possible to choose the behavior of the SD line in output when an \ninactive slot is sent on the data line (via bit TRIS in the SAI_xCR2 register when the SAI is \ndisabled).\n•\nEither the SAI forces 0 on the SD output line when an inactive slot is transmitted, or \n•\nThe line is released in HI-z state at the end of the last bit of data transferred, to release \nthe line for other transmitters connected to this node. \nIt is important to note that the two transmitters do not attempt to drive the same SD output \npin simultaneously, which could result in a short circuit. In order to ensure a gap between \ntransmissions, if the data is lower than 32-bit, the data can be extended to 32-bit by setting \nbit SLOTSZ[1:0] = 10 in the SAI_xSLOTR register. Then, the SD output pin is tristated at the \nend of the LSB of the active slot (during the padding to 0 phase to extend the data to 32-bit) \nif the following slot is declared inactive. \nIn addition, if the number of slots multiplied by the slot size is lower than the frame length, \nthe SD output line is tristated when the padding to 0 is done to complete the audio frame. \nFigure 292 illustrates these behaviors.\n" }, { "page_number": 946, "page_indices": { "start_index": 1845011, "end_index": 1846293 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 946 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.12 Specific features", 943 ], [ 3, "29.12.4 Output data line management on an inactive slot", 945 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n946/1757\nRM0090 Rev 21\nFigure 292. Tristate strategy on SD output line on an inactive slot\nWhen the selected audio protocol uses the FS signal as a start of frame and a channel side \nidentification (bit FSDEF = 1 in the SAI_xFRCR register), the tristate mode is managed \naccording to Figure 293 (where bit TRIS in the SAI_xCR1 register = 1, and FSDEF=1, and \nhalf frame length > number of slots/2, and NBSLOT=6).\nslot\nAudio frame\nBit TRIS = 1 in the SAI_xCR1 and frame length = number of slots\nMS192345V1\nSlot size = data size\nSlot size > data size\nBit TRIS = 1 in the SAI_xCR1 and frame length > number of slots\nSD (output)\nsck\nSlot 0 ON\nSlot 1 OFF\nSlot 2 OFF\nSlot 3 ON\n.. ON\n.. ON\nSlot n ON\nData 0\nData 1\n..\n..\nData m\nSlot 0 ON\nSlot 1 OFF\nSlot 2 OFF\nSlot 3 ON\n.. ON\n.. ON\nSlot n ON\nData 0\nData 1\n..\n..\nData m\nSlot 0 ON\nSlot 1 OFF\nSlot 2 OFF\nSlot 3 ON\n.. ON\n.. ON\nSlot n ON\nData 0\n..\n..\nData m\nslot\nSD (output)\nslot\nSD (output)\nslot\nAudio frame\nSlot size = data size\nSD (output)\nsck\nSlot 0 ON\nSlot 1 OFF\nSlot 2 OFF\n.. ON\nSlot n ON\nData 0\n..\nData m\nslot\nSlot size > data size\nSD (output)\nSlot 0 ON\nSlot 1 OFF\nSlot 2 OFF\n.. ON\nSlot n ON\n..\nData m\nData 0\nslot\nSD (output)\nSlot 0 ON\nSlot 1 OFF\nSlot 2 OFF\n.. ON\n..\nData m\n.. ON\n" }, { "page_number": 947, "page_indices": { "start_index": 1846293, "end_index": 1848174 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 947 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.13 Error flags", 947 ], [ 3, "29.13.1 FIFO overrun/underrun (OVRUDR)", 947 ], [ 4, "Overrun", 947 ] ], "page_content": "RM0090 Rev 21\n947/1757\nRM0090\nSerial audio interface (SAI)\n967\nFigure 293. Tristate on output data line in a protocol like I2S\nIf the TRIS bit in the SAI_xCR2 register is cleared, all the High impedance states on the SD \noutput line on Figure 292 and Figure 293 are replaced by a drive with a value of 0.\n29.13 \nError flags\nThe SAI embeds some error flags:\n–\nFIFO overrun/underrun,\n–\nAnticipated frame synchronization detection,\n–\nLate frame synchronization detection,\n–\nCodec not ready (AC’97 exclusively),\n–\nWrong clock configuration in master mode.\n29.13.1 \nFIFO overrun/underrun (OVRUDR)\nThe FIFO Overrun/Underrun bit is called OVRUDR in the SAI_xSR register.\nThe overrun or underrun errors occupy the same bit since an audio block can be either \nreceiver or transmitter and each audio block in an SAI has its own SAI_xSR register.\nOverrun\nWhen the audio block is configured as receiver, an overrun condition may appear if data is \nreceived in an audio frame when the FIFO is full and is not able to store the received data. \nIn this case, the received data is lost, the flag OVRUDR in the SAI_xSR register is set and \nan interrupt is generated if bit OVRUDRIE is set in the SAI_xIM register. The slot number \nfrom which the overrun occurs, is stored internally. No more data are stored into the FIFO \nuntil it becomes free to store new data. When the FIFO has at least one data free, the SAI \naudio block receiver stores new data (from new audio frame) from the slot number which \nslot\nMS192346V1\nSlot size = data size\nSlot size > data size\nSD (output)\nsck\nSlot 0 ON\nSlot 1 OFF\nSlot 2 ON\nSlot 3 ON\nSlot 4 OFF\nSlot 5 ON\nData 0\nData 1\nSlot 0 ON\nSlot 1 OFF\nSlot 2 ON\nData 0\nslot\nSD (output)\nData 2\nData 3\nSlot 3 ON\nSlot 4 OFF\nSlot 5 ON\nData 1\nData 2\nData 3\nSlot 0 ON\nSlot 1 OFF\nSlot 2 ON\nData 0\nslot\nSD (output)\nSlot 3 ON\nSlot 4 OFF\nSlot 5 ON\nData 1\nData m\n" }, { "page_number": 948, "page_indices": { "start_index": 1848174, "end_index": 1849672 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 948 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.13 Error flags", 947 ], [ 3, "29.13.1 FIFO overrun/underrun (OVRUDR)", 947 ], [ 4, "Underrun", 948 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n948/1757\nRM0090 Rev 21\nwas stored internally when the overrun condition was detected, and this, to avoid data slot \nde-alignment in the destination memory (refer to Figure 294).\nThe OVRUDR flag is cleared when bit COVRUDR is set in the SAI_xCLRFR register. \nFigure 294. Overrun detection error\nUnderrun\nAn underrun may occur when the audio block in the SAI is a transmitter and the FIFO is \nempty when data needs to be transmitted (the audio block configuration (Master or Slave) is \nnot relevant). If an underrun is detected, the software must resynchronize data and slot. \nProceed as follows:\n1.\nDisable the SAI peripheral by resetting the SAIEN bit of the SAI_xCR1 register. Check \nthat the SAI has been disabled by reading back the SAIEN bit (SAIEN should be equal \nto 0).\n2. \nFlush the Tx FIFO through the FFLUS bit of the SAI_xCR2 register.\n3. \nRe-assigned to the correct data to be transferred on the first active slot of the new \nframe.\n4. \nRe-enabling the SAI peripheral (SAIEN bit set to 1).\nThe underrun event sets the OVRUDR flag in the SAI_xSR register and an interrupt is \ngenerated if the OVRUDRIE bit is set in the SAI_xIM register. To clear this flag, set the \nCOVRUDR bit in the SAI_xCLRFR register.\nMS192348V2\nsck\ndata\nSlot 0 ON\nExample: FIFO overrun on Slot 1\nAudio frame\nAudio frame\nSlot n ON\n... ON\nFIFO full\nOVRUDR\nSlot 1 ON\nSlot 1 ON\nSlot 0 ON\nSlot 1 ON\nReceived data discarded\nData stored again in FIFO\nCOVRUDR = 1\n" }, { "page_number": 949, "page_indices": { "start_index": 1849672, "end_index": 1851940 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 949 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.13 Error flags", 947 ], [ 3, "29.13.2 Anticipated frame synchronisation detection (AFSDET)", 949 ], [ 3, "29.13.3 Late frame synchronization detection", 949 ] ], "page_content": "RM0090 Rev 21\n949/1757\nRM0090\nSerial audio interface (SAI)\n967\nFigure 295. FIFO underrun event\n29.13.2 \nAnticipated frame synchronisation detection (AFSDET)\nThis flag AFSDET is used only in Slave mode. In master mode, it is never asserted. It \ninforms about the detection of a frame synchronisation (FS) earlier than expected since the \nframe length, the frame polarity, the frame offset are defined and known. \nEarly detection sets flag AFSDET in the SAI_xSR register. \nThis detection has no effect on the current audio frame which is not sensitive to the \nanticipated FS. This means that “parasitic” events on signal FS are flagged without any \nperturbation of the current audio frame.\nIf bit AFSDETIE is set in the SAI_xIM register, an interrupt is generated. To clear the flag \nAFSDET, bit CAFSDET in the SAI_xCLRFR register has to be set.\nTo resynchronize with the master after Anticipated frame detection error, four steps should \nbe respected:\n1.\nSAI block should be disabled by resetting SAIEN bit in SAI_xCR1 register, to be sure \nthat the SAI is disabled SAIEN bit is should be equal to 0 (reading back this bit).\n2. \nFIFO should be flushed via FFLUS bit in SAI_xCR2 register.\n3. \nRe-enabling the SAI peripheral (SAIEN bit set to 1) then the SAI.\n4. \nSAI block waits for the assertion on FS to restart the synchronization with master.\nNote:\nThis flag is not asserted in AC’97 since the SAI audio block acts as a link controller and \ngenerates the FS signal even when declared as slave.\n29.13.3 \nLate frame synchronization detection\nFlag LFSDET in the SAI_xSR register can be set only when the SAI audio block is defined \nas slave. The frame length, the frame polarity and the frame offset configuration are known \nin register SAI_xFRCR. \nIf the external master does not send the FS signal at the expecting time (generating the \nsignal too late), the flag LFSDET in the SAI_xSR register is set and an interrupt is generated \nif bit LFSDETIE in the SAI_xIM register is set. \nThe flag is cleared when bit CLFSDET is set in the SAI_xCLRFR register. \nMS192347V2\nsck\ndata\nSlot 0 ON\nMUTE\nSlot size = data size\nSD (output)\nExample: FIFO underrun on Slot 1\nAudio frame\nAudio frame\nMUTE\nSlot 1 ON\n... ON\nSlot 0 ON\nOVRUND=1\nMUTE\nFIFO empty\nOVRUND\n" }, { "page_number": 950, "page_indices": { "start_index": 1851940, "end_index": 1854550 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 950 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.13 Error flags", 947 ], [ 3, "29.13.4 Codec not ready (CNRDY AC’97)", 950 ], [ 3, "29.13.5 Wrong clock configuration in master mode (with NODIV = 0)", 950 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n950/1757\nRM0090 Rev 21\nThe late frame synchronisation detection flag is set when the error is detected, SAI needs to \nbe resynchronized with the master (the four steps described above should be respected).\nThis detection and flag assertion can detect glitches on the SCK clock in a noisy \nenvironment, detected by the state machine of the audio block. It could incorrectly shift the \nSAI audio block state machine from one state in the current audio frame, thus corrupting the \nframe.\nThere is no corruption if the external master is not managing the audio data frame transfer in \na continuous mode, which should not be the case for most application purposes. In this \ncase, flag LFSDET is set.\nNote:\nThis flag is not asserted in AC’97 mode since the SAI audio block acts as a link controller \nand generates the FS signal even when declared as slave.\n29.13.4 \nCodec not ready (CNRDY AC’97)\nThe flag CNRDY in the SAI_xSR register is relevant only if the SAI audio block is configured \nto work in AC’97 mode (bit PRTCFG[1:0] = 10 in the SAI_xCR1 register). If bit CNRDYIE is \nset in the SAI_xIM register, an interrupt is generated when the flag CNRDY is set. \nIt is asserted when the codec is not ready to communicate during the reception of the TAG 0 \n(slot0) of the AC’97 audio frame. In this case, no data are automatically stored into the FIFO \nsince the codec is not ready, until the TAG 0 indicates that the codec is ready. All the active \nslots defined in the SAI_xSLOTR register are captured when the codec is ready.\nTo clear the flag, bit CCNRDY in the SAI_xCLRFR register has to be set.\n29.13.5 \nWrong clock configuration in master mode (with NODIV = 0)\nWhen the audio block is master (MODE[1] = 0 in the SAI_xCR1 register) and if bit NODIV in \nthe SAI_xCR1 is clear, the flag WCKCFG is set if bit FRL[7:0] in the SAI_xFRCR is not set \nwith a proper value when the SAIxEN bit in the SAI_xCR1 register is set, in order to respect \nthis following rule:\nwhere n is in the range from 3 to 8.\nIf bit WCKCFGIE is set, an interrupt is generated when flag WCKCFG is set in the SAI_xSR \nregister. To clear the flag, set bit CWCKCFG bit in the SAI_xCLRFR register. \nWhen bit WCKCFG is set, the audio block is automatically disabled, clearing bit SAIxEN in \nthe SAI_xCR1 register via hardware. \nThe above formula is intended to guarantee that the number of MCLK pulses by bit clock is \nan even integer in the audio frame with a 50% duty cycle bit clock generation to guarantee \nthe good quality of the audio sounds or acquisitions. \nFRL[7,0]\n(\n)\n1\n+\n2n\n=\n" }, { "page_number": 951, "page_indices": { "start_index": 1854550, "end_index": 1856339 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 951 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.14 Interrupt sources", 951 ], [ 2, "29.15 Disabling the SAI", 951 ] ], "page_content": "RM0090 Rev 21\n951/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.14 \nInterrupt sources\nThe SAI has 7 possible interrupt sources as illustrated by Table 132.\n \nBelow are the SAI configuration steps to follow when an interrupt occurs:\n1.\nDisable SAI interrupt.\n2. \nConfigure SAI.\n3. \nConfigure SAI interrupt source.\n4. \nEnable SAI.\n29.15 \nDisabling the SAI\nThe audio block in the SAI can be disabled at any moment by clearing bit SAIxEN in the \nSAI_xCR1 register. All the frames that have already started are automatically completed \nbefore the total extinction of the SAI. Bit SAIxEN in the SAI_xCR1 register stays high until \nthe SAI is completely switched-off at the end of the current audio frame transfer.\nTable 132. Interrupt sources\nInterrupt\nsource\nInterru\npt\ngroup\nAudio block mode\nInterrupt enable\nInterrupt clear\nFREQ\nFREQ\nMaster or Slave\nReceiver or transmitter\nFREQIE in \nSAI_xIM register\nDepend on:\n- FIFO threshold setting \n(FLTH bits in SAI_CR2) \n- Communication direction \ntransmitter or receiver\nfor more details please refer \nto Internal FIFOs section\nOVRUDR ERROR Master or Slave\nReceiver or transmitter\nOVRUDRIE in \nSAI_xIM register\nCOVRUDR = 1 in \nSAI_xCLRFR register\nAFSDET\nERROR\nSlave\n(Not used in AC’97 \nmode)\nAFSDETIE in \nSAI_xIM register\nCAFSDET = 1 in \nSAI_xCLRFR register\nLFSDET\nERROR\nSlave\n(Not used in AC’97 \nmode)\nLFSDETIE in \nSAI_xIM register\nCLFSDET = 1 in \nSAI_xCLRFR register\nCNRDY\nERROR Slave\n(Only in AC’97 mode)\nCNRDYIE in \nSAI_xIM register\nCCNRDY = 1 in \nSAI_xCLRFR register\nMUTEDE\nT\nMUTE\nMaster or slave\nReceiver mode only\nMUTEDETIE in \nSAI_xIM register\nCMUTEDET = 1 in \nSAI_xCLRFR register\nWCKCFG ERROR\nMaster with NODIV = 0 \nin the SAI_xCR1 \nregister\nWCKCFGIE in \nSAI_xIM register\nCWCKCFG = 1 in \nSAI_xCLRFR register\n" }, { "page_number": 952, "page_indices": { "start_index": 1856339, "end_index": 1857747 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 952 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.16 SAI DMA interface", 952 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n952/1757\nRM0090 Rev 21\nIf there is an audio block in the SAI synchronous with the other one, the one which is the \nmaster must be disabled first.\n29.16 \nSAI DMA interface\nIn order to free the CPU and to optimize the bus bandwidth, each SAI audio block has an \nindependent DMA interface in order to read or to write into the SAI_xDR register (to hit the \ninternal FIFO). There is one DMA channel per audio block following basic DMA \nrequest/acknowledge protocol.\nTo configure the audio block to transfer through the DMA interface, set bit DMAEN in the \nSAI_xCR1 register. The DMA request is managed directly by the FIFO controller depend of \nFIFO threshold level (for more details please refer to Internal FIFOs section). DMA direction \nis linked to the SAI audio block configuration:\n•\nIf the audio block is a transmitter, the audio block’s FIFO controller outputs a DMA \nrequest to load the FIFO with data written in the SAI_xDR register.\n•\nIf the audio block is a receiver, the DMA request concerns read operations from the \nSAI_xDR register.\nBelow are the SAI configuration steps followed when DMA is used:\n1.\nConfigure SAI and FIFO Threshold level (in order to specify when the DMA request to \nbe launched)\n2. \nConfigure SAI DMA channel\n3. \nEnable DMA\n4. \nEnable SAI\nNote:\nBefore configuring the SAI block, the SAI DMA channel must be disabled. \n" }, { "page_number": 953, "page_indices": { "start_index": 1857747, "end_index": 1860323 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 953 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.17 SAI registers", 953 ], [ 3, "29.17.1 SAI x configuration register 1 (SAI_xCR1) where x is A or B", 953 ] ], "page_content": "RM0090 Rev 21\n953/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.17 \nSAI registers\n29.17.1 \nSAI x configuration register 1 (SAI_xCR1) where x is A or B\nAddress offset: Block A: 0x004\nAddress offset: Block B: 0x024\nReset value: 0x0000 0040\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nMCKDIV[3:0]\nNODIV\nRes.\nDMAEN SAIxEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOutDri\nv\nMONO\nSYNCEN[1:0]\nCKSTR\nLSBFIR\nST\nDS[2:0]\nRes.\nPRTCFG[1:0]\nMODE[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, always read as 0.\nBit 23:20 MCKDIV[3:0]: Master clock divider. These bits are set and cleared by software.\n0000: Divides by 1 the master clock input.\nOtherwise, The Master clock frequency is calculated accordingly to the following formula:\nMCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2)\nThese bits have no meaning when the audio block is slave.\nThey have to be configured when the audio block is disabled.\nBit 19 NODIV: No divider. This bit is set and cleared by software.\n0: Master Clock divider is enabled\n1: No divider used in the clock generator (in this case Master Clock Divider bit has no effect)\nBit 18 Reserved, always read as 0.\nBit 17 DMAEN: DMA enable. This bit is set and cleared by software.\n0: DMA is disabled\n1: DMA is enabled\nNote: In receiver mode, the bits MODE must be configured before setting bit DMAEN to avoid a DMA \nrequest since the audio block is transmitter after reset (default setting)\nBit 16 SAIxEN: Audio block enable where x is A or B. This bit is set by software. It is cleared by hardware, \nafter disabling it by software (writing the bit low), the audio is completely disabled (waiting for the end \nof the current frame).\n0: Audio block is disabled\n1: Audio block is enabled: this bit can be set only if it is at 0 during the write operation (means the \nSAI is completely disabled before being re-enabled).\nThis bit allows to control the state of the audio block. If it is disabled somewhere in an audio frame, \nthe ongoing transfer is complete and the cell is totally disabled at the end of this audio frame \ntransfer.\nNote: When SAIx block is configured as master mode, clock must be present on the input of the SAI \nbefore setting SAIxEN bit.\nBits 15:14 Reserved, always read as 0.\nBit 13 OUTDRIV: Output drive. This bit is set and cleared by software. \n0: Audio block output driven when SAIEN is set\n1: Audio block output driven immediately after the setting of this bit.\nNote: This bit has to be set before enabling the audio block but after the audio block configuration. \n" }, { "page_number": 954, "page_indices": { "start_index": 1860323, "end_index": 1862304 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 954 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.17 SAI registers", 953 ], [ 3, "29.17.1 SAI x configuration register 1 (SAI_xCR1) where x is A or B", 953 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n954/1757\nRM0090 Rev 21\nBit 12 MONO: Mono mode. This bit is set and cleared by software. \n0: Stereo mode\n1: Mono mode.\nThis bit has a meaning only when the number of slots is equal to 2.\nWhen the Mono mode is selected, the data of the slot 0 data is duplicated on the slot 1 when the \naudio block is a transmitter. In reception mode, the slot1 is discarded and only the data received \nfrom the slot 0 are stored.\nRefer to Section 29.12.2 for more details.\nBits 11:10 SYNCEN[1:0]: Synchronization enable. This bit is set and cleared by software. \n00: audio block is asynchronous.\n01: audio block is synchronous with the other internal audio block. In this case audio block should be \nconfigured in Slave mode\n10: Reserved.\n11: Not used\nThese bits have to be configured when the audio block is disabled.\nBit 9 CKSTR: Clock strobing edge. This bit is set and cleared by software. \n0: data strobing edge is falling edge of SCK\n1: data strobing edge is rising edge of SCK\nThis bit has to be configured when the audio block is disabled.\nBit 8 LSBFIRST: Least significant bit first. This bit is set and cleared by software. \n0: data is transferred with the MSB of the data first\n1: data is transferred with the LSB of the data first\nThis bit has to be configured when the audio block is disabled.\nThis bit has no meaning in AC’97 audio protocol since in AC’97 data is transferred with the MSB of \nthe data first.\nBits 7:5 DS[2:0]: Data size. These bits are set and cleared by software. \n000: Not used\n001: Not used\n010: 8-bit\n011: 10-bit\n100: 16-bit\n101: 20-bit\n110: 24-bit\n111: 32-bit\nWhen the companding mode is selected (bit COMP[1:0]), these DS[1:0] are ignored since the data \nsize is fixed to 8-bit mode by the algorithm itself.\nThese bits must be configured when the audio block is disabled.\nNote: When AC’97 mode is selected the data sizes that can be used are: 16-bit or 20-bit only, else \nSAI behavior is not guaranteed.\n" }, { "page_number": 955, "page_indices": { "start_index": 1862304, "end_index": 1863233 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 955 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.17 SAI registers", 953 ], [ 3, "29.17.1 SAI x configuration register 1 (SAI_xCR1) where x is A or B", 953 ] ], "page_content": "RM0090 Rev 21\n955/1757\nRM0090\nSerial audio interface (SAI)\n967\nBit 4 Reserved, always read as 0.\nBits 3:2 PRTCFG[1:0]: Protocol configuration. These bits are set and cleared by software. \n00: Free protocol\n01: Not used\n10: AC’97 protocol\n11: Not used\nFree protocol selection allows to use the powerful configuration of the audio block to address a \nspecific audio protocol (such as I2S, LSB/MSB justified, free protocol, PCM/DSP) setting most of the \nconfiguration register bits as well as frame configuration register.\nThese bits have to be configured when the audio block is disabled.\nBits 1:0 MODE[1:0]: Audio block mode. These bits are set and cleared by software. \n00: Master transmitter\n01: Master receiver\n10: Slave transmitter\n11: Slave receiver\nThese bits have to be configured when the audio block is disabled.\nNote: In Master transmitter mode the audio block starts to generate the FS and clocks\n" }, { "page_number": 956, "page_indices": { "start_index": 1863233, "end_index": 1865112 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 956 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.17 SAI registers", 953 ], [ 3, "29.17.2 SAI x configuration register 2 (SAI_xCR2) where x is A or B", 956 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n956/1757\nRM0090 Rev 21\n29.17.2 \nSAI x configuration register 2 (SAI_xCR2) where x is A or B\nAddress offset: Block A: 0x008\nAddress offset: Block B: 0x028\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCOMP[1:0]\nCPL\nMUTECNT[5:0]\nMUTE\nVAL\nMute\nTRIS\nFFLUS\nFTH\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, always read as 0\nBits 15:14 COMP[1:0]: Companding mode. These bits are set and cleared by software.\n00: No companding algorithm\n01: Reserved.\n10: µ-Law algorithm\n11: A-Law algorithm\nThe µ-Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of \ncomplement that is used depends on ComPLement bit.\nThe data expansion or data compression are determined by the state of bit MODE[0]. \nThe data compression is applied if the audio block is configured as a transmitter.\nThe data expansion is automatically applied when the audio block is configured as a receiver.\nRefer to Section 29.12.3 for more details.\nNote: Companding mode is applicable only when free protocol mode is selected.\nBit 13 CPL: Complement bit. This bit is set and cleared by software. \nIt defines the type of complement to be used for companding mode \n0: 1’s complement representation.\n1: 2’s complement representation.\nNote: This bit has effect only when the companding mode is µ-Law algorithm or A-Law algorithm.\nBits 12:7 MUTECNT[5:0]: Mute counter. These bits are set and cleared by software. \nThese bits are used only in reception mode. \nThe value set in these bits is compared to the number of consecutive mute frames detected in \nreception. When the number of mute frames is equal to this value, the flag MUTEDET is set and an \ninterrupt is generated if bit MUTEDETIE is set.\nRefer to Section 29.12.1 for more details.\n" }, { "page_number": 957, "page_indices": { "start_index": 1865112, "end_index": 1867318 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 957 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.17 SAI registers", 953 ], [ 3, "29.17.2 SAI x configuration register 2 (SAI_xCR2) where x is A or B", 956 ] ], "page_content": "RM0090 Rev 21\n957/1757\nRM0090\nSerial audio interface (SAI)\n967\nBit 6 MUTEVAL: Mute value. This bit is set and cleared by software.This bit has to be written before \nenabling the audio block: SAIxEN.\n0: Bit value 0 is sent during the MUTE mode. \n1: Last values are sent during the MUTE mode.\nThis bit has a meaning only when the audio block is a transmitter and when the number of slots is \nlower or equal to 2 and if the MUTE bit is set.\nIf more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, \nwhatever the value of this MUTEVAL bit.\nif the number of slot is lower or equal to 2 and MUTEVAL = 1, the mute value transmitted for each \nslot is the one sent during the previous frame.\nRefer to Section 29.12.1 for more details.\nBit 5 MUTE: Mute. This bit is set and cleared by software.\n0: No Mute mode. \n1: Mute mode enabled.\nThis bit has a meaning only when the audio block is a transmitter. The MUTE value is linked to the \nMUTEVAL value if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2.\nRefer to Section 29.12.1 for more details.\nBit 4 TRIS: Tristate management on data line. This bit is set and cleared by software. \n0: SD output line is still driven by the SAI when a slot is inactive.\n1: SD output line is released (HI-Z) at the end of the last data bit of the last active slot if the next one \nis inactive.\nThis bit has a meaning only if the audio block is configured to be a transmitter.\nThis bit should be configured when SAI is disabled.\nRefer to Section 29.12.4 for more details.\nBit 3 FFLUSH: FIFO flush. This bit is set by software. It is always read low. \n0: No FIFO flush. \n1: FIFO flush.\nWriting 1 to the bit triggers the FIFO Flush. All the internal FIFO pointers (read and write) are \ncleared.\nData still present in the FIFO are lost in such case (no more transmission or received data lost).\nThis bit should be configured when SAI is disabled.\nBefore flushing SAI, DMA stream/interruption must be disabled\nBits 2:0 FTH: FIFO threshold. This bit is set and cleared by software. \n000: FIFO empty \n001: ¼ FIFO\n010: ½ FIFO\n011: ¾ FIFO\n100: FIFO full\n101: Reserved\n110: Reserved\n111: Reserved\n" }, { "page_number": 958, "page_indices": { "start_index": 1867318, "end_index": 1869184 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 958 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.17 SAI registers", 953 ], [ 3, "29.17.3 SAI x frame configuration register (SAI_XFRCR) where x is A or B", 958 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n958/1757\nRM0090 Rev 21\n29.17.3 \nSAI x frame configuration register (SAI_XFRCR) where x is A or B\nAddress offset: Block A: 0x00C\nAddress offset: Block B: 0x02C\nReset value: 0x0000 0007\nNote:\nThis register has no meaning in AC’97 audio protocol\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nFSOFF\nFSPOL\nFSDEF\nrw \nrw\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nFSALL[6:0]\nFRL[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:19 Reserved, always read as 0.\nBit 18 FSOFF: Frame synchronization offset. This bit is set and cleared by software.\n0: FS is asserted on the first bit of the slot 0.\n1: FS is asserted one bit before the first bit of the slot 0.\nThis bit has no meaning and is not used in AC’97 audio block configuration.\nThis bit must be configured when the audio block is disabled.\nBit 17 FSPOL: Frame synchronization polarity. This bit is set and cleared by software\n0: FS is active low (falling edge)\n1: FS is active high (rising edge)\nThis bit is used to configure the level of the start of frame on the FS signal.\nThis bit has no meaning and is not used in AC’97 audio block configuration.\nThis bit must be configured when the audio block is disabled.\nBit 16 FSDEF: Frame synchronization definition. This bit is set and cleared by software.\n0: FS signal is a start frame signal\n1: FS signal is a start of frame signal + channel side identification\nWhen the bit is set, the number of slots defined in the SAI_ASLOTR register has to be even. It \nmeans that there is half of this number of slots dedicated for the left channel and the other slots for \nthe right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...)\nThis bit has no meaning and is not used in AC’97 audio block configuration.\nThis bit must be configured when the audio block is disabled.\n" }, { "page_number": 959, "page_indices": { "start_index": 1869184, "end_index": 1870745 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 959 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.17 SAI registers", 953 ], [ 3, "29.17.3 SAI x frame configuration register (SAI_XFRCR) where x is A or B", 958 ] ], "page_content": "RM0090 Rev 21\n959/1757\nRM0090\nSerial audio interface (SAI)\n967\nBit 15 Reserved, always read as 0.\nBits 14:8 FSALL[6:0]: Frame synchronization active level length. These bits are set and cleared by software\nThe value set in these bits specifies the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of \nthe active level of the FS signal in the audio frame \nThese bits have no meaning and are not used in AC’97 audio block configuration.\nThese bits must be configured when the audio block is disabled.\nBits 7:0 FRL[7:0]: Frame length. These bits are set and cleared by software.\nThey define the length of the audio frame. More precisely, these bits define the number of SCK \nclocks for each audio frame. \nThe number of bits in the frame is equal to FRL[7:0] + 1. \nThe minimum number of bits to transfer in an audio frame has to be equal to 8 or else the audio \nblock has unexpected behavior. This is the case when the data size is 8-bit and only one slot 0 is \ndefined in NBSLOT[4:0] in the SAI_ASLOTR register (NBSLOT[3:0] = 0000).\nIn master mode, if the master clock MCLK_x pin is declared as an output, the frame length should \nbe aligned to a number equal to a power of 2, from 8 to 256 in order to keep in an audio frame, an \ninteger number of MCLK pulses by bit clock for correct operation for external DAC/ADC inside the \ndecoders.\nThe Frame length should be even.\nThese bits have no meaning and are not used in AC’97 audio block configuration.\nNote: The FRL[7:0] bitfield must be configured when the audio block is disabled. \n" }, { "page_number": 960, "page_indices": { "start_index": 1870745, "end_index": 1873221 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 960 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.17 SAI registers", 953 ], [ 3, "29.17.4 SAI x slot register (SAI_xSLOTR) where x is A or B", 960 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n960/1757\nRM0090 Rev 21\n29.17.4 \nSAI x slot register (SAI_xSLOTR) where x is A or B\nAddress offset: Block A: 0x010\nAddress offset: Block B: 0x030\nReset value: 0x0000 0000\nNote:\nThis register has no meaning in AC’97 audio protocol\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nSLOTEN[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNBSLOT[3:0]\nSLOTSZ[1:0]\nRes\nFBOFF[4:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 SLOTEN[15:0]: Slot enable. These bits are set and cleared by software.\nEach bit of the SLOTEN bits identify a slot position from 0 to 15 (maximum 16 slots)\n0: Inactive slot.\n1: Active slot.\nThese bits must be set when the audio block is disabled.\nThey are ignored in AC’97 mode.\nBits 15:12 Reserved, always read as 0.\nBits 11:8 NBSLOT[3:0]: Number of slots in an audio frame. These bits are set and cleared by software.\nThe value set in these bits register represents the number of slots + 1 in the audio frame (including \nthe number of inactive slots). The maximum number of slots is 16.\nThe number of slots should be even if bit FSDEF in the SAI_AFRCR register is set.\nIf the size is greater than the data size, the remaining bits are forced to 0 if bit TRIS in the SAI_xCR1 \nregister is clear, otherwise they are forced to 0 if the next slot is active or the SD line is forced to HI-\nZ if the next slot is inactive and bit TRIS = 1.\nThese bits must be set when the audio block is disabled.\nThey are ignored in AC’97 omode.\nBits 7:6 SLOTSZ[1:0]: Slot size\nThis bits is set and cleared by software.\n00: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_ACR1 register).\n01: 16-bit\n10: 32-bit\n11: Reserved\nThe slot size must be greater or equal to the data size. If this condition is not respected, the behavior \nof the SAI is undetermined.\nThese bits must be set when the audio block is disabled.\nThey are ignored in AC’97 mode.\nBit 1 Reserved, always read as 0.\nBits 4:0 FBOFF[4:0]: First bit offset \nThese bits are set and cleared by software.\nThe value set in these bits represents the position of the first data transfer bit in the slot. It represents \nan offset value. During this offset phase 0 value are sent on the data line for transmission mode. For \nreception mode, the received bit are discarded during the offset phase.\nThese bits must be set when the audio block is disabled.\nThey are ignored in AC’97 mode.\n" }, { "page_number": 961, "page_indices": { "start_index": 1873221, "end_index": 1875299 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 961 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.17 SAI registers", 953 ], [ 3, "29.17.5 SAI x interrupt mask register (SAI_xIM) where x is A or B", 961 ] ], "page_content": "RM0090 Rev 21\n961/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.17.5 \nSAI x interrupt mask register (SAI_xIM) where x is A or B\nAddress offset: block A: 0x014\nAddress offset: block B: 0x034\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLFSDETI\nE\nAFSDET\nIE\nCNRDY\nIE\nFREQI\nE\nWCKC\nFGIE\nMUT\nEDET\nIE\nOVRU\nDRIE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:7 Reserved, always read as 0.\nBit 6 LFSDETIE: Late frame synchronization detection interrupt enable. This bit is set and cleared by \nsoftware.\n0: Interrupt is disabled\n1: Interrupt is enabled\nWhen this bit is set, an interrupt is generated if the LFSDET bit is set in the SAI_ASR register.\nThis bit has no meaning in AC’97 mode. It has no meaning also if the audio block is master.\nBit 5 AFSDETIE: Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by \nsoftware.\n0: Interrupt is disabled\n1: Interrupt is enabled\nWhen this bit is set, an interrupt is generated if the AFSDET bit in the SAI_ASR register is set.\nThis bit has no meaning in AC’97 mode. It has no meaning also if the audio block is master.\nBit 4 CNRDYIE: Codec not ready interrupt enable (ac’97). This bit is set and cleared by software.\n0: Interrupt is disabled\n1: Interrupt is enabled\nWhen the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC’97 frame if the \ncodec connected on this line is ready or not. If not, the flag CNRDY in the SAI_ASR register is set \nand an interruption is generated.\nThis bit has a meaning only if the AC97 mode is selected (bit PRTCFG[1:0]) and the audio block is a \nreceiver.\nBit 3 FREQIE: FIFO request interrupt enable. This bit is set and cleared by software.\n0: Interrupt is disabled\n1: Interrupt is enabled\nWhen this bit is set, an interrupt is generated if the FREQ bit in the SAI_ASR register is set.\nIn receiver mode, the bit MODE must be configured before setting bit FREQIE to avoid a parasitic \ninterruption since the audio block is a transmitter (default setting).\n" }, { "page_number": 962, "page_indices": { "start_index": 1875299, "end_index": 1876405 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 962 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.17 SAI registers", 953 ], [ 3, "29.17.5 SAI x interrupt mask register (SAI_xIM) where x is A or B", 961 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n962/1757\nRM0090 Rev 21\nBit 2 WCKCFGIE: Wrong clock configuration interrupt enable. This bit is set and cleared by software.\n0: Interrupt is disabled\n1: Interrupt is enabled\nThis bit is considered only if the audio block is configured as master (MODE[1] = 0 in the SAI_ACR1 \nregister) and bit NODIV = 0 in the SAI_xCR1 register.\nIt generates an interrupt if the flag WCKCFG in the SAI_ASR register is set.\nNote: This bit is used only in free protocol mode and has no meaning for other modes.\nBit 1 MUTEDETIE: Mute detection interrupt enable. This bit is set and cleared by software.\n0: Interrupt is disabled\n1: Interrupt is enabled\nWhen this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_ASR register is set.\nThis bit has a meaning only if the audio block is configured in receiver mode.\nBit 0 OVRUDRIE: Overrun/underrun interrupt enable. This bit is set and cleared by software.\n0: Interrupt is disabled\n1: Interrupt is enabled\nWhen this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_ASR register is set.\n" }, { "page_number": 963, "page_indices": { "start_index": 1876405, "end_index": 1878279 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 963 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.17 SAI registers", 953 ], [ 3, "29.17.6 SAI x status register (SAI_xSR) where x is A or B", 963 ] ], "page_content": "RM0090 Rev 21\n963/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.17.6 \nSAI x status register (SAI_xSR) where x is A or B\nAddress offset: block A: 0x018\nAddress offset: block B: 0x038\nReset value: 0x0000 0008\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nFLTH\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLFSDET AFSDET\nCNRDY\nFREQ\nWCKCFG\nMUTED\nET\nOVRUDR\nr\nr\nr\nr\nr\nr\nr\nBits 31:19 Reserved, always read as 0.\nBits 18:16 FLTH: FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by \nhardware and its setting depends on SAI block configuration (transmitter or receiver mode). \nIf SAI block is configured as transmitter:\n000: FIFO_empty\n001: FIFO <= ¼ but not empty\n010: ¼ < FIFO <= ½\n011: ½ < FIFO <= ¾\n100: ¾ < FIFO but not full\n101: FIFO full\nIf SAI block is configured as receiver:\n000: FIFO_empty\n001: FIFO < ¼ but not empty\n010: ¼ <= FIFO < ½\n011: ½ =< FIFO < ¾\n100: ¾ =< FIFO but not full\n101: FIFO full\nBits 15:7 Reserved, always read as 0.\nBit 6 LFSDET: Late frame synchronization detection. This bit is read only.\n0: No error.\n1: Frame synchronization signal is not present at the right time. \nThis flag can be set only if the audio block is configured in Slave mode.\nIt is not used in AC’97 mode.\nIt may generate an interrupt if bit LFSDETIE in the SAI_xIM register is set.\nThis flag is cleared when the software sets bit CLFSDET in the SAI_xCLRFR register\nBit 5 AFSDET: Anticipated frame synchronization detection. This bit is read only.\n0: No error.\n1: Frame synchronization signal is detected earlier than expected. \nThis flag can be set only if the audio block is configured in Slave mode.\nIt is not used in AC’97.\nIt may generate an interrupt if bit AFSDETIE in the SAI_xIM register is set.\nThis flag is cleared when the software sets bit CAFSDET in the SAI_xCLRFR register\n" }, { "page_number": 964, "page_indices": { "start_index": 1878279, "end_index": 1880835 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 964 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.17 SAI registers", 953 ], [ 3, "29.17.6 SAI x status register (SAI_xSR) where x is A or B", 963 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n964/1757\nRM0090 Rev 21\n \nBit 4 CNRDY: Codec not ready. This bit is read only. \n0: The external AC’97 codec is ready \n1: The external AC’97 codec is not ready\nThis bit is used only when the AC’97 audio protocol is selected in the SAI_xCR1 register and is \nconfigured in receiver mode.\nIt may generate an interrupt if bit CNRDYIE in the SAI_xIM register is set.\nThis flag is cleared when the software sets bit CCNRDY in the SAI_xCLRFR register\nBit 3 FREQ: FIFO request. This bit is read only.\n0: No FIFO request.\n1: FIFO request to read or to write the SAI_xDR.\nThe request depends on the audio block configuration. \nIf configured in transmission, the FIFO request concerns a write request operation in the SAI_xDR. \nIf configured in reception, the FIFO request concerns a read request operation from the SAI_xDR.\nThis flag can generate an interrupt if bit FREQIE in the SAI_xIM register is set.\nBit 2 WCKCFG: Wrong clock configuration flag. This bit is read only. \n0: The clock configuration is correct\n1: The clock configuration does not respect the rule concerning the frame length specification \ndefined in Section 29.7 (configuration of FRL[7:0] bit in the SAI_x FRCR register)\nThis bit is used only when the audio block is master (MODE[1] = 0 in the SAI_xCR1 register) and \nwhen NODIV = 0 in the SAI_xCR1 register. \nIt may generate an interrupt if bit WCKCFGIE in the SAI_xIM register is set.\nThis flag is cleared when the software sets bit CWCKCFG in the SAI_xCLRFR register\nBit 1 MUTEDET: Mute detection. This bit is read only.\n0: No MUTE detection on the SD input line\n1: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio \nframe\nThis flag is set if consecutive 0 values are received in each slot of an audio frame and for a \nconsecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register).\nIt may generate an interrupt if bit MUTEDETIE in the SAI_xIM register is set.\nThis flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register.\nBit 0 OVRUDR: Overrun / underrun. This bit is read only.\n0: No overrun/underrun error.\n1: Overrun/underrun error detection.\nThe overrun condition can occur only when the audio block is configured in reception.\nThe underrun condition can occur only when the audio block is configured in transmission.\nIt may generate an interrupt if bit OVRUDRIE in the SAI_xIM register is set.\nThis flag is cleared when the software set bit COVRUDR bit in the SAI_xCLRFR register.\n" }, { "page_number": 965, "page_indices": { "start_index": 1880835, "end_index": 1882759 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 965 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.17 SAI registers", 953 ], [ 3, "29.17.7 SAI x clear flag register (SAI_xCLRFR) where X is A or B", 965 ] ], "page_content": "RM0090 Rev 21\n965/1757\nRM0090\nSerial audio interface (SAI)\n967\n29.17.7 \nSAI x clear flag register (SAI_xCLRFR) where X is A or B\nAddress offset: block A: 0x01C\nAddress offset: block B: 0x03C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCLFSDET\nCAFSDE\nT\nCCNRDY\nReserved\nCWCKCFG CMUTE\nDET\nCOVRUD\nR\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:7 Reserved, always read as 0.\nBit 6 CLFSDET: Clear late frame synchronization detection flag. This bit is write only.\nWriting 1 in this bit clears the flag LFSDET in the SAI_xSR register.\nIt is not used in AC’97.\nReading this bit always returns the value 0. \nBit 5 .CAFSDET: Clear anticipated frame synchronization detection flag. This bit is write only.\nWriting 1 in this bit clears the flag AFSDET in the SAI_xSR register.\nIt is not used in AC’97.\nReading this bit always returns the value 0. \nBit 4 CCNRDY: Clear codec not ready flag. This bit is write only.\nWriting 1 in this bit clears the flag CNRDY in the SAI_xSR register.\nThis bit is used only when the AC’97 audio protocol is selected in the SAI_xCR1 register.\nReading this bit always returns the value 0. \nBit 3 Reserved, always read as 0.\nBit 2 CWCKCFG: Clear wrong clock configuration flag. This bit is write only.\nWriting 1 in this bit clears the flag WCKCFG in the SAI_xSR register.\nThis bit is used only when the audio block is set as master (MODE[1] = 0 in the SAI_ACR1 register) \nand bit NODIV = 0 in the SAI_xCR1 register.\nReading this bit always returns the value 0. \nBit 1 CMUTEDET: Mute detection flag. This bit is write only.\nWriting 1 in this bit clears the flag MUTEDET in the SAI_xSR register.\nReading this bit always returns the value 0. \nBit 0 COVRUDR: Clear overrun / underrun. This bit is write only.\nWriting 1 in this bit clears the flag OVRUDR in the SAI_xSR register.\nReading this bit always returns the value 0.\n" }, { "page_number": 966, "page_indices": { "start_index": 1882759, "end_index": 1884550 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 966 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.17 SAI registers", 953 ], [ 3, "29.17.8 SAI x data register (SAI_xDR) where x is A or B", 966 ], [ 3, "29.17.9 SAI register map", 966 ] ], "page_content": "Serial audio interface (SAI)\nRM0090\n966/1757\nRM0090 Rev 21\n29.17.8 \nSAI x data register (SAI_xDR) where x is A or B\nAddress offset: block A: 0x020\nAddress offset: block B: 0x040\nReset value: 0x0000 0000\n \n \n29.17.9 \nSAI register map\nThe following table summarizes the SAI registers.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATA[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATA[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 DATA[31:0]: Data \nA write into this register has the effect of loading the FIFO if the FIFO is not full.\nA read from this register has to effect of draining-up the FIFO if the FIFO is not empty.\nTable 133. SAI register map and reset values\nOffset\nRegister \nand reset \nvalue\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x0004\nor\n0x0024\nSAI_xCR1\nReserved\nMCKDIV[3:0]\nNODIV\nRes.\nDMAEN\nSAIxEN\nReserved.\nOutDri\nMONO\nSYNCE\nN[1:0]\nCKSTR\nLSBFIRST\nDS[2:0]\nRes.\nPRTCF\nG[1:0]\nMODE[\n1:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0x0008\nor 0x0028\nSAI_xCR2\nReserved\nCOMP[\n1:0]\nCPL\nMUTECN[5:0]\nMUTE VAL\nMUTE\nTRIS\nFFLUS\nFTH\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x000Cor \n0x002C\nSAI_xFRCR\nReserved\nFSOFF\nFSPOL\nFSDEF\nReserved\nFSALL[6:0]\nFRL[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n0x0010 or\n0x0030\nSAI_xSLOTR\nSLOTEN[15:0]\nReserved\nNBSLOT[3:0] SLOTS\nZ[1:0}\nReserved\nFBOFF[4:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0014\nor 0x0034\nSAI_xIM\nReserved\nLFSDET\nAFSDETIE\nCNRDYIE\nFREQIE\nWCKCFG\nMUTEDET\nOVRUDRIE\nReset value\n0\n0\n0\n0\n0\n0\n0\n0x0018\nor \n0x0038\nSAI_xSR\nReserved\nFLVL[2:0]\nReserved\nLFSDET\nAFSDET\nCNRDY\nFREQ\nWCKCFG\nMUTEDET\nOVRUDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n" }, { "page_number": 967, "page_indices": { "start_index": 1884550, "end_index": 1885104 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 967 }, "toc_details": [ [ 1, "29 Serial audio interface (SAI)", 929 ], [ 2, "29.17 SAI registers", 953 ], [ 3, "29.17.9 SAI register map", 966 ] ], "page_content": "RM0090 Rev 21\n967/1757\nRM0090\nSerial audio interface (SAI)\n967\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x001C\nor 0x003C\nSAI_xCLRFR\nReserved\nLFSDET\nCAFSDET\nCNRDY\nRes.\nWCKCFG\nMUTEDET\nOVRUDR\nReset value\n0\n0\n0\n0\n0\n0\n0x0020\nor 0x0040\nSAI_xDR\nDATA[31:0] \nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 133. SAI register map and reset values (continued)\nOffset\nRegister \nand reset \nvalue\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 968, "page_indices": { "start_index": 1885104, "end_index": 1887339 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 968 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.1 USART introduction", 968 ], [ 2, "30.2 USART main features", 968 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n968/1757\nRM0090 Rev 21\n30 \nUniversal synchronous asynchronous receiver\ntransmitter (USART)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n30.1 \nUSART introduction\nThe universal synchronous asynchronous receiver transmitter (USART) offers a flexible \nmeans of full-duplex data exchange with external equipment requiring an industry standard \nNRZ asynchronous serial data format. The USART offers a very wide range of baud rates \nusing a fractional baud rate generator.\nIt supports synchronous one-way communication and half-duplex single wire \ncommunication. It also supports the LIN (local interconnection network), Smartcard Protocol \nand IrDA (infrared data association) SIR ENDEC specifications, and modem operations \n(CTS/RTS). It allows multiprocessor communication.\nHigh speed data communication is possible by using the DMA for multibuffer configuration.\n30.2 \nUSART main features\n•\nFull duplex, asynchronous communications\n•\nNRZ standard format (Mark/Space)\n•\nConfigurable oversampling method by 16 or by 8 to give flexibility between speed and \nclock tolerance\n•\nFractional baud rate generator systems\n–\nCommon programmable transmit and receive baud rate (refer to the datasheets \nfor the value of the baud rate at the maximum APB frequency.\n•\nProgrammable data word length (8 or 9 bits)\n•\nConfigurable stop bits - support for 1 or 2 stop bits\n•\nLIN Master Synchronous Break send capability and LIN slave break detection \ncapability\n–\n13-bit break generation and 10/11 bit break detection when USART is hardware \nconfigured for LIN\n•\nTransmitter clock output for synchronous transmission\n•\nIrDA SIR encoder decoder\n–\nSupport for 3/16 bit duration for normal mode\n•\nSmartcard emulation capability\n–\nThe Smartcard interface supports the asynchronous protocol Smartcards as \ndefined in the ISO 7816-3 standards\n–\n0.5, 1.5 stop bits for Smartcard operation\n•\nSingle-wire half-duplex communication\n•\nConfigurable multibuffer communication using DMA (direct memory access)\n–\nBuffering of received/transmitted bytes in reserved SRAM using centralized DMA\n•\nSeparate enable bits for transmitter and receiver\n" }, { "page_number": 969, "page_indices": { "start_index": 1887339, "end_index": 1888954 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 969 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ] ], "page_content": "RM0090 Rev 21\n969/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n•\nTransfer detection flags:\n–\nReceive buffer full\n–\nTransmit buffer empty\n–\nEnd of transmission flags\n•\nParity control:\n–\nTransmits parity bit\n–\nChecks parity of received data byte\n•\nFour error detection flags:\n–\nOverrun error\n–\nNoise detection\n–\nFrame error\n–\nParity error\n•\nTen interrupt sources with flags:\n–\nCTS changes\n–\nLIN break detection\n–\nTransmit data register empty\n–\nTransmission complete\n–\nReceive data register full\n–\nIdle line received\n–\nOverrun error\n–\nFraming error \n–\nNoise error\n–\nParity error\n•\nMultiprocessor communication - enter into mute mode if address match does not occur\n•\nWake up from mute mode (by idle line detection or address mark detection)\n•\nTwo receiver wake-up modes: Address bit (MSB, 9th bit), Idle line\n30.3 \nUSART functional description\nThe interface is externally connected to another device by three pins (see Figure 296). Any \nUSART bidirectional communication requires a minimum of two pins: Receive Data In (RX) \nand Transmit Data Out (TX):\nRX: Receive Data Input is the serial data input. Oversampling techniques are used for data \nrecovery by discriminating between valid incoming data and noise.\nTX: Transmit Data Output. When the transmitter is disabled, the output pin returns to its I/O \nport configuration. When the transmitter is enabled and nothing is to be transmitted, the TX \npin is at high level. In single-wire and smartcard modes, this I/O is used to transmit and \nreceive the data (at USART level, data are then received on SW_RX).\n" }, { "page_number": 970, "page_indices": { "start_index": 1888954, "end_index": 1890563 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 970 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n970/1757\nRM0090 Rev 21\nThrough these pins, serial data is transmitted and received in normal USART mode as \nframes comprising: \n•\nAn Idle Line prior to transmission or reception\n•\nA start bit\n•\nA data word (8 or 9 bits) least significant bit first\n•\n0.5,1, 1.5, 2 Stop bits indicating that the frame is complete\n•\nThis interface uses a fractional baud rate generator - with a 12-bit mantissa and 4-bit \nfraction\n•\nA status register (USART_SR)\n•\nData Register (USART_DR)\n•\nA baud rate register (USART_BRR) - 12-bit mantissa and 4-bit fraction.\n•\nA Guardtime Register (USART_GTPR) in case of Smartcard mode.\nRefer to Section 30.6: USART registers on page 1010 for the definitions of each bit. \nThe following pin is required to interface in synchronous mode:\n•\nCK: Transmitter clock output. This pin outputs the transmitter data clock for \nsynchronous transmission corresponding to SPI master mode (no clock pulses on start \nbit and stop bit, and a software option to send a clock pulse on the last data bit). In \nparallel data can be received synchronously on RX. This can be used to control \nperipherals that have shift registers (e.g. LCD drivers). The clock phase and polarity \nare software programmable. In smartcard mode, CK can provide the clock to the \nsmartcard. \nThe following pins are required in Hardware flow control mode:\n•\nCTS: Clear To Send blocks the data transmission at the end of the current transfer \nwhen high\n•\nRTS: Request to send indicates that the USART is ready to receive a data (when low).\n" }, { "page_number": 971, "page_indices": { "start_index": 1890563, "end_index": 1891583 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 971 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ] ], "page_content": "RM0090 Rev 21\n971/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nFigure 296. USART block diagram\nWakeup\nunit\nReceiver\ncontrol\nSR\nTransmit\ncontrol\nTXE TC RXNE IDLE ORE NF\nFE\nUSART\ncontrol\ninterrupt\nCR1\nM\nWAKE\nReceive data register (RDR)\nReceive Shift Register\nRead\nTransmit data register (TDR)\nTransmit Shift Register\nWrite\nSW_RX\nTX\n(Data register) DR\nTransmitter\n clock\nReceiver \nclock\nReceiver rate\nTransmitter rate\n \nfPCLKx(x=1,2)\n control\ncontrol\n/ [8 x (2 - OVER8)]\nConventional baud rate generator\nSBK\nRWU\nRE\nTE\nIDLE\nRXNE\nTCIE\nTXEIE\nCR1\nUE\nPCE\nPS\nPEIE\nPE\nPWDATA\nIRLP\nSCEN\nIREN\nDMAR\nDMAT\nUSART Address\nCR2\nCR3\nIrDA\nSIR\nENDEC\nblock\nLINE\nCKEN\nCPOL CPHA LBCL\nSCLK control\nCK\nCR2\nGT\nSTOP[1:0]\nNACK\nDIV_Mantissa\n15\n0\nRE\nUSART_BRR\n/USARTDIV\nTE\nHD\n(CPU or DMA)\n(CPU or DMA)\nPRDATA\nHardware\nflow\ncontroller\nCTS LBD\nRX\nIRDA_OUT\nIRDA_IN\nRTS\nCTS\nGTPR\nPSC\nIE\nIE\nDIV_Fraction\n4\nUSARTDIV = DIV_Mantissa + (DIV_Fraction / 8 × (2 – OVER8))\nSAMPLING\nCR1\nOVER8\nDIVIDER\nai16099b\n" }, { "page_number": 972, "page_indices": { "start_index": 1891583, "end_index": 1893147 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 972 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.1 USART character description", 972 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n972/1757\nRM0090 Rev 21\n30.3.1 \nUSART character description\nWord length may be selected as being either 8 or 9 bits by programming the M bit in the \nUSART_CR1 register (see Figure 297).\nThe TX pin is in low state during the start bit. It is in high state during the stop bit. \nAn Idle character is interpreted as an entire frame of “1”s followed by the start bit of the \nnext frame which contains data (The number of “1” ‘s includes the number of stop bits).\nA Break character is interpreted on receiving “0”s for a frame period. At the end of the \nbreak frame the transmitter inserts either 1 or 2 stop bits (logic “1” bit) to acknowledge the \nstart bit.\nTransmission and reception are driven by a common baud rate generator, the clock for each \nis generated when the enable bit is set respectively for the transmitter and receiver.\nThe details of each block is given below.\nFigure 297. Word length programming\nMS19822V2\nBit0\nBit1\nBit2\nBit3\nBit4\nBit5\nBit6\nBit7\nBit8\nStart\nbit\nStop\nbit\nNext\nStart \nbit\nIdle frame\n9-bit word length (M bit is set), 1 Stop bit\nPossible\nParity\nbit\nBreak frame\nData frame\nNext data frame\nClock\n** LBCL bit controls last data clock pulse\n**\nStart\nbit\nStart\nbit\nStop\nbit\nBit0\nBit1\nBit2\nBit3\nBit4\nBit5\nBit6\nBit7\nStart\nbit\nStop\nbit\nNext\nStart \nbit\nIdle frame\n8-bit word length (M bit is reset), 1 Stop bit\nPossible\nParity\nbit\nBreak frame\nData frame\nNext data frame\nClock\n** LBCL bit controls last data clock pulse\n**\nStart\nbit\nStart\nbit\nStop\nbit\n" }, { "page_number": 973, "page_indices": { "start_index": 1893147, "end_index": 1895062 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 973 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.2 Transmitter", 973 ], [ 4, "Character transmission", 973 ], [ 4, "Configurable stop bits", 973 ] ], "page_content": "RM0090 Rev 21\n973/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n30.3.2 \nTransmitter\nThe transmitter can send data words of either 8 or 9 bits depending on the M bit status. \nWhen the transmit enable bit (TE) is set, the data in the transmit shift register is output on \nthe TX pin and the corresponding clock pulses are output on the CK pin.\nCharacter transmission\nDuring an USART transmission, data shifts out least significant bit first on the TX pin. In this \nmode, the USART_DR register consists of a buffer (TDR) between the internal bus and the \ntransmit shift register (see Figure 296).\nEvery character is preceded by a start bit which is a logic level low for one bit period. The \ncharacter is terminated by a configurable number of stop bits.\nThe following stop bits are supported by USART: 0.5, 1, 1.5 and 2 stop bits.\nNote:\nThe TE bit should not be reset during transmission of data. Resetting the TE bit during the \ntransmission corrupts the data on the TX pin as the baud rate counters get frozen. The \ncurrent data being transmitted are lost. \nAn idle frame is sent after the TE bit is enabled.\nConfigurable stop bits\nThe number of stop bits to be transmitted with every character can be programmed in \nControl register 2, bits 13,12.\n•\n1 stop bit: This is the default value of number of stop bits.\n•\n2 Stop bits: This is supported by normal USART, single-wire and modem modes.\n•\n0.5 stop bit: To be used when receiving data in Smartcard mode.\n•\n1.5 stop bits: To be used when transmitting and receiving data in Smartcard mode.\nAn idle frame transmission includes the stop bits.\nA break transmission is 10 low bits followed by the configured number of stop bits (when m \n= 0) and 11 low bits followed by the configured number of stop bits (when m = 1). It is not \npossible to transmit long breaks (break of length greater than 10/11 low bits).\n" }, { "page_number": 974, "page_indices": { "start_index": 1895062, "end_index": 1897243 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 974 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.2 Transmitter", 973 ], [ 4, "Single byte communication", 974 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n974/1757\nRM0090 Rev 21\nFigure 298. Configurable stop bits \nProcedure:\n1.\nEnable the USART by writing the UE bit in USART_CR1 register to 1.\n2. \nProgram the M bit in USART_CR1 to define the word length.\n3. \nProgram the number of stop bits in USART_CR2.\n4. \nSelect DMA enable (DMAT) in USART_CR3 if Multi buffer Communication is to take \nplace. Configure the DMA register as explained in multibuffer communication.\n5. \nSelect the desired baud rate using the USART_BRR register.\n6. \nSet the TE bit in USART_CR1 to send an idle frame as first transmission.\n7. \nWrite the data to send in the USART_DR register (this clears the TXE bit). Repeat this \nfor each data to be transmitted in case of single buffer.\n8. \nAfter writing the last data into the USART_DR register, wait until TC=1. This indicates \nthat the transmission of the last frame is complete. This is required for instance when \nthe USART is disabled or enters the Halt mode to avoid corrupting the last \ntransmission.\nSingle byte communication\nClearing the TXE bit is always performed by a write to the data register.\nThe TXE bit is set by hardware and it indicates:\n•\nThe data has been moved from TDR to the shift register and the data transmission has \nstarted. \n•\nThe TDR register is empty.\n•\nThe next data can be written in the USART_DR register without overwriting the \nprevious data.\nThis flag generates an interrupt if the TXEIE bit is set.\nMSv42088V1\nBit0\nBit1\nBit2\nBit3\nBit4\nBit5\nBit6\nBit7\nStart\nBit\nStop\nbit\nNext\nstart \n8-bit Word length (M bit is reset)\nPossible\nparity \nbit\nData frame\nNext data frame\n****\n** LBCL bit controls last data clock pulse\nCLOCK\n**\nBit0\nBit1\nBit2\nBit3\nBit4\nBit5\nBit6\nBit7\nStart\nBit\n2 Stop Bits \nNext\nStart \nBit\nPossible\nparity \nbit\nData frame\nNext data frame\nNext data frame\nBit0\nBit1\nBit2\nBit3\nBit4\nBit5\nBit6\nBit7\nStart\nBit\nNext\nstart \nbit\nPossible\nParity \nBit\nData frame\nNext data frame\n1 1/2 stop bits \na) 1 Stop Bit\nb) 1 1/2 stop Bits\nc) 2 Stop Bits\nBit0\nBit1\nBit2\nBit3\nBit4\nBit5\nBit6\nBit7\nStart\nBit\n1/2 Stop Bit \nNext\nStart \nBit\nPossible\nparity \nbit\nData frame\nd) 1/2 Stop Bit\n" }, { "page_number": 975, "page_indices": { "start_index": 1897243, "end_index": 1899690 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 975 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.2 Transmitter", 973 ], [ 4, "Break characters", 975 ] ], "page_content": "RM0090 Rev 21\n975/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nWhen a transmission is taking place, a write instruction to the USART_DR register stores \nthe data in the TDR register and which is copied in the shift register at the end of the current \ntransmission.\nWhen no transmission is taking place, a write instruction to the USART_DR register places \nthe data directly in the shift register, the data transmission starts, and the TXE bit is \nimmediately set.\nIf a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An \ninterrupt is generated if the TCIE bit is set in the USART_CR1 register.\nAfter writing the last data into the USART_DR register, it is mandatory to wait for TC=1 \nbefore disabling the USART or causing the microcontroller to enter the low-power mode \n(see Figure 299: TC/TXE behavior when transmitting).\nThe TC bit is cleared by the following software sequence:\n1.\nA read from the USART_SR register\n2. \nA write to the USART_DR register\nNote:\nThe TC bit can also be cleared by writing a ‘0 to it. This clearing sequence is recommended \nonly for Multibuffer communication.\nFigure 299. TC/TXE behavior when transmitting\nBreak characters\nSetting the SBK bit transmits a break character. The break frame length depends on the M \nbit (see Figure 297).\nIf the SBK bit is set to ‘1 a break character is sent on the TX line after completing the current \ncharacter transmission. This bit is reset by hardware when the break character is completed \n(during the stop bit of the break character). The USART inserts a logic 1 bit at the end of the \nlast break frame to guarantee the recognition of the start bit of the next frame.\nNote:\nIf the software resets the SBK bit before the commencement of break transmission, the \nbreak character is not transmitted. For two consecutive breaks, the SBK bit should be set \nafter the stop bit of the previous break.\nSoftware wait until TC=1\nSoftware \nenables the \nUSART\nSoftware waits until TXE=1 \nand writes F2 into DR\nIdle preamble\nFrame 1\nFrame 2\nFrame 3\nSet by hardware\nset by hardware\ncleared by software\nset by hardware\ncleared by software\nSoftware waits until TXE=1 \nand writes F1 into DR\nSoftware waits until TXE=1 \nand writes F1 into DR\nTC is not set \nbecause TXE=0\nTC is not set \nbecause TXE=1\nUSART_DR\nTC flag\nTXE flag\nTX line\nset\nby hardware\nTC is not set \nbecause TXE=0\nF1\nF2\nF3\nMS48961V1\n" }, { "page_number": 976, "page_indices": { "start_index": 1899690, "end_index": 1901427 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 976 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.2 Transmitter", 973 ], [ 4, "Idle characters", 976 ], [ 3, "30.3.3 Receiver", 976 ], [ 4, "Start bit detection", 976 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n976/1757\nRM0090 Rev 21\nIdle characters\nSetting the TE bit drives the USART to send an idle frame before the first data frame.\n30.3.3 \nReceiver\nThe USART can receive data words of either 8 or 9 bits depending on the M bit in the \nUSART_CR1 register. \nStart bit detection\nThe start bit detection sequence is the same when oversampling by 16 or by 8.\nIn the USART, the start bit is detected when a specific sequence of samples is recognized. \nThis sequence is: 1 1 1 0 X 0 X 0 X 0 0 0 0.\nFigure 300. Start bit detection when oversampling by 16 or 8\nNote:\nIf the sequence is not complete, the start bit detection aborts and the receiver returns to the \nidle state (no flag is set), where it waits for a falling edge.\nThe start bit is confirmed (RXNE flag set, interrupt generated if RXNEIE=1) if the three \nsampled bits are at 0 (first sampling on the third, fifth and seventh bit finds the three bits at 0 \nand second sampling on the eighth, ninth and tenth bit also finds the three bits at 0).\nThe start bit is validated (RXNE flag set, interrupt generated if RXNEIE=1) but the NE noise \nflag is set if, for both samplings, at least two out of the three sampled bits are at 0 (sampling \non the third, fifth and seventh bit and sampling on the eighth, ninth and tenth bit). If this \n0\n1\n0\nX\n0\nX\n0\n0\n0\n0\nX\nX\nX\nX\nX\nX\nFalling edge\ndetection\n1\n1\n1\n2\n3\n4\n5\n6\n7\n8\n9\n10\n11\n12\n13\n14\n15\n16\nX\nX\nX\nX\nX\nX\nX\nX\n9\n1\n0\n1 1\n1 2\n1 3\n1 4\n1 5 1 6\n6/16\n7/16\n7/16\nX\nAt least 2 bits\nout of 3 at 0\nAt least 2 bits\nout of 3 at 0\nOne-bit time\nConditions\nto validate\nthe start bit\nReal\nsample\nclock\nIdeal\nsample\nclock\nRX line\nRX state\nIdle\nStart bit\nSampled values\nai15471b\n" }, { "page_number": 977, "page_indices": { "start_index": 1901427, "end_index": 1903806 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 977 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.3 Receiver", 976 ], [ 4, "Character reception", 977 ], [ 4, "Break character", 977 ], [ 4, "Idle character", 977 ] ], "page_content": "RM0090 Rev 21\n977/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\ncondition is not met, the start detection aborts and the receiver returns to the idle state (no \nflag is set).\nIf, for one of the samplings (on the third, fifth and seventh bit, or on the eighth, ninth and \ntenth bit), two out of the three bits are found at 0, the start bit is validated but the NE noise \nflag bit is set.\nCharacter reception\nDuring an USART reception, data shifts in least significant bit first through the RX pin. In this \nmode, the USART_DR register consists of a buffer (RDR) between the internal bus and the \nreceived shift register.\nProcedure:\n1.\nEnable the USART by writing the UE bit in USART_CR1 register to 1.\n2. \nProgram the M bit in USART_CR1 to define the word length.\n3. \nProgram the number of stop bits in USART_CR2.\n4. \nSelect DMA enable (DMAR) in USART_CR3 if multibuffer communication is to take \nplace. Configure the DMA register as explained in multibuffer communication. STEP 3\n5. \nSelect the desired baud rate using the baud rate register USART_BRR \n6. \nSet the RE bit USART_CR1. This enables the receiver which begins searching for a \nstart bit.\nWhen a character is received\n•\nThe RXNE bit is set. It indicates that the content of the shift register is transferred to the \nRDR. In other words, data has been received and can be read (as well as its \nassociated error flags).\n•\nAn interrupt is generated if the RXNEIE bit is set.\n•\nThe error flags can be set if a frame error, noise or an overrun error has been detected \nduring reception.\n•\nIn multibuffer, RXNE is set after every byte received and is cleared by the DMA read to \nthe Data Register.\n•\nIn single buffer mode, clearing the RXNE bit is performed by a software read to the \nUSART_DR register. The RXNE flag can also be cleared by writing a zero to it. The \nRXNE bit must be cleared before the end of the reception of the next character to avoid \nan overrun error.\nNote:\nThe RE bit should not be reset while receiving data. If the RE bit is disabled during \nreception, the reception of the current byte is aborted.\nBreak character\nWhen a break character is received, the USART handles it as a framing error.\nIdle character\nWhen an idle frame is detected, there is the same procedure as a data received character \nplus an interrupt if the IDLEIE bit is set.\n" }, { "page_number": 978, "page_indices": { "start_index": 1903806, "end_index": 1906191 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 978 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.3 Receiver", 976 ], [ 4, "Overrun error", 978 ], [ 4, "Selecting the proper oversampling method", 978 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n978/1757\nRM0090 Rev 21\nOverrun error\nAn overrun error occurs when a character is received when RXNE has not been reset. Data \ncan not be transferred from the shift register to the RDR register until the RXNE bit is \ncleared.\nThe RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set \nwhen the next data is received or the previous DMA request has not been serviced. When \nan overrun error occurs: \n•\nThe ORE bit is set. \n•\nThe RDR content is not lost. The previous data is available when a read to USART_DR \nis performed. \n•\nThe shift register is overwritten. After that point, any data received during overrun is \nlost.\n•\nAn interrupt is generated if either the RXNEIE bit is set or both the EIE and DMAR bits \nare set.\n•\nThe ORE bit is reset by a read to the USART_SR register followed by a USART_DR \nregister read operation.\nNote:\nThe ORE bit, when set, indicates that at least 1 data has been lost. There are two \npossibilities:\n•\nif RXNE=1, then the last valid data is stored in the receive register RDR and can be \nread,\n•\nif RXNE=0, then it means that the last valid data has already been read and thus there \nis nothing to be read in the RDR. This case can occur when the last valid data is read in \nthe RDR at the same time as the new (and lost) data is received. It may also occur \nwhen the new data is received during the reading sequence (between the USART_SR \nregister read access and the USART_DR read access).\nSelecting the proper oversampling method\nThe receiver implements different user-configurable oversampling techniques (except in \nsynchronous mode) for data recovery by discriminating between valid incoming data and \nnoise.\nThe oversampling method can be selected by programming the OVER8 bit in the \nUSART_CR1 register and can be either 16 or 8 times the baud rate clock (Figure 301 and \nFigure 302).\nDepending on the application:\n•\nselect oversampling by 8 (OVER8=1) to achieve higher speed (up to fPCLK/8). In this \ncase the maximum receiver tolerance to clock deviation is reduced (refer to \nSection 30.3.5: USART receiver tolerance to clock deviation on page 991)\n•\nselect oversampling by 16 (OVER8=0) to increase the tolerance of the receiver to clock \ndeviations. In this case, the maximum speed is limited to maximum fPCLK/16\n" }, { "page_number": 979, "page_indices": { "start_index": 1906191, "end_index": 1908034 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 979 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.3 Receiver", 976 ], [ 4, "Selecting the proper oversampling method", 978 ] ], "page_content": "RM0090 Rev 21\n979/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nProgramming the ONEBIT bit in the USART_CR3 register selects the method used to \nevaluate the logic level. There are two options:\n•\nthe majority vote of the three samples in the center of the received bit. In this case, \nwhen the 3 samples used for the majority vote are not equal, the NF bit is set\n•\na single sample in the center of the received bit\nDepending on the application:\n–\nselect the three samples’ majority vote method (ONEBIT=0) when operating in a \nnoisy environment and reject the data when a noise is detected (refer to \nFigure 134) because this indicates that a glitch occurred during the sampling.\n–\nselect the single sample method (ONEBIT=1) when the line is noise-free to \nincrease the receiver’s tolerance to clock deviations (see Section 30.3.5: USART \nreceiver tolerance to clock deviation on page 991). In this case the NF bit is never \nset.\nWhen noise is detected in a frame:\n•\nThe NF bit is set at the rising edge of the RXNE bit.\n•\nThe invalid data is transferred from the Shift register to the USART_DR register.\n•\nNo interrupt is generated in case of single byte communication. However this bit rises \nat the same time as the RXNE bit which itself generates an interrupt. In case of \nmultibuffer communication an interrupt is issued if the EIE bit is set in the USART_CR3 \nregister.\nThe NF bit is reset by a USART_SR register read operation followed by a USART_DR \nregister read operation.\nNote:\nOversampling by 8 is not available in the Smartcard, IrDA and LIN modes. In those modes, \nthe OVER8 bit is forced to ‘0 by hardware.\nFigure 301. Data sampling when oversampling by 16\nMSv31152V1\n1\n2\n3\n4\n5\n6\n7\n8\n9\n10\n11\n12\n13\n14\n15\n16\nsampled values\n6/16\n7/16\n7/16\nOne bit time\nSample clock\nRX line\n" }, { "page_number": 980, "page_indices": { "start_index": 1908034, "end_index": 1909158 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 980 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.3 Receiver", 976 ], [ 4, "Framing error", 980 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n980/1757\nRM0090 Rev 21\nFigure 302. Data sampling when oversampling by 8\n \nFraming error\nA framing error is detected when:\nThe stop bit is not recognized on reception at the expected time, following either a de-\nsynchronization or excessive noise. \nWhen the framing error is detected:\n•\nThe FE bit is set by hardware\n•\nThe invalid data is transferred from the Shift register to the USART_DR register.\n•\nNo interrupt is generated in case of single byte communication. However this bit rises \nat the same time as the RXNE bit which itself generates an interrupt. In case of \nmultibuffer communication an interrupt isissued if the EIE bit is set in the USART_CR3 \nregister.\nThe FE bit is reset by a USART_SR register read operation followed by a USART_DR \nregister read operation.\nTable 134. Noise detection from sampled data\nSampled value\nNE status\nReceived bit value\n000\n0\n0\n001\n1\n0\n010\n1\n0\n011\n1\n1\n100\n1\n0\n101\n1\n1\n110\n1\n1\n111\n0\n1\nMSv31153V1\n1\n2\n3\n4\n5\n6\n7\nsampled values\n2/8\n3/8\n3/8\nOne bit time\nSample \nclock (x8)\nRX line\n8\n" }, { "page_number": 981, "page_indices": { "start_index": 1909158, "end_index": 1912069 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 981 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.3 Receiver", 976 ], [ 4, "Configurable stop bits during reception", 981 ], [ 3, "30.3.4 Fractional baud rate generation", 981 ] ], "page_content": "RM0090 Rev 21\n981/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nConfigurable stop bits during reception\nThe number of stop bits to be received can be configured through the control bits of Control \nRegister 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 in Smartcard mode.\n1.\n0.5 stop bit (reception in Smartcard mode): No sampling is done for 0.5 stop bit. As \na consequence, no framing error and no break frame can be detected when 0.5 stop bit \nis selected.\n2. \n1 stop bit: Sampling for 1 stop Bit is done on the 8th, 9th and 10th samples.\n3. \n1.5 stop bits (Smartcard mode): When transmitting in smartcard mode, the device \nmust check that the data is correctly sent. Thus the receiver block must be enabled (RE \n=1 in the USART_CR1 register) and the stop bit is checked to test if the smartcard has \ndetected a parity error. In the event of a parity error, the smartcard forces the data \nsignal low during the sampling - NACK signal-, which is flagged as a framing error. \nThen, the FE flag is set with the RXNE at the end of the 1.5 stop bit. Sampling for 1.5 \nstop bits is done on the 16th, 17th and 18th samples (1 baud clock period after the \nbeginning of the stop bit). The 1.5 stop bit can be decomposed into 2 parts: one 0.5 \nbaud clock period during which nothing happens, followed by 1 normal stop bit period \nduring which sampling occurs halfway through. Refer to Section 30.3.11: Smartcard on \npage 1000 for more details.\n4. \n2 stop bits: Sampling for 2 stop bits is done on the 8th, 9th and 10th samples of the \nfirst stop bit. If a framing error is detected during the first stop bit the framing error flag \nis set. The second stop bit is not checked for framing error. The RXNE flag is set at the \nend of the first stop bit.\n30.3.4 \nFractional baud rate generation\nThe baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as \nprogrammed in the Mantissa and Fraction values of USARTDIV.\nEquation 1: Baud rate for standard USART (SPI mode included)\nEquation 2: Baud rate in Smartcard, LIN and IrDA modes\nUSARTDIV is an unsigned fixed point number that is coded on the USART_BRR register.\n•\nWhen OVER8=0, the fractional part is coded on 4 bits and programmed by the \nDIV_fraction[3:0] bits in the USART_BRR register\n•\nWhen OVER8=1, the fractional part is coded on 3 bits and programmed by the \nDIV_fraction[2:0] bits in the USART_BRR register, and bit DIV_fraction[3] must be kept \ncleared.\nNote:\nThe baud counters are updated to the new value in the baud registers after a write operation \nto USART_BRR. Hence the baud rate register value should not be changed during \ncommunication.\nTx/Rx baud\nfCK\n8\n2\nOVER8\n–\n(\n)\nUSARTDIV\n×\n×\n------------------------------------------------------------------------------------\n=\nTx/Rx baud\nfCK\n16\nUSARTDIV\n×\n----------------------------------------------\n=\n" }, { "page_number": 982, "page_indices": { "start_index": 1912069, "end_index": 1913387 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 982 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.4 Fractional baud rate generation", 981 ], [ 4, "How to derive USARTDIV from USART_BRR register values when OVER8=0", 982 ], [ 4, "How to derive USARTDIV from USART_BRR register values when OVER8=1", 982 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n982/1757\nRM0090 Rev 21\nHow to derive USARTDIV from USART_BRR register values when OVER8=0\nExample 1:\nIf DIV_Mantissa = 0d27 and DIV_Fraction = 0d12 (USART_BRR = 0x1BC), then\nMantissa (USARTDIV) = 0d27\nFraction (USARTDIV) = 12/16 = 0d0.75\nTherefore USARTDIV = 0d27.75\nExample 2:\nTo program USARTDIV = 0d25.62\nThis leads to:\nDIV_Fraction = 16*0d0.62 = 0d9.92\nThe nearest real number is 0d10 = 0xA\nDIV_Mantissa = mantissa (0d25.620) = 0d25 = 0x19\nThen, USART_BRR = 0x19A hence USARTDIV = 0d25.625\nExample 3: \nTo program USARTDIV = 0d50.99\nThis leads to:\nDIV_Fraction = 16*0d0.99 = 0d15.84\nThe nearest real number is 0d16 = 0x10 => overflow of DIV_frac[3:0] => carry must be \nadded up to the mantissa\nDIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33\nThen, USART_BRR = 0x330 hence USARTDIV = 0d51.000\nHow to derive USARTDIV from USART_BRR register values when OVER8=1\nExample 1:\nIf DIV_Mantissa = 0x27 and DIV_Fraction[2:0]= 0d6 (USART_BRR = 0x1B6), then\nMantissa (USARTDIV) = 0d27\nFraction (USARTDIV) = 6/8 = 0d0.75\nTherefore USARTDIV = 0d27.75\nExample 2: \nTo program USARTDIV = 0d25.62\nThis leads to:\nDIV_Fraction = 8*0d0.62 = 0d4.96\nThe nearest real number is 0d5 = 0x5\nDIV_Mantissa = mantissa (0d25.620) = 0d25 = 0x19\n" }, { "page_number": 983, "page_indices": { "start_index": 1913387, "end_index": 1914986 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 983 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.4 Fractional baud rate generation", 981 ], [ 4, "How to derive USARTDIV from USART_BRR register values when OVER8=1", 982 ] ], "page_content": "RM0090 Rev 21\n983/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nThen, USART_BRR = 0x195 => USARTDIV = 0d25.625\nExample 3: \nTo program USARTDIV = 0d50.99\nThis leads to:\nDIV_Fraction = 8*0d0.99 = 0d7.92\nThe nearest real number is 0d8 = 0x8 => overflow of the DIV_frac[2:0] => carry must be \nadded up to the mantissa\nDIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33\nThen, USART_BRR = 0x0330 => USARTDIV = 0d51.000\n \nTable 135. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 12 MHz,\noversampling by 16(1)\nOversampling by 16 (OVER8=0)\nBaud rate7\nfPCLK = 8 MHz\nfPCLK = 12 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired) B.rate / \nDesired B.rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error\n1\n1.2 KBps\n1.2 KBps\n416.6875\n0\n1.2 KBps\n625\n0\n2\n2.4 KBps\n2.4 KBps\n208.3125\n0.01\n2.4 KBps\n312.5\n0\n3\n9.6 KBps\n9.604 KBps\n52.0625\n0.04\n9.6 KBps\n78.125\n0\n4\n19.2 KBps\n19.185 KBps\n26.0625\n0.08\n19.2 KBps\n39.0625\n0\n5\n38.4 KBps\n38.462 KBps\n13\n0.16\n38.339 KBps\n19.5625\n0.16\n6\n57.6 KBps\n57.554 KBps\n8.6875\n0.08\n57.692 KBps\n13\n0.16\n7\n115.2 KBps\n115.942 KBps\n4.3125\n0.64\n115.385 KBps\n6.5\n0.16\n8\n230.4 KBps\n228.571 KBps\n2.1875\n0.79\n230.769 KBps\n3.25\n0.16\n9\n460.8 KBps\n470.588 KBps\n1.0625\n2.12\n461.538 KBps\n1.625\n0.16\n10\n921.6 KBps\nNA\nNA\nNA\nNA\nNA\nNA\n11\n2 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n12\n3 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\n" }, { "page_number": 984, "page_indices": { "start_index": 1914986, "end_index": 1916916 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 984 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.4 Fractional baud rate generation", 981 ], [ 4, "How to derive USARTDIV from USART_BRR register values when OVER8=1", 982 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n984/1757\nRM0090 Rev 21\n \n \nTable 136. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK =12 MHz,\noversampling by 8(1)\nOversampling by 8 (OVER8 = 1)\nBaud rate\nfPCLK = 8 MHz\nfPCLK = 12 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired) \nB.rate / \nDesired \nB.rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error\n1\n1.2 KBps\n1.2 KBps\n833.375\n0\n1.2 KBps\n1250\n0\n2\n2.4 KBps\n2.4 KBps\n416.625\n0.01\n2.4 KBps\n625\n0\n3\n9.6 KBps\n9.604 KBps\n104.125\n0.04\n9.6 KBps\n156.25\n0\n4\n19.2 KBps\n19.185 KBps\n52.125\n0.08\n19.2 KBps\n78.125\n0\n5\n38.4 KBps\n38.462 KBps\n26\n0.16\n38.339 KBps\n39.125\n0.16\n6\n57.6 KBps\n57.554 KBps\n17.375\n0.08\n57.692 KBps\n26\n0.16\n7\n115.2 KBps\n115.942 KBps\n8.625\n0.64\n115.385 KBps\n13\n0.16\n8\n230.4 KBps\n228.571 KBps\n4.375\n0.79\n230.769 KBps\n6.5\n0.16\n9\n460.8 KBps\n470.588 KBps\n2.125\n2.12\n461.538 KBps\n3.25\n0.16\n10\n921.6 KBps\n888.889 KBps\n1.125\n3.55\n923.077 KBps\n1.625\n0.16\n11\n2 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n12\n3 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\nTable 137. Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz,\noversampling by 16(1)\nOversampling by 16 (OVER8 = 0)\nBaud rate\nfPCLK = 16 MHz\nfPCLK = 24 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired) B.rate / \nDesired B.rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error\n1\n1.2 KBps\n1.2 KBps\n833.3125\n0\n1.2\n1250\n0\n2\n2.4 KBps\n2.4 KBps\n416.6875\n0\n2.4\n625\n0\n3\n9.6 KBps\n9.598 KBps\n104.1875\n0.02\n9.6\n156.25\n0\n4\n19.2 KBps\n19.208 KBps\n52.0625\n0.04\n19.2\n78.125\n0\n5\n38.4 KBps\n38.369 KBps\n26.0625\n0.08\n38.4\n39.0625\n0\n6\n57.6 KBps\n57.554 KBps\n17.375\n0.08\n57.554\n26.0625\n0.08\n" }, { "page_number": 985, "page_indices": { "start_index": 1916916, "end_index": 1919009 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 985 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.4 Fractional baud rate generation", 981 ], [ 4, "How to derive USARTDIV from USART_BRR register values when OVER8=1", 982 ] ], "page_content": "RM0090 Rev 21\n985/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n \n7\n115.2 KBps\n115.108 KBps\n8.6875\n0.08\n115.385\n13\n0.16\n8\n230.4 KBps\n231.884 KBps\n4.3125\n0.64\n230.769\n6.5\n0.16\n9\n460.8 KBps\n457.143 KBps\n2.1875\n0.79\n461.538\n3.25\n0.16\n10\n921.6 KBps\n941.176 KBps\n1.0625\n2.12\n923.077\n1.625\n0.16\n11\n2 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n12\n3 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\nTable 137. Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz,\noversampling by 16(1) (continued)\nOversampling by 16 (OVER8 = 0)\nBaud rate\nfPCLK = 16 MHz\nfPCLK = 24 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired) B.rate / \nDesired B.rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error\nTable 138. Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz,\noversampling by 8(1)\nOversampling by 8 (OVER8=1)\nBaud rate\nfPCLK = 16 MHz\nfPCLK = 24 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired) B.rate / \nDesired B.rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error\n1\n1.2 KBps\n1.2 KBps\n1666.625\n0\n1.2 KBps\n2500\n0\n2\n2.4 KBps\n2.4 KBps\n833.375\n0\n2.4 KBps\n1250\n0\n3\n9.6 KBps\n9.598 KBps\n208.375\n0.02\n9.6 KBps\n312.5\n0\n4\n19.2 KBps\n19.208 KBps\n104.125\n0.04\n19.2 KBps\n156.25\n0\n5\n38.4 KBps\n38.369 KBps\n52.125\n0.08\n38.4 KBps\n78.125\n0\n6\n57.6 KBps\n57.554 KBps\n34.75\n0.08\n57.554 KBps\n52.125\n0.08\n7\n115.2 KBps\n115.108 KBps\n17.375\n0.08\n115.385 KBps\n26\n0.16\n8\n230.4 KBps\n231.884 KBps\n8.625\n0.64\n230.769 KBps\n13\n0.16\n9\n460.8 KBps\n457.143 KBps\n4.375\n0.79\n461.538 KBps\n6.5\n0.16\n10\n921.6 KBps\n941.176 KBps\n2.125\n2.12\n923.077 KBps\n3.25\n0.16\n11\n2 MBps\n2000 KBps\n1\n0\n2000 KBps\n1.5\n0\n12\n3 MBps\nNA\nNA\nNA\n3000 KBps\n1\n0\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\n" }, { "page_number": 986, "page_indices": { "start_index": 1919009, "end_index": 1920962 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 986 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.4 Fractional baud rate generation", 981 ], [ 4, "How to derive USARTDIV from USART_BRR register values when OVER8=1", 982 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n986/1757\nRM0090 Rev 21\n \nTable 139. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,\noversampling by 16(1)\nOversampling by 16 (OVER8=0)\nBaud rate\nfPCLK = 8 MHz\nfPCLK = 16 MHz\nS.No\nDesired\nActual\nValue \nprogramme\nd in the \nbaud rate \nregister\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error\n1.\n2.4 KBps\n2.400 KBps\n208.3125\n0.00%\n2.400 KBps\n416.6875\n0.00%\n2.\n9.6 KBps\n9.604 KBps\n52.0625\n0.04%\n9.598 KBps\n104.1875\n0.02%\n3.\n19.2 KBps\n19.185 KBps\n26.0625\n0.08%\n19.208 KBps\n52.0625\n0.04%\n4.\n57.6 KBps\n57.554 KBps\n8.6875\n0.08%\n57.554 KBps\n17.3750\n0.08%\n5.\n115.2 KBps\n115.942 KBps 4.3125\n0.64%\n115.108 KBps\n8.6875\n0.08%\n6.\n230.4 KBps\n228.571 \nKBps\n2.1875\n0.79%\n231.884 KBps\n4.3125\n0.64%\n7.\n460.8 KBps\n470.588 \nKBps\n1.0625\n2.12%\n457.143 KBps\n2.1875\n0.79%\n8.\n896 KBps\nNA\nNA\nNA\n888.889 KBps\n1.1250\n0.79%\n9.\n921.6 KBps\nNA\nNA\nNA\n941.176 KBps\n1.0625\n2.12%\n10.\n1.792 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n11.\n1.8432 MBps NA\nNA\nNA\nNA\nNA\nNA\n12.\n3.584 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n13.\n3.6864 MBps NA\nNA\nNA\nNA\nNA\nNA\n14.\n7.168 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n15.\n7.3728 MBps NA\nNA\nNA\nNA\nNA\nNA\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\nTable 140. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,\noversampling by 8(1)\nOversampling by 8 (OVER8=1)\nBaud rate\nfPCLK = 8 MHz\nfPCLK = 16 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\n1.\n2.4 KBps\n2.400 KBps\n416.625\n0.01%\n2.400 KBps\n833.375\n0.00%\n2.\n9.6 KBps\n9.604 KBps\n104.125\n0.04%\n9.598 KBps\n208.375\n0.02%\n3.\n19.2 KBps\n19.185 KBps\n52.125\n0.08%\n19.208 KBps\n104.125\n0.04%\n" }, { "page_number": 987, "page_indices": { "start_index": 1920962, "end_index": 1923132 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 987 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.4 Fractional baud rate generation", 981 ], [ 4, "How to derive USARTDIV from USART_BRR register values when OVER8=1", 982 ] ], "page_content": "RM0090 Rev 21\n987/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n \n4.\n57.6 KBps\n57.557 KBps\n17.375\n0.08%\n57.554 KBps\n34.750\n0.08%\n5.\n115.2 KBps\n115.942 KBps\n8.625\n0.64%\n115.108 KBps\n17.375\n0.08%\n6.\n230.4 KBps\n228.571 KBps\n4.375\n0.79%\n231.884 KBps\n8.625\n0.64%\n7.\n460.8 KBps\n470.588 KBps\n2.125\n2.12%\n457.143 KBps\n4.375\n0.79%\n8.\n896 KBps\n888.889 KBps\n1.125\n0.79%\n888.889 KBps\n2.250\n0.79%\n9.\n921.6 KBps\n888.889 KBps\n1.125\n3.55%\n941.176 KBps\n2.125\n2.12%\n10.\n1.792 MBps\nNA\nNA\nNA\n1.7777 MBps\n1.125\n0.79%\n11.\n1.8432 MBps\nNA\nNA\nNA\n1.7777 MBps\n1.125\n3.55%\n12.\n3.584 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n13.\n3.6864 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n14.\n7.168 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n15.\n7.3728 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\nTable 140. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,\noversampling by 8(1) (continued)\nOversampling by 8 (OVER8=1)\nBaud rate\nfPCLK = 8 MHz\nfPCLK = 16 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\nTable 141. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,\noversampling by 16(1)(2)\nOversampling by 16 (OVER8=0)\nBaud rate\nfPCLK = 30 MHz\nfPCLK = 60 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\n1.\n2.4 KBps\n2.400 KBps\n781.2500\n0.00%\n2.400 KBps\n1562.5000\n0.00%\n2.\n9.6 KBps\n9.600 KBps\n195.3125\n0.00%\n9.600 KBps\n390.6250\n0.00%\n3.\n19.2 KBps\n19.194 KBps\n97.6875\n0.03%\n19.200 KBps\n195.3125\n0.00%\n4.\n57.6 KBps\n57.582KBps\n32.5625\n0.03%\n57.582 KBps\n65.1250\n0.03%\n5.\n115.2 KBps\n115.385 KBps\n16.2500\n0.16%\n115.163 KBps\n32.5625\n0.03%\n6.\n230.4 KBps\n230.769 KBps\n8.1250\n0.16%\n230.769KBps\n16.2500\n0.16%\n7.\n460.8 KBps\n461.538 KBps\n4.0625\n0.16%\n461.538 KBps 8.1250\n0.16%\n8.\n896 KBps\n909.091 KBps\n2.0625\n1.46%\n895.522 KBps 4.1875\n0.05%\n" }, { "page_number": 988, "page_indices": { "start_index": 1923132, "end_index": 1925355 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 988 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.4 Fractional baud rate generation", 981 ], [ 4, "How to derive USARTDIV from USART_BRR register values when OVER8=1", 982 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n988/1757\nRM0090 Rev 21\n \n9.\n921.6 KBps\n909.091 KBps\n2.0625\n1.36%\n923.077 KBps 4.0625\n0.16%\n10.\n1.792 MBps\n1.1764 MBps\n1.0625\n1.52%\n1.8182 MBps\n2.0625\n1.36%\n11.\n1.8432 \nMBps\n1.8750 MBps\n1.0000\n1.73%\n1.8182 MBps\n2.0625\n1.52%\n12.\n3.584 MBps\nNA\nNA\nNA\n3.2594 MBps\n1.0625\n1.52%\n13.\n3.6864 \nMBps\nNA\nNA\nNA\n3.7500 MBps\n1.0000\n1.73%\n14.\n7.168 MBps\nNA\nNA\nNA\nNA\nNA\nNA\n15.\n7.3728 \nMBps\nNA\nNA\nNA\nNA\nNA\nNA\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\n2.\nOnly USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device \ndatasheets for the maximum values for PCLK1 and PCLK2.\nTable 141. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,\noversampling by 16(1)(2) (continued)\nOversampling by 16 (OVER8=0)\nBaud rate\nfPCLK = 30 MHz\nfPCLK = 60 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\nTable 142. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,\noversampling by 8(1) (2)\nOversampling by 8 (OVER8=1)\nBaud rate\nfPCLK = 30 MHz\nfPCLK =60 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\n1.\n2.4 KBps\n2.400 KBps\n1562.5000\n0.00%\n2.400 KBps\n3125.0000\n0.00%\n2.\n9.6 KBps\n9.600 KBps\n390.6250\n0.00%\n9.600 KBps\n781.2500\n0.00%\n3.\n19.2 KBps\n19.194 KBps\n195.3750\n0.03%\n19.200 KBps\n390.6250\n0.00%\n4.\n57.6 KBps\n57.582 KBps\n65.1250\n0.16%\n57.582 KBps\n130.2500\n0.03%\n5.\n115.2 KBps\n115.385 KBps\n32.5000\n0.16%\n115.163 KBps\n65.1250\n0.03%\n6.\n230.4 KBps\n230.769 KBps\n16.2500\n0.16%\n230.769 KBps\n32.5000\n0.16%\n7.\n460.8 KBps\n461.538 KBps\n8.1250\n0.16%\n461.538 KBps\n16.2500\n0.16%\n8.\n896 KBps\n909.091 KBps\n4.1250\n1.46%\n895.522 KBps\n8.3750\n0.05%\n9.\n921.6 KBps\n909.091 KBps\n4.1250\n1.36%\n923.077 KBps\n8.1250\n0.16%\n10.\n1.792 MBps\n1.7647 MBps\n2.1250\n1.52%\n1.8182 MBps\n4.1250\n1.46%\n" }, { "page_number": 989, "page_indices": { "start_index": 1925355, "end_index": 1927658 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 989 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.4 Fractional baud rate generation", 981 ], [ 4, "How to derive USARTDIV from USART_BRR register values when OVER8=1", 982 ] ], "page_content": "RM0090 Rev 21\n989/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n \n11.\n1.8432 MBps\n1.8750 MBps\n2.0000\n1.73%\n1.8182 MBps\n4.1250\n1.36%\n12.\n3.584 MBps\n3.7500 MBps\n1.0000\n4.63%\n3.5294 MBps\n2.1250\n1.52%\n13.\n3.6864 MBps\n3.7500 MBps\n1.0000\n1.73%\n3.7500 MBps\n2.0000\n1.73%\n14.\n7.168 MBps\nNA\nNA\nNA\n7.5000 MBps\n1.0000\n4.63%\n15.\n7.3728 MBps\nNA\nNA\nNA\n7.5000 MBps\n1.0000\n1.73%\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\n2.\nOnly USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device \ndatasheets for the maximum values for PCLK1 and PCLK2.\nTable 142. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,\noversampling by 8(1) (2) (continued)\nOversampling by 8 (OVER8=1)\nBaud rate\nfPCLK = 30 MHz\nfPCLK =60 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\nTable 143. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 Hz,\noversampling by 16(1)(2)\nOversampling by 16 (OVER8=0)\nBaud rate\nfPCLK = 42 MHz\nfPCLK = 84 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\n1.\n1.2 KBps\n1.2 KBps\n2187.5\n0\n1.2 KBps\nNA\n0\n2.\n2.4 KBps\n2.4 KBps\n1093.75\n0\n2.4 KBps\n2187.5\n0\n3.\n9.6 KBps\n9.6 KBps\n273.4375\n0\n9.6 KBps\n546.875\n0\n4.\n19.2 KBps\n19.195 KBps\n136.75\n0.02\n19.2 KBps\n273.4375\n0\n5.\n38.4 KBps\n38.391 KBps\n68.375\n0.02\n38.391 KBps\n136.75\n0.02\n6.\n57.6 KBps\n57.613 KBps\n45.5625\n0.02\n57.613 KBps\n91.125\n0.02\n7.\n115.2 KBps\n115.068 KBps\n22.8125\n0.11\n115.226 KBps\n45.5625\n0.02\n8.\n230.4 KBps\n230.769 KBps\n11.375\n0.16\n230.137 KBps 22.8125\n0.11\n9.\n460.8 KBps\n461.538 KBps\n5.6875\n0.16\n461.538 KBps 11.375\n0.16\n10.\n921.6 KBps\n913.043 KBps\n2.875\n0.93\n923.076 KBps 5.6875\n0.93\n11.\n1.792 MBps\n1.826 MBps\n1.4375\n1.9\n1.787 MBps\n2.9375\n0.27\n12.\n1.8432 MBps 1.826 MBps\n1.4375\n0.93\n1.826 MBps\n2.875\n0.93\n13.\n3.584 MBps\nN.A\nN.A\nN.A\n3.652 MBps\n1.4375\n1.9\n14.\n3.6864 MBps N.A\nN.A\nN.A\n3.652 MBps\n1.4375\n0.93\n" }, { "page_number": 990, "page_indices": { "start_index": 1927658, "end_index": 1929840 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 990 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.4 Fractional baud rate generation", 981 ], [ 4, "How to derive USARTDIV from USART_BRR register values when OVER8=1", 982 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n990/1757\nRM0090 Rev 21\n \n15.\n7.168 MBps\nN.A\nN.A\nN.A\nN.A\nN.A\nN.A\n16.\n7.3728 MBps N.A\nN.A\nN.A\nN.A\nN.A\nN.A\n17.\n9 MBps\nN.A\nN.A\nN.A\nN.A\nN.A\nN.A\n18.\n10.5 MBps\nN.A\nN.A\nN.A\nN.A\nN.A\nN.A\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can be \nfixed with these data.\n2.\nOnly USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device \ndatasheets for the maximum values for PCLK1 and PCLK2.\nTable 143. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 Hz,\noversampling by 16(1)(2) (continued)\nOversampling by 16 (OVER8=0)\nBaud rate\nfPCLK = 42 MHz\nfPCLK = 84 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\n% Error = \n(Calculated - \nDesired)B.Rate \n/Desired B.Rate\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\nTable 144. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 MHz,\noversampling by 8(1)(2)\nOversampling by 8 (OVER8=1)\nBaud rate\nfPCLK = 42 MHz\nfPCLK = 84 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\nValue \nprogrammed \nin the baud \nrate register\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\n1.\n2.4 KBps\n2.4 KBps\n2187.5\n0\n2.4 KBps\nNA\n0\n2.\n9.6 KBps\n9.6 KBps\n546.875\n0\n9.6 KBps\n1093.75\n0\n3.\n19.2 KBps\n19.195 KBps\n273.5\n0.02\n19.2 KBps\n546.875\n0\n4.\n38.4 KBps\n38.391 KBps\n136.75\n0.02\n38.391 KBps\n273.5\n0.02\n5.\n57.6 KBps\n57.613 KBps\n91.125\n0.02\n57.613 KBps\n182.25\n0.02\n6.\n115.2 KBps\n115.068 KBps\n45.625\n0.11\n115.226 KBps\n91.125\n0.02\n7.\n230.4 KBps\n230.769 KBps\n22.75\n0.11\n230.137 KBps\n45.625\n0.11\n8.\n460.8 KBps\n461.538 KBps\n11.375\n0.16\n461.538 KBps\n22.75\n0.16\n9.\n921.6 KBps\n913.043 KBps\n5.75\n0.93\n923.076 KBps\n11.375\n0.93\n10.\n1.792 MBps\n1.826 MBps\n2.875\n1.9\n1.787Mbps\n5.875\n0.27\n11.\n1.8432 MBps\n1.826 MBps\n2.875\n0.93\n1.826 MBps\n5.75\n0.93\n12.\n3.584 MBps\n3.5 MBps\n1.5\n2.34\n3.652 MBps\n2.875\n1.9\n13.\n3.6864 MBps\n3.82 MBps\n1.375\n3.57\n3.652 MBps\n2.875\n0.93\n14.\n7.168 MBps\nN.A\nN.A\nN.A\n7 MBps\n1.5\n2.34\n15.\n7.3728 MBps\nN.A\nN.A\nN.A\n7.636 MBps\n1.375\n3.57\n" }, { "page_number": 991, "page_indices": { "start_index": 1929840, "end_index": 1932115 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 991 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.5 USART receiver tolerance to clock deviation", 991 ] ], "page_content": "RM0090 Rev 21\n991/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n30.3.5 \nUSART receiver tolerance to clock deviation\nThe USART asynchronous receiver works correctly only if the total clock system deviation is \nsmaller than the USART receiver’s tolerance. The causes which contribute to the total \ndeviation are:\n•\nDTRA: Deviation due to the transmitter error (which also includes the deviation of the \ntransmitter’s local oscillator)\n•\nDQUANT: Error due to the baud rate quantization of the receiver\n•\nDREC: Deviation of the receiver’s local oscillator\n•\nDTCL: Deviation due to the transmission line (generally due to the transceivers which \ncan introduce an asymmetry between the low-to-high transition timing and the high-to-\nlow transition timing)\nDTRA + DQUANT + DREC + DTCL < USART receiver’s tolerance\nThe USART receiver’s tolerance to properly receive data is equal to the maximum tolerated \ndeviation and depends on the following choices:\n•\n10- or 11-bit character length defined by the M bit in the USART_CR1 register\n•\noversampling by 8 or 16 defined by the OVER8 bit in the USART_CR1 register\n•\nuse of fractional baud rate or not\n•\nuse of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in \nthe USART_CR3 register\n \n16.\n9 MBps\nN.A\nN.A\nN.A\n9.333 MBps\n1.125\n3.7\n17.\n10.5 MBps\nN.A\nN.A\nN.A\n10.5 MBps\n1\n0\n1.\nThe lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can \nbe fixed with these data.\n2.\nOnly USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device \ndatasheets for the maximum values for PCLK1 and PCLK2.\nTable 144. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 MHz,\noversampling by 8(1)(2) (continued)\nOversampling by 8 (OVER8=1)\nBaud rate\nfPCLK = 42 MHz\nfPCLK = 84 MHz\nS.No\nDesired\nActual\nValue \nprogrammed \nin the baud \nrate register\nValue \nprogrammed \nin the baud \nrate register\nActual\nValue \nprogrammed \nin the baud \nrate register\n% \nError\nTable 145. USART receiver’s tolerance when DIV fraction is 0\nM bit\nOVER8 bit = 0\nOVER8 bit = 1\nONEBIT=0\nONEBIT=1\nONEBIT=0\nONEBIT=1\n0\n3.75%\n4.375%\n2.50%\n3.75%\n1\n3.41%\n3.97%\n2.27%\n3.41%\n" }, { "page_number": 992, "page_indices": { "start_index": 1932115, "end_index": 1934185 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 992 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.6 Multiprocessor communication", 992 ], [ 4, "Idle line detection (WAKE=0)", 992 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n992/1757\nRM0090 Rev 21\n \nNote:\nThe figures specified in Table 145 and Table 146 may slightly differ in the special case when \nthe received frames contain some Idle frames of exactly 10-bit times when M=0 (11-bit times \nwhen M=1).\n30.3.6 \nMultiprocessor communication\nThere is a possibility of performing multiprocessor communication with the USART (several \nUSARTs connected in a network). For instance one of the USARTs can be the master, its TX \noutput is connected to the RX input of the other USART. The others are slaves, their \nrespective TX outputs are logically ANDed together and connected to the RX input of the \nmaster.\nIn multiprocessor configurations it is often desirable that only the intended message \nrecipient should actively receive the full message contents, thus reducing redundant USART \nservice overhead for all non addressed receivers.\nThe non addressed devices may be placed in mute mode by means of the muting function. \nIn mute mode:\n•\nNone of the reception status bits can be set.\n•\nAll the receive interrupts are inhibited.\n•\nThe RWU bit in USART_CR1 register is set to 1. RWU can be controlled automatically \nby hardware or written by the software under certain conditions.\nThe USART can enter or exit from mute mode using one of two methods, depending on the \nWAKE bit in the USART_CR1 register:\n•\nIdle Line detection if the WAKE bit is reset,\n•\nAddress Mark detection if the WAKE bit is set.\nIdle line detection (WAKE=0)\nThe USART enters mute mode when the RWU bit is written to 1.\nIt wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but \nthe IDLE bit is not set in the USART_SR register. RWU can also be written to 0 by software.\nAn example of mute mode behavior using Idle line detection is given in Figure 303.\nTable 146. USART receiver tolerance when DIV_Fraction is different from 0\nM bit\nOVER8 bit = 0\nOVER8 bit = 1\nONEBIT=0\nONEBIT=1\nONEBIT=0\nONEBIT=1\n0\n3.33%\n3.88%\n2%\n3%\n1\n3.03%\n3.53%\n1.82%\n2.73%\n" }, { "page_number": 993, "page_indices": { "start_index": 1934185, "end_index": 1936000 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 993 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.6 Multiprocessor communication", 992 ], [ 4, "Address mark detection (WAKE=1)", 993 ] ], "page_content": "RM0090 Rev 21\n993/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nFigure 303. Mute mode using Idle line detection\nAddress mark detection (WAKE=1)\nIn this mode, bytes are recognized as addresses if their MSB is a ‘1 else they are \nconsidered as data. In an address byte, the address of the targeted receiver is put on the 4 \nLSB. This 4-bit word is compared by the receiver with its own address which is programmed \nin the ADD bits in the USART_CR2 register.\nThe USART enters mute mode when an address character is received which does not \nmatch its programmed address. In this case, the RWU bit is set by hardware. The RXNE \nflag is not set for this address byte and no interrupt nor DMA request is issued as the \nUSART would have entered mute mode.\nIt exits from mute mode when an address character is received which matches the \nprogrammed address. Then the RWU bit is cleared and subsequent bytes are received \nnormally. The RXNE bit is set for the address character since the RWU bit has been \ncleared.\nThe RWU bit can be written to as 0 or 1 when the receiver buffer contains no data (RXNE=0 \nin the USART_SR register). Otherwise the write attempt is ignored.\nAn example of mute mode behavior using address mark detection is given in Figure 304.\nFigure 304. Mute mode using address mark detection\nMSv40881V1\nData 1 Data 2\nIDLE\nData 3 Data 4\nData 6\nIdle frame detected\nRWU written to 1\nRWU\nRX\nMute mode\nNormal mode\nRXNE\nRXNE\nData 5\nMSv40882V1\nIDLE\nAddr=0 Data 1 Data 2\nIDLE\nAddr=1 Data 3 Data 4 Addr=2 Data 5\nIn this example, the current address of the receiver is 1 \n(programmed in the USART_CR2 register)\nRXNE\nNon-matching address\nMatching address\nNon-matching address\nRWU written to 1\n(RXNE was cleared)\nRWU\nRX\nMute mode\nMute mode\nNormal mode\nRXNE\nRXNE\n" }, { "page_number": 994, "page_indices": { "start_index": 1936000, "end_index": 1938427 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 994 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.7 Parity control", 994 ], [ 4, "Even parity", 994 ], [ 4, "Odd parity", 994 ], [ 4, "Parity checking in reception", 994 ], [ 4, "Parity generation in transmission", 994 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n994/1757\nRM0090 Rev 21\n30.3.7 \nParity control\nParity control (generation of parity bit in transmission and parity checking in reception) can \nbe enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame \nlength defined by the M bit, the possible USART frame formats are as listed in Table 147.\n \nEven parity\nThe parity bit is calculated to obtain an even number of “1s” inside the frame made of the 7 \nor 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.\nE.g.: data=00110101; 4 bits set => parity bit is 0 if even parity is selected (PS bit in \nUSART_CR1 = 0).\nOdd parity\nThe parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or \n8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.\nE.g.: data=00110101; 4 bits set => parity bit is 1 if odd parity is selected (PS bit in \nUSART_CR1 = 1).\nParity checking in reception\nIf the parity check fails, the PE flag is set in the USART_SR register and an interrupt is \ngenerated if PEIE is set in the USART_CR1 register. The PE flag is cleared by a software \nsequence (a read from the status register followed by a read or write access to the \nUSART_DR data register).\nNote:\nIn case of wake-up by an address mark: the MSB bit of the data is taken into account to \nidentify an address but not the parity bit. And the receiver does not check the parity of the \naddress data (PE is not set in case of a parity error).\nParity generation in transmission\nIf the PCE bit is set in USART_CR1, then the MSB bit of the data written in the data register \nis transmitted but is changed by the parity bit (even number of “1s” if even parity is selected \n(PS=0) or an odd number of “1s” if odd parity is selected (PS=1)).\nNote:\nThe software routine that manages the transmission can activate the software sequence \nwhich clears the PE flag (a read from the status register followed by a read or write access \nto the data register). When operating in half-duplex mode, depending on the software, this \ncan cause the PE flag to be unexpectedly cleared.\nTable 147. Frame formats\nM bit\nPCE bit \nUSART frame(1)\n1.\nLegends: SB: start bit, STB: stop bit, PB: parity bit.\n0\n0\n| SB | 8 bit data | STB |\n0\n1\n| SB | 7-bit data | PB | STB |\n1\n0\n| SB | 9-bit data | STB |\n1\n1\n| SB | 8-bit data PB | STB |\n" }, { "page_number": 995, "page_indices": { "start_index": 1938427, "end_index": 1941043 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 995 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.8 LIN (local interconnection network) mode", 995 ], [ 4, "LIN transmission", 995 ], [ 4, "LIN reception", 995 ] ], "page_content": "RM0090 Rev 21\n995/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n30.3.8 \nLIN (local interconnection network) mode\nThe LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN \nmode, the following bits must be kept cleared:\n•\nSTOP[1:0] and CLKEN in the USART_CR2 register\n•\nSCEN, HDSEL and IREN in the USART_CR3 register.\nLIN transmission\nThe same procedure explained in Section 30.3.2 has to be applied for LIN Master \ntransmission than for normal USART transmission with the following differences:\n•\nClear the M bit to configure 8-bit word length.\n•\nSet the LINEN bit to enter LIN mode. In this case, setting the SBK bit sends 13 ‘0 bits \nas a break character. Then a bit of value ‘1 is sent to allow the next start detection.\nLIN reception\nA break detection circuit is implemented on the USART interface. The detection is totally \nindependent from the normal USART receiver. A break can be detected whenever it occurs, \nduring Idle state or during a frame.\nWhen the receiver is enabled (RE=1 in USART_CR1), the circuit looks at the RX input for a \nstart signal. The method for detecting start bits is the same when searching break \ncharacters or data. After a start bit has been detected, the circuit samples the next bits \nexactly like for the data (on the 8th, 9th and 10th samples). If 10 (when the LBDL = 0 in \nUSART_CR2) or 11 (when LBDL=1 in USART_CR2) consecutive bits are detected as ‘0, \nand are followed by a delimiter character, the LBD flag is set in USART_SR. If the LBDIE \nbit=1, an interrupt is generated. Before validating the break, the delimiter is checked for as it \nsignifies that the RX line has returned to a high level.\nIf a ‘1 is sampled before the 10 or 11 have occurred, the break detection circuit cancels the \ncurrent detection and searches for a start bit again. \nIf the LIN mode is disabled (LINEN=0), the receiver continues working as normal USART, \nwithout taking into account the break detection.\nIf the LIN mode is enabled (LINEN=1), as soon as a framing error occurs (stop bit detected \nat ‘0, which is the case for any break frame), the receiver stops until the break detection \ncircuit receives either a ‘1, if the break word was not complete, or a delimiter character if a \nbreak has been detected.\nThe behavior of the break detector state machine and the break flag is shown on the \nFigure 305: Break detection in LIN mode (11-bit break length - LBDL bit is set) on page 996.\nExamples of break frames are given on Figure 306: Break detection in LIN mode vs. \nFraming error detection on page 997.\n" }, { "page_number": 996, "page_indices": { "start_index": 1941043, "end_index": 1941968 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 996 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.8 LIN (local interconnection network) mode", 995 ], [ 4, "LIN reception", 995 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n996/1757\nRM0090 Rev 21\nFigure 305. Break detection in LIN mode (11-bit break length - LBDL bit is set)\nMSv40883V1\nIdle\nBit0\nBit1\nBit2 Bit3\nBit4\nBit5 Bit6\nBit7\nBit8\nBit9 Bit10\nIdle\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\nCase 1: break signal not long enough => break discarded, LBD is not set\nRX line\nCapture strobe\nBreak state \nmachine\nRead samples\nIdle\nBit0\nBit1\nBit2 Bit3\nBit4\nBit5 Bit6\nBit7\nBit8\nBit9 B10\nIdle\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nCase 2: break signal just long enough => break detected, LBD is set\nRX line\nCapture strobe\nBreak state \nmachine\nRead samples\nBreak frame\nBreak frame\nDelimiter is immediate\nLBD\nIdle\nBit0\nBit1\nBit2 Bit3\nBit4\nBit5 Bit6\nBit7\nBit8\nBit9 Bit10\nIdle\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nCase 3: break signal long enough => break detected, LBD is set\nRX line\nCapture strobe\nBreak state \nmachine\nRead samples\nBreak frame\nLBD\nwait delimiter\n" }, { "page_number": 997, "page_indices": { "start_index": 1941968, "end_index": 1944096 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 997 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.9 USART synchronous mode", 997 ] ], "page_content": "RM0090 Rev 21\n997/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nFigure 306. Break detection in LIN mode vs. Framing error detection\n30.3.9 \nUSART synchronous mode\nThe synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to \n1. In synchronous mode, the following bits must be kept cleared:\n•\nLINEN bit in the USART_CR2 register,\n•\nSCEN, HDSEL and IREN bits in the USART_CR3 register.\nThe USART allows the user to control a bidirectional synchronous serial communications in \nmaster mode. The CK pin is the output of the USART transmitter clock. No clock pulses are \nsent to the CK pin during start bit and stop bit. Depending on the state of the LBCL bit in the \nUSART_CR2 register clock pulses are generated or not during the last valid data bit \n(address mark). The CPOL bit in the USART_CR2 register allows the user to select the \nclock polarity, and the CPHA bit in the USART_CR2 register allows the user to select the \nphase of the external clock (see Figure 307, Figure 308 & Figure 309).\nDuring the Idle state, preamble and send break, the external CK clock is not activated.\nIn synchronous mode the USART transmitter works exactly like in asynchronous mode. But \nas CK is synchronized with TX (according to CPOL and CPHA), the data on TX is \nsynchronous.\nIn this mode the USART receiver works in a different manner compared to the \nasynchronous mode. If RE=1, the data is sampled on CK (rising or falling edge, depending \non CPOL and CPHA), without any oversampling. A setup and a hold time must be \nrespected (which depends on the baud rate: 1/16 bit time).\nNote:\nThe CK pin works in conjunction with the TX pin. Thus, the clock is provided only if the \ntransmitter is enabled (TE=1) and a data is being transmitted (the data register USART_DR \nMSv31157V1\ndata 1\nIDLE\nBREAK\ndata 2 (0x55)\ndata 3 (header)\n1 data time\n1 data time\nRX line\nRXNE /FE\nLBDF\nCase 1: break occurring after an Idle\ndata 1\ndata2\nBREAK\ndata 2 (0x55)\ndata 3 (header)\n1 data time\n1 data time\nRX line\nRXNE /FE\nLBDF\nCase 2: break occurring while data is being received\n" }, { "page_number": 998, "page_indices": { "start_index": 1944096, "end_index": 1945372 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 998 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.9 USART synchronous mode", 997 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n998/1757\nRM0090 Rev 21\nhas been written). This means that it is not possible to receive a synchronous data without \ntransmitting data.\nThe LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the \nreceiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. These \nbits should not be changed while the transmitter or the receiver is enabled.\nIt is advised that TE and RE are set in the same instruction in order to minimize the setup \nand the hold time of the receiver.\nThe USART supports master mode only: it cannot receive or send data related to an input \nclock (CK is always an output).\nFigure 307. USART example of synchronous transmission\nFigure 308. USART data clock timing diagram (M=0)\nMSv31158V2\nUSART\nSynchronous device\n(slave SPI)\nRX\nTX\nData out\nData in \nClock\nCK\nMSv31159V2\n0\n1\n2\n3\n4\n5\n6\n7\n0\n1\n2\n3\n4\n5\n6\n7\n*\n*\n*\n*\nMSB\nMSB\nLSB\nLSB\nStart\nStart\nStop\nIdle or preceding \ntransmission\nIdle or next \ntransmission\n*\n*LBCL bit controls last data pulse\nCapture strobe\nData on RX \n(from slave)\nData on TX \n(from master)\nClock (CPOL=1, \nCPHA=1\nClock (CPOL=1, \nCPHA=0\nClock (CPOL=0, \nCPHA=1\nClock (CPOL=0, \nCPHA=0\nStop\nM=0 (8 data bits)\n" }, { "page_number": 999, "page_indices": { "start_index": 1945372, "end_index": 1946754 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 999 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.10 Single-wire half-duplex communication", 999 ] ], "page_content": "RM0090 Rev 21\n999/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nFigure 309. USART data clock timing diagram (M=1)\nFigure 310. RX data setup/hold time\nNote:\nThe function of CK is different in Smartcard mode. Refer to the Smartcard mode chapter for \nmore details.\n30.3.10 \nSingle-wire half-duplex communication \nThe single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3 \nregister. In this mode, the following bits must be kept cleared:\n•\nLINEN and CLKEN bits in the USART_CR2 register,\n•\nSCEN and IREN bits in the USART_CR3 register.\nThe USART can be configured to follow a single-wire half-duplex protocol where the TX and \nRX lines are internally connected. The selection between half- and full-duplex \ncommunication is made with a control bit ‘HALF DUPLEX SEL’ (HDSEL in USART_CR3).\nMSv31160V1\n0\n1\n2\n3\n4\n5\n6\n8\n0\n1\n2\n3\n4\n5\n6\n8\n*\n*\n*\n*\nMSB\nMSB\nLSB\nLSB\nStart\nStart\nStop\nIdle or \npreceding \ntransmission\nIdle or next \ntransmission\n*\n*LBCL bit controls last data pulse\nCapture \nstrobe\nData on RX \n(from slave)\nData on TX \n(from master)\nClock (CPOL=1, \nCPHA=1\nClock (CPOL=1, \nCPHA=0\nClock (CPOL=0, \nCPHA=1\nClock (CPOL=0, \nCPHA=0\nStop\nM=1 (9 data bits)\n7\n7\nMSv31161V2\nData on RX (from slave)\nCK\n(capture strobe on CK rising \nedge in this example)\nValid DATA bit\ntSETUP\ntHOLD\ntSETUP=tHOLD 1/16 bit time\n" }, { "page_number": 1000, "page_indices": { "start_index": 1946754, "end_index": 1949190 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1000 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.11 Smartcard", 1000 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1000/1757\nRM0090 Rev 21\nAs soon as HDSEL is written to 1:\n•\nthe TX and RX lines are internally connected\n•\nthe RX pin is no longer used\n•\nthe TX pin is always released when no data is transmitted. Thus, it acts as a standard \nI/O in idle or in reception. It means that the I/O must be configured so that TX is \nconfigured as floating input (or output high open-drain) when not driven by the USART.\nApart from this, the communications are similar to what is done in normal USART mode. \nThe conflicts on the line must be managed by the software (by the use of a centralized \narbiter, for instance). In particular, the transmission is never blocked by hardware and \ncontinue to occur as soon as a data is written in the data register while the TE bit is set.\n30.3.11 \nSmartcard\nThe Smartcard mode is selected by setting the SCEN bit in the USART_CR3 register. In \nsmartcard mode, the following bits must be kept cleared:\n•\nLINEN bit in the USART_CR2 register,\n•\nHDSEL and IREN bits in the USART_CR3 register.\nMoreover, the CLKEN bit may be set in order to provide a clock to the smartcard.\nThe Smartcard interface is designed to support asynchronous protocol Smartcards as \ndefined in the ISO 7816-3 standard. The USART should be configured as:\n•\n8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register\n•\n1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 \nregister. \nNote:\nIt is also possible to choose 0.5 stop bit for receiving but it is recommended to use 1.5 stop \nbits for both transmitting and receiving to avoid switching between the two configurations.\nFigure 311 shows examples of what can be seen on the data line with and without parity \nerror. \nFigure 311. ISO 7816-3 asynchronous protocol\nWhen connected to a Smartcard, the TX output of the USART drives a bidirectional line that \nis also driven by the Smartcard. The TX pin must be configured as open-drain.\nSmartcard is a single wire half duplex communication protocol.\n•\nTransmission of data from the transmit shift register is guaranteed to be delayed by a \nminimum of 1/2 baud clock. In normal operation a full transmit shift register starts \nMSv31162V1\nWithout Parity error\np\n7\n6\n5\n4\n3\n2\n1\n0\nS\nGuard time\nWithParity error\np\n7\n6\n5\n4\n3\n2\n1\n0\nS\nGuard time\nStart bit\nStart bit\nLine pulled low by receiver \nduring stop in case of parity error\n" }, { "page_number": 1001, "page_indices": { "start_index": 1949190, "end_index": 1952092 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1001 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.11 Smartcard", 1000 ] ], "page_content": "RM0090 Rev 21\n1001/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nshifting on the next baud clock edge. In Smartcard mode this transmission is further \ndelayed by a guaranteed 1/2 baud clock.\n•\nIf a parity error is detected during reception of a frame programmed with a 0.5 or 1.5 \nstop bit period, the transmit line is pulled low for a baud clock period after the \ncompletion of the receive frame. This is to indicate to the Smartcard that the data \ntransmitted to USART has not been correctly received. This NACK signal (pulling \ntransmit line low for 1 baud clock) causes a framing error on the transmitter side \n(configured with 1.5 stop bits). The application can handle re-sending of data according \nto the protocol. A parity error is ‘NACK’ed by the receiver if the NACK control bit is set, \notherwise a NACK is not transmitted.\n•\nThe assertion of the TC flag can be delayed by programming the Guard Time register. \nIn normal operation, TC is asserted when the transmit shift register is empty and no \nfurther transmit requests are outstanding. In Smartcard mode an empty transmit shift \nregister triggers the guard time counter to count up to the programmed value in the \nGuard Time register. TC is forced low during this time. When the guard time counter \nreaches the programmed value TC is asserted high.\n•\nThe de-assertion of TC flag is unaffected by Smartcard mode.\n•\nIf a framing error is detected on the transmitter end (due to a NACK from the receiver), \nthe NACK is not detected as a start bit by the receive block of the transmitter. \nAccording to the ISO protocol, the duration of the received NACK can be 1 or 2 baud \nclock periods.\n•\nOn the receiver side, if a parity error is detected and a NACK is transmitted the receiver \ndoes not detect the NACK as a start bit.\nNote:\nA break character is not significant in Smartcard mode. A 0x00 data with a framing error is \ntreated as data and not as a break. \nNo Idle frame is transmitted when toggling the TE bit. The Idle frame (as defined for the \nother configurations) is not defined by the ISO protocol.\nFigure 312 details how the NACK signal is sampled by the USART. In this example the \nUSART is transmitting a data and is configured with 1.5 stop bits. The receiver part of the \nUSART is enabled in order to check the integrity of the data and the NACK signal.\nFigure 312. Parity error detection using the 1.5 stop bits\nThe USART can provide a clock to the smartcard through the CK output. In smartcard \nmode, CK is not associated to the communication but is simply derived from the internal \nperipheral input clock through a 5-bit prescaler. The division ratio is configured in the \nMSv31163V1\nBit 7\nParity bit\n1.5 Stop bit\n1 bit time\n1.5 bit time\n0.5 bit time\nSampling at \n8th, 9th, 10th\nSampling at \n8th, 9th, 10th\nSampling at \n8th, 9th, 10th\nSampling at \n8th, 9th, 10th\n" }, { "page_number": 1002, "page_indices": { "start_index": 1952092, "end_index": 1955117 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1002 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.12 IrDA SIR ENDEC block", 1002 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1002/1757\nRM0090 Rev 21\nprescaler register USART_GTPR. CK frequency can be programmed from fCK/2 to fCK/62, \nwhere fCK is the peripheral input clock.\n30.3.12 \nIrDA SIR ENDEC block \nThe IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA \nmode, the following bits must be kept cleared:\n•\nLINEN, STOP and CLKEN bits in the USART_CR2 register,\n•\nSCEN and HDSEL bits in the USART_CR3 register.\nThe IrDA SIR physical layer specifies use of a Return to Zero, Inverted (RZI) modulation \nscheme that represents logic 0 as an infrared light pulse (see Figure 313).\nThe SIR Transmit encoder modulates the Non Return to Zero (NRZ) transmit bit stream \noutput from USART. The output pulse stream is transmitted to an external output driver and \ninfrared LED. USART supports only bit rates up to 115.2Kbps for the SIR ENDEC. In normal \nmode the transmitted pulse width is specified as 3/16 of a bit period.\nThe SIR receive decoder demodulates the return-to-zero bit stream from the infrared \ndetector and outputs the received NRZ serial bit stream to USART. The decoder input is \nnormally HIGH (marking state) in the Idle state. The transmit encoder output has the \nopposite polarity to the decoder input. A start bit is detected when the decoder input is low.\n•\nIrDA is a half duplex communication protocol. If the Transmitter is busy (i.e. the USART \nis sending data to the IrDA encoder), any data on the IrDA receive line is ignored by the \nIrDA decoder and if the Receiver is busy (USART is receiving decoded data from the \nUSART), data on the TX from the USART to IrDA is not encoded by IrDA. While \nreceiving data, transmission should be avoided as the data to be transmitted could be \ncorrupted.\n•\nA ‘0 is transmitted as a high pulse and a ‘1 is transmitted as a ‘0. The width of the pulse \nis specified as 3/16th of the selected bit period in normal mode (see Figure 314).\n•\nThe SIR decoder converts the IrDA compliant receive signal into a bit stream for \nUSART.\n•\nThe SIR receive logic interprets a high state as a logic one and low pulses as logic \nzeros.\n•\nThe transmit encoder output has the opposite polarity to the decoder input. The SIR \noutput is in low state when Idle.\n•\nThe IrDA specification requires the acceptance of pulses greater than 1.41 us. The \nacceptable pulse width is programmable. Glitch detection logic on the receiver end \nfilters out pulses of width less than 2 PSC periods (PSC is the prescaler value \nprogrammed in the IrDA low-power Baud Register, USART_GTPR). Pulses of width \nless than 1 PSC period are always rejected, but those of width greater than one and \nless than two periods may be accepted or rejected, those greater than 2 periods are \naccepted as a pulse. The IrDA encoder/decoder does not work when PSC = 0.\n•\nThe receiver can communicate with a low-power transmitter.\n•\nIn IrDA mode, the STOP bits in the USART_CR2 register must be configured to “1 stop \nbit”.\n" }, { "page_number": 1003, "page_indices": { "start_index": 1955117, "end_index": 1956510 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1003 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.12 IrDA SIR ENDEC block", 1002 ], [ 4, "IrDA low-power mode", 1003 ] ], "page_content": "RM0090 Rev 21\n1003/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nIrDA low-power mode \nTransmitter:\nIn low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the \nwidth of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz. \nGenerally this value is 1.8432 MHz (1.42 MHz < PSC< 2.12 MHz). A low-power mode \nprogrammable divisor divides the system clock to achieve this value.\nReceiver:\nReceiving in low-power mode is similar to receiving in normal mode. For glitch detection the \nUSART should discard pulses of duration shorter than 1/PSC. A valid low is accepted only if \nits duration is greater than 2 periods of the IrDA low-power Baud clock (PSC value in \nUSART_GTPR).\nNote:\nA pulse of width less than two and greater than one PSC period(s) may or may not be \nrejected.\nThe receiver set up time should be managed by software. The IrDA physical layer \nspecification specifies a minimum of 10 ms delay between transmission and reception (IrDA \nis a half duplex protocol).\nFigure 313. IrDA SIR ENDEC- block diagram\nFigure 314. IrDA data modulation (3/16) -Normal mode\nMSv31164V\nUSART\nIrDA\nUSART\nSIR\nTransmit\nEncoder\nSIR\nReceive\nDEcoder\nTX\nSIREN\nRX\nUSART_RX\nUSART_TX\nMSv31165V1\nTX\nStart \nbit\n0\n1\n0\n1\n0\n0\n1\n1\n0\n1\nStop \nbit\nBit period\nIrDA_OUT\nIrDA_IN\nRX\n3/16\n0\n1\n0\n1\n0\n0\n1\n1\n0\n1\n" }, { "page_number": 1004, "page_indices": { "start_index": 1956510, "end_index": 1958562 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1004 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.13 Continuous communication using DMA", 1004 ], [ 4, "Transmission using DMA", 1004 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1004/1757\nRM0090 Rev 21\n30.3.13 \nContinuous communication using DMA\nThe USART is capable of continuous communication using the DMA. The DMA requests for \nRx buffer and Tx buffer are generated independently.\nTransmission using DMA\nDMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 \nregister. Data is loaded from a SRAM area configured using the DMA peripheral (refer to the \nDMA specification) to the USART_DR register whenever the TXE bit is set. To map a DMA \nchannel for USART transmission, use the following procedure (x denotes the channel \nnumber):\n1.\nWrite the USART_DR register address in the DMA control register to configure it as the \ndestination of the transfer. The data are moved to this address from memory after each \nTXE event.\n2. \nWrite the memory address in the DMA control register to configure it as the source of \nthe transfer. The data are loaded into the USART_DR register from this memory area \nafter each TXE event.\n3. \nConfigure the total number of bytes to be transferred to the DMA control register.\n4. \nConfigure the channel priority in the DMA register\n5. \nConfigure DMA interrupt generation after half/ full transfer as required by the \napplication.\n6. \nClear the TC bit in the SR register by writing 0 to it.\n7. \nActivate the channel in the DMA register.\nWhen the number of data transfers programmed in the DMA Controller is reached, the DMA \ncontroller generates an interrupt on the DMA channel interrupt vector.\nIn transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag \nis set in the DMA_ISR register), the TC flag can be monitored to make sure that the USART \ncommunication is complete. This is required to avoid corrupting the last transmission before \ndisabling the USART or entering the Stop mode. The software must wait until TC=1. The TC \nflag remains cleared during all data transfers and it is set by hardware at the last frame’s \nend of transmission.\n" }, { "page_number": 1005, "page_indices": { "start_index": 1958562, "end_index": 1960584 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1005 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.13 Continuous communication using DMA", 1004 ], [ 4, "Reception using DMA", 1005 ] ], "page_content": "RM0090 Rev 21\n1005/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nFigure 315. Transmission using DMA\nReception using DMA\nDMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register. \nData is loaded from the USART_DR register to a SRAM area configured using the DMA \nperipheral (refer to the DMA specification) whenever a data byte is received. To map a DMA \nchannel for USART reception, use the following procedure:\n1.\nWrite the USART_DR register address in the DMA control register to configure it as the \nsource of the transfer. The data are moved from this address to the memory after each \nRXNE event.\n2. \nWrite the memory address in the DMA control register to configure it as the destination \nof the transfer. The data are loaded from USART_DR to this memory area after each \nRXNE event.\n3. \nConfigure the total number of bytes to be transferred in the DMA control register.\n4. \nConfigure the channel priority in the DMA control register\n5. \nConfigure interrupt generation after half/ full transfer as required by the application.\n6. \nActivate the channel in the DMA control register.\nWhen the number of data transfers programmed in the DMA Controller is reached, the DMA \ncontroller generates an interrupt on the DMA channel interrupt vector. The DMAR bit should \nbe cleared by software in the USART_CR3 register during the interrupt subroutine.\nTX line\nUSART_DR\nFrame 1\nTXE flag\nF2\nTC flag\nF3\nFrame 2\nsoftware waits until TC=1\nFrame 3\nset by hardware\ncleared by DMA read\nset by hardware\ncleared by DMA read\nset by hardware\nset \nIdle preamble\nby hardware\nF1\nsoftware configures \nthe DMA to send 3 \ndata and enables the \nUSART\nDMA request\nignored by the DMA \nDMA writes\nflag DMA TCIF \nset by hardware\nclear \nby software\n USART_DR\nbecause DMA transfer is complete\nDMA writes F1 \ninto \nUSART_DR\nDMA writes F2 \ninto \nUSART_DR\nDMA writes F3 \ninto \nUSART_DR.\nThe DMA transfer \nis complete \n(TCIF=1 in \nDMA_ISR)\n(Transfer complete)\nai17192b\n" }, { "page_number": 1006, "page_indices": { "start_index": 1960584, "end_index": 1962202 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1006 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.13 Continuous communication using DMA", 1004 ], [ 4, "Error flagging and interrupt generation in multibuffer communication", 1006 ], [ 3, "30.3.14 Hardware flow control", 1006 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1006/1757\nRM0090 Rev 21\nFigure 316. Reception using DMA\nError flagging and interrupt generation in multibuffer communication \nIn case of multibuffer communication if any error occurs during the transaction the error flag \nis asserted after the current byte. An interrupt is generated if the interrupt enable flag is set. \nFor framing error, overrun error and noise flag which are asserted with RXNE in case of \nsingle byte reception, there is a separate error flag interrupt enable bit (EIE bit in the \nUSART_CR3 register), which if set, issues an interrupt after the current byte with either of \nthese errors.\n30.3.14 \nHardware flow control\nIt is possible to control the serial data flow between 2 devices by using the CTS input and \nthe RTS output. The Figure 317 shows how to connect 2 devices in this mode:\nFigure 317. Hardware flow control between 2 USARTs\nRTS and CTS flow control can be enabled independently by writing respectively RTSE and \nCTSE bits to 1 (in the USART_CR3 register).\nTX line\nUSART_DR\nFrame 1\nRXNE flag\nF2\nF3\nFrame 2\nFrame 3\nset by hardware\ncleared by DMA read\nF1\nsoftware configures the \nDMA to receive 3 data \nblocks and enables\nthe USART\nDMA request\nDMA reads USART_DR\nDMA TCIF flag\nset by hardware\ncleared \nby software\nDMA reads F1 \nfrom \nUSART_DR\n(Transfer complete)\nDMA reads F2 \nfrom \nUSART_DR\nDMA reads F3 \nfrom \nUSART_DR\nThe DMA transfer \nis complete \n(TCIF=1 in \nDMA_ISR)\nai17193b\nMSv31169V2\nTX circuit\nUSART 1\nTX \nRX circuit\nRX circuit\nUSART 2\nTX circuit\nTX \nCTS\nCTS\nRTS\nRX \nRTS\nRX \n" }, { "page_number": 1007, "page_indices": { "start_index": 1962202, "end_index": 1963629 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1007 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.14 Hardware flow control", 1006 ], [ 4, "RTS flow control", 1007 ], [ 4, "CTS flow control", 1007 ] ], "page_content": "RM0090 Rev 21\n1007/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nRTS flow control\nIf the RTS flow control is enabled (RTSE=1), then RTS is asserted (tied low) as long as the \nUSART receiver is ready to receive a new data. When the receive register is full, RTS is \ndeasserted, indicating that the transmission is expected to stop at the end of the current \nframe. Figure 318 shows an example of communication with RTS flow control enabled.\nFigure 318. RTS flow control\nCTS flow control\nIf the CTS flow control is enabled (CTSE=1), then the transmitter checks the CTS input \nbefore transmitting the next frame. If CTS is asserted (tied low), then the next data is \ntransmitted (assuming that a data is to be transmitted, in other words, if TXE=0), else the \ntransmission does not occur. When CTS is deasserted during a transmission, the current \ntransmission is completed before the transmitter stops.\nWhen CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the CTS \ninput toggles. It indicates when the receiver becomes ready or not ready for communication. \nAn interrupt is generated if the CTSIE bit in the USART_CR3 register is set. The figure \nbelow shows an example of communication with CTS flow control enabled.\nMSv68794V1\nStart\nbit\nStart\nbit\nStop\nbit Idle\nStop\nbit\nRX\nRTS\nData 1 read \nData 2 can now be transmitted\nRXNE\nRXNE\nData 1\nData 2\n" }, { "page_number": 1008, "page_indices": { "start_index": 1963629, "end_index": 1964133 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1008 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.3 USART functional description", 969 ], [ 3, "30.3.14 Hardware flow control", 1006 ], [ 4, "CTS flow control", 1007 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1008/1757\nRM0090 Rev 21\nFigure 319. CTS flow control\nNote:\nSpecial behavior of break frames: when the CTS flow is enabled, the transmitter does not \ncheck the CTS input state to send a break.\nMSv68793V1\nStart\nbit\nStop\nbit\nTX\nTDR\nCTS\nData 1\nData 2\nStop\nbit Idle Start\nbit\nData 2\nData 3\nData 3\nempty\nempty\nCTS\nCTS\nTransmit data register\nWriting data 3 in TDR\nTransmission of Data 3 is \ndelayed until CTS = 0 \n" }, { "page_number": 1009, "page_indices": { "start_index": 1964133, "end_index": 1965376 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1009 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.4 USART interrupts", 1009 ] ], "page_content": "RM0090 Rev 21\n1009/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n30.4 \nUSART interrupts\n \nThe USART interrupt events are connected to the same interrupt vector (see Figure 320).\n•\nDuring transmission: Transmission Complete, Clear to Send or Transmit Data Register \nempty interrupt.\n•\nWhile receiving: Idle Line detection, Overrun error, Receive Data register not empty, \nParity error, LIN break detection, Noise Flag (only in multi buffer communication) and \nFraming Error (only in multi buffer communication).\nThese events generate an interrupt if the corresponding Enable Control Bit is set.\nFigure 320. USART interrupt mapping diagram \nTable 148. USART interrupt requests\nInterrupt event\nEvent flag\nEnable control \nbit\nTransmit Data Register Empty\nTXE\nTXEIE\nCTS flag\nCTS\nCTSIE\nTransmission Complete\nTC\nTCIE\nReceived Data Ready to be Read\nRXNE\nRXNEIE\nOverrun Error Detected\nORE\nIdle Line Detected\nIDLE\nIDLEIE\nParity Error\nPE\nPEIE\nBreak Flag\nLBD\nLBDIE\nNoise Flag, Overrun error and Framing Error in multibuffer \ncommunication\nNF or ORE or FE EIE\nMSv42089V1\nTC\nTCIE\nTXE\nTXEIE\nCTSIF\nCTSIE\nIDLE\nIDLEIE\nRXNEIE\nORE\nRXNEIE\nRXNE\nPE\nPEIE\nLBD\nLBDIE\nFE\nNE\nORE\nEIE\nUSART \ninterrupt\nDMAR\n" }, { "page_number": 1010, "page_indices": { "start_index": 1965376, "end_index": 1966449 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1010 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.5 USART mode configuration", 1010 ], [ 2, "30.6 USART registers", 1010 ], [ 3, "30.6.1 Status register (USART_SR)", 1010 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1010/1757\nRM0090 Rev 21\n30.5 \nUSART mode configuration\n \n30.6 \nUSART registers\nRefer to Section 1.1: List of abbreviations for registers for registers for a list of abbreviations \nused in register descriptions.\nThe peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).\n30.6.1 \nStatus register (USART_SR)\nAddress offset: 0x00\nReset value: 0x000C0 00C0\nTable 149. USART mode configuration(1)\n1.\nX = supported; NA = not applicable.\nUSART modes\nUSART\n1\nUSART\n2\nUSART\n3\nUART4\nUART5\nUSART\n6\nAsynchronous mode\nX\nX\nX\nX\nX\nX\nHardware flow control\nX\nX\nX\nNA\nNA\nX\nMultibuffer communication (DMA)\nX\nX\nX\nX\nX\nX\nMultiprocessor communication\nX\nX\nX\nX\nX\nX\nSynchronous\nX\nX\nX\nNA\nNA\nX\nSmartcard\nX\nX\nX\nNA\nNA\nX\nHalf-duplex (single-wire mode)\nX\nX\nX\nX\nX\nX\nIrDA\nX\nX\nX\nX\nX\nX\nLIN\nX\nX\nX\nX\nX\nX\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCTS\nLBD\nTXE\nTC\nRXNE\nIDLE\nORE\nNF\nFE\nPE\nrc_w0\nrc_w0\nr\nrc_w0\nrc_w0\nr\nr\nr\nr\nr\n" }, { "page_number": 1011, "page_indices": { "start_index": 1966449, "end_index": 1969148 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1011 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.6 USART registers", 1010 ], [ 3, "30.6.1 Status register (USART_SR)", 1010 ] ], "page_content": "RM0090 Rev 21\n1011/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n \nBits 31:10 Reserved, must be kept at reset value\nBit 9 CTS: CTS flag\nThis bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by \nsoftware (by writing it to 0). An interrupt is generated if CTSIE=1 in the USART_CR3 \nregister.\n0: No change occurred on the CTS status line\n1: A change occurred on the CTS status line\nNote: This bit is not available for UART4 & UART5.\nBit 8 LBD: LIN break detection flag\nThis bit is set by hardware when the LIN break is detected. It is cleared by software (by \nwriting it to 0). An interrupt is generated if LBDIE = 1 in the USART_CR2 register.\n0: LIN Break not detected\n1: LIN break detected\nNote: An interrupt is generated when LBD=1 if LBDIE=1\nBit 7 TXE: Transmit data register empty\nThis bit is set by hardware when the content of the TDR register has been transferred into \nthe shift register. An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register. It \nis cleared by a write to the USART_DR register.\n0: Data is not transferred to the shift register\n1: Data is transferred to the shift register)\nNote: This bit is used during single buffer transmission.\nBit 6 TC: Transmission complete\nThis bit is set by hardware if the transmission of a frame containing data is complete and if \nTXE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by \na software sequence (a read from the USART_SR register followed by a write to the \nUSART_DR register). The TC bit can also be cleared by writing a '0' to it. This clearing \nsequence is recommended only for multibuffer communication.\n0: Transmission is not complete\n1: Transmission is complete\nBit 5 RXNE: Read data register not empty\nThis bit is set by hardware when the content of the RDR shift register has been transferred \nto the USART_DR register. An interrupt is generated if RXNEIE=1 in the USART_CR1 \nregister. It is cleared by a read to the USART_DR register. The RXNE flag can also be \ncleared by writing a zero to it. This clearing sequence is recommended only for multibuffer \ncommunication.\n0: Data is not received\n1: Received data is ready to be read.\nBit 4 IDLE: IDLE line detected\nThis bit is set by hardware when an Idle Line is detected. An interrupt is generated if the \nIDLEIE=1 in the USART_CR1 register. It is cleared by a software sequence (an read to the \nUSART_SR register followed by a read to the USART_DR register). \n0: No Idle Line is detected\n1: Idle Line is detected\nNote: The IDLE bit is not set again until the RXNE bit has been set itself (a new idle line \noccurs).\n" }, { "page_number": 1012, "page_indices": { "start_index": 1969148, "end_index": 1971705 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1012 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.6 USART registers", 1010 ], [ 3, "30.6.1 Status register (USART_SR)", 1010 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1012/1757\nRM0090 Rev 21\nBit 3 ORE: Overrun error\nThis bit is set by hardware when the word currently being received in the shift register is \nready to be transferred into the RDR register while RXNE=1. An interrupt is generated if \nRXNEIE=1 in the USART_CR1 register. It is cleared by a software sequence (an read to the \nUSART_SR register followed by a read to the USART_DR register).\n0: No Overrun error\n1: Overrun error is detected\nNote: When this bit is set, the RDR register content is not lost but the shift register is \noverwritten. An interrupt is generated on ORE flag in case of Multi Buffer \ncommunication if the EIE bit is set.\nBit 2 NF: Noise detected flag\nThis bit is set by hardware when noise is detected on a received frame. It is cleared by a \nsoftware sequence (an read to the USART_SR register followed by a read to the \nUSART_DR register).\n0: No noise is detected\n1: Noise is detected\nNote: This bit does not generate interrupt as it appears at the same time as the RXNE bit \nwhich itself generates an interrupting interrupt is generated on NF flag in case of Multi \nBuffer communication if the EIE bit is set.\nNote: When the line is noise-free, the NF flag can be disabled by programming the ONEBIT \nbit to 1 to increase the USART tolerance to deviations (Refer to Section 30.3.5: USART \nreceiver tolerance to clock deviation on page 991).\nBit 1 FE: Framing error\nThis bit is set by hardware when a de-synchronization, excessive noise or a break character \nis detected. It is cleared by a software sequence (an read to the USART_SR register \nfollowed by a read to the USART_DR register).\n0: No Framing error is detected\n1: Framing error or break character is detected\nNote: This bit does not generate interrupt as it appears at the same time as the RXNE bit \nwhich itself generates an interrupt. If the word currently being transferred causes both \nframe error and overrun error, it is transferred and only the ORE bit is set.\nAn interrupt is generated on FE flag in case of Multi Buffer communication if the EIE bit \nis set.\nBit 0 PE: Parity error\nThis bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a \nsoftware sequence (a read from the status register followed by a read or write access to the \nUSART_DR data register). The software must wait for the RXNE flag to be set before \nclearing the PE bit.\nAn interrupt is generated if PEIE = 1 in the USART_CR1 register.\n0: No parity error\n1: Parity error\n" }, { "page_number": 1013, "page_indices": { "start_index": 1971705, "end_index": 1973842 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1013 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.6 USART registers", 1010 ], [ 3, "30.6.2 Data register (USART_DR)", 1013 ], [ 3, "30.6.3 Baud rate register (USART_BRR)", 1013 ], [ 3, "30.6.4 Control register 1 (USART_CR1)", 1013 ] ], "page_content": "RM0090 Rev 21\n1013/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n30.6.2 \nData register (USART_DR)\nAddress offset: 0x04\nReset value: 0xXXXX XXXX \n30.6.3 \nBaud rate register (USART_BRR)\nNote:\nThe baud counters stop counting if the TE or RE bits are disabled respectively.\nAddress offset: 0x08\nReset value: 0x0000 0000\n \n30.6.4 \nControl register 1 (USART_CR1)\nAddress offset: 0x0C\nReset value: 0x0000 0000\nBits 31:9 Reserved, must be kept at reset value\nBits 8:0 DR[8:0]: Data value\nContains the Received or Transmitted data character, depending on whether it is read from \nor written to.\nThe Data register performs a double function (read and write) since it is composed of two \nregisters, one for transmission (TDR) and one for reception (RDR)\nThe TDR register provides the parallel interface between the internal bus and the output shift \nregister (see Figure 296: USART block diagram).\nThe RDR register provides the parallel interface between the input shift register and the \ninternal bus.\nWhen transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the \nvalue written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because \nit is replaced by the parity.\nWhen receiving with the parity enabled, the value read in the MSB bit is the received parity \nbit.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDIV_Mantissa[11:0]\nDIV_Fraction[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value\nBits 15:4 DIV_Mantissa[11:0]: mantissa of USARTDIV\nThese 12 bits define the mantissa of the USART Divider (USARTDIV)\nBits 3:0 DIV_Fraction[3:0]: fraction of USARTDIV\nThese 4 bits define the fraction of the USART Divider (USARTDIV). When OVER8=1, the \nDIV_Fraction3 bit is not considered and must be kept cleared.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOVER8\nReserved\nUE\nM\nWAKE\nPCE\nPS\nPEIE\nTXEIE\nTCIE\nRXNEIE\nIDLEIE\nTE\nRE\nRWU\nSBK\nrw\nRes.\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1014, "page_indices": { "start_index": 1973842, "end_index": 1976208 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1014 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.6 USART registers", 1010 ], [ 3, "30.6.4 Control register 1 (USART_CR1)", 1013 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1014/1757\nRM0090 Rev 21\n \nBits 31:16 Reserved, must be kept at reset value\nBit 15 OVER8: Oversampling mode\n0: oversampling by 16\n1: oversampling by 8\nNote: Oversampling by 8 is not available in the Smartcard, IrDA and LIN modes: when \nSCEN=1,IREN=1 or LINEN=1 then OVER8 is forced to ‘0 by hardware.\nBit 14 Reserved, must be kept at reset value\nBit 13 UE: USART enable\nWhen this bit is cleared, the USART prescalers and outputs are stopped and the end of the \ncurrent byte transfer in order to reduce power consumption. This bit is set and cleared by \nsoftware.\n0: USART prescaler and outputs disabled\n1: USART enabled\nBit 12 M: Word length\nThis bit determines the word length. It is set or cleared by software.\n0: 1 Start bit, 8 Data bits, n Stop bit\n1: 1 Start bit, 9 Data bits, n Stop bit\nNote: The M bit must not be modified during a data transfer (both transmission and reception)\nBit 11 WAKE: Wake-up method\nThis bit determines the USART wake-up method, it is set or cleared by software.\n0: Idle Line\n1: Address Mark\nBit 10 PCE: Parity control enable\nThis bit selects the hardware parity control (generation and detection). When the parity \ncontrol is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit \nif M=0) and parity is checked on the received data. This bit is set and cleared by software. \nOnce it is set, PCE is active after the current byte (in reception and in transmission).\n0: Parity control disabled\n1: Parity control enabled\nBit 9 PS: Parity selection\nThis bit selects the odd or even parity when the parity generation/detection is enabled (PCE \nbit set). It is set and cleared by software. The parity is selected after the current byte.\n0: Even parity\n1: Odd parity\nBit 8 PEIE: PE interrupt enable\nThis bit is set and cleared by software.\n0: Interrupt is inhibited\n1: An USART interrupt is generated whenever PE=1 in the USART_SR register\nBit 7 TXEIE: TXE interrupt enable\nThis bit is set and cleared by software.\n0: Interrupt is inhibited\n1: An USART interrupt is generated whenever TXE=1 in the USART_SR register\nBit 6 TCIE: Transmission complete interrupt enable\nThis bit is set and cleared by software.\n0: Interrupt is inhibited\n1: An USART interrupt is generated whenever TC=1 in the USART_SR register\n" }, { "page_number": 1015, "page_indices": { "start_index": 1976208, "end_index": 1978082 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1015 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.6 USART registers", 1010 ], [ 3, "30.6.4 Control register 1 (USART_CR1)", 1013 ] ], "page_content": "RM0090 Rev 21\n1015/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nBit 5 RXNEIE: RXNE interrupt enable\nThis bit is set and cleared by software.\n0: Interrupt is inhibited\n1: An USART interrupt is generated whenever ORE=1 or RXNE=1 in the USART_SR \nregister\nBit 4 IDLEIE: IDLE interrupt enable\nThis bit is set and cleared by software.\n0: Interrupt is inhibited\n1: An USART interrupt is generated whenever IDLE=1 in the USART_SR register\nBit 3 TE: Transmitter enable\nThis bit enables the transmitter. It is set and cleared by software. \n0: Transmitter is disabled\n1: Transmitter is enabled\nNote: During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble \n(idle line) after the current word, except in smartcard mode.\nWhen TE is set, there is a 1 bit-time delay before the transmission starts.\nBit 2 RE: Receiver enable\nThis bit enables the receiver. It is set and cleared by software. \n0: Receiver is disabled\n1: Receiver is enabled and begins searching for a start bit\nBit 1 RWU: Receiver wake-up\nThis bit determines if the USART is in mute mode or not. It is set and cleared by software \nand can be cleared by hardware when a wake-up sequence is recognized. \n0: Receiver in active mode\n1: Receiver in mute mode\nNote: Before selecting Mute mode (by setting the RWU bit) the USART must first receive a \ndata byte, otherwise it cannot function in Mute mode with wake-up by Idle line \ndetection.\nIn Address Mark Detection wake-up configuration (WAKE bit=1) the RWU bit cannot be \nmodified by software while the RXNE bit is set.\nBit 0 SBK: Send break\nThis bit set is used to send break characters. It can be set and cleared by software. It should \nbe set by software, and is reset by hardware during the stop bit of break.\n0: No break character is transmitted.\n1: Break character is transmitted.\n" }, { "page_number": 1016, "page_indices": { "start_index": 1978082, "end_index": 1979994 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1016 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.6 USART registers", 1010 ], [ 3, "30.6.5 Control register 2 (USART_CR2)", 1016 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1016/1757\nRM0090 Rev 21\n30.6.5 \nControl register 2 (USART_CR2)\nAddress offset: 0x10\nReset value: 0x0000 0000 \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nLINEN\nSTOP[1:0]\nCLKEN\nCPOL\nCPHA\nLBCL\nRes.\nLBDIE\nLBDL\nRes.\nADD[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:15 Reserved, must be kept at reset value\nBit 14 LINEN: LIN mode enable\nThis bit is set and cleared by software.\n0: LIN mode disabled\n1: LIN mode enabled\nThe LIN mode enables the capability to send LIN Synch Breaks (13 low bits) using the SBK bit in \nthe USART_CR1 register, and to detect LIN Sync breaks.\nBits 13:12 STOP: STOP bits\nThese bits are used for programming the stop bits.\n00: 1 Stop bit\n01: 0.5 Stop bit\n10: 2 Stop bits\n11: 1.5 Stop bit\nNote: The 0.5 Stop bit and 1.5 Stop bit are not available for UART4 & UART5.\nBit 11 CLKEN: Clock enable\nThis bit allows the user to enable the CK pin.\n0: CK pin disabled\n1: CK pin enabled\nThis bit is not available for UART4 & UART5.\nBit 10 CPOL: Clock polarity\nThis bit allows the user to select the polarity of the clock output on the CK pin in synchronous mode. \nIt works in conjunction with the CPHA bit to produce the desired clock/data relationship \n0: Steady low value on CK pin outside transmission window.\n1: Steady high value on CK pin outside transmission window.\nThis bit is not available for UART4 & UART5.\nBit 9 CPHA: Clock phase\nThis bit allows the user to select the phase of the clock output on the CK pin in synchronous mode. \nIt works in conjunction with the CPOL bit to produce the desired clock/data relationship (see figures \n308 to 309)\n0: The first clock transition is the first data capture edge\n1: The second clock transition is the first data capture edge\nNote: This bit is not available for UART4 & UART5.\n" }, { "page_number": 1017, "page_indices": { "start_index": 1979994, "end_index": 1982240 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1017 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.6 USART registers", 1010 ], [ 3, "30.6.6 Control register 3 (USART_CR3)", 1017 ] ], "page_content": "RM0090 Rev 21\n1017/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nNote:\nThese 3 bits (CPOL, CPHA, LBCL) should not be written while the transmitter is enabled.\n30.6.6 \nControl register 3 (USART_CR3)\nAddress offset: 0x14\nReset value: 0x0000 0000\n \nBit 8 LBCL: Last bit clock pulse\nThis bit allows the user to select whether the clock pulse associated with the last data bit \ntransmitted (MSB) has to be output on the CK pin in synchronous mode. \n0: The clock pulse of the last data bit is not output to the CK pin\n1: The clock pulse of the last data bit is output to the CK pin\nNote: 1: The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected \nby the M bit in the USART_CR1 register.\n2: This bit is not available for UART4 & UART5.\nBit 7 Reserved, must be kept at reset value\nBit 6 LBDIE: LIN break detection interrupt enable\nBreak interrupt mask (break detection using break delimiter).\n0: Interrupt is inhibited\n1: An interrupt is generated whenever LBD=1 in the USART_SR register\nBit 5 LBDL: lin break detection length\nThis bit is for selection between 11 bit or 10 bit break detection.\n0: 10-bit break detection\n1: 11-bit break detection\nBit 4 Reserved, must be kept at reset value\nBits 3:0 ADD[3:0]: Address of the USART node\nThis bit-field gives the address of the USART node.\nThis is used in multiprocessor communication during mute mode, for wake up with address mark \ndetection.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nONEBIT\nCTSIE\nCTSE\nRTSE\nDMAT\nDMAR\nSCEN\nNACK\nHDSEL\nIRLP\nIREN\nEIE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value\nBit 11 ONEBIT: One sample bit method enable\nThis bit allows the user to select the sample method. When the one sample bit method is \nselected the noise detection flag (NF) is disabled.\n0: Three sample bit method\n1: One sample bit method\nNote: The ONEBIT feature applies only to data bits. It does not apply to START bit.\nBit 10 CTSIE: CTS interrupt enable\n0: Interrupt is inhibited\n1: An interrupt is generated whenever CTS=1 in the USART_SR register\nNote: This bit is not available for UART4 & UART5.\n" }, { "page_number": 1018, "page_indices": { "start_index": 1982240, "end_index": 1983991 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1018 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.6 USART registers", 1010 ], [ 3, "30.6.6 Control register 3 (USART_CR3)", 1017 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1018/1757\nRM0090 Rev 21\nBit 9 CTSE: CTS enable\n0: CTS hardware flow control disabled\n1: CTS mode enabled, data is only transmitted when the CTS input is asserted (tied to 0). If \nthe CTS input is deasserted while a data is being transmitted, then the transmission is \ncompleted before stopping. If a data is written into the data register while CTS is \ndeasserted, the transmission is postponed until CTS is asserted.\nNote: This bit is not available for UART4 & UART5.\nBit 8 RTSE: RTS enable\n0: RTS hardware flow control disabled\n1: RTS interrupt enabled, data is only requested when there is space in the receive buffer. \nThe transmission of data is expected to cease after the current character has been \ntransmitted. The RTS output is asserted (tied to 0) when a data can be received.\nNote: This bit is not available for UART4 & UART5.\nBit 7 DMAT: DMA enable transmitter\nThis bit is set/reset by software\n1: DMA mode is enabled for transmission.\n0: DMA mode is disabled for transmission.\nBit 6 DMAR: DMA enable receiver\nThis bit is set/reset by software\n1: DMA mode is enabled for reception\n0: DMA mode is disabled for reception\nBit 5 SCEN: Smartcard mode enable\nThis bit is used for enabling Smartcard mode.\n0: Smartcard Mode disabled\n1: Smartcard Mode enabled\nNote: This bit is not available for UART4 & UART5.\nBit 4 NACK: Smartcard NACK enable\n0: NACK transmission in case of parity error is disabled\n1: NACK transmission during parity error is enabled\nNote: This bit is not available for UART4 & UART5.\nBit 3 HDSEL: Half-duplex selection\nSelection of Single-wire Half-duplex mode \n0: Half duplex mode is not selected\n1: Half duplex mode is selected \n" }, { "page_number": 1019, "page_indices": { "start_index": 1983991, "end_index": 1984783 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1019 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.6 USART registers", 1010 ], [ 3, "30.6.6 Control register 3 (USART_CR3)", 1017 ] ], "page_content": "RM0090 Rev 21\n1019/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\nBit 2 IRLP: IrDA low-power\nThis bit is used for selecting between normal and low-power IrDA modes\n0: Normal mode\n1: Low-power mode\nBit 1 IREN: IrDA mode enable\nThis bit is set and cleared by software.\n0: IrDA disabled\n1: IrDA enabled\nBit 0 EIE: Error interrupt enable\nError Interrupt Enable Bit is required to enable interrupt generation in case of a framing \nerror, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USART_SR register) in \ncase of Multi Buffer Communication (DMAR=1 in the USART_CR3 register).\n0: Interrupt is inhibited\n1: An interrupt is generated whenever DMAR=1 in the USART_CR3 register and FE=1 or \nORE=1 or NF=1 in the USART_SR register.\n" }, { "page_number": 1020, "page_indices": { "start_index": 1984783, "end_index": 1986501 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1020 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.6 USART registers", 1010 ], [ 3, "30.6.7 Guard time and prescaler register (USART_GTPR)", 1020 ] ], "page_content": "Universal synchronous asynchronous receiver transmitter (USART)\nRM0090\n1020/1757\nRM0090 Rev 21\n30.6.7 \nGuard time and prescaler register (USART_GTPR)\nAddress offset: 0x18\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nGT[7:0]\nPSC[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value\nBits 15:8 GT[7:0]: Guard time value\nThis bit-field gives the Guard time value in terms of number of baud clocks.\nThis is used in Smartcard mode. The Transmission Complete flag is set after this guard time \nvalue.\nNote: This bit is not available for UART4 & UART5.\nBits 7:0 PSC[7:0]: Prescaler value\n– In IrDA Low-power mode: \nPSC[7:0] = IrDA Low-Power Baud Rate\nUsed for programming the prescaler for dividing the system clock to achieve the low-power \nfrequency:\nThe source clock is divided by the value given in the register (8 significant bits):\n00000000: Reserved - do not program this value\n00000001: divides the source clock by 1\n00000010: divides the source clock by 2\n... \n– In normal IrDA mode: PSC must be set to 00000001.\n– In smartcard mode:\nPSC[4:0]: Prescaler value\nUsed for programming the prescaler for dividing the system clock to provide the smartcard \nclock.\nThe value given in the register (5 significant bits) is multiplied by 2 to give the division factor \nof the source clock frequency:\n00000: Reserved - do not program this value\n00001: divides the source clock by 2\n00010: divides the source clock by 4\n00011: divides the source clock by 6\n... \nNote: 1: Bits [7:5] have no effect if Smartcard mode is used.\n2: This bit is not available for UART4 & UART5.\n" }, { "page_number": 1021, "page_indices": { "start_index": 1986501, "end_index": 1987693 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1021 }, "toc_details": [ [ 1, "30 Universal synchronous asynchronous receiver transmitter (USART)", 968 ], [ 2, "30.6 USART registers", 1010 ], [ 3, "30.6.8 USART register map", 1021 ] ], "page_content": "RM0090 Rev 21\n1021/1757\nRM0090\nUniversal synchronous asynchronous receiver transmitter (USART)\n1021\n30.6.8 \nUSART register map\nThe table below gives the USART register map and reset values. \n \nRefer to Section 2.3: Memory map for the register boundary addresses.\nTable 150. USART register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nUSART_SR\nReserved\nCTS\nLBD\nTXE\nTC\nRXNE\nIDLE\nORE\nNF\nFE\nPE\nReset value\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\n0x04\nUSART_DR\nReserved\nDR[8:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nUSART_BRR\nReserved\nDIV_Mantissa[15:4]\nDIV_Fraction\n[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nUSART_CR1\nReserved\nOVER8\nReserved\nUE\nM\nWAKE\nPCE\nPS\nPEIE\nTXEIE\nTCIE\nRXNEIE\nIDLEIE\nTE\nRE\nRWU\nSBK\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nUSART_CR2\nReserved\nLINEN\nSTOP\n[1:0]\nCLKEN\nCPOL\nCPHA\nLBCL\nReserved\nLBDIE\nLBDL\nReserved\nADD[3:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nUSART_CR3\nReserved\nONEBIT\nCTSIE\nCTSE\nRTSE\nDMAT\nDMAR\nSCEN\nNACK\nHDSEL\nIRLP\nIREN\nEIE\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x18\nUSART_GTPR\nReserved\nGT[7:0]\nPSC[7:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n" }, { "page_number": 1022, "page_indices": { "start_index": 1987693, "end_index": 1990246 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1022 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.1 SDIO main features", 1022 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1022/1757\nRM0090 Rev 21\n31 \nSecure digital input/output interface (SDIO)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n31.1 \nSDIO main features\nThe SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2 \nperipheral bus and MultiMediaCards (MMCs), SD memory cards, SDIO cards and CE-ATA \ndevices.\nThe MultiMediaCard system specifications are available through the MultiMediaCard \nAssociation website at http://www.jedec.org/, published by the MMCA technical committee.\nSD memory card and SD I/O card system specifications are available through the SD card \nAssociation website at http://www.sdcard.org. \nCE-ATA system specifications are available through the CE-ATA workgroup website.\nThe SDIO features include the following:\n•\nFull compliance with MultiMediaCard System Specification Version 4.2. Card support \nfor three different databus modes: 1-bit (default), 4-bit and 8-bit\n•\nFull compatibility with previous versions of MultiMediaCards (forward compatibility)\n•\nFull compliance with SD Memory Card Specifications Version 2.0\n•\nFull compliance with SD I/O Card Specification Version 2.0: card support for two \ndifferent databus modes: 1-bit (default) and 4-bit\n•\nFull support of the CE-ATA features (full compliance with CE-ATA digital protocol \nRev1.1)\n•\nData transfer up to 50 MHz for the 8 bit mode\n•\nData and command output enable signals to control external bidirectional drivers.\nNote:\nThe SDIO does not have an SPI-compatible communication mode.\nThe SD memory card protocol is a superset of the MultiMediaCard protocol as defined in the \nMultiMediaCard system specification V2.11. Several commands required for SD memory \ndevices are not supported by either SD I/O-only cards or the I/O portion of combo cards. \nSome of these commands have no use in SD I/O devices, such as erase commands, and \nthus are not supported in the SDIO. In addition, several commands are different between \nSD memory cards and SD I/O cards and thus are not supported in the SDIO. For details \nrefer to SD I/O card Specification Version 1.0. CE-ATA is supported over the MMC electrical \ninterface using a protocol that utilizes the existing MMC access primitives. The interface \nelectrical and signaling definition is as defined in the MMC reference.\nThe MultiMediaCard/SD bus connects cards to the controller.\nThe current version of the SDIO supports only one SD/SDIO/MMC4.2 card at any one time \nand a stack of MMC4.1 or previous.\n" }, { "page_number": 1023, "page_indices": { "start_index": 1990246, "end_index": 1991420 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1023 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.2 SDIO bus topology", 1023 ] ], "page_content": "RM0090 Rev 21\n1023/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.2 \nSDIO bus topology\nCommunication over the bus is based on command and data transfers.\nThe basic transaction on the MultiMediaCard/SD/SD I/O bus is the command/response \ntransaction. These types of bus transaction transfer their information directly within the \ncommand or response structure. In addition, some operations have a data token.\nData transfers to/from SD/SDIO memory cards are done in data blocks. Data transfers \nto/from MMC are done data blocks or streams. Data transfers to/from the CE-ATA Devices \nare done in data blocks.\nFigure 321. SDIO “no response” and “no data” operations\nFigure 322. SDIO (multiple) block read operation\nai14734b\nOperation (no response)\nOperation (no data)\nSDMMC_CMD\nSDMMC_D\nFrom host to card(s)\nFrom host to card\nFrom card to host\nResponse\nCommand\nCommand\nai14735b\nCommand\nResponse\nData block crc\nData block crc\nData block crc\nBlock read operation\nMultiple block read operation\nData stop operation\nFrom host to card From card to host\ndata from card to host\nStop command\nstops data transfer\nCommand\nResponse\nSDMMC_CMD\nSDMMC_D\n" }, { "page_number": 1024, "page_indices": { "start_index": 1991420, "end_index": 1992446 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1024 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.2 SDIO bus topology", 1023 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1024/1757\nRM0090 Rev 21\nFigure 323. SDIO (multiple) block write operation\nNote:\nThe SDIO does not send any data as long as the Busy signal is asserted (SDIO_D0 \npulled low).\nFigure 324. SDIO sequential read operation\nFigure 325. SDIO sequential write operation\nai14737b\nCommand\nResponse\nData block crc\nData block crc\nData stop operation\nFrom host to card From card to host\ndata from host to card\nStop command\nstops data transfer\nCommand\nResponse\nSDMMC_CMD\nSDMMC_D\nBusy\nBlock write operation\nBusy\nMultiple block write operation\nai14738b\nData stop operation\nFrom card to host\nStop command\nstops data transfer\nCommand\nResponse\nCommand\nResponse\nData stream\nData transfer operation\nFrom host to\ncard(s)\nData from card to host\nSDMMC_CMD\nSDMMC_D\nai14739b\nData stop operation\nFrom card to host\nStop command\nstops data transfer\nResponse\nCommand\nResponse\nCommand\nData stream\nData transfer operation\nFrom host to\ncard(s)\nData from host to card\nSDMMC_CMD\nSDMMC_D\n" }, { "page_number": 1025, "page_indices": { "start_index": 1992446, "end_index": 1994158 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1025 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.3 SDIO functional description", 1025 ] ], "page_content": "RM0090 Rev 21\n1025/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.3 \nSDIO functional description\nThe SDIO consists of two parts:\n•\nThe SDIO adapter block provides all functions specific to the MMC/SD/SD I/O card \nsuch as the clock generation unit, command and data transfer.\n•\nThe APB2 interface accesses the SDIO adapter registers, and generates interrupt and \nDMA request signals.\nFigure 326. SDIO block diagram\nBy default SDIO_D0 is used for data transfer. After initialization, the host can change the \ndatabus width.\nIf a MultiMediaCard is connected to the bus, SDIO_D0, SDIO_D[3:0] or SDIO_D[7:0] can be \nused for data transfer. MMC V3.31 or previous, supports only 1 bit of data so only SDIO_D0 \ncan be used.\nIf an SD or SD I/O card is connected to the bus, data transfer can be configured by the host \nto use SDIO_D0 or SDIO_D[3:0]. All data lines are operating in push-pull mode.\nSDIO_CMD has two operational modes:\n•\nOpen-drain for initialization (only for MMCV3.31 or previous)\n•\nPush-pull for command transfer (SD/SD I/O card MMC4.2 use push-pull drivers also for \ninitialization)\nSDIO_CK is the clock to the card: one bit is transferred on both command and data lines \nwith each clock cycle. \nThe SDIO uses two clock signals:\n•\nSDIO adapter clock SDIOCLK up to 50 MHz (48 MHz when in use with USB)\n•\nAPB2 bus clock (PCLK2)\nPCLK2 and SDIO_CK clock frequencies must respect the following condition:\nThe signals shown in Table 151 are used on the MultiMediaCard/SD/SD I/O card bus.\nai15898b\nAPB2 bus\nAPB2\nInterrupts and\nPCLK2\nSDMMC_CK\ninterface\nDMA request\nSDMMCCLK\nSDMMC_D[7:0]\nSDMMC_CMD\nSDMMC\nSDMMC \nadapter\nFrequenc PCLK2\n(\n)\n3\n8\n⁄\nFrequency SDIO_CK\n(\n)\n×\n≥\n" }, { "page_number": 1026, "page_indices": { "start_index": 1994158, "end_index": 1995632 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1026 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.3 SDIO functional description", 1025 ], [ 3, "31.3.1 SDIO adapter", 1026 ], [ 4, "Adapter register block", 1026 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1026/1757\nRM0090 Rev 21\n \n31.3.1 \nSDIO adapter\nFigure 327 shows a simplified block diagram of an SDIO adapter.\nFigure 327. SDIO adapter\nThe SDIO adapter is a multimedia/secure digital memory card bus master that provides an \ninterface to a multimedia card stack or to a secure digital memory card. It consists of five \nsubunits:\n•\nAdapter register block\n•\nControl unit\n•\nCommand path\n•\nData path\n•\nData FIFO\nNote:\nThe adapter registers and FIFO use the APB2 bus clock domain (PCLK2). The control unit, \ncommand path and data path use the SDIO adapter clock domain (SDIOCLK).\nAdapter register block\nThe adapter register block contains all system registers. This block also generates the \nsignals that clear the static flags in the multimedia card. The clear signals are generated \nwhen 1 is written into the corresponding bit location in the SDIO Clear register.\nTable 151. SDIO I/O definitions\nPin\nDirection\nDescription\nSDIO_CK\nOutput\nMultiMediaCard/SD/SDIO card clock. This pin is the clock from \nhost to card.\nSDIO_CMD\nBidirectional\nMultiMediaCard/SD/SDIO card command. This pin is the \nbidirectional command/response signal.\nSDIO_D[7:0]\nBidirectional\nMultiMediaCard/SD/SDIO card data. These pins are the \nbidirectional databus. \nai15899b\nTo APB2 \ninterface\nControl unit\nCommand \npath\nData path\nAdapter \nregisters\nSDMMC_CK\nSDMMC_CMD\nSDMMC_D[7:0]\nSDMMC adapter\nPCLK2\nSDMMCCLK\nFIFO\nCard bus\n" }, { "page_number": 1027, "page_indices": { "start_index": 1995632, "end_index": 1996688 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1027 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.3 SDIO functional description", 1025 ], [ 3, "31.3.1 SDIO adapter", 1026 ], [ 4, "Control unit", 1027 ] ], "page_content": "RM0090 Rev 21\n1027/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nControl unit\nThe control unit contains the power management functions and the clock divider for the \nmemory card clock.\nThere are three power phases:\n•\npower-off\n•\npower-up\n•\npower-on\nFigure 328. Control unit\nThe control unit is illustrated in Figure 328. It consists of a power management subunit and \na clock management subunit.\nThe power management subunit disables the card bus output signals during the power-off \nand power-up phases.\nThe clock management subunit generates and controls the SDIO_CK signal. The SDIO_CK \noutput can use either the clock divide or the clock bypass mode. The clock output is \ninactive:\n•\nafter reset\n•\nduring the power-off or power-up phases\n•\nif the power saving mode is enabled and the card bus is in the Idle state (eight clock \nperiods after both the command and data path subunits enter the Idle phase)\nai14804b\nControl unit\nPower management\nClock management\nAdapter \nregisters\nSDMMC_CK\nTo command and data path\n" }, { "page_number": 1028, "page_indices": { "start_index": 1996688, "end_index": 1997610 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1028 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.3 SDIO functional description", 1025 ], [ 3, "31.3.1 SDIO adapter", 1026 ], [ 4, "Command path", 1028 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1028/1757\nRM0090 Rev 21\nCommand path\nThe command path unit sends commands to and receives responses from the cards.\nFigure 329. SDIO adapter command path\n•\nCommand path state machine (CPSM)\n–\nWhen the command register is written to and the enable bit is set, command \ntransfer starts. When the command has been sent, the command path state \nmachine (CPSM) sets the status flags and enters the Idle state if a response is not \nrequired. If a response is required, it waits for the response (see Figure 330 on \npage 1029). When the response is received, the received CRC code and the \ninternally generated code are compared, and the appropriate status flags are set.\nai15900b\nAdapter registers\nCMD\nStatus\nflag\nCRC\nShift\nregister\nCMD\nTo control unit\nSDMMC_CMDin\nSDMMC_CMDout\nTo APB2 interface\nControl\nlogic\nCommand \ntimer\nArgument\nResponse\nregisters\n" }, { "page_number": 1029, "page_indices": { "start_index": 1997610, "end_index": 1999274 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1029 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.3 SDIO functional description", 1025 ], [ 3, "31.3.1 SDIO adapter", 1026 ], [ 4, "Command path", 1028 ] ], "page_content": "RM0090 Rev 21\n1029/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nFigure 330. Command path state machine (CPSM)\nWhen the Wait state is entered, the command timer starts running. If the timeout is reached \nbefore the CPSM moves to the Receive state, the timeout flag is set and the Idle state is \nentered.\nNote:\nThe command timeout has a fixed value of 64 SDIO_CK clock periods.\nIf the interrupt bit is set in the command register, the timer is disabled and the CPSM waits \nfor an interrupt request from one of the cards. If a pending bit is set in the command register, \nthe CPSM enters the Pend state, and waits for a CmdPend signal from the data path \nsubunit. When CmdPend is detected, the CPSM moves to the Send state. This enables the \ndata counter to trigger the stop command transmission.\nNote:\nThe CPSM remains in the Idle state for at least eight SDIO_CK periods to meet the NCC and \nNRC timing constraints. NCC is the minimum delay between two host commands, and NRC is \nthe minimum delay between the host command and the card response.\nIdle\nPend\nSend\nWait\nReceive\nLast Data\nCPSM\ndisabled\nEnabled and\ncommand start\nCPSM disabled or \nno response\nWait for response\nResponse\nstarted\nResponse received or\ndisabled or command \nCRC failed\nCPSM Disabled or\ncommand timeout\nCPSM Enabled and\npending command\nai14806b\nWait_CPL\nResponse Received in CE-ATA\nmode and no interrupt and\nwait for CE-ATA Command\nCompletion signal enabled\nResponse Received in CE-ATA mode and\nno interrupt and wait for CE-ATA\nCommand Completion signal disabled\nCE-ATA Command\nCompletion signal\nreceived or\nCPSM disabled or\nCommand CRC failed\nOn reset\n" }, { "page_number": 1030, "page_indices": { "start_index": 1999274, "end_index": 2001138 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1030 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.3 SDIO functional description", 1025 ], [ 3, "31.3.1 SDIO adapter", 1026 ], [ 4, "Command path", 1028 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1030/1757\nRM0090 Rev 21\nFigure 331. SDIO command transfer\n•\nCommand format\n–\nCommand: a command is a token that starts an operation. Command are sent \nfrom the host either to a single card (addressed command) or to all connected \ncards (broadcast command are available for MMC V3.31 or previous). Commands \nare transferred serially on the CMD line. All commands have a fixed length of 48 \nbits. The general format for a command token for MultiMediaCards, SD-Memory \ncards and SDIO-Cards is shown in Table 152. CE-ATA commands are an \nextension of MMC commands V4.2, and so have the same format.\nThe command path operates in a half-duplex mode, so that commands and \nresponses can either be sent or received. If the CPSM is not in the Send state, the \nSDIO_CMD output is in the Hi-Z state, as shown in Figure 331 on page 1030. \nData on SDIO_CMD are synchronous with the rising edge of SDIO_CK. Table 152 \nshows the command format.\n \n–\nResponse: a response is a token that is sent from an addressed card (or \nsynchronously from all connected cards for MMC V3.31 or previous), to the host \nas an answer to a previously received command. Responses are transferred \nserially on the CMD line.\nThe SDIO supports two response types. Both use CRC error checking:\n•\n48 bit short response\n•\n136 bit long response\nNote:\nIf the response does not contain a CRC (CMD1 response), the device driver must ignore the \nCRC failed status.\nTable 152. Command format\nBit position\nWidth\nValue\nDescription\n47\n1\n0\nStart bit\n46\n1\n1\nTransmission bit\n[45:40]\n6\n-\nCommand index\n[39:8]\n32\n-\nArgument\n[7:1]\n7\n-\nCRC7\n0\n1\n1\nEnd bit\nai14807b\nSDMMC_CK\nSDMMC_CMD\nCommand\nResponse\nCommand\nState\nIdle\nSend\nWait\nReceive\nIdle\nSend\nHi-Z\nController drives\nHi-Z\nCard drives\nHi-Z\nController drives\nat least 8 SDMMC_CK \ncycles\n" }, { "page_number": 1031, "page_indices": { "start_index": 2001138, "end_index": 2002843 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1031 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.3 SDIO functional description", 1025 ], [ 3, "31.3.1 SDIO adapter", 1026 ], [ 4, "Command path", 1028 ] ], "page_content": "RM0090 Rev 21\n1031/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n \n \nThe command register contains the command index (six bits sent to a card) and the \ncommand type. These determine whether the command requires a response, and whether \nthe response is 48 or 136 bits long (see Section 31.9.4 on page 1065). The command path \nimplements the status flags shown in Table 155:\n \nThe CRC generator calculates the CRC checksum for all bits before the CRC code. This \nincludes the start bit, transmitter bit, command index, and command argument (or card \nstatus). The CRC checksum is calculated for the first 120 bits of CID or CSD for the long \nresponse format. Note that the start bit, transmitter bit and the six reserved bits are not used \nin the CRC calculation.\nThe CRC checksum is a 7-bit value:\n CRC[6:0] = Remainder [(M(x) * x7) / G(x)]\nG(x) = x7 + x3 + 1\nM(x) = (start bit) * x39 + ... + (last bit before CRC) * x0, or\nM(x) = (start bit) * x119 + ... + (last bit before CRC) * x0\nTable 153. Short response format\nBit position\nWidth\nValue\nDescription\n47\n1\n0\nStart bit\n46\n1\n0\nTransmission bit\n[45:40]\n6\n-\nCommand index\n[39:8]\n32\n-\nArgument\n[7:1]\n7\n-\nCRC7(or 1111111)\n0\n1\n1\nEnd bit\nTable 154. Long response format\nBit position\nWidth\nValue\nDescription\n135\n1\n0\nStart bit\n134\n1\n0\nTransmission bit\n[133:128]\n6\n111111\nReserved\n[127:1]\n127\n-\nCID or CSD (including internal CRC7)\n0\n1\n1\nEnd bit\nTable 155. Command path status flags\nFlag\nDescription\nCMDREND\nSet if response CRC is OK.\nCCRCFAIL\nSet if response CRC fails.\nCMDSENT\nSet when command (that does not require response) is sent\nCTIMEOUT\nResponse timeout.\nCMDACT\nCommand transfer in progress.\n" }, { "page_number": 1032, "page_indices": { "start_index": 2002843, "end_index": 2004422 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1032 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.3 SDIO functional description", 1025 ], [ 3, "31.3.1 SDIO adapter", 1026 ], [ 4, "Data path", 1032 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1032/1757\nRM0090 Rev 21\nData path\nThe data path subunit transfers data to and from cards. Figure 332 shows a block diagram \nof the data path.\nFigure 332. Data path\nThe card databus width can be programmed using the clock control register. If the 4-bit wide \nbus mode is enabled, data is transferred at four bits per clock cycle over all four data signals \n(SDIO_D[3:0]). If the 8-bit wide bus mode is enabled, data is transferred at eight bits per \nclock cycle over all eight data signals (SDIO_D[7:0]). If the wide bus mode is not enabled, \nonly one bit per clock cycle is transferred over SDIO_D0.\nDepending on the transfer direction (send or receive), the data path state machine (DPSM) \nmoves to the Wait_S or Wait_R state when it is enabled:\n•\nSend: the DPSM moves to the Wait_S state. If there is data in the transmit FIFO, the \nDPSM moves to the Send state, and the data path subunit starts sending data to a \ncard.\n•\nReceive: the DPSM moves to the Wait_R state and waits for a start bit. When it \nreceives a start bit, the DPSM moves to the Receive state, and the data path subunit \nstarts receiving data from a card.\nData path state machine (DPSM)\nThe DPSM operates at SDIO_CK frequency. Data on the card bus signals is synchronous to \nthe rising edge of SDIO_CK. The DPSM has six states, as shown in Figure 333: Data path \nstate machine (DPSM).\nai14808b\nData path\nData FIFO\nTransmit\nStatus\nflag\nCRC\nShift\nregister\nTo control unit\nSDMMC_Din[7:0]\nSDMMC_Dout[7:0]\nReceive\nControl\nlogic\nData\ntimer\n" }, { "page_number": 1033, "page_indices": { "start_index": 2004422, "end_index": 2006203 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1033 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.3 SDIO functional description", 1025 ], [ 3, "31.3.1 SDIO adapter", 1026 ], [ 4, "Data path", 1032 ] ], "page_content": "RM0090 Rev 21\n1033/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nFigure 333. Data path state machine (DPSM)\n•\nIdle: the data path is inactive, and the SDIO_D[7:0] outputs are in Hi-Z. When the data \ncontrol register is written and the enable bit is set, the DPSM loads the data counter \nwith a new value and, depending on the data direction bit, moves to either the Wait_S \nor the Wait_R state.\n•\nWait_R: if the data counter equals zero, the DPSM moves to the Idle state when the \nreceive FIFO is empty. If the data counter is not zero, the DPSM waits for a start bit on \nSDIO_D. The DPSM moves to the Receive state if it receives a start bit before a \ntimeout, and loads the data block counter. If it reaches a timeout before it detects a \nstart bit, or a start bit error occurs, it moves to the Idle state and sets the timeout status \nflag.\n•\nReceive: serial data received from a card is packed in bytes and written to the data \nFIFO. Depending on the transfer mode bit in the data control register, the data transfer \nmode can be either block or stream:\n–\nIn block mode, when the data block counter reaches zero, the DPSM waits until it \nreceives the CRC code. If the received code matches the internally generated \nIdle\nBusy\nSend\nWait_R\nReceive\nEnd of packet\nDisabled or CRC fail\nor timeout\nNot busy\nDisabled or\nend of data\nData ready\nEnd of packet or\nend of data or\nFIFO overrun\nEnable and not send\nDisabled or\nRx FIFO empty or timeout or\nstart bit error\nDisabled or FIFO underrun or\nend of data or CRC fail\nai14809b\nWait_S\nStart bit\nOn reset\nDisabled or CRC fail\nEnable and send\nDPSM disabled\nRead Wait\nDPSM enabled and\nRead Wait Started\nand SD I/O mode enabled\nReadWait Stop\nData received and\nRead Wait Started and\nSD I/O mode enabled\n" }, { "page_number": 1034, "page_indices": { "start_index": 2006203, "end_index": 2008811 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1034 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.3 SDIO functional description", 1025 ], [ 3, "31.3.1 SDIO adapter", 1026 ], [ 4, "Data path", 1032 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1034/1757\nRM0090 Rev 21\nCRC code, the DPSM moves to the Wait_R state. If not, the CRC fail status flag is \nset and the DPSM moves to the Idle state.\n–\nIn stream mode, the DPSM receives data while the data counter is not zero. When \nthe counter is zero, the remaining data in the shift register is written to the data \nFIFO, and the DPSM moves to the Wait_R state.\nIf a FIFO overrun error occurs, the DPSM sets the FIFO error flag and moves to the \nIdle state:\n•\nWait_S: the DPSM moves to the Idle state if the data counter is zero. If not, it waits until \nthe data FIFO empty flag is deasserted, and moves to the Send state.\nNote:\nThe DPSM remains in the Wait_S state for at least two clock periods to meet the NWR timing \nrequirements, where NWR is the number of clock cycles between the reception of the card \nresponse and the start of the data transfer from the host.\n•\nSend: the DPSM starts sending data to a card. Depending on the transfer mode bit in \nthe data control register, the data transfer mode can be either block or stream:\n–\nIn block mode, when the data block counter reaches zero, the DPSM sends an \ninternally generated CRC code and end bit, and moves to the Busy state.\n–\nIn stream mode, the DPSM sends data to a card while the enable bit is high and \nthe data counter is not zero. It then moves to the Idle state.\nIf a FIFO underrun error occurs, the DPSM sets the FIFO error flag and moves to the \nIdle state.\n•\nBusy: the DPSM waits for the CRC status flag:\n–\nIf it does not receive a positive CRC status, it moves to the Idle state and sets the \nCRC fail status flag.\n–\nIf it receives a positive CRC status, it moves to the Wait_S state if SDIO_D0 is not \nlow (the card is not busy).\nIf a timeout occurs while the DPSM is in the Busy state, it sets the data timeout flag and \nmoves to the Idle state.\nThe data timer is enabled when the DPSM is in the Wait_R or Busy state, and \ngenerates the data timeout error:\n–\nWhen transmitting data, the timeout occurs if the DPSM stays in the Busy state for \nlonger than the programmed timeout period\n–\nWhen receiving data, the timeout occurs if the end of the data is not true, and if the \nDPSM stays in the Wait_R state for longer than the programmed timeout period.\n•\nData: data can be transferred from the card to the host or vice versa. Data is \ntransferred via the data lines. They are stored in a FIFO of 32 words, each word is 32 \nbits wide.\n \nTable 156. Data token format\nDescription\nStart bit\nData\nCRC16\nEnd bit\nBlock Data\n0\n-\nyes\n1\nStream Data\n0\n-\nno\n1\n" }, { "page_number": 1035, "page_indices": { "start_index": 2008811, "end_index": 2011298 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1035 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.3 SDIO functional description", 1025 ], [ 3, "31.3.1 SDIO adapter", 1026 ], [ 4, "Data FIFO", 1035 ] ], "page_content": "RM0090 Rev 21\n1035/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nData FIFO\nThe data FIFO (first-in-first-out) subunit is a data buffer with a transmit and receive unit.\nThe FIFO contains a 32-bit wide, 32-word deep data buffer, and transmit and receive logic. \nBecause the data FIFO operates in the APB2 clock domain (PCLK2), all signals from the \nsubunits in the SDIO clock domain (SDIOCLK) are resynchronized.\nDepending on the TXACT and RXACT flags, the FIFO can be disabled, transmit enabled, or \nreceive enabled. TXACT and RXACT are driven by the data path subunit and are mutually \nexclusive:\n–\nThe transmit FIFO refers to the transmit logic and data buffer when TXACT is \nasserted\n–\nThe receive FIFO refers to the receive logic and data buffer when RXACT is \nasserted\n•\nTransmit FIFO:\nData can be written to the transmit FIFO through the APB2 interface when the SDIO is \nenabled for transmission.\nThe transmit FIFO is accessible via 32 sequential addresses. The transmit FIFO \ncontains a data output register that holds the data word pointed to by the read pointer. \nWhen the data path subunit has loaded its shift register, it increments the read pointer \nand drives new data out.\nIf the transmit FIFO is disabled, all status flags are deasserted. The data path subunit \nasserts TXACT when it transmits data.\n \n•\nReceive FIFO\nWhen the data path subunit receives a word of data, it drives the data on the write \ndatabus. The write pointer is incremented after the write operation completes. On the \nread side, the contents of the FIFO word pointed to by the current value of the read \npointer is driven onto the read databus. If the receive FIFO is disabled, all status flags \nare deasserted, and the read and write pointers are reset. The data path subunit \nasserts RXACT when it receives data. Table 158 lists the receive FIFO status flags. \nThe receive FIFO is accessible via 32 sequential addresses.\nTable 157. Transmit FIFO status flags\nFlag\nDescription\nTXFIFOF\nSet to high when all 32 transmit FIFO words contain valid data.\nTXFIFOE\nSet to high when the transmit FIFO does not contain valid data.\nTXFIFOHE\nSet to high when 8 or more transmit FIFO words are empty. This flag can be used \nas a DMA request.\nTXDAVL\nSet to high when the transmit FIFO contains valid data. This flag is the inverse of \nthe TXFIFOE flag.\nTXUNDERR\nSet to high when an underrun error occurs. This flag is cleared by writing to the \nSDIO Clear register.\n" }, { "page_number": 1036, "page_indices": { "start_index": 2011298, "end_index": 2013099 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1036 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.3 SDIO functional description", 1025 ], [ 3, "31.3.2 SDIO APB2 interface", 1036 ], [ 4, "SDIO interrupts", 1036 ], [ 4, "SDIO/DMA interface - procedure for data transfers between the SDIO and memory", 1036 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1036/1757\nRM0090 Rev 21\n \n31.3.2 \nSDIO APB2 interface\nThe APB2 interface generates the interrupt and DMA requests, and accesses the SDIO \nadapter registers and the data FIFO. It consists of a data path, register decoder, and \ninterrupt/DMA logic.\nSDIO interrupts\nThe interrupt logic generates an interrupt request signal that is asserted when at least one \nof the selected status flags is high. A mask register is provided to allow selection of the \nconditions that generate an interrupt. A status flag generates the interrupt request if a \ncorresponding mask flag is set.\nSDIO/DMA interface - procedure for data transfers between the SDIO and \nmemory\nIn the example shown, the transfer is from the SDIO host controller to an MMC (512 bytes \nusing CMD24 (WRITE_BLOCK). The SDIO FIFO is filled by data stored in a memory using \nthe DMA controller.\n1.\nDo the card identification process\n2. \nIncrease the SDIO_CK frequency\n3. \nSelect the card by sending CMD7\n4. \nConfigure the DMA2 as follows:\na) \nEnable DMA2 controller and clear any pending interrupts.\nb) \nProgram the DMA2_Stream3 or DMA2_Stream6 Channel4 source address \nregister with the memory location’s base address and DMA2_Stream3 or \nTable 158. Receive FIFO status flags\nFlag\nDescription\nRXFIFOF\nSet to high when all 32 receive FIFO words contain valid data\nRXFIFOE\nSet to high when the receive FIFO does not contain valid data. \nRXFIFOHF\n Set to high when 8 or more receive FIFO words contain valid data. This flag can be \nused as a DMA request.\nRXDAVL\nSet to high when the receive FIFO is not empty. This flag is the inverse of the \nRXFIFOE flag.\nRXOVERR\nSet to high when an overrun error occurs. This flag is cleared by writing to the SDIO \nClear register.\n" }, { "page_number": 1037, "page_indices": { "start_index": 2013099, "end_index": 2015846 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1037 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.1 Card identification mode", 1037 ], [ 3, "31.4.2 Card reset", 1037 ], [ 3, "31.4.3 Operating voltage range validation", 1037 ] ], "page_content": "RM0090 Rev 21\n1037/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nDMA2_Stream6 Channel4 destination address register with the SDIO_FIFO \nregister address.\nc) \nProgram DMA2_Stream3 or DMA2_Stream6 Channel4 control register (memory \nincrement, not peripheral increment, peripheral and source width is word size).\nd) \nProgram DMA2_Stream3 or DMA2_Stream6 Channel4 to select the peripheral as \nflow controller (set PFCTRL bit in DMA_S3CR or DMA_S6CR configuration \nregister).\ne) \nConfigure the incremental burst transfer to 4 beats (at least from peripheral side) \nin DMA2_Stream3 or DMA2_Stream6 Channel4.\nf) \nEnable DMA2_Stream3 or DMA2_Stream6 Channel4\n5. \nSend CMD24 (WRITE_BLOCK) as follows:\na) \nProgram the SDIO data length register (SDIO data timer register should be \nalready programmed before the card identification process).\nb) \nProgram the SDIO argument register with the address location of the card where \ndata is to be transferred.\nc) \nProgram the SDIO command register: CmdIndex with 24 (WRITE_BLOCK); \nWaitResp with ‘1’ (SDIO card host waits for a response); CPSMEN with ‘1’ (SDIO \ncard host enabled to send a command). Other fields are at their reset value.\nd) \nWait for SDIO_STA[6] = CMDREND interrupt, then program the SDIO data control \nregister: DTEN with ‘1’ (SDIO card host enabled to send data); DTDIR with ‘0’ \n(from controller to card); DTMODE with ‘0’ (block data transfer); DMAEN with ‘1’ \n(DMA enabled); DBLOCKSIZE with 0x9 (512 bytes). Other fields are don’t care.\ne) \nWait for SDIO_STA[10] = DBCKEND.\n6. \nCheck that no channels are still enabled by polling the DMA Enabled Channel Status \nregister.\n31.4 \nCard functional description\n31.4.1 \nCard identification mode\nWhile in card identification mode the host resets all cards, validates the operation voltage \nrange, identifies cards and sets a relative card address (RCA) for each card on the bus. All \ndata communications in the card identification mode use the command line (CMD) only.\n31.4.2 \nCard reset\nThe GO_IDLE_STATE command (CMD0) is the software reset command and it puts the \nMultiMediaCard and SD memory in the Idle state. The IO_RW_DIRECT command (CMD52) \nresets the SD I/O card. After power-up or CMD0, all cards output bus drivers are in the high-\nimpedance state and the cards are initialized with a default relative card address \n(RCA=0x0001) and with a default driver stage register setting (lowest speed, highest driving \ncurrent capability).\n31.4.3 \nOperating voltage range validation\nAll cards can communicate with the SDIO card host using any operating voltage within the \nspecification range. The supported minimum and maximum VDD values are defined in the \noperation conditions register (OCR) on the card.\n" }, { "page_number": 1038, "page_indices": { "start_index": 2015846, "end_index": 2018778 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1038 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.4 Card identification process", 1038 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1038/1757\nRM0090 Rev 21\nCards that store the card identification number (CID) and card specific data (CSD) in the \npayload memory are able to communicate this information only under data-transfer VDD \nconditions. When the SDIO card host module and the card have incompatible VDD ranges, \nthe card is not able to complete the identification cycle and cannot send CSD data. For this \npurpose, the special commands, SEND_OP_COND (CMD1), SD_APP_OP_COND (ACMD41 \nfor SD Memory), and IO_SEND_OP_COND (CMD5 for SD I/O), are designed to provide a \nmechanism to identify and reject cards that do not match the VDD range desired by the \nSDIO card host. The SDIO card host sends the required VDD voltage window as the \noperand of these commands. Cards that cannot perform data transfer in the specified range \ndisconnect from the bus and go to the inactive state.\nBy using these commands without including the voltage range as the operand, the SDIO \ncard host can query each card and determine the common voltage range before placing out-\nof-range cards in the inactive state. This query is used when the SDIO card host is able to \nselect a common voltage range or when the user requires notification that cards are not \nusable.\n31.4.4 \nCard identification process\nThe card identification process differs for MultiMediaCards and SD cards. For \nMultiMediaCard cards, the identification process starts at clock rate Fod. The SDIO_CMD \nline output drivers are open-drain and allow parallel card operation during this process. The \nregistration process is accomplished as follows:\n1.\nThe bus is activated.\n2. \nThe SDIO card host broadcasts SEND_OP_COND (CMD1) to receive operation \nconditions.\n3. \nThe response is the wired AND operation of the operation condition registers from all \ncards.\n4. \nIncompatible cards are placed in the inactive state.\n5. \nThe SDIO card host broadcasts ALL_SEND_CID (CMD2) to all active cards.\n6. \nThe active cards simultaneously send their CID numbers serially. Cards with outgoing \nCID bits that do not match the bits on the command line stop transmitting and must wait \nfor the next identification cycle. One card successfully transmits a full CID to the SDIO \ncard host and enters the Identification state.\n7. \nThe SDIO card host issues SET_RELATIVE_ADDR (CMD3) to that card. This new \naddress is called the relative card address (RCA); it is shorter than the CID and \naddresses the card. The assigned card changes to the Standby state, it does not react \nto further identification cycles, and its output switches from open-drain to push-pull.\n8. \nThe SDIO card host repeats steps 5 through 7 until it receives a timeout condition.\nFor the SD card, the identification process starts at clock rate Fod, and the SDIO_CMD line \noutput drives are push-pull drivers instead of open-drain. The registration process is \naccomplished as follows:\n" }, { "page_number": 1039, "page_indices": { "start_index": 2018778, "end_index": 2022310 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1039 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.5 Block write", 1039 ] ], "page_content": "RM0090 Rev 21\n1039/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n1.\nThe bus is activated.\n2. \nThe SDIO card host broadcasts SD_APP_OP_COND (ACMD41).\n3. \nThe cards respond with the contents of their operation condition registers.\n4. \nThe incompatible cards are placed in the inactive state.\n5. \nThe SDIO card host broadcasts ALL_SEND_CID (CMD2) to all active cards.\n6. \nThe cards send back their unique card identification numbers (CIDs) and enter the \nIdentification state.\n7. \nThe SDIO card host issues SET_RELATIVE_ADDR (CMD3) to an active card with an \naddress. This new address is called the relative card address (RCA); it is shorter than \nthe CID and addresses the card. The assigned card changes to the Standby state. The \nSDIO card host can reissue this command to change the RCA. The RCA of the card is \nthe last assigned value.\n8. \nThe SDIO card host repeats steps 5 through 7 with all active cards.\nFor the SD I/O card, the registration process is accomplished as follows:\n1.\nThe bus is activated.\n2. \nThe SDIO card host sends IO_SEND_OP_COND (CMD5).\n3. \nThe cards respond with the contents of their operation condition registers.\n4. \nThe incompatible cards are set to the inactive state.\n5. \nThe SDIO card host issues SET_RELATIVE_ADDR (CMD3) to an active card with an \naddress. This new address is called the relative card address (RCA); it is shorter than \nthe CID and addresses the card. The assigned card changes to the Standby state. The \nSDIO card host can reissue this command to change the RCA. The RCA of the card is \nthe last assigned value.\n31.4.5 \nBlock write\nDuring block write (CMD24 - 27) one or more blocks of data are transferred from the host to \nthe card with a CRC appended to the end of each block by the host. A card supporting block \nwrite is always able to accept a block of data defined by WRITE_BL_LEN. If the CRC fails, \nthe card indicates the failure on the SDIO_D line and the transferred data are discarded and \nnot written, and all further transmitted blocks (in multiple block write mode) are ignored.\nIf the host uses partial blocks whose accumulated length is not block aligned and, block \nmisalignment is not allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card \ndetects the block misalignment error before the beginning of the first misaligned block. \n(ADDRESS_ERROR error bit is set in the status register). The write operation is also \naborted if the host tries to write over a write-protected area. In this case, however, the card \nsets the WP_VIOLATION bit.\nProgramming of the CID and CSD registers does not require a previous block length setting. \nThe transferred data is also CRC protected. If a part of the CSD or CID register is stored in \nROM, then this unchangeable part must match the corresponding part of the receive buffer. \nIf this match fails, then the card reports an error and does not change any register contents. \nSome cards may require long and unpredictable times to write a block of data. After \nreceiving a block of data and completing the CRC check, the card begins writing and holds \nthe SDIO_D line low if its write buffer is full and unable to accept new data from a new \nWRITE_BLOCK command. The host may poll the status of the card with a SEND_STATUS \ncommand (CMD13) at any time, and the card responds with its status. The \nREADY_FOR_DATA status bit indicates whether the card can accept new data or whether \nthe write process is still in progress. The host may deselect the card by issuing CMD7 (to \n" }, { "page_number": 1040, "page_indices": { "start_index": 2022310, "end_index": 2025243 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1040 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.6 Block read", 1040 ], [ 3, "31.4.7 Stream access, stream write and stream read (MultiMediaCard only)", 1040 ], [ 4, "Stream write (MultiMediaCard only)", 1040 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1040/1757\nRM0090 Rev 21\nselect a different card), which places the card in the Disconnect state and release the \nSDIO_D line(s) without interrupting the write operation. When selecting the card again, it \nreactivates busy indication by pulling SDIO_D to low if programming is still in progress and \nthe write buffer is unavailable.\n31.4.6 \nBlock read\nIn Block read mode the basic unit of data transfer is a block whose maximum size is defined \nin the CSD (READ_BL_LEN). If READ_BL_PARTIAL is set, smaller blocks whose start and \nend addresses are entirely contained within one physical block (as defined by \nREAD_BL_LEN) may also be transmitted. A CRC is appended to the end of each block, \nensuring data transfer integrity. CMD17 (READ_SINGLE_BLOCK) initiates a block read and \nafter completing the transfer, the card returns to the Transfer state.\nCMD18 (READ_MULTIPLE_BLOCK) starts a transfer of several consecutive blocks.\nThe host can abort reading at any time, within a multiple block operation, regardless of its \ntype. Transaction abort is done by sending the stop transmission command.\nIf the card detects an error (for example, out of range, address misalignment or internal \nerror) during a multiple block read operation (both types) it stops the data transmission and \nremains in the data state. The host must than abort the operation by sending the stop \ntransmission command. The read error is reported in the response to the stop transmission \ncommand.\nIf the host sends a stop transmission command after the card transmits the last block of a \nmultiple block operation with a predefined number of blocks, it is responded to as an illegal \ncommand, since the card is no longer in the data state. If the host uses partial blocks whose \naccumulated length is not block-aligned and block misalignment is not allowed, the card \ndetects a block misalignment error condition at the beginning of the first misaligned block \n(ADDRESS_ERROR error bit is set in the status register).\n31.4.7 \nStream access, stream write and stream read \n(MultiMediaCard only)\nIn stream mode, data is transferred in bytes and no CRC is appended at the end of each \nblock.\nStream write (MultiMediaCard only)\nWRITE_DAT_UNTIL_STOP (CMD20) starts the data transfer from the SDIO card host to the \ncard, beginning at the specified address and continuing until the SDIO card host issues a \nstop command. When partial blocks are allowed (CSD parameter WRITE_BL_PARTIAL is \nset), the data stream can start and stop at any address within the card address space, \notherwise it can only start and stop at block boundaries. Because the amount of data to be \ntransferred is not determined in advance, a CRC cannot be used. When the end of the \nmemory range is reached while sending data and no stop command is sent by the SD card \nhost, any additional transferred data are discarded.\n" }, { "page_number": 1041, "page_indices": { "start_index": 2025243, "end_index": 2027694 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1041 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.7 Stream access, stream write and stream read (MultiMediaCard only)", 1040 ], [ 4, "Stream read (MultiMediaCard only)", 1041 ] ], "page_content": "RM0090 Rev 21\n1041/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nThe maximum clock frequency for a stream write operation is given by the following \nequation fields of the card-specific data register:\n•\nMaximumspeed = maximum write frequency\n•\nTRANSPEED = maximum data transfer rate\n•\nwritebllen = maximum write data block length\n•\nNSAC = data read access time 2 in CLK cycles\n•\nTAAC = data read access time 1\n•\nR2WFACTOR = write speed factor\nIf the host attempts to use a higher frequency, the card may not be able to process the data \nand stop programming, set the OVERRUN error bit in the status register, and while ignoring \nall further data transfer, wait (in the receive data state) for a stop command. The write \noperation is also aborted if the host tries to write over a write-protected area. In this case, \nhowever, the card sets the WP_VIOLATION bit.\nStream read (MultiMediaCard only)\nREAD_DAT_UNTIL_STOP (CMD11) controls a stream-oriented data transfer.\nThis command instructs the card to send its data, starting at a specified address, until the \nSDIO card host sends STOP_TRANSMISSION (CMD12). The stop command has an \nexecution delay due to the serial command transmission and the data transfer stops after \nthe end bit of the stop command. When the end of the memory range is reached while \nsending data and no stop command is sent by the SDIO card host, any subsequent data \nsent are considered undefined.\nThe maximum clock frequency for a stream read operation is given by the following \nequation and uses fields of the card specific data register.\n•\nMaximumspeed = maximum read frequency\n•\nTRANSPEED = maximum data transfer rate\n•\nreadbllen = maximum read data block length\n•\nwritebllen = maximum write data block length\n•\nNSAC = data read access time 2 in CLK cycles\n•\nTAAC = data read access time 1\n•\nR2WFACTOR = write speed factor\nIf the host attempts to use a higher frequency, the card is not able to sustain data transfer. If \nthis happens, the card sets the UNDERRUN error bit in the status register, aborts the \ntransmission and waits in the data state for a stop command.\nMaximumspeed\nMIN TRANSPEED 8\n2writebllen\n×\n(\n)\nNSAC\n–\n(\n)\nTAAC\nR2WFACTOR\n×\n-------------------------------------------------------------------------\n(\n,\n)\n=\nMaximumspeed\nMIN TRANSPEED 8\n2readbllen\n×\n(\n)\nNSAC\n–\n(\n)\nTAAC\nR2WFACTOR\n×\n------------------------------------------------------------------------\n(\n,\n)\n=\n" }, { "page_number": 1042, "page_indices": { "start_index": 2027694, "end_index": 2030847 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1042 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.8 Erase: group erase and sector erase", 1042 ], [ 3, "31.4.9 Wide bus selection or deselection", 1042 ], [ 3, "31.4.10 Protection management", 1042 ], [ 4, "Internal card write protection", 1042 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1042/1757\nRM0090 Rev 21\n31.4.8 \nErase: group erase and sector erase\nThe erasable unit of the MultiMediaCard is the erase group. The erase group is measured in \nwrite blocks, which are the basic writable units of the card. The size of the erase group is a \ncard-specific parameter and defined in the CSD.\nThe host can erase a contiguous range of Erase Groups. Starting the erase process is a \nthree-step sequence.\nFirst the host defines the start address of the range using the ERASE_GROUP_START \n(CMD35) command, next it defines the last address of the range using the \nERASE_GROUP_END (CMD36) command and, finally, it starts the erase process by issuing \nthe ERASE (CMD38) command. The address field in the erase commands is an Erase \nGroup address in byte units. The card ignores all LSBs below the Erase Group size, \neffectively rounding the address down to the Erase Group boundary.\nIf an erase command is received out of sequence, the card sets the ERASE_SEQ_ERROR \nbit in the status register and resets the whole sequence.\nIf an out-of-sequence (neither of the erase commands, except SEND_STATUS) command \nreceived, the card sets the ERASE_RESET status bit in the status register, resets the erase \nsequence and executes the last command.\nIf the erase range includes write protected blocks, they are left intact and only unprotected \nblocks are erased. The WP_ERASE_SKIP status bit in the status register is set.\nThe card indicates that an erase is in progress by holding SDIO_D low. The actual erase \ntime may be quite long, and the host may issue CMD7 to deselect the card.\n31.4.9 \nWide bus selection or deselection\nWide bus (4-bit bus width) operation mode is selected or deselected using \nSET_BUS_WIDTH (ACMD6). The default bus width after power-up or GO_IDLE_STATE \n(CMD0) is 1 bit. SET_BUS_WIDTH (ACMD6) is only valid in a transfer state, which means \nthat the bus width can be changed only after a card is selected by \nSELECT/DESELECT_CARD (CMD7).\n31.4.10 \nProtection management\nThree write protection methods for the cards are supported in the SDIO card host module:\n1.\ninternal card write protection (card responsibility)\n2. \nmechanical write protection switch (SDIO card host module responsibility only)\n3. \npassword-protected card lock operation\nInternal card write protection\nCard data can be protected against write and erase. By setting the permanent or temporary \nwrite-protect bits in the CSD, the entire card can be permanently write-protected by the \nmanufacturer or content provider. For cards that support write protection of groups of \nsectors by setting the WP_GRP_ENABLE bit in the CSD, portions of the data can be \nprotected, and the write protection can be changed by the application. The write protection \nis in units of WP_GRP_SIZE sectors as specified in the CSD. The SET_WRITE_PROT and \nCLR_WRITE_PROT commands control the protection of the addressed group. The \nSEND_WRITE_PROT command is similar to a single block read command. The card sends \na data block containing 32 write protection bits (representing 32 write protect groups starting \n" }, { "page_number": 1043, "page_indices": { "start_index": 2030847, "end_index": 2033877 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1043 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.10 Protection management", 1042 ], [ 4, "Mechanical write protect switch", 1043 ], [ 4, "Password protect", 1043 ], [ 4, "Setting the password", 1043 ] ], "page_content": "RM0090 Rev 21\n1043/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nat the specified address) followed by 16 CRC bits. The address field in the write protect \ncommands is a group address in byte units.\nThe card ignores all LSBs below the group size.\nMechanical write protect switch\nA mechanical sliding tab on the side of the card allows the user to set or clear the write \nprotection on a card. When the sliding tab is positioned with the window open, the card is \nwrite-protected, and when the window is closed, the card contents can be changed. A \nmatched switch on the socket side indicates to the SDIO card host module that the card is \nwrite-protected. The SDIO card host module is responsible for protecting the card. The \nposition of the write protect switch is unknown to the internal circuitry of the card.\nPassword protect\nThe password protection feature enables the SDIO card host module to lock and unlock a \ncard with a password. The password is stored in the 128-bit PWD register and its size is set \nin the 8-bit PWD_LEN register. These registers are nonvolatile so that a power cycle does \nnot erase them. Locked cards respond to and execute certain commands. This means that \nthe SDIO card host module is allowed to reset, initialize, select, and query for status, \nhowever it is not allowed to access data on the card. When the password is set (as indicated \nby a nonzero value of PWD_LEN), the card is locked automatically after power-up. As with \nthe CSD and CID register write commands, the lock/unlock commands are available in the \ntransfer state only. In this state, the command does not include an address argument and \nthe card must be selected before using it. The card lock/unlock commands have the \nstructure and bus transaction types of a regular single-block write command. The \ntransferred data block includes all of the required information for the command (the \npassword setting mode, the PWD itself, and card lock/unlock). The command data block \nsize is defined by the SDIO card host module before it sends the card lock/unlock \ncommand, and has the structure shown in Table 172.\nThe bit settings are as follows:\n•\nERASE: setting it forces an erase operation. All other bits must be zero, and only the \ncommand byte is sent\n•\nLOCK_UNLOCK: setting it locks the card. LOCK_UNLOCK can be set simultaneously \nwith SET_PWD, however not with CLR_PWD\n•\nCLR_PWD: setting it clears the password data\n•\nSET_PWD: setting it saves the password data to memory\n•\nPWD_LEN: it defines the length of the password in bytes\n•\nPWD: the password (new or currently used, depending on the command)\nThe following sections list the command sequences to set/reset a password, lock/unlock the \ncard, and force an erase.\nSetting the password\n1.\nSelect a card (SELECT/DESELECT_CARD, CMD7), if none is already selected.\n2. \nDefine the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card \nlock/unlock mode, the 8-bit PWD_LEN, and the number of bytes of the new password. \n" }, { "page_number": 1044, "page_indices": { "start_index": 2033877, "end_index": 2037176 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1044 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.10 Protection management", 1042 ], [ 4, "Resetting the password", 1044 ], [ 4, "Locking a card", 1044 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1044/1757\nRM0090 Rev 21\nWhen a password replacement is done, the block size must take into account that both \nthe old and the new passwords are sent with the command.\n3. \nSend LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line \nincluding the 16-bit CRC. The data block indicates the mode (SET_PWD = 1), the \nlength (PWD_LEN), and the password (PWD) itself. When a password replacement is \ndone, the length value (PWD_LEN) includes the length of both passwords, the old and \nthe new one, and the PWD field includes the old password (currently used) followed by \nthe new password.\n4. \nWhen the password is matched, the new password and its size are saved into the PWD \nand PWD_LEN fields, respectively. When the old password sent does not correspond \n(in size and/or content) to the expected password, the LOCK_UNLOCK_FAILED error \nbit is set in the card status register, and the password is not changed.\nThe password length field (PWD_LEN) indicates whether a password is currently set. When \nthis field is nonzero, there is a password set and the card locks itself after power-up. It is \npossible to lock the card immediately in the current power session by setting the \nLOCK_UNLOCK bit (while setting the password) or sending an additional command for card \nlocking.\nResetting the password\n1.\nSelect a card (SELECT/DESELECT_CARD, CMD7), if none is already selected.\n2. \nDefine the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card \nlock/unlock mode, the 8-bit PWD_LEN, and the number of bytes in the currently used \npassword.\n3. \nSend LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line \nincluding the 16-bit CRC. The data block indicates the mode (CLR_PWD = 1), the \nlength (PWD_LEN) and the password (PWD) itself. The LOCK_UNLOCK bit is ignored.\n4. \nWhen the password is matched, the PWD field is cleared and PWD_LEN is set to 0. \nWhen the password sent does not correspond (in size and/or content) to the expected \npassword, the LOCK_UNLOCK_FAILED error bit is set in the card status register, and \nthe password is not changed.\nLocking a card\n1.\nSelect a card (SELECT/DESELECT_CARD, CMD7), if none is already selected.\n2. \nDefine the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card \nlock/unlock mode (byte 0 in Table 172), the 8-bit PWD_LEN, and the number of bytes \nof the current password.\n3. \nSend LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line \nincluding the 16-bit CRC. The data block indicates the mode (LOCK_UNLOCK = 1), the \nlength (PWD_LEN), and the password (PWD) itself.\n4. \nWhen the password is matched, the card is locked and the CARD_IS_LOCKED status \nbit is set in the card status register. When the password sent does not correspond (in \nsize and/or content) to the expected password, the LOCK_UNLOCK_FAILED error bit \nis set in the card status register, and the lock fails.\nIt is possible to set the password and to lock the card in the same sequence. In this case, \nthe SDIO card host module performs all the required steps for setting the password (see \nSetting the password on page 1043), however it is necessary to set the LOCK_UNLOCK bit \nin Step 3 when the new password command is sent.\n" }, { "page_number": 1045, "page_indices": { "start_index": 2037176, "end_index": 2040186 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1045 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.10 Protection management", 1042 ], [ 4, "Unlocking the card", 1045 ], [ 4, "Forcing erase", 1045 ], [ 3, "31.4.11 Card status register", 1045 ] ], "page_content": "RM0090 Rev 21\n1045/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nWhen the password is previously set (PWD_LEN is not 0), the card is locked automatically \nafter power-on reset. An attempt to lock a locked card or to lock a card that does not have a \npassword fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register.\nUnlocking the card\n1.\nSelect a card (SELECT/DESELECT_CARD, CMD7), if none is already selected.\n2. \nDefine the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit \ncardlock/unlock mode (byte 0 in Table 172), the 8-bit PWD_LEN, and the number of \nbytes of the current password.\n3. \nSend LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line \nincluding the 16-bit CRC. The data block indicates the mode (LOCK_UNLOCK = 0), the \nlength (PWD_LEN), and the password (PWD) itself.\n4. \nWhen the password is matched, the card is unlocked and the CARD_IS_LOCKED \nstatus bit is cleared in the card status register. When the password sent is not correct in \nsize and/or content and does not correspond to the expected password, the \nLOCK_UNLOCK_FAILED error bit is set in the card status register, and the card \nremains locked.\nThe unlocking function is only valid for the current power session. When the PWD field is not \nclear, the card is locked automatically on the next power-up.\nAn attempt to unlock an unlocked card fails and the LOCK_UNLOCK_FAILED error bit is set \nin the card status register.\nForcing erase\nIf the user has forgotten the password (PWD content), it is possible to access the card after \nclearing all the data on the card. This forced erase operation erases all card data and all \npassword data.\n1.\nSelect a card (SELECT/DESELECT_CARD, CMD7), if none is already selected.\n2. \nSet the block length (SET_BLOCKLEN, CMD16) to 1 byte. Only the 8-bit card \nlock/unlock byte (byte 0 in Table 172) is sent.\n3. \nSend LOCK/UNLOCK (CMD42) with the appropriate data byte on the data line including \nthe 16-bit CRC. The data block indicates the mode (ERASE = 1). All other bits must be \nzero.\n4. \nWhen the ERASE bit is the only bit set in the data field, all card contents are erased, \nincluding the PWD and PWD_LEN fields, and the card is no longer locked. When any \nother bits are set, the LOCK_UNLOCK_FAILED error bit is set in the card status \nregister and the card retains all of its data, and remains locked.\nAn attempt to use a force erase on an unlocked card fails and the LOCK_UNLOCK_FAILED \nerror bit is set in the card status register.\n31.4.11 \nCard status register\nThe response format R1 contains a 32-bit field named card status. This field is intended to \ntransmit the card status information (which may be stored in a local status register) to the \nhost. If not specified otherwise, the status entries are always related to the previously issued \ncommand.\nTable 159 defines the different entries of the status. The type and clear condition fields in \nthe table are abbreviated as follows:\n" }, { "page_number": 1046, "page_indices": { "start_index": 2040186, "end_index": 2042201 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1046 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.11 Card status register", 1045 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1046/1757\nRM0090 Rev 21\nType:\n•\nE: error bit\n•\nS: status bit\n•\nR: detected and set for the actual command response\n•\nX: detected and set during command execution. The SDIO card host must poll the card \nby issuing the status command to read these bits.\nClear condition:\n•\nA: according to the card current state\n•\nB: always related to the previous command. Reception of a valid command clears it \n(with a delay of one command)\n•\nC: clear by read\n \nTable 159. Card status\nBits\nIdentifier\nType \nValue\nDescription \nClear \ncondition\n31\nADDRESS_ \nOUT_OF_RANGE \nE R X ’0’= no error \n’1’= error \nThe command address argument was out \nof the allowed range for this card.\nA multiple block or stream read/write \noperation is (although started in a valid \naddress) attempting to read or write \nbeyond the card capacity.\nC\n30\nADDRESS_MISALIGN \n-\n’0’= no error \n’1’= error \nThe commands address argument (in \naccordance with the currently set block \nlength) positions the first data block \nmisaligned to the card physical blocks.\nA multiple block read/write operation \n(although started with a valid \naddress/block-length combination) is \nattempting to read or write a data block \nwhich is not aligned with the physical \nblocks of the card. \nC\n29\nBLOCK_LEN_ERROR \n-\n’0’= no error \n’1’= error \nEither the argument of a \nSET_BLOCKLEN command exceeds the \nmaximum value allowed for the card, or \nthe previously defined block length is \nillegal for the current command (e.g. the \nhost issues a write command, the current \nblock length is smaller than the maximum \nallowed value for the card and it is not \nallowed to write partial blocks) \nC\n28\nERASE_SEQ_ERROR \n-\n’0’= no error\n’1’= error \nAn error in the sequence of erase \ncommands occurred. \nC\n27\nERASE_PARAM \nE X\n’0’= no error \n’1’= error \nAn invalid selection of erase groups for \nerase occurred. \nC\n26\nWP_VIOLATION \nE X\n’0’= no error \n’1’= error \nAttempt to program a write-protected \nblock. \nC\n" }, { "page_number": 1047, "page_indices": { "start_index": 2042201, "end_index": 2044114 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1047 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.11 Card status register", 1045 ] ], "page_content": "RM0090 Rev 21\n1047/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n25\nCARD_IS_LOCKED \nS R \n‘0’ = card \nunlocked\n‘1’ = card locked \nWhen set, signals that the card is locked \nby the host \nA\n24\nLOCK_UNLOCK_ \nFAILED \nE X\n’0’= no error \n’1’= error \nSet when a sequence or password error \nhas been detected in lock/unlock card \ncommand \nC\n23\nCOM_CRC_ERROR \nE R\n’0’= no error \n’1’= error \nThe CRC check of the previous command \nfailed. \nB\n22\nILLEGAL_COMMAND \nE R\n’0’= no error \n’1’= error \nCommand not legal for the card state \nB\n21\nCARD_ECC_FAILED \nE X\n’0’= success\n’1’= failure \nCard internal ECC was applied but failed \nto correct the data. \nC\n20\nCC_ERROR \nE R\n’0’= no error\n’1’= error \n(Undefined by the standard) A card error \noccurred, which is not related to the host \ncommand. \nC\n19\nERROR \nE X\n’0’= no error \n’1’= error \n(Undefined by the standard) A generic \ncard error related to the (and detected \nduring) execution of the last host \ncommand (e.g. read or write failures). \nC\n18\nReserved\n17\nReserved\n16\nCID/CSD_OVERWRITE \nE X\n’0’= no error ‘1’= \nerror \nCan be either of the following errors:\n– The CID register has already been \nwritten and cannot be overwritten\n– The read-only section of the CSD does \nnot match the card contents\n– An attempt to reverse the copy (set as \noriginal) or permanent WP \n(unprotected) bits was made\nC\n15\nWP_ERASE_SKIP \nE X\n’0’= not protected\n’1’= protected \nSet when only partial address space \nwas erased due to existing write\nC\n14\nCARD_ECC_DISABLED\nS X\n’0’= enabled\n’1’= disabled\nThe command has been executed without \nusing the internal ECC.\nA\n13\nERASE_RESET \n-\n’0’= cleared \n’1’= set \nAn erase sequence was cleared before \nexecuting because an out of erase \nsequence command was received \n(commands other than CMD35, CMD36, \nCMD38 or CMD13) \nC\nTable 159. Card status (continued)\nBits\nIdentifier\nType \nValue\nDescription \nClear \ncondition\n" }, { "page_number": 1048, "page_indices": { "start_index": 2044114, "end_index": 2046094 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1048 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.12 SD status register", 1048 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1048/1757\nRM0090 Rev 21\n31.4.12 \nSD status register\nThe SD status contains status bits that are related to the SD memory card proprietary \nfeatures and may be used for future application-specific usage. The size of the SD Status is \none data block of 512 bits. The contents of this register are transmitted to the SDIO card \nhost if ACMD13 is sent (CMD55 followed with CMD13). ACMD13 can be sent to a card in \ntransfer state only (card is selected).\nTable 160 defines the different entries of the SD status register. The type and clear condition \nfields in the table are abbreviated as follows:\nType:\n•\nE: error bit\n•\nS: status bit\n•\nR: detected and set for the actual command response\n•\nX: detected and set during command execution. The SDIO card Host must poll the card \nby issuing the status command to read these bits\n12:9\nCURRENT_STATE \nS R\n0 = Idle\n1 = Ready \n2 = Ident \n3 = Stby \n4 = Tran \n5 = Data \n6 = Rcv \n7 = Prg \n8 = Dis \n9 = Btst \n10-15 = reserved \nThe state of the card when receiving the \ncommand. If the command execution \ncauses a state change, it is visible to the \nhost in the response on the next \ncommand. The four bits are interpreted as \na binary number between 0 and 15. \nB\n8\nREADY_FOR_DATA \nS R\n’0’= not ready ‘1’ \n= ready \nCorresponds to buffer empty signalling on \nthe bus \n-\n7\nSWITCH_ERROR \nE X\n’0’= no error\n’1’= switch error \nIf set, the card did not switch to the \nexpected mode as requested by the \nSWITCH command \nB\n6\nReserved\n5\nAPP_CMD \nS R\n‘0’ = Disabled \n‘1’ = Enabled \nThe card expects ACMD, or an indication \nthat the command has been interpreted \nas ACMD\nC\n4\nReserved for SD I/O Card\n3\nAKE_SEQ_ERROR\nE R\n’0’= no error \n’1’= error \nError in the sequence of the \nauthentication process\nC\n2\nReserved for application specific commands \n1\nReserved for manufacturer test mode \n0\nTable 159. Card status (continued)\nBits\nIdentifier\nType \nValue\nDescription \nClear \ncondition\n" }, { "page_number": 1049, "page_indices": { "start_index": 2046094, "end_index": 2047928 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1049 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.12 SD status register", 1048 ] ], "page_content": "RM0090 Rev 21\n1049/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nClear condition:\n•\nA: according to the card current state\n•\nB: always related to the previous command. Reception of a valid command clears it \n(with a delay of one command)\n•\nC: clear by read\n \nTable 160. SD status\nBits\nIdentifier\nType\nValue\nDescription \nClear \ncondition\n511: 510\nDAT_BUS_WIDTH S R\n’00’= 1 (default)\n‘01’= reserved\n‘10’= 4 bit width\n‘11’= reserved\nShows the currently defined \ndatabus width that was \ndefined by \nSET_BUS_WIDTH \ncommand\nA\n509\nSECURED_MODE S R\n’0’= Not in the mode\n’1’= In Secured Mode\nCard is in Secured Mode of \noperation (refer to the “SD \nSecurity Specification”).\nA\n508: 496 Reserved\n495: 480 SD_CARD_TYPE\nS R\n’00xxh’= SD Memory Cards as \ndefined in Physical Spec Ver1.01-\n2.00 (’x’= don’t care). The \nfollowing cards are currently \ndefined:\n’0000’= Regular SD RD/WR Card.\n’0001’= SD ROM Card\nIn the future, the 8 LSBs are \nused to define different \nvariations of an SD memory \ncard (each bit defines \ndifferent SD types). The 8 \nMSBs are used to define SD \nCards that do not comply \nwith current SD physical \nlayer specification.\nA\n479: 448 SIZE_OF_PROTE\nCT ED_AREA\nS R\nSize of protected area (See \nbelow)\n(See below)\nA\n447: 440 SPEED_CLASS\nS R\nSpeed Class of the card (See \nbelow)\n(See below)\nA\n439: 432 PERFORMANCE_\nMOVE\nS R\nPerformance of move indicated by \n1 [MB/s] step.\n(See below)\n(See below)\nA\n431:428\nAU_SIZE\nS R\nSize of AU\n(See below)\n(See below)\nA\n427:424\nReserved\n423:408\nERASE_SIZE\nS R\nNumber of AUs to be erased at a \ntime\n(See below)\nA\n407:402\nERASE_TIMEOUT S R\nTimeout value for erasing areas \nspecified by \nUNIT_OF_ERASE_AU\n(See below)\nA\n401:400\nERASE_OFFSET\nS R\nFixed offset value added to erase \ntime.\n(See below)\nA\n399:312\nReserved\n311:0\nReserved for Manufacturer\n" }, { "page_number": 1050, "page_indices": { "start_index": 2047928, "end_index": 2049238 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1050 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.12 SD status register", 1048 ], [ 4, "SIZE_OF_PROTECTED_AREA", 1050 ], [ 4, "SPEED_CLASS", 1050 ], [ 4, "PERFORMANCE_MOVE", 1050 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1050/1757\nRM0090 Rev 21\nSIZE_OF_PROTECTED_AREA\nSetting this field differs between standard- and high-capacity cards. In the case of a \nstandard-capacity card, the capacity of protected area is calculated as follows:\nProtected area = SIZE_OF_PROTECTED_AREA_* MULT * BLOCK_LEN.\nSIZE_OF_PROTECTED_AREA is specified by the unit in MULT*BLOCK_LEN.\nIn the case of a high-capacity card, the capacity of protected area is specified in this field:\nProtected area = SIZE_OF_PROTECTED_AREA\nSIZE_OF_PROTECTED_AREA is specified by the unit in bytes.\nSPEED_CLASS\nThis 8-bit field indicates the speed class and the value can be calculated by PW/2 (where \nPW is the write performance).\n \nPERFORMANCE_MOVE\nThis 8-bit field indicates Pm (performance move) and the value can be set by 1 [MB/sec] \nsteps. If the card does not move used RUs (recording units), Pm should be considered as \ninfinity. Setting the field to FFh means infinity.\n \nTable 161. Speed class code field\nSPEED_CLASS\nValue definition\n00h\nClass 0\n01h\nClass 2\n02h\nClass 4\n03h\nClass 6\n04h – FFh\nReserved\nTable 162. Performance move field\nPERFORMANCE_MOVE\nValue definition\n00h\nNot defined\n01h\n1 [MB/sec]\n02h\n02h 2 [MB/sec]\n---------\n---------\nFEh\n254 [MB/sec]\nFFh\n Infinity\n" }, { "page_number": 1051, "page_indices": { "start_index": 2049238, "end_index": 2050490 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1051 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.12 SD status register", 1048 ], [ 4, "AU_SIZE", 1051 ], [ 4, "ERASE_SIZE", 1051 ] ], "page_content": "RM0090 Rev 21\n1051/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nAU_SIZE\nThis 4-bit field indicates the AU size and the value can be selected in the power of 2 base \nfrom 16 KB.\n \nThe maximum AU size, which depends on the card capacity, is defined in Table 164. The \ncard can be set to any AU size between RU size and maximum AU size.\n \nERASE_SIZE\nThis 16-bit field indicates NERASE. When NERASE numbers of AUs are erased, the \ntimeout value is specified by ERASE_TIMEOUT (Refer to ERASE_TIMEOUT). The host \nshould determine the proper number of AUs to be erased in one operation so that the host \ncan show the progress of the erase operation. If this field is set to 0, the erase timeout \ncalculation is not supported.\n \nTable 163. AU_SIZE field\nAU_SIZE\nValue definition\n00h\nNot defined\n01h\n16 KB\n02h\n32 KB\n03h\n64 KB\n04h\n128 KB\n05h\n256 KB\n06h\n512 KB\n07h\n1 MB\n08h\n2 MB\n09h\n4 MB\nAh – Fh\nReserved\nTable 164. Maximum AU size\nCapacity\n16 MB-64 MB\n128 MB-256 MB\n512 MB\n1 GB-32 GB\nMaximum AU Size\n512 KB\n1 MB\n2 MB\n4 MB\nTable 165. Erase size field\nERASE_SIZE\nValue definition\n0000h \nErase timeout calculation is not supported.\n0001h \n1 AU\n0002h\n2 AU\n0003h\n3 AU\n---------\n---------\nFFFFh\n65535 AU\n" }, { "page_number": 1052, "page_indices": { "start_index": 2050490, "end_index": 2052610 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1052 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.12 SD status register", 1048 ], [ 4, "ERASE_TIMEOUT", 1052 ], [ 4, "ERASE_OFFSET", 1052 ], [ 3, "31.4.13 SD I/O mode", 1052 ], [ 4, "SD I/O interrupts", 1052 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1052/1757\nRM0090 Rev 21\nERASE_TIMEOUT\nThis 6-bit field indicates TERASE and the value indicates the erase timeout from offset \nwhen multiple AUs are being erased as specified by ERASE_SIZE. The range of \nERASE_TIMEOUT can be defined as up to 63 seconds and the card manufacturer can \nchoose any combination of ERASE_SIZE and ERASE_TIMEOUT depending on the \nimplementation. Determining ERASE_TIMEOUT determines the ERASE_SIZE.\n \nERASE_OFFSET\nThis 2-bit field indicates TOFFSET and one of four values can be selected. This field is \nmeaningless if the ERASE_SIZE and ERASE_TIMEOUT fields are set to 0.\n \n31.4.13 \nSD I/O mode\nSD I/O interrupts\nTo allow the SD I/O card to interrupt the MultiMediaCard/SD module, an interrupt function is \navailable on a pin on the SD interface. Pin 8, used as SDIO_D1 when operating in the 4-bit \nSD mode, signals the cards interrupt to the MultiMediaCard/SD module. The use of the \ninterrupt is optional for each card or function within a card. The SD I/O interrupt is level-\nsensitive, which means that the interrupt line must be held active (low) until it is either \nrecognized and acted upon by the MultiMediaCard/SD module or deasserted due to the end \nof the interrupt period. After the MultiMediaCard/SD module has serviced the interrupt, the \ninterrupt status bit is cleared via an I/O write to the appropriate bit in the SD I/O card’s \ninternal registers. The interrupt output of all SD I/O cards is active low and the application \nmust provide external pull-up resistors on all data lines (SDIO_D[3:0]). The \nMultiMediaCard/SD module samples the level of pin 8 (SDIO_D/IRQ) into the interrupt \ndetector only during the interrupt period. At all other times, the MultiMediaCard/SD module \nignores this value.\nTable 166. Erase timeout field\nERASE_TIMEOUT\nValue definition\n00 \nErase timeout calculation is not supported.\n01 \n1 [sec]\n02\n2 [sec]\n03\n3 [sec]\n---------\n---------\n63\n63 [sec]\nTable 167. Erase offset field\nERASE_OFFSET\nValue definition\n0h \n0 [sec]\n1h \n1 [sec]\n2h\n2 [sec]\n3h\n3 [sec]\n" }, { "page_number": 1053, "page_indices": { "start_index": 2052610, "end_index": 2055874 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1053 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.13 SD I/O mode", 1052 ], [ 4, "SD I/O suspend and resume", 1053 ], [ 4, "SD I/O ReadWait", 1053 ], [ 3, "31.4.14 Commands and responses", 1053 ], [ 4, "Application-specific and general commands", 1053 ] ], "page_content": "RM0090 Rev 21\n1053/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nThe interrupt period is applicable for both memory and I/O operations. The definition of the \ninterrupt period for operations with single blocks is different from the definition for multiple-\nblock data transfers.\nSD I/O suspend and resume\nWithin a multifunction SD I/O or a card with both I/O and memory functions, there are \nmultiple devices (I/O and memory) that share access to the MMC/SD bus. To share access \nto the MMC/SD module among multiple devices, SD I/O and combo cards optionally \nimplement the concept of suspend/resume. When a card supports suspend/resume, the \nMMC/SD module can temporarily halt a data transfer operation to one function or memory \n(suspend) to free the bus for a higher-priority transfer to a different function or memory. After \nthis higher-priority transfer is complete, the original transfer is resumed (restarted) where it \nleft off. Support of suspend/resume is optional on a per-card basis. To perform the \nsuspend/resume operation on the MMC/SD bus, the MMC/SD module performs the \nfollowing steps:\n1.\nDetermines the function currently using the SDIO_D [3:0] line(s)\n2. \nRequests the lower-priority or slower transaction to suspend\n3. \nWaits for the transaction suspension to complete\n4. \nBegins the higher-priority transaction\n5. \nWaits for the completion of the higher priority transaction\n6. \nRestores the suspended transaction\nSD I/O ReadWait\nThe optional ReadWait (RW) operation is defined only for the SD 1-bit and 4-bit modes. The \nReadWait operation allows the MMC/SD module to signal a card that it is reading multiple \nregisters (IO_RW_EXTENDED, CMD53) to temporarily stall the data transfer while allowing \nthe MMC/SD module to send commands to any function within the SD I/O device. To \ndetermine when a card supports the ReadWait protocol, the MMC/SD module must test \ncapability bits in the internal card registers. The timing for ReadWait is based on the \ninterrupt period.\n31.4.14 \nCommands and responses\nApplication-specific and general commands\nThe SD card host module system is designed to provide a standard interface for a variety of \napplications types. In this environment, there is a need for specific customer/application \nfeatures. To implement these features, two types of generic commands are defined in the \nstandard: application-specific commands (ACMD) and general commands (GEN_CMD).\nWhen the card receives the APP_CMD (CMD55) command, the card expects the next \ncommand to be an application-specific command. ACMDs have the same structure as \nregular MultiMediaCard commands and can have the same CMD number. The card \nrecognizes it as ACMD because it appears after APP_CMD (CMD55). When the command \nimmediately following the APP_CMD (CMD55) is not a defined application-specific \ncommand, the standard command is used. For example, when the card has a definition for \nSD_STATUS (ACMD13), and receives CMD13 immediately following APP_CMD (CMD55), \nthis is interpreted as SD_STATUS (ACMD13). However, when the card receives CMD7 \nimmediately following APP_CMD (CMD55) and the card does not have a definition for \nACMD7, this is interpreted as the standard (SELECT/DESELECT_CARD) CMD7.\n" }, { "page_number": 1054, "page_indices": { "start_index": 2055874, "end_index": 2058235 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1054 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.14 Commands and responses", 1053 ], [ 4, "Command types", 1054 ], [ 4, "Command formats", 1054 ], [ 4, "Commands for the MultiMediaCard/SD module", 1054 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1054/1757\nRM0090 Rev 21\nTo use one of the manufacturer-specific ACMDs the SD card Host must perform the \nfollowing steps:\n1.\nSend APP_CMD (CMD55)\nThe card responds to the MultiMediaCard/SD module, indicating that the APP_CMD bit \nis set and an ACMD is now expected.\n2. \nSend the required ACMD\nThe card responds to the MultiMediaCard/SD module, indicating that the APP_CMD bit \nis set and that the accepted command is interpreted as an ACMD. When a nonACMD \nis sent, it is handled by the card as a normal MultiMediaCard command and the \nAPP_CMD bit in the card status register stays clear.\nWhen an invalid command is sent (neither ACMD nor CMD) it is handled as a standard \nMultiMediaCard illegal command error.\nThe bus transaction for a GEN_CMD is the same as the single-block read or write \ncommands (WRITE_BLOCK, CMD24 or READ_SINGLE_BLOCK,CMD17). In this case, the \nargument denotes the direction of the data transfer rather than the address, and the data \nblock has vendor-specific format and meaning.\nThe card must be selected (in transfer state) before sending GEN_CMD (CMD56). The data \nblock size is defined by SET_BLOCKLEN (CMD16). The response to GEN_CMD (CMD56) \nis in R1b format.\nCommand types\nBoth application-specific and general commands are divided into the four following types:\n•\nbroadcast command (BC): sent to all cards; no responses returned.\n•\nbroadcast command with response (BCR): sent to all cards; responses received \nfrom all cards simultaneously.\n•\naddressed (point-to-point) command (AC): sent to the card that is selected; does \nnot include a data transfer on the SDIO_D line(s).\n•\naddressed (point-to-point) data transfer command (ADTC): sent to the card that is \nselected; includes a data transfer on the SDIO_D line(s).\nCommand formats\nSee Table 152 on page 1030 for command formats.\nCommands for the MultiMediaCard/SD module\n \nTable 168. Block-oriented write commands\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nCMD23\nac\n[31:16] set to 0 \n[15:0] number \nof blocks\nR1\nSET_BLOCK_COUNT\nDefines the number of blocks which \nare going to be transferred in the \nmultiple-block read or write command \nthat follows.\nCMD24\nadtc\n[31:0] data \naddress\nR1\nWRITE_BLOCK\nWrites a block of the size selected by \nthe SET_BLOCKLEN command.\n" }, { "page_number": 1055, "page_indices": { "start_index": 2058235, "end_index": 2060303 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1055 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.14 Commands and responses", 1053 ], [ 4, "Commands for the MultiMediaCard/SD module", 1054 ] ], "page_content": "RM0090 Rev 21\n1055/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n \n \nCMD25\nadtc\n[31:0] data \naddress\nR1\nWRITE_MULTIPLE_BLOCK\nContinuously writes blocks of data \nuntil a STOP_TRANSMISSION \nfollows or the requested number of \nblocks has been received.\nCMD26\nadtc\n[31:0] stuff bits R1\nPROGRAM_CID\nProgramming of the card identification \nregister. This command must be \nissued only once per card. The card \ncontains hardware to prevent this \noperation after the first programming. \nNormally this command is reserved \nfor manufacturer.\nCMD27\nadtc\n[31:0] stuff bits R1\nPROGRAM_CSD\nProgramming of the programmable \nbits of the CSD.\nTable 168. Block-oriented write commands (continued)\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nTable 169. Block-oriented write protection commands\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nCMD28\nac\n[31:0] data \naddress\nR1b\nSET_WRITE_PROT\nIf the card has write protection features, \nthis command sets the write protection bit \nof the addressed group. The properties of \nwrite protection are coded in the card-\nspecific data (WP_GRP_SIZE).\nCMD29\nac\n[31:0] data \naddress\nR1b\nCLR_WRITE_PROT\nIf the card provides write protection \nfeatures, this command clears the write \nprotection bit of the addressed group.\nCMD30\nadtc\n[31:0] write \nprotect data \naddress\nR1\nSEND_WRITE_PROT\nIf the card provides write protection \nfeatures, this command asks the card to \nsend the status of the write protection \nbits. \nCMD31\nReserved\nTable 170. Erase commands\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nCMD32\n...\nCMD34\nReserved. These command indexes cannot be used in order to maintain backward compatibility with older \nversions of the MultiMediaCard.\nCMD35 ac\n[31:0] data address R1\nERASE_GROUP_START\nSets the address of the first erase \ngroup within a range to be selected \nfor erase.\nCMD36 ac\n[31:0] data address R1\nERASE_GROUP_END\nSets the address of the last erase \ngroup within a continuous range to be \nselected for erase.\n" }, { "page_number": 1056, "page_indices": { "start_index": 2060303, "end_index": 2062200 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1056 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.4 Card functional description", 1037 ], [ 3, "31.4.14 Commands and responses", 1053 ], [ 4, "Commands for the MultiMediaCard/SD module", 1054 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1056/1757\nRM0090 Rev 21\n \n \n \nCMD37 Reserved. This command index cannot be used in order to maintain backward compatibility with older \nversions of the MultiMediaCards\nCMD38 ac\n[31:0] stuff bits\nR1\nERASE\nErases all previously selected write \nblocks.\nTable 170. Erase commands (continued)\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nTable 171. I/O mode commands\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nCMD39\nac\n[31:16] RCA \n[15:15] register \nwrite flag \n[14:8] register \naddress \n[7:0] register data\nR4\nFAST_IO\nUsed to write and read 8-bit (register) data \nfields. The command addresses a card and a \nregister and provides the data for writing if \nthe write flag is set. The R4 response \ncontains data read from the addressed \nregister. This command accesses \napplication-dependent registers that are not \ndefined in the MultiMediaCard standard.\nCMD40\nbcr\n[31:0] stuff bits\nR5\nGO_IRQ_STATE Places the system in the interrupt mode.\nCMD41\nReserved\nTable 172. Lock card\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nCMD42\nadtc\n[31:0] stuff bits\nR1b\nLOCK_UNLOCK\nSets/resets the password or locks/unlocks \nthe card. The size of the data block is set \nby the SET_BLOCK_LEN command.\nCMD43 \n... \nCMD54\nReserved\nTable 173. Application-specific commands\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nCMD55\nac\n[31:16] RCA\n[15:0] stuff bits\nR1\nAPP_CMD\nIndicates to the card that the next command \nbits is an application specific command rather \nthan a standard command\nCMD56\nadtc\n[31:1] stuff bits\n[0]: RD/WR\n-\n-\nUsed either to transfer a data block to the card \nor to get a data block from the card for general \npurpose/application-specific commands. The \nsize of the data block is set by the \nSET_BLOCK_LEN command.\n" }, { "page_number": 1057, "page_indices": { "start_index": 2062200, "end_index": 2064005 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1057 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.5 Response formats", 1057 ], [ 3, "31.5.1 R1 (normal response command)", 1057 ], [ 3, "31.5.2 R1b", 1057 ], [ 3, "31.5.3 R2 (CID, CSD register)", 1057 ] ], "page_content": "RM0090 Rev 21\n1057/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.5 \nResponse formats\nAll responses are sent via the MCCMD command line SDIO_CMD. The response \ntransmission always starts with the left bit of the bit string corresponding to the response \ncode word. The code length depends on the response type.\nA response always starts with a start bit (always 0), followed by the bit indicating the \ndirection of transmission (card = 0). A value denoted by x in the tables below indicates a \nvariable entry. All responses, except for the R3 response type, are protected by a CRC. \nEvery command code word is terminated by the end bit (always 1).\nThere are five types of responses. Their formats are defined as follows:\n31.5.1 \nR1 (normal response command)\nCode length = 48 bits. The 45:40 bits indicate the index of the command to be responded to, \nthis value being interpreted as a binary-coded number (between 0 and 63). The status of the \ncard is coded in 32 bits.\n \n31.5.2 \nR1b\nIt is identical to R1 with an optional busy signal transmitted on the data line. The card may \nbecome busy after receiving these commands based on its state prior to the command \nreception.\n31.5.3 \nR2 (CID, CSD register)\nCode length = 136 bits. The contents of the CID register are sent as a response to the \nCMD2 and CMD10 commands. The contents of the CSD register are sent as a response to \nCMD57 \n... \nCMD59\nReserved.\nCMD60 \n... \nCMD63\nReserved for manufacturer.\nTable 173. Application-specific commands (continued)\nCMD \nindex\nType\nArgument\nResponse \nformat\nAbbreviation\nDescription\nTable 174. R1 response\nBit position\nWidth (bits\nValue\nDescription\n47\n1\n0\nStart bit\n46\n1\n0\nTransmission bit\n[45:40]\n6\nX\nCommand index\n[39:8]\n32\nX\nCard status\n[7:1]\n7\nX\nCRC7\n0\n1\n1\nEnd bit\n" }, { "page_number": 1058, "page_indices": { "start_index": 2064005, "end_index": 2065435 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1058 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.5 Response formats", 1057 ], [ 3, "31.5.4 R3 (OCR register)", 1058 ], [ 3, "31.5.5 R4 (Fast I/O)", 1058 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1058/1757\nRM0090 Rev 21\nCMD9. Only the bits [127...1] of the CID and CSD are transferred, the reserved bit [0] of \nthese registers is replaced by the end bit of the response. The card indicates that an erase \nis in progress by holding MCDAT low. The actual erase time may be quite long, and the host \nmay issue CMD7 to deselect the card.\n \n31.5.4 \nR3 (OCR register)\nCode length: 48 bits. The contents of the OCR register are sent as a response to CMD1. \nThe level coding is as follows: restricted voltage windows = low, card busy = low.\n \n31.5.5 \nR4 (Fast I/O)\nCode length: 48 bits. The argument field contains the RCA of the addressed card, the \nregister address to be read from or written to, and its content.\n \nTable 175. R2 response\nBit position\nWidth (bits\nValue\nDescription\n135\n1\n0\nStart bit\n134\n1\n0\nTransmission bit\n[133:128]\n6\n‘111111’\nCommand index\n[127:1]\n127\nX\nCard status\n0\n1\n1\nEnd bit\nTable 176. R3 response\nBit position\nWidth (bits\nValue\nDescription\n47\n1\n0\nStart bit\n46\n1\n0\nTransmission bit\n[45:40]\n6\n‘111111’\nReserved\n[39:8]\n32\nX\nOCR register\n[7:1]\n7\n‘1111111’\nReserved\n0\n1\n1\nEnd bit\nTable 177. R4 response\nBit position\nWidth (bits\nValue\nDescription\n47\n1\n0\nStart bit\n46\n1\n0\nTransmission bit\n[45:40]\n6\n‘100111’\nCMD39\n[39:8] Argument field\n[31:16]\n16\nX\nRCA\n[15:8]\n8\nX\nregister address\n[7:0]\n8\nX\nread register contents\n" }, { "page_number": 1059, "page_indices": { "start_index": 2065435, "end_index": 2067131 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1059 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.5 Response formats", 1057 ], [ 3, "31.5.6 R4b", 1059 ], [ 3, "31.5.7 R5 (interrupt request)", 1059 ] ], "page_content": "RM0090 Rev 21\n1059/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.5.6 \nR4b\nFor SD I/O only: an SDIO card receiving the CMD5 responds with a unique SDIO response \nR4. The format is:\n \nOnce an SD I/O card has received a CMD5, the I/O portion of that card is enabled to \nrespond normally to all further commands. This I/O enable of the function within the I/O card \nremains set until a reset, power cycle or CMD52 with write to I/O reset is received by the \ncard. Note that an SD memory-only card may respond to a CMD5. The proper response for \na memory-only card would be Present memory = 1 and Number of I/O functions = 0. A \nmemory-only card built to meet the SD Memory Card specification version 1.0 would detect \nthe CMD5 as an illegal command and not respond. The I/O aware host sends CMD5. If the \ncard responds with response R4, the host determines the card’s configuration based on the \ndata contained within the R4 response.\n31.5.7 \nR5 (interrupt request)\nOnly for MultiMediaCard. Code length: 48 bits. If the response is generated by the host, the \nRCA field in the argument is 0x0.\n \n[7:1]\n7\nX\nCRC7\n0\n1\n1\nEnd bit\nTable 177. R4 response (continued)\nBit position\nWidth (bits\nValue\nDescription\nTable 178. R4b response\nBit position\nWidth (bits\nValue\nDescription\n47\n1\n0\nStart bit\n46\n1\n0\nTransmission bit\n[45:40]\n6\nx\nReserved\n[39:8] Argument field\n39\n16\nX\nCard is ready\n[38:36]\n3\nX\nNumber of I/O functions\n35\n1\nX\nPresent memory\n[34:32]\n3\nX\nStuff bits\n[31:8]\n24\nX\nI/O ORC\n[7:1]\n7\nX\nReserved\n0\n1\n1\nEnd bit\nTable 179. R5 response\nBit position\nWidth (bits\nValue\nDescription\n47\n1\n0\nStart bit\n46\n1\n0\nTransmission bit\n[45:40]\n6\n‘101000’\nCMD40\n" }, { "page_number": 1060, "page_indices": { "start_index": 2067131, "end_index": 2068529 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1060 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.5 Response formats", 1057 ], [ 3, "31.5.8 R6", 1060 ], [ 2, "31.6 SDIO I/O card-specific operations", 1060 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1060/1757\nRM0090 Rev 21\n31.5.8 \nR6\nOnly for SD I/O. The normal response to CMD3 by a memory device. It is shown in \nTable 180.\n \nThe card [23:8] status bits are changed when CMD3 is sent to an I/O-only card. In this case, \nthe 16 bits of response are the SD I/O-only values:\n•\nBit [15] COM_CRC_ERROR\n•\nBit [14] ILLEGAL_COMMAND\n•\nBit [13] ERROR\n•\nBits [12:0] Reserved\n31.6 \nSDIO I/O card-specific operations\nThe following features are SD I/O-specific operations:\n•\nSDIO read wait operation by SDIO_D2 signalling\n•\nSDIO read wait operation by stopping the clock\n•\nSDIO suspend/resume operation (write and read suspend)\n•\nSDIO interrupts\nThe SDIO supports these operations only if the SDIO_DCTRL[11] bit is set, except for read \nsuspend that does not need specific hardware implementation.\n[39:8] Argument field\n[31:16]\n16\nX\nRCA [31:16] of winning \ncard or of the host\n[15:0]\n16\nX\nNot defined. May be used \nfor IRQ data\n[7:1]\n7\nX\nCRC7\n0\n1\n1\nEnd bit\nTable 179. R5 response (continued)\nBit position\nWidth (bits\nValue\nDescription\nTable 180. R6 response\nBit position\nWidth (bits)\nValue\nDescription\n47\n1\n0\nStart bit\n46\n1\n0\nTransmission bit\n[45:40]\n6\n‘101000’\nCMD40\n[39:8] Argument \nfield\n[31:16]\n16\nX\nRCA [31:16] of winning card or of the host\n[15:0]\n16\nX\nNot defined. May be used for IRQ data\n[7:1]\n7\nX\nCRC7\n0\n1\n1\nEnd bit\n" }, { "page_number": 1061, "page_indices": { "start_index": 2068529, "end_index": 2071370 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1061 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.6 SDIO I/O card-specific operations", 1060 ], [ 3, "31.6.1 SDIO I/O read wait operation by SDIO_D2 signaling", 1061 ], [ 3, "31.6.2 SDIO read wait operation by stopping SDIO_CK", 1061 ], [ 3, "31.6.3 SDIO suspend/resume operation", 1061 ], [ 3, "31.6.4 SDIO interrupts", 1061 ] ], "page_content": "RM0090 Rev 21\n1061/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.6.1 \nSDIO I/O read wait operation by SDIO_D2 signaling\nIt is possible to start the readwait interval before the first block is received: when the data \npath is enabled (SDIO_DCTRL[0] bit set), the SDIO-specific operation is enabled \n(SDIO_DCTRL[11] bit set), read wait starts (SDI0_DCTRL[10] =0 and SDI_DCTRL[8] =1) \nand data direction is from card to SDIO (SDIO_DCTRL[1] = 1), the DPSM directly moves \nfrom Idle to Readwait. In Readwait the DPSM drives SDIO_D2 to 0 after 2 SDIO_CK clock \ncycles. In this state, when you set the RWSTOP bit (SDIO_DCTRL[9]), the DPSM remains \nin Wait for two more SDIO_CK clock cycles to drive SDIO_D2 to 1 for one clock cycle (in \naccordance with SDIO specification). The DPSM then starts waiting again until it receives \ndata from the card. The DPSM does not start a readwait interval while receiving a block \neven if read wait start is set: the readwait interval starts after the CRC is received. The \nRWSTOP bit has to be cleared to start a new read wait operation. During the readwait \ninterval, the SDIO can detect SDIO interrupts on SDIO_D1.\n31.6.2 \nSDIO read wait operation by stopping SDIO_CK\nIf the SDIO card does not support the previous read wait method, the SDIO can perform a \nread wait by stopping SDIO_CK (SDIO_DCTRL is set just like in the method presented in \nSection 31.6.1, but SDIO_DCTRL[10] =1): DSPM stops the clock two SDIO_CK cycles after \nthe end bit of the current received block and starts the clock again after the read wait start bit \nis set.\nAs SDIO_CK is stopped, any command can be issued to the card. During a read/wait \ninterval, the SDIO can detect SDIO interrupts on SDIO_D1.\n31.6.3 \nSDIO suspend/resume operation\nWhile sending data to the card, the SDIO can suspend the write operation. the \nSDIO_CMD[11] bit is set and indicates to the CPSM that the current command is a suspend \ncommand. The CPSM analyzes the response and when the ACK is received from the card \n(suspend accepted), it acknowledges the DPSM that goes Idle after receiving the CRC \ntoken of the current block.\nThe hardware does not save the number of the remaining block to be sent to complete the \nsuspended operation (resume).\nThe write operation can be suspended by software, just by disabling the DPSM \n(SDIO_DCTRL[0] =0) when the ACK of the suspend command is received from the card. \nThe DPSM enters then the Idle state.\nTo suspend a read: the DPSM waits in the Wait_r state as the function to be suspended \nsends a complete packet just before stopping the data transaction. The application \ncontinues reading RxFIFO until the FIF0 is empty, and the DPSM goes Idle automatically.\n31.6.4 \nSDIO interrupts\nSDIO interrupts are detected on the SDIO_D1 line once the SDIO_DCTRL[11] bit is set.\n" }, { "page_number": 1062, "page_indices": { "start_index": 2071370, "end_index": 2073449 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1062 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.7 CE-ATA specific operations", 1062 ], [ 3, "31.7.1 Command completion signal disable", 1062 ], [ 3, "31.7.2 Command completion signal enable", 1062 ], [ 3, "31.7.3 CE-ATA interrupt", 1062 ], [ 3, "31.7.4 Aborting CMD61", 1062 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1062/1757\nRM0090 Rev 21\n31.7 \nCE-ATA specific operations\nThe following features are CE-ATA specific operations:\n•\nsending the command completion signal disable to the CE-ATA device\n•\nreceiving the command completion signal from the CE-ATA device\n•\nsignaling the completion of the CE-ATA command to the CPU, using the status bit \nand/or interrupt.\nThe SDIO supports these operations only for the CE-ATA CMD61 command, that is, if \nSDIO_CMD[14] is set.\n31.7.1 \nCommand completion signal disable\nCommand completion signal disable is sent 8 bit cycles after the reception of a short \nresponse if the ‘enable CMD completion’ bit, SDIO_CMD[12], is not set and the ‘not interrupt \nEnable’ bit, SDIO_CMD[13], is set.\nThe CPSM enters the Pend state, loading the command shift register with the disable \nsequence “00001” and, the command counter with 43. Eight cycles after, a trigger moves \nthe CPSM to the Send state. When the command counter reaches 48, the CPSM becomes \nIdle as no response is awaited.\n31.7.2 \nCommand completion signal enable\nIf the ‘enable CMD completion’ bit SDIO_CMD[12] is set and the ‘not interrupt Enable’ bit \nSDIO_CMD[13] is set, the CPSM waits for the command completion signal in the Waitcpl \nstate.\nWhen ‘0’ is received on the CMD line, the CPSM enters the Idle state. No new command \ncan be sent for 7 bit cycles. Then, for the last 5 cycles (out of the 7) the CMD line is driven to \n‘1’ in push-pull mode.\n31.7.3 \nCE-ATA interrupt\nThe command completion is signaled to the CPU by the status bit SDIO_STA[23]. This static \nbit can be cleared with the clear bit SDIO_ICR[23].\nThe SDIO_STA[23] status bit can generate an interrupt on each interrupt line, depending on \nthe mask bit SDIO_MASKx[23].\n31.7.4 \nAborting CMD61\nIf the command completion disable signal has not been sent and CMD61 needs to be \naborted, the command state machine must be disabled. It then becomes Idle, and the \nCMD12 command can be sent. No command completion disable signal is sent during the \noperation.\n" }, { "page_number": 1063, "page_indices": { "start_index": 2073449, "end_index": 2075007 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1063 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.8 HW flow control", 1063 ], [ 2, "31.9 SDIO registers", 1063 ], [ 3, "31.9.1 SDIO power control register (SDIO_POWER)", 1063 ] ], "page_content": "RM0090 Rev 21\n1063/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.8 \nHW flow control\nThe HW flow control functionality is used to avoid FIFO underrun (TX mode) and overrun \n(RX mode) errors.\nThe behavior is to stop SDIO_CK and freeze SDIO state machines. The data transfer is \nstalled while the FIFO is unable to transmit or receive data. Only state machines clocked by \nSDIOCLK are frozen, the APB2 interface is still alive. The FIFO can thus be filled or emptied \neven if flow control is activated.\nTo enable HW flow control, the SDIO_CLKCR[14] register bit must be set to 1. After reset \nFlow Control is disabled.\n31.9 \nSDIO registers\nThe device communicates to the system via 32-bit-wide control registers accessible via \nAPB2.\nThe peripheral registers have to be accessed by words (32 bits).\n31.9.1 \nSDIO power control register (SDIO_POWER)\nAddress offset: 0x00\nReset value: 0x0000 0000\n \nNote:\nAt least seven HCLK clock periods are needed between two write accesses to this register.\nAfter a data write, data cannot be written to this register for three SDIOCLK clock periods \nplus two PCLK2 clock periods.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPWRC\nTRL\nrw\nrw\nBits 31:2 Reserved, must be kept at reset value\nBits 1:0 PWRCTRL: Power supply control bits.\nThese bits are used to define the current functional state of the card clock:\n00: Power-off: the clock to card is stopped.\n01: Reserved\n10: Reserved power-up\n11: Power-on: the card is clocked.\n" }, { "page_number": 1064, "page_indices": { "start_index": 2075007, "end_index": 2076922 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1064 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.9 SDIO registers", 1063 ], [ 3, "31.9.2 SDI clock control register (SDIO_CLKCR)", 1064 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1064/1757\nRM0090 Rev 21\n31.9.2 \nSDI clock control register (SDIO_CLKCR)\nAddress offset: 0x04\nReset value: 0x0000 0000\nThe SDIO_CLKCR register controls the SDIO_CK output clock.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nHWFC_EN\nNEGEDGE\nWID\nBUS\nBYPASS\nPWRSAV\nCLKEN\nCLKDIV\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:15 Reserved, must be kept at reset value\nBit 14 HWFC_EN: HW Flow Control enable\n0b: HW Flow Control is disabled\n1b: HW Flow Control is enabled\nWhen HW Flow Control is enabled, the meaning of the TXFIFOE and RXFIFOF interrupt \nsignals, see SDIO Status register definition in Section 31.9.11.\nBit 13 NEGEDGE:SDIO_CK dephasing selection bit\n0b: SDIO_CK generated on the rising edge of the master clock SDIOCLK\n1b: SDIO_CK generated on the falling edge of the master clock SDIOCLK\nBits 12:11 WIDBUS: Wide bus mode enable bit\n00: Default bus mode: SDIO_D0 used\n01: 4-wide bus mode: SDIO_D[3:0] used\n10: 8-wide bus mode: SDIO_D[7:0] used\nBit 10 BYPASS: Clock divider bypass enable bit\n0: Disable bypass: SDIOCLK is divided according to the CLKDIV value before driving the \nSDIO_CK output signal.\n1: Enable bypass: SDIOCLK directly drives the SDIO_CK output signal.\nBit 9 PWRSAV: Power saving configuration bit\nFor power saving, the SDIO_CK clock output can be disabled when the bus is idle by setting \nPWRSAV:\n0: SDIO_CK clock is always enabled\n1: SDIO_CK is only enabled when the bus is active\nBit 8 CLKEN: Clock enable bit\n0: SDIO_CK is disabled\n1: SDIO_CK is enabled\nBits 7:0 CLKDIV: Clock divide factor\nThis field defines the divide factor between the input clock (SDIOCLK) and the output clock \n(SDIO_CK): SDIO_CK frequency = SDIOCLK / [CLKDIV + 2].\nNote: In order to have a duty cycle of 50% it is recommended to select even values of \nCLKDIV.\n" }, { "page_number": 1065, "page_indices": { "start_index": 2076922, "end_index": 2079029 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1065 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.9 SDIO registers", 1063 ], [ 3, "31.9.3 SDIO argument register (SDIO_ARG)", 1065 ], [ 3, "31.9.4 SDIO command register (SDIO_CMD)", 1065 ] ], "page_content": "RM0090 Rev 21\n1065/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nNote:\nWhile the SD/SDIO card or MultiMediaCard is in identification mode, the SDIO_CK \nfrequency must be less than 400 kHz.\nThe clock frequency can be changed to the maximum card bus frequency when relative \ncard addresses are assigned to all cards.\nAfter a data write, data cannot be written to this register for three SDIOCLK clock periods \nplus two PCLK2 clock periods. SDIO_CK can also be stopped during the read wait interval \nfor SD I/O cards: in this case the SDIO_CLKCR register does not control SDIO_CK.\n31.9.3 \nSDIO argument register (SDIO_ARG)\nAddress offset: 0x08\nReset value: 0x0000 0000\nThe SDIO_ARG register contains a 32-bit command argument, which is sent to a card as \npart of a command message.\n \n \n31.9.4 \nSDIO command register (SDIO_CMD)\nAddress offset: 0x0C\nReset value: 0x0000 0000\nThe SDIO_CMD register contains the command index and command type bits. The \ncommand index is sent to a card as part of a command message. The command type bits \ncontrol the command path state machine (CPSM).\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCMDARG\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 CMDARG: Command argument\nCommand argument sent to a card as part of a command message. If a command contains \nan argument, it must be loaded into this register before writing a command to the command \nregister.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCE-ATACMD\nnIEN\nENCMDcompl\nSDIOSuspend\nCPSMEN\nWAITPEND\nWAITINT\nWAITRESP\nCMDINDEX\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:15 Reserved, must be kept at reset value\nBit 14 ATACMD: CE-ATA command\nIf ATACMD is set, the CPSM transfers CMD61.\nBit 13 nIEN: not Interrupt Enable\nif this bit is 0, interrupts in the CE-ATA device are enabled.\nBit 12 ENCMDcompl: Enable CMD completion\nIf this bit is set, the command completion signal is enabled.\n" }, { "page_number": 1066, "page_indices": { "start_index": 2079029, "end_index": 2081325 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1066 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.9 SDIO registers", 1063 ], [ 3, "31.9.5 SDIO command response register (SDIO_RESPCMD)", 1066 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1066/1757\nRM0090 Rev 21\nNote:\nAfter a data write, data cannot be written to this register for three SDIOCLK clock periods \nplus two PCLK2 clock periods.\nMultiMediaCards can send two kinds of response: short responses, 48 bits long, or long \nresponses,136 bits long. SD card and SD I/O card can send only short responses, the \nargument can vary according to the type of response: the software distinguishes the type of \nresponse according to the sent command. CE-ATA devices send only short responses.\n31.9.5 \nSDIO command response register (SDIO_RESPCMD)\nAddress offset: 0x10\nReset value: 0x0000 0000\nThe SDIO_RESPCMD register contains the command index field of the last command \nresponse received. If the command response transmission does not contain the command \nindex field (long or OCR response), the RESPCMD field is unknown, although it must \ncontain 111111b (the value of the reserved field from the response).\n \n \nBit 11 SDIOSuspend: SD I/O suspend command\nIf this bit is set, the command to be sent is a suspend command (to be used only with SDIO \ncard).\nBit 10 CPSMEN: Command path state machine (CPSM) Enable bit\nIf this bit is set, the CPSM is enabled.\nBit 9 WAITPEND: CPSM Waits for ends of data transfer (CmdPend internal signal).\nIf this bit is set, the CPSM waits for the end of data transfer before it starts sending a \ncommand.\nBit 8 WAITINT: CPSM waits for interrupt request\nIf this bit is set, the CPSM disables command timeout and waits for an interrupt request.\nBits 7:6 WAITRESP: Wait for response bits\nThey are used to configure whether the CPSM is to wait for a response, and if yes, which \nkind of response.\n00: No response, expect CMDSENT flag\n01: Short response, expect CMDREND or CCRCFAIL flag\n10: No response, expect CMDSENT flag\n11: Long response, expect CMDREND or CCRCFAIL flag\nBits 5:0 CMDINDEX: Command index\nThe command index is sent to the card as part of a command message.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRESPCMD\nr\nr\nr\nr\nr\nr\nBits 31:6 Reserved, must be kept at reset value\nBits 5:0 RESPCMD: Response command index\nRead-only bit field. Contains the command index of the last command response received.\n" }, { "page_number": 1067, "page_indices": { "start_index": 2081325, "end_index": 2083199 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1067 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.9 SDIO registers", 1063 ], [ 3, "31.9.6 SDIO response 1..4 register (SDIO_RESPx)", 1067 ], [ 3, "31.9.7 SDIO data timer register (SDIO_DTIMER)", 1067 ] ], "page_content": "RM0090 Rev 21\n1067/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.9.6 \nSDIO response 1..4 register (SDIO_RESPx)\nAddress offset: (0x10 + (4 × x)); x = 1..4\nReset value: 0x0000 0000\nThe SDIO_RESP1/2/3/4 registers contain the status of a card, which is part of the received \nresponse.\n \n \nThe Card Status size is 32 or 127 bits, depending on the response type.\n \nThe most significant bit of the card status is received first. The SDIO_RESP3 register LSB is \nalways 0b.\n31.9.7 \nSDIO data timer register (SDIO_DTIMER)\nAddress offset: 0x24\nReset value: 0x0000 0000\nThe SDIO_DTIMER register contains the data timeout period, in card bus clock periods. \nA counter loads the value from the SDIO_DTIMER register, and starts decrementing when \nthe data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 \nwhile the DPSM is in either of these states, the timeout status flag is set.\n \n \nNote:\nA data transfer must be written to the data timer register and the data length register before \nbeing written to the data control register.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCARDSTATUSx\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 CARDSTATUSx: see Table 181.\nTable 181. Response type and SDIO_RESPx registers\nRegister\nShort response\nLong response\nSDIO_RESP1\nCard Status[31:0]\nCard Status [127:96]\nSDIO_RESP2\nUnused\nCard Status [95:64]\nSDIO_RESP3\nUnused\nCard Status [63:32]\nSDIO_RESP4\nUnused\nCard Status [31:1]0b\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATATIME\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 DATATIME: Data timeout period\nData timeout period expressed in card bus clock periods.\n" }, { "page_number": 1068, "page_indices": { "start_index": 2083199, "end_index": 2084230 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1068 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.9 SDIO registers", 1063 ], [ 3, "31.9.8 SDIO data length register (SDIO_DLEN)", 1068 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1068/1757\nRM0090 Rev 21\n31.9.8 \nSDIO data length register (SDIO_DLEN)\nAddress offset: 0x28\nReset value: 0x0000 0000\nThe SDIO_DLEN register contains the number of data bytes to be transferred. The value is \nloaded into the data counter when data transfer starts.\n \n \nNote:\nFor a block data transfer, the value in the data length register must be a multiple of the block \nsize (see SDIO_DCTRL). A data transfer must be written to the data timer register and the \ndata length register before being written to the data control register.\nFor an SDIO multibyte transfer the value in the data length register must be between 1 and \n512.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDATALENGTH\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:25 Reserved, must be kept at reset value\nBits 24:0 DATALENGTH: Data length value\nNumber of data bytes to be transferred.\n" }, { "page_number": 1069, "page_indices": { "start_index": 2084230, "end_index": 2086090 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1069 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.9 SDIO registers", 1063 ], [ 3, "31.9.9 SDIO data control register (SDIO_DCTRL)", 1069 ] ], "page_content": "RM0090 Rev 21\n1069/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.9.9 \nSDIO data control register (SDIO_DCTRL)\nAddress offset: 0x2C\nReset value: 0x0000 0000\nThe SDIO_DCTRL register control the data path state machine (DPSM).\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSDIOEN\nRWMOD\nRWSTOP\nRWSTART\nDBLOCKSIZE\nDMAEN\nDTMODE\nDTDIR\nDTEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value\nBit 11 SDIOEN: SD I/O enable functions\nIf this bit is set, the DPSM performs an SD I/O-card-specific operation.\nBit 10 RWMOD: Read wait mode\n0: Read Wait control stopping SDIO_D2\n1: Read Wait control using SDIO_CK\nBit 9 RWSTOP: Read wait stop\n0: Read wait in progress if RWSTART bit is set\n1: Enable for read wait stop if RWSTART bit is set\nBit 8 RWSTART: Read wait start\nIf this bit is set, read wait operation starts.\nBits 7:4 DBLOCKSIZE: Data block size\nDefine the data block length when the block data transfer mode is selected:\n0000: (0 decimal) lock length = 20 = 1 byte\n0001: (1 decimal) lock length = 21 = 2 bytes\n0010: (2 decimal) lock length = 22 = 4 bytes\n0011: (3 decimal) lock length = 23 = 8 bytes\n0100: (4 decimal) lock length = 24 = 16 bytes\n0101: (5 decimal) lock length = 25 = 32 bytes\n0110: (6 decimal) lock length = 26 = 64 bytes\n0111: (7 decimal) lock length = 27 = 128 bytes\n1000: (8 decimal) lock length = 28 = 256 bytes\n1001: (9 decimal) lock length = 29 = 512 bytes\n1010: (10 decimal) lock length = 210 = 1024 bytes\n1011: (11 decimal) lock length = 211 = 2048 bytes\n1100: (12 decimal) lock length = 212 = 4096 bytes\n1101: (13 decimal) lock length = 213 = 8192 bytes\n1110: (14 decimal) lock length = 214 = 16384 bytes\n1111: (15 decimal) reserved\nBit 3 DMAEN: DMA enable bit\n0: DMA disabled.\n1: DMA enabled.\n" }, { "page_number": 1070, "page_indices": { "start_index": 2086090, "end_index": 2088073 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1070 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.9 SDIO registers", 1063 ], [ 3, "31.9.10 SDIO data counter register (SDIO_DCOUNT)", 1070 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1070/1757\nRM0090 Rev 21\nNote:\nAfter a data write, data cannot be written to this register for three SDIOCLK clock periods \nplus two PCLK2 clock periods.\nThe meaning of the DTMODE bit changes according to the value of the SDIOEN bit. When \nSDIOEN=0 and DTMODE=1, the MultiMediaCard stream mode is enabled, and when \nSDIOEN=1 and DTMODE=1, the peripheral enables an SDIO multibyte transfer.\n31.9.10 \nSDIO data counter register (SDIO_DCOUNT)\nAddress offset: 0x30\nReset value: 0x0000 0000\nThe SDIO_DCOUNT register loads the value from the data length register (see \nSDIO_DLEN) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As \ndata is transferred, the counter decrements the value until it reaches 0. The DPSM then \nmoves to the Idle state and the data status end flag, DATAEND, is set.\n \n \nNote:\nThis register should be read only when the data transfer is complete.\nBit 2 DTMODE: Data transfer mode selection 1: Stream or SDIO multibyte data transfer.\n0: Block data transfer\n1: Stream or SDIO multibyte data transfer\nBit 1 DTDIR: Data transfer direction selection\n0: From controller to card.\n1: From card to controller.\nBit 0 DTEN: Data transfer enabled bit\nData transfer starts if 1b is written to the DTEN bit. Depending on the direction bit, DTDIR, \nthe DPSM moves to the Wait_S, Wait_R state or Readwait if RW Start is set immediately at \nthe beginning of the transfer. It is not necessary to clear the enable bit after the end of a data \ntransfer but the SDIO_DCTRL must be updated to enable a new data transfer\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDATACOUNT\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:25 Reserved, must be kept at reset value\nBits 24:0 DATACOUNT: Data count value\nWhen this bit is read, the number of remaining data bytes to be transferred is returned. Write \nhas no effect.\n" }, { "page_number": 1071, "page_indices": { "start_index": 2088073, "end_index": 2090288 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1071 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.9 SDIO registers", 1063 ], [ 3, "31.9.11 SDIO status register (SDIO_STA)", 1071 ] ], "page_content": "RM0090 Rev 21\n1071/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.9.11 \nSDIO status register (SDIO_STA)\nAddress offset: 0x34\nReset value: 0x0000 0000\nThe SDIO_STA register is a read-only register. It contains two types of flag:\n•\nStatic flags (bits [23:22,10:0]): these bits remain asserted until they are cleared by \nwriting to the SDIO Interrupt Clear register (see SDIO_ICR)\n•\nDynamic flags (bits [21:11]): these bits change state depending on the state of the \nunderlying logic (for example, FIFO full and empty flags are asserted and deasserted \nas data while written to the FIFO)\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCEATAEND\nSDIOIT\nRXDAVL\nTXDAVL\nRXFIFOE\nTXFIFOE\nRXFIFOF\nTXFIFOF\nRXFIFOHF\nTXFIFOHE\nRXACT\nTXACT\nCMDACT\nDBCKEND\nSTBITERR\nDATAEND\nCMDSENT\nCMDREND\nRXOVERR\nTXUNDERR\nDTIMEOUT\nCTIMEOUT\nDCRCFAIL\nCCRCFAIL\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:24 Reserved, must be kept at reset value\nBit 23 CEATAEND: CE-ATA command completion signal received for CMD61\nBit 22 SDIOIT: SDIO interrupt received\nBit 21 RXDAVL: Data available in receive FIFO\nBit 20 TXDAVL: Data available in transmit FIFO\nBit 19 RXFIFOE: Receive FIFO empty\nBit 18 TXFIFOE: Transmit FIFO empty\nWhen HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO \ncontains 2 words.\nBit 17 RXFIFOF: Receive FIFO full\nWhen HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the \nFIFO is full.\nBit 16 TXFIFOF: Transmit FIFO full\nBit 15 RXFIFOHF: Receive FIFO half full: there are at least 8 words in the FIFO\nBit 14 TXFIFOHE: Transmit FIFO half empty: at least 8 words can be written into the FIFO\nBit 13 RXACT: Data receive in progress\nBit 12 TXACT: Data transmit in progress\nBit 11 CMDACT: Command transfer in progress\nBit 10 DBCKEND: Data block sent/received (CRC check passed)\nBit 9 STBITERR: Start bit not detected on all data signals in wide bus mode\nBit 8 DATAEND: Data end (data counter, SDIDCOUNT, is zero)\nBit 7 CMDSENT: Command sent (no response required)\nBit 6 CMDREND: Command response received (CRC check passed)\nBit 5 RXOVERR: Received FIFO overrun error\n" }, { "page_number": 1072, "page_indices": { "start_index": 2090288, "end_index": 2091938 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1072 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.9 SDIO registers", 1063 ], [ 3, "31.9.12 SDIO interrupt clear register (SDIO_ICR)", 1072 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1072/1757\nRM0090 Rev 21\n31.9.12 \nSDIO interrupt clear register (SDIO_ICR)\nAddress offset: 0x38\nReset value: 0x0000 0000\nThe SDIO_ICR register is a write-only register. Writing a bit with 1b clears the corresponding \nbit in the SDIO_STA Status register.\n \n \nBit 4 TXUNDERR: Transmit FIFO underrun error\nBit 3 DTIMEOUT: Data timeout\nBit 2 CTIMEOUT: Command response timeout\nThe Command TimeOut period has a fixed value of 64 SDIO_CK clock periods.\nBit 1 DCRCFAIL: Data block sent/received (CRC check failed)\nBit 0 CCRCFAIL: Command response received (CRC check failed)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCEATAENDC\nSDIOITC\nReserved\nDBCKENDC\nSTBITERRC\nDATAENDC\nCMDSENTC\nCMDRENDC\nRXOVERRC\nTXUNDERRC\nDTIMEOUTC\nCTIMEOUTC\nDCRCFAILC\nCCRCFAILC\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value\nBit 23 CEATAENDC: CEATAEND flag clear bit\nSet by software to clear the CEATAEND flag.\n0: CEATAEND not cleared\n1: CEATAEND cleared\nBit 22 SDIOITC: SDIOIT flag clear bit\nSet by software to clear the SDIOIT flag.\n0: SDIOIT not cleared\n1: SDIOIT cleared\nBits 21:11 Reserved, must be kept at reset value\nBit 10 DBCKENDC: DBCKEND flag clear bit\nSet by software to clear the DBCKEND flag.\n0: DBCKEND not cleared\n1: DBCKEND cleared\nBit 9 STBITERRC: STBITERR flag clear bit\nSet by software to clear the STBITERR flag.\n0: STBITERR not cleared\n1: STBITERR cleared\nBit 8 DATAENDC: DATAEND flag clear bit\nSet by software to clear the DATAEND flag.\n0: DATAEND not cleared\n1: DATAEND cleared\n" }, { "page_number": 1073, "page_indices": { "start_index": 2091938, "end_index": 2093055 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1073 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.9 SDIO registers", 1063 ], [ 3, "31.9.12 SDIO interrupt clear register (SDIO_ICR)", 1072 ] ], "page_content": "RM0090 Rev 21\n1073/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nBit 7 CMDSENTC: CMDSENT flag clear bit\nSet by software to clear the CMDSENT flag.\n0: CMDSENT not cleared\n1: CMDSENT cleared\nBit 6 CMDRENDC: CMDREND flag clear bit\nSet by software to clear the CMDREND flag.\n0: CMDREND not cleared\n1: CMDREND cleared\nBit 5 RXOVERRC: RXOVERR flag clear bit\nSet by software to clear the RXOVERR flag.\n0: RXOVERR not cleared\n1: RXOVERR cleared\nBit 4 TXUNDERRC: TXUNDERR flag clear bit\nSet by software to clear TXUNDERR flag.\n0: TXUNDERR not cleared\n1: TXUNDERR cleared\nBit 3 DTIMEOUTC: DTIMEOUT flag clear bit\nSet by software to clear the DTIMEOUT flag.\n0: DTIMEOUT not cleared\n1: DTIMEOUT cleared\nBit 2 CTIMEOUTC: CTIMEOUT flag clear bit\nSet by software to clear the CTIMEOUT flag.\n0: CTIMEOUT not cleared\n1: CTIMEOUT cleared\nBit 1 DCRCFAILC: DCRCFAIL flag clear bit\nSet by software to clear the DCRCFAIL flag.\n0: DCRCFAIL not cleared\n1: DCRCFAIL cleared\nBit 0 CCRCFAILC: CCRCFAIL flag clear bit\nSet by software to clear the CCRCFAIL flag.\n0: CCRCFAIL not cleared\n1: CCRCFAIL cleared\n" }, { "page_number": 1074, "page_indices": { "start_index": 2093055, "end_index": 2095593 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1074 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.9 SDIO registers", 1063 ], [ 3, "31.9.13 SDIO mask register (SDIO_MASK)", 1074 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1074/1757\nRM0090 Rev 21\n31.9.13 \nSDIO mask register (SDIO_MASK)\nAddress offset: 0x3C\nReset value: 0x0000 0000\nThe interrupt mask register determines which status flags generate an interrupt request by \nsetting the corresponding bit to 1b.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCEATAENDIE\nSDIOITIE\nRXDAVLIE\nTXDAVLIE\nRXFIFOEIE\nTXFIFOEIE\nRXFIFOFIE\nTXFIFOFIE\nRXFIFOHFIE\nTXFIFOHEIE\nRXACTIE\nTXACTIE\nCMDACTIE\nDBCKENDIE\nSTBITERRIE\nDATAENDIE\nCMDSENTIE\nCMDRENDIE\nRXOVERRIE\nTXUNDERRIE\nDTIMEOUTIE\nCTIMEOUTIE\nDCRCFAILIE\nCCRCFAILIE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value\nBit 23 CEATAENDIE: CE-ATA command completion signal received interrupt enable\nSet and cleared by software to enable/disable the interrupt generated when receiving the \nCE-ATA command completion signal.\n0: CE-ATA command completion signal received interrupt disabled\n1: CE-ATA command completion signal received interrupt enabled\nBit 22 SDIOITIE: SDIO mode interrupt received interrupt enable\nSet and cleared by software to enable/disable the interrupt generated when receiving the \nSDIO mode interrupt.\n0: SDIO Mode Interrupt Received interrupt disabled\n1: SDIO Mode Interrupt Received interrupt enabled\nBit 21 RXDAVLIE: Data available in Rx FIFO interrupt enable\nSet and cleared by software to enable/disable the interrupt generated by the presence of \ndata available in Rx FIFO.\n0: Data available in Rx FIFO interrupt disabled\n1: Data available in Rx FIFO interrupt enabled\nBit 20 TXDAVLIE: Data available in Tx FIFO interrupt enable\nSet and cleared by software to enable/disable the interrupt generated by the presence of \ndata available in Tx FIFO.\n0: Data available in Tx FIFO interrupt disabled\n1: Data available in Tx FIFO interrupt enabled\nBit 19 RXFIFOEIE: Rx FIFO empty interrupt enable\nSet and cleared by software to enable/disable interrupt caused by Rx FIFO empty.\n0: Rx FIFO empty interrupt disabled\n1: Rx FIFO empty interrupt enabled\nBit 18 TXFIFOEIE: Tx FIFO empty interrupt enable\nSet and cleared by software to enable/disable interrupt caused by Tx FIFO empty.\n0: Tx FIFO empty interrupt disabled\n1: Tx FIFO empty interrupt enabled\nBit 17 RXFIFOFIE: Rx FIFO full interrupt enable\nSet and cleared by software to enable/disable interrupt caused by Rx FIFO full.\n0: Rx FIFO full interrupt disabled\n1: Rx FIFO full interrupt enabled\n" }, { "page_number": 1075, "page_indices": { "start_index": 2095593, "end_index": 2097861 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1075 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.9 SDIO registers", 1063 ], [ 3, "31.9.13 SDIO mask register (SDIO_MASK)", 1074 ] ], "page_content": "RM0090 Rev 21\n1075/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\nBit 16 TXFIFOFIE: Tx FIFO full interrupt enable\nSet and cleared by software to enable/disable interrupt caused by Tx FIFO full.\n0: Tx FIFO full interrupt disabled\n1: Tx FIFO full interrupt enabled\nBit 15 RXFIFOHFIE: Rx FIFO half full interrupt enable\nSet and cleared by software to enable/disable interrupt caused by Rx FIFO half full.\n0: Rx FIFO half full interrupt disabled\n1: Rx FIFO half full interrupt enabled\nBit 14 TXFIFOHEIE: Tx FIFO half empty interrupt enable\nSet and cleared by software to enable/disable interrupt caused by Tx FIFO half empty.\n0: Tx FIFO half empty interrupt disabled\n1: Tx FIFO half empty interrupt enabled\nBit 13 RXACTIE: Data receive acting interrupt enable\nSet and cleared by software to enable/disable interrupt caused by data being received (data \nreceive acting).\n0: Data receive acting interrupt disabled\n1: Data receive acting interrupt enabled\nBit 12 TXACTIE: Data transmit acting interrupt enable\nSet and cleared by software to enable/disable interrupt caused by data being transferred \n(data transmit acting).\n0: Data transmit acting interrupt disabled\n1: Data transmit acting interrupt enabled\nBit 11 CMDACTIE: Command acting interrupt enable\nSet and cleared by software to enable/disable interrupt caused by a command being \ntransferred (command acting).\n0: Command acting interrupt disabled\n1: Command acting interrupt enabled\nBit 10 DBCKENDIE: Data block end interrupt enable\nSet and cleared by software to enable/disable interrupt caused by data block end.\n0: Data block end interrupt disabled\n1: Data block end interrupt enabled\nBit 9 STBITERRIE: Start bit error interrupt enable\nSet and cleared by software to enable/disable interrupt caused by start bit error.\n0: Start bit error interrupt disabled\n1: Start bit error interrupt enabled\nBit 8 DATAENDIE: Data end interrupt enable\nSet and cleared by software to enable/disable interrupt caused by data end.\n0: Data end interrupt disabled\n1: Data end interrupt enabled\nBit 7 CMDSENTIE: Command sent interrupt enable\nSet and cleared by software to enable/disable interrupt caused by sending command.\n0: Command sent interrupt disabled\n1: Command sent interrupt enabled\n" }, { "page_number": 1076, "page_indices": { "start_index": 2097861, "end_index": 2100340 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1076 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.9 SDIO registers", 1063 ], [ 3, "31.9.14 SDIO FIFO counter register (SDIO_FIFOCNT)", 1076 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1076/1757\nRM0090 Rev 21\n31.9.14 \nSDIO FIFO counter register (SDIO_FIFOCNT)\nAddress offset: 0x48\nReset value: 0x0000 0000\nThe SDIO_FIFOCNT register contains the remaining number of words to be written to or \nread from the FIFO. The FIFO counter loads the value from the data length register (see \nSDIO_DLEN) when the data transfer enable bit, DTEN, is set in the data control register \n(SDIO_DCTRL register) and the DPSM is at the Idle state. If the data length is not word-\naligned (multiple of 4), the remaining 1 to 3 bytes are regarded as a word.\n \n \nBit 6 CMDRENDIE: Command response received interrupt enable\nSet and cleared by software to enable/disable interrupt caused by receiving command \nresponse.\n0: Command response received interrupt disabled\n1: command Response Received interrupt enabled\nBit 5 RXOVERRIE: Rx FIFO overrun error interrupt enable\nSet and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error.\n0: Rx FIFO overrun error interrupt disabled\n1: Rx FIFO overrun error interrupt enabled\nBit 4 TXUNDERRIE: Tx FIFO underrun error interrupt enable\nSet and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error.\n0: Tx FIFO underrun error interrupt disabled\n1: Tx FIFO underrun error interrupt enabled\nBit 3 DTIMEOUTIE: Data timeout interrupt enable\nSet and cleared by software to enable/disable interrupt caused by data timeout.\n0: Data timeout interrupt disabled\n1: Data timeout interrupt enabled\nBit 2 CTIMEOUTIE: Command timeout interrupt enable\nSet and cleared by software to enable/disable interrupt caused by command timeout.\n0: Command timeout interrupt disabled\n1: Command timeout interrupt enabled\nBit 1 DCRCFAILIE: Data CRC fail interrupt enable\nSet and cleared by software to enable/disable interrupt caused by data CRC failure.\n0: Data CRC fail interrupt disabled\n1: Data CRC fail interrupt enabled\nBit 0 CCRCFAILIE: Command CRC fail interrupt enable\nSet and cleared by software to enable/disable interrupt caused by command CRC failure.\n0: Command CRC fail interrupt disabled\n1: Command CRC fail interrupt enabled\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFIFOCOUNT\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:24 Reserved, must be kept at reset value\nBits 23:0\nFIFOCOUNT: Remaining number of words to be written to or read from the FIFO.\n" }, { "page_number": 1077, "page_indices": { "start_index": 2100340, "end_index": 2101920 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1077 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.9 SDIO registers", 1063 ], [ 3, "31.9.15 SDIO data FIFO register (SDIO_FIFO)", 1077 ], [ 3, "31.9.16 SDIO register map", 1077 ] ], "page_content": "RM0090 Rev 21\n1077/1757\nRM0090\nSecure digital input/output interface (SDIO)\n1078\n31.9.15 \nSDIO data FIFO register (SDIO_FIFO)\nAddress offset: 0x80\nReset value: 0x0000 0000\nThe receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs \ncontain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store \nmultiple operands to read from/write to the FIFO.\n \n \n31.9.16 \nSDIO register map\nThe following table summarizes the SDIO registers. \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFIF0Data\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nbits 31:0 FIFOData: Receive and transmit FIFO data\nThe FIFO data occupies 32 entries of 32-bit words, from address:\nSDIO base + 0x080 to SDIO base + 0xFC.\nTable 182. SDIO register map\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nSDIO_POWER\nReserved\nPWRCTRL\n0x04\nSDIO_CLKCR\nReserved\nHWFC_EN\nNEGEDGE\nWIDBUS\nBYPASS\nPWRSAV\nCLKEN\nCLKDIV\n0x08\nSDIO_ARG\nCMDARG\n0x0C\nSDIO_CMD\nReserved\nCE-ATACMD\nnIEN\nENCMDcompl\nSDIOSuspend\nCPSMEN\nWAITPEND\nWAITINT\nWAITRESP\nCMDINDEX\n0x10\nSDIO_RESPCMD\nReserved\nRESPCMD\n0x14\nSDIO_RESP1\nCARDSTATUS1\n0x18\nSDIO_RESP2\nCARDSTATUS2\n0x1C\nSDIO_RESP3\nCARDSTATUS3\n0x20\nSDIO_RESP4\nCARDSTATUS4\n0x24\nSDIO_DTIMER\nDATATIME\n0x28\nSDIO_DLEN\nReserved\nDATALENGTH\n0x2C\nSDIO_DCTRL\nReserved\nSDIOEN\nRWMOD\nRWSTOP\nRWSTART\nDBLOCKSIZE\nDMAEN\nDTMODE\nDTDIR\nDTEN\n0x30\nSDIO_DCOUNT\nReserved\nDATACOUNT\n" }, { "page_number": 1078, "page_indices": { "start_index": 2101920, "end_index": 2102859 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1078 }, "toc_details": [ [ 1, "31 Secure digital input/output interface (SDIO)", 1022 ], [ 2, "31.9 SDIO registers", 1063 ], [ 3, "31.9.16 SDIO register map", 1077 ] ], "page_content": "Secure digital input/output interface (SDIO)\nRM0090\n1078/1757\nRM0090 Rev 21\n0x34\nSDIO_STA\nReserved\nCEATAEND\nSDIOIT\nRXDAVL\nTXDAVL\nRXFIFOE\nTXFIFOE\nRXFIFOF\nTXFIFOF\nRXFIFOHF\nTXFIFOHE\nRXACT\nTXACT\nCMDACT\nDBCKEND\nSTBITERR\nDATAEND\nCMDSENT\nCMDREND\nRXOVERR\nTXUNDERR\nDTIMEOUT\nCTIMEOUT\nDCRCFAIL\nCCRCFAIL\n0x38\nSDIO_ICR\nReserved\nCEATAENDC\nSDIOITC\nReserved\nDBCKENDC\nSTBITERRC\nDATAENDC\nCMDSENTC\nCMDRENDC\nRXOVERRC\nTXUNDERRC\nDTIMEOUTC\nCTIMEOUTC\nDCRCFAILC\nCCRCFAILC\n0x3C\nSDIO_MASK\nReserved\nCEATAENDIE\nSDIOITIE\nRXDAVLIE\nTXDAVLIE\nRXFIFOEIE\nTXFIFOEIE\nRXFIFOFIE\nTXFIFOFIE\nRXFIFOHFIE\nTXFIFOHEIE\nRXACTIE\nTXACTIE\nCMDACTIE\nDBCKENDIE\nSTBITERRIE\nDATAENDIE\nCMDSENTIE\nCMDRENDIE\nRXOVERRIE\nTXUNDERRIE\nDTIMEOUTIE\nCTIMEOUTIE\nDCRCFAILIE\nCCRCFAILIE\n0x48\nSDIO_FIFOCNT\nReserved\nFIFOCOUNT\n0x80\nSDIO_FIFO\nFIF0Data\nTable 182. SDIO register map (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1079, "page_indices": { "start_index": 2102859, "end_index": 2104236 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1079 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.1 bxCAN introduction", 1079 ], [ 2, "32.2 bxCAN main features", 1079 ], [ 3, "Transmission", 1079 ], [ 3, "Reception", 1079 ], [ 3, "Time-triggered communication option", 1079 ], [ 3, "Management", 1079 ] ], "page_content": "RM0090 Rev 21\n1079/1757\nRM0090\nController area network (bxCAN)\n1124\n32 \nController area network (bxCAN)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n32.1 \nbxCAN introduction\nThe Basic Extended CAN peripheral, named bxCAN, interfaces the CAN network. It \nsupports the CAN protocols version 2.0A and B. It has been designed to manage a high \nnumber of incoming messages efficiently with a minimum CPU load. It also meets the \npriority requirements for transmit messages. \nFor safety-critical applications, the CAN controller provides all hardware functions for \nsupporting the CAN Time Triggered Communication option.\n32.2 \nbxCAN main features\n•\nSupports CAN protocol version 2.0 A, B Active\n•\nBit rates up to 1 Mbit/s\n•\nSupports the Time Triggered Communication option\nTransmission\n•\nThree transmit mailboxes\n•\nConfigurable transmit priority\n•\nTime Stamp on SOF transmission\nReception\n•\nTwo receive FIFOs with three stages\n•\nScalable filter banks:\n–\n28 filter banks shared between CAN1 and CAN2\n•\nIdentifier list feature\n•\nConfigurable FIFO overrun\n•\nTime Stamp on SOF reception\nTime-triggered communication option\n•\nDisable automatic retransmission mode\n•\n16-bit free running timer\n•\nTime Stamp sent in last two data bytes\nManagement\n•\nMaskable interrupts\n•\nSoftware-efficient mailbox mapping at a unique address space\n" }, { "page_number": 1080, "page_indices": { "start_index": 2104236, "end_index": 2105804 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1080 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.2 bxCAN main features", 1079 ], [ 3, "Dual CAN", 1080 ], [ 2, "32.3 bxCAN general description", 1080 ], [ 3, "32.3.1 CAN 2.0B active core", 1080 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1080/1757\nRM0090 Rev 21\nDual CAN\n•\nCAN1: Master bxCAN for managing the communication between a Slave bxCAN and \nthe 512-byte SRAM memory\n•\nCAN2: Slave bxCAN, with no direct access to the SRAM memory. \n•\nThe two bxCAN cells share the 512-byte SRAM memory (see Figure 335)\n32.3 \nbxCAN general description\nIn today’s CAN applications, the number of nodes in a network is increasing and often \nseveral networks are linked together via gateways. Typically the number of messages in the \nsystem (and thus to be handled by each node) has significantly increased. In addition to the \napplication messages, Network Management and Diagnostic messages have been \nintroduced. \n•\nAn enhanced filtering mechanism is required to handle each type of message.\nFurthermore, application tasks require more CPU time, therefore real-time constraints \ncaused by message reception have to be reduced.\n•\nA receive FIFO scheme allows the CPU to be dedicated to application tasks for a long \ntime period without losing messages.\nThe standard HLP (Higher Layer Protocol) based on standard CAN drivers requires an \nefficient interface to the CAN controller.\nFigure 334. CAN network topology\n32.3.1 \nCAN 2.0B active core\nThe bxCAN module handles the transmission and the reception of CAN messages fully \nautonomously. Standard identifiers (11-bit) and extended identifiers (29-bit) are fully \nsupported by hardware.\nCAN node 1\nCAN node 2\nCAN node n\nCAN\nCAN\nHigh\nLow\nCAN\nCAN\nRx\nTx\nCAN\nTransceiver\nCAN\nController\nMCU\nCAN Bus\nApplication\n" }, { "page_number": 1081, "page_indices": { "start_index": 2105804, "end_index": 2106666 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1081 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.3 bxCAN general description", 1080 ], [ 3, "32.3.2 Control, status and configuration registers", 1081 ], [ 3, "32.3.3 Tx mailboxes", 1081 ], [ 3, "32.3.4 Acceptance filters", 1081 ], [ 4, "Receive FIFO", 1081 ] ], "page_content": "RM0090 Rev 21\n1081/1757\nRM0090\nController area network (bxCAN)\n1124\n32.3.2 \nControl, status and configuration registers\nThe application uses these registers to:\n•\nConfigure CAN parameters, e.g. baud rate\n•\nRequest transmissions\n•\nHandle receptions\n•\nManage interrupts\n•\nGet diagnostic information\n32.3.3 \nTx mailboxes\nThree transmit mailboxes are provided to the software for setting up messages. The \ntransmission Scheduler decides which mailbox has to be transmitted first.\n32.3.4 \nAcceptance filters\nThe bxCAN provides 28 scalable/configurable identifier filter banks for selecting the \nincoming messages the software needs and discarding the others. \nReceive FIFO\nTwo receive FIFOs are used by hardware to store the incoming messages. Three complete \nmessages can be stored in each FIFO. The FIFOs are managed completely by hardware. \n" }, { "page_number": 1082, "page_indices": { "start_index": 2106666, "end_index": 2108301 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1082 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.4 bxCAN operating modes", 1082 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1082/1757\nRM0090 Rev 21\nFigure 335. Dual CAN block diagram\n32.4 \nbxCAN operating modes\nbxCAN has three main operating modes: initialization, normal and Sleep. After a \nhardware reset, bxCAN is in Sleep mode to reduce power consumption and an internal pull-\nup is active on CANTX. The software requests bxCAN to enter initialization or Sleep mode \nby setting the INRQ or SLEEP bits in the CAN_MCR register. Once the mode has been \nentered, bxCAN confirms it by setting the INAK or SLAK bits in the CAN_MSR register and \nthe internal pull-up is disabled. When neither INAK nor SLAK are set, bxCAN is in normal \n26\n..\nAcceptance Filters\n..\n3\n2\n1\nFilter \n0\n27\nTransmission\nScheduler\nMailbox 0\n1\n2\nReceive FIFO 1\nMailbox 0\n1\n2\nReceive FIFO 0\nMailbox 0\n1\n2\nTx Mailboxes\nTransmission\nScheduler\nMailbox 0\n1\n2\nReceive FIFO 1\nMailbox 0\n1\n2\nReceive FIFO 0\nMailbox 0\n1\n2\nTx Mailboxes\nMemory \nAccess \nController\nMaster Control\nMaster Status\nRx FIFO 0 Status\nRx FIFO 1 Status\nError Status\nBit Timing\nInterrupt Enable\nControl/Status/Configuration\nTx Status\nMaster Control\nMaster Status\nRx FIFO 0 Status\nRx FIFO 1 Status\nError Status\nBit Timing\nFilter Mode\nFilter Scale\nInterrupt Enable\nControl/Status/Configuration\nTx Status\nFilter FIFO Assign\nFilter Master\nFilter Activation\nCAN 2.0B Active Core\nCAN2 (Slave)\nCAN 2.0B Active Core\nCAN1 (Master) with 512 bytes SRAM\nMaster\nr\ne\nts\na\nM\nr\ne\nts\na\nM\nMaster Filters\nSlave\nSlave\nSlave\nSlave Filters\n(0 to 27)\n(0 to 27)\nNote: CAN 2 start filter bank number n is confi gurable by writing to\nthe CAN2SB[5:0] bits in the CAN_ FMR register.\nai16094b\n" }, { "page_number": 1083, "page_indices": { "start_index": 2108301, "end_index": 2111271 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1083 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.4 bxCAN operating modes", 1082 ], [ 3, "32.4.1 Initialization mode", 1083 ], [ 3, "32.4.2 Normal mode", 1083 ], [ 3, "32.4.3 Sleep mode (low-power)", 1083 ] ], "page_content": "RM0090 Rev 21\n1083/1757\nRM0090\nController area network (bxCAN)\n1124\nmode. Before entering normal mode bxCAN always has to synchronize on the CAN bus. \nTo synchronize, bxCAN waits until the CAN bus is idle, this means 11 consecutive recessive \nbits have been monitored on CANRX.\n32.4.1 \nInitialization mode\nThe software initialization can be done while the hardware is in Initialization mode. To enter \nthis mode the software sets the INRQ bit in the CAN_MCR register and waits until the \nhardware has confirmed the request by setting the INAK bit in the CAN_MSR register.\nTo leave Initialization mode, the software clears the INRQ bit. bxCAN has left Initialization \nmode once the INAK bit has been cleared by hardware.\nWhile in Initialization Mode, all message transfers to and from the CAN bus are stopped and \nthe status of the CAN bus output CANTX is recessive (high). \nEntering Initialization Mode does not change any of the configuration registers.\nTo initialize the CAN Controller, software has to set up the Bit Timing (CAN_BTR) and CAN \noptions (CAN_MCR) registers. \nTo initialize the registers associated with the CAN filter banks (mode, scale, FIFO \nassignment, activation and filter values), software has to set the FINIT bit (CAN_FMR). Filter \ninitialization also can be done outside the initialization mode. \nNote:\nWhen FINIT=1, CAN reception is deactivated.\nThe filter values also can be modified by deactivating the associated filter activation bits (in \nthe CAN_FA1R register). \nIf a filter bank is not used, it is recommended to leave it non active (leave the corresponding \nFACT bit cleared).\n32.4.2 \nNormal mode\nOnce the initialization is complete, the software must request the hardware to enter Normal \nmode to be able to synchronize on the CAN bus and start reception and transmission.\nThe request to enter Normal mode is issued by clearing the INRQ bit in the CAN_MCR \nregister. The bxCAN enters Normal mode and is ready to take part in bus activities when it \nhas synchronized with the data transfer on the CAN bus. This is done by waiting for the \noccurrence of a sequence of 11 consecutive recessive bits (Bus Idle state). The switch to \nNormal mode is confirmed by the hardware by clearing the INAK bit in the CAN_MSR \nregister.\nThe initialization of the filter values is independent from Initialization Mode but must be done \nwhile the filter is not active (corresponding FACTx bit cleared). The filter scale and mode \nconfiguration must be configured before entering Normal Mode.\n32.4.3 \nSleep mode (low-power)\nTo reduce power consumption, bxCAN has a low-power mode called Sleep mode. This \nmode is entered on software request by setting the SLEEP bit in the CAN_MCR register. In \nthis mode, the bxCAN clock is stopped, however software can still access the bxCAN \nmailboxes. \nIf software requests entry to initialization mode by setting the INRQ bit while bxCAN is in \nSleep mode, it must also clear the SLEEP bit.\n" }, { "page_number": 1084, "page_indices": { "start_index": 2111271, "end_index": 2113414 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1084 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.5 Test mode", 1084 ], [ 3, "32.5.1 Silent mode", 1084 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1084/1757\nRM0090 Rev 21\nbxCAN can be woken up (exit Sleep mode) either by software clearing the SLEEP bit or on \ndetection of CAN bus activity.\nOn CAN bus activity detection, hardware automatically performs the wake-up sequence by \nclearing the SLEEP bit if the AWUM bit in the CAN_MCR register is set. If the AWUM bit is \ncleared, software has to clear the SLEEP bit when a wake-up interrupt occurs, in order to \nexit from Sleep mode.\nNote:\nIf the wake-up interrupt is enabled (WKUIE bit set in CAN_IER register) a wake-up interrupt \nis generated on detection of CAN bus activity, even if the bxCAN automatically performs the \nwake-up sequence.\nAfter the SLEEP bit has been cleared, Sleep mode is exited once bxCAN has synchronized \nwith the CAN bus, refer to Figure 336. The Sleep mode is exited once the SLAK bit has \nbeen cleared by hardware.\nFigure 336. bxCAN operating modes\n1.\nACK = The wait state during which hardware confirms a request by setting the INAK or SLAK bits in the \nCAN_MSR register\n2.\nSYNC = The state during which bxCAN waits until the CAN bus is idle, meaning 11 consecutive recessive \nbits have been monitored on CANRX\n32.5 \nTest mode\nTest mode can be selected by the SILM and LBKM bits in the CAN_BTR register. These bits \nmust be configured while bxCAN is in Initialization mode. Once test mode has been \nselected, the INRQ bit in the CAN_MCR register must be reset to enter Normal mode.\n32.5.1 \nSilent mode\nThe bxCAN can be put in Silent mode by setting the SILM bit in the CAN_BTR register.\nIn Silent mode, the bxCAN is able to receive valid data frames and valid remote frames, but \nit sends only recessive bits on the CAN bus and it cannot start a transmission. If the bxCAN \nhas to send a dominant bit (ACK bit, overload flag, active error flag), the bit is rerouted \ninternally so that the CAN Core monitors this dominant bit, although the CAN bus may \nSleep\nInitialization\nNormal\nReset\nSLAK= 1\nINAK = 0\nSLAK= 0\nINAK = 1\nSLAK= 0\nINAK = 0\nSLEEP . INRQ . ACK\nSLEEP . INRQ . ACK\nINRQ . ACK\nINRQ . SYNC . SLEEP\nSLEEP . ACK\nSLEEP . SYNC . INRQ \nai15902\n" }, { "page_number": 1085, "page_indices": { "start_index": 2113414, "end_index": 2114968 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1085 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.5 Test mode", 1084 ], [ 3, "32.5.2 Loop back mode", 1085 ], [ 3, "32.5.3 Loop back combined with silent mode", 1085 ] ], "page_content": "RM0090 Rev 21\n1085/1757\nRM0090\nController area network (bxCAN)\n1124\nremain in recessive state. Silent mode can be used to analyze the traffic on a CAN bus \nwithout affecting it by the transmission of dominant bits (Acknowledge Bits, Error Frames).\nFigure 337. bxCAN in silent mode\n32.5.2 \nLoop back mode\nThe bxCAN can be set in Loop Back Mode by setting the LBKM bit in the CAN_BTR \nregister. In Loop Back Mode, the bxCAN treats its own transmitted messages as received \nmessages and stores them (if they pass acceptance filtering) in a Receive mailbox. \nFigure 338. bxCAN in loop back mode\nThis mode is provided for self-test functions. To be independent of external events, the CAN \nCore ignores acknowledge errors (no dominant bit sampled in the acknowledge slot of a \ndata / remote frame) in Loop Back Mode. In this mode, the bxCAN performs an internal \nfeedback from its Tx output to its Rx input. The actual value of the CANRX input pin is \ndisregarded by the bxCAN. The transmitted messages can be monitored on the CANTX pin.\n32.5.3 \nLoop back combined with silent mode\nIt is also possible to combine Loop Back mode and Silent mode by setting the LBKM and \nSILM bits in the CAN_BTR register. This mode can be used for a “Hot Selftest”, meaning the \nbxCAN can be tested like in Loop Back mode but without affecting a running CAN system \nconnected to the CANTX and CANRX pins. In this mode, the CANRX pin is disconnected \nfrom the bxCAN and the CANTX pin is held recessive. \nbxCAN\nCANTX CANRX\nTx\nRx\n=1\nbxCAN\nCANTX CANRX\nTx\nRx\n" }, { "page_number": 1086, "page_indices": { "start_index": 2114968, "end_index": 2116680 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1086 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.6 Debug mode", 1086 ], [ 2, "32.7 bxCAN functional description", 1086 ], [ 3, "32.7.1 Transmission handling", 1086 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1086/1757\nRM0090 Rev 21\nFigure 339. bxCAN in combined mode\n32.6 \nDebug mode\nWhen the microcontroller enters the debug mode (Cortex®-M4 with FPU core halted), the \nbxCAN continues to work normally or stops, depending on:\n•\nthe DBG_CAN1_STOP bit for CAN1 or the DBG_CAN2_STOP bit for CAN2 in the \nDBG module. For more details, refer to Section 38.16.2: Debug support for timers, \nwatchdog, bxCAN and I2C.\n•\nthe DBF bit in CAN_MCR. For more details, refer to Section 32.9.2.\n32.7 \nbxCAN functional description\n32.7.1 \nTransmission handling\nIn order to transmit a message, the application must select one empty transmit mailbox, set \nup the identifier, the data length code (DLC) and the data before requesting the transmission \nby setting the corresponding TXRQ bit in the CAN_TIxR register. Once the mailbox has left \nempty state, the software no longer has write access to the mailbox registers. Immediately \nafter the TXRQ bit has been set, the mailbox enters pending state and waits to become the \nhighest priority mailbox, see Transmit Priority. As soon as the mailbox has the highest \npriority it is scheduled for transmission. The transmission of the message of the scheduled \nmailbox starts (enters transmit state) when the CAN bus becomes idle. Once the mailbox \nhas been successfully transmitted, it becomes empty again. The hardware indicates a \nsuccessful transmission by setting the RQCP and TXOK bits in the CAN_TSR register. \nIf the transmission fails, the cause is indicated by the ALST bit in the CAN_TSR register in \ncase of an Arbitration Lost, and/or the TERR bit, in case of transmission error detection.\nbxCAN\nCANTX CANRX\nTx\nRx\n=1\n" }, { "page_number": 1087, "page_indices": { "start_index": 2116680, "end_index": 2118696 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1087 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.7 bxCAN functional description", 1086 ], [ 3, "32.7.1 Transmission handling", 1086 ], [ 4, "Transmit priority", 1087 ], [ 4, "Abort", 1087 ], [ 4, "Nonautomatic retransmission mode", 1087 ] ], "page_content": "RM0090 Rev 21\n1087/1757\nRM0090\nController area network (bxCAN)\n1124\nTransmit priority\n \nAbort\nA transmission request can be aborted by the user setting the ABRQ bit in the CAN_TSR \nregister. In pending or scheduled state, the mailbox is aborted immediately. An abort \nrequest while the mailbox is in transmit state can have two results. If the mailbox is \ntransmitted successfully the mailbox becomes empty with the TXOK bit set in the \nCAN_TSR register. If the transmission fails, the mailbox becomes scheduled, the \ntransmission is aborted and becomes empty with TXOK cleared. In all cases the mailbox \nbecomes empty again at least at the end of the current transmission.\nNonautomatic retransmission mode\nThis mode has been implemented in order to fulfil the requirement of the Time Triggered \nCommunication option of the CAN standard. To configure the hardware in this mode the \nNART bit in the CAN_MCR register must be set.\nIn this mode, each transmission is started only once. If the first attempt fails, due to an \narbitration loss or an error, the hardware does not automatically restart the message \ntransmission.\nAt the end of the first transmission attempt, the hardware considers the request as \ncompleted and sets the RQCP bit in the CAN_TSR register. The result of the transmission is \nindicated in the CAN_TSR register by the TXOK, ALST and TERR bits.\nBy identifier\nWhen more than one transmit mailbox is pending, the \ntransmission order is given by the identifier of the message \nstored in the mailbox. The message with the lowest identifier \nvalue has the highest priority according to the arbitration of the \nCAN protocol. If the identifier values are equal, the lower mailbox \nnumber is scheduled first.\nBy transmit request order The transmit mailboxes can be configured as a transmit FIFO by \nsetting the TXFP bit in the CAN_MCR register. In this mode the \npriority order is given by the transmit request order. This mode is \nvery useful for segmented transmission.\n" }, { "page_number": 1088, "page_indices": { "start_index": 2118696, "end_index": 2120192 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1088 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.7 bxCAN functional description", 1086 ], [ 3, "32.7.2 Time triggered communication mode", 1088 ], [ 3, "32.7.3 Reception handling", 1088 ], [ 4, "Valid message", 1088 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1088/1757\nRM0090 Rev 21\nFigure 340. Transmit mailbox states\n32.7.2 \nTime triggered communication mode\nIn this mode, the internal counter of the CAN hardware is activated and used to generate the \nTime Stamp value stored in the CAN_RDTxR/CAN_TDTxR registers, respectively (for Rx \nand Tx mailboxes). The internal counter is incremented each CAN bit time (refer to \nSection 32.7.7). The internal counter is captured on the sample point of the Start Of Frame \nbit in both reception and transmission. \n32.7.3 \nReception handling\nFor the reception of CAN messages, three mailboxes organized as a FIFO are provided. In \norder to save CPU load, simplify the software and guarantee data consistency, the FIFO is \nmanaged completely by hardware. The application accesses the messages stored in the \nFIFO through the FIFO output mailbox.\nValid message\nA received message is considered as valid when it has been received correctly according to \nthe CAN protocol (no error until the last but one bit of the EOF field) and It passed through \nthe identifier filtering successfully, see Section 32.7.4.\nEMPTY\nTXRQ=1\nRQCP=X\nTXOK=X\nPENDING\nRQCP=0\nTXOK=0\nSCHEDULED\nRQCP=0\nTXOK=0\nMailbox has\nTRANSMIT\nRQCP=0\nTXOK=0\nCAN Bus = IDLE\nTransmit failed * NART\nTransmit succeeded\nMailbox does not\nEMPTY\nRQCP=1\nTXOK=0\nhighest priority\nhave highest priority\nEMPTY\nRQCP=1\nTXOK=1\nABRQ=1\nABRQ=1\nTransmit failed * NART\nTME = 1\nTME = 0\nTME = 0\nTME = 0\nTME = 1\nTME = 1\n" }, { "page_number": 1089, "page_indices": { "start_index": 2120192, "end_index": 2121897 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1089 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.7 bxCAN functional description", 1086 ], [ 3, "32.7.3 Reception handling", 1088 ], [ 4, "FIFO management", 1089 ], [ 4, "Overrun", 1089 ] ], "page_content": "RM0090 Rev 21\n1089/1757\nRM0090\nController area network (bxCAN)\n1124\nFigure 341. Receive FIFO states\nFIFO management\nStarting from the empty state, the first valid message received is stored in the FIFO which \nbecomes pending_1. The hardware signals the event setting the FMP[1:0] bits in the \nCAN_RFR register to the value 01b. The message is available in the FIFO output mailbox. \nThe software reads out the mailbox content and releases it by setting the RFOM bit in the \nCAN_RFR register. The FIFO becomes empty again. If a new valid message has been \nreceived in the meantime, the FIFO stays in pending_1 state and the new message is \navailable in the output mailbox. \nIf the application does not release the mailbox, the next valid message is stored in the FIFO \nwhich enters pending_2 state (FMP[1:0] = 10b). The storage process is repeated for the \nnext valid message putting the FIFO into pending_3 state (FMP[1:0] = 11b). At this point, \nthe software must release the output mailbox by setting the RFOM bit, so that a mailbox is \nfree to store the next valid message. Otherwise the next valid message received causes a \nloss of message.\nRefer also to Section 32.7.5\nOverrun\nOnce the FIFO is in pending_3 state (i.e. the three mailboxes are full) the next valid \nmessage reception leads to an overrun and a message is lost. The hardware signals the \nEMPTY\nValid Message\nFMP=0x00\nFOVR=0\nPENDING_1\nFMP=0x01\nFOVR=0\nReceived\nPENDING_2\nFMP=0x10\nFOVR=0\nPENDING_3\nFMP=0x11\nFOVR=0\nValid Message\nReceived\nRelease\nOVERRUN\nFMP=0x11\nFOVR=1\nMailbox\nRelease\nMailbox\nValid Message\nReceived\nValid Message\nReceived\nRelease\nMailbox\nRelease\nMailbox\nValid Message\nReceived\nRFOM=1 \nRFOM=1\nRFOM=1\n" }, { "page_number": 1090, "page_indices": { "start_index": 2121897, "end_index": 2124773 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1090 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.7 bxCAN functional description", 1086 ], [ 3, "32.7.3 Reception handling", 1088 ], [ 4, "Reception related interrupts", 1090 ], [ 3, "32.7.4 Identifier filtering", 1090 ], [ 4, "Scalable width", 1090 ], [ 4, "Mask mode", 1090 ], [ 4, "Identifier list mode", 1090 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1090/1757\nRM0090 Rev 21\noverrun condition by setting the FOVR bit in the CAN_RFR register. Which message is lost \ndepends on the configuration of the FIFO:\n•\nIf the FIFO lock function is disabled (RFLM bit in the CAN_MCR register cleared) the \nlast message stored in the FIFO is overwritten by the new incoming message. In this \ncase the latest messages are always available to the application.\n•\nIf the FIFO lock function is enabled (RFLM bit in the CAN_MCR register set) the most \nrecent message is discarded and the software has the three oldest messages in the \nFIFO available.\nReception related interrupts\nOnce a message has been stored in the FIFO, the FMP[1:0] bits are updated and an \ninterrupt request is generated if the FMPIE bit in the CAN_IER register is set.\nWhen the FIFO becomes full (i.e. a third message is stored) the FULL bit in the CAN_RFR \nregister is set and an interrupt is generated if the FFIE bit in the CAN_IER register is set.\nOn overrun condition, the FOVR bit is set and an interrupt is generated if the FOVIE bit in \nthe CAN_IER register is set.\n32.7.4 \nIdentifier filtering\nIn the CAN protocol the identifier of a message is not associated with the address of a node \nbut related to the content of the message. Consequently a transmitter broadcasts its \nmessage to all receivers. On message reception a receiver node decides - depending on \nthe identifier value - whether the software needs the message or not. If the message is \nneeded, it is copied into the SRAM. If not, the message must be discarded without \nintervention by the software.\nTo fulfill this requirement, the bxCAN Controller provides 28 configurable and scalable filter \nbanks (27-0) to the application. This hardware filtering saves CPU resources which would \nbe otherwise needed to perform filtering by software. Each filter bank x consists of two 32-bit \nregisters, CAN_FxR0 and CAN_FxR1. \nScalable width\nTo optimize and adapt the filters to the application needs, each filter bank can be scaled \nindependently. Depending on the filter scale a filter bank provides:\n•\nOne 32-bit filter for the STDID[10:0], EXTID[17:0], IDE and RTR bits.\n•\nTwo 16-bit filters for the STDID[10:0], RTR, IDE and EXTID[17:15] bits.\nRefer to Figure 342.\nFurthermore, the filters can be configured in mask mode or in identifier list mode. \nMask mode \nIn mask mode the identifier registers are associated with mask registers specifying which \nbits of the identifier are handled as “must match” or as “don’t care”. \nIdentifier list mode\nIn identifier list mode, the mask registers are used as identifier registers. Thus instead of \ndefining an identifier and a mask, two identifiers are specified, doubling the number of single \nidentifiers. All bits of the incoming identifier must match the bits specified in the filter \nregisters.\n" }, { "page_number": 1091, "page_indices": { "start_index": 2124773, "end_index": 2127307 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1091 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.7 bxCAN functional description", 1086 ], [ 3, "32.7.4 Identifier filtering", 1090 ], [ 4, "Filter bank scale and mode configuration", 1091 ], [ 4, "Filter match index", 1091 ] ], "page_content": "RM0090 Rev 21\n1091/1757\nRM0090\nController area network (bxCAN)\n1124\nFilter bank scale and mode configuration\nThe filter banks are configured by means of the corresponding CAN_FMR register. To \nconfigure a filter bank it must be deactivated by clearing the FACT bit in the CAN_FAR \nregister. The filter scale is configured by means of the corresponding FSCx bit in the \nCAN_FS1R register, refer to Figure 342. The identifier list or identifier mask mode for the \ncorresponding Mask/Identifier registers is configured by means of the FBMx bits in the \nCAN_FMR register.\nTo filter a group of identifiers, configure the Mask/Identifier registers in mask mode. \nTo select single identifiers, configure the Mask/Identifier registers in identifier list mode.\nFilters not used by the application should be left deactivated.\nEach filter within a filter bank is numbered (called the Filter Number) from 0 to a maximum \ndependent on the mode and the scale of each of the filter banks.\nConcerning the filter configuration, refer to Figure 342.\nFigure 342. Filter bank scale configuration - register organization\nFilter match index\nOnce a message has been received in the FIFO it is available to the application. Typically, \napplication data is copied into SRAM locations. To copy the data to the right location the \nOne 32-Bit Filter - Identifier Mask\nTwo 16-Bit Filters - Identifier Mask\nCAN_FxR1[31:24]\nCAN_FxR2[31:24]\nCAN_FxR1[15:8]\nCAN_FxR1[31:24]\nCAN_FxR1[7:0]\nCAN_FxR1[23:16]\nx = filter bank number\nFSCx = 1\nFSCx = 0\n1 These bits are located in the CAN_FS1R register\nFilter Bank Scale \nID\nMask\nID\nMask\nSTID[10:3]\nSTID[2:0] \nEXID[12:5]\nMapping\nSTID[10:3]\n \nID\nMask\nMapping\nRTR\nTwo 32-Bit Filters - Identifier List\nID\nID\nSTID[10:3]\nSTID[2:0]\nEXID[12:5]\nMapping\nFour 16-Bit Filters - Identifier List\nID\nID\nSTID[10:3]\nID\nID\nMapping\nn\nn+1\nn+2\nn+3\nn+1\nFilter Bank Mode2\nn\nn\nn+1\nEXID[4:0]\nIDE\nEXID[17:13]\nEXID[17:13]\nSTID[2:0] RTR IDE EXID[17:15]\nFBMx = 0\nFBMx = 1\nFilter \n2 These bits are located in the CAN_FM1R register\nn\nNum.\nFBMx = 0\nFBMx = 1\nConfig. Bits1\n STID[2:0] RTR IDE EXID[17:15]\n0\nRTR\nEXID[4:0]\nIDE\n0\nCAN_FxR1[23:16]\nCAN_FxR1[15:8]\nCAN_FxR1[7:0]\nCAN_FxR2[7:0]\nCAN_FxR2[15:8]\nCAN_FxR2[23:16]\nCAN_FxR1[31:24]\nCAN_FxR2[31:24]\nCAN_FxR1[23:16]\nCAN_FxR1[15:8]\nCAN_FxR1[7:0]\nCAN_FxR2[7:0]\nCAN_FxR2[15:8]\nCAN_FxR2[23:16]\nCAN_FxR2[15:8]\nCAN_FxR2[31:24]\nCAN_FxR2[7:0]\nCAN_FxR2[23:16]\nCAN_FxR1[15:8]\nCAN_FxR1[31:24]\nCAN_FxR1[7:0]\nCAN_FxR1[23:16]\nCAN_FxR2[15:8]\nCAN_FxR2[31:24]\nCAN_FxR2[7:0]\nCAN_FxR2[23:16]\nID=Identifier\n" }, { "page_number": 1092, "page_indices": { "start_index": 2127307, "end_index": 2128823 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1092 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.7 bxCAN functional description", 1086 ], [ 3, "32.7.4 Identifier filtering", 1090 ], [ 4, "Filter match index", 1091 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1092/1757\nRM0090 Rev 21\napplication has to identify the data by means of the identifier. To avoid this, and to ease the \naccess to the SRAM locations, the CAN controller provides a Filter Match Index.\nThis index is stored in the mailbox together with the message according to the filter priority \nrules. Thus each received message has its associated filter match index.\nThe Filter Match index can be used in two ways:\n•\nCompare the Filter Match index with a list of expected values.\n•\nUse the Filter Match Index as an index on an array to access the data destination \nlocation.\nFor nonmasked filters, the software no longer has to compare the identifier. \nIf the filter is masked the software reduces the comparison to the masked bits only.\nThe index value of the filter number does not take into account the activation state of the \nfilter banks. In addition, two independent numbering schemes are used, one for each FIFO. \nRefer to Figure 343 for an example.\nFigure 343. Example of filter numbering\n9\n8\nID List (32-bit)\nID Mask (32-bit)\nID List (16-bit)\nID List (32-bit)\nDeactivated\nID Mask (16-bit)\nID List (32-bit)\nFilter \n0\n1\n3\n5\n6\n9\nID Mask (32-bit)\n13\nFIFO0\nFilter \n0\n1\n2\n3\n4\n5\n6\n7\n10\n11\n12\n13\nID Mask (16-bit)\nID List (32-bit)\nID Mask (16-bit)\nID List (16-bit)\nDeactivated\nID Mask (16-bit)\nID List (32-bit)\nFilter \n2\n4\n7\n8\n10\n11\nID Mask (32-bit)\n12\nFIFO1\nFilter \n0\n1\n2\n4\n5\n6\n7\n8\n11\n12\n13\n14\n3\nDeactivated\n9\n10\nNum.\nNum.\nBank\nBank\nID = Identifier\n" }, { "page_number": 1093, "page_indices": { "start_index": 2128823, "end_index": 2130670 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1093 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.7 bxCAN functional description", 1086 ], [ 3, "32.7.4 Identifier filtering", 1090 ], [ 4, "Filter priority rules", 1093 ] ], "page_content": "RM0090 Rev 21\n1093/1757\nRM0090\nController area network (bxCAN)\n1124\nFilter priority rules\nDepending on the filter combination it may occur that an identifier passes successfully \nthrough several filters. In this case the filter match value stored in the receive mailbox is \nchosen according to the following priority rules:\n•\nA 32-bit filter takes priority over a 16-bit filter.\n•\nFor filters of equal scale, priority is given to the Identifier List mode over the Identifier \nMask mode\n•\nFor filters of equal scale and mode, priority is given by the filter number (the lower the \nnumber, the higher the priority).\nFigure 344. Filtering mechanism - Example\nThe example above shows the filtering principle of the bxCAN. On reception of a message, \nthe identifier is compared first with the filters configured in identifier list mode. If there is a \nmatch, the message is stored in the associated FIFO and the index of the matching filter is \nstored in the Filter Match Index. As shown in the example, the identifier matches with \nIdentifier #2 thus the message content and FMI 2 is stored in the FIFO. \nIf there is no match, the incoming identifier is then compared with the filters configured in \nmask mode. \nIf the identifier does not match any of the identifiers configured in the filters, the message is \ndiscarded by hardware without disturbing the software.\nIdentifier List\nMessage Discarded\nIdentifier & Mask\nIdentifier \n0\nIdentifier \n1\nIdentifier \n4\nIdentifier \n5\nIdentifier \n2\nMask\nIdentifier \n3\nMask\nIdentifier\nMessage Received\nCtrl\nData\nIdentifier #4 Match\nMessage\nStored\nReceive FIFO\nNo Match\nFound\nFilter number stored in the \nFilter Match Index field \nwithin the CAN_RDTxR \nregister\nFMI\nFilter bank \n0\n2\n3\n1\n4\nNum\nThree filter banks in 32-bit Unidentified List mode,\nthe remaining in 32-bit Identifier Mask mode\n" }, { "page_number": 1094, "page_indices": { "start_index": 2130670, "end_index": 2131973 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1094 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.7 bxCAN functional description", 1086 ], [ 3, "32.7.5 Message storage", 1094 ], [ 4, "Transmit mailbox", 1094 ], [ 4, "Receive mailbox", 1094 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1094/1757\nRM0090 Rev 21\n32.7.5 \nMessage storage\nThe interface between the software and the hardware for the CAN messages is \nimplemented by means of mailboxes. A mailbox contains all information related to a \nmessage; identifier, data, control, status and time stamp information.\nTransmit mailbox\nThe software sets up the message to be transmitted in an empty transmit mailbox. The \nstatus of the transmission is indicated by hardware in the CAN_TSR register.\n \nReceive mailbox\nWhen a message has been received, it is available to the software in the FIFO output \nmailbox. Once the software has handled the message (e.g. read it) the software must \nrelease the FIFO output mailbox by means of the RFOM bit in the CAN_RFR register to \nmake the next incoming message available. The filter match index is stored in the MFMI \nfield of the CAN_RDTxR register. The 16-bit time stamp value is stored in the TIME[15:0] \nfield of CAN_RDTxR.\n \nTable 183. Transmit mailbox mapping\nOffset to transmit mailbox base address (bytes)\nRegister name\n0\nCAN_TIxR\n4\nCAN_TDTxR \n8\nCAN_TDLxR\n12\nCAN_TDHxR\nTable 184. Receive mailbox mapping\nOffset to receive mailbox base address (bytes)\nRegister name\n0\nCAN_RIxR\n4\nCAN_RDTxR\n8\nCAN_RDLxR\n12\nCAN_RDHxR\n" }, { "page_number": 1095, "page_indices": { "start_index": 2131973, "end_index": 2132241 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1095 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.7 bxCAN functional description", 1086 ], [ 3, "32.7.5 Message storage", 1094 ], [ 4, "Receive mailbox", 1094 ] ], "page_content": "RM0090 Rev 21\n1095/1757\nRM0090\nController area network (bxCAN)\n1124\nFigure 345. CAN error state diagram\nERROR PASSIVE\nWhen TEC or REC > 127\nWhen TEC and REC < 128,\nERROR ACTIVE\nBUS OFF\n When TEC > 255\nWhen 128 * 11 recessive bits occur:\nai15903\n" }, { "page_number": 1096, "page_indices": { "start_index": 2132241, "end_index": 2135255 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1096 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.7 bxCAN functional description", 1086 ], [ 3, "32.7.6 Error management", 1096 ], [ 4, "Bus-Off recovery", 1096 ], [ 3, "32.7.7 Bit timing", 1096 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1096/1757\nRM0090 Rev 21\n32.7.6 \nError management\nThe error management as described in the CAN protocol is handled entirely by hardware \nusing a Transmit Error Counter (TEC value, in CAN_ESR register) and a Receive Error \nCounter (REC value, in the CAN_ESR register), which get incremented or decremented \naccording to the error condition. For detailed information about TEC and REC management, \nrefer to the CAN standard. \nBoth of them may be read by software to determine the stability of the network. \nFurthermore, the CAN hardware provides detailed information on the current error status in \nCAN_ESR register. By means of the CAN_IER register (ERRIE bit, etc.), the software can \nconfigure the interrupt generation on error detection in a very flexible way.\nBus-Off recovery\nThe Bus-Off state is reached when TEC is greater than 255, this state is indicated by BOFF \nbit in CAN_ESR register. In Bus-Off state, the bxCAN is no longer able to transmit and \nreceive messages. \nDepending on the ABOM bit in the CAN_MCR register bxCAN recovers from Bus-Off \n(become error active again) either automatically or on software request. But in both cases \nthe bxCAN has to wait at least for the recovery sequence specified in the CAN standard \n(128 occurrences of 11 consecutive recessive bits monitored on CANRX).\nIf ABOM is set, the bxCAN starts the recovering sequence automatically after it has entered \nBus-Off state.\nIf ABOM is cleared, the software must initiate the recovering sequence by requesting \nbxCAN to enter and to leave initialization mode.\nNote:\nIn initialization mode, bxCAN does not monitor the CANRX signal, therefore it cannot \ncomplete the recovery sequence. To recover, bxCAN must be in normal mode.\n32.7.7 \nBit timing\nThe bit timing logic monitors the serial bus-line and performs sampling and adjustment of \nthe sample point by synchronizing on the start-bit edge and resynchronizing on the following \nedges. \nIts operation may be explained simply by splitting nominal bit time into three segments as \nfollows:\n•\nSynchronization segment (SYNC_SEG): a bit change is expected to occur within this \ntime segment. It has a fixed length of one time quantum (1 x tq).\n•\nBit segment 1 (BS1): defines the location of the sample point. It includes the \nPROP_SEG and PHASE_SEG1 of the CAN standard. Its duration is programmable \nbetween 1 and 16 time quanta but may be automatically lengthened to compensate for \npositive phase drifts due to differences in the frequency of the various nodes of the \nnetwork.\n•\nBit segment 2 (BS2): defines the location of the transmit point. It represents the \nPHASE_SEG2 of the CAN standard. Its duration is programmable between 1 and 8 \ntime quanta but may also be automatically shortened to compensate for negative \nphase drifts.\nThe resynchronization Jump Width (SJW) defines an upper bound to the amount of \nlengthening or shortening of the bit segments. It is programmable between 1 and 4 time \nquanta.\n" }, { "page_number": 1097, "page_indices": { "start_index": 2135255, "end_index": 2136530 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1097 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.7 bxCAN functional description", 1086 ], [ 3, "32.7.7 Bit timing", 1096 ] ], "page_content": "RM0090 Rev 21\n1097/1757\nRM0090\nController area network (bxCAN)\n1124\nA valid edge is defined as the first transition in a bit time from dominant to recessive bus \nlevel provided the controller itself does not send a recessive bit.\nIf a valid edge is detected in BS1 instead of SYNC_SEG, BS1 is extended by up to SJW so \nthat the sample point is delayed.\nConversely, if a valid edge is detected in BS2 instead of SYNC_SEG, BS2 is shortened by \nup to SJW so that the transmit point is moved earlier.\nAs a safeguard against programming errors, the configuration of the Bit Timing register \n(CAN_BTR) is only possible while the device is in Standby mode.\nNote:\nFor a detailed description of the CAN bit timing and resynchronization mechanism, refer to \nthe ISO 11898 standard.\nFigure 346. Bit timing\nSYNC_SEG\nBIT SEGMENT 1 (BS1)\nBIT SEGMENT 2 (BS2)\nNOMINAL BIT TIME\n1 x tq\ntBS1\ntBS2\nSAMPLE POINT\nTRANSMIT POINT\nNominalBitTime\n1\ntq\n×\ntBS1\ntBS2\n+\n+\n=\nwith:\ntBS1 = tq x (TS1[3:0] + 1),\ntBS2 = tq x (TS2[2:0] + 1),\ntq = (BRP[9:0] + 1) x tPCLK\ntPCLK = time period of the APB clock,\nBRP[9:0], TS1[3:0] and TS2[2:0] are defined in the CAN_BTR register.\nBaudRate\n1\nNominalBitTime\n----------------------------------------------\n=\nwhere tq refers to the Time quantum\n" }, { "page_number": 1098, "page_indices": { "start_index": 2136530, "end_index": 2138231 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1098 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.8 bxCAN interrupts", 1098 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1098/1757\nRM0090 Rev 21\nFigure 347. CAN frames\n32.8 \nbxCAN interrupts\nFour interrupt vectors are dedicated to bxCAN. Each interrupt source can be independently \nenabled or disabled by means of the CAN Interrupt Enable register (CAN_IER).\nData Frame or\nRemote Frame\nData Field\n8 * N\nCtrl Field\n6\nArbitration Field\n32\nCRC Field\n16\nAck Field\n7\nSOF\nID\nDLC\nCRC\nData Frame (Standard identifier)\n44 + 8 * N\nArbitration Field\n32\nRTR\nIDE\nr0\nSOF\nID\nDLC\nRemote Frame\n44\nCRC Field\n16\n7\nCRC\nCtrl Field\n6\nOverload \nOverload Frame\n Error \n6\nError Delimiter\n8\nError Frame\nFlag Echo\n 6\nBus Idle\nInter-Frame Space\nSuspend\n8\nIntermission\n3\nTransmission\nACK\nACK\n2\n2\nInter-Frame Space\nor Overload Frame\nInter-Frame Space\nInter-Frame Space\nor Overload Frame\nInter-Frame Space\nInter-Frame Space\nor Overload Frame\nNotes:\n 0 <= N <= 8\n SOF = Start Of Frame\n ID = Identifier\n RTR = Remote Transmission Request\n IDE = Identifier Extension Bit\n r0 = Reserved Bit\n DLC = Data Length Code\n CRC = Cyclic Redundancy Code\n Error flag: 6 dominant bits if node is error \nactive else 6 recessive bits.\n Suspend transmission: applies to error \npassive nodes only.\n EOF = End of Frame\n ACK = Acknowledge bit\n Ctrl = Control\nData Frame or\nRemote Frame\nAny Frame\nInter-Frame Space\nor Error Frame\nEnd Of Frame or\nError Delimiter or\nOverload Delimiter\nAck Field\nEOF\nRTR\nIDE\nr0\nEOF\nData Field\n8 * N\nCtrl Field\n6\n32\nCRC Field\n16\nAck Field\n7\nSOF\nID\nDLC\nCRC\nData Frame (Extended Identifier)\n64 + 8 * N\nACK\n2\nInter-Frame Space\nor Overload Frame\nInter-Frame Space\nSRR\nIDE\nEOF\nRTR\nr1\nr0\n32\n6\nOverload \n8\n 6\nOverload \nFlag\nEcho\nDelimiter\nFlag\nai15154\nArbitration Field\nArbitration Field\n" }, { "page_number": 1099, "page_indices": { "start_index": 2138231, "end_index": 2139763 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1099 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.8 bxCAN interrupts", 1098 ] ], "page_content": "RM0090 Rev 21\n1099/1757\nRM0090\nController area network (bxCAN)\n1124\nFigure 348. Event flags and interrupt generation\n•\nThe transmit interrupt can be generated by the following events:\n–\nTransmit mailbox 0 becomes empty, RQCP0 bit in the CAN_TSR register set.\n–\nTransmit mailbox 1 becomes empty, RQCP1 bit in the CAN_TSR register set.\n–\nTransmit mailbox 2 becomes empty, RQCP2 bit in the CAN_TSR register set.\n•\nThe FIFO 0 interrupt can be generated by the following events:\n–\nReception of a new message, FMP0 bits in the CAN_RF0R register are not ‘00’.\n–\nFIFO0 full condition, FULL0 bit in the CAN_RF0R register set.\n–\nFIFO0 overrun condition, FOVR0 bit in the CAN_RF0R register set.\n•\nThe FIFO 1 interrupt can be generated by the following events:\n–\nReception of a new message, FMP1 bits in the CAN_RF1R register are not ‘00’.\n–\nFIFO1 full condition, FULL1 bit in the CAN_RF1R register set.\n–\nFIFO1 overrun condition, FOVR1 bit in the CAN_RF1R register set.\n•\nThe error and status change interrupt can be generated by the following events:\n–\nError condition, for more details on error conditions refer to the CAN Error Status \nregister (CAN_ESR).\nRQCP0 \nRQCP1 \nFMP1\nCAN_TSR\n+\nTMEIE\nCAN_IER\nTRANSMIT\n&\nFMPIE1\nFULL1\n&\nFFIE1\nFOVR1\n&\nFOVIE1\n&\n+\nCAN_RF1R\nFIFO 1\nEWGF\nEWGIE\nEPVF\nEPVIE\nBOFF\nBOFIE\n1≤LEC≤6\nLECIE\n&\n&\n&\n&\nCAN_ESR\n+\n&\nERRIE\nINTERRUPT\nINTERRUPT\nFMP0\n&\nFMPIE0\nFULL0\n&\nFFIE0\nFOVR0\n&\nFOVIE0\n+\nCAN_RF0R\nFIFO 0\nINTERRUPT\nRQCP2 \nWKUI\n&\nWKUIE\nCAN_MSR\n+\nINTERRUPT\nERROR\nSTATUS CHANGE\nERRI\nSLAKI\nSLKIE\n&\nCAN_MSR\n" }, { "page_number": 1100, "page_indices": { "start_index": 2139763, "end_index": 2141797 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1100 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.1 Register access protection", 1100 ], [ 3, "32.9.2 CAN control and status registers", 1100 ], [ 4, "CAN master control register (CAN_MCR)", 1100 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1100/1757\nRM0090 Rev 21\n–\nWake-up condition, SOF monitored on the CAN Rx signal.\n–\nEntry into Sleep mode.\n32.9 \nCAN registers\nThe peripheral registers have to be accessed by words (32 bits).\n32.9.1 \nRegister access protection\nErroneous access to certain configuration registers can cause the hardware to temporarily \ndisturb the whole CAN network. Therefore the CAN_BTR register can be modified by \nsoftware only while the CAN hardware is in initialization mode.\nAlthough the transmission of incorrect data does not cause problems at the CAN network \nlevel, it can severely disturb the application. A transmit mailbox can be only modified by \nsoftware while it is in empty state, refer to Figure 340.\nThe filter values can be modified either deactivating the associated filter banks or by setting \nthe FINIT bit. Moreover, the modification of the filter configuration (scale, mode and FIFO \nassignment) in CAN_FMxR, CAN_FSxR and CAN_FFAR registers can only be done when \nthe filter initialization mode is set (FINIT=1) in the CAN_FMR register.\n32.9.2 \nCAN control and status registers\nRefer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.\nCAN master control register (CAN_MCR)\nAddress offset: 0x00\nReset value: 0x0001 0002\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nDBF\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRESET\nReserved\nTTCM\nABOM\nAWUM\nNART\nRFLM\nTXFP\nSLEEP\nINRQ\nrs\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:17 Reserved, must be kept at reset value.\nBit 16 DBF: Debug freeze\n0: CAN working during debug\n1: CAN reception/transmission frozen during debug. Reception FIFOs can still be \naccessed/controlled normally.\nBit 15 RESET: bxCAN software master reset\n0: Normal operation.\n1: Force a master reset of the bxCAN -> Sleep mode activated after reset (FMP bits and \nCAN_MCR register are initialized to the reset values). This bit is automatically reset to 0.\nBits 14:8 Reserved, must be kept at reset value.\n" }, { "page_number": 1101, "page_indices": { "start_index": 2141797, "end_index": 2144287 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1101 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.2 CAN control and status registers", 1100 ], [ 4, "CAN master control register (CAN_MCR)", 1100 ] ], "page_content": "RM0090 Rev 21\n1101/1757\nRM0090\nController area network (bxCAN)\n1124\nBit 7 TTCM: Time triggered communication mode\n0: Time Triggered Communication mode disabled.\n1: Time Triggered Communication mode enabled\nNote: For more information on Time Triggered Communication mode refer to Section 32.7.2.\nBit 6 ABOM: Automatic bus-off management\nThis bit controls the behavior of the CAN hardware on leaving the Bus-Off state. \n0: The Bus-Off state is left on software request, once 128 occurrences of 11 recessive bits \nhave been monitored and the software has first set and cleared the INRQ bit of the \nCAN_MCR register. \n1: The Bus-Off state is left automatically by hardware once 128 occurrences of 11 recessive \nbits have been monitored.\nFor detailed information on the Bus-Off state refer to Section 32.7.6.\nBit 5 AWUM: Automatic wake-up mode\nThis bit controls the behavior of the CAN hardware on message reception during Sleep \nmode. \n0: The Sleep mode is left on software request by clearing the SLEEP bit of the CAN_MCR \nregister.\n1: The Sleep mode is left automatically by hardware on CAN message detection.\nThe SLEEP bit of the CAN_MCR register and the SLAK bit of the CAN_MSR register are \ncleared by hardware.\nBit 4 NART: No automatic retransmission\n0: The CAN hardware automatically retransmits the message until it has been successfully \ntransmitted according to the CAN standard.\n1: A message is transmitted only once, independently of the transmission result (successful, \nerror or arbitration lost).\nBit 3 RFLM: Receive FIFO locked mode\n0: Receive FIFO not locked on overrun. Once a receive FIFO is full the next incoming \nmessage overwrites the previous one.\n1: Receive FIFO locked against overrun. Once a receive FIFO is full the next incoming \nmessage is discarded.\nBit 2 TXFP: Transmit FIFO priority\nThis bit controls the transmission order when several mailboxes are pending at the same \ntime.\n0: Priority driven by the identifier of the message\n1: Priority driven by the request order (chronologically)\nBit 1 SLEEP: Sleep mode request\nThis bit is set by software to request the CAN hardware to enter the Sleep mode. Sleep \nmode is entered as soon as the current CAN activity (transmission or reception of a CAN \nframe) has been completed.\nThis bit is cleared by software to exit Sleep mode.\nThis bit is cleared by hardware when the AWUM bit is set and a SOF bit is detected on the \nCAN Rx signal.\nThis bit is set after reset - CAN starts in Sleep mode.\n" }, { "page_number": 1102, "page_indices": { "start_index": 2144287, "end_index": 2146415 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1102 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.2 CAN control and status registers", 1100 ], [ 4, "CAN master status register (CAN_MSR)", 1102 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1102/1757\nRM0090 Rev 21\nCAN master status register (CAN_MSR)\nAddress offset: 0x04\nReset value: 0x0000 0C02\n \n \nBit 0 INRQ: Initialization request\nThe software clears this bit to switch the hardware into normal mode. Once 11 consecutive \nrecessive bits have been monitored on the Rx signal the CAN hardware is synchronized and \nready for transmission and reception. Hardware signals this event by clearing the INAK bit in \nthe CAN_MSR register.\nSoftware sets this bit to request the CAN hardware to enter initialization mode. Once \nsoftware has set the INRQ bit, the CAN hardware waits until the current CAN activity \n(transmission or reception) is completed before entering the initialization mode. Hardware \nsignals this event by setting the INAK bit in the CAN_MSR register.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved.\nRX\nSAMP\nRXM\nTXM\nReserved\nSLAKI\nWKUI\nERRI\nSLAK\nINAK\nr\nr\nr\nr\nrc_w1\nrc_w1\nrc_w1\nr\nr\nBits 31:12 Reserved, must be kept at reset value.\nBit 11 RX: CAN Rx signal\nMonitors the actual value of the CAN_RX Pin.\nBit 10 SAMP: Last sample point \nThe value of RX on the last sample point (current received bit value).\nBit 9 RXM: Receive mode\nThe CAN hardware is currently receiver. \nBit 8 TXM: Transmit mode\nThe CAN hardware is currently transmitter.\nBits 7:5 Reserved, must be kept at reset value.\nBit 4 SLAKI: Sleep acknowledge interrupt\nWhen SLKIE=1, this bit is set by hardware to signal that the bxCAN has entered Sleep \nMode. When set, this bit generates a status change interrupt if the SLKIE bit in the \nCAN_IER register is set.\nThis bit is cleared by software or by hardware, when SLAK is cleared.\nNote: When SLKIE=0, no polling on SLAKI is possible. In this case the SLAK bit can be \npolled.\nBit 3 WKUI: Wake-up interrupt\nThis bit is set by hardware to signal that a SOF bit has been detected while the CAN \nhardware was in Sleep mode. Setting this bit generates a status change interrupt if the \nWKUIE bit in the CAN_IER register is set.\nThis bit is cleared by software.\n" }, { "page_number": 1103, "page_indices": { "start_index": 2146415, "end_index": 2149263 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1103 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.2 CAN control and status registers", 1100 ], [ 4, "CAN transmit status register (CAN_TSR)", 1103 ] ], "page_content": "RM0090 Rev 21\n1103/1757\nRM0090\nController area network (bxCAN)\n1124\nCAN transmit status register (CAN_TSR)\nAddress offset: 0x08\nReset value: 0x1C00 0000\n \n \nBit 2 ERRI: Error interrupt\nThis bit is set by hardware when a bit of the CAN_ESR has been set on error detection and \nthe corresponding interrupt in the CAN_IER is enabled. Setting this bit generates a status \nchange interrupt if the ERRIE bit in the CAN_IER register is set.\nThis bit is cleared by software.\nBit 1 SLAK: Sleep acknowledge\nThis bit is set by hardware and indicates to the software that the CAN hardware is now in \nSleep mode. This bit acknowledges the Sleep mode request from the software (set SLEEP \nbit in CAN_MCR register).\nThis bit is cleared by hardware when the CAN hardware has left Sleep mode (to be \nsynchronized on the CAN bus). To be synchronized the hardware has to monitor a \nsequence of 11 consecutive recessive bits on the CAN RX signal.\nNote: The process of leaving Sleep mode is triggered when the SLEEP bit in the CAN_MCR \nregister is cleared. Refer to the AWUM bit of the CAN_MCR register description for \ndetailed information for clearing SLEEP bit\nBit 0 INAK: Initialization acknowledge\nThis bit is set by hardware and indicates to the software that the CAN hardware is now in \ninitialization mode. This bit acknowledges the initialization request from the software (set \nINRQ bit in CAN_MCR register).\nThis bit is cleared by hardware when the CAN hardware has left the initialization mode (to \nbe synchronized on the CAN bus). To be synchronized the hardware has to monitor a \nsequence of 11 consecutive recessive bits on the CAN RX signal.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nLOW2\nLOW1\nLOW0\nTME2\nTME1\nTME0\nCODE[1:0]\nABRQ2\nReserved\nTERR2\nALST2\nTXOK2 RQCP2\nr\nr\nr\nr\nr\nr\nr\nr\nrs\nrc_w1\nrc_w1\nrc_w1\nrc_w1\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nABRQ1\nReserved\nRes.\nTERR1\nALST1\nTXOK1 RQCP1 ABRQ0\nReserved\nTERR0\nALST0\nTXOK0 RQCP0\nrs\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrs\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nBit 31 LOW2: Lowest priority flag for mailbox 2\nThis bit is set by hardware when more than one mailbox are pending for transmission and \nmailbox 2 has the lowest priority.\nBit 30 LOW1: Lowest priority flag for mailbox 1 \nThis bit is set by hardware when more than one mailbox are pending for transmission and \nmailbox 1 has the lowest priority.\nBit 29 LOW0: Lowest priority flag for mailbox 0\nThis bit is set by hardware when more than one mailbox are pending for transmission and \nmailbox 0 has the lowest priority.\nNote: The LOW[2:0] bits are set to zero when only one mailbox is pending.\nBit 28 TME2: Transmit mailbox 2 empty \nThis bit is set by hardware when no transmit request is pending for mailbox 2.\nBit 27 TME1: Transmit mailbox 1 empty \nThis bit is set by hardware when no transmit request is pending for mailbox 1.\n" }, { "page_number": 1104, "page_indices": { "start_index": 2149263, "end_index": 2152065 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1104 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.2 CAN control and status registers", 1100 ], [ 4, "CAN transmit status register (CAN_TSR)", 1103 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1104/1757\nRM0090 Rev 21\nBit 26 TME0: Transmit mailbox 0 empty\nThis bit is set by hardware when no transmit request is pending for mailbox 0.\nBits 25:24 CODE[1:0]: Mailbox code\nIn case at least one transmit mailbox is free, the code value is equal to the number of the \nnext transmit mailbox free.\nIn case all transmit mailboxes are pending, the code value is equal to the number of the \ntransmit mailbox with the lowest priority.\nBit 23 ABRQ2: Abort request for mailbox 2\nSet by software to abort the transmission request for the corresponding mailbox. \nCleared by hardware when the mailbox becomes empty.\nSetting this bit has no effect when the mailbox is not pending for transmission.\nBits 22:20 Reserved, must be kept at reset value.\nBit 19 TERR2: Transmission error of mailbox 2\nThis bit is set when the previous TX failed due to an error. \nBit 18 ALST2: Arbitration lost for mailbox 2\nThis bit is set when the previous TX failed due to an arbitration lost. \nBit 17 TXOK2: Transmission OK of mailbox 2\nThe hardware updates this bit after each transmission attempt.\n0: The previous transmission failed\n1: The previous transmission was successful\nThis bit is set by hardware when the transmission request on mailbox 2 has been completed \nsuccessfully. Refer to Figure 340.\nBit 16 RQCP2: Request completed mailbox2\nSet by hardware when the last request (transmit or abort) has been performed.\nCleared by software writing a “1” or by hardware on transmission request (TXRQ2 set in \nCAN_TMID2R register).\nClearing this bit clears all the status bits (TXOK2, ALST2 and TERR2) for Mailbox 2.\nBit 15 ABRQ1: Abort request for mailbox 1\nSet by software to abort the transmission request for the corresponding mailbox. \nCleared by hardware when the mailbox becomes empty.\nSetting this bit has no effect when the mailbox is not pending for transmission.\nBits 14:12 Reserved, must be kept at reset value.\nBit 11 TERR1: Transmission error of mailbox1\nThis bit is set when the previous TX failed due to an error. \nBit 10 ALST1: Arbitration lost for mailbox1\nThis bit is set when the previous TX failed due to an arbitration lost. \nBit 9 TXOK1: Transmission OK of mailbox1\nThe hardware updates this bit after each transmission attempt.\n0: The previous transmission failed\n1: The previous transmission was successful\nThis bit is set by hardware when the transmission request on mailbox 1 has been completed \nsuccessfully. Refer to Figure 340\nBit 8 RQCP1: Request completed mailbox1\nSet by hardware when the last request (transmit or abort) has been performed.\nCleared by software writing a “1” or by hardware on transmission request (TXRQ1 set in \nCAN_TI1R register).\nClearing this bit clears all the status bits (TXOK1, ALST1 and TERR1) for Mailbox 1.\n" }, { "page_number": 1105, "page_indices": { "start_index": 2152065, "end_index": 2154389 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1105 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.2 CAN control and status registers", 1100 ], [ 4, "CAN receive FIFO 0 register (CAN_RF0R)", 1105 ] ], "page_content": "RM0090 Rev 21\n1105/1757\nRM0090\nController area network (bxCAN)\n1124\nCAN receive FIFO 0 register (CAN_RF0R)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n \n \nBit 7 ABRQ0: Abort request for mailbox0\nSet by software to abort the transmission request for the corresponding mailbox. \nCleared by hardware when the mailbox becomes empty.\nSetting this bit has no effect when the mailbox is not pending for transmission.\nBits 6:4 Reserved, must be kept at reset value.\nBit 3 TERR0: Transmission error of mailbox0\nThis bit is set when the previous TX failed due to an error. \nBit 2 ALST0: Arbitration lost for mailbox0\nThis bit is set when the previous TX failed due to an arbitration lost.\nBit 1 TXOK0: Transmission OK of mailbox0\nThe hardware updates this bit after each transmission attempt.\n0: The previous transmission failed\n1: The previous transmission was successful\nThis bit is set by hardware when the transmission request on mailbox 1 has been completed \nsuccessfully. Refer to Figure 340\nBit 0 RQCP0: Request completed mailbox0\nSet by hardware when the last request (transmit or abort) has been performed.\nCleared by software writing a “1” or by hardware on transmission request (TXRQ0 set in \nCAN_TI0R register).\nClearing this bit clears all the status bits (TXOK0, ALST0 and TERR0) for Mailbox 0.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRFOM0\nFOVR0\nFULL0\nRes.\nFMP0[1:0]\nrs\nrc_w1\nrc_w1\nr\nr\nBits 31:6 Reserved, must be kept at reset value.\nBit 5 RFOM0: Release FIFO 0 output mailbox\nSet by software to release the output mailbox of the FIFO. The output mailbox can only be \nreleased when at least one message is pending in the FIFO. Setting this bit when the FIFO \nis empty has no effect. If at least two messages are pending in the FIFO, the software has to \nrelease the output mailbox to access the next message.\nCleared by hardware when the output mailbox has been released.\nBit 4 FOVR0: FIFO 0 overrun \nThis bit is set by hardware when a new message has been received and passed the filter \nwhile the FIFO was full. \nThis bit is cleared by software. \nBit 3 FULL0: FIFO 0 full\nSet by hardware when three messages are stored in the FIFO. \nThis bit is cleared by software.\nBit 2 Reserved, must be kept at reset value.\n" }, { "page_number": 1106, "page_indices": { "start_index": 2154389, "end_index": 2156486 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1106 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.2 CAN control and status registers", 1100 ], [ 4, "CAN receive FIFO 1 register (CAN_RF1R)", 1106 ], [ 4, "CAN interrupt enable register (CAN_IER)", 1106 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1106/1757\nRM0090 Rev 21\nCAN receive FIFO 1 register (CAN_RF1R)\nAddress offset: 0x10\nReset value: 0x0000 0000\n \n \nCAN interrupt enable register (CAN_IER)\nAddress offset: 0x14\nReset value: 0x0000 0000\n \nBits 1:0 FMP0[1:0]: FIFO 0 message pending\nThese bits indicate how many messages are pending in the receive FIFO. \nFMP is increased each time the hardware stores a new message in to the FIFO. FMP is \ndecreased each time the software releases the output mailbox by setting the RFOM0 bit.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRFOM1\nFOVR1\nFULL1\nRes.\nFMP1[1:0]\nrs\nrc_w1\nrc_w1\nr\nr\nBits 31:6 Reserved, must be kept at reset value.\nBit 5 RFOM1: Release FIFO 1 output mailbox\nSet by software to release the output mailbox of the FIFO. The output mailbox can only be \nreleased when at least one message is pending in the FIFO. Setting this bit when the FIFO \nis empty has no effect. If at least two messages are pending in the FIFO, the software has to \nrelease the output mailbox to access the next message.\nCleared by hardware when the output mailbox has been released.\nBit 4 FOVR1: FIFO 1 overrun \nThis bit is set by hardware when a new message has been received and passed the filter \nwhile the FIFO was full. \nThis bit is cleared by software. \nBit 3 FULL1: FIFO 1 full\nSet by hardware when three messages are stored in the FIFO.\nThis bit is cleared by software.\nBit 2 Reserved, must be kept at reset value.\nBits 1:0 FMP1[1:0]: FIFO 1 message pending\nThese bits indicate how many messages are pending in the receive FIFO1. \nFMP1 is increased each time the hardware stores a new message in to the FIFO1. FMP is \ndecreased each time the software releases the output mailbox by setting the RFOM1 bit.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nSLKIE\nWKUIE\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nERRIE\nReserved\nLEC\nIE\nBOF\nIE\nEPV\nIE\nEWG\nIE\nRes.\nFOV\nIE1\nFF\nIE1\nFMP\nIE1\nFOV\nIE0\nFF\nIE0\nFMP\nIE0\nTME\nIE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1107, "page_indices": { "start_index": 2156486, "end_index": 2158315 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1107 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.2 CAN control and status registers", 1100 ], [ 4, "CAN interrupt enable register (CAN_IER)", 1106 ] ], "page_content": "RM0090 Rev 21\n1107/1757\nRM0090\nController area network (bxCAN)\n1124\n \nBits 31:18 Reserved, must be kept at reset value.\nBit 17 SLKIE: Sleep interrupt enable\n0: No interrupt when SLAKI bit is set.\n1: Interrupt generated when SLAKI bit is set.\nBit 16 WKUIE: Wake-up interrupt enable\n0: No interrupt when WKUI is set.\n1: Interrupt generated when WKUI bit is set.\nBit 15 ERRIE: Error interrupt enable\n0: No interrupt is generated when an error condition is pending in the CAN_ESR.\n1: An interrupt is generation when an error condition is pending in the CAN_ESR.\nBits 14:12 Reserved, must be kept at reset value.\nBit 11 LECIE: Last error code interrupt enable\n0: ERRI bit is not set when the error code in LEC[2:0] is set by hardware on error detection.\n1: ERRI bit is set when the error code in LEC[2:0] is set by hardware on error detection.\nBit 10 BOFIE: Bus-off interrupt enable\n0: ERRI bit is not set when BOFF is set.\n1: ERRI bit is set when BOFF is set.\nBit 9 EPVIE: Error passive interrupt enable\n0: ERRI bit is not set when EPVF is set.\n1: ERRI bit is set when EPVF is set.\nBit 8 EWGIE: Error warning interrupt enable\n0: ERRI bit is not set when EWGF is set.\n1: ERRI bit is set when EWGF is set.\nBit 7 Reserved, must be kept at reset value.\nBit 6 FOVIE1: FIFO overrun interrupt enable\n0: No interrupt when FOVR is set.\n1: Interrupt generation when FOVR is set.\nBit 5 FFIE1: FIFO full interrupt enable\n0: No interrupt when FULL bit is set.\n1: Interrupt generated when FULL bit is set.\nBit 4 FMPIE1: FIFO message pending interrupt enable\n0: No interrupt generated when state of FMP[1:0] bits are not 00b.\n1: Interrupt generated when state of FMP[1:0] bits are not 00b.\nBit 3 FOVIE0: FIFO overrun interrupt enable\n0: No interrupt when FOVR bit is set.\n1: Interrupt generated when FOVR bit is set.\n" }, { "page_number": 1108, "page_indices": { "start_index": 2158315, "end_index": 2160469 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1108 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.2 CAN control and status registers", 1100 ], [ 4, "CAN error status register (CAN_ESR)", 1108 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1108/1757\nRM0090 Rev 21\nCAN error status register (CAN_ESR)\nAddress offset: 0x18\nReset value: 0x0000 0000\n \n \nBit 2 FFIE0: FIFO full interrupt enable\n0: No interrupt when FULL bit is set.\n1: Interrupt generated when FULL bit is set.\nBit 1 FMPIE0: FIFO message pending interrupt enable\n0: No interrupt generated when state of FMP[1:0] bits are not 00b.\n1: Interrupt generated when state of FMP[1:0] bits are not 00b.\nBit 0 TMEIE: Transmit mailbox empty interrupt enable\n0: No interrupt when RQCPx bit is set.\n1: Interrupt generated when RQCPx bit is set.\nNote: Refer to Section 32.8: bxCAN interrupts.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nREC[7:0]\nTEC[7:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nLEC[2:0]\nRes.\nBOFF\nEPVF\nEWGF\nrw\nrw\nrw\nr\nr\nr\nBits 31:24 REC[7:0]: Receive error counter \nThe implementing part of the fault confinement mechanism of the CAN protocol. In case of \nan error during reception, this counter is incremented by 1 or by 8 depending on the error \ncondition as defined by the CAN standard. After every successful reception the counter is \ndecremented by 1 or reset to 120 if its value was higher than 128. When the counter value \nexceeds 127, the CAN controller enters the error passive state.\nBits 23:16 TEC[7:0]: Least significant byte of the 9-bit transmit error counter\nThe implementing part of the fault confinement mechanism of the CAN protocol.\nBits 15:7 Reserved, must be kept at reset value.\nBits 6:4 LEC[2:0]: Last error code\nThis field is set by hardware and holds a code which indicates the error condition of the last \nerror detected on the CAN bus. If a message has been transferred (reception or \ntransmission) without error, this field is cleared to ‘0’. \nThe LEC[2:0] bits can be set to value 0b111 by software. They are updated by hardware to \nindicate the current communication status.\n000: No Error\n001: Stuff Error\n010: Form Error\n011: Acknowledgment Error\n100: Bit recessive Error\n101: Bit dominant Error\n110: CRC Error\n111: Set by software\nBit 3 Reserved, must be kept at reset value.\n" }, { "page_number": 1109, "page_indices": { "start_index": 2160469, "end_index": 2162071 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1109 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.2 CAN control and status registers", 1100 ], [ 4, "CAN bit timing register (CAN_BTR)", 1109 ] ], "page_content": "RM0090 Rev 21\n1109/1757\nRM0090\nController area network (bxCAN)\n1124\nCAN bit timing register (CAN_BTR)\nAddress offset: 0x1C\nReset value: 0x0123 0000\nThis register can only be accessed by the software when the CAN hardware is in \ninitialization mode.\n \n \nBit 2 BOFF: Bus-off flag\nThis bit is set by hardware when it enters the bus-off state. The bus-off state is entered on \nTEC overflow, greater than 255, refer to Section 32.7.6.\nBit 1 EPVF: Error passive flag\nThis bit is set by hardware when the Error Passive limit has been reached (Receive Error \nCounter or Transmit Error Counter>127).\nBit 0 EWGF: Error warning flag\nThis bit is set by hardware when the warning limit has been reached \n(Receive Error Counter or Transmit Error Counter≥96).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nSILM\nLBKM\nReserved\nSJW[1:0]\nRes.\nTS2[2:0]\nTS1[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBRP[9:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 SILM: Silent mode (debug)\n0: Normal operation\n1: Silent Mode\nBit 30 LBKM: Loop back mode (debug)\n0: Loop Back Mode disabled\n1: Loop Back Mode enabled\nBits 29:26 Reserved, must be kept at reset value.\nBits 25:24 SJW[1:0]: Resynchronization jump width\nThese bits define the maximum number of time quanta the CAN hardware is allowed to \nlengthen or shorten a bit to perform the resynchronization.\ntRJW = tq x (SJW[1:0] + 1)\nBit 23 Reserved, must be kept at reset value.\nBits 22:20 TS2[2:0]: Time segment 2\nThese bits define the number of time quanta in Time Segment 2.\ntBS2 = tq x (TS2[2:0] + 1)\n" }, { "page_number": 1110, "page_indices": { "start_index": 2162071, "end_index": 2163446 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1110 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.3 CAN mailbox registers", 1110 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1110/1757\nRM0090 Rev 21\n32.9.3 \nCAN mailbox registers\nThis chapter describes the registers of the transmit and receive mailboxes. Refer to \nSection 32.7.5: Message storage for detailed register mapping.\nTransmit and receive mailboxes have the same registers except:\n•\nThe FMI field in the CAN_RDTxR register.\n•\nA receive mailbox is always write protected.\n•\nA transmit mailbox is write-enabled only while empty, corresponding TME bit in the \nCAN_TSR register set.\nThere are three TX Mailboxes and two RX Mailboxes , as shown in Figure 349. Each RX \nMailbox allows access to a 3-level depth FIFO, the access being offered only to the oldest \nreceived message in the FIFO. Each mailbox consist of four registers.\nFigure 349. RX and TX mailboxes\nBits 19:16 TS1[3:0]: Time segment 1\nThese bits define the number of time quanta in Time Segment 1\ntBS1 = tq x (TS1[3:0] + 1)\nFor more information on bit timing refer to Section 32.7.7.\nBits 15:10 Reserved, must be kept at reset value.\nBits 9:0 BRP[9:0]: Baud rate prescaler\nThese bits define the length of a time quanta.\ntq = (BRP[9:0]+1) x tPCLK\nCAN_RI0R\nCAN_RDT0R\nCAN_RL0R\nCAN_RH0R\nCAN_TI0R\nCAN_TDT0R\nCAN_TDL0R\nCAN_TDH0R\nFIFO0\nThree Tx Mailboxes\nCAN_RI1R\nCAN_RDT1R\nCAN_RL1R\nCAN_RH1R\nFIFO1\nCAN_TI1R\nCAN_TDT1R\nCAN_TDL1R\nCAN_TDH1R\nCAN_TI2R\nCAN_TDT2R\nCAN_TDL2R\nCAN_TDH2R\n" }, { "page_number": 1111, "page_indices": { "start_index": 2163446, "end_index": 2164743 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1111 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.3 CAN mailbox registers", 1110 ], [ 4, "CAN TX mailbox identifier register (CAN_TIxR) (x=0..2)", 1111 ] ], "page_content": "RM0090 Rev 21\n1111/1757\nRM0090\nController area network (bxCAN)\n1124\nCAN TX mailbox identifier register (CAN_TIxR) (x=0..2)\nAddress offsets: 0x180, 0x190, 0x1A0\nReset value: 0xXXXX XXXX (except bit 0, TXRQ = 0)\nAll TX registers are write protected when the mailbox is pending transmission (TMEx reset). \nThis register also implements the TX request control (bit 0) - reset value 0.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nSTID[10:0]/EXID[28:18]\nEXID[17:13]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXID[12:0]\nIDE\nRTR\nTXRQ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:21 STID[10:0]/EXID[28:18]: Standard identifier or extended identifier\nThe standard identifier or the MSBs of the extended identifier (depending on the IDE bit \nvalue).\nBits 20:3 EXID[17:0]: Extended identifier\nThe LSBs of the extended identifier.\nBit 2 IDE: Identifier extension\nThis bit defines the identifier type of message in the mailbox.\n0: Standard identifier.\n1: Extended identifier.\nBit 1 RTR: Remote transmission request\n0: Data frame\n1: Remote frame\nBit 0 TXRQ: Transmit mailbox request\nSet by software to request the transmission for the corresponding mailbox.\nCleared by hardware when the mailbox becomes empty.\n" }, { "page_number": 1112, "page_indices": { "start_index": 2164743, "end_index": 2166213 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1112 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.3 CAN mailbox registers", 1110 ], [ 4, "CAN mailbox data length control and time stamp register (CAN_TDTxR) (x=0..2)", 1112 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1112/1757\nRM0090 Rev 21\nCAN mailbox data length control and time stamp register (CAN_TDTxR) \n(x=0..2)\nAll bits of this register are write protected when the mailbox is not in empty state.\nAddress offsets: 0x184, 0x194, 0x1A4\nReset value: 0xXXXX XXXX\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nTIME[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTGT\nReserved\nDLC[3:0]\nrw\nrw\nrw\nrw\nrw\nBits 31:16 TIME[15:0]: Message time stamp\nThis field contains the 16-bit timer value captured at the SOF transmission.\nBits 15:9 Reserved, must be kept at reset value.\nBit 8 TGT: Transmit global time \nThis bit is active only when the hardware is in the Time Trigger Communication mode, \nTTCM bit of the CAN_MCR register is set.\n0: Time stamp TIME[15:0] is not sent. \n1: Time stamp TIME[15:0] value is sent in the last two data bytes of the 8-byte message: \nTIME[7:0] in data byte 7 and TIME[15:8] in data byte 6, replacing the data written in \nCAN_TDHxR[31:16] register (DATA6[7:0] and DATA7[7:0]). DLC must be programmed as 8 \nin order these two bytes to be sent over the CAN bus. \nBits 7:4 Reserved, must be kept at reset value.\nBits 3:0 DLC[3:0]: Data length code\nThis field defines the number of data bytes a data frame contains or a remote frame request.\nA message can contain from 0 to 8 data bytes, depending on the value in the DLC field.\n" }, { "page_number": 1113, "page_indices": { "start_index": 2166213, "end_index": 2167878 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1113 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.3 CAN mailbox registers", 1110 ], [ 4, "CAN mailbox data low register (CAN_TDLxR) (x=0..2)", 1113 ], [ 4, "CAN mailbox data high register (CAN_TDHxR) (x=0..2)", 1113 ] ], "page_content": "RM0090 Rev 21\n1113/1757\nRM0090\nController area network (bxCAN)\n1124\nCAN mailbox data low register (CAN_TDLxR) (x=0..2)\nAll bits of this register are write protected when the mailbox is not in empty state.\nAddress offsets: 0x188, 0x198, 0x1A8\nReset value: 0xXXXX XXXX\n \n \nCAN mailbox data high register (CAN_TDHxR) (x=0..2)\nAll bits of this register are write protected when the mailbox is not in empty state.\nAddress offsets: 0x18C, 0x19C, 0x1AC\nReset value: 0xXXXX XXXX\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATA3[7:0]\nDATA2[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATA1[7:0]\nDATA0[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 DATA3[7:0]: Data byte 3 \nData byte 3 of the message.\nBits 23:16 DATA2[7:0]: Data byte 2 \nData byte 2 of the message. \nBits 15:8 DATA1[7:0]: Data byte 1 \nData byte 1 of the message. \nBits 7:0 DATA0[7:0]: Data byte 0\nData byte 0 of the message.\nA message can contain from 0 to 8 data bytes and starts with byte 0.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATA7[7:0]\nDATA6[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATA5[7:0]\nDATA4[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 DATA7[7:0]: Data byte 7 \nData byte 7 of the message.\nNote: If TGT of this message and TTCM are active, DATA7 and DATA6 are replaced by the \nTIME stamp value.\nBits 23:16 DATA6[7:0]: Data byte 6 \nData byte 6 of the message. \nBits 15:8 DATA5[7:0]: Data byte 5 \nData byte 5 of the message. \nBits 7:0 DATA4[7:0]: Data byte 4\nData byte 4 of the message.\n" }, { "page_number": 1114, "page_indices": { "start_index": 2167878, "end_index": 2168863 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1114 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.3 CAN mailbox registers", 1110 ], [ 4, "CAN receive FIFO mailbox identifier register (CAN_RIxR) (x=0..1)", 1114 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1114/1757\nRM0090 Rev 21\nCAN receive FIFO mailbox identifier register (CAN_RIxR) (x=0..1)\nAddress offsets: 0x1B0, 0x1C0\nReset value: 0xXXXX XXXX\nAll RX registers are write protected.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nSTID[10:0]/EXID[28:18]\nEXID[17:13]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEXID[12:0]\nIDE\nRTR\nRes.\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:21 STID[10:0]/EXID[28:18]: Standard identifier or extended identifier\nThe standard identifier or the MSBs of the extended identifier (depending on the IDE bit \nvalue).\nBits 20:3 EXID[17:0]: Extended identifier\nThe LSBs of the extended identifier. \nBit 2 IDE: Identifier extension\nThis bit defines the identifier type of message in the mailbox.\n0: Standard identifier.\n1: Extended identifier.\nBit 1 RTR: Remote transmission request\n0: Data frame\n1: Remote frame\nBit 0 Reserved, must be kept at reset value.\n" }, { "page_number": 1115, "page_indices": { "start_index": 2168863, "end_index": 2169865 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1115 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.3 CAN mailbox registers", 1110 ], [ 4, "CAN receive FIFO mailbox data length control and time stamp register (CAN_RDTxR) (x=0..1)", 1115 ] ], "page_content": "RM0090 Rev 21\n1115/1757\nRM0090\nController area network (bxCAN)\n1124\nCAN receive FIFO mailbox data length control and time stamp register \n(CAN_RDTxR) (x=0..1)\nAddress offsets: 0x1B4, 0x1C4\nReset value: 0xXXXX XXXX\nAll RX registers are write protected.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nTIME[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFMI[7:0]\nReserved\nDLC[3:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 TIME[15:0]: Message time stamp\nThis field contains the 16-bit timer value captured at the SOF detection.\nBits 15:8 FMI[7:0]: Filter match index\nThis register contains the index of the filter the message stored in the mailbox passed \nthrough. For more details on identifier filtering refer to Section 32.7.4 \nBits 7:4 Reserved, must be kept at reset value.\nBits 3:0 DLC[3:0]: Data length code\nThis field defines the number of data bytes a data frame contains (0 to 8). It is 0 in the case \nof a remote frame request.\n" }, { "page_number": 1116, "page_indices": { "start_index": 2169865, "end_index": 2171359 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1116 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.3 CAN mailbox registers", 1110 ], [ 4, "CAN receive FIFO mailbox data low register (CAN_RDLxR) (x=0..1)", 1116 ], [ 4, "CAN receive FIFO mailbox data high register (CAN_RDHxR) (x=0..1)", 1116 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1116/1757\nRM0090 Rev 21\nCAN receive FIFO mailbox data low register (CAN_RDLxR) (x=0..1)\nAll bits of this register are write protected when the mailbox is not in empty state.\nAddress offsets: 0x1B8, 0x1C8\nReset value: 0xXXXX XXXX\nAll RX registers are write protected.\n \n \nCAN receive FIFO mailbox data high register (CAN_RDHxR) (x=0..1)\nAddress offsets: 0x1BC, 0x1CC\nReset value: 0xXXXX XXXX\nAll RX registers are write protected.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATA3[7:0]\nDATA2[7:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATA1[7:0]\nDATA0[7:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:24 DATA3[7:0]: Data Byte 3 \nData byte 3 of the message.\nBits 23:16 DATA2[7:0]: Data Byte 2 \nData byte 2 of the message. \nBits 15:8 DATA1[7:0]: Data Byte 1 \nData byte 1 of the message. \nBits 7:0 DATA0[7:0]: Data Byte 0 \nData byte 0 of the message.\nA message can contain from 0 to 8 data bytes and starts with byte 0.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nDATA7[7:0]\nDATA6[7:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDATA5[7:0]\nDATA4[7:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:24 DATA7[7:0]: Data Byte 7 \nData byte 3 of the message.\nBits 23:16 DATA6[7:0]: Data Byte 6 \nData byte 2 of the message. \nBits 15:8 DATA5[7:0]: Data Byte 5 \nData byte 1 of the message. \nBits 7:0 DATA4[7:0]: Data Byte 4 \nData byte 0 of the message.\n" }, { "page_number": 1117, "page_indices": { "start_index": 2171359, "end_index": 2172319 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1117 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.4 CAN filter registers", 1117 ], [ 4, "CAN filter master register (CAN_FMR)", 1117 ] ], "page_content": "RM0090 Rev 21\n1117/1757\nRM0090\nController area network (bxCAN)\n1124\n32.9.4 \nCAN filter registers\nCAN filter master register (CAN_FMR)\nAddress offset: 0x200\nReset value: 0x2A1C 0E01\nAll bits of this register are set and cleared by software.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCAN2SB[5:0]\nReserved\nFINIT\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:14 Reserved, must be kept at reset value.\nBits 13:8 CAN2SB[5:0]: CAN2 start bank\nThese bits are set and cleared by software. They define the start bank for the CAN2 \ninterface (Slave) in the range 0 to 27.\nNote: When CAN2SB[5:0] = 28d, all the filters to CAN1 can be used.\nWhen CAN2SB[5:0] is set to 0, no filters are assigned to CAN1. \nBits 7:1 Reserved, must be kept at reset value.\nBit 0 FINIT: Filter init mode \nInitialization mode for filter banks\n0: Active filters mode.\n1: Initialization mode for the filters.\n" }, { "page_number": 1118, "page_indices": { "start_index": 2172319, "end_index": 2174044 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1118 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.4 CAN filter registers", 1117 ], [ 4, "CAN filter mode register (CAN_FM1R)", 1118 ], [ 4, "CAN filter scale register (CAN_FS1R)", 1118 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1118/1757\nRM0090 Rev 21\nCAN filter mode register (CAN_FM1R)\nAddress offset: 0x204\nReset value: 0x0000 0000\nThis register can be written only when the filter initialization mode is set (FINIT=1) in the \nCAN_FMR register.\n \nNote:\nRefer to Figure 342.\n \nCAN filter scale register (CAN_FS1R)\nAddress offset: 0x20C\nReset value: 0x0000 0000\nThis register can be written only when the filter initialization mode is set (FINIT=1) in the \nCAN_FMR register.\n \n \nNote:\nRefer to Figure 342.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nFBM27\nFBM26\nFBM25\nFBM24\nFBM23\nFBM22\nFBM21\nFBM20\nFBM19\nFBM18\nFBM17\nFBM16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFBM15\nFBM14\nFBM13\nFBM12\nFBM11\nFBM10\nFBM9\nFBM8\nFBM7\nFBM6\nFBM5\nFBM4\nFBM3\nFBM2\nFBM1\nFBM0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28\nReserved, must be kept at reset value.\nBits 27:0 FBMx: Filter mode\nMode of the registers of Filter x. \n0: Two 32-bit registers of filter bank x are in Identifier Mask mode.\n1: Two 32-bit registers of filter bank x are in Identifier List mode.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nFSC27\nFSC26\nFSC25\nFSC24\nFSC23\nFSC22\nFSC21\nFSC20\nFSC19\nFSC18\nFSC17\nFSC16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFSC15\nFSC14\nFSC13\nFSC12\nFSC11\nFSC10\nFSC9\nFSC8\nFSC7\nFSC6\nFSC5\nFSC4\nFSC3\nFSC2\nFSC1\nFSC0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBits 27:0 FSCx: Filter scale configuration\nThese bits define the scale configuration of Filters 13-0.\n0: Dual 16-bit scale configuration\n1: Single 32-bit scale configuration\n" }, { "page_number": 1119, "page_indices": { "start_index": 2174044, "end_index": 2175719 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1119 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.4 CAN filter registers", 1117 ], [ 4, "CAN filter FIFO assignment register (CAN_FFA1R)", 1119 ], [ 4, "CAN filter activation register (CAN_FA1R)", 1119 ] ], "page_content": "RM0090 Rev 21\n1119/1757\nRM0090\nController area network (bxCAN)\n1124\nCAN filter FIFO assignment register (CAN_FFA1R)\nAddress offset: 0x214\nReset value: 0x0000 0000\nThis register can be written only when the filter initialization mode is set (FINIT=1) in the \nCAN_FMR register.\n \n \nCAN filter activation register (CAN_FA1R)\nAddress offset: 0x21C\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nFFA27\nFFA26\nFFA25\nFFA24\nFFA23\nFFA22\nFFA21\nFFA20\nFFA19\nFFA18\nFFA17\nFFA16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFFA15\nFFA14\nFFA13\nFFA12\nFFA11\nFFA10\nFFA9\nFFA8\nFFA7\nFFA6\nFFA5\nFFA4\nFFA3\nFFA2\nFFA1\nFFA0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBits 27:0 FFAx: Filter FIFO assignment for filter x\nThe message passing through this filter is stored in the specified FIFO.\n0: Filter assigned to FIFO 0\n1: Filter assigned to FIFO 1\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nFACT27 FACT26 FACT25 FACT24 FACT23 FACT22 FACT21 FACT20 FACT19 FACT18 FACT17 FACT16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFACT15 FACT14 FACT13 FACT12 FACT11 FACT10 FACT9\nFACT8\nFACT7\nFACT6\nFACT5\nFACT4\nFACT3\nFACT2\nFACT1\nFACT0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBits 27:0 FACTx: Filter active\nThe software sets this bit to activate Filter x. To modify the Filter x registers (CAN_FxR[0:7]), \nthe FACTx bit must be cleared or the FINIT bit of the CAN_FMR register must be set.\n0: Filter x is not active\n1: Filter x is active\n" }, { "page_number": 1120, "page_indices": { "start_index": 2175719, "end_index": 2177494 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1120 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.4 CAN filter registers", 1117 ], [ 4, "Filter bank i register x (CAN_FiRx) (i=0..27, x=1, 2)", 1120 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1120/1757\nRM0090 Rev 21\nFilter bank i register x (CAN_FiRx) (i=0..27, x=1, 2)\nAddress offsets: 0x240..0x31C\nReset value: 0xXXXX XXXX\nThere are 28 filter banks, i=0 .. 27. Each filter bank i is composed of two 32-bit registers, \nCAN_FiR[2:1].\nThis register can only be modified when the FACTx bit of the CAN_FAxR register is cleared \nor when the FINIT bit of the CAN_FMR register is set.\n \nIn all configurations:\n \nNote:\nDepending on the scale and mode configuration of the filter the function of each register can \ndiffer. For the filter mapping, functions description and mask registers association, refer to \nSection 32.7.4.\nA Mask/Identifier register in mask mode has the same bit mapping as in identifier list \nmode. \nFor the register mapping/addresses of the filter banks refer to Table 185.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nFB31\nFB30\nFB29\nFB28\nFB27\nFB26\nFB25\nFB24\nFB23\nFB22\nFB21\nFB20\nFB19\nFB18\nFB17\nFB16\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFB15\nFB14\nFB13\nFB12\nFB11\nFB10\nFB9\nFB8\nFB7\nFB6\nFB5\nFB4\nFB3\nFB2\nFB1\nFB0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 FB[31:0]: Filter bits \nIdentifier\nEach bit of the register specifies the level of the corresponding bit of the expected identifier.\n0: Dominant bit is expected\n1: Recessive bit is expected\nMask\nEach bit of the register specifies whether the bit of the associated identifier register must \nmatch with the corresponding bit of the expected identifier or not.\n0: Don’t care, the bit is not used for the comparison\n1: Must match, the bit of the incoming identifier must have the same level has specified in \nthe corresponding identifier register of the filter.\n" }, { "page_number": 1121, "page_indices": { "start_index": 2177494, "end_index": 2179339 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1121 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.5 bxCAN register map", 1121 ] ], "page_content": "RM0090 Rev 21\n1121/1757\nRM0090\nController area network (bxCAN)\n1124\n32.9.5 \nbxCAN register map\nRefer to Section 2.3: Memory map for the register boundary addresses. The registers from \noffset 0x200 to 31C are present only in CAN1.\n \nTable 185. bxCAN register map and reset values \nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x000\nCAN_MCR\nReserved\nDBF\nRESET\nReserved\nTTCM\nABOM\nAWUM\nNART\nRFLM\nTXFP\nSLEEP\nINRQ\nReset value\n1\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0x004\nCAN_MSR\nReserved\nRX\nSAMP\nRXM\nTXM\nRes.\nSLAKI\nWKUI\nERRI\nSLAK\nINAK\nReset value\n1\n1\n0\n0\n0\n0\n0\n1\n0\n0x008\nCAN_TSR\nLOW[2:0]\nTME[2:0]\nCODE[1:0]\nABRQ2\nRes.\nTERR2\nALST2\nTXOK2\nRQCP2\nABRQ1\nRes.\nTERR1\nALST1\nTXOK1\nRQCP1\nABRQ0\nRes..\nTERR0\nALST0\nTXOK0\nRQCP0\nReset value\n0\n0\n0\n1\n1\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x00C\nCAN_RF0R\nReserved\nRFOM0\nFOVR0\nFULL0\nReserved\nFMP0[1:0]\nReset value\n0\n0\n0\n0\n0\n0x010\nCAN_RF1R\nReserved\nRFOM1\nFOVR1\nFULL1\nReserved\nFMP1[1:0]\nReset value\n0\n0\n0\n0\n0\n0x014\nCAN_IER\nReserved\nSLKIE\nWKUIE\nERRIE\nRes.\nLECIE\nBOFIE\nEPVIE\nEWGIE\nReserved\nFOVIE1\nFFIE1\nFMPIE1\nFOVIE0\nFFIE0\nFMPIE0\nTMEIE\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x018\nCAN_ESR\nREC[7:0]\nTEC[7:0]\nReserved\nLEC[2:0]\nReserved\nBOFF\nEPVF\nEWGF\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x01C\nCAN_BTR\nSILM\nLBKM\nReserved\nSJW[1:0]\nReserved\nTS2[2:0]\nTS1[3:0]\nReserved\nBRP[9:0]\nReset value\n0\n0\n0\n0\n0\n1\n0\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x020-\n0x17F\nReserved\n0x180\nCAN_TI0R\nSTID[10:0]/EXID[28:18]\nEXID[17:0]\nIDE\nRTR\nTXRQ\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0\n0x184\nCAN_TDT0R\nTIME[15:0]\nReserved\nTGT\nReserved\nDLC[3:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x188\nCAN_TDL0R\nDATA3[7:0]\nDATA2[7:0]\nDATA1[7:0]\nDATA0[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n" }, { "page_number": 1122, "page_indices": { "start_index": 2179339, "end_index": 2181441 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1122 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.5 bxCAN register map", 1121 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1122/1757\nRM0090 Rev 21\n0x18C\nCAN_TDH0R\nDATA7[7:0]\nDATA6[7:0]\nDATA5[7:0]\nDATA4[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x190\nCAN_TI1R\nSTID[10:0]/EXID[28:18]\nEXID[17:0]\nIDE\nRTR\nTXRQ\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0\n0x194\nCAN_TDT1R\nTIME[15:0]\nReserved\nTGT\nReserved\nDLC[3:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x198\nCAN_TDL1R\nDATA3[7:0]\nDATA2[7:0]\nDATA1[7:0]\nDATA0[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x19C\nCAN_TDH1R\nDATA7[7:0]\nDATA6[7:0]\nDATA5[7:0]\nDATA4[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1A0\nCAN_TI2R\nSTID[10:0]/EXID[28:18]\nEXID[17:0]\nIDE\nRTR\nTXRQ\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0\n0x1A4\nCAN_TDT2R\nTIME[15:0]\nReserved\nTGT\nReserved\nDLC[3:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1A8\nCAN_TDL2R\nDATA3[7:0]\nDATA2[7:0]\nDATA1[7:0]\nDATA0[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1AC\nCAN_TDH2R\nDATA7[7:0]\nDATA6[7:0]\nDATA5[7:0]\nDATA4[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1B0\nCAN_RI0R\nSTID[10:0]/EXID[28:18]\nEXID[17:0]\nIDE\nRTR\nReserved\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1B4\nCAN_RDT0R\nTIME[15:0]\nFMI[7:0]\nReserved\nDLC[3:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1B8\nCAN_RDL0R\nDATA3[7:0]\nDATA2[7:0]\nDATA1[7:0]\nDATA0[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1BC\nCAN_RDH0R\nDATA7[7:0]\nDATA6[7:0]\nDATA5[7:0]\nDATA4[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1C0\nCAN_RI1R\nSTID[10:0]/EXID[28:18]\nEXID[17:0]\nIDE\nRTR\nReserved\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nTable 185. bxCAN register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1123, "page_indices": { "start_index": 2181441, "end_index": 2182978 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1123 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.5 bxCAN register map", 1121 ] ], "page_content": "RM0090 Rev 21\n1123/1757\nRM0090\nController area network (bxCAN)\n1124\n0x1C4\nCAN_RDT1R\nTIME[15:0]\nFMI[7:0]\nReserved\nDLC[3:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1C8\nCAN_RDL1R\nDATA3[7:0]\nDATA2[7:0]\nDATA1[7:0]\nDATA0[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1CC\nCAN_RDH1R\nDATA7[7:0]\nDATA6[7:0]\nDATA5[7:0]\nDATA4[7:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x1D0-\n0x1FF\nReserved\n0x200\nCAN_FMR\nReserved\nCAN2SB[5:0]\nReserved\nFINIT\nReset value\n0\n0\n1\n1\n1\n0\n1\n0x204\nCAN_FM1R\nReserved\nFBM[27:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x208\nReserved\n0x20C\nCAN_FS1R\nReserved\nFSC[27:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x210\nReserved\n0x214\nCAN_FFA1R\nReserved\nFFA[27:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x218\nReserved\n0x21C\nCAN_FA1R\nReserved\nFACT[27:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x220\nReserved\n0x224-\n0x23F\nReserved\n0x240\nCAN_F0R1\nFB[31:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x244\nCAN_F0R2\nFB[31:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x248\nCAN_F1R1\nFB[31:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nTable 185. bxCAN register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1124, "page_indices": { "start_index": 2182978, "end_index": 2183552 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1124 }, "toc_details": [ [ 1, "32 Controller area network (bxCAN)", 1079 ], [ 2, "32.9 CAN registers", 1100 ], [ 3, "32.9.5 bxCAN register map", 1121 ] ], "page_content": "Controller area network (bxCAN)\nRM0090\n1124/1757\nRM0090 Rev 21\n0x24C\nCAN_F1R2\nFB[31:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n.\n.\n.\n.\n.\n.\n.\n.\n.\n.\n.\n.\n0x318\nCAN_F27R1\nFB[31:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\n0x31C\nCAN_F27R2\nFB[31:0]\nReset value\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nx\nTable 185. bxCAN register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1125, "page_indices": { "start_index": 2183552, "end_index": 2184861 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1125 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.1 Ethernet introduction", 1125 ], [ 2, "33.2 Ethernet main features", 1125 ] ], "page_content": "RM0090 Rev 21\n1125/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n33 \nEthernet (ETH): media access control (MAC) with\nDMA controller\nThis section applies only to STM32F42xx/F43xx and STM32F407x/F417x devices.\n33.1 \nEthernet introduction\nPortions Copyright (c) 2004, 2005 Synopsys, Inc. All rights reserved. Used with permission.\nThe Ethernet peripheral enables the STM32F4xx to transmit and receive data over Ethernet \nin compliance with the IEEE 802.3-2002 standard.\nThe Ethernet provides a configurable, flexible peripheral to meet the needs of various \napplications and customers. It supports two industry standard interfaces to the external \nphysical layer (PHY): the default media independent interface (MII) defined in the IEEE \n802.3 specifications and the reduced media independent interface (RMII). It can be used in \nnumber of applications such as switches, network interface cards, etc.\nThe Ethernet is compliant with the following standards:\n•\nIEEE 802.3-2002 for Ethernet MAC\n•\nIEEE 1588-2008 standard for precision networked clock synchronization\n•\nAMBA 2.0 for AHB Master/Slave ports\n•\nRMII specification from RMII consortium\n33.2 \nEthernet main features\nThe Ethernet (ETH) peripheral includes the following features, listed by category:\n" }, { "page_number": 1126, "page_indices": { "start_index": 2184861, "end_index": 2187723 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1126 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.2 Ethernet main features", 1125 ], [ 3, "33.2.1 MAC core features", 1126 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1126/1757\nRM0090 Rev 21\n33.2.1 \nMAC core features\n•\nSupports 10/100 Mbit/s data transfer rates with external PHY interfaces\n•\nIEEE 802.3-compliant MII interface to communicate with an external Fast Ethernet \nPHY\n•\nSupports both full-duplex and half-duplex operations\n–\nSupports CSMA/CD Protocol for half-duplex operation\n–\nSupports IEEE 802.3x flow control for full-duplex operation\n–\nOptional forwarding of received pause control frames to the user application in full-\nduplex operation\n–\nBack-pressure support for half-duplex operation\n–\nAutomatic transmission of zero-quanta pause frame on deassertion of flow control \ninput in full-duplex operation\n•\nPreamble and start-of-frame data (SFD) insertion in Transmit, and deletion in Receive \npaths\n•\nAutomatic CRC and pad generation controllable on a per-frame basis\n•\nOptions for automatic pad/CRC stripping on receive frames\n•\nProgrammable frame length to support Standard frames with sizes up to 16 KB\n•\nProgrammable interframe gap (40-96 bit times in steps of 8)\n•\nSupports a variety of flexible address filtering modes:\n–\nUp to four 48-bit perfect (DA) address filters with masks for each byte\n–\nUp to three 48-bit SA address comparison check with masks for each byte\n–\n64-bit Hash filter (optional) for multicast and unicast (DA) addresses\n–\nOption to pass all multicast addressed frames\n–\nPromiscuous mode support to pass all frames without any filtering for network \nmonitoring\n–\nPasses all incoming packets (as per filter) with a status report\n•\nSeparate 32-bit status returned for transmission and reception packets\n•\nSupports IEEE 802.1Q VLAN tag detection for reception frames\n•\nSeparate transmission, reception, and control interfaces to the Application\n•\nSupports mandatory network statistics with RMON/MIB counters (RFC2819/RFC2665)\n•\nMDIO interface for PHY device configuration and management\n•\nDetection of LAN wake-up frames and AMD Magic Packet™ frames\n•\nReceive feature for checksum off-load for received IPv4 and TCP packets \nencapsulated by the Ethernet frame\n•\nEnhanced receive feature for checking IPv4 header checksum and TCP, UDP, or ICMP \nchecksum encapsulated in IPv4 or IPv6 datagrams\n•\nSupport Ethernet frame time stamping as described in IEEE 1588-2008. Sixty-four-bit \ntime stamps are given in each frame’s transmit or receive status\n•\nTwo sets of FIFOs: a 2-KB Transmit FIFO with programmable threshold capability, and \na 2-KB Receive FIFO with a configurable threshold (default of 64 bytes)\n•\nReceive Status vectors inserted into the Receive FIFO after the EOF transfer enables \nmultiple-frame storage in the Receive FIFO without requiring another FIFO to store \nthose frames’ Receive Status\n•\nOption to filter all error frames on reception and not forward them to the application in \n" }, { "page_number": 1127, "page_indices": { "start_index": 2187723, "end_index": 2189971 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1127 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.2 Ethernet main features", 1125 ], [ 3, "33.2.2 DMA features", 1127 ], [ 3, "33.2.3 PTP features", 1127 ] ], "page_content": "RM0090 Rev 21\n1127/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nStore-and-Forward mode\n•\nOption to forward under-sized good frames\n•\nSupports statistics by generating pulses for frames dropped or corrupted (due to \noverflow) in the Receive FIFO\n•\nSupports Store and Forward mechanism for transmission to the MAC core\n•\nAutomatic generation of PAUSE frame control or back pressure signal to the MAC core \nbased on Receive FIFO-fill (threshold configurable) level\n•\nHandles automatic retransmission of Collision frames for transmission\n•\nDiscards frames on late collision, excessive collisions, excessive deferral and underrun \nconditions\n•\nSoftware control to flush Tx FIFO\n•\nCalculates and inserts IPv4 header checksum and TCP, UDP, or ICMP checksum in \nframes transmitted in Store-and-Forward mode\n•\nSupports internal loopback on the MII for debugging\n33.2.2 \nDMA features\n•\nSupports all AHB burst types in the AHB Slave Interface\n•\nSoftware can select the type of AHB burst (fixed or indefinite burst) in the AHB Master \ninterface.\n•\nOption to select address-aligned bursts from AHB master port\n•\nOptimization for packet-oriented DMA transfers with frame delimiters\n•\nByte-aligned addressing for data buffer support\n•\nDual-buffer (ring) or linked-list (chained) descriptor chaining\n•\nDescriptor architecture, allowing large blocks of data transfer with minimum CPU \nintervention;\n•\neach descriptor can transfer up to 8 KB of data\n•\nComprehensive status reporting for normal operation and transfers with errors\n•\nIndividual programmable burst size for Transmit and Receive DMA Engines for optimal \nhost bus utilization\n•\nProgrammable interrupt options for different operational conditions\n•\nPer-frame Transmit/Receive complete interrupt control\n•\nRound-robin or fixed-priority arbitration between Receive and Transmit engines\n•\nStart/Stop modes\n•\nCurrent Tx/Rx buffer pointer as status registers\n•\nCurrent Tx/Rx descriptor pointer as status registers\n33.2.3 \nPTP features\n•\nReceived and transmitted frames time stamping\n•\nCoarse and fine correction methods\n•\nTrigger interrupt when system time becomes greater than target time\n•\nPulse per second output (product alternate function output)\n" }, { "page_number": 1128, "page_indices": { "start_index": 2189971, "end_index": 2191150 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1128 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.3 Ethernet pins", 1128 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1128/1757\nRM0090 Rev 21\n33.3 \nEthernet pins\nTable 186 shows the MAC signals and the corresponding MII/RMII signal mapping. All MAC \nsignals are mapped onto AF11, some signals are mapped onto different I/O pins, and \nshould be configured in Alternate function mode (for more details, refer to Section 8.3.2: I/O \npin multiplexer and mapping).\n \nTable 186. Alternate function mapping\nPort\nAF11\nETH\nPA0-WKUP\nETH_MII_CRS\nPA1\nETH_MII _RX_CLK / ETH_RMII _REF_CLK\nPA2\nETH _MDIO\nPA3\nETH _MII_COL\nPA7\nETH_MII _RX_DV / ETH_RMII _CRS_DV\nPB0\nETH _MII_RXD2\nPB1\nETH _MII_RXD3\nPB5\nETH _PPS_OUT\nPB8\nETH _MII_TXD3\nPB10\nETH_ MII_RX_ER\nPB11\nETH _MII_TX_EN / ETH _RMII_TX_EN\nPB12\nETH _MII_TXD0 / ETH _RMII_TXD0\nPB13\nETH _MII_TXD1 / ETH _RMII_TXD1\nPC1\nETH _MDC\nPC2\nETH _MII_TXD2\nPC3\nETH _MII_TX_CLK\nPC4\nETH_MII_RXD0 / ETH_RMII_RXD0\nPC5\nETH _MII_RXD1/ ETH _RMII_RXD1\nPE2\nETH_MII_TXD3\nPG8\nETH_PPS_OUT\nPG11\nETH _MII_TX_EN / ETH _RMII_TX_EN\nPG13\nETH _MII_TXD0 / ETH _RMII_TXD0\nPG14\nETH _MII_TXD1 / ETH _RMII_TXD1\nPH2\nETH _MII_CRS\nPH3\nETH _MII_COL\nPH6\nETH _MII_RXD2\nPH7\nETH _MII_RXD3\nPI10\nETH _MII_RX_ER\n" }, { "page_number": 1129, "page_indices": { "start_index": 2191150, "end_index": 2193599 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1129 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.4 Ethernet functional description: SMI, MII and RMII", 1129 ], [ 3, "33.4.1 Station management interface: SMI", 1129 ] ], "page_content": "RM0090 Rev 21\n1129/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n33.4 \nEthernet functional description: SMI, MII and RMII\nThe Ethernet peripheral consists of a MAC 802.3 (media access control) with a dedicated \nDMA controller. It supports both default media-independent interface (MII) and reduced \nmedia-independent interface (RMII) through one selection bit (refer to SYSCFG_PMC \nregister).\nThe DMA controller interfaces with the Core and memories through the AHB Master and \nSlave interfaces. The AHB Master Interface controls data transfers while the AHB Slave \ninterface accesses Control and Status registers (CSR) space.\nThe Transmit FIFO (Tx FIFO) buffers data read from system memory by the DMA before \ntransmission by the MAC Core. Similarly, the Receive FIFO (Rx FIFO) stores the Ethernet \nframes received from the line until they are transferred to system memory by the DMA. \nThe Ethernet peripheral also includes an SMI to communicate with external PHY. A set of \nconfiguration registers permit the user to select the desired mode and features for the MAC \nand the DMA controller.\nNote:\nThe AHB clock frequency must be at least 25 MHz when the Ethernet is used.\nFigure 350. ETH block diagram\n1.\nFor AHB connections refer to Figure 1: System architecture for STM32F405xx/07xx and \nSTM32F415xx/17xx devices and Figure 2: System architecture for STM32F42xxx and STM32F43xxx \ndevices.\n33.4.1 \nStation management interface: SMI\nThe station management interface (SMI) allows the application to access any PHY registers \nthrough a 2-wire clock and data lines. The interface supports accessing up to 32 PHYs.\nThe application can select one of the 32 PHYs and one of the 32 registers within any PHY \nand send control data or receive status information. Only one register in one PHY can be \naddressed at any given time.\nBoth the MDC clock line and the MDIO data line are implemented as alternate function I/O \nin the microcontroller:\n•\nMDC: a periodic clock that provides the timing reference for the data transfer at the \nmaximum frequency of 2.5 MHz. The minimum high and low times for MDC must be \n2 Kbyte\nRX FIFO\n \nEthernet\nDMA \nMedia access\ncontrol\nMAC 802.3 \nMAC\ncontrol\nregisters\nDMA\ncontrol &\nstatus\nregisters\nOperation\nmode\nregister\n \nInterface\nSelect \nMII \nMDC \nMDIO\nAHB Slave interface\nRMII \nai15620c\nBus matrix\nExternal PHY\nChecksum\noffload\nPTP\nIEEE1588\nPMT\nMMC\n2 Kbyte\nTX FIFO\n" }, { "page_number": 1130, "page_indices": { "start_index": 2193599, "end_index": 2195677 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1130 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.4 Ethernet functional description: SMI, MII and RMII", 1129 ], [ 3, "33.4.1 Station management interface: SMI", 1129 ], [ 4, "SMI frame format", 1130 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1130/1757\nRM0090 Rev 21\n160 ns each, and the minimum period for MDC must be 400 ns. In idle state the SMI \nmanagement interface drives the MDC clock signal low.\n•\nMDIO: data input/output bitstream to transfer status information to/from the PHY device \nsynchronously with the MDC clock signal\nFigure 351. SMI interface signals\nSMI frame format\nThe frame structure related to a read or write operation is shown in Table 187, the order of \nbit transmission must be from left to right.\n \nThe management frame consists of eight fields:\n•\nPreamble: each transaction (read or write) can be initiated with the preamble field that \ncorresponds to 32 contiguous logic one bits on the MDIO line with 32 corresponding \ncycles on MDC. This field is used to establish synchronization with the PHY device.\n•\nStart: the start of frame is defined by a <01> pattern to verify transitions on the line \nfrom the default logic one state to zero and back to one.\n•\nOperation: defines the type of transaction (read or write) in progress.\n•\nPADDR: the PHY address is 5 bits, allowing 32 unique PHY addresses. The MSB bit of \nthe address is the first transmitted and received.\n•\nRADDR: the register address is 5 bits, allowing 32 individual registers to be addressed \nwithin the selected PHY device. The MSB bit of the address is the first transmitted and \nreceived.\n•\nTA: the turn-around field defines a 2-bit pattern between the RADDR and DATA fields \nto avoid contention during a read transaction. For a read transaction the MAC controller \ndrives high-impedance on the MDIO line for the 2 bits of TA. The PHY device must \ndrive a high-impedance state on the first bit of TA, a zero bit on the second one.\nTable 187. Management frame format\nManagement frame fields\nPreamble \n(32 bits)\nStart\nOperation\nPADDR\nRADDR\nTA\nData (16 bits)\nIdle\nRead\n1... 1\n 01\n 10\nppppp\nrrrrr\nZ0\nddddddddddddddd\nZ\nWrite\n1... 1\n 01\n 01\nppppp\nrrrrr\n10\nddddddddddddddd\nZ\nSTM32 MCU \nMDIO\n \nMDC\nExternal \nPHY \nai15621b\n802.3 MAC\n" }, { "page_number": 1131, "page_indices": { "start_index": 2195677, "end_index": 2198003 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1131 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.4 Ethernet functional description: SMI, MII and RMII", 1129 ], [ 3, "33.4.1 Station management interface: SMI", 1129 ], [ 4, "SMI write operation", 1131 ], [ 4, "SMI read operation", 1131 ] ], "page_content": "RM0090 Rev 21\n1131/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nFor a write transaction, the MAC controller drives a <10> pattern during the TA field. \nThe PHY device must drive a high-impedance state for the 2 bits of TA.\n•\nData: the data field is 16-bit. The first bit transmitted and received must be bit 15 of the \nETH_MIID register.\n•\nIdle: the MDIO line is driven in high-impedance state. All three-state drivers must be \ndisabled and the PHY’s pull-up resistor keeps the line at logic one.\nSMI write operation\nWhen the application sets the MII Write and Busy bits (in Ethernet MAC MII address register \n(ETH_MACMIIAR)), the SMI initiates a write operation into the PHY registers by transferring \nthe PHY address, the register address in PHY, and the write data (in Ethernet MAC MII data \nregister (ETH_MACMIIDR). The application should not change the MII Address register \ncontents or the MII Data register while the transaction is ongoing. Write operations to the MII \nAddress register or the MII Data register during this period are ignored (the Busy bit is high), \nand the transaction is completed without any error. After the Write operation has completed, \nthe SMI indicates this by resetting the Busy bit.\nFigure 352 shows the frame format for the write operation.\nFigure 352. MDIO timing and frame structure - Write cycle\nSMI read operation\nWhen the user sets the MII Busy bit in the Ethernet MAC MII address register \n(ETH_MACMIIAR) with the MII Write bit at 0, the SMI initiates a read operation in the PHY \nregisters by transferring the PHY address and the register address in PHY. The application \nshould not change the MII Address register contents or the MII Data register while the \ntransaction is ongoing. Write operations to the MII Address register or MII Data register \nduring this period are ignored (the Busy bit is high) and the transaction is completed without \nany error. After the read operation has completed, the SMI resets the Busy bit and then \nupdates the MII Data register with the data read from the PHY. \nFigure 353 shows the frame format for the read operation.\nMDC\nMDIO\n32 1's\n0\n1\n0 1\nA4\nA3\nA2\nA1 A0\nR4\nR3\nR2\nR1\nR0\nD15 D14\nD1\nD0\nPreamble\nStart\nof\nframe\nOP\ncode\nPHY address\nRegister address\nTurn\naround\ndata\nData to PHY\nai15626\n" }, { "page_number": 1132, "page_indices": { "start_index": 2198003, "end_index": 2199253 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1132 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.4 Ethernet functional description: SMI, MII and RMII", 1129 ], [ 3, "33.4.1 Station management interface: SMI", 1129 ], [ 4, "SMI clock selection", 1132 ], [ 3, "33.4.2 Media-independent interface: MII", 1132 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1132/1757\nRM0090 Rev 21\nFigure 353. MDIO timing and frame structure - Read cycle\nSMI clock selection\nThe MAC initiates the Management Write/Read operation. The SMI clock is a divided clock \nwhose source is the application clock (AHB clock). The divide factor depends on the clock \nrange setting in the MII Address register.\nTable 188 shows how to set the clock ranges.\n \n33.4.2 \nMedia-independent interface: MII\nThe media-independent interface (MII) defines the interconnection between the MAC \nsublayer and the PHY for data transfer at 10 Mbit/s and 100 Mbit/s.\nFigure 354. Media independent interface signals\nTable 188. Clock range\nSelection\nHCLK clock\nMDC clock\n000\n60-100 MHz\nAHB clock / 42\n001\n100-150 MHz\nAHB clock / 62\n010\n20-35 MHz\nAHB clock / 16\n011\n35-60 MHz\nAHB clock / 26\n100\n150-180 MHz\nAHB clock / 102\n 101, 110, 111\nReserved\n-\nMDC\nMDIO\n32 1's\n0\n1\n1\n0\nA4\nA3\nA2\nA1 A0\nR4\nR3\nR2\nR1\nR0\nD15 D14\nD1\nD0\nPreamble\nStart\nof\nframe\nOP\ncode\nPHY address\nRegister address\nTurn\naround\ndata\nData to PHY\nai15627\nData from PHY\nMDC \nMDIO \nRX_DV \nCRS \nCOL \nTX_EN \nRX_CLK \nRXD[3:0] \nRX_ER \nTX _CLK \nTXD[3:0]\n \nExternal\n PHY\nai15622c\n802.3 MAC\nSTM32 MCU \n" }, { "page_number": 1133, "page_indices": { "start_index": 2199253, "end_index": 2202499 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1133 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.4 Ethernet functional description: SMI, MII and RMII", 1129 ], [ 3, "33.4.2 Media-independent interface: MII", 1132 ] ], "page_content": "RM0090 Rev 21\n1133/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n•\nMII_TX_CLK: continuous clock that provides the timing reference for the TX data \ntransfer. The nominal frequency is: 2.5 MHz at 10 Mbit/s speed; 25 MHz at 100 Mbit/s \nspeed.\n•\nMII_RX_CLK: continuous clock that provides the timing reference for the RX data \ntransfer. The nominal frequency is: 2.5 MHz at 10 Mbit/s speed; 25 MHz at 100 Mbit/s \nspeed.\n•\nMII_TX_EN: transmission enable indicates that the MAC is presenting nibbles on the \nMII for transmission. It must be asserted synchronously (MII_TX_CLK) with the first \nnibble of the preamble and must remain asserted while all nibbles to be transmitted are \npresented to the MII.\n•\nMII_TXD[3:0]: transmit data is a bundle of 4 data signals driven synchronously by the \nMAC sublayer and qualified (valid data) on the assertion of the MII_TX_EN signal. \nMII_TXD[0] is the least significant bit, MII_TXD[3] is the most significant bit. While \nMII_TX_EN is deasserted the transmit data must have no effect upon the PHY.\n•\nMII_CRS: carrier sense is asserted by the PHY when either the transmit or receive \nmedium is non idle. It shall be deasserted by the PHY when both the transmit and \nreceive media are idle. The PHY must ensure that the MII_CS signal remains asserted \nthroughout the duration of a collision condition. This signal is not required to transition \nsynchronously with respect to the TX and RX clocks. In full duplex mode the state of \nthis signal is don’t care for the MAC sublayer.\n•\nMII_COL: collision detection must be asserted by the PHY upon detection of a collision \non the medium and must remain asserted while the collision condition persists. This \nsignal is not required to transition synchronously with respect to the TX and RX clocks. \nIn full duplex mode the state of this signal is don’t care for the MAC sublayer.\n•\nMII_RXD[3:0]: reception data is a bundle of 4 data signals driven synchronously by the \nPHY and qualified (valid data) on the assertion of the MII_RX_DV signal. MII_RXD[0] is \nthe least significant bit, MII_RXD[3] is the most significant bit. While MII_RX_EN is \ndeasserted and MII_RX_ER is asserted, a specific MII_RXD[3:0] value is used to \ntransfer specific information from the PHY (see Table 190).\n•\nMII_RX_DV: receive data valid indicates that the PHY is presenting recovered and \ndecoded nibbles on the MII for reception. It must be asserted synchronously \n(MII_RX_CLK) with the first recovered nibble of the frame and must remain asserted \nthrough the final recovered nibble. It must be deasserted prior to the first clock cycle \nthat follows the final nibble. In order to receive the frame correctly, the MII_RX_DV \nsignal must encompass the frame, starting no later than the SFD field.\n•\nMII_RX_ER: receive error must be asserted for one or more clock periods \n(MII_RX_CLK) to indicate to the MAC sublayer that an error was detected somewhere \nin the frame. This error condition must be qualified by MII_RX_DV assertion as \ndescribed in Table 190.\n \nTable 189. TX interface signal encoding\nMII_TX_EN\nMII_TXD[3:0]\nDescription\n0\n0000 through 1111\nNormal inter-frame\n1\n0000 through 1111\nNormal data transmission\n" }, { "page_number": 1134, "page_indices": { "start_index": 2202499, "end_index": 2203939 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1134 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.4 Ethernet functional description: SMI, MII and RMII", 1129 ], [ 3, "33.4.2 Media-independent interface: MII", 1132 ], [ 4, "MII clock sources", 1134 ], [ 3, "33.4.3 Reduced media-independent interface: RMII", 1134 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1134/1757\nRM0090 Rev 21\n \nMII clock sources\nTo generate both TX_CLK and RX_CLK clock signals, the external PHY must be clocked \nwith an external 25 MHz as shown in Figure 355. Instead of using an external 25 MHz \nquartz to provide this clock, the STM32F4xxmicrocontroller can output this signal on its \nMCO pin. In this case, the PLL multiplier has to be configured so as to get the desired \nfrequency on the MCO pin, from the 25 MHz external quartz.\nFigure 355. MII clock sources\n33.4.3 \nReduced media-independent interface: RMII\nThe reduced media-independent interface (RMII) specification reduces the pin count \nbetween the microcontroller Ethernet peripheral and the external Ethernet in 10/100 Mbit/s. \nAccording to the IEEE 802.3u standard, an MII contains 16 pins for data and control. The \nRMII specification is dedicated to reduce the pin count to 7 pins (a 62.5% decrease in pin \ncount).\nTable 190. RX interface signal encoding\nMII_RX_DV\nMII_RX_ERR\nMII_RXD[3:0]\nDescription\n0\n0\n0000 through 1111\nNormal inter-frame\n0\n1\n0000 \nNormal inter-frame\n0\n1\n0001 through 1101\nReserved\n0\n1\n1110\nFalse carrier indication\n0\n1\n1111\nReserved\n1\n0\n0000 through 1111\nNormal data reception\n1\n1\n0000 through 1111\nData reception with errors\nSTM32 \nMCU \n \nMCO \n25 MHz \n25 MHz \nTX _CLK \nFor 10/100 Mbit/s\nRX _CLK\nHSE\n802.3 MAC\nai15623b\nExternal\n PHY\n" }, { "page_number": 1135, "page_indices": { "start_index": 2203939, "end_index": 2205190 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1135 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.4 Ethernet functional description: SMI, MII and RMII", 1129 ], [ 3, "33.4.3 Reduced media-independent interface: RMII", 1134 ], [ 4, "RMII clock sources", 1135 ], [ 3, "33.4.4 MII/RMII selection", 1135 ] ], "page_content": "RM0090 Rev 21\n1135/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nThe RMII is instantiated between the MAC and the PHY. This helps translation of the MAC’s \nMII into the RMII. The RMII block has the following characteristics:\n•\nIt supports 10-Mbit/s and 100-Mbit/s operating rates\n•\nThe clock reference must be doubled to 50 MHz\n•\nThe same clock reference must be sourced externally to both MAC and external \nEthernet PHY\n•\nIt provides independent 2-bit wide (dibit) transmit and receive data paths\nFigure 356. Reduced media-independent interface signals\nRMII clock sources\nEither clock the PHY from an external 50 MHz clock or use a PHY with an embedded PLL to \ngenerate the 50 MHz frequency. \nFigure 357. RMII clock sources\n33.4.4 \nMII/RMII selection\nThe mode, MII or RMII, is selected using the configuration bit 23, MII_RMII_SEL, in the \nSYSCFG_PMC register. The application has to set the MII/RMII mode while the Ethernet \ncontroller is under reset or before enabling the clocks.\nSTM32 \nMCU \nTXD[1:0] \nTX_EN \nRXD[1:0] \nCRS_DV \nMDC \nMDIO \nREF_ CLK\nClock source\n802.3 MAC\nExternal\n PHY\nai15624b\nMS19930V1\nSTM32 \nMCU \nREF_CLK\n50 MHz \n25 MHz\n \nPLL \nFor 10/100 Mbit/s\nExternal\n PHY\n802.3 MAC\n" }, { "page_number": 1136, "page_indices": { "start_index": 2205190, "end_index": 2207203 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1136 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.4 Ethernet functional description: SMI, MII and RMII", 1129 ], [ 3, "33.4.4 MII/RMII selection", 1135 ], [ 4, "MII/RMII internal clock scheme", 1136 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1136/1757\nRM0090 Rev 21\nMII/RMII internal clock scheme\nThe clock scheme required to support both the MII and RMII, as well as 10 and 100 Mbit/s \noperations is described in Figure 358.\nFigure 358. Clock scheme\n1.\nThe MII/RMII selection is controlled through bit 23, MII_RMII_SEL, in the SYSCFG_PMC register.\nTo save a pin, the two input clock signals, RMII_REF_CK and MII_RX_CLK, are multiplexed \non the same GPIO pin.\n33.5 \nEthernet functional description: MAC 802.3\nThe IEEE 802.3 International Standard for local area networks (LANs) employs the \nCSMA/CD (carrier sense multiple access with collision detection) as the access method.\nThe Ethernet peripheral consists of a MAC 802.3 (media access control) controller with \nmedia independent interface (MII) and a dedicated DMA controller.\nThe MAC block implements the LAN CSMA/CD sublayer for the following families of \nsystems: 10 Mbit/s and 100 Mbit/s of data rates for baseband and broadband systems. Half- \nand full-duplex operation modes are supported. The collision detection access method is \napplied only to the half-duplex operation mode. The MAC control frame sublayer is \nsupported.\nThe MAC sublayer performs the following functions associated with a data link control \nprocedure:\n•\nData encapsulation (transmit and receive)\n–\nFraming (frame boundary delimitation, frame synchronization)\n–\nAddressing (handling of source and destination addresses)\n–\nError detection\n•\nMedia access management\n–\nMedium allocation (collision avoidance)\n–\nContention resolution (collision handling)\nGPIO and AF\ncontroller\nGPIO and AF\ncontroller\nMII_TX_CLK as AF\n(25 MHz or 2.5 MHz)\nMII_RX_CLK as AF\n(25 MHz or 2.5 MHz)\nSync. divider\n/2 for 100 Mb/s\n/20 for 10 Mb/s\n50 MHz\n0\n1\n0\n1\n25 MHz or 2.5 MHz\n25 MHz or 2.5 MHz\n0 MII\n1 RMII(1)\n25 MHz\nor 2.5 MHz\n25 MHz\nor 2.5 MHz\nMACTXCLK\nMACRXCLK\nTX\nRX\nAHB\nHCLK\nHCLK\nMAC\nmust be greater\nthan 25 MHz\nai15650\nRMII\nRMII_REF_CK as AF\n(50 MHz)\n" }, { "page_number": 1137, "page_indices": { "start_index": 2207203, "end_index": 2209965 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1137 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.1 MAC 802.3 frame format", 1137 ] ], "page_content": "RM0090 Rev 21\n1137/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nBasically there are two operating modes of the MAC sublayer:\n•\nHalf-duplex mode: the stations contend for the use of the physical medium, using the \nCSMA/CD algorithms.\n•\nFull duplex mode: simultaneous transmission and reception without contention \nresolution (CSMA/CD algorithm are unnecessary) when all the following conditions are \nmet:\n–\nphysical medium capability to support simultaneous transmission and reception\n–\nexactly 2 stations connected to the LAN\n–\nboth stations configured for full-duplex operation\n33.5.1 \nMAC 802.3 frame format\nThe MAC block implements the MAC sublayer and the optional MAC control sublayer \n(10/100 Mbit/s) as specified by the IEEE 802.3-2002 standard.\nTwo frame formats are specified for data communication systems using the CSMA/CD \nMAC:\n•\nBasic MAC frame format\n•\nTagged MAC frame format (extension of the basic MAC frame format)\nFigure 360 and Figure 361 describe the frame structure (untagged and tagged) that \nincludes the following fields:\n•\nPreamble: 7-byte field used for synchronization purposes (PLS circuitry)\nHexadecimal value: 55-55-55-55-55-55-55\nBit pattern: 01010101 01010101 01010101 01010101 01010101 01010101 01010101 \n(right-to-left bit transmission)\n•\nStart frame delimiter (SFD): 1-byte field used to indicate the start of a frame. \nHexadecimal value: D5\nBit pattern: 11010101 (right-to-left bit transmission)\n•\nDestination and Source Address fields: 6-byte fields to indicate the destination and \nsource station addresses as follows (see Figure 359):\n–\nEach address is 48 bits in length\n–\nThe first LSB bit (I/G) in the destination address field is used to indicate an \nindividual (I/G = 0) or a group address (I/G = 1). A group address could identify \nnone, one or more, or all the stations connected to the LAN. In the source address \nthe first bit is reserved and reset to 0.\n–\nThe second bit (U/L) distinguishes between locally (U/L = 1) or globally (U/L = 0) \nadministered addresses. For broadcast addresses this bit is also 1.\n–\nEach byte of each address field must be transmitted least significant bit first.\nThe address designation is based on the following types:\n•\nIndividual address: this is the physical address associated with a particular station on \nthe network.\n•\nGroup address. A multidestination address associated with one or more stations on a \ngiven network. There are two kinds of multicast address:\n–\nMulticast-group address: an address associated with a group of logically related \nstations.\n–\nBroadcast address: a distinguished, predefined multicast address (all 1’s in the \ndestination address field) that always denotes all the stations on a given LAN.\n" }, { "page_number": 1138, "page_indices": { "start_index": 2209965, "end_index": 2213196 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1138 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.1 MAC 802.3 frame format", 1137 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1138/1757\nRM0090 Rev 21\nFigure 359. Address field format\n•\nQTag Prefix: 4-byte field inserted between the Source address field and the MAC Client \nLength/Type field. This field is an extension of the basic frame (untagged) to obtain the \ntagged MAC frame. The untagged MAC frames do not include this field. The \nextensions for tagging are as follows:\n–\n2-byte constant Length/Type field value consistent with the Type interpretation \n(greater than 0x0600) equal to the value of the 802.1Q Tag Protocol Type (0x8100 \nhexadecimal). This constant field is used to distinguish tagged and untagged MAC \nframes.\n–\n2-byte field containing the Tag control information field subdivided as follows: a 3-\nbit user priority, a canonical format indicator (CFI) bit and a 12-bit VLAN Identifier. \nThe length of the tagged MAC frame is extended by 4 bytes by the QTag Prefix.\n•\nMAC client length/type: 2-byte field with different meaning (mutually exclusive), \ndepending on its value:\n–\nIf the value is less than or equal to maxValidFrame (0d1500) then this field \nindicates the number of MAC client data bytes contained in the subsequent data \nfield of the 802.3 frame (length interpretation).\n–\nIf the value is greater than or equal to MinTypeValue (0d1536 decimal, 0x0600) \nthen this field indicates the nature of the MAC client protocol (Type interpretation) \nrelated to the Ethernet frame.\nRegardless of the interpretation of the length/type field, if the length of the data field is \nless than the minimum required for proper operation of the protocol, a PAD field is \nadded after the data field but prior to the FCS (frame check sequence) field. The \nlength/type field is transmitted and received with the higher-order byte first.\nFor length/type field values in the range between maxValidLength and minTypeValue \n(boundaries excluded), the behavior of the MAC sublayer is not specified: they may or \nmay not be passed by the MAC sublayer.\n•\nData and PAD fields: n-byte data field. Full data transparency is provided, it means that \nany arbitrary sequence of byte values may appear in the data field. The size of the \nPAD, if any, is determined by the size of the data field. Max and min length of the data \nand PAD field are:\n–\nMaximum length = 1500 bytes\n–\nMinimum length for untagged MAC frames = 46 bytes\n–\nMinimum length for tagged MAC frames = 42 bytes\nWhen the data field length is less than the minimum required, the PAD field is added to \nmatch the minimum length (42 bytes for tagged frames, 46 bytes for untagged frames).\n•\nFrame check sequence: 4-byte field that contains the cyclic redundancy check (CRC) \nvalue. The CRC computation is based on the following fields: source address, \ndestination address, QTag prefix, length/type, LLC data and PAD (that is, all fields \nexcept the preamble, SFD). The generating polynomial is the following:\nMSB\nLSB\nBit transmission order (right to left)\nU/L I/G\n46-bit address\nI/G = 0 Individual address\nI/G = 1 Group address\nU/L = 0 Globally administered address\nU/L = 1 Locally administered address \nai15628\nG x\n( )\nx32\nx26\nx23\nx22\nx16\nx12\nx11\nx10\nx8\nx7\nx5\nx4\nx2\nx\n1\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n=\n" }, { "page_number": 1139, "page_indices": { "start_index": 2213196, "end_index": 2214296 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1139 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.1 MAC 802.3 frame format", 1137 ] ], "page_content": "RM0090 Rev 21\n1139/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nThe CRC value of a frame is computed as follows:\n•\nThe first 2 bits of the frame are complemented\n•\nThe n-bits of the frame are the coefficients of a polynomial M(x) of degree (n – 1). The \nfirst bit of the destination address corresponds to the xn – 1 term and the last bit of the \ndata field corresponds to the x0 term\n•\nM(x) is multiplied by x32 and divided by G(x), producing a remainder R(x) of degree \n≤31\n•\nThe coefficients of R(x) are considered as a 32-bit sequence\n•\nThe bit sequence is complemented and the result is the CRC\n•\nThe 32-bits of the CRC value are placed in the frame check sequence. The x32 term is \nthe first transmitted, the x0 term is the last one\nFigure 360. MAC frame format\nPreamble\nSFD\nDestination address\nSource address\nMAC client length/type\nMAC client data\nPAD\nFrame check sequence\n7 bytes\n1 byte\n6 bytes\n6 bytes\n2 bytes\n46-1500 bytes\n4 bytes\nMSB\nLSB\nBit transmission order (right to left)\nBytes within\n frame transmitted\ntop to bottom\nai15629\n" }, { "page_number": 1140, "page_indices": { "start_index": 2214296, "end_index": 2217147 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1140 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.2 MAC frame transmission", 1140 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1140/1757\nRM0090 Rev 21\nFigure 361. Tagged MAC frame format\nEach byte of the MAC frame, except the FCS field, is transmitted low-order bit first.\nAn invalid MAC frame is defined by one of the following conditions:\n•\nThe frame length is inconsistent with the expected value as specified by the length/type \nfield. If the length/type field contains a type value, then the frame length is assumed to \nbe consistent with this field (no invalid frame)\n•\nThe frame length is not an integer number of bytes (extra bits)\n•\nThe CRC value computed on the incoming frame does not match the included FCS\n33.5.2 \nMAC frame transmission\nThe DMA controls all transactions for the transmit path. Ethernet frames read from the \nsystem memory are pushed into the FIFO by the DMA. The frames are then popped out and \ntransferred to the MAC core. When the end-of-frame is transferred, the status of the \ntransmission is taken from the MAC core and transferred back to the DMA. The Transmit \nFIFO has a depth of 2 Kbyte. FIFO-fill level is indicated to the DMA so that it can initiate a \ndata fetch in required bursts from the system memory, using the AHB interface. The data \nfrom the AHB Master interface is pushed into the FIFO.\nWhen the SOF is detected, the MAC accepts the data and begins transmitting to the MII. \nThe time required to transmit the frame data to the MII after the application initiates \ntransmission is variable, depending on delay factors like IFG delay, time to transmit \npreamble/SFD, and any back-off delays for Half-duplex mode. After the EOF is transferred \nto the MAC core, the core completes normal transmission and then gives the status of \ntransmission back to the DMA. If a normal collision (in Half-duplex mode) occurs during \ntransmission, the MAC core makes the transmit status valid, then accepts and drops all \nfurther data until the next SOF is received. The same frame should be retransmitted from \nSOF on observing a Retry request (in the Status) from the MAC. The MAC issues an \nunderflow status if the data are not provided continuously during the transmission. During \nthe normal transfer of a frame, if the MAC receives an SOF without getting an EOF for the \nprevious frame, then the SOF is ignored and the new frame is considered as the \ncontinuation of the previous frame.\nPreamble\nSFD\n Destination address\nSource address\nLength/type = 802.1QTagType\n Tag control information\nMAC client length/type\nMAC client data\n7 bytes\n1 byte\n6 bytes\n6 bytes\nQTag Prefix\n42-1500 bytes\n2 bytes\nMSB\nLSB\nBit transmission order (right to left)\nbytes within\n frame transmitted\ntop to bottom\nFrame check sequence\nPad\n4 bytes\n4 bytes\n1 0 0 0 0 0 0 0 1\nVLAN identifier (VID, 12 bits)\nCFI\nUser priority\nMSB\nLSB\n0 0 0 0 0 0 0 0 0\nai15630\n" }, { "page_number": 1141, "page_indices": { "start_index": 2217147, "end_index": 2220386 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1141 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.2 MAC frame transmission", 1140 ], [ 4, "Automatic CRC and pad generation", 1141 ], [ 4, "Transmit protocol", 1141 ] ], "page_content": "RM0090 Rev 21\n1141/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nThere are two modes of operation for popping data towards the MAC core:\n•\nIn Threshold mode, as soon as the number of bytes in the FIFO crosses the configured \nthreshold level (or when the end-of-frame is written before the threshold is crossed), \nthe data is ready to be popped out and forwarded to the MAC core. The threshold level \nis configured using the TTC bits of ETH_DMABMR.\n•\nIn Store-and-forward mode, only after a complete frame is stored in the FIFO, the frame \nis popped towards the MAC core. If the Tx FIFO size is smaller than the Ethernet frame \nto be transmitted, then the frame is popped towards the MAC core when the Tx FIFO \nbecomes almost full.\nThe application can flush the Transmit FIFO of all contents by setting the FTF \n(ETH_DMAOMR register [20]) bit. This bit is self-clearing and initializes the FIFO pointers to \nthe default state. If the FTF bit is set during a frame transfer to the MAC core, then transfer \nis stopped as the FIFO is considered to be empty. Hence an underflow event occurs at the \nMAC transmitter and the corresponding Status word is forwarded to the DMA.\nAutomatic CRC and pad generation\nWhen the number of bytes received from the application falls below 60 (DA+SA+LT+Data), \nzeros are appended to the transmitting frame to make the data length exactly 46 bytes to \nmeet the minimum data field requirement of IEEE 802.3. The MAC can be programmed not \nto append any padding. The cyclic redundancy check (CRC) for the frame check sequence \n(FCS) field is calculated and appended to the data being transmitted. When the MAC is \nprogrammed to not append the CRC value to the end of Ethernet frames, the computed \nCRC is not transmitted. An exception to this rule is that when the MAC is programmed to \nappend pads for frames (DA+SA+LT+Data) less than 60 bytes, CRC is appended at the end \nof the padded frames.\nThe CRC generator calculates the 32-bit CRC for the FCS field of the Ethernet frame. The \nencoding is defined by the following polynomial.\nTransmit protocol\nThe MAC controls the operation of Ethernet frame transmission. It performs the following \nfunctions to meet the IEEE 802.3/802.3z specifications. It:\n•\ngenerates the preamble and SFD\n•\ngenerates the jam pattern in Half-duplex mode\n•\ncontrols the Jabber timeout\n•\ncontrols the flow for Half-duplex mode (back pressure)\n•\ngenerates the transmit frame status\n•\ncontains time stamp snapshot logic in accordance with IEEE 1588\nWhen a new frame transmission is requested, the MAC sends out the preamble and SFD, \nfollowed by the data. The preamble is defined as 7 bytes of 0b10101010 pattern, and the \nSFD is defined as 1 byte of 0b10101011 pattern. The collision window is defined as 1 slot \ntime (512 bit times for 10/100 Mbit/s Ethernet). The jam pattern generation is applicable only \nto Half-duplex mode, not to Full-duplex mode.\nIn MII mode, if a collision occurs at any time from the beginning of the frame to the end of \nthe CRC field, the MAC sends a 32-bit jam pattern of 0x5555 5555 on the MII to inform all \nG x\n( )\nx32\nx26\nx23\nx22\nx16\nx12\nx11\nx10\nx8\nx7\nx5\nx4\nx2\nx\n1\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n=\n" }, { "page_number": 1142, "page_indices": { "start_index": 2220386, "end_index": 2224360 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1142 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.2 MAC frame transmission", 1140 ], [ 4, "Transmit scheduler", 1142 ], [ 4, "Transmit flow control", 1142 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1142/1757\nRM0090 Rev 21\nother stations that a collision has occurred. If the collision is seen during the preamble \ntransmission phase, the MAC completes the transmission of the preamble and SFD and \nthen sends the jam pattern.\nA jabber timer is maintained to cut off the transmission of Ethernet frames if more than 2048 \n(default) bytes have to be transferred. The MAC uses the deferral mechanism for flow \ncontrol (back pressure) in Half-duplex mode. When the application requests to stop \nreceiving frames, the MAC sends a JAM pattern of 32 bytes whenever it senses the \nreception of a frame, provided that transmit flow control is enabled. This results in a collision \nand the remote station backs off. The application requests flow control by setting the BPA bit \n(bit 0) in the ETH_MACFCR register. If the application requests a frame to be transmitted, \nthen it is scheduled and transmitted even when back pressure is activated. Note that if back \npressure is kept activated for a long time (and more than 16 consecutive collision events \noccur) then the remote stations abort their transmissions due to excessive collisions. If IEEE \n1588 time stamping is enabled for the transmit frame, this block takes a snapshot of the \nsystem time when the SFD is put onto the transmit MII bus.\nTransmit scheduler\nThe MAC is responsible for scheduling the frame transmission on the MII. It maintains the \ninterframe gap between two transmitted frames and follows the truncated binary exponential \nbackoff algorithm for Half-duplex mode. The MAC enables transmission after satisfying the \nIFG and backoff delays. It maintains an idle period of the configured interframe gap (IFG bits \nin the ETH_MACCR register) between any two transmitted frames. If frames to be \ntransmitted arrive sooner than the configured IFG time, the MII waits for the enable signal \nfrom the MAC before starting the transmission on it. The MAC starts its IFG counter as soon \nas the carrier signal of the MII goes inactive. At the end of the programmed IFG value, the \nMAC enables transmission in Full-duplex mode. In Half-duplex mode and when IFG is \nconfigured for 96 bit times, the MAC follows the rule of deference specified in Section \n4.2.3.2.1 of the IEEE 802.3 specification. The MAC resets its IFG counter if a carrier is \ndetected during the first two-thirds (64-bit times for all IFG values) of the IFG interval. If the \ncarrier is detected during the final one third of the IFG interval, the MAC continues the IFG \ncount and enables the transmitter after the IFG interval. The MAC implements the truncated \nbinary exponential backoff algorithm when it operates in Half-duplex mode.\nTransmit flow control\nWhen the Transmit Flow Control Enable bit (TFE bit in ETH_MACFCR) is set, the MAC \ngenerates Pause frames and transmits them as necessary, in Full-duplex mode. The Pause \nframe is appended with the calculated CRC, and is sent. Pause frame generation can be \ninitiated in two ways.\nA pause frame is sent either when the application sets the FCB bit in the ETH_MACFCR \nregister or when the receive FIFO is full (packet buffer).\n•\nIf the application has requested flow control by setting the FCB bit in ETH_MACFCR, \nthe MAC generates and transmits a single Pause frame. The value of the pause time in \nthe generated frame contains the programmed pause time value in ETH_MACFCR. To \nextend the pause or end the pause prior to the time specified in the previously \ntransmitted Pause frame, the application must request another Pause frame \ntransmission after programming the Pause Time value (PT in ETH_MACFCR register) \nwith the appropriate value.\n•\nIf the application has requested flow control when the receive FIFO is full, the MAC \ngenerates and transmits a Pause frame. The value of the pause time in the generated \nframe is the programmed pause time value in ETH_MACFCR. If the receive FIFO \n" }, { "page_number": 1143, "page_indices": { "start_index": 2224360, "end_index": 2228262 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1143 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.2 MAC frame transmission", 1140 ], [ 4, "Retransmission during collision", 1143 ], [ 4, "Transmit FIFO flush operation", 1143 ] ], "page_content": "RM0090 Rev 21\n1143/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nremains full at a configurable number of slot-times (PLT bits in ETH_MACFCR) before \nthis Pause time runs out, a second Pause frame is transmitted. The process is \nrepeated as long as the receive FIFO remains full. If this condition is no more satisfied \nprior to the sampling time, the MAC transmits a Pause frame with zero pause time to \nindicate to the remote end that the receive buffer is ready to receive new data frames.\nSingle-packet transmit operation\nThe general sequence of events for a transmit operation is as follows:\n1.\nIf the system has data to be transferred, the DMA controller fetches them from the \nmemory through the AHB Master interface and starts forwarding them to the FIFO. It \ncontinues to receive the data until the end of frame is transferred.\n2. \nWhen the threshold level is crossed or a full packet of data is received into the FIFO, \nthe frame data are popped and driven to the MAC core. The DMA continues to transfer \ndata from the FIFO until a complete packet has been transferred to the MAC. Upon \ncompletion of the frame, the DMA controller is notified by the status coming from the \nMAC.\nTransmit operation—Two packets in the buffer\n1.\nBecause the DMA must update the descriptor status before releasing it to the Host, \nthere can be at the most two frames inside a transmit FIFO. The second frame is \nfetched by the DMA and put into the FIFO only if the OSF (operate on second frame) \nbit is set. If this bit is not set, the next frame is fetched from the memory only after the \nMAC has completely processed the frame and the DMA has released the descriptors.\n2. \nIf the OSF bit is set, the DMA starts fetching the second frame immediately after \ncompleting the transfer of the first frame to the FIFO. It does not wait for the status to \nbe updated. In the meantime, the second frame is received into the FIFO while the first \nframe is being transmitted. As soon as the first frame has been transferred and the \nstatus is received from the MAC, it is pushed to the DMA. If the DMA has already \ncompleted sending the second packet to the FIFO, the second transmission must wait \nfor the status of the first packet before proceeding to the next frame.\nRetransmission during collision\nWhile a frame is being transferred to the MAC, a collision event may occur on the MAC line \ninterface in Half-duplex mode. The MAC would then indicate a retry attempt by giving the \nstatus even before the end of frame is received. Then the retransmission is enabled and the \nframe is popped out again from the FIFO. After more than 96 bytes have been popped \ntowards the MAC core, the FIFO controller frees up that space and makes it available to the \nDMA to push in more data. This means that the retransmission is not possible after this \nthreshold is crossed or when the MAC core indicates a late collision event.\nTransmit FIFO flush operation\nThe MAC provides a control to the software to flush the Transmit FIFO through the use of Bit \n20 in the Operation mode register. The Flush operation is immediate and the Tx FIFO and \nthe corresponding pointers are cleared to the initial state even if the Tx FIFO is in the middle \nof transferring a frame to the MAC Core. This results in an underflow event in the MAC \ntransmitter, and the frame transmission is aborted. The status of such a frame is marked \nwith both underflow and frame flush events (TDES0 bits 13 and 1). No data are coming to \nthe FIFO from the application (DMA) during the Flush operation. Transfer transmit status \nwords are transferred to the application for the number of frames that is flushed (including \npartial frames). Frames that are completely flushed have the Frame flush status bit (TDES0 \n13) set. The Flush operation is completed when the application (DMA) has accepted all of \n" }, { "page_number": 1144, "page_indices": { "start_index": 2228262, "end_index": 2231678 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1144 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.2 MAC frame transmission", 1140 ], [ 4, "Transmit status word", 1144 ], [ 4, "Transmit checksum offload", 1144 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1144/1757\nRM0090 Rev 21\nthe Status words for the frames that were flushed. The Transmit FIFO Flush control register \nbit is then cleared. At this point, new frames from the application (DMA) are accepted. All \ndata presented for transmission after a Flush operation are discarded unless they start with \nan SOF marker.\nTransmit status word\nAt the end of the Ethernet frame transfer to the MAC core and after the core has completed \nthe transmission of the frame, the transmit status is given to the application. The detailed \ndescription of the Transmit Status is the same as for bits [23:0] in TDES0. If IEEE 1588 time \nstamping is enabled, a specific frames’ 64-bit time stamp is returned, along with the transmit \nstatus.\nTransmit checksum offload\nCommunication protocols such as TCP and UDP implement checksum fields, which helps \ndetermine the integrity of data transmitted over a network. Because the most widespread \nuse of Ethernet is to encapsulate TCP and UDP over IP datagrams, the Ethernet controller \nhas a transmit checksum offload feature that supports checksum calculation and insertion in \nthe transmit path, and error detection in the receive path. This section explains the operation \nof the checksum offload feature for transmitted frames.\nNote:\nThe checksum for TCP, UDP or ICMP is calculated over a complete frame, then inserted \ninto its corresponding header field. Due to this requirement, this function is enabled only \nwhen the Transmit FIFO is configured for Store-and-forward mode (that is, when the TSF bit \nis set in the ETH_ETH_DMAOMR register). If the core is configured for Threshold (cut-\nthrough) mode, the Transmit checksum offload is bypassed.\nYou must make sure the Transmit FIFO is deep enough to store a complete frame before \nthat frame is transferred to the MAC Core transmitter. If the FIFO depth is less than the input \nEthernet frame size, the payload (TCP/UDP/ICMP) checksum insertion function is bypassed \nand only the frame’s IPv4 Header checksum is modified, even in Store-and-forward mode.\nThe transmit checksum offload supports two types of checksum calculation and insertion. \nThis checksum can be controlled for each frame by setting the CIC bits (Bits 27:23 in \nTDES0, described in TDES0: Transmit descriptor Word0).\nSee IETF specifications RFC 791, RFC 793, RFC 768, RFC 792, RFC 2460 and RFC 4443 \nfor IPv4, TCP, UDP, ICMP, IPv6 and ICMPv6 packet header specifications, respectively.\n•\nIP header checksum\nIn IPv4 datagrams, the integrity of the header fields is indicated by the 16-bit header \nchecksum field (the eleventh and twelfth bytes of the IPv4 datagram). The checksum \noffload detects an IPv4 datagram when the Ethernet frame’s Type field has the value \n0x0800 and the IP datagram’s Version field has the value 0x4. The input frame’s \nchecksum field is ignored during calculation and replaced by the calculated value. IPv6 \nheaders do not have a checksum field; thus, the checksum offload does not modify \nIPv6 header fields. The result of this IP header checksum calculation is indicated by the \nIP Header Error status bit in the Transmit status (Bit 16). This status bit is set whenever \nthe values of the Ethernet Type field and the IP header’s Version field are not \nconsistent, or when the Ethernet frame does not have enough data, as indicated by the \n" }, { "page_number": 1145, "page_indices": { "start_index": 2231678, "end_index": 2234743 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1145 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.2 MAC frame transmission", 1140 ], [ 4, "Transmit checksum offload", 1144 ] ], "page_content": "RM0090 Rev 21\n1145/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nIP header Length field. In other words, this bit is set when an IP header error is \nasserted under the following circumstances:\na) \nFor IPv4 datagrams:\n–\nThe received Ethernet type is 0x0800, but the IP header’s Version field does not \nequal 0x4\n–\nThe IPv4 Header Length field indicates a value less than 0x5 (20 bytes)\n–\nThe total frame length is less than the value given in the IPv4 Header Length field\nb) \nFor IPv6 datagrams:\n–\nThe Ethernet type is 0x86DD but the IP header Version field does not equal 0x6 \n–\nThe frame ends before the IPv6 header (40 bytes) or extension header (as given \nin the corresponding Header Length field in an extension header) has been \ncompletely received. Even when the checksum offload detects such an IP header \nerror, it inserts an IPv4 header checksum if the Ethernet Type field indicates an \nIPv4 payload.\n•\nTCP/UDP/ICMP checksum\nThe TCP/UDP/ICMP checksum processes the IPv4 or IPv6 header (including \nextension headers) and determines whether the encapsulated payload is TCP, UDP or \nICMP.\nNote that:\na) \nFor non-TCP, -UDP, or -ICMP/ICMPv6 payloads, this checksum is bypassed and \nnothing further is modified in the frame.\nb) \nFragmented IP frames (IPv4 or IPv6), IP frames with security features (such as an \nauthentication header or encapsulated security payload), and IPv6 frames with \nrouting headers are bypassed and not processed by the checksum.\nThe checksum is calculated for the TCP, UDP, or ICMP payload and inserted into its \ncorresponding field in the header. It can work in the following two modes:\n–\nIn the first mode, the TCP, UDP, or ICMPv6 pseudo-header is not included in the \nchecksum calculation and is assumed to be present in the input frame’s checksum \nfield. The checksum field is included in the checksum calculation, and then \nreplaced by the final calculated checksum.\n–\nIn the second mode, the checksum field is ignored, the TCP, UDP, or ICMPv6 \npseudo-header data are included into the checksum calculation, and the \nchecksum field is overwritten with the final calculated value.\nNote that: for ICMP-over-IPv4 packets, the checksum field in the ICMP packet must \nalways be 0x0000 in both modes, because pseudo-headers are not defined for such \npackets. If it does not equal 0x0000, an incorrect checksum may be inserted into the \npacket.\nThe result of this operation is indicated by the payload checksum error status bit in the \nTransmit Status vector (bit 12). The payload checksum error status bit is set when \neither of the following is detected:\n–\nthe frame has been forwarded to the MAC transmitter in Store-and-forward mode \nwithout the end of frame being written to the FIFO\n–\nthe packet ends before the number of bytes indicated by the payload length field in \nthe IP header is received.\nWhen the packet is longer than the indicated payload length, the bytes are ignored as \nstuff bytes, and no error is reported. When the first type of error is detected, the TCP, \n" }, { "page_number": 1146, "page_indices": { "start_index": 2234743, "end_index": 2235537 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1146 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.2 MAC frame transmission", 1140 ], [ 4, "MII/RMII transmit bit order", 1146 ], [ 4, "MII/RMII transmit timing diagrams", 1146 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1146/1757\nRM0090 Rev 21\nUDP or ICMP header is not modified. For the second error type, still, the calculated \nchecksum is inserted into the corresponding header field.\nMII/RMII transmit bit order\nEach nibble from the MII is transmitted on the RMII a dibit at a time with the order of dibit \ntransmission shown in Figure 362. Lower order bits (D1 and D0) are transmitted first \nfollowed by higher order bits (D2 and D3).\nFigure 362. Transmission bit order\nMII/RMII transmit timing diagrams\nFigure 363. Transmission with no collision\nD0\nD1\nD2\nD3\nLSB\nMII_TXD[3:0]\nMSB\nD0\nD1\nLSB\nMSB\nRMII_TXD[1:0]\nBibit stream\nNibble stream\nai15632\nMII_TX_CLK\nMII_TX_EN\nMII_TXD[3:0]\nPR\nEA\nMB\nLE\nMII_CS\nMII_COL\nai15631\nLow\n" }, { "page_number": 1147, "page_indices": { "start_index": 2235537, "end_index": 2236647 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1147 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.3 MAC frame reception", 1147 ] ], "page_content": "RM0090 Rev 21\n1147/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nFigure 364. Transmission with collision\nFigure 365 shows a frame transmission in MII and RMII.\nFigure 365. Frame transmission in MMI and RMII modes\n33.5.3 \nMAC frame reception\nThe MAC received frames are pushes into the Rx FIFO. The status (fill level) of this FIFO is \nindicated to the DMA once it crosses the configured receive threshold (RTC in the \nETH_DMAOMR register) so that the DMA can initiate pre-configured burst transfers \ntowards the AHB interface.\nIn the default Cut-through mode, when 64 bytes (configured with the RTC bits in the \nETH_DMAOMR register) or a full packet of data are received into the FIFO, the data are \npopped out and the DMA is notified of its availability. Once the DMA has initiated the \ntransfer to the AHB interface, the data transfer continues from the FIFO until a complete \nMII_TX_CLK\nMII_TX_EN\nMII_TXD[3:0]\nPR\nEAM\nBLE\nSFD\nMII_CS\nMII_COL\nai15651\nDA\nDA\nJAM\nJAM\nJAM\nJAM\nMII_RX_CLK\nMII_TX_EN\nMII_TXD[3:0]\nRMII_REF_CLK\nRMII_TXD[1:0]\nRMII_TX_EN\nai15652\n" }, { "page_number": 1148, "page_indices": { "start_index": 2236647, "end_index": 2240163 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1148 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.3 MAC frame reception", 1147 ], [ 4, "Receive protocol", 1148 ], [ 4, "Receive CRC: automatic CRC and pad stripping", 1148 ], [ 4, "Receive checksum offload", 1148 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1148/1757\nRM0090 Rev 21\npacket has been transferred. Upon completion of the EOF frame transfer, the status word is \npopped out and sent to the DMA controller.\nIn Rx FIFO Store-and-forward mode (configured by the RSF bit in the ETH_DMAOMR \nregister), a frame is read only after being written completely into the Receive FIFO. In this \nmode, all error frames are dropped (if the core is configured to do so) such that only valid \nframes are read and forwarded to the application. In Cut-through mode, some error frames \nare not dropped, because the error status is received at the end of the frame, by which time \nthe start of that frame has already been read of the FIFO.\nA receive operation is initiated when the MAC detects an SFD on the MII. The core strips the \npreamble and SFD before proceeding to process the frame. The header fields are checked \nfor the filtering and the FCS field used to verify the CRC for the frame. The frame is dropped \nin the core if it fails the address filter.\nReceive protocol\nThe received frame preamble and SFD are stripped. Once the SFD has been detected, the \nMAC starts sending the Ethernet frame data to the receive FIFO, beginning with the first \nbyte following the SFD (destination address). If IEEE 1588 time stamping is enabled, a \nsnapshot of the system time is taken when any frame's SFD is detected on the MII. Unless \nthe MAC filters out and drops the frame, this time stamp is passed on to the application.\nIf the received frame length/type field is less than 0x600 and if the MAC is programmed for \nthe auto CRC/pad stripping option, the MAC sends the data of the frame to RxFIFO up to \nthe count specified in the length/type field, then starts dropping bytes (including the FCS \nfield). If the Length/Type field is greater than or equal to 0x600, the MAC sends all received \nEthernet frame data to Rx FIFO, regardless of the value on the programmed auto-CRC strip \noption. The MAC watchdog timer is enabled by default, that is, frames above 2048 bytes \n(DA + SA + LT + Data + pad + FCS) are cut off. This feature can be disabled by \nprogramming the watchdog disable (WD) bit in the MAC configuration register. However, \neven if the watchdog timer is disabled, frames greater than 16 KB in size are cut off and a \nwatchdog timeout status is given.\nReceive CRC: automatic CRC and pad stripping\nThe MAC checks for any CRC error in the receiving frame. It calculates the 32-bit CRC for \nthe received frame that includes the Destination address field through the FCS field. The \nencoding is defined by the following polynomial.\nRegardless of the auto-pad/CRC strip, the MAC receives the entire frame to compute the \nCRC check for the received frame.\nReceive checksum offload\nBoth IPv4 and IPv6 frames in the received Ethernet frames are detected and processed for \ndata integrity. You can enable the receive checksum offload by setting the IPCO bit in the \nETH_MACCR register. The MAC receiver identifies IPv4 or IPv6 frames by checking for \nvalue 0x0800 or 0x86DD, respectively, in the received Ethernet frame Type field. This \nidentification applies to VLAN-tagged frames as well. The receive checksum offload \ncalculates IPv4 header checksums and checks that they match the received IPv4 header \nchecksums. The IP Header Error bit is set for any mismatch between the indicated payload \nG x\n( )\nx32\nx26\nx23\nx22\nx16\nx12\nx11\nx10\nx8\nx7\nx5\nx4\nx2\nx\n1\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n=\n" }, { "page_number": 1149, "page_indices": { "start_index": 2240163, "end_index": 2243127 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1149 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.3 MAC frame reception", 1147 ], [ 4, "Receive frame controller", 1149 ] ], "page_content": "RM0090 Rev 21\n1149/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\ntype (Ethernet Type field) and the IP header version, or when the received frame does not \nhave enough bytes, as indicated by the IPv4 header’s Length field (or when fewer than 20 \nbytes are available in an IPv4 or IPv6 header). The receive checksum offload also identifies \na TCP, UDP or ICMP payload in the received IP datagrams (IPv4 or IPv6) and calculates the \nchecksum of such payloads properly, as defined in the TCP, UDP or ICMP specifications. It \nincludes the TCP/UDP/ICMPv6 pseudo-header bytes for checksum calculation and checks \nwhether the received checksum field matches the calculated value. The result of this \noperation is given as a Payload Checksum Error bit in the receive status word. This status \nbit is also set if the length of the TCP, UDP or ICMP payload does not match the expected \npayload length given in the IP header. As mentioned in TCP/UDP/ICMP checksum, the \nreceive checksum offload bypasses the payload of fragmented IP datagrams, IP datagrams \nwith security features, IPv6 routing headers, and payloads other than TCP, UDP or ICMP. \nThis information (whether the checksum is bypassed or not) is given in the receive status, \nas described in the RDES0: Receive descriptor Word0 section. In this configuration, the \ncore does not append any payload checksum bytes to the received Ethernet frames.\nAs mentioned in RDES0: Receive descriptor Word0, the meaning of certain register bits \nchanges as shown in Table 191.\n \nReceive frame controller\nIf the RA bit is reset in the MAC CSR frame filter register, the MAC performs frame filtering \nbased on the destination/source address (the application still needs to perform another level \nof filtering if it decides not to receive any bad frames like runt, CRC error frames, etc.). On \ndetecting a filter-fail, the frame is dropped and not transferred to the application. When the \nfiltering parameters are changed dynamically, and in case of (DA-SA) filter-fail, the rest of \nthe frame is dropped and the Rx Status Word is immediately updated (with zero frame \nTable 191. Frame statuses\nBit 18: \nEthernet frame\nBit 27: Header \nchecksum error\n Bit 28: Payload \nchecksum error\nFrame status\n0\n0\n0\nThe frame is an IEEE 802.3 frame (Length \nfield value is less than 0x0600).\n1\n0\n0\nIPv4/IPv6 Type frame in which no checksum \nerror is detected.\n1\n0\n1\nIPv4/IPv6 Type frame in which a payload \nchecksum error (as described for PCE) is \ndetected\n1\n1\n0\nIPv4/IPv6 Type frame in which IP header \nchecksum error (as described for IPCO HCE) \nis detected.\n1\n1\n1\nIPv4/IPv6 Type frame in which both PCE and \nIPCO HCE are detected.\n0\n0\n1\nIPv4/IPv6 Type frame in which there is no IP \nHCE and the payload check is bypassed due \nto unsupported payload.\n0\n1\n1\nType frame which is neither IPv4 or IPv6 \n(checksum offload bypasses the checksum \ncheck completely)\n0\n1\n0\nReserved\n" }, { "page_number": 1150, "page_indices": { "start_index": 2243127, "end_index": 2246503 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1150 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.3 MAC frame reception", 1147 ], [ 4, "Receive flow control", 1150 ], [ 4, "Receive operation multiframe handling", 1150 ], [ 4, "Error handling", 1150 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1150/1757\nRM0090 Rev 21\nlength, CRC error and Runt Error bits set), indicating the filter fail. In Ethernet power down \nmode, all received frames are dropped, and are not forwarded to the application.\nReceive flow control\nThe MAC detects the receiving Pause frame and pauses the frame transmission for the \ndelay specified within the received Pause frame (only in Full-duplex mode). The Pause \nframe detection function can be enabled or disabled with the RFCE bit in ETH_MACFCR. \nOnce receive flow control has been enabled, the received frame destination address begins \nto be monitored for any match with the multicast address of the control frame \n(0x0180 C200 0001). If a match is detected (the destination address of the received frame \nmatches the reserved control frame destination address), the MAC then decides whether or \nnot to transfer the received control frame to the application, based on the level of the PCF \nbit in ETH_MACFFR.\nThe MAC also decodes the type, opcode, and Pause Timer fields of the receiving control \nframe. If the byte count of the status indicates 64 bytes, and if there is no CRC error, the \nMAC transmitter pauses the transmission of any data frame for the duration of the decoded \nPause time value, multiplied by the slot time (64 byte times for both 10/100 Mbit/s modes). \nMeanwhile, if another Pause frame is detected with a zero Pause time value, the MAC \nresets the Pause time and manages this new pause request.\nIf the received control frame matches neither the type field (0x8808), the opcode (0x00001), \nnor the byte length (64 bytes), or if there is a CRC error, the MAC does not generate a \nPause.\nIn the case of a pause frame with a multicast destination address, the MAC filters the frame \nbased on the address match.\nFor a pause frame with a unicast destination address, the MAC filtering depends on whether \nthe DA matched the contents of the MAC address 0 register and whether the UPDF bit in \nETH_MACFCR is set (detecting a pause frame even with a unicast destination address). \nThe PCF register bits (bits [7:6] in ETH_MACFFR) control filtering for control frames in \naddition to address filtering.\nReceive operation multiframe handling\nSince the status is available immediately following the data, the FIFO is capable of storing \nany number of frames into it, as long as it is not full.\nError handling\nIf the Rx FIFO is full before it receives the EOF data from the MAC, an overflow is declared \nand the whole frame is dropped, and the overflow counter in the (ETH_DMAMFBOCR \nregister) is incremented. The status indicates a partial frame due to overflow. The Rx FIFO \ncan filter error and undersized frames, if enabled (using the FEF and FUGF bits in \nETH_DMAOMR).\nIf the Receive FIFO is configured to operate in Store-and-forward mode, all error frames can \nbe filtered and dropped.\nIn Cut-through mode, if a frame's status and length are available when that frame's SOF is \nread from the Rx FIFO, then the complete erroneous frame can be dropped. The DMA can \nflush the error frame being read from the FIFO, by enabling the receive frame flash bit. The \ndata transfer to the application (DMA) is then stopped and the rest of the frame is internally \nread and dropped. The next frame transfer can then be started, if available.\n" }, { "page_number": 1151, "page_indices": { "start_index": 2246503, "end_index": 2247792 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1151 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.3 MAC frame reception", 1147 ], [ 4, "Receive status word", 1151 ], [ 4, "Frame length interface", 1151 ], [ 4, "MII/RMII receive bit order", 1151 ] ], "page_content": "RM0090 Rev 21\n1151/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nReceive status word\nAt the end of the Ethernet frame reception, the MAC outputs the receive status to the \napplication (DMA). The detailed description of the receive status is the same as for \nbits[31:0] in RDES0, given in RDES0: Receive descriptor Word0.\nFrame length interface\nIn case of switch applications, data transmission and reception between the application and \nMAC happen as complete frame transfers. The application layer should be aware of the \nlength of the frames received from the ingress port in order to transfer the frame to the \negress port. The MAC core provides the frame length of each received frame inside the \nstatus at the end of each frame reception.\nNote:\nA frame length value of 0 is given for partial frames written into the Rx FIFO due to overflow.\nMII/RMII receive bit order\nEach nibble is transmitted to the MII from the dibit received from the RMII in the nibble \ntransmission order shown in Figure 366. The lower-order bits (D0 and D1) are received first, \nfollowed by the higher-order bits (D2 and D3).\nFigure 366. Receive bit order\nD0\nD1\nD2\nD3\nLSB\nMII_RXD[3:0]\nMSB\nD0\nD1\nLSB\nMSB\nRMII_RXD[1:0]\nDi-bit stream\nNibble stream\nai15633\n" }, { "page_number": 1152, "page_indices": { "start_index": 2247792, "end_index": 2248582 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1152 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.4 MAC interrupts", 1152 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1152/1757\nRM0090 Rev 21\nFigure 367. Reception with no error\nFigure 368. Reception with errors\nFigure 369. Reception with false carrier indication\n33.5.4 \nMAC interrupts\nInterrupts can be generated from the MAC core as a result of various events.\nThe ETH_MACSR register describes the events that can cause an interrupt from the MAC \ncore. You can prevent each event from asserting the interrupt by setting the corresponding \nmask bits in the Interrupt Mask register.\nMII_RX_CLK\nMII_RX_DV\nMII_RXD[3:0]\nPREAMBLE\nSFD\nMII_RX_ERR\nai15634\nFCS\nMII_RX_CLK\nMII_RX_DV\nMII_RXD[3:0]\nPREAMBLE\nSFD\nMII_RX_ERR\nai15635\nDA\nDA\nXX\nXX\nXX\nMII_RX_CLK\nMII_RX_DV\nMII_RXD[3:0]\nXX\nMII_RX_ERR\nai15636\n0E\nXX\nXX\nXX\nXX\nXX\nXX\nXX\n" }, { "page_number": 1153, "page_indices": { "start_index": 2248582, "end_index": 2251132 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1153 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.5 MAC filtering", 1153 ], [ 4, "Address filtering", 1153 ], [ 4, "Unicast destination address filter", 1153 ] ], "page_content": "RM0090 Rev 21\n1153/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nThe interrupt register bits only indicate the block from which the event is reported. You have \nto read the corresponding status registers and other registers to clear the interrupt. For \nexample, bit 3 of the Interrupt register, set high, indicates that the Magic packet or Wake-on-\nLAN frame is received in Power-down mode. You must read the ETH_MACPMTCSR \nregister to clear this interrupt event.\nFigure 370. MAC core interrupt masking scheme\n33.5.5 \nMAC filtering\nAddress filtering\nAddress filtering checks the destination and source addresses on all received frames and \nthe address filtering status is reported accordingly. Address checking is based on different \nparameters (Frame filter register) chosen by the application. The filtered frame can also be \nidentified: multicast or broadcast frame.\nAddress filtering uses the station's physical (MAC) address and the Multicast Hash table for \naddress checking purposes.\nUnicast destination address filter\nThe MAC supports up to 4 MAC addresses for unicast perfect filtering. If perfect filtering is \nselected (HU bit in the Frame filter register is reset), the MAC compares all 48 bits of the \nreceived unicast address with the programmed MAC address for any match. Default \nMacAddr0 is always enabled, other addresses MacAddr1–MacAddr3 are selected with an \nindividual enable bit. Each byte of these other addresses (MacAddr1–MacAddr3) can be \nmasked during comparison with the corresponding received DA byte by setting the \ncorresponding Mask Byte Control bit in the register. This helps group address filtering for the \nDA. In Hash filtering mode (when HU bit is set), the MAC performs imperfect filtering for \nunicast addresses using a 64-bit Hash table. For hash filtering, the MAC uses the 6 upper \nCRC (see note 1 below) bits of the received destination address to index the content of the \nHash table. A value of 000000 selects bit 0 in the selected register, and a value of 111111 \nselects bit 63 in the Hash Table register. If the corresponding bit (indicated by the 6-bit CRC) \nis set to 1, the unicast frame is said to have passed the Hash filter; otherwise, the frame has \nfailed the Hash filter.\nNote:\nThis CRC is a 32-bit value coded by the following polynomial (for more details refer to \nSection 33.5.3):\nAND\nAND\nOR\nTSTI\nPMTI\nInterrupt\nTSTS\nPMTS\nPMTIM\nai15637\nTSTIM\nG x\n( )\nx32\nx26\nx23\nx22\nx16\nx12\nx11\nx10\nx8\nx7\nx5\nx4\nx2\nx\n1\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n=\n" }, { "page_number": 1154, "page_indices": { "start_index": 2251132, "end_index": 2254497 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1154 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.5 MAC filtering", 1153 ], [ 4, "Multicast destination address filter", 1154 ], [ 4, "Hash or perfect address filter", 1154 ], [ 4, "Broadcast address filter", 1154 ], [ 4, "Unicast source address filter", 1154 ], [ 4, "Inverse filtering operation", 1154 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1154/1757\nRM0090 Rev 21\nMulticast destination address filter\nThe MAC can be programmed to pass all multicast frames by setting the PAM bit in the \nFrame filter register. If the PAM bit is reset, the MAC performs the filtering for multicast \naddresses based on the HM bit in the Frame filter register. In Perfect filtering mode, the \nmulticast address is compared with the programmed MAC destination address registers \n(1–3). Group address filtering is also supported. In Hash filtering mode, the MAC performs \nimperfect filtering using a 64-bit Hash table. For hash filtering, the MAC uses the 6 upper \nCRC (see note 1 below) bits of the received multicast address to index the content of the \nHash table. A value of 000000 selects bit 0 in the selected register and a value of 111111 \nselects bit 63 in the Hash Table register. If the corresponding bit is set to 1, then the \nmulticast frame is said to have passed the Hash filter; otherwise, the frame has failed the \nHash filter.\nNote:\nThis CRC is a 32-bit value coded by the following polynomial (for more details refer to \nSection 33.5.3):\nHash or perfect address filter\nThe DA filter can be configured to pass a frame when its DA matches either the Hash filter \nor the Perfect filter by setting the HPF bit in the Frame filter register and setting the \ncorresponding HU or HM bits. This configuration applies to both unicast and multicast \nframes. If the HPF bit is reset, only one of the filters (Hash or Perfect) is applied to the \nreceived frame.\nBroadcast address filter\nThe MAC does not filter any broadcast frames in the default mode. However, if the MAC is \nprogrammed to reject all broadcast frames by setting the BFD bit in the Frame filter register, \nany broadcast frames are dropped.\nUnicast source address filter\nThe MAC can also perform perfect filtering based on the source address field of the \nreceived frames. By default, the MAC compares the SA field with the values programmed in \nthe SA registers. The MAC address registers [1:3] can be configured to contain SA instead \nof DA for comparison, by setting bit 30 in the corresponding register. Group filtering with SA \nis also supported. The frames that fail the SA filter are dropped by the MAC if the SAF bit in \nthe Frame filter register is set. Otherwise, the result of the SA filter is given as a status bit in \nthe Receive Status word (see RDES0: Receive descriptor Word0).\nWhen the SAF bit is set, the result of the SA and DA filters is AND’ed to decide whether the \nframe needs to be forwarded. This means that either of the filter fail result drops the frame. \nBoth filters have to pass the frame for the frame to be forwarded to the application.\nInverse filtering operation\nFor both destination and source address filtering, there is an option to invert the filter-match \nresult at the final output. These are controlled by the DAIF and SAIF bits in the Frame filter \nregister, respectively. The DAIF bit is applicable for both Unicast and Multicast DA frames. \nThe result of the unicast/multicast destination address filter is inverted in this mode. \nSimilarly, when the SAIF bit is set, the result of the unicast SA filter is inverted. Table 192 \nG x\n( )\nx32\nx26\nx23\nx22\nx16\nx12\nx11\nx10\nx8\nx7\nx5\nx4\nx2\nx\n1\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n=\n" }, { "page_number": 1155, "page_indices": { "start_index": 2254497, "end_index": 2255850 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1155 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.5 MAC filtering", 1153 ], [ 4, "Inverse filtering operation", 1154 ] ], "page_content": "RM0090 Rev 21\n1155/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nand Table 193 summarize destination and source address filtering based on the type of \nframe received.\n \nTable 192. Destination address filtering\nFrame \ntype\nPM\nHPF\nHU\nDAIF\nHM\nPAM\nDB\nDA filter operation\nBroadcast\n1\nX\nX\nX\nX\nX\nX\nPass\n0\nX\nX\nX\nX\nX\n0\nPass\n0\nX\nX\nX\nX\nX\n1\nFail\nUnicast\n1\nX\nX\nX\nX\nX\nX\nPass all frames\n0\nX\n0\n0\nX\nX\nX\nPass on perfect/group filter match\n0\nX\n0\n1\nX\nX\nX\nFail on perfect/Group filter match\n0\n0\n1\n0\nX\nX\nX\nPass on hash filter match\n0\n0\n1\n1\nX\nX\nX\nFail on hash filter match\n0\n1\n1\n0\nX\nX\nX\nPass on hash or perfect/Group filter \nmatch\n0\n1\n1\n1\nX\nX\nX\nFail on hash or perfect/Group filter match\nMulticast\n1\nX\nX\nX\nX\nX\nX\nPass all frames\nX\nX\nX\nX\nX\n1\nX\nPass all frames\n0\nX\nX\n0\n0\n0\nX\nPass on Perfect/Group filter match and \ndrop PAUSE control frames if PCF = 0x\n0\n0\nX\n0\n1\n0\nX\nPass on hash filter match and drop \nPAUSE control frames if PCF = 0x\n0\n1\nX\n0\n1\n0\nX\nPass on hash or perfect/Group filter \nmatch and drop PAUSE control frames if \nPCF = 0x\n0\nX\nX\n1\n0\n0\nX\nFail on perfect/Group filter match and \ndrop PAUSE control frames if PCF = 0x\n0\n0\nX\n1\n1\n0\nX\nFail on hash filter match and drop PAUSE \ncontrol frames if PCF = 0x\n0\n1\nX\n1\n1\n0\nX\nFail on hash or perfect/Group filter match \nand drop PAUSE control frames if PCF = \n0x\n" }, { "page_number": 1156, "page_indices": { "start_index": 2255850, "end_index": 2257881 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1156 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.6 MAC loopback mode", 1156 ], [ 3, "33.5.7 MAC management counters: MMC", 1156 ], [ 4, "Good transmitted and received frames", 1156 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1156/1757\nRM0090 Rev 21\n \n33.5.6 \nMAC loopback mode\nThe MAC supports loopback of transmitted frames onto its receiver. By default, the MAC \nloopback function is disabled, but this feature can be enabled by programming the \nLoopback bit in the MAC ETH_MACCR register.\n33.5.7 \nMAC management counters: MMC\nThe MAC management counters (MMC) maintain a set of registers for gathering statistics \non the received and transmitted frames. These include a control register for controlling the \nbehavior of the registers, two 32-bit registers containing generated interrupts (receive and \ntransmit), and two 32-bit registers containing masks for the Interrupt register (receive and \ntransmit). These registers are accessible from the application. Each register is 32 bits wide.\nSection 33.8 describes the various counters and lists the addresses of each of the statistics \ncounters. This address is used for read/write accesses to the desired transmit/receive \ncounter.\nThe Receive MMC counters are updated for frames that pass address filtering. Dropped \nframes statistics are not updated unless the dropped frames are runt frames of less than 6 \nbytes (DA bytes are not received fully).\nGood transmitted and received frames\nTransmitted frames are considered “good” if transmitted successfully. In other words, a \ntransmitted frame is good if the frame transmission is not aborted due to any of the following \nerrors:\n+ Jabber Timeout\n+ No Carrier/Loss of Carrier \n+ Late Collision\n+ Frame Underflow\n+ Excessive Deferral\n+ Excessive Collision\nTable 193. Source address filtering\nFrame type\nPM\nSAIF\nSAF\nSA filter operation\nUnicast\n1\nX\nX\nPass all frames\n0\n0\n0\nPass status on perfect/Group filter match but do not drop \nframes that fail\n0\n1\n0\nFail status on perfect/group filter match but do not drop frame\n0\n0\n1\nPass on perfect/group filter match and drop frames that fail\n0\n1\n1\nFail on perfect/group filter match and drop frames that fail\n" }, { "page_number": 1157, "page_indices": { "start_index": 2257881, "end_index": 2260306 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1157 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.8 Power management: PMT", 1157 ], [ 4, "Remote wake-up frame filter register", 1157 ] ], "page_content": "RM0090 Rev 21\n1157/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nReceived frames are considered “good” if none of the following errors exists:\n+ CRC error\n+ Runt Frame (shorter than 64 bytes)\n+ Alignment error (in 10/ 100 Mbit/s only)\n+ Length error (non-Type frames only)\n+ Out of Range (non-Type frames only, longer than maximum size)\n+ MII_RXER Input error\nThe maximum frame size depends on the frame type, as follows:\n+ Untagged frame maxsize = 1518 \n+ VLAN Frame maxsize = 1522\n33.5.8 \nPower management: PMT\nThis section describes the power management (PMT) mechanisms supported by the MAC. \nPMT supports the reception of network (remote) wake-up frames and Magic Packet frames. \nPMT generates interrupts for wake-up frames and Magic Packets received by the MAC. The \nPMT block is enabled with remote wake-up frame enable and Magic Packet enable. These \nenable bits (WFE and MPE) are in the ETH_MACPMTCSR register and are programmed by \nthe application. When the power down mode is enabled in the PMT, then all received frames \nare dropped by the MAC and they are not forwarded to the application. The MAC comes out \nof the power down mode only when either a Magic Packet or a Remote wake-up frame is \nreceived and the corresponding detection is enabled.\nRemote wake-up frame filter register\nThere are eight wake-up frame filter registers. To write on each of them, load the wake-up \nframe filter register value by value. The wanted values of the wake-up frame filter are loaded \nby sequentially loading eight times the wake-up frame filter register. The read operation is \nidentical to the write operation. To read the eight values, you have to read eight times the \nwake-up frame filter register to reach the last register. Each read/write points the wake-up \nframe filter register to the next filter register.\nFigure 371. Wake-up frame filter register\nFilter 0 Byte Mask\nFilter 1 Byte Mask\nFilter 2 Byte Mask\nFilter 3 Byte Mask\nRSVD\nFilter 3\nCommand\nRSVD\nFilter 2\nCommand\nRSVD\nFilter 1\nCommand\nRSVD\nFilter 0\nCommand\nFilter 3 Offset\nFilter 2 Offset\nFilter 1 Offset\nFilter 0 Offset\nFilter 1 CRC - 16\nFilter 0 CRC - 16\nFilter 3 CRC - 16\nFilter 2 CRC - 16\nWakeup frame filter reg0\nWakeup frame filter reg1\nWakeup frame filter reg2\nWakeup frame filter reg3\nWakeup frame filter reg4\nWakeup frame filter reg5\nWakeup frame filter reg6\nWakeup frame filter reg7\nai15647\n" }, { "page_number": 1158, "page_indices": { "start_index": 2260306, "end_index": 2263972 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1158 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.8 Power management: PMT", 1157 ], [ 4, "Remote wake-up frame detection", 1158 ], [ 4, "Magic packet detection", 1158 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1158/1757\nRM0090 Rev 21\n•\nFilter i Byte Mask\nThis register defines which bytes of the frame are examined by filter i (0, 1, 2, and 3) in \norder to determine whether or not the frame is a wake-up frame. The MSB (thirty-first \nbit) must be zero. Bit j [30:0] is the Byte Mask. If bit j (byte number) of the Byte Mask is \nset, then Filter i Offset + j of the incoming frame is processed by the CRC block; \notherwise Filter i Offset + j is ignored.\n•\nFilter i Command\nThis 4-bit command controls the filter i operation. Bit 3 specifies the address type, \ndefining the pattern’s destination address type. When the bit is set, the pattern applies \nto only multicast frames. When the bit is reset, the pattern applies only to unicast \nframes. Bit 2 and bit 1 are reserved. Bit 0 is the enable bit for filter i; if bit 0 is not set, \nfilter i is disabled.\n•\nFilter i Offset\nThis register defines the offset (within the frame) from which the frames are examined \nby filter i. This 8-bit pattern offset is the offset for the filter i first byte to be examined. \nThe minimum allowed is 12, which refers to the 13th byte of the frame (offset value 0 \nrefers to the first byte of the frame).\n•\nFilter i CRC-16\nThis register contains the CRC_16 value calculated from the pattern, as well as the \nbyte mask programmed to the wake-up filter register block.\nRemote wake-up frame detection\nWhen the MAC is in sleep mode and the remote wake-up bit is enabled in the \nETH_MACPMTCSR register, normal operation is resumed after receiving a remote wake-up \nframe. The application writes all eight wake-up filter registers, by performing a sequential \nwrite to the wake-up frame filter register address. The application enables remote wake-up \nby writing a 1 to bit 2 in the ETH_MACPMTCSR register. PMT supports four programmable \nfilters that provide different receive frame patterns. If the incoming frame passes the \naddress filtering of Filter Command, and if Filter CRC-16 matches the incoming examined \npattern, then the wake-up frame is received. Filter_offset (minimum value 12, which refers to \nthe 13th byte of the frame) determines the offset from which the frame is to be examined. \nFilter Byte Mask determines which bytes of the frame must be examined. The thirty-first bit \nof Byte Mask must be set to zero. The wake-up frame is checked only for length error, FCS \nerror, dribble bit error, MII error, collision, and to ensure that it is not a runt frame. Even if the \nwake-up frame is more than 512 bytes long, if the frame has a valid CRC value, it is \nconsidered valid. Wake-up frame detection is updated in the ETH_MACPMTCSR register \nfor every remote wake-up frame received. If enabled, a PMT interrupt is generated to \nindicate the reception of a remote wake-up frame.\nMagic packet detection\nThe Magic Packet frame is based on a method that uses Advanced Micro Device’s Magic \nPacket technology to power up the sleeping device on the network. The MAC receives a \nspecific packet of information, called a Magic Packet, addressed to the node on the network. \nOnly Magic Packets that are addressed to the device or a broadcast address are checked to \ndetermine whether they meet the wake-up requirements. Magic Packets that pass address \nfiltering (unicast or broadcast) are checked to determine whether they meet the remote \nWake-on-LAN data format of 6 bytes of all ones followed by a MAC address appearing 16 \ntimes. The application enables Magic Packet wake-up by writing a 1 to bit 1 in the \nETH_MACPMTCSR register. The PMT block constantly monitors each frame addressed to \n" }, { "page_number": 1159, "page_indices": { "start_index": 2263972, "end_index": 2266206 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1159 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.8 Power management: PMT", 1157 ], [ 4, "System consideration during power-down", 1159 ] ], "page_content": "RM0090 Rev 21\n1159/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nthe node for a specific Magic Packet pattern. Each received frame is checked for a \n0xFFFF FFFF FFFF pattern following the destination and source address field. The PMT \nblock then checks the frame for 16 repetitions of the MAC address without any breaks or \ninterruptions. In case of a break in the 16 repetitions of the address, the 0xFFFF FFFF FFFF \npattern is scanned for again in the incoming frame. The 16 repetitions can be anywhere in \nthe frame, but must be preceded by the synchronization stream (0xFFFF FFFF FFFF). The \ndevice also accepts a multicast frame, as long as the 16 duplications of the MAC address \nare detected. If the MAC address of a node is 0x0011 2233 4455, then the MAC scans for \nthe data sequence:\nDestination address source address ……………….. FFFF FFFF FFFF\n0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455\n0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455\n0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455\n0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455\n …CRC\nMagic Packet detection is updated in the ETH_MACPMTCSR register for received Magic \nPacket. If enabled, a PMT interrupt is generated to indicate the reception of a Magic Packet.\nSystem consideration during power-down\nThe Ethernet PMT block is able to detect frames while the system is in the Stop mode, \nprovided that the EXTI line 19 is enabled.\nThe MAC receiver state machine should remain enabled during the power-down mode. This \nmeans that the RE bit has to remain set in the ETH_MACCR register because it is involved \nin magic packet/ wake-on-LAN frame detection. The transmit state machine should however \nbe turned off during the power-down mode by clearing the TE bit in the ETH_MACCR \nregister. Moreover, the Ethernet DMA should be disabled during the power-down mode, \nbecause it is not necessary to copy the magic packet/wake-on-LAN frame into the SRAM. \nTo disable the Ethernet DMA, clear the ST bit and the SR bit (for the transmit DMA and the \nreceive DMA, respectively) in the ETH_DMAOMR register.\nThe recommended power-down and wake-up sequences are as follows:\n" }, { "page_number": 1160, "page_indices": { "start_index": 2266206, "end_index": 2268734 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1160 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.9 Precision time protocol (IEEE1588 PTP)", 1160 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1160/1757\nRM0090 Rev 21\n1.\nDisable the transmit DMA and wait for any previous frame transmissions to complete. \nThese transmissions can be detected when the transmit interrupt ETH_DMASR \nregister[0] is received.\n2. \nDisable the MAC transmitter and MAC receiver by clearing the RE and TE bits in the \nETH_MACCR configuration register.\n3. \nWait for the receive DMA to have emptied all the frames in the Rx FIFO.\n4. \nDisable the receive DMA.\n5. \nConfigure and enable the EXTI line 19 to generate either an event or an interrupt.\n6. \nIf you configure the EXTI line 19 to generate an interrupt, you also have to correctly \nconfigure the ETH_WKUP_IRQ Handler function, which should clear the pending bit of \nthe EXTI line 19.\n7. \nEnable Magic packet/Wake-on-LAN frame detection by setting the MFE/ WFE bit in the \nETH_MACPMTCSR register.\n8. \nEnable the MAC power-down mode, by setting the PD bit in the ETH_MACPMTCSR \nregister.\n9. \nEnable the MAC Receiver by setting the RE bit in the ETH_MACCR register.\n10. Enter the system’s Stop mode (for more details refer to Section 4.3.4: Stop mode):\n11. On receiving a valid wake-up frame, the Ethernet peripheral exits the power-down \nmode.\n12. Read the ETH_MACPMTCSR to clear the power management event flag, enable the \nMAC transmitter state machine, and the receive and transmit DMA.\n13. Configure the system clock: enable the HSE and set the clocks.\n33.5.9 \nPrecision time protocol (IEEE1588 PTP)\nThe IEEE 1588 standard defines a protocol that allows precise clock synchronization in \nmeasurement and control systems implemented with technologies such as network \ncommunication, local computing and distributed objects. The protocol applies to systems \nthat communicate by local area networks supporting multicast messaging, including (but not \nlimited to) Ethernet. This protocol is used to synchronize heterogeneous systems that \ninclude clocks of varying inherent precision, resolution and stability. The protocol supports \nsystem-wide synchronization accuracy in the submicrosecond range with minimum network \nand local clock computing resources. The message-based protocol, known as the precision \ntime protocol (PTP), is transported over UDP/IP. The system or network is classified into \nMaster and Slave nodes for distributing the timing/clock information. The protocol’s \ntechnique for synchronizing a slave node to a master node by exchanging PTP messages is \ndescribed in Figure 372.\n" }, { "page_number": 1161, "page_indices": { "start_index": 2268734, "end_index": 2270873 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1161 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.9 Precision time protocol (IEEE1588 PTP)", 1160 ], [ 4, "Reference timing source", 1161 ] ], "page_content": "RM0090 Rev 21\n1161/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nFigure 372. Networked time synchronization\n1.\nThe master broadcasts PTP Sync messages to all its nodes. The Sync message \ncontains the master’s reference time information. The time at which this message \nleaves the master’s system is t1. For Ethernet ports, this time has to be captured at the \nMII.\n2. \nA slave receives the Sync message and also captures the exact time, t2, using its \ntiming reference.\n3. \nThe master then sends the slave a Follow_up message, which contains the t1 \ninformation for later use.\n4. \nThe slave sends the master a Delay_Req message, noting the exact time, t3, at which \nthis frame leaves the MII.\n5. \nThe master receives this message and captures the exact time, t4, at which it enters its \nsystem.\n6. \nThe master sends the t4 information to the slave in the Delay_Resp message.\n7. \nThe slave uses the four values of t1, t2, t3, and t4 to synchronize its local timing \nreference to the master’s timing reference.\nMost of the protocol implementation occurs in the software, above the UDP layer. As \ndescribed above, however, hardware support is required to capture the exact time when \nspecific PTP packets enter or leave the Ethernet port at the MII. This timing information has \nto be captured and returned to the software for a proper, high-accuracy implementation of \nPTP.\nReference timing source\nTo get a snapshot of the time, the core requires a reference time in 64-bit format (split into \ntwo 32-bit channels, with the upper 32 bits providing time in seconds, and the lower 32 bits \nindicating time in nanoseconds) as defined in the IEEE 1588 specification.\nThe PTP reference clock input is used to internally generate the reference time (also called \nthe System Time) and to capture time stamps. The frequency of this reference clock must \nMaster clock time\nSlave clock time\nData at\nslave clock\nSync message\nFollow_up message\ncontaining value of t1\nDelay_Req message\nDelay_Resp message\ncontaining value of t4\ntime\nt1\nt2m\nt3m\nt4\nt1, t2, t3, t4\nt2\nt1, t2\nt3\nt2\nt1, t2, t3\nai15669\n" }, { "page_number": 1162, "page_indices": { "start_index": 2270873, "end_index": 2274602 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1162 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.9 Precision time protocol (IEEE1588 PTP)", 1160 ], [ 4, "Transmission of frames with the PTP feature", 1162 ], [ 4, "Reception of frames with the PTP feature", 1162 ], [ 4, "System Time correction methods", 1162 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1162/1757\nRM0090 Rev 21\nbe greater than or equal to the resolution of time stamp counter. The synchronization \naccuracy target between the master node and the slaves is around 100 ns.\nThe generation, update and modification of the System Time are described in System Time \ncorrection methods.\nThe accuracy depends on the PTP reference clock input period, the characteristics of the \noscillator (drift) and the frequency of the synchronization procedure.\nDue to the synchronization from the Tx and Rx clock input domain to the PTP reference \nclock domain, the uncertainty on the time stamp latched value is 1 reference clock period. If \nwe add the uncertainty due to resolution, we add half the period for time stamping.\nTransmission of frames with the PTP feature\nWhen a frame’s SFD is output on the MII, a time stamp is captured. Frames for which time \nstamp capture is required are controllable on a per-frame basis. In other words, each \ntransmitted frame can be marked to indicate whether a time stamp must be captured or not \nfor that frame. The transmitted frames are not processed to identify PTP frames. Frame \ncontrol is exercised through the control bits in the transmit descriptor. Captured time stamps \nare returned to the application in the same way as the status is provided for frames. The \ntime stamp is sent back along with the Transmit status of the frame, inside the \ncorresponding transmit descriptor, thus connecting the time stamp automatically to the \nspecific PTP frame. The 64-bit time stamp information is written back to the TDES2 and \nTDES3 fields, with TDES2 holding the time stamp’s 32 least significant bits.\nReception of frames with the PTP feature\nWhen the IEEE 1588 time stamping feature is enabled, the Ethernet MAC captures the time \nstamp of all frames received on the MII. The MAC provides the time stamp as soon as the \nframe reception is complete. Captured time stamps are returned to the application in the \nsame way as the frame status is provided. The time stamp is sent back along with the \nReceive status of the frame, inside the corresponding receive descriptor. The 64-bit time \nstamp information is written back to the RDES2 and RDES3 fields, with RDES2 holding the \ntime stamp’s 32 least significant bits.\nSystem Time correction methods\nThe 64-bit PTP time is updated using the PTP input reference clock, HCLK. This PTP time \nis used as a source to take snapshots (time stamps) of the Ethernet frames being \ntransmitted or received at the MII. The System Time counter can be initialized or corrected \nusing either the Coarse or the Fine correction method.\nIn the Coarse correction method, the initial value or the offset value is written to the Time \nstamp update register (refer to Section 33.8.3). For initialization, the System Time counter is \nwritten with the value in the Time stamp update registers, whereas for system time \ncorrection, the offset value (Time stamp update register) is added to or subtracted from the \nsystem time.\nIn the Fine correction method, the slave clock (reference clock) frequency drift with respect \nto the master clock (as defined in IEEE 1588) is corrected over a period of time, unlike in the \nCoarse correction method where it is corrected in a single clock cycle. The longer correction \ntime helps maintain linear time and does not introduce drastic changes (or a large jitter) in \nthe reference time between PTP Sync message intervals. In this method, an accumulator \nsums up the contents of the Addend register as shown in Figure 373. The arithmetic carry \nthat the accumulator generates is used as a pulse to increment the system time counter. \n" }, { "page_number": 1163, "page_indices": { "start_index": 2274602, "end_index": 2276694 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1163 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.9 Precision time protocol (IEEE1588 PTP)", 1160 ], [ 4, "System Time correction methods", 1162 ] ], "page_content": "RM0090 Rev 21\n1163/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nThe accumulator and the addend are 32-bit registers. Here, the accumulator acts as a high-\nprecision frequency multiplier or divider. Figure 373 shows this algorithm.\nFigure 373. System time update using the Fine correction method\nThe system time update logic requires a 50 MHz clock frequency to achieve 20 ns accuracy. \nThe frequency division is the ratio of the reference clock frequency to the required clock \nfrequency. Hence, if the reference clock (HCLK) is, let us say, 66 MHz, the ratio is calculated \nas 66 MHz/50 MHz = 1.32. Hence, the default addend value to be set in the register is \n232/1.32, which is equal to 0xC1F0 7C1F.\nIf the reference clock drifts lower, to 65 MHz for example, the ratio is 65/50 or 1.3 and the \nvalue to set in the addend register is 232/1.30 equal to 0xC4EC 4EC4. If the clock drifts \nhigher, to 67 MHz for example, the addend register must be set to 0xBF0 B7672. When the \nclock drift is zero, the default addend value of 0xC1F0 7C1F (232/1.32) should be \nprogrammed.\nIn Figure 373, the constant value used to increment the subsecond register is 0d43. This \nmakes an accuracy of 20 ns in the system time (in other words, it is incremented by 20 ns \nsteps).\nThe software has to calculate the drift in frequency based on the Sync messages, and to \nupdate the Addend register accordingly. Initially, the slave clock is set with \nFreqCompensationValue0 in the Addend register. This value is as follows:\nFreqCompensationValue0 = 232 / FreqDivisionRatio\nIf MasterToSlaveDelay is initially assumed to be the same for consecutive Sync messages, \nthe algorithm described below must be applied. After a few Sync cycles, frequency lock \noccurs. The slave clock can then determine a precise MasterToSlaveDelay value and re-\nsynchronize with the master using the new value.\nAddend register\n+\nAccumulator register\nSubsecond register\n+\nConstant value\nSecond register\nIncrement Second register\nAddend update\nai15670\nIncrement Subsecond\nregister\n" }, { "page_number": 1164, "page_indices": { "start_index": 2276694, "end_index": 2279755 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1164 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.9 Precision time protocol (IEEE1588 PTP)", 1160 ], [ 4, "Programming steps for system time generation initialization", 1164 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1164/1757\nRM0090 Rev 21\nThe algorithm is as follows:\n•\nAt time MasterSyncTime (n) the master sends the slave clock a Sync message. The \nslave receives this message when its local clock is SlaveClockTime (n) and computes \nMasterClockTime (n) as:\nMasterClockTime (n) = MasterSyncTime (n) + MasterToSlaveDelay (n)\n•\nThe master clock count for current Sync cycle, MasterClockCount (n) is given by:\nMasterClockCount (n) = MasterClockTime (n) – MasterClockTime (n – 1) (assuming \nthat MasterToSlaveDelay is the same for Sync cycles n and n – 1)\n•\nThe slave clock count for current Sync cycle, SlaveClockCount (n) is given by:\nSlaveClockCount (n) = SlaveClockTime (n) – SlaveClockTime (n – 1)\n•\nThe difference between master and slave clock counts for current Sync cycle, \nClockDiffCount (n) is given by:\nClockDiffCount (n) = MasterClockCount (n) – SlaveClockCount (n)\n•\nThe frequency-scaling factor for slave clock, FreqScaleFactor (n) is given by:\nFreqScaleFactor (n) = (MasterClockCount (n) + ClockDiffCount (n)) / \nSlaveClockCount (n)\n•\nThe frequency compensation value for Addend register, FreqCompensationValue (n) is \ngiven by:\nFreqCompensationValue (n) = FreqScaleFactor (n) × FreqCompensationValue (n – 1)\nIn theory, this algorithm achieves lock in one Sync cycle; however, it may take several \ncycles, due to changing network propagation delays and operating conditions.\nThis algorithm is self-correcting: if for any reason the slave clock is initially set to a value \nfrom the master that is incorrect, the algorithm corrects it at the cost of more Sync cycles.\nProgramming steps for system time generation initialization\nThe time stamping feature can be enabled by setting bit 0 in the Time stamp control register \n(ETH__PTPTSCR). However, it is essential to initialize the time stamp counter after this bit \nis set to start time stamp operation. The proper sequence is the following:\n1.\nMask the Time stamp trigger interrupt by setting bit 9 in the MACIMR register.\n2. \nProgram Time stamp register bit 0 to enable time stamping.\n3. \nProgram the Subsecond increment register based on the PTP clock frequency.\n4. \nIf you are using the Fine correction method, program the Time stamp addend register \nand set Time stamp control register bit 5 (addend register update).\n5. \nPoll the Time stamp control register until bit 5 is cleared.\n6. \nTo select the Fine correction method (if required), program Time stamp control register \nbit 1.\n7. \nProgram the Time stamp high update and Time stamp low update registers with the \nappropriate time value.\n8. \nSet Time stamp control register bit 2 (Time stamp init).\n9. \nThe Time stamp counter starts operation as soon as it is initialized with the value \nwritten in the Time stamp update register.\n10. Enable the MAC receiver and transmitter for proper time stamping.\nNote:\nIf time stamp operation is disabled by clearing bit 0 in the ETH_PTPTSCR register, the \nabove steps must be repeated to restart the time stamp operation.\n" }, { "page_number": 1165, "page_indices": { "start_index": 2279755, "end_index": 2282333 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1165 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.9 Precision time protocol (IEEE1588 PTP)", 1160 ], [ 4, "Programming steps for system time update in the Coarse correction method", 1165 ], [ 4, "Programming steps for system time update in the Fine correction method", 1165 ], [ 4, "PTP trigger internal connection with TIM2", 1165 ] ], "page_content": "RM0090 Rev 21\n1165/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nProgramming steps for system time update in the Coarse correction method\nTo synchronize or update the system time in one process (coarse correction method), \nperform the following steps: \n1.\nWrite the offset (positive or negative) in the Time stamp update high and low registers. \n2. \nSet bit 3 (TSSTU) in the Time stamp control register.\n3. \nThe value in the Time stamp update registers is added to or subtracted from the system \ntime when the TSSTU bit is cleared.\nProgramming steps for system time update in the Fine correction method\nTo synchronize or update the system time to reduce system-time jitter (fine correction \nmethod), perform the following steps:\n1.\nWith the help of the algorithm explained in System Time correction methods, calculate \nthe rate by which you want to speed up or slow down the system time increments.\n2. \nUpdate the time stamp.\n3. \nWait the time you want the new value of the Addend register to be active. You can do \nthis by activating the Time stamp trigger interrupt after the system time reaches the \ntarget value.\n4. \nProgram the required target time in the Target time high and low registers. Unmask the \nTime stamp interrupt by clearing bit 9 in the ETH_MACIMR register.\n5. \nSet Time stamp control register bit 4 (TSARU).\n6. \nWhen this trigger causes an interrupt, read the ETH_MACSR register.\n7. \nReprogram the Time stamp addend register with the old value and set ETH_TPTSCR \nbit 5 again.\nPTP trigger internal connection with TIM2\nThe MAC provides a trigger interrupt when the system time becomes greater than the target \ntime. Using an interrupt introduces a known latency plus an uncertainty in the command \nexecution time.\nIn order to avoid this uncertainty, a PTP trigger output signal is set high when the system \ntime is greater than the target time. It is internally connected to the TIM2 input trigger. With \nthis signal, the input capture feature, the output compare feature and the waveforms of the \ntimer can be used, triggered by the synchronized PTP system time. No uncertainty is \nintroduced since the clock of the timer (PCLK1: TIM2 APB1 clock) and PTP reference clock \n(HCLK) are synchronous.\nThis PTP trigger signal is connected to the TIM2 ITR1 input selectable by software. The \nconnection is enabled through bits 11 and 10 in the TIM2 option register (TIM2_OR). \nFigure 374 shows the connection.\nFigure 374. PTP trigger output to TIM2 ITR1 connection\nEthernet MAC\nai15671\nTIM2\nITR1\nPTP trigger\n" }, { "page_number": 1166, "page_indices": { "start_index": 2282333, "end_index": 2285498 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1166 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.5 Ethernet functional description: MAC 802.3", 1136 ], [ 3, "33.5.9 Precision time protocol (IEEE1588 PTP)", 1160 ], [ 4, "PTP pulse-per-second output signal", 1166 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1166/1757\nRM0090 Rev 21\nPTP pulse-per-second output signal\nThis PTP pulse output is used to check the synchronization between all nodes in the \nnetwork. To be able to test the difference between the local slave clock and the master \nreference clock, both clocks were given a pulse-per-second (PPS) output signal that may be \nconnected to an oscilloscope if necessary. The deviation between the two signals can \ntherefore be measured. The pulse width of the PPS output is 125 ms.\nThe PPS output is enabled through a GPIO alternate function. (GPIO_AFR register).\nThe default frequency of the PPS output is 1 Hz. PPSFREQ[3:0] (in ETH_PTPPPSCR) can \nbe used to set the frequency of the PPS output to 2PPSFREQ Hz.\nWhen set to 1 Hz, the PPS pulse width is 125 ms with binary rollover (TSSSR=0, bit 9 in \nETH_PTPTSCR) and 100 ms with digital rollover (TSSSR=1). When set to 2 Hz and higher, \nthe duty cycle of the PPS output is 50% with binary rollover.\nWith digital rollover (TSSSR=1), it is recommended not to use the PPS output with a \nfrequency other than 1 Hz as it would have irregular waveforms (though its average \nfrequency would always be correct during any one-second window).\nFigure 375. PPS output\n33.6 \nEthernet functional description: DMA controller operation\nThe DMA has independent transmit and receive engines, and a CSR space. The transmit \nengine transfers data from system memory into the Tx FIFO while the receive engine \ntransfers data from the Rx FIFO into system memory. The controller utilizes descriptors to \nefficiently move data from source to destination with minimum CPU intervention. The DMA \nis designed for packet-oriented data transfers such as frames in Ethernet. The controller can \nbe programmed to interrupt the CPU in cases such as frame transmit and receive transfer \ncompletion, and other normal/error conditions. The DMA and the STM32F4xx communicate \nthrough two data structures:\n•\nControl and status registers (CSR)\n•\nDescriptor lists and data buffers.\nControl and status registers are described in detail in Section 33.8. Descriptors are \ndescribed in detail in Normal Tx DMA descriptors.\nThe DMA transfers the received data frames to the receive buffer in the STM32F4xx \nmemory, and transmits data frames from the transmit buffer in the STM32F4xx memory. \nDescriptors that reside in the STM32F4xx memory act as pointers to these buffers. There \nare two descriptor lists: one for reception, and one for transmission. The base address of \neach list is written into DMA registers 3 and 4, respectively. A descriptor list is forward-linked \n(either implicitly or explicitly). The last descriptor may point back to the first entry to create a \nring structure. Explicit chaining of descriptors is accomplished by configuring the second \naddress chained in both the receive and transmit descriptors (RDES1[14] and TDES0[20]). \nThe descriptor lists reside in the Host’s physical memory space. Each descriptor can point to \na maximum of two buffers. This enables the use of two physically addressed buffers, \nEthernet MAC\nai15672\nPPS output\n" }, { "page_number": 1167, "page_indices": { "start_index": 2285498, "end_index": 2287912 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1167 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.1 Initialization of a transfer using DMA", 1167 ], [ 3, "33.6.2 Host bus burst access", 1167 ] ], "page_content": "RM0090 Rev 21\n1167/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\ninstead of two contiguous buffers in memory. A data buffer resides in the Host’s physical \nmemory space, and consists of an entire frame or part of a frame, but cannot exceed a \nsingle frame. Buffers contain only data. The buffer status is maintained in the descriptor. \nData chaining refers to frames that span multiple data buffers. However, a single descriptor \ncannot span multiple frames. The DMA skips to the next frame buffer when the end of frame \nis detected. Data chaining can be enabled or disabled. The descriptor ring and chain \nstructure is shown in Figure 376.\nFigure 376. Descriptor ring and chain structure\n33.6.1 \nInitialization of a transfer using DMA\nInitialization for the MAC is as follows:\n1.\nWrite to ETH_DMABMR to set STM32F4xx bus access parameters.\n2. \nWrite to the ETH_DMAIER register to mask unnecessary interrupt causes.\n3. \nThe software driver creates the transmit and receive descriptor lists. Then it writes to \nboth the ETH_DMARDLAR and ETH_DMATDLAR registers, providing the DMA with \nthe start address of each list.\n4. \nWrite to MAC registers 1, 2, and 3 to choose the desired filtering options.\n5. \nWrite to the MAC ETH_MACCR register to configure and enable the transmit and \nreceive operating modes. The PS and DM bits are set based on the auto-negotiation \nresult (read from the PHY).\n6. \nWrite to the ETH_DMAOMR register to set bits 13 and 1 and start transmission and \nreception.\n7. \nThe transmit and receive engines enter the running state and attempt to acquire \ndescriptors from the respective descriptor lists. The receive and transmit engines then \nbegin processing receive and transmit operations. The transmit and receive processes \nare independent of each other and can be started or stopped separately.\n33.6.2 \nHost bus burst access\nThe DMA attempts to execute fixed-length burst transfers on the AHB master interface if \nconfigured to do so (FB bit in ETH_DMABMR). The maximum burst length is indicated and \nlimited by the PBL field (ETH_DMABMR [13:8]). The receive and transmit descriptors are \nDescriptor 0\nai15638\nDescriptor 1\nDescriptor 2\nDescriptor n\nBuffer 1\nBuffer 2\nBuffer 1\nBuffer 2\nBuffer 1\nBuffer 2\nBuffer 1\nBuffer 2\nRing structure\nChain structure\nDescriptor 0\nDescriptor 1\nDescriptor 2\nBuffer 1\nBuffer 1\nBuffer 1\nNext descriptor\n" }, { "page_number": 1168, "page_indices": { "start_index": 2287912, "end_index": 2291674 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1168 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.3 Host data buffer alignment", 1168 ], [ 3, "33.6.4 Buffer size calculations", 1168 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1168/1757\nRM0090 Rev 21\nalways accessed in the maximum possible burst size (limited by PBL) for the 16 bytes to be \nread.\nThe Transmit DMA initiates a data transfer only when there is sufficient space in the \nTransmit FIFO to accommodate the configured burst or the number of bytes until the end of \nframe (when it is less than the configured burst length). The DMA indicates the start address \nand the number of transfers required to the AHB Master Interface. When the AHB Interface \nis configured for fixed-length burst, then it transfers data using the best combination of \nINCR4, INCR8, INCR16 and SINGLE transactions. Otherwise (no fixed-length burst), it \ntransfers data using INCR (undefined length) and SINGLE transactions.\nThe Receive DMA initiates a data transfer only when sufficient data for the configured burst \nis available in Receive FIFO or when the end of frame (when it is less than the configured \nburst length) is detected in the Receive FIFO. The DMA indicates the start address and the \nnumber of transfers required to the AHB master interface. When the AHB interface is \nconfigured for fixed-length burst, then it transfers data using the best combination of INCR4, \nINCR8, INCR16 and SINGLE transactions. If the end of frame is reached before the fixed-\nburst ends on the AHB interface, then dummy transfers are performed in order to complete \nthe fixed-length burst. Otherwise (FB bit in ETH_DMABMR is reset), it transfers data using \nINCR (undefined length) and SINGLE transactions.\nWhen the AHB interface is configured for address-aligned beats, both DMA engines ensure \nthat the first burst transfer the AHB initiates is less than or equal to the size of the configured \nPBL. Thus, all subsequent beats start at an address that is aligned to the configured PBL. \nThe DMA can only align the address for beats up to size 16 (for PBL > 16), because the \nAHB interface does not support more than INCR16.\n33.6.3 \nHost data buffer alignment\nThe transmit and receive data buffers do not have any restrictions on start address \nalignment. In our system with 32-bit memory, the start address for the buffers can be aligned \nto any of the four bytes. However, the DMA always initiates transfers with address aligned to \nthe bus width with dummy data for the byte lanes not required. This typically happens during \nthe transfer of the beginning or end of an Ethernet frame.\n•\nExample of buffer read:\nIf the Transmit buffer address is 0x0000 0FF2, and 15 bytes need to be transferred, \nthen the DMA reads five full words from address 0x0000 0FF0, but when transferring \ndata to the Transmit FIFO, the extra bytes (the first two bytes) are dropped or ignored. \nSimilarly, the last 3 bytes of the last transfer are also ignored. The DMA always ensures \nit transfers a full 32-bit data items to the Transmit FIFO, unless it is the end of frame.\n•\nExample of buffer write:\nIf the Receive buffer address is 0x0000 0FF2, and 16 bytes of a received frame need to \nbe transferred, then the DMA writes five full 32-bit data items from address \n0x0000 0FF0. But the first 2 bytes of the first transfer and the last 2 bytes of the third \ntransfer have dummy data.\n33.6.4 \nBuffer size calculations\nThe DMA does not update the size fields in the transmit and receive descriptors. The DMA \nupdates only the status fields (xDES0) of the descriptors. The driver has to calculate the \nsizes. The transmit DMA transfers the exact number of bytes (indicated by buffer size field in \nTDES1) towards the MAC core. If a descriptor is marked as first (FS bit in TDES0 is set), \nthen the DMA marks the first transfer from the buffer as the start of frame. If a descriptor is \n" }, { "page_number": 1169, "page_indices": { "start_index": 2291674, "end_index": 2294797 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1169 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.5 DMA arbiter", 1169 ], [ 3, "33.6.6 Error response to DMA", 1169 ], [ 3, "33.6.7 Tx DMA configuration", 1169 ], [ 4, "TxDMA operation: default (non-OSF) mode", 1169 ] ], "page_content": "RM0090 Rev 21\n1169/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nmarked as last (LS bit in TDES0), then the DMA marks the last transfer from that data buffer \nas the end of frame. The receive DMA transfers data to a buffer until the buffer is full or the \nend of frame is received. If a descriptor is not marked as last (LS bit in RDES0), then the \nbuffer(s) that correspond to the descriptor are full and the amount of valid data in a buffer is \naccurately indicated by the buffer size field minus the data buffer pointer offset when the \ndescriptor’s FS bit is set. The offset is zero when the data buffer pointer is aligned to the \ndatabus width. If a descriptor is marked as last, then the buffer may not be full (as indicated \nby the buffer size in RDES1). To compute the amount of valid data in this final buffer, the \ndriver must read the frame length (FL bits in RDES0[29:16]) and subtract the sum of the \nbuffer sizes of the preceding buffers in this frame. The receive DMA always transfers the \nstart of next frame with a new descriptor.\nNote:\nEven when the start address of a receive buffer is not aligned to the system databus width \nthe system should allocate a receive buffer of a size aligned to the system bus width. For \nexample, if the system allocates a 1024 byte (1 KB) receive buffer starting from address \n0x1000, the software can program the buffer start address in the receive descriptor to have \na 0x1002 offset. The receive DMA writes the frame to this buffer with dummy data in the first \ntwo locations (0x1000 and 0x1001). The actual frame is written from location 0x1002. Thus, \nthe actual useful space in this buffer is 1022 bytes, even though the buffer size is \nprogrammed as 1024 bytes, due to the start address offset.\n33.6.5 \nDMA arbiter\nThe arbiter inside the DMA takes care of the arbitration between transmit and receive \nchannel accesses to the AHB master interface. Two types of arbitrations are possible: \nround-robin, and fixed-priority. When round-robin arbitration is selected (DA bit in \nETH_DMABMR is reset), the arbiter allocates the databus in the ratio set by the PM bits in \nETH_DMABMR, when both transmit and receive DMAs request access simultaneously. \nWhen the DA bit is set, the receive DMA always gets priority over the transmit DMA for data \naccess.\n33.6.6 \nError response to DMA\nFor any data transfer initiated by a DMA channel, if the slave replies with an error response, \nthat DMA stops all operations and updates the error bits and the fatal bus error bit in the \nStatus register (ETH_DMASR register). That DMA controller can resume operation only \nafter soft- or hard-resetting the peripheral and re-initializing the DMA.\n33.6.7 \nTx DMA configuration\nTxDMA operation: default (non-OSF) mode\nThe transmit DMA engine in default mode proceeds as follows:\n1.\nThe user sets up the transmit descriptor (TDES0-TDES3) and sets the OWN bit \n(TDES0[31]) after setting up the corresponding data buffer(s) with Ethernet frame data.\n2. \nOnce the ST bit (ETH_DMAOMR register[13]) is set, the DMA enters the Run state.\n" }, { "page_number": 1170, "page_indices": { "start_index": 2294797, "end_index": 2296889 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1170 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.7 Tx DMA configuration", 1169 ], [ 4, "TxDMA operation: default (non-OSF) mode", 1169 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1170/1757\nRM0090 Rev 21\n3. \nWhile in the Run state, the DMA polls the transmit descriptor list for frames requiring \ntransmission. After polling starts, it continues in either sequential descriptor ring order \nor chained order. If the DMA detects a descriptor flagged as owned by the CPU, or if an \nerror condition occurs, transmission is suspended and both the Transmit buffer \nUnavailable (ETH_DMASR register[2]) and Normal Interrupt Summary (ETH_DMASR \nregister[16]) bits are set. The transmit engine proceeds to Step 9.\n4. \nIf the acquired descriptor is flagged as owned by DMA (TDES0[31] is set), the DMA \ndecodes the transmit data buffer address from the acquired descriptor.\n5. \nThe DMA fetches the transmit data from the STM32F4xx memory and transfers the \ndata.\n6. \nIf an Ethernet frame is stored over data buffers in multiple descriptors, the DMA closes \nthe intermediate descriptor and fetches the next descriptor. Steps 3, 4, and 5 are \nrepeated until the end of Ethernet frame data is transferred.\n7. \nWhen frame transmission is complete, if IEEE 1588 time stamping was enabled for the \nframe (as indicated in the transmit status) the time stamp value is written to the transmit \ndescriptor (TDES2 and TDES3) that contains the end-of-frame buffer. The status \ninformation is then written to this transmit descriptor (TDES0). Because the OWN bit is \ncleared during this step, the CPU now owns this descriptor. If time stamping was not \nenabled for this frame, the DMA does not alter the contents of TDES2 and TDES3.\n8. \nTransmit Interrupt (ETH_DMASR register [0]) is set after completing the transmission \nof a frame that has Interrupt on Completion (TDES1[31]) set in its last descriptor. The \nDMA engine then returns to Step 3.\n9. \nIn the Suspend state, the DMA tries to re-acquire the descriptor (and thereby returns to \nStep 3) when it receives a transmit poll demand, and the Underflow Interrupt Status bit \nis cleared.\nFigure 377 shows the TxDMA transmission flow in default mode.\n" }, { "page_number": 1171, "page_indices": { "start_index": 2296889, "end_index": 2298011 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1171 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.7 Tx DMA configuration", 1169 ], [ 4, "TxDMA operation: OSF mode", 1171 ] ], "page_content": "RM0090 Rev 21\n1171/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nFigure 377. TxDMA operation in Default mode\nTxDMA operation: OSF mode\nWhile in the Run state, the transmit process can simultaneously acquire two frames without \nclosing the Status descriptor of the first (if the OSF bit is set in ETH_DMAOMR register[2]). \nAs the transmit process finishes transferring the first frame, it immediately polls the transmit \ndescriptor list for the second frame. If the second frame is valid, the transmit process \ntransfers this frame before writing the first frame’s status information. In OSF mode, the \nRun-state transmit DMA operates according to the following sequence:\nStart TxDMA\n(Re-)fetch next \ndescriptor\nWrite status word\nto TDES0\nWait for Tx status\nTransfer data from \nbuffer(s)\n(AHB)\nerror?\nOwn\nbit set?\n(AHB)\nerror?\nFrame xfer \ncomplete?\nTime stamp \npresent?\n(AHB)\nerror?\nWrite time stamp to \nTDES2 and TDES3\n(AHB)\nerror?\nStop TxDMA\nTxDMA suspended\nNo\nYes\nNo\nYes\nNo\nNo\nStart\nYes\nYes\nYes\nClose intermediate \ndescriptor\nNo\nYes\nNo\nYes\nNo\nPoll demand\nai15639\n" }, { "page_number": 1172, "page_indices": { "start_index": 2298011, "end_index": 2299934 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1172 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.7 Tx DMA configuration", 1169 ], [ 4, "TxDMA operation: OSF mode", 1171 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1172/1757\nRM0090 Rev 21\n1.\nThe DMA operates as described in steps 1–6 of the TxDMA (default mode).\n2. \nWithout closing the previous frame’s last descriptor, the DMA fetches the next \ndescriptor.\n3. \nIf the DMA owns the acquired descriptor, the DMA decodes the transmit buffer address \nin this descriptor. If the DMA does not own the descriptor, the DMA goes into Suspend \nmode and skips to Step 7.\n4. \nThe DMA fetches the Transmit frame from the STM32F4xx memory and transfers the \nframe until the end of frame data are transferred, closing the intermediate descriptors if \nthis frame is split across multiple descriptors.\n5. \nThe DMA waits for the transmission status and time stamp of the previous frame. When \nthe status is available, the DMA writes the time stamp to TDES2 and TDES3, if such \ntime stamp was captured (as indicated by a status bit). The DMA then writes the status, \nwith a cleared OWN bit, to the corresponding TDES0, thus closing the descriptor. If \ntime stamping was not enabled for the previous frame, the DMA does not alter the \ncontents of TDES2 and TDES3.\n6. \nIf enabled, the Transmit interrupt is set, the DMA fetches the next descriptor, then \nproceeds to Step 3 (when Status is normal). If the previous transmission status shows \nan underflow error, the DMA goes into Suspend mode (Step 7). \n7. \nIn Suspend mode, if a pending status and time stamp are received by the DMA, it \nwrites the time stamp (if enabled for the current frame) to TDES2 and TDES3, then \nwrites the status to the corresponding TDES0. It then sets relevant interrupts and \nreturns to Suspend mode. \n8. \nThe DMA can exit Suspend mode and enter the Run state (go to Step 1 or Step 2 \ndepending on pending status) only after receiving a Transmit Poll demand \n(ETH_DMATPDR register).\nFigure 378 shows the basic flowchart in OSF mode.\n" }, { "page_number": 1173, "page_indices": { "start_index": 2299934, "end_index": 2301794 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1173 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.7 Tx DMA configuration", 1169 ], [ 4, "Transmit frame processing", 1173 ] ], "page_content": "RM0090 Rev 21\n1173/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nFigure 378. TxDMA operation in OSF mode\nTransmit frame processing\nThe transmit DMA expects that the data buffers contain complete Ethernet frames, \nexcluding preamble, pad bytes, and FCS fields. The DA, SA, and Type/Len fields contain \nvalid data. If the transmit descriptor indicates that the MAC core must disable CRC or pad \ninsertion, the buffer must have complete Ethernet frames (excluding preamble), including \nthe CRC bytes. Frames can be data-chained and span over several buffers. Frames have to \nbe delimited by the first descriptor (TDES0[28]) and the last descriptor (TDES0[29]). As the \ntransmission starts, TDES0[28] has to be set in the first descriptor. When this occurs, the \nframe data are transferred from the memory buffer to the Transmit FIFO. Concurrently, if the \nlast descriptor (TDES0[29]) of the current frame is cleared, the transmit process attempts to \nacquire the next descriptor. The transmit process expects TDES0[28] to be cleared in this \ndescriptor. If TDES0[29] is cleared, it indicates an intermediary buffer. If TDES0[29] is set, it \nPrevious frame \nstatus available\nStart TxDMA\n(Re-)fetch next \ndescriptor\nWrite status word to \nprev. frame’s TDES0\nTransfer data from \nbuffer(s)\n(AHB)\nerror?\nOwn\nbit set?\n(AHB)\nerror?\nFrame xfer \ncomplete?\nTime stamp \npresent?\n(AHB)\nerror?\nWrite time stamp to \nTDES2 & TDES3 \nfor previous frame\n(AHB)\nerror?\nStop TxDMA\nNo\nYes\nNo\nYes\nNo\nStart\nYes\nClose intermediate \ndescriptor\nNo\nNo\nWait for previous \nframe’s Tx status\nSecond\nframe?\nYes\nYes\nNo\nYes\nYes\nWrite time stamp to \nTDES2 & TDES3 \nfor previous frame\n(AHB)\nerror?\n(AHB)\nerror?\nYes\nTime stamp \npresent?\nYes\nWrite status word to \nprev. frame’s TDES0\nTxDMA suspended\nYes\nNo\nYes\nNo\nNo\nPoll \ndemand\nNo\nNo\nai15640\n" }, { "page_number": 1174, "page_indices": { "start_index": 2301794, "end_index": 2304679 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1174 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.7 Tx DMA configuration", 1169 ], [ 4, "Transmit polling suspended", 1174 ], [ 4, "Normal Tx DMA descriptors", 1174 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1174/1757\nRM0090 Rev 21\nindicates the last buffer of the frame. After the last buffer of the frame has been transmitted, \nthe DMA writes back the final status information to the transmit descriptor 0 (TDES0) word \nof the descriptor that has the last segment set in transmit descriptor 0 (TDES0[29]). At this \ntime, if Interrupt on Completion (TDES0[30]) is set, Transmit Interrupt (in ETH_DMASR \nregister [0]) is set, the next descriptor is fetched, and the process repeats. Actual frame \ntransmission begins after the Transmit FIFO has reached either a programmable transmit \nthreshold (ETH_DMAOMR register[16:14]), or a full frame is contained in the FIFO. There is \nalso an option for the Store and forward mode (ETH_DMAOMR register[21]). Descriptors \nare released (OWN bit TDES0[31] is cleared) when the DMA finishes transferring the frame.\nTransmit polling suspended\nTransmit polling can be suspended by either of the following conditions:\n•\nThe DMA detects a descriptor owned by the CPU (TDES0[31]=0) and the Transmit \nbuffer unavailable flag is set (ETH_DMASR register[2]). To resume, the driver must \ngive descriptor ownership to the DMA and then issue a Poll Demand command.\n•\nA frame transmission is aborted when a transmit error due to underflow is detected. \nThe appropriate Transmit Descriptor 0 (TDES0) bit is set. If the second condition \noccurs, both the Abnormal Interrupt Summary (in ETH_DMASR register [15]) and \nTransmit Underflow bits (in ETH_DMASR register[5]) are set, and the information is \nwritten to Transmit Descriptor 0, causing the suspension. If the DMA goes into \nSuspend state due to the first condition, then both the Normal Interrupt Summary \n(ETH_DMASR register [16]) and Transmit Buffer Unavailable (ETH_DMASR \nregister[2]) bits are set. In both cases, the position in the transmit list is retained. The \nretained position is that of the descriptor following the last descriptor closed by the \nDMA. The driver must explicitly issue a Transmit Poll Demand command after rectifying \nthe suspension cause.\nNormal Tx DMA descriptors\nThe normal transmit descriptor structure consists of four 32-bit words as shown in \nFigure 379. The bit descriptions of TDES0, TDES1, TDES2 and TDES3 are given below.\nNote that enhanced descriptors must be used if time stamping is activated (ETH_PTPTSCR \nbit 0, TSE=1) or if IPv4 checksum offload is activated (ETH_MACCR bit 10, IPCO=1).\nFigure 379. Normal transmit descriptor\nTDES 3\nO\nW\nN\nCtrl\n[30:26]\nRes.\n24\nCtrl\n[23:20]\nReserved\n[19:18]\nStatus [16:0]\nReserved\n[31:29]\nBuffer 2 byte count\n[28:16]\nReserved\n[15:13]\nBuffer 1 byte count\n[12:0]\nBuffer 1 address [31:0] / Time stamp low [31:0]\nBuffer 2 address [31:0] or Next descriptor address [31:0] / Time stamp high [31:0]\nTDES 0\nTDES 1\nTDES 2\n31\n0\nai15642b\nT\nT\nS\nE\nT\nT\nS\nS\n" }, { "page_number": 1175, "page_indices": { "start_index": 2304679, "end_index": 2307593 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1175 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.7 Tx DMA configuration", 1169 ], [ 4, "Normal Tx DMA descriptors", 1174 ] ], "page_content": "RM0090 Rev 21\n1175/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n•\nTDES0: Transmit descriptor Word0\nThe application software has to program the control bits [30:26]+[23:20] plus the OWN \nbit [31] during descriptor initialization. When the DMA updates the descriptor (or writes \nit back), it resets all the control bits plus the OWN bit, and reports only the status bits.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nOWN\nIC\nLS\nFS\nDC\nDP\nTTSE\nRes\nCIC\nTER\nTCH\nRes.\nTTSS\nIHE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nES\nJT\nFF\nIPE\nLCA\nNC\nLCO\nEC\nVF\nCC\nED\nUF\nDB\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 OWN: Own bit\nWhen set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset, it \nindicates that the descriptor is owned by the CPU. The DMA clears this bit either when it \ncompletes the frame transmission or when the buffers allocated in the descriptor are read \ncompletely. The ownership bit of the frame’s first descriptor must be set after all subsequent \ndescriptors belonging to the same frame have been set.\nBit 30 IC: Interrupt on completion\nWhen set, this bit sets the Transmit Interrupt (ETH_DMASR[0]) after the present frame has \nbeen transmitted.\nBit 29 LS: Last segment\nWhen set, this bit indicates that the buffer contains the last segment of the frame.\nBit 28 FS: First segment\nWhen set, this bit indicates that the buffer contains the first segment of a frame.\nBit 27 DC: Disable CRC\nWhen this bit is set, the MAC does not append a cyclic redundancy check (CRC) to the end \nof the transmitted frame. This is valid only when the first segment (TDES0[28]) is set.\nBit 26 DP: Disable pad\nWhen set, the MAC does not automatically add padding to a frame shorter than 64 bytes. \nWhen this bit is reset, the DMA automatically adds padding and CRC to a frame shorter than \n64 bytes, and the CRC field is added despite the state of the DC (TDES0[27]) bit. This is \nvalid only when the first segment (TDES0[28]) is set.\nBit 25 TTSE: Transmit time stamp enable\n When TTSE is set and when TSE is set (ETH_PTPTSCR bit 0), IEEE1588 hardware time \nstamping is activated for the transmit frame described by the descriptor. This field is only valid \nwhen the First segment control bit (TDES0[28]) is set.\nBit 24 Reserved, must be kept at reset value.\nBits 23:22 CIC: Checksum insertion control\nThese bits control the checksum calculation and insertion. Bit encoding is as shown below:\n00: Checksum Insertion disabled\n01: Only IP header checksum calculation and insertion are enabled\n10: IP header checksum and payload checksum calculation and insertion are enabled, but \npseudo-header checksum is not calculated in hardware\n11: IP Header checksum and payload checksum calculation and insertion are enabled, and \npseudo-header checksum is calculated in hardware.\n" }, { "page_number": 1176, "page_indices": { "start_index": 2307593, "end_index": 2310398 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1176 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.7 Tx DMA configuration", 1169 ], [ 4, "Normal Tx DMA descriptors", 1174 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1176/1757\nRM0090 Rev 21\nBit 21 TER: Transmit end of ring\nWhen set, this bit indicates that the descriptor list reached its final descriptor. The DMA \nreturns to the base address of the list, creating a descriptor ring.\nBit 20 TCH: Second address chained\nWhen set, this bit indicates that the second address in the descriptor is the next descriptor \naddress rather than the second buffer address. When TDES0[20] is set, TBS2 \n(TDES1[28:16]) is a “don’t care” value. TDES0[21] takes precedence over TDES0[20].\nBits 19:18 Reserved, must be kept at reset value.\nBit 17 TTSS: Transmit time stamp status\nThis field is used as a status bit to indicate that a time stamp was captured for the described \ntransmit frame. When this bit is set, TDES2 and TDES3 have a time stamp value captured for the \ntransmit frame. This field is only valid when the descriptor’s Last segment control bit (TDES0[29]) \nis set.\nNote that when enhanced descriptors are enabled (EDFE=1 in ETH_DMABMR), TTSS=1 \nindicates that TDES6 and TDES7 have the time stamp value.\nBit 16 IHE: IP header error\nWhen set, this bit indicates that the MAC transmitter detected an error in the IP datagram \nheader. The transmitter checks the header length in the IPv4 packet against the number of \nheader bytes received from the application and indicates an error status if there is a \nmismatch. For IPv6 frames, a header error is reported if the main header length is not 40 \nbytes. Furthermore, the Ethernet length/type field value for an IPv4 or IPv6 frame must \nmatch the IP header version received with the packet. For IPv4 frames, an error status is \nalso indicated if the Header Length field has a value less than 0x5.\nBit 15 ES: Error summary\nIndicates the logical OR of the following bits:\nTDES0[14]: Jabber timeout \nTDES0[13]: Frame flush \nTDES0[11]: Loss of carrier \nTDES0[10]: No carrier \nTDES0[9]: Late collision \nTDES0[8]: Excessive collision \nTDES0[2]:Excessive deferral \nTDES0[1]: Underflow error \nTDES0[16]: IP header error \nTDES0[12]: IP payload error\nBit 14 JT: Jabber timeout\nWhen set, this bit indicates the MAC transmitter has experienced a jabber timeout. This bit is \nonly set when the MAC configuration register’s JD bit is not set.\nBit 13 FF: Frame flushed\nWhen set, this bit indicates that the DMA/MTL flushed the frame due to a software Flush \ncommand given by the CPU.\nBit 12 IPE: IP payload error\nWhen set, this bit indicates that MAC transmitter detected an error in the TCP, UDP, or ICMP \nIP datagram payload. The transmitter checks the payload length received in the IPv4 or IPv6 \nheader against the actual number of TCP, UDP or ICMP packet bytes received from the \napplication and issues an error status in case of a mismatch.\n" }, { "page_number": 1177, "page_indices": { "start_index": 2310398, "end_index": 2312958 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1177 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.7 Tx DMA configuration", 1169 ], [ 4, "Normal Tx DMA descriptors", 1174 ] ], "page_content": "RM0090 Rev 21\n1177/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n•\nTDES1: Transmit descriptor Word1\n \n \nBit 11 LCA: Loss of carrier\nWhen set, this bit indicates that a loss of carrier occurred during frame transmission (that is, \nthe MII_CRS signal was inactive for one or more transmit clock periods during frame \ntransmission). This is valid only for the frames transmitted without collision when the MAC \noperates in Half-duplex mode.\nBit 10 NC: No carrier\nWhen set, this bit indicates that the Carrier Sense signal form the PHY was not asserted \nduring transmission.\nBit 9 LCO: Late collision\nWhen set, this bit indicates that frame transmission was aborted due to a collision occurring \nafter the collision window (64 byte times, including preamble, in MII mode). This bit is not \nvalid if the Underflow Error bit is set.\nBit 8 EC: Excessive collision\nWhen set, this bit indicates that the transmission was aborted after 16 successive collisions \nwhile attempting to transmit the current frame. If the RD (Disable retry) bit in the MAC \nConfiguration register is set, this bit is set after the first collision, and the transmission of the \nframe is aborted.\nBit 7 VF: VLAN frame\nWhen set, this bit indicates that the transmitted frame was a VLAN-type frame.\nBits 6:3 CC: Collision count\nThis 4-bit counter value indicates the number of collisions occurring before the frame was \ntransmitted. The count is not valid when the Excessive collisions bit (TDES0[8]) is set.\nBit 2 ED: Excessive deferral\nWhen set, this bit indicates that the transmission has ended because of excessive deferral \nof over 24 288 bit times if the Deferral check (DC) bit in the MAC Control register is set high.\nBit 1 UF: Underflow error\nWhen set, this bit indicates that the MAC aborted the frame because data arrived late from \nthe RAM memory. Underflow error indicates that the DMA encountered an empty transmit \nbuffer while transmitting the frame. The transmission process enters the Suspended state \nand sets both Transmit underflow (ETH_DMASR[5]) and Transmit interrupt \n(ETH_DMASR[0]).\nBit 0 DB: Deferred bit\nWhen set, this bit indicates that the MAC defers before transmission because of the \npresence of the carrier. This bit is valid only in Half-duplex mode.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTBS2\nReserved\nTBS1\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw rw rw rw\nrw\nrw\nrw\n31:29 Reserved, must be kept at reset value.\n" }, { "page_number": 1178, "page_indices": { "start_index": 2312958, "end_index": 2315024 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1178 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.7 Tx DMA configuration", 1169 ], [ 4, "Normal Tx DMA descriptors", 1174 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1178/1757\nRM0090 Rev 21\n•\nTDES2: Transmit descriptor Word2\nTDES2 contains the address pointer to the first buffer of the descriptor or it contains \ntime stamp data.\n \n \n•\nTDES3: Transmit descriptor Word3\nTDES3 contains the address pointer either to the second buffer of the descriptor or the \nnext descriptor, or it contains time stamp data.\n \n28:16 TBS2: Transmit buffer 2 size\nThese bits indicate the second data buffer size in bytes. This field is not valid if TDES0[20] is \nset.\n15:13 Reserved, must be kept at reset value.\n12:0 TBS1: Transmit buffer 1 size\nThese bits indicate the first data buffer byte size, in bytes. If this field is 0, the DMA ignores \nthis buffer and uses Buffer 2 or the next descriptor, depending on the value of TCH \n(TDES0[20]).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTBAP1/TBAP/TTSL\nrw\nBits 31:0 TBAP1: Transmit buffer 1 address pointer / Transmit frame time stamp low\nThese bits have two different functions: they indicate to the DMA the location of data in \nmemory, and after all data are transferred, the DMA can then use these bits to pass back time \nstamp data.\nTBAP: When the software makes this descriptor available to the DMA (at the moment that the \nOWN bit is set to 1 in TDES0), these bits indicate the physical address of Buffer 1. There is no \nlimitation on the buffer address alignment. See Host data buffer alignment for further details on \nbuffer address alignment.\nTTSL: Before it clears the OWN bit in TDES0, the DMA updates this field with the 32 least \nsignificant bits of the time stamp captured for the corresponding transmit frame (overwriting \nthe value for TBAP1). This field has the time stamp only if time stamping is activated for this \nframe (see TTSE, TDES0 bit 25) and if the Last segment control bit (LS) in the descriptor is \nset.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTBAP2/TBAP2/TTSH\nrw\n" }, { "page_number": 1179, "page_indices": { "start_index": 2315024, "end_index": 2317197 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1179 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.7 Tx DMA configuration", 1169 ], [ 4, "Enhanced Tx DMA descriptors", 1179 ] ], "page_content": "RM0090 Rev 21\n1179/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n \nEnhanced Tx DMA descriptors\nEnhanced descriptors (enabled with EDFE=1, ETHDMABMR bit 7), must be used if time \nstamping is activated (TSE=1, ETH_PTPTSCR bit 0) or if IPv4 checksum offload is \nactivated (IPCO=1, ETH_MACCR bit 10).\nEnhanced descriptors comprise eight 32-bit words, twice the size of normal descriptors. \nTDES0, TDES1, TDES2 and TDES3 have the same definitions as for normal transmit \ndescriptors (refer to Normal Tx DMA descriptors). TDES6 and TDES7 hold the time stamp. \nTDES4, TDES5, TDES6 and TDES7 are defined below.\nWhen the Enhanced descriptor mode is selected, the software needs to allocate 32-bytes (8 \nwords) of memory for every descriptor. When time stamping or IPv4 checksum offload are \nnot being used, the enhanced descriptor format may be disabled and the software can use \nnormal descriptors with the default size of 16 bytes.\nBits 31:0 TBAP2: Transmit buffer 2 address pointer (Next descriptor address) / Transmit frame time \nstamp high\nThese bits have two different functions: they indicate to the DMA the location of data in \nmemory, and after all data are transferred, the DMA can then use these bits to pass back \ntime stamp data.\nTBAP2: When the software makes this descriptor available to the DMA (at the moment when \nthe OWN bit is set to 1 in TDES0), these bits indicate the physical address of Buffer 2 when a \ndescriptor ring structure is used. If the Second address chained (TDES1 [20]) bit is set, this \naddress contains the pointer to the physical memory where the next descriptor is present. The \nbuffer address pointer must be aligned to the bus width only when TDES1 [20] is set. (LSBs are \nignored internally.)\nTTSH: Before it clears the OWN bit in TDES0, the DMA updates this field with the 32 most \nsignificant bits of the time stamp captured for the corresponding transmit frame (overwriting \nthe value for TBAP2). This field has the time stamp only if time stamping is activated for this \nframe (see TDES0 bit 25, TTSE) and if the Last segment control bit (LS) in the descriptor is \nset.\n" }, { "page_number": 1180, "page_indices": { "start_index": 2317197, "end_index": 2318261 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1180 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.7 Tx DMA configuration", 1169 ], [ 4, "Enhanced Tx DMA descriptors", 1179 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1180/1757\nRM0090 Rev 21\nFigure 380. Enhanced transmit descriptor\n•\nTDES4: Transmit descriptor Word4\nReserved\n•\nTDES5: Transmit descriptor Word5\nReserved\n•\nTDES6: Transmit descriptor Word6\n \n \nTDES 3\nO\nW\nN\nCtrl\n[30:26]\nRes.\n24\nCtrl\n[23:20]\nReserved \n[19:18]\nStatus [16:0]\nReserved\n[31:29]\nBuffer 2 byte count\n[28:16]\nReserved\n[15:13]\nBuffer 1 byte count\n[12:0]\nBuffer 1 address [31:0] \nBuffer 2 address [31:0] or Next descriptor address [31:0] \nTDES 0\nTDES 1\nTDES 2\n31\n0\nai17105b\nT\nT\nS\nE\nT\nT\nS\nS\nTDES 7\nTDES 4\nTDES 5\nTDES 6\nReserved\nReserved\nTime stamp low [31:0]\nTime stamp high [31:0]\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTTSL\nrw\nBits 31:0 TTSL: Transmit frame time stamp low\nThis field is updated by DMA with the 32 least significant bits of the time stamp captured \nfor the corresponding transmit frame. This field has the time stamp only if the Last segment \ncontrol bit (LS) in the descriptor is set.\n" }, { "page_number": 1181, "page_indices": { "start_index": 2318261, "end_index": 2321299 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1181 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.8 Rx DMA configuration", 1181 ] ], "page_content": "RM0090 Rev 21\n1181/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n•\nTDES7: Transmit descriptor Word7\n \n \n33.6.8 \nRx DMA configuration\nThe Receive DMA engine’s reception sequence is illustrated in Figure 381 and described \nbelow:\n1.\nThe CPU sets up Receive descriptors (RDES0-RDES3) and sets the OWN bit \n(RDES0[31]). \n2. \nOnce the SR (ETH_DMAOMR register[1]) bit is set, the DMA enters the Run state. \nWhile in the Run state, the DMA polls the receive descriptor list, attempting to acquire \nfree descriptors. If the fetched descriptor is not free (is owned by the CPU), the DMA \nenters the Suspend state and jumps to Step 9.\n3. \nThe DMA decodes the receive data buffer address from the acquired descriptors.\n4. \nIncoming frames are processed and placed in the acquired descriptor’s data buffers.\n5. \nWhen the buffer is full or the frame transfer is complete, the Receive engine fetches the \nnext descriptor.\n6. \nIf the current frame transfer is complete, the DMA proceeds to step 7. If the DMA does \nnot own the next fetched descriptor and the frame transfer is not complete (EOF is not \nyet transferred), the DMA sets the Descriptor error bit in RDES0 (unless flushing is \ndisabled). The DMA closes the current descriptor (clears the OWN bit) and marks it as \nintermediate by clearing the Last segment (LS) bit in the RDES1 value (marks it as last \ndescriptor if flushing is not disabled), then proceeds to step 8. If the DMA owns the next \ndescriptor but the current frame transfer is not complete, the DMA closes the current \ndescriptor as intermediate and returns to step 4.\n7. \nIf IEEE 1588 time stamping is enabled, the DMA writes the time stamp (if available) to \nthe current descriptor’s RDES2 and RDES3. It then takes the received frame’s status \nand writes the status word to the current descriptor’s RDES0, with the OWN bit cleared \nand the Last segment bit set.\n8. \nThe Receive engine checks the latest descriptor’s OWN bit. If the CPU owns the \ndescriptor (OWN bit is at 0) the Receive buffer unavailable bit (in ETH_DMASR \nregister[7]) is set and the DMA Receive engine enters the Suspended state (step 9). If \nthe DMA owns the descriptor, the engine returns to step 4 and awaits the next frame.\n9. \nBefore the Receive engine enters the Suspend state, partial frames are flushed from \nthe Receive FIFO (you can control flushing using bit 24 in the ETH_DMAOMR \nregister).\n10. The Receive DMA exits the Suspend state when a Receive Poll demand is given or the \nstart of next frame is available from the Receive FIFO. The engine proceeds to step 2 \nand re-fetches the next descriptor.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTTSH\nrw\nBits 31:0 TTSH: Transmit frame time stamp high\nThis field is updated by DMA with the 32 most significant bits of the time stamp captured for \nthe corresponding transmit frame. This field has the time stamp only if the Last segment control \nbit (LS) in the descriptor is set.\n" }, { "page_number": 1182, "page_indices": { "start_index": 2321299, "end_index": 2322614 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1182 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.8 Rx DMA configuration", 1181 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1182/1757\nRM0090 Rev 21\nThe DMA does not acknowledge accepting the status until it has completed the time stamp \nwrite-back and is ready to perform status write-back to the descriptor. If software has \nenabled time stamping through CSR, when a valid time stamp value is not available for the \nframe (for example, because the receive FIFO was full before the time stamp could be \nwritten to it), the DMA writes all ones to RDES2 and RDES3. Otherwise (that is, if time \nstamping is not enabled), RDES2 and RDES3 remain unchanged.\nFigure 381. Receive DMA operation\n(Re-)Fetch next \ndescriptor\n(AHB)\nerror?\nNo\nOwn bit set?\nYes\nYes\nStop RxDMA\nStart RxDMA\nStart\n(AHB)\nerror?\nNo\nRxDMA suspended\nYes\nFrame data \navailable?\nWait for frame data\nWrite data to buffer(s)\nYes\nYes\nFetch next descriptor\nYes\nNo\nFrame transfer \ncomplete?\nNo\nSet descriptor error\nYes\nTime stamp \npresent?\nNo\nClose RDES0 as last \ndescriptor\nWrite time stamp to \nRDES2 & RDES3\nNo\n(AHB)\nerror?\nYes\nClose RDES0 as \nintermediate descriptor\nFrame transfer \ncomplete?\nNo\nFlush disabled?\nNo\nFlush the\nremaining frame\nYes\nYes\nNo\nNo\nNo\nYes\nYes\nPoll demand/\nnew frame available\nNo\nYes\n(AHB)\nerror?\n(AHB)\nerror?\nNo\nOwn bit set\nfor next desc?\nFlush \ndisabled?\nai15643\n" }, { "page_number": 1183, "page_indices": { "start_index": 2322614, "end_index": 2326009 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1183 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.8 Rx DMA configuration", 1181 ], [ 4, "Receive descriptor acquisition", 1183 ], [ 4, "Receive frame processing", 1183 ], [ 4, "Receive process suspended", 1183 ] ], "page_content": "RM0090 Rev 21\n1183/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nReceive descriptor acquisition\nThe receive engine always attempts to acquire an extra descriptor in anticipation of an \nincoming frame. Descriptor acquisition is attempted if any of the following conditions is/are \nsatisfied:\n•\nThe receive Start/Stop bit (ETH_DMAOMR register[1]) has been set immediately after \nthe DMA has been placed in the Run state.\n•\nThe data buffer of the current descriptor is full before the end of the frame currently \nbeing transferred\n•\nThe controller has completed frame reception, but the current receive descriptor has \nnot yet been closed.\n•\nThe receive process has been suspended because of a CPU-owned buffer \n(RDES0[31] = 0) and a new frame is received.\n•\nA Receive poll demand has been issued.\nReceive frame processing\nThe MAC transfers the received frames to the STM32F4xx memory only when the frame \npasses the address filter and the frame size is greater than or equal to the configurable \nthreshold bytes set for the Receive FIFO, or when the complete frame is written to the FIFO \nin Store-and-forward mode. If the frame fails the address filtering, it is dropped in the MAC \nblock itself (unless Receive All ETH_MACFFR [31] bit is set). Frames that are shorter than \n64 bytes, because of collision or premature termination, can be purged from the Receive \nFIFO. After 64 (configurable threshold) bytes have been received, the DMA block begins \ntransferring the frame data to the receive buffer pointed to by the current descriptor. The \nDMA sets the first descriptor (RDES0[9]) after the DMA AHB Interface becomes ready to \nreceive a data transfer (if DMA is not fetching transmit data from the memory), to delimit the \nframe. The descriptors are released when the OWN (RDES0[31]) bit is reset to 0, either as \nthe data buffer fills up or as the last segment of the frame is transferred to the receive buffer. \nIf the frame is contained in a single descriptor, both the last descriptor (RDES0[8]) and first \ndescriptor (RDES0[9]) bits are set. The DMA fetches the next descriptor, sets the last \ndescriptor (RDES0[8]) bit, and releases the RDES0 status bits in the previous frame \ndescriptor. Then the DMA sets the receive interrupt bit (ETH_DMASR register [6]). The \nsame process repeats unless the DMA encounters a descriptor flagged as being owned by \nthe CPU. If this occurs, the receive process sets the receive buffer unavailable bit \n(ETH_DMASR register[7]) and then enters the Suspend state. The position in the receive \nlist is retained.\nReceive process suspended\nIf a new receive frame arrives while the receive process is in Suspend state, the DMA re-\nfetches the current descriptor in the STM32F4xx memory. If the descriptor is now owned by \nthe DMA, the receive process re-enters the Run state and starts frame reception. If the \ndescriptor is still owned by the host, by default, the DMA discards the current frame at the \ntop of the Rx FIFO and increments the missed frame counter. If more than one frame is \nstored in the Rx FIFO, the process repeats. The discarding or flushing of the frame at the \ntop of the Rx FIFO can be avoided by setting the DMA Operation mode register bit 24 \n(DFRF). In such conditions, the receive process sets the receive buffer unavailable status \nbit and returns to the Suspend state.\n" }, { "page_number": 1184, "page_indices": { "start_index": 2326009, "end_index": 2328048 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1184 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.8 Rx DMA configuration", 1181 ], [ 4, "Normal Rx DMA descriptors", 1184 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1184/1757\nRM0090 Rev 21\nNormal Rx DMA descriptors\nThe normal receive descriptor structure consists of four 32-bit words (16 bytes). These are \nshown in Figure 382. The bit descriptions of RDES0, RDES1, RDES2 and RDES3 are given \nbelow.\nNote that enhanced descriptors must be used if time stamping is activated (TSE=1, \nETH_PTPTSCR bit 0) or if IPv4 checksum offload is activated (IPCO=1, ETH_MACCR bit \n10).\nFigure 382. Normal Rx DMA descriptor structure\n•\nRDES0: Receive descriptor Word0\nRDES0 contains the received frame status, the frame length and the descriptor \nownership information.\n \n \nRDES 3\nO\nW\nN\nStatus [30:0]\nReserved\n[30:29]\nBuffer 2 byte count\n[28:16]\nCTRL\n[15:14]\nBuffer 1 byte count\n[12:0]\nBuffer 1 address [31:0]\nBuffer 2 address [31:0] or Next descriptor address [31:0]\nRDES 0\nRDES 1\nRDES 2\n31\n0\nai15644\nRes.\nCT\nRL\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOWN\nAFM\nFL\nES\nDE\nSAF\nLE\nOE\nVLAN\nFS\nLS\nIPHCE/TSV\nLCO\nFT\nRWT\nRE\nDE\nCE\nPCE/ESA\nrw\nBit 31 OWN: Own bit\nWhen set, this bit indicates that the descriptor is owned by the DMA of the MAC Subsystem. \nWhen this bit is reset, it indicates that the descriptor is owned by the Host. The DMA clears this bit \neither when it completes the frame reception or when the buffers that are associated with this \ndescriptor are full.\nBit 30 AFM: Destination address filter fail\nWhen set, this bit indicates a frame that failed the DA filter in the MAC Core.\nBits 29:16 FL: Frame length\nThese bits indicate the byte length of the received frame that was transferred to host memory \n(including CRC). This field is valid only when last descriptor (RDES0[8]) is set and descriptor error \n(RDES0[14]) is reset.\nThis field is valid when last descriptor (RDES0[8]) is set. When the last descriptor and error \nsummary bits are not set, this field indicates the accumulated number of bytes that have been \ntransferred for the current frame.\n" }, { "page_number": 1185, "page_indices": { "start_index": 2328048, "end_index": 2330773 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1185 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.8 Rx DMA configuration", 1181 ], [ 4, "Normal Rx DMA descriptors", 1184 ] ], "page_content": "RM0090 Rev 21\n1185/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nBit 15 ES: Error summary\nIndicates the logical OR of the following bits:\nRDES0[1]: CRC error\nRDES0[3]: Receive error\nRDES0[4]: Watchdog timeout\nRDES0[6]: Late collision\nRDES0[7]: Giant frame (This is not applicable when RDES0[7] indicates an IPV4 header \nchecksum error.)\n RDES0[11]: Overflow error\n RDES0[14]: Descriptor error.\nThis field is valid only when the last descriptor (RDES0[8]) is set.\nBit 14 DE: Descriptor error\nWhen set, this bit indicates a frame truncation caused by a frame that does not fit within the current \ndescriptor buffers, and that the DMA does not own the next descriptor. The frame is truncated. \nThis field is valid only when the last descriptor (RDES0[8]) is set.\nBit 13 SAF: Source address filter fail\nWhen set, this bit indicates that the SA field of frame failed the SA filter in the MAC Core.\nBit 12 LE: Length error\nWhen set, this bit indicates that the actual length of the received frame does not match the value in \nthe Length/ Type field. This bit is valid only when the Frame type (RDES0[5]) bit is reset.\nBit 11 OE: Overflow error\nWhen set, this bit indicates that the received frame was damaged due to buffer overflow.\nBit 10 VLAN: VLAN tag\nWhen set, this bit indicates that the frame pointed to by this descriptor is a VLAN frame tagged \nby the MAC core.\nBit 9 FS: First descriptor\nWhen set, this bit indicates that this descriptor contains the first buffer of the frame. If the size of the \nfirst buffer is 0, the second buffer contains the beginning of the frame. If the size of the second buffer \nis also 0, the next descriptor contains the beginning of the frame.\nBit 8 LS: Last descriptor\nWhen set, this bit indicates that the buffers pointed to by this descriptor are the last buffers of \nthe frame.\nBit 7 IPHCE/TSV: IPv header checksum error / time stamp valid\nIf IPHCE is set, it indicates an error in the IPv4 or IPv6 header. This error can be due to inconsistent \nEthernet Type field and IP header Version field values, a header checksum mismatch in IPv4, or an \nEthernet frame lacking the expected number of IP header bytes. This bit can take on special \nmeaning as specified in Table 194.\nIf enhanced descriptor format is enabled (EDFE=1, bit 7 of ETH_DMABMR), this bit takes on \nthe TSV function (otherwise it is IPHCE). When TSV is set, it indicates that a snapshot of the \ntimestamp is written in descriptor words 6 (RDES6) and 7 (RDES7). TSV is valid only when \nthe Last descriptor bit (RDES0[8]) is set.\nBit 6 LCO: Late collision\nWhen set, this bit indicates that a late collision has occurred while receiving the frame in Half-\nduplex mode.\n" }, { "page_number": 1186, "page_indices": { "start_index": 2330773, "end_index": 2332867 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1186 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.8 Rx DMA configuration", 1181 ], [ 4, "Normal Rx DMA descriptors", 1184 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1186/1757\nRM0090 Rev 21\nBits 5, 7, and 0 reflect the conditions discussed in Table 194.\nBit 5 FT: Frame type\nWhen set, this bit indicates that the Receive frame is an Ethernet-type frame (the LT field is greater \nthan or equal to 0x0600). When this bit is reset, it indicates that the received frame is an \nIEEE802.3 frame. This bit is not valid for Runt frames less than 14 bytes. When the normal \ndescriptor format is used (ETH_DMABMR EDFE=0), FT can take on special meaning as \nspecified in Table 194.\nBit 4 RWT: Receive watchdog timeout\nWhen set, this bit indicates that the Receive watchdog timer has expired while receiving the \ncurrent frame and the current frame is truncated after the watchdog timeout.\nBit 3 RE: Receive error\nWhen set, this bit indicates that the RX_ERR signal is asserted while RX_DV is asserted \nduring frame reception.\nBit 2 DE: Dribble bit error\nWhen set, this bit indicates that the received frame has a non-integer multiple of bytes (odd \nnibbles). This bit is valid only in MII mode.\nBit 1 CE: CRC error\nWhen set, this bit indicates that a cyclic redundancy check (CRC) error occurred on the \nreceived frame. This field is valid only when the last descriptor (RDES0[8]) is set.\nBit 0 PCE/ESA: Payload checksum error / extended status available\nWhen set, it indicates that the TCP, UDP or ICMP checksum the core calculated does not \nmatch the received encapsulated TCP, UDP or ICMP segment’s Checksum field. This bit is \nalso set when the received number of payload bytes does not match the value indicated in \nthe Length field of the encapsulated IPv4 or IPv6 datagram in the received Ethernet frame. \nThis bit can take on special meaning as specified in Table 194.\nIf the enhanced descriptor format is enabled (EDFE=1, bit 7 in ETH_DMABMR), this bit takes \non the ESA function (otherwise it is PCE). When ESA is set, it indicates that the extended \nstatus is available in descriptor word 4 (RDES4). ESA is valid only when the last descriptor bit \n(RDES0[8]) is set.\n" }, { "page_number": 1187, "page_indices": { "start_index": 2332867, "end_index": 2335076 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1187 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.8 Rx DMA configuration", 1181 ], [ 4, "Normal Rx DMA descriptors", 1184 ] ], "page_content": "RM0090 Rev 21\n1187/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n \n•\nRDES1: Receive descriptor Word1\n \n \nTable 194. Receive descriptor 0 - encoding for bits 7, 5 and 0 (normal descriptor\nformat only, EDFE=0)\nBit 5: \nframe \ntype\nBit 7: IPC \nchecksum \nerror\nBit 0: payload \nchecksum \nerror\nFrame status\n0\n0\n0\nIEEE 802.3 Type frame (Length field value is less than \n0x0600.)\n1\n0\n0\nIPv4/IPv6 Type frame, no checksum error detected\n1\n0\n1\nIPv4/IPv6 Type frame with a payload checksum error (as described \nfor PCE) detected\n1\n1\n0\nIPv4/IPv6 Type frame with an IP header checksum error (as \ndescribed for IPC CE) detected\n1\n1\n1\nIPv4/IPv6 Type frame with both IP header and payload checksum \nerrors detected\n0\n0\n1\nIPv4/IPv6 Type frame with no IP header checksum error and the \npayload check bypassed, due to an unsupported payload\n0\n1\n1\nA Type frame that is neither IPv4 or IPv6 (the checksum offload \nengine bypasses checksum completely.)\n0\n1\n0\nReserved\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDIC\nRBS2\nRBS2\nRER\nRCH\nReserved\nRBS\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw rw rw rw\nrw\nrw\nrw\nBit 31 DIC: Disable interrupt on completion\nWhen set, this bit prevents setting the Status register’s RS bit (CSR5[6]) for the received frame \nending in the buffer indicated by this descriptor. This, in turn, disables the assertion of the interrupt to \nHost due to RS for that frame.\nBits 30:29 Reserved, must be kept at reset value.\nBits 28:16 RBS2: Receive buffer 2 size\nThese bits indicate the second data buffer size, in bytes. The buffer size must be a multiple of 4, \n8, or 16, depending on the bus widths (32, 64 or 128, respectively), even if the value of RDES3 \n(buffer2 address pointer) is not aligned to bus width. If the buffer size is not an appropriate multiple \nof 4, 8 or 16, the resulting behavior is undefined. This field is not valid if RDES1 [14] is set.\nBit 15 RER: Receive end of ring\nWhen set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to the \nbase address of the list, creating a descriptor ring.\n" }, { "page_number": 1188, "page_indices": { "start_index": 2335076, "end_index": 2337783 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1188 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.8 Rx DMA configuration", 1181 ], [ 4, "Normal Rx DMA descriptors", 1184 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1188/1757\nRM0090 Rev 21\n•\nRDES2: Receive descriptor Word2\nRDES2 contains the address pointer to the first data buffer in the descriptor, or it \ncontains time stamp data.\n \n \nBit 14 RCH: Second address chained\nWhen set, this bit indicates that the second address in the descriptor is the next descriptor address \nrather than the second buffer address. When this bit is set, RBS2 (RDES1[28:16]) is a “don’t \ncare” value. RDES1[15] takes precedence over RDES1[14].\nBit 13 Reserved, must be kept at reset value.\nBits 12:0 RBS1: Receive buffer 1 size\nIndicates the first data buffer size in bytes. The buffer size must be a multiple of 4, 8 or 16, \ndepending upon the bus widths (32, 64 or 128), even if the value of RDES2 (buffer1 address \npointer) is not aligned. When the buffer size is not a multiple of 4, 8 or 16, the resulting behavior is \nundefined. If this field is 0, the DMA ignores this buffer and uses Buffer 2 or next descriptor \ndepending on the value of RCH (bit 14).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRBP1 / RTSL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw rw rw rw\nrw\nrw\nrw\nBits 31:0 RBAP1 / RTSL: Receive buffer 1 address pointer / Receive frame time stamp low\nThese bits take on two different functions: the application uses them to indicate to the DMA \nwhere to store the data in memory, and then after transferring all the data the DMA may use \nthese bits to pass back time stamp data.\nRBAP1: When the software makes this descriptor available to the DMA (at the moment that \nthe OWN bit is set to 1 in RDES0), these bits indicate the physical address of Buffer 1. There are \nno limitations on the buffer address alignment except for the following condition: the DMA uses the \nconfigured value for its address generation when the RDES2 value is used to store the start of \nframe. Note that the DMA performs a write operation with the RDES2[3/2/1:0] bits as 0 during the \ntransfer of the start of frame but the frame data is shifted as per the actual buffer address pointer. The \nDMA ignores RDES2[3/2/1:0] (corresponding to bus width of 128/64/32) if the address pointer is to \na buffer where the middle or last part of the frame is stored.\nRTSL: Before it clears the OWN bit in RDES0, the DMA updates this field with the 32 least \nsignificant bits of the time stamp captured for the corresponding receive frame (overwriting \nthe value for RBAP1). This field has the time stamp only if time stamping is activated for this \nframe and if the Last segment control bit (LS) in the descriptor is set.\n" }, { "page_number": 1189, "page_indices": { "start_index": 2337783, "end_index": 2340917 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1189 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.8 Rx DMA configuration", 1181 ], [ 4, "Enhanced Rx DMA descriptors format with IEEE1588 time stamp", 1189 ] ], "page_content": "RM0090 Rev 21\n1189/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n•\nRDES3: Receive descriptor Word3\nRDES3 contains the address pointer either to the second data buffer in the descriptor \nor to the next descriptor, or it contains time stamp data.\n \n \nEnhanced Rx DMA descriptors format with IEEE1588 time stamp\nEnhanced descriptors (enabled with EDFE=1, ETHDMABMR bit 7), must be used if time \nstamping is activated (TSE=1, ETH_PTPTSCR bit 0) or if IPv4 checksum offload is \nactivated (IPCO=1, ETH_MACCR bit 10).\nEnhanced descriptors comprise eight 32-bit words, twice the size of normal descriptors. \nRDES0, RDES1, RDES2 and RDES3 have the same definitions as for normal receive \ndescriptors (refer to Normal Rx DMA descriptors). RDES4 contains extended status while \nRDES6 and RDES7 hold the time stamp. RDES4, RDES5, RDES6 and RDES7 are defined \nbelow.\nWhen the Enhanced descriptor mode is selected, the software needs to allocate 32 bytes (8 \nwords) of memory for every descriptor. When time stamping or IPv4 checksum offload are \nnot being used, the enhanced descriptor format may be disabled and the software can use \nnormal descriptors with the default size of 16 bytes.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRBP2 / RTSH\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw rw rw rw\nrw\nrw\nrw\nBits 31:0 RBAP2 / RTSH: Receive buffer 2 address pointer (next descriptor address) / Receive frame \ntime stamp high\nThese bits take on two different functions: the application uses them to indicate to the DMA \nthe location of where to store the data in memory, and then after transferring all the data the \nDMA may use these bits to pass back time stamp data.\nRBAP1: When the software makes this descriptor available to the DMA (at the moment that \nthe OWN bit is set to 1 in RDES0), these bits indicate the physical address of buffer 2 when a \ndescriptor ring structure is used. If the second address chained (RDES1 [24]) bit is set, this address \ncontains the pointer to the physical memory where the next descriptor is present. If RDES1 [24] is \nset, the buffer (next descriptor) address pointer must be bus width-aligned (RDES3[3, 2, or \n1:0] = 0, corresponding to a bus width of 128, 64 or 32. LSBs are ignored internally.) \nHowever, when RDES1 [24] is reset, there are no limitations on the RDES3 value, except for the \nfollowing condition: the DMA uses the configured value for its buffer address generation when the \nRDES3 value is used to store the start of frame. The DMA ignores RDES3[3, 2, or 1:0] \n(corresponding to a bus width of 128, 64 or 32) if the address pointer is to a buffer where the \nmiddle or last part of the frame is stored.\nRTSH: Before it clears the OWN bit in RDES0, the DMA updates this field with the 32 most \nsignificant bits of the time stamp captured for the corresponding receive frame (overwriting \nthe value for RBAP2). This field has the time stamp only if time stamping is activated and if \nthe Last segment control bit (LS) in the descriptor is set.\n" }, { "page_number": 1190, "page_indices": { "start_index": 2340917, "end_index": 2342067 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1190 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.8 Rx DMA configuration", 1181 ], [ 4, "Enhanced Rx DMA descriptors format with IEEE1588 time stamp", 1189 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1190/1757\nRM0090 Rev 21\nFigure 383. Enhanced receive descriptor field format with IEEE1588 time stamp \nenabled\n•\nRDES4: Receive descriptor Word4\nThe extended status, shown below, is valid only when there is status related to IPv4 \nchecksum or time stamp available as indicated by bit 0 in RDES0.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPV\nPFT\nPMT\nIPV6PR\nIPV4PR\nIPCB\nIPPE\nIPHE\nIPPT\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw rw rw rw\nrw\nrw\nrw\nBits 31:14 Reserved, must be kept at reset value.\nBit 13 PV: PTP version\nWhen set, indicates that the received PTP message uses the IEEE 1588 version 2 format. \nWhen cleared, it uses version 1 format. This is valid only if the message type is non-zero.\nBit 12 PFT: PTP frame type\nWhen set, this bit indicates that the PTP message is sent directly over Ethernet. When this bit \nis cleared and the message type is non-zero, it indicates that the PTP message is sent over \nUDP-IPv4 or UDP-IPv6. The information on IPv4 or IPv6 can be obtained from bits 6 and 7.\n" }, { "page_number": 1191, "page_indices": { "start_index": 2342067, "end_index": 2344282 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1191 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.8 Rx DMA configuration", 1181 ], [ 4, "Enhanced Rx DMA descriptors format with IEEE1588 time stamp", 1189 ] ], "page_content": "RM0090 Rev 21\n1191/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n•\nRDES5: Receive descriptor Word5\nReserved.\n•\nRDES6: Receive descriptor Word6\nThe table below describes the fields that have different meaning for RDES6 when the \nreceive descriptor is closed and time stamping is enabled.\nBits 11:8 PMT: PTP message type\nThese bits are encoded to give the type of the message received.\n– 0000: No PTP message received\n– 0001: SYNC (all clock types)\n– 0010: Follow_Up (all clock types)\n– 0011: Delay_Req (all clock types)\n– 0100: Delay_Resp (all clock types)\n– 0101: Pdelay_Req (in peer-to-peer transparent clock) or Announce (in ordinary or boundary \nclock)\n– 0110: Pdelay_Resp (in peer-to-peer transparent clock) or Management (in ordinary or \nboundary clock)\n– 0111: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock) or Signaling (for ordinary \nor boundary clock)\n– 1xxx - Reserved\nBit 7 IPV6PR: IPv6 packet received\nWhen set, this bit indicates that the received packet is an IPv6 packet.\nBit 6 IPV4PR: IPv4 packet received\nWhen set, this bit indicates that the received packet is an IPv4 packet.\nBit 5 IPCB: IP checksum bypassed\nWhen set, this bit indicates that the checksum offload engine is bypassed.\nBit 4 IPPE: IP payload error\nWhen set, this bit indicates that the 16-bit IP payload checksum (that is, the TCP, UDP, or \nICMP checksum) that the core calculated does not match the corresponding checksum field \nin the received segment. It is also set when the TCP, UDP, or ICMP segment length does not \nmatch the payload length value in the IP Header field.\nBit 3 IPHE: IP header error\nWhen set, this bit indicates either that the 16-bit IPv4 header checksum calculated by the \ncore does not match the received checksum bytes, or that the IP datagram version is not \nconsistent with the Ethernet Type value.\nBits 2:0 IPPT: IP payload type\nif IPv4 checksum offload is activated (IPCO=1, ETH_MACCR bit 10), these bits \nindicate the type of payload encapsulated in the IP datagram. These bits are ‘00’ if there is an IP \nheader error or fragmented IP.\n– 000: Unknown or did not process IP payload\n– 001: UDP\n– 010: TCP\n– 011: ICMP\n– 1xx: Reserved\n" }, { "page_number": 1192, "page_indices": { "start_index": 2344282, "end_index": 2347514 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1192 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.6 Ethernet functional description: DMA controller operation", 1166 ], [ 3, "33.6.9 DMA interrupts", 1192 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1192/1757\nRM0090 Rev 21\n \n .\n•\nRDES7: Receive descriptor Word7\nThe table below describes the fields that have a different meaning for RDES7 when the \nreceive descriptor is closed and time stamping is enabled.\n \n .\n33.6.9 \nDMA interrupts\nInterrupts can be generated as a result of various events. The ETH_DMASR register \ncontains all the bits that might cause an interrupt. The ETH_DMAIER register contains an \nenable bit for each of the events that can cause an interrupt.\nThere are two groups of interrupts, Normal and Abnormal, as described in the ETH_DMASR \nregister. Interrupts are cleared by writing a 1 to the corresponding bit position. When all the \nenabled interrupts within a group are cleared, the corresponding summary bit is cleared. If \nthe MAC core is the cause for assertion of the interrupt, then any of the TSTS or PMTS bits \nin the ETH_DMASR register is set high.\nInterrupts are not queued and if the interrupt event occurs before the driver has responded \nto it, no additional interrupts are generated. For example, the Receive Interrupt bit \n(ETH_DMASR register [6]) indicates that one or more frames were transferred to the \nSTM32F4xx buffer. The driver must scan all descriptors, from the last recorded position to \nthe first one owned by the DMA.\nAn interrupt is generated only once for simultaneous, multiple events. The driver must scan \nthe ETH_DMASR register for the cause of the interrupt. The interrupt is not generated again \nunless a new interrupting event occurs, after the driver has cleared the appropriate bit in the \nETH_DMASR register. For example, the controller generates a Receive interrupt \n(ETH_DMASR register[6]) and the driver begins reading the ETH_DMASR register. Next, \nreceive buffer unavailable (ETH_DMASR register[7]) occurs. The driver clears the Receive \ninterrupt. Even then, a new interrupt is generated, due to the active or pending Receive \nbuffer unavailable interrupt.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRTSL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw rw rw rw\nrw\nrw\nrw\nBits 31:0 RTSL: Receive frame time stamp low\nThe DMA updates this field with the 32 least significant bits of the time stamp captured for the \ncorresponding receive frame. The DMA updates this field only for the last descriptor of the receive \nframe indicated by last descriptor status bit (RDES0[8]). When this field and the RTSH field in \nRDES7 show all ones, the time stamp must be treated as corrupt.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRTSH\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw rw rw rw\nrw\nrw\nrw\nBits 31:0 RTSH: Receive frame time stamp high\nThe DMA updates this field with the 32 most significant bits of the time stamp captured for the \ncorresponding receive frame. The DMA updates this field only for the last descriptor of the receive \nframe indicated by last descriptor status bit (RDES0[8]).\nWhen this field and RDES7’s RTSL field show all ones, the time stamp must be treated as \ncorrupt.\n" }, { "page_number": 1193, "page_indices": { "start_index": 2347514, "end_index": 2349441 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1193 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.7 Ethernet interrupts", 1193 ] ], "page_content": "RM0090 Rev 21\n1193/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nFigure 384. Interrupt scheme\n33.7 \nEthernet interrupts\nThe Ethernet controller has two interrupt vectors: one dedicated to normal Ethernet \noperations and the other, used only for the Ethernet wake-up event (with wake-up frame or \nMagic Packet detection) when it is mapped on EXTI lIne19.\nThe first Ethernet vector is reserved for interrupts generated by the MAC and the DMA as \nlisted in the MAC interrupts and DMA interrupts sections.\nThe second vector is reserved for interrupts generated by the PMT on wake-up events. The \nmapping of a wake-up event on EXTI line19 causes the STM32F4xx to exit the low-power \nmode, and generates an interrupt.\nWhen an Ethernet wake-up event mapped on EXTI Line19 occurs and the MAC PMT \ninterrupt is enabled and the EXTI Line19 interrupt, with detection on rising edge, is also \nenabled, both interrupts are generated.\nA watchdog timer (see ETH_DMARSWTR register) is given for flexible control of the RS bit \n(ETH_DMASR register). When this watchdog timer is programmed with a non-zero value, it \ngets activated as soon as the RxDMA completes a transfer of a received frame to system \nmemory without asserting the Receive Status because it is not enabled in the corresponding \nReceive descriptor (RDES1[31]). When this timer runs out as per the programmed value, \nthe RS bit is set and the interrupt is asserted if the corresponding RIE is enabled in the \nETH_DMAIER register. This timer is disabled before it runs out, when a frame is transferred \nto memory and the RS is set because it is enabled for that descriptor.\nAND\nAND\nOR\nOR\nAND\nNIS\nNISE\nAND\nAIS\nAISE\nOR\nInterrupt\nTS\nTIE\nFBES\nFBEIE\nAI15646\nPMTI\nTSTI\nMMCI\nAND\nTBUS\nTBUIE\nAND\nRS\nRIE\nAND\nERS\nERIE\nAND\nTPSS\nTPSSIE\nAND\nTJTS\nTJTIE\nAND\nROS\nROIE\nAND\nTUS\nTUIE\nAND\nRBU\nRBUIE\nAND\nRPSS\nRPSSIE\nAND\nRWTS\nRWTIE\nAND\nETS\nETIE\n" }, { "page_number": 1194, "page_indices": { "start_index": 2349441, "end_index": 2351960 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1194 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC configuration register (ETH_MACCR)", 1194 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1194/1757\nRM0090 Rev 21\nNote:\nReading the PMT control and status register automatically clears the Wake-up Frame \nReceived and Magic Packet Received PMT interrupt flags. However, since the registers for \nthese flags are in the CLK_RX domain, there may be a significant delay before this update \nis visible by the firmware. The delay is especially long when the RX clock is slow (in 10 Mbit \nmode) and when the AHB bus is high-frequency.\nSince interrupt requests from the PMT to the CPU are based on the same registers in the \nCLK_RX domain, the CPU may spuriously call the interrupt routine a second time even after \nreading PMT_CSR. Thus, it may be necessary that the firmware polls the Wake-up Frame \nReceived and Magic Packet Received bits and exits the interrupt service routine only when \nthey are found to be at ‘0’.\n33.8 \nEthernet register descriptions\nThe peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32-\nbits).\n33.8.1 \nMAC register description\nEthernet MAC configuration register (ETH_MACCR)\nAddress offset: 0x0000\nReset value: 0x0000 8000\nThe MAC configuration register is the operation mode register of the MAC. It establishes \nreceive and transmit operating modes.\n \n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCSTF\nReserved\nWD\nJD\nReserved\nIFG\nCSD\nReserved\nFES\nROD\nLM\nDM\nIPCO\nRD\nReserved\nAPCS\nBL\nDC\nTE\nRE\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:26 Reserved, must be kept at reset value.\nBit 25\nCSTF: CRC stripping for Type frames\nWhen set, the last 4 bytes (FCS) of all frames of Ether type (type field greater than 0x0600) \nare stripped and dropped before forwarding the frame to the application. \nBit 24Reserved, must be kept at reset value.\nBit 23 WD: Watchdog disable\nWhen this bit is set, the MAC disables the watchdog timer on the receiver, and can receive \nframes of up to 16 384 bytes.\nWhen this bit is reset, the MAC allows no more than 2 048 bytes of the frame being received \nand cuts off any bytes received after that.\nBit 22 JD: Jabber disable\nWhen this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer \nframes of up to 16 384 bytes.\nWhen this bit is reset, the MAC cuts off the transmitter if the application sends out more than \n2 048 bytes of data during transmission.\nBits 21:20 Reserved, must be kept at reset value.\n" }, { "page_number": 1195, "page_indices": { "start_index": 2351960, "end_index": 2354319 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1195 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC configuration register (ETH_MACCR)", 1194 ] ], "page_content": "RM0090 Rev 21\n1195/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nBits 19:17 IFG: Interframe gap\nThese bits control the minimum interframe gap between frames during transmission.\n000: 96 bit times\n001: 88 bit times\n010: 80 bit times\n….\n111: 40 bit times\nNote: In Half-duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) \nonly. Lower values are not considered.\nBit 16 CSD: Carrier sense disable\nWhen set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame \ntransmission in Half-duplex mode. No error is generated due to Loss of Carrier or No Carrier \nduring such transmission.\nWhen this bit is low, the MAC transmitter generates such errors due to Carrier Sense and \neven aborts the transmissions.\nBit 15 Reserved, must be kept at reset value.\nBit 14 FES: Fast Ethernet speed\nIndicates the speed in Fast Ethernet (MII) mode:\n0: 10 Mbit/s\n1: 100 Mbit/s \nBit 13 ROD: Receive own disable\nWhen this bit is set, the MAC disables the reception of frames in Half-duplex mode.\nWhen this bit is reset, the MAC receives all packets that are given by the PHY while \ntransmitting.\nThis bit is not applicable if the MAC is operating in Full-duplex mode.\nBit 12 LM: Loopback mode\nWhen this bit is set, the MAC operates in loopback mode at the MII. The MII receive clock \ninput (RX_CLK) is required for the loopback to work properly, as the transmit clock is not \nlooped-back internally.\nBit 11 DM: Duplex mode\nWhen this bit is set, the MAC operates in a Full-duplex mode where it can transmit and \nreceive simultaneously.\nBit 10 IPCO: IPv4 checksum offload\nWhen set, this bit enables IPv4 checksum checking for received frame payloads' \nTCP/UDP/ICMP headers. When this bit is reset, the checksum offload function in the \nreceiver is disabled and the corresponding PCE and IP HCE status bits (see Table 191) are \nalways cleared.\nBit 9 RD: Retry disable\nWhen this bit is set, the MAC attempts only 1 transmission. When a collision occurs on the \nMII, the MAC ignores the current frame transmission and reports a Frame Abort with \nexcessive collision error in the transmit frame status.\nWhen this bit is reset, the MAC attempts retries based on the settings of BL.\nNote: This bit is applicable only in the Half-duplex mode.\nBit 8 Reserved, must be kept at reset value.\n" }, { "page_number": 1196, "page_indices": { "start_index": 2354319, "end_index": 2356846 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1196 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC configuration register (ETH_MACCR)", 1194 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1196/1757\nRM0090 Rev 21\nBit 7 APCS: Automatic pad/CRC stripping\nWhen this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the \nlength’s field value is less than or equal to 1 500 bytes. All received frames with length field \ngreater than or equal to 1 501 bytes are passed on to the application without stripping the \nPad/FCS field.\nWhen this bit is reset, the MAC passes all incoming frames unmodified.\nBits 6:5 BL: Back-off limit\nThe Back-off limit determines the random integer number (r) of slot time delays (4 096 bit \ntimes for 1000 Mbit/s and 512 bit times for 10/100 Mbit/s) the MAC waits before \nrescheduling a transmission attempt during retries after a collision.\nNote: This bit is applicable only to Half-duplex mode.\n00: k = min (n, 10)\n01: k = min (n, 8)\n10: k = min (n, 4)\n11: k = min (n, 1),\nwhere n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < \n2k\nBit 4 DC: Deferral check\nWhen this bit is set, the deferral check function is enabled in the MAC. The MAC issues a \nFrame Abort status, along with the excessive deferral error bit set in the transmit frame \nstatus when the transmit state machine is deferred for more than 24 288 bit times in 10/100-\nMbit/s mode. Deferral begins when the transmitter is ready to transmit, but is prevented \nbecause of an active CRS (carrier sense) signal on the MII. Defer time is not cumulative. If \nthe transmitter defers for 10 000 bit times, then transmits, collides, backs off, and then has \nto defer again after completion of back-off, the deferral timer resets to 0 and restarts.\nWhen this bit is reset, the deferral check function is disabled and the MAC defers until the \nCRS signal goes inactive. This bit is applicable only in Half-duplex mode.\nBit 3 TE: Transmitter enable\nWhen this bit is set, the transmit state machine of the MAC is enabled for transmission on \nthe MII. When this bit is reset, the MAC transmit state machine is disabled after the \ncompletion of the transmission of the current frame, and does not transmit any further \nframes.\nBit 2 RE: Receiver enable\nWhen this bit is set, the receiver state machine of the MAC is enabled for receiving frames \nfrom the MII. When this bit is reset, the MAC receive state machine is disabled after the \ncompletion of the reception of the current frame, and does not receive any further frames \nfrom the MII.\nBits 1:0 Reserved, must be kept at reset value.\n" }, { "page_number": 1197, "page_indices": { "start_index": 2356846, "end_index": 2359235 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1197 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC frame filter register (ETH_MACFFR)", 1197 ] ], "page_content": "RM0090 Rev 21\n1197/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet MAC frame filter register (ETH_MACFFR)\nAddress offset: 0x0004\nReset value: 0x0000 0000\nThe MAC frame filter register contains the filter controls for receiving frames. Some of the \ncontrols from this register go to the address check block of the MAC, which performs the \nfirst level of address filtering. The second level of filtering is performed on the incoming \nframe, based on other controls such as pass bad frames and pass control frames.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRA\nReserved\nHPF\nSAF\nSAIF\nPCF\nBFD\nPAM\nDAIF\nHM\nHU\nPM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 RA: Receive all\nWhen this bit is set, the MAC receiver passes all received frames on to the application, \nirrespective of whether they have passed the address filter. The result of the SA/DA filtering \nis updated (pass or fail) in the corresponding bits in the receive status word. When this bit is \nreset, the MAC receiver passes on to the application only those frames that have passed the \nSA/DA address filter.\nBits 30:11 Reserved, must be kept at reset value.\nBit 10 HPF: Hash or perfect filter\nWhen this bit is set and if the HM or HU bit is set, the address filter passes frames that \nmatch either the perfect filtering or the hash filtering.\nWhen this bit is cleared and if the HU or HM bit is set, only frames that match the Hash filter \nare passed.\nBit 9 SAF: Source address filter\nThe MAC core compares the SA field of the received frames with the values programmed in \nthe enabled SA registers. If the comparison matches, then the SAMatch bit in the RxStatus \nword is set high. When this bit is set high and the SA filter fails, the MAC drops the frame.\nWhen this bit is reset, the MAC core forwards the received frame to the application. It also \nforwards the updated SA Match bit in RxStatus depending on the SA address comparison.\nBit 8 SAIF: Source address inverse filtering\nWhen this bit is set, the address check block operates in inverse filtering mode for the SA \naddress comparison. The frames whose SA matches the SA registers are marked as failing \nthe SA address filter.\nWhen this bit is reset, frames whose SA does not match the SA registers are marked as \nfailing the SA address filter.\n" }, { "page_number": 1198, "page_indices": { "start_index": 2359235, "end_index": 2362420 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1198 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC hash table high register (ETH_MACHTHR)", 1198 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1198/1757\nRM0090 Rev 21\nEthernet MAC hash table high register (ETH_MACHTHR)\nAddress offset: 0x0008\nReset value: 0x0000 0000\nThe 64-bit Hash table is used for group address filtering. For hash filtering, the contents of \nthe destination address in the incoming frame are passed through the CRC logic, and the \nupper 6 bits in the CRC register are used to index the contents of the Hash table. This CRC \nis a 32-bit value coded by the following polynomial (for more details refer to Section 33.5.3):\nBits 7:6 PCF: Pass control frames\nThese bits control the forwarding of all control frames (including unicast and multicast \nPAUSE frames). Note that the processing of PAUSE control frames depends only on RFCE \nin Flow Control Register[2].\n00: MAC prevents all control frames from reaching the application\n01: MAC forwards all control frames to application except Pause control frames \n10: MAC forwards all control frames to application even if they fail the address filter\n11: MAC forwards control frames that pass the address filter.\nThese bits control the forwarding of all control frames (including unicast and multicast \nPAUSE frames). Note that the processing of PAUSE control frames depends only on RFCE \nin Flow Control register[2].\n00 or 01: MAC prevents all control frames from reaching the application\n10: MAC forwards all control frames to application even if they fail the address filter\n11: MAC forwards control frames that pass the address filter.\nBit 5 BFD: Broadcast frames disable\nWhen this bit is set, the address filters filter all incoming broadcast frames.\nWhen this bit is reset, the address filters pass all received broadcast frames.\nBit 4 PAM: Pass all multicast\nWhen set, this bit indicates that all received frames with a multicast destination address (first \nbit in the destination address field is '1') are passed.\nWhen reset, filtering of multicast frame depends on the HM bit.\nBit 3 DAIF: Destination address inverse filtering\nWhen this bit is set, the address check block operates in inverse filtering mode for the DA \naddress comparison for both unicast and multicast frames.\nWhen reset, normal filtering of frames is performed.\nBit 2 HM: Hash multicast\nWhen set, MAC performs destination address filtering of received multicast frames \naccording to the hash table.\nWhen reset, the MAC performs a perfect destination address filtering for multicast frames, \nthat is, it compares the DA field with the values programmed in DA registers.\nBit 1 HU: Hash unicast\nWhen set, MAC performs destination address filtering of unicast frames according to the \nhash table.\nWhen reset, the MAC performs a perfect destination address filtering for unicast frames, that \nis, it compares the DA field with the values programmed in DA registers.\nBit 0 PM: Promiscuous mode\nWhen this bit is set, the address filters pass all incoming frames regardless of their \ndestination or source address. The SA/DA filter fails status bits in the receive status word \nare always cleared when PM is set.\nG x\n( )\nx32\nx26\nx23\nx22\nx16\nx12\nx11\nx10\nx8\nx7\nx5\nx4\nx2\nx\n1\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n+\n=\n" }, { "page_number": 1199, "page_indices": { "start_index": 2362420, "end_index": 2364727 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1199 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC hash table low register (ETH_MACHTLR)", 1199 ], [ 4, "Ethernet MAC MII address register (ETH_MACMIIAR)", 1199 ] ], "page_content": "RM0090 Rev 21\n1199/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nThe most significant bit determines the register to be used (hash table high/hash table low), \nand the other 5 bits determine which bit within the register. A hash value of 0b0 0000 selects \nbit 0 in the selected register, and a value of 0b1 1111 selects bit 31 in the selected register.\nFor example, if the DA of the incoming frame is received as 0x1F52 419C B6AF (0x1F is the \nfirst byte received on the MII interface), then the internally calculated 6-bit Hash value is \n0x2C and the HTH register bit[12] is checked for filtering. If the DA of the incoming frame is \nreceived as 0xA00A 9800 0045, then the calculated 6-bit Hash value is 0x07 and the HTL \nregister bit[7] is checked for filtering.\nIf the corresponding bit value in the register is 1, the frame is accepted. Otherwise, it is \nrejected. If the PAM (pass all multicast) bit is set in the ETH_MACFFR register, then all \nmulticast frames are accepted regardless of the multicast hash values.\nThe Hash table high register contains the higher 32 bits of the multicast Hash table.\n \nEthernet MAC hash table low register (ETH_MACHTLR)\nAddress offset: 0x000C\nReset value: 0x0000 0000\nThe Hash table low register contains the lower 32 bits of the multi-cast Hash table.\n \n \nEthernet MAC MII address register (ETH_MACMIIAR)\nAddress offset: 0x0010\nReset value: 0x0000 0000\nThe MII address register controls the management cycles to the external PHY through the \nmanagement interface.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nHTH\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 HTH: Hash table high\nThis field contains the upper 32 bits of Hash table.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nHTL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 HTL: Hash table low\nThis field contains the lower 32 bits of the Hash table.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPA\nMR\nReserved\nCR\nMW MB\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrc_\nw1\n" }, { "page_number": 1200, "page_indices": { "start_index": 2364727, "end_index": 2366993 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1200 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC MII data register (ETH_MACMIIDR)", 1200 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1200/1757\nRM0090 Rev 21\n \nEthernet MAC MII data register (ETH_MACMIIDR)\nAddress offset: 0x0014\nReset value: 0x0000 0000\nThe MAC MII Data register stores write data to be written to the PHY register located at the \naddress specified in ETH_MACMIIAR. ETH_MACMIIDR also stores read data from the PHY \nregister located at the address specified by ETH_MACMIIAR.\n \n \nBits 31:16 Reserved, must be kept at reset value.\nBits 15:11 PA: PHY address\nThis field tells which of the 32 possible PHY devices are being accessed.\nBits 10:6 MR: MII register\nThese bits select the desired MII register in the selected PHY device.\nBit 5 Reserved, must be kept at reset value.\nBits 4:2 CR: Clock range\nThe CR clock range selection determines the HCLK frequency and is used to decide the \nfrequency of the MDC clock:\nSelection HCLK MDC clock\n000 60-100 MHz HCLK/42\n001 100-150 MHzHCLK/62\n010 20-35 MHz HCLK/16\n011 35-60 MHz HCLK/26\n100 150-180 MHz HCLK/102\n101, 110, 111 Reserved -\nBit 1 MW: MII write\nWhen set, this bit tells the PHY that this is a Write operation using the MII Data register. If this \nbit is not set, this is a Read operation, placing the data in the MII Data register.\nBit 0 MB: MII busy\nThis bit should read a logic 0 before writing to ETH_MACMIIAR and ETH_MACMIIDR. This \nbit must also be reset to 0 during a Write to ETH_MACMIIAR. During a PHY register access, \nthis bit is set to 0b1 by the application to indicate that a read or write access is in progress. \nETH_MACMIIDR (MII Data) should be kept valid until this bit is cleared by the MAC during a \nPHY Write operation. The ETH_MACMIIDR is invalid until this bit is cleared by the MAC \nduring a PHY Read operation. The ETH_MACMIIAR (MII Address) should not be written to \nuntil this bit is cleared.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMD\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 MD: MII data\nThis contains the 16-bit data value read from the PHY after a Management Read operation, \nor the 16-bit data value to be written to the PHY before a Management Write operation.\n" }, { "page_number": 1201, "page_indices": { "start_index": 2366993, "end_index": 2369842 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1201 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC flow control register (ETH_MACFCR)", 1201 ] ], "page_content": "RM0090 Rev 21\n1201/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet MAC flow control register (ETH_MACFCR)\nAddress offset: 0x0018\nReset value: 0x0000 0000\nThe Flow control register controls the generation and reception of the control (Pause \nCommand) frames by the MAC. A write to a register with the Busy bit set to '1' causes the \nMAC to generate a pause control frame. The fields of the control frame are selected as \nspecified in the 802.3x specification, and the Pause Time value from this register is used in \nthe Pause Time field of the control frame. The Busy bit remains set until the control frame is \ntransferred onto the cable. The Host must make sure that the Busy bit is cleared before \nwriting to the register.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPT\nReserved\nZQPD\nReserved\nPLT\nUPFD\nRFCE\nTFCE\nFCB/\nBPA\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrc_w1\n/rw\nBits 31:16 PT: Pause time\nThis field holds the value to be used in the Pause Time field in the transmit control frame. If \nthe Pause Time bits is configured to be double-synchronized to the MII clock domain, then \nconsecutive write operations to this register should be performed only after at least 4 clock \ncycles in the destination clock domain.\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 ZQPD: Zero-quanta pause disable\nWhen set, this bit disables the automatic generation of Zero-quanta pause control frames on \nthe deassertion of the flow-control signal from the FIFO layer.\nWhen this bit is reset, normal operation with automatic Zero-quanta pause control frame \ngeneration is enabled.\nBit 6 Reserved, must be kept at reset value.\nBits 5:4 PLT: Pause low threshold\nThis field configures the threshold of the Pause timer at which the Pause frame is \nautomatically retransmitted. The threshold values should always be less than the Pause \nTime configured in bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, \nthen a second PAUSE frame is automatically transmitted if initiated at 228 (256 – 28) slot-\ntimes after the first PAUSE frame is transmitted. \nSelection Threshold\n00 Pause time minus 4 slot times\n01 Pause time minus 28 slot times\n10 Pause time minus 144 slot times\n11 Pause time minus 256 slot times\nSlot time is defined as time taken to transmit 512 bits (64 bytes) on the MII interface.\nBit 3 UPFD: Unicast pause frame detect\nWhen this bit is set, the MAC detects the Pause frames with the station’s unicast address \nspecified in the ETH_MACA0HR and ETH_MACA0LR registers, in addition to detecting \nPause frames with the unique multicast address.\nWhen this bit is reset, the MAC detects only a Pause frame with the unique multicast \naddress specified in the 802.3x standard.\n" }, { "page_number": 1202, "page_indices": { "start_index": 2369842, "end_index": 2372266 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1202 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC VLAN tag register (ETH_MACVLANTR)", 1202 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1202/1757\nRM0090 Rev 21\nEthernet MAC VLAN tag register (ETH_MACVLANTR)\nAddress offset: 0x001C\nReset value: 0x0000 0000\nThe VLAN tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN frames. \nThe MAC compares the 13th and 14th bytes of the receiving frame (Length/Type) with \n0x8100, and the following 2 bytes are compared with the VLAN tag; if a match occurs, the \nreceived VLAN bit in the receive frame status is set. The legal length of the frame is \nincreased from 1518 bytes to 1522 bytes.\n \nBit 2 RFCE: Receive flow control enable\nWhen this bit is set, the MAC decodes the received Pause frame and disables its transmitter \nfor a specified (Pause Time) time.\nWhen this bit is reset, the decode function of the Pause frame is disabled.\nBit 1 TFCE: Transmit flow control enable\nIn Full-duplex mode, when this bit is set, the MAC enables the flow control operation to \ntransmit Pause frames. When this bit is reset, the flow control operation in the MAC is \ndisabled, and the MAC does not transmit any Pause frames.\nIn Half-duplex mode, when this bit is set, the MAC enables the back-pressure operation. \nWhen this bit is reset, the back pressure feature is disabled.\nBit 0 FCB/BPA: Flow control busy/back pressure activate\nThis bit initiates a Pause Control frame in Full-duplex mode and activates the back pressure \nfunction in Half-duplex mode if TFCE bit is set.\nIn Full-duplex mode, this bit should be read as 0 before writing to the Flow control register. \nTo initiate a Pause control frame, the Application must set this bit to 1. During a transfer of \nthe Control frame, this bit continues to be set to signify that a frame transmission is in \nprogress. After completion of the Pause control frame transmission, the MAC resets this bit \nto 0. The Flow control register should not be written to until this bit is cleared.\nIn Half-duplex mode, when this bit is set (and TFCE is set), back pressure is asserted by the \nMAC core. During back pressure, when the MAC receives a new frame, the transmitter \nstarts sending a JAM pattern resulting in a collision. When the MAC is configured to Full-\nduplex mode, the BPA is automatically disabled.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nVLANTC\nVLANTI\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1203, "page_indices": { "start_index": 2372266, "end_index": 2374825 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1203 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC remote wake-up frame filter register (ETH_MACRWUFFR)", 1203 ] ], "page_content": "RM0090 Rev 21\n1203/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n \nEthernet MAC remote wake-up frame filter register (ETH_MACRWUFFR)\nAddress offset: 0x0028\nReset value: 0x0000 0000\nThis is the address through which the remote wake-up frame filter registers are written/read \nby the application. The Wake-up frame filter register is actually a pointer to eight (not \ntransparent) such wake-up frame filter registers. Eight sequential write operations to this \naddress with the offset (0x0028) write all wake-up frame filter registers. Eight sequential \nread operations from this address with the offset (0x0028) read all wake-up frame filter \nregisters. This register contains the higher 16 bits of the 7th MAC address. Refer to Remote \nwake-up frame filter register section for additional information.\nFigure 385. Ethernet MAC remote wake-up frame filter register (ETH_MACRWUFFR)\nBits 31:17 Reserved, must be kept at reset value.\nBit 16 VLANTC: 12-bit VLAN tag comparison\nWhen this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is \nused for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the \ncorresponding field in the received VLAN-tagged frame.\nWhen this bit is reset, all 16 bits of the received VLAN frame’s fifteenth and sixteenth bytes \nare used for comparison.\nBits 15:0 VLANTI: VLAN tag identifier (for receive frames)\nThis contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth \nand sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the user \npriority, Bit[12] is the canonical format indicator (CFI) and bits[11:0] are the VLAN tag’s VLAN \nidentifier (VID) field. When the VLANTC bit is set, only the VID (bits[11:0]) is used for \ncomparison.\nIf VLANTI (VLANTI[11:0] if VLANTC is set) is all zeros, the MAC does not check the fifteenth \nand sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field value \nof 0x8100 as VLAN frames.\nFilter 0 Byte Mask\nFilter 1 Byte Mask\nFilter 2 Byte Mask\nFilter 3 Byte Mask\nRSVD\nFilter 3\nCommand\nRSVD\nFilter 2\nCommand\nRSVD\nFilter 1\nCommand\nRSVD\nFilter 0\nCommand\nFilter 3 Offset\nFilter 2 Offset\nFilter 1 Offset\nFilter 0 Offset\nFilter 1 CRC - 16\nFilter 0 CRC - 16\nFilter 3 CRC - 16\nFilter 2 CRC - 16\nWakeup frame filter reg0\nWakeup frame filter reg1\nWakeup frame filter reg2\nWakeup frame filter reg3\nWakeup frame filter reg4\nWakeup frame filter reg5\nWakeup frame filter reg6\nWakeup frame filter reg7\nai15648\n" }, { "page_number": 1204, "page_indices": { "start_index": 2374825, "end_index": 2376825 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1204 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC PMT control and status register (ETH_MACPMTCSR)", 1204 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1204/1757\nRM0090 Rev 21\nEthernet MAC PMT control and status register (ETH_MACPMTCSR)\nAddress offset: 0x002C\nReset value: 0x0000 0000\nThe ETH_MACPMTCSR programs the request wake-up events and monitors the wake-up \nevents.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nWFFRPR\nReserved\nGU\nReserved\nWFR\nMPR\nReserved\nWFE\nMPE\nPD\nrs\nRes.\nrw\nrc_r rc_r\nrw\nrw\nrs\nBit 31 WFFRPR: Wake-up frame filter register pointer reset\nWhen set, it resets the Remote wake-up frame filter register pointer to 0b000. It is \nautomatically cleared after 1 clock cycle.\nBits 30:10 Reserved, must be kept at reset value.\nBit 9 GU: Global unicast\nWhen set, it enables any unicast packet filtered by the MAC (DAF) address recognition to be \na wake-up frame.\nBits 8:7 Reserved, must be kept at reset value.\nBit 6 WFR: Wake-up frame received\nWhen set, this bit indicates the power management event was generated due to reception of \na wake-up frame. This bit is cleared by a read into this register.\nBit 5 MPR: Magic packet received\nWhen set, this bit indicates the power management event was generated by the reception of \na Magic Packet. This bit is cleared by a read into this register.\nBits 4:3 Reserved, must be kept at reset value.\nBit 2 WFE: Wake-up frame enable\nWhen set, this bit enables the generation of a power management event due to wake-up \nframe reception.\nBit 1 MPE: Magic Packet enable\nWhen set, this bit enables the generation of a power management event due to Magic \nPacket reception.\nBit 0 PD: Power down\nWhen this bit is set, all received frames are dropped. This bit is cleared automatically when \na magic packet or wake-up frame is received, and Power-down mode is disabled. Frames \nreceived after this bit is cleared are forwarded to the application. This bit must only be set \nwhen either the Magic Packet Enable or Wake-up Frame Enable bit is set high.\n" }, { "page_number": 1205, "page_indices": { "start_index": 2376825, "end_index": 2379052 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1205 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC debug register (ETH_MACDBGR)", 1205 ] ], "page_content": "RM0090 Rev 21\n1205/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet MAC debug register (ETH_MACDBGR)\nAddress offset: 0x0034\nReset value: 0x0000 0000\nThis debug register gives the status of all the main modules of the transmit and receive data \npaths and the FIFOs. An all-zero status indicates that the MAC core is in Idle state (and \nFIFOs are empty) and no activity is going on in the data paths.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTFF\nTFNE\nReserved\nTFWA\nTFRS\nMTP\nMTFCS\nMMTEA\nReserved\nRFFL\nReserved\nRFRCS\nRFWRA\nReserved\nMSFRWCS\nMMRPEA\nro\nro\nro\nro\nro\nro\nro\nro\nro\nro\nro\nro\nro\nro\nro\nro\nro\nBits 31:26 Reserved, must be kept at reset value.\nBit 25 TFF: Tx FIFO full\nWhen high, it indicates that the Tx FIFO is full and hence no more frames are accepted for \ntransmission.\nBit 24 TFNE: Tx FIFO not empty\nWhen high, it indicates that the TxFIFO is not empty and has some data left for \ntransmission.\nBit 23 Reserved, must be kept at reset value.\nBit 22 TFWA: Tx FIFO write active\nWhen high, it indicates that the TxFIFO write controller is active and transferring data to the \nTxFIFO.\nBits 21:20 TFRS: Tx FIFO read status\nThis indicates the state of the TxFIFO read controller:\n00: Idle state\n01: Read state (transferring data to the MAC transmitter)\n10: Waiting for TxStatus from MAC transmitter\n11: Writing the received TxStatus or flushing the TxFIFO\nBit 19 MTP: MAC transmitter in pause\nWhen high, it indicates that the MAC transmitter is in Pause condition (in full-duplex mode \nonly) and hence does not schedule any frame for transmission\nBits 18:17 MTFCS: MAC transmit frame controller status\nThis indicates the state of the MAC transmit frame controller:\n00: Idle\n01: Waiting for Status of previous frame or IFG/backoff period to be over\n10: Generating and transmitting a Pause control frame (in full duplex mode)\n11: Transferring input frame for transmission\nBit 16 MMTEA: MAC MII transmit engine active\nWhen high, it indicates that the MAC MII transmit engine is actively transmitting data and \nthat it is not in the Idle state.\nBits 15:10 Reserved, must be kept at reset value.\n" }, { "page_number": 1206, "page_indices": { "start_index": 2379052, "end_index": 2380265 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1206 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC debug register (ETH_MACDBGR)", 1205 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1206/1757\nRM0090 Rev 21\nBits 9:8 RFFL: Rx FIFO fill level\nThis gives the status of the Rx FIFO fill-level:\n00: RxFIFO empty\n01: RxFIFO fill-level below flow-control de-activate threshold\n10: RxFIFO fill-level above flow-control activate threshold\n11: RxFIFO full\nBit 7 Reserved, must be kept at reset value.\nBits 6:5 RFRCS: Rx FIFO read controller status\nIt gives the state of the Rx FIFO read controller:\n00: IDLE state\n01: Reading frame data\n10: Reading frame status (or time-stamp)\n11: Flushing the frame data and status\nBit 4 RFWRA: Rx FIFO write controller active\nWhen high, it indicates that the Rx FIFO write controller is active and transferring a received \nframe to the FIFO.\nBit 3 Reserved, must be kept at reset value.\nBits 2:1 MSFRWCS: MAC small FIFO read / write controllers status\nWhen high, these bits indicate the respective active state of the small FIFO read and write \ncontrollers of the MAC receive frame controller module.\nBit 0 MMRPEA: MAC MII receive protocol engine active\nWhen high, it indicates that the MAC MII receive protocol engine is actively receiving data \nand is not in the Idle state.\n" }, { "page_number": 1207, "page_indices": { "start_index": 2380265, "end_index": 2382022 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1207 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC interrupt status register (ETH_MACSR)", 1207 ] ], "page_content": "RM0090 Rev 21\n1207/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet MAC interrupt status register (ETH_MACSR)\nAddress offset: 0x0038\nReset value: 0x0000 0000\nThe ETH_MACSR register contents identify the events in the MAC that can generate an \ninterrupt.\n \n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTSTS\nReserved\nMMCTS\nMMCRS\nMMCS\nPMTS\nReserved\nrc_r\nr\nr\nr\nr\nBits 15:10 Reserved, must be kept at reset value.\nBit 9 TSTS: Time stamp trigger status \nThis bit is set high when the system time value equals or exceeds the value specified in the \nTarget time high and low registers. This bit is cleared by reading the ETH_PTPTSSR \nregister.\nBits 8:7 Reserved, must be kept at reset value.\nBit 6 MMCTS: MMC transmit status \nThis bit is set high whenever an interrupt is generated in the Ethernet MMC transmit interrupt \nregister (ETH_MMCTIR). This bit is cleared when all the bits in this interrupt register \n(ETH_MMCTIR) are cleared.\nBit 5 MMCRS: MMC receive status \nThis bit is set high whenever an interrupt is generated in the ETH_MMCRIR register. This bit \nis cleared when all the bits in this interrupt register (ETH_MMCRIR) are cleared.\nBit 4 MMCS: MMC status \nThis bit is set high whenever any of bits 6:5 is set high. It is cleared only when both bits are \nlow.\nBit 3 PMTS: PMT status \nThis bit is set whenever a Magic packet or Wake-on-LAN frame is received in Power-down \nmode (see bits 5 and 6 in the ETH_MACPMTCSR register Ethernet MAC PMT control and \nstatus register (ETH_MACPMTCSR)). This bit is cleared when both bits[6:5], of this last \nregister, are cleared due to a read operation to the ETH_MACPMTCSR register.\nBits 2:0 Reserved, must be kept at reset value.\n" }, { "page_number": 1208, "page_indices": { "start_index": 2382022, "end_index": 2383920 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1208 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC interrupt mask register (ETH_MACIMR)", 1208 ], [ 4, "Ethernet MAC address 0 high register (ETH_MACA0HR)", 1208 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1208/1757\nRM0090 Rev 21\nEthernet MAC interrupt mask register (ETH_MACIMR)\nAddress offset: 0x003C\nReset value: 0x0000 0000\nThe ETH_MACIMR register bits make it possible to mask the interrupt signal due to the \ncorresponding event in the ETH_MACSR register.\n \n \nEthernet MAC address 0 high register (ETH_MACA0HR)\nAddress offset: 0x0040\nReset value: 0x8000 FFFF\nThe MAC address 0 high register holds the upper 16 bits of the 6-byte first MAC address of \nthe station. Note that the first DA byte that is received on the MII interface corresponds to \nthe LS Byte (bits [7:0]) of the MAC address low register. For example, if 0x1122 3344 5566 \nis received (0x11 is the first byte) on the MII as the destination address, then the MAC \naddress 0 register [47:0] is compared with 0x6655 4433 2211.\n \n \n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTSTIM\nReserved\nPMTIM\nReserved\nrw\nrw\nBits 15:10 Reserved, must be kept at reset value.\nBit 9 TSTIM: Time stamp trigger interrupt mask \nWhen set, this bit disables the time stamp interrupt generation.\nBits 8:4 Reserved, must be kept at reset value.\nBit 3 PMTIM: PMT interrupt mask \nWhen set, this bit disables the assertion of the interrupt signal due to the setting of the PMT \nStatus bit in ETH_MACSR.\nBits 2:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMO\nReserved\nMACA0H\n1\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 MO: Always 1.\nBits 30:16 Reserved, must be kept at reset value.\nBits 15:0 MACA0H: MAC address0 high [47:32]\nThis field contains the upper 16 bits (47:32) of the 6-byte MAC address0. This is used by the \nMAC for filtering for received frames and for inserting the MAC address in the transmit flow \ncontrol (Pause) frames.\n" }, { "page_number": 1209, "page_indices": { "start_index": 2383920, "end_index": 2385990 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1209 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC address 0 low register (ETH_MACA0LR)", 1209 ], [ 4, "Ethernet MAC address 1 high register (ETH_MACA1HR)", 1209 ] ], "page_content": "RM0090 Rev 21\n1209/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet MAC address 0 low register (ETH_MACA0LR)\nAddress offset: 0x0044\nReset value: 0xFFFF FFFF\nThe MAC address 0 low register holds the lower 32 bits of the 6-byte first MAC address of \nthe station.\n \n \nEthernet MAC address 1 high register (ETH_MACA1HR)\nAddress offset: 0x0048\nReset value: 0x0000 FFFF\nThe MAC address 1 high register holds the upper 16 bits of the 6-byte second MAC address \nof the station.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMACA0L\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 MACA0L: MAC address0 low [31:0]\nThis field contains the lower 32 bits of the 6-byte MAC address0. This is used by the MAC \nfor filtering for received frames and for inserting the MAC address in the transmit flow control \n(Pause) frames.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nAE SA\nMBC\nReserved\nMACA1H\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 AE: Address enable\nWhen this bit is set, the address filters use the MAC address1 for perfect filtering. When this \nbit is cleared, the address filters ignore the address for filtering.\nBit 30 SA: Source address\nWhen this bit is set, the MAC address1[47:0] is used for comparison with the SA fields of the \nreceived frame.\nWhen this bit is cleared, the MAC address1[47:0] is used for comparison with the DA fields \nof the received frame.\nBits 29:24 MBC: Mask byte control\nThese bits are mask control bits for comparison of each of the MAC address1 bytes. When \nthey are set high, the MAC core does not compare the corresponding byte of received \nDA/SA with the contents of the MAC address1 registers. Each bit controls the masking of the \nbytes as follows:\n– Bit 29: ETH_MACA1HR [15:8]\n– Bit 28: ETH_MACA1HR [7:0]\n– Bit 27: ETH_MACA1LR [31:24]\n…\n– Bit 24: ETH_MACA1LR [7:0]\n" }, { "page_number": 1210, "page_indices": { "start_index": 2385990, "end_index": 2387305 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1210 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC address1 low register (ETH_MACA1LR)", 1210 ], [ 4, "Ethernet MAC address 2 high register (ETH_MACA2HR)", 1210 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1210/1757\nRM0090 Rev 21\nEthernet MAC address1 low register (ETH_MACA1LR)\nAddress offset: 0x004C\nReset value: 0xFFFF FFFF\nThe MAC address 1 low register holds the lower 32 bits of the 6-byte second MAC address \nof the station.\n \n \nEthernet MAC address 2 high register (ETH_MACA2HR)\nAddress offset: 0x0050\nReset value: 0x0000 FFFF\nThe MAC address 2 high register holds the upper 16 bits of the 6-byte second MAC address \nof the station.\n \nBits 23:16 Reserved, must be kept at reset value.\nBits 15:0 MACA1H: MAC address1 high [47:32]\nThis field contains the upper 16 bits (47:32) of the 6-byte second MAC address.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMACA1L\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 MACA1L: MAC address1 low [31:0]\nThis field contains the lower 32 bits of the 6-byte MAC address1. The content of this field is \nundefined until loaded by the application after the initialization process.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nAE SA\nMBC\nReserved\nMACA2H\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1211, "page_indices": { "start_index": 2387305, "end_index": 2389099 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1211 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC address 2 low register (ETH_MACA2LR)", 1211 ] ], "page_content": "RM0090 Rev 21\n1211/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n \nEthernet MAC address 2 low register (ETH_MACA2LR)\nAddress offset: 0x0054\nReset value: 0xFFFF FFFF\nThe MAC address 2 low register holds the lower 32 bits of the 6-byte second MAC address \nof the station.\n \n \nBit 31 AE: Address enable\nWhen this bit is set, the address filters use the MAC address2 for perfect filtering. When \nreset, the address filters ignore the address for filtering.\nBit 30 SA: Source address\nWhen this bit is set, the MAC address 2 [47:0] is used for comparison with the SA fields of \nthe received frame.\nWhen this bit is reset, the MAC address 2 [47:0] is used for comparison with the DA fields of \nthe received frame.\nBits 29:24 MBC: Mask byte control\nThese bits are mask control bits for comparison of each of the MAC address2 bytes. When \nset high, the MAC core does not compare the corresponding byte of received DA/SA with the \ncontents of the MAC address 2 registers. Each bit controls the masking of the bytes as \nfollows:\n– Bit 29: ETH_MACA2HR [15:8]\n– Bit 28: ETH_MACA2HR [7:0]\n– Bit 27: ETH_MACA2LR [31:24]\n…\n– Bit 24: ETH_MACA2LR [7:0]\nBits 23:16 Reserved, must be kept at reset value.\nBits 15:0 MACA2H: MAC address2 high [47:32]\nThis field contains the upper 16 bits (47:32) of the 6-byte MAC address2.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMACA2L\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 MACA2L: MAC address2 low [31:0]\nThis field contains the lower 32 bits of the 6-byte second MAC address2. The content of this \nfield is undefined until loaded by the application after the initialization process.\n" }, { "page_number": 1212, "page_indices": { "start_index": 2389099, "end_index": 2391317 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1212 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.1 MAC register description", 1194 ], [ 4, "Ethernet MAC address 3 high register (ETH_MACA3HR)", 1212 ], [ 4, "Ethernet MAC address 3 low register (ETH_MACA3LR)", 1212 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1212/1757\nRM0090 Rev 21\nEthernet MAC address 3 high register (ETH_MACA3HR)\nAddress offset: 0x0058\nReset value: 0x0000 FFFF\nThe MAC address 3 high register holds the upper 16 bits of the 6-byte second MAC address \nof the station.\n \n \nEthernet MAC address 3 low register (ETH_MACA3LR)\nAddress offset: 0x005C\nReset value: 0xFFFF FFFF\nThe MAC address 3 low register holds the lower 32 bits of the 6-byte second MAC address \nof the station.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nAE SA\nMBC\nReserved\nMACA3H\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 AE: Address enable\nWhen this bit is set, the address filters use the MAC address3 for perfect filtering. When this \nbit is cleared, the address filters ignore the address for filtering.\nBit 30 SA: Source address\nWhen this bit is set, the MAC address 3 [47:0] is used for comparison with the SA fields of the \nreceived frame.\nWhen this bit is cleared, the MAC address 3[47:0] is used for comparison with the DA fields \nof the received frame.\nBits 29:24 MBC: Mask byte control\nThese bits are mask control bits for comparison of each of the MAC address3 bytes. When \nthese bits are set high, the MAC core does not compare the corresponding byte of received \nDA/SA with the contents of the MAC address 3 registers. Each bit controls the masking of the \nbytes as follows:\n– Bit 29: ETH_MACA3HR [15:8]\n– Bit 28: ETH_MACA3HR [7:0]\n– Bit 27: ETH_MACA3LR [31:24]\n…\n– Bit 24: ETH_MACA3LR [7:0]\nBits 23:16 Reserved, must be kept at reset value.\nBits 15:0 MACA3H: MAC address3 high [47:32]\nThis field contains the upper 16 bits (47:32) of the 6-byte MAC address3.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMACA3L\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 MACA3L: MAC address3 low [31:0]\nThis field contains the lower 32 bits of the 6-byte second MAC address3. The content of this \nfield is undefined until loaded by the application after the initialization process.\n" }, { "page_number": 1213, "page_indices": { "start_index": 2391317, "end_index": 2393663 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1213 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.2 MMC register description", 1213 ], [ 4, "Ethernet MMC control register (ETH_MMCCR)", 1213 ], [ 4, "Ethernet MMC receive interrupt register (ETH_MMCRIR)", 1213 ] ], "page_content": "RM0090 Rev 21\n1213/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n33.8.2 \nMMC register description\nEthernet MMC control register (ETH_MMCCR)\nAddress offset: 0x0100\nReset value: 0x0000 0000\nThe Ethernet MMC Control register establishes the operating mode of the management \ncounters.\n \n \nEthernet MMC receive interrupt register (ETH_MMCRIR)\nAddress offset: 0x0104\nReset value: 0x0000 0000\nThe Ethernet MMC receive interrupt register maintains the interrupts generated when \nreceive statistic counters reach half their maximum values. (MSB of the counter is set.) It is \na 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMCFHP\nMCP\nMCF\nROR\nCSR\nCR\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:6 Reserved, must be kept at reset value.\nBit 5\nMCFHP: MMC counter Full-Half preset\nWhen MCFHP is low and bit4 is set, all MMC counters get preset to almost-half value. All \nframe-counters get preset to 0x7FFF_FFF0 (half - 16)\nWhen MCFHP is high and bit4 is set, all MMC counters get preset to almost-full value. All \nframe-counters get preset to 0xFFFF_FFF0 (full - 16)\nBit 4\nMCP: MMC counter preset\nWhen set, all counters are initialized or preset to almost full or almost half as per\nBit5 above. This bit is cleared automatically after 1 clock cycle. This bit along\nwith bit5 is useful for debugging and testing the assertion of interrupts due to MMC\ncounter becoming half-full or full.\nBit 3 MCF: MMC counter freeze\nWhen set, this bit freezes all the MMC counters to their current value. (None of the MMC \ncounters are updated due to any transmitted or received frame until this bit is cleared to 0. If \nany MMC counter is read with the Reset on Read bit set, then that counter is also cleared in \nthis mode.)\nBit 2 ROR: Reset on read\nWhen this bit is set, the MMC counters is reset to zero after read (self-clearing after reset). \nThe counters are cleared when the least significant byte lane (bits [7:0]) is read.\nBit 1 CSR: Counter stop rollover\nWhen this bit is set, the counter does not roll over to zero after it reaches the maximum \nvalue.\nBit 0 CR: Counter reset\nWhen it is set, all counters are reset. This bit is cleared automatically after 1 clock cycle.\n" }, { "page_number": 1214, "page_indices": { "start_index": 2393663, "end_index": 2395624 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1214 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.2 MMC register description", 1213 ], [ 4, "Ethernet MMC transmit interrupt register (ETH_MMCTIR)", 1214 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1214/1757\nRM0090 Rev 21\ncaused the interrupt is read. The least significant byte lane (bits [7:0]) of the respective \ncounter must be read in order to clear the interrupt bit.\n \n \nEthernet MMC transmit interrupt register (ETH_MMCTIR)\nAddress offset: 0x0108\nReset value: 0x0000 0000\nThe Ethernet MMC transmit Interrupt register maintains the interrupts generated when \ntransmit statistic counters reach half their maximum values. (MSB of the counter is set.) It is \na 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that \ncaused the interrupt is read. The least significant byte lane (bits [7:0]) of the respective \ncounter must be read in order to clear the interrupt bit.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRGUFS\nReserved\nRFAES\nRFCES\nReserved\nrc_r\nrc_r rc_r\nBits 31:18 Reserved, must be kept at reset value.\nBit 17 RGUFS: Received Good Unicast Frames Status\nThis bit is set when the received, good unicast frames, counter reaches half the maximum \nvalue.\nBits 16:7 Reserved, must be kept at reset value.\nBit 6 RFAES: Received frames alignment error status\nThis bit is set when the received frames, with alignment error, counter reaches half the \nmaximum value.\nBit 5 RFCES: Received frames CRC error status\nThis bit is set when the received frames, with CRC error, counter reaches half the maximum \nvalue.\nBits 4:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTGFS\nReserved\nTGFMSCS\nTGFSCS\nReserved\nrc_r\nrc_r rc_r\nBits 31:22 Reserved, must be kept at reset value.\nBit 21 TGFS: Transmitted good frames status\nThis bit is set when the transmitted, good frames, counter reaches half the maximum value.\nBits 20:16 Reserved, must be kept at reset value.\n" }, { "page_number": 1215, "page_indices": { "start_index": 2395624, "end_index": 2397313 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1215 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.2 MMC register description", 1213 ], [ 4, "Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)", 1215 ] ], "page_content": "RM0090 Rev 21\n1215/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet MMC receive interrupt mask register (ETH_MMCRIMR)\nAddress offset: 0x010C\nReset value: 0x0000 0000\nThe Ethernet MMC receive interrupt mask register maintains the masks for interrupts \ngenerated when the receive statistic counters reach half their maximum value. (MSB of the \ncounter is set.) It is a 32-bit wide register.\n \n \nBit 15 TGFMSCS: Transmitted good frames more single collision status\nThis bit is set when the transmitted, good frames after more than a single collision, counter \nreaches half the maximum value.\nBit 14 TGFSCS: Transmitted good frames single collision status\nThis bit is set when the transmitted, good frames after a single collision, counter reaches half \nthe maximum value.\nBits 13:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRGUFM\nReserved\nRFAEM\nRFCEM\nReserved\nrw\nrw\nrw\nBits 31:18 Reserved, must be kept at reset value.\nBit 17 RGUFM: Received good unicast frames mask\nSetting this bit masks the interrupt when the received, good unicast frames, counter \nreaches half the maximum value.\nBits 16:7 Reserved, must be kept at reset value.\nBit 6 RFAEM: Received frames alignment error mask\nSetting this bit masks the interrupt when the received frames, with alignment error, counter \nreaches half the maximum value.\nBit 5 RFCEM: Received frame CRC error mask\nSetting this bit masks the interrupt when the received frames, with CRC error, counter \nreaches half the maximum value.\nBits 4:0 Reserved, must be kept at reset value.\n" }, { "page_number": 1216, "page_indices": { "start_index": 2397313, "end_index": 2399201 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1216 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.2 MMC register description", 1213 ], [ 4, "Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)", 1216 ], [ 4, "Ethernet MMC transmitted good frames after a single collision counter register (ETH_MMCTGFSCCR)", 1216 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1216/1757\nRM0090 Rev 21\nEthernet MMC transmit interrupt mask register (ETH_MMCTIMR)\nAddress offset: 0x0110\nReset value: 0x0000 0000\nThe Ethernet MMC transmit interrupt mask register maintains the masks for interrupts \ngenerated when the transmit statistic counters reach half their maximum value. (MSB of the \ncounter is set). It is a 32-bit wide register.\n \n \nEthernet MMC transmitted good frames after a single collision counter\nregister (ETH_MMCTGFSCCR)\nAddress offset: 0x014C\nReset value: 0x0000 0000\nThis register contains the number of successfully transmitted frames after a single collision \nin Half-duplex mode.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTGFM\nReserved\nTGFMSCM\nTGFSCM\nReserved\nrw\nrw\nrw\nBits 31:22 Reserved, must be kept at reset value.\nBit 21 TGFM: Transmitted good frames mask\nSetting this bit masks the interrupt when the transmitted, good frames, counter reaches half \nthe maximum value.\nBits 20:16 Reserved, must be kept at reset value.\nBit 15 TGFMSCM: Transmitted good frames more single collision mask\nSetting this bit masks the interrupt when the transmitted good frames after more than a \nsingle collision counter reaches half the maximum value.\nBit 14 TGFSCM: Transmitted good frames single collision mask\nSetting this bit masks the interrupt when the transmitted good frames after a single collision \ncounter reaches half the maximum value.\nBits 13:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTGFSCC\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 TGFSCC: Transmitted good frames single collision counter\nTransmitted good frames after a single collision counter.\n" }, { "page_number": 1217, "page_indices": { "start_index": 2399201, "end_index": 2400786 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1217 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.2 MMC register description", 1213 ], [ 4, "Ethernet MMC transmitted good frames after more than a single collision counter register (ETH_MMCTGFMSCCR)", 1217 ], [ 4, "Ethernet MMC transmitted good frames counter register (ETH_MMCTGFCR)", 1217 ], [ 4, "Ethernet MMC received frames with CRC error counter register (ETH_MMCRFCECR)", 1217 ] ], "page_content": "RM0090 Rev 21\n1217/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet MMC transmitted good frames after more than a single collision \ncounter register (ETH_MMCTGFMSCCR)\nAddress offset: 0x0150\nReset value: 0x0000 0000\nThis register contains the number of successfully transmitted frames after more than a \nsingle collision in Half-duplex mode.\n \n \nEthernet MMC transmitted good frames counter register (ETH_MMCTGFCR)\nAddress offset: 0x0168\nReset value: 0x0000 0000\nThis register contains the number of good frames transmitted.\n \n \nEthernet MMC received frames with CRC error counter register \n(ETH_MMCRFCECR)\nAddress offset: 0x0194\nReset value: 0x0000 0000\nThis register contains the number of frames received with CRC error.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTGFMSCC\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 TGFMSCC: Transmitted good frames more single collision counter\nTransmitted good frames after more than a single collision counter\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTGFC\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 TGFC: Transmitted good frames counter\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRFCEC\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 RFCEC: Received frames CRC error counter\nReceived frames with CRC error counter\n" }, { "page_number": 1218, "page_indices": { "start_index": 2400786, "end_index": 2402453 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1218 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.2 MMC register description", 1213 ], [ 4, "Ethernet MMC received frames with alignment error counter register (ETH_MMCRFAECR)", 1218 ], [ 4, "MMC received good unicast frames counter register (ETH_MMCRGUFCR)", 1218 ], [ 3, "33.8.3 IEEE 1588 time stamp registers", 1218 ], [ 4, "Ethernet PTP time stamp control register (ETH_PTPTSCR)", 1218 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1218/1757\nRM0090 Rev 21\nEthernet MMC received frames with alignment error counter register \n(ETH_MMCRFAECR)\nAddress offset: 0x0198\nReset value: 0x0000 0000\nThis register contains the number of frames received with alignment (dribble) error.\n \n \nMMC received good unicast frames counter register (ETH_MMCRGUFCR)\nAddress offset: 0x01C4\nReset value: 0x0000 0000\nThis register contains the number of good unicast frames received.\n \n \n33.8.3 \nIEEE 1588 time stamp registers\nThis section describes the registers required to support precision network clock \nsynchronization functions under the IEEE 1588 standard.\nEthernet PTP time stamp control register (ETH_PTPTSCR)\nAddress offset: 0x0700\nReset value: 0x0000 00002000\nThis register controls the time stamp generation and update logic.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRFAEC\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 RFAEC: Received frames alignment error counter\nReceived frames with alignment error counter\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRGUFC\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 RGUFC: Received good unicast frames counter\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTSPFFMAE\nTSCNT\nTSSMRME\nTSSEME\nTSSIPV4FE\nTSSIPV6FE\nTSSPTPOEFE\nTSPTPPSV2E\nTSSSR\nTSSARFE\nReserved\nTTSARU\nTSITE\nTSSTU\nTSSTI\nTSFCU\nTSE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1219, "page_indices": { "start_index": 2402453, "end_index": 2405545 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1219 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.3 IEEE 1588 time stamp registers", 1218 ], [ 4, "Ethernet PTP time stamp control register (ETH_PTPTSCR)", 1218 ] ], "page_content": "RM0090 Rev 21\n1219/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n \nBits 31:19 Reserved, must be kept at reset value.\nBit 18 TSPFFMAE: Time stamp PTP frame filtering MAC address enable\nWhen set, this bit uses the MAC address (except for MAC address 0) to filter the PTP frames \nwhen PTP is sent directly over Ethernet.\nBits 17:16 TSCNT: Time stamp clock node type\nThe following are the available types of clock node:\n00: Ordinary clock\n01: Boundary clock\n10: End-to-end transparent clock\n11: Peer-to-peer transparent clock\nBit 15 TSSMRME: Time stamp snapshot for message relevant to master enable\nWhen this bit is set, the snapshot is taken for messages relevant to the master node only. \nWhen this bit is cleared the snapshot is taken for messages relevant to the slave node only. \nThis is valid only for the ordinary clock and boundary clock nodes.\nBit 14 TSSEME: Time stamp snapshot for event message enable\nWhen this bit is set, the time stamp snapshot is taken for event messages only (SYNC, \nDelay_Req, Pdelay_Req or Pdelay_Resp). When this bit is cleared the snapshot is taken for \nall other messages except for Announce, Management and Signaling.\nBit 13 TSSIPV4FE: Time stamp snapshot for IPv4 frames enable\nWhen this bit is set, the time stamp snapshot is taken for IPv4 frames.\nBit 12 TSSIPV6FE: Time stamp snapshot for IPv6 frames enable\nWhen this bit is set, the time stamp snapshot is taken for IPv6 frames.\nBit 11 TSSPTPOEFE: Time stamp snapshot for PTP over ethernet frames enable\nWhen this bit is set, the time stamp snapshot is taken for frames which have PTP messages \nin Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP-\nIPEthernet PTP packets.\nBit 10 TSPTPPSV2E: Time stamp PTP packet snooping for version2 format enable\nWhen this bit is set, the PTP packets are snooped using the version 2 format. When the bit is \ncleared, the PTP packets are snooped using the version 1 format.\nNote: IEEE 1588 Version 1 and Version 2 formats as indicated in IEEE standard 1588-2008 \n(Revision of IEEE STD. 1588-2002).\nBit 9 TSSSR: Time stamp subsecond rollover: digital or binary rollover control\nWhen this bit is set, the Time stamp low register rolls over when the subsecond counter \nreaches the value 0x3B9A C9FF (999 999 999 in decimal), and increments the Time Stamp \n(high) seconds.\nWhen this bit is cleared, the rollover value of the subsecond register reaches 0x7FFF FFFF. \nThe subsecond increment has to be programmed correctly depending on the PTP’s \nreference clock frequency and this bit value.\nBit 8 TSSARFE: Time stamp snapshot for all received frames enable\nWhen this bit is set, the time stamp snapshot is enabled for all frames received by the core.\nBits 7:6 Reserved, must be kept at reset value.\nBit 5 TSARU: Time stamp addend register update\nWhen this bit is set, the Time stamp addend register’s contents are updated to the PTP block \nfor fine correction. This bit is cleared when the update is complete. This register bit must be \nread as zero before you can set it.\n" }, { "page_number": 1220, "page_indices": { "start_index": 2405545, "end_index": 2407892 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1220 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.3 IEEE 1588 time stamp registers", 1218 ], [ 4, "Ethernet PTP time stamp control register (ETH_PTPTSCR)", 1218 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1220/1757\nRM0090 Rev 21\nThe table below indicates the messages for which a snapshot is taken depending on the \nclock, enable master and enable snapshot for event message register settings.\n \nBit 4 TSITE: Time stamp interrupt trigger enable\nWhen this bit is set, a time stamp interrupt is generated when the system time becomes \ngreater than the value written in the Target time register. When the Time stamp trigger \ninterrupt is generated, this bit is cleared.\nBit 3 TSSTU: Time stamp system time update\nWhen this bit is set, the system time is updated (added to or subtracted from) with the value \nspecified in the Time stamp high update and Time stamp low update registers. Both the \nTSSTU and TSSTI bits must be read as zero before you can set this bit. Once the update is \ncompleted in hardware, this bit is cleared.\nBit 2 TSSTI: Time stamp system time initialize\nWhen this bit is set, the system time is initialized (overwritten) with the value specified in the \nTime stamp high update and Time stamp low update registers. This bit must be read as zero \nbefore you can set it. When initialization is complete, this bit is cleared.\nBit 1 TSFCU: Time stamp fine or coarse update\nWhen set, this bit indicates that the system time stamp is to be updated using the Fine \nUpdate method. When cleared, it indicates the system time stamp is to be updated using the \nCoarse method.\nBit 0 TSE: Time stamp enable\nWhen this bit is set, time stamping is enabled for transmit and receive frames. When this bit \nis cleared, the time stamp function is suspended and time stamps are not added for transmit \nand receive frames. Because the maintained system time is suspended, you must always \ninitialize the time stamp feature (system time) after setting this bit high.\nTable 195. Time stamp snapshot dependency on registers bits\nTSCNT\n(bits 17:16)\nTSSMRME\n(bit 15)(1)\n1.\nN/A = not applicable.\nTSSEME\n(bit 14)\nMessages for which snapshots are taken\n00 or 01\nX(2)\n2.\nX = don’t care.\n0\nSYNC, Follow_Up, Delay_Req, Delay_Resp \n00 or 01\n1\n1\nDelay_Req \n00 or 01\n0\n1\nSYNC \n10\nN/A\n0\nSYNC, Follow_Up, Delay_Req, Delay_Resp \n10\nN/A\n1\nSYNC, Follow_Up \n11\nN/A\n0\nSYNC, Follow_Up, Delay_Req, Delay_Resp, \nPdelay_Req, Pdelay_Resp \n11\nN/A\n1\nSYNC, Pdelay_Req, Pdelay_Resp \n" }, { "page_number": 1221, "page_indices": { "start_index": 2407892, "end_index": 2409636 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1221 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.3 IEEE 1588 time stamp registers", 1218 ], [ 4, "Ethernet PTP subsecond increment register (ETH_PTPSSIR)", 1221 ], [ 4, "Ethernet PTP time stamp high register (ETH_PTPTSHR)", 1221 ] ], "page_content": "RM0090 Rev 21\n1221/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet PTP subsecond increment register (ETH_PTPSSIR)\nAddress offset: 0x0704\nReset value: 0x0000 0000\nThis register contains the 8-bit value by which the subsecond register is incremented. In \nCoarse update mode (TSFCU bit in ETH_PTPTSCR), the value in this register is added to \nthe system time every clock cycle of HCLK. In Fine update mode, the value in this register is \nadded to the system time whenever the accumulator gets an overflow.\n \n \nEthernet PTP time stamp high register (ETH_PTPTSHR)\nAddress offset: 0x0708\nReset value: 0x0000 0000\nThis register contains the most significant (higher) 32 time bits. This read-only register \ncontains the seconds system time value. The Time stamp high register, along with Time \nstamp low register, indicates the current value of the system time maintained by the MAC. \nThough it is updated on a continuous basis.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSTSSI\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBits 7:0 STSSI: System time subsecond increment\nThe value programmed in this register is added to the contents of the subsecond value of the \nsystem time in every update.\nFor example, to achieve 20 ns accuracy, the value is: 20 / 0.467 = ~ 43 (or 0x2A).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSTS\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 STS: System time second\nThe value in this field indicates the current value in seconds of the System Time maintained \nby the core.\n" }, { "page_number": 1222, "page_indices": { "start_index": 2409636, "end_index": 2411480 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1222 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.3 IEEE 1588 time stamp registers", 1218 ], [ 4, "Ethernet PTP time stamp low register (ETH_PTPTSLR)", 1222 ], [ 4, "Ethernet PTP time stamp high update register (ETH_PTPTSHUR)", 1222 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1222/1757\nRM0090 Rev 21\nEthernet PTP time stamp low register (ETH_PTPTSLR)\nAddress offset: 0x070C\nReset value: 0x0000 0000\nThis register contains the least significant (lower) 32 time bits. This read-only register \ncontains the subsecond system time value.\n \n \nEthernet PTP time stamp high update register (ETH_PTPTSHUR)\nAddress offset: 0x0710\nReset value: 0x0000 0000\nThis register contains the most significant (higher) 32 bits of the time to be written to, added \nto, or subtracted from the System Time value. The Time stamp high update register, along \nwith the Time stamp update low register, initializes or updates the system time maintained \nby the MAC. You have to write both of these registers before setting the TSSTI or TSSTU \nbits in the Time stamp control register.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSTPNS\nSTSS\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBit 31 STPNS: System time positive or negative sign\nThis bit indicates a positive or negative time value. When set, the bit indicates that time \nrepresentation is negative. When cleared, it indicates that time representation is positive. \nBecause the system time should always be positive, this bit is normally zero.\nBits 30:0 STSS: System time subseconds \nThe value in this field has the subsecond time representation, with 0.46 ns accuracy.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTSUS\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 TSUS: Time stamp update second\nThe value in this field indicates the time, in seconds, to be initialized or added to the system \ntime.\n" }, { "page_number": 1223, "page_indices": { "start_index": 2411480, "end_index": 2413627 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1223 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.3 IEEE 1588 time stamp registers", 1218 ], [ 4, "Ethernet PTP time stamp low update register (ETH_PTPTSLUR)", 1223 ], [ 4, "Ethernet PTP time stamp addend register (ETH_PTPTSAR)", 1223 ] ], "page_content": "RM0090 Rev 21\n1223/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet PTP time stamp low update register (ETH_PTPTSLUR)\nAddress offset: 0x0714\nReset value: 0x0000 0000\nThis register contains the least significant (lower) 32 bits of the time to be written to, added \nto, or subtracted from the System Time value.\n \n \nEthernet PTP time stamp addend register (ETH_PTPTSAR)\nAddress offset: 0x0718\nReset value: 0x0000 0000\nThis register is used by the software to readjust the clock frequency linearly to match the \nmaster clock frequency. This register value is used only when the system time is configured \nfor Fine update mode (TSFCU bit in ETH_PTPTSCR). This register content is added to a \n32-bit accumulator in every clock cycle and the system time is updated whenever the \naccumulator overflows.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTSUPNS\nTSUSS\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 TSUPNS: Time stamp update positive or negative sign\nThis bit indicates positive or negative time value. When set, the bit indicates that time \nrepresentation is negative. When cleared, it indicates that time representation is positive. \nWhen TSSTI is set (system time initialization) this bit should be zero. If this bit is set when \nTSSTU is set, the value in the Time stamp update registers is subtracted from the system \ntime. Otherwise it is added to the system time.\nBits 30:0 TSUSS: Time stamp update subseconds\nThe value in this field indicates the subsecond time to be initialized or added to the system \ntime. This value has an accuracy of 0.46 ns (in other words, a value of 0x0000_0001 is \n0.46 ns).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTSA\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 TSA: Time stamp addend\nThis register indicates the 32-bit time value to be added to the Accumulator register to \nachieve time synchronization.\n" }, { "page_number": 1224, "page_indices": { "start_index": 2413627, "end_index": 2415513 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1224 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.3 IEEE 1588 time stamp registers", 1218 ], [ 4, "Ethernet PTP target time high register (ETH_PTPTTHR)", 1224 ], [ 4, "Ethernet PTP target time low register (ETH_PTPTTLR)", 1224 ], [ 4, "Ethernet PTP time stamp status register (ETH_PTPTSSR)", 1224 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1224/1757\nRM0090 Rev 21\nEthernet PTP target time high register (ETH_PTPTTHR)\nAddress offset: 0x071C\nReset value: 0x0000 0000\nThis register contains the higher 32 bits of time to be compared with the system time for \ninterrupt event generation. The Target time high register, along with Target time low register, \nis used to schedule an interrupt event (TSARU bit in ETH_PTPTSCR) when the system time \nexceeds the value programmed in these registers.\n \n \nEthernet PTP target time low register (ETH_PTPTTLR)\nAddress offset: 0x0720\nReset value: 0x0000 0000\nThis register contains the lower 32 bits of time to be compared with the system time for \ninterrupt event generation.\n \n \nEthernet PTP time stamp status register (ETH_PTPTSSR)\nAddress offset: 0x0728\nReset value: 0x0000 0000\nThis register contains the time stamp status register.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTTSH\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 TTSH: Target time stamp high\nThis register stores the time in seconds. When the time stamp value matches or exceeds \nboth Target time stamp registers, the MAC, if enabled, generates an interrupt.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTTSL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 TTSL: Target time stamp low\nThis register stores the time in (signed) nanoseconds. When the value of the time stamp \nmatches or exceeds both Target time stamp registers, the MAC, if enabled, generates an \ninterrupt.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTSTTR\nTSSO\nro\nro\n" }, { "page_number": 1225, "page_indices": { "start_index": 2415513, "end_index": 2417371 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1225 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.3 IEEE 1588 time stamp registers", 1218 ], [ 4, "Ethernet PTP PPS control register (ETH_PTPPPSCR)", 1225 ] ], "page_content": "RM0090 Rev 21\n1225/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet PTP PPS control register (ETH_PTPPPSCR)\nAddress offset: 0x072C\nReset value: 0x0000 0000\nThis register controls the frequency of the PPS output.\n \n \nBits 31:2 Reserved, must be kept at reset value.\nBit 1 TSTTR: Time stamp target time reached\nWhen set, this bit indicates that the value of the system time is greater than or equal to the \nvalue specified in the Target time high and low registers. This bit is cleared when the \nETH_PTPTSSR register is read.\nBit 0 TSSO: Time stamp second overflow\nWhen set, this bit indicates that the second value of the time stamp has overflowed beyond \n0xFFFF FFFF.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPPSFREQ\nro\nro\nro\nro\nBits 31:4 Reserved, must be kept at reset value.\nBits 3:0 PPSFREQ: PPS frequency selection\nThe PPS output frequency is set to 2PPSFREQ Hz.\n0000: 1 Hz with a pulse width of 125 ms for binary rollover and, of 100 ms for digital rollover\n0001: 2 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)\n0010: 4 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)\n0011: 8 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)\n0100: 16 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)\n...\n1111: 32768 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)\nNote: If digital rollover is used (TSSSR=1, bit 9 in ETH_PTPTSCR), it is recommended not to \nuse the PPS output with a frequency other than 1 Hz. Otherwise, with digital rollover, \nthe PPS output has irregular waveforms at higher frequencies (though its average \nfrequency is always correct during any one-second window).\n" }, { "page_number": 1226, "page_indices": { "start_index": 2417371, "end_index": 2420005 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1226 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.4 DMA register description", 1226 ], [ 4, "Ethernet DMA bus mode register (ETH_DMABMR)", 1226 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1226/1757\nRM0090 Rev 21\n33.8.4 \nDMA register description\nThis section defines the bits for each DMA register. Non-32 bit accesses are allowed as long \nas the address is word-aligned.\nEthernet DMA bus mode register (ETH_DMABMR)\nAddress offset: 0x1000\nReset value: 0x0002 0101\nThe bus mode register establishes the bus operating modes for the DMA.\n \n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMB\nAAB\nFPM\nUSP\nRDP\nFB\nPM\nPBL\nEDFE\nDSL\nDA\nSR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrs\nBits 31:27 Reserved, must be kept at reset value.\nBit 26 MB: Mixed burst\nWhen this bit is set high and the FB bit is low, the AHB master interface starts all bursts of a \nlength greater than 16 with INCR (undefined burst). When this bit is cleared, it reverts to \nfixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below.\nBit 25 AAB: Address-aligned beats\nWhen this bit is set high and the FB bit equals 1, the AHB interface generates all bursts \naligned to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data \nbuffer’s start address) is not aligned, but subsequent bursts are aligned to the address.\nBit 24 FPM: 4xPBL mode\nWhen set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) \nfour times. Thus the DMA transfers data in a maximum of 4, 8, 16, 32, 64 and 128 beats \ndepending on the PBL value.\nBit 23 USP: Use separate PBL\nWhen set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL \nwhile the PBL value in bits [13:8] is applicable to TxDMA operations only. When this bit is \ncleared, the PBL value in bits [13:8] is applicable for both DMA engines.\nBits 22:17 RDP: Rx DMA PBL\nThese bits indicate the maximum number of beats to be transferred in one RxDMA \ntransaction. This is the maximum value that is used in a single block read/write operation. \nThe RxDMA always attempts to burst as specified in RDP each time it starts a burst transfer \non the host bus. RDP can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. \nAny other value results in undefined behavior.\nThese bits are valid and applicable only when USP is set high.\nBit 16 FB: Fixed burst\nThis bit controls whether the AHB Master interface performs fixed burst transfers or not. \nWhen set, the AHB uses only SINGLE, INCR4, INCR8 or INCR16 during start of normal \nburst transfers. When reset, the AHB uses SINGLE and INCR burst transfer operations.\n" }, { "page_number": 1227, "page_indices": { "start_index": 2420005, "end_index": 2422882 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1227 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.4 DMA register description", 1226 ], [ 4, "Ethernet DMA transmit poll demand register (ETH_DMATPDR)", 1227 ] ], "page_content": "RM0090 Rev 21\n1227/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet DMA transmit poll demand register (ETH_DMATPDR)\nAddress offset: 0x1004\nReset value: 0x0000 0000\nThis register is used by the application to instruct the DMA to poll the transmit descriptor list. \nThe transmit poll demand register enables the Transmit DMA to check whether or not the \ncurrent descriptor is owned by DMA. The Transmit Poll Demand command is given to wake \nup the TxDMA if it is in Suspend mode. The TxDMA can go into Suspend mode due to an \nunderflow error in a transmitted frame or due to the unavailability of descriptors owned by \nBits 15:14 PM: Rx Tx priority ratio\nRxDMA requests are given priority over TxDMA requests in the following ratio:\n00: 1:1\n01: 2:1\n10: 3:1\n11: 4:1\nThis is valid only when the DA bit is cleared.\nBits 13:8 PBL: Programmable burst length\nThese bits indicate the maximum number of beats to be transferred in one DMA transaction. \nThis is the maximum value that is used in a single block read/write operation. The DMA \nalways attempts to burst as specified in PBL each time it starts a burst transfer on the host \nbus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other \nvalue results in undefined behavior. When USP is set, this PBL value is applicable for \nTxDMA transactions only.\nThe PBL values have the following limitations:\n– The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx \nFIFO.\n– The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO.\n– If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx \nFIFO depths must be considered.\n– Do not program out-of-range PBL values, because the system may not behave properly.\nBit 7 EDFE: Enhanced descriptor format enable\nWhen this bit is set, the enhanced descriptor format is enabled and the descriptor size is \nincreased to 32 bytes (8 words). This is required when time stamping is activated (TSE=1, \nETH_PTPTSCR bit 0) or if IPv4 checksum offload is activated (IPCO=1, ETH_MACCR bit \n10).\nBits 6:2 DSL: Descriptor skip length\nThis bit specifies the number of words to skip between two unchained descriptors. The \naddress skipping starts from the end of current descriptor to the start of next descriptor. \nWhen DSL value equals zero, the descriptor table is taken as contiguous by the DMA, in \nRing mode.\nBit 1 DA: DMA Arbitration\n0: Round-robin with Rx:Tx priority given in bits [15:14]\n1: Rx has priority over Tx\nBit 0 SR: Software reset\nWhen this bit is set, the MAC DMA controller resets all MAC Subsystem internal registers \nand logic. It is cleared automatically after the reset operation has completed in all of the core \nclock domains. Read a 0 value in this bit before re-programming any register of the core.\n" }, { "page_number": 1228, "page_indices": { "start_index": 2422882, "end_index": 2425339 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1228 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.4 DMA register description", 1226 ], [ 4, "EHERNET DMA receive poll demand register (ETH_DMARPDR)", 1228 ], [ 4, "Ethernet DMA receive descriptor list address register (ETH_DMARDLAR)", 1228 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1228/1757\nRM0090 Rev 21\ntransmit DMA. You can issue this command anytime and the TxDMA resets it once it starts \nre-fetching the current descriptor from host memory.\n \n \nEHERNET DMA receive poll demand register (ETH_DMARPDR)\nAddress offset: 0x1008\nReset value: 0x0000 0000\nThis register is used by the application to instruct the DMA to poll the receive descriptor list. \nThe Receive poll demand register enables the receive DMA to check for new descriptors. \nThis command is given to wake up the RxDMA from Suspend state. The RxDMA can go into \nSuspend state only due to the unavailability of descriptors owned by it.\n \n \nEthernet DMA receive descriptor list address register (ETH_DMARDLAR)\nAddress offset: 0x100C\nReset value: 0x0000 0000\nThe Receive descriptor list address register points to the start of the receive descriptor list. \nThe descriptor lists reside in the STM32F4xx's physical memory space and must be word-\naligned. The DMA internally converts it to bus-width aligned address by making the \ncorresponding LS bits low. Writing to the ETH_DMARDLAR register is permitted only when \nreception is stopped. When stopped, the ETH_DMARDLAR register must be written to \nbefore the receive Start command is given.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTPD\nrw\nBits 31:0 TPD: Transmit poll demand\nWhen these bits are written with any value, the DMA reads the current descriptor pointed to \nby the ETH_DMACHTDR register. If that descriptor is not available (owned by Host), \ntransmission returns to the Suspend state and ETH_DMASR register bit 2 is asserted. If the \ndescriptor is available, transmission resumes.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRPD\nrw_wt\nBits 31:0 RPD: Receive poll demand\nWhen these bits are written with any value, the DMA reads the current descriptor pointed to \nby the ETH_DMACHRDR register. If that descriptor is not available (owned by Host), \nreception returns to the Suspended state and ETH_DMASR register bit 7 is not asserted. If \nthe descriptor is available, the Receive DMA returns to active state.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSRL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1229, "page_indices": { "start_index": 2425339, "end_index": 2427817 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1229 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.4 DMA register description", 1226 ], [ 4, "Ethernet DMA transmit descriptor list address register (ETH_DMATDLAR)", 1229 ], [ 4, "Ethernet DMA status register (ETH_DMASR)", 1229 ] ], "page_content": "RM0090 Rev 21\n1229/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n \nEthernet DMA transmit descriptor list address register (ETH_DMATDLAR)\nAddress offset: 0x1010\nReset value: 0x0000 0000\nThe Transmit descriptor list address register points to the start of the transmit descriptor list. \nThe descriptor lists reside in the STM32F4xx's physical memory space and must be word-\naligned. The DMA internally converts it to bus-width-aligned address by taking the \ncorresponding LSB to low. Writing to the ETH_DMATDLAR register is permitted only when \ntransmission has stopped. Once transmission has stopped, the ETH_DMATDLAR register \ncan be written before the transmission Start command is given.\n \n \nEthernet DMA status register (ETH_DMASR)\nAddress offset: 0x1014\nReset value: 0x0000 0000\nThe Status register contains all the status bits that the DMA reports to the application. The \nETH_DMASR register is usually read by the software driver during an interrupt service \nroutine or polling. Most of the fields in this register cause the host to be interrupted. The \nETH_DMASR register bits are not cleared when read. Writing 1 to (unreserved) bits in \nETH_DMASR register[16:0] clears them and writing 0 has no effect. Each field (bits [16:0]) \ncan be masked by masking the appropriate bit in the ETH_DMAIER register.\n \nBits 31:0 SRL: Start of receive list\nThis field contains the base address of the first descriptor in the receive descriptor list. The \nLSB bits [1/2/3:0] for 32/64/128-bit bus width) are internally ignored and taken as all-zero by \nthe DMA. Hence these LSB bits are read only.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSTL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 STL: Start of transmit list\nThis field contains the base address of the first descriptor in the transmit descriptor list. The \nLSB bits [1/2/3:0] for 32/64/128-bit bus width) are internally ignored and taken as all-zero \nby the DMA. Hence these LSB bits are read-only.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTSTS\nPMTS\nMMCS\nReserved\nEBS\nTPS\nRPS\nNIS\nAIS\nERS\nFBES\nReserved\nETS\nRWTS\nRPSS\nRBUS\nRS\nTUS\nROS\nTJTS\nTBUS\nTPSS\nTS\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\nrc-\nw1\n" }, { "page_number": 1230, "page_indices": { "start_index": 2427817, "end_index": 2430416 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1230 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.4 DMA register description", 1226 ], [ 4, "Ethernet DMA status register (ETH_DMASR)", 1229 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1230/1757\nRM0090 Rev 21\n \nBits 31:30 Reserved, must be kept at reset value.\nBit 29 TSTS: Time stamp trigger status\nThis bit indicates an interrupt event in the MAC core's Time stamp generator block. The \nsoftware must read the MAC core’s status register, clearing its source (bit 9), to reset this bit \nto 0. When this bit is high an interrupt is generated if enabled.\nBit 28 PMTS: PMT status\nThis bit indicates an event in the MAC core’s PMT. The software must read the \ncorresponding registers in the MAC core to get the exact cause of interrupt and clear its \nsource to reset this bit to 0. The interrupt is generated when this bit is high if enabled.\nBit 27 MMCS: MMC status\nThis bit reflects an event in the MMC of the MAC core. The software must read the \ncorresponding registers in the MAC core to get the exact cause of interrupt and clear the \nsource of interrupt to make this bit as 0. The interrupt is generated when this bit is high if \nenabled.\nBit 26 Reserved, must be kept at reset value.\nBits 25:23 EBS: Error bits status\nThese bits indicate the type of error that caused a bus error (error response on the AHB \ninterface). Valid only with the fatal bus error bit (ETH_DMASR register [13]) set. This field \ndoes not generate an interrupt.\nBit 231 Error during data transfer by TxDMA \n0 Error during data transfer by RxDMA\nBit 24 1 Error during read transfer\n0 Error during write transfer\nBit 25 1 Error during descriptor access\n0 Error during data buffer access\nBits 22:20 TPS: Transmit process state\nThese bits indicate the Transmit DMA FSM state. This field does not generate an interrupt.\n000: Stopped; Reset or Stop Transmit Command issued\n001: Running; Fetching transmit transfer descriptor\n010: Running; Waiting for status\n011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx \nFIFO)\n100, 101: Reserved for future use\n110: Suspended; Transmit descriptor unavailable or transmit buffer underflow\n111: Running; Closing transmit descriptor\nBits 19:17 RPS: Receive process state \nThese bits indicate the Receive DMA FSM state. This field does not generate an interrupt.\n000: Stopped: Reset or Stop Receive Command issued\n001: Running: Fetching receive transfer descriptor\n010: Reserved for future use\n011: Running: Waiting for receive packet\n100: Suspended: Receive descriptor unavailable\n101: Running: Closing receive descriptor\n110: Reserved for future use\n111: Running: Transferring the receive packet data from receive buffer to host memory\n" }, { "page_number": 1231, "page_indices": { "start_index": 2430416, "end_index": 2433146 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1231 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.4 DMA register description", 1226 ], [ 4, "Ethernet DMA status register (ETH_DMASR)", 1229 ] ], "page_content": "RM0090 Rev 21\n1231/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nBit 16 NIS: Normal interrupt summary\nThe normal interrupt summary bit value is the logical OR of the following when the \ncorresponding interrupt bits are enabled in the ETH_DMAIER register:\n– ETH_DMASR [0]: Transmit interrupt\n– ETH_DMASR [2]: Transmit buffer unavailable\n– ETH_DMASR [6]: Receive interrupt\n– ETH_DMASR [14]: Early receive interrupt\nOnly unmasked bits affect the normal interrupt summary bit.\nThis is a sticky bit and it must be cleared (by writing a 1 to this bit) each time a corresponding \nbit that causes NIS to be set is cleared.\nBit 15 AIS: Abnormal interrupt summary\nThe abnormal interrupt summary bit value is the logical OR of the following when the \ncorresponding interrupt bits are enabled in the ETH_DMAIER register:\n– ETH_DMASR [1]:Transmit process stopped\n– ETH_DMASR [3]:Transmit jabber timeout\n– ETH_DMASR [4]: Receive FIFO overflow\n– ETH_DMASR [5]: Transmit underflow\n– ETH_DMASR [7]: Receive buffer unavailable\n– ETH_DMASR [8]: Receive process stopped\n– ETH_DMASR [9]: Receive watchdog timeout\n– ETH_DMASR [10]: Early transmit interrupt\n– ETH_DMASR [13]: Fatal bus error\nOnly unmasked bits affect the abnormal interrupt summary bit.\nThis is a sticky bit and it must be cleared each time a corresponding bit that causes AIS to be \nset is cleared.\nBit 14 ERS: Early receive status\nThis bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt \nETH_DMASR [6] automatically clears this bit.\nBit 13 FBES: Fatal bus error status\nThis bit indicates that a bus error occurred, as detailed in [25:23]. When this bit is set, the \ncorresponding DMA engine disables all its bus accesses.\nBits 12:11 Reserved, must be kept at reset value.\nBit 10 ETS: Early transmit status\nThis bit indicates that the frame to be transmitted was fully transferred to the Transmit FIFO.\nBit 9\nRWTS: Receive watchdog timeout status\nThis bit is asserted when a frame with a length greater than 2 048 bytes is received.\nBit 8 RPSS: Receive process stopped status\nThis bit is asserted when the receive process enters the Stopped state.\nBit 7 RBUS: Receive buffer unavailable status\nThis bit indicates that the next descriptor in the receive list is owned by the host and cannot \nbe acquired by the DMA. Receive process is suspended. To resume processing receive \ndescriptors, the host should change the ownership of the descriptor and issue a Receive Poll \nDemand command. If no Receive Poll Demand is issued, receive process resumes when the \nnext recognized incoming frame is received. ETH_DMASR [7] is set only when the previous \nreceive descriptor was owned by the DMA.\n" }, { "page_number": 1232, "page_indices": { "start_index": 2433146, "end_index": 2435815 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1232 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.4 DMA register description", 1226 ], [ 4, "Ethernet DMA operation mode register (ETH_DMAOMR)", 1232 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1232/1757\nRM0090 Rev 21\nEthernet DMA operation mode register (ETH_DMAOMR)\nAddress offset: 0x1018\nReset value: 0x0000 0000\nThe operation mode register establishes the Transmit and Receive operating modes and \ncommands. The ETH_DMAOMR register should be the last CSR to be written as part of \nDMA initialization.\n \n \nBit 6 RS: Receive status\nThis bit indicates the completion of the frame reception. Specific frame status information \nhas been posted in the descriptor. Reception remains in the Running state.\nBit 5 TUS: Transmit underflow status\nThis bit indicates that the transmit buffer had an underflow during frame transmission. \nTransmission is suspended and an underflow error TDES0[1] is set.\nBit 4 ROS: Receive overflow status\nThis bit indicates that the receive buffer had an overflow during frame reception. If the partial \nframe is transferred to the application, the overflow status is set in RDES0[11].\nBit 3 TJTS: Transmit jabber timeout status\nThis bit indicates that the transmit jabber timer expired, meaning that the transmitter had \nbeen excessively active. The transmission process is aborted and placed in the Stopped \nstate. This causes the transmit jabber timeout TDES0[14] flag to be asserted.\nBit 2 TBUS: Transmit buffer unavailable status\nThis bit indicates that the next descriptor in the transmit list is owned by the host and cannot \nbe acquired by the DMA. Transmission is suspended. Bits [22:20] explain the transmit \nprocess state transitions. To resume processing transmit descriptors, the host should change \nthe ownership of the bit of the descriptor and then issue a Transmit Poll Demand command.\nBit 1 TPSS: Transmit process stopped status\nThis bit is set when the transmission is stopped.\nBit 0 TS: Transmit status\nThis bit indicates that frame transmission is finished and TDES1[31] is set in the first \ndescriptor.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDTCEFD\nRSF\nDFRF\nReserved\nTSF\nFTF\nReserved\nTTC\nST\nReserved\nFEF\nFUGF\nReserved\nRTC\nOSF\nSR\nReserved\nrw\nrw\nrw\nrw\nrs\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:27 Reserved, must be kept at reset value.\nBit 26 DTCEFD: Dropping of TCP/IP checksum error frames disable\nWhen this bit is set, the core does not drop frames that only have errors detected by the \nreceive checksum offload engine. Such frames do not have any errors (including FCS error) \nin the Ethernet frame received by the MAC but have errors in the encapsulated payload only. \nWhen this bit is cleared, all error frames are dropped if the FEF bit is reset.\n" }, { "page_number": 1233, "page_indices": { "start_index": 2435815, "end_index": 2438915 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1233 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.4 DMA register description", 1226 ], [ 4, "Ethernet DMA operation mode register (ETH_DMAOMR)", 1232 ] ], "page_content": "RM0090 Rev 21\n1233/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nBit 25 RSF: Receive store and forward\nWhen this bit is set, a frame is read from the Rx FIFO after the complete frame has been \nwritten to it, ignoring RTC bits. When this bit is cleared, the Rx FIFO operates in Cut-through \nmode, subject to the threshold specified by the RTC bits.\nBit 24 DFRF: Disable flushing of received frames\nWhen this bit is set, the RxDMA does not flush any frames due to the unavailability of \nreceive descriptors/buffers as it does normally when this bit is cleared (see Receive process \nsuspended).\nBits 23:22 Reserved, must be kept at reset value.\nBit 21 TSF: Transmit store and forward\nWhen this bit is set, transmission starts when a full frame resides in the Transmit FIFO. \nWhen this bit is set, the TTC values specified by the ETH_DMAOMR register bits [16:14] are \nignored.\nWhen this bit is cleared, the TTC values specified by the ETH_DMAOMR register bits \n[16:14] are taken into account.\nThis bit should be changed only when transmission is stopped.\nBit 20 FTF: Flush transmit FIFO\nWhen this bit is set, the transmit FIFO controller logic is reset to its default values and thus \nall data in the Tx FIFO are lost/flushed. This bit is cleared internally when the flushing \noperation is complete. The Operation mode register should not be written to until this bit is \ncleared.\nBits 19:17 Reserved, must be kept at reset value.\nBits 16:14 TTC: Transmit threshold control\nThese three bits control the threshold level of the Transmit FIFO. Transmission starts when \nthe frame size within the Transmit FIFO is larger than the threshold. In addition, full frames \nwith a length less than the threshold are also transmitted. These bits are used only when the \nTSF bit (Bit 21) is cleared.\n000: 64\n001: 128\n010: 192\n011: 256\n100: 40\n101: 32\n110: 24\n111: 16\nBit 13 ST: Start/stop transmission \nWhen this bit is set, transmission is placed in the Running state, and the DMA checks the \ntransmit list at the current position for a frame to be transmitted. Descriptor acquisition is \nattempted either from the current position in the list, which is the transmit list base address \nset by the ETH_DMATDLAR register, or from the position retained when transmission was \nstopped previously. If the current descriptor is not owned by the DMA, transmission enters \nthe Suspended state and the transmit buffer unavailable bit (ETH_DMASR [2]) is set. The \nStart Transmission command is effective only when transmission is stopped. If the command \nis issued before setting the DMA ETH_DMATDLAR register, the DMA behavior is \nunpredictable.\nWhen this bit is cleared, the transmission process is placed in the Stopped state after \ncompleting the transmission of the current frame. The next descriptor position in the transmit \nlist is saved, and becomes the current position when transmission is restarted. The Stop \nTransmission command is effective only when the transmission of the current frame is \ncomplete or when the transmission is in the Suspended state.\n" }, { "page_number": 1234, "page_indices": { "start_index": 2438915, "end_index": 2441870 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1234 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.4 DMA register description", 1226 ], [ 4, "Ethernet DMA operation mode register (ETH_DMAOMR)", 1232 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1234/1757\nRM0090 Rev 21\nBits 12:8 Reserved, must be kept at reset value.\nBit 7 FEF: Forward error frames\nWhen this bit is set, all frames except runt error frames are forwarded to the DMA.\nWhen this bit is cleared, the Rx FIFO drops frames with error status (CRC error, collision \nerror, giant frame, watchdog timeout, overflow). However, if the frame’s start byte (write) \npointer is already transferred to the read controller side (in Threshold mode), then the \nframes are not dropped. The Rx FIFO drops the error frames if that frame's start byte is not \ntransferred (output) on the ARI bus.\nBit 6 FUGF: Forward undersized good frames\nWhen this bit is set, the Rx FIFO forwards undersized frames (frames with no error and \nlength less than 64 bytes) including pad-bytes and CRC).\nWhen this bit is cleared, the Rx FIFO drops all frames of less than 64 bytes, unless such a \nframe has already been transferred due to lower value of receive threshold (e.g., RTC = 01).\nBit 5 Reserved, must be kept at reset value.\nBits 4:3 RTC: Receive threshold control\nThese two bits control the threshold level of the Receive FIFO. Transfer (request) to DMA \nstarts when the frame size within the Receive FIFO is larger than the threshold. In addition, \nfull frames with a length less than the threshold are transferred automatically.\nNote: Note that value of 11 is not applicable if the configured Receive FIFO size is 128 bytes.\nNote: These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is \nset to 1.\n00: 64\n01: 32\n10: 96\n11: 128\nBit 2 OSF: Operate on second frame\nWhen this bit is set, this bit instructs the DMA to process a second frame of Transmit data \neven before status for first frame is obtained.\nBit 1 SR: Start/stop receive\nWhen this bit is set, the receive process is placed in the Running state. The DMA attempts to \nacquire the descriptor from the receive list and processes incoming frames. Descriptor \nacquisition is attempted from the current position in the list, which is the address set by the \nDMA ETH_DMARDLAR register or the position retained when the receive process was \npreviously stopped. If no descriptor is owned by the DMA, reception is suspended and the \nreceive buffer unavailable bit (ETH_DMASR [7]) is set. The Start Receive command is \neffective only when reception has stopped. If the command was issued before setting the \nDMA ETH_DMARDLAR register, the DMA behavior is unpredictable.\nWhen this bit is cleared, RxDMA operation is stopped after the transfer of the current frame. \nThe next descriptor position in the receive list is saved and becomes the current position \nwhen the receive process is restarted. The Stop Receive command is effective only when \nthe Receive process is in either the Running (waiting for receive packet) or the Suspended \nstate.\nBit 0 Reserved, must be kept at reset value.\n" }, { "page_number": 1235, "page_indices": { "start_index": 2441870, "end_index": 2444306 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1235 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.4 DMA register description", 1226 ], [ 4, "Ethernet DMA interrupt enable register (ETH_DMAIER)", 1235 ] ], "page_content": "RM0090 Rev 21\n1235/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet DMA interrupt enable register (ETH_DMAIER)\nAddress offset: 0x101C\nReset value: 0x0000 0000\nThe Interrupt enable register enables the interrupts reported by ETH_DMASR. Setting a bit \nto 1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are \ndisabled.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNISE\nAISE\nERIE\nFBEIE\nReserved\nETIE\nRWTIE\nRPSIE\nRBUIE\nRIE\nTUIE\nROIE\nTJTIE\nTBUIE\nTPSIE\nTIE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:17 Reserved, must be kept at reset value.\nBit 16 NISE: Normal interrupt summary enable\nWhen this bit is set, a normal interrupt is enabled. When this bit is cleared, a normal \ninterrupt is disabled. This bit enables the following bits:\n– ETH_DMASR [0]: Transmit Interrupt\n– ETH_DMASR [2]: Transmit buffer unavailable\n– ETH_DMASR [6]: Receive interrupt\n– ETH_DMASR [14]: Early receive interrupt\nBit 15 AISE: Abnormal interrupt summary enable\nWhen this bit is set, an abnormal interrupt is enabled. When this bit is cleared, an abnormal \ninterrupt is disabled. This bit enables the following bits:\n– ETH_DMASR [1]: Transmit process stopped\n– ETH_DMASR [3]: Transmit jabber timeout\n– ETH_DMASR [4]: Receive overflow\n– ETH_DMASR [5]: Transmit underflow\n– ETH_DMASR [7]: Receive buffer unavailable\n– ETH_DMASR [8]: Receive process stopped\n– ETH_DMASR [9]: Receive watchdog timeout\n– ETH_DMASR [10]: Early transmit interrupt\n– ETH_DMASR [13]: Fatal bus error\nBit 14 ERIE: Early receive interrupt enable\nWhen this bit is set with the normal interrupt summary enable bit (ETH_DMAIER \nregister[16]), the early receive interrupt is enabled.\nWhen this bit is cleared, the early receive interrupt is disabled.\nBit 13 FBEIE: Fatal bus error interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER \nregister[15]), the fatal bus error interrupt is enabled.\nWhen this bit is cleared, the fatal bus error enable interrupt is disabled.\nBits 12:11 Reserved, must be kept at reset value.\nBit 10 ETIE: Early transmit interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER register \n[15]), the early transmit interrupt is enabled.\nWhen this bit is cleared, the early transmit interrupt is disabled.\n" }, { "page_number": 1236, "page_indices": { "start_index": 2444306, "end_index": 2447292 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1236 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.4 DMA register description", 1226 ], [ 4, "Ethernet DMA interrupt enable register (ETH_DMAIER)", 1235 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1236/1757\nRM0090 Rev 21\nThe Ethernet interrupt is generated only when the TSTS or PMTS bits of the DMA Status \nregister is asserted with their corresponding interrupt are unmasked, or when the NIS/AIS \nStatus bit is asserted and the corresponding Interrupt Enable bits (NISE/AISE) are enabled.\nBit 9 RWTIE: receive watchdog timeout interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER \nregister[15]), the receive watchdog timeout interrupt is enabled.\nWhen this bit is cleared, the receive watchdog timeout interrupt is disabled.\nBit 8 RPSIE: Receive process stopped interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER \nregister[15]), the receive stopped interrupt is enabled. When this bit is cleared, the receive \nstopped interrupt is disabled.\nBit 7 RBUIE: Receive buffer unavailable interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER \nregister[15]), the receive buffer unavailable interrupt is enabled.\nWhen this bit is cleared, the receive buffer unavailable interrupt is disabled.\nBit 6 RIE: Receive interrupt enable\nWhen this bit is set with the normal interrupt summary enable bit (ETH_DMAIER \nregister[16]), the receive interrupt is enabled.\nWhen this bit is cleared, the receive interrupt is disabled.\nBit 5 TUIE: Underflow interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER \nregister[15]), the transmit underflow interrupt is enabled.\nWhen this bit is cleared, the underflow interrupt is disabled.\nBit 4\nROIE: Overflow interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER \nregister[15]), the receive overflow interrupt is enabled.\nWhen this bit is cleared, the overflow interrupt is disabled.\nBit 3 TJTIE: Transmit jabber timeout interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER \nregister[15]), the transmit jabber timeout interrupt is enabled.\nWhen this bit is cleared, the transmit jabber timeout interrupt is disabled.\nBit 2 TBUIE: Transmit buffer unavailable interrupt enable\nWhen this bit is set with the normal interrupt summary enable bit (ETH_DMAIER \nregister[16]), the transmit buffer unavailable interrupt is enabled.\nWhen this bit is cleared, the transmit buffer unavailable interrupt is disabled.\nBit 1 TPSIE: Transmit process stopped interrupt enable\nWhen this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER \nregister[15]), the transmission stopped interrupt is enabled.\nWhen this bit is cleared, the transmission stopped interrupt is disabled.\nBit 0 TIE: Transmit interrupt enable\nWhen this bit is set with the normal interrupt summary enable bit (ETH_DMAIER \nregister[16]), the transmit interrupt is enabled.\nWhen this bit is cleared, the transmit interrupt is disabled.\n" }, { "page_number": 1237, "page_indices": { "start_index": 2447292, "end_index": 2449780 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1237 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.4 DMA register description", 1226 ], [ 4, "Ethernet DMA missed frame and buffer overflow counter register (ETH_DMAMFBOCR)", 1237 ], [ 4, "Ethernet DMA receive status watchdog timer register (ETH_DMARSWTR)", 1237 ] ], "page_content": "RM0090 Rev 21\n1237/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet DMA missed frame and buffer overflow counter register \n(ETH_DMAMFBOCR)\nAddress offset: 0x1020\nReset value: 0x0000 0000\nThe DMA maintains two counters to track the number of missed frames during reception. \nThis register reports the current value of the counter. The counter is used for diagnostic \npurposes. Bits [15:0] indicate missed frames due to the STM32F4xx buffer being \nunavailable (no receive descriptor was available). Bits [27:17] indicate missed frames due to \nRx FIFO overflow conditions and runt frames (good frames of less than 64 bytes).\n \n \nEthernet DMA receive status watchdog timer register (ETH_DMARSWTR)\nAddress offset: 0x1024\nReset value: 0x0000 0000\nThis register, when written with a non-zero value, enables the watchdog timer for the receive \nstatus (RS, ETH_DMASR[6]).\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOFOC\nMFA\nOMFC\nMFC\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nrc_\nr\nBits 31:29 Reserved, must be kept at reset value.\nBit 28 OFOC: Overflow bit for FIFO overflow counter\nBits 27:17 MFA: Missed frames by the application\nIndicates the number of frames missed by the application\nBit 16 OMFC: Overflow bit for missed frame counter\nBits 15:0 MFC: Missed frames by the controller\nIndicates the number of frames missed by the Controller due to the host receive buffer being \nunavailable. This counter is incremented each time the DMA discards an incoming frame.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRSWTC\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBits 7:0 RSWTC: Receive status (RS) watchdog timer count\nIndicates the number of HCLK clock cycles multiplied by 256 for which the watchdog timer \nis set. The watchdog timer gets triggered with the programmed value after the RxDMA \ncompletes the transfer of a frame for which the RS status bit is not set due to the setting of \nRDES1[31] in the corresponding descriptor. When the watchdog timer runs out, the RS bit \nis set and the timer is stopped. The watchdog timer is reset when the RS bit is set high due \nto automatic setting of RS as per RDES1[31] of any received frame.\n" }, { "page_number": 1238, "page_indices": { "start_index": 2449780, "end_index": 2451493 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1238 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.4 DMA register description", 1226 ], [ 4, "Ethernet DMA current host transmit descriptor register (ETH_DMACHTDR)", 1238 ], [ 4, "Ethernet DMA current host receive descriptor register (ETH_DMACHRDR)", 1238 ], [ 4, "Ethernet DMA current host transmit buffer address register (ETH_DMACHTBAR)", 1238 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1238/1757\nRM0090 Rev 21\nEthernet DMA current host transmit descriptor register (ETH_DMACHTDR)\nAddress offset: 0x1048\nReset value: 0x0000 0000\nThe Current host transmit descriptor register points to the start address of the current \ntransmit descriptor read by the DMA.\n \n \nEthernet DMA current host receive descriptor register (ETH_DMACHRDR)\nAddress offset: 0x104C\nReset value: 0x0000 0000\nThe Current host receive descriptor register points to the start address of the current receive \ndescriptor read by the DMA.\n \n \nEthernet DMA current host transmit buffer address register\n(ETH_DMACHTBAR)\nAddress offset: 0x1050\nReset value: 0x0000 0000\nThe Current host transmit buffer address register points to the current transmit buffer \naddress being read by the DMA.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nHTDAP\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 HTDAP: Host transmit descriptor address pointer\nCleared . Pointer updated by DMA during operation.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nHRDAP\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 HRDAP: Host receive descriptor address pointer\nCleared On Reset. Pointer updated by DMA during operation.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nHTBAP\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 HTBAP: Host transmit buffer address pointer\nCleared On Reset. Pointer updated by DMA during operation.\n" }, { "page_number": 1239, "page_indices": { "start_index": 2451493, "end_index": 2453401 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1239 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.4 DMA register description", 1226 ], [ 4, "Ethernet DMA current host receive buffer address register (ETH_DMACHRBAR)", 1239 ], [ 3, "33.8.5 Ethernet register maps", 1239 ] ], "page_content": "RM0090 Rev 21\n1239/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\nEthernet DMA current host receive buffer address register \n(ETH_DMACHRBAR)\nAddress offset: 0x1054\nReset value: 0x0000 0000\nThe current host receive buffer address register points to the current receive buffer address \nbeing read by the DMA.\n \n \n33.8.5 \nEthernet register maps\nTable 196 gives the ETH register map and reset values.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nHRBAP\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 HRBAP: Host receive buffer address pointer\nCleared On Reset. Pointer updated by DMA during operation.\nTable 196. Ethernet register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nETH_MACCR\nReserved\nCSTF\neserved\nWD\nJD\nReserved\nIFG\nCSD\nReserved\nFES\nROD\nLM\nDM\nIPCO\nRD\nReserved\nAPCS\nBL\nDC\nTE\nRE\nReserved\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x04\nETH_MACFFR\nRA\nReserved\nHPF\nSAF\nSAIF\nPCF\nBFD\nPAM\nDAIF\nHM\nHU\nPM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x08\nETH_MACHTHR\nHTH[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x0C\nETH_MACHTLR\nHTL[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10\nETH_MACMIIAR\nReserved\nPA\nMR\nCR\nM\nW\nM\nB\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x14\nETH_MACMIIDR\nReserved\nMD\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x18\nETH_MACFCR\nPT\nReserved\nZQPD\nReserved\nPLT\nUPFD\nRFCE\nTFCE\nFCB/BPA\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C\nETH_\nMACVLANTR\nReserved\nVLANTC\nVLANTI\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x28\nETH_\nMACRWUFFR\nFrame filter reg0\\Frame filter reg1\\Frame filter reg2\\Frame filter reg3\\Frame filter reg4\\...\\Frame filter reg7\nReset value\n0\n" }, { "page_number": 1240, "page_indices": { "start_index": 2453401, "end_index": 2455299 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1240 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.5 Ethernet register maps", 1239 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1240/1757\nRM0090 Rev 21\n0x2C\nETH_\nMACPMTCSR\nWFFRPR\nReserved\nGU\nReserved\nWFR\nMPR\nReserved\nWFE\nMPE\nPD\nReset value\n0\n0\n0\n0\n0\n0\n0\n0x34\nETH_\nMACDBGR\nReserved\nTFF\nTFNEGU\nReserved\nTFWA\nTFRS\nMTP\nMTFCS\nMMTEA\nReserved\nRFFL\nReserved\nRFRCS\nRFWRA\nReserved\nMSFRWCS\nMMRPEA\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x38\nETH_MACSR\nNot applicable\nReserved\nTSTS\nReserved\nMMCTS\nMMCRS\nMMCS\nPMTS\nReserve\nd\nReset value\n0\n0\n0\n0\n0\n0x3C\nETH_MACIMR\nNot applicable\nReserved\nTSTIM\nReserved\nPMTIM\nReserve\nd\nReset value\n0\n0\n0x40\nETH_MACA0HR\nMO\nReserved\nMACA0H\nReset value\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x44\nETH_MACA0LR\nMACA0L\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x48\nETH_MACA1HR\nAE\nSA\nMBC[6:0]\nReserved\nMACA1H\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x4C\nETH_MACA1LR\nMACA1L\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x50\nETH_MACA2HR\nAE\nSA\nMBC\nReserved\nMACA2H\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x54\nETH_MACA2LR\nMACA2L\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x58\nETH_MACA3HR\nAE\nSA\nMBC\nReserved\nMACA3H\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x5C\nETH_MACA3LR\nMACA3L\nReset value\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x100\nETH_MMCCR\nReserved\nMCFHP\nMCP\nMCF\nROR\nCSR\nCR\nReset value\n0\n0\n0\n0\n0\n0\n0x104\nETH_MMCRIR\nReserved\nRGUFS\nReserved\nRFAES\nRFCES\nReserved\nReset value\n0\n0\n0\n0x108\nETH_MMCTIR\nReserved\nTGFS\nReserved\nTGFMSCS\nTGFSCS\nReserved\nReset value\n0\n0\n0\n0x10C\nETH_MMCRIMR\nReserved\nRGUFM\nReserved\nRFAEM\nRFCEM\nReserved\nReset value\n0\n0\n0\nTable 196. Ethernet register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1241, "page_indices": { "start_index": 2455299, "end_index": 2457269 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1241 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.5 Ethernet register maps", 1239 ] ], "page_content": "RM0090 Rev 21\n1241/1757\nRM0090\nEthernet (ETH): media access control (MAC) with DMA controller\n1242\n0x110\nETH_MMCTIMR\nReserved\nTGFM\nReserved\nTGFMSCM\nTGFSCM\nReserved\nReset value\n0\n0\n0\n0x14C\nETH_MMCTGFS\nCCR\nTGFSCC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x150\nETH_MMCTGF\nMSCCR\nTGFMSCC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x168\nETH_MMCTGF\nCR\nTGFC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x194\nETH_MMCRFC\nECR\nRFCEC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x198\nETH_MMCRFAE\nCR\nRFAEC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1C4\nETH_MMCRGU\nFCR\nRGUFC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x700\nETH_PTPTSCR\nReserved\nTSPFFMAE\nTSCNT\nTSSMRME\nTSSEME\nTSSIPV4FE\nTSSIPV6FE\nTSSPTPOEFE\nTSPTPPSV2E\nTSSSR\nTSSARFE\nReserved\nTTSARU\nTSITE\nTSSTU\nTSSTI\nTSFCU\nTSE\nReset value\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x704\nETH_PTPSSIR\nReserved\nSTSSI\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x708\nETH_PTPTSHR\nSTS[31:0]\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x70C\nETH_PTPTSLR\nSTPNS\nSTSS\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x710\nETH_PTPTSHU\nR\nTSUS\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x714\nETH_PTPTSLU\nR\nTSUPNS\nTSUSS\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x718\nETH_PTPTSAR\nTSA\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x71C\nETH_PTPTTHR\nTTSH\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x720\nETH_PTPTTLR\nTTSL\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 196. Ethernet register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1242, "page_indices": { "start_index": 2457269, "end_index": 2459389 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1242 }, "toc_details": [ [ 1, "33 Ethernet (ETH): media access control (MAC) with DMA controller", 1125 ], [ 2, "33.8 Ethernet register descriptions", 1194 ], [ 3, "33.8.5 Ethernet register maps", 1239 ] ], "page_content": "Ethernet (ETH): media access control (MAC) with DMA controller\nRM0090\n1242/1757\nRM0090 Rev 21\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0x728\nETH_PTPTSSR\nReserved\nTSTTR\nTSSO\nReset value\n0\n0\n0x72C\nETH_PTPPPSC\nR\nReserved\nPPS\nFREQ\nReset value\n0\n0\n0\n0x1000\nETH_DMABMR\nReserved\nMB\nAAB\nFPM\nUSP\nRDP\nFB\nPM\nPBL\nEDFE\nDSL\nDA\nSR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n1\n0x1004\nETH_DMATPDR\nTPD\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1008\nETH_DMARPDR\nRPD\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x100C\nETH_DMARDLA\nR\nSRL\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1010\nETH_DMATDLA\nR\nSTL\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1014\nETH_DMASR\nReserved\nTSTS\nPMTS\nMMCS\nReserved\nEBS\nTPS\nRPS\nNIS\nAIS\nERS\nFBES\nReserved\nETS\nRWTS\nRPSS\nRBUS\nRS\nTUS\nROS\nTJTS\nTBUS\nTPSS\nTS\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1018\nETH_DMAOMR\nReserved\nDTCEFD\nRSF\nDFRF\nReserved\nTSF\nFTF\nReserved\nTTC\nST\nReserved\nFEF\nFUGF\nReserved\nRTC\nOSF\nSR\nReserved\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x101C\nETH_DMAIER\nReserved\nNISE\nAISE\nERIE\nFBEIE\nReserved\nETIE\nRWTIE\nRPSIE\nRBUIE\nRIE\nTUIE\nROIE\nTJTIE\nTBUIE\nTPSIE\nTIE\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1020\nETH_DMAMFB\nOCR\nReserved\nOFOC\nMFA\nOMFC\nMFC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1024\nETH_\nDMARSWTR\nReserved\nRSWTC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x1048\nETH_\nDMACHTDR\nHTDAP\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x104C\nETH_\nDMACHRDR\nHRDAP\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1050\nETH_\nDMACHTBAR\nHTBAP\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x1054\nETH_\nDMACHRBAR\nHRBAP\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 196. Ethernet register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1243, "page_indices": { "start_index": 2459389, "end_index": 2460794 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1243 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.1 OTG_FS introduction", 1243 ] ], "page_content": "RM0090 Rev 21\n1243/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34 \nUSB on-the-go full-speed (OTG_FS)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n34.1 \nOTG_FS introduction\nPortions Copyright (c) 2004, 2005 Synopsys, Inc. All rights reserved. Used with permission.\nThis section presents the architecture and the programming model of the OTG_FS \ncontroller.\nThe following acronyms are used throughout this section:\nReferences are made to the following documents:\n•\nUSB On-The-Go Supplement, Revision 1.3\n•\nUniversal Serial Bus Revision 2.0 Specification\nThe OTG_FS is a dual-role device (DRD) controller that supports both device and host \nfunctions and is fully compliant with the On-The-Go Supplement to the USB 2.0 \nSpecification. It can also be configured as a host-only or device-only controller, fully \ncompliant with the USB 2.0 Specification. In host mode, the OTG_FS supports full-speed \n(FS, 12 Mbits/s) and low-speed (LS, 1.5 Mbits/s) transfers whereas in device mode, it only \nsupports full-speed (FS, 12 Mbits/s) transfers. The OTG_FS supports both HNP and SRP. \nThe only external device required is a charge pump for VBUS in host mode.\nFS\nFull-speed\nLS\nLow-speed\nMAC\nMedia access controller\nOTG\nOn-the-go\nPFC\nPacket FIFO controller\nPHY\nPhysical layer\nUSB\nUniversal serial bus\nUTMI\nUSB 2.0 transceiver macrocell interface (UTMI)\n" }, { "page_number": 1244, "page_indices": { "start_index": 2460794, "end_index": 2462631 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1244 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.2 OTG_FS main features", 1244 ], [ 3, "34.2.1 General features", 1244 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1244/1757\nRM0090 Rev 21\n34.2 \nOTG_FS main features\nThe main features can be divided into three categories: general, host-mode and device-\nmode features.\n34.2.1 \nGeneral features\nThe OTG_FS interface general features are the following:\n•\nIt is USB-IF certified to the Universal Serial Bus Specification Rev 2.0\n•\nIt includes full support (PHY) for the optional On-The-Go (OTG) protocol detailed in the \nOn-The-Go Supplement Rev 1.3 specification\n–\nIntegrated support for A-B Device Identification (ID line)\n–\nIntegrated support for host Negotiation Protocol (HNP) and Session Request \nProtocol (SRP)\n–\nIt allows host to turn VBUS off to conserve battery power in OTG applications\n–\nIt supports OTG monitoring of VBUS levels with internal comparators\n–\nIt supports dynamic host-peripheral switch of role\n•\nIt is software-configurable to operate as:\n–\nSRP capable USB FS Peripheral (B-device)\n–\nSRP capable USB FS/LS host (A-device)\n–\nUSB On-The-Go Full-Speed Dual Role device\n•\nIt supports FS SOF and LS Keep-alives with\n–\nSOF pulse PAD connectivity (OTG_FS_SOF)\n–\nSOF pulse internal connection to timer2 (TIM2)\n–\nConfigurable framing period\n–\nConfigurable end of frame interrupt\n•\nIt includes power saving features such as system stop during USB Suspend, switch-off \nof clock domains internal to the digital core, PHY and DFIFO power management\n•\nIt features a dedicated RAM of 1.25 Kbytes with advanced FIFO control:\n–\nConfigurable partitioning of RAM space into different FIFOs for flexible and \nefficient use of RAM\n–\nEach FIFO can hold multiple packets\n–\nDynamic memory allocation\n–\nConfigurable FIFO sizes that are not powers of 2 to allow the use of contiguous \nmemory locations\n•\nIt guarantees max USB bandwidth for up to one frame (1ms) without system \nintervention\n" }, { "page_number": 1245, "page_indices": { "start_index": 2462631, "end_index": 2463890 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1245 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.2 OTG_FS main features", 1244 ], [ 3, "34.2.2 Host-mode features", 1245 ], [ 3, "34.2.3 Peripheral-mode features", 1245 ] ], "page_content": "RM0090 Rev 21\n1245/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34.2.2 \nHost-mode features\nThe OTG_FS interface main features and requirements in host-mode are the following:\n•\nExternal charge pump for VBUS voltage generation.\n•\nUp to 8 host channels (pipes): each channel is dynamically reconfigurable to allocate \nany type of USB transfer. \n•\nBuilt-in hardware scheduler holding:\n–\nUp to 8 interrupt plus isochronous transfer requests in the periodic hardware \nqueue\n–\nUp to 8 control plus bulk transfer requests in the non-periodic hardware queue\n•\nManagement of a shared RX FIFO, a periodic TX FIFO and a nonperiodic TX FIFO for \nefficient usage of the USB data RAM.\n34.2.3 \nPeripheral-mode features\nThe OTG_FS interface main features in peripheral-mode are the following:\n•\n1 bidirectional control endpoint0\n•\n3 IN endpoints (EPs) configurable to support Bulk, Interrupt or Isochronous transfers\n•\n3 OUT endpoints configurable to support Bulk, Interrupt or Isochronous transfers\n•\nManagement of a shared Rx FIFO and a Tx-OUT FIFO for efficient usage of the USB \ndata RAM\n•\nManagement of up to 4 dedicated Tx-IN FIFOs (one for each active IN EP) to put less \nload on the application\n•\nSupport for the soft disconnect feature.\n" }, { "page_number": 1246, "page_indices": { "start_index": 2463890, "end_index": 2465140 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1246 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.3 OTG_FS functional description", 1246 ], [ 3, "34.3.1 OTG pins", 1246 ], [ 3, "34.3.2 OTG full-speed core", 1246 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1246/1757\nRM0090 Rev 21\n34.3 \nOTG_FS functional description\nFigure 386. OTG full-speed block diagram\n34.3.1 \nOTG pins\n \n34.3.2 \nOTG full-speed core\nThe USB OTG FS receives the 48 MHz ±0.25% clock from the reset and clock controller \n(RCC), via an external quartz. The USB clock is used for driving the 48 MHz domain at full-\nspeed (12 Mbit/s) and must be enabled prior to configuring the OTG FS core.\nThe CPU reads and writes from/to the OTG FS core registers through the AHB peripheral \nbus. It is informed of USB events through the single USB OTG interrupt line described in \nSection 34.15: OTG_FS interrupts.\nMS19928V4\nUSB2.0\nOTG FS\ncore\nSystem clock domain\nUSB clock \ndomain\nOTG\nFS\nPHY\nOTG_FS_DP\nOTG_FS_DM\nOTG_FS_ID\nOTG_FS_VBUS\nUniversal serial bus\nPower\nand\nclock\ncontroller\nCortex® core\nUTMIFS\nRAM bus\n1.25 Kbyte\nUSB data\nFIFOs\nUSB clock at 48 MHz\nUSB suspend\nOTG_FS_SOF\nTable 197. OTG_FS input/output pins\nSignal name\nSignal type\nDescription\nOTG_FS_DP\nDigital input/output\nUSB OTG D+ line\nOTG_FS_DM\nDigital input/output\nUSB OTG D- line\nOTG_FS_ID\nDigital input\nUSB OTG ID\nOTG_FS_VBUS\nAnalog input\nUSB OTG VBUS\nOTG_FS_SOF\nDigital output\nUSB OTG Start Of Frame (visibility)\n" }, { "page_number": 1247, "page_indices": { "start_index": 2465140, "end_index": 2467861 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1247 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.3 OTG_FS functional description", 1246 ], [ 3, "34.3.3 Full-speed OTG PHY", 1247 ] ], "page_content": "RM0090 Rev 21\n1247/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nThe CPU submits data over the USB by writing 32-bit words to dedicated OTG_FS locations \n(push registers). The data are then automatically stored into Tx-data FIFOs configured \nwithin the USB data RAM. There is one Tx-FIFO push register for each in-endpoint \n(peripheral mode) or out-channel (host mode).\nThe CPU receives the data from the USB by reading 32-bit words from dedicated OTG_FS \naddresses (pop registers). The data are then automatically retrieved from a shared Rx-FIFO \nconfigured within the 1.25 KB USB data RAM. There is one Rx-FIFO pop register for each \nout-endpoint or in-channel.\nThe USB protocol layer is driven by the serial interface engine (SIE) and serialized over the \nUSB by the full-/low-speed transceiver module within the on-chip physical layer (PHY).\n34.3.3 \nFull-speed OTG PHY\nThe embedded full-speed OTG PHY is controlled by the OTG FS core and conveys USB \ncontrol & data signals through the full-speed subset of the UTMI+ Bus (UTMIFS). It provides \nthe physical support to USB connectivity.\nThe full-speed OTG PHY includes the following components:\n•\nFS/LS transceiver module used by both host and device. It directly drives transmission \nand reception on the single-ended USB lines.\n•\nintegrated ID pull-up resistor used to sample the ID line for A/B device identification.\n•\nDP/DM integrated pull-up and pull-down resistors controlled by the OTG_FS core \ndepending on the current role of the device. As a peripheral, it enables the DP pull-up \nresistor to signal full-speed peripheral connections as soon as VBUS is sensed to be at \na valid level (B-session valid). In host mode, pull-down resistors are enabled on both \nDP/DM. Pull-up and pull-down resistors are dynamically switched when the device’s \nrole is changed via the host negotiation protocol (HNP).\n•\nPull-up/pull-down resistor ECN circuit. The DP pull-up consists of 2 resistors controlled \nseparately from the OTG_FS as per the resistor Engineering Change Notice applied to \nUSB Rev2.0. The dynamic trimming of the DP pull-up strength allows for better noise \nrejection and Tx/Rx signal quality.\n•\nVBUS sensing comparators with hysteresis used to detect VBUS Valid, A-B Session \nValid and session-end voltage thresholds. They are used to drive the session request \nprotocol (SRP), detect valid startup and end-of-session conditions, and constantly \nmonitor the VBUS supply during USB operations.\n•\nVBUS pulsing method circuit used to charge/discharge VBUS through resistors during \nthe SRP (weak drive).\nCaution:\nTo guarantee a correct operation for the USB OTG FS peripheral, the AHB frequency should \nbe higher than 14.2 MHz.\n" }, { "page_number": 1248, "page_indices": { "start_index": 2467861, "end_index": 2470212 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1248 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.4 OTG dual role device (DRD)", 1248 ], [ 3, "34.4.1 ID line detection", 1248 ], [ 3, "34.4.2 HNP dual role device", 1248 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1248/1757\nRM0090 Rev 21\n34.4 \nOTG dual role device (DRD)\nFigure 387. OTG A-B device connection\n1.\nExternal voltage regulator only needed when building a VBUS powered device\n2.\nSTMPS2141STR needed only if the application has to support a VBUS powered device. A basic power \nswitch can be used if 5 V are available on the application board.\n34.4.1 \nID line detection\nThe host or peripheral (the default) role is assumed depending on the ID input pin \n(OTG_FS_ID). The ID line status is determined on plugging in the USB, depending on which \nside of the USB cable is connected to the micro-AB receptacle.\n•\nIf the B-side of the USB cable is connected with a floating ID wire, the integrated pull-\nup resistor detects a high ID level and the default Peripheral role is confirmed. In this \nconfiguration the OTG_FS complies with the standard FSM described by section 6.8.2: \nOn-The-Go B-device of the On-The-Go Specification Rev1.3 supplement to the \nUSB2.0.\n•\nIf the A-side of the USB cable is connected with a grounded ID, the OTG_FS issues an \nID line status change interrupt (CIDSCHG bit in OTG_FS_GINTSTS) for host software \ninitialization, and automatically switches to the host role. In this configuration the \nOTG_FS complies with the standard FSM described by section 6.8.1: On-The-Go A-\ndevice of the On-The-Go Specification Rev1.3 supplement to the USB2.0.\n34.4.2 \nHNP dual role device\nThe HNP capable bit in the Global USB configuration register (HNPCAP bit in OTG_FS_ \nGUSBCFG) enables the OTG_FS core to dynamically change its role from A-host to A-\nperipheral and vice-versa, or from B-Peripheral to B-host and vice-versa according to the \nhost negotiation protocol (HNP). The current device status can be read by the combined \nvalues of the Connector ID Status bit in the Global OTG control and status register (CIDSTS \nbit in OTG_FS_GOTGCTL) and the current mode of operation bit in the global interrupt and \nstatus register (CMOD bit in OTG_FS_GINTSTS).\nThe HNP program model is described in detail in Section 34.17: OTG_FS programming \nmodel.\nSTM32 MCU\nSTMPS2141STR\nCurrent-limited \npower distribution \nswitch (2)\nVDD\nVBUS\nDP\nVSS\nPA9\nPA12\nPA11\nUSB micro-AB connector\nDM\nGPIO+IRQ\nGPIO\nEN\nOvercurrent\n5 V Pwr\n5 V to VDD\nvoltage regulator\nVDD\nID\nPA10\nOSC_IN\nOSC_OUT\nMS19904V4\n" }, { "page_number": 1249, "page_indices": { "start_index": 2470212, "end_index": 2472109 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1249 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.4 OTG dual role device (DRD)", 1248 ], [ 3, "34.4.3 SRP dual role device", 1249 ], [ 2, "34.5 USB peripheral", 1249 ] ], "page_content": "RM0090 Rev 21\n1249/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34.4.3 \nSRP dual role device\nThe SRP capable bit in the global USB configuration register (SRPCAP bit in \nOTG_FS_GUSBCFG) enables the OTG_FS core to switch off the generation of VBUS for \nthe A-device to save power. Note that the A-device is always in charge of driving VBUS \nregardless of the host or peripheral role of the OTG_FS.\nthe SRP A/B-device program model is described in detail in Section 34.17: OTG_FS \nprogramming model.\n34.5 \nUSB peripheral\nThis section gives the functional description of the OTG_FS in the USB peripheral mode. \nThe OTG_FS works as an USB peripheral in the following circumstances:\n•\nOTG B-Peripheral\n–\nOTG B-device default state if B-side of USB cable is plugged in\n•\nOTG A-Peripheral\n–\nOTG A-device state after the HNP switches the OTG_FS to its peripheral role\n•\nB-device\n–\nIf the ID line is present, functional and connected to the B-side of the USB cable, \nand the HNP-capable bit in the Global USB Configuration register (HNPCAP bit in \nOTG_FS_GUSBCFG) is cleared (see On-The-Go Rev1.3 par. 6.8.3).\n•\nPeripheral only (see Figure 388: USB peripheral-only connection)\n–\nThe force device mode bit in the Global USB configuration register (FDMOD in \nOTG_FS_GUSBCFG) is set to 1, forcing the OTG_FS core to work as a USB \nperipheral-only (see On-The-Go Rev1.3 par. 6.8.3). In this case, the ID line is \nignored even if present on the USB connector.\nNote:\nTo build a bus-powered device implementation in case of the B-device or peripheral-only \nconfiguration, an external regulator has to be added that generates the VDD chip-supply \nfrom VBUS.\nThe VBUS pin can be freed by disabling the VBUS sensing option. This is done by setting the \nNOVBUSSENS bit in the OTG_FS_GCCFG register. In this case the VBUS is considered \ninternally to be always at VBUS valid level (5 V). \n" }, { "page_number": 1250, "page_indices": { "start_index": 2472109, "end_index": 2474043 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1250 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.5 USB peripheral", 1249 ], [ 3, "34.5.1 SRP-capable peripheral", 1250 ], [ 3, "34.5.2 Peripheral states", 1250 ], [ 4, "Powered state", 1250 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1250/1757\nRM0090 Rev 21\nFigure 388. USB peripheral-only connection\n1.\nUse a regulator to build a bus-powered device.\n34.5.1 \nSRP-capable peripheral\nThe SRP capable bit in the Global USB configuration register (SRPCAP bit in \nOTG_FS_GUSBCFG) enables the OTG_FS to support the session request protocol (SRP). \nIn this way, it allows the remote A-device to save power by switching off VBUS while the USB \nsession is suspended.\nThe SRP peripheral mode program model is described in detail in the B-device session \nrequest protocol section.\n34.5.2 \nPeripheral states\nPowered state\nThe VBUS input detects the B-Session valid voltage by which the USB peripheral is allowed \nto enter the powered state (see USB2.0 par9.1). The OTG_FS then automatically connects \nthe DP pull-up resistor to signal full-speed device connection to the host and generates the \nsession request interrupt (SRQINT bit in OTG_FS_GINTSTS) to notify the powered state.\nThe VBUS input also ensures that valid VBUS levels are supplied by the host during USB \noperations. If a drop in VBUS below B-session valid happens to be detected (for instance \nbecause of a power disturbance or if the host port has been switched off), the OTG_FS \nautomatically disconnects and the session end detected (SEDET bit in \nOTG_FS_GOTGINT) interrupt is generated to notify that the OTG_FS has exited the \npowered state.\nIn the powered state, the OTG_FS expects to receive some reset signaling from the host. \nNo other USB operation is possible. When a reset signaling is received the reset detected \ninterrupt (USBRST in OTG_FS_GINTSTS) is generated. When the reset signaling is \ncomplete, the enumeration done interrupt (ENUMDNE bit in OTG_FS_GINTSTS) is \ngenerated and the OTG_FS enters the Default state.\nSTM32 MCU\n5V to VDD\nVolatge regulator\nVDD\nVBUS\nDP\nVSS\nPA9\nPA12\nPA11\nUSB Std-B connector\nDM\nOSC_IN\nOSC_OUT\nMS19905V4\n" }, { "page_number": 1251, "page_indices": { "start_index": 2474043, "end_index": 2476910 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1251 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.5 USB peripheral", 1249 ], [ 3, "34.5.2 Peripheral states", 1250 ], [ 4, "Soft disconnect", 1251 ], [ 4, "Default state", 1251 ], [ 4, "Suspended state", 1251 ], [ 3, "34.5.3 Peripheral endpoints", 1251 ] ], "page_content": "RM0090 Rev 21\n1251/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nSoft disconnect\nThe powered state can be exited by software with the soft disconnect feature. The DP pull-\nup resistor is removed by setting the soft disconnect bit in the device control register (SDIS \nbit in OTG_FS_DCTL), causing a device disconnect detection interrupt on the host side \neven though the USB cable was not really removed from the host port.\nDefault state\nIn the Default state the OTG_FS expects to receive a SET_ADDRESS command from the \nhost. No other USB operation is possible. When a valid SET_ADDRESS command is \ndecoded on the USB, the application writes the corresponding number into the device \naddress field in the device configuration register (DAD bit in OTG_FS_DCFG). The \nOTG_FS then enters the address state and is ready to answer host transactions at the \nconfigured USB address.\nSuspended state\nThe OTG_FS peripheral constantly monitors the USB activity. After counting 3 ms of USB \nidleness, the early suspend interrupt (ESUSP bit in OTG_FS_GINTSTS) is issued, and \nconfirmed 3 ms later, if appropriate, by the suspend interrupt (USBSUSP bit in \nOTG_FS_GINTSTS). The device suspend bit is then automatically set in the device status \nregister (SUSPSTS bit in OTG_FS_DSTS) and the OTG_FS enters the suspended state.\nThe suspended state may optionally be exited by the device itself. In this case the \napplication sets the remote wake-up signaling bit in the device control register (RWUSIG bit \nin OTG_FS_DCTL) and clears it after 1 to 15 ms.\nWhen a resume signaling is detected from the host, the resume interrupt (WKUPINT bit in \nOTG_FS_GINTSTS) is generated and the device suspend bit is automatically cleared.\n34.5.3 \nPeripheral endpoints\nThe OTG_FS core instantiates the following USB endpoints:\n•\nControl endpoint 0:\n–\nBidirectional and handles control messages only\n–\nSeparate set of registers to handle in and out transactions\n–\nProper control (OTG_FS_DIEPCTL0/OTG_FS_DOEPCTL0), transfer \nconfiguration (OTG_FS_DIEPTSIZ0/OTG_FS_DIEPTSIZ0), and status-interrupt \n(OTG_FS_DIEPINTx/)OTG_FS_DOEPINT0) registers. The available set of bits \ninside the control and transfer size registers slightly differs from that of other \nendpoints\n•\n3 IN endpoints\n–\nEach of them can be configured to support the isochronous, bulk or interrupt \ntransfer type\n–\nEach of them has proper control (OTG_FS_DIEPCTLx), transfer configuration \n(OTG_FS_DIEPTSIZx), and status-interrupt (OTG_FS_DIEPINTx) registers\n–\nThe Device IN endpoints common interrupt mask register (OTG_FS_DIEPMSK) is \navailable to enable/disable a single kind of endpoint interrupt source on all of the \nIN endpoints (EP0 included)\n–\nSupport for incomplete isochronous IN transfer interrupt (IISOIXFR bit in \nOTG_FS_GINTSTS), asserted when there is at least one isochronous IN endpoint \n" }, { "page_number": 1252, "page_indices": { "start_index": 2476910, "end_index": 2479312 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1252 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.5 USB peripheral", 1249 ], [ 3, "34.5.3 Peripheral endpoints", 1251 ], [ 4, "Endpoint control", 1252 ], [ 4, "Endpoint transfer", 1252 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1252/1757\nRM0090 Rev 21\non which the transfer is not completed in the current frame. This interrupt is \nasserted along with the end of periodic frame interrupt \n(OTG_FS_GINTSTS/EOPF).\n•\n3 OUT endpoints\n–\nEach of them can be configured to support the isochronous, bulk or interrupt \ntransfer type\n–\nEach of them has a proper control (OTG_FS_DOEPCTLx), transfer configuration \n(OTG_FS_DOEPTSIZx) and status-interrupt (OTG_FS_DOEPINTx) register\n–\nDevice Out endpoints common interrupt mask register (OTG_FS_DOEPMSK) is \navailable to enable/disable a single kind of endpoint interrupt source on all of the \nOUT endpoints (EP0 included)\n–\nSupport for incomplete isochronous OUT transfer interrupt (INCOMPISOOUT bit \nin OTG_FS_GINTSTS), asserted when there is at least one isochronous OUT \nendpoint on which the transfer is not completed in the current frame. This interrupt \nis asserted along with the end of periodic frame interrupt \n(OTG_FS_GINTSTS/EOPF).\nEndpoint control\n•\nThe following endpoint controls are available to the application through the device \nendpoint-x IN/OUT control register (DIEPCTLx/DOEPCTLx):\n–\nEndpoint enable/disable\n–\nEndpoint activate in current configuration\n–\nProgram USB transfer type (isochronous, bulk, interrupt)\n–\nProgram supported packet size\n–\nProgram Tx-FIFO number associated with the IN endpoint\n–\nProgram the expected or transmitted data0/data1 PID (bulk/interrupt only)\n–\nProgram the even/odd frame during which the transaction is received or \ntransmitted (isochronous only)\n–\nOptionally program the NAK bit to always negative-acknowledge the host \nregardless of the FIFO status\n–\nOptionally program the STALL bit to always stall host tokens to that endpoint\n–\nOptionally program the SNOOP mode for OUT endpoint not to check the CRC \nfield of received data\nEndpoint transfer\nThe device endpoint-x transfer size registers (DIEPTSIZx/DOEPTSIZx) allow the application \nto program the transfer size parameters and read the transfer status. Programming must be \ndone before setting the endpoint enable bit in the endpoint control register. Once the \nendpoint is enabled, these fields are read-only as the OTG FS core updates them with the \ncurrent transfer status.\nThe following transfer parameters can be programmed:\n•\nTransfer size in bytes\n•\nNumber of packets that constitute the overall transfer size\n" }, { "page_number": 1253, "page_indices": { "start_index": 2479312, "end_index": 2482158 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1253 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.5 USB peripheral", 1249 ], [ 3, "34.5.3 Peripheral endpoints", 1251 ], [ 4, "Endpoint status/interrupt", 1253 ], [ 2, "34.6 USB host", 1253 ] ], "page_content": "RM0090 Rev 21\n1253/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nEndpoint status/interrupt\nThe device endpoint-x interrupt registers (DIEPINTx/DOPEPINTx) indicate the status of an \nendpoint with respect to USB- and AHB-related events. The application must read these \nregisters when the OUT endpoint interrupt bit or the IN endpoint interrupt bit in the core \ninterrupt register (OEPINT bit in OTG_FS_GINTSTS or IEPINT bit in OTG_FS_GINTSTS, \nrespectively) is set. Before the application can read these registers, it must first read the \ndevice all endpoints interrupt (OTG_FS_DAINT) register to get the exact endpoint number \nfor the device endpoint-x interrupt register. The application must clear the appropriate bit in \nthis register to clear the corresponding bits in the DAINT and GINTSTS registers\nThe peripheral core provides the following status checks and interrupt generation:\n•\nTransfer completed interrupt, indicating that data transfer was completed on both the \napplication (AHB) and USB sides\n•\nSetup stage has been done (control-out only)\n•\nAssociated transmit FIFO is half or completely empty (in endpoints)\n•\nNAK acknowledge has been transmitted to the host (isochronous-in only)\n•\nIN token received when Tx-FIFO was empty (bulk-in/interrupt-in only)\n•\nOut token received when endpoint was not yet enabled\n•\nBabble error condition has been detected\n•\nEndpoint disable by application is effective\n•\nEndpoint NAK by application is effective (isochronous-in only)\n•\nMore than 3 back-to-back setup packets were received (control-out only)\n•\nTimeout condition detected (control-in only)\n•\nIsochronous out packet has been dropped, without generating an interrupt\n34.6 \nUSB host\nThis section gives the functional description of the OTG_FS in the USB host mode. The \nOTG_FS works as a USB host in the following circumstances:\n•\nOTG A-host\n–\nOTG A-device default state when the A-side of the USB cable is plugged in\n•\nOTG B-host\n–\nOTG B-device after HNP switching to the host role\n•\nA-device\n–\nIf the ID line is present, functional and connected to the A-side of the USB cable, \nand the HNP-capable bit is cleared in the Global USB Configuration register \n(HNPCAP bit in OTG_FS_GUSBCFG). Integrated pull-down resistors are \nautomatically set on the DP/DM lines.\n•\nHost only (see Figure 389: USB host-only connection).\n–\nThe force host mode bit in the global USB configuration register (FHMOD bit in \nOTG_FS_GUSBCFG) forces the OTG_FS core to work as a USB host-only. In this \ncase, the ID line is ignored even if present on the USB connector. Integrated pull-\ndown resistors are automatically set on the DP/DM lines.\nNote:\nOn-chip 5 V VBUS generation is not supported. For this reason, a charge pump or, if 5 V are \navailable on the application board, a basic power switch must be added externally to drive \n" }, { "page_number": 1254, "page_indices": { "start_index": 2482158, "end_index": 2484178 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1254 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.6 USB host", 1253 ], [ 3, "34.6.1 SRP-capable host", 1254 ], [ 3, "34.6.2 USB host states", 1254 ], [ 4, "Host port power", 1254 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1254/1757\nRM0090 Rev 21\nthe 5 V VBUS line. The external charge pump can be driven by any GPIO output. This is \nrequired for the OTG A-host, A-device and host-only configurations.\nThe VBUS input ensures that valid VBUS levels are supplied by the charge pump during USB \noperations while the charge pump overcurrent output can be input to any GPIO pin \nconfigured to generate port interrupts. The overcurrent ISR must promptly disable the VBUS \ngeneration.\nThe VBUS pin can be freed by disabling the VBUS sensing option. This is done by setting the \nNOVBUSSENS bit in the OTG_FS_GCCFG register. In this case the VBUS is considered \ninternally to be always at VBUS valid level (5 V). \nFigure 389. USB host-only connection\n1.\nSTMPS2141STR needed only if the application has to support a VBUS powered device. A basic power \nswitch can be used if 5 V are available on the application board.\n2.\nVDD range is between 2 V and 3.6 V.\n34.6.1 \nSRP-capable host\nSRP support is available through the SRP capable bit in the global USB configuration \nregister (SRPCAP bit in OTG_FS_GUSBCFG). With the SRP feature enabled, the host can \nsave power by switching off the VBUS power while the USB session is suspended.\nThe SRP host mode program model is described in detail in the A-device session request \nprotocol section.\n34.6.2 \nUSB host states\nHost port power\nOn-chip 5 V VBUS generation is not supported. For this reason, a charge pump or, if 5 V are \navailable on the application board, a basic power switch, must be added externally to drive \nthe 5 V VBUS line. The external charge pump can be driven by any GPIO output. When the \napplication decides to power on VBUS using the chosen GPIO, it must also set the port \npower bit in the host port control and status register (PPWR bit in OTG_FS_HPRT).\nMSv36915V2\nSTMPS2141STR\nCurrent-limited\n power distribution \nswitch(2)\nOSC_IN\nOSC_OUT\nGPIO\nGPIO + IRQ\nEN\nOvercurrent\n5 V\n5 V Pwr\nVBUS\nDM\nDP\nVSS\nUSB Std-A connector\nVDD\n" }, { "page_number": 1255, "page_indices": { "start_index": 2484178, "end_index": 2487365 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1255 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.6 USB host", 1253 ], [ 3, "34.6.2 USB host states", 1254 ], [ 4, "VBUS valid", 1255 ], [ 4, "Host detection of a peripheral connection", 1255 ], [ 4, "Host detection of peripheral a disconnection", 1255 ], [ 4, "Host enumeration", 1255 ] ], "page_content": "RM0090 Rev 21\n1255/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nVBUS valid\nWhen HNP or SRP is enabled the VBUS sensing pin (PA9) pin should be connected to \nVBUS. The VBUS input ensures that valid VBUS levels are supplied by the charge pump \nduring USB operations. Any unforeseen VBUS voltage drop below the VBUS valid threshold \n(4.25 V) leads to an OTG interrupt triggered by the session end detected bit (SEDET bit in \nOTG_FS_GOTGINT). The application is then required to remove the VBUS power and clear \nthe port power bit. \nWhen HNP and SRP are both disabled, the VBUS sensing pin (PA9) should not be \nconnected to VBUS. This pin can be can be used as GPIO.\nThe charge pump overcurrent flag can also be used to prevent electrical damage. Connect \nthe overcurrent flag output from the charge pump to any GPIO input and configure it to \ngenerate a port interrupt on the active level. The overcurrent ISR must promptly disable the \nVBUS generation and clear the port power bit.\nHost detection of a peripheral connection\nIf SRP or HNP are enabled, even if USB peripherals or B-devices can be attached at any \ntime, the OTG_FS does not detect any bus connection until VBUS is no longer sensed at a \nvalid level (5 V). When VBUS is at a valid level and a remote B-device is attached, the \nOTG_FS core issues a host port interrupt triggered by the device connected bit in the host \nport control and status register (PCDET bit in OTG_FS_HPRT).\nWhen HNP and SRP are both disabled, USB peripherals or B-device are detected as soon \nas they are connected. The OTG_FS core issues a host port interrupt triggered by the \ndevice connected bit in the host port control and status (PCDET bit in OTG_FS_HPRT).\nHost detection of peripheral a disconnection\nThe peripheral disconnection event triggers the disconnect detected interrupt (DISCINT bit \nin OTG_FS_GINTSTS).\nHost enumeration\nAfter detecting a peripheral connection the host must start the enumeration process by \nsending USB reset and configuration commands to the new peripheral.\nBefore starting to drive a USB reset, the application waits for the OTG interrupt triggered by \nthe debounce done bit (DBCDNE bit in OTG_FS_GOTGINT), which indicates that the bus is \nstable again after the electrical debounce caused by the attachment of a pull-up resistor on \nDP (FS) or DM (LS).\nThe application drives a USB reset signaling (single-ended zero) over the USB by keeping \nthe port reset bit set in the host port control and status register (PRST bit in \nOTG_FS_HPRT) for a minimum of 10 ms and a maximum of 20 ms. The application takes \ncare of the timing count and then of clearing the port reset bit.\nOnce the USB reset sequence has completed, the host port interrupt is triggered by the port \nenable/disable change bit (PENCHNG bit in OTG_FS_HPRT). This informs the application \nthat the speed of the enumerated peripheral can be read from the port speed field in the \nhost port control and status register (PSPD bit in OTG_FS_HPRT) and that the host is \nstarting to drive SOFs (FS) or Keep alives (LS). The host is now ready to complete the \nperipheral enumeration by sending peripheral configuration commands.\n" }, { "page_number": 1256, "page_indices": { "start_index": 2487365, "end_index": 2490022 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1256 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.6 USB host", 1253 ], [ 3, "34.6.2 USB host states", 1254 ], [ 4, "Host suspend", 1256 ], [ 3, "34.6.3 Host channels", 1256 ], [ 4, "Host channel control", 1256 ], [ 4, "Host channel transfer", 1256 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1256/1757\nRM0090 Rev 21\nHost suspend\nThe application decides to suspend the USB activity by setting the port suspend bit in the \nhost port control and status register (PSUSP bit in OTG_FS_HPRT). The OTG_FS core \nstops sending SOFs and enters the suspended state.\nThe suspended state can be optionally exited on the remote device’s initiative (remote \nwake-up). In this case the remote wake-up interrupt (WKUPINT bit in OTG_FS_GINTSTS) \nis generated upon detection of a remote wake-up signaling, the port resume bit in the host \nport control and status register (PRES bit in OTG_FS_HPRT) self-sets, and resume \nsignaling is automatically driven over the USB. The application must time the resume \nwindow and then clear the port resume bit to exit the suspended state and restart the SOF.\nIf the suspended state is exited on the host initiative, the application must set the port \nresume bit to start resume signaling on the host port, time the resume window and finally \nclear the port resume bit.\n34.6.3 \nHost channels\nThe OTG_FS core instantiates 8 host channels. Each host channel supports an USB host \ntransfer (USB pipe). The host is not able to support more than 8 transfer requests at the \nsame time. If more than 8 transfer requests are pending from the application, the host \ncontroller driver (HCD) must re-allocate channels when they become available from \nprevious duty, that is, after receiving the transfer completed and channel halted interrupts.\nEach host channel can be configured to support in/out and any type of periodic/nonperiodic \ntransaction. Each host channel makes us of proper control (HCCHARx), transfer \nconfiguration (HCTSIZx) and status/interrupt (HCINTx) registers with associated mask \n(HCINTMSKx) registers.\nHost channel control\n•\nThe following host channel controls are available to the application through the host \nchannel-x characteristics register (HCCHARx):\n–\nChannel enable/disable\n–\nProgram the FS/LS speed of target USB peripheral\n–\nProgram the address of target USB peripheral\n–\nProgram the endpoint number of target USB peripheral\n–\nProgram the transfer IN/OUT direction\n–\nProgram the USB transfer type (control, bulk, interrupt, isochronous)\n–\nProgram the maximum packet size (MPS)\n–\nProgram the periodic transfer to be executed during odd/even frames\nHost channel transfer\nThe host channel transfer size registers (HCTSIZx) allow the application to program the \ntransfer size parameters, and read the transfer status. Programming must be done before \nsetting the channel enable bit in the host channel characteristics register. Once the endpoint \n" }, { "page_number": 1257, "page_indices": { "start_index": 2490022, "end_index": 2493034 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1257 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.6 USB host", 1253 ], [ 3, "34.6.3 Host channels", 1256 ], [ 4, "Host channel status/interrupt", 1257 ], [ 3, "34.6.4 Host scheduler", 1257 ] ], "page_content": "RM0090 Rev 21\n1257/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nis enabled the packet count field is read-only as the OTG FS core updates it according to \nthe current transfer status.\n•\nThe following transfer parameters can be programmed:\n–\ntransfer size in bytes\n–\nnumber of packets making up the overall transfer size\n–\ninitial data PID\nHost channel status/interrupt\nThe host channel-x interrupt register (HCINTx) indicates the status of an endpoint with \nrespect to USB- and AHB-related events. The application must read these register when the \nhost channels interrupt bit in the core interrupt register (HCINT bit in OTG_FS_GINTSTS) is \nset. Before the application can read these registers, it must first read the host all channels \ninterrupt (HCAINT) register to get the exact channel number for the host channel-x interrupt \nregister. The application must clear the appropriate bit in this register to clear the \ncorresponding bits in the HAINT and GINTSTS registers. The mask bits for each interrupt \nsource of each channel are also available in the OTG_FS_HCINTMSK-x register.\n•\nThe host core provides the following status checks and interrupt generation:\n–\nTransfer completed interrupt, indicating that the data transfer is complete on both \nthe application (AHB) and USB sides\n–\nChannel has stopped due to transfer completed, USB transaction error or disable \ncommand from the application\n–\nAssociated transmit FIFO is half or completely empty (IN endpoints)\n–\nACK response received\n–\nNAK response received\n–\nSTALL response received\n–\nUSB transaction error due to CRC failure, timeout, bit stuff error, false EOP\n–\nBabble error\n–\nfraMe overrun\n–\ndAta toggle error\n34.6.4 \nHost scheduler\nThe host core features a built-in hardware scheduler which is able to autonomously re-order \nand manage the USB transaction requests posted by the application. At the beginning of \neach frame the host executes the periodic (isochronous and interrupt) transactions first, \nfollowed by the nonperiodic (control and bulk) transactions to achieve the higher level of \npriority granted to the isochronous and interrupt transfer types by the USB specification. \nThe host processes the USB transactions through request queues (one for periodic and one \nfor nonperiodic). Each request queue can hold up to 8 entries. Each entry represents a \npending transaction request from the application, and holds the IN or OUT channel number \nalong with other information to perform a transaction on the USB. The order in which the \nrequests are written to the queue determines the sequence of the transactions on the USB \ninterface.\nAt the beginning of each frame, the host processes the periodic request queue first, followed \nby the nonperiodic request queue. The host issues an incomplete periodic transfer interrupt \n(IPXFR bit in OTG_FS_GINTSTS) if an isochronous or interrupt transaction scheduled for \nthe current frame is still pending at the end of the current frame. The OTG HS core is fully \n" }, { "page_number": 1258, "page_indices": { "start_index": 2493034, "end_index": 2495192 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1258 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.7 SOF trigger", 1258 ], [ 3, "34.7.1 Host SOFs", 1258 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1258/1757\nRM0090 Rev 21\nresponsible for the management of the periodic and nonperiodic request queues.The \nperiodic transmit FIFO and queue status register (HPTXSTS) and nonperiodic transmit \nFIFO and queue status register (HNPTXSTS) are read-only registers which can be used by \nthe application to read the status of each request queue. They contain: \n•\nThe number of free entries currently available in the periodic (nonperiodic) request \nqueue (8 max) \n•\nFree space currently available in the periodic (nonperiodic) Tx-FIFO (out-transactions) \n•\nIN/OUT token, host channel number and other status information.\nAs request queues can hold a maximum of 8 entries each, the application can push to \nschedule host transactions in advance with respect to the moment they physically reach the \nSB for a maximum of 8 pending periodic transactions plus 8 pending nonperiodic \ntransactions.\nTo post a transaction request to the host scheduler (queue) the application must check that \nthere is at least 1 entry available in the periodic (nonperiodic) request queue by reading the \nPTXQSAV bits in the OTG_FS_HNPTXSTS register or NPTQXSAV bits in the \nOTG_FS_HNPTXSTS register. \n34.7 \nSOF trigger\nFigure 390. SOF connectivity\nThe OTG FS core provides means to monitor, track and configure SOF framing in the host \nand peripheral, as well as an SOF pulse output connectivity feature.\nSuch utilities are especially useful for adaptive audio clock generation techniques, where \nthe audio peripheral needs to synchronize to the isochronous stream provided by the PC, or \nthe host needs to trim its framing rate according to the requirements of the audio peripheral.\n34.7.1 \nHost SOFs\nIn host mode the number of PHY clocks occurring between the generation of two \nconsecutive SOF (FS) or Keep-alive (LS) tokens is programmable in the host frame interval \nregister (HFIR), thus providing application control over the SOF framing period. An interrupt \nSTM32 MCU\nVBUS\nD+\nVSS\nPA8\nPA12\nPA11\nUSB mic ro-AB connector\nD-\nID\nTIM2\nITR1\nSOF \npulse\nSOFgen\nPA9\nPA10\nSOF pulse output, to \nexternal audio control\nMS19907V3\n" }, { "page_number": 1259, "page_indices": { "start_index": 2495192, "end_index": 2498034 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1259 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.7 SOF trigger", 1258 ], [ 3, "34.7.2 Peripheral SOFs", 1259 ], [ 2, "34.8 OTG low-power modes", 1259 ] ], "page_content": "RM0090 Rev 21\n1259/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nis generated at any start of frame (SOF bit in OTH_FS_GINTSTS). The current frame \nnumber and the time remaining until the next SOF are tracked in the host frame number \nregister (HFNUM).\nAn SOF pulse signal, generated at any SOF starting token and with a width of 20 HCLK \ncycles, can be made available externally on the OTG_FS_SOF pin using the SOFOUTEN \nbit in the global control and configuration register. The SOF pulse is also internally \nconnected to the input trigger of timer 2 (TIM2), so that the input capture feature, the output \ncompare feature and the timer can be triggered by the SOF pulse. The TIM2 connection is \nenabled through the ITR1_RMP bits of TIM2_OR register.\n34.7.2 \nPeripheral SOFs\nIn device mode, the start of frame interrupt is generated each time an SOF token is received \non the USB (SOF bit in OTH_FS_GINTSTS). The corresponding frame number can be read \nfrom the device status register (FNSOF bit in OTG_FS_DSTS). An SOF pulse signal with a \nwidth of 20 HCLK cycles is also generated and can be made available externally on the \nOTG_FS_SOF pin by using the SOF output enable bit in the global control and configuration \nregister (SOFOUTEN bit in OTG_FS_GCCFG). The SOF pulse signal is also internally \nconnected to the TIM2 input trigger, so that the input capture feature, the output compare \nfeature and the timer can be triggered by the SOF pulse. The TIM2 connection is enabled \nthrough the ITR1_RMP bits of the TIM2 option register (TIM2_OR).\nThe end of periodic frame interrupt (GINTSTS/EOPF) is used to notify the application when \n80%, 85%, 90% or 95% of the time frame interval elapsed depending on the periodic frame \ninterval field in the device configuration register (PFIVL bit in OTG_FS_DCFG). This feature \ncan be used to determine if all of the isochronous traffic for that frame is complete.\n34.8 \nOTG low-power modes\nTable 198 below defines the STM32 low power modes and their compatibility with the OTG.\n \nTable 198. Compatibility of STM32 low power modes with the OTG\nMode\nDescription\nUSB compatibility\nRun\nMCU fully active\nRequired when USB not in \nsuspend state.\nSleep\nUSB suspend exit causes the device to exit Sleep mode. \nPeripheral registers content is kept.\nAvailable while USB is in \nsuspend state. \nStop\nUSB suspend exit causes the device to exit Stop mode. \nPeripheral registers content is kept(1).\n1.\nWithin Stop mode there are different possible settings. Some restrictions may also exist, please refer to \nSection 5: Power controller (PWR) to understand which (if any) restrictions apply when using OTG.\nAvailable while USB is in \nsuspend state. \nStandby\nPowered-down. The peripheral must be reinitialized after \nexiting Standby mode.\nNot compatible with USB \napplications.\n" }, { "page_number": 1260, "page_indices": { "start_index": 2498034, "end_index": 2500837 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1260 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.9 Dynamic update of the OTG_FS_HFIR register", 1260 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1260/1757\nRM0090 Rev 21\nThe power consumption of the OTG PHY is controlled by three bits in the general core \nconfiguration register:\n•\nPHY power down (GCCFG/PWRDWN)\nIt switches on/off the full-speed transceiver module of the PHY. It must be preliminarily \nset to allow any USB operation.\n•\nA-VBUS sensing enable (GCCFG/VBUSASEN)\nIt switches on/off the VBUS comparators associated with A-device operations. It must \nbe set when in A-device (USB host) mode and during HNP.\n•\nB-VBUS sensing enable (GCCFG/VBUSASEN)\nIt switches on/off the VBUS comparators associated with B-device operations. It must \nbe set when in B-device (USB peripheral) mode and during HNP.\nPower reduction techniques are available while in the USB suspended state, when the USB \nsession is not yet valid or the device is disconnected.\n•\nStop PHY clock (STPPCLK bit in OTG_FS_PCGCCTL)\nWhen setting the stop PHY clock bit in the clock gating control register, most of the \n48 MHz clock domain internal to the OTG full-speed core is switched off by clock \ngating. The dynamic power consumption due to the USB clock switching activity is cut \neven if the 48 MHz clock input is kept running by the application\nMost of the transceiver is also disabled, and only the part in charge of detecting the \nasynchronous resume or remote wake-up event is kept alive.\n•\nGate HCLK (GATEHCLK bit in OTG_FS_PCGCCTL)\nWhen setting the Gate HCLK bit in the clock gating control register, most of the system \nclock domain internal to the OTG_FS core is switched off by clock gating. Only the \nregister read and write interface is kept alive. The dynamic power consumption due to \nthe USB clock switching activity is cut even if the system clock is kept running by the \napplication for other purposes.\n•\nUSB system stop\nWhen the OTG_FS is in the USB suspended state, the application may decide to \ndrastically reduce the overall power consumption by a complete shut down of all the \nclock sources in the system. USB System Stop is activated by first setting the Stop \nPHY clock bit and then configuring the system deep sleep mode in the power control \nsystem module (PWR).\nThe OTG_FS core automatically reactivates both system and USB clocks by \nasynchronous detection of remote wake-up (as an host) or resume (as a device) \nsignaling on the USB.\nTo save dynamic power, the USB data FIFO is clocked only when accessed by the OTG_FS \ncore.\n34.9 \nDynamic update of the OTG_FS_HFIR register\nThe USB core embeds a dynamic trimming capability of SOF framing period in host mode \nallowing to synchronize an external device with the SOF frames. \nWhen the OTG_FS_HFIR register is changed within a current SOF frame, the SOF period \ncorrection is applied in the next frame as described in Figure 391.\n" }, { "page_number": 1261, "page_indices": { "start_index": 2500837, "end_index": 2501963 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1261 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.10 USB data FIFOs", 1261 ] ], "page_content": "RM0090 Rev 21\n1261/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nFigure 391. Updating OTG_FS_HFIR dynamically\n34.10 \nUSB data FIFOs\nThe USB system features 1.25 Kbyte of dedicated RAM with a sophisticated FIFO control \nmechanism. The packet FIFO controller module in the OTG_FS core organizes RAM space \ninto Tx-FIFOs into which the application pushes the data to be temporarily stored before the \nUSB transmission, and into a single Rx FIFO where the data received from the USB are \ntemporarily stored before retrieval (popped) by the application. The number of instructed \nFIFOs and how these are organized inside the RAM depends on the device’s role. In \nperipheral mode an additional Tx-FIFO is instructed for each active IN endpoint. Any FIFO \nsize is software configured to better meet the application requirements.\n400\n…\n…\n…\n…\n450\nLatency \nSOF \nreload \nOTG_FS_HFIR \nwrite \nvalue \nFrame\ntimer \nOld OTG_FS_HIFR value\n= 400 periods\nOTG_FS_HIFR value\n= 450 periods+HIFR write latency\nNew OTG_FS_HIFR value\n= 450 periods\n1\n400\n0\n399\n1\n400\n0\n399\n450\n449\n1\n450\n0\n449\n1\n450\n0\n449\nOTG_FS_HFIR \nai184\n" }, { "page_number": 1262, "page_indices": { "start_index": 2501963, "end_index": 2504045 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1262 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.11 Peripheral FIFO architecture", 1262 ], [ 3, "34.11.1 Peripheral Rx FIFO", 1262 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1262/1757\nRM0090 Rev 21\n34.11 \nPeripheral FIFO architecture\nFigure 392. Device-mode FIFO address mapping and AHB FIFO access mapping\n34.11.1 \nPeripheral Rx FIFO\nThe OTG peripheral uses a single receive FIFO that receives the data directed to all OUT \nendpoints. Received packets are stacked back-to-back until free space is available in the \nRx-FIFO. The status of the received packet (which contains the OUT endpoint destination \nnumber, the byte count, the data PID and the validity of the received data) is also stored by \nthe core on top of the data payload. When no more space is available, host transactions are \nNACKed and an interrupt is received on the addressed endpoint. The size of the receive \nFIFO is configured in the receive FIFO Size register (GRXFSIZ).\nThe single receive FIFO architecture makes it more efficient for the USB peripheral to fill in \nthe receive RAM buffer:\n•\nAll OUT endpoints share the same RAM buffer (shared FIFO)\n•\nThe OTG FS core can fill in the receive FIFO up to the limit for any host sequence of \nOUT tokens\nThe application keeps receiving the Rx-FIFO non-empty interrupt (RXFLVL bit in \nOTG_FS_GINTSTS) as long as there is at least one packet available for download. It reads \nthe packet information from the receive status read and pop register (GRXSTSP) and finally \npops data off the receive FIFO by reading from the endpoint-related pop address.\nMSv72655V1\nIN endpoint Tx FIFO #nDFIFO \npush accessfrom AHB\nAny OUT endpoint DFIFO \npopaccess from AHB\nDedicated \nTxFIFO #n \ncontrol(optional)\nDedicated \nTxFIFO #1 \ncontrol(optional)\nRx FIFO control\nIN endpoint Tx FIFO #1DFIFO \npush accessfrom AHB\nMAC pop\nMAC pop\nMAC push\nSingle dataFIFO\nTx FIFO #npacket\nTx FIFO #0 packet\nDIEPTXF2[31:16]\nDIEPTXF2[15:0]\nDIEPTXF1[31:16]\nGNPTXFSIZ[31:16]\nIN endpoint Tx FIFO #0DFIFO \npush accessfrom AHB\nDedicated \nTxFIFO #0 \ncontrol(optional)\nMAC pop\nTx FIFO #1 packet\nRx packets\n...\n...\n...\nGNPTXFSIZ[15:0]\nGRXFSIZ[15:0]\nA1 = 0\n(Rx start address \nfixed to 0)\nDIEPTXFx[15:0]\nDIEPTXF1[15:0]\n" }, { "page_number": 1263, "page_indices": { "start_index": 2504045, "end_index": 2506132 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1263 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.11 Peripheral FIFO architecture", 1262 ], [ 3, "34.11.2 Peripheral Tx FIFOs", 1263 ], [ 2, "34.12 Host FIFO architecture", 1263 ], [ 3, "34.12.1 Host Rx FIFO", 1263 ] ], "page_content": "RM0090 Rev 21\n1263/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34.11.2 \nPeripheral Tx FIFOs\nThe core has a dedicated FIFO for each IN endpoint. The application configures FIFO sizes \nby writing the non periodic transmit FIFO size register (OTG_FS_TX0FSIZ) for IN endpoint0 \nand the device IN endpoint transmit FIFOx registers (DIEPTXFx) for IN endpoint-x.\n34.12 \nHost FIFO architecture\nFigure 393. Host-mode FIFO address mapping and AHB FIFO access mapping\n34.12.1 \nHost Rx FIFO\nThe host uses one receiver FIFO for all periodic and nonperiodic transactions. The FIFO is \nused as a receive buffer to hold the received data (payload of the received packet) from the \nUSB until it is transferred to the system memory. Packets received from any remote IN \nendpoint are stacked back-to-back until free space is available. The status of each received \npacket with the host channel destination, byte count, data PID and validity of the received \ndata are also stored into the FIFO. The size of the receive FIFO is configured in the receive \nFIFO size register (GRXFSIZ).\nThe single receive FIFO architecture makes it highly efficient for the USB host to fill in the \nreceive data buffer:\n•\nAll IN configured host channels share the same RAM buffer (shared FIFO)\n•\nThe OTG FS core can fill in the receive FIFO up to the limit for any sequence of IN \ntokens driven by the host software\nThe application receives the Rx FIFO not-empty interrupt as long as there is at least one \npacket available for download. It reads the packet information from the receive status read \nand pop register and finally pops the data off the receive FIFO.\nAny periodic channel\nDFIFO push access\nfrom AHB\nAny channel DFIFO pop\naccess from AHB\nPeriodic Tx\nFIFO control\n(optional)\nNon-periodic\nTx FIFO control\nRx FIFO control\nAny non-periodic\nchannel DFIFO push\naccess from AHB\nMAC pop\nMAC pop\nMAC push\nSingle data\nFIFO\nPeriodic Tx packets\nPeriodic Tx packets\nRx packets\nHPTXFSIZ[31:16]\nHPTXFSIZ[15:0]\nNPTXFSIZ[31:16]\nNPTXFSIZ[15:0]\nRXFSIZ[31:16]\nRx start address\nfixed to 0\nA1 = 0\nai15610\n" }, { "page_number": 1264, "page_indices": { "start_index": 2506132, "end_index": 2509583 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1264 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.12 Host FIFO architecture", 1263 ], [ 3, "34.12.2 Host Tx FIFOs", 1264 ], [ 2, "34.13 FIFO RAM allocation", 1264 ], [ 3, "34.13.1 Device mode", 1264 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1264/1757\nRM0090 Rev 21\n34.12.2 \nHost Tx FIFOs\nThe host uses one transmit FIFO for all non-periodic (control and bulk) OUT transactions \nand one transmit FIFO for all periodic (isochronous and interrupt) OUT transactions. FIFOs \nare used as transmit buffers to hold the data (payload of the transmit packet) to be \ntransmitted over the USB. The size of the periodic (nonperiodic) Tx FIFO is configured in the \nhost periodic (nonperiodic) transmit FIFO size (HPTXFSIZ/HNPTXFSIZ) register.\nThe two Tx FIFO implementation derives from the higher priority granted to the periodic type \nof traffic over the USB frame. At the beginning of each frame, the built-in host scheduler \nprocesses the periodic request queue first, followed by the nonperiodic request queue.\nThe two transmit FIFO architecture provides the USB host with separate optimization for \nperiodic and nonperiodic transmit data buffer management:\n•\nAll host channels configured to support periodic (nonperiodic) transactions in the OUT \ndirection share the same RAM buffer (shared FIFOs)\n•\nThe OTG FS core can fill in the periodic (nonperiodic) transmit FIFO up to the limit for \nany sequence of OUT tokens driven by the host software\nThe OTG_FS core issues the periodic Tx FIFO empty interrupt (PTXFE bit in \nOTG_FS_GINTSTS) as long as the periodic Tx-FIFO is half or completely empty, \ndepending on the value of the periodic Tx-FIFO empty level bit in the AHB configuration \nregister (PTXFELVL bit in OTG_FS_GAHBCFG). The application can push the transmission \ndata in advance as long as free space is available in both the periodic Tx FIFO and the \nperiodic request queue. The host periodic transmit FIFO and queue status register \n(HPTXSTS) can be read to know how much space is available in both.\nOTG_FS core issues the non periodic Tx FIFO empty interrupt (NPTXFE bit in \nOTG_FS_GINTSTS) as long as the nonperiodic Tx FIFO is half or completely empty \ndepending on the non periodic Tx FIFO empty level bit in the AHB configuration register \n(TXFELVL bit in OTG_FS_GAHBCFG). The application can push the transmission data as \nlong as free space is available in both the nonperiodic Tx FIFO and nonperiodic request \nqueue. The host nonperiodic transmit FIFO and queue status register (HNPTXSTS) can be \nread to know how much space is available in both.\n34.13 \nFIFO RAM allocation\n34.13.1 \nDevice mode\nReceive FIFO RAM allocation: the application should allocate RAM for SETUP Packets: \n10 locations must be reserved in the receive FIFO to receive SETUP packets on control \nendpoint. The core does not use these locations, which are reserved for SETUP packets, to \nwrite any other data. One location is to be allocated for Global OUT NAK. Status information \nis written to the FIFO along with each received packet. Therefore, a minimum space of \n(Largest Packet Size / 4) + 1 must be allocated to receive packets. If multiple isochronous \nendpoints are enabled, then at least two (Largest Packet Size / 4) + 1 spaces must be \nallocated to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 1 \nspaces are recommended so that when the previous packet is being transferred to the CPU, \nthe USB can receive the subsequent packet. \nAlong with the last packet for each endpoint, transfer complete status information is also \npushed to the FIFO. Typically, one location for each OUT endpoint is recommended.\n" }, { "page_number": 1265, "page_indices": { "start_index": 2509583, "end_index": 2512412 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1265 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.13 FIFO RAM allocation", 1264 ], [ 3, "34.13.2 Host mode", 1265 ], [ 4, "Receive FIFO RAM allocation", 1265 ], [ 4, "Transmit FIFO RAM allocation", 1265 ], [ 2, "34.14 USB system performance", 1265 ] ], "page_content": "RM0090 Rev 21\n1265/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nTransmit FIFO RAM allocation: the minimum RAM space required for each IN Endpoint \nTransmit FIFO is the maximum packet size for that particular IN endpoint. \nNote:\nMore space allocated in the transmit IN Endpoint FIFO results in better performance on the \nUSB. \n34.13.2 \nHost mode\nReceive FIFO RAM allocation\nStatus information is written to the FIFO along with each received packet. Therefore, a \nminimum space of (Largest Packet Size / 4) + 1 must be allocated to receive packets. If \nmultiple isochronous channels are enabled, then at least two (Largest Packet Size / 4) + 1 \nspaces must be allocated to receive back-to-back packets. Typically, two (Largest Packet \nSize / 4) + 1 spaces are recommended so that when the previous packet is being \ntransferred to the CPU, the USB can receive the subsequent packet. \nAlong with the last packet in the host channel, transfer complete status information is also \npushed to the FIFO. So one location must be allocated for this. \nTransmit FIFO RAM allocation\nThe minimum amount of RAM required for the host Non-periodic Transmit FIFO is the \nlargest maximum packet size among all supported non-periodic OUT channels.\nTypically, two Largest Packet Sizes worth of space is recommended, so that when the \ncurrent packet is under transfer to the USB, the CPU can get the next packet.\nThe minimum amount of RAM required for host periodic Transmit FIFO is the largest \nmaximum packet size out of all the supported periodic OUT channels. If there is at least one \nIsochronous OUT endpoint, then the space must be at least two times the maximum packet \nsize of that channel. \nNote:\nMore space allocated in the Transmit Non-periodic FIFO results in better performance on \nthe USB.\n34.14 \nUSB system performance\nBest USB and system performance is achieved owing to the large RAM buffers, the highly \nconfigurable FIFO sizes, the quick 32-bit FIFO access through AHB push/pop registers and, \nespecially, the advanced FIFO control mechanism. Indeed, this mechanism allows the \nOTG_FS to fill in the available RAM space at best regardless of the current USB sequence. \nWith these features:\n•\nThe application gains good margins to calibrate its intervention in order to optimize the \nCPU bandwidth usage:\n–\nIt can accumulate large amounts of transmission data in advance compared to \nwhen they are effectively sent over the USB\n–\nIt benefits of a large time margin to download data from the single receive FIFO\n•\nThe USB Core is able to maintain its full operating rate, that is to provide maximum full-\nspeed bandwidth with a great margin of autonomy versus application intervention:\n–\nIt has a large reserve of transmission data at its disposal to autonomously manage \nthe sending of data over the USB\n" }, { "page_number": 1266, "page_indices": { "start_index": 2512412, "end_index": 2513454 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1266 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.15 OTG_FS interrupts", 1266 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1266/1757\nRM0090 Rev 21\n–\nIt has a lot of empty space available in the receive buffer to autonomously fill it in \nwith the data coming from the USB\nAs the OTG_FS core is able to fill in the 1.25 Kbyte RAM buffer very efficiently, and as \n1.25 Kbyte of transmit/receive data is more than enough to cover a full speed frame, the \nUSB system is able to withstand the maximum full-speed data rate for up to one USB frame \n(1 ms) without any CPU intervention.\n34.15 \nOTG_FS interrupts\nWhen the OTG_FS controller is operating in one mode, either device or host, the application \nmust not access registers from the other mode. If an illegal access occurs, a mode \nmismatch interrupt is generated and reflected in the Core interrupt register (MMIS bit in the \nOTG_FS_GINTSTS register). When the core switches from one mode to the other, the \nregisters in the new mode of operation must be reprogrammed as they would be after a \npower-on reset.\nFigure 394 shows the interrupt hierarchy.\n" }, { "page_number": 1267, "page_indices": { "start_index": 2513454, "end_index": 2514619 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1267 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.15 OTG_FS interrupts", 1266 ] ], "page_content": "RM0090 Rev 21\n1267/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nFigure 394. Interrupt hierarchy\n1.\nOTG_FS_WKUP become active (high state) when resume condition occurs during L1 SLEEP or L2 SUSPEND states.\nMSv36921V3\nOTG_DAINTMSK\nDevice all endpoints interrupt mask \nregister\nOTG_DIEPMSK/\nOTG_DOEPMSK\nDevice IN/OUT endpoints common \ninterrupt mask register\nOTG_HCTINTMSKx\nHost channels interrupt mask registers\nOTG_HAINTMSK\nHost all channels interrupt mask register\n31:26\n25 24\n23:20\n19 18\n17:3\n2\n1:0\nOTG_HCTINTx\nHost channels interrupt registers\nOTG_HAINT\nHost all channels interrupt register\nOTG_HPRT\nHost port control and status register\nOTG_DAINT\nDevice all endpoints interrupt register\n(15 + #EP):16\nOUT endpoints\n(#EP-1):0\nIN endpoints\nOTG_GOTGINT\nOTG interrupt register\nOTG_DIEPINTx/\nOTG_DOEPINTx\nDevice IN/OUT endpoint interrupt \nregisters\nOTG_GINTSTS\nCore register interrupt\nOTG_GINTMSK\nCore interrupt mask register\nOTG_AHBCFG\nAHB configuration register\nGlobal interrupt mask (bit 0)\nOR\nAND\nGlobal interrupt\nOTG_FS\nWakeup interrupt \nOTG_FS_WKUP\nAND\n(1)\nx = 0\nx = #HC-1\nx = 0\nx = #HC-1\nHCINT\nHPRTINT\nOEPINP\nIEPINT\nOTGINT\n...\n...\n" }, { "page_number": 1268, "page_indices": { "start_index": 2514619, "end_index": 2515964 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1268 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1268/1757\nRM0090 Rev 21\n34.16 \nOTG_FS control and status registers\nBy reading from and writing to the control and status registers (CSRs) through the AHB \nslave interface, the application controls the OTG_FS controller. These registers are 32 bits \nwide, and the addresses are 32-bit block aligned. The OTG_FS registers must be accessed \nby words (32 bits).\nCSRs are classified as follows:\n•\nCore global registers\n•\nHost-mode registers\n•\nHost global registers\n•\nHost port CSRs\n•\nHost channel-specific registers\n•\nDevice-mode registers\n•\nDevice global registers\n•\nDevice endpoint-specific registers\n•\nPower and clock-gating registers\n•\nData FIFO (DFIFO) access registers\nOnly the Core global, Power and clock-gating, Data FIFO access, and host port control and \nstatus registers can be accessed in both host and device modes. When the OTG_FS \ncontroller is operating in one mode, either device or host, the application must not access \nregisters from the other mode. If an illegal access occurs, a mode mismatch interrupt is \ngenerated and reflected in the Core interrupt register (MMIS bit in the OTG_FS_GINTSTS \nregister). When the core switches from one mode to the other, the registers in the new mode \nof operation must be reprogrammed as they would be after a power-on reset.\n" }, { "page_number": 1269, "page_indices": { "start_index": 2515964, "end_index": 2517378 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1269 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.1 CSR memory map", 1269 ], [ 4, "Global CSR map", 1269 ] ], "page_content": "RM0090 Rev 21\n1269/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34.16.1 \nCSR memory map\nThe host and device mode registers occupy different addresses. All registers are \nimplemented in the AHB clock domain.\nFigure 395. CSR memory map\n1.\nx = 3 in device mode and x = 7 in host mode.\nGlobal CSR map\nThese registers are available in both host and device modes.\n \n0000h\nCore global CSRs (1 Kbyte)\n0400h\nHost mode CSRs (1 Kbyte)\n0800h\nDevice mode CSRs (1.5 Kbyte)\n0E00h\nPower and clock gating CSRs (0.5 Kbyte)\n1000h\nDevice EP 0/Host channel 0 FIFO (4 Kbyte)\n2000h\nDevice EP1/Host channel 1 FIFO (4 Kbyte)\n3000h\nDevice EP (x – 1)(1)/Host channel (x – 1)(1) FIFO (4 Kbyte)\nDevice EP x(1)/Host channel x(1) FIFO (4 Kbyte)\nReserved\nDFIFO\npush/pop\nto this region\n2 0000h\n3 FFFFh\nDirect access to data FIFO RAM\nfor debugging (128 Kbyte)\nDFIFO\ndebug read/\nwrite to this\nregion\nai15615b\nTable 199. Core global control and status registers (CSRs)\nAcronym\nAddress \noffset\nRegister name\nOTG_FS_GOTGCTL\n0x000\nOTG_FS control and status register (OTG_FS_GOTGCTL) on page 1274\nOTG_FS_GOTGINT\n0x004\nOTG_FS interrupt register (OTG_FS_GOTGINT) on page 1275\nOTG_FS_GAHBCFG\n0x008\nOTG_FS AHB configuration register (OTG_FS_GAHBCFG) on page 1277\nOTG_FS_GUSBCFG\n0x00C\nOTG_FS USB configuration register (OTG_FS_GUSBCFG) on page 1278\nOTG_FS_GRSTCTL\n0x010\nOTG_FS reset register (OTG_FS_GRSTCTL) on page 1280\n" }, { "page_number": 1270, "page_indices": { "start_index": 2517378, "end_index": 2519541 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1270 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.1 CSR memory map", 1269 ], [ 4, "Host-mode CSR map", 1270 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1270/1757\nRM0090 Rev 21\nHost-mode CSR map\nThese registers must be programmed every time the core changes to host mode.\n \nOTG_FS_GINTSTS\n0x014\nOTG_FS core interrupt register (OTG_FS_GINTSTS) on page 1282\nOTG_FS_GINTMSK\n0x018\nOTG_FS interrupt mask register (OTG_FS_GINTMSK) on page 1286\nOTG_FS_GRXSTSR\n0x01C\nOTG_FS Receive status debug read/OTG status read and pop registers \n(OTG_FS_GRXSTSR/OTG_FS_GRXSTSP) on page 1289\nOTG_FS_GRXSTSP\n0x020\nOTG_FS_GRXFSIZ\n0x024\nOTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) on page 1290\nOTG_FS_HNPTXFSIZ/ \nOTG_FS_DIEPTXF0(1)\n0x028\nOTG_FS Host non-periodic transmit FIFO size register \n(OTG_FS_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size \n(OTG_FS_DIEPTXF0)\nOTG_FS_HNPTXSTS\n0x02C\nOTG_FS non-periodic transmit FIFO/queue status register \n(OTG_FS_HNPTXSTS) on page 1291\nOTG_FS_GCCFG\n0x038\nOTG_FS general core configuration register (OTG_FS_GCCFG) on \npage 1292\nOTG_FS_CID\n0x03C\nOTG_FS core ID register (OTG_FS_CID) on page 1293\nOTG_FS_HPTXFSIZ\n0x100\nOTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) on \npage 1294\nOTG_FS_DIEPTXFx\n0x104\n0x108\n0x10C\nOTG_FS device IN endpoint transmit FIFO size register \n(OTG_FS_DIEPTXFx) (x = 1..3, where x is the FIFO_number) on page 1294\n1.\nThe general rule is to use OTG_FS_HNPTXFSIZ for host mode and OTG_FS_DIEPTXF0 for device mode.\nTable 199. Core global control and status registers (CSRs) (continued)\nAcronym\nAddress \noffset\nRegister name\nTable 200. Host-mode control and status registers (CSRs)\nAcronym\nOffset \naddress\nRegister name\nOTG_FS_HCFG\n0x400\nOTG_FS Host configuration register (OTG_FS_HCFG) on page 1295\nOTG_FS_HFIR\n0x404\nOTG_FS Host frame interval register (OTG_FS_HFIR) on page 1295\nOTG_FS_HFNUM\n0x408\nOTG_FS Host frame number/frame time remaining register \n(OTG_FS_HFNUM) on page 1296\nOTG_FS_HPTXSTS\n0x410\nOTG_FS_Host periodic transmit FIFO/queue status register \n(OTG_FS_HPTXSTS) on page 1296\nOTG_FS_HAINT\n0x414\nOTG_FS Host all channels interrupt register (OTG_FS_HAINT) on \npage 1297\nOTG_FS_HAINTMSK\n0x418\nOTG_FS Host all channels interrupt mask register (OTG_FS_HAINTMSK) \non page 1298\n" }, { "page_number": 1271, "page_indices": { "start_index": 2519541, "end_index": 2521653 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1271 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.1 CSR memory map", 1269 ], [ 4, "Device-mode CSR map", 1271 ] ], "page_content": "RM0090 Rev 21\n1271/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nDevice-mode CSR map\nThese registers must be programmed every time the core changes to device mode.\n \nOTG_FS_HPRT\n0x440\nOTG_FS Host port control and status register (OTG_FS_HPRT) on \npage 1298\nOTG_FS_HCCHARx\n0x500\n0x520\n...\n0x5E0\nOTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx) \n(x = 0..7, where x = Channel_number) on page 1301\nOTG_FS_HCINTx\n0x508\nOTG_FS Host channel-x interrupt register (OTG_FS_HCINTx) (x = 0..7, \nwhere x = Channel_number) on page 1302\nOTG_FS_HCINTMSKx\n0x50C\nOTG_FS Host channel-x interrupt mask register (OTG_FS_HCINTMSKx) \n(x = 0..7, where x = Channel_number) on page 1303\nOTG_FS_HCTSIZx\n0x510\nOTG_FS Host channel-x transfer size register (OTG_FS_HCTSIZx) \n(x = 0..7, where x = Channel_number) on page 1304\nTable 200. Host-mode control and status registers (CSRs) (continued)\nAcronym\nOffset \naddress\nRegister name\nTable 201. Device-mode control and status registers\nAcronym\nOffset \naddress\nRegister name\nOTG_FS_DCFG\n0x800\nOTG_FS device configuration register (OTG_FS_DCFG) on page 1305\nOTG_FS_DCTL\n0x804\nOTG_FS device control register (OTG_FS_DCTL) on page 1306\nOTG_FS_DSTS\n0x808\nOTG_FS device status register (OTG_FS_DSTS) on page 1307\nOTG_FS_DIEPMSK\n0x810\nOTG_FS device IN endpoint common interrupt mask register \n(OTG_FS_DIEPMSK) on page 1308\nOTG_FS_DOEPMSK\n0x814\nOTG_FS device OUT endpoint common interrupt mask register \n(OTG_FS_DOEPMSK) on page 1309\nOTG_FS_DAINT\n0x818\nOTG_FS device all endpoints interrupt register (OTG_FS_DAINT) on \npage 1310\nOTG_FS_DAINTMSK\n0x81C\nOTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) on \npage 1311\nOTG_FS_DVBUSDIS\n0x828\nOTG_FS device VBUS discharge time register (OTG_FS_DVBUSDIS) on \npage 1311\nOTG_FS_DVBUSPULSE\n0x82C\nOTG_FS device VBUS pulsing time register (OTG_FS_DVBUSPULSE) \non page 1311\nOTG_FS_DIEPEMPMSK\n0x834\nOTG_FS device IN endpoint FIFO empty interrupt mask register: \n(OTG_FS_DIEPEMPMSK) on page 1312\nOTG_FS_DIEPCTL0\n0x900\nOTG_FS device control IN endpoint 0 control register \n(OTG_FS_DIEPCTL0) on page 1312\n" }, { "page_number": 1272, "page_indices": { "start_index": 2521653, "end_index": 2523945 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1272 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.1 CSR memory map", 1269 ], [ 4, "Data FIFO (DFIFO) access register map", 1272 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1272/1757\nRM0090 Rev 21\n \nData FIFO (DFIFO) access register map\nThese registers, available in both host and device modes, are used to read or write the FIFO \nspace for a specific endpoint or a channel, in a given direction. If a host channel is of type \nIN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the \nFIFO can only be written on the channel.\n \nOTG_FS_DIEPCTLx\n0x920\n0x940\n0x960\nOTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3, \nwhere x = Endpoint_number) on page 1314\nOTG_FS_DIEPINTx\n0x908\nOTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) \n(x = 0..3, where x = Endpoint_number) on page 1321\nOTG_FS_DIEPTSIZ0\n0x910\nOTG_FS device IN endpoint 0 transfer size register \n(OTG_FS_DIEPTSIZ0) on page 1323\nOTG_FS_DTXFSTSx \n0x918\nOTG_FS device IN endpoint transmit FIFO status register \n(OTG_FS_DTXFSTSx) (x = 0..3, where x = Endpoint_number) on \npage 1327\nOTG_FS_DIEPTSIZx\n0x930\n0x950\n0x970\nOTG_FS device endpoint-x transfer size register (OTG_FS_DIEPTSIZx) \n(x = 1..3, where x = Endpoint_number) on page 1326\nOTG_FS_DOEPCTL0\n0xB00\nOTG_FS device control OUT endpoint 0 control register \n(OTG_FS_DOEPCTL0) on page 1317\nOTG_FS_DOEPCTLx\n0xB20\n0xB40\n0xB60\nOTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3, \nwhere x = Endpoint_number) on page 1314\nOTG_FS_DOEPINTx\n0xB08\nOTG_FS device endpoint-x interrupt register (OTG_FS_DOEPINTx) \n(x = 0..3, where x = Endpoint_number) on page 1322\nOTG_FS_DOEPTSIZ0\n0xB10\nOTG_FS device OUT endpoint 0 transfer size register \n(OTG_FS_DOEPTSIZ0) on page 1325\nOTG_FS_DOEPTSIZx\n0xB30\n0xB50\n0xB70\nOTG_FS device OUT endpoint-x transfer size register \n(OTG_FS_DOEPTSIZx) (x = 1..3, where x = Endpoint_number) on \npage 1327\nTable 201. Device-mode control and status registers (continued)\nAcronym\nOffset \naddress\nRegister name\nTable 202. Data FIFO (DFIFO) access register map\nFIFO access register section\nAddress range\nAccess\nDevice IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access\nDevice OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access\n0x1000–0x1FFC\nw\nr\nDevice IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access\nDevice OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access\n0x2000–0x2FFC\nw\nr\n" }, { "page_number": 1273, "page_indices": { "start_index": 2523945, "end_index": 2524708 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1273 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.1 CSR memory map", 1269 ], [ 4, "Power and clock gating CSR map", 1273 ] ], "page_content": "RM0090 Rev 21\n1273/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nPower and clock gating CSR map\nThere is a single register for power and clock gating. It is available in both host and device \nmodes.\n \n...\n...\n...\nDevice IN Endpoint x(1)/Host OUT Channel x(1): DFIFO Write Access\nDevice OUT Endpoint x(1)/Host IN Channel x(1): DFIFO Read Access 0xX000–0xXFFC\nw\nr\n1.\nWhere x is 3 in device mode and 7 in host mode.\nTable 203. Power and clock gating control and status registers\nRegister name\nAcronym\nOffset address: 0xE00–0xFFF\nPower and clock gating control register\nOTG_FS_PCGCCTL\n0xE00-0xE04\nReserved\n-\n0xE05–0xFFF\nTable 202. Data FIFO (DFIFO) access register map (continued)\nFIFO access register section\nAddress range\nAccess\n" }, { "page_number": 1274, "page_indices": { "start_index": 2524708, "end_index": 2526479 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1274 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS control and status register (OTG_FS_GOTGCTL)", 1274 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1274/1757\nRM0090 Rev 21\n34.16.2 \nOTG_FS global registers\nThese registers are available in both host and device modes, and do not need to be \nreprogrammed when switching between these modes.\nBit values in the register descriptions are expressed in binary unless otherwise specified.\nOTG_FS control and status register (OTG_FS_GOTGCTL)\nAddress offset: 0x000\nReset value: 0x0001 0000\nThe OTG_FS_GOTGCTL register controls the behavior and reflects the status of the OTG \nfunction of the core.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBSVLD\nASVLD\nDBCT\nCIDSTS\nReserved\nDHNPEN\nHSHNPEN\nHNPRQ\nHNGSCS\nReserved\nSRQ\nSRQSCS\nr\nr\nr\nr\nrw\nrw\nrw\nr\nrw\nr\nBits 31:20 Reserved, must be kept at reset value.\nBit 19 BSVLD: B-session valid\nIndicates the device mode transceiver status.\n0: B-session is not valid.\n1: B-session is valid.\nIn OTG mode, you can use this bit to determine if the device is connected or disconnected.\nNote: Only accessible in device mode.\nBit 18 ASVLD: A-session valid\nIndicates the host mode transceiver status.\n0: A-session is not valid\n1: A-session is valid\nNote: Only accessible in host mode.\nBit 17 DBCT: Long/short debounce time\nIndicates the debounce time of a detected connection.\n0: Long debounce time, used for physical connections (100 ms + 2.5 µs)\n1: Short debounce time, used for soft connections (2.5 µs)\nNote: Only accessible in host mode.\nBit 16 CIDSTS: Connector ID status\nIndicates the connector ID status on a connect event.\n0: The OTG_FS controller is in A-device mode\n1: The OTG_FS controller is in B-device mode\nNote: Accessible in both device and host modes.\nBits 15:12 Reserved, must be kept at reset value.\n" }, { "page_number": 1275, "page_indices": { "start_index": 2526479, "end_index": 2528800 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1275 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS interrupt register (OTG_FS_GOTGINT)", 1275 ] ], "page_content": "RM0090 Rev 21\n1275/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS interrupt register (OTG_FS_GOTGINT)\nAddress offset: 0x04\nReset value: 0x0000 0000\nBit 11 DHNPEN: Device HNP enabled\nThe application sets this bit when it successfully receives a SetFeature.SetHNPEnable \ncommand from the connected USB host.\n0: HNP is not enabled in the application\n1: HNP is enabled in the application\nNote: Only accessible in device mode.\nBit 10 HSHNPEN: host set HNP enable\nThe application sets this bit when it has successfully enabled HNP (using the \nSetFeature.SetHNPEnable command) on the connected device.\n0: Host Set HNP is not enabled\n1: Host Set HNP is enabled\nNote: Only accessible in host mode.\nBit 9 HNPRQ: HNP request\nThe application sets this bit to initiate an HNP request to the connected USB host. The \napplication can clear this bit by writing a 0 when the host negotiation success status change \nbit in the OTG_FS_GOTGINT register (HNSSCHG bit in OTG_FS_GOTGINT) is set. The \ncore clears this bit when the HNSSCHG bit is cleared.\n0: No HNP request\n1: HNP request\nNote: Only accessible in device mode.\nBit 8 HNGSCS: Host negotiation success\nThe core sets this bit when host negotiation is successful. The core clears this bit when the \nHNP Request (HNPRQ) bit in this register is set.\n0: Host negotiation failure\n1: Host negotiation success\nNote: Only accessible in device mode.\nBits 7:2 Reserved, must be kept at reset value.\nBit 1 SRQ: Session request\nThe application sets this bit to initiate a session request on the USB. The application can \nclear this bit by writing a 0 when the host negotiation success status change bit in the \nOTG_FS_GOTGINT register (HNSSCHG bit in OTG_FS_GOTGINT) is set. The core clears \nthis bit when the HNSSCHG bit is cleared.\nIf you use the USB 1.1 full-speed serial transceiver interface to initiate the session request, \nthe application must wait until VBUS discharges to 0.2 V, after the B-Session Valid bit in this \nregister (BSVLD bit in OTG_FS_GOTGCTL) is cleared.\n0: No session request\n1: Session request\nNote: Only accessible in device mode.\nBit 0 SRQSCS: Session request success\nThe core sets this bit when a session request initiation is successful.\n0: Session request failure\n1: Session request success\nNote: Only accessible in device mode.\n" }, { "page_number": 1276, "page_indices": { "start_index": 2528800, "end_index": 2531032 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1276 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS interrupt register (OTG_FS_GOTGINT)", 1275 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1276/1757\nRM0090 Rev 21\nThe application reads this register whenever there is an OTG interrupt and clears the bits in \nthis register to clear the OTG interrupt.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDBCDNE\nADTOCHG\nHNGDET\nReserved\nHNSSCHG\nSRSSCHG\nReserved\nSEDET\nRes.\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nBits 31:20 Reserved, must be kept at reset value.\nBit 19 DBCDNE: Debounce done\nThe core sets this bit when the debounce is completed after the device connect. The \napplication can start driving USB reset after seeing this interrupt. This bit is only valid when \nthe HNP Capable or SRP Capable bit is set in the OTG_FS_GUSBCFG register (HNPCAP \nbit or SRPCAP bit in OTG_FS_GUSBCFG, respectively).\nNote: Only accessible in host mode.\nBit 18 ADTOCHG: A-device timeout change\nThe core sets this bit to indicate that the A-device has timed out while waiting for the B-device \nto connect.\nNote: Accessible in both device and host modes.\nBit 17 HNGDET: Host negotiation detected\nThe core sets this bit when it detects a host negotiation request on the USB. \nNote: Accessible in both device and host modes.\nBits 16:10 Reserved, must be kept at reset value.\nBit 9 HNSSCHG: Host negotiation success status change\nThe core sets this bit on the success or failure of a USB host negotiation request. The \napplication must read the host negotiation success bit of the OTG_FS_GOTGCTL register \n(HNGSCS in OTG_FS_GOTGCTL) to check for success or failure.\nNote: Accessible in both device and host modes.\nBits 7:3 Reserved, must be kept at reset value.\nBit 8 SRSSCHG: Session request success status change\nThe core sets this bit on the success or failure of a session request. The application must \nread the session request success bit in the OTG_FS_GOTGCTL register (SRQSCS bit in \nOTG_FS_GOTGCTL) to check for success or failure.\nNote: Accessible in both device and host modes.\nBit 2 SEDET: Session end detected\nThe core sets this bit to indicate that the level of the voltage on VBUS is no longer valid for a \nB-Peripheral session when VBUS < 0.8 V.\nBits 1:0 Reserved, must be kept at reset value.\n" }, { "page_number": 1277, "page_indices": { "start_index": 2531032, "end_index": 2533253 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1277 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS AHB configuration register (OTG_FS_GAHBCFG)", 1277 ] ], "page_content": "RM0090 Rev 21\n1277/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS AHB configuration register (OTG_FS_GAHBCFG)\nAddress offset: 0x008\nReset value: 0x0000 0000\nThis register can be used to configure the core after power-on or a change in mode. This \nregister mainly contains AHB system-related configuration parameters. Do not change this \nregister after the initial programming. The application must program this register before \nstarting any transactions on either the AHB or the USB.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPTXFELVL\nTXFELVL\nReserved\nGINTMSK\nrw\nrw\nrw\nBits 31:9 Reserved, must be kept at reset value.\nBit 8 PTXFELVL: Periodic TxFIFO empty level\nIndicates when the periodic TxFIFO empty interrupt bit in the OTG_FS_GINTSTS register \n(PTXFE bit in OTG_FS_GINTSTS) is triggered.\n0: PTXFE (in OTG_FS_GINTSTS) interrupt indicates that the Periodic TxFIFO is half empty\n1: PTXFE (in OTG_FS_GINTSTS) interrupt indicates that the Periodic TxFIFO is completely \nempty\nNote: Only accessible in host mode.\nBit 7 TXFELVL: TxFIFO empty level\nIn device mode, this bit indicates when IN endpoint Transmit FIFO empty interrupt (TXFE in \nOTG_FS_DIEPINTx.) is triggered.\n0: the TXFE (in OTG_FS_DIEPINTx) interrupt indicates that the IN Endpoint TxFIFO is half \nempty\n1: the TXFE (in OTG_FS_DIEPINTx) interrupt indicates that the IN Endpoint TxFIFO is \ncompletely empty\nIn host mode, this bit indicates when the nonperiodic Tx FIFO empty interrupt (NPTXFE bit in \nOTG_FS_GINTSTS) is triggered:\n0: the NPTXFE (in OTG_FS_GINTSTS) interrupt indicates that the nonperiodic Tx FIFO is \nhalf empty\n1: the NPTXFE (in OTG_FS_GINTSTS) interrupt indicates that the nonperiodic Tx FIFO is \ncompletely empty\nBits 6:1 Reserved, must be kept at reset value.\nBit 0 GINTMSK: Global interrupt mask\nThe application uses this bit to mask or unmask the interrupt line assertion to itself. \nIrrespective of this bit’s setting, the interrupt status registers are updated by the core.\n0: Mask the interrupt assertion to the application.\n1: Unmask the interrupt assertion to the application.\nNote: Accessible in both device and host modes.\n" }, { "page_number": 1278, "page_indices": { "start_index": 2533253, "end_index": 2535418 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1278 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS USB configuration register (OTG_FS_GUSBCFG)", 1278 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1278/1757\nRM0090 Rev 21\nOTG_FS USB configuration register (OTG_FS_GUSBCFG)\nAddress offset: 0x00C\nReset value: 0x0000 0A40\nThis register can be used to configure the core after power-on or a changing to host mode \nor device mode. It contains USB and USB-PHY related configuration parameters. The \napplication must program this register before starting any transactions on either the AHB or \nthe USB. Do not make changes to this register after the initial programming.\n \n \n31\n30\n29\n28 27 26 25 24 23 22 21 20 19 18 17 16 15 14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCTXPKT\nFDMOD\nFHMOD\nReserved\nTRDT\nHNPCA\nP\nSRPCAP\nRes.\nPHYSEL\nReserved\nTOCAL\nrw\nrw\nrw\nrw\nrw\nrw\nr\nrw\nBit 31 CTXPKT: Corrupt Tx packet\nThis bit is for debug purposes only. Never set this bit to 1.\nNote: Accessible in both device and host modes.\nBit 30 FDMOD: Force device mode\nWriting a 1 to this bit forces the core to device mode irrespective of the OTG_FS_ID input \npin.\n0: Normal mode\n1: Force device mode\nAfter setting the force bit, the application must wait at least 25 ms before the change takes \neffect.\nNote: Accessible in both device and host modes.\nBit 29 FHMOD: Force host mode\nWriting a 1 to this bit forces the core to host mode irrespective of the OTG_FS_ID input pin.\n0: Normal mode\n1: Force host mode\nAfter setting the force bit, the application must wait at least 25 ms before the change takes \neffect.\nNote: Accessible in both device and host modes.\nBits 28:14 Reserved, must be kept at reset value.\nBits 13:10 TRDT: USB turnaround time\nThese bits allow setting the turnaround time in PHY clocks. They must be configured \naccording to Table 204: TRDT values, depending on the application AHB frequency. Higher \nTRDT values allow stretching the USB response time to IN tokens in order to compensate for \nlonger AHB read access latency to the Data FIFO. \nNote: Only accessible in device mode.\nBit 9 HNPCAP: HNP-capable\nThe application uses this bit to control the OTG_FS controller’s HNP capabilities.\n0: HNP capability is not enabled.\n1: HNP capability is enabled.\nNote: Accessible in both device and host modes.\n" }, { "page_number": 1279, "page_indices": { "start_index": 2535418, "end_index": 2536871 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1279 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS USB configuration register (OTG_FS_GUSBCFG)", 1278 ] ], "page_content": "RM0090 Rev 21\n1279/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n \nBit 8 SRPCAP: SRP-capable\nThe application uses this bit to control the OTG_FS controller’s SRP capabilities. If the core \noperates as a non-SRP-capable \nB-device, it cannot request the connected A-device (host) to activate VBUS and start a \nsession.\n0: SRP capability is not enabled.\n1: SRP capability is enabled.\nNote: Accessible in both device and host modes.\nBit 7 Reserved, must be kept at reset value.\nBit 6 PHYSEL: Full speed serial transceiver select\nThis bit is always 1 with read-only access.\nBits 5:3 Reserved, must be kept at reset value.\nBits 2:0 TOCAL: FS timeout calibration\nThe number of PHY clocks that the application programs in this field is added to the full-\nspeed interpacket timeout duration in the core to account for any additional delays \nintroduced by the PHY. This can be required, because the delay introduced by the PHY in \ngenerating the line state condition can vary from one PHY to another.\nThe USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The \napplication must program this field based on the speed of enumeration. The number of bit \ntimes added per PHY clock is 0.25 bit times.\nTable 204. TRDT values\nAHB frequency range (MHz)\nTRDT minimum value\nMin.\nMax\n14.2\n15\n0xF\n15\n16\n0xE\n16\n17.2\n0xD\n17.2\n18.5\n0xC\n18.5\n20\n0xB\n20\n21.8\n0xA\n21.8\n24\n0x9\n24\n27.5\n0x8\n27.5\n32\n0x7\n32\n-\n0x6\n" }, { "page_number": 1280, "page_indices": { "start_index": 2536871, "end_index": 2539132 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1280 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS reset register (OTG_FS_GRSTCTL)", 1280 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1280/1757\nRM0090 Rev 21\nOTG_FS reset register (OTG_FS_GRSTCTL)\nAddress offset: 0x010\nReset value: 0x8000 0000\nThe application uses this register to reset various hardware features inside the core.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nAHBIDL\nReserved\nTXFNUM\nTXFFLSH\nRXFFLSH\nReserved\nFCRST\nHSRST\nCSRST\nr\nrw\nrs\nrs\nrs\nrs\nrs\nBit 31 AHBIDL: AHB master idle\nIndicates that the AHB master state machine is in the Idle condition.\nNote: Accessible in both device and host modes.\nBits 30:11 Reserved, must be kept at reset value.\nBits 10:6 TXFNUM: TxFIFO number\nThis is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not \nbe changed until the core clears the TxFIFO Flush bit.\n00000:\n–\nNon-periodic TxFIFO flush in host mode\n–\nTx FIFO 0 flush in device mode\n00001:\n–\nPeriodic TxFIFO flush in host mode\n–\nTXFIFO 1 flush in device mode \n00010: TXFIFO 2 flush in device mode \n...\n00101: TXFIFO 15 flush in device mode \n10000: Flush all the transmit FIFOs in device or host mode.\nNote: Accessible in both device and host modes.\nBit 5 TXFFLSH: TxFIFO flush\nThis bit selectively flushes a single or all transmit FIFOs, but cannot do so if the core is in the \nmidst of a transaction.\nThe application must write this bit only after checking that the core is neither writing to the \nTxFIFO nor reading from the TxFIFO. Verify using these registers:\nRead—NAK Effective Interrupt ensures the core is not reading from the FIFO\nWrite—AHBIDL bit in OTG_FS_GRSTCTL ensures the core is not writing anything to the \nFIFO.\nNote: Accessible in both device and host modes.\nBit 4 RXFFLSH: RxFIFO flush\nThe application can flush the entire RxFIFO using this bit, but must first ensure that the core \nis not in the middle of a transaction.\nThe application must only write to this bit after checking that the core is neither reading from \nthe RxFIFO nor writing to the RxFIFO.\nThe application must wait until the bit is cleared before performing any other operations. This \nbit requires 8 clocks (slowest of PHY or AHB clock) to clear.\nNote: Accessible in both device and host modes.\nBit 3 Reserved, must be kept at reset value.\n" }, { "page_number": 1281, "page_indices": { "start_index": 2539132, "end_index": 2541998 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1281 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS reset register (OTG_FS_GRSTCTL)", 1280 ] ], "page_content": "RM0090 Rev 21\n1281/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nBit 2 FCRST: Host frame counter reset\nThe application writes this bit to reset the frame number counter inside the core. When the \nframe counter is reset, the subsequent SOF sent out by the core has a frame number of 0.\nNote: Only accessible in host mode.\nBit 1 HSRST: HCLK soft reset\nThe application uses this bit to flush the control logic in the AHB Clock domain. Only AHB \nClock Domain pipelines are reset.\nFIFOs are not flushed with this bit.\nAll state machines in the AHB clock domain are reset to the Idle state after terminating the \ntransactions on the AHB, following the protocol.\nCSR control bits used by the AHB clock domain state machines are cleared.\nTo clear this interrupt, status mask bits that control the interrupt status and are generated by \nthe AHB clock domain state machine are cleared.\nBecause interrupt status bits are not cleared, the application can get the status of any core \nevents that occurred after it set this bit.\nThis is a self-clearing bit that the core clears after all necessary logic is reset in the core. This \ncan take several clocks, depending on the core’s current state.\nNote: Accessible in both device and host modes.\nBit 0 CSRST: Core soft reset\nResets the HCLK and PCLK domains as follows:\nClears the interrupts and all the CSR register bits except for the following bits:\n– RSTPDMODL bit in OTG_FS_PCGCCTL\n– GAYEHCLK bit in OTG_FS_PCGCCTL\n– PWRCLMP bit in OTG_FS_PCGCCTL\n– STPPCLK bit in OTG_FS_PCGCCTL\n– FSLSPCS bit in OTG_FS_HCFG\n– DSPD bit in OTG_FS_DCFG\nAll module state machines (except for the AHB slave unit) are reset to the Idle state, and all \nthe transmit FIFOs and the receive FIFO are flushed.\nAny transactions on the AHB Master are terminated as soon as possible, after completing the \nlast data phase of an AHB transfer. Any transactions on the USB are terminated immediately.\nThe application can write to this bit any time it wants to reset the core. This is a self-clearing \nbit and the core clears this bit after all the necessary logic is reset in the core, which can take \nseveral clocks, depending on the current state of the core. Once this bit has been cleared, \nthe software must wait at least 3 PHY clocks before accessing the PHY domain \n(synchronization delay). The software must also check that bit 31 in this register is set to 1 \n(AHB Master is Idle) before starting any operation.\nTypically, the software reset is used during software development and also when you \ndynamically change the PHY selection bits in the above listed USB configuration registers. \nWhen you change the PHY, the corresponding clock for the PHY is selected and used in the \nPHY domain. Once a new clock is selected, the PHY domain has to be reset for proper \noperation.\nNote: Accessible in both device and host modes.\n" }, { "page_number": 1282, "page_indices": { "start_index": 2541998, "end_index": 2544582 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1282 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS core interrupt register (OTG_FS_GINTSTS)", 1282 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1282/1757\nRM0090 Rev 21\nOTG_FS core interrupt register (OTG_FS_GINTSTS)\nAddress offset: 0x014\nReset value: 0x0400 0020\nThis register interrupts the application for system-level events in the current mode (device \nmode or host mode).\nSome of the bits in this register are valid only in host mode, while others are valid in device \nmode only. This register also indicates the current mode. To clear the interrupt status bits of \nthe rc_w1 type, the application must write 1 into the bit.\nThe FIFO status interrupts are read-only; once software reads from or writes to the FIFO \nwhile servicing these interrupts, FIFO interrupt conditions are cleared automatically.\nThe application must clear the OTG_FS_GINTSTS register at initialization before \nunmasking the interrupt bit to avoid any interrupts generated prior to initialization.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nWKUINT\nSRQINT\nDISCINT\nCIDSCHG\nReserved\nPTXFE\nHCINT\nHPRTINT\nReserved\nIPXFR/INCOMPISOOUT\nIISOIXFR\nOEPINT\nIEPINT\nReserved\nEOPF\nISOODRP\nENUMDNE\nUSBRST\nUSBSUSP\nESUSP\nReserved\nGONAKEFF\nGINAKEFF\nNPTXFE\nRXFLVL\nSOF\nOTGINT\nMMIS\nCMOD\nrc_w1\nr\nr\nr\nRes.\nrc_w1\nr\nr\nrc_w1\nr\nr\nr\nr\nrc_w1\nr\nrc_w1\nr\nBit 31 WKUPINT: Resume/remote wake-up detected interrupt\nIn device mode, this interrupt is asserted when a resume is detected on the USB. In host \nmode, this interrupt is asserted when a remote wake-up is detected on the USB.\nNote: Accessible in both device and host modes.\nBit 30 SRQINT: Session request/new session detected interrupt\nIn host mode, this interrupt is asserted when a session request is detected from the device. \nIn device mode, this interrupt is asserted when VBUS is in the valid range for a B-peripheral \ndevice. Accessible in both device and host modes.\nBit 29 DISCINT: Disconnect detected interrupt\nAsserted when a device disconnect is detected.\nNote: Only accessible in host mode.\nBit 28 CIDSCHG: Connector ID status change\nThe core sets this bit when there is a change in connector ID status.\nNote: Accessible in both device and host modes.\nBit 27 Reserved, must be kept at reset value.\nBit 26 PTXFE: Periodic TxFIFO empty\nAsserted when the periodic transmit FIFO is either half or completely empty and there is \nspace for at least one entry to be written in the periodic request queue. The half or \ncompletely empty status is determined by the periodic TxFIFO empty level bit in the \nOTG_FS_GAHBCFG register (PTXFELVL bit in OTG_FS_GAHBCFG).\nNote: Only accessible in host mode.\n" }, { "page_number": 1283, "page_indices": { "start_index": 2544582, "end_index": 2547939 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1283 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS core interrupt register (OTG_FS_GINTSTS)", 1282 ] ], "page_content": "RM0090 Rev 21\n1283/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nBit 25 HCINT: Host channels interrupt\nThe core sets this bit to indicate that an interrupt is pending on one of the channels of the \ncore (in host mode). The application must read the OTG_FS_HAINT register to determine \nthe exact number of the channel on which the interrupt occurred, and then read the \ncorresponding OTG_FS_HCINTx register to determine the exact cause of the interrupt. The \napplication must clear the appropriate status bit in the OTG_FS_HCINTx register to clear \nthis bit.\nNote: Only accessible in host mode.\nBit 24 HPRTINT: Host port interrupt\nThe core sets this bit to indicate a change in port status of one of the OTG_FS controller \nports in host mode. The application must read the OTG_FS_HPRT register to determine the \nexact event that caused this interrupt. The application must clear the appropriate status bit in \nthe OTG_FS_HPRT register to clear this bit.\nNote: Only accessible in host mode.\nBits 23:22 Reserved, must be kept at reset value.\nBit 21 IPXFR: Incomplete periodic transfer\nIn host mode, the core sets this interrupt bit when there are incomplete periodic transactions \nstill pending, which are scheduled for the current frame.\nINCOMPISOOUT: Incomplete isochronous OUT transfer\nIn device mode, the core sets this interrupt to indicate that there is at least one isochronous \nOUT endpoint on which the transfer is not completed in the current frame. This interrupt is \nasserted along with the End of periodic frame interrupt (EOPF) bit in this register.\nBit 20 IISOIXFR: Incomplete isochronous IN transfer\nThe core sets this interrupt to indicate that there is at least one isochronous IN endpoint on \nwhich the transfer is not completed in the current frame. This interrupt is asserted along with \nthe End of periodic frame interrupt (EOPF) bit in this register.\nNote: Only accessible in device mode.\nBit 19 OEPINT: OUT endpoint interrupt\nThe core sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of \nthe core (in device mode). The application must read the OTG_FS_DAINT register to \ndetermine the exact number of the OUT endpoint on which the interrupt occurred, and then \nread the corresponding OTG_FS_DOEPINTx register to determine the exact cause of the \ninterrupt. The application must clear the appropriate status bit in the corresponding \nOTG_FS_DOEPINTx register to clear this bit.\nNote: Only accessible in device mode.\nBit 18 IEPINT: IN endpoint interrupt\nThe core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the \ncore (in device mode). The application must read the OTG_FS_DAINT register to determine \nthe exact number of the IN endpoint on which the interrupt occurred, and then read the \ncorresponding OTG_FS_DIEPINTx register to determine the exact cause of the interrupt. \nThe application must clear the appropriate status bit in the corresponding \nOTG_FS_DIEPINTx register to clear this bit.\nNote: Only accessible in device mode.\nBits 17:16 Reserved, must be kept at reset value.\nBit 15 EOPF: End of periodic frame interrupt\nIndicates that the period specified in the periodic frame interval field of the OTG_FS_DCFG \nregister (PFIVL bit in OTG_FS_DCFG) has been reached in the current frame.\nNote: Only accessible in device mode.\n" }, { "page_number": 1284, "page_indices": { "start_index": 2547939, "end_index": 2550690 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1284 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS core interrupt register (OTG_FS_GINTSTS)", 1282 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1284/1757\nRM0090 Rev 21\nBit 14 ISOODRP: Isochronous OUT packet dropped interrupt\nThe core sets this bit when it fails to write an isochronous OUT packet into the RxFIFO \nbecause the RxFIFO does not have enough space to accommodate a maximum size packet \nfor the isochronous OUT endpoint.\nNote: Only accessible in device mode.\nBit 13 ENUMDNE: Enumeration done\nThe core sets this bit to indicate that speed enumeration is complete. The application must \nread the OTG_FS_DSTS register to obtain the enumerated speed.\nNote: Only accessible in device mode.\nBit 12 USBRST: USB reset\nThe core sets this bit to indicate that a reset is detected on the USB.\nNote: Only accessible in device mode.\nBit 11 USBSUSP: USB suspend\nThe core sets this bit to indicate that a suspend was detected on the USB. The core enters \nthe Suspended state when there is no activity on the data lines for a period of 3 ms.\nNote: Only accessible in device mode.\nBit 10 ESUSP: Early suspend\nThe core sets this bit to indicate that an Idle state has been detected on the USB for 3 ms.\nNote: Only accessible in device mode.\nBits 9:8 Reserved, must be kept at reset value.\nBit 7 GONAKEFF: Global OUT NAK effective\nIndicates that the Set global OUT NAK bit in the OTG_FS_DCTL register (SGONAK bit in \nOTG_FS_DCTL), set by the application, has taken effect in the core. This bit can be cleared \nby writing the Clear global OUT NAK bit in the OTG_FS_DCTL register (CGONAK bit in \nOTG_FS_DCTL).\nNote: Only accessible in device mode.\nBit 6 GINAKEFF: Global IN non-periodic NAK effective\nIndicates that the Set global non-periodic IN NAK bit in the OTG_FS_DCTL register \n(SGINAK bit in OTG_FS_DCTL), set by the application, has taken effect in the core. That is, \nthe core has sampled the Global IN NAK bit set by the application. This bit can be cleared by \nclearing the Clear global non-periodic IN NAK bit in the OTG_FS_DCTL register (CGINAK \nbit in OTG_FS_DCTL).\nThis interrupt does not necessarily mean that a NAK handshake is sent out on the USB. The \nSTALL bit takes precedence over the NAK bit.\nNote: Only accessible in device mode.\nBit 5 NPTXFE: Non-periodic TxFIFO empty\nThis interrupt is asserted when the non-periodic TxFIFO is either half or completely empty, \nand there is space for at least one entry to be written to the non-periodic transmit request \nqueue. The half or completely empty status is determined by the non-periodic TxFIFO empty \nlevel bit in the OTG_FS_GAHBCFG register (TXFELVL bit in OTG_FS_GAHBCFG).\nNote: Accessible in host mode only.\nBit 4 RXFLVL: RxFIFO non-empty\nIndicates that there is at least one packet pending to be read from the RxFIFO.\nNote: Accessible in both host and device modes.\n" }, { "page_number": 1285, "page_indices": { "start_index": 2550690, "end_index": 2552240 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1285 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS core interrupt register (OTG_FS_GINTSTS)", 1282 ] ], "page_content": "RM0090 Rev 21\n1285/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nBit 3 SOF: Start of frame\nIn host mode, the core sets this bit to indicate that an SOF (FS), or Keep-Alive (LS) is \ntransmitted on the USB. The application must write a 1 to this bit to clear the interrupt.\nIn device mode, in the core sets this bit to indicate that an SOF token has been received on \nthe USB. The application can read the Device Status register to get the current frame \nnumber. This interrupt is seen only when the core is operating in FS.\nNote: Accessible in both host and device modes.\nBit 2 OTGINT: OTG interrupt\nThe core sets this bit to indicate an OTG protocol event. The application must read the OTG \nInterrupt Status (OTG_FS_GOTGINT) register to determine the exact event that caused this \ninterrupt. The application must clear the appropriate status bit in the OTG_FS_GOTGINT \nregister to clear this bit.\nNote: Accessible in both host and device modes.\nBit 1 MMIS: Mode mismatch interrupt\nThe core sets this bit when the application is trying to access:\n–\nA host mode register, when the core is operating in device mode\n–\nA device mode register, when the core is operating in host mode\nThe register access is completed on the AHB with an OKAY response, but is ignored by the \ncore internally and does not affect the operation of the core.\nNote: Accessible in both host and device modes.\nBit 0 CMOD: Current mode of operation\nIndicates the current mode.\n0: Device mode\n1: Host mode\nNote: Accessible in both host and device modes.\n" }, { "page_number": 1286, "page_indices": { "start_index": 2552240, "end_index": 2554091 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1286 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS interrupt mask register (OTG_FS_GINTMSK)", 1286 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1286/1757\nRM0090 Rev 21\nOTG_FS interrupt mask register (OTG_FS_GINTMSK)\nAddress offset: 0x018\nReset value: 0x0000 0000\nThis register works with the Core interrupt register to interrupt the application. When an \ninterrupt bit is masked, the interrupt associated with that bit is not generated. However, the \nCore Interrupt (OTG_FS_GINTSTS) register bit corresponding to that interrupt is still set.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nWUIM\nSRQIM\nDISCINT\nCIDSCHGM\nReserved\nPTXFEM\nHCIM\nPRTIM\nReserved\nIPXFRM/IISOOXFRM\nIISOIXFRM\nOEPINT\nIEPINT\nReserved\nEOPFM\nISOODRPM\nENUMDNEM\nUSBRST\nUSBSUSPM\nESUSPM\nReserved\nGONAKEFFM\nGINAKEFFM\nNPTXFEM\nRXFLVLM\nSOFM\nOTGINT\nMMISM\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 WUIM: Resume/remote wake-up detected interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both host and device modes.\nBit 30 SRQIM: Session request/new session detected interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both host and device modes.\nBit 29 DISCINT: Disconnect detected interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 28 CIDSCHGM: Connector ID status change mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both host and device modes.\nBit 27 Reserved, must be kept at reset value.\nBit 26 PTXFEM: Periodic TxFIFO empty mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in host mode.\nBit 25 HCIM: Host channels interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in host mode.\nBit 24 PRTIM: Host port interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in host mode.\n" }, { "page_number": 1287, "page_indices": { "start_index": 2554091, "end_index": 2555545 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1287 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS interrupt mask register (OTG_FS_GINTMSK)", 1286 ] ], "page_content": "RM0090 Rev 21\n1287/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nBits 23:22 Reserved, must be kept at reset value.\nBit 21 IPXFRM: Incomplete periodic transfer mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in host mode.\nIISOOXFRM: Incomplete isochronous OUT transfer mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 20 IISOIXFRM: Incomplete isochronous IN transfer mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 19 OEPINT: OUT endpoints interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 18 IEPINT: IN endpoints interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBits 17:16 Reserved, must be kept at reset value.\nBit 15 EOPFM: End of periodic frame interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 14 ISOODRPM: Isochronous OUT packet dropped interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 13 ENUMDNEM: Enumeration done mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 12 USBRST: USB reset mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 11 USBSUSPM: USB suspend mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\n" }, { "page_number": 1288, "page_indices": { "start_index": 2555545, "end_index": 2556740 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1288 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS interrupt mask register (OTG_FS_GINTMSK)", 1286 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1288/1757\nRM0090 Rev 21\nBit 10 ESUSPM: Early suspend mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBits 9:8 Reserved, must be kept at reset value.\nBit 7 GONAKEFFM: Global OUT NAK effective mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 6 GINAKEFFM: Global non-periodic IN NAK effective mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in device mode.\nBit 5 NPTXFEM: Non-periodic TxFIFO empty mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in Host mode.\nBit 4 RXFLVLM: Receive FIFO non-empty mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both device and host modes.\nBit 3 SOFM: Start of frame mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both device and host modes.\nBit 2 OTGINT: OTG interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both device and host modes.\nBit 1 MMISM: Mode mismatch interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both device and host modes.\nBit 0 Reserved, must be kept at reset value.\n" }, { "page_number": 1289, "page_indices": { "start_index": 2556740, "end_index": 2558374 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1289 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS Receive status debug read/OTG status read and pop registers (OTG_FS_GRXSTSR/OTG_FS_GRXSTSP)", 1289 ] ], "page_content": "RM0090 Rev 21\n1289/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS Receive status debug read/OTG status read and pop registers \n(OTG_FS_GRXSTSR/OTG_FS_GRXSTSP)\nAddress offset for Read: 0x01C\nAddress offset for Pop: 0x020\nReset value: 0x0000 0000\nA read to the Receive status debug read register returns the contents of the top of the \nReceive FIFO. A read to the Receive status read and pop register additionally pops the top \ndata entry out of the RxFIFO.\nThe receive status contents must be interpreted differently in host and device modes. The \ncore ignores the receive status pop/read when the receive FIFO is empty and returns a \nvalue of 0x0000 0000. The application must only pop the Receive Status FIFO when the \nReceive FIFO non-empty bit of the Core interrupt register (RXFLVL bit in \nOTG_FS_GINTSTS) is asserted.\nHost mode\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPKTSTS\nDPID\nBCNT\nCHNUM\nr\nr\nr\nr\nBits 31:21 Reserved, must be kept at reset value.\nBits 20:17 PKTSTS: Packet status\nIndicates the status of the received packet\n0010: IN data packet received\n0011: IN transfer completed (triggers an interrupt)\n0101: Data toggle error (triggers an interrupt)\n0111: Channel halted (triggers an interrupt)\nOthers: Reserved\nBits 16:15 DPID: Data PID\nIndicates the Data PID of the received packet\n00: DATA0\n10: DATA1\n01: DATA2\n11: MDATA\nBits 14:4 BCNT: Byte count\nIndicates the byte count of the received IN data packet.\nBits 3:0 CHNUM: Channel number\nIndicates the channel number to which the current received packet belongs.\n" }, { "page_number": 1290, "page_indices": { "start_index": 2558374, "end_index": 2560062 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1290 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)", 1290 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1290/1757\nRM0090 Rev 21\nDevice mode\n \n \nOTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)\nAddress offset: 0x024\nReset value: 0x0000 0200\nThe application can program the RAM size that must be allocated to the RxFIFO.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFRMNUM\nPKTSTS\nDPID\nBCNT\nEPNUM\nr\nr\nr\nr\nr\nBits 31:25 Reserved, must be kept at reset value.\nBits 24:21 FRMNUM: Frame number\nThis is the least significant 4 bits of the frame number in which the packet is received on the \nUSB. This field is supported only when isochronous OUT endpoints are supported.\nBits 20:17 PKTSTS: Packet status\nIndicates the status of the received packet\n0001: Global OUT NAK (triggers an interrupt)\n0010: OUT data packet received\n0011: OUT transfer completed (triggers an interrupt)\n0100: SETUP transaction completed (triggers an interrupt)\n0110: SETUP data packet received\nOthers: Reserved\nBits 16:15 DPID: Data PID\nIndicates the Data PID of the received OUT data packet\n00: DATA0\n10: DATA1\n01: DATA2\n11: MDATA\nBits 14:4 BCNT: Byte count\nIndicates the byte count of the received data packet.\nBits 3:0 EPNUM: Endpoint number\nIndicates the endpoint number to which the current received packet belongs.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRXFD\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 RXFD: RxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nMaximum value is 256\nThe power-on reset value of this register is specified as the largest Rx data FIFO depth.\n" }, { "page_number": 1291, "page_indices": { "start_index": 2560062, "end_index": 2561467 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1291 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS Host non-periodic transmit FIFO size register (OTG_FS_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_FS_DIEPTXF0)", 1291 ], [ 4, "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_HNPTXSTS)", 1291 ] ], "page_content": "RM0090 Rev 21\n1291/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS Host non-periodic transmit FIFO size register \n(OTG_FS_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_FS_DIEPTXF0)\nAddress offset: 0x028\nReset value: 0x0000 0200\n \nHost mode\n \nDevice mode\n \nOTG_FS non-periodic transmit FIFO/queue status register \n(OTG_FS_HNPTXSTS)\nAddress offset: 0x02C\nReset value: 0x0008 0200\nNote:\nIn Device mode, this register is not valid.\nThis read-only register contains the free space information for the non-periodic TxFIFO and \nthe non-periodic transmit request queue.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nNPTXFD/TX0FD\nNPTXFSA/TX0FSA\nrw\nrw\nBits 31:16 NPTXFD: Non-periodic TxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nMaximum value is 256\nBits 15:0 NPTXFSA: Non-periodic transmit RAM start address\nThis field contains the memory start address for non-periodic transmit FIFO RAM.\nBits 31:16 TX0FD: Endpoint 0 TxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nMaximum value is 256\nBits 15:0 TX0FSA: Endpoint 0 transmit RAM start address\nThis field contains the memory start address for the endpoint 0 transmit FIFO RAM.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNPTXQTOP\nNPTQXSAV\nNPTXFSAV\nr\nr\nr\n" }, { "page_number": 1292, "page_indices": { "start_index": 2561467, "end_index": 2562977 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1292 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS general core configuration register (OTG_FS_GCCFG)", 1292 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1292/1757\nRM0090 Rev 21\n \nOTG_FS general core configuration register (OTG_FS_GCCFG)\nAddress offset: 0x038\nReset value: 0x0000 XXXX\n \nBit 31 Reserved, must be kept at reset value.\nBits 30:24 NPTXQTOP: Top of the non-periodic transmit request queue\nEntry in the non-periodic Tx request queue that is currently being processed by the MAC.\nBits 30:27: Channel/endpoint number\nBits 26:25:\n–\n00: IN/OUT token\n–\n01: Zero-length transmit packet (device IN/host OUT)\n–\n11: Channel halt command\nBit 24: Terminate (last entry for selected channel/endpoint)\nBits 23:16 NPTQXSAV: Non-periodic transmit request queue space available\nIndicates the amount of free space available in the non-periodic transmit request queue. \nThis queue holds both IN and OUT requests in host mode. Device mode has only IN \nrequests.\n00: Non-periodic transmit request queue is full\n01: 1 location available\n10: 2 locations available\nbxn: n locations available (0 ≤ n ≤ 8)\nOthers: Reserved\nBits 15:0 NPTXFSAV: Non-periodic TxFIFO space available\nIndicates the amount of free space available in the non-periodic TxFIFO.\nValues are in terms of 32-bit words.\n00: Non-periodic TxFIFO is full\n01: 1 word available\n10: 2 words available\n0xn: n words available (where 0 ≤ n ≤ 256)\nOthers: Reserved\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNOVBUSSENS\nSOFOUTEN\nVBUSBSEN\nVBUSASEN\nReserved\n.PWRDWN\nReserved\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1293, "page_indices": { "start_index": 2562977, "end_index": 2564690 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1293 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS core ID register (OTG_FS_CID)", 1293 ] ], "page_content": "RM0090 Rev 21\n1293/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n \nOTG_FS core ID register (OTG_FS_CID)\nAddress offset: 0x03C\nReset value:0x0000 1200\nThis is a register containing the Product ID as reset value.\n \n \nBits 31:22 Reserved, must be kept at reset value.\nBit 21 NOVBUSSENS: VBUS sensing disable option\nWhen this bit is set, VBUS is considered internally to be always at VBUS valid level (5 V). This \noption removes the need for a dedicated VBUS pad, and leave this pad free to be used for \nother purposes such as a shared functionality. VBUS connection can be remapped on \nanother general purpose input pad and monitored by software. \nThis option is only suitable for host-only or device-only applications. \n0: VBUS sensing available by hardware \n1: VBUS sensing not available by hardware. \nBit 20 SOFOUTEN: SOF output enable\n0: SOF pulse not available on PAD (OTG_FS_SOF)\n1: SOF pulse available on PAD (OTG_FS_SOF)\nBit 19 VBUSBSEN: Enable the VBUS sensing “B” device\n0: VBUS sensing “B” disabled\n1: VBUS sensing “B” enabled\nBit 18 VBUSASEN: Enable the VBUS sensing “A” device\n0: VBUS sensing “A” disabled\n1: VBUS sensing “A” enabled\nBit 17 Reserved, must be kept at reset value.\nBit 16 PWRDWN: Power down\nUsed to activate the transceiver in transmission/reception\n0: Power down active\n1: Power down deactivated (“Transceiver active”)\nBits 15:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPRODUCT_ID\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 PRODUCT_ID: Product ID field\nApplication-programmable ID field.\n" }, { "page_number": 1294, "page_indices": { "start_index": 2564690, "end_index": 2566140 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1294 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.2 OTG_FS global registers", 1274 ], [ 4, "OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)", 1294 ], [ 4, "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXFx) (x = 1..3, where x is the FIFO_number)", 1294 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1294/1757\nRM0090 Rev 21\nOTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)\nAddress offset: 0x100\nReset value: 0x0200 0400\n \n \nOTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXFx) \n(x = 1..3, where x is the FIFO_number)\nAddress offset: 0x104 + 0x04 * (x -1)\nReset value: 0x0200 0200\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPTXFSIZ\nPTXSA\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 PTXFD: Host periodic TxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nBits 15:0 PTXSA: Host periodic TxFIFO start address\nThe power-on reset value of this register is the sum of the largest Rx data FIFO depth and \nlargest non-periodic Tx data FIFO depth.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nINEPTXFD\nINEPTXSA\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 INEPTXFD: IN endpoint TxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nThe power-on reset value of this register is specified as the largest IN endpoint FIFO \nnumber depth.\nBits 15:0 INEPTXSA: IN endpoint FIFOx transmit RAM start address\nThis field contains the memory start address for IN endpoint transmit FIFOx. The address \nmust be aligned with a 32-bit memory location. \n" }, { "page_number": 1295, "page_indices": { "start_index": 2566140, "end_index": 2568134 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1295 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.3 Host-mode registers", 1295 ], [ 4, "OTG_FS Host configuration register (OTG_FS_HCFG)", 1295 ], [ 4, "OTG_FS Host frame interval register (OTG_FS_HFIR)", 1295 ] ], "page_content": "RM0090 Rev 21\n1295/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34.16.3 \nHost-mode registers\nBit values in the register descriptions are expressed in binary unless otherwise specified.\nHost-mode registers affect the operation of the core in the host mode. Host mode registers \nmust not be accessed in device mode, as the results are undefined. Host mode registers \ncan be categorized as follows:\nOTG_FS Host configuration register (OTG_FS_HCFG)\nAddress offset: 0x400\nReset value: 0x0000 0000\nThis register configures the core after power-on. Do not make changes to this register after \ninitializing the host.\n \n \nOTG_FS Host frame interval register (OTG_FS_HFIR)\nAddress offset: 0x404\nReset value: 0x0000 EA60\nThis register stores the frame interval information for the current speed to which the \nOTG_FS controller has enumerated.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFSLSS\nFSLSPCS\nr\nrw\nrw\nBits 31:3 Reserved, must be kept at reset value.\nBit 2 FSLSS: FS- and LS-only support\nThe application uses this bit to control the core’s enumeration speed. Using this bit, the \napplication can make the core enumerate as an FS host, even if the connected device \nsupports HS traffic. Do not make changes to this field after initial programming.\n1: FS/LS-only, even if the connected device can support HS (read-only)\nBits 1:0 FSLSPCS: FS/LS PHY clock select\nWhen the core is in FS host mode\n01: PHY clock is running at 48 MHz\nOthers: Reserved\nWhen the core is in LS host mode\n00: Reserved\n01: Select 48 MHz PHY clock frequency \n10: Select 6 MHz PHY clock frequency \n11: Reserved\nNote: The FSLSPCS must be set on a connection event according to the speed of the \nconnected device (after changing this bit, a software reset must be performed).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFRIVL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1296, "page_indices": { "start_index": 2568134, "end_index": 2570331 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1296 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.3 Host-mode registers", 1295 ], [ 4, "OTG_FS Host frame number/frame time remaining register (OTG_FS_HFNUM)", 1296 ], [ 4, "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)", 1296 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1296/1757\nRM0090 Rev 21\n \nOTG_FS Host frame number/frame time remaining register (OTG_FS_HFNUM)\nAddress offset: 0x408\nReset value: 0x0000 3FFF\nThis register indicates the current frame number. It also indicates the time remaining (in \nterms of the number of PHY clocks) in the current frame.\n \n \nOTG_FS_Host periodic transmit FIFO/queue status register \n(OTG_FS_HPTXSTS)\nAddress offset: 0x410\nReset value: 0x0008 0100\nThis read-only register contains the free space information for the periodic TxFIFO and the \nperiodic transmit request queue.\n \nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 FRIVL: Frame interval\nThe value that the application programs to this field specifies the interval between two \nconsecutive SOFs (FS) or Keep-Alive tokens (LS). This field contains the number of PHY \nclocks that constitute the required frame interval. The application can write a value to this \nregister only after the Port enable bit of the host port control and status register (PENA bit in \nOTG_FS_HPRT) has been set. If no value is programmed, the core calculates the value \nbased on the PHY clock specified in the FS/LS PHY Clock Select field of the host \nconfiguration register (FSLSPCS in OTG_FS_HCFG). Do not change the value of this field \nafter the initial configuration.\n– Frame interval = 1 ms × (FRIVL - 1)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFTREM\nFRNUM\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 FTREM: Frame time remaining\nIndicates the amount of time remaining in the current frame, in terms of PHY clocks. This \nfield decrements on each PHY clock. When it reaches zero, this field is reloaded with the \nvalue in the Frame interval register and a new SOF is transmitted on the USB.\nBits 15:0 FRNUM: Frame number\nThis field increments when a new SOF is transmitted on the USB, and is cleared to 0 when \nit reaches 0x3FFF.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPTXQTOP\nPTXQSAV\nPTXFSAVL\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n" }, { "page_number": 1297, "page_indices": { "start_index": 2570331, "end_index": 2572453 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1297 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.3 Host-mode registers", 1295 ], [ 4, "OTG_FS Host all channels interrupt register (OTG_FS_HAINT)", 1297 ] ], "page_content": "RM0090 Rev 21\n1297/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n \nOTG_FS Host all channels interrupt register (OTG_FS_HAINT)\nAddress offset: 0x414\nReset value: 0x0000 000\nWhen a significant event occurs on a channel, the host all channels interrupt register \ninterrupts the application using the host channels interrupt bit of the Core interrupt register \n(HCINT bit in OTG_FS_GINTSTS). This is shown in Figure 394. There is one interrupt bit \nper channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the \napplication sets and clears bits in the corresponding host channel-x interrupt register.\n \n \nBits 31:24 PTXQTOP: Top of the periodic transmit request queue\nThis indicates the entry in the periodic Tx request queue that is currently being processed by \nthe MAC.\nThis register is used for debugging.\nBit 31: Odd/Even frame\n–\n0: send in even frame\n–\n1: send in odd frame\nBits 30:27: Channel/endpoint number\nBits 26:25: Type\n–\n00: IN/OUT\n–\n01: Zero-length packet\n–\n11: Disable channel command\nBit 24: Terminate (last entry for the selected channel/endpoint)\nBits 23:16 PTXQSAV: Periodic transmit request queue space available\nIndicates the number of free locations available to be written in the periodic transmit request \nqueue. This queue holds both IN and OUT requests.\n00: Periodic transmit request queue is full\n01: 1 location available\n10: 2 locations available\nbxn: n locations available (0 ≤ n ≤ 8)\nOthers: Reserved\nBits 15:0 PTXFSAVL: Periodic transmit data FIFO space available\nIndicates the number of free locations available to be written to in the periodic TxFIFO.\nValues are in terms of 32-bit words\n0000: Periodic TxFIFO is full\n0001: 1 word available\n0010: 2 words available\nbxn: n words available (where 0 ≤ n ≤ PTXFD)\nOthers: Reserved\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nHAINT\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 HAINT: Channel interrupts\nOne bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15\n" }, { "page_number": 1298, "page_indices": { "start_index": 2572453, "end_index": 2574440 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1298 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.3 Host-mode registers", 1295 ], [ 4, "OTG_FS Host all channels interrupt mask register (OTG_FS_HAINTMSK)", 1298 ], [ 4, "OTG_FS Host port control and status register (OTG_FS_HPRT)", 1298 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1298/1757\nRM0090 Rev 21\nOTG_FS Host all channels interrupt mask register (OTG_FS_HAINTMSK)\nAddress offset: 0x418\nReset value: 0x0000 0000\nThe host all channel interrupt mask register works with the host all channel interrupt register \nto interrupt the application when an event occurs on a channel. There is one interrupt mask \nbit per channel, up to a maximum of 16 bits.\n \n \nOTG_FS Host port control and status register (OTG_FS_HPRT)\nAddress offset: 0x440\nReset value: 0x0000 0000\nThis register is available only in host mode. Currently, the OTG host supports only one port.\nA single register holds USB port-related information such as USB reset, enable, suspend, \nresume, connect status, and test mode for each port. It is shown in Figure 394. The rc_w1 \nbits in this register can trigger an interrupt to the application through the host port interrupt \nbit of the core interrupt register (HPRTINT bit in OTG_FS_GINTSTS). On a Port Interrupt, \nthe application must read this register and clear the bit that caused the interrupt. For the \nrc_w1 bits, the application must write a 1 to the bit to clear the interrupt.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nHAINTM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 HAINTM: Channel interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nOne bit per channel: Bit 0 for channel 0, bit 15 for channel 15\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPSPD\nPTCTL\nPPWR\nPLSTS\nReserved\nPRST\nPSUSP\nPRES\nPOCCHNG\nPOCA\nPENCHNG\nPENA\nPCDET\nPCSTS\nr\nr\nrw\nrw\nrw\nrw\nrw\nr\nr\nrw\nrs\nrw\nrc_\nw1\nr\nrc_\nw1\nrc_\nw0\nrc_\nw1\nr\nBits 31:19 Reserved, must be kept at reset value.\nBits 18:17 PSPD: Port speed\nIndicates the speed of the device attached to this port.\n01: Full speed\n10: Low speed\n11: Reserved\n" }, { "page_number": 1299, "page_indices": { "start_index": 2574440, "end_index": 2577119 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1299 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.3 Host-mode registers", 1295 ], [ 4, "OTG_FS Host port control and status register (OTG_FS_HPRT)", 1298 ] ], "page_content": "RM0090 Rev 21\n1299/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nBits 16:13 PTCTL: Port test control\nThe application writes a nonzero value to this field to put the port into a Test mode, and the \ncorresponding pattern is signaled on the port.\n0000: Test mode disabled\n0001: Test_J mode\n0010: Test_K mode\n0011: Test_SE0_NAK mode\n0100: Test_Packet mode\n0101: Test_Force_Enable\nOthers: Reserved\nBit 12 PPWR: Port power\nThe application uses this field to control power to this port, and the core clears this bit on an \novercurrent condition.\n0: Power off\n1: Power on\nBits 11:10 PLSTS: Port line status\nIndicates the current logic level USB data lines\nBit 10: Logic level of OTG_FS_DP\nBit 11: Logic level of OTG_FS_DM\nBit 9 Reserved, must be kept at reset value.\nBit 8 PRST: Port reset\nWhen the application sets this bit, a reset sequence is started on this port. The application \nmust time the reset period and clear this bit after the reset sequence is complete.\n0: Port not in reset\n1: Port in reset\nThe application must leave this bit set for a minimum duration of at least 10 ms to start a \nreset on the port. The application can leave it set for another 10 ms in addition to the \nrequired minimum duration, before clearing the bit, even though there is no maximum limit \nset by the USB standard.\nBit 7 PSUSP: Port suspend\nThe application sets this bit to put this port in Suspend mode. The core only stops sending \nSOFs when this is set. To stop the PHY clock, the application must set the Port clock stop \nbit, which asserts the suspend input pin of the PHY.\nThe read value of this bit reflects the current suspend status of the port. This bit is cleared \nby the core after a remote wake-up signal is detected or the application sets the Port reset \nbit or Port resume bit in this register or the Resume/remote wake-up detected interrupt bit or \nDisconnect detected interrupt bit in the Core interrupt register (WKUINT or DISCINT in \nOTG_FS_GINTSTS, respectively).\n0: Port not in Suspend mode\n1: Port in Suspend mode\nBit 6 PRES: Port resume\nThe application sets this bit to drive resume signaling on the port. The core continues to \ndrive the resume signal until the application clears this bit.\nIf the core detects a USB remote wake-up sequence, as indicated by the Port \nresume/remote wake-up detected interrupt bit of the Core interrupt register (WKUINT bit in \nOTG_FS_GINTSTS), the core starts driving resume signaling without application \nintervention and clears this bit when it detects a disconnect condition. The read value of this \nbit indicates whether the core is currently driving resume signaling.\n0: No resume driven\n1: Resume driven\n" }, { "page_number": 1300, "page_indices": { "start_index": 2577119, "end_index": 2578424 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1300 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.3 Host-mode registers", 1295 ], [ 4, "OTG_FS Host port control and status register (OTG_FS_HPRT)", 1298 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1300/1757\nRM0090 Rev 21\nBit 5 POCCHNG: Port overcurrent change\nThe core sets this bit when the status of the Port overcurrent active bit (bit 4) in this register \nchanges.\nBit 4 POCA: Port overcurrent active\nIndicates the overcurrent condition of the port.\n0: No overcurrent condition\n1: Overcurrent condition\nBit 3 PENCHNG: Port enable/disable change\nThe core sets this bit when the status of the Port enable bit 2 in this register changes.\nBit 2 PENA: Port enable\nA port is enabled only by the core after a reset sequence, and is disabled by an overcurrent \ncondition, a disconnect condition, or by the application clearing this bit. The application \ncannot set this bit by a register write. It can only clear it to disable the port. This bit does not \ntrigger any interrupt to the application.\n0: Port disabled\n1: Port enabled\nBit 1 PCDET: Port connect detected\nThe core sets this bit when a device connection is detected to trigger an interrupt to the \napplication using the host port interrupt bit in the Core interrupt register (HPRTINT bit in \nOTG_FS_GINTSTS). The application must write a 1 to this bit to clear the interrupt.\nBit 0 PCSTS: Port connect status\n0: No device is attached to the port\n1: A device is attached to the port\n" }, { "page_number": 1301, "page_indices": { "start_index": 2578424, "end_index": 2580446 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1301 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.3 Host-mode registers", 1295 ], [ 4, "OTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx) (x = 0..7, where x = Channel_number)", 1301 ] ], "page_content": "RM0090 Rev 21\n1301/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx) \n(x = 0..7, where x = Channel_number)\nAddress offset: 0x500 + 0x20 * x\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nrs\nrs\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 CHENA: Channel enable\nThis field is set by the application and cleared by the OTG host.\n0: Channel disabled\n1: Channel enabled\nBit 30 CHDIS: Channel disable\nThe application sets this bit to stop transmitting/receiving data on a channel, even before \nthe transfer for that channel is complete. The application must wait for the Channel disabled \ninterrupt before treating the channel as disabled.\nBit 29 ODDFRM: Odd frame\nThis field is set (reset) by the application to indicate that the OTG host must perform a \ntransfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) \ntransactions.\n0: Even frame\n1: Odd frame\nBits 28:22 DAD: Device address\nThis field selects the specific device serving as the data source or sink.\nBits 21:20 MCNT: Multicount\nThis field indicates to the host the number of transactions that must be executed per frame \nfor this periodic endpoint. For non-periodic transfers, this field is not used\n00: Reserved. This field yields undefined results\n01: 1 transaction\n10: 2 transactions per frame to be issued for this endpoint\n11: 3 transactions per frame to be issued for this endpoint\nNote: This field must be set to at least 01.\nBits 19:18 EPTYP: Endpoint type\nIndicates the transfer type selected.\n00: Control\n01: Isochronous\n10: Bulk\n11: Interrupt\nBit 17 LSDEV: Low-speed device\nThis field is set by the application to indicate that this channel is communicating to a low-\nspeed device.\nBit 16 Reserved, must be kept at reset value.\n" }, { "page_number": 1302, "page_indices": { "start_index": 2580446, "end_index": 2582319 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1302 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.3 Host-mode registers", 1295 ], [ 4, "OTG_FS Host channel-x interrupt register (OTG_FS_HCINTx) (x = 0..7, where x = Channel_number)", 1302 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1302/1757\nRM0090 Rev 21\nOTG_FS Host channel-x interrupt register (OTG_FS_HCINTx) (x = 0..7, where \nx = Channel_number)\nAddress offset: 0x508 + 0x20 * x\nReset value: 0x0000 0000\nThis register indicates the status of a channel with respect to USB- and AHB-related events. \nIt is shown in Figure 394. The application must read this register when the host channels \ninterrupt bit in the Core interrupt register (HCINT bit in OTG_FS_GINTSTS) is set. Before \nthe application can read this register, it must first read the host all channels interrupt \n(OTG_FS_HAINT) register to get the exact channel number for the host channel-x interrupt \nregister. The application must clear the appropriate bit in this register to clear the \ncorresponding bits in the OTG_FS_HAINT and OTG_FS_GINTSTS registers.\n \n \nBit 15 EPDIR: Endpoint direction\nIndicates whether the transaction is IN or OUT.\n0: OUT\n1: IN\nBits 14:11 EPNUM: Endpoint number\nIndicates the endpoint number on the device serving as the data source or sink.\nBits 10:0 MPSIZ: Maximum packet size\nIndicates the maximum packet size of the associated endpoint.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nBits 31:11 Reserved, must be kept at reset value.\nBit 10 DTERR: Data toggle error\nBit 9 FRMOR: Frame overrun\nBit 8 BBERR: Babble error\nBit 7 TXERR: Transaction error\nIndicates one of the following errors occurred on the USB.\nCRC check failure\nTimeout\nBit stuff error\nFalse EOP\nBit 6 Reserved, must be kept at reset value.\nBit 5 ACK: ACK response received/transmitted interrupt\nBit 4 NAK: NAK response received interrupt\nBit 3 STALL: STALL response received interrupt\n" }, { "page_number": 1303, "page_indices": { "start_index": 2582319, "end_index": 2583865 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1303 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.3 Host-mode registers", 1295 ], [ 4, "OTG_FS Host channel-x interrupt mask register (OTG_FS_HCINTMSKx) (x = 0..7, where x = Channel_number)", 1303 ] ], "page_content": "RM0090 Rev 21\n1303/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS Host channel-x interrupt mask register (OTG_FS_HCINTMSKx) \n(x = 0..7, where x = Channel_number)\nAddress offset: 0x50C + 0x20 * x\nReset value: 0x0000 0000\nThis register reflects the mask for each channel status described in the previous section.\n \n \nBit 2 Reserved, must be kept at reset value.\nBit 1 CHH: Channel halted\nIndicates the transfer completed abnormally either because of any USB transaction error or \nin response to disable request by the application.\nBit 0 XFRC: Transfer completed\nTransfer completed normally without any errors.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:11 Reserved, must be kept at reset value.\nBit 10 DTERRM: Data toggle error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 9 FRMORM: Frame overrun mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 8 BBERRM: Babble error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 7 TXERRM: Transaction error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 6 Reserved, must be kept at reset value.\nBit 5 ACKM: ACK response received/transmitted interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 4 NAKM: NAK response received interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 3 STALLM: STALL response received interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\n" }, { "page_number": 1304, "page_indices": { "start_index": 2583865, "end_index": 2585545 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1304 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.3 Host-mode registers", 1295 ], [ 4, "OTG_FS Host channel-x transfer size register (OTG_FS_HCTSIZx) (x = 0..7, where x = Channel_number)", 1304 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1304/1757\nRM0090 Rev 21\nOTG_FS Host channel-x transfer size register (OTG_FS_HCTSIZx) (x = 0..7, \nwhere x = Channel_number)\nAddress offset: 0x510 + 0x20 * x\nReset value: 0x0000 0000\n \n \nBit 2 Reserved, must be kept at reset value.\nBit 1 CHHM: Channel halted mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 0 XFRCM: Transfer completed mask\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDPID\nPKTCNT\nXFRSIZ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBits 30:29 DPID: Data PID\nThe application programs this field with the type of PID to use for the initial transaction. The \nhost maintains this field for the rest of the transfer.\n00: DATA0\n01: DATA2\n10: DATA1\n11: MDATA (non-control)/SETUP (control)\nBits 28:19 PKTCNT: Packet count\nThis field is programmed by the application with the expected number of packets to be \ntransmitted (OUT) or received (IN).\nThe host decrements this count on every successful transmission or reception of an OUT/IN \npacket. Once this count reaches zero, the application is interrupted to indicate normal \ncompletion.\nBits 18:0 XFRSIZ: Transfer size\nFor an OUT, this field is the number of data bytes the host sends during the transfer.\nFor an IN, this field is the buffer size that the application has reserved for the transfer. The \napplication is expected to program this field as an integer multiple of the maximum packet \nsize for IN transactions (periodic and non-periodic).\n" }, { "page_number": 1305, "page_indices": { "start_index": 2585545, "end_index": 2587677 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1305 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device configuration register (OTG_FS_DCFG)", 1305 ] ], "page_content": "RM0090 Rev 21\n1305/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34.16.4 \nDevice-mode registers\nOTG_FS device configuration register (OTG_FS_DCFG)\nAddress offset: 0x800\nReset value: 0x0220 0000\nThis register configures the core in device mode after power-on or after certain control \ncommands or enumeration. Do not make changes to this register after initial programming.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPFIVL\nDAD\nReserved\nNZLSOHSK\nDSPD\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:13 Reserved, must be kept at reset value.\nBits 12:11 PFIVL: Periodic frame interval\nIndicates the time within a frame at which the application must be notified using the end of \nperiodic frame interrupt. This can be used to determine if all the isochronous traffic for that \nframe is complete.\n00: 80% of the frame interval\n01: 85% of the frame interval\n10: 90% of the frame interval\n11: 95% of the frame interval\nBits 10:4 DAD: Device address\nThe application must program this field after every SetAddress control command.\nBit 3 Reserved, must be kept at reset value.\nBit 2 NZLSOHSK: Non-zero-length status OUT handshake\nThe application can use this field to select the handshake the core sends on receiving a \nnonzero-length data packet during the OUT transaction of a control transfer’s Status stage.\n1: Send a STALL handshake on a nonzero-length status OUT transaction and do not send \nthe received OUT packet to the application.\n0: Send the received OUT packet to the application (zero-length or nonzero-length) and \nsend a handshake based on the NAK and STALL bits for the endpoint in the Device \nendpoint control register.\nBits 1:0 DSPD: Device speed\nIndicates the speed at which the application requires the core to enumerate, or the \nmaximum speed the application can support. However, the actual bus speed is determined \nonly after the chirp sequence is completed, and is based on the speed of the USB host to \nwhich the core is connected.\n00: Reserved\n01: Reserved\n10: Reserved\n11: Full speed (USB 1.1 transceiver clock is 48 MHz)\n" }, { "page_number": 1306, "page_indices": { "start_index": 2587677, "end_index": 2589616 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1306 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device control register (OTG_FS_DCTL)", 1306 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1306/1757\nRM0090 Rev 21\nOTG_FS device control register (OTG_FS_DCTL)\nAddress offset: 0x804\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPOPRGDNE\nCGONAK\nSGONAK\nCGINAK\nSGINAK\nTCTL\nGONSTS\nGINSTS\nSDIS\nRWUSIG\nrw\nw\nw\nw\nw\nrw\nrw\nrw\nr\nr\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBit 11 POPRGDNE: Power-on programming done\nThe application uses this bit to indicate that register programming is completed after a \nwake-up from power down mode.\nBit 10 CGONAK: Clear global OUT NAK\nWriting 1 to this field clears the Global OUT NAK.\nBit 9 SGONAK: Set global OUT NAK\nWriting 1 to this field sets the Global OUT NAK.\nThe application uses this bit to send a NAK handshake on all OUT endpoints.\nThe application must set the this bit only after making sure that the Global OUT NAK \neffective bit in the Core interrupt register (GONAKEFF bit in OTG_FS_GINTSTS) is cleared.\nBit 8 CGINAK: Clear global IN NAK\nWriting 1 to this field clears the Global IN NAK.\nBit 7 SGINAK: Set global IN NAK\nWriting 1 to this field sets the Global non-periodic IN NAK. The application uses this bit to \nsend a NAK handshake on all non-periodic IN endpoints.\nThe application must set this bit only after making sure that the Global IN NAK effective bit \nin the Core interrupt register (GINAKEFF bit in OTG_FS_GINTSTS) is cleared.\nBits 6:4 TCTL: Test control\n000: Test mode disabled\n001: Test_J mode\n010: Test_K mode\n011: Test_SE0_NAK mode\n100: Test_Packet mode\n101: Test_Force_Enable\nOthers: Reserved\nBit 3 GONSTS: Global OUT NAK status\n0: A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.\n1: No data is written to the RxFIFO, irrespective of space availability. Sends a NAK \nhandshake on all packets, except on SETUP transactions. All isochronous OUT packets are \ndropped.\n" }, { "page_number": 1307, "page_indices": { "start_index": 2589616, "end_index": 2592003 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1307 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device status register (OTG_FS_DSTS)", 1307 ] ], "page_content": "RM0090 Rev 21\n1307/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nTable 205 contains the minimum duration (according to device state) for which the Soft \ndisconnect (SDIS) bit must be set for the USB host to detect a device disconnect. To \naccommodate clock jitter, it is recommended that the application add some extra delay to \nthe specified minimum duration.\n \nOTG_FS device status register (OTG_FS_DSTS)\nAddress offset: 0x808\nReset value: 0x0000 0010\nThis register indicates the status of the core with respect to USB-related events. It must be \nread on interrupts from the device all interrupts (OTG_FS_DAINT) register.\n \n \nBit 2 GINSTS: Global IN NAK status\n0: A handshake is sent out based on the data availability in the transmit FIFO.\n1: A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data \navailability in the transmit FIFO.\nBit 1 SDIS: Soft disconnect\nThe application uses this bit to signal the USB OTG core to perform a soft disconnect. As \nlong as this bit is set, the host does not see that the device is connected, and the device \ndoes not receive signals on the USB. The core stays in the disconnected state until the \napplication clears this bit.\n0: Normal operation. When this bit is cleared after a soft disconnect, the core generates a \ndevice connect event to the USB host. When the device is reconnected, the USB host \nrestarts device enumeration.\n1: The core generates a device disconnect event to the USB host.\nBit 0 RWUSIG: Remote wake-up signaling\nWhen the application sets this bit, the core initiates remote signaling to wake up the USB \nhost. The application must set this bit to instruct the core to exit the Suspend state. As \nspecified in the USB 2.0 specification, the application must clear this bit 1 ms to 15 ms after \nsetting it.\nTable 205. Minimum duration for soft disconnect\nOperating speed\nDevice state\nMinimum duration\nFull speed\nSuspended\n1 ms + 2.5 µs\nFull speed\nIdle\n2.5 µs\nFull speed\nNot Idle or Suspended (Performing transactions)\n2.5 µs\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFNSOF\nReserved\nEERR\nENUMSPD\nSUSPSTS\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:22 Reserved, must be kept at reset value.\nBits 21:8 FNSOF: Frame number of the received SOF\nBits 7:4 Reserved, must be kept at reset value.\n" }, { "page_number": 1308, "page_indices": { "start_index": 2592003, "end_index": 2594060 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1308 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)", 1308 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1308/1757\nRM0090 Rev 21\nOTG_FS device IN endpoint common interrupt mask register \n(OTG_FS_DIEPMSK)\nAddress offset: 0x810\nReset value: 0x0000 0000\nThis register works with each of the OTG_FS_DIEPINTx registers for all endpoints to \ngenerate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the \nOTG_FS_DIEPINTx register can be masked by writing to the corresponding bit in this \nregister. Status bits are masked by default.\n \n \nBit 3 EERR: Erratic error\nThe core sets this bit to report any erratic errors.\nDue to erratic errors, the OTG_FS controller goes into Suspended state and an interrupt is \ngenerated to the application with Early suspend bit of the OTG_FS_GINTSTS register \n(ESUSP bit in OTG_FS_GINTSTS). If the early suspend is asserted due to an erratic error, \nthe application can only perform a soft disconnect recover.\nBits 2:1 ENUMSPD: Enumerated speed\nIndicates the speed at which the OTG_FS controller has come up after speed detection \nthrough a chirp sequence.\n01: Reserved\n10: Reserved\n11: Full speed (PHY clock is running at 48 MHz)\nOthers: reserved\nBit 0 SUSPSTS: Suspend status\nIn device mode, this bit is set as long as a Suspend condition is detected on the USB. The \ncore enters the Suspended state when there is no activity on the USB data lines for a period \nof 3 ms. The core comes out of the suspend:\n– When there is an activity on the USB data lines\n– When the application writes to the Remote wake-up signaling bit in the OTG_FS_DCTL \nregister (RWUSIG bit in OTG_FS_DCTL).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNAKM\nReserved\nINEPNEM\nINEPNMM\nITTXFEMSK\nTOM\nReserved\nEPDM\nXFRCM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:14 Reserved, must be kept at reset value.\nBit 13 NAKM: NAK interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBits 12:7 Reserved, must be kept at reset value.\nBit 6 INEPNEM: IN endpoint NAK effective mask\n0: Masked interrupt\n1: Unmasked interrupt\n" }, { "page_number": 1309, "page_indices": { "start_index": 2594060, "end_index": 2595664 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1309 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)", 1309 ] ], "page_content": "RM0090 Rev 21\n1309/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS device OUT endpoint common interrupt mask register \n(OTG_FS_DOEPMSK)\nAddress offset: 0x814\nReset value: 0x0000 0000\nThis register works with each of the OTG_FS_DOEPINTx registers for all endpoints to \ngenerate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in \nthe OTG_FS_DOEPINTx register can be masked by writing into the corresponding bit in this \nregister. Status bits are masked by default.\n \nBit 5 INEPNMM: IN token received with EP mismatch mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 4 ITTXFEMSK: IN token received when TxFIFO empty mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 3 TOM: Timeout condition mask (Non-isochronous endpoints)\n0: Masked interrupt\n1: Unmasked interrupt\nBit 2 Reserved, must be kept at reset value.\nBit 1 EPDM: Endpoint disabled interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 0 XFRCM: Transfer completed interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNAK\nBERRM\nReserved\nOUTPKTERRM\nReserved\nSTSPHSRXM\n OTEPDM\nSTUPM\nReserved\nEPDM\nXFRCM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:14 Reserved, must be kept at reset value.\nBit 13 NAKMSK: NAK interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 12 BERRM: Babble error interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBits 11:9 Reserved, must be kept at reset value.\nBit 8 OUTPKTERRM: Out packet error mask\n0: Masked interrupt\n1: Unmasked interrupt\n" }, { "page_number": 1310, "page_indices": { "start_index": 2595664, "end_index": 2597566 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1310 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)", 1310 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1310/1757\nRM0090 Rev 21\nOTG_FS device all endpoints interrupt register (OTG_FS_DAINT)\nAddress offset: 0x818\nReset value: 0x0000 0000\nWhen a significant event occurs on an endpoint, a OTG_FS_DAINT register interrupts the \napplication using the Device OUT endpoints interrupt bit or Device IN endpoints interrupt bit \nof the OTG_FS_GINTSTS register (OEPINT or IEPINT in OTG_FS_GINTSTS, \nrespectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT \nendpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN \nand OUT interrupt bits are used. Bits in this register are set and cleared when the \napplication sets and clears bits in the corresponding Device Endpoint-x interrupt register \n(OTG_FS_DIEPINTx/OTG_FS_DOEPINTx).\n \n \nBits 7:6 Reserved, must be kept at reset value.\nBit 5 STSPHSRXM: Status phase received for control write mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 4 OTEPDM: OUT token received when endpoint disabled mask\nApplies to control OUT endpoints only.\n0: Masked interrupt\n1: Unmasked interrupt\nBit 3 STUPM: SETUP phase done mask\nApplies to control endpoints only.\n0: Masked interrupt\n1: Unmasked interrupt\nBit 2 Reserved, must be kept at reset value.\nBit 1 EPDM: Endpoint disabled interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 0 XFRCM: Transfer completed interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOEPINT\nIEPINT\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 OEPINT: OUT endpoint interrupt bits\nOne bit per OUT endpoint: \nBit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3.\nBits 15:0 IEPINT: IN endpoint interrupt bits\nOne bit per IN endpoint: \nBit 0 for IN endpoint 0, bit 3 for endpoint 3.\n" }, { "page_number": 1311, "page_indices": { "start_index": 2597566, "end_index": 2599320 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1311 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)", 1311 ], [ 4, "OTG_FS device VBUS discharge time register (OTG_FS_DVBUSDIS)", 1311 ], [ 4, "OTG_FS device VBUS pulsing time register (OTG_FS_DVBUSPULSE)", 1311 ] ], "page_content": "RM0090 Rev 21\n1311/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)\nAddress offset: 0x81C\nReset value: 0x0000 0000\nThe OTG_FS_DAINTMSK register works with the Device endpoint interrupt register to \ninterrupt the application when an event occurs on a device endpoint. However, the \nOTG_FS_DAINT register bit corresponding to that interrupt is still set.\n \n \nOTG_FS device VBUS discharge time register (OTG_FS_DVBUSDIS)\nAddress offset: 0x0828\nReset value: 0x0000 17D7\nThis register specifies the VBUS discharge time after VBUS pulsing during SRP.\n \n \nOTG_FS device VBUS pulsing time register (OTG_FS_DVBUSPULSE)\nAddress offset: 0x082C\nReset value: 0x0000 05B8\nThis register specifies the VBUS pulsing time during SRP.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOEPM\nIEPM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 OEPM: OUT EP interrupt mask bits\nOne per OUT endpoint:\nBit 16 for OUT EP 0, bit 19 for OUT EP 3\n0: Masked interrupt\n1: Unmasked interrupt\nBits 15:0 IEPM: IN EP interrupt mask bits\nOne bit per IN endpoint:\nBit 0 for IN EP 0, bit 3 for IN EP 3\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nVBUSDT\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 VBUSDT: Device VBUS discharge time\nSpecifies the VBUS discharge time after VBUS pulsing during SRP. This value equals:\nVBUS discharge time in PHY clocks / 1 024\nDepending on your VBUS load, this value may need adjusting.\n" }, { "page_number": 1312, "page_indices": { "start_index": 2599320, "end_index": 2600923 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1312 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device IN endpoint FIFO empty interrupt mask register: (OTG_FS_DIEPEMPMSK)", 1312 ], [ 4, "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)", 1312 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1312/1757\nRM0090 Rev 21\n \n \nOTG_FS device IN endpoint FIFO empty interrupt mask register: \n(OTG_FS_DIEPEMPMSK)\nAddress offset: 0x834\nReset value: 0x0000 0000\nThis register is used to control the IN endpoint FIFO empty interrupt generation \n(TXFE_OTG_FS_DIEPINTx).\n \n \nOTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)\nAddress offset: 0x900\nReset value: 0x0000 0000\nThis section describes the OTG_FS_DIEPCTL0 register. Nonzero control endpoints use \nregisters for endpoints 1–3.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDVBUSP\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 DVBUSP: Device VBUS pulsing time\nSpecifies the VBUS pulsing time during SRP. This value equals:\nVBUS pulsing time in PHY clocks / 1 024\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nINEPTXFEM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 INEPTXFEM: IN EP Tx FIFO empty interrupt mask bits\nThese bits act as mask bits for OTG_FS_DIEPINTx.\nTXFE interrupt one bit per IN endpoint:\nBit 0 for IN endpoint 0, bit 3 for IN endpoint 3\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEPENA\nEPDIS\nReserved\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nReserved\nUSBAEP\nReserved\nMPSIZ\nr\nr\nw\nw\nrw\nrw\nrw\nrw\nrs\nr\nr\nr\nr\nrw\nrw\n" }, { "page_number": 1313, "page_indices": { "start_index": 2600923, "end_index": 2603037 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1313 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)", 1312 ] ], "page_content": "RM0090 Rev 21\n1313/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n \nBit 31 EPENA: Endpoint enable\nThe application sets this bit to start transmitting data on the endpoint 0.\nThe core clears this bit before setting any of the following interrupts on this endpoint:\n– Endpoint disabled\n– Transfer completed\nBit 30 EPDIS: Endpoint disable\nThe application sets this bit to stop transmitting data on an endpoint, even before the \ntransfer for that endpoint is complete. The application must wait for the Endpoint disabled \ninterrupt before treating the endpoint as disabled. The core clears this bit before setting the \nEndpoint disabled interrupt. The application must set this bit only if Endpoint enable is \nalready set for this endpoint.\nBits 29:28 Reserved, must be kept at reset value.\nBit 27 SNAK: Set NAK\nA write to this bit sets the NAK bit for the endpoint.\nUsing this bit, the application can control the transmission of NAK handshakes on an \nendpoint. The core can also set this bit for an endpoint after a SETUP packet is received on \nthat endpoint.\nBit 26 CNAK: Clear NAK\nA write to this bit clears the NAK bit for the endpoint.\nBits 25:22 TXFNUM: TxFIFO number\nThis value is set to the FIFO number that is assigned to IN endpoint 0.\nBit 21 STALL: STALL handshake\nThe application can only set this bit, and the core clears it when a SETUP token is received \nfor this endpoint. If a NAK bit, a Global IN NAK or Global OUT NAK is set along with this bit, \nthe STALL bit takes priority.\nBit 20 Reserved, must be kept at reset value.\nBits 19:18 EPTYP: Endpoint type\nHardcoded to ‘00’ for control.\nBit 17 NAKSTS: NAK status\nIndicates the following:\n0: The core is transmitting non-NAK handshakes based on the FIFO status\n1: The core is transmitting NAK handshakes on this endpoint.\nWhen this bit is set, either by the application or core, the core stops transmitting data, even \nif there are data available in the TxFIFO. Irrespective of this bit’s setting, the core always \nresponds to SETUP data packets with an ACK handshake.\nBit 16 Reserved, must be kept at reset value.\n" }, { "page_number": 1314, "page_indices": { "start_index": 2603037, "end_index": 2604925 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1314 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3, where x = Endpoint_number)", 1314 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1314/1757\nRM0090 Rev 21\nOTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3, where \nx = Endpoint_number)\nAddress offset: 0x900 + 0x20 * x\nReset value: 0x0000 0000\nThe application uses this register to control the behavior of each logical endpoint other than \nendpoint 0.\n \n \nBit 15 USBAEP: USB active endpoint\nThis bit is always set to 1, indicating that control endpoint 0 is always active in all \nconfigurations and interfaces.\nBits 14:2 Reserved, must be kept at reset value.\nBits 1:0 MPSIZ: Maximum packet size\nThe application must program this field with the maximum packet size for the current logical \nendpoint.\n00: 64 bytes\n01: 32 bytes\n10: 16 bytes\n11: 8 bytes\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nrs\nrs\nw\nw\nw\nw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nr\nr\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 EPENA: Endpoint enable\nThe application sets this bit to start transmitting data on an endpoint.\nThe core clears this bit before setting any of the following interrupts on this endpoint:\n–\nSETUP phase done\n–\nEndpoint disabled\n–\nTransfer completed\nBit 30 EPDIS: Endpoint disable\nThe application sets this bit to stop transmitting/receiving data on an endpoint, even before \nthe transfer for that endpoint is complete. The application must wait for the Endpoint \ndisabled interrupt before treating the endpoint as disabled. The core clears this bit before \nsetting the Endpoint disabled interrupt. The application must set this bit only if Endpoint \nenable is already set for this endpoint.\nBit 29 SODDFRM: Set odd frame\nApplies to isochronous IN and OUT endpoints only.\nWriting to this field sets the Even/Odd frame (EONUM) field to odd frame.\n" }, { "page_number": 1315, "page_indices": { "start_index": 2604925, "end_index": 2607082 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1315 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3, where x = Endpoint_number)", 1314 ] ], "page_content": "RM0090 Rev 21\n1315/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nBit 28 SD0PID: Set DATA0 PID\nApplies to interrupt/bulk IN endpoints only.\nWriting to this field sets the endpoint data PID (DPID) field in this register to DATA0.\nSEVNFRM: Set even frame\nApplies to isochronous IN endpoints only.\nWriting to this field sets the Even/Odd frame (EONUM) field to even frame.\nBit 27 SNAK: Set NAK\nA write to this bit sets the NAK bit for the endpoint.\nUsing this bit, the application can control the transmission of NAK handshakes on an \nendpoint. The core can also set this bit for OUT endpoints on a Transfer completed interrupt, \nor after a SETUP is received on the endpoint.\nBit 26 CNAK: Clear NAK\nA write to this bit clears the NAK bit for the endpoint.\nBits 25:22 TXFNUM: TxFIFO number\nThese bits specify the FIFO number associated with this endpoint. Each active IN endpoint \nmust be programmed to a separate FIFO number.\nThis field is valid only for IN endpoints.\nBit 21 STALL: STALL handshake\nApplies to non-control, non-isochronous IN endpoints only (access type is rw).\nThe application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK \nbit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. \nOnly the application can clear this bit, never the core.\nBit 20 Reserved, must be kept at reset value.\nBits 19:18 EPTYP: Endpoint type\nThis is the transfer type supported by this logical endpoint.\n00: Control\n01: Isochronous\n10: Bulk\n11: Interrupt\nBit 17 NAKSTS: NAK status\nIt indicates the following:\n0: The core is transmitting non-NAK handshakes based on the FIFO status.\n1: The core is transmitting NAK handshakes on this endpoint.\nWhen either the application or the core sets this bit:\nFor non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, \neven if there are data available in the TxFIFO.\nFor isochronous IN endpoints: The core sends out a zero-length data packet, even if there \nare data available in the TxFIFO.\nIrrespective of this bit’s setting, the core always responds to SETUP data packets with an \nACK handshake.\n" }, { "page_number": 1316, "page_indices": { "start_index": 2607082, "end_index": 2608519 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1316 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3, where x = Endpoint_number)", 1314 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1316/1757\nRM0090 Rev 21\nBit 16 EONUM: Even/odd frame\nApplies to isochronous IN endpoints only.\nIndicates the frame number in which the core transmits/receives isochronous data for this \nendpoint. The application must program the even/odd frame number in which it intends to \ntransmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM \nfields in this register.\n0: Even frame\n1: Odd frame\nDPID: Endpoint data PID\nApplies to interrupt/bulk IN endpoints only.\nContains the PID of the packet to be received or transmitted on this endpoint. The \napplication must program the PID of the first packet to be received or transmitted on this \nendpoint, after the endpoint is activated. The application uses the SD0PID register field to \nprogram either DATA0 or DATA1 PID.\n0: DATA0\n1: DATA1\nBit 15 USBAEP: USB active endpoint\nIndicates whether this endpoint is active in the current configuration and interface. The core \nclears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving \nthe SetConfiguration and SetInterface commands, the application must program endpoint \nregisters accordingly and set this bit.\nBits 14:11 Reserved, must be kept at reset value.\nBits 10:0 MPSIZ: Maximum packet size\nThe application must program this field with the maximum packet size for the current logical \nendpoint. This value is in bytes.\n" }, { "page_number": 1317, "page_indices": { "start_index": 2608519, "end_index": 2610471 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1317 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device control OUT endpoint 0 control register (OTG_FS_DOEPCTL0)", 1317 ] ], "page_content": "RM0090 Rev 21\n1317/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS device control OUT endpoint 0 control register \n(OTG_FS_DOEPCTL0)\nAddress offset: 0xB00\nReset value: 0x0000 8000\nThis section describes the OTG_FS_DOEPCTL0 register. Nonzero control endpoints use \nregisters for endpoints 1–3.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEPENA\nEPDIS\nReserved\nSNAK\nCNAK\nReserved\nSTALL\nSNPM\nEPTYP\nNAKSTS\nReserved\nUSBAEP\nReserved\nMPSIZ\nw\nr\nw\nw\nrs\nrw\nr\nr\nr\nr\nr\nr\nBit 31 EPENA: Endpoint enable\nThe application sets this bit to start transmitting data on endpoint 0.\nThe core clears this bit before setting any of the following interrupts on this endpoint:\n–\nSETUP phase done\n–\nEndpoint disabled\n–\nTransfer completed\nBit 30 EPDIS: Endpoint disable\nThe application cannot disable control OUT endpoint 0.\nBits 29:28 Reserved, must be kept at reset value.\nBit 27 SNAK: Set NAK\nA write to this bit sets the NAK bit for the endpoint.\nUsing this bit, the application can control the transmission of NAK handshakes on an \nendpoint. The core can also set this bit on a Transfer completed interrupt, or after a SETUP \nis received on the endpoint.\nBit 26 CNAK: Clear NAK\nA write to this bit clears the NAK bit for the endpoint.\nBits 25:22 Reserved, must be kept at reset value.\nBit 21 STALL: STALL handshake\nThe application can only set this bit, and the core clears it, when a SETUP token is received \nfor this endpoint. If a NAK bit or Global OUT NAK is set along with this bit, the STALL bit \ntakes priority. Irrespective of this bit’s setting, the core always responds to SETUP data \npackets with an ACK handshake.\nBit 20 SNPM: Snoop mode\nThis bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check \nthe correctness of OUT packets before transferring them to application memory.\nBits 19:18 EPTYP: Endpoint type\nHardcoded to 2’b00 for control.\n" }, { "page_number": 1318, "page_indices": { "start_index": 2610471, "end_index": 2612321 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1318 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device endpoint-x control register (OTG_FS_DOEPCTLx) (x = 1..3, where x = Endpoint_number)", 1318 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1318/1757\nRM0090 Rev 21\nOTG_FS device endpoint-x control register (OTG_FS_DOEPCTLx) (x = 1..3, \nwhere x = Endpoint_number)\nAddress offset for OUT endpoints: 0xB00 + 0x20 * x\nReset value: 0x0000 0000\nThe application uses this register to control the behavior of each logical endpoint other than \nendpoint 0.\n \n \nBit 17 NAKSTS: NAK status\nIndicates the following:\n0: The core is transmitting non-NAK handshakes based on the FIFO status.\n1: The core is transmitting NAK handshakes on this endpoint.\nWhen either the application or the core sets this bit, the core stops receiving data, even if \nthere is space in the RxFIFO to accommodate the incoming packet. Irrespective of this bit’s \nsetting, the core always responds to SETUP data packets with an ACK handshake.\nBit 16 Reserved, must be kept at reset value.\nBit 15 USBAEP: USB active endpoint\nThis bit is always set to 1, indicating that a control endpoint 0 is always active in all \nconfigurations and interfaces.\nBits 14:2 Reserved, must be kept at reset value.\nBits 1:0 MPSIZ: Maximum packet size\nThe maximum packet size for control OUT endpoint 0 is the same as what is programmed in \ncontrol IN endpoint 0.\n00: 64 bytes\n01: 32 bytes\n10: 16 bytes\n11: 8 bytes\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEPENA\nEPDIS\nSODDFRM/SD1PID\nSD0PID/SEVNFRM\nSNAK\nCNAK\nReserved\nSTALL\nSNPM\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nrs\nrs\nw\nw\nw\nw\nrw\nrw\nrw\nrw\nr\nr\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 EPENA: Endpoint enable\nApplies to IN and OUT endpoints.\nThe application sets this bit to start transmitting data on an endpoint.\nThe core clears this bit before setting any of the following interrupts on this endpoint:\n–\nSETUP phase done\n–\nEndpoint disabled\n–\nTransfer completed\n" }, { "page_number": 1319, "page_indices": { "start_index": 2612321, "end_index": 2614611 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1319 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device endpoint-x control register (OTG_FS_DOEPCTLx) (x = 1..3, where x = Endpoint_number)", 1318 ] ], "page_content": "RM0090 Rev 21\n1319/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nBit 30 EPDIS: Endpoint disable\nThe application sets this bit to stop transmitting/receiving data on an endpoint, even before \nthe transfer for that endpoint is complete. The application must wait for the Endpoint \ndisabled interrupt before treating the endpoint as disabled. The core clears this bit before \nsetting the Endpoint disabled interrupt. The application must set this bit only if Endpoint \nenable is already set for this endpoint.\nBit 29 SD1PID: Set DATA1 PID\nApplies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the endpoint \ndata PID (DPID) field in this register to DATA1.\nSODDFRM: Set odd frame\nApplies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd \nframe (EONUM) field to odd frame.\nBit 28 SD0PID: Set DATA0 PID\nApplies to interrupt/bulk OUT endpoints only.\nWriting to this field sets the endpoint data PID (DPID) field in this register to DATA0.\nSEVNFRM: Set even frame\nApplies to isochronous OUT endpoints only.\nWriting to this field sets the Even/Odd frame (EONUM) field to even frame.\nBit 27 SNAK: Set NAK\nA write to this bit sets the NAK bit for the endpoint.\nUsing this bit, the application can control the transmission of NAK handshakes on an \nendpoint. The core can also set this bit for OUT endpoints on a Transfer Completed \ninterrupt, or after a SETUP is received on the endpoint.\nBit 26 CNAK: Clear NAK\nA write to this bit clears the NAK bit for the endpoint.\nBits 25:22 Reserved, must be kept at reset value.\nBit 21 STALL: STALL handshake\nApplies to non-control, non-isochronous OUT endpoints only (access type is rw).\nThe application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK \nbit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes \npriority. Only the application can clear this bit, never the core.\nBit 20 SNPM: Snoop mode\nThis bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check \nthe correctness of OUT packets before transferring them to application memory.\nBits 19:18 EPTYP: Endpoint type\nThis is the transfer type supported by this logical endpoint.\n00: Control\n01: Isochronous\n10: Bulk\n11: Interrupt\n" }, { "page_number": 1320, "page_indices": { "start_index": 2614611, "end_index": 2616532 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1320 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device endpoint-x control register (OTG_FS_DOEPCTLx) (x = 1..3, where x = Endpoint_number)", 1318 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1320/1757\nRM0090 Rev 21\nBit 17 NAKSTS: NAK status\nIndicates the following:\n0: The core is transmitting non-NAK handshakes based on the FIFO status.\n1: The core is transmitting NAK handshakes on this endpoint.\nWhen either the application or the core sets this bit:\nThe core stops receiving any data on an OUT endpoint, even if there is space in the \nRxFIFO to accommodate the incoming packet.\nIrrespective of this bit’s setting, the core always responds to SETUP data packets with an \nACK handshake.\nBit 16 EONUM: Even/odd frame\nApplies to isochronous IN and OUT endpoints only.\nIndicates the frame number in which the core transmits/receives isochronous data for this \nendpoint. The application must program the even/odd frame number in which it intends to \ntransmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM \nfields in this register.\n0: Even frame\n1: Odd frame\nDPID: Endpoint data PID\nApplies to interrupt/bulk OUT endpoints only.\nContains the PID of the packet to be received or transmitted on this endpoint. The \napplication must program the PID of the first packet to be received or transmitted on this \nendpoint, after the endpoint is activated. The application uses the SD0PID register field to \nprogram either DATA0 or DATA1 PID.\n0: DATA0\n1: DATA1\nBit 15 USBAEP: USB active endpoint\nIndicates whether this endpoint is active in the current configuration and interface. The core \nclears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving \nthe SetConfiguration and SetInterface commands, the application must program endpoint \nregisters accordingly and set this bit.\nBits 14:11 Reserved, must be kept at reset value.\nBits 10:0 MPSIZ: Maximum packet size\nThe application must program this field with the maximum packet size for the current logical \nendpoint. This value is in bytes.\n" }, { "page_number": 1321, "page_indices": { "start_index": 2616532, "end_index": 2619317 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1321 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) (x = 0..3, where x = Endpoint_number)", 1321 ] ], "page_content": "RM0090 Rev 21\n1321/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) (x = 0..3, \nwhere x = Endpoint_number)\nAddress offset: 0x908 + 0x20 * x\nReset value: 0x0000 0080\nThis register indicates the status of an endpoint with respect to USB- and AHB-related \nevents. It is shown in Figure 394. The application must read this register when the IN \nendpoints interrupt bit of the Core interrupt register (IEPINT in OTG_FS_GINTSTS) is set. \nBefore the application can read this register, it must first read the device all endpoints \ninterrupt (OTG_FS_DAINT) register to get the exact endpoint number for the Device \nendpoint-x interrupt register. The application must clear the appropriate bit in this register to \nclear the corresponding bits in the OTG_FS_DAINT and OTG_FS_GINTSTS registers.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nReserved\nEPDISD\nXFRC\nrc_\nw1\nrc_\nw1\nr\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nBits 31:14 Reserved, must be kept at reset value.\nBit 13 NAK: NAK input\nThe core generates this interrupt when a NAK is transmitted or received by the device. In \ncase of isochronous IN endpoints the interrupt gets generated when a zero length packet is \ntransmitted due to unavailability of data in the Tx FIFO.\nBit 12 Reserved, must be kept at reset value.\nBit 11 PKTDRPSTS: Packet dropped status\nThis bit indicates to the application that an ISOC OUT packet has been dropped. This bit \ndoes not have an associated mask bit and does not generate an interrupt.\nBits 10:8 Reserved, must be kept at reset value.\nBit 7 TXFE: Transmit FIFO empty\nThis interrupt is asserted when the TxFIFO for this endpoint is either half or completely \nempty. The half or completely empty status is determined by the TxFIFO Empty Level bit in \nthe OTG_FS_GAHBCFG register (TXFELVL bit in OTG_FS_GAHBCFG).\nBit 6 INEPNE: IN endpoint NAK effective\nThis bit can be cleared when the application clears the IN endpoint NAK by writing to the \nCNAK bit in OTG_FS_DIEPCTLx.\nThis interrupt indicates that the core has sampled the NAK bit set (either by the application \nor by the core). The interrupt indicates that the IN endpoint NAK bit set by the application \nhas taken effect in the core.\nThis interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit \ntakes priority over a NAK bit.\nBit 5 INEPNM: IN token received with EP mismatch.\nIndicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other \nthan the one for which the IN token was received. This interrupt is asserted on the endpoint \nfor which the IN token was received.\n" }, { "page_number": 1322, "page_indices": { "start_index": 2619317, "end_index": 2621641 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1322 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device endpoint-x interrupt register (OTG_FS_DOEPINTx) (x = 0..3, where x = Endpoint_number)", 1322 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1322/1757\nRM0090 Rev 21\nOTG_FS device endpoint-x interrupt register (OTG_FS_DOEPINTx) (x = 0..3, \nwhere x = Endpoint_number)\nAddress offset: 0xB08 + 0x20 * x\nReset value: 0x0000 0080\nThis register indicates the status of an endpoint with respect to USB- and AHB-related \nevents. It is shown in Figure 394. The application must read this register when the OUT \nEndpoints Interrupt bit of the OTG_FS_GINTSTS register (OEPINT bit in \nOTG_FS_GINTSTS) is set. Before the application can read this register, it must first read \nthe OTG_FS_DAINT register to get the exact endpoint number for the OTG_FS_DOEPINTx \nregister. The application must clear the appropriate bit in this register to clear the \ncorresponding bits in the OTG_FS_DAINT and OTG_FS_GINTSTS registers.\n \n \nBit 4 ITTXFE: IN token received when TxFIFO is empty\nApplies to non-periodic IN endpoints only.\nIndicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) \nwas empty. This interrupt is asserted on the endpoint for which the IN token was received.\nBit 3 TOC: Timeout condition\nApplies only to Control IN endpoints.\nIndicates that the core has detected a timeout condition on the USB for the last IN token on \nthis endpoint. \nBit 2 Reserved, must be kept at reset value.\nBit 1 EPDISD: Endpoint disabled interrupt\nThis bit indicates that the endpoint is disabled per the application’s request.\nBit 0 XFRC: Transfer completed interrupt\nThis field indicates that the programmed transfer is complete on the AHB as well as on the \nUSB, for this endpoint.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nSTSPHSRX\nOTEPDIS\nSTUP\nReserved\nEPDISD\nXFRC\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nrc_w1\nBits 31:14 Reserved, must be kept at reset value.\nBit 13 NAK: NAK input\nThe core generates this interrupt when a NAK is transmitted or received by the device. In \ncase of isochronous IN endpoints the interrupt gets generated when a zero length packet is \ntransmitted due to unavailability of data in the Tx FIFO.\nBit 12 BERR: Babble error interrupt\nThe core generates this interrupt when babble is received for the endpoint.\nBits 11:9 Reserved, must be kept at reset value.\n" }, { "page_number": 1323, "page_indices": { "start_index": 2621641, "end_index": 2624014 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1323 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device IN endpoint 0 transfer size register (OTG_FS_DIEPTSIZ0)", 1323 ] ], "page_content": "RM0090 Rev 21\n1323/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS device IN endpoint 0 transfer size register (OTG_FS_DIEPTSIZ0)\nAddress offset: 0x910\nReset value: 0x0000 0000\nThe application must modify this register before enabling endpoint 0. Once endpoint 0 is \nenabled using the endpoint enable bit in the device control endpoint 0 control registers \n(EPENA in OTG_FS_DIEPCTL0), the core modifies this register. The application can only \nread this register once the core has cleared the Endpoint enable bit.\nNonzero endpoints use the registers for endpoints 1–3.\n \n \nBit 8 OUTPKTERR: OUT packet error\nThis interrupt is asserted when the core detects an overflow or a CRC error for an OUT \npacket. This interrupt is valid only when thresholding is enabled.\nBits 7:6 Reserved, must be kept at reset value.\nBit 5 STSPHSRX: Status phase received for control write\nThis interrupt is generated only after the core has transferred all the data that the host has \nsent during the data phase of a control write transfer, to the system memory buffer. The \ninterrupt indicates to the application that the host has switched from data phase to the status \nphase of a control write transfer. The application can use this interrupt to ACK or STALL the \nstatus phase, after it has decoded the data phase.\nBit 4 OTEPDIS: OUT token received when endpoint disabled\nApplies only to control OUT endpoints.\nIndicates that an OUT token was received when the endpoint was not yet enabled. This \ninterrupt is asserted on the endpoint for which the OUT token was received.\nBit 3 STUP: SETUP phase done\nApplies to control OUT endpoint only.\nIndicates that the SETUP phase for the control endpoint is complete and no more back-to-\nback SETUP packets were received for the current control transfer. On this interrupt, the \napplication can decode the received SETUP data packet.\nBit 2 Reserved, must be kept at reset value.\nBit 1 EPDISD: Endpoint disabled interrupt\nThis bit indicates that the endpoint is disabled per the application’s request.\nBit 0 XFRC: Transfer completed interrupt\nThis field indicates that the programmed transfer is complete on the AHB as well as on the \nUSB, for this endpoint.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPKTCNT\nReserved\nXFRSIZ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1324, "page_indices": { "start_index": 2624014, "end_index": 2624849 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1324 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device IN endpoint 0 transfer size register (OTG_FS_DIEPTSIZ0)", 1323 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1324/1757\nRM0090 Rev 21\nBits 31:21 Reserved, must be kept at reset value.\nBits 20:19 PKTCNT: Packet count\nIndicates the total number of USB packets that constitute the Transfer Size amount of data \nfor endpoint 0.\nThis field is decremented every time a packet (maximum size or short packet) is read from \nthe TxFIFO.\nBits 18:7 Reserved, must be kept at reset value.\nBits 6:0 XFRSIZ: Transfer size\nIndicates the transfer size in bytes for endpoint 0. The core interrupts the application only \nafter it has exhausted the transfer size amount of data. The transfer size can be set to the \nmaximum packet size of the endpoint, to be interrupted at the end of each packet.\nThe core decrements this field every time a packet from the external memory is written to \nthe TxFIFO.\n" }, { "page_number": 1325, "page_indices": { "start_index": 2624849, "end_index": 2626461 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1325 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device OUT endpoint 0 transfer size register (OTG_FS_DOEPTSIZ0)", 1325 ] ], "page_content": "RM0090 Rev 21\n1325/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS device OUT endpoint 0 transfer size register (OTG_FS_DOEPTSIZ0)\nAddress offset: 0xB10\nReset value: 0x0000 0000\nThe application must modify this register before enabling endpoint 0. Once endpoint 0 is \nenabled using the Endpoint enable bit in the OTG_FS_DOEPCTL0 registers (EPENA bit in \nOTG_FS_DOEPCTL0), the core modifies this register. The application can only read this \nregister once the core has cleared the Endpoint enable bit.\nNonzero endpoints use the registers for endpoints 1–3.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSTUPCNT\nReserved\nPKTCNT\nReserved\nXFRSIZ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBits 30:29 STUPCNT: SETUP packet count\nThis field specifies the number of back-to-back SETUP data packets the endpoint can \nreceive.\n01: 1 packet\n10: 2 packets\n11: 3 packets\nBits 28:20 Reserved, must be kept at reset value.\nBit 19 PKTCNT: Packet count\nThis field is decremented to zero after a packet is written into the RxFIFO.\nBits 18:7 Reserved, must be kept at reset value.\nBits 6:0 XFRSIZ: Transfer size\nIndicates the transfer size in bytes for endpoint 0. The core interrupts the application only \nafter it has exhausted the transfer size amount of data. The transfer size can be set to the \nmaximum packet size of the endpoint, to be interrupted at the end of each packet.\nThe core decrements this field every time a packet is read from the RxFIFO and written to \nthe external memory.\n" }, { "page_number": 1326, "page_indices": { "start_index": 2626461, "end_index": 2627979 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1326 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device endpoint-x transfer size register (OTG_FS_DIEPTSIZx) (x = 1..3, where x = Endpoint_number)", 1326 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1326/1757\nRM0090 Rev 21\nOTG_FS device endpoint-x transfer size register (OTG_FS_DIEPTSIZx) \n(x = 1..3, where x = Endpoint_number)\nAddress offset: 0x910 + 0x20 * x\nReset value: 0x0000 0000\nThe application must modify this register before enabling the endpoint. Once the endpoint is \nenabled using the Endpoint enable bit in the OTG_FS_DIEPCTLx registers (EPENA bit in \nOTG_FS_DIEPCTLx), the core modifies this register. The application can only read this \nregister once the core has cleared the Endpoint enable bit.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPKTCNT\nXFRSIZ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:29 Reserved, must be kept at reset value.\nBit 28:19 PKTCNT: Packet count\nIndicates the total number of USB packets that constitute the Transfer Size amount of data \nfor this endpoint. \nThis field is decremented every time a packet (maximum size or short packet) is read from \nthe TxFIFO.\nBits 18:0 XFRSIZ: Transfer size\nThis field contains the transfer size in bytes for the current endpoint. The core only interrupts \nthe application after it has exhausted the transfer size amount of data. The transfer size can \nbe set to the maximum packet size of the endpoint, to be interrupted at the end of each \npacket.\nThe core decrements this field every time a packet from the external memory is written to the \nTxFIFO.\n" }, { "page_number": 1327, "page_indices": { "start_index": 2627979, "end_index": 2629771 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1327 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.4 Device-mode registers", 1305 ], [ 4, "OTG_FS device IN endpoint transmit FIFO status register (OTG_FS_DTXFSTSx) (x = 0..3, where x = Endpoint_number)", 1327 ], [ 4, "OTG_FS device OUT endpoint-x transfer size register (OTG_FS_DOEPTSIZx) (x = 1..3, where x = Endpoint_number)", 1327 ] ], "page_content": "RM0090 Rev 21\n1327/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nOTG_FS device IN endpoint transmit FIFO status register \n(OTG_FS_DTXFSTSx) (x = 0..3, where x = Endpoint_number)\nAddress offset for IN endpoints: 0x918 + 0x20 * x\nThis read-only register contains the free space information for the Device IN endpoint \nTxFIFO.\n \n \nOTG_FS device OUT endpoint-x transfer size register (OTG_FS_DOEPTSIZx) \n(x = 1..3, where x = Endpoint_number)\nAddress offset: 0xB10 + 0x20 * x\nReset value: 0x0000 0000\nThe application must modify this register before enabling the endpoint. Once the endpoint is \nenabled using Endpoint Enable bit of the OTG_FS_DOEPCTLx registers (EPENA bit in \nOTG_FS_DOEPCTLx), the core modifies this register. The application can only read this \nregister once the core has cleared the Endpoint enable bit.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nINEPTFSAV\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31:16 Reserved, must be kept at reset value.\n15:0 INEPTFSAV: IN endpoint TxFIFO space available\nIndicates the amount of free space available in the Endpoint TxFIFO.\nValues are in terms of 32-bit words:\n0x0: Endpoint TxFIFO is full\n0x1: 1 word available\n0x2: 2 words available\n0xn: n words available\nOthers: Reserved\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRXDPID/S\nTUPCNT\nPKTCNT\nXFRSIZ\nr/rw\nr/rw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBits 30:29 RXDPID: Received data PID\nApplies to isochronous OUT endpoints only.\nThis is the data PID received in the last packet for this endpoint.\n00: DATA0\n01: DATA2\n10: DATA1\n11: MDATA\n" }, { "page_number": 1328, "page_indices": { "start_index": 2629771, "end_index": 2631865 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1328 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.5 OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)", 1328 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1328/1757\nRM0090 Rev 21\n34.16.5 \nOTG_FS power and clock gating control register\n(OTG_FS_PCGCCTL)\nAddress offset: 0xE00\nReset value: 0x0000 0000\nThis register is available in host and device modes.\n \n \nSTUPCNT: SETUP packet count\nApplies to control OUT Endpoints only.\nThis field specifies the number of back-to-back SETUP data packets the endpoint can \nreceive.\n01: 1 packet\n10: 2 packets\n11: 3 packets\nBit 28:19 PKTCNT: Packet count\nIndicates the total number of USB packets that constitute the Transfer Size amount of data \nfor this endpoint.\nThis field is decremented every time a packet (maximum size or short packet) is written to \nthe RxFIFO.\nBits 18:0 XFRSIZ: Transfer size\nThis field contains the transfer size in bytes for the current endpoint. The core only interrupts \nthe application after it has exhausted the transfer size amount of data. The transfer size can \nbe set to the maximum packet size of the endpoint, to be interrupted at the end of each \npacket.\nThe core decrements this field every time a packet is read from the RxFIFO and written to \nthe external memory.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPHYSUSP\nReserved\nGATEHCLK\nSTPPCLK\nrw\nrw\nrw\nBit 31:5 Reserved, must be kept at reset value.\nBit 4 PHYSUSP: PHY Suspended\nIndicates that the PHY has been suspended. This bit is updated once the PHY is suspended \nafter the application has set the STPPCLK bit (bit 0).\nBits 3:2 Reserved, must be kept at reset value.\nBit 1 GATEHCLK: Gate HCLK\nThe application sets this bit to gate HCLK to modules other than the AHB Slave and Master \nand wake-up logic when the USB is suspended or the session is not valid. The application \nclears this bit when the USB is resumed or a new session starts.\nBit 0 STPPCLK: Stop PHY clock\nThe application sets this bit to stop the PHY clock when the USB is suspended, the session \nis not valid, or the device is disconnected. The application clears this bit when the USB is \nresumed or a new session starts.\n" }, { "page_number": 1329, "page_indices": { "start_index": 2631865, "end_index": 2633691 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1329 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.6 OTG_FS register map", 1329 ] ], "page_content": "RM0090 Rev 21\n1329/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34.16.6 \nOTG_FS register map\nThe table below gives the USB OTG register map and reset values.\n \nTable 206. OTG_FS register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x000\nOTG_FS_GOTG\nCTL\nReserved\nBSVLD\nASVLD\nDBCT\nCIDSTS\nReserved\nDHNPEN\nHSHNPEN\nHNPRQ\nHNGSCS\nReserved\nSRQ\nSRQSCS\nReset value\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0x004\nOTG_FS_GOTG\nINT\nReserved\nDBCDNE\nADTOCHG\nHNGDET\nReserved\nHNSSCHG\nSRSSCHG\nReserved\nSEDET\nRes.\nReset value\n0\n0\n0\n0\n0\n0\n0x008\nOTG_FS_GAHB\nCFG\nReserved\nPTXFELVL\nTXFELVL\nReserved\nGINTMSK\nReset value\n0\n0\n0\n0x00C\nOTG_FS_GUSB\nCFG\nCTXPKT\nFDMOD\nFHMOD\nReserved\nTRDT\nHNPCA\nSRPCAP\nReserved\nPHYSEL\nReserved\nTOCAL\nReset value\n0\n0\n0\n0\n0\n1\n0\n1\n0\n0\n0\n0\n0\n0x010\nOTG_FS_GRST\nCTL\nAHBIDL\nReserved\nTXFNUM\nTXFFLSH\nRXFFLSH\nReserved\nFCRST\nHSRST\nCSRST\nReset value\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x014\nOTG_FS_GINTS\nTS\nWKUINT\nSRQINT\nDISCINT\nCIDSCHG\nReserved\nPTXFE\nHCINT\nHPRTINT\nReserved\nIPXFR/INCOMPISOOUT\nIISOIXFR\nOEPINT\nIEPINT\nReserved\nEOPF\nISOODRP\nENUMDNE\nUSBRST\nUSBSUSP\nESUSP\nReserved\nGONAKEFF\nGINAKEFF\nNPTXFE\nRXFLVL\nSOF\nOTGINT\nMMIS\nCMOD\nReset value\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0x018\nOTG_FS_GINT\nMSK\nWUIM\nSRQIM\nDISCINT\nCIDSCHGM\nReserved\nPTXFEM\nHCIM\nPRTIM\nReserved\nIPXFRM/IISOOXFRM\nIISOIXFRM\nOEPINT\nIEPINT\nReserved\nEOPFM\nISOODRPM\nENUMDNEM\nUSBRST\nUSBSUSPM\nESUSPM\nReserved\nGONAKEFFM\nGINAKEFFM\nNPTXFEM\nRXFLVLM\nSOFM\nOTGINT\nMMISM\nReserved\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x01C\nOTG_FS_GRXS\nTSR (host \nmode)\nReserved\nPKTSTS\nDPID\nBCNT\nCHNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nOTG_FS_GRXS\nTSR (Device \nmode)\nReserved\nFRMNUM\nPKTSTS\nDPID\nBCNT\nEPNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n" }, { "page_number": 1330, "page_indices": { "start_index": 2633691, "end_index": 2635474 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1330 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.6 OTG_FS register map", 1329 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1330/1757\nRM0090 Rev 21\n0x020\nOTG_FS_GRXS\nTSR (host \nmode)\nReserved\nPKTSTS\nDPID\nBCNT\nCHNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nOTG_FS_GRXS\nTSPR (Device \nmode)\nReserved\nFRMNUM\nPKTSTS\nDPID\nBCNT\nEPNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x024\nOTG_FS_GRXF\nSIZ\nReserved\nRXFD\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x028\nOTG_FS_HNPT\nXFSIZ/ \nOTG_FS_DIEPT\nXF0\nNPTXFD/TX0FD\nNPTXFSA/TX0FSA\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x02C\nOTG_FS_HNPT\nXSTS\nRes.\nNPTXQTOP\nNPTQXSAV\nNPTXFSAV\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x038\nOTG_FS_\nGCCFG\nReserved\nNOVBUSSENS\nSOFOUTEN\nVBUSBSEN\nVBUSASEN\nReserved\n.PWRDWN\nReserved\nReset value\n0\n0\n0\n0\n0\n0x03C\nOTG_FS_CID\nPRODUCT_ID\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x100\nOTG_FS_HPTX\nFSIZ\nPTXFSIZ\nPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x104\nOTG_FS_DIEPT\nXF1\nINEPTXFD\nINEPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x108\nOTG_FS_DIEPT\nXF2\nINEPTXFD\nINEPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10C\nOTG_FS_DIEPT\nXF3\nINEPTXFD\nINEPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x400\nOTG_FS_HCFG\nReserved\nFSLSS\nFSLSPCS\nReset value\n0\n0\n0\n0x404\nOTG_FS_HFIR\nReserved\nFRIVL\nReset value\n1\n1\n1\n0\n1\n0\n1\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0x408\nOTG_FS_HFNU\nM\nFTREM\nFRNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\nTable 206. OTG_FS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1331, "page_indices": { "start_index": 2635474, "end_index": 2637602 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1331 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.6 OTG_FS register map", 1329 ] ], "page_content": "RM0090 Rev 21\n1331/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n0x410\nOTG_FS_HPTX\nSTS\nPTXQTOP\nPTXQSAV\nPTXFSAVL\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\n0x414\nOTG_FS_HAINT\nReserved\nHAINT\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x418\nOTG_FS_HAINT\nMSK\nReserved\nHAINTM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x440\nOTG_FS_HPRT\nReserved\nPSPD\nPTCTL\nPPWR\nPLSTS\nReserved\nPRST\nPSUSP\nPRES\nPOCCHNG\nPOCA\nPENCHNG\nPENA\nPCDET\nPCSTS\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x500\nOTG_FS_HCCH\nAR0\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x520\nOTG_FS_HCCH\nAR1\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x540\nOTG_FS_HCCH\nAR2\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x560\nOTG_FS_HCCH\nAR3\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x580\nOTG_FS_HCCH\nAR4\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5A0\nOTG_FS_HCCH\nAR5\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5C0\nOTG_FS_HCCH\nAR6\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5E0\nOTG_FS_HCCH\nAR7\nCHENA\nCHDIS\nODDFRM\nDAD\nMCNT\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x508\nOTG_FS_HCINT\n0\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 206. OTG_FS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1332, "page_indices": { "start_index": 2637602, "end_index": 2639412 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1332 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.6 OTG_FS register map", 1329 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1332/1757\nRM0090 Rev 21\n0x528\nOTG_FS_HCINT\n1\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x548\nOTG_FS_HCINT\n2\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x568\nOTG_FS_HCINT\n3\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x588\nOTG_FS_HCINT\n4\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5A8\nOTG_FS_HCINT\n5\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5C8\nOTG_FS_HCINT\n6\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5E8\nOTG_FS_HCINT\n7\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nReserved\nACK\nNAK\nSTALL\nReserved\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x50C\nOTG_FS_HCINT\nMSK0\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x52C\nOTG_FS_HCINT\nMSK1\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x54C\nOTG_FS_HCINT\nMSK2\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x56C\nOTG_FS_HCINT\nMSK3\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x58C\nOTG_FS_HCINT\nMSK4\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 206. OTG_FS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1333, "page_indices": { "start_index": 2639412, "end_index": 2641297 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1333 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.6 OTG_FS register map", 1329 ] ], "page_content": "RM0090 Rev 21\n1333/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n0x5AC\nOTG_FS_HCINT\nMSK5\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5CC\nOTG_FS_HCINT\nMSK6\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5EC\nOTG_FS_HCINT\nMSK7\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nReserved\nACKM\nNAKM\nSTALLM\nReserved\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x510\nOTG_FS_HCTSI\nZ0\nReserved\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x530\nOTG_FS_HCTSI\nZ1\nReserved\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x550\nOTG_FS_HCTSI\nZ2\nReserved\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x570\nOTG_FS_HCTSI\nZ3\nReserved\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x590\nOTG_FS_HCTSI\nZ4\nReserved\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5B0\nOTG_FS_HCTSI\nZ5\nReserved\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5D0\nOTG_FS_HCTSI\nZ6\nReserved\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5F0\nOTG_FS_HCTSI\nZ7\nReserved\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x800\nOTG_FS_DCFG\nReserved\nPFIVL\nDAD\nReserved\nNZLSOHSK\nDSPD\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x804\nOTG_FS_DCTL\nReserved\nPOPRGDNE\nCGONAK\nSGONAK\nCGINAK\nSGINAK\nTCTL\nGONSTS\nGINSTS\nSDIS\nRWUSIG\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 206. OTG_FS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1334, "page_indices": { "start_index": 2641297, "end_index": 2642933 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1334 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.6 OTG_FS register map", 1329 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1334/1757\nRM0090 Rev 21\n0x808\nOTG_FS_DSTS\nReserved\nFNSOF\nReserved\nEERR\nENUMSPD\nSUSPSTS\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x810\nOTG_FS_DIEPM\nSK\nReserved\nNAKM\nReserved\nINEPNEM\nINEPNMM\nITTXFEMSK\nTOM\nReserved\nEPDM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0x814\nOTG_FS_DOEP\nMSK\nReserved\nNAKMSK\nBERRM\nReserved\nOUTPKTERRM\nReserved\nSTSPHSRXM\n OTEPDM\nSTUPM\nReserved\nEPDM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x818\nOTG_FS_DAINT\nOEPINT\nIEPINT\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x81C\nOTG_FS_DAINT\nMSK\nOEPM\nIEPM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x828\nOTG_FS_DVBU\nSDIS\nReserved\nVBUSDT\nReset value\n0\n0\n0\n1\n0\n1\n1\n1\n1\n1\n0\n1\n0\n1\n1\n1\n0x82C\nOTG_FS_DVBU\nSPULSE\nReserved\nDVBUSP\nReset value\n0\n1\n0\n1\n1\n0\n1\n1\n1\n0\n0\n0\n0x834\nOTG_FS_DIEPE\nMPMSK\nReserved\nINEPTXFEM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x900\nOTG_FS_DIEPC\nTL0\nEPENA\nEPDIS\nReserved\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTY\nP\nNAKSTS\nReserved\nUSBAEP\nReserved\nMPSI\nZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0x918\nTG_FS_DTXFST\nS0\nReserved\nINEPTFSAV\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x920\nOTG_FS_DIEPC\nTL1\nEPENA\nEPDIS\nSODDFRM/SD1PID\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x938\nTG_FS_DTXFST\nS1\nReserved\nINEPTFSAV\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 206. OTG_FS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1335, "page_indices": { "start_index": 2642933, "end_index": 2644645 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1335 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.6 OTG_FS register map", 1329 ] ], "page_content": "RM0090 Rev 21\n1335/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n0x940\nOTG_FS_DIEPC\nTL2\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x958\nTG_FS_DTXFST\nS2\nReserved\nINEPTFSAV\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x960\nOTG_FS_DIEPC\nTL3\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x978\nTG_FS_DTXFST\nS3\nReserved\nINEPTFSAV\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB00\nOTG_FS_DOEP\nCTL0\nEPENA\nEPDIS\nReserved\nSNAK\nCNAK\nReserved\nSTALL\nSNPM\nEPTY\nP\nNAKSTS\nReserved\nUSBAEP\nReserved\nMPSI\nZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0xB20\nOTG_FS_DOEP\nCTL1\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nReserved\nSTALL\nSNPM\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB40\nOTG_FS_DOEP\nCTL2\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nReserved\nSTALL\nSNPM\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB60\nOTG_FS_DOEP\nCTL3\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nReserved\nSTALL\nSNPM\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x908\nOTG_FS_DIEPI\nNT0\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nReserved\nEPDISD\nXFRC\nReset value\n0\n0\n1\n0\n0\n0\n0\n0\n0\nTable 206. OTG_FS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1336, "page_indices": { "start_index": 2644645, "end_index": 2646328 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1336 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.6 OTG_FS register map", 1329 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1336/1757\nRM0090 Rev 21\n0x928\nOTG_FS_DIEPI\nNT1\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nReserved\nEPDISD\nXFRC\nReset value\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0x948\nOTG_FS_DIEPI\nNT2\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nReserved\nEPDISD\nXFRC\nReset value\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0x968\nOTG_FS_DIEPI\nNT3\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nReserved\nEPDISD\nXFRC\nReset value\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0xB08\nOTG_FS_DOEPI\nNT0\nReserved\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nSTSPHSRX\nOTEPDIS\nSTUP\nReserved\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0xB28\nOTG_FS_DOEPI\nNT1\nReserved\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nSTSPHSRX\nOTEPDIS\nSTUP\nReserved\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0xB48\nOTG_FS_DOEPI\nNT2\nReserved\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nSTSPHSRX\nOTEPDIS\nSTUP\nReserved\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0xB68\nOTG_FS_DOEPI\nNT3\nReserved\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nSTSPHSRX\nOTEPDIS\nSTUP\nReserved\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0x910\nOTG_FS_DIEPT\nSIZ0\nReserved\nPKTC\nNT\nReserved\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x930\nOTG_FS_DIEPT\nSIZ1\nReserved\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x950\nOTG_FS_DIEPT\nSIZ2\nReserved\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x970\nOTG_FS_DIEPT\nSIZ3\nReserved\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 206. OTG_FS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1337, "page_indices": { "start_index": 2646328, "end_index": 2647247 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1337 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.16 OTG_FS control and status registers", 1268 ], [ 3, "34.16.6 OTG_FS register map", 1329 ] ], "page_content": "RM0090 Rev 21\n1337/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0xB10\nOTG_FS_DOEP\nTSIZ0\nReserved\nSTUP\nCNT\nReserved\nPKTCNT\nReserved\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB30\nOTG_FS_DOEP\nTSIZ1\nReserved\nRXDPID/\nSTUPCNT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB50\nOTG_FS_DOEP\nTSIZ2\nReserved\nRXDPID/\nSTUPCNT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB70\nOTG_FS_DOEP\nTSIZ3\nReserved\nRXDPID/\nSTUPCNT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xE00\nOTG_FS_PCGC\nCTL\nReserved\nPHYSUSP\nReserved\nGATEHCLK\nSTPPCLK\nReset value\nTable 206. OTG_FS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1338, "page_indices": { "start_index": 2647247, "end_index": 2648602 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1338 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.1 Core initialization", 1338 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1338/1757\nRM0090 Rev 21\n34.17 \nOTG_FS programming model\n34.17.1 \nCore initialization\nThe application must perform the core initialization sequence. If the cable is connected \nduring power-up, the current mode of operation bit in the OTG_FS_GINTSTS (CMOD bit in \nOTG_FS_GINTSTS) reflects the mode. The OTG_FS controller enters host mode when an \n“A” plug is connected or device mode when a “B” plug is connected.\nThis section explains the initialization of the OTG_FS controller after power-on. The \napplication must follow the initialization sequence irrespective of host or device mode \noperation. All core global registers are initialized according to the core’s configuration:\n1.\nProgram the following fields in the OTG_FS_GAHBCFG register:\n–\nGlobal interrupt mask bit GINTMSK = 1\n–\nRxFIFO non-empty (RXFLVL bit in OTG_FS_GINTSTS)\n–\nPeriodic TxFIFO empty level\n2. \nProgram the following fields in the OTG_FS_GUSBCFG register:\n–\nHNP capable bit \n–\nSRP capable bit\n–\nFS timeout calibration field\n–\nUSB turnaround time field\n3. \nThe software must unmask the following bits in the OTG_FS_GINTMSK register:\nOTG interrupt mask\nMode mismatch interrupt mask\n4. \nThe software can read the CMOD bit in OTG_FS_GINTSTS to determine whether the \nOTG_FS controller is operating in host or device mode.\n" }, { "page_number": 1339, "page_indices": { "start_index": 2648602, "end_index": 2651077 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1339 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.2 Host initialization", 1339 ], [ 3, "34.17.3 Device initialization", 1339 ] ], "page_content": "RM0090 Rev 21\n1339/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n34.17.2 \nHost initialization\nTo initialize the core as host, the application must perform the following steps:\n1.\nProgram the HPRTINT in the OTG_FS_GINTMSK register to unmask\n2. \nProgram the OTG_FS_HCFG register to select full-speed host\n3. \nProgram the PPWR bit in OTG_FS_HPRT to 1. This drives VBUS on the USB.\n4. \nWait for the PCDET interrupt in OTG_FS_HPRT0. This indicates that a device is \nconnecting to the port.\n5. \nProgram the PRST bit in OTG_FS_HPRT to 1. This starts the reset process.\n6. \nWait at least 10 ms for the reset process to complete.\n7. \nProgram the PRST bit in OTG_FS_HPRT to 0.\n8. \nWait for the PENCHNG interrupt in OTG_FS_HPRT.\n9. \nRead the PSPD bit in OTG_FS_HPRT to get the enumerated speed.\n10. Program the HFIR register with a value corresponding to the selected PHY clock 1\n11. Program the FSLSPCS field in the OTG_FS_HCFG register following the speed of the \ndevice detected in step 9. If FSLSPCS has been changed a port reset must be \nperformed.\n12. Program the OTG_FS_GRXFSIZ register to select the size of the receive FIFO.\n13. Program the OTG_FS_HNPTXFSIZ register to select the size and the start address of \nthe Non-periodic transmit FIFO for non-periodic transactions.\n14. Program the OTG_FS_HPTXFSIZ register to select the size and start address of the \nperiodic transmit FIFO for periodic transactions.\nTo communicate with devices, the system software must initialize and enable at least one \nchannel.\n34.17.3 \nDevice initialization\nThe application must perform the following steps to initialize the core as a device on power-\nup or after a mode change from host to device.\n1.\nProgram the following fields in the OTG_FS_DCFG register:\n–\nDevice speed\n–\nNon-zero-length status OUT handshake\n2. \nProgram the OTG_FS_GINTMSK register to unmask the following interrupts:\n–\nUSB reset\n–\nEnumeration done\n–\nEarly suspend\n–\nUSB suspend\n–\nSOF\n3. \nProgram the VBUSBSEN bit in the OTG_FS_GCCFG register to enable VBUS sensing \nin “B” device mode and supply the 5 volts across the pull-up resistor on the DP line.\n4. \nWait for the USBRST interrupt in OTG_FS_GINTSTS. It indicates that a reset has been \ndetected on the USB that lasts for about 10 ms on receiving this interrupt.\nWait for the ENUMDNE interrupt in OTG_FS_GINTSTS. This interrupt indicates the end of \nreset on the USB. On receiving this interrupt, the application must read the OTG_FS_DSTS \n" }, { "page_number": 1340, "page_indices": { "start_index": 2651077, "end_index": 2653985 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1340 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.4 Host programming model", 1340 ], [ 4, "Channel initialization", 1340 ], [ 4, "Halting a channel", 1340 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1340/1757\nRM0090 Rev 21\nregister to determine the enumeration speed and perform the steps listed in Endpoint \ninitialization on enumeration completion on page 1356. \nAt this point, the device is ready to accept SOF packets and perform control transfers on \ncontrol endpoint 0.\n34.17.4 \nHost programming model\nChannel initialization\nThe application must initialize one or more channels before it can communicate with \nconnected devices. To initialize and enable a channel, the application must perform the \nfollowing steps:\n1.\nProgram the OTG_FS_GINTMSK register to unmask the following:\n2. \nChannel interrupt\n–\nNon-periodic transmit FIFO empty for OUT transactions (applicable when \noperating in pipelined transaction-level with the packet count field programmed \nwith more than one).\n–\nNon-periodic transmit FIFO half-empty for OUT transactions (applicable when \noperating in pipelined transaction-level with the packet count field programmed \nwith more than one).\n3. \nProgram the OTG_FS_HAINTMSK register to unmask the selected channels’ \ninterrupts.\n4. \nProgram the OTG_FS_HCINTMSK register to unmask the transaction-related \ninterrupts of interest given in the host channel interrupt register.\n5. \nProgram the selected channel’s OTG_FS_HCTSIZx register with the total transfer size, \nin bytes, and the expected number of packets, including short packets. The application \nmust program the PID field with the initial data PID (to be used on the first OUT \ntransaction or to be expected from the first IN transaction).\n6. \nProgram the OTG_FS_HCCHARx register of the selected channel with the device’s \nendpoint characteristics, such as type, speed, direction, and so forth. (The channel can \nbe enabled by setting the channel enable bit to 1 only when the application is ready to \ntransmit or receive any packet).\nHalting a channel\nThe application can disable any channel by programming the OTG_FS_HCCHARx register \nwith the CHDIS and CHENA bits set to 1. This enables the OTG_FS host to flush the posted \nrequests (if any) and generates a channel halted interrupt. The application must wait for the \nCHH interrupt in OTG_FS_HCINTx before reallocating the channel for other transactions. \nThe OTG_FS host does not interrupt the transaction that has already been started on the \nUSB.\nBefore disabling a channel, the application must ensure that there is at least one free space \navailable in the non-periodic request queue (when disabling a non-periodic channel) or the \nperiodic request queue (when disabling a periodic channel). The application can simply \nflush the posted requests when the Request queue is full (before disabling the channel), by \nprogramming the OTG_FS_HCCHARx register with the CHDIS bit set to 1, and the CHENA \nbit cleared to 0.\nThe application is expected to disable a channel on any of the following conditions:\n" }, { "page_number": 1341, "page_indices": { "start_index": 2653985, "end_index": 2655697 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1341 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.4 Host programming model", 1340 ], [ 4, "Operational model", 1341 ] ], "page_content": "RM0090 Rev 21\n1341/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n1.\nWhen an STALL, TXERR, BBERR or DTERR interrupt in OTG_FS_HCINTx is received \nfor an IN or OUT channel. The application must be able to receive other interrupts \n(DTERR, Nak, Data, TXERR) for the same channel before receiving the halt.\n2. \nWhen a DISCINT (Disconnect Device) interrupt in OTG_FS_GINTSTS is received. \n(The application is expected to disable all enabled channels).\n3. \nWhen the application aborts a transfer before normal completion.\nOperational model\nThe application must initialize a channel before communicating to the connected device. \nThis section explains the sequence of operation to be performed for different types of USB \ntransactions.\n•\nWriting the transmit FIFO\nThe OTG_FS host automatically writes an entry (OUT request) to the periodic/non-\nperiodic request queue, along with the last word write of a packet. The application must \nensure that at least one free space is available in the periodic/non-periodic request \nqueue before starting to write to the transmit FIFO. The application must always write \nto the transmit FIFO in words. If the packet size is non-word aligned, the application \nmust use padding. The OTG_FS host determines the actual packet size based on the \nprogrammed maximum packet size and transfer size.\nFigure 396. Transmit FIFO write task\n•\nReading the receive FIFO\n \nMPS: Maximum packet size\nStart\nai15673b\nWait for NPTXFE/PTXFE\ninterrupt in\nOTG_FS_GINTSTS\nRead GNPTXSTS/HPTXFSIZ\nregisters for available FIFO\n and queue spaces\n1 MPS or\nLPS FIFO space\navailable?\nWrite 1 packet\ndata to\ntransmit FIFO\nMore packets\nto send?\nDone\nNo\nNo\nYes\nYes\nLPS: Last packet size\n" }, { "page_number": 1342, "page_indices": { "start_index": 2655697, "end_index": 2657189 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1342 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.4 Host programming model", 1340 ], [ 4, "Operational model", 1341 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1342/1757\nRM0090 Rev 21\nThe application must ignore all packet statuses other than IN data packet (bx0010).\nFigure 397. Receive FIFO read task\n•\nBulk and control OUT/SETUP transactions\nA typical bulk or control OUT/SETUP pipelined transaction-level operation is shown in \nFigure 398. See channel 1 (ch_1). Two bulk OUT packets are transmitted. A control \nSETUP transaction operates in the same way but has only one packet. The \nassumptions are:\n–\nThe application is attempting to send two maximum-packet-size packets (transfer \nsize = 1, 024 bytes).\n–\nThe non-periodic transmit FIFO can hold two packets (128 bytes for FS).\n–\nThe non-periodic request queue depth = 4.\n•\nNormal bulk and control OUT/SETUP operations\nThe sequence of operations in (channel 1) is as follows:\na) \nInitialize channel 1\nb) \nWrite the first packet for channel 1\nc) \nAlong with the last word write, the core writes an entry to the non-periodic request \nqueue\nd) \nAs soon as the non-periodic queue becomes non-empty, the core attempts to \nsend an OUT token in the current frame\ne) \nWrite the second (last) packet for channel 1\nf) \nThe core generates the XFRC interrupt as soon as the last transaction is \ncompleted successfully\nRXFLVL\ninterrupt ?\nRead the received \npacket from the \nReceive FIFO\nRead\nOTG_FS_GRXSTSP\nPKTSTS\n0b0010?\n \nYes\nYes\nUnmask RXFLVL\n \ninterrupt\nBCNT > 0?\n \nNo\nMask RXFLVL\ninterrupt\nYes\nUnmask RXFLVL\n \ninterrupt\nNo\nNo\nStart\nai15674\n" }, { "page_number": 1343, "page_indices": { "start_index": 2657189, "end_index": 2658434 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1343 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.4 Host programming model", 1340 ], [ 4, "Operational model", 1341 ] ], "page_content": "RM0090 Rev 21\n1343/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\ng) \nIn response to the XFRC interrupt, de-allocate the channel for other transfers\nh) \nHandling non-ACK responses\nFigure 398. Normal bulk/control OUT/SETUP and bulk/control IN transactions\nThe channel-specific interrupt service routine for bulk and control OUT/SETUP \ntransactions is shown in the following code samples.\n•\nInterrupt service routine for bulk/control OUT/SETUP and bulk/control IN \ntransactions\na) \nBulk/Control OUT/SETUP\nUnmask (NAK/TXERR/STALL/XFRC)\nif (XFRC)\n{\nACK\nHost\nApplication\nDevice\nAHB\nUSB\nOUT\nDATA0\nMPS\n1 \nMPS\n1 \nMPS\nwrite_tx_fifo\n(ch_1)\ninit_reg(ch_1)\nset_ch_en\n(ch_2)\ninit_reg(ch_2)\nwrite_tx_fifo\n(ch_1)\nset_ch_en\n(ch_2)\nch_2\nch_2\nch_1\nch_1\nDe-allocate\n(ch_1)\nIN\nch_2\nch_2\nch_2\nch_1\nACK\nOUT\nset_ch_en\n(ch_2)\nNon-Periodic Request \nQueue\nAssume that this queue \ncan hold 4 entries.\n4\n1\n6\nACK\nDATA0\nIN\nACK\nread_rx_sts\nread_rx_fifo\n1 \nMPS\nset_ch_en\n(ch_2)\n1 \nMPS\nread_rx_stsre\nad_rx_fifo\nread_rx_sts\nDisable\n(ch_2)\n1\n2\n3\n4\n5\n6\n7\nDe-allocate\n(ch_2)\nCHH interrupt\nr\nch_2\n2\n3\n5\n7\n8\n9\n12\n13\nread_rx_sts\n10\n11\nDATA1 \nMPS\nDATA1\nai15675\nRXFLVL interrupt\nXFRC interrupt\nRXFLVL interrupt\nRXFLVL interrupt\nRXFLVL interrupt\nXFRC interrupt\n" }, { "page_number": 1344, "page_indices": { "start_index": 2658434, "end_index": 2659308 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1344 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.4 Host programming model", 1340 ], [ 4, "Operational model", 1341 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1344/1757\nRM0090 Rev 21\nReset Error Count\nMask ACK\nDe-allocate Channel\n}\nelse if (STALL)\n{\nTransfer Done = 1\nUnmask CHH\nDisable Channel\n}\nelse if (NAK or TXERR )\n{\nRewind Buffer Pointers\nUnmask CHH\nDisable Channel\nif (TXERR)\n{\nIncrement Error Count\nUnmask ACK\n}\nelse\n{\nReset Error Count\n}\n}\nelse if (CHH)\n{\nMask CHH\nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\nelse\n{\nRe-initialize Channel\n}\n}\nelse if (ACK)\n{\nReset Error Count\nMask ACK\n}\nThe application is expected to write the data packets into the transmit FIFO as and \nwhen the space is available in the transmit FIFO and the Request queue. The \napplication can make use of the NPTXFE interrupt in OTG_FS_GINTSTS to find the \ntransmit FIFO space.\nb) \nBulk/Control IN\nUnmask (TXERR/XFRC/BBERR/STALL/DTERR)\nif (XFRC)\n{\nReset Error Count\n" }, { "page_number": 1345, "page_indices": { "start_index": 2659308, "end_index": 2660362 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1345 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.4 Host programming model", 1340 ], [ 4, "Operational model", 1341 ] ], "page_content": "RM0090 Rev 21\n1345/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nUnmask CHH\nDisable Channel\nReset Error Count\nMask ACK\n}\nelse if (TXERR or BBERR or STALL)\n{\nUnmask CHH\nDisable Channel\nif (TXERR)\n{\nIncrement Error Count\nUnmask ACK\n}\n}\nelse if (CHH)\n{\nMask CHH\nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\nelse\n{\nRe-initialize Channel\n}\n}\nelse if (ACK)\n{\nReset Error Count\nMask ACK\n}\nelse if (DTERR)\n{\nReset Error Count\n}\nThe application is expected to write the requests as and when the Request queue space is \navailable and until the XFRC interrupt is received.\n•\nBulk and control IN transactions\nA typical bulk or control IN pipelined transaction-level operation is shown in Figure 399. \nSee channel 2 (ch_2). The assumptions are:\n–\nThe application is attempting to receive two maximum-packet-size packets \n(transfer size = 1 024 bytes).\n–\nThe receive FIFO can contain at least one maximum-packet-size packet and two \nstatus words per packet (72 bytes for FS).\n–\nThe non-periodic request queue depth = 4.\n" }, { "page_number": 1346, "page_indices": { "start_index": 2660362, "end_index": 2661753 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1346 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.4 Host programming model", 1340 ], [ 4, "Operational model", 1341 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1346/1757\nRM0090 Rev 21\nFigure 399. Bulk/control IN transactions\nThe sequence of operations is as follows:\na) \nInitialize channel 2.\nb) \nSet the CHENA bit in HCCHAR2 to write an IN request to the non-periodic request \nqueue.\nc) \nThe core attempts to send an IN token after completing the current OUT \ntransaction.\nd) \nThe core generates an RXFLVL interrupt as soon as the received packet is written \nto the receive FIFO.\ne) \nIn response to the RXFLVL interrupt, mask the RXFLVL interrupt and read the \nreceived packet status to determine the number of bytes received, then read the \nreceive FIFO accordingly. Following this, unmask the RXFLVL interrupt.\nACK\nHost\nApplication\nDevice\nAHB\nUSB\nOUT\nDATA0\nMPS\n1 \nMPS\n1 \nMPS\nwrite_tx_fifo\n(ch_1)\ninit_reg(ch_1)\nset_ch_en\n(ch_2)\ninit_reg(ch_2)\nwrite_tx_fifo\n(ch_1)\nset_ch_en\n(ch_2)\nch_2\nch_2\nch_1\nch_1\nDe-allocate\n(ch_1)\nIN\nch_2\nch_2\nch_2\nch_1\nACK\nOUT\nset_ch_en\n(ch_2)\nNon-Periodic Request \nQueue\nAssume that this queue \ncan hold 4 entries.\n4\n1\n6\nACK\nDATA0\nIN\nACK\nread_rx_sts\nread_rx_fifo\n1 \nMPS\nset_ch_en\n(ch_2)\n1 \nMPS\nread_rx_stsre\nad_rx_fifo\nread_rx_sts\nDisable\n(ch_2)\n1\n2\n3\n4\n5\n6\n7\nDe-allocate\n(ch_2)\nCHH interrupt\nr\nch_2\n2\n3\n5\n7\n8\n9\n12\n13\nread_rx_sts\n10\n11\nDATA1 \nMPS\nDATA1\nai15675\nRXFLVL interrupt\nXFRC interrupt\nRXFLVL interrupt\nRXFLVL interrupt\nRXFLVL interrupt\nXFRC interrupt\n" }, { "page_number": 1347, "page_indices": { "start_index": 2661753, "end_index": 2664301 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1347 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.4 Host programming model", 1340 ], [ 4, "Operational model", 1341 ] ], "page_content": "RM0090 Rev 21\n1347/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nf) \nThe core generates the RXFLVL interrupt for the transfer completion status entry \nin the receive FIFO.\ng) \nThe application must read and ignore the receive packet status when the receive \npacket status is not an IN data packet (PKTSTS in GRXSTSR ≠0b0010).\nh) \nThe core generates the XFRC interrupt as soon as the receive packet status is \nread.\ni) \nIn response to the XFRC interrupt, disable the channel and stop writing the \nOTG_FS_HCCHAR2 register for further requests. The core writes a channel \ndisable request to the non-periodic request queue as soon as the \nOTG_FS_HCCHAR2 register is written.\nj) \nThe core generates the RXFLVL interrupt as soon as the halt status is written to \nthe receive FIFO.\nk) \nRead and ignore the receive packet status.\nl) \nThe core generates a CHH interrupt as soon as the halt status is popped from the \nreceive FIFO.\nm) In response to the CHH interrupt, de-allocate the channel for other transfers.\nn) \nHandling non-ACK responses\n•\nControl transactions\nSetup, Data, and Status stages of a control transfer must be performed as three \nseparate transfers. Setup-, Data- or Status-stage OUT transactions are performed \nsimilarly to the bulk OUT transactions explained previously. Data- or Status-stage IN \ntransactions are performed similarly to the bulk IN transactions explained previously. \nFor all three stages, the application is expected to set the EPTYP field in \nOTG_FS_HCCHAR1 to Control. During the Setup stage, the application is expected to \nset the PID field in OTG_FS_HCTSIZ1 to SETUP.\n•\nInterrupt OUT transactions\nA typical interrupt OUT operation is shown in Figure 400. The assumptions are:\n–\nThe application is attempting to send one packet in every frame (up to 1 maximum \npacket size), starting with the odd frame (transfer size = 1 024 bytes)\n–\nThe periodic transmit FIFO can hold one packet (1 KB)\n–\nPeriodic request queue depth = 4\nThe sequence of operations is as follows:\na) \nInitialize and enable channel 1. The application must set the ODDFRM bit in \nOTG_FS_HCCHAR1.\nb) \nWrite the first packet for channel 1. \nc) \nAlong with the last word write of each packet, the OTG_FS host writes an entry to \nthe periodic request queue.\nd) \nThe OTG_FS host attempts to send an OUT token in the next (odd) frame.\ne) \nThe OTG_FS host generates an XFRC interrupt as soon as the last packet is \ntransmitted successfully.\nf) \nIn response to the XFRC interrupt, reinitialize the channel for the next transfer.\n" }, { "page_number": 1348, "page_indices": { "start_index": 2664301, "end_index": 2665230 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1348 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.4 Host programming model", 1340 ], [ 4, "Operational model", 1341 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1348/1757\nRM0090 Rev 21\nFigure 400. Normal interrupt OUT/IN transactions\n•\nInterrupt service routine for interrupt OUT/IN transactions\na) \nInterrupt OUT\nUnmask (NAK/TXERR/STALL/XFRC/FRMOR)\nif (XFRC)\n{\nReset Error Count\nMask ACK\nDe-allocate Channel\n}\nelse\nif (STALL or FRMOR)\n{\nMask ACK\nUnmask CHH\nHost\nApplication\nDevice\nAHB\nUSB\nOUT\nDATA0\nMPS\n1 \nMPS\n1 \nMPS\nwrite_tx_fifo\n(ch_1)\ninit_reg(ch_1)\nset_ch_en\n(ch_2)\ninit_reg(ch_2)\nwrite_tx_fifo\n(ch_1)\nIN\nOUT\nDATA1\nMPS\nPeriodic Request Queue\nAssume that this queue \ncan hold 4 entries.\n1\n5\nDATA0\nIN\nRXFLVL interrupt\n1 \nMPS\nread_rx_sts\nread_rx_fifo\nread_rx_sts\n1\n2\n3\n4\n6\n2\n3\n6\n7\n8\n9\nOdd\n(micro)\nframe\nEven\n(micro)\nframe\ninit_reg(ch_1)\nset_ch_en\n(ch_2)\ninit_reg(ch_2)\nwrite_tx_fifo\n(ch_1)\ninit_reg(ch_1)\n1 \nMPS\nDATA1\n5\n4\nACK\nACK\nACK\nch_1\nch_2\nch_2\nch_1\nai15676\nRXFLVL interrupt\nXFRC interrupt\nXFRC interrupt\nXFRC interrupt\n" }, { "page_number": 1349, "page_indices": { "start_index": 2665230, "end_index": 2665983 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1349 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.4 Host programming model", 1340 ], [ 4, "Operational model", 1341 ] ], "page_content": "RM0090 Rev 21\n1349/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nDisable Channel\nif (STALL)\n{\nTransfer Done = 1\n}\n}\nelse\nif (NAK or TXERR)\n{\nRewind Buffer Pointers\nReset Error Count\nMask ACK\nUnmask CHH\nDisable Channel\n}\nelse\nif (CHH)\n{\nMask CHH\nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\nelse\n{\nRe-initialize Channel (in next b_interval - 1 Frame)\n}\n}\nelse\nif (ACK)\n{\nReset Error Count\nMask ACK\n}\nThe application uses the NPTXFE interrupt in OTG_FS_GINTSTS to find the transmit \nFIFO space.\nb) \nInterrupt IN\nUnmask (NAK/TXERR/XFRC/BBERR/STALL/FRMOR/DTERR)\nif (XFRC)\n{\nReset Error Count\nMask ACK\nif (OTG_FS_HCTSIZx.PKTCNT == 0)\n{\nDe-allocate Channel\n}\nelse\n{\nTransfer Done = 1\nUnmask CHH\nDisable Channel\n" }, { "page_number": 1350, "page_indices": { "start_index": 2665983, "end_index": 2666551 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1350 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.4 Host programming model", 1340 ], [ 4, "Operational model", 1341 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1350/1757\nRM0090 Rev 21\n}\n}\nelse\nif (STALL or FRMOR or NAK or DTERR or BBERR)\n{\nMask ACK\nUnmask CHH\nDisable Channel\n \nif (STALL or BBERR)\n{\nReset Error Count\nTransfer Done = 1\n}\nelse\nif (!FRMOR)\n{\nReset Error Count\n}\n}\nelse\nif (TXERR)\n{\nIncrement Error Count\nUnmask ACK\nUnmask CHH\nDisable Channel\n}\nelse\nif (CHH)\n{\nMask CHH\n \nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\n \nelse\n \nRe-initialize Channel (in next b_interval - 1 /Frame)\n}\n}\nelse\nif (ACK)\n{\nReset Error Count\nMask ACK\n" }, { "page_number": 1351, "page_indices": { "start_index": 2666551, "end_index": 2668454 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1351 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.4 Host programming model", 1340 ], [ 4, "Operational model", 1341 ] ], "page_content": "RM0090 Rev 21\n1351/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n}\n•\nInterrupt IN transactions\nThe assumptions are:\n–\nThe application is attempting to receive one packet (up to 1 maximum packet size) \nin every frame, starting with odd (transfer size = 1 024 bytes).\n–\nThe receive FIFO can hold at least one maximum-packet-size packet and two \nstatus words per packet (1 031 bytes).\n–\nPeriodic request queue depth = 4.\n•\nNormal interrupt IN operation\nThe sequence of operations is as follows:\na) \nInitialize channel 2. The application must set the ODDFRM bit in \nOTG_FS_HCCHAR2.\nb) \nSet the CHENA bit in OTG_FS_HCCHAR2 to write an IN request to the periodic \nrequest queue. \nc) \nThe OTG_FS host writes an IN request to the periodic request queue for each \nOTG_FS_HCCHAR2 register write with the CHENA bit set.\nd) \nThe OTG_FS host attempts to send an IN token in the next (odd) frame.\ne) \nAs soon as the IN packet is received and written to the receive FIFO, the OTG_FS \nhost generates an RXFLVL interrupt.\nf) \nIn response to the RXFLVL interrupt, read the received packet status to determine \nthe number of bytes received, then read the receive FIFO accordingly. The \napplication must mask the RXFLVL interrupt before reading the receive FIFO, and \nunmask after reading the entire packet.\ng) \nThe core generates the RXFLVL interrupt for the transfer completion status entry \nin the receive FIFO. The application must read and ignore the receive packet \nstatus when the receive packet status is not an IN data packet (PKTSTS in \nGRXSTSR ≠0b0010).\nh) \nThe core generates an XFRC interrupt as soon as the receive packet status is \nread.\ni) \nIn response to the XFRC interrupt, read the PKTCNT field in OTG_FS_HCTSIZ2. \nIf the PKTCNT bit in OTG_FS_HCTSIZ2 is not equal to 0, disable the channel \nbefore re-initializing the channel for the next transfer, if any). If PKTCNT bit in \n" }, { "page_number": 1352, "page_indices": { "start_index": 2668454, "end_index": 2669638 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1352 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.4 Host programming model", 1340 ], [ 4, "Operational model", 1341 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1352/1757\nRM0090 Rev 21\nOTG_FS_HCTSIZ2 = 0, reinitialize the channel for the next transfer. This time, the \napplication must reset the ODDFRM bit in OTG_FS_HCCHAR2.\n•\nIsochronous OUT transactions\nA typical isochronous OUT operation is shown in Figure 401. The assumptions are:\n–\nThe application is attempting to send one packet every frame (up to 1 maximum \npacket size), starting with an odd frame. (transfer size = 1 024 bytes).\n–\nThe periodic transmit FIFO can hold one packet (1 KB).\n–\nPeriodic request queue depth = 4.\nThe sequence of operations is as follows:\na) \nInitialize and enable channel 1. The application must set the ODDFRM bit in \nOTG_FS_HCCHAR1.\nb) \nWrite the first packet for channel 1.\nc) \nAlong with the last word write of each packet, the OTG_FS host writes an entry to \nthe periodic request queue.\nd) \nThe OTG_FS host attempts to send the OUT token in the next frame (odd).\ne) \nThe OTG_FS host generates the XFRC interrupt as soon as the last packet is \ntransmitted successfully.\nf) \nIn response to the XFRC interrupt, reinitialize the channel for the next transfer.\ng) \nHandling non-ACK responses\n" }, { "page_number": 1353, "page_indices": { "start_index": 2669638, "end_index": 2670544 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1353 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.4 Host programming model", 1340 ], [ 4, "Operational model", 1341 ] ], "page_content": "RM0090 Rev 21\n1353/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nFigure 401. Normal isochronous OUT/IN transactions\n•\nInterrupt service routine for isochronous OUT/IN transactions\nCode sample: Isochronous OUT\nUnmask (FRMOR/XFRC)\nif (XFRC)\n{\nDe-allocate Channel\n}\nelse\nif (FRMOR)\n{\nUnmask CHH\nDisable Channel\n}\nHost\nApplication\nDevice\nAHB\nUSB\nOUT\nDATA0\nMPS\n1 \nMPS\n1 \nMPS\nwrite_tx_fifo\n(ch_1)\ninit_reg(ch_1)\nset_ch_en\n(ch_2)\ninit_reg(ch_2)\nwrite_tx_fifo\n(ch_1)\nIN\nOUT\nDATA1\nMPS\nPeriodic Request Queue\nAssume that this queue \ncan hold 4 entries.\n1\n5\nDATA0\nIN\nRXFLVL interrupt\n1 \nMPS\nread_rx_sts\nread_rx_fifo\nread_rx_sts\n1\n2\n3\n4\n6\n2\n3\n6\n7\n8\n9\nOdd\n(micro)\nframe\nEven\n(micro)\nframe\ninit_reg(ch_1)\nset_ch_en\n(ch_2)\ninit_reg(ch_2)\nwrite_tx_fifo\n(ch_1)\ninit_reg(ch_1)\n1 \nMPS\nDATA1\n5\n4\nACK\nACK\nACK\nch_1\nch_2\nch_2\nch_1\nai15676\nRXFLVL interrupt\nXFRC interrupt\nXFRC interrupt\nXFRC interrupt\n" }, { "page_number": 1354, "page_indices": { "start_index": 2670544, "end_index": 2671084 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1354 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.4 Host programming model", 1340 ], [ 4, "Operational model", 1341 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1354/1757\nRM0090 Rev 21\nelse\nif (CHH)\n{\nMask CHH\nDe-allocate Channel\n}\nCode sample: Isochronous IN\nUnmask (TXERR/XFRC/FRMOR/BBERR)\nif (XFRC or FRMOR)\n{\nif (XFRC and (OTG_FS_HCTSIZx.PKTCNT == 0))\n{\nReset Error Count\nDe-allocate Channel\n}\nelse\n{\nUnmask CHH\nDisable Channel\n}\n}\nelse\nif (TXERR or BBERR)\n{\nIncrement Error Count\nUnmask CHH\nDisable Channel\n}\nelse\nif (CHH)\n{\nMask CHH\nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\nelse\n{\nRe-initialize Channel\n}\n}\n" }, { "page_number": 1355, "page_indices": { "start_index": 2671084, "end_index": 2674128 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1355 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.4 Host programming model", 1340 ], [ 4, "Operational model", 1341 ] ], "page_content": "RM0090 Rev 21\n1355/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n \n•\nIsochronous IN transactions\nThe assumptions are:\n–\nThe application is attempting to receive one packet (up to 1 maximum packet size) \nin every frame starting with the next odd frame (transfer size = 1 024 bytes).\n–\nThe receive FIFO can hold at least one maximum-packet-size packet and two \nstatus word per packet (1 031 bytes).\n–\nPeriodic request queue depth = 4.\nThe sequence of operations is as follows:\na) \nInitialize channel 2. The application must set the ODDFRM bit in \nOTG_FS_HCCHAR2.\nb) \nSet the CHENA bit in OTG_FS_HCCHAR2 to write an IN request to the periodic \nrequest queue. \nc) \nThe OTG_FS host writes an IN request to the periodic request queue for each \nOTG_FS_HCCHAR2 register write with the CHENA bit set.\nd) \nThe OTG_FS host attempts to send an IN token in the next odd frame.\ne) \nAs soon as the IN packet is received and written to the receive FIFO, the OTG_FS \nhost generates an RXFLVL interrupt.\nf) \nIn response to the RXFLVL interrupt, read the received packet status to determine \nthe number of bytes received, then read the receive FIFO accordingly. The \napplication must mask the RXFLVL interrupt before reading the receive FIFO, and \nunmask it after reading the entire packet.\ng) \nThe core generates an RXFLVL interrupt for the transfer completion status entry in \nthe receive FIFO. This time, the application must read and ignore the receive \npacket status when the receive packet status is not an IN data packet (PKTSTS bit \nin OTG_FS_GRXSTSR ≠0b0010).\nh) \nThe core generates an XFRC interrupt as soon as the receive packet status is \nread.\ni) \nIn response to the XFRC interrupt, read the PKTCNT field in OTG_FS_HCTSIZ2. \nIf PKTCNT ≠0 in OTG_FS_HCTSIZ2, disable the channel before re-initializing the \nchannel for the next transfer, if any. If PKTCNT = 0 in OTG_FS_HCTSIZ2, \nreinitialize the channel for the next transfer. This time, the application must reset \nthe ODDFRM bit in OTG_FS_HCCHAR2.\n•\nSelecting the queue depth\nChoose the periodic and non-periodic request queue depths carefully to match the \nnumber of periodic/non-periodic endpoints accessed.\nThe non-periodic request queue depth affects the performance of non-periodic \ntransfers. The deeper the queue (along with sufficient FIFO size), the more often the \ncore is able to pipeline non-periodic transfers. If the queue size is small, the core is \nable to put in new requests only when the queue space is freed up.\nThe core’s periodic request queue depth is critical to perform periodic transfers as \nscheduled. Select the periodic queue depth, based on the number of periodic transfers \nscheduled in a microframe. If the periodic request queue depth is smaller than the \nperiodic transfers scheduled in a microframe, a frame overrun condition occurs.\n•\nHandling babble conditions\nOTG_FS controller handles two cases of babble: packet babble and port babble. \nPacket babble occurs if the device sends more data than the maximum packet size for \n" }, { "page_number": 1356, "page_indices": { "start_index": 2674128, "end_index": 2676733 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1356 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.5 Device programming model", 1356 ], [ 4, "Endpoint initialization on USB reset", 1356 ], [ 4, "Endpoint initialization on enumeration completion", 1356 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1356/1757\nRM0090 Rev 21\nthe channel. Port babble occurs if the core continues to receive data from the device at \nEOF2 (the end of frame 2, which is very close to SOF).\nWhen OTG_FS controller detects a packet babble, it stops writing data into the Rx \nbuffer and waits for the end of packet (EOP). When it detects an EOP, it flushes already \nwritten data in the Rx buffer and generates a Babble interrupt to the application.\nWhen OTG_FS controller detects a port babble, it flushes the RxFIFO and disables the \nport. The core then generates a Port disabled interrupt (HPRTINT in \nOTG_FS_GINTSTS, PENCHNG in OTG_FS_HPRT). On receiving this interrupt, the \napplication must determine that this is not due to an overcurrent condition (another \ncause of the Port Disabled interrupt) by checking POCA in OTG_FS_HPRT, then \nperform a soft reset. The core does not send any more tokens after it has detected a \nport babble condition.\n34.17.5 \nDevice programming model\nEndpoint initialization on USB reset\n1.\nSet the NAK bit for all OUT endpoints\n–\nSNAK = 1 in OTG_FS_DOEPCTLx (for all OUT endpoints)\n2. \nUnmask the following interrupt bits\n–\nINEP0 = 1 in OTG_FS_DAINTMSK (control 0 IN endpoint)\n–\nOUTEP0 = 1 in OTG_FS_DAINTMSK (control 0 OUT endpoint)\n–\nSTUP = 1 in DOEPMSK\n–\nXFRC = 1 in DOEPMSK\n–\nXFRC = 1 in DIEPMSK\n–\nTOC = 1 in DIEPMSK\n3. \nSet up the Data FIFO RAM for each of the FIFOs\n–\nProgram the OTG_FS_GRXFSIZ register, to be able to receive control OUT data \nand setup data. If thresholding is not enabled, at a minimum, this must be equal to \n1 max packet size of control endpoint 0 + 2 words (for the status of the control \nOUT data packet) + 10 words (for setup packets).\n–\nProgram the OTG_FS_TX0FSIZ register (depending on the FIFO number chosen) \nto be able to transmit control IN data. At a minimum, this must be equal to 1 max \npacket size of control endpoint 0.\n4. \nProgram the following fields in the endpoint-specific registers for control OUT endpoint \n0 to receive a SETUP packet\n–\nSTUPCNT = 3 in OTG_FS_DOEPTSIZ0 (to receive up to 3 back-to-back SETUP \npackets)\nAt this point, all initialization required to receive SETUP packets is done.\nEndpoint initialization on enumeration completion\n1.\nOn the Enumeration Done interrupt (ENUMDNE in OTG_FS_GINTSTS), read the \nOTG_FS_DSTS register to determine the enumeration speed.\n2. \nProgram the MPSIZ field in OTG_FS_DIEPCTL0 to set the maximum packet size. This \nstep configures control endpoint 0. The maximum packet size for a control endpoint \ndepends on the enumeration speed.\n" }, { "page_number": 1357, "page_indices": { "start_index": 2676733, "end_index": 2679071 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1357 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.5 Device programming model", 1356 ], [ 4, "Endpoint initialization on SetAddress command", 1357 ], [ 4, "Endpoint initialization on SetConfiguration/SetInterface command", 1357 ], [ 4, "Endpoint activation", 1357 ] ], "page_content": "RM0090 Rev 21\n1357/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nAt this point, the device is ready to receive SOF packets and is configured to perform control \ntransfers on control endpoint 0.\nEndpoint initialization on SetAddress command\nThis section describes what the application must do when it receives a SetAddress \ncommand in a SETUP packet.\n1.\nProgram the OTG_FS_DCFG register with the device address received in the \nSetAddress command\n2. \nProgram the core to send out a status IN packet\nEndpoint initialization on SetConfiguration/SetInterface command\nThis section describes what the application must do when it receives a SetConfiguration or \nSetInterface command in a SETUP packet.\n1.\nWhen a SetConfiguration command is received, the application must program the \nendpoint registers to configure them with the characteristics of the valid endpoints in \nthe new configuration.\n2. \nWhen a SetInterface command is received, the application must program the endpoint \nregisters of the endpoints affected by this command.\n3. \nSome endpoints that were active in the prior configuration or alternate setting are not \nvalid in the new configuration or alternate setting. These invalid endpoints must be \ndeactivated.\n4. \nUnmask the interrupt for each active endpoint and mask the interrupts for all inactive \nendpoints in the OTG_FS_DAINTMSK register.\n5. \nSet up the Data FIFO RAM for each FIFO.\n6. \nAfter all required endpoints are configured; the application must program the core to \nsend a status IN packet.\nAt this point, the device core is configured to receive and transmit any type of data packet.\nEndpoint activation\nThis section describes the steps required to activate a device endpoint or to configure an \nexisting device endpoint to a new type.\n1.\nProgram the characteristics of the required endpoint into the following fields of the \nOTG_FS_DIEPCTLx register (for IN or bidirectional endpoints) or the \nOTG_FS_DOEPCTLx register (for OUT or bidirectional endpoints).\n–\nMaximum packet size\n–\nUSB active endpoint = 1\n–\nEndpoint start data toggle (for interrupt and bulk endpoints)\n–\nEndpoint type\n–\nTxFIFO number\n2. \nOnce the endpoint is activated, the core starts decoding the tokens addressed to that \nendpoint and sends out a valid handshake for each valid token received for the \nendpoint.\n" }, { "page_number": 1358, "page_indices": { "start_index": 2679071, "end_index": 2681622 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1358 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.5 Device programming model", 1356 ], [ 4, "Endpoint deactivation", 1358 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "SETUP and OUT data transfers", 1358 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1358/1757\nRM0090 Rev 21\nEndpoint deactivation\nThis section describes the steps required to deactivate an existing endpoint.\n1.\nIn the endpoint to be deactivated, clear the USB active endpoint bit in the \nOTG_FS_DIEPCTLx register (for IN or bidirectional endpoints) or the \nOTG_FS_DOEPCTLx register (for OUT or bidirectional endpoints).\n2. \nOnce the endpoint is deactivated, the core ignores tokens addressed to that endpoint, \nwhich results in a timeout on the USB.\nNote:\nThe application must meet the following conditions to set up the device core to handle \ntraffic:\nNPTXFEM and RXFLVLM in the OTG_FS_GINTMSK register must be cleared.\n34.17.6 \nOperational model\nSETUP and OUT data transfers\nThis section describes the internal data flow and application-level operations during data \nOUT transfers and SETUP transactions.\n•\nPacket read\nThis section describes how to read packets (OUT data and SETUP packets) from the \nreceive FIFO.\n1.\nOn catching an RXFLVL interrupt (OTG_FS_GINTSTS register), the application must \nread the Receive status pop register (OTG_FS_GRXSTSP).\n2. \nThe application can mask the RXFLVL interrupt (in OTG_FS_GINTSTS) by writing to \nRXFLVL = 0 (in OTG_FS_GINTMSK), until it has read the packet from the receive \nFIFO.\n3. \nIf the received packet’s byte count is not 0, the byte count amount of data is popped \nfrom the receive Data FIFO and stored in memory. If the received packet byte count is \n0, no data is popped from the receive data FIFO.\n4. \nThe receive FIFO’s packet status readout indicates one of the following:\na) \nGlobal OUT NAK pattern:\nPKTSTS = Global OUT NAK, BCNT = 0x000, EPNUM = Don’t Care (0x0), \nDPID = Don’t Care (0b00).\nThese data indicate that the global OUT NAK bit has taken effect.\nb) \nSETUP packet pattern:\nPKTSTS = SETUP, BCNT = 0x008, EPNUM = Control EP Num, DPID = D0. \nThese data indicate that a SETUP packet for the specified endpoint is now \navailable for reading from the receive FIFO.\nc) \nSetup stage done pattern:\nPKTSTS = Setup Stage Done, BCNT = 0x0, EPNUM = Control EP Num, \nDPID = Don’t Care (0b00).\nThese data indicate that the Setup stage for the specified endpoint has completed \nand the Data stage has started. After this entry is popped from the receive FIFO, \nthe core asserts a Setup interrupt on the specified control OUT endpoint.\nd) \nData OUT packet pattern:\nPKTSTS = DataOUT, BCNT = size of the received data OUT packet (0 ≤BCNT \n≤1 024), EPNUM = EPNUM on which the packet was received, DPID = Actual \nData PID.\n" }, { "page_number": 1359, "page_indices": { "start_index": 2681622, "end_index": 2683581 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1359 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "SETUP and OUT data transfers", 1358 ] ], "page_content": "RM0090 Rev 21\n1359/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\ne) \nData transfer completed pattern:\nPKTSTS = Data OUT Transfer Done, BCNT = 0x0, EPNUM = OUT EP Num \non which the data transfer is complete, DPID = Don’t Care (0b00).\nThese data indicate that an OUT data transfer for the specified OUT endpoint has \ncompleted. After this entry is popped from the receive FIFO, the core asserts a \nTransfer Completed interrupt on the specified OUT endpoint.\n5. \nAfter the data payload is popped from the receive FIFO, the RXFLVL interrupt \n(OTG_FS_GINTSTS) must be unmasked.\n6. \nSteps 1–5 are repeated every time the application detects assertion of the interrupt line \ndue to RXFLVL in OTG_FS_GINTSTS. Reading an empty receive FIFO can result in \nundefined core behavior.\nFigure 402 provides a flowchart of the above procedure.\nFigure 402. Receive FIFO packet read\n•\nSETUP transactions\nThis section describes how the core handles SETUP packets and the application’s \nsequence for handling SETUP transactions.\n•\nApplication requirements\n1.\nTo receive a SETUP packet, the STUPCNT field (OTG_FS_DOEPTSIZx) in a control \nOUT endpoint must be programmed to a non-zero value. When the application \nprograms the STUPCNT field to a non-zero value, the core receives SETUP packets \nand writes them to the receive FIFO, irrespective of the NAK status and EPENA bit \nsetting in OTG_FS_DOEPCTLx. The STUPCNT field is decremented every time the \ncontrol endpoint receives a SETUP packet. If the STUPCNT field is not programmed to \na proper value before receiving a SETUP packet, the core still receives the SETUP \npacket and decrements the STUPCNT field, but the application may not be able to \nword_cnt =\nBCNT[11:2] +\nC\n \n(BCNT[1] | BCNT[1])\nrcv_out_pkt()\nrd_data = rd_reg (OTG_FS_GRXSTSP);\nmem[0: word_cnt – 1] =\nrd_rxfifo(rd_data.EPNUM, \nword_cnt)\nN\nrd_data.BCNT = 0\n \nwait until RXFLVL in OTG_FS_GINTSTSG\npacket \nstore in \nmemory\nY\nai15677b\n" }, { "page_number": 1360, "page_indices": { "start_index": 2683581, "end_index": 2686326 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1360 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "SETUP and OUT data transfers", 1358 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1360/1757\nRM0090 Rev 21\ndetermine the correct number of SETUP packets received in the Setup stage of a \ncontrol transfer.\n–\nSTUPCNT = 3 in OTG_FS_DOEPTSIZx\n2. \nThe application must always allocate some extra space in the Receive data FIFO, to be \nable to receive up to three SETUP packets on a control endpoint.\n–\nThe space to be reserved is 10 words. Three words are required for the first \nSETUP packet, 1 word is required for the Setup stage done word and 6 words are \nrequired to store two extra SETUP packets among all control endpoints.\n–\n3 words per SETUP packet are required to store 8 bytes of SETUP data and 4 \nbytes of SETUP status (Setup packet pattern). The core reserves this space in the \nreceive data FIFO to write SETUP data only, and never uses this space for data \npackets.\n3. \nThe application must read the 2 words of the SETUP packet from the receive FIFO. \n4. \nThe application must read and discard the Setup stage done word from the receive \nFIFO.\n•\nInternal data flow\n1.\nWhen a SETUP packet is received, the core writes the received data to the receive \nFIFO, without checking for available space in the receive FIFO and irrespective of the \nendpoint’s NAK and STALL bit settings.\n–\nThe core internally sets the IN NAK and OUT NAK bits for the control IN/OUT \nendpoints on which the SETUP packet was received.\n2. \nFor every SETUP packet received on the USB, 3 words of data are written to the \nreceive FIFO, and the STUPCNT field is decremented by 1.\n–\nThe first word contains control information used internally by the core\n–\nThe second word contains the first 4 bytes of the SETUP command\n–\nThe third word contains the last 4 bytes of the SETUP command\n3. \nWhen the Setup stage changes to a Data IN/OUT stage, the core writes an entry \n(Setup stage done word) to the receive FIFO, indicating the completion of the Setup \nstage.\n4. \nOn the AHB side, SETUP packets are emptied by the application.\n5. \nWhen the application pops the Setup stage done word from the receive FIFO, the core \ninterrupts the application with an STUP interrupt (OTG_FS_DOEPINTx), indicating it \ncan process the received SETUP packet.\n–\nThe core clears the endpoint enable bit for control OUT endpoints.\n•\nApplication programming sequence\n1.\nProgram the OTG_FS_DOEPTSIZx register.\n–\nSTUPCNT = 3\n2. \nWait for the RXFLVL interrupt (OTG_FS_GINTSTS) and empty the data packets from \nthe receive FIFO.\n3. \nAssertion of the STUP interrupt (OTG_FS_DOEPINTx) marks a successful completion \nof the SETUP Data Transfer.\n–\nOn this interrupt, the application must read the OTG_FS_DOEPTSIZx register to \ndetermine the number of SETUP packets received and process the last received \nSETUP packet.\n" }, { "page_number": 1361, "page_indices": { "start_index": 2686326, "end_index": 2688063 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1361 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "SETUP and OUT data transfers", 1358 ] ], "page_content": "RM0090 Rev 21\n1361/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nFigure 403. Processing a SETUP packet\n•\nHandling more than three back-to-back SETUP packets\nPer the USB 2.0 specification, normally, during a SETUP packet error, a host does not send \nmore than three back-to-back SETUP packets to the same endpoint. However, the USB 2.0 \nspecification does not limit the number of back-to-back SETUP packets a host can send to \nthe same endpoint. When this condition occurs, the OTG_FS controller generates an \ninterrupt (B2BSTUP in OTG_FS_DOEPINTx).\n•\nSetting the global OUT NAK\nInternal data flow\n1.\nWhen the application sets the Global OUT NAK (SGONAK bit in OTG_FS_DCTL), the \ncore stops writing data, except SETUP packets, to the receive FIFO. Irrespective of the \nspace availability in the receive FIFO, non-isochronous OUT tokens receive a NAK \nhandshake response, and the core ignores isochronous OUT data packets\n2. \nThe core writes the Global OUT NAK pattern to the receive FIFO. The application must \nreserve enough receive FIFO space to write this data pattern.\n3. \nWhen the application pops the Global OUT NAK pattern word from the receive FIFO, \nthe core sets the GONAKEFF interrupt (OTG_FS_GINTSTS).\n4. \nOnce the application detects this interrupt, it can assume that the core is in Global OUT \nNAK mode. The application can clear this interrupt by clearing the SGONAK bit in \nOTG_FS_DCTL.\nWait for STUP in OTG_FS_DOEPINTx\nrem_supcnt = \nrd_reg(DOEPTSIZx)\nsetup_cmd[31:0] = mem[4 – 2 * rem_supcnt]\nsetup_cmd[63:32] = mem[5 – 2 * rem_supcnt]\nctrl-rd/wr/2 stage\nFind setup cmd type\nWrite\n2-stage\nRead\nsetup_np_in_pkt\nStatus IN phase\nrcv_out_pkt\nData OUT phase\nsetup_np_in_pkt\nData IN phase\nai15678\n" }, { "page_number": 1362, "page_indices": { "start_index": 2688063, "end_index": 2690253 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1362 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "SETUP and OUT data transfers", 1358 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1362/1757\nRM0090 Rev 21\nApplication programming sequence\n1.\nTo stop receiving any kind of data in the receive FIFO, the application must set the \nGlobal OUT NAK bit by programming the following field:\n–\nSGONAK = 1 in OTG_FS_DCTL\n2. \nWait for the assertion of the GONAKEFF interrupt in OTG_FS_GINTSTS. When \nasserted, this interrupt indicates that the core has stopped receiving any type of data \nexcept SETUP packets.\n3. \nThe application can receive valid OUT packets after it has set SGONAK in \nOTG_FS_DCTL and before the core asserts the GONAKEFF interrupt \n(OTG_FS_GINTSTS).\n4. \nThe application can temporarily mask this interrupt by writing to the GINAKEFFM bit in \nthe OTG_FS_GINTMSK register.\n–\nGINAKEFFM = 0 in the OTG_FS_GINTMSK register \n5. \nWhenever the application is ready to exit the Global OUT NAK mode, it must clear the \nSGONAK bit in OTG_FS_DCTL. This also clears the GONAKEFF interrupt \n(OTG_FS_GINTSTS).\n–\nOTG_FS_DCTL = 1 in CGONAK\n6. \nIf the application has masked this interrupt earlier, it must be unmasked as follows:\n–\nGINAKEFFM = 1 in GINTMSK\n•\nDisabling an OUT endpoint\nThe application must use this sequence to disable an OUT endpoint that it has enabled.\nApplication programming sequence\n1.\nBefore disabling any OUT endpoint, the application must enable Global OUT NAK \nmode in the core.\n–\nSGONAK = 1 in OTG_FS_DCTL\n2. \nWait for the GONAKEFF interrupt (OTG_FS_GINTSTS)\n3. \nDisable the required OUT endpoint by programming the following fields:\n–\nEPDIS = 1 in OTG_FS_DOEPCTLx\n–\nSNAK = 1 in OTG_FS_DOEPCTLx\n4. \nWait for the EPDISD interrupt (OTG_FS_DOEPINTx), which indicates that the OUT \nendpoint is completely disabled. When the EPDISD interrupt is asserted, the core also \nclears the following bits:\n–\nEPDIS = 0 in OTG_FS_DOEPCTLx\n–\nEPENA = 0 in OTG_FS_DOEPCTLx\n5. \nThe application must clear the Global OUT NAK bit to start receiving data from other \nnon-disabled OUT endpoints.\n–\nSGONAK = 0 in OTG_FS_DCTL\n•\nTransfer Stop Programming for OUT endpoints\nThe application must use the following programing sequence to stop any transfers (because \nof an interrupt from the host, typically a reset).\n" }, { "page_number": 1363, "page_indices": { "start_index": 2690253, "end_index": 2692931 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1363 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "SETUP and OUT data transfers", 1358 ] ], "page_content": "RM0090 Rev 21\n1363/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nSequence of operations:\n1.\nEnable all OUT endpoints by setting\n–\nEPENA = 1 in all OTG_FS_DOEPCTLx registers.\n2. \nFlush the RxFIFO as follows\n–\nPoll OTG_FS_GRSTCTL.AHBIDL until it is 1. This indicates that AHB master is \nidle.\n–\nPerform read modify write operation on OTG_FS_GRSTCTL.RXFFLSH =1\n–\nPoll OTG_FS_GRSTCTL.RXFFLSH until it is 0, but also using a timeout of less \nthan 10 milli-seconds (corresponds to minimum reset signaling duration). If 0 is \nseen before the timeout, then the RxFIFO flush is successful. If at the moment the \ntimeout occurs, there is still a 1, (this may be due to a packet on EP0 coming from \nthe host) then go back (once only) to the previous step (“Perform read modify write \noperation”).\n3. \nBefore disabling any OUT endpoint, the application must enable Global OUT NAK \nmode in the core, according to the instructions in “Setting the global OUT NAK on \npage 1361”. This ensures that data in the RxFIFO is sent to the application \nsuccessfully. Set SGONAK = 1 in OTG_FS_DCTL\n4. \nWait for the GONAKEFF interrupt (OTG_FS_GINTSTS)\n5. \nDisable all active OUT endpoints by programming the following register bits:\n–\nEPDIS = 1 in registers OTG_FS_DOEPCTLx\n–\nSNAK = 1 in registers OTG_FS_DOEPCTLx\n6. \nWait for the EPDIS interrupt in OTG_FS_DOEPINTx for each OUT endpoint \nprogrammed in the previous step. The EPDIS interrupt in OTG_FS_DOEPINTx \nindicates that the corresponding OUT endpoint is completely disabled. When the \nEPDIS interrupt is asserted, the following bits are cleared:\n–\nEPENA = 0 in registers OTG_FS_DOEPCTLx\n–\nEPDIS = 0 in registers OTG_FS_DOEPCTLx\n–\nSNAK = 0 in registers OTG_FS_DOEPCTLx\n•\nGeneric non-isochronous OUT data transfers\nThis section describes a regular non-isochronous OUT data transfer (control, bulk, or \ninterrupt).\nApplication requirements\n1.\nBefore setting up an OUT transfer, the application must allocate a buffer in the memory \nto accommodate all data to be received as part of the OUT transfer.\n2. \nFor OUT transfers, the transfer size field in the endpoint’s transfer size register must be \na multiple of the maximum packet size of the endpoint, adjusted to the word boundary.\n–\ntransfer size[EPNUM] = n × (MPSIZ[EPNUM] + 4 – (MPSIZ[EPNUM] mod 4))\n–\npacket count[EPNUM] = n\n–\nn > 0\n3. \nOn any OUT endpoint interrupt, the application must read the endpoint’s transfer size \nregister to calculate the size of the payload in the memory. The received payload size \ncan be less than the programmed transfer size.\n–\nPayload size in memory = application programmed initial transfer size – core \nupdated final transfer size\n" }, { "page_number": 1364, "page_indices": { "start_index": 2692931, "end_index": 2695607 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1364 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "SETUP and OUT data transfers", 1358 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1364/1757\nRM0090 Rev 21\n–\nNumber of USB packets in which this payload was received = application \nprogrammed initial packet count – core updated final packet count\nInternal data flow\n1.\nThe application must set the transfer size and packet count fields in the endpoint-\nspecific registers, clear the NAK bit, and enable the endpoint to receive the data.\n2. \nOnce the NAK bit is cleared, the core starts receiving data and writes it to the receive \nFIFO, as long as there is space in the receive FIFO. For every data packet received on \nthe USB, the data packet and its status are written to the receive FIFO. Every packet \n(maximum packet size or short packet) written to the receive FIFO decrements the \npacket count field for that endpoint by 1.\n–\nOUT data packets received with bad data CRC are flushed from the receive FIFO \nautomatically.\n–\nAfter sending an ACK for the packet on the USB, the core discards non-\nisochronous OUT data packets that the host, which cannot detect the ACK, re-\nsends. The application does not detect multiple back-to-back data OUT packets \non the same endpoint with the same data PID. In this case the packet count is not \ndecremented.\n–\nIf there is no space in the receive FIFO, isochronous or non-isochronous data \npackets are ignored and not written to the receive FIFO. Additionally, non-\nisochronous OUT tokens receive a NAK handshake reply.\n–\nIn all the above three cases, the packet count is not decremented because no data \nare written to the receive FIFO.\n3. \nWhen the packet count becomes 0 or when a short packet is received on the endpoint, \nthe NAK bit for that endpoint is set. Once the NAK bit is set, the isochronous or non-\nisochronous data packets are ignored and not written to the receive FIFO, and non-\nisochronous OUT tokens receive a NAK handshake reply.\n4. \nAfter the data are written to the receive FIFO, the application reads the data from the \nreceive FIFO and writes it to external memory, one packet at a time per endpoint.\n5. \nAt the end of every packet write on the AHB to external memory, the transfer size for \nthe endpoint is decremented by the size of the written packet.\n6. \nThe OUT data transfer completed pattern for an OUT endpoint is written to the receive \nFIFO on one of the following conditions:\n–\nThe transfer size is 0 and the packet count is 0\n–\nThe last OUT data packet written to the receive FIFO is a short packet\n(0 ≤packet size < maximum packet size)\n7. \nWhen either the application pops this entry (OUT data transfer completed), a transfer \ncompleted interrupt is generated for the endpoint and the endpoint enable is cleared.\n" }, { "page_number": 1365, "page_indices": { "start_index": 2695607, "end_index": 2697999 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1365 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "SETUP and OUT data transfers", 1358 ] ], "page_content": "RM0090 Rev 21\n1365/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nApplication programming sequence\n1.\nProgram the OTG_FS_DOEPTSIZx register for the transfer size and the corresponding \npacket count.\n2. \nProgram the OTG_FS_DOEPCTLx register with the endpoint characteristics, and set \nthe EPENA and CNAK bits.\n–\nEPENA = 1 in OTG_FS_DOEPCTLx\n–\nCNAK = 1 in OTG_FS_DOEPCTLx\n3. \nWait for the RXFLVL interrupt (in OTG_FS_GINTSTS) and empty the data packets \nfrom the receive FIFO.\n–\nThis step can be repeated many times, depending on the transfer size.\n4. \nAsserting the XFRC interrupt (OTG_FS_DOEPINTx) marks a successful completion of \nthe non-isochronous OUT data transfer.\n5. \nRead the OTG_FS_DOEPTSIZx register to determine the size of the received data \npayload.\n•\nGeneric isochronous OUT data transfer\nThis section describes a regular isochronous OUT data transfer.\nApplication requirements\n1.\nAll the application requirements for non-isochronous OUT data transfers also apply to \nisochronous OUT data transfers.\n2. \nFor isochronous OUT data transfers, the transfer size and packet count fields must \nalways be set to the number of maximum-packet-size packets that can be received in a \nsingle frame and no more. Isochronous OUT data transfers cannot span more than 1 \nframe.\n3. \nThe application must read all isochronous OUT data packets from the receive FIFO \n(data and status) before the end of the periodic frame (EOPF interrupt in \nOTG_FS_GINTSTS).\n4. \nTo receive data in the following frame, an isochronous OUT endpoint must be enabled \nafter the EOPF (OTG_FS_GINTSTS) and before the SOF (OTG_FS_GINTSTS).\nInternal data flow\n1.\nThe internal data flow for isochronous OUT endpoints is the same as that for non-\nisochronous OUT endpoints, but for a few differences.\n2. \nWhen an isochronous OUT endpoint is enabled by setting the Endpoint Enable and \nclearing the NAK bits, the Even/Odd frame bit must also be set appropriately. The core \nreceives data on an isochronous OUT endpoint in a particular frame only if the \nfollowing condition is met:\n–\nEONUM (in OTG_FS_DOEPCTLx) = SOFFN[0] (in OTG_FS_DSTS)\n3. \nWhen the application completely reads an isochronous OUT data packet (data and \nstatus) from the receive FIFO, the core updates the RXDPID field in \nOTG_FS_DOEPTSIZx with the data PID of the last isochronous OUT data packet read \nfrom the receive FIFO.\n" }, { "page_number": 1366, "page_indices": { "start_index": 2697999, "end_index": 2700806 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1366 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "SETUP and OUT data transfers", 1358 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1366/1757\nRM0090 Rev 21\nApplication programming sequence\n1.\nProgram the OTG_FS_DOEPTSIZx register for the transfer size and the corresponding \npacket count\n2. \nProgram the OTG_FS_DOEPCTLx register with the endpoint characteristics and set \nthe Endpoint Enable, ClearNAK, and Even/Odd frame bits.\n–\nEPENA = 1\n–\nCNAK = 1\n–\nEONUM = (0: Even/1: Odd)\n3. \nWait for the RXFLVL interrupt (in OTG_FS_GINTSTS) and empty the data packets \nfrom the receive FIFO\n–\nThis step can be repeated many times, depending on the transfer size.\n4. \nThe assertion of the XFRC interrupt (in OTG_FS_DOEPINTx) marks the completion of \nthe isochronous OUT data transfer. This interrupt does not necessarily mean that the \ndata in memory are good.\n5. \nThis interrupt cannot always be detected for isochronous OUT transfers. Instead, the \napplication can detect the IISOOXFRM interrupt in OTG_FS_GINTSTS.\n6. \nRead the OTG_FS_DOEPTSIZx register to determine the size of the received transfer \nand to determine the validity of the data received in the frame. The application must \ntreat the data received in memory as valid only if one of the following conditions is met:\n–\nRXDPID = D0 (in OTG_FS_DOEPTSIZx) and the number of USB packets in \nwhich this payload was received = 1\n–\nRXDPID = D1 (in OTG_FS_DOEPTSIZx) and the number of USB packets in \nwhich this payload was received = 2\n–\nRXDPID = D2 (in OTG_FS_DOEPTSIZx) and the number of USB packets in \nwhich this payload was received = 3\nThe number of USB packets in which this payload was received =\nApplication programmed initial packet count – Core updated final packet count\nThe application can discard invalid data packets.\n•\nIncomplete isochronous OUT data transfers\nThis section describes the application programming sequence when isochronous OUT data \npackets are dropped inside the core.\nInternal data flow\n1.\nFor isochronous OUT endpoints, the XFRC interrupt (in OTG_FS_DOEPINTx) may not \nalways be asserted. If the core drops isochronous OUT data packets, the application \ncould fail to detect the XFRC interrupt (OTG_FS_DOEPINTx) under the following \ncircumstances:\n–\nWhen the receive FIFO cannot accommodate the complete ISO OUT data packet, \nthe core drops the received ISO OUT data\n–\nWhen the isochronous OUT data packet is received with CRC errors\n–\nWhen the isochronous OUT token received by the core is corrupted\n–\nWhen the application is very slow in reading the data from the receive FIFO\n2. \nWhen the core detects an end of periodic frame before transfer completion to all \nisochronous OUT endpoints, it asserts the incomplete Isochronous OUT data interrupt \n(IISOOXFRM in OTG_FS_GINTSTS), indicating that an XFRC interrupt (in \nOTG_FS_DOEPINTx) is not asserted on at least one of the isochronous OUT \n" }, { "page_number": 1367, "page_indices": { "start_index": 2700806, "end_index": 2703650 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1367 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "Examples", 1367 ] ], "page_content": "RM0090 Rev 21\n1367/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nendpoints. At this point, the endpoint with the incomplete transfer remains enabled, but \nno active transfers remain in progress on this endpoint on the USB.\nApplication programming sequence\n1.\nAsserting the IISOOXFRM interrupt (OTG_FS_GINTSTS) indicates that in the current \nframe, at least one isochronous OUT endpoint has an incomplete transfer.\n2. \nIf this occurs because isochronous OUT data is not completely emptied from the \nendpoint, the application must ensure that the application empties all isochronous OUT \ndata (data and status) from the receive FIFO before proceeding.\n–\nWhen all data are emptied from the receive FIFO, the application can detect the \nXFRC interrupt (OTG_FS_DOEPINTx). In this case, the application must re-\nenable the endpoint to receive isochronous OUT data in the next frame.\n3. \nWhen it receives an IISOOXFRM interrupt (in OTG_FS_GINTSTS), the application \nmust read the control registers of all isochronous OUT endpoints \n(OTG_FS_DOEPCTLx) to determine which endpoints had an incomplete transfer in the \ncurrent microframe. An endpoint transfer is incomplete if both the following conditions \nare met:\n–\nEONUM bit (in OTG_FS_DOEPCTLx) = SOFFN[0] (in OTG_FS_DSTS)\n–\nEPENA = 1 (in OTG_FS_DOEPCTLx)\n4. \nThe previous step must be performed before the SOF interrupt (in OTG_FS_GINTSTS) \nis detected, to ensure that the current frame number is not changed.\n5. \nFor isochronous OUT endpoints with incomplete transfers, the application must discard \nthe data in the memory and disable the endpoint by setting the EPDIS bit in \nOTG_FS_DOEPCTLx.\n6. \nWait for the EPDIS interrupt (in OTG_FS_DOEPINTx) and enable the endpoint to \nreceive new data in the next frame.\n–\nBecause the core can take some time to disable the endpoint, the application may \nnot be able to receive the data in the next frame after receiving bad isochronous \ndata.\n•\nStalling a non-isochronous OUT endpoint\nThis section describes how the application can stall a non-isochronous endpoint.\n1.\nPut the core in the Global OUT NAK mode.\n2. \nDisable the required endpoint\n–\nWhen disabling the endpoint, instead of setting the SNAK bit in \nOTG_FS_DOEPCTL, set STALL = 1 (in OTG_FS_DOEPCTL).\nThe STALL bit always takes precedence over the NAK bit.\n3. \nWhen the application is ready to end the STALL handshake for the endpoint, the \nSTALL bit (in OTG_FS_DOEPCTLx) must be cleared.\n4. \nIf the application is setting or clearing a STALL for an endpoint due to a \nSetFeature.Endpoint Halt or ClearFeature.Endpoint Halt command, the STALL bit must \nbe set or cleared before the application sets up the Status stage transfer on the control \nendpoint.\nExamples\nThis section describes and depicts some fundamental transfer types and scenarios.\n•\nBulk OUT transaction\n" }, { "page_number": 1368, "page_indices": { "start_index": 2703650, "end_index": 2705530 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1368 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "IN data transfers", 1368 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1368/1757\nRM0090 Rev 21\nFigure 404 depicts the reception of a single Bulk OUT Data packet from the USB to the AHB \nand describes the events involved in the process.\nFigure 404. Bulk OUT transaction\nAfter a SetConfiguration/SetInterface command, the application initializes all OUT endpoints \nby setting CNAK = 1 and EPENA = 1 (in OTG_FS_DOEPCTLx), and setting a suitable \nXFRSIZ and PKTCNT in the OTG_FS_DOEPTSIZx register.\n1.\nhost attempts to send data (OUT token) to an endpoint.\n2. \nWhen the core receives the OUT token on the USB, it stores the packet in the RxFIFO \nbecause space is available there.\n3. \nAfter writing the complete packet in the RxFIFO, the core then asserts the RXFLVL \ninterrupt (in OTG_FS_GINTSTS).\n4. \nOn receiving the PKTCNT number of USB packets, the core internally sets the NAK bit \nfor this endpoint to prevent it from receiving any more packets.\n5. \nThe application processes the interrupt and reads the data from the RxFIFO.\n6. \nWhen the application has read all the data (equivalent to XFRSIZ), the core generates \nan XFRC interrupt (in OTG_FS_DOEPINTx).\n7. \nThe application processes the interrupt and uses the setting of the XFRC interrupt bit \n(in OTG_FS_DOEPINTx) to determine that the intended transfer is complete.\nIN data transfers\n•\nPacket write\nThis section describes how the application writes data packets to the endpoint FIFO when \ndedicated transmit FIFOs are enabled.\n1.\nThe application can either choose the polling or the interrupt mode.\ninit_out_ep\n Host\nDevice\nUSB\nOUT\nACK\nRXFLVL intr\n i\nwr_reg (DOEPTSIZx)\nwr_reg(DOEPCTLx)\n64 bytes\nOUT\nNAK\nxact_1\nApplication\nXFRC \nintr\nDOEPCTLx.NAK=1\nPKTCNT 0\nXFRSIZ = 0\nr\n \n \nidle until intr\nrcv_out_pkt()\nidle until intr\nOn new xfer\nor RxFIFO\nnot empty\n1\n2\n3\n4\n5\n6\n7\n8\nXFRSIZ = 64 bytes\nPKTCNT = 1\nEPENA = 1\nCNAK = 1\nai15679b\n" }, { "page_number": 1369, "page_indices": { "start_index": 2705530, "end_index": 2708598 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1369 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "IN data transfers", 1368 ] ], "page_content": "RM0090 Rev 21\n1369/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n–\nIn polling mode, the application monitors the status of the endpoint transmit data \nFIFO by reading the OTG_FS_DTXFSTSx register, to determine if there is enough \nspace in the data FIFO.\n–\nIn interrupt mode, the application waits for the TXFE interrupt (in \nOTG_FS_DIEPINTx) and then reads the OTG_FS_DTXFSTSx register, to \ndetermine if there is enough space in the data FIFO.\n–\nTo write a single non-zero length data packet, there must be space to write the \nentire packet in the data FIFO.\n–\nTo write zero length packet, the application must not look at the FIFO space.\n2. \nUsing one of the above mentioned methods, when the application determines that \nthere is enough space to write a transmit packet, the application must first write into the \nendpoint control register, before writing the data into the data FIFO. Typically, the \napplication, must do a read modify write on the OTG_FS_DIEPCTLx register to avoid \nmodifying the contents of the register, except for setting the Endpoint Enable bit.\nThe application can write multiple packets for the same endpoint into the transmit FIFO, if \nspace is available. For periodic IN endpoints, the application must write packets only for one \nmicroframe. It can write packets for the next periodic transaction only after getting transfer \ncomplete for the previous transaction.\n•\nSetting IN endpoint NAK\nInternal data flow\n1.\nWhen the application sets the IN NAK for a particular endpoint, the core stops \ntransmitting data on the endpoint, irrespective of data availability in the endpoint’s \ntransmit FIFO.\n2. \nNon-isochronous IN tokens receive a NAK handshake reply\n–\nIsochronous IN tokens receive a zero-data-length packet reply\n3. \nThe core asserts the INEPNE (IN endpoint NAK effective) interrupt in \nOTG_FS_DIEPINTx in response to the SNAK bit in OTG_FS_DIEPCTLx.\n4. \nOnce this interrupt is seen by the application, the application can assume that the \nendpoint is in IN NAK mode. This interrupt can be cleared by the application by setting \nthe CNAK bit in OTG_FS_DIEPCTLx.\nApplication programming sequence\n1.\nTo stop transmitting any data on a particular IN endpoint, the application must set the \nIN NAK bit. To set this bit, the following field must be programmed.\n–\nSNAK = 1 in OTG_FS_DIEPCTLx\n2. \nWait for assertion of the INEPNE interrupt in OTG_FS_DIEPINTx. This interrupt \nindicates that the core has stopped transmitting data on the endpoint.\n3. \nThe core can transmit valid IN data on the endpoint after the application has set the \nNAK bit, but before the assertion of the NAK Effective interrupt.\n4. \nThe application can mask this interrupt temporarily by writing to the INEPNEM bit in \nDIEPMSK.\n–\nINEPNEM = 0 in DIEPMSK\n5. \nTo exit Endpoint NAK mode, the application must clear the NAK status bit (NAKSTS) in \nOTG_FS_DIEPCTLx. This also clears the INEPNE interrupt (in OTG_FS_DIEPINTx).\n–\nCNAK = 1 in OTG_FS_DIEPCTLx\n6. \nIf the application masked this interrupt earlier, it must be unmasked as follows:\n" }, { "page_number": 1370, "page_indices": { "start_index": 2708598, "end_index": 2710351 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1370 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "IN data transfers", 1368 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1370/1757\nRM0090 Rev 21\n–\nINEPNEM = 1 in DIEPMSK\n•\nIN endpoint disable\nUse the following sequence to disable a specific IN endpoint that has been previously \nenabled.\nApplication programming sequence\n1.\nThe application must stop writing data on the AHB for the IN endpoint to be disabled.\n2. \nThe application must set the endpoint in NAK mode. \n–\nSNAK = 1 in OTG_FS_DIEPCTLx\n3. \nWait for the INEPNE interrupt in OTG_FS_DIEPINTx.\n4. \nSet the following bits in the OTG_FS_DIEPCTLx register for the endpoint that must be \ndisabled.\n–\nEPDIS = 1 in OTG_FS_DIEPCTLx\n–\nSNAK = 1 in OTG_FS_DIEPCTLx\n5. \nAssertion of the EPDISD interrupt in OTG_FS_DIEPINTx indicates that the core has \ncompletely disabled the specified endpoint. Along with the assertion of the interrupt, the \ncore also clears the following bits:\n–\nEPENA = 0 in OTG_FS_DIEPCTLx\n–\nEPDIS = 0 in OTG_FS_DIEPCTLx\n6. \nThe application must read the OTG_FS_DIEPTSIZx register for the periodic IN EP, to \ncalculate how much data on the endpoint were transmitted on the USB.\n7. \nThe application must flush the data in the Endpoint transmit FIFO, by setting the \nfollowing fields in the OTG_FS_GRSTCTL register:\n–\nTXFNUM (in OTG_FS_GRSTCTL) = Endpoint transmit FIFO number\n–\nTXFFLSH in (OTG_FS_GRSTCTL) = 1\nThe application must poll the OTG_FS_GRSTCTL register, until the TXFFLSH bit is cleared \nby the core, which indicates the end of flush operation. To transmit new data on this \nendpoint, the application can re-enable the endpoint at a later point.\n•\nTransfer Stop Programming for IN endpoints\nThe application must use the following programing sequence to stop any transfers (because \nof an interrupt from the host, typically a reset).\n" }, { "page_number": 1371, "page_indices": { "start_index": 2710351, "end_index": 2712936 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1371 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "IN data transfers", 1368 ] ], "page_content": "RM0090 Rev 21\n1371/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nSequence of operations:\n1.\nDisable the IN endpoint by setting:\n–\nEPDIS = 1 in all OTG_FS_DIEPCTLx registers\n2. \nWait for the EPDIS interrupt in OTG_FS_DIEPINTx, which indicates that the IN \nendpoint is completely disabled. When the EPDIS interrupt is asserted the following \nbits are cleared:\n–\nEPDIS = 0 in OTG_FS_DIEPCTLx\n–\nEPENA = 0 in OTG_FS_DIEPCTLx\n3. \nFlush the TxFIFO by programming the following bits:\n–\nTXFFLSH = 1 in OTG_FS_GRSTCTL\n–\nTXFNUM = “FIFO number specific to endpoint” in OTG_FS_GRSTCTL\n4. \nThe application can start polling till TXFFLSH in OTG_FS_GRSTCTL is cleared. When \nthis bit is cleared, it ensures that there is no data left in the Tx FIFO.\n•\nGeneric non-periodic IN data transfers\nApplication requirements\n1.\nBefore setting up an IN transfer, the application must ensure that all data to be \ntransmitted as part of the IN transfer are part of a single buffer.\n2. \nFor IN transfers, the Transfer Size field in the Endpoint Transfer Size register denotes a \npayload that constitutes multiple maximum-packet-size packets and a single short \npacket. This short packet is transmitted at the end of the transfer.\n–\nTo transmit a few maximum-packet-size packets and a short packet at the end of \nthe transfer:\nTransfer size[EPNUM] = x × MPSIZ[EPNUM] + sp\nIf (sp > 0), then packet count[EPNUM] = x + 1. \nOtherwise, packet count[EPNUM] = x\n–\nTo transmit a single zero-length data packet:\nTransfer size[EPNUM] = 0\nPacket count[EPNUM] = 1\n–\nTo transmit a few maximum-packet-size packets and a zero-length data packet at \nthe end of the transfer, the application must split the transfer into two parts. The \nfirst sends maximum-packet-size data packets and the second sends the zero-\nlength data packet alone.\nFirst transfer: transfer size[EPNUM] = x × MPSIZ[epnum]; packet count = n;\nSecond transfer: transfer size[EPNUM] = 0; packet count = 1;\n3. \nOnce an endpoint is enabled for data transfers, the core updates the Transfer size \nregister. At the end of the IN transfer, the application must read the Transfer size \nregister to determine how much data posted in the transmit FIFO have already been \nsent on the USB.\n4. \nData fetched into transmit FIFO = Application-programmed initial transfer size – core-\nupdated final transfer size\n–\nData transmitted on USB = (application-programmed initial packet count – Core \nupdated final packet count) × MPSIZ[EPNUM]\n–\nData yet to be transmitted on USB = (Application-programmed initial transfer size \n– data transmitted on USB)\n" }, { "page_number": 1372, "page_indices": { "start_index": 2712936, "end_index": 2716364 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1372 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "IN data transfers", 1368 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1372/1757\nRM0090 Rev 21\nInternal data flow\n1.\nThe application must set the transfer size and packet count fields in the endpoint-\nspecific registers and enable the endpoint to transmit the data.\n2. \nThe application must also write the required data to the transmit FIFO for the endpoint.\n3. \nEvery time a packet is written into the transmit FIFO by the application, the transfer size \nfor that endpoint is decremented by the packet size. The data is fetched from the \nmemory by the application, until the transfer size for the endpoint becomes 0. After \nwriting the data into the FIFO, the “number of packets in FIFO” count is incremented \n(this is a 3-bit count, internally maintained by the core for each IN endpoint transmit \nFIFO. The maximum number of packets maintained by the core at any time in an IN \nendpoint FIFO is eight). For zero-length packets, a separate flag is set for each FIFO, \nwithout any data in the FIFO.\n4. \nOnce the data are written to the transmit FIFO, the core reads them out upon receiving \nan IN token. For every non-isochronous IN data packet transmitted with an ACK \nhandshake, the packet count for the endpoint is decremented by one, until the packet \ncount is zero. The packet count is not decremented on a timeout.\n5. \nFor zero length packets (indicated by an internal zero length flag), the core sends out a \nzero-length packet for the IN token and decrements the packet count field.\n6. \nIf there are no data in the FIFO for a received IN token and the packet count field for \nthat endpoint is zero, the core generates an “IN token received when TxFIFO is empty” \n(ITTXFE) Interrupt for the endpoint, provided that the endpoint NAK bit is not set. The \ncore responds with a NAK handshake for non-isochronous endpoints on the USB.\n7. \nThe core internally rewinds the FIFO pointers and no timeout interrupt is generated.\n8. \nWhen the transfer size is 0 and the packet count is 0, the transfer complete (XFRC) \ninterrupt for the endpoint is generated and the endpoint enable is cleared.\nApplication programming sequence\n1.\nProgram the OTG_FS_DIEPTSIZx register with the transfer size and corresponding \npacket count.\n2. \nProgram the OTG_FS_DIEPCTLx register with the endpoint characteristics and set the \nCNAK and EPENA (Endpoint Enable) bits.\n3. \nWhen transmitting non-zero length data packet, the application must poll the \nOTG_FS_DTXFSTSx register (where x is the FIFO number associated with that \nendpoint) to determine whether there is enough space in the data FIFO. The \napplication can optionally use TXFE (in OTG_FS_DIEPINTx) before writing the data.\n•\nGeneric periodic IN data transfers\nThis section describes a typical periodic IN data transfer.\nApplication requirements\n1.\nApplication requirements 1, 2, 3, and 4 of Generic non-periodic IN data transfers also \napply to periodic IN data transfers, except for a slight modification of requirement 2.\n–\nThe application can only transmit multiples of maximum-packet-size data packets \nor multiples of maximum-packet-size packets, plus a short packet at the end. To \ntransmit a few maximum-packet-size packets and a short packet at the end of the \ntransfer, the following conditions must be met:\ntransfer size[EPNUM] = x × MPSIZ[EPNUM] + sp\n(where x is an integer ≥ 0, and 0 ≤ sp < MPSIZ[EPNUM])\nIf (sp > 0), packet count[EPNUM] = x + 1\nOtherwise, packet count[EPNUM] = x;\n" }, { "page_number": 1373, "page_indices": { "start_index": 2716364, "end_index": 2719299 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1373 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "IN data transfers", 1368 ] ], "page_content": "RM0090 Rev 21\n1373/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nMCNT[EPNUM] = packet count[EPNUM]\n–\nThe application cannot transmit a zero-length data packet at the end of a transfer. \nIt can transmit a single zero-length data packet by itself. To transmit a single zero-\nlength data packet:\n–\ntransfer size[EPNUM] = 0\npacket count[EPNUM] = 1\nMCNT[EPNUM] = packet count[EPNUM]\n2. \nThe application can only schedule data transfers one frame at a time.\n–\n(MCNT – 1) × MPSIZ ≤XFERSIZ ≤MCNT × MPSIZ\n–\nPKTCNT = MCNT (in OTG_FS_DIEPTSIZx)\n–\nIf XFERSIZ < MCNT × MPSIZ, the last data packet of the transfer is a short \npacket.\n–\nNote that: MCNT is in OTG_FS_DIEPTSIZx, MPSIZ is in OTG_FS_DIEPCTLx, \nPKTCNT is in OTG_FS_DIEPTSIZx and XFERSIZ is in OTG_FS_DIEPTSIZx\n3. \nThe complete data to be transmitted in the frame must be written into the transmit FIFO \nby the application, before the IN token is received. Even when 1 word of the data to be \ntransmitted per frame is missing in the transmit FIFO when the IN token is received, the \ncore behaves as when the FIFO is empty. When the transmit FIFO is empty:\n–\nA zero data length packet would be transmitted on the USB for isochronous IN \nendpoints\n–\nA NAK handshake would be transmitted on the USB for interrupt IN endpoints\nInternal data flow\n1.\nThe application must set the transfer size and packet count fields in the endpoint-\nspecific registers and enable the endpoint to transmit the data.\n2. \nThe application must also write the required data to the associated transmit FIFO for \nthe endpoint.\n3. \nEvery time the application writes a packet to the transmit FIFO, the transfer size for that \nendpoint is decremented by the packet size. The data are fetched from application \nmemory until the transfer size for the endpoint becomes 0.\n4. \nWhen an IN token is received for a periodic endpoint, the core transmits the data in the \nFIFO, if available. If the complete data payload (complete packet, in dedicated FIFO \nmode) for the frame is not present in the FIFO, then the core generates an IN token \nreceived when TxFIFO empty interrupt for the endpoint.\n–\nA zero-length data packet is transmitted on the USB for isochronous IN endpoints\n–\nA NAK handshake is transmitted on the USB for interrupt IN endpoints\n5. \nThe packet count for the endpoint is decremented by 1 under the following conditions:\n–\nFor isochronous endpoints, when a zero- or non-zero-length data packet is \ntransmitted\n–\nFor interrupt endpoints, when an ACK handshake is transmitted\n–\nWhen the transfer size and packet count are both 0, the transfer completed \ninterrupt for the endpoint is generated and the endpoint enable is cleared.\n6. \nAt the “Periodic frame Interval” (controlled by PFIVL in OTG_FS_DCFG), when the \ncore finds non-empty any of the isochronous IN endpoint FIFOs scheduled for the \ncurrent frame non-empty, the core generates an IISOIXFR interrupt in \nOTG_FS_GINTSTS.\n" }, { "page_number": 1374, "page_indices": { "start_index": 2719299, "end_index": 2722410 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1374 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "IN data transfers", 1368 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1374/1757\nRM0090 Rev 21\nApplication programming sequence\n1.\nProgram the OTG_FS_DIEPCTLx register with the endpoint characteristics and set the \nCNAK and EPENA bits.\n2. \nWrite the data to be transmitted in the next frame to the transmit FIFO.\n3. \nAsserting the ITTXFE interrupt (in OTG_FS_DIEPINTx) indicates that the application \nhas not yet written all data to be transmitted to the transmit FIFO.\n4. \nIf the interrupt endpoint is already enabled when this interrupt is detected, ignore the \ninterrupt. If it is not enabled, enable the endpoint so that the data can be transmitted on \nthe next IN token attempt.\n5. \nAsserting the XFRC interrupt (in OTG_FS_DIEPINTx) with no ITTXFE interrupt in \nOTG_FS_DIEPINTx indicates the successful completion of an isochronous IN transfer. \nA read to the OTG_FS_DIEPTSIZx register must give transfer size = 0 and packet \ncount = 0, indicating all data were transmitted on the USB.\n6. \nAsserting the XFRC interrupt (in OTG_FS_DIEPINTx), with or without the ITTXFE \ninterrupt (in OTG_FS_DIEPINTx), indicates the successful completion of an interrupt \nIN transfer. A read to the OTG_FS_DIEPTSIZx register must give transfer size = 0 and \npacket count = 0, indicating all data were transmitted on the USB.\n7. \nAsserting the incomplete isochronous IN transfer (IISOIXFR) interrupt in \nOTG_FS_GINTSTS with none of the aforementioned interrupts indicates the core did \nnot receive at least 1 periodic IN token in the current frame.\n•\nIncomplete isochronous IN data transfers\nThis section describes what the application must do on an incomplete isochronous IN data \ntransfer.\nInternal data flow\n1.\nAn isochronous IN transfer is treated as incomplete in one of the following conditions:\na) \nThe core receives a corrupted isochronous IN token on at least one isochronous \nIN endpoint. In this case, the application detects an incomplete isochronous IN \ntransfer interrupt (IISOIXFR in OTG_FS_GINTSTS).\nb) \nThe application is slow to write the complete data payload to the transmit FIFO \nand an IN token is received before the complete data payload is written to the \nFIFO. In this case, the application detects an IN token received when TxFIFO \nempty interrupt in OTG_FS_DIEPINTx. The application can ignore this interrupt, \nas it eventually results in an incomplete isochronous IN transfer interrupt \n(IISOIXFR in OTG_FS_GINTSTS) at the end of periodic frame.\nThe core transmits a zero-length data packet on the USB in response to the \nreceived IN token.\n2. \nThe application must stop writing the data payload to the transmit FIFO as soon as \npossible.\n3. \nThe application must set the NAK bit and the disable bit for the endpoint.\n4. \nThe core disables the endpoint, clears the disable bit, and asserts the Endpoint Disable \ninterrupt for the endpoint.\nApplication programming sequence\n1.\nThe application can ignore the IN token received when TxFIFO empty interrupt in \nOTG_FS_DIEPINTx on any isochronous IN endpoint, as it eventually results in an \nincomplete isochronous IN transfer interrupt (in OTG_FS_GINTSTS).\n" }, { "page_number": 1375, "page_indices": { "start_index": 2722410, "end_index": 2725317 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1375 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.6 Operational model", 1358 ], [ 4, "IN data transfers", 1368 ] ], "page_content": "RM0090 Rev 21\n1375/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n2. \nAssertion of the incomplete isochronous IN transfer interrupt (in OTG_FS_GINTSTS) \nindicates an incomplete isochronous IN transfer on at least one of the isochronous IN \nendpoints.\n3. \nThe application must read the Endpoint Control register for all isochronous IN \nendpoints to detect endpoints with incomplete IN data transfers.\n4. \nThe application must stop writing data to the Periodic Transmit FIFOs associated with \nthese endpoints on the AHB.\n5. \nProgram the following fields in the OTG_FS_DIEPCTLx register to disable the \nendpoint:\n–\nSNAK = 1 in OTG_FS_DIEPCTLx\n–\nEPDIS = 1 in OTG_FS_DIEPCTLx\n6. \nThe assertion of the Endpoint Disabled interrupt in OTG_FS_DIEPINTx indicates that \nthe core has disabled the endpoint.\n–\nAt this point, the application must flush the data in the associated transmit FIFO or \noverwrite the existing data in the FIFO by enabling the endpoint for a new transfer \nin the next microframe. To flush the data, the application must use the \nOTG_FS_GRSTCTL register.\n•\nStalling non-isochronous IN endpoints\nThis section describes how the application can stall a non-isochronous endpoint.\nApplication programming sequence\n1.\nDisable the IN endpoint to be stalled. Set the STALL bit as well.\n2. \nEPDIS = 1 in OTG_FS_DIEPCTLx, when the endpoint is already enabled\n–\nSTALL = 1 in OTG_FS_DIEPCTLx\n–\nThe STALL bit always takes precedence over the NAK bit\n3. \nAssertion of the Endpoint Disabled interrupt (in OTG_FS_DIEPINTx) indicates to the \napplication that the core has disabled the specified endpoint.\n4. \nThe application must flush the non-periodic or periodic transmit FIFO, depending on \nthe endpoint type. In case of a non-periodic endpoint, the application must re-enable \nthe other non-periodic endpoints that do not need to be stalled, to transmit data.\n5. \nWhenever the application is ready to end the STALL handshake for the endpoint, the \nSTALL bit must be cleared in OTG_FS_DIEPCTLx.\n6. \nIf the application sets or clears a STALL bit for an endpoint due to a \nSetFeature.Endpoint Halt command or ClearFeature.Endpoint Halt command, the \nSTALL bit must be set or cleared before the application sets up the Status stage \ntransfer on the control endpoint.\nSpecial case: stalling the control OUT endpoint\nThe core must stall IN/OUT tokens if, during the data stage of a control transfer, the host \nsends more IN/OUT tokens than are specified in the SETUP packet. In this case, the \napplication must enable the ITTXFE interrupt in OTG_FS_DIEPINTx and the OTEPDIS \ninterrupt in OTG_FS_DOEPINTx during the data stage of the control transfer, after the core \nhas transferred the amount of data specified in the SETUP packet. Then, when the \napplication receives this interrupt, it must set the STALL bit in the corresponding endpoint \ncontrol register, and clear this interrupt.\n" }, { "page_number": 1376, "page_indices": { "start_index": 2725317, "end_index": 2727822 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1376 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.7 Worst case response time", 1376 ], [ 4, "Choosing the value of TRDT in OTG_FS_GUSBCFG", 1376 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1376/1757\nRM0090 Rev 21\n34.17.7 \nWorst case response time\nWhen the OTG_FS controller acts as a device, there is a worst case response time for any \ntokens that follow an isochronous OUT. This worst case response time depends on the AHB \nclock frequency.\nThe core registers are in the AHB domain, and the core does not accept another token \nbefore updating these register values. The worst case is for any token following an \nisochronous OUT, because for an isochronous transaction, there is no handshake and the \nnext token could come sooner. This worst case value is 7 PHY clocks when the AHB clock \nis the same as the PHY clock. When the AHB clock is faster, this value is smaller.\nIf this worst case condition occurs, the core responds to bulk/interrupt tokens with a NAK \nand drops isochronous and SETUP tokens. The host interprets this as a timeout condition \nfor SETUP and retries the SETUP packet. For isochronous transfers, the Incomplete \nisochronous IN transfer interrupt (IISOIXFR) and Incomplete isochronous OUT transfer \ninterrupt (IISOOXFR) inform the application that isochronous IN/OUT packets were \ndropped.\nChoosing the value of TRDT in OTG_FS_GUSBCFG\nThe value in TRDT (OTG_FS_GUSBCFG) is the time it takes for the MAC, in terms of PHY \nclocks after it has received an IN token, to get the FIFO status, and thus the first data from \nthe PFC block. This time involves the synchronization delay between the PHY and AHB \nclocks. The worst case delay for this is when the AHB clock is the same as the PHY clock. \nIn this case, the delay is 5 clocks.\nOnce the MAC receives an IN token, this information (token received) is synchronized to the \nAHB clock by the PFC (the PFC runs on the AHB clock). The PFC then reads the data from \nthe SPRAM and writes them into the dual clock source buffer. The MAC then reads the data \nout of the source buffer (4 deep).\nIf the AHB is running at a higher frequency than the PHY, the application can use a smaller \nvalue for TRDT (in OTG_FS_GUSBCFG).\nFigure 405 has the following signals:\n•\ntkn_rcvd: Token received information from MAC to PFC\n•\ndynced_tkn_rcvd: Doubled sync tkn_rcvd, from PCLK to HCLK domain\n•\nspr_read: Read to SPRAM\n•\nspr_addr: Address to SPRAM\n•\nspr_rdata: Read data from SPRAM\n•\nsrcbuf_push: Push to the source buffer\n•\nsrcbuf_rdata: Read data from the source buffer. Data seen by MAC\nRefer to Table 204: TRDT values for the values of TRDT versus AHB clock frequency. \n" }, { "page_number": 1377, "page_indices": { "start_index": 2727822, "end_index": 2728814 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1377 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.8 OTG programming model", 1377 ] ], "page_content": "RM0090 Rev 21\n1377/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nFigure 405. TRDT max timing case \n34.17.8 \nOTG programming model\nThe OTG_FS controller is an OTG device supporting HNP and SRP. When the core is \nconnected to an “A” plug, it is referred to as an A-device. When the core is connected to a \n“B” plug it is referred to as a B-device. In host mode, the OTG_FS controller turns off VBUS \nto conserve power. SRP is a method by which the B-device signals the A-device to turn on \nVBUS power. A device must perform both data-line pulsing and VBUS pulsing, but a host can \ndetect either data-line pulsing or VBUS pulsing for SRP. HNP is a method by which the B-\ndevice negotiates and switches to host role. In Negotiated mode after HNP, the B-device \nsuspends the bus and reverts to the device role.\n1\n2\n3\n4\n5\n6\n7\n8\n0ns\n50ns\n100ns\n150ns\n200ns\nHCLK\nPCLK\ntkn_rcvd\ndsynced_tkn_rcvd\nspr_read\nspr_addr\nspr_rdata\nsrcbuf_push\nsrcbuf_rdata\n5 Clocks\nD1\nA1\nD1\nai15680\n" }, { "page_number": 1378, "page_indices": { "start_index": 2728814, "end_index": 2730470 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1378 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.8 OTG programming model", 1377 ], [ 4, "A-device session request protocol", 1378 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1378/1757\nRM0090 Rev 21\nA-device session request protocol\nThe application must set the SRP-capable bit in the Core USB configuration register. This \nenables the OTG_FS controller to detect SRP as an A-device.\nFigure 406. A-device SRP\n1.\nDRV_VBUS = VBUS drive signal to the PHY\nVBUS_VALID = VBUS valid signal from PHY\nA_VALID = A-peripheral VBUS level signal to PHY\nD+ = Data plus line\nD- = Data minus line\n1.\nTo save power, the application suspends and turns off port power when the bus is idle \nby writing the port suspend and port power bits in the host port control and status \nregister.\n2. \nPHY indicates port power off by deasserting the VBUS_VALID signal.\n3. \nThe device must detect SE0 for at least 2 ms to start SRP when VBUS power is off.\n4. \nTo initiate SRP, the device turns on its data line pull-up resistor for 5 to 10 ms. The \nOTG_FS controller detects data-line pulsing.\n5. \nThe device drives VBUS above the A-device session valid (2.0 V minimum) for VBUS \npulsing.\nThe OTG_FS controller interrupts the application on detecting SRP. The Session \nrequest detected bit is set in Global interrupt status register (SRQINT set in \nOTG_FS_GINTSTS).\n6. \nThe application must service the Session request detected interrupt and turn on the \nport power bit by writing the port power bit in the host port control and status register. \nThe PHY indicates port power-on by asserting the VBUS_VALID signal.\n7. \nWhen the USB is powered, the device connects, completing the SRP process.\nai15681\nDRV_VBUS\nVBUS_VALID\nA_VALID\nD+\nD-\nSuspend\nVBUS pulsing\nData line pulsing\nConnect\n1\n6\n2\n5\n3\n4\n7\nLow\n" }, { "page_number": 1379, "page_indices": { "start_index": 2730470, "end_index": 2732387 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1379 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.8 OTG programming model", 1377 ], [ 4, "B-device session request protocol", 1379 ] ], "page_content": "RM0090 Rev 21\n1379/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nB-device session request protocol\nThe application must set the SRP-capable bit in the Core USB configuration register. This \nenables the OTG_FS controller to initiate SRP as a B-device. SRP is a means by which the \nOTG_FS controller can request a new session from the host.\nFigure 407. B-device SRP\n1.\nVBUS_VALID = VBUS valid signal from PHY\nB_VALID = B-peripheral valid session to PHY\nDISCHRG_VBUS = discharge signal to PHY\nSESS_END = session end signal to PHY\nCHRG_VBUS = charge VBUS signal to PHY\nDP = Data plus line\nDM = Data minus line\n1.\nTo save power, the host suspends and turns off port power when the bus is idle.\nThe OTG_FS controller sets the early suspend bit in the Core interrupt register after 3 \nms of bus idleness. Following this, the OTG_FS controller sets the USB suspend bit in \nthe Core interrupt register.\nThe OTG_FS controller informs the PHY to discharge VBUS.\n2. \nThe PHY indicates the session’s end to the device. This is the initial condition for SRP. \nThe OTG_FS controller requires 2 ms of SE0 before initiating SRP.\nFor a USB 1.1 full-speed serial transceiver, the application must wait until VBUS \ndischarges to 0.2 V after BSVLD (in OTG_FS_GOTGCTL) is deasserted. This \ndischarge time can be obtained from the transceiver vendor and varies from one \ntransceiver to another.\n3. \nThe USB OTG core informs the PHY to speed up VBUS discharge.\n4. \nThe application initiates SRP by writing the session request bit in the OTG Control and \nstatus register. The OTG_FS controller perform data-line pulsing followed by VBUS \npulsing.\n5. \nThe host detects SRP from either the data-line or VBUS pulsing, and turns on VBUS. \nThe PHY indicates VBUS power-on to the device.\nai15682\nVBUS_VALID\nB_VALID\nDISCHRG_VBUS\nSESS_END\nDP\nDM\nCHRG_VBUS\nSuspend\nData line pulsing\nConnect\nVBUS pulsing\n1\n6\n2\n3\n4\n5\n8\n7\nLow\n" }, { "page_number": 1380, "page_indices": { "start_index": 2732387, "end_index": 2733768 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1380 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.8 OTG programming model", 1377 ], [ 4, "A-device host negotiation protocol", 1380 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1380/1757\nRM0090 Rev 21\n6. \nThe OTG_FS controller performs VBUS pulsing.\nThe host starts a new session by turning on VBUS, indicating SRP success. The \nOTG_FS controller interrupts the application by setting the session request success \nstatus change bit in the OTG interrupt status register. The application reads the session \nrequest success bit in the OTG control and status register.\n7. \nWhen the USB is powered, the OTG_FS controller connects, completing the SRP \nprocess.\nA-device host negotiation protocol\nHNP switches the USB host role from the A-device to the B-device. The application must set \nthe HNP-capable bit in the Core USB configuration register to enable the OTG_FS \ncontroller to perform HNP as an A-device.\nFigure 408. A-device HNP\n1.\nDPPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DP line inside the PHY.\nDMPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DM line inside the PHY.\n1.\nThe OTG_FS controller sends the B-device a SetFeature b_hnp_enable descriptor to \nenable HNP support. The B-device’s ACK response indicates that the B-device \nsupports HNP. The application must set host Set HNP Enable bit in the OTG Control \nai15683\nOTG core\nDP\nDM\nDPPULLDOWN\nDMPULLDOWN\nHost\nDevice\nHost\n1\nSuspend 2\n3\n4\n5\nReset\n6\nTraffic\n7\n8\nConnect\nTraffic\n" }, { "page_number": 1381, "page_indices": { "start_index": 2733768, "end_index": 2735916 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1381 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.8 OTG programming model", 1377 ], [ 4, "A-device host negotiation protocol", 1380 ] ], "page_content": "RM0090 Rev 21\n1381/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\nand status register to indicate to the OTG_FS controller that the B-device supports \nHNP.\n2. \nWhen it has finished using the bus, the application suspends by writing the Port \nsuspend bit in the host port control and status register.\n3. \nWhen the B-device observes a USB suspend, it disconnects, indicating the initial \ncondition for HNP. The B-device initiates HNP only when it must switch to the host role; \notherwise, the bus continues to be suspended.\nThe OTG_FS controller sets the host negotiation detected interrupt in the OTG \ninterrupt status register, indicating the start of HNP.\nThe OTG_FS controller deasserts the DM pull down and DM pull down in the PHY to \nindicate a device role. The PHY enables the OTG_FS_DP pull-up resistor to indicate a \nconnect for B-device.\nThe application must read the current mode bit in the OTG Control and status register \nto determine device mode operation.\n4. \nThe B-device detects the connection, issues a USB reset, and enumerates the \nOTG_FS controller for data traffic.\n5. \nThe B-device continues the host role, initiating traffic, and suspends the bus when \ndone.\nThe OTG_FS controller sets the early suspend bit in the Core interrupt register after 3 \nms of bus idleness. Following this, the OTG_FS controller sets the USB Suspend bit in \nthe Core interrupt register.\n6. \nIn Negotiated mode, the OTG_FS controller detects the suspend, disconnects, and \nswitches back to the host role. The OTG_FS controller asserts the DM pull down and \nDM pull down in the PHY to indicate its assumption of the host role.\n7. \nThe OTG_FS controller sets the Connector ID status change interrupt in the OTG \nInterrupt Status register. The application must read the connector ID status in the OTG \nControl and Status register to determine the OTG_FS controller operation as an A-\ndevice. This indicates the completion of HNP to the application. The application must \nread the Current mode bit in the OTG control and status register to determine host \nmode operation.\n8. \nThe B-device connects, completing the HNP process.\n" }, { "page_number": 1382, "page_indices": { "start_index": 2735916, "end_index": 2738271 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1382 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.8 OTG programming model", 1377 ], [ 4, "B-device host negotiation protocol", 1382 ] ], "page_content": "USB on-the-go full-speed (OTG_FS)\nRM0090\n1382/1757\nRM0090 Rev 21\nB-device host negotiation protocol\nHNP switches the USB host role from B-device to A-device. The application must set the \nHNP-capable bit in the Core USB configuration register to enable the OTG_FS controller to \nperform HNP as a B-device.\nFigure 409. B-device HNP\n1.\nDPPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DP line inside the PHY.\nDMPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DM line inside the PHY.\n1.\nThe A-device sends the SetFeature b_hnp_enable descriptor to enable HNP support. \nThe OTG_FS controller’s ACK response indicates that it supports HNP. The application \nmust set the device HNP enable bit in the OTG Control and status register to indicate \nHNP support.\nThe application sets the HNP request bit in the OTG Control and status register to \nindicate to the OTG_FS controller to initiate HNP.\n2. \nWhen it has finished using the bus, the A-device suspends by writing the Port suspend \nbit in the host port control and status register.\nThe OTG_FS controller sets the Early suspend bit in the Core interrupt register after 3 \nms of bus idleness. Following this, the OTG_FS controller sets the USB suspend bit in \nthe Core interrupt register.\nThe OTG_FS controller disconnects and the A-device detects SE0 on the bus, \nindicating HNP. The OTG_FS controller asserts the DP pull down and DM pull down in \nthe PHY to indicate its assumption of the host role.\nThe A-device responds by activating its OTG_FS_DP pull-up resistor within 3 ms of \ndetecting SE0. The OTG_FS controller detects this as a connect.\nThe OTG_FS controller sets the host negotiation success status change interrupt in the \nOTG Interrupt status register, indicating the HNP status. The application must read the \nhost negotiation success bit in the OTG Control and status register to determine host \nnegotiation success. The application must read the current Mode bit in the Core \ninterrupt register (OTG_FS_GINTSTS) to determine host mode operation.\n3. \nThe application sets the reset bit (PRST in OTG_FS_HPRT) and the OTG_FS \ncontroller issues a USB reset and enumerates the A-device for data traffic.\nai15684\nOTG core\nDP\nDM\nDPPULLDOWN\nDMPULLDOWN\nHost\nDevice\nDevice\n1\nSuspend 2\n3\n4\n5\nReset\n6\nTraffic\n7\n8\nConnect\nTraffic\n" }, { "page_number": 1383, "page_indices": { "start_index": 2738271, "end_index": 2738989 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1383 }, "toc_details": [ [ 1, "34 USB on-the-go full-speed (OTG_FS)", 1243 ], [ 2, "34.17 OTG_FS programming model", 1338 ], [ 3, "34.17.8 OTG programming model", 1377 ], [ 4, "B-device host negotiation protocol", 1382 ] ], "page_content": "RM0090 Rev 21\n1383/1757\nRM0090\nUSB on-the-go full-speed (OTG_FS)\n1383\n4. \nThe OTG_FS controller continues the host role of initiating traffic, and when done, \nsuspends the bus by writing the Port suspend bit in the host port control and status \nregister.\n5. \nIn Negotiated mode, when the A-device detects a suspend, it disconnects and switches \nback to the host role. The OTG_FS controller deasserts the DP pull down and DM pull \ndown in the PHY to indicate the assumption of the device role.\n6. \nThe application must read the current mode bit in the Core interrupt \n(OTG_FS_GINTSTS) register to determine the host mode operation.\n7. \nThe OTG_FS controller connects, completing the HNP process.\n" }, { "page_number": 1384, "page_indices": { "start_index": 2738989, "end_index": 2740629 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1384 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.1 OTG_HS introduction", 1384 ], [ 2, "35.2 OTG_HS main features", 1384 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1384/1757\nRM0090 Rev 21\n35 \nUSB on-the-go high-speed (OTG_HS)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n35.1 \nOTG_HS introduction\nPortions Copyright (c) 2004, 2005 Synopsys, Inc. All rights reserved. Used with permission.\nThis section presents the architecture and the programming model of the OTG_HS \ncontroller.\nThe following acronyms are used throughout the section:\nReferences are made to the following documents:\n•\nUSB On-The-Go Supplement, Revision 1.3\n•\nUniversal Serial Bus Revision 2.0 Specification\nThe OTG_HS is a dual-role device (DRD) controller that supports both peripheral and host \nfunctions and is fully compliant with the On-The-Go Supplement to the USB 2.0 \nSpecification. It can also be configured as a host-only or peripheral-only controller, fully \ncompliant with the USB 2.0 Specification. In host mode, the OTG_HS supports high-speed \n(HS, 480 Mbits/s), full-speed (FS, 12 Mbits/s) and low-speed (LS, 1.5 Mbits/s) transfers \nwhereas in peripheral mode, it only supports high-speed (HS, 480Mbits/s) and full-speed \n(FS, 12 Mbits/s) transfers. The OTG_HS supports both HNP and SRP. The only external \ndevice required is a charge pump for VBUS in OTG mode.\n35.2 \nOTG_HS main features\nThe main features can be divided into three categories: general, host-mode and peripheral-\nmode features.\nFS\nfull-speed\nHS\nHigh-speed\nLS\nLow-speed\nUSB\nUniversal serial bus\nOTG\nOn-the-go\nPHY\nPhysical layer\nMAC\n Media access controller\nPFC\n Packet FIFO controller\nUTMI\nUSB Transceiver Macrocell Interface\nULPI\nUTMI+ Low Pin Interface\n" }, { "page_number": 1385, "page_indices": { "start_index": 2740629, "end_index": 2742477 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1385 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.2 OTG_HS main features", 1384 ], [ 3, "35.2.1 General features", 1385 ] ], "page_content": "RM0090 Rev 21\n1385/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n35.2.1 \nGeneral features\nThe OTG_HS interface main features are the following:\n•\nIt is USB-IF certified in compliance with the Universal Serial Bus Revision 2.0 \nSpecification\n•\nIt supports 3 PHY interfaces\n–\nAn on-chip full-speed PHY\n–\nAn ULPI interface for external high-speed PHY.\n•\nIt supports the host negotiation protocol (HNP) and the session request protocol (SRP) \n•\nIt allows the host to turn VBUS off to save power in OTG applications, with no need for \nexternal components\n•\nIt allows to monitor VBUS levels using internal comparators\n•\nIt supports dynamic host-peripheral role switching\n•\nIt is software-configurable to operate as:\n–\nAn SRP-capable USB HS/FS peripheral (B-device)\n–\nAn SRP-capable USB HS/FS/low-speed host (A-device) \n–\nAn USB OTG FS dual-role device\n•\nIt supports HS/FS SOFs as well as low-speed (LS) keep-alive tokens with:\n–\nSOF pulse PAD output capability\n–\nSOF pulse internal connection to timer 2 (TIM2)\n–\nConfigurable framing period\n–\nConfigurable end-of-frame interrupt\n•\nIt embeds an internal DMA with shareholding support and software selectable AHB \nburst type in DMA mode\n•\nIt has power saving features such as system clock stop during USB suspend, switching \noff of the digital core internal clock domains, PHY and DFIFO power management\n•\nIt features a dedicated 4-Kbyte data RAM with advanced FIFO management:\n–\nThe memory partition can be configured into different FIFOs to allow flexible and \nefficient use of RAM\n–\nEach FIFO can contain multiple packets\n–\nMemory allocation is performed dynamically\n–\nThe FIFO size can be configured to values that are not powers of 2 to allow the \nuse of contiguous memory locations\n•\nIt ensures a maximum USB bandwidth of up to one frame without application \nintervention\n" }, { "page_number": 1386, "page_indices": { "start_index": 2742477, "end_index": 2743910 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1386 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.2 OTG_HS main features", 1384 ], [ 3, "35.2.2 Host-mode features", 1386 ], [ 3, "35.2.3 Peripheral-mode features", 1386 ], [ 2, "35.3 OTG_HS functional description", 1386 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1386/1757\nRM0090 Rev 21\n35.2.2 \nHost-mode features\nThe OTG_HS interface features in host mode are the following:\n•\nIt requires an external charge pump to generate VBUS\n•\nIt has up to 12 host channels (pipes), each channel being dynamically reconfigurable to \nsupport any kind of USB transfer\n•\nIt features a built-in hardware scheduler holding:\n–\nUp to 8 interrupt plus isochronous transfer requests in the periodic hardware \nqueue\n–\nUp to 8 control plus bulk transfer requests in the nonperiodic hardware queue\n•\nIt manages a shared RX FIFO, a periodic TX FIFO, and a nonperiodic TX FIFO for \nefficient usage of the USB data RAM\n•\nIt features dynamic trimming capability of SOF framing period in host mode.\n35.2.3 \nPeripheral-mode features\nThe OTG_HS interface main features in peripheral mode are the following:\n•\nIt has 1 bidirectional control endpoint 0\n•\nIt has 5 IN endpoints (EP) configurable to support bulk, interrupt or isochronous \ntransfers\n•\nIt has 5 OUT endpoints configurable to support bulk, interrupt or isochronous transfers\n•\nIt manages a shared Rx FIFO and a Tx-OUT FIFO for efficient usage of the USB data \nRAM\n•\nIt manages up to 6 dedicated Tx-IN FIFOs (one for each IN-configured EP) to reduce \nthe application load\n•\nIt features soft disconnect capability\n35.3 \nOTG_HS functional description\nFigure 410 shows the OTG_HS interface block diagram.\n" }, { "page_number": 1387, "page_indices": { "start_index": 2743910, "end_index": 2745387 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1387 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.3 OTG_HS functional description", 1386 ], [ 3, "35.3.1 OTG pins", 1387 ], [ 3, "35.3.2 High-speed OTG PHY", 1387 ] ], "page_content": "RM0090 Rev 21\n1387/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nFigure 410. USB OTG interface block diagram\n1.\nThe USB DMA cannot directly address the internal Flash memory.\n35.3.1 \nOTG pins\n \n35.3.2 \nHigh-speed OTG PHY\nThe USB OTG HS core embeds an ULPI interface to connect an external HS phy.\nMSv43325V1\nData FIFO \nSingle-port RAM \n(SPRAM)\nAHB \nmaster \ninterface\nAHB \nslave \ninterface\nCPU\nMemory\nPeripheral 1\nPeripheral 2\nData FIFO\nRAM interface\nAHB (application bus)\nOTG_HS\n(USB OTG HS core)\nOTG_HS_DP\nOTG_HS_DM\nOTG_HS_ID\nOTG_HS_VBUS\nOTG FS PHY \ntransceiver\nOTG_HS_SOF\nULPI interface (12 pins)\nULPI PHY\n(external\ncomponent)\nUSB2.0 (D+/D-)\nULPI_CK;\nULPI_DIR;\nULPI_STP;\nULPI_NXT;\nULPI_D0-7\nNVIC\nInterrupt: EP1 out\nInterrupt: EP1 in\nInterrupt: global\nInterrupt: async wakeup\nOTG detections\nEXTI\nEXTI\nserial\nTable 207. OTG_HS input/output pins\nSignal name\nSignal type\nDescription\nOTG_HS_DP\nDigital input/output\nUSB OTG D+ line\nOTG_HS_DM\nDigital input/output\nUSB OTG D- line\nOTG_HS_ID\nDigital input\nUSB OTG ID\nOTG_HS_VBUS\nAnalog input\nUSB OTG VBUS\nOTG_HS_SOF\nDigital output\nUSB OTG Start Of Frame (visibility)\nOTG_HS_ULPI_CK\nDigital input\nUSB OTG ULPI clock\nOTG_HS_ULPI_DIR\nDigital input\nUSB OTG ULPI data bus direction control\nOTG_HS_ULPI_STP\nDigital output\nUSB OTG ULPI data stream stop\nOTG_HS_ULPI_NXT\nDigital input\nUSB OTG ULPI next data stream request\nOTG_HS_ULPI_D[0..7]\nDigital input/output\nUSB OTG ULPI 8-bit bi-directional data bus\n" }, { "page_number": 1388, "page_indices": { "start_index": 2745387, "end_index": 2748507 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1388 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.3 OTG_HS functional description", 1386 ], [ 3, "35.3.3 Embedded Full-speed OTG PHY", 1388 ], [ 2, "35.4 OTG dual-role device", 1388 ], [ 3, "35.4.1 ID line detection", 1388 ], [ 3, "35.4.2 HNP dual role device", 1388 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1388/1757\nRM0090 Rev 21\n35.3.3 \nEmbedded Full-speed OTG PHY\nThe full-speed OTG PHY includes the following components:\n•\nFS/LS transceiver module used by both host and Device. It directly drives transmission \nand reception on the single-ended USB lines.\n•\nIntegrated ID pull-up resistor used to sample the ID line for A/B Device identification.\n•\nDP/DM integrated pull-up and pull-down resistors controlled by the OTG_HS core \ndepending on the current role of the device. As a peripheral, it enables the DP pull-up \nresistor to signal full-speed peripheral connections as soon as VBUS is sensed to be at \na valid level (B-session valid). In host mode, pull-down resistors are enabled on both \nDP/DM. Pull-up and pull-down resistors are dynamically switched when the peripheral \nrole is changed via the host negotiation protocol (HNP).\n•\nPull-up/pull-down resistor ECN circuit\nThe DP pull-up consists of 2 resistors controlled separately from the OTG_HS as per \nthe resistor Engineering Change Notice applied to USB Rev2.0. The dynamic trimming \nof the DP pull-up strength allows to achieve a better noise rejection and Tx/Rx signal \nquality.\n•\nVBUS sensing comparators with hysteresis used to detect VBUS_VALID, A-B Session \nValid and session-end voltage thresholds. They are used to drive the session request \nprotocol (SRP), detect valid startup and end-of-session conditions, and constantly \nmonitor the VBUS supply during USB operations.\n•\nVBUS pulsing method circuit used to charge/discharge VBUS through resistors during \nthe SRP (weak drive).\nCaution:\nTo guarantee a correct operation for the USB OTG HS peripheral, the AHB frequency \nshould be higher than 30 MHz.\n35.4 \nOTG dual-role device\n35.4.1 \nID line detection\nThe host or peripheral (the default) role depends on the level of the ID input line. It is \ndetermined when the USB cable is plugged in and depends on which side of the USB cable \nis connected to the micro-AB receptacle:\n•\nIf the B-side of the USB cable is connected with a floating ID wire, the integrated pull-\nup resistor detects a high ID level and the default peripheral role is confirmed. In this \nconfiguration the OTG_HS conforms to the FSM standard described in \nsection 6.8.2. On-The-Go B-device of the USB On-The-Go Supplement, Revision 1.3.\n•\nIf the A-side of the USB cable is connected with a grounded ID, the OTG_HS issues an \nID line status change interrupt (CIDSCHG bit in the OTG_HS_GINTSTS register) for \nhost software initialization, and automatically switches to host role. In this configuration \nthe OTG_HS conforms to the FSM standard described by section 6.8.1: On-The-Go A- \nDevice of the USB On-The-Go Supplement, Revision 1.3.\n35.4.2 \nHNP dual role device\nThe HNP capable bit in the Global USB configuration register (HNPCAP bit in the \nOTG_HS_ GUSBCFG register) configures the OTG_HS core to dynamically change from \nA-host to A-device role and vice-versa, or from B-device to B-host role and vice-versa, \naccording to the host negotiation protocol (HNP). The current device status is defined by the \n" }, { "page_number": 1389, "page_indices": { "start_index": 2748507, "end_index": 2750890 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1389 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.4 OTG dual-role device", 1388 ], [ 3, "35.4.3 SRP dual-role device", 1389 ], [ 2, "35.5 USB functional description in peripheral mode", 1389 ], [ 3, "35.5.1 SRP-capable peripheral", 1389 ] ], "page_content": "RM0090 Rev 21\n1389/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\ncombination of the Connector ID Status bit in the Global OTG control and status register \n(CIDSTS bit in OTG_HS_GOTGCTL) and the current mode of operation bit in the global \ninterrupt and status register (CMOD bit in OTG_HS_GINTSTS).\nThe HNP programming model is described in detail in Section 35.13: OTG_HS \nprogramming model.\n35.4.3 \nSRP dual-role device\nThe SRP capable bit in the global USB configuration register (SRPCAP bit in \nOTG_HS_GUSBCFG) configures the OTG_HS core to switch VBUS off for the A-device in \norder to save power. The A-device is always in charge of driving VBUS regardless of the \nOTG_HS role (host or peripheral). The SRP A/B-device program model is described in \ndetail in Section 35.13: OTG_HS programming model. \n35.5 \nUSB functional description in peripheral mode\nThe OTG_HS operates as an USB peripheral in the following circumstances:\n•\nOTG B-device\nOTG B-device default state if the B-side of USB cable is plugged in\n•\nOTG A-device\nOTG A-device state after the HNP switches the OTG_HS to peripheral role\n•\nB-Device\nIf the ID line is present, functional and connected to the B-side of the USB cable, and \nthe HNP-capable bit in the Global USB Configuration register (HNPCAP bit in \nOTG_HS_GUSBCFG) is cleared (see On-The-Go specification Revision 1.3 section \n6.8.3).\n•\nPeripheral only (see Figure 388: USB peripheral-only connection)\nThe force peripheral mode bit in the Global USB configuration register (FDMOD in \nOTG_HS_GUSBCFG) is set to 1, forcing the OTG_HS core to operate in USB \nperipheral-only mode (see On-The-Go specification Revision 1.3 section 6.8.3). In this \ncase, the ID line is ignored even if it is available on the USB connector.\nNote:\nTo build a bus-powered device architecture in the B-Device or peripheral-only configuration, \nan external regulator must be added to generate the VDD supply voltage from VBUS.\n35.5.1 \nSRP-capable peripheral\nThe SRP capable bit in the Global USB configuration register (SRPCAP bit in \nOTG_HS_GUSBCFG) configures the OTG_HS to support the session request protocol \n(SRP). As a result, it allows the remote A-device to save power by switching VBUS off when \nthe USB session is suspended.\nThe SRP peripheral mode program model is described in detail in Section : B-device \nsession request protocol.\n" }, { "page_number": 1390, "page_indices": { "start_index": 2750890, "end_index": 2753807 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1390 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.5 USB functional description in peripheral mode", 1389 ], [ 3, "35.5.2 Peripheral states", 1390 ], [ 4, "Powered state", 1390 ], [ 4, "Soft disconnect", 1390 ], [ 4, "Default state", 1390 ], [ 4, "Suspended state", 1390 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1390/1757\nRM0090 Rev 21\n35.5.2 \nPeripheral states\nPowered state\nThe VBUS input detects the B-session valid voltage used to put the USB peripheral in the \nPowered state (see USB2.0 specification section 9.1). The OTG_HS then automatically \nconnects the DP pull-up resistor to signal full-speed device connection to the host, and \ngenerates the session request interrupt (SRQINT bit in OTG_HS_GINTSTS) to notify the \nPowered state. The VBUS input also ensures that valid VBUS levels are supplied by the host \nduring USB operations. If VBUS drops below the B-session valid voltage (for example \nbecause power disturbances occurred or the host port has been switched off), the OTG_HS \nautomatically disconnects and the session end detected (SEDET bit in \nOTG_HS_GOTGINT) interrupt is generated to notify that the OTG_HS has exited the \nPowered state. \nIn Powered state, the OTG_HS expects a reset from the host. No other USB operations are \npossible. When a reset is received, the reset detected interrupt (USBRST in \nOTG_HS_GINTSTS) is generated. When the reset is complete, the enumeration done \ninterrupt (ENUMDNE bit in OTG_HS_GINTSTS) is generated and the OTG_HS enters the \nDefault state.\nSoft disconnect\nThe Powered state can be exited by software by using the soft disconnect feature. The DP \npull-up resistor is removed by setting the Soft disconnect bit in the device control register \n(SDIS bit in OTG_HS_DCTL), thus generating a device disconnect detection interrupt on \nthe host side even though the USB cable was not really unplugged from the host port.\nDefault state\nIn Default state the OTG_HS expects to receive a SET_ADDRESS command from the host. \nNo other USB operations are possible. When a valid SET_ADDRESS command is decoded \non the USB, the application writes the corresponding number into the device address field in \nthe device configuration register (DAD bit in OTG_HS_DCFG). The OTG_HS then enters \nthe address state and is ready to answer host transactions at the configured USB address.\nSuspended state\nThe OTG_HS peripheral constantly monitors the USB activity. When the USB remains idle \nfor 3 ms, the early suspend interrupt (ESUSP bit in OTG_HS_GINTSTS) is issued. It is \nconfirmed 3 ms later, if appropriate, by generating a suspend interrupt (USBSUSP bit in \nOTG_HS_GINTSTS). The device suspend bit is then automatically set in the device status \nregister (SUSPSTS bit in OTG_HS_DSTS) and the OTG_HS enters the Suspended state.\nThe device can also exit from the Suspended state by itself. In this case the application sets \nthe remote wake-up signaling bit in the device control register (RWUSIG bit in \nOTG_HS_DCTL) and clears it after 1 to 15 ms.\nWhen a resume signaling is detected from the host, the resume interrupt (WKUPINT bit in \nOTG_HS_GINTSTS) is generated and the device suspend bit is automatically cleared.\n" }, { "page_number": 1391, "page_indices": { "start_index": 2753807, "end_index": 2755969 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1391 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.5 USB functional description in peripheral mode", 1389 ], [ 3, "35.5.3 Peripheral endpoints", 1391 ] ], "page_content": "RM0090 Rev 21\n1391/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n35.5.3 \nPeripheral endpoints\nThe OTG_HS core instantiates the following USB endpoints:\n•\nControl endpoint 0\nThis endpoint is bidirectional and handles control messages only.\nIt has a separate set of registers to handle IN and OUT transactions, as well as \ndedicated control (OTG_HS_DIEPCTL0/OTG_HS_DOEPCTL0), transfer configuration \n(OTG_HS_DIEPTSIZ0/OTG_HS_DIEPTSIZ0), and status-interrupt \n(OTG_HS_DIEPINTx/)OTG_HS_DOEPINT0) registers. The bits available inside the \ncontrol and transfer size registers slightly differ from other endpoints.\n•\n5 IN endpoints\n–\nThey can be configured to support the isochronous, bulk or interrupt transfer type.\n–\nThey feature dedicated control (OTG_HS_DIEPCTLx), transfer configuration \n(OTG_HS_DIEPTSIZx), and status-interrupt (OTG_HS_DIEPINTx) registers.\n–\nThe Device IN endpoints common interrupt mask register (OTG_HS_DIEPMSK) \nallows to enable/disable a single endpoint interrupt source on all of the \nIN endpoints (EP0 included).\n–\nThey support incomplete isochronous IN transfer interrupt (IISOIXFR bit in \nOTG_HS_GINTSTS). This interrupt is asserted when there is at least one \nisochronous IN endpoint for which the transfer is not completed in the current \nframe. This interrupt is asserted along with the end of periodic frame interrupt \n(OTG_HS_GINTSTS/EOPF).\n•\n5 OUT endpoints\n–\nThey can be configured to support the isochronous, bulk or interrupt transfer type.\n–\nThey feature dedicated control (OTG_HS_DOEPCTLx), transfer configuration \n(OTG_HS_DOEPTSIZx) and status-interrupt (OTG_HS_DOEPINTx) registers.\n–\nThe Device Out endpoints common interrupt mask register \n(OTG_HS_DOEPMSK) allows to enable/disable a single endpoint interrupt source \non all OUT endpoints (EP0 included).\n–\nThey support incomplete isochronous OUT transfer interrupt (INCOMPISOOUT \nbit in OTG_HS_GINTSTS). This interrupt is asserted when there is at least one \nisochronous OUT endpoint on which the transfer is not completed in the current \nframe. This interrupt is asserted along with the end of periodic frame interrupt \n(OTG_HS_GINTSTS/EOPF).\n" }, { "page_number": 1392, "page_indices": { "start_index": 2755969, "end_index": 2758203 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1392 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.5 USB functional description in peripheral mode", 1389 ], [ 3, "35.5.3 Peripheral endpoints", 1391 ], [ 4, "Endpoint controls", 1392 ], [ 4, "Endpoint transfer", 1392 ], [ 4, "Endpoint status/interrupt", 1392 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1392/1757\nRM0090 Rev 21\nEndpoint controls\nThe following endpoint controls are available through the device endpoint-x IN/OUT control \nregister (DIEPCTLx/DOEPCTLx):\n•\nEndpoint enable/disable\n•\nEndpoint activation in current configuration\n•\nProgram the USB transfer type (isochronous, bulk, interrupt)\n•\nProgram the supported packet size\n•\nProgram the Tx-FIFO number associated with the IN endpoint\n•\nProgram the expected or transmitted data0/data1 PID (bulk/interrupt only)\n•\nProgram the even/odd frame during which the transaction is received or transmitted \n(isochronous only)\n•\nOptionally program the NAK bit to always send a negative acknowledge to the host \nregardless of the FIFO status\n•\nOptionally program the STALL bit to always stall host tokens to that endpoint\n•\nOptionally program the Snoop mode for OUT endpoint where the received data CRC is \nnot checked\nEndpoint transfer\nThe device endpoint-x transfer size registers (DIEPTSIZx/DOEPTSIZx) allow the application \nto program the transfer size parameters and read the transfer status.\nThe programming operation must be performed before setting the endpoint enable bit in the \nendpoint control register. \nOnce the endpoint is enabled, these fields are read-only as the OTG FS core updates them \nwith the current transfer status.\nThe following transfer parameters can be programmed:\n•\nTransfer size in bytes\n•\nNumber of packets constituting the overall transfer size.\nEndpoint status/interrupt\nThe device endpoint-x interrupt registers (DIEPINTx/DOPEPINTx) indicate the status of an \nendpoint with respect to USB- and AHB-related events. The application must read these \nregisters when the OUT endpoint interrupt bit or the IN endpoint interrupt bit in the core \ninterrupt register (OEPINT bit in OTG_HS_GINTSTS or IEPINT bit in OTG_HS_GINTSTS, \nrespectively) is set. Before the application can read these registers, it must first read the \ndevice all endpoints interrupt register (OTG_HS_DAINT) to get the exact endpoint number \nfor the device endpoint-x interrupt register. The application must clear the appropriate bit in \nthis register to clear the corresponding bits in the DAINT and GINTSTS registers.\n" }, { "page_number": 1393, "page_indices": { "start_index": 2758203, "end_index": 2759125 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1393 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.5 USB functional description in peripheral mode", 1389 ], [ 3, "35.5.3 Peripheral endpoints", 1391 ], [ 4, "Endpoint status/interrupt", 1392 ] ], "page_content": "RM0090 Rev 21\n1393/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nThe peripheral core provides the following status checks and interrupt generation:\n•\nTransfer completed interrupt, indicating that data transfer has completed on both the \napplication (AHB) and USB sides\n•\nSetup stage done (control-out only)\n•\nAssociated transmit FIFO is half or completely empty (in endpoints)\n•\nNAK acknowledge transmitted to the host (isochronous-in only)\n•\nIN token received when Tx-FIFO was empty (bulk-in/interrupt-in only)\n•\nOUT token received when endpoint was not yet enabled\n•\nBabble error condition detected\n•\nEndpoint disable by application is effective\n•\nEndpoint NAK by application is effective (isochronous-in only)\n•\nMore than 3 back-to-back setup packets received (control-out only)\n•\nTimeout condition detected (control-in only)\n•\nIsochronous out packet dropped without generating an interrupt\n" }, { "page_number": 1394, "page_indices": { "start_index": 2759125, "end_index": 2761333 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1394 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.6 USB functional description on host mode", 1394 ], [ 3, "35.6.1 SRP-capable host", 1394 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1394/1757\nRM0090 Rev 21\n35.6 \nUSB functional description on host mode\nThis section gives the functional description of the OTG_HS in the USB host mode. The \nOTG_HS works as a USB host in the following circumstances:\n•\nOTG A-host\nOTG A-device default state when the A-side of the USB cable is plugged in\n•\nOTG B-host\nOTG B-device after HNP switching to the host role\n•\nA-device\nIf the ID line is present, functional and connected to the A-side of the USB cable, and \nthe HNP-capable bit is cleared in the Global USB Configuration register (HNPCAP bit \nin OTG_HS_GUSBCFG). Integrated pull-down resistors are automatically set on the \nDP/DM lines.\n•\nHost only (Figure 389: USB host-only connection).\nThe force host mode bit in the global USB configuration register (FHMOD bit in \nOTG_HS_GUSBCFG) forces the OTG_HS core to operate in USB host-only mode. In \nthis case, the ID line is ignored even if it is available on the USB connector. Integrated \npull-down resistors are automatically set on the OTG_HS_FS_DP/OTG_HS_FS_DM \nlines.\nNote:\nOn-chip 5 V VBUS generation is not supported. As a result, a charge pump or a basic power \nswitch (if a 5 V supply is available on the application board) must be added externally to \ndrive the 5 V VBUS line. The external charge pump can be driven by any GPIO output. This \nis required for the OTG A-host, A-device and host-only configurations.\nThe VBUS input ensures that valid VBUS levels are supplied by the charge pump during USB \noperations while the charge pump overcurrent output can be input to any GPIO pin \nconfigured to generate port interrupts. The overcurrent ISR must promptly disable the VBUS \ngeneration.\nFigure 411. USB host-only connection\n35.6.1 \nSRP-capable host\nSRP support is available through the SRP capable bit in the global USB configuration \nregister (SRPCAP bit in OTG_HS_GUSBCFG). When the SRP feature is enabled, the host \ncan save power by switching off the VBUS power while the USB session is suspended. The \nMSv36915V2\nSTMPS2141STR\nCurrent-limited\n power distribution \nswitch(2)\nOSC_IN\nOSC_OUT\nGPIO\nGPIO + IRQ\nEN\nOvercurrent\n5 V\n5 V Pwr\nVBUS\nDM\nDP\nVSS\nUSB Std-A connector\nVDD\n" }, { "page_number": 1395, "page_indices": { "start_index": 2761333, "end_index": 2764162 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1395 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.6 USB functional description on host mode", 1394 ], [ 3, "35.6.2 USB host states", 1395 ], [ 4, "Host port power", 1395 ], [ 4, "VBUS valid", 1395 ], [ 4, "Detection of peripheral connection by the host", 1395 ], [ 4, "Detection of peripheral disconnection by the host", 1395 ], [ 4, "Host enumeration", 1395 ] ], "page_content": "RM0090 Rev 21\n1395/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nSRP host mode program model is described in detail in Section : A-device session request \nprotocol.\n35.6.2 \nUSB host states\nHost port power \nOn-chip 5 V VBUS generation is not supported. As a result, a charge pump or a basic power \nswitch (if a 5 V supply voltage is available on the application board) must be added \nexternally to drive the 5 V VBUS line. The external charge pump can be driven by any GPIO \noutput. When the application powers on VBUS through the selected GPIO, it must also set \nthe port power bit in the host port control and status register (PPWR bit in OTG_HS_HPRT).\nVBUS valid\nWhen SRP or HNP is enabled the VBUS sensing pin (PB13) pin should be connected to \nVBUS. The VBUS input ensures that valid VBUS levels are supplied by the charge pump \nduring USB operations. Any unforeseen VBUS voltage drop below the VBUS valid threshold \n(4.25 V) generates an OTG interrupt triggered by the session end detected bit (SEDET bit in \nOTG_HS_GOTGINT). The application must then switch the VBUS power off and clear the \nport power bit. \nWhen HNP and SRP are both disabled, the VBUS sensing pin (PB13) should not be \nconnected to VBUS. This pin can be can be used as GPIO.\nThe charge pump overcurrent flag can also be used to prevent electrical damage. Connect \nthe overcurrent flag output from the charge pump to any GPIO input, and configure it to \ngenerate a port interrupt on the active level. The overcurrent ISR must promptly disable the \nVBUS generation and clear the port power bit.\nDetection of peripheral connection by the host\nIf SRP or HNP are enabled, even if USB peripherals or B-devices can be attached at any \ntime, the OTG_HS does not detect a bus connection until the end of the VBUS sensing \n(VBUS over 4.75 V).\nWhen VBUS is at a valid level and a remote B-device is attached, the OTG_HS core issues a \nhost port interrupt triggered by the device connected bit in the host port control and status \nregister (PCDET bit in OTG_HS_HPRT).\nWhen HNP and SRP are both disabled, USB peripherals or B-device are detected as \nsoon as they are connected. The OTG_HS core issues a host port interrupt triggered by \nthe device connected bit in the host port control and status (PCDET bit in OTG_HS_HPRT).\nDetection of peripheral disconnection by the host\nThe peripheral disconnection event triggers the disconnect detected interrupt (DISCINT bit \nin OTG_HS_GINTSTS).\nHost enumeration\nAfter detecting a peripheral connection, the host must start the enumeration process by \nissuing an USB reset and configuration commands to the new peripheral.\nBefore sending an USB reset, the application waits for the OTG interrupt triggered by the \ndebounce done bit (DBCDNE bit in OTG_HS_GOTGINT), which indicates that the bus is \n" }, { "page_number": 1396, "page_indices": { "start_index": 2764162, "end_index": 2766920 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1396 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.6 USB functional description on host mode", 1394 ], [ 3, "35.6.2 USB host states", 1395 ], [ 4, "Host suspend", 1396 ], [ 3, "35.6.3 Host channels", 1396 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1396/1757\nRM0090 Rev 21\nstable again after the electrical debounce caused by the attachment of a pull-up resistor on \nOTG_HS_FS_DP (full speed) or OTG_HS_FS_DM (low speed).\nThe application issues an USB reset (single-ended zero) via the USB by keeping the port \nreset bit set in the Host port control and status register (PRST bit in OTG_HS_HPRT) for a \nminimum of 10 ms and a maximum of 20 ms. The application monitors the time and then \nclears the port reset bit.\nOnce the USB reset sequence has completed, the host port interrupt is triggered by the port \nenable/disable change bit (PENCHNG bit in OTG_HS_HPRT) to inform the application that \nthe speed of the enumerated peripheral can be read from the port speed field in the host \nport control and status register (PSPD bit in OTG_HS_HPRT), and that the host is starting \nto drive SOFs (full speed) or keep-alive tokens (low speed). The host is then ready to \ncomplete the peripheral enumeration by sending peripheral configuration commands.\nHost suspend\nThe application can decide to suspend the USB activity by setting the port suspend bit in the \nhost port control and status register (PSUSP bit in OTG_HS_HPRT). The OTG_HS core \nstops sending SOFs and enters the Suspended state.\nThe Suspended state can be exited on the remote device initiative (remote wake-up). In this \ncase the remote wake-up interrupt (WKUPINT bit in OTG_HS_GINTSTS) is generated upon \ndetection of a remote wake-up event, the port resume bit in the host port control and status \nregister (PRES bit in OTG_HS_HPRT) is set, and a resume signaling is automatically \nissued on the USB. The application must monitor the resume window duration, and then \nclear the port resume bit to exit the Suspended state and restart the SOF.\nIf the Suspended state is exited on the host initiative, the application must set the port \nresume bit to start resume signaling on the host port, monitor the resume window duration \nand then clear the port resume bit.\n35.6.3 \nHost channels\nThe OTG_HS core instantiates 12 host channels. Each host channel supports an USB host \ntransfer (USB pipe). The host is not able to support more than 8 transfer requests \nsimultaneously. If more than 8 transfer requests are pending from the application, the host \ncontroller driver (HCD) must re-allocate channels when they become available, that is, after \nreceiving the transfer completed and channel halted interrupts.\nEach host channel can be configured to support IN/OUT and any type of \nperiodic/nonperiodic transaction. Each host channel has dedicated control (HCCHARx), \ntransfer configuration (HCTSIZx) and status/interrupt (HCINTx) registers with associated \nmask (HCINTMSKx) registers.\n" }, { "page_number": 1397, "page_indices": { "start_index": 2766920, "end_index": 2768890 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1397 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.6 USB functional description on host mode", 1394 ], [ 3, "35.6.3 Host channels", 1396 ], [ 4, "Host channel controls", 1397 ], [ 4, "Host channel transfer", 1397 ], [ 4, "Host channel status/interrupt", 1397 ] ], "page_content": "RM0090 Rev 21\n1397/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nHost channel controls\nThe following host channel controls are available through the host channel-x characteristics \nregister (HCCHARx):\n•\nChannel enable/disable\n•\nProgram the HS/FS/LS speed of target USB peripheral\n•\nProgram the address of target USB peripheral\n•\nProgram the endpoint number of target USB peripheral\n•\nProgram the transfer IN/OUT direction\n•\nProgram the USB transfer type (control, bulk, interrupt, isochronous)\n•\nProgram the maximum packet size (MPS)\n•\nProgram the periodic transfer to be executed during odd/even frames\nHost channel transfer\nThe host channel transfer size registers (HCTSIZx) allow the application to program the \ntransfer size parameters, and read the transfer status.\nThe programming operation must be performed before setting the channel enable bit in the \nhost channel characteristics register. Once the endpoint is enabled, the packet count field is \nread-only as the OTG HS core updates it according to the current transfer status.\nThe following transfer parameters can be programmed:\n•\nTransfer size in bytes\n•\nNumber of packets constituting the overall transfer size\n•\nInitial data PID\nHost channel status/interrupt\nThe host channel-x interrupt register (HCINTx) indicates the status of an endpoint with \nrespect to USB- and AHB-related events. The application must read these register when the \nhost channels interrupt bit in the core interrupt register (HCINT bit in OTG_HS_GINTSTS) is \nset. Before the application can read these registers, it must first read the host all channels \ninterrupt (HCAINT) register to get the exact channel number for the host channel-x interrupt \nregister. The application must clear the appropriate bit in this register to clear the \ncorresponding bits in the HAINT and GINTSTS registers. The mask bits for each interrupt \nsource of each channel are also available in the OTG_HS_HCINTMSK-x register.\n" }, { "page_number": 1398, "page_indices": { "start_index": 2768890, "end_index": 2772016 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1398 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.6 USB functional description on host mode", 1394 ], [ 3, "35.6.4 Host scheduler", 1398 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1398/1757\nRM0090 Rev 21\nThe host core provides the following status checks and interrupt generation:\n•\nTransfer completed interrupt, indicating that the data transfer is complete on both the \napplication (AHB) and USB sides\n•\nChannel stopped due to transfer completed, USB transaction error or disable \ncommand from the application\n•\nAssociated transmit FIFO half or completely empty (IN endpoints)\n•\nACK response received\n•\nNAK response received\n•\nSTALL response received\n•\nUSB transaction error due to CRC failure, timeout, bit stuff error, false EOP\n•\nBabble error\n•\nFrame overrun\n•\nData toggle error\n35.6.4 \nHost scheduler\nThe host core features a built-in hardware scheduler which is able to autonomously re-order \nand manage the USB the transaction requests posted by the application. At the beginning of \neach frame the host executes the periodic (isochronous and interrupt) transactions first, \nfollowed by the nonperiodic (control and bulk) transactions to achieve the higher level of \npriority granted to the isochronous and interrupt transfer types by the USB specification.\nThe host processes the USB transactions through request queues (one for periodic and one \nfor nonperiodic). Each request queue can hold up to 8 entries. Each entry represents a \npending transaction request from the application, and holds the IN or OUT channel number \nalong with other information to perform a transaction on the USB. The order in which the \nrequests are written to the queue determines the sequence of the transactions on the USB \ninterface. \nAt the beginning of each frame, the host processes the periodic request queue first, followed \nby the nonperiodic request queue. The host issues an incomplete periodic transfer interrupt \n(IPXFR bit in OTG_HS_GINTSTS) if an isochronous or interrupt transaction scheduled for \nthe current frame is still pending at the end of the current frame. The OTG HS core is fully \nresponsible for the management of the periodic and nonperiodic request queues.The \nperiodic transmit FIFO and queue status register (HPTXSTS) and nonperiodic transmit \nFIFO and queue status register (HNPTXSTS) are read-only registers which can be used by \nthe application to read the status of each request queue. They contain: \n•\nThe number of free entries currently available in the periodic (nonperiodic) request \nqueue (8 max) \n•\nFree space currently available in the periodic (nonperiodic) Tx-FIFO (out-transactions)\n•\nIN/OUT token, host channel number and other status information.\nAs request queues can hold a maximum of 8 entries each, the application can push to \nschedule host transactions in advance with respect to the moment they physically reach the \nUSB for a maximum of 8 pending periodic transactions plus 8 pending nonperiodic \ntransactions.\nTo post a transaction request to the host scheduler (queue) the application must check that \nthere is at least 1 entry available in the periodic (nonperiodic) request queue by reading the \nPTXQSAV bits in the OTG_HS_HNPTXSTS register or NPTQXSAV bits in the \nOTG_HS_HNPTXSTS register. \n" }, { "page_number": 1399, "page_indices": { "start_index": 2772016, "end_index": 2774484 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1399 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.7 SOF trigger", 1399 ], [ 3, "35.7.1 Host SOFs", 1399 ], [ 3, "35.7.2 Peripheral SOFs", 1399 ] ], "page_content": "RM0090 Rev 21\n1399/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n35.7 \nSOF trigger\nThe OTG FS core allows to monitor, track and configure SOF framing in the host and \nperipheral. It also features an SOF pulse output connectivity.\nThese capabilities are particularly useful to implement adaptive audio clock generation \ntechniques, where the audio peripheral needs to synchronize to the isochronous stream \nprovided by the PC, or the host needs trimming its framing rate according to the \nrequirements of the audio peripheral.\n35.7.1 \nHost SOFs\nIn host mode the number of PHY clocks occurring between the generation of two \nconsecutive SOF (FS) or keep-alive (LS) tokens is programmable in the host frame interval \nregister (OTG_HS_HFIR), thus providing application control over the SOF framing period. \nAn interrupt is generated at any start of frame (SOF bit in OTG_HS_GINTSTS). The current \nframe number and the time remaining until the next SOF are tracked in the host frame \nnumber register (OTG_HS_HFNUM).\nAn SOF pulse signal is generated at any SOF starting token and with a width of 20 HCLK \ncycles. It can be made available externally on the SOF pin using the SOFOUTEN bit in the \nglobal control and configuration register. The SOF pulse is also internally connected to the \ninput trigger of timer 2 (TIM2), so that the input capture feature, the output compare feature \nand the timer can be triggered by the SOF pulse. The TIM2 connection is enabled through \nITR1_RMP bits of TIM2_OR register.\nFigure 412. SOF trigger output to TIM2 ITR1 connection\n35.7.2 \nPeripheral SOFs\nIn peripheral mode, the start of frame interrupt is generated each time an SOF token is \nreceived on the USB (SOF bit in OTG_HS_GINTSTS). The corresponding frame number \ncan be read from the device status register (FNSOF bit in OTG_HS_DSTS). An SOF pulse \nsignal with a width of 20 HCLK cycles is also generated and can be made available \nexternally on the SOF pin by using the SOF output enable bit in the global control and \nconfiguration register (SOFOUTEN bit in OTG_HS_GCCFG). The SOF pulse signal is also \ninternally connected to the TIM2 input trigger, so that the input capture feature, the output \ncompare feature and the timer can be triggered by the SOF pulse (see Figure 412). The \nTIM2 connection is enabled through ITR1_RMP bits of TIM2_OR register.\nSOF\npulse\nITR1\nTIM2\nOTG_HS_Core\nSOF output pulse\nUSB Micro-AB connector\nVBUS\nDP\nDM\nID\nai16092\n" }, { "page_number": 1400, "page_indices": { "start_index": 2774484, "end_index": 2776911 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1400 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.8 OTG_HS low-power modes", 1400 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1400/1757\nRM0090 Rev 21\nThe end of periodic frame interrupt (GINTSTS/EOPF) is used to notify the application when \n80%, 85%, 90% or 95% of the time frame interval elapsed depending on the periodic frame \ninterval field in the device configuration register (PFIVL bit in OTG_HS_DCFG). \nThis feature can be used to determine if all of the isochronous traffic for that frame is \ncomplete.\n35.8 \nOTG_HS low-power modes\nTable 208 below defines the STM32 low power modes and their compatibility with the OTG.\n \nThe following bits and procedures reduce power consumption.\nThe power consumption of the OTG PHY is controlled by three bits in the general core \nconfiguration register:\n•\nPHY power down (GCCFG/PWRDWN)\nThis bit switches on/off the PHY full-speed transceiver module. It must be preliminarily \nset to allow any USB operation.\n•\nA-VBUS sensing enable (GCCFG/VBUSASEN)\nThis bit switches on/off the VBUS comparators associated with A-device operations. It \nmust be set when in A-device (USB host) mode and during HNP.\n•\nB-VBUS sensing enable (GCCFG/VBUSASEN)\nThis bit switches on/off the VBUS comparators associated with B-device operations. It \nmust be set when in B-device (USB peripheral) mode and during HNP.\nPower reduction techniques are available in the USB suspended state, when the USB \nsession is not yet valid or the device is disconnected.\n•\nStop PHY clock (STPPCLK bit in OTG_HS_PCGCCTL)\n–\nWhen setting the stop PHY clock bit in the clock gating control register, most of the \nclock domain internal to the OTG high-speed core is switched off by clock gating. \nTable 208. Compatibility of STM32 low power modes with the OTG\nMode\nDescription\nUSB compatibility\nRun\nMCU fully active\nRequired when USB not in \nsuspend state.\nSleep\nUSB suspend exit causes the device to exit Sleep mode. Peripheral \nregisters content is kept.\nAvailable while USB is in \nsuspend state. \nStop\nUSB suspend exit causes the device to exit Stop mode. Peripheral \nregisters content is kept(1).\nAvailable while USB is in \nsuspend state. \nStandby\nPowered-down. The peripheral must be reinitialized after exiting \nStandby mode.\nNot compatible with USB \napplications.\n1.\nWithin Stop mode there are different possible settings. Some restrictions may also exist, please refer to Section 5: Power \ncontroller (PWR) to understand which (if any) restrictions apply when using OTG.\n" }, { "page_number": 1401, "page_indices": { "start_index": 2776911, "end_index": 2778946 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1401 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.9 Dynamic update of the OTG_HS_HFIR register", 1401 ] ], "page_content": "RM0090 Rev 21\n1401/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nThe dynamic power consumption due to the USB clock switching activity is cut \neven if the clock input is kept running by the application\n–\nMost of the transceiver is also disabled, and only the part in charge of detecting \nthe asynchronous resume or remote wake-up event is kept alive.\n•\nGate HCLK (GATEHCLK bit in OTG_HS_PCGCCTL)\nWhen setting the Gate HCLK bit in the clock gating control register, most of the system \nclock domain internal to the OTG_HS core is switched off by clock gating. Only the \nregister read and write interface is kept alive. The dynamic power consumption due to \nthe USB clock switching activity is cut even if the system clock is kept running by the \napplication for other purposes.\n•\nUSB system stop\n–\nWhen the OTG_HS is in USB suspended state, the application can decide to \ndrastically reduce the overall power consumption by shutting down all the clock \nsources in the system. USB System Stop is activated by first setting the Stop PHY \nclock bit and then configuring the system deep sleep mode in the powercontrol \nsystem module (PWR).\n–\nThe OTG_HS core automatically reactivates both system and USB clocks by \nasynchronous detection of remote wake-up (as an host) or resume (as a Device) \nsignaling on the USB.\n35.9 \nDynamic update of the OTG_HS_HFIR register\nThe USB core embeds a dynamic trimming capability of micro-SOF framing period in host \nmode allowing to synchronize an external device with the micro-SOF frames. \nWhen the OTG_HS_HFIR register is changed within a current micro-SOF frame, the SOF \nperiod correction is applied in the next frame as described in Figure 413.\nFigure 413. Updating OTG_HS_HFIR dynamically\n400\n…\n…\n…\n…\n…\n450\nLatency \nSOF\nreload \nOTG_HS_HFIR \nwrite \nvalue \nFrame\ntimer \nOld OTG_HS_HIFR value\n= 400 periods\nOTG_HS_HIFR value\n= 450 periods+HIFR write latency\nNew OTG_HS_HIFR value\n= 450 periods\n1\n400\n0\n399\n1\n400\n0\n399\n450\n449\n1\n450\n0\n449\n1\n450\n0\n449\nOTG_HS_HFIR \nai18439b\n" }, { "page_number": 1402, "page_indices": { "start_index": 2778946, "end_index": 2781753 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1402 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.10 FIFO RAM allocation", 1402 ], [ 3, "35.10.1 Peripheral mode", 1402 ], [ 4, "Receive FIFO RAM", 1402 ], [ 4, "Transmit FIFO RAM", 1402 ], [ 3, "35.10.2 Host mode", 1402 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1402/1757\nRM0090 Rev 21\n35.10 \nFIFO RAM allocation\n35.10.1 \nPeripheral mode\nReceive FIFO RAM\nFor Receive FIFO RAM, the application should allocate RAM for SETUP packets: 10 \nlocations must be reserved in the receive FIFO to receive SETUP packets on control \nendpoints. These locations are reserved for SETUP packets and are not used by the core to \nwrite any other data. \nOne location must be allocated for Global OUT NAK. Status information are also written to \nthe FIFO along with each received packet. Therefore, a minimum space of (Largest Packet \nSize / 4) + 1 must be allocated to receive packets. If a high-bandwidth endpoint or multiple \nisochronous endpoints are enabled, at least two spaces of (Largest Packet Size / 4) + 1 \nmust be allotted to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 1 \nspaces are recommended so that when the previous packet is being transferred to AHB, the \nUSB can receive the subsequent packet. \nAlong with each endpoints last packet, transfer complete status information are also pushed \nto the FIFO. Typically, one location for each OUT endpoint is recommended.\nTransmit FIFO RAM\nFor Transmit FIFO RAM, the minimum RAM space required for each IN Endpoint Transmit \nFIFO is the maximum packet size for this IN endpoint. \nNote:\nMore space allocated in the transmit IN Endpoint FIFO results in a better performance on \nthe USB. \n35.10.2 \nHost mode\nReceive FIFO RAM\nFor Receive FIFO RAM allocation, Status information are written to the FIFO along with \neach received packet. Therefore, a minimum space of (Largest Packet Size / 4) + 1 must be \nallocated to receive packets. If a high-bandwidth channel or multiple isochronous channels \nare enabled, at least two spaces of (Largest Packet Size / 4) + 1 must be allocated to \nreceive back-to-back packets. Typically, two (Largest Packet Size / 4) + 1 spaces are \nrecommended so that when the previous packet is being transferred to AHB, the USB can \nreceive the subsequent packet. \nAlong with each host channels last packet, transfer complete status information are also \npushed to the FIFO. As a consequence, one location must be allocated to store this data. \nTransmit FIFO RAM\nFor Transmit FIFO RAM allocation, the minimum amount of RAM required for the host \nnonperiodic Transmit FIFO is the largest maximum packet size for all supported nonperiodic \nOUT channels. Typically, a space corresponding to two Largest Packet Size is \nrecommended, so that when the current packet is being transferred to the USB, the AHB \ncan transmit the subsequent packet.\nThe minimum amount of RAM required for Host periodic Transmit FIFO is the largest \nmaximum packet size for all supported periodic OUT channels. If there is at least one High \n" }, { "page_number": 1403, "page_indices": { "start_index": 2781753, "end_index": 2782771 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1403 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.11 OTG_HS interrupts", 1403 ] ], "page_content": "RM0090 Rev 21\n1403/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBandwidth Isochronous OUT endpoint, then the space must be at least two times the \nmaximum packet size for that channel. \nNote:\nMore space allocated in the Transmit nonperiodic FIFO results in better performance on the \nUSB.\nWhen operating in DMA mode, the DMA address register for each host channel (HCDMAn) \nis stored in the SPRAM (FIFO). One location for each channel must be reserved for this.\n35.11 \nOTG_HS interrupts\nWhen the OTG_HS controller is operating in one mode, either peripheral or host, the \napplication must not access registers from the other mode. If an illegal access occurs, a \nmode mismatch interrupt is generated and reflected in the Core interrupt register (MMIS bit \nin the OTG_HS_GINTSTS register). When the core switches from one mode to the other, \nthe registers in the new mode of operation must be reprogrammed as they would be after a \npower-on reset.\nFigure 414 shows the interrupt hierarchy.\n" }, { "page_number": 1404, "page_indices": { "start_index": 2782771, "end_index": 2784218 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1404 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.11 OTG_HS interrupts", 1403 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1404/1757\nRM0090 Rev 21\nFigure 414. Interrupt hierarchy\n1.\nOTG_HS_WKUP becomes active (high state) when resume condition occurs during L1 SLEEP or L2 SUSPEND states.\nMSv47472V2\nOTG_DEACHINTMSK\nDevice each endpoint interrupt mask \nregister\nOTG_DAINTMSK\nDevice all endpoints interrupt mask \nregister\nOTG_DIEPMSK/\nOTG_DOEPMSK\nDevice IN/OUT endpoints common \ninterrupt mask register\nOTG_DIEPEACHMSK1/\nOTG_DOEPEACHMSK1\nDevice each IN/OUT endpoint interrupt \nmask registers\nOTG_HCTINTMSKx\nHost channels interrupt mask registers\nOTG_HAINTMSK\nHost all channels interrupt mask register\n31:26\n25 24\n23:20\n19 18\n17:3\n2\n1:0\nOTG_HCTINTx\nHost channels interrupt registers\nOTG_HAINT\nHost all channels interrupt register\nOTG_HPRT\nHost port control and status register\nOTG_DAINT\nDevice all endpoints interrupt register\n(15 + #EP):16\nOUT endpoints\n(#EP-1):0\nIN endpoints\nOTG_GOTGINT\nOTG interrupt register\nOTG_DEACHINT\nDevice each endpoint interrupt register\n17\nEP1OUT\n1\nEP1IN\nOTG_DIEPINTx/\nOTG_DOEPINTx\nDevice IN/OUT endpoint interrupt \nregisters\nOTG_GINTSTS\nCore register interrupt\nOTG_GINTMSK\nCore interrupt mask register\nOTG_AHBCFG\nAHB configuration register\nGlobal interrupt mask (bit 0)\nOR\nAND\nAND\n(1)\nx = 0\nx = #HC-1\nx = 0\nx = #HC-1\nHCINT\nHPRTINT\nOEPINP\nIEPINT\nOTGINT\n...\n...\nGlobal interrupt\nOTG_HS\nWakeup interrupt \nOTG_HS_WKUP\nEP1_OUT interrupt OTG_HS_EP1_OUT\nEP1_IN interrupt OTG_HS_EP1_IN\n" }, { "page_number": 1405, "page_indices": { "start_index": 2784218, "end_index": 2785734 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1405 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.1 CSR memory map", 1405 ] ], "page_content": "RM0090 Rev 21\n1405/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n35.12 \nOTG_HS control and status registers\nBy reading from and writing to the control and status registers (CSRs) through the AHB \nslave interface, the application controls the OTG_HS controller. These registers are 32 bits \nwide, and the addresses are 32-bit block aligned. The OTG_HS registers must be accessed \nby words (32 bits). CSRs are classified as follows:\n•\nCore global registers\n•\nHost-mode registers\n•\nHost global registers\n•\nHost port CSRs\n•\nHost channel-specific registers\n•\nDevice-mode registers\n•\nDevice global registers\n•\nDevice endpoint-specific registers\n•\nPower and clock-gating registers\n•\nData FIFO (DFIFO) access registers\nOnly the Core global, Power and clock-gating, Data FIFO access, and host port control and \nstatus registers can be accessed in both host and peripheral modes. When the OTG_HS \ncontroller is operating in one mode, either peripheral or host, the application must not \naccess registers from the other mode. If an illegal access occurs, a mode mismatch \ninterrupt is generated and reflected in the Core interrupt register (MMIS bit in the \nOTG_HS_GINTSTS register). When the core switches from one mode to the other, the \nregisters in the new mode of operation must be reprogrammed as they would be after a \npower-on reset.\n \n35.12.1 \nCSR memory map\nThe host and peripheral mode registers occupy different addresses. All registers are \nimplemented in the AHB clock domain.\n" }, { "page_number": 1406, "page_indices": { "start_index": 2785734, "end_index": 2787173 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1406 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.1 CSR memory map", 1405 ], [ 4, "Global CSR map", 1406 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1406/1757\nRM0090 Rev 21\nFigure 415. CSR memory map\n1.\nx = 5 in peripheral mode and x = 11 in host mode.\nGlobal CSR map\nThese registers are available in both host and peripheral modes.\n \n0000h\nCore global CSRs (1 Kbyte)\n0400h\nHost mode CSRs (1 Kbyte)\n0800h\nDevice mode CSRs (1.5 Kbyte)\n0E00h\nPower and clock gating CSRs (0.5 Kbyte)\n1000h\nDevice EP 0/Host channel 0 FIFO (4 Kbyte)\n2000h\nDevice EP1/Host channel 1 FIFO (4 Kbyte)\n3000h\nDevice EP (x – 1)(1)/Host channel (x – 1)(1) FIFO (4 Kbyte)\nDevice EP x(1)/Host channel x(1) FIFO (4 Kbyte)\nReserved\nDFIFO\npush/pop\nto this region\n2 0000h\n3 FFFFh\nDirect access to data FIFO RAM\nfor debugging (128 Kbyte)\nDFIFO\ndebug read/\nwrite to this\nregion\nai15615b\nTable 209. Core global control and status registers (CSRs)\nAcronym\nAddress \noffset\nRegister name\nOTG_HS_GOTGCTL\n0x000\nOTG_HS control and status register (OTG_HS_GOTGCTL) on page 1411\nOTG_HS_GOTGINT\n0x004\nOTG_HS interrupt register (OTG_HS_GOTGINT) on page 1412\nOTG_HS_GAHBCFG\n0x008\nOTG_HS AHB configuration register (OTG_HS_GAHBCFG) on page 1414\nOTG_HS_GUSBCFG\n0x00C\nOTG_HS USB configuration register (OTG_HS_GUSBCFG) on page 1415\nOTG_HS_GRSTCTL\n0x010\nOTG_HS reset register (OTG_HS_GRSTCTL) on page 1418\nOTG_HS_GINTSTS\n0x014\nOTG_HS core interrupt register (OTG_HS_GINTSTS) on page 1421\nOTG_HS_GINTMSK\n0x018\nOTG_HS interrupt mask register (OTG_HS_GINTMSK) on page 1425\n" }, { "page_number": 1407, "page_indices": { "start_index": 2787173, "end_index": 2789181 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1407 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.1 CSR memory map", 1405 ], [ 4, "Host-mode CSR map", 1407 ] ], "page_content": "RM0090 Rev 21\n1407/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n \nHost-mode CSR map\nThese registers must be programmed every time the core changes to host mode.\n \nOTG_HS_GRXSTSR\n0x01C\nOTG_HS Receive status debug read/OTG status read and pop registers \n(OTG_HS_GRXSTSR/OTG_HS_GRXSTSP) on page 1428\nOTG_HS_GRXSTSP\n0x020\nOTG_HS_GRXFSIZ\n0x024\nOTG_HS Receive FIFO size register (OTG_HS_GRXFSIZ) on page 1429\nOTG_HS_GNPTXFSIZ/\nOTG_HS_TX0FSIZ\n0x028\nOTG_HS nonperiodic transmit FIFO size/Endpoint 0 transmit FIFO size \nregister (OTG_HS_GNPTXFSIZ/OTG_HS_TX0FSIZ) on page 1430\nOTG_HS_GNPTXSTS\n0x02C\nOTG_HS nonperiodic transmit FIFO/queue status register \n(OTG_HS_GNPTXSTS) on page 1430\nOTG_HS_GCCFG\n0x038\nOTG_HS general core configuration register (OTG_HS_GCCFG) on \npage 1431\nOTG_HS_CID\n0x03C\nOTG_HS core ID register (OTG_HS_CID) on page 1432\nOTG_HS_HPTXFSIZ\n0x100\nOTG_HS Host periodic transmit FIFO size register (OTG_HS_HPTXFSIZ) \non page 1432\nOTG_HS_DIEPTXFx\n0x104\n0x108\n...\n0x114\nOTG_HS device IN endpoint transmit FIFO size register \n(OTG_HS_DIEPTXFx) (x = 1..5, where x is the FIFO_number) on page 1433\nTable 209. Core global control and status registers (CSRs) (continued)\nAcronym\nAddress \noffset\nRegister name\nTable 210. Host-mode control and status registers (CSRs)\nAcronym\nOffset \naddress\nRegister name\nOTG_HS_HCFG\n0x400\nOTG_HS host configuration register (OTG_HS_HCFG) on page 1433\nOTG_HS_HFIR\n0x404\nOTG_HS Host frame interval register (OTG_HS_HFIR) on page 1435\nOTG_HS_HFNUM\n0x408\nOTG_HS host frame number/frame time remaining register \n(OTG_HS_HFNUM) on page 1435\nOTG_HS_HPTXSTS\n0x410\nOTG_HS_Host periodic transmit FIFO/queue status register \n(OTG_HS_HPTXSTS) on page 1436\nOTG_HS_HAINT\n0x414\nOTG_HS Host all channels interrupt register (OTG_HS_HAINT) on \npage 1437\nOTG_HS_HAINTMSK\n0x418\nOTG_HS host all channels interrupt mask register (OTG_HS_HAINTMSK) \non page 1437\nOTG_HS_HPRT\n0x440\nOTG_HS host port control and status register (OTG_HS_HPRT) on \npage 1438\n" }, { "page_number": 1408, "page_indices": { "start_index": 2789181, "end_index": 2791338 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1408 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.1 CSR memory map", 1405 ], [ 4, "Device-mode CSR map", 1408 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1408/1757\nRM0090 Rev 21\nDevice-mode CSR map\nThese registers must be programmed every time the core changes to peripheral mode.\n \nOTG_HS_HCCHARx\n0x500\n0x520\n...\n0x660\nOTG_HS host channel-x characteristics register (OTG_HS_HCCHARx) \n(x = 0..11, where x = Channel_number) on page 1440\nOTG_HS_HCSPLTx\n0x504\nOTG_HS host channel-x split control register (OTG_HS_HCSPLTx) \n(x = 0..11, where x = Channel_number) on page 1442\nOTG_HS_HCINTx\n0x508\nOTG_HS host channel-x interrupt register (OTG_HS_HCINTx) (x = 0..11, \nwhere x = Channel_number) on page 1443\nOTG_HS_HCINTMSKx\n0x50C\nOTG_HS host channel-x interrupt mask register (OTG_HS_HCINTMSKx) \n(x = 0..11, where x = Channel_number) on page 1444\nOTG_HS_HCTSIZx\n0x510\nOTG_HS host channel-x transfer size register (OTG_HS_HCTSIZx) \n(x = 0..11, where x = Channel_number) on page 1445\nOTG_HS_HCDMAx\n0x514\nOTG_HS host channel-x DMA address register (OTG_HS_HCDMAx) \n(x = 0..11, where x = Channel_number) on page 1446\nTable 210. Host-mode control and status registers (CSRs) (continued)\nAcronym\nOffset \naddress\nRegister name\nTable 211. Device-mode control and status registers\nAcronym\nOffset \naddress\nRegister name\nOTG_HS_DCFG\n0x800\nOTG_HS device configuration register (OTG_HS_DCFG) on \npage 1446\nOTG_HS_DCTL\n0x804\nOTG_HS device control register (OTG_HS_DCTL) on page 1448\nOTG_HS_DSTS\n0x808\nOTG_HS device status register (OTG_HS_DSTS) on page 1450\nOTG_HS_DIEPMSK\n0x810\nOTG_HS device IN endpoint common interrupt mask register \n(OTG_HS_DIEPMSK) on page 1451\nOTG_HS_DOEPMSK\n0x814\nOTG_HS device OUT endpoint common interrupt mask register \n(OTG_HS_DOEPMSK) on page 1452\nOTG_HS_DAINT\n0x818\nOTG_HS device all endpoints interrupt register (OTG_HS_DAINT) \non page 1453\nOTG_HS_DAINTMSK\n0x81C\nOTG_HS all endpoints interrupt mask register \n(OTG_HS_DAINTMSK) on page 1454\nOTG_HS_DVBUSDIS\n0x828\nOTG_HS device VBUS discharge time register \n(OTG_HS_DVBUSDIS) on page 1454\nOTG_HS_DVBUSPULSE\n0x82C\nOTG_HS device VBUS pulsing time register \n(OTG_HS_DVBUSPULSE) on page 1455\nOTG_HS_DTHRCTL\n0x830\nOTG_HS Device threshold control register (OTG_HS_DTHRCTL) \non page 1456\n" }, { "page_number": 1409, "page_indices": { "start_index": 2791338, "end_index": 2793341 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1409 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.1 CSR memory map", 1405 ], [ 4, "Device-mode CSR map", 1408 ] ], "page_content": "RM0090 Rev 21\n1409/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS_DIEPEMPMSK\n0x834\nOTG_HS device IN endpoint FIFO empty interrupt mask register: \n(OTG_HS_DIEPEMPMSK) on page 1457\nOTG_HS_DEACHINT\n0x838\nOTG_HS device each endpoint interrupt register \n(OTG_HS_DEACHINT) on page 1457\nOTG_HS_DEACHINTMSK\n0x83C\nOTG_HS device each endpoint interrupt register mask \n(OTG_HS_DEACHINTMSK) on page 1458\nOTG_HS_DIEPEACHMSK1\n0x844\nOTG_HS device each in endpoint-1 interrupt register \n(OTG_HS_DIEPEACHMSK1) on page 1458\nOTG_HS_DOEPEACHMSK1\n0x884\nOTG_HS device each OUT endpoint-1 interrupt register \n(OTG_HS_DOEPEACHMSK1) on page 1459\nOTG_HS_DIEPCTLx\n0x900\n0x920\n...\n0x9A0\nOTG device endpoint-x control register (OTG_HS_DIEPCTLx) (x = \n0..5, where x = Endpoint_number) on page 1460\nOTG_HS_DIEPINTx\n0x908\nOTG_HS device endpoint-x interrupt register \n(OTG_HS_DIEPINTx) (x = 0..5, where x = Endpoint_number) on \npage 1467\nOTG_HS_DIEPTSIZ0\n0x910\nOTG_HS device IN endpoint 0 transfer size register \n(OTG_HS_DIEPTSIZ0) on page 1470\nOTG_HS_DIEPDMAx/\nOTG_HS_DOEPDMAx\n0x914/0xB14\nOTG_HS device endpoint-x DMA address register \n(OTG_HS_DIEPDMAx / OTG_HS_DOEPDMAx) (x = 0..5, where \nx = Endpoint_number) on page 1474\nOTG_HS_DTXFSTSx \n0x918\nOTG_HS device IN endpoint transmit FIFO status register \n(OTG_HS_DTXFSTSx) (x = 0..5, where x = Endpoint_number) on \npage 1473\nOTG_HS_DIEPTSIZx\n0x930\n0x950\n...\n0x9B0\nOTG_HS device endpoint-x transfer size register \n(OTG_HS_DIEPTSIZx) (x = 1..5, where x = Endpoint_number) on \npage 1472\nOTG_HS_DOEPCTL0\n0xB00\nOTG_HS device control OUT endpoint 0 control register \n(OTG_HS_DOEPCTL0) on page 1463\nOTG_HS_DOEPSIZ0\n0xB10\nOTG_HS device OUT endpoint 0 transfer size register \n(OTG_HS_DOEPTSIZ0) on page 1471\nOTG_HS_DOEPCTLx\n0xB20\n0xB40\n...\n0xBA0\nOTG_HS device endpoint-x control register \n(OTG_HS_DOEPCTLx) (x = 1..5, where x = Endpoint_number) on \npage 1464\nTable 211. Device-mode control and status registers (continued)\nAcronym\nOffset \naddress\nRegister name\n" }, { "page_number": 1410, "page_indices": { "start_index": 2793341, "end_index": 2795333 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1410 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.1 CSR memory map", 1405 ], [ 4, "Data FIFO (DFIFO) access register map", 1410 ], [ 4, "Power and clock gating CSR map", 1410 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1410/1757\nRM0090 Rev 21\nData FIFO (DFIFO) access register map\nThese registers, available in both host and peripheral modes, are used to read or write the \nFIFO space for a specific endpoint or a channel, in a given direction. If a host channel is of \ntype IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type \nOUT, the FIFO can only be written on the channel.\n \nPower and clock gating CSR map\nThere is a single register for power and clock gating. It is available in both host and \nperipheral modes.\n \n35.12.2 \nOTG_HS global registers\nThese registers are available in both host and peripheral modes, and do not need to be \nreprogrammed when switching between these modes.\nOTG_HS_DOEPINTx\n0xB08\n0xB28\n...\n0xBA8\nOTG_HS device endpoint-x interrupt register \n(OTG_HS_DOEPINTx) (x = 0..5, where x = Endpoint_number) on \npage 1469\nOTG_HS_DOEPTSIZx\n0xB30\n0xB50\n...\n0xBB0\nOTG_HS device endpoint-x transfer size register \n(OTG_HS_DOEPTSIZx) (x = 1..5, where x = Endpoint_number) \non page 1473\nTable 211. Device-mode control and status registers (continued)\nAcronym\nOffset \naddress\nRegister name\nTable 212. Data FIFO (DFIFO) access register map\nFIFO access register section\nAddress range\nAccess\nDevice IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access\nDevice OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access\n0x1000–0x1FFC\nw\nr\nDevice IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access\nDevice OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access\n0x2000–0x2FFC\nw\nr\n...\n...\n...\nDevice IN Endpoint x(1)/Host OUT Channel x(1): DFIFO Write Access\nDevice OUT Endpoint x(1)/Host IN Channel x(1): DFIFO Read Access\n1.\nWhere x is 5 in peripheral mode and 11 in host mode.\n0xX000–0xXFFC\nw\nr\nTable 213. Power and clock gating control and status registers\nRegister name\nAcronym\nOffset address: 0xE00–0xFFF\nPower and clock gating control register\nOTG_HS_PCGCCTL\n0xE00-0xE04\nReserved\n-\n0xE05–0xFFF\n" }, { "page_number": 1411, "page_indices": { "start_index": 2795333, "end_index": 2797241 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1411 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS control and status register (OTG_HS_GOTGCTL)", 1411 ] ], "page_content": "RM0090 Rev 21\n1411/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBit values in the register descriptions are expressed in binary unless otherwise specified.\nOTG_HS control and status register (OTG_HS_GOTGCTL)\nAddress offset: 0x000\nReset value: 0x0001 0000\nThe OTG control and status register controls the behavior and reflects the status of the OTG \nfunction of the core.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBSVLD\nASVLD\nDBCT\nCIDSTS\nReserved\nDHNPEN\nHSHNPEN\nHNPRQ\nHNGSCS\nReserved\nSRQ\nSRQSCS\nr\nr\nr\nr\nrw\nrw\nrw\nr\nrw\nr\nBits 31:20 Reserved, must be kept at reset value.\nBit 19 BSVLD: B-session valid\nIndicates the peripheral mode transceiver status.\n0: B-session is not valid.\n1: B-session is valid.\nIn OTG mode, you can use this bit to determine if the device is connected or disconnected.\nNote: Only accessible in peripheral mode.\nBit 18 ASVLD: A-session valid\nIndicates the host mode transceiver status.\n0: A-session is not valid\n1: A-session is valid\nNote: Only accessible in host mode.\nBit 17 DBCT: Long/short debounce time\nIndicates the debounce time of a detected connection.\n0: Long debounce time, used for physical connections (100 ms + 2.5 µs)\n1: Short debounce time, used for soft connections (2.5 µs)\nNote: Only accessible in host mode.\nBit 16 CIDSTS: Connector ID status\nIndicates the connector ID status on a connect event.\n0: The OTG_HS controller is in A-device mode\n1: The OTG_HS controller is in B-device mode\nNote: Accessible in both peripheral and host modes.\nBits 15:12 Reserved, must be kept at reset value.\nBit 11 DHNPEN: Device HNP enabled\nThe application sets this bit when it successfully receives a SetFeature.SetHNPEnable \ncommand from the connected USB host.\n0: HNP is not enabled in the application\n1: HNP is enabled in the application\nNote: Only accessible in peripheral mode.\n" }, { "page_number": 1412, "page_indices": { "start_index": 2797241, "end_index": 2799434 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1412 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS interrupt register (OTG_HS_GOTGINT)", 1412 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1412/1757\nRM0090 Rev 21\nOTG_HS interrupt register (OTG_HS_GOTGINT)\nAddress offset: 0x04\nReset value: 0x0000 0000\nThe application reads this register whenever there is an OTG interrupt and clears the bits in \nthis register to clear the OTG interrupt.\nBit 10 HSHNPEN: Host set HNP enable\nThe application sets this bit when it has successfully enabled HNP (using the \nSetFeature.SetHNPEnable command) on the connected device.\n0: Host Set HNP is not enabled\n1: Host Set HNP is enabled\nNote: Only accessible in host mode.\nBit 9 HNPRQ: HNP request\nThe application sets this bit to initiate an HNP request to the connected USB host. The \napplication can clear this bit by writing a 0 when the host negotiation success status change \nbit in the OTG interrupt register (HNSSCHG bit in OTG_HS_GOTGINT) is set. The core \nclears this bit when the HNSSCHG bit is cleared.\n0: No HNP request\n1: HNP request\nNote: Only accessible in peripheral mode.\nBit 8 HNGSCS: Host negotiation success\nThe core sets this bit when host negotiation is successful. The core clears this bit when the \nHNP Request (HNPRQ) bit in this register is set.\n0: Host negotiation failure\n1: Host negotiation success\nNote: Only accessible in peripheral mode.\nBits 7:2 Reserved, must be kept at reset value.\nBit 1 SRQ: Session request\nThe application sets this bit to initiate a session request on the USB. The application can \nclear this bit by writing a 0 when the host negotiation success status change bit in the OTG \nInterrupt register (HNSSCHG bit in OTG_HS_GOTGINT) is set. The core clears this bit when \nthe HNSSCHG bit is cleared.\nIf you use the USB 1.1 full-speed serial transceiver interface to initiate the session request, \nthe application must wait until VBUS discharges to 0.2 V, after the B-Session Valid bit in this \nregister (BSVLD bit in OTG_HS_GOTGCTL) is cleared.\n0: No session request\n1: Session request\nNote: Only accessible in peripheral mode.\nBit 0 SRQSCS: Session request success\nThe core sets this bit when a session request initiation is successful.\n0: Session request failure\n1: Session request success\nNote: Only accessible in peripheral mode.\n" }, { "page_number": 1413, "page_indices": { "start_index": 2799434, "end_index": 2801570 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1413 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS interrupt register (OTG_HS_GOTGINT)", 1412 ] ], "page_content": "RM0090 Rev 21\n1413/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDBCDNE\nADTOCHG\nHNGDET\nReserved\nHNSSCHG\nSRSSCHG\nReserved\nSEDET\nRes.\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nBits 31:20 Reserved, must be kept at reset value.\nBit 19 DBCDNE: Debounce done\nThe core sets this bit when the debounce is completed after the device connect. The \napplication can start driving USB reset after seeing this interrupt. This bit is only valid when \nthe HNP Capable or SRP Capable bit is set in the Core USB Configuration register (HNPCAP \nbit or SRPCAP bit in OTG_HS_GUSBCFG, respectively).\nNote: Only accessible in host mode.\nBit 18 ADTOCHG: A-device timeout change\nThe core sets this bit to indicate that the A-device has timed out while waiting for the B-device \nto connect.\nNote: Accessible in both peripheral and host modes.\nBit 17 HNGDET: Host negotiation detected\nThe core sets this bit when it detects a host negotiation request on the USB. \nNote: Accessible in both peripheral and host modes.\nBits 16:10 Reserved, must be kept at reset value.\nBit 9 HNSSCHG: Host negotiation success status change\nThe core sets this bit on the success or failure of a USB host negotiation request. The \napplication must read the host negotiation success bit of the OTG Control and Status register \n(HNGSCS in OTG_HS_GOTGCTL) to check for success or failure.\nNote: Accessible in both peripheral and host modes.\nBits 7:3 Reserved, must be kept at reset value.\nBit 8 SRSSCHG: Session request success status change\nThe core sets this bit on the success or failure of a session request. The application must \nread the session request success bit in the OTG Control and status register (SRQSCS bit in \nOTG_HS_GOTGCTL) to check for success or failure.\nNote: Accessible in both peripheral and host modes.\nBit 2 SEDET: Session end detected\nThe core sets this bit to indicate that the level of the voltage on VBUS is no longer valid for a \nB-device session when VBUS < 0.8 V.\nBits 1:0 Reserved, must be kept at reset value.\n" }, { "page_number": 1414, "page_indices": { "start_index": 2801570, "end_index": 2803722 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1414 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS AHB configuration register (OTG_HS_GAHBCFG)", 1414 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1414/1757\nRM0090 Rev 21\nOTG_HS AHB configuration register (OTG_HS_GAHBCFG)\nAddress offset: 0x008\nReset value: 0x0000 0000\nThis register can be used to configure the core after power-on or a change in mode. This \nregister mainly contains AHB system-related configuration parameters. Do not change this \nregister after the initial programming. The application must program this register before \nstarting any transactions on either the AHB or the USB.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPTXFELVL\nTXFELVL\nReserved\nDMAEN\nHBSTLEN\nGINT\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:20 Reserved, must be kept at reset value.\nBit 8 PTXFELVL: Periodic TxFIFO empty level\nIndicates when the periodic TxFIFO empty interrupt bit in the Core interrupt register (PTXFE \nbit in OTG_HS_GINTSTS) is triggered.\n0: PTXFE (in OTG_HS_GINTSTS) interrupt indicates that the Periodic TxFIFO is half empty\n1: PTXFE (in OTG_HS_GINTSTS) interrupt indicates that the Periodic TxFIFO is completely \nempty\nNote: Only accessible in host mode.\nBit 7 TXFELVL: TxFIFO empty level\nIn peripheral mode, this bit indicates when the IN endpoint Transmit FIFO empty interrupt \n(TXFE in OTG_HS_DIEPINTx.) is triggered.\n0: TXFE (in OTG_HS_DIEPINTx) interrupt indicates that the IN Endpoint TxFIFO is half \nempty\n1: TXFE (in OTG_HS_DIEPINTx) interrupt indicates that the IN Endpoint TxFIFO is \ncompletely empty\nNote: Only accessible in peripheral mode.\nBit 6 Reserved, must be kept at reset value.\nBits5 DMAEN: DMA enable\n0: The core operates in slave mode\n1: The core operates in DMA mode\nBits 4:1 HBSTLEN: Burst length/type\n0000 Single\n0001 INCR\n0011 INCR4\n0101 INCR8\n0111 INCR16\nOthers: Reserved \nBit 0 GINT: Global interrupt mask\nThis bit is used to mask or unmask the interrupt line assertion to the application. Irrespective \nof this bit setting, the interrupt status registers are updated by the core.\n0: Mask the interrupt assertion to the application.\n1: Unmask the interrupt assertion to the application\nNote: Accessible in both peripheral and host modes.\n" }, { "page_number": 1415, "page_indices": { "start_index": 2803722, "end_index": 2806246 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1415 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS USB configuration register (OTG_HS_GUSBCFG)", 1415 ] ], "page_content": "RM0090 Rev 21\n1415/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS USB configuration register (OTG_HS_GUSBCFG)\nAddress offset: 0x00C\nReset value: 0x0000 1440\nThis register can be used to configure the core after power-on or a changing to host mode \nor peripheral mode. It contains USB and USB-PHY related configuration parameters. The \napplication must program this register before starting any transactions on either the AHB or \nthe USB. Do not make changes to this register after the initial programming.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCTXPKT\nFDMOD\nFHMOD\nReserved\nULPIIPD\nPTCI\nPCCI\nTSDPS\nULPIEVBUSI\nULPIEVBUSD\nULPICSM\nULPIAR\nULPIFSLS\nReserved\nPHYLPCS\nReserved\nTRDT\nHNPCAP\nSRPCAP\nReserved\nPHYSEL\nReserved\nTOCAL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 CTXPKT: Corrupt Tx packet\nThis bit is for debug purposes only. Never set this bit to 1.\nNote: Accessible in both peripheral and host modes.\nBit 30 FDMOD: Forced peripheral mode\nWriting a 1 to this bit forces the core to peripheral mode irrespective of the OTG_HS_ID input \npin.\n0: Normal mode\n1: Forced peripheral mode\nAfter setting the force bit, the application must wait at least 25 ms before the change takes \neffect.\nNote: Accessible in both peripheral and host modes.\nBit 29 FHMOD: Forced host mode\nWriting a 1 to this bit forces the core to host mode irrespective of the OTG_HS_ID input pin.\n0: Normal mode\n1: Forced host mode\nAfter setting the force bit, the application must wait at least 25 ms before the change takes \neffect.\nNote: Accessible in both peripheral and host modes.\nBits 28:26 Reserved, must be kept at reset value.\nBit 25 ULPIIPD: ULPI interface protect disable\nThis bit controls the circuitry built in the PHY to protect the ULPI interface when the link tri-\nstates stp and data. Any pull-up or pull-down resistors employed by this feature can be \ndisabled. Please refer to the ULPI specification for more details.\n0: Enables the interface protection circuit\n1: Disables the interface protection circuit \nBit 24 PTCI: Indicator pass through\nThis bit controls whether the complement output is qualified with the internal VBUS valid \ncomparator before being used in the VBUS state in the RX CMD. Please refer to the ULPI \nspecification for more details.\n0: Complement Output signal is qualified with the Internal VBUS valid comparator\n1: Complement Output signal is not qualified with the Internal VBUS valid comparator\n" }, { "page_number": 1416, "page_indices": { "start_index": 2806246, "end_index": 2808945 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1416 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS USB configuration register (OTG_HS_GUSBCFG)", 1415 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1416/1757\nRM0090 Rev 21\nBit 23 PCCI: Indicator complement\nThis bit controls the PHY to invert the ExternalVbusIndicator input signal, and generate the \ncomplement output. Please refer to the ULPI specification for more details.\n0: PHY does not invert the ExternalVbusIndicator signal\n1: PHY inverts ExternalVbusIndicator signal\nBit 22 TSDPS: TermSel DLine pulsing selection\nThis bit selects utmi_termselect to drive the data line pulse during SRP (session request \nprotocol).\n0: Data line pulsing using utmi_txvalid (default)\n1: Data line pulsing using utmi_termsel\nBit 21 ULPIEVBUSI: ULPI external VBUS indicator\nThis bit indicates to the ULPI PHY to use an external VBUS overcurrent indicator.\n0: PHY uses an internal VBUS valid comparator\n1: PHY uses an external VBUS valid comparator\nBit 20 ULPIEVBUSD: ULPI External VBUS Drive\nThis bit selects between internal or external supply to drive 5 V on VBUS, in the ULPI PHY.\n0: PHY drives VBUS using internal charge pump (default)\n1: PHY drives VBUS using external supply.\nBit 19 ULPICSM: ULPI Clock SuspendM\nThis bit sets the ClockSuspendM bit in the interface control register on the ULPI PHY. This bit \napplies only in the serial and carkit modes.\n0: PHY powers down the internal clock during suspend\n1: PHY does not power down the internal clock\nBit 18 ULPIAR: ULPI Auto-resume\nThis bit sets the AutoResume bit in the interface control register on the ULPI PHY.\n0: PHY does not use AutoResume feature\n1: PHY uses AutoResume feature\nBit 17 ULPIFSLS: ULPI FS/LS select\nThe application uses this bit to select the FS/LS serial interface for the ULPI PHY. This bit is \nvalid only when the FS serial transceiver is selected on the ULPI PHY. \n0: ULPI interface\n1: ULPI FS/LS serial interface\nBit 16\nReserved, must be kept at reset value.\nBit 15 PHYLPCS: PHY Low-power clock select\nThis bit selects either 480 MHz or 48 MHz (low-power) PHY mode. In FS and LS modes, the \nPHY can usually operate on a 48 MHz clock to save power.\n0: 480 MHz internal PLL clock\n1: 48 MHz external clock\nIn 480 MHz mode, the UTMI interface operates at either 60 or 30 MHz, depending on \nwhether the 8- or 16-bit data width is selected. In 48 MHz mode, the UTMI interface operates \nat 48 MHz in FS and LS modes.\nBit 14 Reserved, must be kept at reset value.\nBits 13:10 TRDT: USB turnaround time\nThese bits allows to set the turnaround time in PHY clocks. They must be configured \naccording to Table 214: TRDT values, depending on the application AHB frequency. Higher \nTRDT values allow stretching the USB response time to IN tokens in order to compensate for \nlonger AHB read access latency to the Data FIFO. \n" }, { "page_number": 1417, "page_indices": { "start_index": 2808945, "end_index": 2810591 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1417 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS USB configuration register (OTG_HS_GUSBCFG)", 1415 ] ], "page_content": "RM0090 Rev 21\n1417/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n \n \nBit 9 HNPCAP: HNP-capable\nThe application uses this bit to control the OTG_HS controller’s HNP capabilities.\n0: HNP capability is not enabled\n1: HNP capability is enabled\nNote: Accessible in both peripheral and host modes.\nBit 8 SRPCAP: SRP-capable\nThe application uses this bit to control the OTG_HS controller’s SRP capabilities. If the core \noperates as a nonSRP-capable B-device, it cannot request the connected A-device (host) to \nactivate VBUS and start a session.\n0: SRP capability is not enabled\n1: SRP capability is enabled\nNote: Accessible in both peripheral and host modes.\nBit 7 Reserved, must be kept at reset value.\nBit 6 PHYSEL: USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select\n0: USB 2.0 high-speed ULPI PHY\n1: USB 1.1 full-speed serial transceiver \nBits 5:3\nReserved, must be kept at reset value.\nBits 2:0 TOCAL: FS timeout calibration\nThe number of PHY clocks that the application programs in this field is added to the full-\nspeed interpacket timeout duration in the core to account for any additional delays \nintroduced by the PHY. This can be required, because the delay introduced by the PHY in \ngenerating the line state condition can vary from one PHY to another.\nThe USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The \napplication must program this field based on the speed of enumeration. The number of bit \ntimes added per PHY clock is 0.25 bit times.\nTable 214. TRDT values\nAHB frequency range (MHz)\nTRDT minimum value\nMin.\nMax\n30\n-\n0x9\n" }, { "page_number": 1418, "page_indices": { "start_index": 2810591, "end_index": 2812464 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1418 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS reset register (OTG_HS_GRSTCTL)", 1418 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1418/1757\nRM0090 Rev 21\nOTG_HS reset register (OTG_HS_GRSTCTL)\nAddress offset: 0x010\nReset value: 0x8000 0000\nThe application uses this register to reset various hardware features inside the core.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nAHBIDL\nDMAREQ\nReserved\nTXFNUM\nTXFFLSH\nRXFFLSH\nReserved\nFCRST\nHSRST\nCSRST\nr\nr\nrw\nrs\nrs\nrs\nrs\nrs\nBit 31 AHBIDL: AHB master idle\nIndicates that the AHB master state machine is in the Idle condition.\nNote: Accessible in both peripheral and host modes.\nBit 30 DMAREQ: DMA request signal\nThis bit indicates that the DMA request is in progress. Used for debug.\nBits 29:11\nReserved, must be kept at reset value.\nBits 10:6 TXFNUM: TxFIFO number\nThis is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not \nbe changed until the core clears the TxFIFO Flush bit.\n00000:\n– Nonperiodic TxFIFO flush in host mode\n– Tx FIFO 0 flush in peripheral mode\n00001:\n– Periodic TxFIFO flush in host mode\n– TXFIFO 1 flush in peripheral mode \n00010: TXFIFO 2 flush in peripheral mode \n...\n00101: TXFIFO 15 flush in peripheral mode \n10000: Flush all the transmit FIFOs in peripheral or host mode.\nNote: Accessible in both peripheral and host modes.\nBit 5 TXFFLSH: TxFIFO flush\nThis bit selectively flushes a single or all transmit FIFOs, but cannot do so if the core is in the \nmidst of a transaction.\nThe application must write this bit only after checking that the core is neither writing to the \nTxFIFO nor reading from the TxFIFO. Verify using these registers:\n–\nRead: the NAK effective interrupt ensures the core is not reading from the FIFO\n–\nWrite: the AHBIDL bit in OTG_HS_GRSTCTL ensures that the core is not writing \nanything to the FIFO\nNote: Accessible in both peripheral and host modes.\n" }, { "page_number": 1419, "page_indices": { "start_index": 2812464, "end_index": 2813117 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1419 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS reset register (OTG_HS_GRSTCTL)", 1418 ] ], "page_content": "RM0090 Rev 21\n1419/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBit 4 RXFFLSH: RxFIFO flush\nThe application can flush the entire RxFIFO using this bit, but must first ensure that the core \nis not in the middle of a transaction.\nThe application must only write to this bit after checking that the core is neither reading from \nthe RxFIFO nor writing to the RxFIFO.\nThe application must wait until the bit is cleared before performing any other operation. This \nbit requires 8 clocks (slowest of PHY or AHB clock) to be cleared.\nNote: Accessible in both peripheral and host modes.\nBit 3\nReserved, must be kept at reset value.\n" }, { "page_number": 1420, "page_indices": { "start_index": 2813117, "end_index": 2816003 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1420 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS reset register (OTG_HS_GRSTCTL)", 1418 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1420/1757\nRM0090 Rev 21\nBit 2 FCRST: Host frame counter reset\nThe application writes this bit to reset the (micro) frame number counter inside the core. \nWhen the (micro) frame counter is reset, the subsequent SOF sent out by the core has a \nframe number of 0.\nNote: Only accessible in host mode.\nBit 1 HSRST: HCLK soft reset\nThe application uses this bit to flush the control logic in the AHB Clock domain. Only AHB \nClock Domain pipelines are reset.\nFIFOs are not flushed with this bit.\nAll state machines in the AHB clock domain are reset to the Idle state after terminating the \ntransactions on the AHB, following the protocol.\nCSR control bits used by the AHB clock domain state machines are cleared.\nTo clear this interrupt, status mask bits that control the interrupt status and are generated by \nthe AHB clock domain state machine are cleared.\nBecause interrupt status bits are not cleared, the application can get the status of any core \nevents that occurred after it set this bit.\nThis is a self-clearing bit that the core clears after all necessary logic is reset in the core. This \ncan take several clocks, depending on the core’s current state.\nNote: Accessible in both peripheral and host modes.\nBit 0 CSRST: Core soft reset\nResets the HCLK and PCLK domains as follows:\nClears the interrupts and all the CSR register bits except for the following bits:\n– RSTPDMODL bit in OTG_HS_PCGCCTL\n– GAYEHCLK bit in OTG_HS_PCGCCTL\n– PWRCLMP bit in OTG_HS_PCGCCTL\n– STPPCLK bit in OTG_HS_PCGCCTL\n– FSLSPCS bit in OTG_HS_HCFG\n– DSPD bit in OTG_HS_DCFG\nAll module state machines (except for the AHB slave unit) are reset to the Idle state, and all \nthe transmit FIFOs and the receive FIFO are flushed.\nAny transactions on the AHB Master are terminated as soon as possible, after completing the \nlast data phase of an AHB transfer. Any transactions on the USB are terminated immediately.\nThe application can write to this bit any time it wants to reset the core. This is a self-clearing bit \nand the core clears this bit after all the necessary logic is reset in the core, which can take \nseveral clocks, depending on the current state of the core. Once this bit has been cleared, the \nsoftware must wait at least 3 PHY clocks before accessing the PHY domain (synchronization \ndelay). The software must also check that bit 31 in this register is set to 1 (AHB Master is Idle) \nbefore starting any operation.\nTypically, the software reset is used during software development and also when you \ndynamically change the PHY selection bits in the above listed USB configuration registers. \nWhen you change the PHY, the corresponding clock for the PHY is selected and used in the \nPHY domain. Once a new clock is selected, the PHY domain has to be reset for proper \noperation.\nNote: Accessible in both peripheral and host modes.\n" }, { "page_number": 1421, "page_indices": { "start_index": 2816003, "end_index": 2818629 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1421 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS core interrupt register (OTG_HS_GINTSTS)", 1421 ] ], "page_content": "RM0090 Rev 21\n1421/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS core interrupt register (OTG_HS_GINTSTS)\nAddress offset: 0x014\nReset value: 0x0400 0020\nThis register interrupts the application for system-level events in the current mode \n(peripheral mode or host mode).\nSome of the bits in this register are valid only in host mode, while others are valid in \nperipheral mode only. This register also indicates the current mode. To clear the interrupt \nstatus bits of the rc_w1 type, the application must write 1 into the bit.\nThe FIFO status interrupts are read-only; once software reads from or writes to the FIFO \nwhile servicing these interrupts, FIFO interrupt conditions are cleared automatically.\nThe application must clear the OTG_HS_GINTSTS register at initialization before \nunmasking the interrupt bit to avoid any interrupts generated prior to initialization.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nWKUINT\nSRQINT\nDISCINT\nCIDSCHG\nReserved\nPTXFE\nHCINT\nHPRTINT\nReserved\nDATAFSUSP\nIPXFR/INCOMPISOOUT\nIISOIXFR\nOEPINT\nIEPINT\nReserved\nEOPF\nISOODRP\nENUMDNE\nUSBRST\nUSBSUSP\nESUSP\nReserved\nGONAKEFF\nGINAKEFF\nNPTXFE\nRXFLVL\nSOF\nOTGINT\nMMIS\nCMOD\nrc_w1\nr\nr\nr\nrc_w1\nr\nr\nrc_w1\nr\nr\nr\nr\nrc_w1\nr\nrc_w1\nr\nBit 31 WKUPINT: Resume/remote wake-up detected interrupt\nIn peripheral mode, this interrupt is asserted when a resume is detected on the USB. In host \nmode, this interrupt is asserted when a remote wake-up is detected on the USB.\nNote: Accessible in both peripheral and host modes.\nBit 30 SRQINT: Session request/new session detected interrupt\nIn host mode, this interrupt is asserted when a session request is detected from the device. \nIn peripheral mode, this interrupt is asserted when VBUS is in the valid range for a B-device \ndevice. Accessible in both peripheral and host modes.\nBit 29 DISCINT: Disconnect detected interrupt\nAsserted when a device disconnect is detected.\nNote: Only accessible in host mode.\nBit 28 CIDSCHG: Connector ID status change\nThe core sets this bit when there is a change in connector ID status.\nNote: Accessible in both peripheral and host modes.\nBit 27 Reserved, must be kept at reset value.\nBit 26 PTXFE: Periodic TxFIFO empty\nAsserted when the periodic transmit FIFO is either half or completely empty and there is \nspace for at least one entry to be written in the periodic request queue. The half or \ncompletely empty status is determined by the periodic TxFIFO empty level bit in the Core \nAHB configuration register (PTXFELVL bit in OTG_HS_GAHBCFG).\nNote: Only accessible in host mode.\n" }, { "page_number": 1422, "page_indices": { "start_index": 2818629, "end_index": 2821918 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1422 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS core interrupt register (OTG_HS_GINTSTS)", 1421 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1422/1757\nRM0090 Rev 21\nBit 25 HCINT: Host channels interrupt\nThe core sets this bit to indicate that an interrupt is pending on one of the channels of the \ncore (in host mode). The application must read the host all channels interrupt \n(OTG_HS_HAINT) register to determine the exact number of the channel on which the \ninterrupt occurred, and then read the corresponding host channel-x interrupt \n(OTG_HS_HCINTx) register to determine the exact cause of the interrupt. The application \nmust clear the appropriate status bit in the OTG_HS_HCINTx register to clear this bit.\nNote: Only accessible in host mode.\nBit 24 HPRTINT: Host port interrupt\nThe core sets this bit to indicate a change in port status of one of the OTG_HS controller \nports in host mode. The application must read the host port control and status \n(OTG_HS_HPRT) register to determine the exact event that caused this interrupt. The \napplication must clear the appropriate status bit in the host port control and status register to \nclear this bit.\nNote: Only accessible in host mode.\nBits 23 Reserved, must be kept at reset value.\nBit 22 DATAFSUSP: Data fetch suspended\nThis interrupt is valid only in DMA mode. This interrupt indicates that the core has stopped \nfetching data for IN endpoints due to the unavailability of TxFIFO space or request queue \nspace. This interrupt is used by the application for an endpoint mismatch algorithm. For \nexample, after detecting an endpoint mismatch, the application:\n–\nSets a global nonperiodic IN NAK handshake\n–\nDisables IN endpoints \n–\nFlushes the FIFO\n–\nDetermines the token sequence from the IN token sequence learning queue\n–\nRe-enables the endpoints\n–\nClears the global nonperiodic IN NAK handshake If the global nonperiodic IN NAK \nis cleared, the core has not yet fetched data for the IN endpoint, and the IN token is \nreceived: the core generates an “IN token received when FIFO empty” interrupt. \nThe OTG then sends a NAK response to the host. To avoid this scenario, the \napplication can check the FetSusp interrupt in OTG_HS_GINTSTS, which ensures \nthat the FIFO is full before clearing a global NAK handshake. Alternatively, the \napplication can mask the “IN token received when FIFO empty” interrupt when \nclearing a global IN NAK handshake.\nBit 21 IPXFR: Incomplete periodic transfer\nIn host mode, the core sets this interrupt bit when there are incomplete periodic transactions \nstill pending, which are scheduled for the current frame.\nNote: Only accessible in host mode.\nINCOMPISOOUT: Incomplete isochronous OUT transfer\nIn peripheral mode, the core sets this interrupt to indicate that there is at least one \nisochronous OUT endpoint on which the transfer is not completed in the current frame. This \ninterrupt is asserted along with the End of periodic frame interrupt (EOPF) bit in this register.\nNote: Only accessible in peripheral mode.\nBit 20 IISOIXFR: Incomplete isochronous IN transfer\nThe core sets this interrupt to indicate that there is at least one isochronous IN endpoint on \nwhich the transfer is not completed in the current frame. This interrupt is asserted along with \nthe End of periodic frame interrupt (EOPF) bit in this register.\nNote: Only accessible in peripheral mode.\n" }, { "page_number": 1423, "page_indices": { "start_index": 2821918, "end_index": 2824745 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1423 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS core interrupt register (OTG_HS_GINTSTS)", 1421 ] ], "page_content": "RM0090 Rev 21\n1423/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBit 19 OEPINT: OUT endpoint interrupt\nThe core sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of \nthe core (in peripheral mode). The application must read the device all endpoints interrupt \n(OTG_HS_DAINT) register to determine the exact number of the OUT endpoint on which \nthe interrupt occurred, and then read the corresponding device OUT Endpoint-x Interrupt \n(OTG_HS_DOEPINTx) register to determine the exact cause of the interrupt. The \napplication must clear the appropriate status bit in the corresponding OTG_HS_DOEPINTx \nregister to clear this bit.\nNote: Only accessible in peripheral mode.\nBit 18 IEPINT: IN endpoint interrupt\nThe core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the \ncore (in peripheral mode). The application must read the device All Endpoints Interrupt \n(OTG_HS_DAINT) register to determine the exact number of the IN endpoint on which the \ninterrupt occurred, and then read the corresponding device IN Endpoint-x interrupt \n(OTG_HS_DIEPINTx) register to determine the exact cause of the interrupt. The application \nmust clear the appropriate status bit in the corresponding OTG_HS_DIEPINTx register to \nclear this bit.\nNote: Only accessible in peripheral mode.\nBits 17:16 Reserved, must be kept at reset value.\nBit 15 EOPF: End of periodic frame interrupt\nIndicates that the period specified in the periodic frame interval field of the device \nconfiguration register (PFIVL bit in OTG_HS_DCFG) has been reached in the current frame.\nNote: Only accessible in peripheral mode.\nBit 14 ISOODRP: Isochronous OUT packet dropped interrupt\nThe core sets this bit when it fails to write an isochronous OUT packet into the RxFIFO \nbecause the RxFIFO does not have enough space to accommodate a maximum size packet \nfor the isochronous OUT endpoint.\nNote: Only accessible in peripheral mode.\nBit 13 ENUMDNE: Enumeration done\nThe core sets this bit to indicate that speed enumeration is complete. The application must \nread the device Status (OTG_HS_DSTS) register to obtain the enumerated speed.\nNote: Only accessible in peripheral mode.\nBit 12 USBRST: USB reset\nThe core sets this bit to indicate that a reset is detected on the USB.\nNote: Only accessible in peripheral mode.\nBit 11 USBSUSP: USB suspend\nThe core sets this bit to indicate that a suspend was detected on the USB. The core enters \nthe Suspended state when there is no activity on the data lines for a period of 3 ms.\nNote: Only accessible in peripheral mode.\nBit 10 ESUSP: Early suspend\nThe core sets this bit to indicate that an Idle state has been detected on the USB for 3 ms.\nNote: Only accessible in peripheral mode.\nBits 9:8\nReserved, must be kept at reset value.\n" }, { "page_number": 1424, "page_indices": { "start_index": 2824745, "end_index": 2827883 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1424 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS core interrupt register (OTG_HS_GINTSTS)", 1421 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1424/1757\nRM0090 Rev 21\nBit 7 GONAKEFF: Global OUT NAK effective\nIndicates that the Set global OUT NAK bit in the Device control register (SGONAK bit in \nOTG_HS_DCTL), set by the application, has taken effect in the core. This bit can be cleared \nby writing the Clear global OUT NAK bit in the Device control register (CGONAK bit in \nOTG_HS_DCTL).\nNote: Only accessible in peripheral mode.\nBit 6 GINAKEFF: Global IN nonperiodic NAK effective\nIndicates that the Set global nonperiodic IN NAK bit in the Device control register (SGINAK \nbit in OTG_HS_DCTL), set by the application, has taken effect in the core. That is, the core \nhas sampled the Global IN NAK bit set by the application. This bit can be cleared by clearing \nthe Clear global nonperiodic IN NAK bit in the Device control register (CGINAK bit in \nOTG_HS_DCTL).\nThis interrupt does not necessarily mean that a NAK handshake is sent out on the USB. The \nSTALL bit takes precedence over the NAK bit.\nNote: Only accessible in peripheral mode.\nBit 5 NPTXFE: Nonperiodic TxFIFO empty\nThis interrupt is asserted when the nonperiodic TxFIFO is either half or completely empty, \nand there is space in at least one entry to be written to the nonperiodic transmit request \nqueue. The half or completely empty status is determined by the nonperiodic TxFIFO empty \nlevel bit in the OTG_HS_GAHBCFG register (TXFELVL bit in OTG_HS_GAHBCFG). \nNote: Only accessible in host mode.\nBit 4 RXFLVL: RxFIFO nonempty\nIndicates that there is at least one packet pending to be read from the RxFIFO.\nNote: Accessible in both host and peripheral modes.\nBit 3 SOF: Start of frame\nIn host mode, the core sets this bit to indicate that an SOF (FS), or Keep-Alive (LS) is \ntransmitted on the USB. The application must write a 1 to this bit to clear the interrupt.\nIn peripheral mode, in the core sets this bit to indicate that an SOF token has been received \non the USB. The application can read the Device Status register to get the current frame \nnumber. This interrupt is seen only when the core is operating in FS.\nNote: Accessible in both host and peripheral modes.\nBit 2 OTGINT: OTG interrupt\nThe core sets this bit to indicate an OTG protocol event. The application must read the OTG \nInterrupt Status (OTG_HS_GOTGINT) register to determine the exact event that caused this \ninterrupt. The application must clear the appropriate status bit in the OTG_HS_GOTGINT \nregister to clear this bit.\nNote: Accessible in both host and peripheral modes.\nBit 1 MMIS: Mode mismatch interrupt\nThe core sets this bit when the application is trying to access:\nA host mode register, when the core is operating in peripheral mode\nA peripheral mode register, when the core is operating in host mode\nThe register access is completed on the AHB with an OKAY response, but is ignored by the \ncore internally and does not affect the operation of the core.\nNote: Accessible in both host and peripheral modes.\nBit 0 CMOD: Current mode of operation\nIndicates the current mode.\n0: Peripheral mode\n1: Host mode\nNote: Accessible in both host and peripheral modes.\n" }, { "page_number": 1425, "page_indices": { "start_index": 2827883, "end_index": 2829821 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1425 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS interrupt mask register (OTG_HS_GINTMSK)", 1425 ] ], "page_content": "RM0090 Rev 21\n1425/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS interrupt mask register (OTG_HS_GINTMSK)\nAddress offset: 0x018\nReset value: 0x0000 0000\nThis register works with the Core interrupt register to interrupt the application. When an \ninterrupt bit is masked, the interrupt associated with that bit is not generated. However, the \nCore Interrupt (OTG_HS_GINTSTS) register bit corresponding to that interrupt is still set.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nWUIM\nSRQIM\nDISCINT\nCIDSCHGM\nReserved\nPTXFEM\nHCIM\nPRTIM\nReserved\nFSUSPM\nIPXFRM/IISOOXFRM\nIISOIXFRM\nOEPINT\nIEPINT\nReserved\nEOPFM\nISOODRPM\nENUMDNEM\nUSBRST\nUSBSUSPM\nESUSPM\nReserved\nGONAKEFFM\nGINAKEFFM\nNPTXFEM\nRXFLVLM\nSOFM\nOTGINT\nMMISM\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 WUIM: Resume/remote wake-up detected interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both host and peripheral modes.\nBit 30 SRQIM: Session request/new session detected interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both host and peripheral modes.\nBit 29 DISCINT: Disconnect detected interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both host and peripheral modes.\nBit 28 CIDSCHGM: Connector ID status change mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both host and peripheral modes.\nBit 27 Reserved, must be kept at reset value.\nBit 26 PTXFEM: Periodic TxFIFO empty mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in host mode.\nBit 25 HCIM: Host channels interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in host mode.\nBit 24 PRTIM: Host port interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in host mode.\nBit 23 Reserved, must be kept at reset value.\n" }, { "page_number": 1426, "page_indices": { "start_index": 2829821, "end_index": 2831381 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1426 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS interrupt mask register (OTG_HS_GINTMSK)", 1425 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1426/1757\nRM0090 Rev 21\nBit 22 FSUSPM: Data fetch suspended mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 21 IPXFRM: Incomplete periodic transfer mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in host mode.\nIISOOXFRM: Incomplete isochronous OUT transfer mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 20 IISOIXFRM: Incomplete isochronous IN transfer mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 19 OEPINT: OUT endpoints interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 18 IEPINT: IN endpoints interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBits 17:16 Reserved, must be kept at reset value.\nBit 15 EOPFM: End of periodic frame interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 14 ISOODRPM: Isochronous OUT packet dropped interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 13 ENUMDNEM: Enumeration done mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 12 USBRST: USB reset mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 11 USBSUSPM: USB suspend mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\n" }, { "page_number": 1427, "page_indices": { "start_index": 2831381, "end_index": 2832622 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1427 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS interrupt mask register (OTG_HS_GINTMSK)", 1425 ] ], "page_content": "RM0090 Rev 21\n1427/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBit 10 ESUSPM: Early suspend mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBits 9:8 Reserved, must be kept at reset value.\nBit 7 GONAKEFFM: Global OUT NAK effective mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 6 GINAKEFFM: Global nonperiodic IN NAK effective mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Only accessible in peripheral mode.\nBit 5 NPTXFEM: Nonperiodic TxFIFO empty mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both peripheral and host modes.\nBit 4 RXFLVLM: Receive FIFO nonempty mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both peripheral and host modes.\nBit 3 SOFM: Start of frame mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both peripheral and host modes.\nBit 2 OTGINT: OTG interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both peripheral and host modes.\nBit 1 MMISM: Mode mismatch interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nNote: Accessible in both peripheral and host modes.\nBit 0 Reserved, must be kept at reset value.\n" }, { "page_number": 1428, "page_indices": { "start_index": 2832622, "end_index": 2834255 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1428 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS Receive status debug read/OTG status read and pop registers (OTG_HS_GRXSTSR/OTG_HS_GRXSTSP)", 1428 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1428/1757\nRM0090 Rev 21\nOTG_HS Receive status debug read/OTG status read and pop registers \n(OTG_HS_GRXSTSR/OTG_HS_GRXSTSP)\nAddress offset for Read: 0x01C\nAddress offset for Pop: 0x020\nReset value: 0x0000 0000\nA read to the Receive status debug read register returns the contents of the top of the \nReceive FIFO. A read to the Receive status read and pop register additionally pops the top \ndata entry out of the RxFIFO.\nThe receive status contents must be interpreted differently in host and peripheral modes. \nThe core ignores the receive status pop/read when the receive FIFO is empty and returns a \nvalue of 0x0000 0000. The application must only pop the Receive Status FIFO when the \nReceive FIFO nonempty bit of the Core interrupt register (RXFLVL bit in \nOTG_HS_GINTSTS) is asserted.\nHost mode:\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPKTSTS\nDPID\nBCNT\nCHNUM\nr\nr\nr\nr\nBits 31:21 Reserved, must be kept at reset value.\nBits 20:17 PKTSTS: Packet status\nIndicates the status of the received packet\n0010: IN data packet received\n0011: IN transfer completed (triggers an interrupt)\n0101: Data toggle error (triggers an interrupt)\n0111: Channel halted (triggers an interrupt)\nOthers: Reserved\nBits 16:15 DPID: Data PID\nIndicates the Data PID of the received packet\n00: DATA0\n10: DATA1\n01: DATA2\n11: MDATA\nBits 14:4 BCNT: Byte count\nIndicates the byte count of the received IN data packet.\nBits 3:0 CHNUM: Channel number\nIndicates the channel number to which the current received packet belongs.\n" }, { "page_number": 1429, "page_indices": { "start_index": 2834255, "end_index": 2835954 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1429 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS Receive FIFO size register (OTG_HS_GRXFSIZ)", 1429 ] ], "page_content": "RM0090 Rev 21\n1429/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nPeripheral mode:\n \n \nOTG_HS Receive FIFO size register (OTG_HS_GRXFSIZ)\nAddress offset: 0x024\nReset value: 0x0000 0400\nThe application can program the RAM size that must be allocated to the RxFIFO.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFRMNUM\nPKTSTS\nDPID\nBCNT\nEPNUM\nr\nr\nr\nr\nr\nBits 31:25 Reserved, must be kept at reset value.\nBits 24:21 FRMNUM: Frame number\nThis is the least significant 4 bits of the frame number in which the packet is received on the \nUSB. This field is supported only when isochronous OUT endpoints are supported.\nBits 20:17 PKTSTS: Packet status\nIndicates the status of the received packet\n0001: Global OUT NAK (triggers an interrupt)\n0010: OUT data packet received\n0011: OUT transfer completed (triggers an interrupt)\n0100: SETUP transaction completed (triggers an interrupt)\n0110: SETUP data packet received\nOthers: Reserved\nBits 16:15 DPID: Data PID\nIndicates the Data PID of the received OUT data packet\n00: DATA0\n10: DATA1\n01: DATA2\n11: MDATA\nBits 14:4 BCNT: Byte count\nIndicates the byte count of the received data packet.\nBits 3:0 EPNUM: Endpoint number\nIndicates the endpoint number to which the current received packet belongs.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRXFD\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 RXFD: RxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nMaximum value is 1024\nThe power-on reset value of this register is specified as the largest Rx data FIFO depth.\n" }, { "page_number": 1430, "page_indices": { "start_index": 2835954, "end_index": 2837442 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1430 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS nonperiodic transmit FIFO size/Endpoint 0 transmit FIFO size register (OTG_HS_GNPTXFSIZ/OTG_HS_TX0FSIZ)", 1430 ], [ 4, "OTG_HS nonperiodic transmit FIFO/queue status register (OTG_HS_GNPTXSTS)", 1430 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1430/1757\nRM0090 Rev 21\nOTG_HS nonperiodic transmit FIFO size/Endpoint 0 transmit FIFO size \nregister (OTG_HS_GNPTXFSIZ/OTG_HS_TX0FSIZ)\nAddress offset: 0x028\nReset value: 0x0000 0200\nHost mode:\n \nPeripheral mode:\n \n \nOTG_HS nonperiodic transmit FIFO/queue status register \n(OTG_HS_GNPTXSTS)\nAddress offset: 0x02C\nReset value: 0x0008 0400\nNote:\nIn peripheral mode, this register is not valid.\nThis read-only register contains the free space information for the nonperiodic TxFIFO and \nthe nonperiodic transmit request queue.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nNPTXFD\nNPTXFSA\nrw\nrw\nBits 31:16 NPTXFD: Nonperiodic TxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nMaximum value is 1024\nBits 15:0 NPTXFSA: Nonperiodic transmit RAM start address\nThis field contains the memory start address for nonperiodic transmit FIFO RAM.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nTX0FD\nTX0FSA\nr/rw\nr/rw\nBits 31:16 T0XFD: Endpoint 0 TxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nMaximum value is 256\nBits 15:0 TX0FSA: Endpoint 0 transmit RAM start address\nThis field contains the memory start address for Endpoint 0 transmit FIFO RAM.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNPTXQTOP\nNPTQXSAV\nNPTXFSAV\nr\nr\nr\n" }, { "page_number": 1431, "page_indices": { "start_index": 2837442, "end_index": 2839000 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1431 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS general core configuration register (OTG_HS_GCCFG)", 1431 ] ], "page_content": "RM0090 Rev 21\n1431/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n \nOTG_HS general core configuration register (OTG_HS_GCCFG)\nAddress offset: 0x038\nReset value: 0x0000 XXXX\n \nBit 31 Reserved, must be kept at reset value.\nBits 30:24 NPTXQTOP: Top of the nonperiodic transmit request queue\nEntry in the nonperiodic Tx request queue that is currently being processed by the MAC.\nBits [30:27]: Channel/endpoint number\nBits [26:25]:\n–\n00: IN/OUT token\n–\n01: Zero-length transmit packet (device IN/host OUT)\n–\n10: PING/CSPLIT token \n–\n11: Channel halt command\nBit [24]: Terminate (last entry for selected channel/endpoint)\nBits 23:16 NPTQXSAV: Nonperiodic transmit request queue space available\nIndicates the amount of free space available in the nonperiodic transmit request queue. \nThis queue holds both IN and OUT requests in host mode. Peripheral mode has only IN \nrequests.\n00: Nonperiodic transmit request queue is full\n01: dx1 location available\n10: dx2 locations available\nbxn: dxn locations available (0 ≤n ≤dx8)\nOthers: Reserved\nBits 15:0 NPTXFSAV: Nonperiodic TxFIFO space available\nIndicates the amount of free space available in the nonperiodic TxFIFO.\nValues are in terms of 32-bit words.\n00: Nonperiodic TxFIFO is full\n01: dx1 word available\n10: dx2 words available\n0xn: dxn words available (where 0 ≤n ≤dx1024)\nOthers: Reserved\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNOVBUSSENS\nSOFOUTEN\nVBUSBSEN\nVBUSASEN\nI2CPADEN\n.PWRDWN\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1432, "page_indices": { "start_index": 2839000, "end_index": 2840868 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1432 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS core ID register (OTG_HS_CID)", 1432 ], [ 4, "OTG_HS Host periodic transmit FIFO size register (OTG_HS_HPTXFSIZ)", 1432 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1432/1757\nRM0090 Rev 21\n \nOTG_HS core ID register (OTG_HS_CID)\nAddress offset: 0x03C\nReset value:0x0000 1100\nThis is a register containing the Product ID as reset value.\n \n \nOTG_HS Host periodic transmit FIFO size register (OTG_HS_HPTXFSIZ)\nAddress offset: 0x100\nReset value: 0x0200 0800\nBits 31:22 Reserved, must be kept at reset value.\nBit 21 NOVBUSSENS: VBUS sensing disable option\nWhen this bit is set, VBUS is considered internally to be always at VBUS valid level (5 V). This \noption removes the need for a dedicated VBUS pad, and leave this pad free to be used for \nother purposes such as a shared functionality. VBUS connection can be remapped on \nanother general purpose input pad and monitored by software. \nThis option is only suitable for host-only or device-only applications. \n0: VBUS sensing available by hardware \n1: VBUS sensing not available by hardware. \nBit 20 SOFOUTEN: SOF output enable\n0: SOF pulse not available on PAD\n1: SOF pulse available on PAD\nBit 19 VBUSBSEN: Enable the VBUS sensing “B” device\n0: VBUS sensing “B” disabled\n1: VBUS sensing “B” enabled\nBit 18 VBUSASEN: Enable the VBUS sensing “A” device\n0: VBUS sensing “A” disabled\n1: VBUS sensing “A” enabled\nBit 17 I2CPADEN: Enable I2C bus connection for the external I2C PHY interface.\n0: I2C bus disabled\n1: I2C bus enabled\nBit 16 PWRDWN: Power down\nUsed to activate the transceiver in transmission/reception\n0: Power down active\n1: Power down deactivated (“Transceiver active”)\nBits 15:0 Reserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPRODUCT_ID\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 PRODUCT_ID: Product ID field\nApplication-programmable ID field.\n" }, { "page_number": 1433, "page_indices": { "start_index": 2840868, "end_index": 2842791 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1433 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.2 OTG_HS global registers", 1410 ], [ 4, "OTG_HS device IN endpoint transmit FIFO size register (OTG_HS_DIEPTXFx) (x = 1..5, where x is the FIFO_number)", 1433 ], [ 3, "35.12.3 Host-mode registers", 1433 ], [ 4, "OTG_HS host configuration register (OTG_HS_HCFG)", 1433 ] ], "page_content": "RM0090 Rev 21\n1433/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n \n \nOTG_HS device IN endpoint transmit FIFO size register (OTG_HS_DIEPTXFx) \n(x = 1..5, where x is the FIFO_number)\nAddress offset: 0x104 + 0x04 * (x - 1)\nReset value: 0x02000400\n \n \n35.12.3 \nHost-mode registers\nBit values in the register descriptions are expressed in binary unless otherwise specified.\nHost-mode registers affect the operation of the core in the host mode. Host mode registers \nmust not be accessed in peripheral mode, as the results are undefined. Host mode registers \ncan be categorized as follows:\nOTG_HS host configuration register (OTG_HS_HCFG)\nAddress offset: 0x400\nReset value: 0x0000 0000\nThis register configures the core after power-on. Do not change to this register after \ninitializing the host.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPTXFD\nPTXSA\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 PTXFD: Host periodic TxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nMaximum value is 512\nBits 15:0 PTXSA: Host periodic TxFIFO start address\nThe power-on reset value of this register is the sum of the largest Rx data FIFO depth and \nlargest nonperiodic Tx data FIFO depth.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nINEPTXFD\nINEPTXSA\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 INEPTXFD: IN endpoint TxFIFO depth\nThis value is in terms of 32-bit words.\nMinimum value is 16\nMaximum value is 512\nThe power-on reset value of this register is specified as the largest IN endpoint FIFO \nnumber depth.\nBits 15:0 INEPTXSA: IN endpoint FIFOx transmit RAM start address\nThis field contains the memory start address for IN endpoint transmit FIFOx. The address \nmust be aligned with a 32-bit memory location. \n" }, { "page_number": 1434, "page_indices": { "start_index": 2842791, "end_index": 2843932 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1434 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.3 Host-mode registers", 1433 ], [ 4, "OTG_HS host configuration register (OTG_HS_HCFG)", 1433 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1434/1757\nRM0090 Rev 21\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFSLSS\nFSLSPCS\nr\nrw\nrw\nBits 31:3 Reserved, must be kept at reset value.\nBit 2 FSLSS: FS- and LS-only support\nThe application uses this bit to control the core’s enumeration speed. Using this bit, the \napplication can make the core enumerate as an FS host, even if the connected device \nsupports HS traffic. Do not make changes to this field after initial programming.\n0: HS/FS/LS, based on the maximum speed supported by the connected device \n1: FS/LS-only, even if the connected device can support HS (read-only)\nBits 1:0 FSLSPCS: FS/LS PHY clock select\nWhen the core is in FS host mode:\n01: PHY clock is running at 48 MHz\nOthers: Reserved\nWhen the core is in LS host mode:\n00: Reserved\n01: PHY clock is running at 48 MHz.\n10: Select 6 MHz PHY clock frequency\n11: Reserved\nNote: The FSLSPCS bit must be set on a connection event according to the speed of the \nconnected device. A software reset must be performed after changing this bit.\n" }, { "page_number": 1435, "page_indices": { "start_index": 2843932, "end_index": 2846165 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1435 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.3 Host-mode registers", 1433 ], [ 4, "OTG_HS Host frame interval register (OTG_HS_HFIR)", 1435 ], [ 4, "OTG_HS host frame number/frame time remaining register (OTG_HS_HFNUM)", 1435 ] ], "page_content": "RM0090 Rev 21\n1435/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS Host frame interval register (OTG_HS_HFIR)\nAddress offset: 0x404\nReset value: 0x0000 EA60\nThis register stores the frame interval information for the current speed to which the \nOTG_HS controller has enumerated.\n \n \nOTG_HS host frame number/frame time remaining register \n(OTG_HS_HFNUM)\nAddress offset: 0x408\nReset value: 0x0000 3FFF\nThis register indicates the current frame number. It also indicates the time remaining (in \nterms of the number of PHY clocks) in the current frame.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFRIVL\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 FRIVL: Frame interval\nThe value that the application programs to this field specifies the interval between two \nconsecutive SOFs (FS), micro-SOFs (HS) or Keep-Alive tokens (LS). This field contains the \nnumber of PHY clocks that constitute the required frame interval. The application can write a \nvalue to this register only after the Port enable bit of the host port control and status register \n(PENA bit in OTG_HS_HPRT) has been set. If no value is programmed, the core calculates \nthe value based on the PHY clock specified in the FS/LS PHY Clock Select field of the Host \nconfiguration register (FSLSPCS in OTG_HS_HCFG):\nframe duration × PHY clock frequency\n– Frame interval = 1 ms × (FRIVL - 1)\nNote: The FRIVL bit can be modified whenever the application needs to change the Frame \ninterval time.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nFTREM\nFRNUM\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 FTREM: Frame time remaining\nIndicates the amount of time remaining in the current frame, in terms of PHY clocks. This \nfield decrements on each PHY clock. When it reaches zero, this field is reloaded with the \nvalue in the Frame interval register and a new SOF is transmitted on the USB.\nBits 15:0 FRNUM: Frame number\nThis field increments when a new SOF is transmitted on the USB, and is cleared to 0 when \nit reaches 0x3FFF.\n" }, { "page_number": 1436, "page_indices": { "start_index": 2846165, "end_index": 2847892 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1436 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.3 Host-mode registers", 1433 ], [ 4, "OTG_HS_Host periodic transmit FIFO/queue status register (OTG_HS_HPTXSTS)", 1436 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1436/1757\nRM0090 Rev 21\nOTG_HS_Host periodic transmit FIFO/queue status register \n(OTG_HS_HPTXSTS)\nAddress offset: 0x410\nReset value: 0x0008 0100\nThis read-only register contains the free space information for the periodic TxFIFO and the \nperiodic transmit request queue.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPTXQTOP\nPTXQSAV\nPTXFSAVL\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:24 PTXQTOP: Top of the periodic transmit request queue\nThis indicates the entry in the periodic Tx request queue that is currently being processed by \nthe MAC.\nThis register is used for debugging.\nBit [31]: Odd/Even frame\n–\n0: send in even (micro) frame\n–\n1: send in odd (micro) frame\nBits [30:27]: Channel/endpoint number\nBits [26:25]: Type\n–\n00: IN/OUT\n–\n01: Zero-length packet\n–\n11: Disable channel command\nBit [24]: Terminate (last entry for the selected channel/endpoint)\nBits 23:16 PTXQSAV: Periodic transmit request queue space available\nIndicates the number of free locations available to be written in the periodic transmit request \nqueue. This queue holds both IN and OUT requests.\n00: Periodic transmit request queue is full\n01: dx1 location available\n10: dx2 locations available\nbxn: dxn locations available (0 ≤dxn ≤PTXFD)\nOthers: Reserved\nBits 15:0 PTXFSAVL: Periodic transmit data FIFO space available\nIndicates the number of free locations available to be written to in the periodic TxFIFO.\nValues are in terms of 32-bit words\n0000: Periodic TxFIFO is full\n0001: dx1 word available\n0010: dx2 words available\nbxn: dxn words available (where 0 ≤dxn ≤dx512)\nOthers: Reserved\n" }, { "page_number": 1437, "page_indices": { "start_index": 2847892, "end_index": 2849564 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1437 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.3 Host-mode registers", 1433 ], [ 4, "OTG_HS Host all channels interrupt register (OTG_HS_HAINT)", 1437 ], [ 4, "OTG_HS host all channels interrupt mask register (OTG_HS_HAINTMSK)", 1437 ] ], "page_content": "RM0090 Rev 21\n1437/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS Host all channels interrupt register (OTG_HS_HAINT)\nAddress offset: 0x414\nReset value: 0x0000 000\nWhen a significant event occurs on a channel, the host all channels interrupt register \ninterrupts the application using the host channels interrupt bit of the Core interrupt register \n(HCINT bit in OTG_HS_GINTSTS). This is shown in Figure 414. There is one interrupt bit \nper channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the \napplication sets and clears bits in the corresponding host channel-x interrupt register.\n \n \nOTG_HS host all channels interrupt mask register (OTG_HS_HAINTMSK)\nAddress offset: 0x418\nReset value: 0x0000 0000\nThe host all channel interrupt mask register works with the host all channel interrupt register \nto interrupt the application when an event occurs on a channel. There is one interrupt mask \nbit per channel, up to a maximum of 16 bits.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nHAINT\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 HAINT: Channel interrupts\nOne bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nHAINTM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 HAINTM: Channel interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nOne bit per channel: Bit 0 for channel 0, bit 15 for channel 15\n" }, { "page_number": 1438, "page_indices": { "start_index": 2849564, "end_index": 2851554 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1438 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.3 Host-mode registers", 1433 ], [ 4, "OTG_HS host port control and status register (OTG_HS_HPRT)", 1438 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1438/1757\nRM0090 Rev 21\nOTG_HS host port control and status register (OTG_HS_HPRT)\nAddress offset: 0x440\nReset value: 0x0000 0000\nThis register is available only in host mode. Currently, the OTG host supports only one port.\nA single register holds USB port-related information such as USB reset, enable, suspend, \nresume, connect status, and test mode for each port. It is shown in Figure 414. The rc_w1 \nbits in this register can trigger an interrupt to the application through the host port interrupt \nbit of the core interrupt register (HPRTINT bit in OTG_HS_GINTSTS). On a Port Interrupt, \nthe application must read this register and clear the bit that caused the interrupt. For the \nrc_w1 bits, the application must write a 1 to the bit to clear the interrupt.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPSPD\nPTCTL\nPPWR\nPLSTS\nReserved\nPRST\nPSUSP\nPRES\nPOCCHNG\nPOCA\nPENCHNG\nPENA\nPCDET\nPCSTS\nr\nr\nrw\nrw\nrw\nrw\nrw\nr\nr\nrw\nrs\nrw\nrc_\nw1\nr\nrc_\nw1\nrc_\nw0\nrc_\nw1\nr\nBits 31:19 Reserved, must be kept at reset value.\nBits 18:17 PSPD: Port speed\nIndicates the speed of the device attached to this port.\n00: High speed\n01: Full speed\n10: Low speed\n11: Reserved\nBits 16:13 PTCTL: Port test control\nThe application writes a nonzero value to this field to put the port into a Test mode, and the \ncorresponding pattern is signaled on the port.\n0000: Test mode disabled\n0001: Test_J mode\n0010: Test_K mode\n0011: Test_SE0_NAK mode\n0100: Test_Packet mode\n0101: Test_Force_Enable\nOthers: Reserved\nBit 12 PPWR: Port power\nThe application uses this field to control power to this port, and the core clears this bit on an \novercurrent condition.\n0: Power off\n1: Power on\nBits 11:10 PLSTS: Port line status\nIndicates the current logic level USB data lines\nBit [10]: Logic level of OTG_HS_FS_DP\nBit [11]: Logic level of OTG_HS_FS_DM\nBit 9 Reserved, must be kept at reset value.\n" }, { "page_number": 1439, "page_indices": { "start_index": 2851554, "end_index": 2854005 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1439 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.3 Host-mode registers", 1433 ], [ 4, "OTG_HS host port control and status register (OTG_HS_HPRT)", 1438 ] ], "page_content": "RM0090 Rev 21\n1439/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBit 8 PRST: Port reset\nWhen the application sets this bit, a reset sequence is started on this port. The application \nmust time the reset period and clear this bit after the reset sequence is complete.\n0: Port not in reset\n1: Port in reset\nThe application must leave this bit set for a minimum duration of at least 10 ms to start a \nreset on the port. The application can leave it set for another 10 ms in addition to the \nrequired minimum duration, before clearing the bit, even though there is no maximum limit \nset by the USB standard.\nHigh speed: 50 ms\nFull speed/Low speed: 10 ms\nBit 7 PSUSP: Port suspend\nThe application sets this bit to put this port in Suspend mode. The core only stops sending \nSOFs when this is set. To stop the PHY clock, the application must set the Port clock stop \nbit, which asserts the suspend input pin of the PHY.\nThe read value of this bit reflects the current suspend status of the port. This bit is cleared \nby the core after a remote wake-up signal is detected or the application sets the Port reset \nbit or Port resume bit in this register or the Resume/remote wake-up detected interrupt bit or \nDisconnect detected interrupt bit in the Core interrupt register (WKUINT or DISCINT in \nOTG_HS_GINTSTS, respectively).\n0: Port not in Suspend mode\n1: Port in Suspend mode\nBit 6\nPRES: Port resume\nThe application sets this bit to drive resume signaling on the port. The core continues to \ndrive the resume signal until the application clears this bit.\nIf the core detects a USB remote wake-up sequence, as indicated by the Port \nresume/remote wake-up detected interrupt bit of the Core interrupt register (WKUINT bit in \nOTG_HS_GINTSTS), the core starts driving resume signaling without application \nintervention and clears this bit when it detects a disconnect condition. The read value of this \nbit indicates whether the core is currently driving resume signaling.\n0: No resume driven\n1: Resume driven\nBit 5 POCCHNG: Port overcurrent change\nThe core sets this bit when the status of the Port overcurrent active bit (bit 4) in this register \nchanges.\nBit 4 POCA: Port overcurrent active\nIndicates the overcurrent condition of the port.\n0: No overcurrent condition\n1: Overcurrent condition\nBit 3 PENCHNG: Port enable/disable change\nThe core sets this bit when the status of the Port enable bit [2] in this register changes.\n" }, { "page_number": 1440, "page_indices": { "start_index": 2854005, "end_index": 2856097 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1440 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.3 Host-mode registers", 1433 ], [ 4, "OTG_HS host channel-x characteristics register (OTG_HS_HCCHARx) (x = 0..11, where x = Channel_number)", 1440 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1440/1757\nRM0090 Rev 21\nOTG_HS host channel-x characteristics register (OTG_HS_HCCHARx) \n(x = 0..11, where x = Channel_number)\nAddress offset: 0x500 + 0x20 * x\nReset value: 0x0000 0000\n \n \nBit 2 PENA: Port enable\nA port is enabled only by the core after a reset sequence, and is disabled by an overcurrent \ncondition, a disconnect condition, or by the application clearing this bit. The application \ncannot set this bit by a register write. It can only clear it to disable the port. This bit does not \ntrigger any interrupt to the application.\n0: Port disabled\n1: Port enabled\nBit 1 PCDET: Port connect detected\nThe core sets this bit when a device connection is detected to trigger an interrupt to the \napplication using the host port interrupt bit in the Core interrupt register (HPRTINT bit in \nOTG_HS_GINTSTS). The application must write a 1 to this bit to clear the interrupt.\nBit 0 PCSTS: Port connect status\n0: No device is attached to the port\n1: A device is attached to the port\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nrs\nrs\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 CHENA: Channel enable\nThis field is set by the application and cleared by the OTG host.\n0: Channel disabled\n1: Channel enabled\nBit 30 CHDIS: Channel disable\nThe application sets this bit to stop transmitting/receiving data on a channel, even before \nthe transfer for that channel is complete. The application must wait for the Channel disabled \ninterrupt before treating the channel as disabled.\nBit 29 ODDFRM: Odd frame\nThis field is set (reset) by the application to indicate that the OTG host must perform a \ntransfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) \ntransactions.\n0: Even (micro) frame\n1: Odd (micro) frame\nBits 28:22 DAD: Device address\nThis field selects the specific device serving as the data source or sink.\n" }, { "page_number": 1441, "page_indices": { "start_index": 2856097, "end_index": 2857671 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1441 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.3 Host-mode registers", 1433 ], [ 4, "OTG_HS host channel-x characteristics register (OTG_HS_HCCHARx) (x = 0..11, where x = Channel_number)", 1440 ] ], "page_content": "RM0090 Rev 21\n1441/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBits 21:20 MC: Multi Count (MC) / Error Count (EC)\n– When the split enable bit (SPLITEN) in the host channel-x split control register \n(OTG_HS_HCSPLTx) is reset (0), this field indicates to the host the number of transactions \nthat must be executed per micro-frame for this periodic endpoint. For nonperiodic transfers, \nthis field specifies the number of packets to be fetched for this channel before the internal \nDMA engine changes arbitration.\n00: Reserved This field yields undefined results\n01: 1 transaction\nb10: 2 transactions to be issued for this endpoint per micro-frame\n11: 3 transactions to be issued for this endpoint per micro-frame.\n– When the SPLITEN bit is set (1) in OTG_HS_HCSPLTx, this field indicates the number of \nimmediate retries to be performed for a periodic split transaction on transaction errors. This \nfield must be set to at least 01.\nBits 19:18 EPTYP: Endpoint type\nIndicates the transfer type selected.\n00: Control\n01: Isochronous\n10: Bulk\n11: Interrupt\nBit 17 LSDEV: Low-speed device\nThis field is set by the application to indicate that this channel is communicating to a low-\nspeed device.\nBit 16 Reserved, must be kept at reset value.\nBit 15 EPDIR: Endpoint direction\nIndicates whether the transaction is IN or OUT.\n0: OUT\n1: IN\nBits 14:11 EPNUM: Endpoint number\nIndicates the endpoint number on the device serving as the data source or sink.\nBits 10:0 MPSIZ: Maximum packet size\nIndicates the maximum packet size of the associated endpoint.\n" }, { "page_number": 1442, "page_indices": { "start_index": 2857671, "end_index": 2859179 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1442 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.3 Host-mode registers", 1433 ], [ 4, "OTG_HS host channel-x split control register (OTG_HS_HCSPLTx) (x = 0..11, where x = Channel_number)", 1442 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1442/1757\nRM0090 Rev 21\nOTG_HS host channel-x split control register (OTG_HS_HCSPLTx) (x = 0..11, \nwhere x = Channel_number)\nAddress offset: 0x504 + 0x20 * x\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 SPLITEN: Split enable\nThe application sets this bit to indicate that this channel is enabled to perform split \ntransactions.\nBits 30:17\nReserved, must be kept at reset value.\nBit 16 COMPLSPLT: Do complete split\nThe application sets this bit to request the OTG host to perform a complete split transaction. \nBits 15:14 XACTPOS: Transaction position\nThis field is used to determine whether to send all, first, middle, or last payloads with each \nOUT transaction.\n11: All. This is the entire data payload of this transaction (which is less than or equal to 188 \nbytes)\n10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes)\n00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes)\n01: End. This is the last payload of this transaction (which is larger than 188 bytes)\nBits 13:7 HUBADDR: Hub address\nThis field holds the device address of the transaction translator’s hub.\nBits 6:0 PRTADDR: Port address\nThis field is the port number of the recipient transaction translator.\n" }, { "page_number": 1443, "page_indices": { "start_index": 2859179, "end_index": 2861237 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1443 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.3 Host-mode registers", 1433 ], [ 4, "OTG_HS host channel-x interrupt register (OTG_HS_HCINTx) (x = 0..11, where x = Channel_number)", 1443 ] ], "page_content": "RM0090 Rev 21\n1443/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS host channel-x interrupt register (OTG_HS_HCINTx) (x = 0..11, where \nx = Channel_number)\nAddress offset: 0x508 + 0x20 * x\nReset value: 0x0000 0000\nThis register indicates the status of a channel with respect to USB- and AHB-related events. \nIt is shown in Figure 414. The application must read this register when the host channels \ninterrupt bit in the Core interrupt register (HCINT bit in OTG_HS_GINTSTS) is set. Before \nthe application can read this register, it must first read the host all channels interrupt \n(OTG_HS_HAINT) register to get the exact channel number for the host channel-x interrupt \nregister. The application must clear the appropriate bit in this register to clear the \ncorresponding bits in the OTG_HS_HAINT and OTG_HS_GINTSTS registers.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nBits 31:11 Reserved, must be kept at reset value.\nBit 10 DTERR: Data toggle error\nBit 9 FRMOR: Frame overrun\nBit 8 BBERR: Babble error\nBit 7 TXERR: Transaction error\nIndicates one of the following errors occurred on the USB.\nCRC check failure\nTimeout\nBit stuff error\nFalse EOP\nBit 6 NYET: Response received interrupt\nBit 5 ACK: ACK response received/transmitted interrupt\nBit 4 NAK: NAK response received interrupt\nBit 3 STALL: STALL response received interrupt\nBit 2 AHBERR: AHB error\nThis error is generated only in Internal DMA mode when an AHB error occurs during an AHB \nread/write operation. The application can read the corresponding DMA channel address \nregister to get the error address.\nBit 1 CHH: Channel halted\nIndicates the transfer completed abnormally either because of any USB transaction error or in \nresponse to disable request by the application.\nBit 0 XFRC: Transfer completed\nTransfer completed normally without any errors.\n" }, { "page_number": 1444, "page_indices": { "start_index": 2861237, "end_index": 2862529 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1444 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.3 Host-mode registers", 1433 ], [ 4, "OTG_HS host channel-x interrupt mask register (OTG_HS_HCINTMSKx) (x = 0..11, where x = Channel_number)", 1444 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1444/1757\nRM0090 Rev 21\nOTG_HS host channel-x interrupt mask register (OTG_HS_HCINTMSKx) \n(x = 0..11, where x = Channel_number)\nAddress offset: 0x50C + 0x20 * x\nReset value: 0x0000 0000\nThis register reflects the mask for each channel status described in the previous section.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:11 Reserved, must be kept at reset value.\nBit 10 DTERRM: Data toggle error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 9 FRMORM: Frame overrun mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 8 BBERRM: Babble error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 7 TXERRM: Transaction error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 6 NYET: response received interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 5 ACKM: ACK response received/transmitted interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 4 NAKM: NAK response received interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 3 STALLM: STALL response received interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\n" }, { "page_number": 1445, "page_indices": { "start_index": 2862529, "end_index": 2864425 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1445 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.3 Host-mode registers", 1433 ], [ 4, "OTG_HS host channel-x transfer size register (OTG_HS_HCTSIZx) (x = 0..11, where x = Channel_number)", 1445 ] ], "page_content": "RM0090 Rev 21\n1445/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS host channel-x transfer size register (OTG_HS_HCTSIZx) (x = 0..11, \nwhere x = Channel_number)\nAddress offset: 0x510 + 0x20 * x\nReset value: 0x0000 0000\n \n \nBit 2 AHBERRM: AHB error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 1 CHHM: Channel halted mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 0 XFRCM: Transfer completed mask\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 DOPING: Do ping\nThis bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING \nprotocol.\nNote: Do not set this bit for IN transfers. If this bit is set for IN transfers it disables the channel. \nBits 30:29 DPID: Data PID\nThe application programs this field with the type of PID to use for the initial transaction. The \nhost maintains this field for the rest of the transfer.\n00: DATA0\n01: DATA2\n10: DATA1\n11: MDATA (noncontrol)/SETUP (control)\nBits 28:19 PKTCNT: Packet count\nThis field is programmed by the application with the expected number of packets to be \ntransmitted (OUT) or received (IN).\nThe host decrements this count on every successful transmission or reception of an OUT/IN \npacket. Once this count reaches zero, the application is interrupted to indicate normal \ncompletion.\nBits 18:0 XFRSIZ: Transfer size\nFor an OUT, this field is the number of data bytes the host sends during the transfer.\nFor an IN, this field is the buffer size that the application has reserved for the transfer. The \napplication is expected to program this field as an integer multiple of the maximum packet \nsize for IN transactions (periodic and nonperiodic).\n" }, { "page_number": 1446, "page_indices": { "start_index": 2864425, "end_index": 2866470 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1446 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.3 Host-mode registers", 1433 ], [ 4, "OTG_HS host channel-x DMA address register (OTG_HS_HCDMAx) (x = 0..11, where x = Channel_number)", 1446 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device configuration register (OTG_HS_DCFG)", 1446 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1446/1757\nRM0090 Rev 21\nOTG_HS host channel-x DMA address register (OTG_HS_HCDMAx) (x = 0..11, \nwhere x = Channel_number)\nAddress offset: 0x514 + 0x20 * x\nReset value: 0x0000 0000\n \n \n35.12.4 \nDevice-mode registers\nOTG_HS device configuration register (OTG_HS_DCFG)\nAddress offset: 0x800\nReset value: 0x0220 0000\nThis register configures the core in peripheral mode after power-on or after certain control \ncommands or enumeration. Do not make changes to this register after initial programming.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDMAADDR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 DMAADDR: DMA address\nThis field holds the start address in the external memory from which the data for the endpoint \nmust be fetched or to which it must be stored. This register is incremented on every AHB \ntransaction. \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPERSCHIVL\nReserved\nReserved\nPFIVL\nDAD\nReserved\nNZLSOHSK\nDSPD\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:26 Reserved, must be kept at reset value.\nBits 25:24 PERSCHIVL: Periodic scheduling interval\nThis field specifies the amount of time the Internal DMA engine must allocate for fetching \nperiodic IN endpoint data. Based on the number of periodic endpoints, this value must be \nspecified as 25, 50 or 75% of the (micro)frame.\n–\nWhen any periodic endpoints are active, the internal DMA engine allocates the \nspecified amount of time in fetching periodic IN endpoint data\n–\nWhen no periodic endpoint is active, then the internal DMA engine services \nnonperiodic endpoints, ignoring this field\n–\nAfter the specified time within a (micro)frame, the DMA switches to fetching \nnonperiodic endpoints\n00: 25% of (micro)frame\n01: 50% of (micro)frame\n10: 75% of (micro)frame\n11: Reserved\nBits 23:13 Reserved, must be kept at reset value.\n" }, { "page_number": 1447, "page_indices": { "start_index": 2866470, "end_index": 2868103 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1447 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device configuration register (OTG_HS_DCFG)", 1446 ] ], "page_content": "RM0090 Rev 21\n1447/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBits 12:11 PFIVL: Periodic (micro)frame interval\nIndicates the time within a (micro) frame at which the application must be notified using the \nend of periodic (micro) frame interrupt. This can be used to determine if all the isochronous \ntraffic for that frame is complete.\n00: 80% of the frame interval\n01: 85% of the frame interval\n10: 90% of the frame interval\n11: 95% of the frame interval\nBits 10:4 DAD: Device address\nThe application must program this field after every SetAddress control command.\nBit 3 Reserved, must be kept at reset value.\nBit 2 NZLSOHSK: Nonzero-length status OUT handshake\nThe application can use this field to select the handshake the core sends on receiving a \nnonzero-length data packet during the OUT transaction of a control transfer’s Status stage.\n1: Send a STALL handshake on a nonzero-length status OUT transaction and do not send \nthe received OUT packet to the application.\n0: Send the received OUT packet to the application (zero-length or nonzero-length) and \nsend a handshake based on the NAK and STALL bits for the endpoint in the device endpoint \ncontrol register.\nBits 1:0 DSPD: Device speed\nIndicates the speed at which the application requires the core to enumerate, or the \nmaximum speed the application can support. However, the actual bus speed is determined \nonly after the chirp sequence is completed, and is based on the speed of the USB host to \nwhich the core is connected.\n00: High speed\n01: Full speed using external ULPI PHY\n10: Reserved\n11: Full speed using internal embedded PHY\n" }, { "page_number": 1448, "page_indices": { "start_index": 2868103, "end_index": 2870040 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1448 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device control register (OTG_HS_DCTL)", 1448 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1448/1757\nRM0090 Rev 21\nOTG_HS device control register (OTG_HS_DCTL)\nAddress offset: 0x804\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPOPRGDNE\nCGONAK\nSGONAK\nCGINAK\nSGINAK\nTCTL\nGONSTS\nGINSTS\nSDIS\nRWUSIG\nrw\nw\nw\nw\nw\nrw\nrw\nrw\nr\nr\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBit 11 POPRGDNE: Power-on programming done\nThe application uses this bit to indicate that register programming is completed after a \nwake-up from power down mode.\nBit 10 CGONAK: Clear global OUT NAK\nWriting 1 to this field clears the Global OUT NAK.\nBit 9 SGONAK: Set global OUT NAK\nWriting 1 to this field sets the Global OUT NAK.\nThe application uses this bit to send a NAK handshake on all OUT endpoints.\nThe application must set the this bit only after making sure that the Global OUT NAK \neffective bit in the Core interrupt register (GONAKEFF bit in OTG_HS_GINTSTS) is \ncleared.\nBit 8 CGINAK: Clear global IN NAK\nWriting 1 to this field clears the Global IN NAK.\nBit 7 SGINAK: Set global IN NAK\nWriting 1 to this field sets the Global nonperiodic IN NAK.The application uses this bit to \nsend a NAK handshake on all nonperiodic IN endpoints.\nThe application must set this bit only after making sure that the Global IN NAK effective bit \nin the Core interrupt register (GINAKEFF bit in OTG_HS_GINTSTS) is cleared.\nBits 6:4 TCTL: Test control\n000: Test mode disabled\n001: Test_J mode\n010: Test_K mode\n011: Test_SE0_NAK mode\n100: Test_Packet mode\n101: Test_Force_Enable\nOthers: Reserved\nBit 3 GONSTS: Global OUT NAK status\n0: A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.\n1: No data is written to the RxFIFO, irrespective of space availability. Sends a NAK \nhandshake on all packets, except on SETUP transactions. All isochronous OUT packets are \ndropped.\n" }, { "page_number": 1449, "page_indices": { "start_index": 2870040, "end_index": 2871897 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1449 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device control register (OTG_HS_DCTL)", 1448 ] ], "page_content": "RM0090 Rev 21\n1449/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nTable 215 contains the minimum duration (according to device state) for which the Soft \ndisconnect (SDIS) bit must be set for the USB host to detect a device disconnect. To \naccommodate clock jitter, it is recommended that the application add some extra delay to \nthe specified minimum duration.\n \nBit 2 GINSTS: Global IN NAK status\n0: A handshake is sent out based on the data availability in the transmit FIFO.\n1: A NAK handshake is sent out on all nonperiodic IN endpoints, irrespective of the data \navailability in the transmit FIFO.\nBit 1 SDIS: Soft disconnect\nThe application uses this bit to signal the USB OTG core to perform a soft disconnect. As \nlong as this bit is set, the host does not see that the device is connected, and the device \ndoes not receive signals on the USB. The core stays in the disconnected state until the \napplication clears this bit.\n0: Normal operation. When this bit is cleared after a soft disconnect, the core generates a \ndevice connect event to the USB host. When the device is reconnected, the USB host \nrestarts device enumeration.\n1: The core generates a device disconnect event to the USB host.\nBit 0 RWUSIG: Remote wake-up signaling\nWhen the application sets this bit, the core initiates remote signaling to wake up the USB \nhost. The application must set this bit to instruct the core to exit the Suspend state. As \nspecified in the USB 2.0 specification, the application must clear this bit 1 ms to 15 ms after \nsetting it.\nTable 215. Minimum duration for soft disconnect\nOperating speed\nDevice state\nMinimum duration\nHigh speed\nNot Idle or Suspended (Performing transactions) \n125 µs\nFull speed\nSuspended\n1 ms + 2.5 µs\nFull speed\nIdle\n2.5 µs\nFull speed\nNot Idle or Suspended (Performing transactions)\n2.5 µs\n" }, { "page_number": 1450, "page_indices": { "start_index": 2871897, "end_index": 2873680 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1450 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device status register (OTG_HS_DSTS)", 1450 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1450/1757\nRM0090 Rev 21\nOTG_HS device status register (OTG_HS_DSTS)\nAddress offset: 0x808\nReset value: 0x0000 0010\nThis register indicates the status of the core with respect to USB-related events. It must be \nread on interrupts from the device all interrupts (OTG_HS_DAINT) register.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFNSOF\nReserved\nEERR\nENUMSPD\nSUSPSTS\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:22 Reserved, must be kept at reset value.\nBits 21:8 FNSOF: Frame number of the received SOF\nBits 7:4 Reserved, must be kept at reset value.\nBit 3 EERR: Erratic error\nThe core sets this bit to report any erratic errors.\nDue to erratic errors, the OTG_HS controller goes into Suspended state and an interrupt is \ngenerated to the application with Early suspend bit of the Core interrupt register (ESUSP bit \nin OTG_HS_GINTSTS). If the early suspend is asserted due to an erratic error, the \napplication can only perform a soft disconnect recover.\nBits 2:1 ENUMSPD: Enumerated speed\nIndicates the speed at which the OTG_HS controller has come up after speed detection \nthrough a chirp sequence.\n00: High speed\n01: Reserved\n10: Reserved\n11: Full speed (PHY clock is running at 48 MHz)\nOthers: reserved\nBit 0 SUSPSTS: Suspend status\nIn peripheral mode, this bit is set as long as a Suspend condition is detected on the USB. \nThe core enters the Suspended state when there is no activity on the USB data lines for a \nperiod of 3 ms. The core comes out of the suspend:\n– When there is an activity on the USB data lines\n– When the application writes to the Remote wake-up signaling bit in the Device control \nregister (RWUSIG bit in OTG_HS_DCTL).\n" }, { "page_number": 1451, "page_indices": { "start_index": 2873680, "end_index": 2875137 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1451 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device IN endpoint common interrupt mask register (OTG_HS_DIEPMSK)", 1451 ] ], "page_content": "RM0090 Rev 21\n1451/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device IN endpoint common interrupt mask register \n(OTG_HS_DIEPMSK)\nAddress offset: 0x810\nReset value: 0x0000 0000\nThis register works with each of the Device IN endpoint interrupt (OTG_HS_DIEPINTx) \nregisters for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt \nfor a specific status in the OTG_HS_DIEPINTx register can be masked by writing to the \ncorresponding bit in this register. Status bits are masked by default.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNAKM\nReserved\nTXFURM\nReserved\nINEPNEM\nINEPNMM\nITTXFEMSK\nTOM\nAHBERRM\nEPDM\nXFRCM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:10 Reserved, must be kept at reset value.\nBit 13 NAKM: NAK interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBits 12:9 Reserved, must be kept at reset value.\nBit 8 TXFURM: FIFO underrun mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 7 Reserved, must be kept at reset value.\nBit 6 INEPNEM: IN endpoint NAK effective mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 5 INEPNMM: IN token received with EP mismatch mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 4 ITTXFEMSK: IN token received when TxFIFO empty mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 3 TOM: Timeout condition mask (nonisochronous endpoints)\n0: Masked interrupt\n1: Unmasked interrupt\n" }, { "page_number": 1452, "page_indices": { "start_index": 2875137, "end_index": 2876633 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1452 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device OUT endpoint common interrupt mask register (OTG_HS_DOEPMSK)", 1452 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1452/1757\nRM0090 Rev 21\nOTG_HS device OUT endpoint common interrupt mask register \n(OTG_HS_DOEPMSK)\nAddress offset: 0x814\nReset value: 0x0000 0000\nThis register works with each of the Device OUT endpoint interrupt (OTG_HS_DOEPINTx) \nregisters for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint \ninterrupt for a specific status in the OTG_HS_DOEPINTx register can be masked by writing \ninto the corresponding bit in this register. Status bits are masked by default.\n \nBit 2 AHBERRM: AHB error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 1 EPDM: Endpoint disabled interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 0 XFRCM: Transfer completed interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNYETMSK\nNAKMSK\nBERRM\nReserved\nOPEM\nReserved\n B2BSTUP\nSTSPHSRXM\n OTEPDM\nSTUPM\nAHBERRM\nEPDM\nXFRCM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:15 Reserved, must be kept at reset value.\nBit 14 NYETMSK: NYET interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 13 NAKMSK: NAK interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 12 BERRM: Babble error interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBits 11:9 Reserved, must be kept at reset value.\nBit 8 OPEM: OUT packet error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 7 Reserved, must be kept at reset value.\n" }, { "page_number": 1453, "page_indices": { "start_index": 2876633, "end_index": 2878418 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1453 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device all endpoints interrupt register (OTG_HS_DAINT)", 1453 ] ], "page_content": "RM0090 Rev 21\n1453/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device all endpoints interrupt register (OTG_HS_DAINT)\nAddress offset: 0x818\nReset value: 0x0000 0000\nWhen a significant event occurs on an endpoint, a device all endpoints interrupt register \ninterrupts the application using the Device OUT endpoints interrupt bit or Device IN \nendpoints interrupt bit of the Core interrupt register (OEPINT or IEPINT in \nOTG_HS_GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum \nof 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the \ncorresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared \nwhen the application sets and clears bits in the corresponding Device Endpoint-x interrupt \nregister (OTG_HS_DIEPINTx/OTG_HS_DOEPINTx).\n \nBit 6 B2BSTUP: Back-to-back SETUP packets received mask\nApplies to control OUT endpoints only.\n0: Masked interrupt\n1: Unmasked interrupt\nBit 5 STSPHSRXM: Status phase received for control write mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 4 OTEPDM: OUT token received when endpoint disabled mask\nApplies to control OUT endpoints only.\n0: Masked interrupt\n1: Unmasked interrupt\nBit 3 STUPM: SETUP phase done mask\nApplies to control endpoints only.\n0: Masked interrupt\n1: Unmasked interrupt\nBit 2 AHBERRM: AHB error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 1 EPDM: Endpoint disabled interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 0 XFRCM: Transfer completed interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOEPINT\nIEPINT\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n" }, { "page_number": 1454, "page_indices": { "start_index": 2878418, "end_index": 2880306 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1454 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS all endpoints interrupt mask register (OTG_HS_DAINTMSK)", 1454 ], [ 4, "OTG_HS device VBUS discharge time register (OTG_HS_DVBUSDIS)", 1454 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1454/1757\nRM0090 Rev 21\n \nOTG_HS all endpoints interrupt mask register (OTG_HS_DAINTMSK)\nAddress offset: 0x81C\nReset value: 0x0000 0000\nThe device endpoint interrupt mask register works with the device endpoint interrupt register \nto interrupt the application when an event occurs on a device endpoint. However, the device \nall endpoints interrupt (OTG_HS_DAINT) register bit corresponding to that interrupt is still \nset.\n \n \nOTG_HS device VBUS discharge time register (OTG_HS_DVBUSDIS)\nAddress offset: 0x0828\nReset value: 0x0000 17D7\nThis register specifies the VBUS discharge time after VBUS pulsing during SRP.\n \n \nBits 31:16 OEPINT: OUT endpoint interrupt bits\nOne bit per OUT endpoint: \nBit 16 for OUT endpoint 0, bit 31 for OUT endpoint 15\nBits 15:0 IEPINT: IN endpoint interrupt bits\nOne bit per IN endpoint: \nBit 0 for IN endpoint 0, bit 15 for endpoint 15\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nOEPM\nIEPM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 OEPM: OUT EP interrupt mask bits\nOne per OUT endpoint:\nBit 16 for OUT EP 0, bit 19 for OUT EP 3\n0: Masked interrupt\n1: Unmasked interrupt\nBits 15:0 IEPM: IN EP interrupt mask bits\nOne bit per IN endpoint:\nBit 0 for IN EP 0, bit 3 for IN EP 3\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nVBUSDT\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 VBUSDT: Device VBUS discharge time\nSpecifies the VBUS discharge time after VBUS pulsing during SRP. This value equals:\nVBUS discharge time in PHY clocks / 1 024\nDepending on your VBUS load, this value may need adjusting.\n" }, { "page_number": 1455, "page_indices": { "start_index": 2880306, "end_index": 2880920 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1455 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device VBUS pulsing time register (OTG_HS_DVBUSPULSE)", 1455 ] ], "page_content": "RM0090 Rev 21\n1455/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device VBUS pulsing time register (OTG_HS_DVBUSPULSE)\nAddress offset: 0x082C\nReset value: 0x0000 05B8\nThis register specifies the VBUS pulsing time during SRP.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDVBUSP\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 DVBUSP: Device VBUS pulsing time\nSpecifies the VBUS pulsing time during SRP. This value equals:\nVBUS pulsing time in PHY clocks / 1 024\n" }, { "page_number": 1456, "page_indices": { "start_index": 2880920, "end_index": 2883173 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1456 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS Device threshold control register (OTG_HS_DTHRCTL)", 1456 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1456/1757\nRM0090 Rev 21\nOTG_HS Device threshold control register (OTG_HS_DTHRCTL)\nAddress offset: 0x0830\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nARPEN\nReserved\nRXTHRLEN\nRXTHREN\nReserved\nTXTHRLEN\nISOTHREN\nNONISOTHREN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value.\nBit 27 ARPEN: Arbiter parking enable\nThis bit controls internal DMA arbiter parking for IN endpoints. When thresholding is enabled \nand this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token \nreceived on the USB. This is done to avoid getting into underrun conditions. By default \nparking is enabled.\nBit 26\nReserved, must be kept at reset value.\nBits 25: 17 RXTHRLEN: Receive threshold length\nThis field specifies the receive thresholding size in words. This field also specifies the \namount of data received on the USB before the core can start transmitting on the AHB. The \nthreshold length has to be at least eight words. The recommended value for RXTHRLEN is \nto be the same as the programmed AHB burst length (HBSTLEN bit in \nOTG_HS_GAHBCFG). \nBit 16 RXTHREN: Receive threshold enable\nWhen this bit is set, the core enables thresholding in the receive direction.\nBits 15: 11\nReserved, must be kept at reset value.\nBits 10:2 TXTHRLEN: Transmit threshold length\nThis field specifies the transmit thresholding size in words. This field specifies the amount of \ndata in bytes to be in the corresponding endpoint transmit FIFO, before the core can start \ntransmitting on the USB. The threshold length has to be at least eight words. This field \ncontrols both isochronous and nonisochronous IN endpoint thresholds. The recommended \nvalue for TXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit \nin OTG_HS_GAHBCFG).\nBit 1 ISOTHREN: ISO IN endpoint threshold enable\nWhen this bit is set, the core enables thresholding for isochronous IN endpoints.\nBit 0 NONISOTHREN: Nonisochronous IN endpoints threshold enable\nWhen this bit is set, the core enables thresholding for nonisochronous IN endpoints. \n" }, { "page_number": 1457, "page_indices": { "start_index": 2883173, "end_index": 2884554 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1457 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device IN endpoint FIFO empty interrupt mask register: (OTG_HS_DIEPEMPMSK)", 1457 ], [ 4, "OTG_HS device each endpoint interrupt register (OTG_HS_DEACHINT)", 1457 ] ], "page_content": "RM0090 Rev 21\n1457/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device IN endpoint FIFO empty interrupt mask register: \n(OTG_HS_DIEPEMPMSK)\nAddress offset: 0x834\nReset value: 0x0000 0000\nThis register is used to control the IN endpoint FIFO empty interrupt generation \n(TXFE_OTG_HS_DIEPINTx).\n \n \nOTG_HS device each endpoint interrupt register (OTG_HS_DEACHINT)\nAddress offset: 0x0838\nReset value: 0x0000 0000\nThere is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nINEPTXFEM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 INEPTXFEM: IN EP Tx FIFO empty interrupt mask bits\nThese bits act as mask bits for OTG_HS_DIEPINTx.\nTXFE interrupt one bit per IN endpoint:\nBit 0 for IN endpoint 0, bit 15 for IN endpoint 15\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOEP1INT\nReserved\nIEP1INT\nReserved\nr\nr\nBits 31:18 Reserved, must be kept at reset value.\nBit 17 OEP1INT: OUT endpoint 1 interrupt bit \nBits 16:2 Reserved, must be kept at reset value.\nBit 1 IEP1INT: IN endpoint 1interrupt bit \nBit 0\nReserved, must be kept at reset value.\n" }, { "page_number": 1458, "page_indices": { "start_index": 2884554, "end_index": 2885959 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1458 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device each endpoint interrupt register mask (OTG_HS_DEACHINTMSK)", 1458 ], [ 4, "OTG_HS device each in endpoint-1 interrupt register (OTG_HS_DIEPEACHMSK1)", 1458 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1458/1757\nRM0090 Rev 21\nOTG_HS device each endpoint interrupt register mask \n(OTG_HS_DEACHINTMSK)\nAddress offset: 0x083C\nReset value: 0x0000 0000\nThere is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT.\n \nOTG_HS device each in endpoint-1 interrupt register \n(OTG_HS_DIEPEACHMSK1)\nAddress offset: 0x844\nReset value: 0x0000 0000\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nOEP1INTM\nReserved\nIEP1INTM\nReserved\nrw\nrw\nBits 31:18 Reserved, must be kept at reset value.\nBit 17 OEP1INTM: OUT Endpoint 1 interrupt mask bit \nBits 16:2\nReserved, must be kept at reset value.\nBit 1 IEP1INTM: IN Endpoint 1 interrupt mask bit \nBit 0\nReserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNAKM\nReserved\nBIM\nTXFURM\nReserved\nINEPNEM\nINEPNMM\nITTXFEMSK\nTOM\nAHBERRM\nEPDM\nXFRCM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:14 Reserved, must be kept at reset value.\nBit 13 NAKM: NAK interrupt mask\n0: Masked interrupt\n1: unmasked interrupt\nBit 12:10 Reserved, must be kept at reset value.\nBit 9 BIM: BNA interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 8 TXFURM: FIFO underrun mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 7 Reserved, must be kept at reset value.\n" }, { "page_number": 1459, "page_indices": { "start_index": 2885959, "end_index": 2887390 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1459 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device each OUT endpoint-1 interrupt register (OTG_HS_DOEPEACHMSK1)", 1459 ] ], "page_content": "RM0090 Rev 21\n1459/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device each OUT endpoint-1 interrupt register \n(OTG_HS_DOEPEACHMSK1)\nAddress offset: 0x884\nReset value: 0x0000 0000\n \n \nBit 6 INEPNEM: IN endpoint NAK effective mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 5 INEPNMM: IN token received with EP mismatch mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 4 ITTXFEMSK: IN token received when TxFIFO empty mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 3 TOM: Timeout condition mask (nonisochronous endpoints)\n0: Masked interrupt\n1: Unmasked interrupt\nBit 2 AHBERRM: AHB error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 1 EPDM: Endpoint disabled interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 0 XFRCM: Transfer completed interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNYETM\nNAKM\nBERRM\nReserved\nBIM\nTXFURM\nReserved\nINEPNEM\nINEPNMM\nITTXFEMSK\nTOM\nAHBERRM\nEPDM\nXFRCM\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:15 Reserved, must be kept at reset value.\nBit 14 NYETM: NYET interrupt mask\n0: Masked interrupt\n1: unmasked interrupt\nBit 13 NAKM: NAK interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 12 BERRM: Bubble error interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 11:10 Reserved, must be kept at reset value.\n" }, { "page_number": 1460, "page_indices": { "start_index": 2887390, "end_index": 2888482 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1460 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG device endpoint-x control register (OTG_HS_DIEPCTLx) (x = 0..5, where x = Endpoint_number)", 1460 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1460/1757\nRM0090 Rev 21\nOTG device endpoint-x control register (OTG_HS_DIEPCTLx) (x = 0..5, where \nx = Endpoint_number)\nAddress offset: 0x900 + 0x20 * x\nReset value: 0x0000 0000\nThe application uses this register to control the behavior of each logical endpoint other than \nendpoint 0.\n \n \nBit 9 BIM: BNA interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 8 OPEM: OUT packet error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBits 7:3 Reserved, must be kept at reset value.\nBit 2 AHBERRM: AHB error mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 1 EPDM: Endpoint disabled interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\nBit 0 XFRCM: Transfer completed interrupt mask\n0: Masked interrupt\n1: Unmasked interrupt\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nStall\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nrs\nrs\nw\nw\nw\nw\nrw\nrw\nrw\nrw\nrw/\nrs\nrw\nrw\nr\nr\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1461, "page_indices": { "start_index": 2888482, "end_index": 2891109 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1461 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG device endpoint-x control register (OTG_HS_DIEPCTLx) (x = 0..5, where x = Endpoint_number)", 1460 ] ], "page_content": "RM0090 Rev 21\n1461/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBit 31 EPENA: Endpoint enable\nThe application sets this bit to start transmitting data on an endpoint.\nThe core clears this bit before setting any of the following interrupts on this endpoint:\n– SETUP phase done\n– Endpoint disabled\n– Transfer completed\nBit 30 EPDIS: Endpoint disable\nThe application sets this bit to stop transmitting/receiving data on an endpoint, even before \nthe transfer for that endpoint is complete. The application must wait for the Endpoint \ndisabled interrupt before treating the endpoint as disabled. The core clears this bit before \nsetting the Endpoint disabled interrupt. The application must set this bit only if Endpoint \nenable is already set for this endpoint.\nBit 29 SODDFRM: Set odd frame\nApplies to isochronous IN and OUT endpoints only.\nWriting to this field sets the Even/Odd frame (EONUM) field to odd frame.\nBit 28 SD0PID: Set DATA0 PID\nApplies to interrupt/bulk IN endpoints only.\nWriting to this field sets the endpoint data PID (DPID) field in this register to DATA0.\nSEVNFRM: Set even frame\nApplies to isochronous IN endpoints only.\nWriting to this field sets the Even/Odd frame (EONUM) field to even frame.\nBit 27\nSNAK: Set NAK\nA write to this bit sets the NAK bit for the endpoint.\nUsing this bit, the application can control the transmission of NAK handshakes on an \nendpoint. The core can also set this bit for OUT endpoints on a Transfer completed interrupt, \nor after a SETUP is received on the endpoint.\nBit 26 CNAK: Clear NAK\nA write to this bit clears the NAK bit for the endpoint.\nBits 25:22 TXFNUM: TxFIFO number\nThese bits specify the FIFO number associated with this endpoint. Each active IN endpoint \nmust be programmed to a separate FIFO number.\nThis field is valid only for IN endpoints.\nBit 21 STALL: STALL handshake\nApplies to noncontrol, nonisochronous IN endpoints only (access type is rw).\nThe application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK \nbit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. \nOnly the application can clear this bit, never the core.\nApplies to control endpoints only (access type is rs).\nThe application can only set this bit, and the core clears it, when a SETUP token is received \nfor this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, \nthe STALL bit takes priority. Irrespective of this bit’s setting, the core always responds to \nSETUP data packets with an ACK handshake.\nBit 20 Reserved, must be kept at reset value.\n" }, { "page_number": 1462, "page_indices": { "start_index": 2891109, "end_index": 2893303 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1462 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG device endpoint-x control register (OTG_HS_DIEPCTLx) (x = 0..5, where x = Endpoint_number)", 1460 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1462/1757\nRM0090 Rev 21\nBits 19:18 EPTYP: Endpoint type\nThis is the transfer type supported by this logical endpoint.\n00: Control\n01: Isochronous\n10: Bulk\n11: Interrupt\nBit 17 NAKSTS: NAK status\nIt indicates the following:\n0: The core is transmitting nonNAK handshakes based on the FIFO status.\n1: The core is transmitting NAK handshakes on this endpoint.\nWhen either the application or the core sets this bit:\nFor nonisochronous IN endpoints: The core stops transmitting any data on an IN endpoint, \neven if there are data available in the TxFIFO.\nFor isochronous IN endpoints: The core sends out a zero-length data packet, even if there \nare data available in the TxFIFO.\nIrrespective of this bit’s setting, the core always responds to SETUP data packets with an ACK \nhandshake.\nBit 16 EONUM: Even/odd frame\nApplies to isochronous IN endpoints only.\nIndicates the frame number in which the core transmits/receives isochronous data for this \nendpoint. The application must program the even/odd frame number in which it intends to \ntransmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM \nfields in this register.\n0: Even frame\n1: Odd frame\nDPID: Endpoint data PID\nApplies to interrupt/bulk IN endpoints only.\nContains the PID of the packet to be received or transmitted on this endpoint. The \napplication must program the PID of the first packet to be received or transmitted on this \nendpoint, after the endpoint is activated. The application uses the SD0PID register field to \nprogram either DATA0 or DATA1 PID.\n0: DATA0\n1: DATA1\nBit 15 USBAEP: USB active endpoint\nIndicates whether this endpoint is active in the current configuration and interface. The core \nclears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving \nthe SetConfiguration and SetInterface commands, the application must program endpoint \nregisters accordingly and set this bit.\nBits 14:11 Reserved, must be kept at reset value.\nBits 10:0 MPSIZ: Maximum packet size\nThe application must program this field with the maximum packet size for the current logical \nendpoint. This value is in bytes.\n" }, { "page_number": 1463, "page_indices": { "start_index": 2893303, "end_index": 2895278 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1463 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device control OUT endpoint 0 control register (OTG_HS_DOEPCTL0)", 1463 ] ], "page_content": "RM0090 Rev 21\n1463/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device control OUT endpoint 0 control register \n(OTG_HS_DOEPCTL0)\nAddress offset: 0xB00\nReset value: 0x0000 8000\nThis section describes the device control OUT endpoint 0 control register. Nonzero control \nendpoints use registers for endpoints 1–15.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEPENA\nEPDIS\nReserved\nSNAK\nCNAK\nReserved\nStall\nSNPM\nEPTYP\nNAKSTS\nReserved\nUSBAEP\nReserved\nMPSIZ\nw\nr\nw\nw\nrs\nrw\nr\nr\nr\nr\nr\nr\nBit 31 EPENA: Endpoint enable\nThe application sets this bit to start transmitting data on endpoint 0.\nThe core clears this bit before setting any of the following interrupts on this endpoint:\n– SETUP phase done\n– Endpoint disabled\n– Transfer completed\nBit 30 EPDIS: Endpoint disable\nThe application cannot disable control OUT endpoint 0.\nBits 29:28 Reserved, must be kept at reset value.\nBit 27 SNAK: Set NAK\nA write to this bit sets the NAK bit for the endpoint.\nUsing this bit, the application can control the transmission of NAK handshakes on an \nendpoint. The core can also set this bit on a Transfer completed interrupt, or after a SETUP \nis received on the endpoint.\nBit 26 CNAK: Clear NAK\nA write to this bit clears the NAK bit for the endpoint.\nBits 25:22 Reserved, must be kept at reset value.\nBit 21 STALL: STALL handshake\nThe application can only set this bit, and the core clears it, when a SETUP token is received \nfor this endpoint. If a NAK bit or Global OUT NAK is set along with this bit, the STALL bit \ntakes priority. Irrespective of this bit’s setting, the core always responds to SETUP data \npackets with an ACK handshake.\nBit 20 SNPM: Snoop mode\nThis bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check \nthe correctness of OUT packets before transferring them to application memory.\nBits 19:18 EPTYP: Endpoint type\nHardcoded to 2’b00 for control.\n" }, { "page_number": 1464, "page_indices": { "start_index": 2895278, "end_index": 2896834 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1464 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device endpoint-x control register (OTG_HS_DOEPCTLx) (x = 1..5, where x = Endpoint_number)", 1464 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1464/1757\nRM0090 Rev 21\nOTG_HS device endpoint-x control register (OTG_HS_DOEPCTLx) (x = 1..5, \nwhere x = Endpoint_number)\nAddress offset for OUT endpoints: 0xB00 + 0x20 * x\nReset value: 0x0000 0000\nThe application uses this register to control the behavior of each logical endpoint other than \nendpoint 0.\n \n \nBit 17 NAKSTS: NAK status\nIndicates the following:\n0: The core is transmitting nonNAK handshakes based on the FIFO status.\n1: The core is transmitting NAK handshakes on this endpoint.\nWhen either the application or the core sets this bit, the core stops receiving data, even if \nthere is space in the RxFIFO to accommodate the incoming packet. Irrespective of this bit’s \nsetting, the core always responds to SETUP data packets with an ACK handshake.\nBit 16 Reserved, must be kept at reset value.\nBit 15 USBAEP: USB active endpoint\nThis bit is always set to 1, indicating that a control endpoint 0 is always active in all \nconfigurations and interfaces.\nBits 14:2 Reserved, must be kept at reset value.\nBits 1:0 MPSIZ: Maximum packet size\nThe maximum packet size for control OUT endpoint 0 is the same as what is programmed in \ncontrol IN endpoint 0.\n00: 64 bytes\n01: 32 bytes\n10: 16 bytes\n11: 8 bytes\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nReserved\nStall\nSNPM\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nrs\nrs\nw\nw\nw\nw\nrw\nrw\nrw\nrw\nr\nr\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1465, "page_indices": { "start_index": 2896834, "end_index": 2899235 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1465 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device endpoint-x control register (OTG_HS_DOEPCTLx) (x = 1..5, where x = Endpoint_number)", 1464 ] ], "page_content": "RM0090 Rev 21\n1465/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nBit 31 EPENA: Endpoint enable\nApplies to IN and OUT endpoints.\nThe application sets this bit to start transmitting data on an endpoint.\nThe core clears this bit before setting any of the following interrupts on this endpoint:\n– SETUP phase done\n– Endpoint disabled\n– Transfer completed\nBit 30 EPDIS: Endpoint disable\nThe application sets this bit to stop transmitting/receiving data on an endpoint, even before \nthe transfer for that endpoint is complete. The application must wait for the Endpoint \ndisabled interrupt before treating the endpoint as disabled. The core clears this bit before \nsetting the Endpoint disabled interrupt. The application must set this bit only if Endpoint \nenable is already set for this endpoint.\nBit 29 SODDFRM: Set odd frame\nApplies to isochronous OUT endpoints only.\nWriting to this field sets the Even/Odd frame (EONUM) field to odd frame.\nBit 28 SD0PID: Set DATA0 PID\nApplies to interrupt/bulk OUT endpoints only.\nWriting to this field sets the endpoint data PID (DPID) field in this register to DATA0.\nSEVNFRM: Set even frame\nApplies to isochronous OUT endpoints only.\nWriting to this field sets the Even/Odd frame (EONUM) field to even frame.\nBit 27 SNAK: Set NAK\nA write to this bit sets the NAK bit for the endpoint.\nUsing this bit, the application can control the transmission of NAK handshakes on an \nendpoint. The core can also set this bit for OUT endpoints on a Transfer Completed \ninterrupt, or after a SETUP is received on the endpoint.\nBit 26 CNAK: Clear NAK\nA write to this bit clears the NAK bit for the endpoint.\nBits 25:22 Reserved, must be kept at reset value.\nBit 21 STALL: STALL handshake\nApplies to noncontrol, nonisochronous OUT endpoints only (access type is rw).\nThe application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK \nbit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes \npriority. Only the application can clear this bit, never the core.\nBit 20 SNPM: Snoop mode\nThis bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check \nthe correctness of OUT packets before transferring them to application memory.\nBits 19:18 EPTYP: Endpoint type\nThis is the transfer type supported by this logical endpoint.\n00: Control\n01: Isochronous\n10: Bulk\n11: Interrupt\n" }, { "page_number": 1466, "page_indices": { "start_index": 2899235, "end_index": 2901155 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1466 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device endpoint-x control register (OTG_HS_DOEPCTLx) (x = 1..5, where x = Endpoint_number)", 1464 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1466/1757\nRM0090 Rev 21\nBit 17 NAKSTS: NAK status\nIndicates the following:\n0: The core is transmitting nonNAK handshakes based on the FIFO status.\n1: The core is transmitting NAK handshakes on this endpoint.\nWhen either the application or the core sets this bit:\nThe core stops receiving any data on an OUT endpoint, even if there is space in the \nRxFIFO to accommodate the incoming packet.\nIrrespective of this bit’s setting, the core always responds to SETUP data packets with an \nACK handshake.\nBit 16 EONUM: Even/odd frame\nApplies to isochronous IN and OUT endpoints only.\nIndicates the frame number in which the core transmits/receives isochronous data for this \nendpoint. The application must program the even/odd frame number in which it intends to \ntransmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM \nfields in this register.\n0: Even frame\n1: Odd frame\nDPID: Endpoint data PID\nApplies to interrupt/bulk OUT endpoints only.\nContains the PID of the packet to be received or transmitted on this endpoint. The \napplication must program the PID of the first packet to be received or transmitted on this \nendpoint, after the endpoint is activated. The application uses the SD0PID register field to \nprogram either DATA0 or DATA1 PID.\n0: DATA0\n1: DATA1\nBit 15 USBAEP: USB active endpoint\nIndicates whether this endpoint is active in the current configuration and interface. The core \nclears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving \nthe SetConfiguration and SetInterface commands, the application must program endpoint \nregisters accordingly and set this bit.\nBits 14:11 Reserved, must be kept at reset value.\nBits 10:0 MPSIZ: Maximum packet size\nThe application must program this field with the maximum packet size for the current logical \nendpoint. This value is in bytes.\n" }, { "page_number": 1467, "page_indices": { "start_index": 2901155, "end_index": 2903934 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1467 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device endpoint-x interrupt register (OTG_HS_DIEPINTx) (x = 0..5, where x = Endpoint_number)", 1467 ] ], "page_content": "RM0090 Rev 21\n1467/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device endpoint-x interrupt register (OTG_HS_DIEPINTx) (x = 0..5, \nwhere x = Endpoint_number)\nAddress offset: 0x908 + 0x20 * x\nReset value: 0x0000 0080\nThis register indicates the status of an endpoint with respect to USB- and AHB-related \nevents. It is shown in Figure 414. The application must read this register when the IN \nendpoints interrupt bit of the Core interrupt register (IEPINT in OTG_HS_GINTSTS) is set. \nBefore the application can read this register, it must first read the device all endpoints \ninterrupt (OTG_HS_DAINT) register to get the exact endpoint number for the device \nendpoint-x interrupt register. The application must clear the appropriate bit in this register to \nclear the corresponding bits in the OTG_HS_DAINT and OTG_HS_GINTSTS registers.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nrc_\nw1\nrc_\nw1\nrc_\nw1\nr\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nBits 31:14 Reserved, must be kept at reset value.\nBit 13 NAK: NAK interrupt\nThe core generates this interrupt when a NAK is transmitted or received by the device. In \ncase of isochronous IN endpoints the interrupt gets generated when a zero length packet is \ntransmitted due to unavailability of data in the Tx FIFO.\nBit 12 Reserved, must be kept at reset value.\nBit 11 PKTDRPSTS: Packet dropped status\nThis bit indicates to the application that an ISOC OUT packet has been dropped. This bit \ndoes not have an associated mask bit and does not generate an interrupt.\nBits 10:9\nReserved, must be kept at reset value.\nBit 8 TXFIFOUDRN: Transmit Fifo Underrun (TxfifoUndrn) The core generates this interrupt when it \ndetects a transmit FIFO underrun condition for this endpoint. \nDependency: This interrupt is valid only when Thresholding is enabled \nBit 7 TXFE: Transmit FIFO empty\nThis interrupt is asserted when the TxFIFO for this endpoint is either half or completely \nempty. The half or completely empty status is determined by the TxFIFO empty level bit in \nthe Core AHB configuration register (TXFELVL bit in OTG_HS_GAHBCFG).\nBit 6 INEPNE: IN endpoint NAK effective\nThis bit can be cleared when the application clears the IN endpoint NAK by writing to the \nCNAK bit in OTG_HS_DIEPCTLx.\nThis interrupt indicates that the core has sampled the NAK bit set (either by the application \nor by the core). The interrupt indicates that the IN endpoint NAK bit set by the application \nhas taken effect in the core.\nThis interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit \ntakes priority over a NAK bit.\n" }, { "page_number": 1468, "page_indices": { "start_index": 2903934, "end_index": 2905249 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1468 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device endpoint-x interrupt register (OTG_HS_DIEPINTx) (x = 0..5, where x = Endpoint_number)", 1467 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1468/1757\nRM0090 Rev 21\nBit 5 INEPNM: IN token received with EP mismatch\nIndicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other \nthan the one for which the IN token was received. This interrupt is asserted on the endpoint \nfor which the IN token was received.\nBit 4 ITTXFE: IN token received when TxFIFO is empty\nApplies to nonperiodic IN endpoints only.\nIndicates that an IN token was received when the associated TxFIFO (periodic/nonperiodic) \nwas empty. This interrupt is asserted on the endpoint for which the IN token was received.\nBit 3 TOC: Timeout condition\nApplies only to Control IN endpoints.\nIndicates that the core has detected a timeout condition on the USB for the last IN token on \nthis endpoint. \nBit 2 AHBERR: AHB error\nThis is generated only in internal DMA mode when there is an AHB error during an AHB \nread/write. The application can read the corresponding endpoint DMA address register to \nget the error address.\nBit 1 EPDISD: Endpoint disabled interrupt\nThis bit indicates that the endpoint is disabled per the application’s request.\nBit 0 XFRC: Transfer completed interrupt\nThis field indicates that the programmed transfer is complete on the AHB as well as on the \nUSB, for this endpoint.\n" }, { "page_number": 1469, "page_indices": { "start_index": 2905249, "end_index": 2907755 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1469 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device endpoint-x interrupt register (OTG_HS_DOEPINTx) (x = 0..5, where x = Endpoint_number)", 1469 ] ], "page_content": "RM0090 Rev 21\n1469/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device endpoint-x interrupt register (OTG_HS_DOEPINTx) (x = 0..5, \nwhere x = Endpoint_number)\nAddress offset: 0xB08 + 0x20 * x\nReset value: 0x0000 0080\nThis register indicates the status of an endpoint with respect to USB- and AHB-related \nevents. It is shown in Figure 414. The application must read this register when the OUT \nEndpoints Interrupt bit of the Core interrupt register (OEPINT bit in OTG_HS_GINTSTS) is \nset. Before the application can read this register, it must first read the device all endpoints \ninterrupt (OTG_HS_DAINT) register to get the exact endpoint number for the device \nEndpoint-x interrupt register. The application must clear the appropriate bit in this register to \nclear the corresponding bits in the OTG_HS_DAINT and OTG_HS_GINTSTS registers.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nrc_\nw1\nBits 31:15 Reserved, must be kept at reset value.\nBit 14 NYET: NYET interrupt\nThe core generates this interrupt when a NYET response is transmitted for a \nnonisochronous OUT endpoint.\nBit 13 NAK: NAK input\nThe core generates this interrupt when a NAK is transmitted or received by the device. In \ncase of isochronous IN endpoints the interrupt gets generated when a zero length packet is \ntransmitted due to unavailability of data in the Tx FIFO.\nBit 12 BERR: Babble error interrupt\nThe core generates this interrupt when babble is received for the endpoint.\nBits 11:9 Reserved, must be kept at reset value.\nBit 8 OUTPKTERR: OUT packet error\nThis interrupt is asserted when the core detects an overflow or a CRC error for an OUT \npacket. This interrupt is valid only when thresholding is enabled.\nBit 7 Reserved, must be kept at reset value.\nBit 6 B2BSTUP: Back-to-back SETUP packets received\nApplies to Control OUT endpoint only.\nThis bit indicates that the core has received more than three back-to-back SETUP packets \nfor this particular endpoint.\nBit 5\nReserved, must be kept at reset value.\nBit 4 OTEPDIS: OUT token received when endpoint disabled\nApplies only to control OUT endpoint.\nIndicates that an OUT token was received when the endpoint was not yet enabled. This \ninterrupt is asserted on the endpoint for which the OUT token was received.\n" }, { "page_number": 1470, "page_indices": { "start_index": 2907755, "end_index": 2910069 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1470 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device IN endpoint 0 transfer size register (OTG_HS_DIEPTSIZ0)", 1470 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1470/1757\nRM0090 Rev 21\nOTG_HS device IN endpoint 0 transfer size register (OTG_HS_DIEPTSIZ0)\nAddress offset: 0x910\nReset value: 0x0000 0000\nThe application must modify this register before enabling endpoint 0. Once endpoint 0 is \nenabled using the endpoint enable bit in the device control endpoint 0 control registers \n(EPENA in OTG_HS_DIEPCTL0), the core modifies this register. The application can only \nread this register once the core has cleared the Endpoint enable bit.\nNonzero endpoints use the registers for endpoints 1–15.\n \n \nBit 3 STUP: SETUP phase done\nApplies to control OUT endpoints only.\nIndicates that the SETUP phase for the control endpoint is complete and no more back-to-\nback SETUP packets were received for the current control transfer. On this interrupt, the \napplication can decode the received SETUP data packet.\nBit 2 AHBERR: AHB error\nThis is generated only in internal DMA mode when there is an AHB error during an AHB \nread/write. The application can read the corresponding endpoint DMA address register to \nget the error address.\nBit 1 EPDISD: Endpoint disabled interrupt\nThis bit indicates that the endpoint is disabled per the application’s request.\nBit 0 XFRC: Transfer completed interrupt\nThis field indicates that the programmed transfer is complete on the AHB as well as on the \nUSB, for this endpoint.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPKTCNT\nReserved\nXFRSIZ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:21 Reserved, must be kept at reset value.\nBits 20:19 PKTCNT: Packet count\nIndicates the total number of USB packets that constitute the Transfer Size amount of data \nfor endpoint 0.\nThis field is decremented every time a packet (maximum size or short packet) is read from \nthe TxFIFO.\nBits 18:7 Reserved, must be kept at reset value.\nBits 6:0 XFRSIZ: Transfer size\nIndicates the transfer size in bytes for endpoint 0. The core interrupts the application only \nafter it has exhausted the transfer size amount of data. The transfer size can be set to the \nmaximum packet size of the endpoint, to be interrupted at the end of each packet.\nThe core decrements this field every time a packet from the external memory is written to \nthe TxFIFO.\n" }, { "page_number": 1471, "page_indices": { "start_index": 2910069, "end_index": 2911701 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1471 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device OUT endpoint 0 transfer size register (OTG_HS_DOEPTSIZ0)", 1471 ] ], "page_content": "RM0090 Rev 21\n1471/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device OUT endpoint 0 transfer size register (OTG_HS_DOEPTSIZ0)\nAddress offset: 0xB10\nReset value: 0x0000 0000\nThe application must modify this register before enabling endpoint 0. Once endpoint 0 is \nenabled using the Endpoint enable bit in the device control endpoint 0 control registers \n(EPENA bit in OTG_HS_DOEPCTL0), the core modifies this register. The application can \nonly read this register once the core has cleared the Endpoint enable bit.\nNonzero endpoints use the registers for endpoints 1–15.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nSTUPC\nNT\nReserved\nPKTCNT\nReserved\nXFRSIZ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBits 30:29 STUPCNT: SETUP packet count\nThis field specifies the number of back-to-back SETUP data packets the endpoint can \nreceive.\n01: 1 packet\n10: 2 packets\n11: 3 packets\nBits 28:20 Reserved, must be kept at reset value.\nBit 19 PKTCNT: Packet count\nThis field is decremented to zero after a packet is written into the RxFIFO.\nBits 18:7 Reserved, must be kept at reset value.\nBits 6:0 XFRSIZ: Transfer size\nIndicates the transfer size in bytes for endpoint 0. The core interrupts the application only \nafter it has exhausted the transfer size amount of data. The transfer size can be set to the \nmaximum packet size of the endpoint, to be interrupted at the end of each packet.\nThe core decrements this field every time a packet is read from the RxFIFO and written to \nthe external memory.\n" }, { "page_number": 1472, "page_indices": { "start_index": 2911701, "end_index": 2913506 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1472 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device endpoint-x transfer size register (OTG_HS_DIEPTSIZx) (x = 1..5, where x = Endpoint_number)", 1472 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1472/1757\nRM0090 Rev 21\nOTG_HS device endpoint-x transfer size register (OTG_HS_DIEPTSIZx) \n(x = 1..5, where x = Endpoint_number)\nAddress offset: 0x910 + 0x20 * x\nReset value: 0x0000 0000\nThe application must modify this register before enabling the endpoint. Once the endpoint is \nenabled using the Endpoint enable bit in the device endpoint-x control registers (EPENA bit \nin OTG_HS_DIEPCTLx), the core modifies this register. The application can only read this \nregister once the core has cleared the Endpoint enable bit.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMCNT\nPKTCNT\nXFRSIZ\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 31 Reserved, must be kept at reset value.\nBits 30:29 MCNT: Multi count\nFor periodic IN endpoints, this field indicates the number of packets that must be transmitted \nper frame on the USB. The core uses this field to calculate the data PID for isochronous IN \nendpoints.\n01: 1 packet\n10: 2 packets\n11: 3 packets\nBit 28:19 PKTCNT: Packet count\nIndicates the total number of USB packets that constitute the Transfer Size amount of data \nfor this endpoint. \nThis field is decremented every time a packet (maximum size or short packet) is read from \nthe TxFIFO.\nBits 18:0 XFRSIZ: Transfer size\nThis field contains the transfer size in bytes for the current endpoint. The core only interrupts \nthe application after it has exhausted the transfer size amount of data. The transfer size can \nbe set to the maximum packet size of the endpoint, to be interrupted at the end of each \npacket.\nThe core decrements this field every time a packet from the external memory is written to the \nTxFIFO.\n" }, { "page_number": 1473, "page_indices": { "start_index": 2913506, "end_index": 2915073 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1473 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device IN endpoint transmit FIFO status register (OTG_HS_DTXFSTSx) (x = 0..5, where x = Endpoint_number)", 1473 ], [ 4, "OTG_HS device endpoint-x transfer size register (OTG_HS_DOEPTSIZx) (x = 1..5, where x = Endpoint_number)", 1473 ] ], "page_content": "RM0090 Rev 21\n1473/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS device IN endpoint transmit FIFO status register \n(OTG_HS_DTXFSTSx) (x = 0..5, where x = Endpoint_number)\nAddress offset for IN endpoints: 0x918 + 0x20 + x\nThis read-only register contains the free space information for the Device IN endpoint \nTxFIFO.\n \n \nOTG_HS device endpoint-x transfer size register (OTG_HS_DOEPTSIZx) \n(x = 1..5, where x = Endpoint_number)\nAddress offset: 0xB10 + 0x20 * x\nReset value: 0x0000 0000\nThe application must modify this register before enabling the endpoint. Once the endpoint is \nenabled using Endpoint Enable bit of the device endpoint-x control registers (EPENA bit in \nOTG_HS_DOEPCTLx), the core modifies this register. The application can only read this \nregister once the core has cleared the Endpoint enable bit.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nINEPTFSAV\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n31:16 Reserved, must be kept at reset value.\n15:0 INEPTFSAV: IN endpoint TxFIFO space avail ()\nIndicates the amount of free space available in the Endpoint TxFIFO.\nValues are in terms of 32-bit words:\n0x0: Endpoint TxFIFO is full\n0x1: 1 word available\n0x2: 2 words available\n0xn: n words available (0 < n < 512)\nOthers: Reserved\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRXDPID/S\nTUPCNT\nPKTCNT\nXFRSIZ\nr/rw\nr/rw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1474, "page_indices": { "start_index": 2915073, "end_index": 2917271 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1474 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.4 Device-mode registers", 1446 ], [ 4, "OTG_HS device endpoint-x DMA address register (OTG_HS_DIEPDMAx / OTG_HS_DOEPDMAx) (x = 0..5, where x = Endpoint_number)", 1474 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1474/1757\nRM0090 Rev 21\n \nOTG_HS device endpoint-x DMA address register (OTG_HS_DIEPDMAx / \nOTG_HS_DOEPDMAx) (x = 0..5, where x = Endpoint_number)\nAddress offset for IN endpoints: 0x914 + 0x20 * x\nReset value: 0xXXXX XXXX\nAddress offset for OUT endpoints: 0xB14 + 0x20 * x\nReset value: 0xXXXX XXXX\n \nBit 31 Reserved, must be kept at reset value.\nBits 30:29 RXDPID: Received data PID (access type is \"r\")\nApplies to isochronous OUT endpoints only.\nThis is the data PID received in the last packet for this endpoint.\n00: DATA0\n01: DATA2\n10: DATA1\n11: MDATA\nSTUPCNT: SETUP packet count (access type is \"rw\")\nApplies to control OUT Endpoints only.\nThis field specifies the number of back-to-back SETUP data packets the endpoint can \nreceive.\n01: 1 packet\n10: 2 packets\n11: 3 packets\nBit 28:19 PKTCNT: Packet count\nIndicates the total number of USB packets that constitute the Transfer Size amount of data \nfor this endpoint.\nThis field is decremented every time a packet (maximum size or short packet) is written to \nthe RxFIFO.\nBits 18:0 XFRSIZ: Transfer size\nThis field contains the transfer size in bytes for the current endpoint. The core only interrupts \nthe application after it has exhausted the transfer size amount of data. The transfer size can \nbe set to the maximum packet size of the endpoint, to be interrupted at the end of each \npacket.\nThe core decrements this field every time a packet is read from the RxFIFO and written to \nthe external memory.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nDMAADDR\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 DMAADDR: DMA address\nThis bit holds the start address of the external memory for storing or fetching endpoint data.\nNote: For control endpoints, this field stores control OUT data packets as well as SETUP \ntransaction data packets. When more than three SETUP packets are received back-to-\nback, the SETUP data packet in the memory is overwritten. This register is incremented \non every AHB transaction. The application can give only a word-aligned address.\n" }, { "page_number": 1475, "page_indices": { "start_index": 2917271, "end_index": 2919090 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1475 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.5 OTG_HS power and clock gating control register (OTG_HS_PCGCCTL)", 1475 ], [ 3, "35.12.6 OTG_HS register map", 1475 ] ], "page_content": "RM0090 Rev 21\n1475/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n35.12.5 \nOTG_HS power and clock gating control register\n(OTG_HS_PCGCCTL)\nAddress offset: 0xE00\nReset value: 0x0000 0000\nThis register is available in host and peripheral modes.\n \n \n35.12.6 \nOTG_HS register map\nThe table below gives the USB OTG register map and reset values.\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nPHYSUSP\nReserved\nGATEHCLK\nSTPPCLK\nrw\nrw\nrw\nBit 31:5 Reserved, must be kept at reset value.\nBit 4 PHYSUSP: PHY suspended\nIndicates that the PHY has been suspended. This bit is updated once the PHY is suspended \nafter the application has set the STPPCLK bit (bit 0).\nBits 3:2 Reserved, must be kept at reset value.\nBit 1 GATEHCLK: Gate HCLK\nThe application sets this bit to gate HCLK to modules other than the AHB Slave and Master \nand wake-up logic when the USB is suspended or the session is not valid. The application \nclears this bit when the USB is resumed or a new session starts.\nBit 0 STPPCLK: Stop PHY clock\nThe application sets this bit to stop the PHY clock when the USB is suspended, the session \nis not valid, or the device is disconnected. The application clears this bit when the USB is \nresumed or a new session starts.\nTable 216. OTG_HS register map and reset values\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x000\nOTG_HS_GO\nTGCTL\nReserved\nBSVLD\nASVLD\nDBCT\nCIDSTS\nReserved\nDHNPEN\nHSHNPEN\nHNPRQ\nHNGSCS\nReserved\nSRQ\nSRQSCS\nReset value\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0x004\nOTG_HS_GO\nTGINT\nReserved\nDBCDNE\nADTOCHG\nHNGDET\nReserved\nHNSSCHG\nSRSSCHG\nReserved\nSEDET\nRes.\nReset value\n0\n0\n0\n0\n0\n0\n0x008\nOTG_HS_GA\nHBCFG\nReserved\nPTXFELVL\nTXFELVL\nReserved\nGINT\nReset value\n0\n0\n0\n" }, { "page_number": 1476, "page_indices": { "start_index": 2919090, "end_index": 2920959 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1476 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.6 OTG_HS register map", 1475 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1476/1757\nRM0090 Rev 21\n0x00C\nOTG_HS_GU\nSBCFG\nCTXPKT\nFDMOD\nFHMOD\nReserved\nULPIIPD\nPTCI\nPCCI\nTSDPS\nULPIEVBUSI\nULPIEVBUSD\nULPICSM\nULPIAR\nULPIFSLS\nReserved\nPHYLPCS\nReserved\nTRDT\nHNPCAP\nSRPCAP\nReserved\nPHYSEL\nReserve\nd\nTOCAL\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n1\n0\n0\n1\n0\n0\n0\n0x010\nOTG_HS_GR\nSTCTL\nAHBIDL\nDMAREQ\nReserved\nTXFNUM\nTXFFLSH\nRXFFLSH\nReserved\nFCRST\nHSRST\nCSRST\nReset value\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x014\nOTG_HS_GIN\nTSTS\nWKUINT\nSRQINT\nDISCINT\nCIDSCHG\nReserved\nPTXFE\nHCINT\nHPRTINT\nReserved\nDATAFSUSP\nIPXFR/INCOMPISOOUT\nIISOIXFR\nOEPINT\nIEPINT\nReserved\nEOPF\nISOODRP\nENUMDNE\nUSBRST\nUSBSUSP\nESUSP\nReserved\nGONAKEFF\nGINAKEFF\nNPTXFE\nRXFLVL\nSOF\nOTGINT\nMMIS\nCMOD\nReset value\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0x018\nOTG_HS_GIN\nTMSK\nWUIM\nSRQIM\nDISCINT\nCIDSCHGM\nReserved\nPTXFEM\nHCIM\nPRTIM\nReserved\nFSUSPM\nIPXFRM/IISOOXFRM\nIISOIXFRM\nOEPINT\nIEPINT\nReserved\nEOPFM\nISOODRPM\nENUMDNEM\nUSBRST\nUSBSUSPM\nESUSPM\nReserved\nGONAKEFFM\nGINAKEFFM\nNPTXFEM\nRXFLVLM\nSOFM\nOTGINT\nMMISM\nReserved\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x01C\nOTG_HS_GR\nXSTSR (Host \nmode)\nReserved\nPKTSTS\nDPID\nBCNT\nCHNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nOTG_HS_GR\nXSTSR \n(peripheral \nmode)\nReserved\nFRMNUM\nPKTSTS\nDPID\nBCNT\nEPNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x020\nOTG_HS_GR\nXSTSP (Host \nmode)\nReserved\nPKTSTS\nDPID\nBCNT\nCHNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nOTG_HS_GR\nXSTSP \n(peripheral \nmode)\nReserved\nFRMNUM\nPKTSTS\nDPID\nBCNT\nEPNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x024\nOTG_HS_GR\nXFSIZ\nReserved\nRXFD\nReset value\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1477, "page_indices": { "start_index": 2920959, "end_index": 2922867 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1477 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.6 OTG_HS register map", 1475 ] ], "page_content": "RM0090 Rev 21\n1477/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n0x028\nOTG_HS_GN\nPTXFSIZ \n(Host mode)\nNPTXFD\nNPTXFSA\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\nOTG_HS_GN\nPTXFSIZ\n(peripheral \nmode)\nTX0FD\nTX0FSA\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x02C\nOTG_HS_GN\nPTXSTS\nRes.\nNPTXQTOP\nNPTQXSAV\nNPTXFSAV\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x030\nOTG_HS_GI2\nCCTL\nBSYDNE\nRW\nReserved\nI2CDATSE0\nI2CDEVADR\nReserved\nACK\nI2CEN\nADDR\nREGADDR\nRWDATA\n0x038\nOTG_HS_GC\nCFG\nReserved\nNOVBUSSENS\nSOFOUTEN\nVBUSBSEN\nVBUSASEN\n.I2CPADEN\n.PWRDWN\nReserved\nReset value\n0\n0\n0\n0\n0\n0\n0x03C\nOTG_HS_CID\nPRODUCT_ID\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0x100\nOTG_HS_HPT\nXFSIZ\nPTXFD\nPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x104\nOTG_HS_DIE\nPTXF1\nINEPTXFD\nINEPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x108\nOTG_HS_DIE\nPTXF2\nINEPTXFD\nINEPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x10C\nOTG_HS_DIE\nPTXF3\nINEPTXFD\nINEPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x110\nOTG_HS_DIE\nPTXF4\nINEPTXFD\nINEPTXSA\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x400\nOTG_HS_HCF\nG\nReserved\nFSLSS\nFSLSPCS\nReset value\n0\n0\n0\n0x404\nOTG_HS_HFI\nR\nReserved\nFRIVL\nReset value\n1\n1\n1\n0\n1\n0\n1\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0x408\nOTG_HS_HFN\nUM\nFTREM\nFRNUM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n1\n0x410\nOTG_HS_HPT\nXSTS\nPTXQTOP\nPTXQSAV\nPTXFSAVL\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nY\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1478, "page_indices": { "start_index": 2922867, "end_index": 2924892 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1478 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.6 OTG_HS register map", 1475 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1478/1757\nRM0090 Rev 21\n0x414\nOTG_HS_HAI\nNT\nReserved\nHAINT\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x418\nOTG_HS_HAI\nNTMSK\nReserved\nHAINTM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x440\nOTG_HS_HPR\nT\nReserved\nPSP\nD\nPTCTL\nPPWR\nPLSTS\nReserved\nPRST\nPSUSP\nPRES\nPOCCHNG\nPOCA\nPENCHNG\nPENA\nPCDET\nPCSTS\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x500\nOTG_HS_HC\nCHAR0\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x520\nOTG_HS_HC\nCHAR1\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x540\nOTG_HS_HC\nCHAR2\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x560\nOTG_HS_HC\nCHAR3\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x580\nOTG_HS_HC\nCHAR4\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5A0\nOTG_HS_HC\nCHAR5\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5C0\nOTG_HS_HC\nCHAR6\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5E0\nOTG_HS_HC\nCHAR7\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x600\nOTG_HS_HC\nCHAR8\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1479, "page_indices": { "start_index": 2924892, "end_index": 2926607 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1479 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.6 OTG_HS register map", 1475 ] ], "page_content": "RM0090 Rev 21\n1479/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n0x620\nOTG_HS_HC\nCHAR9\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x640\nOTG_HS_HC\nCHAR10\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x660\nOTG_HS_HC\nCHAR11\nCHENA\nCHDIS\nODDFRM\nDAD\nMC\nEPTYP\nLSDEV\nReserved\nEPDIR\nEPNUM\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x504\nOTG_HS_HCS\nPLT0\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x508\nOTG_HS_HCI\nNT0\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x524\nOTG_HS_HCS\nPL1\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x528\nOTG_HS_HCI\nNT1\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x544\nOTG_HS_HCS\nPLT2\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x548\nOTG_HS_HCI\nNT2\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x564\nOTG_HS_HCS\nPLT3\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x568\nOTG_HS_HCI\nNT3\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1480, "page_indices": { "start_index": 2926607, "end_index": 2928077 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1480 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.6 OTG_HS register map", 1475 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1480/1757\nRM0090 Rev 21\n0x584\nOTG_HS_HCS\nPLT4\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x588\nOTG_HS_HCI\nNT4\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5A4\nOTG_HS_HCS\nPLT5\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5A8\nOTG_HS_HCI\nNT5\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5C4\nOTG_HS_HCS\nPLT6\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5C8\nOTG_HS_HCI\nNT6\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5E4\nOTG_HS_HCS\nPLT7\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5E8\nOTG_HS_HCI\nNT7\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x604\nOTG_HS_HCS\nPLT8\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x608\nOTG_HS_HCI\nNT8\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1481, "page_indices": { "start_index": 2928077, "end_index": 2929748 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1481 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.6 OTG_HS register map", 1475 ] ], "page_content": "RM0090 Rev 21\n1481/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n0x624\nOTG_HS_HCS\nPLT9\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x628\nOTG_HS_HCI\nNT9\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x644\nOTG_HS_HCS\nPLT10\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x648\nOTG_HS_HCI\nNT10\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x664\nOTG_HS_HCS\nPLT11\nSPLITEN\nReserved\nCOMPLSPLT\nXACTPOS\nHUBADDR\nPRTADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x668\nOTG_HS_HCI\nNT11\nReserved\nDTERR\nFRMOR\nBBERR\nTXERR\nNYET\nACK\nNAK\nSTALL\nAHBERR\nCHH\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x50C\nOTG_HS_HCI\nNTMSK0\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x52C\nOTG_HS_HCI\nNTMSK1\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x54C\nOTG_HS_HCI\nNTMSK2\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x56C\nOTG_HS_HCI\nNTMSK3\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x58C\nOTG_HS_HCI\nNTMSK4\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1482, "page_indices": { "start_index": 2929748, "end_index": 2931448 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1482 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.6 OTG_HS register map", 1475 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1482/1757\nRM0090 Rev 21\n0x5AC\nOTG_HS_HCI\nNTMSK5\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5CC\nOTG_HS_HCI\nNTMSK6\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5EC\nOTG_HS_HCI\nNTMSK7\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x60C\nOTG_HS_HCI\nNTMSK8\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x62C\nOTG_HS_HCI\nNTMSK9\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x64C\nOTG_HS_HCI\nNTMSK10\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x66C\nOTG_HS_HCI\nNTMSK11\nReserved\nDTERRM\nFRMORM\nBBERRM\nTXERRM\nNYET\nACKM\nNAKM\nSTALLM\nAHBERRM\nCHHM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x510\nOTG_HS_HCT\nSIZ0\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x530\nOTG_HS_HCT\nSIZ1\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x550\nOTG_HS_HCT\nSIZ2\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x570\nOTG_HS_HCT\nSIZ3\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1483, "page_indices": { "start_index": 2931448, "end_index": 2933327 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1483 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.6 OTG_HS register map", 1475 ] ], "page_content": "RM0090 Rev 21\n1483/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n0x590\nOTG_HS_HCT\nSIZ4\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5B0\nOTG_HS_HCT\nSIZ5\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5D0\nOTG_HS_HCT\nSIZ6\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5F0\nOTG_HS_HCT\nSIZ7\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x610\nOTG_HS_HCT\nSIZ8\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x630\nOTG_HS_HCT\nSIZ9\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x650\nOTG_HS_HCT\nSIZ10\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x670\nOTG_HS_HCT\nSIZ11\nDOPING\nDPID\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x514\nOTG_HS_HC\nDMA0\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x524\nOTG_HS_HC\nDMA1\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x544\nOTG_HS_HC\nDMA2\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x564\nOTG_HS_HC\nDMA3\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x584\nOTG_HS_HC\nDMA4\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5A4\nOTG_HS_HC\nDMA5\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1484, "page_indices": { "start_index": 2933327, "end_index": 2935187 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1484 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.6 OTG_HS register map", 1475 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1484/1757\nRM0090 Rev 21\n0x5C4\nOTG_HS_HC\nDMA6\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x5E4\nOTG_HS_HC\nDMA7\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x604\nOTG_HS_HC\nDMA8\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x624\nOTG_HS_HC\nDMA9\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x644\nOTG_HS_HC\nDMA10\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x664\nOTG_HS_HC\nDMA11\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x800\nOTG_HS_\nDCFG\nReserved\nPERSCHIVL\nReserved\nReserved\nPFIVL\nDAD\nReserved\nNZLSOHSK\nDSPD\nReset value\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x804\nOTG_HS_DCT\nL\nReserved\nPOPRGDNE\nCGONAK\nSGONAK\nCGINAK\nSGINAK\nTCTL\nGONSTS\nGINSTS\nSDIS\nRWUSIG\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x808\nOTG_HS_DST\nS\nReserved\nFNSOF\nReserved\nEERR\nENUMSPD\nSUSPSTS\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x810\nOTG_HS_DIE\nPMSK\nReserved\nNAKM\nReserved\nTXFURM\nReserved\nINEPNEM\nINEPNMM\nITTXFEMSK\nTOM\nAHBERRM\nEPDM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x814\nOTG_HS_DO\nEPMSK\nReserved\nNYETMSK\nNAKMSK\nBERRM\nReserved\nOPEM\nReserved\n B2BSTUP\nSTSPHSRXM\n OTEPDM\nSTUPM\nAHBERRM\nEPDM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x818\nOTG_HS_DAI\nNT\nOEPINT\nIEPINT\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x81C\nOTG_HS_DAI\nNTMSK\nOEPM\nIEPM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x828\nOTG_HS_DVB\nUSDIS\nReserved\nVBUSDT\nReset value\n0\n0\n0\n1\n0\n1\n1\n1\n1\n1\n0\n1\n0\n1\n1\n1\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1485, "page_indices": { "start_index": 2935187, "end_index": 2936796 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1485 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.6 OTG_HS register map", 1475 ] ], "page_content": "RM0090 Rev 21\n1485/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n0x82C\nOTG_HS_DVB\nUSPULSE\nReserved\nDVBUSP\nReset value\n0\n1\n0\n1\n1\n0\n1\n1\n1\n0\n0\n0\n0x830\nOTG_HS_DTH\nRCTL\nReserved\nARPEN\nReserved\nRXTHRLEN\nRXTHREN\nReserved\nTXTHRLEN\nISOTHREN\nNONISOTHREN\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x834\nOTG_HS_DIE\nPEMPMSK\nReserved\nINEPTXFEM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x838\nOTG_HS_DEA\nCHINT\nReserved\nReserved\nReserved\nReset value\n0\n0\n0x83C\nOTG_HS_DEA\nCHINTMSK\nReserved\nReserved\nReserved\nReset value\n0\n0\n0x844\nOTG_HS_DIE\nPEACHMSK1\nReserved\nNAKM\nReserve\nd\nBIM\nTXFURM\nReserved\nINEPNEM\nINEPNMM\nITTXFEMSK\nTOM\nAHBERRM\nEPDM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x884\nOTG_HS_DO\nEPEACHMSK\n1\nReserved\nNYETM\nNAKM\nBERRM\nReserved\nBIM\nTXFURM\nReserved\nINEPNEM\nINEPNMM\nITTXFEMSK\nTOM\nAHBERRM\nEPDM\nXFRCM\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x900\nOTG_HS_DIE\nPCTL0\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x918\nOTG_HS_DTX\nFSTS0\nReserved\nINEPTFSAV\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x920\nOTG_HS_DIE\nPCTL1\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nStall\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x938\nOTG_HS_DTX\nFSTS1\nReserved\nINEPTFSAV\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1486, "page_indices": { "start_index": 2936796, "end_index": 2938586 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1486 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.6 OTG_HS register map", 1475 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1486/1757\nRM0090 Rev 21\n0x940\nOTG_HS_DIE\nPCTL2\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nStall\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x958\nOTG_HS_DTX\nFSTS2\nReserved\nINEPTFSAV\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x960\nOTG_HS_DIE\nPCTL3\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nStall\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x978\nOTG_HS_DTX\nFSTS3\nReserved\nINEPTFSAV\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x980\nOTG_HS_DIE\nPCTL4\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nStall\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x9A0\nOTG_HS_DIE\nPCTL5\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x9C0\nOTG_HS_DIE\nPCTL6\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x9E0\nOTG_HS_DIE\nPCTL7\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nTXFNUM\nSTALL\nReserved\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB00\nOTG_HS_DO\nEPCTL0\nEPENA\nEPDIS\nReserved\nSNAK\nCNAK\nReserved\nSTALL\nSNPM\nEPT\nYP\nNAKSTS\nReserved\nUSBAEP\nReserved\nMPSI\nZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1487, "page_indices": { "start_index": 2938586, "end_index": 2940211 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1487 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.6 OTG_HS register map", 1475 ] ], "page_content": "RM0090 Rev 21\n1487/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n0xB20\nOTG_HS_DO\nEPCTL1\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nReserved\nSTALL\nSNPM\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB40\nOTG_HS_DO\nEPCTL2\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nReserved\nStall\nSNPM\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB60\nOTG_HS_DO\nEPCTL3\nEPENA\nEPDIS\nSODDFRM\nSD0PID/SEVNFRM\nSNAK\nCNAK\nReserved\nStall\nSNPM\nEPTYP\nNAKSTS\nEONUM/DPID\nUSBAEP\nReserved\nMPSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x908\nOTG_HS_DIE\nPINT0\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0x928\nOTG_HS_DIE\nPINT1\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0x948\nOTG_HS_DIE\nPINT2\nReserved\nNAK\nBERR\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nReset value\n0\nReserved\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0x968\nOTG_HS_DIE\nPINT3\nReserved\nNAK\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0x988\nOTG_HS_DIE\nPINT4\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1488, "page_indices": { "start_index": 2940211, "end_index": 2941865 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1488 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.6 OTG_HS register map", 1475 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1488/1757\nRM0090 Rev 21\n0x9A8\nOTG_HS_DIE\nPINT5\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0x9C8\nOTG_HS_DIE\nPINT6\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0x9E8\nOTG_HS_DIE\nPINT7\nReserved\nNAK\nReserved\nPKTDRPSTS\nReserved\nTXFIFOUDRN\nTXFE\nINEPNE\nINEPNM\nITTXFE\nTOC\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n1\n0\n0\n0\n0\n0\n0\n0\n0xB08\nOTG_HS_DO\nEPINT0\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n1\n0\n0\n0\n0xB28\nOTG_HS_DO\nEPINT1\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB48\nOTG_HS_DO\nEPINT2\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB68\nOTG_HS_DO\nEPINT3\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB88\nOTG_HS_DO\nEPINT4\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xBA8\nOTG_HS_DO\nEPINT5\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1489, "page_indices": { "start_index": 2941865, "end_index": 2943895 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1489 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.12 OTG_HS control and status registers", 1405 ], [ 3, "35.12.6 OTG_HS register map", 1475 ] ], "page_content": "RM0090 Rev 21\n1489/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n0xBC8\nOTG_HS_DO\nEPINT6\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xBE8\nOTG_HS_DO\nEPINT7\nReserved\nNYET\nNAK\nBERR\nReserved\nOUTPKTERR\nReserved\nB2BSTUP\nReserved\nOTEPDIS\nSTUP\nAHBERR\nEPDISD\nXFRC\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x910\nOTG_HS_DIE\nPTSIZ0\nReserved\nPKT\nCNT\nReserved\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x930\nOTG_HS_DIE\nPTSIZ1\nReserved\nMCN\nT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x934\nOTG_HS_DIE\nPDMA1\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x93C\nOTG_HS_DIE\nPDMAB1\nDMABADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x950\nOTG_HS_DIE\nPTSIZ2\nReserved\nMCN\nT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x954\nOTG_HS_DIE\nPDMA2\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x95C\nOTG_HS_DIE\nPDMAB2\nDMABADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x970\nOTG_HS_DIE\nPTSIZ3\nReserved\nMCN\nT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x974\nOTG_HS_DIE\nPDMA3\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x97C\nOTG_HS_DIE\nPDMAB3\nDMABADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB10\nOTG_HS_DO\nEPTSIZ0\nReserved\nSTU\nPCN\nT\nReserved\nPKTCNT\nReserved\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB30\nOTG_HS_DO\nEPTSIZ1\nReserved\nRXDPID/\nSTUPCNT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB34\nOTG_HS_DO\nEPDMA1\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1490, "page_indices": { "start_index": 2943895, "end_index": 2945780 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1490 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.1 Core initialization", 1490 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1490/1757\nRM0090 Rev 21\nRefer to Section 2.3: Memory map for the register boundary addresses.\n35.13 \nOTG_HS programming model\n35.13.1 \nCore initialization\nThe application must perform the core initialization sequence. If the cable is connected \nduring power-up, the current mode of operation bit in the Core interrupt register (CMOD bit \nin OTG_HS_GINTSTS) reflects the mode. The OTG_HS controller enters host mode when \nan “A” plug is connected or peripheral mode when a “B” plug is connected.\nThis section explains the initialization of the OTG_HS controller after power-on. The \napplication must follow the initialization sequence irrespective of host or peripheral mode \noperation. All core global registers are initialized according to the core’s configuration:\n0xB3C\nOTG_HS_DO\nEPDMAB1\nDMABADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB50\nOTG_HS_DO\nEPTSIZ2\nReserved\nRXDPID/\nSTUPCNT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB54\nOTG_HS_DO\nEPDMA2\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB5C\nOTG_HS_DO\nEPDMAB2\nDMABADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB70\nOTG_HS_DO\nEPTSIZ3\nReserved\nRXDPID/\nSTUPCNT\nPKTCNT\nXFRSIZ\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB74\nOTG_HS_DO\nEPDMA3\nDMAADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xB7C\nOTG_HS_DO\nEPDMAB3\nDMABADDR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xE00\nOTG_HS_PC\nGCCTL\nReserved\nPHYSUSP\nReserved\nGATEHCLK\nSTPPCLK\nReset value\nTable 216. OTG_HS register map and reset values (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1491, "page_indices": { "start_index": 2945780, "end_index": 2947950 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1491 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.2 Host initialization", 1491 ] ], "page_content": "RM0090 Rev 21\n1491/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n1.\nProgram the following fields in the Global AHB configuration (OTG_HS_GAHBCFG) \nregister:\n–\nDMA mode bit\n–\nAHB burst length field\n–\nGlobal interrupt mask bit GINT = 1\n–\nRxFIFO nonempty (RXFLVL bit in OTG_HS_GINTSTS)\n–\nPeriodic TxFIFO empty level\n2. \nProgram the following fields in OTG_HS_GUSBCFG register:\n–\nHNP capable bit \n–\nSRP capable bit\n–\nFS timeout calibration field\n–\nUSB turnaround time field\n3. \nThe software must unmask the following bits in the GINTMSK register:\nOTG interrupt mask\nMode mismatch interrupt mask\n4. \nThe software can read the CMOD bit in OTG_HS_GINTSTS to determine whether the \nOTG_HS controller is operating in host or peripheral mode.\n35.13.2 \nHost initialization\nTo initialize the core as host, the application must perform the following steps:\n1.\nProgram the HPRTINT in GINTMSK to unmask\n2. \nProgram the OTG_HS_HCFG register to select full-speed host\n3. \nProgram the PPWR bit in OTG_HS_HPRT to 1. This drives VBUS on the USB.\n4. \nWait for the PCDET interrupt in OTG_HS_HPRT0. This indicates that a device is \nconnecting to the port.\n5. \nProgram the PRST bit in OTG_HS_HPRT to 1. This starts the reset process.\n6. \nWait at least 10 ms for the reset process to complete.\n7. \nProgram the PRST bit in OTG_HS_HPRT to 0.\n8. \nWait for the PENCHNG interrupt in OTG_HS_HPRT.\n9. \nRead the PSPD bit in OTG_HS_HPRT to get the enumerated speed.\n10. Program the HFIR register with a value corresponding to the selected PHY clock 1.\n11. Program the FSLSPCS field in OTG_HS_HCFG register according to the speed of the \ndetected device read in step 9. If FSLSPCS has been changed, reset the port.\n12. Program the OTG_HS_GRXFSIZ register to select the size of the receive FIFO.\n13. Program the OTG_HS_GNPTXFSIZ register to select the size and the start address of \nthe nonperiodic transmit FIFO for nonperiodic transactions.\n14. Program the OTG_HS_HPTXFSIZ register to select the size and start address of the \nperiodic transmit FIFO for periodic transactions.\nTo communicate with devices, the system software must initialize and enable at least one \nchannel.\n" }, { "page_number": 1492, "page_indices": { "start_index": 2947950, "end_index": 2949789 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1492 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.3 Device initialization", 1492 ], [ 3, "35.13.4 DMA mode", 1492 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Channel initialization", 1492 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1492/1757\nRM0090 Rev 21\n35.13.3 \nDevice initialization\nThe application must perform the following steps to initialize the core as a device on power-\nup or after a mode change from host to device.\n1.\nProgram the following fields in the OTG_HS_DCFG register:\n–\nDevice speed\n–\nNonzero-length status OUT handshake\n2. \nProgram the OTG_HS_GINTMSK register to unmask the following interrupts:\n–\nUSB reset\n–\nEnumeration done\n–\nEarly suspend\n–\nUSB suspend\n–\nSOF\n3. \nProgram the VBUSBSEN bit in the OTG_HS_GCCFG register to enable VBUS sensing \nin “B” peripheral mode and supply the 5 volts across the pull-up resistor on the DP line.\n4. \nWait for the USBRST interrupt in OTG_HS_GINTSTS. It indicates that a reset has \nbeen detected on the USB that lasts for about 10 ms on receiving this interrupt.\nWait for the ENUMDNE interrupt in OTG_HS_GINTSTS. This interrupt indicates the end of \nreset on the USB. On receiving this interrupt, the application must read the OTG_HS_DSTS \nregister to determine the enumeration speed and perform the steps listed in Endpoint \ninitialization on enumeration completion on page 1519. \nAt this point, the device is ready to accept SOF packets and perform control transfers on \ncontrol endpoint 0.\n35.13.4 \nDMA mode\nThe OTG host uses the AHB master interface to fetch the transmit packet data (AHB to \nUSB) and receive the data update (USB to AHB). The AHB master uses the programmed \nDMA address (HCDMAx register in host mode and DIEPDMAx/DOEPDMAx register in \nperipheral mode) to access the data buffers.\n35.13.5 \nHost programming model\nChannel initialization\nThe application must initialize one or more channels before it can communicate with \nconnected devices. To initialize and enable a channel, the application must perform the \nfollowing steps:\n" }, { "page_number": 1493, "page_indices": { "start_index": 2949789, "end_index": 2953174 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1493 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Halting a channel", 1493 ] ], "page_content": "RM0090 Rev 21\n1493/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n1.\nProgram the GINTMSK register to unmask the following:\n2. \nChannel interrupt\n–\nNonperiodic transmit FIFO empty for OUT transactions (applicable for Slave mode \nthat operates in pipelined transaction-level with the packet count field \nprogrammed with more than one).\n–\nNonperiodic transmit FIFO half-empty for OUT transactions (applicable for Slave \nmode that operates in pipelined transaction-level with the packet count field \nprogrammed with more than one).\n3. \nProgram the OTG_HS_HAINTMSK register to unmask the selected channels’ \ninterrupts.\n4. \nProgram the OTG_HS_HCINTMSK register to unmask the transaction-related \ninterrupts of interest given in the host channel interrupt register.\n5. \nProgram the selected channel’s OTG_HS_HCTSIZx register with the total transfer size, \nin bytes, and the expected number of packets, including short packets. The application \nmust program the PID field with the initial data PID (to be used on the first OUT \ntransaction or to be expected from the first IN transaction).\n6. \nProgram the selected channels in the OTG_HS_HCSPLTx register(s) with the hub and \nport addresses (split transactions only).\n7. \nProgram the selected channels in the HCDMAx register(s) with the buffer start address.\n8. \nProgram the OTG_HS_HCCHARx register of the selected channel with the device’s \nendpoint characteristics, such as type, speed, direction, and so forth. (The channel can \nbe enabled by setting the channel enable bit to 1 only when the application is ready to \ntransmit or receive any packet).\nHalting a channel\nThe application can disable any channel by programming the OTG_HS_HCCHARx register \nwith the CHDIS and CHENA bits set to 1. This enables the OTG_HS host to flush the posted \nrequests (if any) and generates a channel halted interrupt. The application must wait for the \nCHH interrupt in OTG_HS_HCINTx before reallocating the channel for other transactions. \nThe OTG_HS host does not interrupt the transaction that has already been started on the \nUSB.\nTo disable a channel in DMA mode operation, the application does not need to check for \nspace in the request queue. The OTG_HS host checks for space to write the disable \nrequest on the disabled channel’s turn during arbitration. Meanwhile, all posted requests are \ndropped from the request queue when the CHDIS bit in HCCHARx is set to 1. \nBefore disabling a channel, the application must ensure that there is at least one free space \navailable in the nonperiodic request queue (when disabling a nonperiodic channel) or the \nperiodic request queue (when disabling a periodic channel). The application can simply \nflush the posted requests when the Request queue is full (before disabling the channel), by \nprogramming the OTG_HS_HCCHARx register with the CHDIS bit set to 1, and the CHENA \nbit cleared to 0.\nThe application is expected to disable a channel on any of the following conditions:\n1.\nWhen an XFRC interrupt in OTG_HS_HCINTx is received during a nonperiodic IN \ntransfer or high-bandwidth interrupt IN transfer (Slave mode only)\n2. \nWhen an STALL, TXERR, BBERR or DTERR interrupt in OTG_HS_HCINTx is \nreceived for an IN or OUT channel (Slave mode only). For high-bandwidth interrupt INs \nin Slave mode, once the application has received a DTERR interrupt it must disable the \n" }, { "page_number": 1494, "page_indices": { "start_index": 2953174, "end_index": 2956017 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1494 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Ping protocol", 1494 ], [ 4, "Operational model", 1494 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1494/1757\nRM0090 Rev 21\nchannel and wait for a channel halted interrupt. The application must be able to receive \nother interrupts (DTERR, NAK, Data, TXERR) for the same channel before receiving \nthe halt.\n3. \nWhen a DISCINT (Disconnect Device) interrupt in OTG_HS_GINTSTS is received. \n(The application is expected to disable all enabled channels\n4. \nWhen the application aborts a transfer before normal completion.\nPing protocol\nWhen the OTG_HS host operates in high speed, the application must initiate the ping \nprotocol when communicating with high-speed bulk or control (data and status stage) OUT \nendpoints.\nThe application must initiate the ping protocol when it receives a NAK/NYET/TXERR \ninterrupt. When the HS_OTG host receives one of the above responses, it does not \ncontinue any transaction for a specific endpoint, drops all posted or fetched OUT requests \n(from the request queue), and flushes the corresponding data (from the transmit FIFO).\nThis is valid in slave mode only. In Slave mode, the application can send a ping token either \nby setting the DOPING bit in HCTSIZx before enabling the channel or by just writing the \nHCTSIZx register with the DOPING bit set when the channel is already enabled. This \nenables the HS_OTG host to write a ping request entry to the request queue. The \napplication must wait for the response to the ping token (a NAK, ACK, or TXERR interrupt) \nbefore continuing the transaction or sending another ping token. The application can \ncontinue the data transaction only after receiving an ACK from the OUT endpoint for the \nrequested ping. In DMA mode operation, the application does not need to set the DOPING \nbit in HCTSIZx for a NAK/NYET response in case of Bulk/Control OUT. The OTG_HS host \nautomatically sets the DOPING bit in HCTSIZx, and issues the ping tokens for Bulk/Control \nOUT. The HS_OTG host continues sending ping tokens until it receives an ACK, and then \nswitches automatically to the data transaction.\nOperational model\nThe application must initialize a channel before communicating to the connected device. \nThis section explains the sequence of operation to be performed for different types of USB \ntransactions.\n•\nWriting the transmit FIFO\nThe OTG_HS host automatically writes an entry (OUT request) to the periodic/nonperiodic \nrequest queue, along with the last word write of a packet. The application must ensure that \nat least one free space is available in the periodic/nonperiodic request queue before starting \nto write to the transmit FIFO. The application must always write to the transmit FIFO in \nwords. If the packet size is non-word-aligned, the application must use padding. The \nOTG_HS host determines the actual packet size based on the programmed maximum \npacket size and transfer size.\n" }, { "page_number": 1495, "page_indices": { "start_index": 2956017, "end_index": 2956455 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1495 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "RM0090 Rev 21\n1495/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nFigure 416. Transmit FIFO write task\nMSv65219V1\n1 MPS\nor LPS FIFO space\navailable?\nWait for\nTXFELVL or PTXFELVL \ninterrupt in \nOTG_HS_GAHBCFG\nWrite 1 packet \ndata to\nTransmit FIFO\nMore packets\nto send?\nRead GNPTXSTS/HPTXFSIZ \nregisters for available FIFO \nand queue spaces\nStart\nDone\nNo\nYes\nYes\nNo\nMPS: Maximum packet size\nLPS: Last packet size\n" }, { "page_number": 1496, "page_indices": { "start_index": 2956455, "end_index": 2957600 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1496 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1496/1757\nRM0090 Rev 21\n•\nReading the receive FIFO\nThe application must ignore all packet statuses other than IN data packet (bx0010).\nFigure 417. Receive FIFO read task\n•\nBulk and control OUT/SETUP transactions\nA typical bulk or control OUT/SETUP pipelined transaction-level operation is shown in \nFigure 418. See channel 1 (ch_1). Two bulk OUT packets are transmitted. A control \nSETUP transaction operates in the same way but has only one packet. The \nassumptions are:\n–\nThe application is attempting to send two maximum-packet-size packets (transfer \nsize = 1, 024 bytes).\n–\nThe nonperiodic transmit FIFO can hold two packets (128 bytes for FS).\n–\nThe nonperiodic request queue depth = 4.\n•\nNormal bulk and control OUT/SETUP operations\nThe sequence of operations for channel 1 is as follows:\na) \nInitialize channel 1\nb) \nWrite the first packet for channel 1\nMSv65220V1\nRXFLVL\ninterrupt?\nRead the received\npacket from the\nReceive FIFO\nRead \nOTG_HS_GRXSTSP\nPKTSTS\n0b0010?\nUnmask RXFLVL\ninterrupt\nBCNT > 0?\nMask RXFLVL\ninterrupt\nUnmask RXFLVL\ninterrupt\nStart\nNo\nNo\nNo\nYes\nYes\nYes\n" }, { "page_number": 1497, "page_indices": { "start_index": 2957600, "end_index": 2958253 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1497 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "RM0090 Rev 21\n1497/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nc) \nAlong with the last word write, the core writes an entry to the nonperiodic request \nqueue\nd) \nAs soon as the nonperiodic queue becomes nonempty, the core attempts to send \nan OUT token in the current frame\ne) \nWrite the second (last) packet for channel 1\nf) \nThe core generates the XFRC interrupt as soon as the last transaction is \ncompleted successfully\ng) \nIn response to the XFRC interrupt, de-allocate the channel for other transfers\nh) \nHandling nonACK responses\nFigure 418. Normal bulk/control OUT/SETUP and bulk/control IN transactions - DMA\nmode\n" }, { "page_number": 1498, "page_indices": { "start_index": 2958253, "end_index": 2958751 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1498 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1498/1757\nRM0090 Rev 21\nFigure 419. Normal bulk/control OUT/SETUP and bulk/control IN transactions - Slave\nmode\nThe channel-specific interrupt service routine for bulk and control OUT/SETUP \ntransactions in Slave mode is shown in the following code samples.\n•\nInterrupt service routine for bulk/control OUT/SETUP and bulk/control IN \ntransactions\na) \nBulk/Control OUT/SETUP\nUnmask (NAK/TXERR/STALL/XFRC)\nif (XFRC)\n{\nReset Error Count\n" }, { "page_number": 1499, "page_indices": { "start_index": 2958751, "end_index": 2959639 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1499 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "RM0090 Rev 21\n1499/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nMask ACK\nDe-allocate Channel\n}\nelse if (STALL)\n{\nTransfer Done = 1\nUnmask CHH\nDisable Channel\n}\nelse if (NAK or TXERR )\n{\nRewind Buffer Pointers\nUnmask CHH\nDisable Channel\nif (TXERR)\n{\nIncrement Error Count\nUnmask ACK\n}\nelse\n{\nReset Error Count\n}\n}\nelse if (CHH)\n{\nMask CHH\nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\nelse\n{\nRe-initialize Channel\n}\n}\nelse if (ACK)\n{\nReset Error Count\nMask ACK\n}\nThe application is expected to write the data packets into the transmit FIFO as and \nwhen the space is available in the transmit FIFO and the Request queue. The \napplication can make use of the NPTXFE interrupt in OTG_HS_GINTSTS to find the \ntransmit FIFO space.\nb) \nBulk/Control IN\nUnmask (TXERR/XFRC/BBERR/STALL/DTERR)\nif (XFRC)\n{\nReset Error Count\nUnmask CHH\nDisable Channel\n" }, { "page_number": 1500, "page_indices": { "start_index": 2959639, "end_index": 2960660 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1500 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1500/1757\nRM0090 Rev 21\nReset Error Count\nMask ACK\n}\nelse if (TXERR or BBERR or STALL)\n{\nUnmask CHH\nDisable Channel\nif (TXERR)\n{\nIncrement Error Count\nUnmask ACK\n}\n}\nelse if (CHH)\n{\nMask CHH\nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\nelse\n{\nRe-initialize Channel\n}\n}\nelse if (ACK)\n{\nReset Error Count\nMask ACK\n}\nelse if (DTERR)\n{\nReset Error Count\n}\nThe application is expected to write the requests as and when the Request queue \nspace is available and until the XFRC interrupt is received.\n•\nBulk and control IN transactions\nA typical bulk or control IN pipelined transaction-level operation is shown in Figure 420. \nSee channel 2 (ch_2). The assumptions are:\n–\nThe application is attempting to receive two maximum-packet-size packets \n(transfer size = 1 024 bytes).\n–\nThe receive FIFO can contain at least one maximum-packet-size packet and two \nstatus words per packet (72 bytes for FS).\n–\nThe nonperiodic request queue depth = 4.\n" }, { "page_number": 1501, "page_indices": { "start_index": 2960660, "end_index": 2960805 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1501 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "RM0090 Rev 21\n1501/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nFigure 420. Bulk/control IN transactions - DMA mode\n" }, { "page_number": 1502, "page_indices": { "start_index": 2960805, "end_index": 2961464 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1502 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1502/1757\nRM0090 Rev 21\nFigure 421. Bulk/control IN transactions - Slave mode\nThe sequence of operations is as follows:\na) \nInitialize channel 2.\nb) \nSet the CHENA bit in HCCHAR2 to write an IN request to the nonperiodic request \nqueue.\nc) \nThe core attempts to send an IN token after completing the current OUT \ntransaction.\nd) \nThe core generates an RXFLVL interrupt as soon as the received packet is written \nto the receive FIFO.\ne) \nIn response to the RXFLVL interrupt, mask the RXFLVL interrupt and read the \nreceived packet status to determine the number of bytes received, then read the \n" }, { "page_number": 1503, "page_indices": { "start_index": 2961464, "end_index": 2964321 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1503 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "RM0090 Rev 21\n1503/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nreceive FIFO accordingly. Following this, unmask the RXFLVL interrupt.\nf) \nThe core generates the RXFLVL interrupt for the transfer completion status entry \nin the receive FIFO.\ng) \nThe application must read and ignore the receive packet status when the receive \npacket status is not an IN data packet (PKTSTS in GRXSTSR ≠0b0010).\nh) \nThe core generates the XFRC interrupt as soon as the receive packet status is \nread.\ni) \nIn response to the XFRC interrupt, disable the channel and stop writing the \nOTG_HS_HCCHAR2 register for further requests. The core writes a channel \ndisable request to the nonperiodic request queue as soon as the \nOTG_HS_HCCHAR2 register is written.\nj) \nThe core generates the RXFLVL interrupt as soon as the halt status is written to \nthe receive FIFO.\nk) \nRead and ignore the receive packet status.\nl) \nThe core generates a CHH interrupt as soon as the halt status is popped from the \nreceive FIFO.\nm) In response to the CHH interrupt, de-allocate the channel for other transfers.\nn) \nHandling nonACK responses\n•\nControl transactions in slave mode\nSetup, Data, and Status stages of a control transfer must be performed as three \nseparate transfers. Setup-, Data- or Status-stage OUT transactions are performed \nsimilarly to the bulk OUT transactions explained previously. Data- or Status-stage IN \ntransactions are performed similarly to the bulk IN transactions explained previously. \nFor all three stages, the application is expected to set the EPTYP field in \nOTG_HS_HCCHAR1 to Control. During the Setup stage, the application is expected to \nset the PID field in OTG_HS_HCTSIZ1 to SETUP.\n•\nInterrupt OUT transactions\nA typical interrupt OUT operation in Slave mode is shown in Figure 422. The \nassumptions are:\n–\nThe application is attempting to send one packet in every frame (up to 1 maximum \npacket size), starting with the odd frame (transfer size = 1 024 bytes)\n–\nThe periodic transmit FIFO can hold one packet (1 KB)\n–\nPeriodic request queue depth = 4\nThe sequence of operations is as follows:\na) \nInitialize and enable channel 1. The application must set the ODDFRM bit in \nOTG_HS_HCCHAR1.\nb) \nWrite the first packet for channel 1. For a high-bandwidth interrupt transfer, the \napplication must write the subsequent packets up to MCNT (maximum number of \npackets to be transmitted in the next frame times) before switching to another \nchannel.\nc) \nAlong with the last word write of each packet, the OTG_HS host writes an entry to \nthe periodic request queue.\nd) \nThe OTG_HS host attempts to send an OUT token in the next (odd) frame.\ne) \nThe OTG_HS host generates an XFRC interrupt as soon as the last packet is \ntransmitted successfully.\nf) \nIn response to the XFRC interrupt, reinitialize the channel for the next transfer.\n" }, { "page_number": 1504, "page_indices": { "start_index": 2964321, "end_index": 2964469 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1504 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1504/1757\nRM0090 Rev 21\nFigure 422. Normal interrupt OUT/IN transactions - DMA mode\n" }, { "page_number": 1505, "page_indices": { "start_index": 2964469, "end_index": 2964828 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1505 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "RM0090 Rev 21\n1505/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nFigure 423. Normal interrupt OUT/IN transactions - Slave mode\n•\nInterrupt service routine for interrupt OUT/IN transactions\na) \nInterrupt OUT\nUnmask (NAK/TXERR/STALL/XFRC/FRMOR)\nif (XFRC)\n{\nReset Error Count\nMask ACK\nDe-allocate Channel\n}\nelse\nif (STALL or FRMOR)\n{\n" }, { "page_number": 1506, "page_indices": { "start_index": 2964828, "end_index": 2965782 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1506 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1506/1757\nRM0090 Rev 21\nMask ACK\nUnmask CHH\nDisable Channel\nif (STALL)\n{\nTransfer Done = 1\n}\n}\nelse\nif (NAK or TXERR)\n{\nRewind Buffer Pointers\nReset Error Count\nMask ACK\nUnmask CHH\nDisable Channel\n}\nelse\nif (CHH)\n{\nMask CHH\nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\nelse\n{\nRe-initialize Channel (in next b_interval - 1 Frame)\n}\n}\nelse\nif (ACK)\n{\nReset Error Count\nMask ACK\n}\nThe application is expected to write the data packets into the transmit FIFO when the \nspace is available in the transmit FIFO and the Request queue up to the count \nspecified in the MCNT field before switching to another channel. The application uses \nthe NPTXFE interrupt in OTG_HS_GINTSTS to find the transmit FIFO space.\nb) \nInterrupt IN\nUnmask (NAK/TXERR/XFRC/BBERR/STALL/FRMOR/DTERR)\nif (XFRC)\n{\nReset Error Count\nMask ACK\nif (OTG_HS_HCTSIZx.PKTCNT == 0)\n{\nDe-allocate Channel\n}\nelse\n{\n" }, { "page_number": 1507, "page_indices": { "start_index": 2965782, "end_index": 2966400 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1507 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "RM0090 Rev 21\n1507/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nTransfer Done = 1\nUnmask CHH\nDisable Channel\n}\n}\nelse\nif (STALL or FRMOR or NAK or DTERR or BBERR)\n{\nMask ACK\nUnmask CHH\nDisable Channel\n \nif (STALL or BBERR)\n{\nReset Error Count\nTransfer Done = 1\n}\nelse\nif (!FRMOR)\n{\nReset Error Count\n}\n}\nelse\nif (TXERR)\n{\nIncrement Error Count\nUnmask ACK\nUnmask CHH\nDisable Channel\n}\nelse\nif (CHH)\n{\nMask CHH\n \nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\n \nelse\n \nRe-initialize Channel (in next b_interval - 1 /Frame)\n}\n}\nelse\nif (ACK)\n{\nReset Error Count\nMask ACK\n" }, { "page_number": 1508, "page_indices": { "start_index": 2966400, "end_index": 2968703 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1508 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1508/1757\nRM0090 Rev 21\n}\nThe application is expected to write the requests for the same channel when the \nRequest queue space is available up to the count specified in the MCNT field before \nswitching to another channel (if any).\n•\nInterrupt IN transactions\nThe assumptions are:\n–\nThe application is attempting to receive one packet (up to 1 maximum packet size) \nin every frame, starting with odd (transfer size = 1 024 bytes).\n–\nThe receive FIFO can hold at least one maximum-packet-size packet and two \nstatus words per packet (1 031 bytes).\n–\nPeriodic request queue depth = 4.\n•\nNormal interrupt IN operation\nThe sequence of operations is as follows:\na) \nInitialize channel 2. The application must set the ODDFRM bit in \nOTG_HS_HCCHAR2.\nb) \nSet the CHENA bit in OTG_HS_HCCHAR2 to write an IN request to the periodic \nrequest queue. For a high-bandwidth interrupt transfer, the application must write \nthe OTG_HS_HCCHAR2 register MCNT (maximum number of expected packets \nin the next frame times) before switching to another channel.\nc) \nThe OTG_HS host writes an IN request to the periodic request queue for each \nOTG_HS_HCCHAR2 register write with the CHENA bit set.\nd) \nThe OTG_HS host attempts to send an IN token in the next (odd) frame.\ne) \nAs soon as the IN packet is received and written to the receive FIFO, the OTG_HS \nhost generates an RXFLVL interrupt.\nf) \nIn response to the RXFLVL interrupt, read the received packet status to determine \nthe number of bytes received, then read the receive FIFO accordingly. The \napplication must mask the RXFLVL interrupt before reading the receive FIFO, and \nunmask after reading the entire packet.\ng) \nThe core generates the RXFLVL interrupt for the transfer completion status entry \nin the receive FIFO. The application must read and ignore the receive packet \nstatus when the receive packet status is not an IN data packet (PKTSTS in \nGRXSTSR ≠0b0010).\nh) \nThe core generates an XFRC interrupt as soon as the receive packet status is \nread.\ni) \nIn response to the XFRC interrupt, read the PKTCNT field in OTG_HS_HCTSIZ2. \nIf the PKTCNT bit in OTG_HS_HCTSIZ2 is not equal to 0, disable the channel \nbefore re-initializing the channel for the next transfer, if any). If PKTCNT bit in \n" }, { "page_number": 1509, "page_indices": { "start_index": 2968703, "end_index": 2970119 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1509 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "RM0090 Rev 21\n1509/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nOTG_HS_HCTSIZ2 = 0, reinitialize the channel for the next transfer. This time, the \napplication must reset the ODDFRM bit in OTG_HS_HCCHAR2.\n•\nIsochronous OUT transactions\nA typical isochronous OUT operation in Slave mode is shown in Figure 424. The \nassumptions are:\n–\nThe application is attempting to send one packet every frame (up to 1 maximum \npacket size), starting with an odd frame. (transfer size = 1 024 bytes).\n–\nThe periodic transmit FIFO can hold one packet (1 KB).\n–\nPeriodic request queue depth = 4.\nThe sequence of operations is as follows:\na) \nInitialize and enable channel 1. The application must set the ODDFRM bit in \nOTG_HS_HCCHAR1.\nb) \nWrite the first packet for channel 1. For a high-bandwidth isochronous transfer, the \napplication must write the subsequent packets up to MCNT (maximum number of \npackets to be transmitted in the next frame times before switching to another \nchannel.\nc) \nAlong with the last word write of each packet, the OTG_HS host writes an entry to \nthe periodic request queue.\nd) \nThe OTG_HS host attempts to send the OUT token in the next frame (odd).\ne) \nThe OTG_HS host generates the XFRC interrupt as soon as the last packet is \ntransmitted successfully.\nf) \nIn response to the XFRC interrupt, reinitialize the channel for the next transfer.\ng) \nHandling nonACK responses\n" }, { "page_number": 1510, "page_indices": { "start_index": 2970119, "end_index": 2970269 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1510 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1510/1757\nRM0090 Rev 21\nFigure 424. Normal isochronous OUT/IN transactions - DMA mode\n" }, { "page_number": 1511, "page_indices": { "start_index": 2970269, "end_index": 2970620 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1511 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "RM0090 Rev 21\n1511/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nFigure 425. Normal isochronous OUT/IN transactions - Slave mode\n•\nInterrupt service routine for isochronous OUT/IN transactions\nCode sample: Isochronous OUT\nUnmask (FRMOR/XFRC)\nif (XFRC)\n{\nDe-allocate Channel\n}\nelse\nif (FRMOR)\n{\nUnmask CHH\nDisable Channel\n}\n" }, { "page_number": 1512, "page_indices": { "start_index": 2970620, "end_index": 2971160 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1512 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1512/1757\nRM0090 Rev 21\nelse\nif (CHH)\n{\nMask CHH\nDe-allocate Channel\n}\nCode sample: Isochronous IN\nUnmask (TXERR/XFRC/FRMOR/BBERR)\nif (XFRC or FRMOR)\n{\nif (XFRC and (OTG_HS_HCTSIZx.PKTCNT == 0))\n{\nReset Error Count\nDe-allocate Channel\n}\nelse\n{\nUnmask CHH\nDisable Channel\n}\n}\nelse\nif (TXERR or BBERR)\n{\nIncrement Error Count\nUnmask CHH\nDisable Channel\n}\nelse\nif (CHH)\n{\nMask CHH\nif (Transfer Done or (Error_count == 3))\n{\nDe-allocate Channel\n}\nelse\n{\nRe-initialize Channel\n}\n}\n" }, { "page_number": 1513, "page_indices": { "start_index": 2971160, "end_index": 2974386 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1513 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "RM0090 Rev 21\n1513/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n \n•\nIsochronous IN transactions\nThe assumptions are:\n–\nThe application is attempting to receive one packet (up to 1 maximum packet size) \nin every frame starting with the next odd frame (transfer size = 1 024 bytes).\n–\nThe receive FIFO can hold at least one maximum-packet-size packet and two \nstatus words per packet (1 031 bytes).\n–\nPeriodic request queue depth = 4.\nThe sequence of operations is as follows:\na) \nInitialize channel 2. The application must set the ODDFRM bit in \nOTG_HS_HCCHAR2.\nb) \nSet the CHENA bit in OTG_HS_HCCHAR2 to write an IN request to the periodic \nrequest queue. For a high-bandwidth isochronous transfer, the application must \nwrite the OTG_HS_HCCHAR2 register MCNT (maximum number of expected \npackets in the next frame times) before switching to another channel.\nc) \nThe OTG_HS host writes an IN request to the periodic request queue for each \nOTG_HS_HCCHAR2 register write with the CHENA bit set.\nd) \nThe OTG_HS host attempts to send an IN token in the next odd frame.\ne) \nAs soon as the IN packet is received and written to the receive FIFO, the OTG_HS \nhost generates an RXFLVL interrupt.\nf) \nIn response to the RXFLVL interrupt, read the received packet status to determine \nthe number of bytes received, then read the receive FIFO accordingly. The \napplication must mask the RXFLVL interrupt before reading the receive FIFO, and \nunmask it after reading the entire packet.\ng) \nThe core generates an RXFLVL interrupt for the transfer completion status entry in \nthe receive FIFO. This time, the application must read and ignore the receive \npacket status when the receive packet status is not an IN data packet (PKTSTS bit \nin OTG_HS_GRXSTSR ≠0b0010).\nh) \nThe core generates an XFRC interrupt as soon as the receive packet status is \nread.\ni) \nIn response to the XFRC interrupt, read the PKTCNT field in OTG_HS_HCTSIZ2. \nIf PKTCNT ≠0 in OTG_HS_HCTSIZ2, disable the channel before re-initializing \nthe channel for the next transfer, if any. If PKTCNT = 0 in OTG_HS_HCTSIZ2, \nreinitialize the channel for the next transfer. This time, the application must reset \nthe ODDFRM bit in OTG_HS_HCCHAR2.\n•\nSelecting the queue depth\nChoose the periodic and nonperiodic request queue depths carefully to match the \nnumber of periodic/nonperiodic endpoints accessed.\nThe nonperiodic request queue depth affects the performance of nonperiodic transfers. \nThe deeper the queue (along with sufficient FIFO size), the more often the core is able \nto pipeline nonperiodic transfers. If the queue size is small, the core is able to put in \nnew requests only when the queue space is freed up.\nThe core’s periodic request queue depth is critical to perform periodic transfers as \nscheduled. Select the periodic queue depth, based on the number of periodic transfers \nscheduled in a micro-frame. In Slave mode, however, the application must also take \ninto account the disable entry that must be put into the queue. So, if there are two \nnonhigh-bandwidth periodic endpoints, the periodic request queue depth must be at \nleast 4. If at least one high-bandwidth endpoint is supported, the queue depth must be \n" }, { "page_number": 1514, "page_indices": { "start_index": 2974386, "end_index": 2977541 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1514 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1514/1757\nRM0090 Rev 21\n8. If the periodic request queue depth is smaller than the periodic transfers scheduled \nin a micro-frame, a frame overrun condition occurs.\n•\nHandling babble conditions\nOTG_HS controller handles two cases of babble: packet babble and port babble. \nPacket babble occurs if the device sends more data than the maximum packet size for \nthe channel. Port babble occurs if the core continues to receive data from the device at \nEOF2 (the end of frame 2, which is very close to SOF).\nWhen OTG_HS controller detects a packet babble, it stops writing data into the Rx \nbuffer and waits for the end of packet (EOP). When it detects an EOP, it flushes already \nwritten data in the Rx buffer and generates a Babble interrupt to the application.\nWhen OTG_HS controller detects a port babble, it flushes the RxFIFO and disables the \nport. The core then generates a Port disabled interrupt (HPRTINT in \nOTG_HS_GINTSTS, PENCHNG in OTG_HS_HPRT). On receiving this interrupt, the \napplication must determine that this is not due to an overcurrent condition (another \ncause of the Port Disabled interrupt) by checking POCA in OTG_HS_HPRT, then \nperform a soft reset. The core does not send any more tokens after it has detected a \nport babble condition.\n•\nBulk and control OUT/SETUP transactions in DMA mode\nThe sequence of operations is as follows:\na) \nInitialize and enable channel 1 as explained in Section : Channel initialization.\nb) \nThe HS_OTG host starts fetching the first packet as soon as the channel is \nenabled. For internal DMA mode, the OTG_HS host uses the programmed DMA \naddress to fetch the packet.\nc) \nAfter fetching the last word of the second (last) packet, the OTG_HS host masks \nchannel 1 internally for further arbitration.\nd) \nThe HS_OTG host generates a CHH interrupt as soon as the last packet is sent.\ne) \nIn response to the CHH interrupt, de-allocate the channel for other transfers.\n•\nNAK and NYET handling with internal DMA\na) \nThe OTG_HS host sends a bulk OUT transaction.\nb) \nThe device responds with NAK or NYET.\nc) \nIf the application has unmasked NAK or NYET, the core generates the \ncorresponding interrupt(s) to the application. The application is not required to \nservice these interrupts, since the core takes care of rewinding the buffer pointers \nand re-initializing the Channel without application intervention.\nd) \nThe core automatically issues a ping token.\ne) \nWhen the device returns an ACK, the core continues with the transfer. Optionally, \nthe application can utilize these interrupts, in which case the NAK or NYET \ninterrupt is masked by the application.\nThe core does not generate a separate interrupt when NAK or NYET is received by the \nhost functionality.\n•\nBulk and control IN transactions in DMA mode\nThe sequence of operations is as follows:\na) \nInitialize and enable the used channel (channel x) as explained in Section : \nChannel initialization.\nb) \nThe OTG_HS host writes an IN request to the request queue as soon as the \nchannel receives the grant from the arbiter (arbitration is performed in a round-\nrobin fashion).\n" }, { "page_number": 1515, "page_indices": { "start_index": 2977541, "end_index": 2980541 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1515 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "RM0090 Rev 21\n1515/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nc) \nThe OTG_HS host starts writing the received data to the system memory as soon \nas the last byte is received with no errors.\nd) \nWhen the last packet is received, the OTG_HS host sets an internal flag to remove \nany extra IN requests from the request queue.\ne) \nThe OTG_HS host flushes the extra requests.\nf) \nThe final request to disable channel x is written to the request queue. At this point, \nchannel 2 is internally masked for further arbitration.\ng) \nThe OTG_HS host generates the CHH interrupt as soon as the disable request \ncomes to the top of the queue.\nh) \nIn response to the CHH interrupt, de-allocate the channel for other transfers.\n•\nInterrupt OUT transactions in DMA mode\na) \nInitialize and enable channel x as explained in Section : Channel initialization.\nb) \nThe OTG_HS host starts fetching the first packet as soon the channel is enabled \nand writes the OUT request along with the last word fetch. In high-bandwidth \ntransfers, the HS_OTG host continues fetching the next packet (up to the value \nspecified in the MC field) before switching to the next channel.\nc) \nThe OTG_HS host attempts to send the OUT token at the beginning of the next \nodd frame/micro-frame.\nd) \nAfter successfully transmitting the packet, the OTG_HS host generates a CHH \ninterrupt.\ne) \nIn response to the CHH interrupt, reinitialize the channel for the next transfer.\n•\nInterrupt IN transactions in DMA mode\nThe sequence of operations (channelx) is as follows:\na) \nInitialize and enable channel x as explained in Section : Channel initialization.\nb) \nThe OTG_HS host writes an IN request to the request queue as soon as the \nchannel x gets the grant from the arbiter (round-robin with fairness). In high-\nbandwidth transfers, the OTG_HS host writes consecutive writes up to MC times.\nc) \nThe OTG_HS host attempts to send an IN token at the beginning of the next (odd) \nframe/micro-frame.\nd) \nAs soon the packet is received and written to the receive FIFO, the OTG_HS host \ngenerates a CHH interrupt.\ne) \nIn response to the CHH interrupt, reinitialize the channel for the next transfer.\n•\nIsochronous OUT transactions in DMA mode\na) \nInitialize and enable channel x as explained in Section : Channel initialization.\nb) \nThe OTG_HS host starts fetching the first packet as soon as the channel is \nenabled, and writes the OUT request along with the last word fetch. In high-\nbandwidth transfers, the OTG_HS host continues fetching the next packet (up to \nthe value specified in the MC field) before switching to the next channel.\nc) \nThe OTG_HS host attempts to send an OUT token at the beginning of the next \n(odd) frame/micro-frame.\nd) \nAfter successfully transmitting the packet, the HS_OTG host generates a CHH \ninterrupt.\ne) \nIn response to the CHH interrupt, reinitialize the channel for the next transfer.\n•\nIsochronous IN transactions in DMA mode\nThe sequence of operations ((channel x) is as follows:\n" }, { "page_number": 1516, "page_indices": { "start_index": 2980541, "end_index": 2983372 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1516 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1516/1757\nRM0090 Rev 21\na) \nInitialize and enable channel x as explained in Section : Channel initialization.\nb) \nThe OTG_HS host writes an IN request to the request queue as soon as the \nchannel x gets the grant from the arbiter (round-robin with fairness). In high-\nbandwidth transfers, the OTG_HS host performs consecutive write operations up \nto MC times.\nc) \nThe OTG_HS host attempts to send an IN token at the beginning of the next (odd) \nframe/micro-frame.\nd) \nAs soon the packet is received and written to the receive FIFO, the OTG_HS host \ngenerates a CHH interrupt.\ne) \nIn response to the CHH interrupt, reinitialize the channel for the next transfer.\n•\nBulk and control OUT/SETUP split transactions in DMA mode\nThe sequence of operations in (channel x) is as follows:\na) \nInitialize and enable channel x for start split as explained in Section : Channel \ninitialization. \nb) \nThe OTG_HS host starts fetching the first packet as soon the channel is enabled \nand writes the OUT request along with the last word fetch.\nc) \nAfter successfully transmitting start split, the OTG_HS host generates the CHH \ninterrupt.\nd) \nIn response to the CHH interrupt, set the COMPLSPLT bit in HCSPLT1 to send the \ncomplete split.\ne) \nAfter successfully transmitting complete split, the OTG_HS host generates the \nCHH interrupt.\nf) \nIn response to the CHH interrupt, de-allocate the channel.\n•\nBulk/Control IN split transactions in DMA mode\nThe sequence of operations (channel x) is as follows:\na) \nInitialize and enable channel x as explained in Section : Channel initialization.\nb) \nThe OTG_HS host writes the start split request to the nonperiodic request after \ngetting the grant from the arbiter. The OTG_HS host masks the channel x \ninternally for the arbitration after writing the request.\nc) \nAs soon as the IN token is transmitted, the OTG_HS host generates the CHH \ninterrupt.\nd) \nIn response to the CHH interrupt, set the COMPLSPLT bit in HCSPLT2 and re-\nenable the channel to send the complete split token. This unmasks channel x for \narbitration.\ne) \nThe OTG_HS host writes the complete split request to the nonperiodic request \nafter receiving the grant from the arbiter.\nf) \nThe OTG_HS host starts writing the packet to the system memory after receiving \nthe packet successfully.\ng) \nAs soon as the received packet is written to the system memory, the OTG_HS \nhost generates a CHH interrupt.\nh) \nIn response to the CHH interrupt, de-allocate the channel.\n•\nInterrupt OUT split transactions in DMA mode\nThe sequence of operations in (channel x) is as follows:\na) \nInitialize and enable channel 1 for start split as explained in Section : Channel \ninitialization. The application must set the ODDFRM bit in HCCHAR1.\nb) \nThe HS_OTG host starts reading the packet.\n" }, { "page_number": 1517, "page_indices": { "start_index": 2983372, "end_index": 2985906 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1517 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.5 Host programming model", 1492 ], [ 4, "Operational model", 1494 ] ], "page_content": "RM0090 Rev 21\n1517/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nc) \nThe HS_OTG host attempts to send the start split transaction.\nd) \nAfter successfully transmitting the start split, the OTG_HS host generates the \nCHH interrupt.\ne) \nIn response to the CHH interrupt, set the COMPLSPLT bit in HCSPLT1 to send the \ncomplete split.\nf) \nAfter successfully completing the complete split transaction, the OTG_HS host \ngenerates the CHH interrupt.\ng) \nIn response to CHH interrupt, de-allocate the channel.\n•\nInterrupt IN split transactions in DMA mode\nThe sequence of operations in (channel x) is as follows:\na) \nInitialize and enable channel x for start split as explained in Section : Channel \ninitialization.\nb) \nThe OTG_HS host writes an IN request to the request queue as soon as channel \nx receives the grant from the arbiter.\nc) \nThe OTG_HS host attempts to send the start split IN token at the beginning of the \nnext odd micro-frame.\nd) \nThe OTG_HS host generates the CHH interrupt after successfully transmitting the \nstart split IN token.\ne) \nIn response to the CHH interrupt, set the COMPLSPLT bit in HCSPLT2 to send the \ncomplete split.\nf) \nAs soon as the packet is received successfully, the OTG_HS host starts writing the \ndata to the system memory.\ng) \nThe OTG_HS host generates the CHH interrupt after transferring the received \ndata to the system memory.\nh) \nIn response to the CHH interrupt, de-allocate or reinitialize the channel for the next \nstart split.\n•\nIsochronous OUT split transactions in DMA mode\nThe sequence of operations (channel x) is as follows:\na) \nInitialize and enable channel x for start split (begin) as explained in Section : \nChannel initialization. The application must set the ODDFRM bit in HCCHAR1. \nProgram the MPS field.\nb) \nThe HS_OTG host starts reading the packet.\nc) \nAfter successfully transmitting the start split (begin), the HS_OTG host generates \nthe CHH interrupt.\nd) \nIn response to the CHH interrupt, reinitialize the registers to send the start split \n(end). \ne) \nAfter successfully transmitting the start split (end), the OTG_HS host generates a \nCHH interrupt.\nf) \nIn response to the CHH interrupt, de-allocate the channel.\n•\nIsochronous IN split transactions in DMA mode\nThe sequence of operations (channel x) is as follows:\na) \nInitialize and enable channel x for start split as explained in Section : Channel \ninitialization.\nb) \nThe OTG_HS host writes an IN request to the request queue as soon as channel \nx receives the grant from the arbiter.\n" }, { "page_number": 1518, "page_indices": { "start_index": 2985906, "end_index": 2987986 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1518 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.6 Device programming model", 1518 ], [ 4, "Endpoint initialization on USB reset", 1518 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1518/1757\nRM0090 Rev 21\nc) \nThe OTG_HS host attempts to send the start split IN token at the beginning of the \nnext odd micro-frame.\nd) \nThe OTG_HS host generates the CHH interrupt after successfully transmitting the \nstart split IN token.\ne) \nIn response to the CHH interrupt, set the COMPLSPLT bit in HCSPLT2 to send the \ncomplete split.\nf) \nAs soon as the packet is received successfully, the OTG_HS host starts writing the \ndata to the system memory.\ng) \nThe OTG_HS host generates the CHH interrupt after transferring the received \ndata to the system memory. In response to the CHH interrupt, de-allocate the \nchannel or reinitialize the channel for the next start split.\n35.13.6 \nDevice programming model\nEndpoint initialization on USB reset\n1.\nSet the NAK bit for all OUT endpoints\n–\nSNAK = 1 in OTG_HS_DOEPCTLx (for all OUT endpoints)\n2. \nUnmask the following interrupt bits\n–\nINEP0 = 1 in OTG_HS_DAINTMSK (control 0 IN endpoint)\n–\nOUTEP0 = 1 in OTG_HS_DAINTMSK (control 0 OUT endpoint)\n–\nSTUP = 1 in DOEPMSK\n–\nXFRC = 1 in DOEPMSK\n–\nXFRC = 1 in DIEPMSK\n–\nTOC = 1 in DIEPMSK\n3. \nSet up the Data FIFO RAM for each of the FIFOs\n–\nProgram the OTG_HS_GRXFSIZ register, to be able to receive control OUT data \nand setup data. If thresholding is not enabled, at a minimum, this must be equal to \n1 max packet size of control endpoint 0 + 2 words (for the status of the control \nOUT data packet) + 10 words (for setup packets).\n–\nProgram the OTG_HS_TX0FSIZ register (depending on the FIFO number \nchosen) to be able to transmit control IN data. At a minimum, this must be equal to \n1 max packet size of control endpoint 0.\n4. \nProgram the following fields in the endpoint-specific registers for control OUT endpoint \n0 to receive a SETUP packet\n–\nSTUPCNT = 3 in OTG_HS_DOEPTSIZ0 (to receive up to 3 back-to-back SETUP \npackets)\n5. \nIn DMA mode, the DOEPDMA0 register should have a valid memory address to store \nany SETUP packets received.\nAt this point, all initialization required to receive SETUP packets is done.\n" }, { "page_number": 1519, "page_indices": { "start_index": 2987986, "end_index": 2990147 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1519 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.6 Device programming model", 1518 ], [ 4, "Endpoint initialization on enumeration completion", 1519 ], [ 4, "Endpoint initialization on SetAddress command", 1519 ], [ 4, "Endpoint initialization on SetConfiguration/SetInterface command", 1519 ] ], "page_content": "RM0090 Rev 21\n1519/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nEndpoint initialization on enumeration completion\n1.\nOn the Enumeration Done interrupt (ENUMDNE in OTG_HS_GINTSTS), read the \nOTG_HS_DSTS register to determine the enumeration speed.\n2. \nProgram the MPSIZ field in OTG_HS_DIEPCTL0 to set the maximum packet size. This \nstep configures control endpoint 0. The maximum packet size for a control endpoint \ndepends on the enumeration speed.\n3. \nIn DMA mode, program the DOEPCTL0 register to enable control OUT endpoint 0, to \nreceive a SETUP packet.\n–\nEPENA bit in DOEPCTL0 = 1\nAt this point, the device is ready to receive SOF packets and is configured to perform control \ntransfers on control endpoint 0.\nEndpoint initialization on SetAddress command\nThis section describes what the application must do when it receives a SetAddress \ncommand in a SETUP packet.\n1.\nProgram the OTG_HS_DCFG register with the device address received in the \nSetAddress command\n1.\nProgram the core to send out a status IN packet\nEndpoint initialization on SetConfiguration/SetInterface command\nThis section describes what the application must do when it receives a SetConfiguration or \nSetInterface command in a SETUP packet.\n1.\nWhen a SetConfiguration command is received, the application must program the \nendpoint registers to configure them with the characteristics of the valid endpoints in \nthe new configuration.\n2. \nWhen a SetInterface command is received, the application must program the endpoint \nregisters of the endpoints affected by this command.\n3. \nSome endpoints that were active in the prior configuration or alternate setting are not \nvalid in the new configuration or alternate setting. These invalid endpoints must be \ndeactivated.\n4. \nUnmask the interrupt for each active endpoint and mask the interrupts for all inactive \nendpoints in the OTG_HS_DAINTMSK register.\n5. \nSet up the Data FIFO RAM for each FIFO.\n6. \nAfter all required endpoints are configured; the application must program the core to \nsend a status IN packet.\nAt this point, the device core is configured to receive and transmit any type of data packet.\n" }, { "page_number": 1520, "page_indices": { "start_index": 2990147, "end_index": 2992365 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1520 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.6 Device programming model", 1518 ], [ 4, "Endpoint activation", 1520 ], [ 4, "Endpoint deactivation", 1520 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "SETUP and OUT data transfers", 1520 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1520/1757\nRM0090 Rev 21\nEndpoint activation\nThis section describes the steps required to activate a device endpoint or to configure an \nexisting device endpoint to a new type.\n1.\nProgram the characteristics of the required endpoint into the following fields of the \nOTG_HS_DIEPCTLx register (for IN or bidirectional endpoints) or the \nOTG_HS_DOEPCTLx register (for OUT or bidirectional endpoints).\n–\nMaximum packet size\n–\nUSB active endpoint = 1\n–\nEndpoint start data toggle (for interrupt and bulk endpoints)\n–\nEndpoint type\n–\nTxFIFO number\n2. \nOnce the endpoint is activated, the core starts decoding the tokens addressed to that \nendpoint and sends out a valid handshake for each valid token received for the \nendpoint.\nEndpoint deactivation\nThis section describes the steps required to deactivate an existing endpoint.\n1.\nIn the endpoint to be deactivated, clear the USB active endpoint bit in the \nOTG_HS_DIEPCTLx register (for IN or bidirectional endpoints) or the \nOTG_HS_DOEPCTLx register (for OUT or bidirectional endpoints).\n2. \nOnce the endpoint is deactivated, the core ignores tokens addressed to that endpoint, \nwhich results in a timeout on the USB.\nNote:\nThe application must meet the following conditions to set up the device core to handle \ntraffic:\nNPTXFEM and RXFLVLM in GINTMSK must be cleared.\n35.13.7 \nOperational model\nSETUP and OUT data transfers\nThis section describes the internal data flow and application-level operations during data \nOUT transfers and SETUP transactions.\n•\nPacket read\nThis section describes how to read packets (OUT data and SETUP packets) from the \nreceive FIFO in Slave mode.\n1.\nOn catching an RXFLVL interrupt (OTG_HS_GINTSTS register), the application must \nread the Receive status pop register (OTG_HS_GRXSTSP).\n2. \nThe application can mask the RXFLVL interrupt (in OTG_HS_GINTSTS) by writing to \nRXFLVL = 0 (in GINTMSK), until it has read the packet from the receive FIFO.\n3. \nIf the received packet’s byte count is not 0, the byte count amount of data is popped \nfrom the receive Data FIFO and stored in memory. If the received packet byte count is \n0, no data is popped from the receive data FIFO.\n" }, { "page_number": 1521, "page_indices": { "start_index": 2992365, "end_index": 2994236 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1521 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "SETUP and OUT data transfers", 1520 ] ], "page_content": "RM0090 Rev 21\n1521/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n4. \nThe receive FIFO packet status readout indicates one of the following:\na) \nGlobal OUT NAK pattern:\nPKTSTS = Global OUT NAK, BCNT = 0x000, EPNUM = Don’t Care (0x0), \nDPID = Don’t Care (0b00).\nThese data indicate that the global OUT NAK bit has taken effect.\nb) \nSETUP packet pattern:\nPKTSTS = SETUP, BCNT = 0x008, EPNUM = Control EP Num, DPID = D0. \nThese data indicate that a SETUP packet for the specified endpoint is now \navailable for reading from the receive FIFO.\nc) \nSetup stage done pattern:\nPKTSTS = Setup Stage Done, BCNT = 0x0, EPNUM = Control EP Num, \nDPID = Don’t Care (0b00).\nThese data indicate that the Setup stage for the specified endpoint has completed \nand the Data stage has started. After this entry is popped from the receive FIFO, \nthe core asserts a Setup interrupt on the specified control OUT endpoint.\nd) \nData OUT packet pattern:\nPKTSTS = DataOUT, BCNT = size of the received data OUT packet \n(0 ≤BCNT ≤1 024), EPNUM = EPNUM on which the packet was received, \nDPID = Actual Data PID.\ne) \nData transfer completed pattern:\nPKTSTS = Data OUT Transfer Done, BCNT = 0x0, EPNUM = OUT EP Num \non which the data transfer is complete, DPID = Don’t Care (0b00).\nThese data indicate that an OUT data transfer for the specified OUT endpoint has \ncompleted. After this entry is popped from the receive FIFO, the core asserts a \nTransfer Completed interrupt on the specified OUT endpoint.\n5. \nAfter the data payload is popped from the receive FIFO, the RXFLVL interrupt \n(OTG_HS_GINTSTS) must be unmasked.\n6. \nSteps 1–5 are repeated every time the application detects assertion of the interrupt line \ndue to RXFLVL in OTG_HS_GINTSTS. Reading an empty receive FIFO can result in \nundefined core behavior.\nFigure 426 provides a flowchart of the above procedure.\n" }, { "page_number": 1522, "page_indices": { "start_index": 2994236, "end_index": 2996205 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1522 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "SETUP and OUT data transfers", 1520 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1522/1757\nRM0090 Rev 21\nFigure 426. Receive FIFO packet read in slave mode\n•\nSETUP transactions\nThis section describes how the core handles SETUP packets and the application’s \nsequence for handling SETUP transactions.\n•\nApplication requirements\n1.\nTo receive a SETUP packet, the STUPCNT field (OTG_HS_DOEPTSIZx) in a control \nOUT endpoint must be programmed to a nonzero value. When the application \nprograms the STUPCNT field to a nonzero value, the core receives SETUP packets \nand writes them to the receive FIFO, irrespective of the NAK status and EPENA bit \nsetting in OTG_HS_DOEPCTLx. The STUPCNT field is decremented every time the \ncontrol endpoint receives a SETUP packet. If the STUPCNT field is not programmed to \na proper value before receiving a SETUP packet, the core still receives the SETUP \npacket and decrements the STUPCNT field, but the application may not be able to \ndetermine the correct number of SETUP packets received in the Setup stage of a \ncontrol transfer.\n–\nSTUPCNT = 3 in OTG_HS_DOEPTSIZx\n2. \nThe application must always allocate some extra space in the Receive data FIFO, to be \nable to receive up to three SETUP packets on a control endpoint.\n–\nThe space to be reserved is 10 words. Three words are required for the first \nSETUP packet, 1 word is required for the Setup stage done word and 6 words are \nrequired to store two extra SETUP packets among all control endpoints.\n–\n3 words per SETUP packet are required to store 8 bytes of SETUP data and 4 \nbytes of SETUP status (Setup packet pattern). The core reserves this space in the \nreceive data.\n–\nFIFO to write SETUP data only, and never uses this space for data packets.\nMSv65221V1\nrd_data = rd_reg(OTG_HS_GRXSTSP);\nmem[0:dword_cnt-1] = \nrd_rxfifo(rd_data.EPNUM,\ndword_cnt)\nrd_data.BCNT = 0\nWait until RXFLVL in OTG_HS_GINTSTSG\ndword_cnt =\nBCNT[11:2] +\n(BCNT[1]| BCNT[1])\nrcv_out_pkt()\nPacket \nstore in \nmemory\nN\nY\n" }, { "page_number": 1523, "page_indices": { "start_index": 2996205, "end_index": 2998187 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1523 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "SETUP and OUT data transfers", 1520 ] ], "page_content": "RM0090 Rev 21\n1523/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n3. \nThe application must read the 2 words of the SETUP packet from the receive FIFO. \n4. \nThe application must read and discard the Setup stage done word from the receive \nFIFO.\n•\nInternal data flow\n5. \nWhen a SETUP packet is received, the core writes the received data to the receive \nFIFO, without checking for available space in the receive FIFO and irrespective of the \nendpoint’s NAK and STALL bit settings.\n–\nThe core internally sets the IN NAK and OUT NAK bits for the control IN/OUT \nendpoints on which the SETUP packet was received.\n6. \nFor every SETUP packet received on the USB, 3 words of data are written to the \nreceive FIFO, and the STUPCNT field is decremented by 1.\n–\nThe first word contains control information used internally by the core\n–\nThe second word contains the first 4 bytes of the SETUP command\n–\nThe third word contains the last 4 bytes of the SETUP command\n7. \nWhen the Setup stage changes to a Data IN/OUT stage, the core writes an entry \n(Setup stage done word) to the receive FIFO, indicating the completion of the Setup \nstage.\n8. \nOn the AHB side, SETUP packets are emptied by the application.\n9. \nWhen the application pops the Setup stage done word from the receive FIFO, the core \ninterrupts the application with an STUP interrupt (OTG_HS_DOEPINTx), indicating it \ncan process the received SETUP packet.\n–\nThe core clears the endpoint enable bit for control OUT endpoints.\n•\nApplication programming sequence\n1.\nProgram the OTG_HS_DOEPTSIZx register.\n–\nSTUPCNT = 3\n2. \nWait for the RXFLVL interrupt (OTG_HS_GINTSTS) and empty the data packets from \nthe receive FIFO.\n3. \nAssertion of the STUP interrupt (OTG_HS_DOEPINTx) marks a successful completion \nof the SETUP Data Transfer.\n–\nOn this interrupt, the application must read the OTG_HS_DOEPTSIZx register to \ndetermine the number of SETUP packets received and process the last received \nSETUP packet.\n" }, { "page_number": 1524, "page_indices": { "start_index": 2998187, "end_index": 2999920 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1524 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "SETUP and OUT data transfers", 1520 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1524/1757\nRM0090 Rev 21\nFigure 427. Processing a SETUP packet\n•\nHandling more than three back-to-back SETUP packets\nPer the USB 2.0 specification, normally, during a SETUP packet error, a host does not send \nmore than three back-to-back SETUP packets to the same endpoint. However, the USB 2.0 \nspecification does not limit the number of back-to-back SETUP packets a host can send to \nthe same endpoint. When this condition occurs, the OTG_HS controller generates an \ninterrupt (B2BSTUP in OTG_HS_DOEPINTx).\n•\nSetting the global OUT NAK\nInternal data flow:\n1.\nWhen the application sets the Global OUT NAK (SGONAK bit in OTG_HS_DCTL), the \ncore stops writing data, except SETUP packets, to the receive FIFO. Irrespective of the \nspace availability in the receive FIFO, nonisochronous OUT tokens receive a NAK \nhandshake response, and the core ignores isochronous OUT data packets\n2. \nThe core writes the Global OUT NAK pattern to the receive FIFO. The application must \nreserve enough receive FIFO space to write this data pattern.\n3. \nWhen the application pops the Global OUT NAK pattern word from the receive FIFO, \nthe core sets the GONAKEFF interrupt (OTG_HS_GINTSTS).\n4. \nOnce the application detects this interrupt, it can assume that the core is in Global OUT \nNAK mode. The application can clear this interrupt by clearing the SGONAK bit in \nOTG_HS_DCTL.\nMSv65222V1\nWait for STUP in OTG_HS_DOEPINTx\nrem_supcnt =\nrd_reg(DOEPTSIZx))\nsetup_cmd[31:0] = mem[4 – 2 * rem_supcnt]\nsetup_cmd[63:32] = mem[5 – 2* rem_supcnt]\nctrl-rd/wr/2 stage\nFind setup cmd type\nSetup_np_in_pkt\nStatus IN phase\nrcv_out_pkt\nData OUT phase\nSetup_np_in_pkt\nData IN phase\nWrite\nRead\n2-stage\n" }, { "page_number": 1525, "page_indices": { "start_index": 2999920, "end_index": 3002099 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1525 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "SETUP and OUT data transfers", 1520 ] ], "page_content": "RM0090 Rev 21\n1525/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nApplication programming sequence:\n1.\nTo stop receiving any kind of data in the receive FIFO, the application must set the \nGlobal OUT NAK bit by programming the following field:\n–\nSGONAK = 1 in OTG_HS_DCTL\n2. \nWait for the assertion of the GONAKEFF interrupt in OTG_HS_GINTSTS. When \nasserted, this interrupt indicates that the core has stopped receiving any type of data \nexcept SETUP packets.\n3. \nThe application can receive valid OUT packets after it has set SGONAK in \nOTG_HS_DCTL and before the core asserts the GONAKEFF interrupt \n(OTG_HS_GINTSTS).\n4. \nThe application can temporarily mask this interrupt by writing to the GINAKEFFM bit in \nGINTMSK.\n–\nGINAKEFFM = 0 in GINTMSK\n5. \nWhenever the application is ready to exit the Global OUT NAK mode, it must clear the \nSGONAK bit in OTG_HS_DCTL. This also clears the GONAKEFF interrupt \n(OTG_HS_GINTSTS).\n–\nOTG_HS_DCTL = 1 in CGONAK\n6. \nIf the application has masked this interrupt earlier, it must be unmasked as follows:\n–\nGINAKEFFM = 1 in GINTMSK\n•\nDisabling an OUT endpoint\nThe application must use this sequence to disable an OUT endpoint that it has enabled.\nApplication programming sequence:\n1.\nBefore disabling any OUT endpoint, the application must enable Global OUT NAK \nmode in the core.\n–\nSGONAK = 1 in OTG_HS_DCTL\n2. \nWait for the GONAKEFF interrupt (OTG_HS_GINTSTS)\n3. \nDisable the required OUT endpoint by programming the following fields:\n–\nEPDIS = 1 in OTG_HS_DOEPCTLx\n–\nSNAK = 1 in OTG_HS_DOEPCTLx\n4. \nWait for the EPDISD interrupt (OTG_HS_DOEPINTx), which indicates that the OUT \nendpoint is completely disabled. When the EPDISD interrupt is asserted, the core also \nclears the following bits:\n–\nEPDIS = 0 in OTG_HS_DOEPCTLx\n–\nEPENA = 0 in OTG_HS_DOEPCTLx\n5. \nThe application must clear the Global OUT NAK bit to start receiving data from other \nnondisabled OUT endpoints.\n–\nSGONAK = 0 in OTG_HS_DCTL\n•\nTransfer Stop Programming for OUT endpoints\nThe application must use the following programing sequence to stop any transfers (because \nof an interrupt from the host, typically a reset).\nSequence of operations:\n" }, { "page_number": 1526, "page_indices": { "start_index": 3002099, "end_index": 3004888 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1526 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "SETUP and OUT data transfers", 1520 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1526/1757\nRM0090 Rev 21\n1.\nEnable all OUT endpoints by setting\n–\nEPENA = 1 in all OTG_HS_DOEPCTLx registers.\n2. \nFlush the RxFIFO as follows\n–\nPoll OTG_HS_GRSTCTL.AHBIDL until it is 1. This indicates that AHB master is \nidle.\n–\nPerform read modify write operation on OTG_HS_GRSTCTL.RXFFLSH =1\n–\nPoll OTG_HS_GRSTCTL.RXFFLSH until it is 0, but also using a timeout of less \nthan 10 milli-seconds (corresponds to minimum reset signaling duration). If 0 is \nseen before the timeout, then the RxFIFO flush is successful. If at the moment the \ntimeout occurs, there is still a 1, (this may be due to a packet on EP0 coming from \nthe host) then go back (once only) to the previous step (“Perform read modify write \noperation”).\n3. \nBefore disabling any OUT endpoint, the application must enable Global OUT NAK \nmode in the core, according to the instructions in “Setting the global OUT NAK on \npage 1524”. This ensures that data in the RxFIFO is sent to the application \nsuccessfully. Set SGONAK = 1 in OTG_HS_DCTL\n4. \nWait for the GONAKEFF interrupt (OTG_HS_GINTSTS)\n5. \nDisable all active OUT endpoints by programming the following register bits:\n–\nEPDIS = 1 in registers OTG_HS_DOEPCTLx\n–\nSNAK = 1 in registers OTG_HS_DOEPCTLx\n6. \nWait for the EPDIS interrupt in OTG_HS_DOEPINTx for each OUT endpoint \nprogrammed in the previous step. The EPDIS interrupt in OTG_HS_DOEPINTx \nindicates that the corresponding OUT endpoint is completely disabled. When the \nEPDIS interrupt is asserted, the following bits are cleared:\n–\nEPENA = 0 in registers OTG_HS_DOEPCTLx\n–\nEPDIS = 0 in registers OTG_HS_DOEPCTLx\n–\nSNAK = 0 in registers OTG_HS_DOEPCTLx\n•\nGeneric non-isochronous OUT data transfers\nThis section describes a regular nonisochronous OUT data transfer (control, bulk, or \ninterrupt).\nApplication requirements:\n1.\nBefore setting up an OUT transfer, the application must allocate a buffer in the memory \nto accommodate all data to be received as part of the OUT transfer.\n2. \nFor OUT transfers, the transfer size field in the endpoint’s transfer size register must be \na multiple of the maximum packet size of the endpoint, adjusted to the word boundary.\n–\ntransfer size[EPNUM] = n × (MPSIZ[EPNUM] + 4 – (MPSIZ[EPNUM] mod 4))\n–\npacket count[EPNUM] = n\n–\nn > 0\n3. \nOn any OUT endpoint interrupt, the application must read the endpoint’s transfer size \nregister to calculate the size of the payload in the memory. The received payload size \ncan be less than the programmed transfer size.\n–\nPayload size in memory = application programmed initial transfer size – core \nupdated final transfer size\n–\nNumber of USB packets in which this payload was received = application \nprogrammed initial packet count – core updated final packet count\n" }, { "page_number": 1527, "page_indices": { "start_index": 3004888, "end_index": 3007459 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1527 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "SETUP and OUT data transfers", 1520 ] ], "page_content": "RM0090 Rev 21\n1527/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nInternal data flow:\n1.\nThe application must set the transfer size and packet count fields in the endpoint-\nspecific registers, clear the NAK bit, and enable the endpoint to receive the data.\n2. \nOnce the NAK bit is cleared, the core starts receiving data and writes it to the receive \nFIFO, as long as there is space in the receive FIFO. For every data packet received on \nthe USB, the data packet and its status are written to the receive FIFO. Every packet \n(maximum packet size or short packet) written to the receive FIFO decrements the \npacket count field for that endpoint by 1.\n–\nOUT data packets received with bad data CRC are flushed from the receive FIFO \nautomatically.\n–\nAfter sending an ACK for the packet on the USB, the core discards \nnonisochronous OUT data packets that the host, which cannot detect the ACK, re-\nsends. The application does not detect multiple back-to-back data OUT packets \non the same endpoint with the same data PID. In this case the packet count is not \ndecremented.\n–\nIf there is no space in the receive FIFO, isochronous or nonisochronous data \npackets are ignored and not written to the receive FIFO. Additionally, \nnonisochronous OUT tokens receive a NAK handshake reply.\n–\nIn all the above three cases, the packet count is not decremented because no data \nare written to the receive FIFO.\n3. \nWhen the packet count becomes 0 or when a short packet is received on the endpoint, \nthe NAK bit for that endpoint is set. Once the NAK bit is set, the isochronous or \nnonisochronous data packets are ignored and not written to the receive FIFO, and \nnonisochronous OUT tokens receive a NAK handshake reply.\n4. \nAfter the data are written to the receive FIFO, the application reads the data from the \nreceive FIFO and writes it to external memory, one packet at a time per endpoint.\n5. \nAt the end of every packet write on the AHB to external memory, the transfer size for \nthe endpoint is decremented by the size of the written packet.\n6. \nThe OUT data transfer completed pattern for an OUT endpoint is written to the receive \nFIFO on one of the following conditions:\n–\nThe transfer size is 0 and the packet count is 0\n–\nThe last OUT data packet written to the receive FIFO is a short packet\n(0 ≤packet size < maximum packet size)\n7. \nWhen either the application pops this entry (OUT data transfer completed), a transfer \ncompleted interrupt is generated for the endpoint and the endpoint enable is cleared.\nApplication programming sequence:\n" }, { "page_number": 1528, "page_indices": { "start_index": 3007459, "end_index": 3009846 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1528 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "SETUP and OUT data transfers", 1520 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1528/1757\nRM0090 Rev 21\n1.\nProgram the OTG_HS_DOEPTSIZx register for the transfer size and the \ncorresponding packet count.\n2. \nProgram the OTG_HS_DOEPCTLx register with the endpoint characteristics, and set \nthe EPENA and CNAK bits.\n–\nEPENA = 1 in OTG_HS_DOEPCTLx\n–\nCNAK = 1 in OTG_HS_DOEPCTLx\n3. \nWait for the RXFLVL interrupt (in OTG_HS_GINTSTS) and empty the data packets \nfrom the receive FIFO.\n–\nThis step can be repeated many times, depending on the transfer size.\n4. \nAsserting the XFRC interrupt (OTG_HS_DOEPINTx) marks a successful completion of \nthe nonisochronous OUT data transfer.\n5. \nRead the OTG_HS_DOEPTSIZx register to determine the size of the received data \npayload.\n•\nGeneric isochronous OUT data transfer\nThis section describes a regular isochronous OUT data transfer.\nApplication requirements:\n1.\nAll the application requirements for nonisochronous OUT data transfers also apply to \nisochronous OUT data transfers.\n2. \nFor isochronous OUT data transfers, the transfer size and packet count fields must \nalways be set to the number of maximum-packet-size packets that can be received in a \nsingle frame and no more. Isochronous OUT data transfers cannot span more than 1 \nframe.\n3. \nThe application must read all isochronous OUT data packets from the receive FIFO \n(data and status) before the end of the periodic frame (EOPF interrupt in \nOTG_HS_GINTSTS).\n4. \nTo receive data in the following frame, an isochronous OUT endpoint must be enabled \nafter the EOPF (OTG_HS_GINTSTS) and before the SOF (OTG_HS_GINTSTS).\nInternal data flow:\n1.\nThe internal data flow for isochronous OUT endpoints is the same as that for \nnonisochronous OUT endpoints, but for a few differences.\n2. \nWhen an isochronous OUT endpoint is enabled by setting the Endpoint Enable and \nclearing the NAK bits, the Even/Odd frame bit must also be set appropriately. The core \nreceives data on an isochronous OUT endpoint in a particular frame only if the \nfollowing condition is met:\n–\nEONUM (in OTG_HS_DOEPCTLx) = SOFFN[0] (in OTG_HS_DSTS)\n3. \nWhen the application completely reads an isochronous OUT data packet (data and \nstatus) from the receive FIFO, the core updates the RXDPID field in \nOTG_HS_DOEPTSIZx with the data PID of the last isochronous OUT data packet read \nfrom the receive FIFO.\nApplication programming sequence:\n" }, { "page_number": 1529, "page_indices": { "start_index": 3009846, "end_index": 3012799 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1529 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "SETUP and OUT data transfers", 1520 ] ], "page_content": "RM0090 Rev 21\n1529/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n1.\nProgram the OTG_HS_DOEPTSIZx register for the transfer size and the \ncorresponding packet count\n2. \nProgram the OTG_HS_DOEPCTLx register with the endpoint characteristics and set \nthe Endpoint Enable, ClearNAK, and Even/Odd frame bits.\n–\nEPENA = 1\n–\nCNAK = 1\n–\nEONUM = (0: Even/1: Odd)\n3. \nIn Slave mode, wait for the RXFLVL interrupt (in OTG_HS_GINTSTS) and empty the \ndata packets from the receive FIFO\n–\nThis step can be repeated many times, depending on the transfer size.\n4. \nThe assertion of the XFRC interrupt (in OTG_HS_DOEPINTx) marks the completion of \nthe isochronous OUT data transfer. This interrupt does not necessarily mean that the \ndata in memory are good.\n5. \nThis interrupt cannot always be detected for isochronous OUT transfers. Instead, the \napplication can detect the IISOOXFRM interrupt in OTG_HS_GINTSTS.\n6. \nRead the OTG_HS_DOEPTSIZx register to determine the size of the received transfer \nand to determine the validity of the data received in the frame. The application must \ntreat the data received in memory as valid only if one of the following conditions is met:\n–\nRXDPID = D0 (in OTG_HS_DOEPTSIZx) and the number of USB packets in \nwhich this payload was received = 1\n–\nRXDPID = D1 (in OTG_HS_DOEPTSIZx) and the number of USB packets in \nwhich this payload was received = 2\n–\nRXDPID = D2 (in OTG_HS_DOEPTSIZx) and the number of USB packets in \nwhich this payload was received = 3\nThe number of USB packets in which this payload was received =\nApplication programmed initial packet count – Core updated final packet count\nThe application can discard invalid data packets.\n•\nIncomplete isochronous OUT data transfers\nThis section describes the application programming sequence when isochronous OUT data \npackets are dropped inside the core.\nInternal data flow:\n1.\nFor isochronous OUT endpoints, the XFRC interrupt (in OTG_HS_DOEPINTx) may not \nalways be asserted. If the core drops isochronous OUT data packets, the application \ncould fail to detect the XFRC interrupt (OTG_HS_DOEPINTx) under the following \ncircumstances:\n–\nWhen the receive FIFO cannot accommodate the complete ISO OUT data packet, \nthe core drops the received ISO OUT data\n–\nWhen the isochronous OUT data packet is received with CRC errors\n–\nWhen the isochronous OUT token received by the core is corrupted\n–\nWhen the application is very slow in reading the data from the receive FIFO\n2. \nWhen the core detects an end of periodic frame before transfer completion to all \nisochronous OUT endpoints, it asserts the incomplete Isochronous OUT data interrupt \n(IISOOXFRM in OTG_HS_GINTSTS), indicating that an XFRC interrupt (in \nOTG_HS_DOEPINTx) is not asserted on at least one of the isochronous OUT \nendpoints. At this point, the endpoint with the incomplete transfer remains enabled, but \nno active transfers remain in progress on this endpoint on the USB.\n" }, { "page_number": 1530, "page_indices": { "start_index": 3012799, "end_index": 3015633 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1530 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "Examples", 1530 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1530/1757\nRM0090 Rev 21\nApplication programming sequence:\n1.\nAsserting the IISOOXFRM interrupt (OTG_HS_GINTSTS) indicates that in the current \nframe, at least one isochronous OUT endpoint has an incomplete transfer.\n2. \nIf this occurs because isochronous OUT data is not completely emptied from the \nendpoint, the application must ensure that the application empties all isochronous OUT \ndata (data and status) from the receive FIFO before proceeding.\n–\nWhen all data are emptied from the receive FIFO, the application can detect the \nXFRC interrupt (OTG_HS_DOEPINTx). In this case, the application must re-\nenable the endpoint to receive isochronous OUT data in the next frame.\n3. \nWhen it receives an IISOOXFRM interrupt (in OTG_HS_GINTSTS), the application \nmust read the control registers of all isochronous OUT endpoints \n(OTG_HS_DOEPCTLx) to determine which endpoints had an incomplete transfer in \nthe current micro-frame. An endpoint transfer is incomplete if both the following \nconditions are met:\n–\nEONUM bit (in OTG_HS_DOEPCTLx) = SOFFN[0] (in OTG_HS_DSTS)\n–\nEPENA = 1 (in OTG_HS_DOEPCTLx)\n4. \nThe previous step must be performed before the SOF interrupt (in \nOTG_HS_GINTSTS) is detected, to ensure that the current frame number is not \nchanged.\n5. \nFor isochronous OUT endpoints with incomplete transfers, the application must discard \nthe data in the memory and disable the endpoint by setting the EPDIS bit in \nOTG_HS_DOEPCTLx.\n6. \nWait for the EPDIS interrupt (in OTG_HS_DOEPINTx) and enable the endpoint to \nreceive new data in the next frame.\n–\nBecause the core can take some time to disable the endpoint, the application may \nnot be able to receive the data in the next frame after receiving bad isochronous \ndata.\n•\nStalling a nonisochronous OUT endpoint\nThis section describes how the application can stall a nonisochronous endpoint.\n1.\nPut the core in the Global OUT NAK mode.\n2. \nDisable the required endpoint\n–\nWhen disabling the endpoint, instead of setting the SNAK bit in \nOTG_HS_DOEPCTL, set STALL = 1 (in OTG_HS_DOEPCTL).\nThe STALL bit always takes precedence over the NAK bit.\n3. \nWhen the application is ready to end the STALL handshake for the endpoint, the \nSTALL bit (in OTG_HS_DOEPCTLx) must be cleared.\n4. \nIf the application is setting or clearing a STALL for an endpoint due to a \nSetFeature.Endpoint Halt or ClearFeature.Endpoint Halt command, the STALL bit must \nbe set or cleared before the application sets up the Status stage transfer on the control \nendpoint.\nExamples\nThis section describes and depicts some fundamental transfer types and scenarios.\n•\nSlave mode bulk OUT transaction\nFigure 428 depicts the reception of a single Bulk OUT Data packet from the USB to the AHB \nand describes the events involved in the process.\n" }, { "page_number": 1531, "page_indices": { "start_index": 3015633, "end_index": 3017331 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1531 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "IN data transfers", 1531 ] ], "page_content": "RM0090 Rev 21\n1531/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nFigure 428. Slave mode bulk OUT transaction\nAfter a SetConfiguration/SetInterface command, the application initializes all OUT endpoints \nby setting CNAK = 1 and EPENA = 1 (in OTG_HS_DOEPCTLx), and setting a suitable \nXFRSIZ and PKTCNT in the OTG_HS_DOEPTSIZx register.\n1.\nHost attempts to send data (OUT token) to an endpoint.\n2. \nWhen the core receives the OUT token on the USB, it stores the packet in the RxFIFO \nbecause space is available there.\n3. \nAfter writing the complete packet in the RxFIFO, the core then asserts the RXFLVL \ninterrupt (in OTG_HS_GINTSTS).\n4. \nOn receiving the PKTCNT number of USB packets, the core internally sets the NAK bit \nfor this endpoint to prevent it from receiving any more packets.\n5. \nThe application processes the interrupt and reads the data from the RxFIFO.\n6. \nWhen the application has read all the data (equivalent to XFRSIZ), the core generates \nan XFRC interrupt (in OTG_HS_DOEPINTx).\n7. \nThe application processes the interrupt and uses the setting of the XFRC interrupt bit \n(in OTG_HS_DOEPINTx) to determine that the intended transfer is complete.\nIN data transfers\n•\nPacket write\nThis section describes how the application writes data packets to the endpoint FIFO in Slave \nmode when dedicated transmit FIFOs are enabled.\ninit_out_ep\n Host\nDevice\nUSB\nOUT\nACK\nRXFLVL intr\n i\nwr_reg (DOEPTSIZx)\nwr_reg(DOEPCTLx)\n512 bytes\nOUT\nNAK\nxact_1\nApplication\nXFRC \nintr\nDOEPCTLx.NAK=1\nPKTCNT 0\nXFRSIZ = 0\nr\n \n \nidle until intr\nrcv_out_pkt()\nidle until intr\nOn new xfer\nor RxFIFO\nnot empty\n1\n2\n3\n4\n5\n6\n7\n8\nXFRSIZ = 512 bytes\nPKTCNT = 1\nEPENA = 1\nCNAK = 1\nai15679\n" }, { "page_number": 1532, "page_indices": { "start_index": 3017331, "end_index": 3019558 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1532 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "IN data transfers", 1531 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1532/1757\nRM0090 Rev 21\n1.\nThe application can either choose the polling or the interrupt mode.\n–\nIn polling mode, the application monitors the status of the endpoint transmit data \nFIFO by reading the OTG_HS_DTXFSTSx register, to determine if there is \nenough space in the data FIFO.\n–\nIn interrupt mode, the application waits for the TXFE interrupt (in \nOTG_HS_DIEPINTx) and then reads the OTG_HS_DTXFSTSx register, to \ndetermine if there is enough space in the data FIFO.\n–\nTo write a single nonzero length data packet, there must be space to write the \nentire packet in the data FIFO.\n–\nTo write zero length packet, the application must not look at the FIFO space.\n2. \nUsing one of the above mentioned methods, when the application determines that \nthere is enough space to write a transmit packet, the application must first write into the \nendpoint control register, before writing the data into the data FIFO. Typically, the \napplication, must do a read modify write on the OTG_HS_DIEPCTLx register to avoid \nmodifying the contents of the register, except for setting the Endpoint Enable bit.\nThe application can write multiple packets for the same endpoint into the transmit FIFO, if \nspace is available. For periodic IN endpoints, the application must write packets only for one \nmicro-frame. It can write packets for the next periodic transaction only after getting transfer \ncomplete for the previous transaction.\n•\nSetting IN endpoint NAK\nInternal data flow:\n1.\nWhen the application sets the IN NAK for a particular endpoint, the core stops \ntransmitting data on the endpoint, irrespective of data availability in the endpoint’s \ntransmit FIFO.\n2. \nNonisochronous IN tokens receive a NAK handshake reply\n–\nIsochronous IN tokens receive a zero-data-length packet reply\n3. \nThe core asserts the INEPNE (IN endpoint NAK effective) interrupt in \nOTG_HS_DIEPINTx in response to the SNAK bit in OTG_HS_DIEPCTLx.\n4. \nOnce this interrupt is seen by the application, the application can assume that the \nendpoint is in IN NAK mode. This interrupt can be cleared by the application by setting \nthe CNAK bit in OTG_HS_DIEPCTLx.\nApplication programming sequence:\n" }, { "page_number": 1533, "page_indices": { "start_index": 3019558, "end_index": 3022226 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1533 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "IN data transfers", 1531 ] ], "page_content": "RM0090 Rev 21\n1533/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n1.\nTo stop transmitting any data on a particular IN endpoint, the application must set the \nIN NAK bit. To set this bit, the following field must be programmed.\n–\nSNAK = 1 in OTG_HS_DIEPCTLx\n2. \nWait for assertion of the INEPNE interrupt in OTG_HS_DIEPINTx. This interrupt \nindicates that the core has stopped transmitting data on the endpoint.\n3. \nThe core can transmit valid IN data on the endpoint after the application has set the \nNAK bit, but before the assertion of the NAK Effective interrupt.\n4. \nThe application can mask this interrupt temporarily by writing to the INEPNEM bit in \nDIEPMSK.\n–\nINEPNEM = 0 in DIEPMSK\n5. \nTo exit Endpoint NAK mode, the application must clear the NAK status bit (NAKSTS) in \nOTG_HS_DIEPCTLx. This also clears the INEPNE interrupt (in OTG_HS_DIEPINTx).\n–\nCNAK = 1 in OTG_HS_DIEPCTLx\n6. \nIf the application masked this interrupt earlier, it must be unmasked as follows:\n–\nINEPNEM = 1 in DIEPMSK\n•\nIN endpoint disable\nUse the following sequence to disable a specific IN endpoint that has been previously \nenabled.\nApplication programming sequence:\n1.\nThe application must stop writing data on the AHB for the IN endpoint to be disabled.\n2. \nThe application must set the endpoint in NAK mode. \n–\nSNAK = 1 in OTG_HS_DIEPCTLx\n3. \nWait for the INEPNE interrupt in OTG_HS_DIEPINTx.\n4. \nSet the following bits in the OTG_HS_DIEPCTLx register for the endpoint that must be \ndisabled.\n–\nEPDIS = 1 in OTG_HS_DIEPCTLx\n–\nSNAK = 1 in OTG_HS_DIEPCTLx\n5. \nAssertion of the EPDISD interrupt in OTG_HS_DIEPINTx indicates that the core has \ncompletely disabled the specified endpoint. Along with the assertion of the interrupt, the \ncore also clears the following bits:\n–\nEPENA = 0 in OTG_HS_DIEPCTLx\n–\nEPDIS = 0 in OTG_HS_DIEPCTLx\n6. \nThe application must read the OTG_HS_DIEPTSIZx register for the periodic IN EP, to \ncalculate how much data on the endpoint were transmitted on the USB.\n7. \nThe application must flush the data in the Endpoint transmit FIFO, by setting the \nfollowing fields in the OTG_HS_GRSTCTL register:\n–\nTXFNUM (in OTG_HS_GRSTCTL) = Endpoint transmit FIFO number\n–\nTXFFLSH in (OTG_HS_GRSTCTL) = 1\nThe application must poll the OTG_HS_GRSTCTL register, until the TXFFLSH bit is cleared \nby the core, which indicates the end of flush operation. To transmit new data on this \nendpoint, the application can re-enable the endpoint at a later point.\n•\nTransfer Stop Programming for IN endpoints\nThe application must use the following programing sequence to stop any transfers (because \nof an interrupt from the host, typically a reset).\n" }, { "page_number": 1534, "page_indices": { "start_index": 3022226, "end_index": 3024827 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1534 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "IN data transfers", 1531 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1534/1757\nRM0090 Rev 21\nSequence of operations:\n1.\nDisable the IN endpoint by setting:\n–\nEPDIS = 1 in all OTG_HS_DIEPCTLx registers\n2. \nWait for the EPDIS interrupt in OTG_HS_DIEPINTx, which indicates that the IN \nendpoint is completely disabled. When the EPDIS interrupt is asserted the following \nbits are cleared:\n–\nEPDIS = 0 in OTG_HS_DIEPCTLx\n–\nEPENA = 0 in OTG_HS_DIEPCTLx\n3. \nFlush the TxFIFO by programming the following bits:\n–\nTXFFLSH = 1 in OTG_HS_GRSTCTL\n–\nTXFNUM = “FIFO number specific to endpoint” in OTG_HS_GRSTCTL\n4. \nThe application can start polling till TXFFLSH in OTG_HS_GRSTCTL is cleared. When \nthis bit is cleared, it ensures that there is no data left in the Tx FIFO.\n•\nGeneric non-periodic IN data transfers\nApplication requirements:\n1.\nBefore setting up an IN transfer, the application must ensure that all data to be \ntransmitted as part of the IN transfer are part of a single buffer.\n2. \nFor IN transfers, the Transfer Size field in the Endpoint Transfer Size register denotes a \npayload that constitutes multiple maximum-packet-size packets and a single short \npacket. This short packet is transmitted at the end of the transfer.\n–\nTo transmit a few maximum-packet-size packets and a short packet at the end of \nthe transfer:\nTransfer size[EPNUM] = x × MPSIZ[EPNUM] + sp\nIf (sp > 0), then packet count[EPNUM] = x + 1. \nOtherwise, packet count[EPNUM] = x\n–\nTo transmit a single zero-length data packet:\nTransfer size[EPNUM] = 0\nPacket count[EPNUM] = 1\n–\nTo transmit a few maximum-packet-size packets and a zero-length data packet at \nthe end of the transfer, the application must split the transfer into two parts. The \nfirst sends maximum-packet-size data packets and the second sends the zero-\nlength data packet alone.\nFirst transfer: transfer size[EPNUM] = x × MPSIZ[epnum]; packet count = n;\nSecond transfer: transfer size[EPNUM] = 0; packet count = 1;\n3. \nOnce an endpoint is enabled for data transfers, the core updates the Transfer size \nregister. At the end of the IN transfer, the application must read the Transfer size \nregister to determine how much data posted in the transmit FIFO have already been \nsent on the USB.\n4. \nData fetched into transmit FIFO = Application-programmed initial transfer size – core-\nupdated final transfer size\n–\nData transmitted on USB = (application-programmed initial packet count – Core \nupdated final packet count) × MPSIZ[EPNUM]\n–\nData yet to be transmitted on USB = (Application-programmed initial transfer size \n– data transmitted on USB)\nInternal data flow:\n" }, { "page_number": 1535, "page_indices": { "start_index": 3024827, "end_index": 3027947 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1535 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "IN data transfers", 1531 ] ], "page_content": "RM0090 Rev 21\n1535/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n1.\nThe application must set the transfer size and packet count fields in the endpoint-\nspecific registers and enable the endpoint to transmit the data.\n2. \nThe application must also write the required data to the transmit FIFO for the endpoint.\n3. \nEvery time a packet is written into the transmit FIFO by the application, the transfer size \nfor that endpoint is decremented by the packet size. The data is fetched from the \nmemory by the application, until the transfer size for the endpoint becomes 0. After \nwriting the data into the FIFO, the “number of packets in FIFO” count is incremented \n(this is a 3-bit count, internally maintained by the core for each IN endpoint transmit \nFIFO. The maximum number of packets maintained by the core at any time in an IN \nendpoint FIFO is eight). For zero-length packets, a separate flag is set for each FIFO, \nwithout any data in the FIFO.\n4. \nOnce the data are written to the transmit FIFO, the core reads them out upon receiving \nan IN token. For every nonisochronous IN data packet transmitted with an ACK \nhandshake, the packet count for the endpoint is decremented by one, until the packet \ncount is zero. The packet count is not decremented on a timeout.\n5. \nFor zero length packets (indicated by an internal zero length flag), the core sends out a \nzero-length packet for the IN token and decrements the packet count field.\n6. \nIf there are no data in the FIFO for a received IN token and the packet count field for \nthat endpoint is zero, the core generates an “IN token received when TxFIFO is empty” \n(ITTXFE) Interrupt for the endpoint, provided that the endpoint NAK bit is not set. The \ncore responds with a NAK handshake for nonisochronous endpoints on the USB.\n7. \nThe core internally rewinds the FIFO pointers and no timeout interrupt is generated.\n8. \nWhen the transfer size is 0 and the packet count is 0, the transfer complete (XFRC) \ninterrupt for the endpoint is generated and the endpoint enable is cleared.\nApplication programming sequence:\n1.\nProgram the OTG_HS_DIEPTSIZx register with the transfer size and corresponding \npacket count.\n2. \nProgram the OTG_HS_DIEPCTLx register with the endpoint characteristics and set the \nCNAK and EPENA (Endpoint Enable) bits.\n3. \nWhen transmitting nonzero length data packet, the application must poll the \nOTG_HS_DTXFSTSx register (where x is the FIFO number associated with that \nendpoint) to determine whether there is enough space in the data FIFO. The \napplication can optionally use TXFE (in OTG_HS_DIEPINTx) before writing the data.\n•\nGeneric periodic IN data transfers\nThis section describes a typical periodic IN data transfer.\nApplication requirements:\n1.\nApplication requirements 1, 2, 3, and 4 of Generic non-periodic IN data transfers on \npage 1534also apply to periodic IN data transfers, except for a slight modification of \nrequirement 2.\n–\nThe application can only transmit multiples of maximum-packet-size data packets \nor multiples of maximum-packet-size packets, plus a short packet at the end. To \n" }, { "page_number": 1536, "page_indices": { "start_index": 3027947, "end_index": 3030475 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1536 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "IN data transfers", 1531 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1536/1757\nRM0090 Rev 21\ntransmit a few maximum-packet-size packets and a short packet at the end of the \ntransfer, the following conditions must be met:\ntransfer size[EPNUM] = x × MPSIZ[EPNUM] + sp\n(where x is an integer ≥0, and 0 ≤sp < MPSIZ[EPNUM])\nIf (sp > 0), packet count[EPNUM] = x + 1\nOtherwise, packet count[EPNUM] = x;\nMCNT[EPNUM] = packet count[EPNUM]\n–\nThe application cannot transmit a zero-length data packet at the end of a transfer. \nIt can transmit a single zero-length data packet by itself. To transmit a single zero-\nlength data packet:\n–\ntransfer size[EPNUM] = 0\npacket count[EPNUM] = 1\nMCNT[EPNUM] = packet count[EPNUM]\n2. \nThe application can only schedule data transfers one frame at a time.\n–\n(MCNT – 1) × MPSIZ ≤XFERSIZ ≤MCNT × MPSIZ\n–\nPKTCNT = MCNT (in OTG_HS_DIEPTSIZx)\n–\nIf XFERSIZ < MCNT × MPSIZ, the last data packet of the transfer is a short \npacket.\n–\nNote that: MCNT is in OTG_HS_DIEPTSIZx, MPSIZ is in OTG_HS_DIEPCTLx, \nPKTCNT is in OTG_HS_DIEPTSIZx and XFERSIZ is in OTG_HS_DIEPTSIZx\n3. \nThe complete data to be transmitted in the frame must be written into the transmit FIFO \nby the application, before the IN token is received. Even when 1 word of the data to be \ntransmitted per frame is missing in the transmit FIFO when the IN token is received, the \ncore behaves as when the FIFO is empty. When the transmit FIFO is empty:\n–\nA zero data length packet would be transmitted on the USB for isochronous IN \nendpoints\n–\nA NAK handshake would be transmitted on the USB for interrupt IN endpoints\n4. \nFor a high-bandwidth IN endpoint with three packets in a frame, the application can \nprogram the endpoint FIFO size to be 2 × max_pkt_size and have the third packet \nloaded in after the first packet has been transmitted on the USB.\nInternal data flow:\n1.\nThe application must set the transfer size and packet count fields in the endpoint-\nspecific registers and enable the endpoint to transmit the data.\n2. \nThe application must also write the required data to the associated transmit FIFO for \nthe endpoint.\n3. \nEvery time the application writes a packet to the transmit FIFO, the transfer size for that \nendpoint is decremented by the packet size. The data are fetched from application \nmemory until the transfer size for the endpoint becomes 0.\n4. \nWhen an IN token is received for a periodic endpoint, the core transmits the data in the \nFIFO, if available. If the complete data payload (complete packet, in dedicated FIFO \n" }, { "page_number": 1537, "page_indices": { "start_index": 3030475, "end_index": 3033740 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1537 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "IN data transfers", 1531 ] ], "page_content": "RM0090 Rev 21\n1537/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nmode) for the frame is not present in the FIFO, then the core generates an IN token \nreceived when TxFIFO empty interrupt for the endpoint.\n–\nA zero-length data packet is transmitted on the USB for isochronous IN endpoints\n–\nA NAK handshake is transmitted on the USB for interrupt IN endpoints\n5. \nThe packet count for the endpoint is decremented by 1 under the following conditions:\n–\nFor isochronous endpoints, when a zero- or nonzero-length data packet is \ntransmitted\n–\nFor interrupt endpoints, when an ACK handshake is transmitted\n–\nWhen the transfer size and packet count are both 0, the transfer completed \ninterrupt for the endpoint is generated and the endpoint enable is cleared.\n6. \nAt the “Periodic frame Interval” (controlled by PFIVL in OTG_HS_DCFG), when the \ncore finds nonempty any of the isochronous IN endpoint FIFOs scheduled for the \ncurrent frame nonempty, the core generates an IISOIXFR interrupt in \nOTG_HS_GINTSTS.\nApplication programming sequence:\n1.\nProgram the OTG_HS_DIEPCTLx register with the endpoint characteristics and set the \nCNAK and EPENA bits.\n2. \nWrite the data to be transmitted in the next frame to the transmit FIFO.\n3. \nAsserting the ITTXFE interrupt (in OTG_HS_DIEPINTx) indicates that the application \nhas not yet written all data to be transmitted to the transmit FIFO.\n4. \nIf the interrupt endpoint is already enabled when this interrupt is detected, ignore the \ninterrupt. If it is not enabled, enable the endpoint so that the data can be transmitted on \nthe next IN token attempt.\n5. \nAsserting the XFRC interrupt (in OTG_HS_DIEPINTx) with no ITTXFE interrupt in \nOTG_HS_DIEPINTx indicates the successful completion of an isochronous IN transfer. \nA read to the OTG_HS_DIEPTSIZx register must give transfer size = 0 and packet \ncount = 0, indicating all data were transmitted on the USB.\n6. \nAsserting the XFRC interrupt (in OTG_HS_DIEPINTx), with or without the ITTXFE \ninterrupt (in OTG_HS_DIEPINTx), indicates the successful completion of an interrupt \nIN transfer. A read to the OTG_HS_DIEPTSIZx register must give transfer size = 0 and \npacket count = 0, indicating all data were transmitted on the USB.\n7. \nAsserting the incomplete isochronous IN transfer (IISOIXFR) interrupt in \nOTG_HS_GINTSTS with none of the aforementioned interrupts indicates the core did \nnot receive at least 1 periodic IN token in the current frame.\n•\nIncomplete isochronous IN data transfers\nThis section describes what the application must do on an incomplete isochronous IN data \ntransfer.\nInternal data flow:\n1.\nAn isochronous IN transfer is treated as incomplete in one of the following conditions:\na) \nThe core receives a corrupted isochronous IN token on at least one isochronous \nIN endpoint. In this case, the application detects an incomplete isochronous IN \ntransfer interrupt (IISOIXFR in OTG_HS_GINTSTS).\nb) \nThe application is slow to write the complete data payload to the transmit FIFO \nand an IN token is received before the complete data payload is written to the \nFIFO. In this case, the application detects an IN token received when TxFIFO \nempty interrupt in OTG_HS_DIEPINTx. The application can ignore this interrupt, \n" }, { "page_number": 1538, "page_indices": { "start_index": 3033740, "end_index": 3035776 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1538 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.7 Operational model", 1520 ], [ 4, "IN data transfers", 1531 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1538/1757\nRM0090 Rev 21\nas it eventually results in an incomplete isochronous IN transfer interrupt \n(IISOIXFR in OTG_HS_GINTSTS) at the end of periodic frame.\nThe core transmits a zero-length data packet on the USB in response to the \nreceived IN token.\n2. \nThe application must stop writing the data payload to the transmit FIFO as soon as \npossible.\n3. \nThe application must set the NAK bit and the disable bit for the endpoint.\n4. \nThe core disables the endpoint, clears the disable bit, and asserts the Endpoint Disable \ninterrupt for the endpoint.\nApplication programming sequence\n1.\nThe application can ignore the IN token received when TxFIFO empty interrupt in \nOTG_HS_DIEPINTx on any isochronous IN endpoint, as it eventually results in an \nincomplete isochronous IN transfer interrupt (in OTG_HS_GINTSTS).\n2. \nAssertion of the incomplete isochronous IN transfer interrupt (in OTG_HS_GINTSTS) \nindicates an incomplete isochronous IN transfer on at least one of the isochronous IN \nendpoints.\n3. \nThe application must read the Endpoint Control register for all isochronous IN \nendpoints to detect endpoints with incomplete IN data transfers.\n4. \nThe application must stop writing data to the Periodic Transmit FIFOs associated with \nthese endpoints on the AHB.\n5. \nProgram the following fields in the OTG_HS_DIEPCTLx register to disable the \nendpoint:\n–\nSNAK = 1 in OTG_HS_DIEPCTLx\n–\nEPDIS = 1 in OTG_HS_DIEPCTLx\n6. \nThe assertion of the Endpoint Disabled interrupt in OTG_HS_DIEPINTx indicates that \nthe core has disabled the endpoint.\n–\nAt this point, the application must flush the data in the associated transmit FIFO or \noverwrite the existing data in the FIFO by enabling the endpoint for a new transfer \nin the next micro-frame. To flush the data, the application must use the \nOTG_HS_GRSTCTL register.\n•\nStalling nonisochronous IN endpoints\nThis section describes how the application can stall a nonisochronous endpoint.\nApplication programming sequence:\n" }, { "page_number": 1539, "page_indices": { "start_index": 3035776, "end_index": 3039066 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1539 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.8 Worst case response time", 1539 ], [ 4, "Choosing the value of TRDT in OTG_HS_GUSBCFG", 1539 ] ], "page_content": "RM0090 Rev 21\n1539/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n1.\nDisable the IN endpoint to be stalled. Set the STALL bit as well.\n2. \nEPDIS = 1 in OTG_HS_DIEPCTLx, when the endpoint is already enabled\n–\nSTALL = 1 in OTG_HS_DIEPCTLx\n–\nThe STALL bit always takes precedence over the NAK bit\n3. \nAssertion of the Endpoint Disabled interrupt (in OTG_HS_DIEPINTx) indicates to the \napplication that the core has disabled the specified endpoint.\n4. \nThe application must flush the nonperiodic or periodic transmit FIFO, depending on the \nendpoint type. In case of a nonperiodic endpoint, the application must re-enable the \nother nonperiodic endpoints that do not need to be stalled, to transmit data.\n5. \nWhenever the application is ready to end the STALL handshake for the endpoint, the \nSTALL bit must be cleared in OTG_HS_DIEPCTLx.\n6. \nIf the application sets or clears a STALL bit for an endpoint due to a \nSetFeature.Endpoint Halt command or ClearFeature.Endpoint Halt command, the \nSTALL bit must be set or cleared before the application sets up the Status stage \ntransfer on the control endpoint.\nSpecial case: stalling the control OUT endpoint\nThe core must stall IN/OUT tokens if, during the data stage of a control transfer, the host \nsends more IN/OUT tokens than are specified in the SETUP packet. In this case, the \napplication must enable the ITTXFE interrupt in OTG_HS_DIEPINTx and the OTEPDIS \ninterrupt in OTG_HS_DOEPINTx during the data stage of the control transfer, after the core \nhas transferred the amount of data specified in the SETUP packet. Then, when the \napplication receives this interrupt, it must set the STALL bit in the corresponding endpoint \ncontrol register, and clear this interrupt.\n35.13.8 \nWorst case response time\nWhen the OTG_HS controller acts as a device, there is a worst case response time for any \ntokens that follow an isochronous OUT. This worst case response time depends on the AHB \nclock frequency.\nThe core registers are in the AHB domain, and the core does not accept another token \nbefore updating these register values. The worst case is for any token following an \nisochronous OUT, because for an isochronous transaction, there is no handshake and the \nnext token could come sooner. This worst case value is 7 PHY clocks when the AHB clock \nis the same as the PHY clock. When the AHB clock is faster, this value is smaller.\nIf this worst case condition occurs, the core responds to bulk/interrupt tokens with a NAK \nand drops isochronous and SETUP tokens. The host interprets this as a timeout condition \nfor SETUP and retries the SETUP packet. For isochronous transfers, the Incomplete \nisochronous IN transfer interrupt (IISOIXFR) and Incomplete isochronous OUT transfer \ninterrupt (IISOOXFR) inform the application that isochronous IN/OUT packets were \ndropped.\nChoosing the value of TRDT in OTG_HS_GUSBCFG\nThe value in TRDT (OTG_HS_GUSBCFG) is the time it takes for the MAC, in terms of PHY \nclocks after it has received an IN token, to get the FIFO status, and thus the first data from \nthe PFC block. This time involves the synchronization delay between the PHY and AHB \nclocks. The worst case delay for this is when the AHB clock is the same as the PHY clock. \nIn this case, the delay is 5 clocks.\n" }, { "page_number": 1540, "page_indices": { "start_index": 3039066, "end_index": 3040222 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1540 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.8 Worst case response time", 1539 ], [ 4, "Choosing the value of TRDT in OTG_HS_GUSBCFG", 1539 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1540/1757\nRM0090 Rev 21\nOnce the MAC receives an IN token, this information (token received) is synchronized to the \nAHB clock by the PFC (the PFC runs on the AHB clock). The PFC then reads the data from \nthe SPRAM and writes them into the dual clock source buffer. The MAC then reads the data \nout of the source buffer (4 deep).\nIf the AHB is running at a higher frequency than the PHY, the application can use a smaller \nvalue for TRDT (in OTG_HS_GUSBCFG).\nFigure 429 has the following signals:\n•\ntkn_rcvd: Token received information from MAC to PFC\n•\ndynced_tkn_rcvd: Doubled sync tkn_rcvd, from PCLK to HCLK domain\n•\nspr_read: Read to SPRAM\n•\nspr_addr: Address to SPRAM\n•\nspr_rdata: Read data from SPRAM\n•\nsrcbuf_push: Push to the source buffer\n•\nsrcbuf_rdata: Read data from the source buffer. Data seen by MAC\nRefer to Table 214: TRDT values for the values of TRDT versus AHB clock frequency. \nFigure 429. TRDT max timing case \n1\n2\n3\n4\n5\n6\n7\n8\n0ns\n50ns\n100ns\n150ns\n200ns\nHCLK\nPCLK\ntkn_rcvd\ndsynced_tkn_rcvd\nspr_read\nspr_addr\nspr_rdata\nsrcbuf_push\nsrcbuf_rdata\n5 Clocks\nD1\nA1\nD1\nai15680\n" }, { "page_number": 1541, "page_indices": { "start_index": 3040222, "end_index": 3041528 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1541 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.9 OTG programming model", 1541 ], [ 4, "A-device session request protocol", 1541 ] ], "page_content": "RM0090 Rev 21\n1541/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n35.13.9 \nOTG programming model\nThe OTG_HS controller is an OTG device supporting HNP and SRP. When the core is \nconnected to an “A” plug, it is referred to as an A-device. When the core is connected to a \n“B” plug it is referred to as a B-device. In host mode, the OTG_HS controller turns off VBUS \nto conserve power. SRP is a method by which the B-device signals the A-device to turn on \nVBUS power. A device must perform both data-line pulsing and VBUS pulsing, but a host can \ndetect either data-line pulsing or VBUS pulsing for SRP. HNP is a method by which the B-\ndevice negotiates and switches to host role. In Negotiated mode after HNP, the B-device \nsuspends the bus and reverts to the device role.\nA-device session request protocol\nThe application must set the SRP-capable bit in the Core USB configuration register. This \nenables the OTG_HS controller to detect SRP as an A-device.\nFigure 430. A-device SRP\n1.\nDRV_VBUS = VBUS drive signal to the PHY\nVBUS_VALID = VBUS valid signal from PHY\nA_VALID = A-device VBUS level signal to PHY\nDP = Data plus line\nDM = Data minus line\nai15681b\nDRV_VBUS\nVBUS_VALID\nA_VALID\nOTG_HS_FS_DP\nOTG_HS_FS_DM\nSuspend\nVBUS pulsing\nData line pulsing\nConnect\n1\n6\n2\n5\n3\n4\n7\nLow\n" }, { "page_number": 1542, "page_indices": { "start_index": 3041528, "end_index": 3043385 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1542 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.9 OTG programming model", 1541 ], [ 4, "B-device session request protocol", 1542 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1542/1757\nRM0090 Rev 21\n1.\nTo save power, the application suspends and turns off port power when the bus is idle \nby writing the port suspend and port power bits in the host port control and status \nregister.\n2. \nPHY indicates port power off by deasserting the VBUS_VALID signal.\n3. \nThe device must detect SE0 for at least 2 ms to start SRP when VBUS power is off.\n4. \nTo initiate SRP, the device turns on its data line pull-up resistor for 5 to 10 ms. The \nOTG_HS controller detects data-line pulsing.\n5. \nThe device drives VBUS above the A-device session valid (2.0 V minimum) for VBUS \npulsing.\nThe OTG_HS controller interrupts the application on detecting SRP. The Session \nrequest detected bit is set in Global interrupt status register (SRQINT set in \nOTG_HS_GINTSTS).\n6. \nThe application must service the Session request detected interrupt and turn on the \nport power bit by writing the port power bit in the host port control and status register. \nThe PHY indicates port power-on by asserting the VBUS_VALID signal.\n7. \nWhen the USB is powered, the device connects, completing the SRP process.\nB-device session request protocol\nThe application must set the SRP-capable bit in the Core USB configuration register. This \nenables the OTG_HS controller to initiate SRP as a B-device. SRP is a means by which the \nOTG_HS controller can request a new session from the host.\nFigure 431. B-device SRP\n1.\nVBUS_VALID = VBUS valid signal from PHY\nB_VALID = B-device valid session to PHY\nDISCHRG_VBUS = discharge signal to PHY\nSESS_END = session end signal to PHY\nCHRG_VBUS = charge VBUS signal to PHY\nDP = Data plus line\nDM = Data minus line\nai1568b2\nVBUS_VALID\nB_VALID\nDISCHRG_VBUS\nSESS_END\nOTG_HS_FS_DP\nOTG_HS_FS_DM\nCHRG_VBUS\nSuspend\nData line pulsing\nConnect\nVBUS pulsing\n1\n6\n2\n3\n4\n5\n8\n7\nLow\n" }, { "page_number": 1543, "page_indices": { "start_index": 3043385, "end_index": 3045678 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1543 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.9 OTG programming model", 1541 ], [ 4, "A-device host negotiation protocol", 1543 ] ], "page_content": "RM0090 Rev 21\n1543/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\n1.\nTo save power, the host suspends and turns off port power when the bus is idle.\nThe OTG_HS controller sets the early suspend bit in the Core interrupt register after 3 \nms of bus idleness. Following this, the OTG_HS controller sets the USB suspend bit in \nthe Core interrupt register.\nThe OTG_HS controller informs the PHY to discharge VBUS.\n2. \nThe PHY indicates the session’s end to the device. This is the initial condition for SRP. \nThe OTG_HS controller requires 2 ms of SE0 before initiating SRP.\nFor a USB 1.1 full-speed serial transceiver, the application must wait until VBUS \ndischarges to 0.2 V after BSVLD (in OTG_HS_GOTGCTL) is deasserted. This \ndischarge time can be obtained from the transceiver vendor and varies from one \ntransceiver to another.\n3. \nThe USB OTG core informs the PHY to speed up VBUS discharge.\n4. \nThe application initiates SRP by writing the session request bit in the OTG Control and \nstatus register. The OTG_HS controller perform data-line pulsing followed by VBUS \npulsing.\n5. \nThe host detects SRP from either the data-line or VBUS pulsing, and turns on VBUS. \nThe PHY indicates VBUS power-on to the device.\n6. \nThe OTG_HS controller performs VBUS pulsing.\nThe host starts a new session by turning on VBUS, indicating SRP success. The \nOTG_HS controller interrupts the application by setting the session request success \nstatus change bit in the OTG interrupt status register. The application reads the session \nrequest success bit in the OTG control and status register.\n7. \nWhen the USB is powered, the OTG_HS controller connects, completing the SRP \nprocess.\nA-device host negotiation protocol\nHNP switches the USB host role from the A-device to the B-device. The application must set \nthe HNP-capable bit in the Core USB configuration register to enable the OTG_HS \ncontroller to perform HNP as an A-device.\nFigure 432. A-device HNP\n1.\nDPPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DP line inside the PHY.\nDMPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DM line inside the PHY.\nai15683b\nOTG core\nDP\nDM\nDPPULLDOWN\nDMPULLDOWN\nHost\nDevice\nHost\n1\nSuspend 2\n3\n4\n5\nReset\n6\nTraffic\n7\n8\nConnect\nTraffic\n" }, { "page_number": 1544, "page_indices": { "start_index": 3045678, "end_index": 3048311 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1544 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.9 OTG programming model", 1541 ], [ 4, "B-device host negotiation protocol", 1544 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1544/1757\nRM0090 Rev 21\n1.\nThe OTG_HS controller sends the B-device a SetFeature b_hnp_enable descriptor to \nenable HNP support. The B-device’s ACK response indicates that the B-device \nsupports HNP. The application must set host Set HNP Enable bit in the OTG Control \nand status register to indicate to the OTG_HS controller that the B-device supports \nHNP.\n2. \nWhen it has finished using the bus, the application suspends by writing the Port \nsuspend bit in the host port control and status register.\n3. \nWhen the B-device observes a USB suspend, it disconnects, indicating the initial \ncondition for HNP. The B-device initiates HNP only when it must switch to the host role; \notherwise, the bus continues to be suspended.\nThe OTG_HS controller sets the host negotiation detected interrupt in the OTG \ninterrupt status register, indicating the start of HNP.\nThe OTG_HS controller deasserts the DM pull down and DM pull down in the PHY to \nindicate a device role. The PHY enables the OTG_HS_DP pull-up resistor to indicate a \nconnect for B-device.\nThe application must read the current mode bit in the OTG Control and status register \nto determine peripheral mode operation.\n4. \nThe B-device detects the connection, issues a USB reset, and enumerates the \nOTG_HS controller for data traffic.\n5. \nThe B-device continues the host role, initiating traffic, and suspends the bus when \ndone.\nThe OTG_HS controller sets the early suspend bit in the Core interrupt register after 3 \nms of bus idleness. Following this, the OTG_HS controller sets the USB Suspend bit in \nthe Core interrupt register.\n6. \nIn Negotiated mode, the OTG_HS controller detects the suspend, disconnects, and \nswitches back to the host role. The OTG_HS controller asserts the DM pull down and \nDM pull down in the PHY to indicate its assumption of the host role.\n7. \nThe OTG_HS controller sets the Connector ID status change interrupt in the OTG \nInterrupt Status register. The application must read the connector ID status in the OTG \nControl and Status register to determine the OTG_HS controller operation as an A-\ndevice. This indicates the completion of HNP to the application. The application must \nread the Current mode bit in the OTG control and status register to determine host \nmode operation.\n8. \nThe B-device connects, completing the HNP process.\nB-device host negotiation protocol\nHNP switches the USB host role from B-device to A-device. The application must set the \nHNP-capable bit in the Core USB configuration register to enable the OTG_HS controller to \nperform HNP as a B-device.\n" }, { "page_number": 1545, "page_indices": { "start_index": 3048311, "end_index": 3050122 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1545 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.9 OTG programming model", 1541 ], [ 4, "B-device host negotiation protocol", 1544 ] ], "page_content": "RM0090 Rev 21\n1545/1757\nRM0090\nUSB on-the-go high-speed (OTG_HS)\n1546\nFigure 433. B-device HNP\n1.\nDPPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DP line inside the PHY.\nDMPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DM line inside the PHY.\n1.\nThe A-device sends the SetFeature b_hnp_enable descriptor to enable HNP support. \nThe OTG_HS controller’s ACK response indicates that it supports HNP. The \napplication must set the Device HNP enable bit in the OTG Control and status register \nto indicate HNP support.\nThe application sets the HNP request bit in the OTG Control and status register to \nindicate to the OTG_HS controller to initiate HNP.\n2. \nWhen it has finished using the bus, the A-device suspends by writing the Port suspend \nbit in the host port control and status register.\nThe OTG_HS controller sets the Early suspend bit in the Core interrupt register after 3 \nms of bus idleness. Following this, the OTG_HS controller sets the USB suspend bit in \nthe Core interrupt register.\nThe OTG_HS controller disconnects and the A-device detects SE0 on the bus, \nindicating HNP. The OTG_HS controller asserts the DP pull down and DM pull down in \nthe PHY to indicate its assumption of the host role.\nThe A-device responds by activating its OTG_HS_DP pull-up resistor within 3 ms of \ndetecting SE0. The OTG_HS controller detects this as a connect.\nThe OTG_HS controller sets the host negotiation success status change interrupt in \nthe OTG Interrupt status register, indicating the HNP status. The application must read \nthe host negotiation success bit in the OTG Control and status register to determine \nai15684b\nOTG core\nDP\nDM\nDPPULLDOWN\nDMPULLDOWN\nHost\nDevice\nDevice\n1\nSuspend 2\n3\n4\n5\nReset\n6\nTraffic\n7\n8\nConnect\nTraffic\n" }, { "page_number": 1546, "page_indices": { "start_index": 3050122, "end_index": 3051154 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1546 }, "toc_details": [ [ 1, "35 USB on-the-go high-speed (OTG_HS)", 1384 ], [ 2, "35.13 OTG_HS programming model", 1490 ], [ 3, "35.13.9 OTG programming model", 1541 ], [ 4, "B-device host negotiation protocol", 1544 ] ], "page_content": "USB on-the-go high-speed (OTG_HS)\nRM0090\n1546/1757\nRM0090 Rev 21\nhost negotiation success. The application must read the current Mode bit in the Core \ninterrupt register (OTG_HS_GINTSTS) to determine host mode operation.\n3. \nThe application sets the reset bit (PRST in OTG_HS_HPRT) and the OTG_HS \ncontroller issues a USB reset and enumerates the A-device for data traffic.\n4. \nThe OTG_HS controller continues the host role of initiating traffic, and when done, \nsuspends the bus by writing the Port suspend bit in the host port control and status \nregister.\n5. \nIn Negotiated mode, when the A-device detects a suspend, it disconnects and switches \nback to the host role. The OTG_HS controller deasserts the DP pull down and DM pull \ndown in the PHY to indicate the assumption of the device role.\n6. \nThe application must read the current mode bit in the Core interrupt \n(OTG_HS_GINTSTS) register to determine the host mode operation.\n7. \nThe OTG_HS controller connects, completing the HNP process.\n \n" }, { "page_number": 1547, "page_indices": { "start_index": 3051154, "end_index": 3053720 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1547 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.1 FSMC main features", 1547 ] ], "page_content": "RM0090 Rev 21\n1547/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n36 \nFlexible static memory controller (FSMC)\nThis section applies to the whole STM32F40x/41x family only.\n36.1 \nFSMC main features\nThe FSMC block is able to interface with synchronous and asynchronous memories and \n16-bit PC memory cards. Its main purpose is to:\n•\nTranslate the AHB transactions into the appropriate external device protocol\n•\nMeet the access timing requirements of the external devices\nAll external memories share the addresses, data and control signals with the controller. \nEach external device is accessed by means of a unique chip select. The FSMC performs \nonly one access at a time to an external device.\nThe FSMC has the following main features:\n•\nInterfaces with static memory-mapped devices including: \n–\nStatic random access memory (SRAM)\n–\nNOR/OneNAND flash memory\n–\nPSRAM (4 memory banks)\n•\nTwo banks of NAND Flash with ECC hardware that checks up to 8 Kbytes of data\n•\n16-bit PC Card compatible devices\n•\nSupports burst mode access to synchronous devices (NOR flash and PSRAM)\n•\n8- or 16-bit wide databus\n•\nIndependent chip select control for each memory bank\n•\nIndependent configuration for each memory bank\n•\nProgrammable timings to support a wide range of devices, in particular:\n–\nProgrammable wait states (up to 15)\n–\nProgrammable bus turnaround cycles (up to 15)\n–\nProgrammable output enable and write enable delays (up to 15)\n–\nIndependent read and write timings and protocol, so as to support the widest \nvariety of memories and timings\n•\nWrite enable and byte lane select outputs for use with PSRAM and SRAM devices\n•\nTranslation of 32-bit wide AHB transactions into consecutive 16-bit or 8-bit accesses to \nexternal 16-bit or 8-bit devices\n•\nA Write FIFO, 2-word long (16-word long for STM32F42x and STM32F43x), each word \nis 32 bits wide, only stores data and not the address. Therefore, this FIFO only buffers \nAHB write burst transactions. This makes it possible to write to slow memories and free \nthe AHB quickly for other operations. Only one burst at a time is buffered: if a new AHB \nburst or single transaction occurs while an operation is in progress, the FIFO is \ndrained. The FSMC inserts wait states until the current memory access is complete.\n•\nExternal asynchronous wait control\nThe FSMC registers that define the external device type and associated characteristics are \nusually set at boot time and do not change until the next reset or power-up. However, it is \npossible to change the settings at any time.\n" }, { "page_number": 1548, "page_indices": { "start_index": 3053720, "end_index": 3054943 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1548 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.2 Block diagram", 1548 ], [ 2, "36.3 AHB interface", 1548 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1548/1757\nRM0090 Rev 21\n36.2 \nBlock diagram\nThe FSMC consists of four main blocks:\n•\nThe AHB interface (including the FSMC configuration registers)\n•\nThe NOR flash/PSRAM controller\n•\nThe NAND Flash/PC Card controller\n•\nThe external device interface\nThe block diagram is shown in Figure 434.\nFigure 434. FSMC block diagram\n36.3 \nAHB interface\nThe AHB slave interface enables internal CPUs and other bus master peripherals to access \nthe external static memories.\nAHB transactions are translated into the external device protocol. In particular, if the \nselected external memory is 16 or 8 bits wide, 32-bit wide transactions on the AHB are split \ninto consecutive 16- or 8-bit accesses. The FSMC Chip Select (FSMC_NEx) does not \nAHB bus\nFSMC interrupt to NVIC\nNOR/PSRAM\nmemory \ncontroller\nHCLK\nFrom clock\ncontroller\nNAND/PC Card\nmemory\ncontroller\nsignals\nNAND\nShared\nsignals\nsignals\nNOR/PSRAM\nFSMC_NE[4:1]\nFSMC_NL (or NADV)\nFSMC_NWAIT\nFSMC_NOE\nFSMC_NWE\nFSMC_NIORD\nFSMC_NREG\nFSMC_CD\nsignals\nPC Card\nai15591b\nFSMC_NBL[1:0]\nFSMC_NCE[3:2]\nFSMC_INT[3:2]\nFSMC_INTR\nFSMC_NCE4_1\nFSMC_NCE4_2\nFSMC_NIOWR\nFSMC_CLK\nConfiguration\nregisters\nFSMC_A[25:0]\nFSMC_D[15:0]\n" }, { "page_number": 1549, "page_indices": { "start_index": 3054943, "end_index": 3057397 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1549 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.3 AHB interface", 1548 ], [ 3, "36.3.1 Supported memories and transactions", 1549 ], [ 4, "General transaction rules", 1549 ] ], "page_content": "RM0090 Rev 21\n1549/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\ntoggle between consecutive accesses except when performing accesses in mode D with the \nextended mode enabled.\nThe FSMC generates an AHB error in the following conditions:\n•\nWhen reading or writing to an FSMC bank which is not enabled\n•\nWhen reading or writing to the NOR flash bank while the FACCEN bit is reset in the \nFSMC_BCRx register.\n•\nWhen reading or writing to the PC Card banks while the input pin FSMC_CD (Card \nPresence Detection) is low.\nThe effect of this AHB error depends on the AHB master which has attempted the R/W \naccess:\n•\nIf it is the Cortex®-M4 with FPU CPU, a hard fault interrupt is generated\n•\nIf is a DMA, a DMA transfer error is generated and the corresponding DMA channel is \nautomatically disabled. \nThe AHB clock (HCLK) is the reference clock for the FSMC.\n36.3.1 \nSupported memories and transactions\nGeneral transaction rules\nThe requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the \naccessed external device has a fixed data width. This may lead to inconsistent transfers.\nTherefore, some simple transaction rules must be followed:\n•\nAHB transaction size and memory data size are equal\nThere is no issue in this case.\n•\nAHB transaction size is greater than the memory size\nIn this case, the FSMC splits the AHB transaction into smaller consecutive memory \naccesses in order to meet the external data width.\n•\nAHB transaction size is smaller than the memory size\nAsynchronous transfers may or not be consistent depending on the type of external \ndevice.\n–\nAsynchronous accesses to devices that have the byte select feature (SRAM, \nROM, PSRAM).\na) FSMC allows write transactions accessing the right data through its byte lanes \nNBL[1:0]\nb) Read transactions are allowed. All memory bytes are read and the useless \nones are discarded. The NBL[1:0] are kept low during read transactions. \n–\nAsynchronous accesses to devices that do not have the byte select feature (NOR \nand NAND Flash 16-bit).\nThis situation occurs when a byte access is requested to a 16-bit wide flash \nmemory. Clearly, the device cannot be accessed in byte mode (only 16-bit words \ncan be read from/written to the flash memory) therefore:\na) \nWrite transactions are not allowed\nb) \nRead transactions are allowed. All memory bytes are read and the useless ones \nare discarded. The NBL[1:0] are set to 0 during read transactions.\n" }, { "page_number": 1550, "page_indices": { "start_index": 3057397, "end_index": 3058748 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1550 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.3 AHB interface", 1548 ], [ 3, "36.3.1 Supported memories and transactions", 1549 ], [ 4, "Configuration registers", 1550 ], [ 2, "36.4 External device address mapping", 1550 ], [ 3, "36.4.1 NOR/PSRAM address mapping", 1550 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1550/1757\nRM0090 Rev 21\nConfiguration registers\nThe FSMC can be configured using a register set. See Section 36.5.6, for a detailed \ndescription of the NOR flash/PSRAM control registers. See Section 36.6.8, for a detailed \ndescription of the NAND Flash/PC Card registers.\n36.4 \nExternal device address mapping\nFrom the FSMC point of view, the external memory is divided into 4 fixed-size banks of \n256 Mbytes each (Refer to Figure 435):\n•\nBank 1 used to address up to four NOR flash or PSRAM memory devices. This bank is \nsplit into 4 NOR/PSRAM subbanks with four dedicated chip selects, as follows:\n–\nBank 1 - NOR/PSRAM 1\n–\nBank 1 - NOR/PSRAM 2\n–\nBank 1 - NOR/PSRAM 3\n–\nBank 1 - NOR/PSRAM 4\n•\nBanks 2 and 3 used to address NAND Flash devices (1 device per bank)\n•\nBank 4 used to address a PC Card device\nFor each bank the type of memory to be used is user-defined in the Configuration register.\nFigure 435. FSMC memory banks\n36.4.1 \nNOR/PSRAM address mapping\nHADDR[27:26] bits are used to select one of the four memory banks as shown in Table 217.\nBank 1\nNAND Flash\nNOR / PSRAM\nSupported memory type\nBanks\n4 × 64 MB\n6000 0000h\n6FFF FFFFh\nAddress\n7000 0000h\n7FFF FFFFh\n8000 0000h\n8FFF FFFFh\n9000 0000h\n9FFF FFFFh\nBank 2\n4 × 64 MB\nBank 3\n4 × 64 MB\nBank 4\n4 × 64 MB\nPC Card\nai14719\n" }, { "page_number": 1551, "page_indices": { "start_index": 3058748, "end_index": 3060674 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1551 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.4 External device address mapping", 1550 ], [ 3, "36.4.1 NOR/PSRAM address mapping", 1550 ], [ 4, "Wrap support for NOR flash/PSRAM", 1551 ], [ 3, "36.4.2 NAND/PC Card address mapping", 1551 ] ], "page_content": "RM0090 Rev 21\n1551/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \nHADDR[25:0] contain the external memory address. Since HADDR is a byte address \nwhereas the memory is addressed in words, the address actually issued to the memory \nvaries according to the memory data width, as shown in the following table.\n \nWrap support for NOR flash/PSRAM\nWrap burst mode for synchronous memories is not supported. The memories must be \nconfigured in linear burst mode of undefined length.\n36.4.2 \nNAND/PC Card address mapping\nIn this case, three banks are available, each of them divided into memory spaces as \nindicated in Table 219.\n \nTable 217. NOR/PSRAM bank selection\nHADDR[27:26](1)\n1.\nHADDR are internal AHB address lines that are translated to external memory.\nSelected bank\n00 \nBank 1 - NOR/PSRAM 1\n01 \nBank 1 - NOR/PSRAM 2\n10 \nBank 1 - NOR/PSRAM 3\n11 \nBank 1 - NOR/PSRAM 4\nTable 218. External memory address\nMemory width(1)\n1.\nIn case of a 16-bit external memory width, the FSMC internally uses HADDR[25:1] to generate the address \nfor external memory FSMC_A[24:0].\nWhatever the external memory width (16-bit or 8-bit), FSMC_A[0] should be connected to external memory \naddress A[0].\nData address issued to the memory\nMaximum memory capacity (bits) \n8-bit \nHADDR[25:0] \n64 Mbyte x 8 = 512 Mbit \n16-bit\nHADDR[25:1] >> 1 \n64 Mbyte/2 x 16 = 512 Mbit \nTable 219. Memory mapping and timing registers\nStart address\nEnd address\nFSMC Bank\nMemory space\nTiming register\n0x9C00 0000\n0x9FFF FFFF\nBank 4 - PC card\nI/O\nFSMC_PIO4 (0xB0)\n0x9800 0000\n0x9BFF FFFF\nAttribute\n FSMC_PATT4 (0xAC)\n0x9000 0000\n0x93FF FFFF\nCommon\n FSMC_PMEM4 (0xA8)\n0x8800 0000\n0x8BFF FFFF\nBank 3 - NAND Flash\nAttribute\n FSMC_PATT3 (0x8C)\n0x8000 0000\n0x83FF FFFF\nCommon\n FSMC_PMEM3 (0x88)\n0x7800 0000\n0x7BFF FFFF\nBank 2- NAND Flash\nAttribute\nFSMC_PATT2 (0x6C)\n0x7000 0000\n0x73FF FFFF\nCommon\n FSMC_PMEM2 (0x68)\n" }, { "page_number": 1552, "page_indices": { "start_index": 3060674, "end_index": 3062695 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1552 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1552/1757\nRM0090 Rev 21\nFor NAND Flash memory, the common and attribute memory spaces are subdivided into \nthree sections (see in Table 220 below) located in the lower 256 Kbytes:\n•\nData section (first 64 Kbytes in the common/attribute memory space)\n•\nCommand section (second 64 Kbytes in the common / attribute memory space)\n•\nAddress section (next 128 Kbytes in the common / attribute memory space)\n \nThe application software uses the 3 sections to access the NAND Flash memory:\n•\nTo send a command to NAND Flash memory: the software must write the command \nvalue to any memory location in the command section.\n•\nTo specify the NAND Flash address that must be read or written: the software \nmust write the address value to any memory location in the address section. Since an \naddress can be 4 or 5 bytes long (depending on the actual memory size), several \nconsecutive writes to the address section are needed to specify the full address.\n•\nTo read or write data: the software reads or writes the data value from or to any \nmemory location in the data section.\nSince the NAND Flash memory automatically increments addresses, there is no need to \nincrement the address of the data section to access consecutive memory locations.\n36.5 \nNOR flash/PSRAM controller\nThe FSMC generates the appropriate signal timings to drive the following types of \nmemories:\n•\nAsynchronous SRAM and ROM\n–\n8-bit\n–\n16-bit\n–\n32-bit\n•\nPSRAM (Cellular RAM)\n–\nAsynchronous mode\n–\nBurst mode for synchronous accesses\n–\nMultiplexed or nonmultiplexed\n•\nNOR flash\n–\nAsynchronous mode\n–\nBurst mode for synchronous accesses\n–\nMultiplexed or nonmultiplexed\nThe FSMC outputs a unique chip select signal NE[4:1] per bank. All the other signals \n(addresses, data and control) are shared.\nTable 220. NAND bank selections\nSection name\nHADDR[17:16]\nAddress range\nAddress section \n1X \n0x020000-0x03FFFF \nCommand section \n01 \n0x010000-0x01FFFF \nData section \n00 \n0x000000-0x0FFFF \n" }, { "page_number": 1553, "page_indices": { "start_index": 3062695, "end_index": 3064734 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1553 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.1 External memory interface signals", 1553 ], [ 4, "NOR flash, nonmultiplexed I/Os", 1553 ] ], "page_content": "RM0090 Rev 21\n1553/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nFor synchronous accesses, the FSMC issues the clock (CLK) to the selected external \ndevice only during the read/write transactions. This clock is a submultiple of the HCLK clock. \nThe size of each bank is fixed and equal to 64 Mbytes.\nEach bank is configured by means of dedicated registers (see Section 36.5.6).\nThe programmable memory parameters include access timings (see Table 221) and support \nfor wait management (for PSRAM and NOR flash accessed in burst mode).\n \n36.5.1 \nExternal memory interface signals\nTable 222, Table 223 and Table 224 list the signals that are typically used to interface NOR \nflash, SRAM and PSRAM.\nNote:\nPrefix “N”. specifies the associated signal as active low.\nNOR flash, nonmultiplexed I/Os\n \nTable 221. Programmable NOR/PSRAM access parameters\nParameter \nFunction \nAccess mode \nUnit \nMin. \nMax. \nAddress \nsetup\nDuration of the address \nsetup phase \nAsynchronous\nAHB clock cycle \n(HCLK) \n0\n15\nAddress hold\nDuration of the address hold \nphase \nAsynchronous, \nmuxed I/Os \nAHB clock cycle \n(HCLK) \n1\n15\nData setup\nDuration of the data setup \nphase \nAsynchronous\nAHB clock cycle \n(HCLK) \n1\n256 \nBus turn\nDuration of the bus \nturnaround phase \nAsynchronous and \nsynchronous \nread/write\nAHB clock cycle \n(HCLK) \n0\n15\nClock divide \nratio\nNumber of AHB clock cycles \n(HCLK) to build one memory \nclock cycle (CLK) \nSynchronous\nAHB clock cycle \n(HCLK) \n2\n16 \nData latency\nNumber of clock cycles to \nissue to the memory before \nthe first data of the burst \nSynchronous\nMemory clock \ncycle (CLK) \n2\n17 \nTable 222. Nonmultiplexed I/O NOR flash\nFSMC signal name\nI/O\nFunction\nCLK \nO \nClock (for synchronous access) \nA[25:0] \nO \nAddress bus \nD[15:0] \nI/O \nBidirectional data bus \nNE[x]\nO \nChip select, x = 1..4\nNOE\nO \nOutput enable \nNWE\nO \nWrite enable \nNL(=NADV)\nO \nLatch enable (this signal is called address \nvalid, NADV, by some NOR flash devices) \nNWAIT\nI \nNOR flash wait input signal to the FSMC \n" }, { "page_number": 1554, "page_indices": { "start_index": 3064734, "end_index": 3066209 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1554 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.1 External memory interface signals", 1553 ], [ 4, "NOR flash, multiplexed I/Os", 1554 ], [ 4, "PSRAM/SRAM, nonmultiplexed I/Os", 1554 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1554/1757\nRM0090 Rev 21\nNOR flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 \naddress lines).\nNOR flash, multiplexed I/Os\n \nNOR-flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 \naddress lines).\nPSRAM/SRAM, nonmultiplexed I/Os\n \nPSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 \naddress lines).\nPSRAM, multiplexed I/Os\nTable 223. Multiplexed I/O NOR flash\nFSMC signal name \nI/O\nFunction \nCLK \nO \nClock (for synchronous access) \nA[25:16] \nO \nAddress bus \nAD[15:0] \nI/O \n16-bit multiplexed, bidirectional address/data bus\nNE[x]\nO \nChip select, x = 1..4\nNOE\nO \nOutput enable \nNWE\nO \nWrite enable \nNL(=NADV)\nO \nLatch enable (this signal is called address valid, NADV, by some NOR \nflash devices) \nNWAIT\nI \nNOR flash wait input signal to the FSMC \nTable 224. Nonmultiplexed I/Os PSRAM/SRAM\nFSMC signal name\nI/O \nFunction \nCLK \nO \nClock (only for PSRAM synchronous access) \nA[25:0] \nO \nAddress bus \nD[15:0] \nI/O \nData bidirectional bus \nNE[x]\nO \nChip select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))\nNOE\nO \nOutput enable \nNWE\nO \nWrite enable \nNL(= NADV)\nO \nAddress valid only for PSRAM input (memory signal name: NADV) \nNWAIT\nI \nPSRAM wait input signal to the FSMC \nNBL[1] \nO \nUpper byte enable (memory signal name: NUB) \nNBL[0] \nO \nLowed byte enable (memory signal name: NLB) \n" }, { "page_number": 1555, "page_indices": { "start_index": 3066209, "end_index": 3067839 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1555 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.2 Supported memories and transactions", 1555 ] ], "page_content": "RM0090 Rev 21\n1555/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \nPSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 \naddress lines).\n36.5.2 \nSupported memories and transactions\nTable 226 below displays an example of the supported devices, access modes and \ntransactions when the memory data bus is 16-bit for NOR, PSRAM and SRAM. \nTransactions not allowed (or not supported) by the FSMC in this example appear in gray.\n \nTable 225. Multiplexed I/O PSRAM\nFSMC signal name\nI/O \nFunction \nCLK \nO \nClock (for synchronous access) \nA[25:16] \nO \nAddress bus \nAD[15:0] \nI/O \n16-bit multiplexed, bidirectional address/data bus\nNE[x]\nO \nChip select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))\nNOE\nO \nOutput enable \nNWE\nO \nWrite enable \nNL(= NADV)\nO \nAddress valid PSRAM input (memory signal name: NADV) \nNWAIT\nI \nPSRAM wait input signal to the FSMC \nNBL[1] \nO \nUpper byte enable (memory signal name: NUB) \nNBL[0] \nO \nLowed byte enable (memory signal name: NLB) \nTable 226. NOR flash/PSRAM controller: example of supported memories and transactions\nDevice\nMode\nR/W\nAHB \ndata \nsize\nMemory \ndata size\nAllowed/\nnot \nallowed\nComments\nNOR flash\n(muxed I/Os and \nnonmuxed I/Os) \nAsynchronous\nR \n8 \n16 \nY \n-\nAsynchronous \nW \n8 \n16 \nN \n-\nAsynchronous\nR \n16 \n16 \nY \n-\nAsynchronous\nW \n16 \n16 \nY \n-\nAsynchronous \nR \n32 \n16 \nY \nSplit into two FSMC accesses \nAsynchronous \nW \n32 \n16 \nY \nSplit into two FSMC accesses \nAsynchronous page\nR \n-\n16 \nN \nMode is not supported \nSynchronous \nR \n8 \n16 \nN \n-\nSynchronous \nR \n16 \n16 \nY \n-\nSynchronous \nR \n32 \n16 \nY \n-\n" }, { "page_number": 1556, "page_indices": { "start_index": 3067839, "end_index": 3069367 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1556 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.3 General timing rules", 1556 ], [ 4, "Signals synchronization", 1556 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1556/1757\nRM0090 Rev 21\n36.5.3 \nGeneral timing rules\nSignals synchronization\n•\nAll controller output signals change on the rising edge of the internal clock (HCLK)\n•\nIn synchronous mode (read or write), all output signals change on the rising edge of \nHCLK. Whatever the CLKDIV value, all outputs change as follows:\n–\nNOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the \nfalling edge of FSMC_CLK clock.\n–\nNOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising \nedge of FSMC_CLK clock.\nPSRAM \n(multiplexed and \nnonmultiplexed \nI/Os)\nAsynchronous\nR \n8 \n16 \nY \n-\nAsynchronous \nW \n8 \n16 \nY \nUse of byte lanes NBL[1:0] \nAsynchronous\nR \n16 \n16 \nY \n-\nAsynchronous\nW \n16 \n16 \nY \n-\nAsynchronous \nR \n32 \n16 \nY \nSplit into two FSMC accesses \nAsynchronous \nW \n32 \n16 \nY \nSplit into two FSMC accesses \nAsynchronous page\nR \n-\n16 \nN \nMode is not supported \nSynchronous \nR \n8 \n16 \nN \n-\nSynchronous \nR \n16 \n16 \nY \n-\nSynchronous \nR \n32 \n16 \nY \n-\nSynchronous\nW\n8\n16\nY\nUse of byte lanes NBL[1:0]\nSynchronous\nW\n16 / 32\n16\nY\n-\nSRAM and ROM\nAsynchronous \nR \n8 / 16 \n16\nY \n-\nAsynchronous \nW \n8 / 16 \n16\nY \nUse of byte lanes NBL[1:0]\nAsynchronous \nR \n32 \n16\nY \nSplit into two FSMC accesses \nAsynchronous \nW \n32 \n16\nY \nSplit into two FSMC accesses. \nUse of byte lanes NBL[1:0]\nTable 226. NOR flash/PSRAM controller: example of supported memories and transactions \nDevice\nMode\nR/W\nAHB \ndata \nsize\nMemory \ndata size\nAllowed/\nnot \nallowed\nComments\n" }, { "page_number": 1557, "page_indices": { "start_index": 3069367, "end_index": 3070946 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1557 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "Asynchronous static memories (NOR flash memory, PSRAM, SRAM)", 1557 ], [ 4, "Mode 1 - SRAM/PSRAM (CRAM)", 1557 ] ], "page_content": "RM0090 Rev 21\n1557/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n36.5.4 \nNOR flash/PSRAM controller asynchronous transactions\nAsynchronous static memories (NOR flash memory, PSRAM, SRAM)\n•\nSignals are synchronized by the internal clock HCLK. This clock is not issued to the \nmemory\n•\nThe FSMC always samples the data before de-asserting the NOE signals. This \nguarantees that the memory data-hold timing constraint is met (chip enable high to \ndata transition, usually 0 ns min.)\n•\nIf the extended mode is enabled (EXTMOD bit is set in the FSMC_BCRx register), up \nto four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and \nD modes for read and write operations. For example, read operation can be performed \nin mode A and write in mode B.\n•\nIf the extended mode is disabled (EXTMOD bit is reset in the FSMC_BCRx register), \nthe FSMC can operate in Mode1 or Mode2 as follows:\n–\nMode 1 is the default mode when SRAM/PSRAM memory type is selected \n(MTYP[0:1] = 0x0 or 0x01 in the FSMC_BCRx register)\n–\nMode 2 is the default mode when NOR memory type is selected (MTYP[0:1] = \n0x10 in the FSMC_BCRx register).\nMode 1 - SRAM/PSRAM (CRAM)\nThe next figures show the read and write transactions for the supported modes followed by \nthe required configuration of FSMC _BCRx, and FSMC_BTRx/FSMC_BWTRx registers. \nFigure 436. Mode1 read accesses\n1.\nNBL[1:0] are driven low during read access.\nA[25:0]\nNOE\nADDSET\nDATAST \nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNBL[1:0]\ndata driven\nby memory\nai15557\nHigh\n" }, { "page_number": 1558, "page_indices": { "start_index": 3070946, "end_index": 3071999 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1558 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "Mode 1 - SRAM/PSRAM (CRAM)", 1557 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1558/1757\nRM0090 Rev 21\nFigure 437. Mode1 write accesses\nThe one HCLK cycle at the end of the write transaction helps guarantee the address and \ndata hold time after the NWE rising edge. Due to the presence of this one HCLK cycle, the \nDATAST value must be greater than zero (DATAST > 0).\n \nTable 227. FSMC_BCRx bit fields\nBit number\nBit name\nValue to set\n31-20\nReserved\n0x000\n19\nCBURSTRW\n0x0 (no effect on asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect on asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at 0.\n14\nEXTMOD\n0x0\n13\nWAITEN\n0x0 (no effect on asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0\n7 \nReserved\n0x1\n6 \nFACCEN\nDon’t care\n5-4 \nMWID\nAs needed\n3-2 \nMTYP[0:1]\nAs needed, exclude 0x2 (NOR flash)\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNBL[1:0]\ndata driven by FSMC\nai15558\n1HCLK\n" }, { "page_number": 1559, "page_indices": { "start_index": 3071999, "end_index": 3072937 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1559 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "Mode A - SRAM/PSRAM (CRAM) OE toggling", 1559 ] ], "page_content": "RM0090 Rev 21\n1559/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \nMode A - SRAM/PSRAM (CRAM) OE toggling\nFigure 438. ModeA read accesses\n1.\nNBL[1:0] are driven low during read access.\n1 \nMUXE\n0x0\n0 \nMBKEN \n0x1\nTable 228. FSMC_BTRx bit fields\nBit number\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\nDon’t care\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST+1 HCLK cycles for \nwrite accesses, DATAST HCLK cycles for read accesses). \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles).\nMinimum value for ADDSET is 0.\nTable 227. FSMC_BCRx bit fields (continued)\nBit number\nBit name\nValue to set\nA[25:0]\nNOE\nADDSET \nDATAST\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNBL[1:0]\ndata driven\nby memory\nai15559\nHigh\n" }, { "page_number": 1560, "page_indices": { "start_index": 3072937, "end_index": 3073867 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1560 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "Mode A - SRAM/PSRAM (CRAM) OE toggling", 1559 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1560/1757\nRM0090 Rev 21\nFigure 439. ModeA write accesses\nThe differences compared with mode1 are the toggling of NOE and the independent read \nand write timings.\n \nTable 229. FSMC_BCRx bit fields\nBit \nnumber\nBit name \nValue to set\n31-20\nReserved\n0x000\n19\nCBURSTRW\n0x0 (no effect on asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect on asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at \n0.\n14 \nEXTMOD\n0x1\n13\nWAITEN\n0x0 (no effect on asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0\n7 \nReserved\n0x1\n6 \nFACCEN\nDon’t care\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[0:1]\nAs needed, exclude 0x2 (NOR flash)\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNBL[1:0]\ndata driven by FSMC\nai15560\n1HCLK\n" }, { "page_number": 1561, "page_indices": { "start_index": 3073867, "end_index": 3074992 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1561 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "Mode A - SRAM/PSRAM (CRAM) OE toggling", 1559 ] ], "page_content": "RM0090 Rev 21\n1561/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \n \n1 \nMUXEN\n0x0\n0 \nMBKEN\n0x1\nTable 230. FSMC_BTRx bit fields\nBit \nnumber\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x0\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for \nread accesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for read \naccesses.\nMinimum value for ADDSET is 0.\nTable 231. FSMC_BWTRx bit fields\nBit \nnumber\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x0\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST+1 HCLK cycles for \nwrite accesses, \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for write \naccesses.\nMinimum value for ADDSET is 0.\nTable 229. FSMC_BCRx bit fields (continued)\nBit \nnumber\nBit name \nValue to set\n" }, { "page_number": 1562, "page_indices": { "start_index": 3074992, "end_index": 3075443 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1562 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "Mode 2/B - NOR flash", 1562 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1562/1757\nRM0090 Rev 21\nMode 2/B - NOR flash\nFigure 440. Mode2 and mode B read accesses\nFigure 441. Mode2 write accesses\nA[25:0]\nNOE\nADDSET \nDATAST\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven\nby memory\nai15561\nHigh\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven by FSMC\nai15562\n1HCLK\n" }, { "page_number": 1563, "page_indices": { "start_index": 3075443, "end_index": 3076376 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1563 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "Mode 2/B - NOR flash", 1562 ] ], "page_content": "RM0090 Rev 21\n1563/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nFigure 442. Mode B write accesses \nThe differences with mode1 are the toggling of NWE and the independent read and write \ntimings when extended mode is set (Mode B).\n \nTable 232. FSMC_BCRx bit fields\nBit \nnumber\nBit name \nValue to set \n31-20\nReserved\n0x000\n19\nCBURSTRW\n0x0 (no effect on asynchronous mode)\n18:16\nReserved\n0x0 (no effect on asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at \n0.\n14 \nEXTMOD\n0x1 for mode B, 0x0 for mode 2\n13\nWAITEN\n0x0 (no effect on asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0 \n7 \nReserved\n0x1\n6 \nFACCEN\n0x1\n5-4 \nMWID \nAs needed\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven by FSMC\nai15563\n1HCLK\n" }, { "page_number": 1564, "page_indices": { "start_index": 3076376, "end_index": 3077657 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1564 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "Mode 2/B - NOR flash", 1562 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1564/1757\nRM0090 Rev 21\n \n \nNote:\nThe FSMC_BWTRx register is valid only if extended mode is set (mode B), otherwise all its \ncontent is don’t care.\n3-2 \nMTYP[0:1]\n0x2 (NOR flash memory)\n1 \nMUXEN\n0x0 \n0 \nMBKEN\n0x1 \nTable 233. FSMC_BTRx bit fields\nBit \nnumber\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x1\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for \nread accesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for read \naccesses.\nMinimum value for ADDSET is 0.\nTable 234. FSMC_BWTRx bit fields\nBit \nnumber\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x1\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST+1 HCLK cycles for \nwrite accesses, \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for write \naccesses.\nMinimum value for ADDSET is 0.\nTable 232. FSMC_BCRx bit fields (continued)\nBit \nnumber\nBit name \nValue to set \n" }, { "page_number": 1565, "page_indices": { "start_index": 3077657, "end_index": 3078226 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1565 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "Mode C - NOR flash - OE toggling", 1565 ] ], "page_content": "RM0090 Rev 21\n1565/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nMode C - NOR flash - OE toggling\nFigure 443. Mode C read accesses \nFigure 444. Mode C write accesses \nThe differences compared with mode1 are the toggling of NOE and the independent read \nand write timings.\nA[25:0]\nNOE\nADDSET \nDATAST\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven\nby memory\nai15564\nHigh\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven by FSMC\nai15565\n1HCLK\n" }, { "page_number": 1566, "page_indices": { "start_index": 3078226, "end_index": 3079329 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1566 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "Mode C - NOR flash - OE toggling", 1565 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1566/1757\nRM0090 Rev 21\n \n \nTable 235. FSMC_BCRx bit fields\nBit No.\nBit name\nValue to set\n31-20\nReserved\n0x000\n19\nCBURSTRW\n0x0 (no effect on asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect on asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep \nat 0.\n14 \nEXTMOD\n0x1\n13\nWAITEN\n0x0 (no effect on asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0 \n7 \nReserved\n0x1\n6 \nFACCEN\n0x1\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[0:1]\n0x2 (NOR flash memory)\n1 \nMUXEN\n0x0\n0 \nMBKEN\n0x1\nTable 236. FSMC_BTRx bit fields\nBit \nnumber\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x2\n27-24\nDATLAT\n0x0\n23-20\nCLKDIV\n0x0\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for \nread accesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for read \naccesses.\nMinimum value for ADDSET is 0.\n" }, { "page_number": 1567, "page_indices": { "start_index": 3079329, "end_index": 3080131 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1567 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "Mode D - asynchronous access with extended address", 1567 ] ], "page_content": "RM0090 Rev 21\n1567/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \n \nMode D - asynchronous access with extended address\nFigure 445. Mode D read accesses\nTable 237. FSMC_BWTRx bit fields\nBit \nnumber\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x2\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST+1 HCLK cycles for \nwrite accesses, \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for write \naccesses.\nMinimum value for ADDSET is 0.\nA[25:0]\nNOE\nADDSET \nDATAST\nMemory transaction\nNEx\nD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven\nby memory\nai15566\nHigh\nADDHLD\nHCLK cycles\n" }, { "page_number": 1568, "page_indices": { "start_index": 3080131, "end_index": 3080926 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1568 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "Mode D - asynchronous access with extended address", 1567 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1568/1757\nRM0090 Rev 21\nFigure 446. Mode D write accesses\nThe differences with mode1 are the toggling of NOE that goes on toggling after NADV \nchanges and the independent read and write timings.\n \nTable 238. FSMC_BCRx bit fields\nBit No.\nBit name \nValue to set \n31-20\nReserved\n0x000\n19\nCBURSTRW\n0x0 (no effect on asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect on asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep \nat 0.\n14 \nEXTMOD\n0x1\n13\nWAITEN\n0x0 (no effect on asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0 \n7 \nReserved\n0x1\n6 \nFACCEN\nSet according to memory support\n5-4 \nMWID\nAs needed\n" }, { "page_number": 1569, "page_indices": { "start_index": 3080926, "end_index": 3082177 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1569 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "Mode D - asynchronous access with extended address", 1567 ] ], "page_content": "RM0090 Rev 21\n1569/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \n \n3-2 \nMTYP[0:1]\nAs needed\n1 \nMUXEN\n0x0 \n0 \nMBKEN\n0x1 \nTable 239. FSMC_BTRx bit fields\nBit No.\nBit name\nValue to set \n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x3\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for \nread accesses. \n7-4\nADDHLD\nDuration of the middle phase of the read access (ADDHLD HCLK \ncycles) \n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for read \naccesses. Minimum value for ADDSET is 0.\nTable 240. FSMC_BWTRx bit fields\nBit No.\nBit name\nValue to set \n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x3\n27-24\nDATLAT\n0x0\n23-20\nCLKDIV\n0x0\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST+1 HCLK cycles) for \nwrite accesses\n7-4\nADDHLD\nDuration of the middle phase of the write access (ADDHLD HCLK \ncycles) \n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET+1 HCLK cycles) for \nwrite accesses. Minimum value for ADDSET is 0.\nTable 238. FSMC_BCRx bit fields (continued)\nBit No.\nBit name \nValue to set \n" }, { "page_number": 1570, "page_indices": { "start_index": 3082177, "end_index": 3082666 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1570 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "Muxed mode - multiplexed asynchronous access to NOR flash memory", 1570 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1570/1757\nRM0090 Rev 21\nMuxed mode - multiplexed asynchronous access to NOR flash memory\nFigure 447. Multiplexed read accesses\nFigure 448. Multiplexed write accesses\nThe difference with mode D is the drive of the lower address byte(s) on the databus.\nA[25:16]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nAD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven by FSMC\nai15569\n1HCLK\nADDHLD\nHCLK cycles\nLower address\n" }, { "page_number": 1571, "page_indices": { "start_index": 3082666, "end_index": 3084082 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1571 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "WAIT management in asynchronous accesses", 1571 ] ], "page_content": "RM0090 Rev 21\n1571/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \n \nWAIT management in asynchronous accesses\nIf the asynchronous memory asserts a WAIT signal to indicate that it is not yet ready to \naccept or to provide data, the ASYNCWAIT bit has to be set in FSMC_BCRx register.\nTable 241. FSMC_BCRx bit fields\nBit No.\nBit name\nValue to set\n31-21\nReserved\n0x000\n19\nCBURSTRW\n0x0 (no effect on asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect on asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at \n0.\n14 \nEXTMOD\n0x0\n13\nWAITEN\n0x0 (no effect on asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care \n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0 \n7 \nReserved\n0x1\n6 \nFACCEN\n0x1\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[0:1] \n0x2 (NOR flash memory)\n1 \nMUXEN\n0x1\n0 \nMBKEN\n0x1 \nTable 242. FSMC_BTRx bit fields\nBit No.\nBit name \nValue to set \n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x0\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles for \nread accesses and DATAST+1 HCLK cycles for write accesses). \n7-4\nADDHLD\nDuration of the middle phase of the access (ADDHLD HCLK cycles).\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles). \nMinimum value for ADDSET is 1.\n" }, { "page_number": 1572, "page_indices": { "start_index": 3084082, "end_index": 3085469 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1572 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "WAIT management in asynchronous accesses", 1571 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1572/1757\nRM0090 Rev 21\nIf the WAIT signal is active (high or low depending on the WAITPOL bit), the second access \nphase (Data setup phase) programmed by the DATAST bits, is extended until WAIT \nbecomes inactive. Unlike the data setup phase, the first access phases (Address setup and \nAddress hold phases), programmed by the ADDSET[3:0] and ADDHLD bits, are not WAIT \nsensitive and so they are not prolonged.\nThe data setup phase (DATAST in the FSMC_BTRx register) must be programmed so that \nWAIT can be detected 4 HCLK cycles before the end of memory transaction. The following \ncases must be considered:\n1.\nDATAST in FSMC_BTRx register) Memory asserts the WAIT signal aligned to \nNOE/NWE which toggles: \n2. \nMemory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):\nif \nthen \notherwise \nwhere max_wait_assertion_time is the maximum time taken by the memory to assert \nthe WAIT signal once NEx/NOE/NWE is low.\nFigure 449 and Figure 450 show the number of HCLK clock cycles that are added to the \nmemory access after WAIT is released by the asynchronous memory (independently of the \nabove cases).\nDATAST\n4\nHCLK\n×\n(\n)\nmax_wait_assertion_time\n+\n≥\nmax_wait_assertion_time\naddress_phase\nhold_phase\n+\n>\nDATAST\n4\nHCLK\n×\n(\n)\nmax_wait_assertion_time\naddress_phase\n–\nhold_phase\n–\n(\n)\n+\n≥\nDATAST\n4\nHCLK\n×\n≥\n" }, { "page_number": 1573, "page_indices": { "start_index": 3085469, "end_index": 3086107 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1573 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.4 NOR flash/PSRAM controller asynchronous transactions", 1557 ], [ 4, "WAIT management in asynchronous accesses", 1571 ] ], "page_content": "RM0090 Rev 21\n1573/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nFigure 449. Asynchronous wait during a read access \n1.\nNWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register. \nFigure 450. Asynchronous wait during a write access \n1.\nNWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register. \nA[25:0]\nNOE\n4HCLK \nMemory transaction\nNWAIT\nD[15:0]\nNEx\ndata driven \nby memory\nai18471b\naddress phase\ndon’t care\ndata setup phase\ndon’t care\nA[25:0]\nNWE\nMemory transaction\nNWAIT\nD[15:0]\nNEx\ndata driven by FSMC\nai15797c\n3HCLK \naddress phase\ndata setup phase\n1HCLK \ndon’t care\ndon’t care\n" }, { "page_number": 1574, "page_indices": { "start_index": 3086107, "end_index": 3089076 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1574 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.5 Synchronous transactions", 1574 ], [ 4, "Data latency versus NOR flash latency", 1574 ], [ 4, "Single-burst transfer", 1574 ], [ 4, "Cross boundary page for Cellular RAM 1.5", 1574 ], [ 4, "Wait management", 1574 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1574/1757\nRM0090 Rev 21\n36.5.5 \nSynchronous transactions\nThe memory clock, CLK, is a submultiple of HCLK according to the value of parameter \nCLKDIV.\nNOR flash memories specify a minimum time from NADV assertion to CLK high. To meet \nthis constraint, the FSMC does not issue the clock to the memory during the first internal \nclock cycle of the synchronous access (before NADV assertion). This guarantees that the \nrising edge of the memory clock occurs in the middle of the NADV low pulse.\nData latency versus NOR flash latency\nThe data latency is the number of cycles to wait before sampling the data. The DATLAT \nvalue must be consistent with the latency value specified in the NOR flash configuration \nregister. The FSMC does not include the clock cycle when NADV is low in the data latency \ncount.\nCaution:\nSome NOR flash memories include the NADV Low cycle in the data latency count, so the \nexact relation between the latency and the FMSC DATLAT parameter can be either of:\n•\nNOR flash latency = (DATLAT + 2) CLK clock cycles\n•\nNOR flash latency = (DATLAT + 3) CLK clock cycles\nSome recent memories assert NWAIT during the latency phase. In such cases DATLAT can \nbe set to its minimum value. As a result, the FSMC samples the data and waits long enough \nto evaluate if the data are valid. Thus the FSMC detects when the memory exits latency and \nreal data are taken.\nOther memories do not assert NWAIT during latency. In this case the latency must be set \ncorrectly for both the FSMC and the memory, otherwise invalid data are mistaken for good \ndata, or valid data are lost in the initial phase of the memory access.\nSingle-burst transfer\nWhen the selected bank is configured in burst mode for synchronous accesses, if for \nexample an AHB single-burst transaction is requested on 16-bit memories, the FSMC \nperforms a burst transaction of length 1 (if the AHB transfer is 16-bit), or length 2 (if the AHB \ntransfer is 32-bit) and de-assert the chip select signal when the last data is strobed.\nClearly, such a transfer is not the most efficient in terms of cycles (compared to an \nasynchronous read). Nevertheless, a random asynchronous access would first require to re-\nprogram the memory access mode, which would altogether last longer.\nCross boundary page for Cellular RAM 1.5\nCellular RAM 1.5 does not allow burst access to cross the page boundary. The FSMC \ncontroller allows to split automatically the burst access when the memory page size is \nreached by configuring the CPSIZE bits in the FSMC_BCR1 register following the memory \npage size.\nWait management\nFor synchronous NOR flash memories, NWAIT is evaluated after the programmed latency \nperiod, (DATLAT+2) CLK clock cycles.\nIf NWAIT is sensed active (low level when WAITPOL = 0, high level when WAITPOL = 1), \nwait states are inserted until NWAIT is sensed inactive (high level when WAITPOL = 0, low \nlevel when WAITPOL = 1).\n" }, { "page_number": 1575, "page_indices": { "start_index": 3089076, "end_index": 3090154 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1575 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.5 Synchronous transactions", 1574 ], [ 4, "Wait management", 1574 ] ], "page_content": "RM0090 Rev 21\n1575/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nWhen NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1) \nor on the next clock edge (bit WAITCFG = 0).\nDuring wait-state insertion via the NWAIT signal, the controller continues to send clock \npulses to the memory, keeping the chip select and output enable signals valid, and does not \nconsider the data valid.\nThere are two timing configurations for the NOR flash NWAIT signal in burst mode:\n•\nFlash memory asserts the NWAIT signal one data cycle before the wait state (default \nafter reset)\n•\nFlash memory asserts the NWAIT signal during the wait state\nThese two NOR flash wait state configurations are supported by the FSMC, individually for \neach chip select, thanks to the WAITCFG bit in the FSMC_BCRx registers (x = 0..3).\nFigure 451. Wait configurations\naaddr[15:0]\ndata\ndata\naddr[25:16]\nMemory transaction = burst of 4 half words\nHCLK\nCLK\nA[25:16]\nNADV\nNWAIT\n(WAITCFG = 1)\nA/D[15:0]\ninserted wait state\ndata\nNWAIT\n(WAITCFG = 0)\nai15798b\n" }, { "page_number": 1576, "page_indices": { "start_index": 3090154, "end_index": 3091268 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1576 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.5 Synchronous transactions", 1574 ], [ 4, "Wait management", 1574 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1576/1757\nRM0090 Rev 21\nFigure 452. Synchronous multiplexed read mode - NOR, PSRAM (CRAM)\n1.\nByte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, \nthey are held low. \n2.\nNWAIT polarity is set to 0.\n \nTable 243. FSMC_BCRx bit fields\nBit No.\nBit name\nValue to set\n31-20\nReserved\n0x000\n19\nCBURSTRW\nNo effect on synchronous read\n18-16\nCPSIZE\nAs needed (0x1 for CRAM 1.5)\n15\nASCYCWAIT\n0x0\n14 \nEXTMOD\n0x0\n13\nWAITEN\nSet to 1 if the memory supports this feature, otherwise keep at 0.\n12\nWREN\nno effect on synchronous read\n11\nWAITCFG\nto be set according to memory\n10\nWRAPMOD\n0x0\n9 \nWAITPOL\nto be set according to memory\n8 \nBURSTEN\n0x1\n7 \nReserved\n0x1\n6 \nFACCEN\nSet according to memory support (NOR flash memory)\n5-4 \nMWID \nAs needed\nAddr[15:0]\ndata\ndata\naddr[25:16]\nMemory transaction = burst of 4 half words\nHCLK\nCLK\nA[25:16]\nNEx\nNOE\nNWE\nHigh\nNADV\nNWAIT\n(WAITCFG=\n0)\nA/D[15:0]\n1 clock\ncycle\n1 clock\ncycle\n(DATLAT + 2)\ninserted wait state\nData strobes\nai17723f\nCLK cycles\ndata\ndata\nData strobes\n" }, { "page_number": 1577, "page_indices": { "start_index": 3091268, "end_index": 3091849 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1577 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.5 Synchronous transactions", 1574 ], [ 4, "Wait management", 1574 ] ], "page_content": "RM0090 Rev 21\n1577/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \n3-2 \nMTYP[0:1]\n0x1 or 0x2\n1 \nMUXEN\nAs needed\n0 \nMBKEN\n0x1 \nTable 244. FSMC_BTRx bit fields\nBit No.\nBit name\nValue to set\n31:30\nReserved\n0x0\n29:28\nACCMOD\n0x0\n27-24\nDATLAT\nData latency\n23-20\nCLKDIV\n0x0 to get CLK = HCLK (not supported)\n0x1 to get CLK = 2 × HCLK\n..\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK)\n15-8\nDATAST\nDon’t care\n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDon’t care\nTable 243. FSMC_BCRx bit fields (continued)\nBit No.\nBit name\nValue to set\n" }, { "page_number": 1578, "page_indices": { "start_index": 3091849, "end_index": 3092727 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1578 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.5 Synchronous transactions", 1574 ], [ 4, "Wait management", 1574 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1578/1757\nRM0090 Rev 21\nFigure 453. Synchronous multiplexed write mode - PSRAM (CRAM)\n1.\nMemory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.\n2.\nNWAIT polarity is set to 0.\n3.\nByte Lane (NBL) outputs are not shown, they are held low while NEx is active.\nAddr[15:0]\ndata\naddr[25:16]\nMemory transaction = burst of 2 half words\nHCLK\nCLK\nA[25:16]\nNEx\nNOE\nNWE\nHi-Z\nNADV\nNWAIT\n(WAITCFG = 0)\nA/D[15:0]\n1 clock 1 clock\n(DATLAT + 2)\ninserted wait state\nai14731f\n CLK cycles\ndata\nTable 245. FSMC_BCRx bit fields\nBit No.\nBit name\nValue to set\n31-20\nReserved\n0x000\n19\nCBURSTRW\n0x1\n18-16\nCPSIZE\nAs needed (0x1 for CRAM 1.5)\n15\nASCYCWAIT\n0x0\n14 \nEXTMOD\n0x0\n13\nWAITEN\nSet to 1 if the memory supports this feature, otherwise keep at 0.\n12\nWREN\n0x1\n11\nWAITCFG\n0x0\n10\nWRAPMOD\n0x0\n" }, { "page_number": 1579, "page_indices": { "start_index": 3092727, "end_index": 3093461 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1579 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.5 Synchronous transactions", 1574 ], [ 4, "Wait management", 1574 ] ], "page_content": "RM0090 Rev 21\n1579/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \n9 \nWAITPOL\nto be set according to memory\n8 \nBURSTEN\nno effect on synchronous write\n7 \nReserved\n0x1\n6 \nFACCEN\nSet according to memory support\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[0:1]\n0x1\n1 \nMUXEN\nAs needed\n0 \nMBKEN\n0x1 \nTable 246. FSMC_BTRx bit fields\nBit No.\nBit name\nValue to set\n31:30\nReserved\n0x0\n29:28\nACCMOD\n0x0\n27-24\nDATLAT\nData latency\n23-20\nCLKDIV\n0x0 to get CLK = HCLK (not supported)\n0x1 to get CLK = 2 × HCLK\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDon’t care\n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDon’t care\nTable 245. FSMC_BCRx bit fields (continued)\nBit No.\nBit name\nValue to set\n" }, { "page_number": 1580, "page_indices": { "start_index": 3093461, "end_index": 3095479 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1580 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.6 NOR/PSRAM control registers", 1580 ], [ 4, "SRAM/NOR-flash chip-select control registers 1..4 (FSMC_BCR1..4)", 1580 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1580/1757\nRM0090 Rev 21\n36.5.6 \nNOR/PSRAM control registers\nThe NOR/PSRAM control registers have to be accessed by words (32 bits).\nSRAM/NOR-flash chip-select control registers 1..4 (FSMC_BCR1..4)\nAddress offset: 0xA000 0000 + 8 * (x – 1), x = 1...4\nReset value: 0x0000 30DB for Bank1 and 0x0000 30D2 for Bank 2 to 4\nThis register contains the control information of each memory bank, used for SRAMs, \nPSRAM and NOR flash memories.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCBURSTRW\nCPSIZE[2:0]\nASCYCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[1:0]\nMUXEN\nMBKEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31: 20 Reserved, must be kept at reset value.\nBit 19 CBURSTRW: Write burst enable.\nFor Cellular RAM (PSRAM) memories, this bit enables the synchronous burst protocol \nduring write operations. The enable bit for synchronous read accesses is the BURSTEN \nbit in the FSMC_BCRx register.\n0: Write operations are always performed in asynchronous mode\n1: Write operations are performed in synchronous mode.\nBits 18: 16 CPSIZE[2:0]: CRAM page size.\nThese are used for Cellular RAM 1.5 which does not allow burst access to cross the \naddress boundaries between pages. When these bits are configured, the FSMC \ncontroller splits automatically the burst access when the memory page size is reached \n(refer to memory datasheet for page size).\n000: No burst split when crossing page boundary (default after reset)\n001: 128 bytes\n010: 256 bytes\n011: 512 bytes\n100: 1024 bytes\nOthers: reserved.\nBit 15 ASYNCWAIT: Wait signal during asynchronous transfers\nThis bit enables/disables the FSMC to use the wait signal even during an asynchronous \nprotocol.\n0: NWAIT signal is not taken into account when running an asynchronous protocol \n(default after reset)\n1: NWAIT signal is taken into account when running an asynchronous protocol\n" }, { "page_number": 1581, "page_indices": { "start_index": 3095479, "end_index": 3098385 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1581 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.6 NOR/PSRAM control registers", 1580 ], [ 4, "SRAM/NOR-flash chip-select control registers 1..4 (FSMC_BCR1..4)", 1580 ] ], "page_content": "RM0090 Rev 21\n1581/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nBit 14 EXTMOD: Extended mode enable.\nThis bit enables the FSMC to program the write timings for non-multiplexed \nasynchronous accesses inside the FSMC_BWTR register, thus resulting in different \ntimings for read and write operations.\n0: values inside FSMC_BWTR register are not taken into account (default after reset)\n1: values inside FSMC_BWTR register are taken into account\nNote: When the extended mode is disabled, the FSMC can operate in Mode1 or Mode2 \nas follows:\n–\nMode 1 is the default mode when the SRAM/PSRAM memory type is selected \n(MTYP [0:1]=0x0 or 0x01)\n–\nMode 2 is the default mode when the NOR memory type is selected \n(MTYP [0:1]= 0x10).\nBit 13 WAITEN: Wait enable bit.\nThis bit enables/disables wait-state insertion via the NWAIT signal when accessing the \nflash memory in synchronous mode.\n0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after \nthe programmed flash latency period)\n1: NWAIT signal is enabled (its level is taken into account after the programmed flash \nlatency period to insert wait states if asserted) (default after reset)\nBit 12 WREN: Write enable bit.\nThis bit indicates whether write operations are enabled/disabled in the bank by the \nFSMC:\n0: Write operations are disabled in the bank by the FSMC, an AHB error is reported,\n1: Write operations are enabled for the bank by the FSMC (default after reset).\nBit 11 WAITCFG: Wait timing configuration.\nThe NWAIT signal indicates whether the data from the memory are valid or if a wait state \nmust be inserted when accessing the flash memory in synchronous mode. This \nconfiguration bit determines if NWAIT is asserted by the memory one clock cycle before \nthe wait state or during the wait state:\n0: NWAIT signal is active one data cycle before wait state (default after reset),\n1: NWAIT signal is active during wait state (not used for PRAM).\nBit 10 WRAPMOD: Wrapped burst mode support.\nDefines whether the controller splits or not an AHB burst wrap access into two linear \naccesses. Valid only when accessing memories in burst mode\n0: Direct wrapped burst is not enabled (default after reset),\n1: Direct wrapped burst is enabled.\nNote: This bit has no effect as the CPU and DMA cannot generate wrapping burst \ntransfers.\nBit 9 WAITPOL: Wait signal polarity bit.\nDefines the polarity of the wait signal from memory. Valid only when accessing the \nmemory in burst mode:\n0: NWAIT active low (default after reset),\n1: NWAIT active high.\nBit 8 BURSTEN: Burst enable bit.\nThis bit enables/disables synchronous accesses during read operations. It is valid only \nfor synchronous memories operating in burst mode:\n0: Burst mode disabled (default after reset). Read accesses are performed in \nasynchronous mode. \n1: Burst mode enable. Read accesses are performed in synchronous mode. \n" }, { "page_number": 1582, "page_indices": { "start_index": 3098385, "end_index": 3099713 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1582 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.6 NOR/PSRAM control registers", 1580 ], [ 4, "SRAM/NOR-flash chip-select control registers 1..4 (FSMC_BCR1..4)", 1580 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1582/1757\nRM0090 Rev 21\nBit 7 Reserved, must be kept at reset value.\nBit 6 FACCEN: Flash access enable\nEnables NOR flash memory access operations.\n0: Corresponding NOR flash memory access is disabled\n1: Corresponding NOR flash memory access is enabled (default after reset)\nBits 5:4 MWID[1:0]: Memory databus width.\nDefines the external memory device width, valid for all type of memories.\n00: 8 bits,\n01: 16 bits (default after reset),\n10: reserved, do not use,\n11: reserved, do not use.\nBits 3:2 MTYP[1:0]: Memory type.\nDefines the type of external memory attached to the corresponding memory bank:\n00: SRAM (default after reset for Bank 2...4)\n01: PSRAM (CRAM)\n10: NOR flash/OneNAND flash (default after reset for Bank 1)\n11: reserved\nBit 1 MUXEN: Address/data multiplexing enable bit.\nWhen this bit is set, the address and data values are multiplexed on the databus, valid \nonly with NOR and PSRAM memories:\n0: Address/Data nonmultiplexed\n1: Address/Data multiplexed on databus (default after reset)\nBit 0 MBKEN: Memory bank enable bit.\nEnables the memory bank. After reset Bank1 is enabled, all others are disabled. \nAccessing a disabled bank causes an ERROR on AHB bus.\n0: Corresponding memory bank is disabled\n1: Corresponding memory bank is enabled\n" }, { "page_number": 1583, "page_indices": { "start_index": 3099713, "end_index": 3102257 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1583 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.6 NOR/PSRAM control registers", 1580 ], [ 4, "SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4)", 1583 ] ], "page_content": "RM0090 Rev 21\n1583/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nSRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4)\nAddress offset: 0xA000 0000 + 0x04 + 8 * (x – 1), x = 1..4\nReset value: 0x0FFF FFFF\nFSMC_BTRx bits are written by software to add a delay at the end of a read /write \ntransaction. This delay allows matching the minimum time between consecutive \ntransactions (tEHEL from NEx high to FSMC_NEx low) and the maximum time required by \nthe memory to free the data bus after a read access (tEHQZ).\nThis register contains the control information of each memory bank, used for SRAMs, \nPSRAM and NOR flash memories.If the EXTMOD bit is set in the FSMC_BCRx register, \nthen this register is partitioned for write and read access, that is, 2 registers are available: \none to configure read accesses (this register) and one to configure write accesses \n(FSMC_BWTRx registers).\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0]\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30\nReserved, must be kept at reset value.\nBits 29:28 ACCMOD[1:0]: Access mode\nSpecifies the asynchronous access modes as shown in the timing diagrams. These bits are \ntaken into account only when the EXTMOD bit in the FSMC_BCRx register is 1.\n00: access mode A\n01: access mode B\n10: access mode C\n11: access mode D\nBits 27:24 DATLAT[3:0]: Data latency for synchronous memory (see note below bit description table)\nFor synchronous accesses with read/write burst mode enabled (BURSTEN / CBURSTRW bits \nset), this field defines the number of memory clock cycles (+2) to issue to the memory before \nreading/writing the first data. This timing parameter is not expressed in HCLK periods, but in \nFSMC_CLK periods. For asynchronous accesses, this value is don't care. \n0000: Data latency of 2 CLK clock cycles for first burst access\n1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)\nBits 23:20 CLKDIV[3:0]: Clock divide ratio (for FSMC_CLK signal)\nDefines the period of FSMC_CLK clock output signal, expressed in number of HCLK cycles:\n0000: Reserved\n0001: FSMC_CLK period = 2 × HCLK periods\n0010: FSMC_CLK period = 3 × HCLK periods\n1111: FSMC_CLK period = 16 × HCLK periods (default value after reset) \nIn asynchronous NOR flash, SRAM or PSRAM accesses, this value is don’t care.\n" }, { "page_number": 1584, "page_indices": { "start_index": 3102257, "end_index": 3104459 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1584 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.6 NOR/PSRAM control registers", 1580 ], [ 4, "SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4)", 1583 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1584/1757\nRM0090 Rev 21\nBits 19:16 BUSTURN[3:0]: Bus turnaround phase duration\nThese bits are written by software to add a delay at the end of a write-to-read (and read-to \nwrite) transaction. The programmed bus turnaround delay is inserted between an \nasynchronous read (muxed or D mode) or a write transaction and any other \nasynchronous/synchronous read or write to/from a static bank (for a read operation, the bank \ncan be the same or a different one; for a write operation, the bank can be different except in r \nmuxed or D mode).\nIn some cases, the bus turnaround delay is fixed, whatever the programmed BUSTURN \nvalues: \n– No bus turnaround delay is inserted between two consecutive asynchronous write transfers \nto the same static memory bank except in muxed and D mode.\n– A bus turnaround delay of 1 FSMC clock cycle is inserted between:\n–\nTwo consecutive asynchronous read transfers to the same static memory bank \nexcept for muxed and D modes. \n–\nAn asynchronous read to an asynchronous or synchronous write to any static bank \nor dynamic bank except for muxed and D modes.\n–\nAn asynchronous (modes 1, 2, A, B or C) read and a read operation from another \nstatic bank.\n– A bus turnaround delay of 2 FSMC clock cycles is inserted between:\n–\nTwo consecutive synchronous write accesses (in burst or single mode) to the same \nbank\n–\nA synchronous write (burst or single) access and an asynchronous write or read \ntransfer to or from static memory bank (the bank can be the same or different in case \nof a read operation). \n–\nTwo consecutive synchronous read accesses (in burst or single mode) followed by a \nany synchronous/asynchronous read or write from/to another static memory bank.\n– A bus turnaround delay of 3 FSMC clock cycles is inserted between:\n–\nTwo consecutive synchronous write operations (in burst or single mode) to different \nstatic banks.\n–\nA synchronous write access (in burst or single mode) and a synchronous read \naccess from the same or to a different bank.\n0000: BUSTURN phase duration = 0 HCLK clock cycle added\n...\n1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)\n" }, { "page_number": 1585, "page_indices": { "start_index": 3104459, "end_index": 3107053 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1585 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.6 NOR/PSRAM control registers", 1580 ], [ 4, "SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4)", 1583 ] ], "page_content": "RM0090 Rev 21\n1585/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nNote:\nPSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these \nmemories issue the NWAIT signal during the whole latency phase to prolong the latency as \nneeded.\nWith PSRAMs (CRAMs) the DATLAT field must be set to 0, so that the FSMC exits its \nlatency phase soon and starts sampling NWAIT from memory, then starts to read or write \nwhen the memory is ready.\nThis method can be used also with the latest generation of synchronous flash memories that \nissue the NWAIT signal, unlike older flash memories (check the datasheet of the specific \nflash memory being used).\nBits 15:8 DATAST[7:0]: Data-phase duration\nThese bits are written by software to define the duration of the data phase (refer to Figure 436 \nto Figure 448), used in asynchronous accesses:\n0000 0000: Reserved\n0000 0001: DATAST phase duration = 1 × HCLK clock cycles\n0000 0010: DATAST phase duration = 2 × HCLK clock cycles\n...\n1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)\nFor each memory type and access mode data-phase duration, refer to the respective figure \n(Figure 436 to Figure 448).\nExample: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock \ncycles.\nNote: In synchronous accesses, this value is don't care.\nBits 7:4 ADDHLD[3:0]: Address-hold phase duration\nThese bits are written by software to define the duration of the address hold phase (refer to \nFigure 445 to Figure 448), used in mode D and multiplexed accesses:\n0000: Reserved\n0001: ADDHLD phase duration =1 × HCLK clock cycle\n0010: ADDHLD phase duration = 2 × HCLK clock cycle\n...\n1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)\nFor each access mode address-hold phase duration, refer to the respective figure (Figure 445 \nto Figure 448).\nNote: In synchronous accesses, this value is not used, the address hold phase is always 1 \nmemory clock period duration.\nBits 3:0 ADDSET[3:0]: Address setup phase duration\nThese bits are written by software to define the duration of the address setup phase (refer to \nFigure 436 to Figure 448), used in SRAMs, ROMs and asynchronous NOR flash and PSRAM \naccesses:\n0000: ADDSET phase duration = 0 × HCLK clock cycle\n...\n1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)\nFor each access mode address setup phase duration, refer to the respective figure (refer to \nFigure 436 to Figure 448).\nNote: In synchronous NOR flash and PSRAM accesses, this value is don’t care.\n" }, { "page_number": 1586, "page_indices": { "start_index": 3107053, "end_index": 3109495 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1586 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.5 NOR flash/PSRAM controller", 1552 ], [ 3, "36.5.6 NOR/PSRAM control registers", 1580 ], [ 4, "SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4)", 1586 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1586/1757\nRM0090 Rev 21\nSRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4)\nAddress offset: 0xA000 0000 + 0x104 + 8 * (x – 1), x = 1...4\nReset value: 0x0FFF FFFF\nThis register contains the control information of each memory bank, used for SRAMs, \nPSRAMs and NOR flash memories. This register is active for write asynchronous access \nonly when the EXTMOD bit is set in the FSMC_BCRx register.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRes.\nACCM\nOD[2:0]\nReserved\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30\nReserved, must be kept at reset value.\nBits 29:28 ACCMOD[2:0]: Access mode.\nSpecifies the asynchronous access modes as shown in the next timing diagrams.These bits are \ntaken into account only when the EXTMOD bit in the FSMC_BCRx register is 1.\n00: access mode A\n01: access mode B\n10: access mode C\n11: access mode D\nBits 27:20\nReserved, must be kept at reset value.\nBits 19:16 BUSTURN[3:0]: Bus turnaround phase duration\nThe programmed bus turnaround delay is inserted between a an asynchronous write transfer and \nany other asynchronous/synchronous read or write transfer to/from a static bank (for a read \noperation, the bank can be the same or a different one; for a write operation, the bank can be \ndifferent except in r muxed or D mode).\nIn some cases, the bus turnaround delay is fixed, whatever the programmed BUSTURN values: \n– No bus turnaround delay is inserted between two consecutive asynchronous write transfers to the \nsame static memory bank except in muxed and D mode.\n– A bus turnaround delay of 2 FSMC clock cycles is inserted between:\n–\nTwo consecutive synchronous write accesses (in burst or single mode) to the same bank.\n–\nA synchronous write transfer (in burst or single mode) and an asynchronous write or read \ntransfer to/from static a memory bank.\n– A bus turnaround delay of 3 FSMC clock cycles is inserted between:\n–\nTwo consecutive synchronous write accesses (in burst or single mode) to different static \nbanks.\n–\nA synchronous write transfer (in burst or single mode) and a synchronous read from the \nsame or from a different bank.\n0000: BUSTURN phase duration = 0 HCLK clock cycle added\n... \n1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) \n" }, { "page_number": 1587, "page_indices": { "start_index": 3109495, "end_index": 3111593 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1587 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ] ], "page_content": "RM0090 Rev 21\n1587/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n36.6 \nNAND Flash/PC Card controller\nThe FSMC generates the appropriate signal timings to drive the following types of device:\n•\nNAND Flash\n–\n8-bit\n–\n16-bit\n•\n16-bit PC Card compatible devices\nThe NAND/PC Card controller can control three external banks. Bank 2 and bank 3 support \nNAND Flash devices. Bank 4 supports PC Card devices.\nEach bank is configured by means of dedicated registers (Section 36.6.8). The \nprogrammable memory parameters include access timings (shown in Table 247) and ECC \nconfiguration.\nBits 15:8 DATAST[7:0]: Data-phase duration.\nThese bits are written by software to define the duration of the data phase (refer to Figure 436 to \nFigure 448), used in asynchronous SRAM, PSRAM and NOR flash memory accesses:\n0000 0000: Reserved\n0000 0001: DATAST phase duration = 1 × HCLK clock cycles\n0000 0010: DATAST phase duration = 2 × HCLK clock cycles\n...\n1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)\nNote: In synchronous accesses, this value is don't care.\nBits 7:4 ADDHLD[3:0]: Address-hold phase duration.\nThese bits are written by software to define the duration of the address hold phase (refer to \nFigure 445 to Figure 448), used in asynchronous multiplexed accesses:\n0000: Reserved\n0001: ADDHLD phase duration = 1 × HCLK clock cycle\n0010: ADDHLD phase duration = 2 × HCLK clock cycle\n...\n1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)\nNote: In synchronous NOR flash accesses, this value is not used, the address hold phase is always \n1 flash clock period duration.\nBits 3:0 ADDSET[3:0]: Address setup phase duration.\nThese bits are written by software to define the duration of the address setup phase in HCLK cycles \n(refer to Figure 445 to Figure 448), used in asynchronous accessed:\n0000: ADDSET phase duration = 0 × HCLK clock cycle\n...\n1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)\nNote: In synchronous NOR flash and PSRAM accesses, this value is don’t care.\n" }, { "page_number": 1588, "page_indices": { "start_index": 3111593, "end_index": 3113187 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1588 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.1 External memory interface signals", 1588 ], [ 4, "8-bit NAND Flash", 1588 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1588/1757\nRM0090 Rev 21\n \n36.6.1 \nExternal memory interface signals\nThe following tables list the signals that are typically used to interface NAND Flash and PC \nCard.\nNote:\nPrefix “N”. specifies the associated signal as active low.\n8-bit NAND Flash\n t\nThere is no theoretical capacity limitation as the FSMC can manage as many address \ncycles as needed.\nTable 247. Programmable NAND/PC Card access parameters\nParameter\nFunction\nAccess mode\nUnit\nMin. Max. \nMemory setup \ntime\nNumber of clock cycles (HCLK) \nto set up the address before the \ncommand assertion\nRead/Write \nAHB clock cycle \n(HCLK) \n1 \n255\nMemory wait\nMinimum duration (HCLK clock \ncycles) of the command assertion Read/Write \nAHB clock cycle \n(HCLK) \n2\n256 \nMemory hold \nNumber of clock cycles (HCLK) \nto hold the address (and the data \nin case of a write access) after \nthe command de-assertion \nRead/Write \nAHB clock cycle \n(HCLK) \n1 \n254\nMemory \ndatabus high-Z \nNumber of clock cycles (HCLK) \nduring which the databus is kept \nin high-Z state after the start of a \nwrite access \nWrite \nAHB clock cycle \n(HCLK) \n0 \n255 \nTable 248. 8-bit NAND Flash\nFSMC signal name\nI/O \nFunction\nA[17] \nO \nNAND Flash address latch enable (ALE) signal \nA[16] \nO \nNAND Flash command latch enable (CLE) signal \nD[7:0] \nI/O \n8-bit multiplexed, bidirectional address/data bus \nNCE[x]\nO\nChip select, x = 2, 3\nNOE(= NRE)\nO \nOutput enable (memory signal name: read enable, NRE) \nNWE\nO \nWrite enable \nNWAIT/INT[3:2]\nI \nNAND Flash ready/busy input signal to the FSMC \n" }, { "page_number": 1589, "page_indices": { "start_index": 3113187, "end_index": 3114647 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1589 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.1 External memory interface signals", 1588 ], [ 4, "16-bit NAND Flash", 1589 ], [ 4, "16-bit PC Card", 1589 ] ], "page_content": "RM0090 Rev 21\n1589/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n16-bit NAND Flash\n \nThere is no theoretical capacity limitation as the FSMC can manage as many address \ncycles as needed.\n16-bit PC Card\nTable 249. 16-bit NAND Flash\nFSMC signal name \nI/O \nFunction \nA[17]\nO \nNAND Flash address latch enable (ALE) signal \nA[16] \nO \nNAND Flash command latch enable (CLE) signal \nD[15:0] \nI/O \n16-bit multiplexed, bidirectional address/data bus \nNCE[x]\nO\nChip select, x = 2, 3\nNOE(= NRE)\nO \nOutput enable (memory signal name: read enable, NRE) \nNWE\nO \nWrite enable \nNWAIT/INT[3:2]\nI \nNAND Flash ready/busy input signal to the FSMC \nTable 250. 16-bit PC Card\nFSMC signal name\nI/O\nFunction\nA[10:0]\nO\nAddress bus\nNIORD\nO\nOutput enable for I/O space\nNIOWR\nO\nWrite enable for I/O space\nNREG\nO\nRegister signal indicating if access is in Common or Attribute space\nD[15:0]\nI/O\nBidirectional databus\nNCE4_1\nO\nChip select 1\nNCE4_2\nO\nChip select 2 (indicates if access is 16-bit or 8-bit)\nNOE\nO\nOutput enable in Common and in Attribute space\nNWE\nO\nWrite enable in Common and in Attribute space\nNWAIT\nI\nPC Card wait input signal to the FSMC (memory signal name \nIORDY)\nINTR\nI\nPC Card interrupt to the FSMC (only for PC Cards that can generate \nan interrupt)\nCD\nI\nPC Card presence detection. Active high. If an access is performed \nto the PC Card banks while CD is low, an AHB error is generated. \nRefer to Section 36.3: AHB interface\n" }, { "page_number": 1590, "page_indices": { "start_index": 3114647, "end_index": 3116471 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1590 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.2 NAND Flash / PC Card supported memories and transactions", 1590 ], [ 3, "36.6.3 Timing diagrams for NAND and PC Card", 1590 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1590/1757\nRM0090 Rev 21\n36.6.2 \nNAND Flash / PC Card supported memories and transactions\nTable 251 below shows the supported devices, access modes and transactions. \nTransactions not allowed (or not supported) by the NAND Flash / PC Card controller appear \nin gray.\n \n36.6.3 \nTiming diagrams for NAND and PC Card\nEach PC Card/CompactFlash and NAND Flash memory bank is managed through a set of \nregisters:\n•\nControl register: FSMC_PCRx\n•\nInterrupt status register: FSMC_SRx\n•\nECC register: FSMC_ECCRx\n•\nTiming register for Common memory space: FSMC_PMEMx\n•\nTiming register for Attribute memory space: FSMC_PATTx\n•\nTiming register for I/O space: FSMC_PIOx\nEach timing configuration register contains three parameters used to define number of \nHCLK cycles for the three phases of any PC Card/CompactFlash or NAND Flash access, \nplus one parameter that defines the timing for starting driving the databus in the case of a \nwrite. Figure 454 shows the timing parameter definitions for common memory accesses, \nknowing that Attribute and I/O (only for PC Card) memory space access timings are similar.\nTable 251. Supported memories and transactions\nDevice\nMode \nR/W \nAHB \ndata size\nMemory \ndata size\nAllowed/\nnot allowed\nComments \nNAND 8-bit \nAsynchronous R \n8 \n8 \nY \n-\nAsynchronous W \n8 \n8 \nY \n-\nAsynchronous R \n16 \n8 \nY \nSplit into 2 FSMC accesses \nAsynchronous W \n16 \n8 \nY \nSplit into 2 FSMC accesses \nAsynchronous R \n32 \n8 \nY \nSplit into 4 FSMC accesses \nAsynchronous W \n32 \n8 \nY \nSplit into 4 FSMC accesses \nNAND 16-bit \nAsynchronous R \n8 \n16 \nY \n-\nAsynchronous W \n8 \n16 \nN \n-\nAsynchronous R \n16 \n16 \nY \n-\nAsynchronous W \n16 \n16 \nY \n-\nAsynchronous R \n32 \n16 \nY \nSplit into 2 FSMC accesses \nAsynchronous W \n32 \n16 \nY \nSplit into 2 FSMC accesses \n" }, { "page_number": 1591, "page_indices": { "start_index": 3116471, "end_index": 3118663 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1591 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.4 NAND Flash operations", 1591 ] ], "page_content": "RM0090 Rev 21\n1591/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nFigure 454. NAND/PC Card controller timing for common memory access \n1.\nNOE remains high (inactive) during write access. NWE remains high (inactive) during read access.\n2.\nFor write accesses, the hold phase delay is (MEMHOLD) x HCLK cycles, while it is (MEMHOLD + 2) x \nHCLK cycles for read accesses.\n36.6.4 \nNAND Flash operations\nThe command latch enable (CLE) and address latch enable (ALE) signals of the NAND \nFlash device are driven by some address signals of the FSMC controller. This means that to \nsend a command or an address to the NAND Flash memory, the CPU has to perform a write \nto a certain address in its memory space.\nA typical page read operation from the NAND Flash device is as follows:\n1.\nProgram and enable the corresponding memory bank by configuring the FSMC_PCRx \nand FSMC_PMEMx (and for some devices, FSMC_PATTx, see Section 36.6.5) \nregisters according to the characteristics of the NAND Flash (PWID bits for the databus \nwidth of the NAND Flash, PTYP = 1, PWAITEN = 0 or 1 as needed, see Common \nmemory space timing register 2..4 (FSMC_PMEM2..4) for timing configuration).\n2. \nThe CPU performs a byte write in the common memory space, with data byte equal to \none Flash command byte (for example 0x00 for Samsung NAND Flash devices). The \nCLE input of the NAND Flash is active during the write strobe (low pulse on NWE), thus \nthe written byte is interpreted as a command by the NAND Flash. Once the command \nis latched by the NAND Flash device, it does not need to be written for the following \npage read operations.\n3. \nThe CPU can send the start address (STARTAD) for a read operation by writing the \nrequired bytes (for example four bytes or three for smaller capacity devices), \nSTARTAD[7:0], STARTAD[15:8], STARTAD[23:16] and finally STARTAD[25:24] for \n64 Mb x 8 bit NAND Flash) in the common memory or attribute space. The ALE input of \nthe NAND Flash device is active during the write strobe (low pulse on NWE), thus the \ni15570b\nHCLK\nA[25:0]\nNCEx\nNREG,\nNIOW,\nNIOR\nNWE,\nNOE(1)\nwrite_data\nread_data\nHigh\nValid\nMEMxSET + 1\nMEMxWAIT + 1\nMEMxHOLD + 1\nMEMxHIZ\n" }, { "page_number": 1592, "page_indices": { "start_index": 3118663, "end_index": 3120666 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1592 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.5 NAND Flash prewait functionality", 1592 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1592/1757\nRM0090 Rev 21\nwritten bytes are interpreted as the start address for read operations. Using the \nattribute memory space makes it possible to use a different timing configuration of the \nFSMC, which can be used to implement the prewait functionality needed by some \nNAND Flash memories (see details in Section 36.6.5).\n4. \nThe controller waits for the NAND Flash to be ready (R/NB signal high) to become \nactive, before starting a new access (to same or another memory bank). While waiting, \nthe controller maintains the NCE signal active (low).\n5. \nThe CPU can then perform byte read operations in the common memory space to read \nthe NAND Flash page (data field + Spare field) byte by byte.\n6. \nThe next NAND Flash page can be read without any CPU command or address write \noperation, in three different ways:\n–\nby simply performing the operation described in step 5\n–\na new random address can be accessed by restarting the operation at step 3\n–\na new command can be sent to the NAND Flash device by restarting at step 2\n36.6.5 \nNAND Flash prewait functionality\nSome NAND Flash devices require that, after writing the last part of the address, the \ncontroller wait for the R/NB signal to go low as shown in Figure 455.\nFigure 455. Access to non ‘CE don’t care’ NAND-Flash\n1.\nCPU wrote byte 0x00 at address 0x7001 0000.\n2.\nCPU wrote byte A7-A0 at address 0x7002 0000.\n3.\nCPU wrote byte A15-A8 at address 0x7002 0000.\n4.\nCPU wrote byte A23-A16 at address 0x7002 0000.\n5.\nCPU wrote byte A25-A24 at address 0x7802 0000: FSMC performs a write access using FSMC_PATT2 \ntiming definition, where ATTHOLD ≥ 7 (providing that (7+1) × HCLK = 112 ns > tWB max). This guarantees \nthat NCE remains low until R/NB goes low and high again (only requested for NAND Flash memories \nwhere NCE is not don’t care).\nNCE\nNOE\nI/O[7:0]\nR/NB\nai17733b\nHigh\ntWB\nCLE\nALE\n0x00\nA7-A0\nA15-A8\nA23-A16\nA25-A14\ntR\nNWE\n(1)\n(2)\n(3)\n(4)\n(5)\nNCE must stay low\n" }, { "page_number": 1593, "page_indices": { "start_index": 3120666, "end_index": 3123197 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1593 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.6 Computation of the error correction code (ECC) in NAND Flash memory", 1593 ] ], "page_content": "RM0090 Rev 21\n1593/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nWhen this functionality is needed, it can be guaranteed by programming the MEMHOLD \nvalue to meet the tWB timing. However CPU read accesses to the NAND Flash memory has \na hold delay of (MEMHOLD + 2) x HCLK cycles, while CPU write accesses have a hold \ndelay of (MEMHOLD) x HCLK cycles. \nTo overcome this timing constraint, the attribute memory space can be used by \nprogramming its timing register with an ATTHOLD value that meets the tWB timing, and \nleaving the MEMHOLD value at its minimum. Then, the CPU must use the common memory \nspace for all NAND Flash read and write accesses, except when writing the last address \nbyte to the NAND Flash device, where the CPU must write to the attribute memory space.\n36.6.6 \nComputation of the error correction code (ECC)\nin NAND Flash memory\nThe FSMC PC-Card controller includes two error correction code computation hardware \nblocks, one per memory bank. They are used to reduce the host CPU workload when \nprocessing the error correction code by software in the system.\nThese two registers are identical and associated with bank 2 and bank 3, respectively. As a \nconsequence, no hardware ECC computation is available for memories connected to bank \n4.\nThe error correction code (ECC) algorithm implemented in the FSMC can perform 1-bit error \ncorrection and 2-bit error detection per 256, 512, 1 024, 2 048, 4 096 or 8 192 bytes read \nfrom or written to NAND Flash memory. It is based on the Hamming coding algorithm and \nconsists in calculating the row and column parity.\nThe ECC modules monitor the NAND Flash databus and read/write signals (NCE and NWE) \neach time the NAND Flash memory bank is active.\nThe functional operations are:\n•\nWhen access to NAND Flash is made to bank 2 or bank 3, the data present on the \nD[15:0] bus is latched and used for ECC computation. \n•\nWhen access to NAND Flash occurs at any other address, the ECC logic is idle, and \ndoes not perform any operation. Thus, write operations for defining commands or \naddresses to NAND Flash are not taken into account for ECC computation.\nOnce the desired number of bytes has been read from/written to the NAND Flash by the \nhost CPU, the FSMC_ECCR2/3 registers must be read in order to retrieve the computed \nvalue. Once read, they should be cleared by resetting the ECCEN bit to zero. To compute a \nnew data block, the ECCEN bit must be set to one in the FSMC_PCR2/3 registers.\nTo perform an ECC computation:\n" }, { "page_number": 1594, "page_indices": { "start_index": 3123197, "end_index": 3125894 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1594 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.7 PC Card/CompactFlash operations", 1594 ], [ 4, "Address spaces and memory accesses", 1594 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1594/1757\nRM0090 Rev 21\n1.\nEnable the ECCEN bit in the FSMC_PCR2/3 register.\n2. \nWrite data to the NAND Flash memory page. While the NAND page is written, the ECC \nblock computes the ECC value. \n3. \nRead the ECC value available in the FSMC_ECCR2/3 register and store it in a \nvariable.\n4. \nClear the ECCEN bit and then enable it in the FSMC_PCR2/3 register before reading \nback the written data from the NAND page. While the NAND page is read, the ECC \nblock computes the ECC value. \n5. \nRead the new ECC value available in the FSMC_ECCR2/3 register.\n6. \nIf the two ECC values are the same, no correction is required, otherwise there is an \nECC error and the software correction routine returns information on whether the error \ncan be corrected or not. \n36.6.7 \nPC Card/CompactFlash operations\nAddress spaces and memory accesses \nThe FSMC supports Compact Flash storage or PC Cards in Memory Mode and I/O Mode \n(True IDE mode is not supported).\nThe Compact Flash storage and PC Cards are made of 3 memory spaces:\n•\nCommon Memory Space\n•\nAttribute Space\n•\nI/O Memory Space\nThe nCE2 and nCE1 pins (FSMC_NCE4_2 and FSMC_NCE4_1 respectively) select the \ncard and indicate whether a byte or a word operation is being performed: nCE2 accesses \nthe odd byte on D15-8 and nCE1 accesses the even byte on D7-0 if A0=0 or the odd byte on \nD7-0 if A0=1. The full word is accessed on D15-0 if both nCE2 and nCE1 are low.\nThe memory space is selected by asserting low nOE for read accesses or nWE for write \naccesses, combined with the low assertion of nCE2/nCE1 and nREG.\n•\nIf pin nREG=1 during the memory access, the common memory space is selected\n•\nIf pin nREG=0 during the memory access, the attribute memory space is selected\nThe I/O Space is selected by asserting low nIORD for read accesses or nIOWR for write \naccesses [instead of nOE/nWE for memory Space], combined with nCE2/nCE1. Note that \nnREG must also be asserted low during accesses to I/O Space.\nThree type of accesses are allowed for a 16-bit PC Card:\n•\nAccesses to Common Memory Space for data storage can be either 8-bit accesses at \neven addresses or 16 bit AHB accesses. \nNote that 8-bit accesses at odd addresses are not supported and do not lead to the low \nassertion of nCE2. A 32-bit AHB request is translated into two 16-bit memory \naccesses.\n•\nAccesses to Attribute Memory Space where the PC Card stores configuration \ninformation are limited to 8-bit AHB accesses at even addresses.\nNote that a 16-bit AHB access is converted into a single 8-bit memory transfer: nCE1 is \nasserted low, nCE2 is asserted high and only the even Byte on D7-D0 is valid. Instead \n" }, { "page_number": 1595, "page_indices": { "start_index": 3125894, "end_index": 3127876 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1595 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.7 PC Card/CompactFlash operations", 1594 ], [ 4, "Wait Feature", 1595 ] ], "page_content": "RM0090 Rev 21\n1595/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\na 32-bit AHB access is converted into two 8-bit memory transfers at even addresses: \nnCE1 is asserted low, NCE2 is asserted high and only the even bytes are valid.\n•\nAccesses to I/O Space can be performed either through AHB 8-bit or 16-bit accesses.\n \nThe FSMC Bank 4 gives access to those 3 memory spaces as described in Section 36.4.2: \nNAND/PC Card address mapping and Table 219: Memory mapping and timing registers.\nWait Feature \nThe CompactFlash Storage or PC Card may request the FSMC to extend the length of the \naccess phase programmed by MEMWAITx/ATTWAITx/IOWAITx bits, asserting the nWAIT \nsignal after nOE/nWE or nIORD/nIOWR activation if the wait feature is enabled through the \nPWAITEN bit in the FSMC_PCRx register. In order to detect the nWAIT assertion correctly, \nthe MEMWAITx/ATTWAITx/IOWAITx bits must be programmed as follows:\nTable 252. 16-bit PC-Card signals and access type \nnCE2\nnCE1\nnREG\nnOE/nWE\nnIORD /nIOWR\nA10\nA9\nA7-1\nA0 \nSpace \nAccess Type\nAllowed/not \nAllowed \n1\n0\n1\n0\n1\nX\nX\nX-X\nX\nCommon \nMemory \nSpace\nRead/Write byte on D7-D0\nYES\n0\n1\n1\n0\n1\nX\nX\nX-X\nX\nRead/Write byte on D15-D8\nNot supported\n0\n0\n1\n0\n1\nX\nX\nX-X\n0\nRead/Write word on D15-D0\nYES\nX\n0\n0\n0\n1\n0\n1\nX-X\n0\nAttribute \nSpace\nRead or Write Configuration \nregisters\nYES\nX\n0\n0\n0\n1\n0\n0\nX-X\n0\nRead or Write CIS (Card \nInformation Structure)\nYES\n1\n0\n0\n0\n1\nX\nX\nX-X\n1\nAttribute \nSpace\nInvalid Read or Write (odd \naddress)\nYES\n0\n1\n0\n0\n1\nX\nX\nX-X\nx\nInvalid Read or Write (odd \naddress)\nYES\n1\n0\n0\n1\n0\nX\nX\nX-X\n0\nI/O space\nRead Even Byte on D7-0 \nYES\n1\n0\n0\n1\n0\nX\nX\nX-X\n1\nRead Odd Byte on D7-0\nYES\n1\n0\n0\n1\n0\nX\nX\nX-X\n0\nWrite Even Byte on D7-0 \nYES\n1\n0\n0\n1\n0\nX\nX\nX-X\n1\nWrite Odd Byte on D7-0 \nYES\n0\n0\n0\n1\n0\nX\nX\nX-X\n0\nRead Word on D15-0\nYES\n0\n0\n0\n1\n0\nX\nX\nX-X\n0\nWrite word on D15-0 \nYES\n0\n1\n0\n1\n0\nX\nX\nX-X\nX\nRead Odd Byte on D15-8\nNot supported\n0\n1\n0\n1\n0\nX\nX\nX-X\nX\nWrite Odd Byte on D15-8\nNot supported\n" }, { "page_number": 1596, "page_indices": { "start_index": 3127876, "end_index": 3129737 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1596 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.8 NAND Flash/PC Card control registers", 1596 ], [ 4, "PC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4)", 1596 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1596/1757\nRM0090 Rev 21\nxxWAITx >= 4 + max_wait_assertion_time/HCLK\nWhere max_wait_assertion_time is the maximum time taken by NWAIT to go low once \nnOE/nWE or nIORD/nIOWR is low.\nAfter the de-assertion of nWAIT, the FSMC extends the WAIT phase for 4 HCLK clock \ncycles. \n36.6.8 \nNAND Flash/PC Card control registers\nThe NAND Flash/PC Card control registers have to be accessed by words (32 bits).\nPC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4)\nAddress offset: 0xA0000000 + 0x40 + 0x20 * (x – 1), x = 2..4\nReset value: 0x0000 0018\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nECCPS[2:0]\nTAR[2:0]\nTCLR[2:0]\nRes.\nECCEN\nPWID[1:0]\nPTYP\nPBKEN\nPWAITEN\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:20 Reserved, must be kept at reset value.\nBits 19:17 ECCPS[2:0]: ECC page size.\nDefines the page size for the extended ECC:\n000: 256 bytes\n001: 512 bytes\n010: 1024 bytes\n011: 2048 bytes\n100: 4096 bytes\n101: 8192 bytes\nBits 16:13 TAR[2:0]: ALE to RE delay.\nSets time from ALE low to RE low in number of AHB clock cycles (HCLK).\nTime is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period\n0000: 1 HCLK cycle (default)\n1111: 16 HCLK cycles\nNote: SET is MEMSET or ATTSET according to the addressed space.\nBits 12:9 TCLR[2:0]: CLE to RE delay.\nSets time from CLE low to RE low in number of AHB clock cycles (HCLK).\nTime is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period\n0000: 1 HCLK cycle (default)\n1111: 16 HCLK cycles\nNote: SET is MEMSET or ATTSET according to the addressed space.\nBits 8:7 Reserved, must be kept at reset value.\nBit 6 ECCEN: ECC computation logic enable bit\n0: ECC logic is disabled and reset (default after reset),\n1: ECC logic is enabled.\n" }, { "page_number": 1597, "page_indices": { "start_index": 3129737, "end_index": 3131796 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1597 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.8 NAND Flash/PC Card control registers", 1596 ], [ 4, "FIFO status and interrupt register 2..4 (FSMC_SR2..4)", 1597 ] ], "page_content": "RM0090 Rev 21\n1597/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\nFIFO status and interrupt register 2..4 (FSMC_SR2..4)\nAddress offset: 0xA000 0000 + 0x44 + 0x20 * (x-1), x = 2..4\nReset value: 0x0000 0040\nThis register contains information about FIFO status and interrupt. The FSMC has a FIFO \nthat is used when writing to memories to store up to16 words of data from the AHB.\nThis is used to quickly write to the AHB and free it for transactions to peripherals other than \nthe FSMC, while the FSMC is draining its FIFO into the memory. This register has one of its \nbits that indicates the status of the FIFO, for ECC purposes.\nThe ECC is calculated while the data are written to the memory, so in order to read the \ncorrect ECC the software must wait until the FIFO is empty.\n \nBits 5:4 PWID[1:0]: Databus width.\nDefines the external memory device width.\n00: 8 bits\n01: 16 bits (default after reset). This value is mandatory for PC Cards.\n10: reserved, do not use\n11: reserved, do not use\nBit 3 PTYP: Memory type.\nDefines the type of device attached to the corresponding memory bank:\n0: PC Card, CompactFlash, CF+ or PCMCIA\n1: NAND Flash (default after reset)\nBit 2 PBKEN: PC Card/NAND Flash memory bank enable bit.\nEnables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB \nbus \n0: Corresponding memory bank is disabled (default after reset)\n1: Corresponding memory bank is enabled\nBit 1 PWAITEN: Wait feature enable bit.\nEnables the Wait feature for the PC Card/NAND Flash memory bank:\n0: disabled\n1: enabled\nNote: For a PC Card, when the wait feature is enabled, the MEMWAITx/ATTWAITx/IOWAITx \nbits must be programmed to a value as follows:\nxxWAITx ≥ 4 + max_wait_assertion_time/HCLK\nWhere max_wait_assertion_time is the maximum time taken by NWAIT to go low once \nnOE/nWE or nIORD/nIOWR is low.\nBit 0\nReserved, must be kept at reset value.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFEMPT\nIFEN\nILEN\nIREN\nIFS\nILS\nIRS\nr\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1598, "page_indices": { "start_index": 3131796, "end_index": 3133823 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1598 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.8 NAND Flash/PC Card control registers", 1596 ], [ 4, "Common memory space timing register 2..4 (FSMC_PMEM2..4)", 1598 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1598/1757\nRM0090 Rev 21\n \nCommon memory space timing register 2..4 (FSMC_PMEM2..4)\nAddress offset: Address: 0xA000 0000 + 0x48 + 0x20 * (x – 1), x = 2..4\nReset value: 0xFCFC FCFC\nEach FSMC_PMEMx (x = 2..4) read/write register contains the timing information for PC \nCard or NAND Flash memory bank x, used for access to the common memory space of the \n16-bit PC Card/CompactFlash, or to access the NAND Flash for command, address write \naccess and data read/write access.\n \nBits 31:7\nReserved, must be kept at reset value.\nBit 6\nFEMPT: FIFO empty.\nRead-only bit that provides the status of the FIFO\n0: FIFO not empty\n1: FIFO empty\nBit 5\nIFEN: Interrupt falling edge detection enable bit\n0: Interrupt falling edge detection request disabled\n1: Interrupt falling edge detection request enabled\nBit 4\nILEN: Interrupt high-level detection enable bit\n0: Interrupt high-level detection request disabled\n1: Interrupt high-level detection request enabled\nBit 3\nIREN: Interrupt rising edge detection enable bit\n0: Interrupt rising edge detection request disabled\n1: Interrupt rising edge detection request enabled\nBit 2\nIFS: Interrupt falling edge status\nThe flag is set by hardware and reset by software.\n0: No interrupt falling edge occurred\n1: Interrupt falling edge occurred\nNote: This bit is set by programming it to 1 by software. \nBit 1\nILS: Interrupt high-level status\nThe flag is set by hardware and reset by software.\n0: No Interrupt high-level occurred\n1: Interrupt high-level occurred\nBit 0\nIRS: Interrupt rising edge status\nThe flag is set by hardware and reset by software.\n0: No interrupt rising edge occurred\n1: Interrupt rising edge occurred\nNote: This bit is set by programming it to 1 by software. \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMEMHIZ[7:0]\nMEMHOLD[7:0]\nMEMWAIT[7:0]\nMEMSET[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1599, "page_indices": { "start_index": 3133823, "end_index": 3136564 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1599 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.8 NAND Flash/PC Card control registers", 1596 ], [ 4, "Attribute memory space timing registers 2..4 (FSMC_PATT2..4)", 1599 ] ], "page_content": "RM0090 Rev 21\n1599/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \nAttribute memory space timing registers 2..4 (FSMC_PATT2..4)\nAddress offset: 0xA000 0000 + 0x4C + 0x20 * (x – 1), x = 2..4\nReset value: 0xFCFC FCFC\nEach FSMC_PATTx (x = 2..4) read/write register contains the timing information for PC \nCard/CompactFlash or NAND Flash memory bank x. It is used for 8-bit accesses to the \nattribute memory space of the PC Card/CompactFlash or to access the NAND Flash for the \nlast address write access if the timing must differ from that of previous accesses (for \nReady/Busy management, refer to Section 36.6.5: NAND Flash prewait functionality).\n \nBits 31:24 MEMHIZx[7:0]: Common memory x databus HiZ time\nDefines the number of HCLK clock cycles during which the databus is kept in HiZ after the \nstart of a PC Card/NAND Flash write access to common memory space on socket x. Only \nvalid for write transaction:\n0000 0000: 1 HCLK cycle\n1111 1110: 255 HCLK cycles\n1111 1111: Reserved\nBits 23:16 MEMHOLDx[7:0]: Common memory x hold time\nFor NAND Flash read accesses to the common memory space, these bits define the \nnumber of (HCLK+2) clock cycles during which the address is held after the command is \ndeasserted (NWE, NOE).\nFor NAND Flash write accesses to the common memory space, these bits define the \nnumber of HCLK clock cycles during which the data are held after the command is \ndeasserted (NWE, NOE).\n0000 0000: Reserved\n0000 0001: 1 HCLK cycle for write accesses, 3 HCLK cycles for read accesses\n1111 1110: 254 HCLK cycle for write accesses, 256 HCLK cycles for read accesses\n1111 1111: Reserved\nBits 15:8 MEMWAITx[7:0]: Common memory x wait time\nDefines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, \nNOE), for PC Card/NAND Flash read or write access to common memory space on socket \nx. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) \nat the end of the programmed value of HCLK:\n0000 0000: Reserved\n0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)\n1111 1110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)\n1111 1111: Reserved.\nBits 7:0 MEMSETx[7:0]: Common memory x setup time\nDefines the number of HCLK () clock cycles to set up the address before the command \nassertion (NWE, NOE), for PC Card/NAND Flash read or write access to common memory \nspace on socket x:\n0000 0000: 1 HCLK cycle\n1111 1110: 255 HCLK cycles\n1111 1111: Reserved \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nATTHIZ[7:0]\nATTHOLD[7:0]\nATTWAIT[7:0]\nATTSET[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1600, "page_indices": { "start_index": 3136564, "end_index": 3139028 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1600 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.8 NAND Flash/PC Card control registers", 1596 ], [ 4, "I/O space timing register 4 (FSMC_PIO4)", 1600 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1600/1757\nRM0090 Rev 21\n \nI/O space timing register 4 (FSMC_PIO4)\nAddress offset: 0xA000 0000 + 0xB0\nReset value: 0xFCFCFCFC\nThe FSMC_PIO4 read/write registers contain the timing information used to gain access to \nthe I/O space of the 16-bit PC Card/CompactFlash.\n \nBits 31:24 ATTHIZ[7:0]: Attribute memory x databus HiZ time\nDefines the number of HCLK clock cycles during which the databus is kept in HiZ after the \nstart of a PC CARD/NAND Flash write access to attribute memory space on socket x. Only \nvalid for write transaction:\n0000 0000: 0 HCLK cycle\n1111 1110: 255 HCLK cycles\n1111 1111: Reserved.\nBits 23:16 ATTHOLD[7:0]: Attribute memory x hold time\nFor PC Card/NAND Flash read accesses to attribute memory space on socket x, these bits \ndefine the number of HCLK clock cycles (HCLK +2) clock cycles during which the address is \nheld after the command is deasserted (NWE, NOE).\nFor PC Card/NAND Flash write accesses to attribute memory space on socket x, these bits \ndefine the number of HCLK clock cycles during which the data are held after the command \nis deasserted (NWE, NOE).\n0000 0000: reserved\n0000 0001: 1 HCLK cycle for write access, 3 HCLK cycles for read accesses\n1111 1110: 254 HCLK cycle for write access, 256 HCLK cycles for read accesses\n1111 1111: Reserved\nBits 15:8 ATTWAIT[7:0]: Attribute memory x wait time\nDefines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, \nNOE), for PC Card/NAND Flash read or write access to attribute memory space on socket x. \nThe duration for command assertion is extended if the wait signal (NWAIT) is active (low) at \nthe end of the programmed value of HCLK:\n0000 0000: Reserved\n0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)\n1111 1111: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)\n1111 1111: Reserved.\nBits 7:0 ATTSET[7:0]: Attribute memory x setup time\nDefines the number of HCLK (+1) clock cycles to set up address before the command \nassertion (NWE, NOE), for PC CARD/NAND Flash read or write access to attribute memory \nspace on socket x:\n0000 0000: 1 HCLK cycle\n1111 1110: 255 HCLK cycles\n1111 1111: Reserved. \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nIOHIZ[7:0]\nIOHOLD[7:0]\nIOWAIT[7:0]\nIOSET[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1601, "page_indices": { "start_index": 3139028, "end_index": 3141811 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1601 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.8 NAND Flash/PC Card control registers", 1596 ], [ 4, "ECC result registers 2/3 (FSMC_ECCR2/3)", 1601 ] ], "page_content": "RM0090 Rev 21\n1601/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n \nECC result registers 2/3 (FSMC_ECCR2/3)\nAddress offset: 0xA000 0000 + 0x54 + 0x20 * (x – 1), x = 2 or 3\nReset value: 0x0000 0000\nThese registers contain the current error correction code value computed by the ECC \ncomputation modules of the FSMC controller (one module per NAND Flash memory bank). \nWhen the CPU reads the data from a NAND Flash memory page at the correct address \n(refer to Section 36.6.6: Computation of the error correction code (ECC) in NAND Flash \nmemory), the data read from or written to the NAND Flash are processed automatically by \nECC computation module. At the end of X bytes read (according to the ECCPS field in the \nFSMC_PCRx registers), the CPU must read the computed ECC value from the \nFSMC_ECCx registers, and then verify whether these computed parity data are the same \nas the parity value recorded in the spare area, to determine whether a page is valid, and, to \ncorrect it if applicable. The FSMC_ECCRx registers should be cleared after being read by \nsetting the ECCEN bit to zero. For computing a new data block, the ECCEN bit must be set \nto one.\n \nBits 31:24 IOHIZ[7:0]: I/O x databus HiZ time\nDefines the number of HCLK clock cycles during which the databus is kept in HiZ after the start \nof a PC Card write access to I/O space on socket x. Only valid for write transaction:\n0000 0000: 0 HCLK cycle\n1111 1111: 255 HCLK cycles (default value after reset)\nBits 23:16 IOHOLD[7:0]: I/O x hold time\nDefines the number of HCLK clock cycles to hold address (and data for write access) after the \ncommand deassertion (NWE, NOE), for PC Card read or write access to I/O space on socket \nx:\n0000 0000: reserved\n0000 0001: 1 HCLK cycle\n1111 1111: 255 HCLK cycles (default value after reset)\nBits 15:8 IOWAIT[7:0]: I/O x wait time\nDefines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE, \nSMNOE), for PC Card read or write access to I/O space on socket x. The duration for \ncommand assertion is extended if the wait signal (NWAIT) is active (low) at the end of the \nprogrammed value of HCLK:\n0000 0000: reserved, do not use this value\n0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)\n1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) \n(default value after reset)\nBits 7:0 IOSET[7:0]: I/O x setup time\nDefines the number of HCLK (+1) clock cycles to set up the address before the command \nassertion (NWE, NOE), for PC Card read or write access to I/O space on socket x:\n0000 0000: 1 HCLK cycle\n1111 1111: 256 HCLK cycles (default value after reset)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nECCx[31:0]\nr\n" }, { "page_number": 1602, "page_indices": { "start_index": 3141811, "end_index": 3142280 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1602 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.8 NAND Flash/PC Card control registers", 1596 ], [ 4, "ECC result registers 2/3 (FSMC_ECCR2/3)", 1601 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1602/1757\nRM0090 Rev 21\n \n \nBits 31:0 ECCx[31:0]: ECC result\nThis field provides the value computed by the ECC computation logic. Table 253 hereafter \ndescribes the contents of these bit fields.\nTable 253. ECC result relevant bits\nECCPS[2:0]\nPage size in bytes\nECC bits\n000\n256\nECC[21:0]\n001\n512\nECC[23:0]\n010\n1024\nECC[25:0]\n011\n2048\nECC[27:0]\n100\n4096\nECC[29:0]\n101\n8192\nECC[31:0]\n" }, { "page_number": 1603, "page_indices": { "start_index": 3142280, "end_index": 3143815 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1603 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.9 FSMC register map", 1603 ] ], "page_content": "RM0090 Rev 21\n1603/1757\nRM0090\nFlexible static memory controller (FSMC)\n1604\n36.6.9 \nFSMC register map\nThe following table summarizes the FSMC registers. \n \nTable 254. FSMC register map\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0000\nFSMC_BCR1\nReserved\nCBURSTRW\nCPSIZE[2:0]\nASYNCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[0:1]\nMUXEN\nMBKEN\n0008\nFSMC_BCR2\nReserved\nCBURSTRW\nCPSIZE[2:0]\nASYNCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[0:1]\nMUXEN\nMBKEN\n0010\nFSMC_BCR3\nReserved\nCBURSTRW\nCPSIZE[2:0]\nASYNCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[0:1]\nMUXEN\nMBKEN\n0018\nFSMC_BCR4\nReserved\nCBURSTRW\nCPSIZE[2:0]\nASYNCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[0:1]\nMUXEN\nMBKEN\n0004\nFSMC_BTR1\nRes.\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0]\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\n000C\nFSMC_BTR2\nRes.\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0]\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\n0014\nFSMC_BTR3\nRes.\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0]\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\n001C\nFSMC_BTR4\nRes.\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0]\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\n0104\nFSMC_BWTR\n1\nRes.\nACC\nMOD\n[1:0]\nRes.\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\n010C\nFSMC_BWTR\n2\nRes.\nACC\nMOD\n[1:0]\nRes.\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\n" }, { "page_number": 1604, "page_indices": { "start_index": 3143815, "end_index": 3145397 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1604 }, "toc_details": [ [ 1, "36 Flexible static memory controller (FSMC)", 1547 ], [ 2, "36.6 NAND Flash/PC Card controller", 1587 ], [ 3, "36.6.9 FSMC register map", 1603 ] ], "page_content": "Flexible static memory controller (FSMC)\nRM0090\n1604/1757\nRM0090 Rev 21\nRefer to Section 2.3: Memory map for the register boundary addresses.\n0114\nFSMC_BWTR\n3\nRes.\nACC\nMOD\n[1:0]\nRes.\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\n011C\nFSMC_BWTR\n4\nRes.\nACC\nMOD\n[1:0]\nRes.\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\n0xA000\n0060\nFSMC_PCR2\nReserved\nECCPS[2:0]\nTAR[2:0]\nTCLR[2:0]\nRes.\nECCEN\nPWID[1:0]\nPTYP\nPBKEN\nPWAITEN\nReserved\n0xA000\n0080\nFSMC_PCR3\nReserved\nECCPS[2:0]\nTAR[2:0]\nTCLR[2:0]\nRes.\nECCEN\nPWID[1:0]\nPTYP\nPBKEN\nPWAITEN\nReserved\n0xA000\n00A0\nFSMC_PCR4\nReserved\nECCPS[2:0]\nTAR[2:0]\nTCLR[2:0]\nRes.\nECCEN\nPWID[1:0]\nPTYP\nPBKEN\nPWAITEN\nReserved\n0xA000\n0064\nFSMC_SR2\nReserved\nFEMPT\nIFEN\nILEN\nIREN\nIFS\nILS\nIRS\n0xA000\n0084\nFSMC_SR3\nReserved\nFEMPT\nIFEN\nILEN\nIREN\nIFS\nILS\nIRS\n0xA000\n00A4\nFSMC_SR4\nReserved\nFEMPT\nIFEN\nILEN\nIREN\nIFS\nILS\nIRS\n0xA000\n0068\nFSMC_PMEM\n2\nMEMHIZ[7:0]\nMEMHOLD[7:0]\nMEMWAIT[7:0]\nMEMSET[7:0]\n0xA000\n0088\nFSMC_PMEM\n3\nMEMHIZ[7:0]\nMEMHOLD[7:0]\nMEMWAIT[7:0]\nMEMSET[7:0]\n0xA000\n00A8\nFSMC_PMEM\n4\nMEMHIZ[7:0]\nMEMHOLD[7:0]\nMEMWAIT[7:0]\nMEMSET[7:0]\n0xA000\n006C\nFSMC_PATT2\nATTHIZ[7:0]\nATTHOLD[7:0]\nATTWAIT[7:0]\nATTSET[7:0]\n0xA000\n008C\nFSMC_PATT3\nATTHIZ[7:0]\nATTHOLD[7:0]\nATTWAIT[7:0]\nATTSET[7:0]\n0xA000\n00AC\nFSMC_PATT4\nATTHIZ[7:0]\nATTHOLD[7:0]\nATTWAIT[7:0]\nATTSET[7:0]\n0xA000\n00B0\nFSMC_PIO4\nIOHIZ[7:0]\nIOHOLD[7:0]\nIOWAIT[7:0]\nIOSET[7:0]\n0xA000\n0074\nFSMC_ECCR2\nECC[31:0]\n0xA000\n0094\nFSMC_ECCR3\nECC[31:0]\nTable 254. FSMC register map (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1605, "page_indices": { "start_index": 3145397, "end_index": 3147380 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1605 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.1 FMC main features", 1605 ] ], "page_content": "RM0090 Rev 21\n1605/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n37 \nFlexible memory controller (FMC)\nThe Flexible memory controller (FMC) includes three memory controllers:\n•\nThe NOR/PSRAM memory controller \n•\nThe NAND/PC Card memory controller\n•\nThe Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller \nThis section applies to STM32F42xxx and STM32F43xxx only.\n37.1 \nFMC main features\nThe FMC functional block makes the interface with synchronous and asynchronous static \nmemories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:\n•\nto translate AHB transactions into the appropriate external device protocol\n•\nto meet the access time requirements of the external memory devices\nAll external memories share the addresses, data and control signals with the controller. \nEach external device is accessed by means of a unique Chip Select. The FMC performs \nonly one access at a time to an external device.\nThe main features of the FMC controller are the following:\n•\nInterface with static-memory mapped devices including: \n–\nStatic random access memory (SRAM)\n–\nNOR Flash memory/OneNAND Flash memory\n–\nPSRAM (4 memory banks)\n–\n16-bit PC Card compatible devices\n–\nTwo banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of \ndata\n•\nInterface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories\n•\nBurst mode support for faster access to synchronous devices such as NOR Flash \nmemory, PSRAM and SDRAM)\n•\nProgrammable continuous clock output for asynchronous and synchronous accesses\n•\n8-,16- or 32-bit wide data bus\n•\nIndependent Chip Select control for each memory bank\n•\nIndependent configuration for each memory bank\n•\nWrite enable and byte lane select outputs for use with PSRAM, SRAM and SDRAM \ndevices\n•\nExternal asynchronous wait control\n•\nWrite Data FIFO with 16 x33-bit depth\n•\nWrite Address FIFO with 16x30-bit depth\n•\nCacheable Read FIFO with 6 x32-bit depth (6 x14-bit address tag) for SDRAM \ncontroller.\n" }, { "page_number": 1606, "page_indices": { "start_index": 3147380, "end_index": 3148701 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1606 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.2 Block diagram", 1606 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1606/1757\nRM0090 Rev 21\nThe FMC embeds two Write FIFOs: a Write Data FIFO with a 16x33-bit depth and a Write \nAddress FIFO with a 16x30-bit depth. \n•\nThe Write Data FIFO stores the AHB data to be written to the memory (up to 32 bits) \nplus one bit for the AHB transfer (burst or not sequential mode)\n•\nThe Write Address FIFO stores the AHB address (up to 28 bits) plus the AHB data size \n(up to 2 bits). When operating in burst mode, only the start address is stored except \nwhen crossing a page boundary (for PSRAM and SDRAM). In this case, the AHB burst \nis broken into two FIFO entries.\nAt startup the FMC pins must be configured by the user application. The FMC I/O pins which \nare not used by the application can be used for other purposes.\nThe FMC registers that define the external device type and associated characteristics are \nusually set at boot time and do not change until the next reset or power-up. However, the \nsettings can be changed at any time.\n37.2 \nBlock diagram\nThe FMC consists of five main blocks:\n•\nThe AHB interface (including the FMC configuration registers)\n•\nThe NOR Flash/PSRAM/SRAM controller\n•\nThe NAND Flash/PC Card controller\n•\nThe SDRAM controller\n•\nThe external device interface\nThe block diagram is shown in Figure 456.\n" }, { "page_number": 1607, "page_indices": { "start_index": 3148701, "end_index": 3149893 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1607 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.3 AHB interface", 1607 ] ], "page_content": "RM0090 Rev 21\n1607/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nFigure 456. FMC block diagram\n37.3 \nAHB interface\nThe AHB slave interface allows internal CPUs and other bus master peripherals to access \nthe external memories.\nAHB transactions are translated into the external device protocol. In particular, if the \nselected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split \ninto consecutive 16- or 8-bit accesses. The FMC Chip Select (FMC_NEx) does not toggle \nbetween consecutive accesses except when performing accesses in mode D with the \nextended mode enabled.\nMS30443V5\nHCLK\nNAND/PC Card\nmemory\ncontroller\nNAND\nsignals\nShared \nsignals\nNOR/PSRAM\nsignals\nFMC_NE[4:1]\nFMC_NL(or NADV)\nFMC_NWAIT\nFMC_D[31:0]\nFMC_NOE\nFMC_NWE\nFMC_NIORD\nFMC_NREG\nFMC_CD\nPC Card \nsignals\nFMC_NBL[3:0]\nFMC_NCE[3:2]\nFMC_INT[3:2]\nFMC_INTR\nFMC_NCE4_1\nFMC_NCE4_2\nFMC_NIOWR\nFMC_CLK\nSDRAM\ncontroller\nFMC_SDNWE\nFMC_SDCKE[1:0]\nFMC_SDNE[1:0]\nFMC_NRAS\nFMC_NCAS\nSDRAM\nsignals\nFMC_A[25:0]\nNOR/PSRAM/SRAM \nShared signals\nSRAM/PSRAM/SDRAM \nShared signals\nFMC_SDCLK\nFMC interrupts to NVIC\nFrom clock\ncontroller\nConfiguration\nregisters\nNOR/PSRAM\nmemory\ncontroller\n" }, { "page_number": 1608, "page_indices": { "start_index": 3149893, "end_index": 3152490 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1608 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.3 AHB interface", 1607 ], [ 3, "37.3.1 Supported memories and transactions", 1608 ], [ 4, "General transaction rules", 1608 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1608/1757\nRM0090 Rev 21\nThe FMC generates an AHB error in the following conditions:\n•\nWhen reading or writing to an FMC bank (Bank 1 to 4) which is not enabled.\n•\nWhen reading or writing to the NOR Flash bank while the FACCEN bit is reset in the \nFMC_BCRx register.\n•\nWhen reading or writing to the PC Card banks while the FMC_CD input pin (Card \nPresence Detection) is low.\n•\nWhen writing to a write protected SDRAM bank (WP bit set in the SDRAM_SDCRx \nregister).\n•\nWhen the SDRAM address range is violated (access to reserved address range)\nThe effect of an AHB error depends on the AHB master which has attempted the R/W \naccess:\n•\nIf the access has been attempted by the Cortex®-M4 with FPU CPU, a hard fault \ninterrupt is generated.\n•\nIf the access has been performed by a DMA controller, a DMA transfer error is \ngenerated and the corresponding DMA channel is automatically disabled. \nThe AHB clock (HCLK) is the reference clock for the FMC.\n37.3.1 \nSupported memories and transactions\nGeneral transaction rules\nThe requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the \naccessed external device has a fixed data width. This may lead to inconsistent transfers.\nTherefore, some simple transaction rules must be followed:\n•\nAHB transaction size and memory data size are equal\nThere is no issue in this case.\n•\nAHB transaction size is greater than the memory size:\nIn this case, the FMC splits the AHB transaction into smaller consecutive memory \naccesses to meet the external data width. The FMC Chip Select (FMC_NEx) does not \ntoggle between the consecutive accesses.\n•\nAHB transaction size is smaller than the memory size:\nThe transfer may or not be consistent depending on the type of external device:\n–\nAccesses to devices that have the byte select feature (SRAM, ROM, PSRAM, \nSDRAM)\nIn this case, the FMC allows read/write transactions and accesses the right data \nthrough its byte lanes BL[3:0]. \nbyte to be written are addressed by NBL[3:0]. \nAll memory byte are read (NBL[3:0] are driven low during read transaction) and \nthe useless ones are discarded.\n–\nAccesses to devices that do not have the byte select feature (16-bit NOR and \nNAND Flash memories)\nThis situation occurs when a byte access is requested to a 16-bit wide Flash \nmemory. Since the device cannot be accessed in byte mode (only 16-bit words \ncan be read/written from/to the Flash memory), Write transactions and Read \ntransactions are allowed (the controller reads the entire 16-bit memory word and \nuses only the required byte).\n" }, { "page_number": 1609, "page_indices": { "start_index": 3152490, "end_index": 3153642 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1609 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.3 AHB interface", 1607 ], [ 3, "37.3.1 Supported memories and transactions", 1608 ], [ 4, "Configuration registers", 1609 ], [ 2, "37.4 External device address mapping", 1609 ] ], "page_content": "RM0090 Rev 21\n1609/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nConfiguration registers\nThe FMC can be configured through a set of registers. Refer to Section 37.5.6, for a \ndetailed description of the NOR Flash/PSRAM controller registers. Refer to Section 37.6.8, \nfor a detailed description of the NAND Flash/PC Card registers and to Section 37.7.5 for a \ndetailed description of the SDRAM controller registers.\n37.4 \nExternal device address mapping\nFrom the FMC point of view, the external memory is divided into 6 fixed-size banks of \n256 Mbyte each (see Figure 457):\n•\nBank 1 used to address up to 4 NOR Flash memory or PSRAM devices. This bank is \nsplit into 4 NOR/PSRAM subbanks with 4 dedicated Chip Selects, as follows:\n–\nBank 1 - NOR/PSRAM 1\n–\nBank 1 - NOR/PSRAM 2\n–\nBank 1 - NOR/PSRAM 3\n–\nBank 1 - NOR/PSRAM 4\n•\nBanks 2 and 3 used to address NAND Flash memory devices (1 device per bank)\n•\nBank 4 used to address a PC Card\n•\nBank 5 and 6 used to address SDRAM devices (1 device per bank).\nFor each bank the type of memory to be used can be configured by the user application \nthrough the Configuration register.\n" }, { "page_number": 1610, "page_indices": { "start_index": 3153642, "end_index": 3154487 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1610 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.4 External device address mapping", 1609 ], [ 3, "37.4.1 NOR/PSRAM address mapping", 1610 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1610/1757\nRM0090 Rev 21\nFigure 457. FMC memory banks\n37.4.1 \nNOR/PSRAM address mapping\nHADDR[27:26] bits are used to select one of the four memory banks as shown in Table 255.\n \nBank 1\n4 x 64 MB\nNOR/PSRAM/SRAM\nSupported memory type\nBank\n0x6000 0000\nAddress\nPC Card\nMS30444V2\nSDRAM\n0x6FFF FFFF\n0x7000 0000\n0x7FFF FFFF\n0x8000 0000\n0x8FFF FFFF\n0x9000 0000\n0x9FFF FFFF\n0xC000 0000\n0xCFFF FFFF\n0xD000 0000\n0xDFFF FFFF\nBank 2\n4 x 64 MB\nBank 3\n4 x 64 MB\nBank 4\n4 x 64 MB\nSDRAM Bank 1\n4 x 64 MB\nSDRAM Bank 2\n4 x 64 MB\nNAND Flash memory\nTable 255. NOR/PSRAM bank selection\nHADDR[27:26](1)\n1.\nHADDR are internal AHB address lines that are translated to external memory.\nSelected bank\n00 \nBank 1 - NOR/PSRAM 1\n01 \nBank 1 - NOR/PSRAM 2\n10 \nBank 1 - NOR/PSRAM 3\n11 \nBank 1 - NOR/PSRAM 4\n" }, { "page_number": 1611, "page_indices": { "start_index": 3154487, "end_index": 3156709 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1611 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.4 External device address mapping", 1609 ], [ 3, "37.4.1 NOR/PSRAM address mapping", 1610 ], [ 4, "Wrap support for NOR Flash/PSRAM", 1611 ], [ 3, "37.4.2 NAND Flash memory/PC Card address mapping", 1611 ] ], "page_content": "RM0090 Rev 21\n1611/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nThe HADDR[25:0] bits contain the external memory address. Since HADDR is a byte \naddress whereas the memory is addressed at word level, the address actually issued to the \nmemory varies according to the memory data width, as shown in the following table.\n \nWrap support for NOR Flash/PSRAM\nWrap burst mode for synchronous memories is not supported. The memories must be \nconfigured in linear burst mode of undefined length.\n37.4.2 \nNAND Flash memory/PC Card address mapping\nIn this case, three banks are available, each of them being divided into memory areas as \nindicated in Table 257.\n \nFor NAND Flash memory, the common and attribute memory spaces are subdivided into \nthree sections (see in Table 258 below) located in the lower 256 Kbytes:\n•\nData section (first 64 Kbytes in the common/attribute memory space)\n•\nCommand section (second 64 Kbytes in the common / attribute memory space)\n•\nAddress section (next 128 Kbytes in the common / attribute memory space)\nTable 256. NOR/PSRAM External memory address\nMemory width(1)\n1.\nIn case of a 16-bit external memory width, the FMC internally uses HADDR[25:1] to generate the address \nfor external memory FMC_A[24:0]. In case of a 32-bit memory width, the FMC internally uses \nHADDR[25:2] to generate the external address. \nWhatever the external memory width, FMC_A[0] should be connected to external memory address A[0].\nData address issued to the memory\nMaximum memory capacity (bits) \n8-bit \nHADDR[25:0] \n64 Mbyte x 8 = 512 Mbit \n16-bit\nHADDR[25:1] >> 1 \n64 Mbyte/2 x 16 = 512 Mbit \n32-bit\nHADDR[25:2] >> 2\n64 Mbyte/4 x 32 = 512 Mbit \nTable 257. NAND/PC Card memory mapping and timing registers\nStart address\nEnd address\nFMC bank\nMemory space\nTiming register\n0x9C00 0000\n0x9FFF FFFF\nBank 4 - PC card\nI/O\nFMC_PIO4 (0xB0)\n0x9800 0000\n0x9BFF FFFF\nAttribute\n FMC_PATT4 (0xAC)\n0x9000 0000\n0x93FF FFFF\nCommon\n FMC_PMEM4 (0xA8)\n0x8800 0000\n0x8BFF FFFF\nBank 3 - NAND Flash\nAttribute\n FMC_PATT3 (0x8C)\n0x8000 0000\n0x83FF FFFF\nCommon\n FMC_PMEM3 (0x88)\n0x7800 0000\n0x7BFF FFFF\nBank 2- NAND Flash\nAttribute\nFMC_PATT2 (0x6C)\n0x7000 0000\n0x73FF FFFF\nCommon\n FMC_PMEM2 (0x68)\n" }, { "page_number": 1612, "page_indices": { "start_index": 3156709, "end_index": 3158607 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1612 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.4 External device address mapping", 1609 ], [ 3, "37.4.3 SDRAM address mapping", 1612 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1612/1757\nRM0090 Rev 21\n \nThe application software uses the 3 sections to access the NAND Flash memory:\n•\nTo send a command to NAND Flash memory, the software must write the command \nvalue to any memory location in the command section.\n•\nTo specify the NAND Flash address that must be read or written, the software \nmust write the address value to any memory location in the address section. Since an \naddress can be 4 or 5 byte long (depending on the actual memory size), several \nconsecutive write operations to the address section are required to specify the full \naddress.\n•\nTo read or write data, the software reads or writes the data from/to any memory \nlocation in the data section.\nSince the NAND Flash memory automatically increments addresses, there is no need to \nincrement the address of the data section to access consecutive memory locations.\n37.4.3 \nSDRAM address mapping \nThe HADDR[28] bit (internal AHB address line 28) is used to select one of the two memory \nbanks as indicated in Table 259.\n \nThe following table shows SDRAM mapping for an 13-bit row ,a 11-bit column and 4 internal \nbank configurations.\n \nTable 258. NAND bank selection\nSection name\nHADDR[17:16]\nAddress range\nAddress section \n1X \n0x020000-0x03FFFF \nCommand section \n01 \n0x010000-0x01FFFF \nData section \n00 \n0x000000-0x0FFFF \nTable 259. SDRAM bank selection\nHADDR[28]\nSelected bank\nControl register\nTiming register\n0\nSDRAM Bank1\nFMC_SDCR1\nFMC_SDTR1\n1\nSDRAM Bank2\nFMC_SDCR2\nFMC_SDTR2\nTable 260. SDRAM address mapping\nMemory width(1)\nInternal bank\nRow address\nColumn \naddress(2)\nMaximum \nmemory capacity \n(Mbyte)\n8-bit\nHADDR[25:24]\nHADDR[23:11]\nHADDR[10:0]\n64 Mbyte: \n4 x 8K x 2K\n16-bit\nHADDR[26:25]\nHADDR[24:12]\nHADDR[11:1]\n128 Mbyte: \n4 x 8K x 2K x 2\n32-bit\nHADDR[27:26]\nHADDR[25:13]\nHADDR[12:2]\n256 Mbyte:\n4 x 8K x 2K x 4\n" }, { "page_number": 1613, "page_indices": { "start_index": 3158607, "end_index": 3160485 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1613 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.4 External device address mapping", 1609 ], [ 3, "37.4.3 SDRAM address mapping", 1612 ] ], "page_content": "RM0090 Rev 21\n1613/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nThe HADDR[27:0] bits are translated to external SDRAM address depending on the \nSDRAM controller configuration:\n•\nData size:8, 16 or 32 bits\n•\nRow size:11, 12 or 13 bits\n•\nColumn size: 8, 9, 10 or 11 bits\n•\nNumber of internal banks: two or four internal banks\nTable 261 to Table 263 shows the SDRAM address mapping versus the SDRAM controller \nconfiguration. \n ) \n1.\nWhen interfacing with a 16-bit memory, the FMC internally uses the HADDR[11:1] internal AHB address \nlines to generate the external address. When interfacing with a 32-bit memory, the FMC internally uses \nHADDR[12:2] lines to generate the external address. Whatever the memory width, FMC_A[0] has to be \nconnected to the external memory address A[0].\n2.\nThe AutoPrecharge is not supported. FMC_A[10] must be connected to the external memory address \nA[10] but it is always driven ‘low’.\nTable 261. SDRAM address mapping with 8-bit data bus width(1)(2)\nRow size \nconfiguration\nHADDR(AHB Internal Address Lines)\n27 26 25 24\n23\n22\n21\n20\n19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\n11-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[7:0]\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[8:0]\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[9:0]\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[10:0]\n12-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[7:0]\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[8:0]\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[9:0]\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[10:0]\n13-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[7:0]\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[8:0]\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[9:0]\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[10:0]\n1.\nBANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’.\n2.\nAccess to Reserved (Res.) address range generates an AHB error.\n" }, { "page_number": 1614, "page_indices": { "start_index": 3160485, "end_index": 3162220 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1614 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.4 External device address mapping", 1609 ], [ 3, "37.4.3 SDRAM address mapping", 1612 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1614/1757\nRM0090 Rev 21\n )\n \nTable 262. SDRAM address mapping with 16-bit data bus width(1)(2)\nRow size \nConfiguration\nHADDR(AHB address Lines)\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n11-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[7:0]\nBM0(3)\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[8:0]\nBM0\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[9:0]\nBM0\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[10:0]\nBM0\n12-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[7:0]\nBM0\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[8:0]\nBM0\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[9:0]\nBM0\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[10:0]\nBM0\n13-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[7:0]\nBM0\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[8:0]\nBM0\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[9:0]\nBM0\nRe\ns.\nBank\n[1:0]\nRow[12:0]\nColumn[10:0]\nBM0\n1.\nBANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’.\n2.\nAccess to Reserved space (Res.) generates an AHB error. \n3.\nBM0: is the byte mask for 16-bit access.\nTable 263. SDRAM address mapping with 32-bit data bus width(1)(2)\nRow size \nconfiguration\nHADDR(AHB address Lines)\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n11-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[7:0]\nBM[1:0](3)\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[8:0]\nBM[1:0]\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[9:0]\nBM[1:0]\nRes.\nBank\n[1:0]\nRow[10:0]\nColumn[10:0]\nBM[1:0]\n12-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[7:0]\nBM[1:0]\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[8:0]\nBM[1:0]\nRes.\nBank\n[1:0]\nRow[11:0]\nColumn[9:0]\nBM[1:0]\nRes. Bank\n[1:0]\nRow[11:0]\nColumn[10:0]\nBM[1:0]\n" }, { "page_number": 1615, "page_indices": { "start_index": 3162220, "end_index": 3164043 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1615 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ] ], "page_content": "RM0090 Rev 21\n1615/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n37.5 \nNOR Flash/PSRAM controller\nThe FMC generates the appropriate signal timings to drive the following types of memories:\n•\nAsynchronous SRAM and ROM\n–\n8 bits\n–\n16 bits\n–\n32 bits\n•\nPSRAM (Cellular RAM)\n–\nAsynchronous mode\n–\nBurst mode for synchronous accesses\n–\nMultiplexed or non-multiplexed\n•\nNOR Flash memory\n–\nAsynchronous mode \n–\nBurst mode for synchronous accesses\n–\nMultiplexed or non-multiplexed\nThe FMC outputs a unique Chip Select signal, NE[4:1], per bank. All the other signals \n(addresses, data and control) are shared.\nThe FMC supports a wide range of devices through a programmable timings among which:\n•\nProgrammable wait states (up to 15)\n•\nProgrammable bus turnaround cycles (up to 15)\n•\nProgrammable output enable and write enable delays (up to 15)\n•\nIndependent read and write timings and protocol to support the widest variety of \nmemories and timings\n•\nProgrammable continuous clock (FMC_CLK) output.\nThe FMC Clock (FMC_CLK) is a submultiple of the HCLK clock. It can be delivered to the \nselected external device either during synchronous accesses only or during asynchronous \n13-bit row size\nconfiguration\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[7:0]\nBM[1:0]\nRes.\nBank\n[1:0]\nRow[12:0]\nColumn[8:0]\nBM[1:0]\nRes. Bank\n[1:0]\nRow[12:0]\nColumn[9:0]\nBM[1:0]\nBank\n[1:0]\nRow[12:0]\nColumn[10:0]\nBM[1:0]\n1.\nBANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’.\n2.\nAccess to Reserved space (Res.) generates an AHB error.\n3.\nBM[1:0]: is the byte mask for 32-bit access.\nTable 263. SDRAM address mapping with 32-bit data bus width(1)(2) (continued)\nRow size \nconfiguration\nHADDR(AHB address Lines)\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1616, "page_indices": { "start_index": 3164043, "end_index": 3166349 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1616 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.1 External memory interface signals", 1616 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1616/1757\nRM0090 Rev 21\nand synchronous accesses depending on the CCKEN bit configuration in the FMC_BCR1 \nregister:\n•\nIf the CCLKEN bit is reset, the FMC generates the clock (CLK) only during \nsynchronous accesses (Read/write transactions). \n•\nIf the CCLKEN bit is set, the FMC generates a continuous clock during asynchronous \nand synchronous accesses. To generate the FMC_CLK continuous clock, Bank 1 must \nbe configured in synchronous mode (see Section 37.5.6: NOR/PSRAM controller \nregisters). Since the same clock is used for all synchronous memories, when a \ncontinuous output clock is generated and synchronous accesses are performed, the \nAHB data size has to be the same as the memory data width (MWID) otherwise the \nFMC_CLK frequency is changed depending on AHB data transaction (refer to \nSection 37.5.5: Synchronous transactions for FMC_CLK divider ratio formula). \nThe size of each bank is fixed and equal to 64 Mbyte. Each bank is configured through \ndedicated registers (see Section 37.5.6: NOR/PSRAM controller registers).\nThe programmable memory parameters include access times (see Table 264) and support \nfor wait management (for PSRAM and NOR Flash accessed in burst mode).\n \n37.5.1 \nExternal memory interface signals\nTable 265, Table 266 and Table 267 list the signals that are typically used to interface with \nNOR Flash memory, SRAM and PSRAM.\nNote:\nThe prefix “N” identifies the signals which are active low.\nTable 264. Programmable NOR/PSRAM access parameters\nParameter \nFunction \nAccess mode \nUnit \nMin. \nMax. \nAddress \nsetup\nDuration of the address \nsetup phase \nAsynchronous \nAHB clock cycle \n(HCLK) \n0\n15\nAddress hold\nDuration of the address hold \nphase \nAsynchronous, \nmuxed I/Os \nAHB clock cycle \n(HCLK) \n1\n15\nData setup\nDuration of the data setup \nphase \nAsynchronous \nAHB clock cycle \n(HCLK) \n1\n256\nBust turn\nDuration of the bus \nturnaround phase \nAsynchronous and \nsynchronous \nread/write\nAHB clock cycle \n(HCLK) \n0\n15\nClock divide \nratio\nNumber of AHB clock cycles \n(HCLK) to build one memory \nclock cycle (CLK) \nSynchronous\nAHB clock cycle \n(HCLK) \n2\n16 \nData latency\nNumber of clock cycles to \nissue to the memory before \nthe first data of the burst \nSynchronous\nMemory clock \ncycle (CLK) \n2\n17 \n" }, { "page_number": 1617, "page_indices": { "start_index": 3166349, "end_index": 3167779 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1617 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.1 External memory interface signals", 1616 ], [ 4, "NOR Flash memory, non-multiplexed I/Os", 1617 ], [ 4, "NOR Flash memory, 16-bit multiplexed I/Os", 1617 ], [ 4, "PSRAM/SRAM, non-multiplexed I/Os", 1617 ] ], "page_content": "RM0090 Rev 21\n1617/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nNOR Flash memory, non-multiplexed I/Os\n \nThe maximum capacity is 512 Mbits (26 address lines).\nNOR Flash memory, 16-bit multiplexed I/Os\n \nThe maximum capacity is 512 Mbits.\nPSRAM/SRAM, non-multiplexed I/Os\n \nTable 265. Non-multiplexed I/O NOR Flash memory\nFMC signal name\nI/O\nFunction\nCLK \nO \nClock (for synchronous access) \nA[25:0] \nO \nAddress bus \nD[31:0] \nI/O \nBidirectional data bus \nNE[x]\nO \nChip Select, x = 1..4\nNOE\nO \nOutput enable \nNWE\nO \nWrite enable \nNL(=NADV)\nO \nLatch enable (this signal is called address \nvalid, NADV, by some NOR Flash devices) \nNWAIT\nI \nNOR Flash wait input signal to the FMC \nTable 266. 16-bit multiplexed I/O NOR Flash memory\nFMC signal name \nI/O \nFunction \nCLK \nO \nClock (for synchronous access) \nA[25:16] \nO \nAddress bus \nAD[15:0] \nI/O \n16-bit multiplexed, bidirectional address/data bus (the 16-bit address \nA[15:0] and data D[15:0] are multiplexed on the databus)\nNE[x]\nO \nChip Select, x = 1..4\nNOE\nO \nOutput enable \nNWE\nO \nWrite enable \nNL(=NADV)\nO \nLatch enable (this signal is called address valid, NADV, by some NOR \nFlash devices) \nNWAIT\nI \nNOR Flash wait input signal to the FMC \nTable 267. Non-multiplexed I/Os PSRAM/SRAM\nFMC signal name\nI/O \nFunction \nCLK \nO \nClock (only for PSRAM synchronous access) \nA[25:0] \nO \nAddress bus \nD[31:0] \nI/O \nData bidirectional bus \n" }, { "page_number": 1618, "page_indices": { "start_index": 3167779, "end_index": 3169510 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1618 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.1 External memory interface signals", 1616 ], [ 4, "PSRAM, 16-bit multiplexed I/Os", 1618 ], [ 3, "37.5.2 Supported memories and transactions", 1618 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1618/1757\nRM0090 Rev 21\nThe maximum capacity is 512 Mbits.\nPSRAM, 16-bit multiplexed I/Os\n \nThe maximum capacity is 512 Mbits (26 address lines).\n37.5.2 \nSupported memories and transactions\nTable 269 below shows an example of the supported devices, access modes and \ntransactions when the memory data bus is 16-bit wide for NOR Flash memory, PSRAM and \nSRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in \nthis example.\nNE[x]\nO \nChip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. \nCRAM))\nNOE\nO \nOutput enable \nNWE\nO \nWrite enable \nNL(= NADV)\nO \nAddress valid only for PSRAM input (memory signal name: NADV) \nNWAIT\nI \nPSRAM wait input signal to the FMC \nNBL[3] \nO \nByte3 Upper byte enable (memory signal name: NUB) \nNBL[2] \nO \nByte2 Lowed byte enable (memory signal name: NLB) \nNBL[1] \nO \nByte1 Upper byte enable (memory signal name: NLB) \nNBL[0] \nO \nByte0 Lower byte enable (memory signal name: NLB) \nTable 268. 16-Bit multiplexed I/O PSRAM\nFMC signal name\nI/O \nFunction \nCLK \nO \nClock (for synchronous access) \nA[25:16] \nO \nAddress bus \nAD[15:0] \nI/O \n16-bit multiplexed, bidirectional address/data bus (the 16-bit address \nA[15:0] and data D[15:0] are multiplexed on the databus)\nNE[x]\nO \nChip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. \nCRAM))\nNOE\nO \nOutput enable \nNWE\nO \nWrite enable \nNL(= NADV)\nO \nAddress valid PSRAM input (memory signal name: NADV) \nNWAIT\nI \nPSRAM wait input signal to the FMC \nNBL[1] \nO \nUpper byte enable (memory signal name: NUB) \nNBL[0] \nO \nLowed byte enable (memory signal name: NLB) \nTable 267. Non-multiplexed I/Os PSRAM/SRAM (continued)\nFMC signal name\nI/O \nFunction \n" }, { "page_number": 1619, "page_indices": { "start_index": 3169510, "end_index": 3170941 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1619 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.2 Supported memories and transactions", 1618 ] ], "page_content": "RM0090 Rev 21\n1619/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n Table 269. NOR Flash/PSRAM: Example of supported memories and transactions\nDevice\nMode\nR/W\nAHB \ndata \nsize\nMemory \ndata size\nAllowed/\nnot \nallowed \nComments\nNOR Flash \n(muxed I/Os \nand nonmuxed \nI/Os) \nAsynchronous\nR \n8 \n16 \nY \n-\nAsynchronous \nW \n8 \n16 \nN \n-\nAsynchronous\nR \n16 \n16 \nY \n-\nAsynchronous\nW \n16 \n16 \nY \n-\nAsynchronous \nR \n32 \n16 \nY \nSplit into 2 FMC accesses \nAsynchronous \nW \n32 \n16 \nY \nSplit into 2 FMC accesses \nAsynchronous \npage \nR \n-\n16 \nN \nMode is not supported \nSynchronous \nR \n8 \n16 \nN \n-\nSynchronous \nR \n16 \n16 \nY \n-\nSynchronous \nR \n32 \n16 \nY \n-\nPSRAM \n(multiplexed \nI/Os and non-\nmultiplexed \nI/Os)\nAsynchronous\nR \n8 \n16 \nY \n-\nAsynchronous \nW \n8 \n16 \nY \nUse of byte lanes NBL[1:0] \nAsynchronous\nR \n16 \n16 \nY \n-\nAsynchronous\nW \n16 \n16 \nY \n-\nAsynchronous \nR \n32 \n16 \nY \nSplit into 2 FMC accesses \nAsynchronous \nW \n32 \n16 \nY \nSplit into 2 FMC accesses \nAsynchronous \npage \nR \n-\n16 \nN \nMode is not supported \nSynchronous \nR \n8 \n16 \nN \n-\nSynchronous \nR \n16 \n16 \nY \n-\nSynchronous \nR \n32 \n16 \nY \n-\nSynchronous\nW\n8\n16\nY\nUse of byte lanes NBL[1:0]\nSynchronous\nW\n16/32\n16\nY\n-\nSRAM and \nROM\nAsynchronous \nR \n8 / 16 \n16\nY \n-\nAsynchronous \nW \n8 / 16 \n16\nY \nUse of byte lanes NBL[1:0] \nAsynchronous \nR \n32 \n16\nY \nSplit into 2 FMC accesses \nAsynchronous \nW \n32 \n16\nY \nSplit into 2 FMC accesses \nUse of byte lanes NBL[1:0]\n" }, { "page_number": 1620, "page_indices": { "start_index": 3170941, "end_index": 3172588 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1620 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.3 General timing rules", 1620 ], [ 4, "Signals synchronization", 1620 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "Asynchronous static memories (NOR Flash, PSRAM, SRAM)", 1620 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1620/1757\nRM0090 Rev 21\n37.5.3 \nGeneral timing rules\nSignals synchronization\n•\nAll controller output signals change on the rising edge of the internal clock (HCLK)\n•\nIn synchronous mode (read or write), all output signals change on the rising edge of \nHCLK. Whatever the CLKDIV value, all outputs change as follows:\n–\nNOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the \nfalling edge of FMC_CLK clock.\n–\nNOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising \nedge of FMC_CLK clock.\n37.5.4 \nNOR Flash/PSRAM controller asynchronous transactions\nAsynchronous static memories (NOR Flash, PSRAM, SRAM)\n•\nSignals are synchronized by the internal clock HCLK. This clock is not issued to the \nmemory\n•\nThe FMC always samples the data before de-asserting the NOE signal. This \nguarantees that the memory data hold timing constraint is met (minimum Chip Enable \nhigh to data transition is usually 0 ns)\n•\nIf the extended mode is enabled (EXTMOD bit is set in the FMC_BCRx register), up to \nfour extended modes (A, B, C and D) are available. It is possible to mix A, B, C and D \nmodes for read and write operations. For example, read operation can be performed in \nmode A and write in mode B.\n•\nIf the extended mode is disabled (EXTMOD bit is reset in the FMC_BCRx register), the \nFMC can operate in Mode1 or Mode2 as follows:\n–\nMode 1 is the default mode when SRAM/PSRAM memory type is selected \n(MTYP[1:0] = 0x0 or 0x01 in the FMC_BCRx register)\n–\nMode 2 is the default mode when NOR memory type is selected \n(MTYP[1:0] = 0x10 in the FMC_BCRx register).\n" }, { "page_number": 1621, "page_indices": { "start_index": 3172588, "end_index": 3173228 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1621 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "Mode 1 - SRAM/PSRAM (CRAM)", 1621 ] ], "page_content": "RM0090 Rev 21\n1621/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nMode 1 - SRAM/PSRAM (CRAM)\nThe next figures show the read and write transactions for the supported modes followed by \nthe required configuration of FMC _BCRx, and FMC_BTRx/FMC_BWTRx registers. \nFigure 458. Mode1 read access waveforms\nFigure 459. Mode1 write access waveforms\nA[25:0]\nNOE\nADDSET\nDATAST \nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\nHCLK cycles\nNWE\nNBL[3:0]\ndata driven\nby memory\nMS30452V1\nHigh\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\nHCLK cycles\nNWE\nNBL[3:0]\ndata driven by FSMC\nMS30453V1\n1HCLK\n" }, { "page_number": 1622, "page_indices": { "start_index": 3173228, "end_index": 3174513 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1622 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "Mode 1 - SRAM/PSRAM (CRAM)", 1621 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1622/1757\nRM0090 Rev 21\nThe one HCLK cycle at the end of the write transaction helps guarantee the address and \ndata hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the \nDATAST value must be greater than zero (DATAST > 0).\n \n \nTable 270. FMC_BCRx bit fields\nBit \nnumber\nBit name\nValue to set\n31-21\nReserved\n0x000\n20\nCCLKEN\nAs needed\n19\nCBURSTRW\n0x0 (no effect in asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect in asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at \n0.\n14\nEXTMOD\n0x0\n13\nWAITEN\n0x0 (no effect in asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0\n7 \nReserved\n0x1\n6 \nFACCEN\nDon’t care\n5-4 \nMWID\nAs needed\n3-2 \nMTYP[1:0]\nAs needed, exclude 0x2 (NOR Flash memory)\n1 \nMUXE\n0x0\n0 \nMBKEN \n0x1\nTable 271. FMC_BTRx bit fields\nBit \nnumber\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\nDon’t care\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST+1 HCLK cycles for \nwrite accesses, DATAST HCLK cycles for read accesses). \n" }, { "page_number": 1623, "page_indices": { "start_index": 3174513, "end_index": 3175065 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1623 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "Mode A - SRAM/PSRAM (CRAM) OE toggling", 1623 ] ], "page_content": "RM0090 Rev 21\n1623/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nMode A - SRAM/PSRAM (CRAM) OE toggling\nFigure 460. ModeA read access waveforms\n1.\nNBL[3:0] are driven low during the read access\n7-4\nADDHLD\nDon’t care\n3-0\nADDSET\nDuration of the first access phase (ADDSET HCLK cycles).\nMinimum value for ADDSET is 0.\nTable 271. FMC_BTRx bit fields (continued)\nBit \nnumber\nBit name\nValue to set\nA[25:0]\nNOE\nADDSET \nDATAST\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\nHCLK cycles\nNWE\nNBL[3:0]\ndata driven\nby memory\nMS30454V1\nHigh\n" }, { "page_number": 1624, "page_indices": { "start_index": 3175065, "end_index": 3175945 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1624 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "Mode A - SRAM/PSRAM (CRAM) OE toggling", 1623 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1624/1757\nRM0090 Rev 21\nFigure 461. ModeA write access waveforms\nThe differences compared with mode1 are the toggling of NOE and the independent read \nand write timings.\n \nTable 272. FMC_BCRx bit fields\nBit \nnumber\nBit name \nValue to set\n31-21\nReserved\n0x000\n20\nCCLKEN\nAs needed\n19\nCBURSTRW\n0x0 (no effect in asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect in asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at \n0.\n14 \nEXTMOD\n0x1\n13\nWAITEN\n0x0 (no effect in asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0\n7 \nReserved\n0x1\n6 \nFACCEN\nDon’t care\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\nHCLK cycles\nNWE\nNBL[3:0]\ndata driven by FSMC\nMS30455V1\n1HCLK\n" }, { "page_number": 1625, "page_indices": { "start_index": 3175945, "end_index": 3177140 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1625 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "Mode A - SRAM/PSRAM (CRAM) OE toggling", 1623 ] ], "page_content": "RM0090 Rev 21\n1625/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n \n \n5-4 \nMWID \nAs needed\n3-2 \nMTYP[1:0]\nAs needed, exclude 0x2 (NOR Flash memory)\n1 \nMUXEN\n0x0\n0 \nMBKEN\n0x1\nTable 273. FMC_BTRx bit fields\nBit \nnumber\nBit name \nValue to set \n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x0\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for read \naccesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for read \naccesses.\nMinimum value for ADDSET is 0.\nTable 274. FMC_BWTRx bit fields\nBit \nnumber\nBit name \nValue to set \n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x0\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for write \naccesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for write \naccesses.\nMinimum value for ADDSET is 0.\nTable 272. FMC_BCRx bit fields (continued)\nBit \nnumber\nBit name \nValue to set\n" }, { "page_number": 1626, "page_indices": { "start_index": 3177140, "end_index": 3177653 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1626 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "Mode 2/B - NOR Flash", 1626 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1626/1757\nRM0090 Rev 21\nMode 2/B - NOR Flash\nFigure 462. Mode2 and mode B read access waveforms\n1.\nNBL[3:0] are driven low during the read access\nFigure 463. Mode2 write access waveforms\nA[25:0]\nNOE\nADDSET \nDATAST\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven\nby memory\nMS30456V1\nHigh\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\nHCLK cycles\nNWE\nNADV\ndata driven by FSMC\nMS30457V1\n1HCLK\n" }, { "page_number": 1627, "page_indices": { "start_index": 3177653, "end_index": 3178584 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1627 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "Mode 2/B - NOR Flash", 1626 ] ], "page_content": "RM0090 Rev 21\n1627/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nFigure 464. ModeB write access waveforms \nThe differences with mode1 are the toggling of NWE and the independent read and write \ntimings when extended mode is set (Mode B).\n \nTable 275. FMC_BCRx bit fields\nBit \nnumber\nBit name \nValue to set \n31-21\nReserved\n0x000\n20\nCCLKEN\nAs needed\n19\nCBURSTRW\n0x0 (no effect in asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect in asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at \n0.\n14 \nEXTMOD\n0x1 for mode B, 0x0 for mode 2\n13\nWAITEN\n0x0 (no effect in asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0 \n7 \nReserved\n0x1\n6 \nFACCEN\n0x1\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven by FSMC\nMS30458V1.\n1HCLK\n" }, { "page_number": 1628, "page_indices": { "start_index": 3178584, "end_index": 3179923 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1628 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "Mode 2/B - NOR Flash", 1626 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1628/1757\nRM0090 Rev 21\n \n \nNote:\nThe FMC_BWTRx register is valid only if the extended mode is set (mode B), otherwise its \ncontent is don’t care.\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[1:0]\n0x2 (NOR Flash memory)\n1 \nMUXEN\n0x0 \n0 \nMBKEN\n0x1 \nTable 276. FMC_BTRx bit fields\nBit number\nBit name \nValue to set \n31-30\nReserved\n0x0\n29-28\nACCMOD\n0x1 if extended mode is set\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the access second phase (DATAST HCLK cycles) for \nread accesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the access first phase (ADDSET HCLK cycles) for read \naccesses. Minimum value for ADDSET is 0.\nTable 277. FMC_BWTRx bit fields\nBit number\nBit name \nValue to set \n31-30\nReserved\n0x0\n29-28\nACCMOD\n0x1 if extended mode is set\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the access second phase (DATAST HCLK cycles) for \nwrite accesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the access first phase (ADDSET HCLK cycles) for write \naccesses. Minimum value for ADDSET is 0.\nTable 275. FMC_BCRx bit fields (continued)\nBit \nnumber\nBit name \nValue to set \n" }, { "page_number": 1629, "page_indices": { "start_index": 3179923, "end_index": 3180500 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1629 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "Mode C - NOR Flash - OE toggling", 1629 ] ], "page_content": "RM0090 Rev 21\n1629/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nMode C - NOR Flash - OE toggling\nFigure 465. ModeC read access waveforms \nFigure 466. ModeC write access waveforms \nThe differences compared with mode1 are the toggling of NOE and the independent read \nand write timings.\nA[25:0]\nNOE\nADDSET \nDATAST\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven\nby memory\nMS30459V1\nHigh\nA[25:0]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven by FSMC\nMS30460V1\n1HCLK\n" }, { "page_number": 1630, "page_indices": { "start_index": 3180500, "end_index": 3181613 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1630 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "Mode C - NOR Flash - OE toggling", 1629 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1630/1757\nRM0090 Rev 21\n \n \nTable 278. FMC_BCRx bit fields\nBit No.\nBit name\nValue to set\n31-21\nReserved\n0x000\n20\nCCLKEN\nAs needed\n19\nCBURSTRW\n0x0 (no effect in asynchronous mode)\n18:16\nReserved\n0x0 (no effect in asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at 0.\n14 \nEXTMOD\n0x1\n13\nWAITEN\n0x0 (no effect in asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0 \n7 \nReserved\n0x1\n6 \nFACCEN\n0x1\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[1:0]\n0x02 (NOR Flash memory)\n1 \nMUXEN\n0x0 \n0 \nMBKEN\n0x1 \nTable 279. FMC_BTRx bit fields\nBit No.\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x2\n27-24\nDATLAT\n0x0\n23-20\nCLKDIV\n0x0\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for \nread accesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for read \naccesses. Minimum value for ADDSET is 0.\n" }, { "page_number": 1631, "page_indices": { "start_index": 3181613, "end_index": 3182400 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1631 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "Mode D - asynchronous access with extended address", 1631 ] ], "page_content": "RM0090 Rev 21\n1631/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n \nMode D - asynchronous access with extended address\nFigure 467. ModeD read access waveforms\nTable 280. FMC_BWTRx bit fields\nBit No.\nBit name\nValue to set\n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x2\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for \nwrite accesses. \n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for write \naccesses. Minimum value for ADDSET is 0.\nA[25:0]\nNOE\nADDSET \nDATAST\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven\nby memory\nMS30461V1\nHigh\nADDHLD\nHCLK cycles\n" }, { "page_number": 1632, "page_indices": { "start_index": 3182400, "end_index": 3183365 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1632 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "Mode D - asynchronous access with extended address", 1631 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1632/1757\nRM0090 Rev 21\nFigure 468. ModeD write access waveforms\nThe differences with mode1 are the toggling of NOE that goes on toggling after NADV \nchanges and the independent read and write timings.\n \nTable 281. FMC_BCRx bit fields\nBit No.\nBit name \nValue to set \n31-21\nReserved\n0x000\n20\nCCLKEN\nAs needed\n19\nCBURSTRW\n0x0 (no effect in asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect in asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep \nat 0.\n14 \nEXTMOD\n0x1\n13\nWAITEN\n0x0 (no effect in asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0 \n7 \nReserved\n0x1\n6 \nFACCEN\nSet according to memory support\n5-4 \nMWID\nAs needed\nA[25:0]\nNOE\nADDSET \n(DATAST+ 1)\nMemory transaction\nNEx\nD[31:0]\nHCLK cycles\nHCLK cycles\nNWE\nNADV\ndata driven by FSMC\nMS30462V1\n1HCLK\nADDHLD\nHCLK cycles\n" }, { "page_number": 1633, "page_indices": { "start_index": 3183365, "end_index": 3184621 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1633 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "Mode D - asynchronous access with extended address", 1631 ] ], "page_content": "RM0090 Rev 21\n1633/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n \n \n3-2 \nMTYP[1:0]\nAs needed\n1 \nMUXEN\n0x0 \n0 \nMBKEN\n0x1 \nTable 282. FMC_BTRx bit fields\nBit No.\nBit name\nValue to set \n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x3\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles) for \nread accesses. \n7-4\nADDHLD\nDuration of the middle phase of the read access (ADDHLD HCLK \ncycles) \n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for read \naccesses. Minimum value for ADDSET is 1.\nTable 283. FMC_BWTRx bit fields\nBit No.\nBit name\nValue to set \n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x3\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST + 1 HCLK cycles) for \nwrite accesses. \n7-4\nADDHLD\nDuration of the middle phase of the write access (ADDHLD HCLK \ncycles) \n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles) for write \naccesses. Minimum value for ADDSET is 1.\nTable 281. FMC_BCRx bit fields (continued)\nBit No.\nBit name \nValue to set \n" }, { "page_number": 1634, "page_indices": { "start_index": 3184621, "end_index": 3185107 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1634 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "Muxed mode - multiplexed asynchronous access to NOR Flash memory", 1634 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1634/1757\nRM0090 Rev 21\nMuxed mode - multiplexed asynchronous access to NOR Flash memory\nFigure 469. Muxed read access waveforms\nFigure 470. Muxed write access waveforms\nThe difference with mode D is the drive of the lower address byte(s) on the data bus.\nA[25:16]\nNOE\nADDSET \n(DATAST + 1)\nMemory transaction\nNEx\nAD[15:0]\nHCLK cycles\n HCLK cycles\nNWE\nNADV\ndata driven by FSMC\nai15569\n1HCLK\nADDHLD\nHCLK cycles\nLower address\n" }, { "page_number": 1635, "page_indices": { "start_index": 3185107, "end_index": 3186532 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1635 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "WAIT management in asynchronous accesses", 1635 ] ], "page_content": "RM0090 Rev 21\n1635/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n \n \nWAIT management in asynchronous accesses\nIf the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to \naccept or to provide data, the ASYNCWAIT bit has to be set in FMC_BCRx register.\nTable 284. FMC_BCRx bit fields\nBit No.\nBit name\nValue to set\n31-21\nReserved\n0x000\n20\nCCLKEN\nAs needed\n19\nCBURSTRW\n0x0 (no effect in asynchronous mode)\n18:16\nCPSIZE\n0x0 (no effect in asynchronous mode)\n15\nASYNCWAIT\nSet to 1 if the memory supports this feature. Otherwise keep at \n0.\n14 \nEXTMOD\n0x0\n13\nWAITEN\n0x0 (no effect in asynchronous mode)\n12\nWREN\nAs needed\n11\nWAITCFG\nDon’t care\n10\nWRAPMOD\n0x0\n9 \nWAITPOL \nMeaningful only if bit 15 is 1\n8 \nBURSTEN\n0x0 \n7 \nReserved\n0x1\n6 \nFACCEN\n0x1\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[1:0]\n0x2 (NOR Flash memory)\n1 \nMUXEN\n0x1\n0 \nMBKEN\n0x1 \nTable 285. FMC_BTRx bit fields\nBit No.\nBit name \nValue to set \n31:30\nReserved\n0x0\n29-28\nACCMOD\n0x0\n27-24\nDATLAT\nDon’t care\n23-20\nCLKDIV\nDon’t care\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK) \n15-8\nDATAST\nDuration of the second access phase (DATAST HCLK cycles for \nread accesses and DATAST+1 HCLK cycles for write accesses). \n7-4\nADDHLD\nDuration of the middle phase of the access (ADDHLD HCLK cycles).\n3-0\nADDSET[3:0]\nDuration of the first access phase (ADDSET HCLK cycles). \nMinimum value for ADDSET is 1.\n" }, { "page_number": 1636, "page_indices": { "start_index": 3186532, "end_index": 3188135 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1636 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.4 NOR Flash/PSRAM controller asynchronous transactions", 1620 ], [ 4, "WAIT management in asynchronous accesses", 1635 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1636/1757\nRM0090 Rev 21\nIf the WAIT signal is active (high or low depending on the WAITPOL bit), the second access \nphase (Data setup phase), programmed by the DATAST bits, is extended until WAIT \nbecomes inactive. Unlike the data setup phase, the first access phases (Address setup and \nAddress hold phases), programmed by the ADDSET[3:0] and ADDHLD bits, are not WAIT \nsensitive and so they are not prolonged.\nThe data setup phase must be programmed so that WAIT can be detected 4 HCLK cycles \nbefore the end of the memory transaction. The following cases must be considered:\n1.\nThe memory asserts the WAIT signal aligned to NOE/NWE which toggles:\n2. \nThe memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):\nif \nthen:\notherwise\nwhere max_wait_assertion_time is the maximum time taken by the memory to assert \nthe WAIT signal once NEx/NOE/NWE is low.\nFigure 471 and Figure 472 show the number of HCLK clock cycles that are added to the \nmemory access phase after WAIT is released by the asynchronous memory (independently \nof the above cases).\nFigure 471. Asynchronous wait during a read access waveforms\n1.\nNWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register. \nDATAST\n4\nHCLK\n×\n(\n)\nmax_wait_assertion_time\n+\n≥\nmax_wait_assertion_time\naddress_phase\nhold_phase\n+\n>\nDATAST\n4\nHCLK\n×\n(\n)\nmax_wait_assertion_time\naddress_phase\n–\nhold_phase\n–\n(\n)\n+\n≥\nDATAST\n4\nHCLK\n×\n≥\nA[25:0]\nNOE\n4HCLK \nMemory transaction\nD[15:0]\nNEx\ndata driven by memory\nMS30463V2\naddress phase\ndata setup phase\nNWAIT\ndon’t care\ndon’t care\n" }, { "page_number": 1637, "page_indices": { "start_index": 3188135, "end_index": 3189639 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1637 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.5 Synchronous transactions", 1637 ], [ 4, "Data latency versus NOR memory latency", 1637 ] ], "page_content": "RM0090 Rev 21\n1637/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nFigure 472. Asynchronous wait during a write access waveforms\n1.\nNWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register. \n37.5.5 \nSynchronous transactions\nThe memory clock, FMC_CLK, is a submultiple of HCLK. It depends on the value of \nCLKDIV and the MWID/ AHB data size, following the formula given below:\nIf MWID is 16 or 8 bits, the FMC_CLK divider ratio is always defined by the programmed \nCLKDIV value.\nIf MWID is 32 bits, the FMC_CLK divider ratio depends also on AHB data size.\nExample: \n•\nIf CLKDIV=1, MWID=32 bits, AHB data size=8 bits, FMC_CLK=HCLK/4.\n•\nIf CLKDIV=1, MWID=16 bits, AHB data size=8 bits, FMC_CLK=HCLK/2.\nNOR Flash memories specify a minimum time from NADV assertion to CLK high. To meet \nthis constraint, the FMC does not issue the clock to the memory during the first internal \nclock cycle of the synchronous access (before NADV assertion). This guarantees that the \nrising edge of the memory clock occurs in the middle of the NADV low pulse.\nData latency versus NOR memory latency\nThe data latency is the number of cycles to wait before sampling the data. The DATLAT \nvalue must be consistent with the latency value specified in the NOR Flash configuration \nA[25:0]\nNWE\nMemory transaction\nD[15:0]\nNEx\ndata driven by FSMC\nMS30464V2\n3HCLK \naddress phase\ndata setup phase\n1HCLK \nNWAIT\ndon’t care\ndon’t care\nFMC_CLK divider ratio\nmax CLKDIV\n1\n+\nMWID AHB data size\n(\n)\n(\n,\n)\n=\n" }, { "page_number": 1638, "page_indices": { "start_index": 3189639, "end_index": 3192536 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1638 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.5 Synchronous transactions", 1637 ], [ 4, "Single-burst transfer", 1638 ], [ 4, "Cross boundary page for Cellular RAM 1.5", 1638 ], [ 4, "Wait management", 1638 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1638/1757\nRM0090 Rev 21\nregister. The FMC does not include the clock cycle when NADV is low in the data latency \ncount.\nCaution:\nSome NOR Flash memories include the NADV Low cycle in the data latency count, so that \nthe exact relation between the NOR Flash latency and the FMC DATLAT parameter can be \neither:\n•\nNOR Flash latency = (DATLAT + 2) CLK clock cycles\n•\nor NOR Flash latency = (DATLAT + 3) CLK clock cycles\nSome recent memories assert NWAIT during the latency phase. In such cases DATLAT can \nbe set to its minimum value. As a result, the FMC samples the data and waits long enough \nto evaluate if the data are valid. Thus the FMC detects when the memory exits latency and \nreal data are processed.\nOther memories do not assert NWAIT during latency. In this case the latency must be set \ncorrectly for both the FMC and the memory, otherwise invalid data are mistaken for good \ndata, or valid data are lost in the initial phase of the memory access.\nSingle-burst transfer\nWhen the selected bank is configured in burst mode for synchronous accesses, if for \nexample an AHB single-burst transaction is requested on 16-bit memories, the FMC \nperforms a burst transaction of length 1 (if the AHB transfer is 16 bits), or length 2 (if the \nAHB transfer is 32 bits) and de-assert the Chip Select signal when the last data is strobed.\nSuch transfers are not the most efficient in terms of cycles compared to asynchronous read \noperations. Nevertheless, a random asynchronous access would first require to re-program \nthe memory access mode, which would altogether last longer.\nCross boundary page for Cellular RAM 1.5\nCellular RAM 1.5 does not allow burst access to cross the page boundary. The FMC \ncontroller allows to split automatically the burst access when the memory page size is \nreached by configuring the CPSIZE bits in the FMC_BCR1 register following the memory \npage size.\nWait management\nFor synchronous NOR Flash memories, NWAIT is evaluated after the programmed latency \nperiod, which corresponds to (DATLAT+2) CLK clock cycles.\nIf NWAIT is active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait \nstates are inserted until NWAIT is inactive (high level when WAITPOL = 0, low level when \nWAITPOL = 1).\nWhen NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1) \nor on the next clock edge (bit WAITCFG = 0).\nDuring wait-state insertion via the NWAIT signal, the controller continues to send clock \npulses to the memory, keeping the Chip Select and output enable signals valid. It does not \nconsider the data as valid.\nIn burst mode, there are two timing configurations for the NOR Flash NWAIT signal:\n•\nThe Flash memory asserts the NWAIT signal one data cycle before the wait state \n(default after reset).\n•\nThe Flash memory asserts the NWAIT signal during the wait state\n" }, { "page_number": 1639, "page_indices": { "start_index": 3192536, "end_index": 3193442 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1639 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.5 Synchronous transactions", 1637 ], [ 4, "Wait management", 1638 ] ], "page_content": "RM0090 Rev 21\n1639/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nThe FMC supports both NOR Flash wait state configurations, for each Chip Select, thanks \nto the WAITCFG bit in the FMC_BCRx registers (x = 0..3).\nFigure 473. Wait configuration waveforms\nFigure 474. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM)\n1.\nByte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, \naddr[15:0]\ndata\ndata\naddr[25:16]\nMemory transaction = burst of 4 half words\nHCLK\nCLK\nA[25:16]\nNADV\nNWAIT\n(WAITCFG = 1)\nA/D[15:0]\ninserted wait state\ndata\nNWAIT\n(WAITCFG = 0)\nai15798c\nAddr[15:0]\ndata\ndata\naddr[25:16]\nMemory transaction = burst of 4 half words\nHCLK\nCLK\nA[25:16]\nNEx\nNOE\nNWE\nHigh\nNADV\nNWAIT\n(WAITCFG=\n0)\nA/D[15:0]\n1 clock\ncycle\n1 clock\ncycle\n(DATLAT + 2)\ninserted wait state\nData strobes\nai17723f\nCLK cycles\ndata\ndata\nData strobes\n" }, { "page_number": 1640, "page_indices": { "start_index": 3193442, "end_index": 3194546 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1640 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.5 Synchronous transactions", 1637 ], [ 4, "Wait management", 1638 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1640/1757\nRM0090 Rev 21\nthey are held low.\n \n \nTable 286. FMC_BCRx bit fields\nBit No.\nBit name\nValue to set\n31-21 \nReserved\n0x000\n20\nCCLKEN\nAs needed\n19\nCBURSTRW\nNo effect on synchronous read\n18-16\nCPSIZE\nAs needed (0x1 for CRAM 1.5)\n15\nASYNCWAIT\n0x0\n14 \nEXTMOD\n0x0\n13\nWAITEN\nto be set to 1 if the memory supports this feature, to be kept at 0 \notherwise\n12\nWREN\nno effect on synchronous read\n11\nWAITCFG\nto be set according to memory\n10\nWRAPMOD\n0x0\n9 \nWAITPOL\nto be set according to memory\n8 \nBURSTEN\n0x1\n7 \nReserved\n0x1\n6 \nFACCEN\nSet according to memory support (NOR Flash memory)\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[1:0]\n0x1 or 0x2\n1 \nMUXEN\nAs needed\n0 \nMBKEN\n0x1 \nTable 287. FMC_BTRx bit fields\nBit No.\nBit name\nValue to set\n31:30\nReserved\n0x0\n29:28\nACCMOD\n0x0\n27-24\nDATLAT\nData latency\n27-24\nDATLAT\nData latency\n23-20\nCLKDIV\n0x0 to get CLK = HCLK (Not supported)\n0x1 to get CLK = 2 × HCLK\n..\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK)\n15-8\nDATAST\nDon’t care\n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDon’t care\n" }, { "page_number": 1641, "page_indices": { "start_index": 3194546, "end_index": 3195417 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1641 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.5 Synchronous transactions", 1637 ], [ 4, "Wait management", 1638 ] ], "page_content": "RM0090 Rev 21\n1641/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nFigure 475. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)\n1.\nThe memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed \nto 0.\n2.\nByte Lane (NBL) outputs are not shown, they are held low while NEx is active.\n \nAddr[15:0]\ndata\naddr[25:16]\nMemory transaction = burst of 2 half words\nHCLK\nCLK\nA[25:16]\nNEx\nNOE\nNWE\nHi-Z\nNADV\nNWAIT\n(WAITCFG = 0)\nA/D[15:0]\n1 clock 1 clock\n(DATLAT + 2)\ninserted wait state\nai14731f\n CLK cycles\ndata\nTable 288. FMC_BCRx bit fields\nBit No.\nBit name\nValue to set\n31-20\nReserved\n0x000\n20\nCCLKEN\nAs needed\n19\nCBURSTRW\n0x1\n18-16\nCPSIZE\nAs needed (0x1 for CRAM 1.5)\n15\nASYNCWAIT\n0x0\n14 \nEXTMOD\n0x0\n13\nWAITEN\nto be set to 1 if the memory supports this feature, to be kept at 0 \notherwise.\n12\nWREN\n0x1\n" }, { "page_number": 1642, "page_indices": { "start_index": 3195417, "end_index": 3196165 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1642 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.5 Synchronous transactions", 1637 ], [ 4, "Wait management", 1638 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1642/1757\nRM0090 Rev 21\n \n11\nWAITCFG\n0x0\n10\nWRAPMOD\n0x0\n9 \nWAITPOL\nto be set according to memory\n8 \nBURSTEN\nno effect on synchronous write\n7 \nReserved\n0x1\n6 \nFACCEN\nSet according to memory support\n5-4 \nMWID \nAs needed\n3-2 \nMTYP[1:0]\n0x1\n1 \nMUXEN\nAs needed\n0 \nMBKEN\n0x1 \nTable 289. FMC_BTRx bit fields\nBit No.\nBit name\nValue to set\n31-30\nReserved\n0x0\n29:28\nACCMOD\n0x0\n27-24\nDATLAT\nData latency\n23-20\nCLKDIV\n0x0 to get CLK = HCLK (not supported)\n0x1 to get CLK = 2 × HCLK\n19-16\nBUSTURN\nTime between NEx high to NEx low (BUSTURN HCLK)\n15-8\nDATAST\nDon’t care\n7-4\nADDHLD\nDon’t care\n3-0\nADDSET[3:0]\nDon’t care\nTable 288. FMC_BCRx bit fields (continued)\nBit No.\nBit name\nValue to set\n" }, { "page_number": 1643, "page_indices": { "start_index": 3196165, "end_index": 3198825 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1643 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.6 NOR/PSRAM controller registers", 1643 ], [ 4, "SRAM/NOR-Flash chip-select control registers 1..4 (FMC_BCR1..4)", 1643 ] ], "page_content": "RM0090 Rev 21\n1643/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n37.5.6 \nNOR/PSRAM controller registers\nSRAM/NOR-Flash chip-select control registers 1..4 (FMC_BCR1..4)\nAddress offset: 8 * (x – 1), x = 1...4\nReset value: 0x0000 30DB for Bank1 and 0x0000 30D2 for Bank 2 to 4\nThis register contains the control information of each memory bank, used for SRAMs, \nPSRAM and NOR Flash memories.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nCCLKEN\nCBURSTRW\nCPSIZE[2:0]\nASCYCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[1:0]\nMUXEN\nMBKEN\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31: 21 Reserved, must be kept at reset value\nBit 20 CCLKEN: Continuous Clock Enable.\nThis bit enables the FMC_CLK clock output to external memory devices.\n0: The FMC_CLK is only generated during the synchronous memory access (read/write \ntransaction). The FMC_CLK clock ratio is specified by the programmed CLKDIV value in the \nFMC_BCRx register (default after reset) .\n1: The FMC_CLK is generated continuously during asynchronous and synchronous access. The \nFMC_CLK clock is activated when the CCLKEN is set.\nNote: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the \nFMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the \nFMC_CLK continuous clock.\nNote: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the \nFMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care.\nNote: If the synchronous mode is used and CCLKEN bit is set, the synchronous memories \nconnected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in \nthe FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)\nBit 19 CBURSTRW: Write burst enable.\nFor PSRAM (CRAM) operating in burst mode, the bit enables synchronous accesses during write \noperations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx \nregister.\n0: Write operations are always performed in asynchronous mode\n1: Write operations are performed in synchronous mode.\nBits 18:16 CPSIZE[2:0]: CRAM page size.\nThese are used for Cellular RAM 1.5 which does not allow burst access to cross the address \nboundaries between pages. When these bits are configured, the FMC controller splits automatically \nthe burst access when the memory page size is reached (refer to memory datasheet for page size).\n000: No burst split when crossing page boundary (default after reset)\n001: 128 bytes\n010: 256 bytes\n011: 512 bytes\n100: 1024 bytes\nOthers: reserved\n" }, { "page_number": 1644, "page_indices": { "start_index": 3198825, "end_index": 3202066 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1644 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.6 NOR/PSRAM controller registers", 1643 ], [ 4, "SRAM/NOR-Flash chip-select control registers 1..4 (FMC_BCR1..4)", 1643 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1644/1757\nRM0090 Rev 21\nBit 15 ASYNCWAIT: Wait signal during asynchronous transfers\nThis bit enables/disables the FMC to use the wait signal even during an asynchronous protocol.\n0: NWAIT signal is not taken in to account when running an asynchronous protocol (default after \nreset)\n1: NWAIT signal is taken in to account when running an asynchronous protocol\nBit 14 EXTMOD: Extended mode enable.\nThis bit enables the FMC to program the write timings for non-multiplexed asynchronous accesses \ninside the FMC_BWTR register, thus resulting in different timings for read and write operations.\n0: values inside FMC_BWTR register are not taken into account (default after reset)\n1: values inside FMC_BWTR register are taken into account\nNote: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows:\n–\nMode 1 is the default mode when the SRAM/PSRAM memory type is selected \n(MTYP[1:0] =0x0 or 0x01)\n–\nMode 2 is the default mode when the NOR memory type is selected (MTYP[1:0] = 0x10).\nBit 13 WAITEN: Wait enable bit.\nThis bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in \nsynchronous mode.\n0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the \nprogrammed Flash latency period)\n1: NWAIT signal is enabled (its level is taken into account after the programmed latency period to \ninsert wait states if asserted) (default after reset)\nBit 12 WREN: Write enable bit.\nThis bit indicates whether write operations are enabled/disabled in the bank by the FMC:\n0: Write operations are disabled in the bank by the FMC, an AHB error is reported,\n1: Write operations are enabled for the bank by the FMC (default after reset).\nBit 11 WAITCFG: Wait timing configuration.\nThe NWAIT signal indicates whether the data from the memory are valid or if a wait state must be \ninserted when accessing the memory in synchronous mode. This configuration bit determines if \nNWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:\n0: NWAIT signal is active one data cycle before wait state (default after reset),\n1: NWAIT signal is active during wait state (not used for PSRAM).\nBit 10 WRAPMOD: Wrapped burst mode support.\nDefines whether the controller splits or not an AHB burst wrap access into two linear accesses. Valid \nonly when accessing memories in burst mode\n0: Direct wrapped burst is not enabled (default after reset),\n1: Direct wrapped burst is enabled.\nNote: This bit has no effect as the CPU and DMA cannot generate wrapping burst transfers.\nBit 9 WAITPOL: Wait signal polarity bit.\nDefines the polarity of the wait signal from memory used for either in synchronous or asynchronous \nmode:\n0: NWAIT active low (default after reset),\n1: NWAIT active high.\nBit 8 BURSTEN: Burst enable bit.\nThis bit enables/disables synchronous accesses during read operations. It is valid only for \nsynchronous memories operating in burst mode:\n0: Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode. \n1: Burst mode enable. Read accesses are performed in synchronous mode. \nBit 7 Reserved, must be kept at reset value\n" }, { "page_number": 1645, "page_indices": { "start_index": 3202066, "end_index": 3204169 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1645 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.6 NOR/PSRAM controller registers", 1643 ], [ 4, "SRAM/NOR-Flash chip-select timing registers 1..4 (FMC_BTR1..4)", 1645 ] ], "page_content": "RM0090 Rev 21\n1645/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nSRAM/NOR-Flash chip-select timing registers 1..4 (FMC_BTR1..4)\nAddress offset: 0x04 + 8 * (x – 1), x = 1..4\nReset value: 0x0FFF FFFF\nReset value: 0x0FFF FFFF\nFMC_BTRx bits are written by software to add a delay at the end of a read /write \ntransaction. This delay allows matching the minimum time between consecutive \ntransactions (tEHEL from NEx high to FMC_NEx low) and the maximum time required by the \nmemory to free the data bus after a read access (tEHQZ).\nThis register contains the control information of each memory bank, used for SRAMs, \nPSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then \nthis register is partitioned for write and read access, that is, 2 registers are available: one to \nconfigure read accesses (this register) and one to configure write accesses (FMC_BWTRx \nregisters).\nBit 6 FACCEN: Flash access enable\nEnables NOR Flash memory access operations.\n0: Corresponding NOR Flash memory access is disabled\n1: Corresponding NOR Flash memory access is enabled (default after reset)\nBits 5:4 MWID[1:0]: Memory data bus width.\nDefines the external memory device width, valid for all type of memories.\n00: 8 bits,\n01: 16 bits (default after reset),\n10: 32 bits,\n11: reserved, do not use.\nBits 3:2 MTYP[1:0]: Memory type.\nDefines the type of external memory attached to the corresponding memory bank:\n00: SRAM (default after reset for Bank 2...4)\n01: PSRAM (CRAM)\n10: NOR Flash/OneNAND Flash (default after reset for Bank 1)\n11: reserved\nBit 1 MUXEN: Address/data multiplexing enable bit.\nWhen this bit is set, the address and data values are multiplexed on the data bus, valid only with \nNOR and PSRAM memories:\n0: Address/Data nonmultiplexed\n1: Address/Data multiplexed on databus (default after reset)\nBit 0 MBKEN: Memory bank enable bit.\nEnables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a \ndisabled bank causes an ERROR on AHB bus.\n0: Corresponding memory bank is disabled\n1: Corresponding memory bank is enabled\n" }, { "page_number": 1646, "page_indices": { "start_index": 3204169, "end_index": 3205962 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1646 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.6 NOR/PSRAM controller registers", 1643 ], [ 4, "SRAM/NOR-Flash chip-select timing registers 1..4 (FMC_BTR1..4)", 1645 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1646/1757\nRM0090 Rev 21\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV3:0]\nBUSTURN3:0]\nDATAST7:0]\nADDHLD3:0]\nADDSET[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value\nBits 29:28 ACCMOD[1:0]: Access mode\nSpecifies the asynchronous access modes as shown in the timing diagrams. These bits are \ntaken into account only when the EXTMOD bit in the FMC_BCRx register is 1.\n00: access mode A\n01: access mode B\n10: access mode C\n11: access mode D\nBits 27:24 DATLAT[3:0]: Data latency for synchronous NOR Flash memory (see note below bit \ndescription table)\nFor synchronous accesses with read/write burst mode enabled (BURSTEN / CBURSTRW bits \nset), this field defines the number of memory clock cycles (+2) to issue to the memory before \nreading/writing the first data. This timing parameter is not expressed in HCLK periods, but in \nFMC_CLK periods. For asynchronous accesses, this value is don't care. \n0000: Data latency of 2 CLK clock cycles for first burst access\n1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)\nBits 23:20 CLKDIV[3:0]: Clock divide ratio (for FMC_CLK signal)\nDefines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles:\n0000: Reserved\n0001: FMC_CLK period = 2 × HCLK periods\n0010: FMC_CLK period = 3 × HCLK periods\n1111: FMC_CLK period = 16 × HCLK periods (default value after reset) \nIn asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care.\nNote: Refer to section 37.5.5: Synchronous transactions for FMC_CLK divider ratio formula)\n" }, { "page_number": 1647, "page_indices": { "start_index": 3205962, "end_index": 3208257 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1647 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.6 NOR/PSRAM controller registers", 1643 ], [ 4, "SRAM/NOR-Flash chip-select timing registers 1..4 (FMC_BTR1..4)", 1645 ] ], "page_content": "RM0090 Rev 21\n1647/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nBits 19:16 BUSTURN[3:0]: Bus turnaround phase duration\nThese bits are written by software to add a delay at the end of a write-to-read (and read-to-\nwrite) transaction. This delay allows to match the minimum time between consecutive \ntransactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory \nto free the data bus after a read access (tEHQZ). The programmed bus turnaround delay is \ninserted between an asynchronous read (muxed or mode D) or write transaction and any \nother asynchronous /synchronous read or write to or from a static bank. The bank can be the \nsame or different in case of read, in case of write the bank can be different except for muxed \nor mode D.\nIn some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is \nfixed as follows:\n• The bus turnaround delay is not inserted between two consecutive asynchronous write \ntransfers to the same static memory bank except for modes muxed and D.\n• There is a bus turnaround delay of 1 FMC clock cycle between:\n–Two consecutive asynchronous read transfers to the same static memory bank except for \nmodes muxed and D. \n–An asynchronous read to an asynchronous or synchronous write to any static bank or \ndynamic bank except for modes muxed and D.\n–An asynchronous (modes 1, 2, A, B or C) read and a read from another static bank.\n• There is a bus turnaround delay of 2 FMC clock cycle between:\n–Two consecutive synchronous writes (burst or single) to the same bank.\n–A synchronous write (burst or single) access and an asynchronous write or read transfer to \nor from static memory bank (the bank can be the same or different for the case of read.\n–Two consecutive synchronous reads (burst or single) followed by any \nsynchronous/asynchronous read or write from/to another static memory bank.\n• There is a bus turnaround delay of 3 FMC clock cycle between:\n–Two consecutive synchronous writes (burst or single) to different static bank.\n–A synchronous write (burst or single) access and a synchronous read from the same or a \ndifferent bank.\n0000: BUSTURN phase duration = 0 HCLK clock cycle added\n... \n1111: BUSTURN phase duration = 15 x HCLK clock cycles added (default value after reset) \n" }, { "page_number": 1648, "page_indices": { "start_index": 3208257, "end_index": 3210896 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1648 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.6 NOR/PSRAM controller registers", 1643 ], [ 4, "SRAM/NOR-Flash chip-select timing registers 1..4 (FMC_BTR1..4)", 1645 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1648/1757\nRM0090 Rev 21\nNote:\nPSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these \nmemories issue the NWAIT signal during the whole latency phase to prolong the latency as \nneeded.\nWith PSRAMs (CRAMs) the filled DATLAT must be set to 0, so that the FMC exits its latency \nphase soon and starts sampling NWAIT from memory, then starts to read or write when the \nmemory is ready.\nThis method can be used also with the latest generation of synchronous Flash memories \nthat issue the NWAIT signal, unlike older Flash memories (check the datasheet of the \nspecific Flash memory being used).\nBits 15:8 DATAST[7:0]: Data-phase duration\nThese bits are written by software to define the duration of the data phase (refer to Figure 458 \nto Figure 470), used in asynchronous accesses:\n0000 0000: Reserved\n0000 0001: DATAST phase duration = 1 × HCLK clock cycles\n0000 0010: DATAST phase duration = 2 × HCLK clock cycles\n...\n1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)\nFor each memory type and access mode data-phase duration, please refer to the respective \nfigure (Figure 458 to Figure 470).\nExample: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock \ncycles.\nNote: In synchronous accesses, this value is don’t care.\nBits 7:4 ADDHLD[3:0]: Address-hold phase duration\nThese bits are written by software to define the duration of the address hold phase (refer to \nFigure 467 to Figure 470), used in mode D or multiplexed accesses:\n0000: Reserved\n0001: ADDHLD phase duration =1 × HCLK clock cycle\n0010: ADDHLD phase duration = 2 × HCLK clock cycle\n...\n1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)\nFor each access mode address-hold phase duration, please refer to the respective figure \n(Figure 467 to Figure 470).\nNote: In synchronous accesses, this value is not used, the address hold phase is always 1 \nmemory clock period duration.\nBits 3:0 ADDSET[3:0]: Address setup phase duration\nThese bits are written by software to define the duration of the address setup phase (refer to \nFigure 458 to Figure 470), used in SRAMs, ROMs and asynchronous NOR Flash and PSRAM \naccesses:\n0000: ADDSET phase duration = 0 × HCLK clock cycle\n...\n1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)\nFor each access mode address setup phase duration, please refer to the respective figure \n(refer to Figure 458 to Figure 470).\nNote: In synchronous accesses, this value is don’t care.\nIn Muxed mode or Mode D, the minimum value for ADDSET is 1.\n" }, { "page_number": 1649, "page_indices": { "start_index": 3210896, "end_index": 3213243 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1649 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.5 NOR Flash/PSRAM controller", 1615 ], [ 3, "37.5.6 NOR/PSRAM controller registers", 1643 ], [ 4, "SRAM/NOR-Flash write timing registers 1..4 (FMC_BWTR1..4)", 1649 ] ], "page_content": "RM0090 Rev 21\n1649/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nSRAM/NOR-Flash write timing registers 1..4 (FMC_BWTR1..4)\nAddress offset: 0x104 + 8 * (x – 1), x = 1...4\nReset value: 0x0FFF FFFF\nThis register contains the control information of each memory bank. It is used for SRAMs, \nPSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx \nregister, then this register is active for write access.\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nACCMOD[1:0]\nReserved\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0]\nADDSET[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value\nBits 29:28 ACCMOD[1:0]: Access mode.\nSpecifies the asynchronous access modes as shown in the next timing diagrams.These bits are \ntaken into account only when the EXTMOD bit in the FMC_BCRx register is 1.\n00: access mode A\n01: access mode B\n10: access mode C\n11: access mode D\nBits 27:20 Reserved, must be kept at reset value\nBits 19:16 BUSTURN[3:0]: Bus turnaround phase duration\nThe programmed bus turnaround delay is inserted between an asynchronous write transfer and \nany other asynchronous /synchronous read or write transfer to or from a static bank. The bank can \nbe the same or different in case of read, in case of write the bank can be different expect for muxed \nor mode D.\nIn some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as\nfollows:\n• The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to \nthe same static memory bank except for modes muxed and D.\n• There is a bus turnaround delay of 2 FMC clock cycle between:\n–Two consecutive synchronous writes (burst or single) to the same bank.\n–A synchronous write (burst or single) transfer and an asynchronous write or read transfer to or \nfrom static memory bank.\n• There is a bus turnaround delay of 3 FMC clock cycle between:\n–Two consecutive synchronous writes (burst or single) to different static bank.\n–A synchronous write (burst or single) transfer and a synchronous read from the same or a \ndifferent bank.\n0000: BUSTURN phase duration = 0 HCLK clock cycle added\n... \n1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)\n" }, { "page_number": 1650, "page_indices": { "start_index": 3213243, "end_index": 3215406 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1650 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.6 NAND Flash/PC Card controller", 1650 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1650/1757\nRM0090 Rev 21\n37.6 \nNAND Flash/PC Card controller\nThe FMC generates the appropriate signal timings to drive the following types of device:\n•\n8- and 16-bit NAND Flash memories\n•\n16-bit PC Card compatible devices\nThe NAND Flash/PC Card controller can control three external banks, Bank 2, 3 and 4:\n•\nBank 2 and Bank 3 support NAND Flash devices\n•\nBank 4 supports PC Card devices.\nEach bank is configured through dedicated registers (Section 37.6.8). The programmable \nmemory parameters include access timings (shown in Table 290) and ECC configuration.\nBits 15:8 DATAST[3:0]: Data-phase duration.\nThese bits are written by software to define the duration of the data phase (refer toFigure 458 to \nFigure 470), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:\n0000 0000: Reserved\n0000 0001: DATAST phase duration = 1 × HCLK clock cycles\n0000 0010: DATAST phase duration = 2 × HCLK clock cycles\n...\n1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)\nBits 7:4 ADDHLD[3:0]: Address-hold phase duration.\nThese bits are written by software to define the duration of the address hold phase (refer to \nFigure 467 to Figure 470), used in asynchronous multiplexed accesses:\n0000: Reserved\n0001: ADDHLD phase duration = 1 × HCLK clock cycle\n0010: ADDHLD phase duration = 2 × HCLK clock cycle\n...\n1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)\nNote: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always \n1 Flash clock period duration.\nBits 3:0 ADDSET[3:0]: Address setup phase duration.\nThese bits are written by software to define the duration of the address setup phase in HCLK cycles \n(refer to Figure 467 to Figure 470), used in asynchronous accesses:\n0000: ADDSET phase duration = 0 × HCLK clock cycle\n...\n1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)\nNote: In synchronous NOR Flash and PSRAM accesses, this value is not used, the address setup \nphase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value \nis 1.\n" }, { "page_number": 1651, "page_indices": { "start_index": 3215406, "end_index": 3217062 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1651 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.6 NAND Flash/PC Card controller", 1650 ], [ 3, "37.6.1 External memory interface signals", 1651 ], [ 4, "8-bit NAND Flash memory", 1651 ] ], "page_content": "RM0090 Rev 21\n1651/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n \n37.6.1 \nExternal memory interface signals\nThe following tables list the signals that are typically used to interface NAND Flash memory \nand PC Card.\nNote:\nThe prefix “N” identifies the signals which are active low.\n8-bit NAND Flash memory\n t\nTheoretically, there is no capacity limitation as the FMC can manage as many address \ncycles as needed.\nTable 290. Programmable NAND Flash/PC Card access parameters\nParameter\nFunction\nAccess mode\nUnit\nMin. Max. \nMemory setup \ntime\nNumber of clock cycles (HCLK) \nrequired to set up the address \nbefore the command assertion\nRead/Write \nAHB clock cycle \n(HCLK) \n1 \n256 \nMemory wait\nMinimum duration (in HCLK clock \ncycles) of the command assertion \nRead/Write \nAHB clock cycle \n(HCLK) \n2\n255 \nMemory hold \nNumber of clock cycles (HCLK) \nduring which the address must be \nheld (as well as the data if a write \naccess is performed) after the \ncommand de-assertion \nRead/Write \nAHB clock cycle \n(HCLK) \n1 \n254\nMemory \ndatabus high-Z \nNumber of clock cycles (HCLK) \nduring which the data bus is kept \nin high-Z state after a write \naccess has started\nWrite \nAHB clock cycle \n(HCLK) \n1 \n255 \nTable 291. 8-bit NAND Flash\nFMC signal name\nI/O \nFunction\nA[17] \nO \nNAND Flash address latch enable (ALE) signal \nA[16] \nO \nNAND Flash command latch enable (CLE) signal \nD[7:0] \nI/O \n8-bit multiplexed, bidirectional address/data bus \nNCE[x]\nO\nChip Select, x = 2, 3\nNOE(= NRE)\nO \nOutput enable (memory signal name: read enable, NRE) \nNWE\nO \nWrite enable \nNWAIT/INT[3:2]\nI \nNAND Flash ready/busy input signal to the FMC \n" }, { "page_number": 1652, "page_indices": { "start_index": 3217062, "end_index": 3218507 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1652 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.6 NAND Flash/PC Card controller", 1650 ], [ 3, "37.6.1 External memory interface signals", 1651 ], [ 4, "16-bit NAND Flash memory", 1652 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1652/1757\nRM0090 Rev 21\n16-bit NAND Flash memory\n \nTheoretically, there is no capacity limitation as the FMC can manage as many address \ncycles as needed.\n \nTable 292. 16-bit NAND Flash\nFMC signal name \nI/O \nFunction \nA[17]\nO \nNAND Flash address latch enable (ALE) signal \nA[16] \nO \nNAND Flash command latch enable (CLE) signal \nD[15:0] \nI/O \n16-bit multiplexed, bidirectional address/data bus \nNCE[x]\nO\nChip Select, x = 2, 3\nNOE(= NRE)\nO \nOutput enable (memory signal name: read enable, NRE) \nNWE\nO \nWrite enable \nNWAIT/INT[3:2]\nI \nNAND Flash ready/busy input signal to the FMC \nTable 293. 16-bit PC Card\nFMC signal name\nI/O\nFunction\nA[10:0]\nO\nAddress bus\nNIORD\nO\nOutput enable for I/O space\nNIOWR\nO\nWrite enable for I/O space\nNREG\nO\nRegister signal indicating if access is in Common or Attribute space\nD[15:0]\nI/O\nBidirectional databus\nNCE4_1\nO\nChip Select 1\nNCE4_2\nO\nChip Select 2 (indicates if access is 16-bit or 8-bit)\nNOE\nO\nOutput enable in Common and in Attribute space\nNWE\nO\nWrite enable in Common and in Attribute space\nNWAIT\nI\nPC Card wait input signal to the FMC (memory signal name IORDY)\nINTR\nI\nPC Card interrupt to the FMC (only for PC Cards that can generate \nan interrupt)\nCD\nI\nPC Card presence detection. Active high. If an access is performed \nto the PC Card banks while CD is low, an AHB error is generated. \nRefer to Section 37.3: AHB interface\n" }, { "page_number": 1653, "page_indices": { "start_index": 3218507, "end_index": 3220337 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1653 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.6 NAND Flash/PC Card controller", 1650 ], [ 3, "37.6.2 NAND Flash / PC Card supported memories and transactions", 1653 ], [ 3, "37.6.3 Timing diagrams for NAND Flash memory and PC Card", 1653 ] ], "page_content": "RM0090 Rev 21\n1653/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n37.6.2 \nNAND Flash / PC Card supported memories and transactions\nTable 294 shows the supported devices, access modes and transactions. Transactions not \nallowed (or not supported) by the NAND Flash / PC Card controller are shown in gray.\n \n37.6.3 \nTiming diagrams for NAND Flash memory and PC Card\nEach PC Card/CompactFlash and NAND Flash memory bank is managed through a set of \nregisters:\n•\nControl register: FMC_PCRx\n•\nInterrupt status register: FMC_SRx\n•\nECC register: FMC_ECCRx\n•\nTiming register for Common memory space: FMC_PMEMx\n•\nTiming register for Attribute memory space: FMC_PATTx\n•\nTiming register for I/O space: FMC_PIOx\nEach timing configuration register contains three parameters used to define number of \nHCLK cycles for the three phases of any PC Card/CompactFlash or NAND Flash access, \nplus one parameter that defines the timing for starting driving the data bus when a write \naccess is performed. Figure 476 shows the timing parameter definitions for common \nmemory accesses, knowing that Attribute and I/O (only for PC Card) memory space access \ntimings are similar.\nTable 294. Supported memories and transactions\nDevice\nMode \nR/W \nAHB \ndata size\nMemory \ndata size\nAllowed/\nnot allowed\nComments \nNAND 8-bit \nAsynchronous R \n8 \n8 \nY \n-\nAsynchronous W \n8 \n8 \nY \n-\nAsynchronous R \n16 \n8 \nY \nSplit into 2 FMC accesses \nAsynchronous W \n16 \n8 \nY \nSplit into 2 FMC accesses \nAsynchronous R \n32 \n8 \nY \nSplit into 4 FMC accesses \nAsynchronous W \n32 \n8 \nY \nSplit into 4 FMC accesses \nNAND 16-bit \nAsynchronous R \n8 \n16 \nY \n-\nAsynchronous W \n8 \n16 \nN \n-\nAsynchronous R \n16 \n16 \nY \n-\nAsynchronous W \n16 \n16 \nY \n-\nAsynchronous R \n32 \n16 \nY \nSplit into 2 FMC accesses \nAsynchronous W \n32 \n16 \nY \nSplit into 2 FMC accesses \n" }, { "page_number": 1654, "page_indices": { "start_index": 3220337, "end_index": 3222785 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1654 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.6 NAND Flash/PC Card controller", 1650 ], [ 3, "37.6.4 NAND Flash operations", 1654 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1654/1757\nRM0090 Rev 21\nFigure 476. NAND Flash/PC Card controller waveforms for common memory access\n1.\nNOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses.\n2.\nFor write accesses, the hold phase delay is (MEMHOLD) x HCLK cycles, while it is (MEMHOLD + 2) x \nHCLK cycles for read accesses.\n37.6.4 \nNAND Flash operations\nThe command latch enable (CLE) and address latch enable (ALE) signals of the NAND \nFlash memory device are driven by address signals from the FMC controller. This means \nthat to send a command or an address to the NAND Flash memory, the CPU has to perform \na write to a specific address in its memory space.\nA typical page read operation from the NAND Flash device requires the following steps:\n3. \nProgram and enable the corresponding memory bank by configuring the FMC_PCRx \nand FMC_PMEMx (and for some devices, FMC_PATTx, see Section 37.6.5: NAND \nFlash prewait functionality) registers according to the characteristics of the NAND \nFlash memory (PWID bits for the data bus width of the NAND Flash, PTYP = 1, \nPWAITEN = 0 or 1 as needed, see section Section 37.4.2: NAND Flash memory/PC \nCard address mapping for timing configuration).\n4. \nThe CPU performs a byte write to the common memory space, with data byte equal to \none Flash command byte (for example 0x00 for Samsung NAND Flash devices). The \nLE input of the NAND Flash memory is active during the write strobe (low pulse on \nNWE), thus the written byte is interpreted as a command by the NAND Flash memory. \nOnce the command is latched by the memory device, it does not need to be written \nagain for the following page read operations.\n5. \nThe CPU can send the start address (STARTAD) for a read operation by writing four \nbyte (or three for smaller capacity devices), STARTAD[7:0], STARTAD[16:9], \nSTARTAD[24:17] and finally STARTAD[25] (for 64 Mb x 8 bit NAND Flash memories) in \nthe common memory or attribute space. The ALE input of the NAND Flash device is \nactive during the write strobe (low pulse on NWE), thus the written byte are interpreted \nas the start address for read operations. Using the attribute memory space makes it \npossible to use a different timing configuration of the FMC, which can be used to \nMS33733V2\nHCLK\nA[25:0]\nNCEx\nNREG,\nNIOW,\nNIOR\nNWE,\nNOE\n(1)\nwrite_data\nread_data\nHigh\nValid\nMEMxSET\n + 1\nMEMxWAIT + 1\nMEMxHOLD \nMEMxHIZ\n" }, { "page_number": 1655, "page_indices": { "start_index": 3222785, "end_index": 3224490 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1655 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.6 NAND Flash/PC Card controller", 1650 ], [ 3, "37.6.5 NAND Flash prewait functionality", 1655 ] ], "page_content": "RM0090 Rev 21\n1655/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nimplement the prewait functionality needed by some NAND Flash memories (see \ndetails in Section 37.6.5: NAND Flash prewait functionality).\n6. \nThe controller waits for the NAND Flash memory to be ready (R/NB signal high), before \nstarting a new access to the same or another memory bank. While waiting, the \ncontroller holds the NCE signal active (low).\n7. \nThe CPU can then perform byte read operations from the common memory space to \nread the NAND Flash page (data field + Spare field) byte by byte.\n8. \nThe next NAND Flash page can be read without any CPU command or address write \noperation. This can be done in three different ways:\n–\nby simply performing the operation described in step 5\n–\na new random address can be accessed by restarting the operation at step 3\n–\na new command can be sent to the NAND Flash device by restarting at step 2\n37.6.5 \nNAND Flash prewait functionality\nSome NAND Flash devices require that, after writing the last part of the address, the \ncontroller waits for the R/NB signal to go low. (see Figure 457).\nFigure 477. Access to non ‘CE don’t care’ NAND-Flash\n1.\nCPU wrote byte 0x00 at address 0x7001 0000.\n2.\nCPU wrote byte A7~A0 at address 0x7002 0000.\n3.\nCPU wrote byte A16~A9 at address 0x7002 0000.\n4.\nCPU wrote byte A24~A17 at address 0x7002 0000.\n5.\nCPU wrote byte A25 at address 0x7802 0000: FMC performs a write access using FMC_PATT2 timing \ndefinition, where ATTHOLD ≥ 7 (providing that (7+1) × HCLK = 112 ns > tWB max). This guarantees that \nNCE remains low until R/NB goes low and high again (only requested for NAND Flash memories where \nNCE is not don’t care).\n" }, { "page_number": 1656, "page_indices": { "start_index": 3224490, "end_index": 3226912 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1656 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.6 NAND Flash/PC Card controller", 1650 ], [ 3, "37.6.6 Computation of the error correction code (ECC) in NAND Flash memory", 1656 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1656/1757\nRM0090 Rev 21\nWhen this functionality is required, it can be ensured by programming the MEMHOLD value \nto meet the tWB timing. However CPU read accesses to the NAND Flash memory has a hold \ndelay of (MEMHOLD + 2) x HCLK cycles, while CPU write accesses have a hold delay of \n(MEMHOLD) x HCLK cycles. \nTo cope with this timing constraint, the attribute memory space can be used by \nprogramming its timing register with an ATTHOLD value that meets the tWB timing, and by \nkeeping the MEMHOLD value at its minimum value. The CPU must then use the common \nmemory space for all NAND Flash read and write accesses, except when writing the last \naddress byte to the NAND Flash device, where the CPU must write to the attribute memory \nspace.\n37.6.6 \nComputation of the error correction code (ECC) \nin NAND Flash memory\nThe FMC PC Card controller includes two error correction code computation hardware \nblocks, one per memory bank. They reduce the host CPU workload when processing the \nECC by software.\nThese two ECC blocks are identical and associated with Bank 2 and Bank 3. As a \nconsequence, no hardware ECC computation is available for memories connected to Bank \n4.\nThe ECC algorithm implemented in the FMC can perform 1-bit error correction and 2-bit \nerror detection per 256, 512, 1 024, 2 048, 4 096 or 8 192 byte read or written from/to the \nNAND Flash memory. It is based on the Hamming coding algorithm and consists in \ncalculating the row and column parity.\nThe ECC modules monitor the NAND Flash data bus and read/write signals (NCE and \nNWE) each time the NAND Flash memory bank is active.\nThe ECC operates as follows:\n•\nWhen accessing NAND Flash memory bank 2 or bank 3, the data present on the \nD[15:0] bus is latched and used for ECC computation. \n•\nWhen accessing any other address in NAND Flash memory, the ECC logic is idle, and \ndoes not perform any operation. As a result, write operations to define commands or \naddresses to the NAND Flash memory are not taken into account for ECC \ncomputation.\nOnce the desired number of byte has been read/written from/to the NAND Flash memory by \nthe host CPU, the FMC_ECCR2/3 registers must be read to retrieve the computed value. \nOnce read, they should be cleared by resetting the ECCEN bit to ‘0’. To compute a new data \nblock, the ECCEN bit must be set to one in the FMC_PCR2/3 registers.\n" }, { "page_number": 1657, "page_indices": { "start_index": 3226912, "end_index": 3229832 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1657 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.6 NAND Flash/PC Card controller", 1650 ], [ 3, "37.6.7 PC Card/CompactFlash operations", 1657 ], [ 4, "Address spaces and memory accesses", 1657 ] ], "page_content": "RM0090 Rev 21\n1657/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nTo perform an ECC computation:\n1.\nEnable the ECCEN bit in the FMC_PCR2/3 register.\n2. \nWrite data to the NAND Flash memory page. While the NAND page is written, the ECC \nblock computes the ECC value. \n3. \nRead the ECC value available in the FMC_ECCR2/3 register and store it in a variable.\n4. \nClear the ECCEN bit and then enable it in the FMC_PCR2/3 register before reading \nback the written data from the NAND page. While the NAND page is read, the ECC \nblock computes the ECC value. \n5. \nRead the new ECC value available in the FMC_ECCR2/3 register.\n6. \nIf the two ECC values are the same, no correction is required, otherwise there is an \nECC error and the software correction routine returns information on whether the error \ncan be corrected or not. \n37.6.7 \nPC Card/CompactFlash operations\nAddress spaces and memory accesses \nThe FMC supports CompactFlash devices and PC Cards in Memory mode and I/O mode \n(True IDE mode is not supported).\nThe CompactFlash and PC Cards are made of 3 memory spaces:\n•\nCommon Memory space\n•\nAttribute space\n•\nI/O Memory space\nThe nCE2 and nCE1 pins (FMC_NCE4_2 and FMC_NCE4_1 respectively) select the card \nand indicate whether a byte or a word operation is being performed: nCE2 accesses the odd \nbyte on D15-8 and nCE1 accesses the even byte on D7-0 if A0=0 or the odd byte on D7-0 if \nA0=1. The full word is accessed on D15-0 if both nCE2 and nCE1 are low.\nThe memory space is selected by asserting low nOE for read accesses or nWE for write \naccesses, combined with the low assertion of nCE2/nCE1 and nREG.\n•\nIf pin nREG=1 during the memory access, the common memory space is selected\n•\nIf pin nREG=0 during the memory access, the attribute memory space is selected\nThe I/O space is selected by asserting nIORD space for read accesses or nIOWR for write \naccesses [instead of nOE/nWE for memory space], combined with nCE2/nCE1. Note that \nnREG must also be asserted low when accessing I/O space.\nThree type of accesses are allowed for a 16-bit PC Card:\n•\nAccesses to Common Memory space for data storage can be either 8-bit accesses at \neven addresses or 16-bit AHB accesses. \nNote that 8-bit accesses at odd addresses are not supported and nCE2 is not driven \nlow. A 32-bit AHB request is translated into two 16-bit memory accesses.\n•\nAccesses to Attribute Memory space where the PC Card stores configuration \ninformation are limited to 8-bit AHB accesses at even addresses.\nNote that a 16-bit AHB access is converted into a single 8-bit memory transfer: nCE1 is \nasserted low, nCE2 is asserted high and only the even byte on D7-D0 are valid. Instead \na 32-bit AHB access is converted into two 8-bit memory transfers at even addresses: \nnCE1 is asserted low, NCE2 is asserted high and only the even byte are valid.\n•\nAccesses to I/O space can be either 8-bit or 16 bit AHB accesses. \n" }, { "page_number": 1658, "page_indices": { "start_index": 3229832, "end_index": 3231854 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1658 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.6 NAND Flash/PC Card controller", 1650 ], [ 3, "37.6.7 PC Card/CompactFlash operations", 1657 ], [ 4, "Wait feature", 1658 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1658/1757\nRM0090 Rev 21\n \nFMC Bank 4 gives access to those 3 memory spaces as described in Section 37.4.2: NAND \nFlash memory/PC Card address mapping and Table 257: NAND/PC Card memory mapping \nand timing registers.\nWait feature\nThe CompactFlash or PC Card may request the FMC to extend the length of the access \nphase programmed by MEMWAITx/ATTWAITx/IOWAITx bits, asserting the nWAIT signal \nafter nOE/nWE or nIORD/nIOWR activation if the wait feature is enabled through the \nPWAITEN bit in the FMC_PCRx register. To detect correctly the nWAIT assertion, the \nMEMWAITx/ATTWAITx/IOWAITx bits must be programmed as follows:\nwhere max_wait_assertion_time is the maximum time taken by NWAIT to go low once \nnOE/nWE or nIORD/nIOWR is low.\nAfter WAIT de-assertion, the FMC extends the WAIT phase for 4 HCLK clock cycles. \nTable 295. 16-bit PC-Card signals and access type \nnCE2\nnCE1\nnREG\nnOE/nWE\nnIORD \nA10\nA9\nA7-1\nA0 \nSpace \nAccess type\nAllowed/not \nAllowed \n1\n0\n1\n0\n1\nX\nX\nX-X\nX\nCommon \nMemory \nSpace\nRead/Write byte on D7-D0\nYES\n0\n1\n1\n0\n1\nX\nX\nX-X\nX\nRead/Write byte on D15-D8\nNot supported\n0\n0\n1\n0\n1\nX\nX\nX-X\n0\nRead/Write word on D15-D0\nYES\nX\n0\n0\n0\n1\n0\n1\nX-X\n0\nAttribute \nSpace\nRead or Write Configuration \nRegisters\nYES\nX\n0\n0\n0\n1\n0\n0\nX-X\n0\nRead or Write CIS (Card \nInformation Structure)\nYES\n1\n0\n0\n0\n1\nX\nX\nX-X\n1\n Attribute \nSpace\nInvalid Read or Write (odd \naddress)\nYES\n0\n1\n0\n0\n1\nX\nX\nX-X\nx\nInvalid Read or Write (odd \naddress)\nYES\n1\n0\n0\n1\n0\nX\nX\nX-X\n0\nI/O space\nRead Even Byte on D7-0 \nYES\n1\n0\n0\n1\n0\nX\nX\nX-X\n1\nRead Odd Byte on D7-0\nYES\n1\n0\n0\n1\n0\nX\nX\nX-X\n0\nWrite Even Byte on D7-0 \nYES\n1\n0\n0\n1\n0\nX\nX\nX-X\n1\nWrite Odd Byte on D7-0 \nYES\n0\n0\n0\n1\n0\nX\nX\nX-X\n0\nRead Word on D15-0\nYES\n0\n0\n0\n1\n0\nX\nX\nX-X\n0\nWrite word on D15-0 \nYES\n0\n1\n0\n1\n0\nX\nX\nX-X\nX\nRead Odd Byte on D15-8\nNot supported\n0\n1\n0\n1\n0\nX\nX\nX-X\nX\nWrite Odd Byte on D15-8\nNot supported\nxxWAITx\n4\nmax_wait_assertion_time\nHCLK\n-------------------------------------------------------------------\n+\n≥\n" }, { "page_number": 1659, "page_indices": { "start_index": 3231854, "end_index": 3233581 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1659 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.6 NAND Flash/PC Card controller", 1650 ], [ 3, "37.6.8 NAND Flash/PC Card controller registers", 1659 ], [ 4, "PC Card/NAND Flash control registers 2..4 (FMC_PCR2..4)", 1659 ] ], "page_content": "RM0090 Rev 21\n1659/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n37.6.8 \nNAND Flash/PC Card controller registers\nPC Card/NAND Flash control registers 2..4 (FMC_PCR2..4)\nAddress offset: 0x40 + 0x20 * (x – 1), x = 2..4\nReset value: 0x0000 0018\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nECCPS[2:0]\nTAR[3:0]\nTCLR[3:0]\nReserved\nECCEN\nPWID[1:0]\nPTYP\nPBKEN\nPWAITEN\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:20 Reserved, must be kept at reset value\nBits 19:17 ECCPS[2:0]: ECC page size.\nDefines the page size for the extended ECC:\n000: 256 byte\n001: 512 byte\n010: 1024 byte\n011: 2048 byte\n100: 4096 byte\n101: 8192 byte\nBits 16:13 TAR[3:0]: ALE to RE delay.\nSets time from ALE low to RE low in number of AHB clock cycles (HCLK).\nTime is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period\n0000: 1 HCLK cycle (default)\n1111: 16 HCLK cycles\nNote: SET is MEMSET or ATTSET according to the addressed space.\nBits 12:9 TCLR[3:0]: CLE to RE delay.\nSets time from CLE low to RE low in number of AHB clock cycles (HCLK).\nTime is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period\n0000: 1 HCLK cycle (default)\n1111: 16 HCLK cycles\nNote: SET is MEMSET or ATTSET according to the addressed space.\nBits 8:7 Reserved, must be kept at reset value\nBit 6 ECCEN: ECC computation logic enable bit\n0: ECC logic is disabled and reset (default after reset),\n1: ECC logic is enabled.\nBits 5:4 PWID[1:0]: Data bus width.\nDefines the external memory device width.\n00: 8 bits \n01: 16 bits (default after reset). This value is mandatory for PC Cards.\n10: reserved, do not use\n11: reserved, do not use\n" }, { "page_number": 1660, "page_indices": { "start_index": 3233581, "end_index": 3235704 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1660 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.6 NAND Flash/PC Card controller", 1650 ], [ 3, "37.6.8 NAND Flash/PC Card controller registers", 1659 ], [ 4, "FIFO status and interrupt register 2..4 (FMC_SR2..4)", 1660 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1660/1757\nRM0090 Rev 21\nFIFO status and interrupt register 2..4 (FMC_SR2..4)\nAddress offset: 0x44 + 0x20 * (x-1), x = 2..4\nReset value: 0x0000 0040\nThis register contains information about the FIFO status and interrupt. The FMC features a \nFIFO that is used when writing to memories to transfer up to 16 words of data from the AHB.\nThis is used to quickly write to the FIFO and free the AHB for transactions to peripherals \nother than the FMC, while the FMC is draining its FIFO into the memory. One of these \nregister bits indicates the status of the FIFO, for ECC purposes.\nThe ECC is calculated while the data are written to the memory. To read the correct ECC, \nthe software must consequently wait until the FIFO is empty.\n \n \nBit 3 PTYP: Memory type.\nDefines the type of device attached to the corresponding memory bank:\n0: PC Card, CompactFlash, CF+ or PCMCIA\n1: NAND Flash (default after reset)\nBit 2 PBKEN: PC Card/NAND Flash memory bank enable bit.\nEnables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB \nbus\n0: Corresponding memory bank is disabled (default after reset)\n1: Corresponding memory bank is enabled\nBit 1 PWAITEN: Wait feature enable bit.\nEnables the Wait feature for the PC Card/NAND Flash memory bank:\n0: disabled\n1: enabled\nNote: For a PC Card, when the wait feature is enabled, the MEMWAITx/ATTWAITx/IOWAITx \nbits must be programmed to a value as follows:\nxxWAITx ≥ 4 + max_wait_assertion_time/HCLK\nWhere max_wait_assertion_time is the maximum time taken by NWAIT to go low once \nnOE/nWE or nIORD/nIOWR is low.\nBit 0 Reserved.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nFEMPT\nIFEN\nILEN\nIREN\nIFS\nILS\nIRS\nr\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:7 Reserved, must be kept at reset value\nBit 6 FEMPT: FIFO empty.\nRead-only bit that provides the status of the FIFO\n0: FIFO not empty\n1: FIFO empty\nBit 5 IFEN: Interrupt falling edge detection enable bit\n0: Interrupt falling edge detection request disabled\n1: Interrupt falling edge detection request enabled\n" }, { "page_number": 1661, "page_indices": { "start_index": 3235704, "end_index": 3237751 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1661 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.6 NAND Flash/PC Card controller", 1650 ], [ 3, "37.6.8 NAND Flash/PC Card controller registers", 1659 ], [ 4, "Common memory space timing register 2..4 (FMC_PMEM2..4)", 1661 ] ], "page_content": "RM0090 Rev 21\n1661/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nCommon memory space timing register 2..4 (FMC_PMEM2..4)\nAddress offset: Address: 0x48 + 0x20 * (x – 1), x = 2..4\nReset value: 0xFCFC FCFC\nEach FMC_PMEMx (x = 2..4) read/write register contains the timing information for PC Card \nor NAND Flash memory bank x. This information is used to access either the common \nmemory space of the 16-bit PC Card/CompactFlash, or the NAND Flash for command, \naddress write access and data read/write access.\n \n \nBit 4 ILEN: Interrupt high-level detection enable bit\n0: Interrupt high-level detection request disabled\n1: Interrupt high-level detection request enabled\nBit 3 IREN: Interrupt rising edge detection enable bit\n0: Interrupt rising edge detection request disabled\n1: Interrupt rising edge detection request enabled\nBit 2 IFS: Interrupt falling edge status\nThe flag is set by hardware and reset by software.\n0: No interrupt falling edge occurred\n1: Interrupt falling edge occurred\nNote: This bit is set by programming it to 1 by software. \nBit 1 ILS: Interrupt high-level status\nThe flag is set by hardware and reset by software.\n0: No Interrupt high-level occurred\n1: Interrupt high-level occurred\nBit 0 IRS: Interrupt rising edge status\nThe flag is set by hardware and reset by software.\n0: No interrupt rising edge occurred\n1: Interrupt rising edge occurred\nNote: This bit is set by programming it to 1 by software. \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMEMHIZ[7:0]\nMEMHOLD[7:0]\nMEMWAIT[7:0]\nMEMSET[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 MEMHIZ[7:0]: Common memory x data bus Hi-Z time\nDefines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the \nstart of a PC Card/NAND Flash write access to common memory space on socket x. This is \nonly valid for write transactions:\n0000 0000: 1 HCLK cycle\n1111 1110: 255 HCLK cycles\n1111 1111: Reserved.\n" }, { "page_number": 1662, "page_indices": { "start_index": 3237751, "end_index": 3240471 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1662 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.6 NAND Flash/PC Card controller", 1650 ], [ 3, "37.6.8 NAND Flash/PC Card controller registers", 1659 ], [ 4, "Attribute memory space timing registers 2..4 (FMC_PATT2..4)", 1662 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1662/1757\nRM0090 Rev 21\nAttribute memory space timing registers 2..4 (FMC_PATT2..4)\nAddress offset: 0x4C + 0x20 * (x – 1), x = 2..4\nReset value: 0xFCFC FCFC\nEach FMC_PATTx (x = 2..4) read/write register contains the timing information for PC \nCard/CompactFlash or NAND Flash memory bank x. It is used for 8-bit accesses to the \nattribute memory space of the PC Card/CompactFlash or to access the NAND Flash for the \nlast address write access if the timing must differ from that of previous accesses (for \nReady/Busy management, refer to Section 37.6.5: NAND Flash prewait functionality).\n \n \nBits 23:16 MEMHOLD[7:0]: Common memory x hold time\nFor NAND Flash read accesses to the common memory space, these bits define the \nnumber of (HCLK+2) clock cycles during which the address is held after the command is \ndeasserted (NWE, NOE).\nFor NAND Flash write accesses to the common memory space, these bits define the \nnumber of HCLK clock cycles during which the data are held after the command is \ndeasserted (NWE, NOE).\n0000 0000: reserved\n0000 0001: 1 HCLK cycle for write accesses, 3 HCLK cycles for read accesses\n1111 1110: 254 HCLK cycle for write accesses, 256 HCLK cycles for read accesses\n1111 1111: Reserved.\nBits 15:8 MEMWAIT[7:0]: Common memory x wait time\nDefines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, \nNOE), for PC Card/NAND Flash read or write access to common memory space on socket \nx. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) \nat the end of the programmed value of HCLK:\n0000 0000: reserved\n0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)\n1111 1110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)\n1111 1111: Reserved\nBits 7:0 MEMSET[7:0]: Common memory x setup time\nDefines the number of HCLK (+1) clock cycles to set up the address before the command \nassertion (NWE, NOE), for PC Card/NAND Flash read or write access to common memory \nspace on socket x:\n0000 0000: 1 HCLK cycle\n1111 1110: 255 HCLK cycles\n1111 1111: Reserved.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nATTHIZ[7:0]\nATTHOLD[7:0]\nATTWAIT[7:0]\nATTSET[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 ATTHIZ[7:0]: Attribute memory x data bus Hi-Z time\nDefines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the \nstart of a PC CARD/NAND Flash write access to attribute memory space on socket x. Only \nvalid for write transaction:\n0000 0000: 0 HCLK cycle\n1111 1110: 255 HCLK cycles\n1111 1111: Reserved.\n" }, { "page_number": 1663, "page_indices": { "start_index": 3240471, "end_index": 3242575 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1663 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.6 NAND Flash/PC Card controller", 1650 ], [ 3, "37.6.8 NAND Flash/PC Card controller registers", 1659 ], [ 4, "I/O space timing register 4 (FMC_PIO4)", 1663 ] ], "page_content": "RM0090 Rev 21\n1663/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nI/O space timing register 4 (FMC_PIO4)\nAddress offset: 0xB0\nReset value: 0xFCFCFCFC\nThe FMC_PIO4 read/write registers contain the timing information used to access the I/O \nspace of the 16-bit PC Card/CompactFlash.\n \n \nBits 23:16 ATTHOLD[7:0]: Attribute memory x hold time\nFor PC Card/NAND Flash read accesses to attribute memory space on socket x, these bits \ndefine the number of HCLK clock cycles (HCLK +2) clock cycles during which the address is \nheld after the command is deasserted (NWE, NOE).\nFor PC Card/NAND Flash write accesses to attribute memory space on socket x, these bits \ndefine the number of HCLK clock cycles during which the data are held after the command \nis deasserted (NWE, NOE).\n0000 0000: Reserved\n0000 0001: 1 HCLK cycle for write access, 3 HCLK cycles for read accesses\n1111 1110: 254 HCLK cycle for write access, 256 HCLK cycles for read accesses\n1111 1111: Reserved.\nBits 15:8 ATTWAIT[7:0]: Attribute memory x wait time\nDefines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, \nNOE), for PC Card/NAND Flash read or write access to attribute memory space on socket x. \nThe duration for command assertion is extended if the wait signal (NWAIT) is active (low) at \nthe end of the programmed value of HCLK:\n0000 0000: reserved\n0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)\n1111 1110: 255 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)\n1111 1111: Reserved\nBits 7:0 ATTSET[7:0]: Attribute memory x setup time\nDefines the number of HCLK (+1) clock cycles to set up address before the command \nassertion (NWE, NOE), for PC CARD/NAND Flash read or write access to attribute memory \nspace on socket x:\n0000 0000: 1 HCLK cycle\n1111 1110: 255 HCLK cycles\n1111 1111: Reserved\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nIOHIZ[7:0]\nIOHOLD[7:0]\nIOWAIT[7:0]\nIOSET[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n" }, { "page_number": 1664, "page_indices": { "start_index": 3242575, "end_index": 3244047 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1664 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.6 NAND Flash/PC Card controller", 1650 ], [ 3, "37.6.8 NAND Flash/PC Card controller registers", 1659 ], [ 4, "I/O space timing register 4 (FMC_PIO4)", 1663 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1664/1757\nRM0090 Rev 21\nBits 31:24 IOHIZ[7:0]: I/O x data bus Hi-Z time\nDefines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the \nstart of a PC Card write access to I/O space on socket x. Only valid for write transaction:\n0000 0000: 0 HCLK cycle\n1111 1111: 255 HCLK cycles\nBits 23:16 IOHOLD[7:0]: I/O x hold time\nDefines the number of HCLK clock cycles during which the address is held (and data for write \naccess) after the command deassertion (NWE, NOE), for PC Card read or write access to I/O \nspace on socket x:\n0000 0000: reserved\n0000 0001: 1 HCLK cycle\n1111 1111: 255 HCLK cycles \nBits 15:8 IOWAIT[7:0]: I/O x wait time\nDefines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE, \nSMNOE), for PC Card read or write access to I/O space on socket x. The duration for \ncommand assertion is extended if the wait signal (NWAIT) is active (low) at the end of the \nprogrammed value of HCLK:\n0000 0000: reserved, do not use this value\n0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)\n1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) \nBits 7:0 IOSET[7:0]: I/O x setup time\nDefines the number of HCLK (+1) clock cycles to set up the address before the command \nassertion (NWE, NOE), for PC Card read or write access to I/O space on socket x:\n0000 0000: 1 HCLK cycle\n1111 1111: 256 HCLK cycles\n" }, { "page_number": 1665, "page_indices": { "start_index": 3244047, "end_index": 3245674 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1665 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.6 NAND Flash/PC Card controller", 1650 ], [ 3, "37.6.8 NAND Flash/PC Card controller registers", 1659 ], [ 4, "ECC result registers 2/3 (FMC_ECCR2/3)", 1665 ] ], "page_content": "RM0090 Rev 21\n1665/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nECC result registers 2/3 (FMC_ECCR2/3)\nAddress offset: 0x54 + 0x20 * (x – 1), x = 2 or 3\nReset value: 0x0000 0000\nThese registers contain the current error correction code value computed by the ECC \ncomputation modules of the FMC controller (one module per NAND Flash memory bank). \nWhen the CPU reads the data from a NAND Flash memory page at the correct address \n(refer to Section 37.6.6: Computation of the error correction code (ECC) in NAND Flash \nmemory), the data read/written from/to the NAND Flash memory are processed \nautomatically by the ECC computation module. When X byte have been read (according to \nthe ECCPS field in the FMC_PCRx registers), the CPU must read the computed ECC value \nfrom the FMC_ECCx registers. It then verifies if these computed parity data are the same as \nthe parity value recorded in the spare area, to determine whether a page is valid, and, to \ncorrect it otherwise. The FMC_ECCRx registers should be cleared after being read by \nsetting the ECCEN bit to ‘0’. To compute a new data block, the ECCEN bit must be set to ’1’.\n \n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nECC[31:0]\nr\nBits 31:0 ECC[31:0]: ECC result\nThis field contains the value computed by the ECC computation logic. Table 296 describes the \ncontents of these bit fields.\nTable 296. ECC result relevant bits\nECCPS[2:0]\nPage size in byte\nECC bits\n000\n256\nECC[21:0]\n001\n512\nECC[23:0]\n010\n1024\nECC[25:0]\n011\n2048\nECC[27:0]\n100\n4096\nECC[29:0]\n101\n8192\nECC[31:0]\n" }, { "page_number": 1666, "page_indices": { "start_index": 3245674, "end_index": 3247384 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1666 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.1 SDRAM controller main features", 1666 ], [ 3, "37.7.2 SDRAM External memory interface signals", 1666 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1666/1757\nRM0090 Rev 21\n37.7 \nSDRAM controller\n37.7.1 \nSDRAM controller main features\nThe main features of the SDRAM controller are the following:\n•\nTwo SDRAM banks with independent configuration\n•\n8-bit, 16-bit, 32-bit data bus width\n•\n13-bits Address Row, 11-bits Address Column, 4 internal banks: 4x16Mx32bit \n(256 MB), 4x16Mx16bit (128 MB), 4x16Mx8bit (64 MB)\n•\nWord, half-word, byte access\n•\nSDRAM clock can be HCLK/2 or HCLK/3\n•\nAutomatic row and bank boundary management \n•\nMultibank ping-pong access\n•\nProgrammable timing parameters \n•\nAutomatic Refresh operation with programmable Refresh rate\n•\nSelf-refresh mode\n•\nPower-down mode\n•\nSDRAM power-up initialization by software\n•\nCAS latency of 1,2,3 \n•\nCacheable Read FIFO with depth of 6 lines x32-bit (6 x14-bit address tag)\n37.7.2 \nSDRAM External memory interface signals\nAt startup, the SDRAM I/O pins used to interface the FMC SDRAM controller with the \nexternal SDRAM devices must configured by the user application. The SDRAM controller \nI/O pins which are not used by the application, can be used for other purposes.\n \nTable 297. SDRAM signals\nSDRAM signal \nI/O \ntype\nDescription\nAlternate function\nSDCLK\nO\nSDRAM clock\n-\nSDCKE[1:0]\nO\nSDCKE0: SDRAM Bank 1 Clock Enable \nSDCKE1: SDRAM Bank 2 Clock Enable\n-\nSDNE[1:0]\nO\nSDNE0: SDRAM Bank 1 Chip Enable \nSDNE1: SDRAM Bank 2 Chip Enable\n-\nA[12:0]\nO\nAddress\nFMC_A[12:0]\nD[31:0]\nI/O\nBidirectional data bus\nFMC_D[31:0]\nBA[1:0]\nO\nBank Address\nFMC_A[15:14]\nNRAS\nO\nRow Address Strobe\n-\nNCAS\nO\nColumn Address Strobe\n-\nSDNWE\nO\nWrite Enable\n-\nNBL[3:0]\nO\nOutput Byte Mask for write accesses \n(memory signal name: DQM[3:0]) \n FMC_NBL[3:0]\n" }, { "page_number": 1667, "page_indices": { "start_index": 3247384, "end_index": 3250658 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1667 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.3 SDRAM controller functional description", 1667 ], [ 4, "SDRAM initialization", 1667 ] ], "page_content": "RM0090 Rev 21\n1667/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n37.7.3 \nSDRAM controller functional description\nAll SDRAM controller outputs (signals, address and data) change on the falling edge of the \nmemory clock (FMC_SDCLK).\nSDRAM initialization\nThe initialization sequence is managed by software. If the two banks are used, the \ninitialization sequence must be generated simultaneously to Bank 1and Bank 2 by setting \nthe Target Bank bits CTB1 and CTB2 in the FMC_SDCMR register:\n1.\nProgram the memory device features into the FMC_SDCRx register.The SDRAM clock \nfrequency, RBURST and RPIPE must be programmed in the FMC_SDCR1 register.\n2. \nProgram the memory device timing into the FMC_SDTRx register. The TRP and TRC \ntimings must be programmed in the FMC_SDTR1 register.\n3. \nSet MODE bits to ‘001’ and configure the Target Bank bits (CTB1 and/or CTB2) in the \nFMC_SDCMR register to start delivering the clock to the memory (SDCKE is driven \nhigh).\n4. \nWait during the prescribed delay period. Typical delay is around 100 μs (refer to the \nSDRAM datasheet for the required delay after power-up).\n5. \nSet MODE bits to ‘010’ and configure the Target Bank bits (CTB1 and/or CTB2) in the \nFMC_SDCMR register to issue a “Precharge All” command.\n6. \nSet MODE bits to ‘011’, and configure the Target Bank bits (CTB1 and/or CTB2) as well \nas the number of consecutive Auto-refresh commands (NRFS) in the FMC_SDCMR \nregister. Refer to the SDRAM datasheet for the number of Auto-refresh commands that \nshould be issued. Typical number is 8.\n7. \nConfigure the MRD field according to your SDRAM device, set the MODE bits to '100', \nand configure the Target Bank bits (CTB1 and/or CTB2) in the FMC_SDCMR register \nto issue a \"Load Mode Register\" command in order to program the SDRAM. In \nparticular: \na) \nThe CAS latency must be selected following configured value in FMC_SDCR1/2 \nregisters \nb) \nThe Burst Length (BL) of 1 must be selected by configuring the M[2:0] bits to 000 \nin the mode register (refer to the SDRAM datasheet). If the Mode Register is not \nthe same for both SDRAM banks, this step has to be repeated twice, once for \neach bank, and the Target Bank bits set accordingly.\n8. \nProgram the refresh rate in the FMC_SDRTR register\nThe refresh rate corresponds to the delay between refresh cycles. Its value must be \nadapted to SDRAM devices.\n9. \nFor mobile SDRAM devices, to program the extended mode register it should be done \nonce the SDRAM device is initialized: First, a dummy read access should be performed \nwhile BA1=1 and BA=0 (refer to SDRAM address mapping section for BA[1:0] address \nmapping) in order to select the extended mode register instead of Load mode register \nand then program the needed value. \nAt this stage the SDRAM device is ready to accept commands. If a system reset occurs \nduring an ongoing SDRAM access, the data bus might still be driven by the SDRAM device. \nTherefor the SDRAM device must be first reinitialized after reset before issuing any new \naccess by the NOR Flash/PSRAM/SRAM or NAND Flash/PC Card controller. \nNote:\nIf two SDRAM devices are connected to the FMC, all the accesses performed at the same \ntime to both devices by the Command Mode register (Load Mode Register and Self-refresh \n" }, { "page_number": 1668, "page_indices": { "start_index": 3250658, "end_index": 3251883 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1668 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.3 SDRAM controller functional description", 1667 ], [ 4, "SDRAM controller write cycle", 1668 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1668/1757\nRM0090 Rev 21\ncommands) are issued using the timing parameters configured for SDRAM Bank 1 (TMRD, \nTRAS and TXSR timings) in the FMC_SDTR1 register.\nSDRAM controller write cycle\nThe SDRAM controller accepts single and burst write requests and translates them into \nsingle memory accesses. In both cases, the SDRAM controller keeps track of the active row \nfor each bank to be able to perform consecutive write accesses to different banks (Multibank \nping-pong access). \nBefore performing any write access, the SDRAM bank write protection must be disabled by \nclearing the WP bit in the FMC_SDCRx register.\nFigure 478. Burst write SDRAM access waveforms\nThe SDRAM controller always checks the next access. \n•\nIf the next access is in the same row or in another active row, the write operation is \ncarried out, \n•\nif the next access targets another row (not active), the SDRAM controller generates a \nprecharge command, activates the new row and initiates a write command. \nMS30448V3\nNRAS\nA[12:0]\nSDCLK\nRow n \nColc\nSDNE\nTRCD = 3\nSDNWE\nCola\nCold\nColb\nCole Colf\nCog Colh Coli\nColj\nColk Coll\nNCAS\nDATA[31:0]\nDnc\nDne\nDna\nDnf\nDng Dnh Dni\nDnj\nDnk\nDnl\nDnb\nDnd\n" }, { "page_number": 1669, "page_indices": { "start_index": 3251883, "end_index": 3253437 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1669 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.3 SDRAM controller functional description", 1667 ], [ 4, "SDRAM controller read cycle", 1669 ] ], "page_content": "RM0090 Rev 21\n1669/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nSDRAM controller read cycle\nThe SDRAM controller accepts single and burst read requests and translates them into \nsingle memory accesses. In both cases, the SDRAM controller keeps track of the active row \nin each bank to be able to perform consecutive read accesses in different banks (Multibank \nping-pong access). \nFigure 479. Burst read SDRAM access\nThe FMC SDRAM controller features a Cacheable read FIFO (6 lines x 32 bits). It is used to \nstore data read in advance during the CAS latency period and during the RPIPE delay. The \nfollowing the formula is applied:\nThe RBURST bit must be set in the FMC_SDCR1 register to anticipate the next read \naccess.\nExample:\n•\nCAS latency = 3, RPIPE delay = 0: 4 data (not committed) are stored in the FIFO.\n•\nCAS latency = 3, RPIPE delay = 2: 5 data (not committed) are stored in the FIFO. \nThe read FIFO features a 14-bit address tag to each line to identify its content: 11 bits for the \ncolumn address, 2 bits to select the internal bank and the active row, and 1 bit to select the \nSDRAM device\nWhen the end of the row is reached in advance during an AHB burst read, the data read in \nadvance (not committed) are not stored in the read FIFO. For single read access, data are \ncorrectly stored in the FIFO.\nMS30449V3\nNRAS\nA[12:0]\nSDCLK\nRow n \nColc\nSDNE\nTRCD = 3\nNWE\nCola\nCold\nColb\nCole\nColf\nNCAS\nDATA[31:0]\nDnc\nDne\nDna\nDnf\nDnb\nDnd\nCAS latency = 2\nNumber of anticipated data\nCAS latency\n1\nRPIPE delay\n(\n)\n2\n⁄\n+\n+\n=\n" }, { "page_number": 1670, "page_indices": { "start_index": 3253437, "end_index": 3255057 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1670 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.3 SDRAM controller functional description", 1667 ], [ 4, "SDRAM controller read cycle", 1669 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1670/1757\nRM0090 Rev 21\nEach time a read request occurs, the SDRAM controller checks:\n•\nIf the address matches one of the address tags, data are directly read from the FIFO \nand the corresponding address tag/ line content is cleared and the remaining data in \nthe FIFO are compacted to avoid empty lines. \n•\nOtherwise, a new read command is issued to the memory and the FIFO is updated with \nnew data. If the FIFO is full, the older data are lost. \nFigure 480. Logic diagram of Read access with RBURST bit set (CAS=2, RPIPE=0)\nDuring a write access or a Precharge command, the read FIFO is flushed and ready to be \nfilled with new data.\nAfter the first read request, if the current access was not performed to a row boundary, the \nSDRAM controller anticipates the next read access during the CAS latency period and the \nRPIPE delay (if configured). This is done by incrementing the memory address. The \nfollowing condition must be met: \n•\nRBURST control bit should be set to ‘1’ in the FMC_SDCR1 register.\nMS30445V1\nAHB Master\n@0x04\n@0x08\nData 2\nData 3\n...\n...\nSDRAM\nDevice\n(CAS = 2) \nread request@0x00\nData 1\n6 lines FIFO\nAdd. Tag read FIFO\nData stored in FIFO\nin advance during\nthe CAS latency period\nAddress matches with \none of the address tags\nFMC SDRAM Controller\n2nd Read access\n: Requested data was previously stored in the FIFO \n1st Read access: Requested data is not in the FIFO\nAHB Master\n@0x04\n@0x08\nData 2\nData 3\n...\n...\nSDRAM\nDevice\n(CAS = 2) \nread request@0x04\nData 2\n6 lines FIFO\nData read from FIFO\nFMC SDRAM Controller\nAdd. Tag read FIFO\n" }, { "page_number": 1671, "page_indices": { "start_index": 3255057, "end_index": 3256683 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1671 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.3 SDRAM controller functional description", 1667 ], [ 4, "Row and bank boundary management", 1671 ] ], "page_content": "RM0090 Rev 21\n1671/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nThe address management depends on the next AHB request: \n•\nNext AHB request is sequential (AHB Burst)\nIn this case, the SDRAM controller increments the address.\n•\nNext AHB request is not sequential\n–\nIf the new read request targets the same row or another active row, the new \naddress is passed to the memory and the master is stalled for the CAS latency \nperiod, waiting for the new data from memory.\n–\nIf the new read request does not target an active row, the SDRAM controller \ngenerates a Precharge command, activates the new row, and initiates a read \ncommand.\nIf the RURST is reset, the read FIFO is not used.\nRow and bank boundary management \nWhen a read or write access crosses a row boundary, if the next read or write access is \nsequential and the current access was performed to a row boundary, the SDRAM controller \nexecutes the following operations:\n1.\nPrecharge of the active row,\n2. \nActivation of the new row \n3. \nStart of a read/write command. \nAt a row boundary, the automatic activation of the next row is supported for all columns and \ndata bus width configurations.\nIf necessary, the SDRAM controller inserts additional clock cycles between the following \ncommands:\n•\nBetween Precharge and Active commands to match TRP parameter (only if the next \naccess is in a different row in the same bank), \n•\nBetween Active and Read commands to match the TRCD parameter. \nThese parameters are defined into the FMC_SDTRx register.\nRefer to Figure 481 and Figure 482 for read and burst write access crossing a row \nboundary.\n" }, { "page_number": 1672, "page_indices": { "start_index": 3256683, "end_index": 3257187 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1672 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.3 SDRAM controller functional description", 1667 ], [ 4, "Row and bank boundary management", 1671 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1672/1757\nRM0090 Rev 21\nFigure 481. Read access crossing row boundary\nFigure 482. Write access crossing row boundary\nMS30446V2\nData[31:0]\nNCAS\nNRAS\nA[12:0]\nSDCLK\nCol a\nCol a Col b\nRow n +1\nDna\nDn+1 a\nSDNE\nTRP = 3\nCAS latency = 2\nNWE\nPrecharge\nActivate Row\nRead Command\nRow n\nTRCD = 3\nMS30447V2\nData[31:0]\nNCAS\nNRAS\nA[12:0]\nSDCLK\nCna\nCola\nRow n+1\nDna\nDn+1a\nSDNE\nTRP = 3\nNWE\nPrecharge\nActivate Row\nWrite command\nColb\nColb\nDnb\nDn+1b\nTRCD = 3\n" }, { "page_number": 1673, "page_indices": { "start_index": 3257187, "end_index": 3259863 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1673 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.3 SDRAM controller functional description", 1667 ], [ 4, "SDRAM controller refresh cycle", 1673 ] ], "page_content": "RM0090 Rev 21\n1673/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nIf the next access is sequential and the current access crosses a bank boundary, the \nSDRAM controller activates the first row in the next bank and initiates a new read/write \ncommand. Two cases are possible:\n•\nIf the current bank is not the last one, the active row in the new bank must be \nprecharged. At a bank boundary, the automatic activation of the next row is supported \nfor all rows/columns and data bus width configuration.\n•\nFor 13-bit row address, 11-bit column address, 4 internal banks and bus width 32-bit \nSDRAM memories, if the current bank is the last one and the selected SDRAM device \nis connected to Bank 1, the SDRAM controller continues to read/write from the second \nSDRAM device (assuming it has been initialized):\na) \nThe SDRAM controller activates the first row (after precharging the active row, if \nthere is already an active row in the first internal bank, and initiates a new \nread/write command.\nb) \nIf the first row is already activated, the SDRAM controller just initiates a read/write \ncommand.\nNote:\nAt bank boundary, if the current bank is the last one, the automatic activation of the next row \nis supported only when addressing 13-bit rows, 11-bit columns, 4 internal banks and 32-bit \ndata bus SDRAM devices. Otherwise, the SDRAM address range is violated and an AHB \nerror is generated.\nSDRAM controller refresh cycle\nThe Auto-refresh command is used to refresh the SDRAM device content. The SDRAM \ncontroller periodically issues auto-refresh commands. An internal counter is loaded with the \nCOUNT value in the register FMC_SDRTR. This value defines the number of memory clock \ncycles between the refresh cycles (refresh rate). When this counter reaches zero, an \ninternal pulse is generated.\nIf a memory access is ongoing, the auto-refresh request is delayed. However, if the memory \naccess and the auto-refresh requests are generated simultaneously, the auto-refresh \nrequest takes precedence. \nIf the memory access occurs during an auto-refresh operation, the request is buffered and \nprocessed when the auto-refresh is complete.\nIf a new auto-refresh request occurs while the previous one was not served, the RE \n(Refresh Error) bit is set in the Status register. An Interrupt is generated if it has been \nenabled (REIE = ‘1’).\nIf SDRAM lines are not in idle state (not all row are closed), the SDRAM controller generates \na PALL (Precharge ALL) command before the auto-refresh.\nIf the Auto-refresh command is generated by the FMC_SDCMR Command Mode register \n(Mode bits = ‘011’), a PALL command (Mode bits =’ 010’) must be issued first.\n" }, { "page_number": 1674, "page_indices": { "start_index": 3259863, "end_index": 3261642 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1674 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.4 Low power modes", 1674 ], [ 4, "Self-refresh mode", 1674 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1674/1757\nRM0090 Rev 21\n37.7.4 \nLow power modes\nTwo low power modes are available:\n•\nSelf-refresh mode\nThe auto-refresh cycles are performed by the SDRAM device itself to retain data \nwithout external clocking.\n•\nPower-down mode\nThe auto-refresh cycles are performed by the SDRAM controller.\nSelf-refresh mode\nThis mode is selected by setting the MODE bits to ‘101’ and by configuring the Target Bank \nbits (CTB1 and/or CTB2) in the FMC_SDCMR register.\nThe SDRAM clock stops running after a TRAS delay and the internal refresh timer stops \ncounting only if one of the following conditions is met:\n•\nA Self-refresh command is issued to both devices \n•\nOne of the devices is not activated (SDRAM bank is not initialized).\nBefore entering Self-Refresh mode, the SDRAM controller automatically issues a PALL \ncommand.\nIf the Write data FIFO is not empty, all data are sent to the memory before activating the \nSelf-refresh mode and the BUSY status flag remains set.\nIn Self-refresh mode, all SDRAM device inputs become don’t care except for SDCKE which \nremains low. \nThe SDRAM device must remain in Self-refresh mode for a minimum period of time of \nTRAS and can remain in Self-refresh mode for an indefinite period beyond that. To \nguarantee this minimum period, the BUSY status flag remains high after the Self-refresh \nactivation during a TRAS delay. \nAs soon as an SDRAM device is selected, the SDRAM controller generates a sequence of \ncommands to exit from Self-refresh mode. After the memory access, the selected device \nremains in Normal mode.\nTo exit from Self-refresh, the MODE bits must be set to ‘000’ (Normal mode) and the Target \nBank bits (CTB1 and/or CTB2) must be configured in the FMC_SDCMR register.\n" }, { "page_number": 1675, "page_indices": { "start_index": 3261642, "end_index": 3262279 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1675 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.4 Low power modes", 1674 ], [ 4, "Power-down mode", 1675 ] ], "page_content": "RM0090 Rev 21\n1675/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nFigure 483. Self-refresh mode\nPower-down mode\nThis mode is selected by setting the MODE bits to ‘110’ and by configuring the Target Bank \nbits (CTB1 and/or CTB2) in the FMC_SDCMR register. \nPRECHARGE\nSDCLK\nSDCKE\nT0\nT1\nT2\nTn+1\nT0+1\nT0+2\ntRAS(min)\nCOMMAND\nNOP\nAUTO\nREFRESH\nNOP or COMMAND \nINHERIT\nAUTO\nREFRESH\nDOM/\nDOML/DOMU\nA0- A9\nA11, A12\nA10\nALL \nBANKS\nData[31:0] Hi-Z\ntRP\nPrecharge all\nactive banks\nEnter Self-refresh mode\nCLK stable prior to existing\nSelf-refresh mode\nExit Self-refresh mode\n(restart refresh timebase)\ntXSR\nMS30450V1\n" }, { "page_number": 1676, "page_indices": { "start_index": 3262279, "end_index": 3263571 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1676 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.4 Low power modes", 1674 ], [ 4, "Power-down mode", 1675 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1676/1757\nRM0090 Rev 21\nFigure 484. Power-down mode\nIf the Write data FIFO is not empty, all data are sent to the memory before activating the \nPower-down mode.\nAs soon as an SDRAM device is selected, the SDRAM controller exits from the Power-down \nmode. After the memory access, the selected SDRAM device remains in Normal mode.\nDuring Power-down mode, all SDRAM device input and output buffers are deactivated \nexcept for the SDCKE which remains low. \nThe SDRAM device cannot remain in Power-down mode longer than the refresh period and \ncannot perform the Auto-refresh cycles by itself. Therefore, the SDRAM controller carries \nout the refresh operation by executing the operations below:\n1.\nExit from Power-down mode and drive the SDCKE high\n2. \nGenerate the PALL command only if a row was active during Power-down mode\n3. \nGenerate the auto-refresh command \n4. \nDrive SDCKE low again to return to Power-down mode.\nTo exit from Power-down mode, the MODE bits must be set to ‘000’ (Normal mode) and the \nTarget Bank bits (CTB1 and/or CTB2) must be configured in the FMC_SDCMR register.\nSDCLK\nSDCKE\nCOMMAND\nNOP\nNOP \nACTIVE\nInput buffers gated off\nAll banks idle\nEnter Power-down\nExit Power-down\ntRCD\ntRAS\ntRC\nMS30451V1\n" }, { "page_number": 1677, "page_indices": { "start_index": 3263571, "end_index": 3265502 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1677 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.5 SDRAM controller registers", 1677 ], [ 4, "SDRAM Control registers 1,2 (FMC_SDCR1,2)", 1677 ] ], "page_content": "RM0090 Rev 21\n1677/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n37.7.5 \nSDRAM controller registers\nSDRAM Control registers 1,2 (FMC_SDCR1,2)\nAddress offset: 0x140+ 4* (x – 1), x = 1,2\nReset value: 0x0000 02D0\nThis register contains the control parameters for each SDRAM memory bank\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nRPIPE[1:0]\nRBURST.\nSDCLK[1:0]\nWP\nCAS[1:0]\nNB\nMWID[1:0]\nNR[1:0]\nNC[1:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:15 Reserved, must be kept at reset value\nBits 14:13 RPIPE[1:0]: Read pipe\nThese bits define the delay, in HCLK clock cycles, for reading data after CAS latency.\n00: No HCLK clock cycle delay \n01: One HCLK clock cycle delay\n10: Two HCLK clock cycle delay\n11: reserved, do not use\nNote: The corresponding bits in the FMC_SDCR2 register are read only.\nBit 12 RBURST: Burst read\nThis bit enables burst read mode. The SDRAM controller anticipates the next read commands\nduring the CAS latency and stores data in the Read FIFO.\n0: single read requests are not managed as bursts\n1: single read requests are always managed as bursts\nNote: The corresponding bit in the FMC_SDCR2 register is don’t care.\nBits 11:10 SDCLK[1:0]: SDRAM clock configuration\nThese bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock \nbefore changing the frequency. In this case the SDRAM must be re-initialized.\n00: SDCLK clock disabled\n01: Reserved\n10: SDCLK period = 2 x HCLK periods\n11: SDCLK period = 3 x HCLK periods\nNote: The corresponding bits in the FMC_SDCR2 register are read only.\nBit 9 WP: Write protection\nThis bit enables write mode access to the SDRAM bank.\n0: Write accesses allowed\n1: Write accesses ignored\nBits 8:7 CAS[1:0]: CAS Latency\nThis bits sets the SDRAM CAS latency in number of memory clock cycles\n00: reserved, do not use.\n01: 1 cycle\n10: 2 cycles\n11: 3 cycles\n" }, { "page_number": 1678, "page_indices": { "start_index": 3265502, "end_index": 3267039 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1678 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.5 SDRAM controller registers", 1677 ], [ 4, "SDRAM Timing registers 1,2 (FMC_SDTR1,2)", 1678 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1678/1757\nRM0090 Rev 21\nNote:\nBefore modifying the RBURST or RPIPE settings or disabling the SDCLK clock, the user \nmust first send a PALL command to make sure ongoing operations are complete.\nSDRAM Timing registers 1,2 (FMC_SDTR1,2)\nAddress offset: 0x148 + 4 * (x – 1), x = 1,2\nReset value: 0x0FFF FFFF\nThis register contains the timing parameters of each SDRAM bank\n \nBit 6 NB: Number of internal banks\nThis bit sets the number of internal banks.\n0: Two internal Banks\n1: Four internal Banks\nBits 5:4 MWID[1:0]: Memory data bus width.\nThese bits define the memory device width.\n00: 8 bits\n01: 16 bits\n10: 32 bits\n11: reserved, do not use.\nBits 3:2 NR[1:0]: Number of row address bits\nThese bits define the number of bits of a row address.\n00: 11 bit\n01: 12 bits\n10: 13 bits\n11: reserved, do not use.\nBits 1:0 NC[1:0]: Number of column address bits\nThese bits define the number of bits of a column address.\n00: 8 bits\n01: 9 bits\n10: 10 bits\n11: 11 bits.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTRCD[3:0]\nTRP[3:0\nTWR[3:0\nTRC[3:0\nTRAS[3:0\nTXSR[3:0\nTMRD[3:0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved, must be kept at reset value\nBits 27:24 TRCD[3:0]: Row to column delay\nThese bits define the delay between the Activate command and a Read/Write command in number of \nmemory clock cycles.\n0000: 1 cycle.\n0001: 2 cycles\n....\n1111: 16 cycles\n" }, { "page_number": 1679, "page_indices": { "start_index": 3267039, "end_index": 3269188 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1679 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.5 SDRAM controller registers", 1677 ], [ 4, "SDRAM Timing registers 1,2 (FMC_SDTR1,2)", 1678 ] ], "page_content": "RM0090 Rev 21\n1679/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nBits 23:20 TRP[3:0]: Row precharge delay\nThese bits define the delay between a Precharge command and another command in number of \nmemory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM \ndevices are used, the TRP must be programmed with the timing of the slowest device.\n0000: 1 cycle\n0001: 2 cycles\n....\n1111: 16 cycles\nNote: The corresponding bits in the FMC_SDTR2 register are don’t care.\nBits 19:16 TWR[3:0]: Recovery delay\nThese bits define the delay between a Write and a Precharge command in number of memory clock \ncycles.\n0000: 1 cycle\n0001: 2 cycles\n....\n1111: 16 cycles\nNote: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM \ndatasheet, and to guarantee that:\nTWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP\nExample: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be \nprogrammed to 0x1.\nIf two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed \nwith the same TWR timing corresponding to the slowest SDRAM device.\nBits 15:12 TRC[3:0]: Row cycle delay\nThese bits define the delay between the Refresh command and the Activate command, as well as d \nthe delay between two consecutive Refresh commands. It is expressed in number of memory clock \ncycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are \nused, the TRC must be programmed with the timings of the slowest device.\n0000: 1 cycle\n0001: 2 cycles\n....\n1111: 16 cycles\nNote: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM \ndevice datasheet.\nNote: The corresponding bits in the FMC_SDTR2 register are don’t care.\nBits 11:8 TRAS[3:0]: Self refresh time\nThese bits define the minimum Self-refresh period in number of memory clock cycles.\n0000: 1 cycle\n0001: 2 cycles\n....\n1111: 16 cycles\nBits 7:4 TXSR[3:0]: Exit Self-refresh delay\nThese bits define the delay from releasing the Self-refresh command to issuing the Activate \ncommand in number of memory clock cycles.\n0000: 1 cycle\n0001: 2 cycles\n....\n1111: 16 cycles\n" }, { "page_number": 1680, "page_indices": { "start_index": 3269188, "end_index": 3271308 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1680 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.5 SDRAM controller registers", 1677 ], [ 4, "SDRAM Command Mode register (FMC_SDCMR)", 1680 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1680/1757\nRM0090 Rev 21\nNote:\nIf two SDRAM devices are connected, all the accesses performed simultaneously to both \ndevices by the Command Mode register (Load Mode Register and Self-refresh commands) \nare issued using the timing parameters configured for Bank 1 (TMRD, TRAS and TXSR \ntimings) in the FMC_SDTR1 register.\nThe TRP and TRC timings are only configured in the FMC_SDTR1 register. If two SDRAM \ndevices are used, the TRP and TRC timings must be programmed with the timings of the \nslowest device. \nSDRAM Command Mode register (FMC_SDCMR)\nAddress offset: 0x150 \nReset value: 0x0000 0000\nThis register contains the command issued when the SDRAM device is accessed. This \nregister is used to initialize the SDRAM device, and to activate the Self-refresh and the \nPower-down modes. As soon as the MODE field is written, the command is issued only to \none or to both SDRAM banks according to CTB1 and CTB2 command bits. This register is \nthe same for both SDRAM banks.\n \nBits 3:0 TMRD[3:0]: Load Mode Register to Active \nThese bits define the delay between a Load Mode Register command and an Active or Refresh \ncommand in number of memory clock cycles.\n0000: 1 cycle\n0001: 2 cycles\n....\n1111: 16 cycles\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nMRD[11:0]\nNRFS[3:0]\nCTB1\nCTB2\nMODE[2:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nw\nw\nw\nw\nw\nBits 31:22 Reserved, must be kept at reset value\nBits 21:9 MRD[11:0]: Mode Register definition\nThis 13-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using \nthe Load Mode Register command.\nBits 8:5 NRFS[3:0]: Number of Auto-refresh\nThese bits define the number of consecutive Auto-refresh commands issued when MODE = ‘011’.\n0000: 1 Auto-refresh cycle\n0001: 2 Auto-refresh cycles\n....\n1110: 15 Auto-refresh cycles\n1111: Reserved\nBit 4 CTB1: Command Target Bank 1\nThis bit indicates whether the command is issued to SDRAM Bank 1 or not.\n0: Command not issued to SDRAM Bank 1\n1: Command issued to SDRAM Bank 1\n" }, { "page_number": 1681, "page_indices": { "start_index": 3271308, "end_index": 3273409 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1681 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.5 SDRAM controller registers", 1677 ], [ 4, "SDRAM Refresh Timer register (FMC_SDRTR)", 1681 ], [ 4, "Example", 1681 ] ], "page_content": "RM0090 Rev 21\n1681/1757\nRM0090\nFlexible memory controller (FMC)\n1685\nSDRAM Refresh Timer register (FMC_SDRTR)\nAddress offset:0x154\nReset value: 0x0000 0000\nThis register sets the refresh rate in number of SDCLK clock cycles between the refresh \ncycles by configuring the Refresh Timer Count value.\nExample\n \nwhere 64 ms is the SDRAM refresh period.\n \nThe refresh rate must be increased by 20 SDRAM clock cycles (as in the above example) to \nobtain a safe margin if an internal refresh request occurs when a read request has been \naccepted. It corresponds to a COUNT value of ‘0000111000000’ (448). \nThis 13-bit field is loaded into a timer which is decremented using the SDRAM clock. This \ntimer generates a refresh pulse when zero is reached. The COUNT value must be set at \nleast to 41 SDRAM clock cycles.\nAs soon as the FMC_SDRTR register is programmed, the timer starts counting. If the value \nprogrammed in the register is ’0’, no refresh is carried out. This register must not be \nreprogrammed after the initialization procedure to avoid modifying the refresh rate.\nEach time a refresh pulse is generated, this 13-bit COUNT field is reloaded into the counter.\nBit 3 CTB2: Command Target Bank 2\nThis bit indicates whether the command is issued to SDRAM Bank 2 or not.\n0: Command not issued to SDRAM Bank 2\n1: Command issued to SDRAM Bank 2\nBits 2:0 MODE[2:0]: Command mode\nThese bits define the command issued to the SDRAM device.\n000: Normal Mode\n001: Clock Configuration Enable\n010: PALL (“All Bank Precharge”) command\n011: Auto-refresh command\n100: Load Mode Register\n101: Self-refresh command\n110: Power-down command\n111: Reserved\nNote: When a command is issued, at least one Command Target Bank bit ( CBT1 or CBT2) must be \nset. If both banks are used, the commands must be issued to the two banks at the same time \nby setting the CBT1 and CBT2 bits.\nRefresh rate\nSDRAM refresh rate\nSDRAM clock frequency\n×\n(\n)\n20\n–\n=\nSDRAM refresh rate\nSDRAM refresh period\nNumber of rows\n⁄\n=\nSDRAM refresh rate\n64 ms\n8196rows\n(\n)\n⁄\n7.81μs\n=\n=\n7.81μs\n60MHz\n×\n468.6\n=\n" }, { "page_number": 1682, "page_indices": { "start_index": 3273409, "end_index": 3275466 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1682 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.7 SDRAM controller", 1666 ], [ 3, "37.7.5 SDRAM controller registers", 1677 ], [ 4, "Example", 1681 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1682/1757\nRM0090 Rev 21\nIf a memory access is in progress, the Auto-refresh request is delayed. However, if the \nmemory access and Auto-refresh requests are generated simultaneously, the Auto-refresh \ntakes precedence. If the memory access occurs during a refresh operation, the request is \nbuffered to be processed when the refresh is complete.\nThis register common to SDRAM bank 1 and bank 2.\n .\n \nNote:\nThe programmed COUNT value must not be equal to the sum of the following timings: \nTWR+TRP+TRC+TRCD+4 memory clock cycles . \nSDRAM Status register (FMC_SDSR)\nAddress offset: 0x158\nReset value: 0x0000 0000\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nREIE\nCOUNT[12:0]\nCRE\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nw\nBits 31: 15 Reserved, must be kept at reset value\nBit 14 REIE: RES Interrupt Enable\n0: Interrupt is disabled\n1: An Interrupt is generated if RE = 1\nBits 13:1 COUNT[12:0]: Refresh Timer Count\nThis 13-bit field defines the refresh rate of the SDRAM device. It is expressed in number of memory \nclock cycles. It must be set at least to 41 SDRAM clock cycles (0x29).\nCOUNT = (SDRAM refresh rate x SDRAM clock frequency) - 20\nSDRAM refresh rate = SDRAM refresh period / Number of rows\nBit 0 CRE: Clear Refresh error flag\nThis bit is used to clear the Refresh Error Flag (RE) in the Status Register.\n0: no effect\n1: Refresh Error flag is cleared\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nBUSY\nMODES2[1:0]\nMODES1[1:0]\nRE\nr\nr\nr\nr\nr\nr\nBits 31:5 Reserved, must be kept at reset value\nBit 5 BUSY: Busy status \nThis bit defines the status of the SDRAM controller after a Command Mode request\n0: SDRAM Controller is ready to accept a new request\n1; SDRAM Controller is not ready to accept a new request\nBits 4:3 MODES2[1:0]: Status Mode for Bank 2\nThis bit defines the Status Mode of SDRAM Bank 2.\n00: Normal Mode \n01: Self-refresh mode\n10: Power-down mode\n" }, { "page_number": 1683, "page_indices": { "start_index": 3275466, "end_index": 3277202 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1683 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.8 FMC register map", 1683 ] ], "page_content": "RM0090 Rev 21\n1683/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n37.8 \nFMC register map \nThe following table summarizes the FMC registers. \n \nBits 2:1 MODES1[1:0]: Status Mode for Bank 1\nThis bit defines the Status Mode of SDRAM Bank 1.\n00: Normal Mode \n01: Self-refresh mode\n10: Power-down mode\nBit 0 RE: Refresh error flag\n0: No refresh error has been detected\n1: A refresh error has been detected\nAn interrupt is generated if REIE = 1 and RE = 1\nTable 298. FMC register map\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0x00\nFMC_BCR1\nReserved\nCCLKEN\nCBURSTRW\nCPSIZE[2:0]\nASYNCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[1:0]\nMUXEN\nMBKEN\n0x08\nFMC_BCR2\nReserved\nCBURSTRW\nCPSIZE[2:0]\nASYNCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[1:0]\nMUXEN\nMBKEN\n0x10\nFMC_BCR3\nReserved\nCBURSTRW\nCPSIZE[2:0]\nASYNCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[1:0]\nMUXEN\nMBKEN\n0x18\nFMC_BCR4\nReserved\nCBURSTRW\nCPSIZE[2:0]\nASYNCWAIT\nEXTMOD\nWAITEN\nWREN\nWAITCFG\nWRAPMOD\nWAITPOL\nBURSTEN\nReserved\nFACCEN\nMWID[1:0]\nMTYP[1:0]\nMUXEN\nMBKEN\n0x04\nFMC_BTR1\nRes.\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0] BUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0] ADDSET[3:0]\n0x0C\nFMC_BTR2\nRes.\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0] BUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0] ADDSET[3:0]\n0x14\nFMC_BTR3\nRes.\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0] BUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0] ADDSET[3:0]\n0x1C\nFMC_BTR4\nRes.\nACCMOD[1:0]\nDATLAT[3:0]\nCLKDIV[3:0] BUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0] ADDSET[3:0]\n0x104\nFMC_BWTR1\nRes.\nACCMOD[1:0]\nRes.\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0] ADDSET[3:0]\n" }, { "page_number": 1684, "page_indices": { "start_index": 3277202, "end_index": 3279082 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1684 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.8 FMC register map", 1683 ] ], "page_content": "Flexible memory controller (FMC)\nRM0090\n1684/1757\nRM0090 Rev 21\n0x10C\nFMC_BWTR2\nRes.\nACCMOD[1:0]\nRes.\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0] ADDSET[3:0]\n0x104\nFMC_BWTR3\nRes.\nACCMOD[1:0]\nRes.\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0] ADDSET[3:0]\n0x10C\nFMC_BWTR4\nRes.\nACCMOD[1:0]\nRes.\nBUSTURN[3:0]\nDATAST[7:0]\nADDHLD[3:0] ADDSET[3:0]\n0x60\nFMC_PCR2\nReserved\nECCPS[2:0]\nTAR[3:0]\nTCLR[3:0]\nRes.\nECCEN\nPWID[1:0]\nPTYP\nPBKEN\nPWAITEN\nReserved\n0x80\nFMC_PCR3\nReserved\nECCPS[2:0]\nTAR[3:0]\nTCLR[3:0]\nRes.\nECCEN\nPWID[1:0]\nPTYP\nPBKEN\nPWAITEN\nReserved\n0xA0\nFMC_PCR4\nReserved\nECCPS[2:0]\nTAR[3:0]\nTCLR[3:0]\nRes.\nECCEN\nPWID[1:0]\nPTYP\nPBKEN\nPWAITEN\nReserved\n0x64\nFMC_SR2\nReserved\nFEMPT\nIFEN\nILEN\nIREN\nIFS\nILS\nIRS\n0x84\nFMC_SR3\nReserved\nFEMPT\nIFEN\nILEN\nIREN\nIFS\nILS\nIRS\n0xA4\nFMC_SR4\nReserved\nFEMPT\nIFEN\nILEN\nIREN\nIFS\nILS\nIRS\n0x68\nFMC_PMEM2\nMEMHIZ[7:0]\nMEMHOLD[7:0]\nMEMWAIT[7:0]\nMEMSET[7:0]\n0x88\nFMC_PMEM3\nMEMHIZ[7:0]\nMEMHOLD[7:0]\nMEMWAIT[7:0]\nMEMSET[7:0]\n0xA8\nFMC_PMEM4\nMEMHIZ[7:0]\nMEMHOLD[7:0]\nMEMWAIT[7:0]\nMEMSET[7:0]\n0x6C\nFMC_PATT2\nATTHIZ[7:0]\nATTHOLD[7:0]\nATTWAIT[7:0]\nATTSET[7:0]\n0x8C\nFMC_PATT3\nATTHIZ[7:0]\nATTHOLD[7:0]\nATTWAIT[7:0]\nATTSET[7:0]\n0xAC\nFMC_PATT4\nATTHIZ[7:0]\nATTHOLD[7:0]\nATTWAIT[7:0]\nATTSET[7:0]\n0xB0\nFMC_PIO4\nIOHIZ[7:0]\nIOHOLD[7:0]\nIOWAIT[7:0]\nIOSET[7:0]\n0x74\nFMC_ECCR2\nECC[31:0]\n0x94\nFMC_ECCR3\nECC[31:0]\n0x140\nFMC_SDCR_1\nReserved\nRPIPE[1:0]\nRBURST\nCLK[1:0]\nWP\nCAS[1:0]\nNB\nMWID[1:0]\nNR[1:0]\nNC[1:0]\n0x144\nFMC_SDCR_2\nReserved\nCLK[1:0]\nWP\nCAS[1:0]\nNB\nMWID[1:0]\nNR[1:0]\nNC[1:0]\n0x148\nFMC_SDTR1\nReserved\nTRCD[3:0]\nTRP[3:0]\nTWR[3:0]\nTRC[3:0]\nTRAS[3:0]\nTXSR[3:0]\nTMRD[3:0]\n0x14C\nFMC_SDTR2\nReserved\nTRCD[3:0]\nTRP[3:0]\nTWR[3:0]\nTRC[3:0]\nTRAS[3:0]\nTXSR[3:0]\nTMRD[3:0]\n0x150\nFMC_SDCMR\nReserved\nMRD[12:0]\nNRFS[3:0]\nCTB1\nCTB2\nMODE[2:0]\nTable 298. FMC register map (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1685, "page_indices": { "start_index": 3279082, "end_index": 3279418 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1685 }, "toc_details": [ [ 1, "37 Flexible memory controller (FMC)", 1605 ], [ 2, "37.8 FMC register map", 1683 ] ], "page_content": "RM0090 Rev 21\n1685/1757\nRM0090\nFlexible memory controller (FMC)\n1685\n0x154\nFMC_SDRTR\nReserved\nREIE\nCOUNT[12:0]\nCRE\n0x158\nFMC_SDSR\nReserved\nBUSY\nMODES2[1:0]\nMODES1[1:0]\nRE\nTable 298. FMC register map (continued)\nOffset\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n" }, { "page_number": 1686, "page_indices": { "start_index": 3279418, "end_index": 3280794 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1686 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.1 Overview", 1686 ] ], "page_content": "Debug support (DBG)\nRM0090\n1686/1757\nRM0090 Rev 21\n38 \nDebug support (DBG)\nThis section applies to the whole STM32F4xx family, unless otherwise specified.\n38.1 \nOverview\nThe STM32F4xx are built around a Cortex®-M4 with FPU core, which contains hardware \nextensions for advanced debugging features. The debug extensions allow the core to be \nstopped either on a given instruction fetch (breakpoint), or on data access (watchpoint). \nWhen stopped, the core’s internal state and the system’s external state may be examined. \nOnce examination is complete, the core and the system may be restored and program \nexecution resumed.\nThe debug features are used by the debugger host when connecting to and debugging the \nSTM32F4xx MCUs.\nTwo interfaces for debug are available:\n•\nSerial wire\n•\nJTAG debug port\nFigure 485. Block diagram of STM32 MCU and Cortex®-M4 with FPU-level debug \nsupport\nNote:\nThe debug features embedded in the Cortex®-M4 with FPU core are a subset of the Arm® \nCoreSight Design Kit.\nestricted Di\nCortex-M4\ncore\nSWJ-DP\nAHB-AP\nBridge\nNVIC\nDWT\nFPB\nITM\nTPIU\nDCode\ninterface\nSystem\ninterface\nInternal private\nperipheral bus (PPB)\nExternal private\nperipheral bus (PPB)\nBus matrix\nData\nTrace port\nDBGMCU\nSTM32F4xx debug support \n \nCortex-M4 debug suppo rt\nJTMS/\nJTDI\nJTDO/\nNJTRST\nJTCK/\nSWDIO\nSWCLK\nTRACESWO\nTRACESWO\nTRACECK\nTRACED[3:0]\nMS19908V3\n" }, { "page_number": 1687, "page_indices": { "start_index": 3280794, "end_index": 3282531 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1687 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.2 Reference Arm® documentation", 1687 ], [ 2, "38.3 SWJ debug port (serial wire and JTAG)", 1687 ] ], "page_content": "RM0090 Rev 21\n1687/1757\nRM0090\nDebug support (DBG)\n1716\nThe Arm® Cortex®-M4 with FPU core provides integrated on-chip debug support. It is \ncomprised of:\n•\nSWJ-DP: Serial wire / JTAG debug port\n•\nAHP-AP: AHB access port\n•\nITM: Instrumentation trace macrocell\n•\nFPB: Flash patch breakpoint\n•\nDWT: Data watchpoint trigger\n•\nTPUI: Trace port unit interface (available on larger packages, where the corresponding \npins are mapped)\n•\nETM: Embedded Trace Macrocell (available on larger packages, where the \ncorresponding pins are mapped)\nIt also includes debug features dedicated to the STM32F4xx:\n•\nFlexible debug pinout assignment\n•\nMCU debug box (support for low-power modes, control over peripheral clocks, etc.)\nNote:\nFor further information on debug functionality supported by the Arm® Cortex®-M4 with FPU \ncore, refer to the Cortex®-M4 with FPU -r0p1 Technical Reference Manual and to the \nCoreSight Design Kit-r0p1 TRM (see Section 38.2).\n38.2 \nReference Arm® documentation\n•\nCortex®-M4 with FPU r0p1 Technical Reference Manual (TRM)\n(see Related documents on page 1)\n•\nArm® Debug Interface V5\n•\nArm® CoreSight Design Kit revision r0p1 Technical Reference Manual\n38.3 \nSWJ debug port (serial wire and JTAG)\nThe core of the STM32F4xx integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an \nArm® standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW-\nDP (2-pin) interface.\n•\nThe JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the \nAHP-AP port.\n•\nThe Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the \nAHP-AP port.\nIn the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG \npins of the JTAG-DP.\n" }, { "page_number": 1688, "page_indices": { "start_index": 3282531, "end_index": 3283615 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1688 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.3 SWJ debug port (serial wire and JTAG)", 1687 ], [ 3, "38.3.1 Mechanism to select the JTAG-DP or the SW-DP", 1688 ], [ 2, "38.4 Pinout and debug port pins", 1688 ] ], "page_content": "Debug support (DBG)\nRM0090\n1688/1757\nRM0090 Rev 21\nFigure 486. SWJ debug port\nFigure 486 shows that the asynchronous TRACE output (TRACESWO) is multiplexed with \nTDO. This means that the asynchronous trace can only be used with SW-DP, not JTAG-DP. \n38.3.1 \nMechanism to select the JTAG-DP or the SW-DP\nBy default, the JTAG-Debug Port is active.\nIf the debugger host wants to switch to the SW-DP, it must provide a dedicated JTAG \nsequence on TMS/TCK (respectively mapped to SWDIO and SWCLK) which disables the \nJTAG-DP and enables the SW-DP. This way it is possible to activate the SWDP using only \nthe SWCLK and SWDIO pins.\nThis sequence is:\n1.\nSend more than 50 TCK cycles with TMS (SWDIO) =1\n2. \nSend the 16-bit sequence on TMS (SWDIO) = 0111100111100111 (MSB transmitted \nfirst)\n3. \nSend more than 50 TCK cycles with TMS (SWDIO) =1\n38.4 \nPinout and debug port pins\nThe STM32F4xx MCUs are available in various packages with different numbers of \navailable pins. As a result, some functionality (ETM) related to pin availability may differ \nbetween packages.\n" }, { "page_number": 1689, "page_indices": { "start_index": 3283615, "end_index": 3285564 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1689 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.4 Pinout and debug port pins", 1688 ], [ 3, "38.4.1 SWJ debug port pins", 1689 ], [ 3, "38.4.2 Flexible SWJ-DP pin assignment", 1689 ], [ 3, "38.4.3 Internal pull-up and pull-down on JTAG pins", 1689 ] ], "page_content": "RM0090 Rev 21\n1689/1757\nRM0090\nDebug support (DBG)\n1716\n38.4.1 \nSWJ debug port pins\nFive pins are used as outputs from the STM32F4xx for the SWJ-DP as alternate functions of \ngeneral-purpose I/Os. These pins are available on all packages.\n \n38.4.2 \nFlexible SWJ-DP pin assignment\nAfter RESET (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned \nas dedicated pins immediately usable by the debugger host (note that the trace outputs are \nnot assigned except if explicitly programmed by the debugger host).\nHowever, the STM32F4xx MCUs offers the possibility of disabling some or all of the SWJ-\nDP ports and so, of releasing the associated pins for general-purpose IO (GPIO) usage. For \nmore details on how to disable SWJ-DP port pins, please refer to Section 8.3.2: I/O pin \nmultiplexer and mapping.\n \n38.4.3 \nInternal pull-up and pull-down on JTAG pins\nIt is necessary to ensure that the JTAG input pins are not floating since they are directly \nconnected to flip-flops to control the debug mode features. Special care must be taken with \nthe SWCLK/TCK pin which is directly connected to the clock of some of these flip-flops.\nTable 299. SWJ debug port pins\nSWJ-DP pin name\nJTAG debug port\nSW debug port\nPin \nassignment\nType\nDescription\nType\nDebug assignment\nJTMS/SWDIO\nI\nJTAG Test Mode Selection\nIO\nSerial Wire Data Input/Output\nPA13\nJTCK/SWCLK\nI\nJTAG Test Clock\nI\nSerial Wire Clock\nPA14\nJTDI\nI\nJTAG Test Data Input\n-\n-\nPA15\nJTDO/TRACESWO\nO\nJTAG Test Data Output\n-\nTRACESWO if async trace is \nenabled\nPB3\nNJTRST\nI\nJTAG Test nReset\n-\n-\nPB4\nTable 300. Flexible SWJ-DP pin assignment\nAvailable debug ports\nSWJ IO pin assigned\nPA13 /\nJTMS /\nSWDIO\nPA14 /\nJTCK /\nSWCLK\nPA15 /\nJTDI\nPB3 / \nJTDO\nPB4 /\nNJTRST\nFull SWJ (JTAG-DP + SW-DP) - Reset State\nX\nX\nX\nX\nX\nFull SWJ (JTAG-DP + SW-DP) but without NJTRST\nX\nX\nX\nX\nJTAG-DP Disabled and SW-DP Enabled\nX\nX\nJTAG-DP Disabled and SW-DP Disabled\nReleased\n" }, { "page_number": 1690, "page_indices": { "start_index": 3285564, "end_index": 3286515 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1690 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.4 Pinout and debug port pins", 1688 ], [ 3, "38.4.3 Internal pull-up and pull-down on JTAG pins", 1689 ] ], "page_content": "Debug support (DBG)\nRM0090\n1690/1757\nRM0090 Rev 21\nTo avoid any uncontrolled IO levels, the device embeds internal pull-ups and pull-downs on \nthe JTAG input pins:\n•\nNJTRST: Internal pull-up\n•\nJTDI: Internal pull-up\n•\nJTMS/SWDIO: Internal pull-up\n•\nTCK/SWCLK: Internal pull-down\nOnce a JTAG IO is released by the user software, the GPIO controller takes control again. \nThe reset states of the GPIO control registers put the I/Os in the equivalent state:\n•\nNJTRST: AF input pull-up\n•\nJTDI: AF input pull-up\n•\nJTMS/SWDIO: AF input pull-up\n•\nJTCK/SWCLK: AF input pull-down \n•\nJTDO: AF output floating\nThe software can then use these I/Os as standard GPIOs.\nNote:\nThe JTAG IEEE standard recommends to add pull-ups on TDI, TMS and nTRST but there is \nno special recommendation for TCK. However, for JTCK, the device needs an integrated \npull-down.\nHaving embedded pull-ups and pull-downs removes the need to add external resistors.\n" }, { "page_number": 1691, "page_indices": { "start_index": 3286515, "end_index": 3288587 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1691 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.4 Pinout and debug port pins", 1688 ], [ 3, "38.4.4 Using serial wire and releasing the unused debug pins as GPIOs", 1691 ], [ 2, "38.5 STM32F4xx JTAG TAP connection", 1691 ] ], "page_content": "RM0090 Rev 21\n1691/1757\nRM0090\nDebug support (DBG)\n1716\n38.4.4 \nUsing serial wire and releasing the unused debug pins as GPIOs\nTo use the serial wire DP to release some GPIOs, the user software must change the GPIO \n(PA15, PB3 and PB4) configuration mode in the GPIO_MODER register. This releases \nPA15, PB3 and PB4 which now become available as GPIOs.\nWhen debugging, the host performs the following actions:\n•\nUnder system reset, all SWJ pins are assigned (JTAG-DP + SW-DP).\n•\nUnder system reset, the debugger host sends the JTAG sequence to switch from the \nJTAG-DP to the SW-DP.\n•\nStill under system reset, the debugger sets a breakpoint on vector reset.\n•\nThe system reset is released and the Core halts.\n•\nAll the debug communications from this point are done using the SW-DP. The other \nJTAG pins can then be reassigned as GPIOs by the user software.\nNote:\nFor user software designs, note that:\nTo release the debug pins, remember that they are first configured either in input-pull-up \n(nTRST, TMS, TDI) or pull-down (TCK) or output tristate (TDO) for a certain duration after \nreset until the instant when the user software releases the pins.\nWhen debug pins (JTAG or SW or TRACE) are mapped, changing the corresponding IO pin \nconfiguration in the IOPORT controller has no effect.\n38.5 \nSTM32F4xx JTAG TAP connection\nThe STM32F4xx MCUs integrate two serially connected JTAG TAPs, the boundary scan \nTAP (IR is 5-bit wide) and the Cortex®-M4 with FPU TAP (IR is 4-bit wide).\nTo access the TAP of the Cortex®-M4 with FPU for debug purposes:\n1.\nFirst, it is necessary to shift the BYPASS instruction of the boundary scan TAP.\n2. \nThen, for each IR shift, the scan chain contains 9 bits (=5+4) and the unused TAP \ninstruction must be shifted in using the BYPASS instruction.\n3. \nFor each data shift, the unused TAP, which is in BYPASS mode, adds 1 extra data bit in \nthe data scan chain.\nNote:\nImportant: Once Serial-Wire is selected using the dedicated Arm® JTAG sequence, the \nboundary scan TAP is automatically disabled (JTMS forced high).\n" }, { "page_number": 1692, "page_indices": { "start_index": 3288587, "end_index": 3288858 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1692 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.5 STM32F4xx JTAG TAP connection", 1691 ] ], "page_content": "Debug support (DBG)\nRM0090\n1692/1757\nRM0090 Rev 21\nFigure 487. JTAG TAP connections\nBoundary scan\nTAP\nNJTRST\nCortex-M4 TAP \nJTMS\nTMS nTRST\nTMS nTRST\nJTDI\nJTDO\nTDI\nTDO\nTDI\nTDO\nSW-DP\nSTM32F4xxx\nSelected\nIR is 5-bit wide\nIR is 4-bit wide\nMS19929V2\n" }, { "page_number": 1693, "page_indices": { "start_index": 3288858, "end_index": 3290643 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1693 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.6 ID codes and locking mechanism", 1693 ], [ 3, "38.6.1 MCU device ID code", 1693 ], [ 4, "DBGMCU_IDCODE", 1693 ] ], "page_content": "RM0090 Rev 21\n1693/1757\nRM0090\nDebug support (DBG)\n1716\n38.6 \nID codes and locking mechanism\nThere are several ID codes inside the STM32F4xx MCUs. ST strongly recommends tools \ndesigners to lock their debuggers using the MCU DEVICE ID code located in the external \nPPB memory map at address 0xE0042000.\n38.6.1 \nMCU device ID code\nThe STM32F4xx MCUs integrate an MCU ID code. This ID identifies the ST MCU part-\nnumber and the die revision. It is part of the DBG_MCU component and is mapped on the \nexternal PPB bus (see Section 38.16). This code is accessible using the JTAG debug port \n(four to five pins) or the SW debug port (two pins) or by the user software. It is even \naccessible while the MCU is under system reset. \nOnly the DEV_ID[11:0] must be used for identification by the debugger/programmer tools.\nDBGMCU_IDCODE\nAddress: 0xE004 2000\nOnly 32-bits access supported. Read-only.\n \n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nREV_ID[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDEV_ID[11:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 REV_ID[15:0] Revision identifier\nThis field indicates the revision of the device.\nSTM32F405xx/07xx and STM32F415xx/17xx devices:\n0x1000 = Revision A\n0x1001 = Revision Z\n0x1003 = Revision 1\n0x1007 = Revision 2\n0x100F= Revision Y and 4\n0x101F= Revision 5 and 6\nSTM32F42xxx and STM32F43xxx devices:\n0x1000 = Revision A\n0x1003 = Revision Y\n0x1007 = Revision 1\n0x2001= Revision 3\n0x2003= Revision 4, 5 and B\nBits 15:12 Reserved, must be kept at reset value.\nBits 11:0 DEV_ID[11:0]: Device identifier (STM32F405xx/07xx and STM32F415xx/17xx)\nThe device ID is 0x413.\nBits 11:0 DEV_ID[11:0]: Device identifier (STM32F42xxx and STM32F43xxx)\nThe device ID is 0x419\n" }, { "page_number": 1694, "page_indices": { "start_index": 3290643, "end_index": 3292608 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1694 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.6 ID codes and locking mechanism", 1693 ], [ 3, "38.6.2 Boundary scan TAP", 1694 ], [ 4, "JTAG ID code", 1694 ], [ 3, "38.6.3 Cortex®-M4 with FPU TAP", 1694 ], [ 3, "38.6.4 Cortex®-M4 with FPU JEDEC-106 ID code", 1694 ], [ 2, "38.7 JTAG debug port", 1694 ] ], "page_content": "Debug support (DBG)\nRM0090\n1694/1757\nRM0090 Rev 21\n38.6.2 \nBoundary scan TAP\nJTAG ID code\nThe TAP of the STM32F4xx BSC (boundary scan) integrates a JTAG ID code equal to .\n•\n0x06413041 for STM32F405xx/07xx and STM32F415xx/17xx devices\n•\n0x06419041 for STM32F42xxx and STM32F43xxx devices \n38.6.3 \nCortex®-M4 with FPU TAP\nThe TAP of the Arm® Cortex®-M4 with FPU integrates a JTAG ID code. This ID code is the \nArm® default one and has not been modified. This code is only accessible by the JTAG \nDebug Port, it is 0x4BA00477 (corresponds to Cortex®-M4 with FPU r0p1, see \nSection 38.2).\n38.6.4 \nCortex®-M4 with FPU JEDEC-106 ID code\nThe Arm® Cortex®-M4 with FPU integrates a JEDEC-106 ID code. It is located in the 4 KB \nROM table mapped on the internal PPB bus at address 0xE00FF000_0xE00FFFFF. \nThis code is accessible by the JTAG Debug Port (4 to 5 pins) or by the SW Debug Port (two \npins) or by the user software.\n38.7 \nJTAG debug port\nA standard JTAG state machine is implemented with a 4-bit instruction register (IR) and five \ndata registers (for full details, refer to the Cortex®-M4 with FPU r0p1 Technical Reference \nManual (TRM), for references, see Section 38.2).\n \nTable 301. JTAG debug port data registers\nIR(3:0)\nData register\nDetails\n1111\nBYPASS\n[1 bit]\n-\n1110\nIDCODE\n[32 bits]\nID CODE\n0x4BA00477 (Arm® Cortex®-M4 with FPU r0p1 ID Code)\n1010\nDPACC \n[35 bits]\nDebug port access register\nThis initiates a debug port and allows access to a debug port register.\n– When transferring data IN: \nBits 34:3 = DATA[31:0] = 32-bit data to transfer for a write request\nBits 2:1 = A[3:2] = 2-bit address of a debug port register.\nBit 0 = RnW = Read request (1) or write request (0).\n– When transferring data OUT: \nBits 34:3 = DATA[31:0] = 32-bit data which is read following a read \nrequest\nBits 2:0 = ACK[2:0] = 3-bit Acknowledge:\n010 = OK/FAULT\n001 = WAIT\nOTHER = reserved\nRefer to Table 302 for a description of the A[3:2] bits\n" }, { "page_number": 1695, "page_indices": { "start_index": 3292608, "end_index": 3294405 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1695 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.7 JTAG debug port", 1694 ] ], "page_content": "RM0090 Rev 21\n1695/1757\nRM0090\nDebug support (DBG)\n1716\n \n1011\nAPACC\n[35 bits]\nAccess port access register\nInitiates an access port and allows access to an access port register.\n– When transferring data IN: \nBits 34:3 = DATA[31:0] = 32-bit data to shift in for a write request\nBits 2:1 = A[3:2] = 2-bit address (sub-address AP registers).\nBit 0 = RnW= Read request (1) or write request (0).\n– When transferring data OUT: \nBits 34:3 = DATA[31:0] = 32-bit data which is read following a read \nrequest \nBits 2:0 = ACK[2:0] = 3-bit Acknowledge:\n010 = OK/FAULT\n001 = WAIT\nOTHER = reserved\nThere are many AP registers (see AHB-AP) addressed as the \ncombination of:\n– The shifted value A[3:2]\n– The current value of the DP SELECT register\n1000\nABORT\n[35 bits]\nAbort register\n– Bits 31:1 = Reserved\n– Bit 0 = DAPABORT: write 1 to generate a DAP abort.\nTable 302. 32-bit debug port registers addressed through the shifted value A[3:2] \nAddress\nA[3:2] value\nDescription\n0x0\n00\nReserved, must be kept at reset value.\n0x4\n01\nDP CTRL/STAT register. Used to:\n– Request a system or debug power-up\n– Configure the transfer operation for AP accesses\n– Control the pushed compare and pushed verify operations.\n– Read some status flags (overrun, power-up acknowledges)\n0x8\n10\nDP SELECT register: Used to select the current access port and the \nactive 4-words register window.\n– Bits 31:24: APSEL: select the current AP\n– Bits 23:8: reserved\n– Bits 7:4: APBANKSEL: select the active 4-words register window on the \ncurrent AP\n– Bits 3:0: reserved\n0xC\n11\nDP RDBUFF register: Used to allow the debugger to get the final result \nafter a sequence of operations (without requesting new JTAG-DP \noperation)\nTable 301. JTAG debug port data registers (continued)\nIR(3:0)\nData register\nDetails\n" }, { "page_number": 1696, "page_indices": { "start_index": 3294405, "end_index": 3296014 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1696 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.8 SW debug port", 1696 ], [ 3, "38.8.1 SW protocol introduction", 1696 ], [ 3, "38.8.2 SW protocol sequence", 1696 ] ], "page_content": "Debug support (DBG)\nRM0090\n1696/1757\nRM0090 Rev 21\n38.8 \nSW debug port\n38.8.1 \nSW protocol introduction\nThis synchronous serial protocol uses two pins:\n•\nSWCLK: clock from host to target\n•\nSWDIO: bidirectional\nThe protocol allows two banks of registers (DPACC registers and APACC registers) to be \nread and written to.\nBits are transferred LSB-first on the wire.\nFor SWDIO bidirectional management, the line must be pulled-up on the board (100 KΩ \nrecommended by Arm®).\nEach time the direction of SWDIO changes in the protocol, a turnaround time is inserted \nwhere the line is not driven by the host nor the target. By default, this turnaround time is one \nbit time, however this can be adjusted by configuring the SWCLK frequency.\n38.8.2 \nSW protocol sequence\nEach sequence consist of three phases:\n1.\nPacket request (8 bits) transmitted by the host \n2. \nAcknowledge response (3 bits) transmitted by the target\n3. \nData transfer phase (33 bits) transmitted by the host or the target\n \nRefer to the Cortex®-M4 with FPU r0p1 TRM for a detailed description of DPACC and \nAPACC registers.\nThe packet request is always followed by the turnaround time (default 1 bit) where neither \nthe host nor target drive the line.\nTable 303. Packet request (8-bits)\nBit\nName\nDescription\n0\nStart\nMust be “1”\n1\nAPnDP\n0: DP Access\n1: AP Access\n2\nRnW\n0: Write Request\n1: Read Request\n4:3\nA[3:2]\nAddress field of the DP or AP registers (refer to Table 302)\n5\nParity\nSingle bit parity of preceding bits\n6\nStop\n0\n7\nPark\nNot driven by the host. Must be read as “1” by the target because of \nthe pull-up\n" }, { "page_number": 1697, "page_indices": { "start_index": 3296014, "end_index": 3298376 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1697 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.8 SW debug port", 1696 ], [ 3, "38.8.3 SW-DP state machine (reset, idle states, ID code)", 1697 ], [ 3, "38.8.4 DP and AP read/write accesses", 1697 ] ], "page_content": "RM0090 Rev 21\n1697/1757\nRM0090\nDebug support (DBG)\n1716\n \nThe ACK Response must be followed by a turnaround time only if it is a READ transaction \nor if a WAIT or FAULT acknowledge has been received.\n \nThe DATA transfer must be followed by a turnaround time only if it is a READ transaction.\n38.8.3 \nSW-DP state machine (reset, idle states, ID code)\nThe State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It \nfollows the JEP-106 standard. This ID code is the default Arm® one and is set to \n0x2BA01477 (corresponding to Cortex®-M4 with FPU r0p1). \nNote:\nNote that the SW-DP state machine is inactive until the target reads this ID code.\n•\nThe SW-DP state machine is in RESET STATE either after power-on reset, or after the \nDP has switched from JTAG to SWD or after the line is high for more than 50 cycles \n•\nThe SW-DP state machine is in IDLE STATE if the line is low for at least two cycles \nafter RESET state.\n•\nAfter RESET state, it is mandatory to first enter into an IDLE state AND to perform a \nREAD access of the DP-SW ID CODE register. Otherwise, the target issues a FAULT \nacknowledge response on another transactions.\nFurther details of the SW-DP state machine can be found in the Cortex®-M4 with FPU r0p1 \nTRM and the CoreSight Design Kit r0p1 TRM.\n38.8.4 \nDP and AP read/write accesses\n•\nRead accesses to the DP are not posted: the target response can be immediate (if \nACK=OK) or can be delayed (if ACK=WAIT).\n•\nRead accesses to the AP are posted. This means that the result of the access is \nreturned on the next transfer. If the next access to be done is NOT an AP access, then \nthe DP-RDBUFF register must be read to obtain the result.\nThe READOK flag of the DP-CTRL/STAT register is updated on every AP read access \nor RDBUFF read request to know if the AP read access was successful.\n•\nThe SW-DP implements a write buffer (for both DP or AP writes), that enables it to \naccept a write operation even when other transactions are still outstanding. If the write \nbuffer is full, the target acknowledge response is “WAIT”. With the exception of \nTable 304. ACK response (3 bits)\nBit\nName\nDescription\n0..2\nACK\n001: FAULT\n010: WAIT\n100: OK\nTable 305. DATA transfer (33 bits)\nBit\nName\nDescription\n0..31\nWDATA or RDATA\nWrite or Read data\n32\nParity\nSingle parity of the 32 data bits\n" }, { "page_number": 1698, "page_indices": { "start_index": 3298376, "end_index": 3300399 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1698 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.8 SW debug port", 1696 ], [ 3, "38.8.5 SW-DP registers", 1698 ], [ 3, "38.8.6 SW-AP registers", 1698 ] ], "page_content": "Debug support (DBG)\nRM0090\n1698/1757\nRM0090 Rev 21\nIDCODE read or CTRL/STAT read or ABORT write which are accepted even if the write \nbuffer is full.\n•\nBecause of the asynchronous clock domains SWCLK and HCLK, two extra SWCLK \ncycles are needed after a write transaction (after the parity bit) to make the write \neffective internally. These cycles must be applied while driving the line low (IDLE state)\nThis is particularly important when writing the CTRL/STAT for a power-up request. If the \nnext transaction (requiring a power-up) occurs immediately, it fails.\n38.8.5 \nSW-DP registers\nAccess to these registers are initiated when APnDP=0\n \n38.8.6 \nSW-AP registers\nAccess to these registers are initiated when APnDP=1\nThere are many AP registers (see AHB-AP) addressed as the combination of:\n•\nThe shifted value A[3:2]\n•\nThe current value of the DP SELECT register\nTable 306. SW-DP registers\nA[3:2]\nR/W\nCTRLSEL bit \nof SELECT \nregister\nRegister\nNotes\n00\nRead\n-\nIDCODE\nThe manufacturer code is not set to ST code. \n0x2BA01477 (identifies the SW-DP)\n00\nWrite\n-\nABORT\n-\n01\nRead/Write\n0\nDP-\nCTRL/STAT\nPurpose is to:\n– request a system or debug power-up\n– configure the transfer operation for AP \naccesses\n– control the pushed compare and pushed verify \noperations.\n– read some status flags (overrun, power-up \nacknowledges)\n01\nRead/Write\n1\nWIRE \nCONTROL\nPurpose is to configure the physical serial port \nprotocol (like the duration of the turnaround \ntime)\n10\nRead\n-\nREAD \nRESEND\nEnables recovery of the read data from a \ncorrupted debugger transfer, without repeating \nthe original AP transfer.\n10\nWrite\n-\nSELECT\nThe purpose is to select the current access port \nand the active 4-words register window\n11\nRead/Write\n-\nREAD \nBUFFER\nThis read buffer is useful because AP accesses \nare posted (the result of a read AP request is \navailable on the next AP transaction).\nThis read buffer captures data from the AP, \npresented as the result of a previous read, \nwithout initiating a new transaction\n" }, { "page_number": 1699, "page_indices": { "start_index": 3300399, "end_index": 3301908 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1699 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.9 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP", 1699 ], [ 3, "Features:", 1699 ] ], "page_content": "RM0090 Rev 21\n1699/1757\nRM0090\nDebug support (DBG)\n1716\n38.9 \nAHB-AP (AHB access port) - valid for both JTAG-DP\nand SW-DP\nFeatures:\n•\nSystem access is independent of the processor status. \n•\nEither SW-DP or JTAG-DP accesses AHB-AP.\n•\nThe AHB-AP is an AHB master into the Bus Matrix. Consequently, it can access all the \ndata buses (Dcode Bus, System Bus, internal and external PPB bus) but the ICode \nbus.\n•\nBitband transactions are supported.\n•\nAHB-AP transactions bypass the FPB.\nThe address of the 32-bits AHP-AP resisters are 6-bits wide (up to 64 words or 256 bytes) \nand consists of:\nc) \nBits [7:4] = the bits [7:4] APBANKSEL of the DP SELECT register\nd) \nBits [3:2] = the 2 address bits of A[3:2] of the 35-bit packet request for SW-DP.\nThe AHB-AP of the Cortex®-M4 with FPU includes 9 x 32-bits registers:\n \nRefer to the Cortex®-M4 with FPU r0p1 TRM for further details.\nTable 307. Cortex®-M4 with FPU AHB-AP registers\nAddress \noffset\nRegister name\nNotes\n0x00\nAHB-AP Control and Status \nWord\nConfigures and controls transfers through the AHB \ninterface (size, hprot, status on current transfer, address \nincrement type\n0x04\nAHB-AP Transfer Address\n-\n0x0C\nAHB-AP Data Read/Write\n-\n0x10\nAHB-AP Banked Data 0 \nDirectly maps the 4 aligned data words without rewriting \nthe Transfer Address register.\n0x14\nAHB-AP Banked Data 1 \n0x18\nAHB-AP Banked Data 2 \n0x1C\nAHB-AP Banked Data 3 \n0xF8\nAHB-AP Debug ROM Address\nBase Address of the debug interface\n0xFC\nAHB-AP ID register\n-\n" }, { "page_number": 1700, "page_indices": { "start_index": 3301908, "end_index": 3303381 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1700 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.10 Core debug", 1700 ] ], "page_content": "Debug support (DBG)\nRM0090\n1700/1757\nRM0090 Rev 21\n38.10 \nCore debug\nCore debug is accessed through the core debug registers. Debug access to these registers \nis by means of the Advanced High-performance Bus (AHB-AP) port. The processor can \naccess these registers directly over the internal Private Peripheral Bus (PPB).\nIt consists of 4 registers:\n \nNote:\nImportant: these registers are not reset by a system reset. They are only reset by a power-\non reset.\nRefer to the Cortex®-M4 with FPU r0p1 TRM for further details.\nTo Halt on reset, it is necessary to:\n•\nenable the bit0 (VC_CORRESET) of the Debug and Exception Monitor Control register\n•\nenable the bit0 (C_DEBUGEN) of the Debug Halting Control and Status register.\nTable 308. Core debug registers\nRegister\nDescription\nDHCSR\nThe 32-bit Debug Halting Control and Status register\nThis provides status information about the state of the processor enable core debug \nhalt and step the processor\nDCRSR\nThe 17-bit Debug Core register Selector register: \nThis selects the processor register to transfer data to or from.\nDCRDR\nThe 32-bit Debug Core register Data register: \nThis holds data for reading and writing registers to and from the processor selected \nby the DCRSR (Selector) register.\nDEMCR\nThe 32-bit Debug Exception and Monitor Control register: \nThis provides Vector Catching and Debug Monitor Control. This register contains a \nbit named TRCENA which enable the use of a TRACE.\n" }, { "page_number": 1701, "page_indices": { "start_index": 3303381, "end_index": 3305007 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1701 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.11 Capability of the debugger host to connect under system reset", 1701 ], [ 2, "38.12 FPB (Flash patch breakpoint)", 1701 ] ], "page_content": "RM0090 Rev 21\n1701/1757\nRM0090\nDebug support (DBG)\n1716\n38.11 \nCapability of the debugger host to connect under system \nreset\nThe reset system of the STM32F4xx MCU comprises the following reset sources:\n•\nPOR (power-on reset) which asserts a RESET at each power-up.\n•\nInternal watchdog reset\n•\nSoftware reset\n•\nExternal reset\nThe Cortex®-M4 with FPU differentiates the reset of the debug part (generally \nPORRESETn) and the other one (SYSRESETn)\nThis way, it is possible for the debugger to connect under System Reset, programming the \nCore Debug registers to halt the core when fetching the reset vector. Then the host can \nrelease the system reset and the core immediately halts without having executed any \ninstructions. In addition, it is possible to program any debug features under System Reset.\nNote:\nIt is highly recommended for the debugger host to connect (set a breakpoint in the reset \nvector) under system reset.\n38.12 \nFPB (Flash patch breakpoint)\nThe FPB unit:\n•\nimplements hardware breakpoints\n•\npatches code and data from code space to system space. This feature gives the \npossibility to correct software bugs located in the Code Memory Space.\nThe use of a Software Patch or a Hardware Breakpoint is exclusive.\nThe FPB consists of:\n•\n2 literal comparators for matching against literal loads from Code Space and remapping \nto a corresponding area in the System Space.\n•\n6 instruction comparators for matching against instruction fetches from Code Space. \nThey can be used either to remap to a corresponding area in the System Space or to \ngenerate a Breakpoint Instruction to the core.\n" }, { "page_number": 1702, "page_indices": { "start_index": 3305007, "end_index": 3307199 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1702 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.13 DWT (data watchpoint trigger)", 1702 ], [ 2, "38.14 ITM (instrumentation trace macrocell)", 1702 ], [ 3, "38.14.1 General description", 1702 ], [ 3, "38.14.2 Time stamp packets, synchronization and overflow packets", 1702 ] ], "page_content": "Debug support (DBG)\nRM0090\n1702/1757\nRM0090 Rev 21\n38.13 \nDWT (data watchpoint trigger)\nThe DWT unit consists of four comparators. They are configurable as:\n•\na hardware watchpoint or\n•\na trigger to an ETM or\n•\na PC sampler or\n•\na data address sampler\nThe DWT also provides some means to give some profiling informations. For this, some \ncounters are accessible to give the number of:\n•\nClock cycle\n•\nFolded instructions\n•\nLoad store unit (LSU) operations\n•\nSleep cycles\n•\nCPI (clock per instructions)\n•\nInterrupt overhead\n38.14 \nITM (instrumentation trace macrocell)\n38.14.1 \nGeneral description\nThe ITM is an application-driven trace source that supports printf style debugging to trace \nOperating System (OS) and application events, and emits diagnostic system information. \nThe ITM emits trace information as packets which can be generated as:\n•\nSoftware trace. Software can write directly to the ITM stimulus registers to emit \npackets.\n•\nHardware trace. The DWT generates these packets, and the ITM emits them.\n•\nTime stamping. Timestamps are emitted relative to packets. The ITM contains a 21-bit \ncounter to generate the timestamp. The Cortex®-M4 with FPU clock or the bit clock rate \nof the Serial Wire Viewer (SWV) output clocks the counter.\nThe packets emitted by the ITM are output to the TPIU (Trace Port Interface Unit). The \nformatter of the TPIU adds some extra packets (refer to TPIU) and then output the complete \npackets sequence to the debugger host.\nThe bit TRCEN of the Debug Exception and Monitor Control register must be enabled \nbefore programming or using the ITM.\n38.14.2 \nTime stamp packets, synchronization and overflow packets\nTime stamp packets encode time stamp information, generic control and synchronization. It \nuses a 21-bit timestamp counter (with possible prescalers) which is reset at each time \nstamp packet emission. This counter can be either clocked by the CPU clock or the SWV \nclock.\nA synchronization packet consists of 6 bytes equal to 0x80_00_00_00_00_00 which is \nemitted to the TPIU as 00 00 00 00 00 80 (LSB emitted first). \nA synchronization packet is a timestamp packet control. It is emitted at each DWT trigger. \n" }, { "page_number": 1703, "page_indices": { "start_index": 3307199, "end_index": 3308956 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1703 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.14 ITM (instrumentation trace macrocell)", 1702 ], [ 3, "38.14.2 Time stamp packets, synchronization and overflow packets", 1702 ] ], "page_content": "RM0090 Rev 21\n1703/1757\nRM0090\nDebug support (DBG)\n1716\nFor this, the DWT must be configured to trigger the ITM: the bit CYCCNTENA (bit0) of the \nDWT Control register must be set. In addition, the bit2 (SYNCENA) of the ITM Trace Control \nregister must be set.\nNote:\nIf the SYNENA bit is not set, the DWT generates Synchronization triggers to the TPIU which \nsends only TPIU synchronization packets and not ITM synchronization packets.\nAn overflow packet consists is a special timestamp packets which indicates that data has \nbeen written but the FIFO was full.\n \nTable 309. Main ITM registers\nAddress\nRegister\nDetails\n@E0000FB0\nITM lock access\nWrite 0xC5ACCE55 to unlock Write Access to the other ITM \nregisters\n@E0000E80\nITM trace control\nBits 31-24 = Always 0\nBits 23 = Busy\nBits 22-16 = 7-bits ATB ID which identifies the source of the \ntrace data.\nBits 15-10 = Always 0\nBits 9:8 = TSPrescale = Time Stamp Prescaler\nBits 7-5 = Reserved\nBit 4 = SWOENA = Enable SWV behavior (to clock the \ntimestamp counter by the SWV clock).\nBit 3 = DWTENA: Enable the DWT Stimulus\nBit 2 = SYNCENA: this bit must be to 1 to enable the DWT to \ngenerate synchronization triggers so that the TPIU can then \nemit the synchronization packets.\nBit 1 = TSENA (Timestamp Enable)\nBit 0 = ITMENA: Global Enable Bit of the ITM\n@E0000E40\nITM trace privilege\nBit 3: mask to enable tracing ports31:24\nBit 2: mask to enable tracing ports23:16\nBit 1: mask to enable tracing ports15:8\nBit 0: mask to enable tracing ports7:0\n@E0000E00\nITM trace enable\nEach bit enables the corresponding Stimulus port to generate \ntrace.\n@E0000000-\nE000007C\nStimulus port \nregisters 0-31\nWrite the 32-bits data on the selected Stimulus Port (32 \navailable) to be traced out.\n" }, { "page_number": 1704, "page_indices": { "start_index": 3308956, "end_index": 3310951 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1704 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.14 ITM (instrumentation trace macrocell)", 1702 ], [ 3, "38.14.2 Time stamp packets, synchronization and overflow packets", 1702 ], [ 4, "Example of configuration", 1704 ], [ 2, "38.15 ETM (Embedded Trace Macrocell™)", 1704 ], [ 3, "38.15.1 ETM general description", 1704 ], [ 3, "38.15.2 ETM signal protocol and packet types", 1704 ] ], "page_content": "Debug support (DBG)\nRM0090\n1704/1757\nRM0090 Rev 21\nExample of configuration\nTo output a simple value to the TPIU:\n•\nConfigure the TPIU and assign TRACE I/Os by configuring the DBGMCU_CR (refer to \nSection 38.17.2 and Section 38.16.3)\n•\nWrite 0xC5ACCE55 to the ITM Lock Access register to unlock the write access to the \nITM registers\n•\nWrite 0x00010005 to the ITM Trace Control register to enable the ITM with Sync \nenabled and an ATB ID different from 0x00\n•\nWrite 0x1 to the ITM Trace Enable register to enable the Stimulus Port 0\n•\nWrite 0x1 to the ITM Trace Privilege register to unmask stimulus ports 7:0\n•\nWrite the value to output in the Stimulus Port register 0: this can be done by software \n(using a printf function)\n38.15 \nETM (Embedded Trace Macrocell™)\n38.15.1 \nETM general description\nThe ETM enables the reconstruction of program execution. Data are traced using the Data \nWatchpoint and Trace (DWT) component or the Instruction Trace Macrocell (ITM) whereas \ninstructions are traced using the Embedded Trace Macrocell (ETM).\nThe ETM transmits information as packets and is triggered by embedded resources. These \nresources must be programmed independently and the trigger source is selected using the \nTrigger Event register (0xE0041008). An event could be a simple event (address match \nfrom an address comparator) or a logic equation between 2 events. The trigger source is \none of the fourth comparators of the DWT module, The following events can be monitored:\n•\nClock cycle matching\n•\nData address matching\nFor more informations on the trigger resources refer to Section 38.13.\nThe packets transmitted by the ETM are output to the TPIU (Trace Port Interface Unit). The \nformatter of the TPIU adds some extra packets (refer to Section 38.17) and then outputs the \ncomplete packet sequence to the debugger host.\n38.15.2 \nETM signal protocol and packet types\nThis part is described in the chapter 7 ETMv3 Signal Protocol of the Arm® IHI 0014N \ndocument.\n" }, { "page_number": 1705, "page_indices": { "start_index": 3310951, "end_index": 3313093 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1705 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.15 ETM (Embedded Trace Macrocell™)", 1704 ], [ 3, "38.15.3 Main ETM registers", 1705 ], [ 3, "38.15.4 ETM configuration example", 1705 ], [ 2, "38.16 MCU debug component (DBGMCU)", 1705 ], [ 3, "38.16.1 Debug support for low-power modes", 1705 ] ], "page_content": "RM0090 Rev 21\n1705/1757\nRM0090\nDebug support (DBG)\n1716\n38.15.3 \nMain ETM registers\nFor more information on registers refer to the chapter 3 of the Arm® IHI 0014N specification.\n \n38.15.4 \nETM configuration example\nTo output a simple value to the TPIU:\n•\nConfigure the TPIU and enable the I/IO_TRACEN to assign TRACE I/Os in the \nSTM32F4xx debug configuration register.\n•\nWrite 0xC5AC CE55 to the ETM Lock Access register to unlock the write access to the \nITM registers\n•\nWrite 0x0000 1D1E to the ETM control register (configure the trace)\n•\nWrite 0x0000 406F to the ETM Trigger Event register (define the trigger event)\n•\nWrite 0x0000 006F to the ETM Trace Enable Event register (define an event to \nstart/stop)\n•\nWrite 0x0200 00000x0000 0001 to the ETM Trace Start/stop register (enable the trace)\n•\nWrite 0x0000191E to the ETM Control register (end of configuration)\n38.16 \nMCU debug component (DBGMCU)\nThe MCU debug component helps the debugger provide support for: \n•\nLow-power modes\n•\nClock control for timers, watchdog, I2C and bxCAN during a breakpoint\n•\nControl of the trace pins assignment\n38.16.1 \nDebug support for low-power modes\nTo enter low-power mode, the instruction WFI or WFE must be executed.\nThe MCU implements several low-power modes which can either deactivate the CPU clock \nor reduce the power of the CPU.\nTable 310. Main ETM registers\nAddress\nRegister\nDetails\n0xE0041FB0 ETM Lock Access\nWrite 0xC5ACCE55 to unlock the write access to the \nother ETM registers.\n0xE0041000 ETM Control\nThis register controls the general operation of the ETM, \nfor instance how tracing is enabled.\n0xE0041010 ETM Status\nThis register provides information about the current status \nof the trace and trigger logic.\n0xE0041008 ETM Trigger Event\nThis register defines the event that controls trigger.\n0xE004101C ETM Trace Enable \nControl\nThis register defines which comparator is selected.\n0xE0041020 ETM Trace Enable Event\nThis register defines the trace enabling event.\n0xE0041024 ETM Trace Start/Stop\nThis register defines the traces used by the trigger source \nto start and stop the trace, respectively.\n" }, { "page_number": 1706, "page_indices": { "start_index": 3313093, "end_index": 3315309 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1706 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.16 MCU debug component (DBGMCU)", 1705 ], [ 3, "38.16.2 Debug support for timers, watchdog, bxCAN and I2C", 1706 ], [ 3, "38.16.3 Debug MCU configuration register", 1706 ], [ 4, "DBGMCU_CR register", 1706 ] ], "page_content": "Debug support (DBG)\nRM0090\n1706/1757\nRM0090 Rev 21\nThe core does not allow FCLK or HCLK to be turned off during a debug session. As these \nare required for the debugger connection, during a debug, they must remain active. The \nMCU integrates special means to allow the user to debug software in low-power modes.\nFor this, the debugger host must first set some debug configuration registers to change the \nlow-power mode behavior:\n•\nIn Sleep mode, DBG_SLEEP bit of DBGMCU_CR register must be previously set by \nthe debugger. This feeds HCLK with the same clock that is provided to FCLK (system \nclock previously configured by the software).\n•\nIn Stop mode, the bit DBG_STOP must be previously set by the debugger. This \nenables the internal RC oscillator clock to feed FCLK and HCLK in STOP mode.\n38.16.2 \nDebug support for timers, watchdog, bxCAN and I2C\nDuring a breakpoint, it is necessary to choose how the counter of timers and watchdog must \nbehave:\n•\nThey can continue to count inside a breakpoint. This is usually required when a PWM is \ncontrolling a motor, for example.\n•\nThey can stop to count inside a breakpoint. This is required for watchdog purposes.\nFor the bxCAN, the user can choose to block the update of the receive register during a \nbreakpoint.\nFor the I2C, the user can choose to block the SMBUS timeout during a breakpoint.\nFor timers having complementary outputs, when the counter is stopped \n(DBG_TIMx_STOP = 1), the outputs are disabled (as if the MOE bit was reset) for safety \npurposes.\n38.16.3 \nDebug MCU configuration register\nThis register allows the configuration of the MCU under DEBUG. This concerns:\n•\nLow-power mode support\n•\nTimer and watchdog counter support\n•\nbxCAN communication support\n•\nTrace pin assignment\nThis DBGMCU_CR is mapped on the External PPB bus at address 0xE0042004\nIt is asynchronously reset by the PORESET (and not the system reset). It can be written by \nthe debugger under system reset.\nIf the debugger host does not support these features, it is still possible for the user software \nto write to these registers.\nDBGMCU_CR register\nAddress: 0xE004 2004\nOnly 32-bit access supported\nPOR Reset: 0x0000 0000 (not reset by system reset)\n" }, { "page_number": 1707, "page_indices": { "start_index": 3315309, "end_index": 3318006 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1707 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.16 MCU debug component (DBGMCU)", 1705 ], [ 3, "38.16.3 Debug MCU configuration register", 1706 ], [ 4, "DBGMCU_CR register", 1706 ] ], "page_content": "RM0090 Rev 21\n1707/1757\nRM0090\nDebug support (DBG)\n1716\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nTRACE_\nMODE\n[1:0]\nTRACE\n_IOEN\nReserved\nDBG_\nSTAND\nBY\nDBG_\nSTOP\nDBG_\nSLEEP\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved, must be kept at reset value.\nBits 7:5 TRACE_MODE[1:0] and TRACE_IOEN: Trace pin assignment control\n– With TRACE_IOEN=0:\nTRACE_MODE=xx: TRACE pins not assigned (default state)\n– With TRACE_IOEN=1:\n–\nTRACE_MODE=00: TRACE pin assignment for Asynchronous mode\n–\nTRACE_MODE=01: TRACE pin assignment for Synchronous mode with a \nTRACEDATA size of 1\n–\nTRACE_MODE=10: TRACE pin assignment for Synchronous mode with a \nTRACEDATA size of 2\n–\nTRACE_MODE=11: TRACE pin assignment for Synchronous mode with a \nTRACEDATA size of 4\nBits 4:3 Reserved, must be kept at reset value.\nBit 2 DBG_STANDBY: Debug Standby mode\n0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.\nFrom software point of view, exiting from Standby is identical than fetching reset vector \n(except a few status bit indicated that the MCU is resuming from Standby)\n1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and FCLK and \nHCLK are provided by the internal RC oscillator which remains active. In addition, the MCU \ngenerate a system reset during Standby mode so that exiting from Standby is identical than \nfetching from reset\nBit 1 DBG_STOP: Debug Stop mode\n0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all clocks (including \nHCLK and FCLK). When exiting from STOP mode, the clock configuration is identical to the \none after RESET (CPU clocked by the 8 MHz internal RC oscillator (HSI)). Consequently, \nthe software must reprogram the clock controller to enable the PLL, the Xtal, etc.\n1: (FCLK=On, HCLK=On) In this case, when entering STOP mode, FCLK and HCLK are \nprovided by the internal RC oscillator which remains active in STOP mode. When exiting \nSTOP mode, the software must reprogram the clock controller to enable the PLL, the Xtal, \netc. (in the same way it would do in case of DBG_STOP=0)\nBit 0 DBG_SLEEP: Debug Sleep mode\n0: (FCLK=On, HCLK=Off) In Sleep mode, FCLK is clocked by the system clock as \npreviously configured by the software while HCLK is disabled.\nIn Sleep mode, the clock controller configuration is not reset and remains in the previously \nprogrammed state. Consequently, when exiting from Sleep mode, the software does not \nneed to reconfigure the clock controller.\n1: (FCLK=On, HCLK=On) In this case, when entering Sleep mode, HCLK is fed by the same \nclock that is provided to FCLK (system clock as previously configured by the software). \n" }, { "page_number": 1708, "page_indices": { "start_index": 3318006, "end_index": 3319817 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1708 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.16 MCU debug component (DBGMCU)", 1705 ], [ 3, "38.16.4 Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)", 1708 ] ], "page_content": "Debug support (DBG)\nRM0090\n1708/1757\nRM0090 Rev 21\n38.16.4 \nDebug MCU APB1 freeze register (DBGMCU_APB1_FZ)\nThe DBGMCU_APB1_FZ register is used to configure the MCU under Debug. It concerns \nAPB1 peripherals. It is mapped on the external PPB bus at address 0xE004 2008.\nThe register is asynchronously reset by the POR (and not the system reset). It can be \nwritten by the debugger under system reset.\nAddress : 0xE004 2008\nOnly 32-bits access are supported.\nPower-on reset (POR): 0x0000 0000 (not reset by system reset)\n \n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nDBG_CAN2_STOP\nDBG_CAN1_STOP\nReserved\nDBG_I2C3_SMBUS_TIMEOUT\nDBG_I2C2_SMBUS_TIMEOUT\nDBG_I2C1_SMBUS_TIMEOUT\nReserved\nrw\nrw\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDBG_IWDG_STOP\nDBG_WWDG_STOP\nDBG_RTC_STOP\nReserved\nDBG_TIM14_STOP\nDBG_TIM13_STOP\nDBG_TIM12_STOP\nDBG_TIM7_STOP\nDBG_TIM6_STOP\nDBG_TIM5_STOP\nDBG_TIM4_STOP\nDBG_TIM3_STOP\nDBG_TIM2_STOP\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:27\nReserved, must be kept at reset value.\nBit 26 DBG_CAN2_STOP: Debug CAN2 stopped when Core is halted\n0: Same behavior as in normal mode\n1: The CAN2 receive registers are frozen\nBit 25 DBG_CAN1_STOP: Debug CAN2 stopped when Core is halted\n0: Same behavior as in normal mode\n1: The CAN2 receive registers are frozen\nBit 24\nReserved, must be kept at reset value.\nBit 23 DBG_I2C3_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted\n0: Same behavior as in normal mode\n1: The SMBUS timeout is frozen\nBit 22 DBG_I2C2_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted\n0: Same behavior as in normal mode\n1: The SMBUS timeout is frozen\nBit 21 DBG_I2C1_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted\n0: Same behavior as in normal mode\n1: The SMBUS timeout is frozen\n" }, { "page_number": 1709, "page_indices": { "start_index": 3319817, "end_index": 3321862 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1709 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.16 MCU debug component (DBGMCU)", 1705 ], [ 3, "38.16.5 Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ)", 1709 ] ], "page_content": "RM0090 Rev 21\n1709/1757\nRM0090\nDebug support (DBG)\n1716\n38.16.5 \nDebug MCU APB2 Freeze register (DBGMCU_APB2_FZ)\nThe DBGMCU_APB2_FZ register is used to configure the MCU under Debug. It concerns \nAPB2 peripherals.\nThis register is mapped on the external PPB bus at address 0xE004 200C\nIt is asynchronously reset by the POR (and not the system reset). It can be written by the \ndebugger under system reset.\nAddress: 0xE004 200C\nOnly 32-bit access is supported.\nPOR: 0x0000 0000 (not reset by system reset)\n \n \nBit 20:13\nReserved, must be kept at reset value.\nBit 12 DBG_IWDG_STOP: Debug independent watchdog stopped when core is halted\n0: The independent watchdog counter clock continues even if the core is halted\n1: The independent watchdog counter clock is stopped when the core is halted\nBit 11 DBG_WWDG_STOP: Debug Window Watchdog stopped when Core is halted\n0: The window watchdog counter clock continues even if the core is halted\n1: The window watchdog counter clock is stopped when the core is halted\nBit 10 DBG_RTC_STOP: RTC stopped when Core is halted\n0: The RTC counter clock continues even if the core is halted\n1: The RTC counter clock is stopped when the core is halted\nBit 9\nReserved, must be kept at reset value.\nBits 8:0 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=2..7, 12..14)\n0: The clock of the involved timer counter is fed even if the core is halted \n1: The clock of the involved timer counter is stopped and the outputs are disabled when the \ncore is halted\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\nDBG_TIM11\n_STOP\nDBG_TIM10\n_STOP\nDBG_TIM9_\nSTOP\nrw\nrw\nrw\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nReserved\nDBG_TIM8_\nSTOP\nDBG_TIM1_\nSTOP\nrw\nrw\nBits 31:19\nReserved, must be kept at reset value.\nBits 18:16 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=9..11)\n0: The clock of the involved timer counter is fed even if the core is halted \n1: The clock of the involved timer counter is stopped and the outputs are disabled when the \ncore is halted\n" }, { "page_number": 1710, "page_indices": { "start_index": 3321862, "end_index": 3322896 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1710 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.17 TPIU (trace port interface unit)", 1710 ], [ 3, "38.17.1 Introduction", 1710 ] ], "page_content": "Debug support (DBG)\nRM0090\n1710/1757\nRM0090 Rev 21\n38.17 \nTPIU (trace port interface unit)\n38.17.1 \nIntroduction\nThe TPIU acts as a bridge between the on-chip trace data from the ITM and the ETM.\nThe output data stream encapsulates the trace source ID, that is then captured by a trace \nport analyzer (TPA).\nThe core embeds a simple TPIU, especially designed for low-cost debug (consisting of a \nspecial version of the CoreSight TPIU).\nFigure 488. TPIU block diagram\nBits 15:\nReserved, must be kept at reset value.\nBit 1 DBG_TIM8_STOP: TIM8 counter stopped when core is halted\n0: The clock of the involved timer counter is fed even if the core is halted \n1: The clock of the involved timer counter is stopped and the outputs are disabled when the \ncore is halted\nBit 0 DBG_TIM1_STOP: TIM1 counter stopped when core is halted\n0: The clock of the involved timer counter is fed even if the core is halted \n1: The clock of the involved timer counter is stopped and the outputs are disabled when the \ncore is halted\n" }, { "page_number": 1711, "page_indices": { "start_index": 3322896, "end_index": 3324931 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1711 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.17 TPIU (trace port interface unit)", 1710 ], [ 3, "38.17.2 TRACE pin assignment", 1711 ], [ 4, "TPUI TRACE pin assignment", 1711 ] ], "page_content": "RM0090 Rev 21\n1711/1757\nRM0090\nDebug support (DBG)\n1716\n38.17.2 \nTRACE pin assignment\n•\nAsynchronous mode\nThe asynchronous mode requires 1 extra pin and is available on all packages. It is only \navailable if using Serial Wire mode (not in JTAG mode).\n \n•\nSynchronous mode\nThe synchronous mode requires from 2 to 6 extra pins depending on the data trace \nsize and is only available in the larger packages. In addition it is available in JTAG \nmode and in Serial Wire mode and provides better bandwidth output capabilities than \nasynchronous trace.\n \nTPUI TRACE pin assignment\nBy default, these pins are NOT assigned. They can be assigned by setting the \nTRACE_IOEN and TRACE_MODE bits in the MCU Debug component configuration \nregister. This configuration has to be done by the debugger host.\nIn addition, the number of pins to assign depends on the trace configuration (asynchronous \nor synchronous). \n•\nAsynchronous mode: 1 extra pin is needed\n•\nSynchronous mode: from 2 to 5 extra pins are needed depending on the size of the \ndata trace port register (1, 2 or 4):\n–\nTRACECK\n–\nTRACED(0) if port size is configured to 1, 2 or 4\n–\nTRACED(1) if port size is configured to 2 or 4\n–\nTRACED(2) if port size is configured to 4\n–\nTRACED(3) if port size is configured to 4\nTo assign the TRACE pin, the debugger host must program the bits TRACE_IOEN and \nTRACE_MODE[1:0] of the Debug MCU configuration register (DBGMCU_CR). By default \nthe TRACE pins are not assigned.\nThis register is mapped on the external PPB and is reset by the PORESET (and not by the \nSYSTEM reset). It can be written by the debugger under SYSTEM reset.\nTable 311. Asynchronous TRACE pin assignment\nTPUI pin name\nTrace synchronous mode\nSTM32F4xx pin \nassignment\nType\nDescription\nTRACESWO\nO\nTRACE Async Data Output\nPB3\nTable 312. Synchronous TRACE pin assignment\nTPUI pin name\nTrace synchronous mode\nSTM32F4xxpin \nassignment\nType\nDescription\nTRACECK\nO\nTRACE Clock\nPE2\nTRACED[3:0]\nO\nTRACE Sync Data Outputs\nCan be 1, 2 or 4.\nPE[6:3]\n" }, { "page_number": 1712, "page_indices": { "start_index": 3324931, "end_index": 3326843 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1712 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.17 TPIU (trace port interface unit)", 1710 ], [ 3, "38.17.3 TPUI formatter", 1712 ] ], "page_content": "Debug support (DBG)\nRM0090\n1712/1757\nRM0090 Rev 21\n \nNote:\nBy default, the TRACECLKIN input clock of the TPIU is tied to GND. It is assigned to HCLK \ntwo clock cycles after the bit TRACE_IOEN has been set.\nThe debugger must then program the Trace Mode by writing the PROTOCOL[1:0] bits in the \nSPP_R (Selected Pin Protocol) register of the TPIU.\n•\nPROTOCOL=00: Trace Port Mode (synchronous)\n•\nPROTOCOL=01 or 10: Serial Wire (Manchester or NRZ) Mode (asynchronous mode).\nDefault state is 01\nIt then also configures the TRACE port size by writing the bits [3:0] in the CPSPS_R \n(Current Sync Port Size register) of the TPIU:\n•\n0x1 for 1 pin (default state)\n•\n0x2 for 2 pins\n•\n0x8 for 4 pins\n38.17.3 \nTPUI formatter\nThe formatter protocol outputs data in 16-byte frames:\n•\nseven bytes of data\n•\neight bytes of mixed-use bytes consisting of:\n–\n1 bit (LSB) to indicate it is a DATA byte (‘0) or an ID byte (‘1).\n–\n7 bits (MSB) which can be data or change of source ID trace.\n•\none byte of auxiliary bits where each bit corresponds to one of the eight mixed-use \nbytes:\n–\nif the corresponding byte was a data, this bit gives bit0 of the data.\n–\nif the corresponding byte was an ID change, this bit indicates when that ID change \ntakes effect.\nTable 313. Flexible TRACE pin assignment\nDBGMCU_CR\nregister\nPins \nassigned\nfor:\nTRACE IO pin assigned\nTRACE\n_IOEN\nTRACE\n_MODE\n[1:0]\nPB3 /JTDO/ \nTRACESWO\nPE2/\nTRACECK\nPE3 /\nTRACED[0]\nPE4 /\nTRACED[1]\nPE5 /\nTRACED[2]\nPE6 /\nTRACED[3]\n0\nXX\nNo Trace \n(default state)\nReleased (1)\n-\n1\n00\nAsynchronous \nTrace\nTRACESWO\n-\n-\nReleased\n(usable as GPIO)\n1\n01\nSynchronous \nTrace 1 bit\nReleased (1)\nTRACECK\nTRACED[0]\n-\n-\n-\n1\n10\nSynchronous \nTrace 2 bit\nTRACECK\nTRACED[0]\nTRACED[1]\n-\n-\n1\n11\nSynchronous \nTrace 4 bit\nTRACECK\nTRACED[0]\nTRACED[1]\nTRACED[2]\nTRACED[3]\n1.\nWhen Serial Wire mode is used, it is released. But when JTAG is used, it is assigned to JTDO.\n" }, { "page_number": 1713, "page_indices": { "start_index": 3326843, "end_index": 3329427 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1713 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.17 TPIU (trace port interface unit)", 1710 ], [ 3, "38.17.4 TPUI frame synchronization packets", 1713 ], [ 3, "38.17.5 Transmission of the synchronization frame packet", 1713 ], [ 3, "38.17.6 Synchronous mode", 1713 ] ], "page_content": "RM0090 Rev 21\n1713/1757\nRM0090\nDebug support (DBG)\n1716\nNote:\nRefer to the Arm® CoreSight Architecture Specification v1.0 (Arm® IHI 0029B) for further \ninformation\n38.17.4 \nTPUI frame synchronization packets\nThe TPUI can generate two types of synchronization packets:\n•\nThe Frame Synchronization packet (or Full Word Synchronization packet) \nIt consists of the word: 0x7F_FF_FF_FF (LSB emitted first). This sequence can not \noccur at any other time provided that the ID source code 0x7F has not been used.\nIt is output periodically between frames. \nIn continuous mode, the TPA must discard all these frames once a synchronization \nframe has been found.\n•\nThe Half-Word Synchronization packet \nIt consists of the half word: 0x7F_FF (LSB emitted first).\nIt is output periodically between or within frames. \nThese packets are only generated in continuous mode and enable the TPA to detect \nthat the TRACE port is in IDLE mode (no TRACE to be captured). When detected by \nthe TPA, it must be discarded.\n38.17.5 \nTransmission of the synchronization frame packet\nThere is no Synchronization Counter register implemented in the TPIU of the core. \nConsequently, the synchronization trigger can only be generated by the DWT. Refer to the \nregisters DWT Control register (bits SYNCTAP[11:10]) and the DWT Current PC Sampler \nCycle Count register.\nThe TPUI Frame synchronization packet (0x7F_FF_FF_FF) is emitted:\n•\nafter each TPIU reset release. This reset is synchronously released with the rising \nedge of the TRACECLKIN clock. This means that this packet is transmitted when the \nTRACE_IOEN bit in the DBGMCU_CFG register is set. In this case, the word \n0x7F_FF_FF_FF is not followed by any formatted packet.\n•\nat each DWT trigger (assuming DWT has been previously configured). Two cases \noccur:\n–\nIf the bit SYNENA of the ITM is reset, only the word 0x7F_FF_FF_FF is emitted \nwithout any formatted stream which follows.\n–\nIf the bit SYNENA of the ITM is set, then the ITM synchronization packets follow \n(0x80_00_00_00_00_00), formatted by the TPUI (trace source ID added). \n38.17.6 \nSynchronous mode\nThe trace data output size can be configured to 4, 2 or 1 pin: TRACED(3:0)\nThe output clock is output to the debugger (TRACECK)\nHere, TRACECLKIN is driven internally and is connected to HCLK only when TRACE is \nused.\nNote:\nIn this synchronous mode, it is not required to provide a stable clock frequency.\nThe TRACE I/Os (including TRACECK) are driven by the rising edge of TRACLKIN (equal \nto HCLK). Consequently, the output frequency of TRACECK is equal to HCLK/2.\n" }, { "page_number": 1714, "page_indices": { "start_index": 3329427, "end_index": 3331664 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1714 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.17 TPIU (trace port interface unit)", 1710 ], [ 3, "38.17.7 Asynchronous mode", 1714 ], [ 3, "38.17.8 TRACECLKIN connection inside the STM32F4xx", 1714 ], [ 3, "38.17.9 TPIU registers", 1714 ] ], "page_content": "Debug support (DBG)\nRM0090\n1714/1757\nRM0090 Rev 21\n38.17.7 \nAsynchronous mode\nThis is a low cost alternative to output the trace using only 1 pin: this is the asynchronous \noutput pin TRACESWO. Obviously there is a limited bandwidth. \nTRACESWO is multiplexed with JTDO when using the SW-DP pin. This way, this \nfunctionality is available in all STM32F4xx packages.\nThis asynchronous mode requires a constant frequency for TRACECLKIN. For the standard \nUART (NRZ) capture mechanism, 5% accuracy is needed. The Manchester encoded \nversion is tolerant up to 10%.\n38.17.8 \nTRACECLKIN connection inside the STM32F4xx\nIn the STM32F4xx, this TRACECLKIN input is internally connected to HCLK. This means \nthat when in asynchronous trace mode, the application is restricted to use to time frames \nwhere the CPU frequency is stable.\nNote:\nImportant: when using asynchronous trace: it is important to be aware that:\nThe default clock of the STM32F4xx MCUs is the internal RC oscillator. Its frequency under \nreset is different from the one after reset release. This is because the RC calibration is the \ndefault one under system reset and is updated at each system reset release.\nConsequently, the trace port analyzer (TPA) must not enable the trace (with the \nTRACE_IOEN bit) under system reset, because a Synchronization Frame Packet is issued \nwith a different bit time than trace packets which are transmitted after reset release.\n38.17.9 \nTPIU registers\nThe TPIU APB registers can be read and written only if the bit TRCENA of the Debug \nException and Monitor Control register (DEMCR) is set. Otherwise, the registers are read as \nzero (the output of this bit enables the PCLK of the TPIU).\n \nTable 314. Important TPIU registers\nAddress\nRegister\nDescription\n0xE0040004\nCurrent port size\nAllows the trace port size to be selected:\nBit 0: Port size = 1\nBit 1: Port size = 2\nBit 2: Port size = 3, not supported\nBit 3: Port Size = 4\nOnly 1 bit must be set. By default, the port size is one bit. (0x00000001)\n0xE00400F0\nSelected pin protocol\nAllows the Trace Port Protocol to be selected:\nBit1:0= \n00: Sync Trace Port Mode\n01: Serial Wire Output - manchester (default value)\n10: Serial Wire Output - NRZ\n11: reserved\n" }, { "page_number": 1715, "page_indices": { "start_index": 3331664, "end_index": 3333308 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1715 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.17 TPIU (trace port interface unit)", 1710 ], [ 3, "38.17.10 Example of configuration", 1715 ] ], "page_content": "RM0090 Rev 21\n1715/1757\nRM0090\nDebug support (DBG)\n1716\n38.17.10 Example of configuration\n•\nSet the bit TRCENA in the Debug Exception and Monitor Control register (DEMCR)\n•\nWrite the TPIU Current Port Size register to the desired value (default is 0x1 for a 1-bit \nport size)\n•\nWrite TPIU Formatter and Flush Control register to 0x102 (default value)\n•\nWrite the TPIU Select Pin Protocol to select the sync or async mode. Example: 0x2 for \nasync NRZ mode (UART like)\n•\nWrite the DBGMCU control register to 0x20 (bit IO_TRACEN) to assign TRACE I/Os \nfor async mode. A TPIU Sync packet is emitted at this time (FF_FF_FF_7F)\n•\nConfigure the ITM and write the ITM Stimulus register to output a value\n0xE0040304\nFormatter and flush \ncontrol\nBits 31-9 = always ‘0\nBit 8 = TrigIn = always ‘1 to indicate that triggers are indicated\nBits 7-4 = always 0\nBits 3-2 = always 0\nBit 1 = EnFCont. In Sync Trace mode (Select_Pin_Protocol register \nbit1:0=00), this bit is forced to ‘1: the formatter is automatically enabled in \ncontinuous mode. In asynchronous mode (Select_Pin_Protocol register \nbit1:0 <> 00), this bit can be written to activate or not the formatter.\nBit 0 = always 0\nThe resulting default value is 0x102\nNote: In synchronous mode, because the TRACECTL pin is not mapped \noutside the chip, the formatter is always enabled in continuous mode -this \nway the formatter inserts some control packets to identify the source of the \ntrace packets).\n0xE0040300\nFormatter and flush \nstatus\nNot used in Cortex®-M4 with FPU, always read as 0x00000008\nTable 314. Important TPIU registers (continued)\nAddress\nRegister\nDescription\n" }, { "page_number": 1716, "page_indices": { "start_index": 3333308, "end_index": 3334589 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1716 }, "toc_details": [ [ 1, "38 Debug support (DBG)", 1686 ], [ 2, "38.18 DBG register map", 1716 ] ], "page_content": "Debug support (DBG)\nRM0090\n1716/1757\nRM0090 Rev 21\n38.18 \nDBG register map\nThe following table summarizes the Debug registers. \n \n \nTable 315. DBG register map and reset values\nAddr.\nRegister\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n0xE004 \n2000\nDBGMCU\n_IDCODE\nREV_ID\nReserved\nDEV_ID\nReset value(1)\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\nX\n0xE004 \n2004\nDBGMCU_CR\nReserved\nDBG_TIM7_STOP\nDBG_TIM6_STOP\nDBG_TIM5_STOP\nDBG_TIM8_STOP\nDBG_I2C2_SMBUS_TIMEOUT\nReserved\nTRACE_MODE[1:0]\nTRACE_IOEN\nReserved\nDBG_STANDBY\nDBG_STOP\nDBG_SLEEP\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xE004 \n2008\nDBGMCU_\nAPB1_FZ\nReserved\nDBG_CAN2_STOP\nDBG_CAN1_STOP\nReserved\nDBG_I2C3_SMBUS_TIMEOUT\nDBG_I2C2_SMBUS_TIMEOUT\nDBG_I2C1_SMBUS_TIMEOUT\nReserved\nDBG_IWDG_STOP\nDBG_WWDG_STOP\nReserved\nDBG_RTC_STOP\nDBG_TIM14_STOP\nDBG_TIM13_STOP\nDBG_TIM12_STOP\nDBG_TIM7_STOP\nDBG_TIM6_STOP\nDBG_TIM5_STOP\nDBG_TIM4_STOP\nDBG_TIM3_STOP\nDBG_TIM2_STOP\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0xE004 \n200C\nDBGMCU_\nAPB2_FZ\nReserved\nDBG_TIM11_STOP\nDBG_TIM10_STOP\nDBG_TIM9_STOP\nReserved\nDBG_TIM8_STOP\nDBG_TIM1_STOP\nReset value\n0\n0\n0\n0\n0\n1.\nThe reset value is product dependent. For more information, refer to Section 38.6.1: MCU device ID code.\n" }, { "page_number": 1717, "page_indices": { "start_index": 3334589, "end_index": 3336381 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1717 }, "toc_details": [ [ 1, "39 Device electronic signature", 1717 ], [ 2, "39.1 Unique device ID register (96 bits)", 1717 ], [ 3, "Base address: 0x1FFF 7A10", 1717 ] ], "page_content": "RM0090 Rev 21\n1717/1757\nRM0090\nDevice electronic signature\n1718\n39 \nDevice electronic signature\nThe electronic signature is stored in the Flash memory area. It can be read using the \nJTAG/SWD or the CPU. It contains factory-programmed identification data that allow the \nuser firmware or other external devices to automatically match its interface to the \ncharacteristics of the STM32F4xx microcontrollers.\n39.1 \nUnique device ID register (96 bits)\nThe unique device identifier is ideally suited:\n•\nfor use as serial numbers (for example USB string serial numbers or other end \napplications)\n•\nfor use as security keys in order to increase the security of code in Flash memory while \nusing and combining this unique ID with software cryptographic primitives and \nprotocols before programming the internal Flash memory\n•\nto activate secure boot processes, etc.\nThe 96-bit unique device identifier provides a reference number which is unique for any \ndevice and in any context. These bits can never be altered by the user.\nThe 96-bit unique device identifier can also be read in single bytes/half-words/words in \ndifferent ways and then be concatenated using a custom algorithm.\nBase address: 0x1FFF 7A10\nAddress offset: 0x00\nRead only = 0xXXXX XXXX where X is factory-programmed\n \n \nAddress offset: 0x04\nRead only = 0xXXXX XXXX where X is factory-programmed\n \n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nUID(31:0)\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 UID(31:0): X and Y coordinates on the wafer\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nUID(63:48)\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nUID(47:32)\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n" }, { "page_number": 1718, "page_indices": { "start_index": 3336381, "end_index": 3337314 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1718 }, "toc_details": [ [ 1, "39 Device electronic signature", 1717 ], [ 2, "39.2 Flash size", 1718 ] ], "page_content": "Device electronic signature\nRM0090\n1718/1757\nRM0090 Rev 21\n \nAddress offset: 0x08\nRead only = 0xXXXX XXXX where X is factory-programmed\n \n \n39.2 \nFlash size\nBase address: 0x1FFF 7A22\nAddress offset: 0x00\nRead only = 0xXXXX where X is factory-programmed\n \n \nBits 31:8 UID(63:40): LOT_NUM[23:0]\nLot number (ASCII encoded).\nBits 7:0 UID(39:32): WAF_NUM[7:0]\nWafer number (ASCII encoded).\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nUID(95:80)\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nUID(79:64)\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:0 UID(95:64): LOT_NUM[55:24]\nLot number (ASCII encoded).\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nF_SIZE\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 15:0 F_ID(15:0): Flash memory size\nThis bitfield indicates the size of the device Flash memory expressed in Kbytes.\nAs an example, 0x0400 corresponds to 1024 Kbytes.\n" }, { "page_number": 1719, "page_indices": { "start_index": 3337314, "end_index": 3341305 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1719 }, "toc_details": [ [ 1, "40 Important security notice", 1719 ] ], "page_content": "RM0090 Rev 21\n1719/1757\nRM0090\nImportant security notice\n1719\n40 \nImportant security notice\nThe STMicroelectronics group of companies (ST) places a high value on product security, \nwhich is why the ST product(s) identified in this documentation may be certified by various \nsecurity certification bodies and/or may implement our own security measures as set forth \nherein. However, no level of security certification and/or built-in security measures can \nguarantee that ST products are resistant to all forms of attacks. As such, it is the \nresponsibility of each of ST's customers to determine if the level of security provided in an \nST product meets the customer needs both in relation to the ST product alone, as well as \nwhen combined with other components and/or software for the customer end product or \napplication. In particular, take note that:\n•\nST products may have been certified by one or more security certification bodies, such \nas Platform Security Architecture (www.psacertified.org) and/or Security Evaluation \nstandard for IoT Platforms (www.trustcb.com). For details concerning whether the ST \nproduct(s) referenced herein have received security certification along with the level \nand current status of such certification, either visit the relevant certification standards \nwebsite or go to the relevant product page on www.st.com for the most up to date \ninformation. As the status and/or level of security certification for an ST product can \nchange from time to time, customers should re-check security certification status/level \nas needed. If an ST product is not shown to be certified under a particular security \nstandard, customers should not assume it is certified. \n•\nCertification bodies have the right to evaluate, grant and revoke security certification in \nrelation to ST products. These certification bodies are therefore independently \nresponsible for granting or revoking security certification for an ST product, and ST \ndoes not take any responsibility for mistakes, evaluations, assessments, testing, or \nother activity carried out by the certification body with respect to any ST product. \n•\nIndustry-based cryptographic algorithms (such as AES, DES, or MD5) and other open \nstandard technologies which may be used in conjunction with an ST product are based \non standards which were not developed by ST. ST does not take responsibility for any \nflaws in such cryptographic algorithms or open technologies or for any methods which \nhave been or may be developed to bypass, decrypt or crack such algorithms or \ntechnologies. \n•\nWhile robust security testing may be done, no level of certification can absolutely \nguarantee protections against all attacks, including, for example, against advanced \nattacks which have not been tested for, against new or unidentified forms of attack, or \nagainst any form of attack when using an ST product outside of its specification or \nintended use, or in conjunction with other components or software which are used by \ncustomer to create their end product or application. ST is not responsible for resistance \nagainst such attacks. As such, regardless of the incorporated security features and/or \nany information or support that may be provided by ST, each customer is solely \nresponsible for determining if the level of attacks tested for meets their needs, both in \nrelation to the ST product alone and when incorporated into a customer end product or \napplication. \n•\nAll security features of ST products (inclusive of any hardware, software, \ndocumentation, and the like), including but not limited to any enhanced security \nfeatures added by ST, are provided on an \"AS IS\" BASIS. AS SUCH, TO THE EXTENT \nPERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS \nOR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF \nMERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the \napplicable written and signed contract terms specifically provide otherwise.\n" }, { "page_number": 1720, "page_indices": { "start_index": 3341305, "end_index": 3342916 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1720 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Revision history\nRM0090\n1720/1757\nRM0090 Rev 21\n41 \nRevision history\n \nTable 316. Document revision history\nDate\nVersion\nChanges\n15-Sep-2011\n1\nInitial release.\n19-Oct-2012\n2\nUpdated reference documents and added Table 1: Applicable products on cover \npage.\nMEMORY:\nUpdated Section 2: Memory and bus architecture.\nPWR:\nUpdated VDDA and VREF+ decoupling capacitor in Figure 7: Power supply \noverview.\nVOSRDY bit changed to read-only in Section 5.4.3: PWR power control/status \nregister (PWR_CSR).\nRemoved VDDA in Section 5.2.3: Programmable voltage detector (PVD) and \nremove VDDA in PVDO bit description (Section 5.4.3: PWR power control/status \nregister (PWR_CSR)).\nRCC:\nUpdated Figure 20: Simplified diagram of the reset circuit and minimum reset pulse \nduration guaranteed by pulse generator restricted to internal reset sources.\nGPIOs:\nUpdated Section 8.3.1: General-purpose I/O (GPIO).\nDMA:\nUpdated direct mode description in Section 10.2: DMA main features.\nUpdated direct mode description in Section : Memory-to-peripheral mode, and \nSection 10.3.12: FIFO/: Direct mode.\nUpdated register access in Section 10.5: DMA registers.\nModified Stream2 /Channel 2 in Table 42: DMA1 request mapping.\nAdded note related to EN bit in Section 10.5.5: DMA stream x configuration register \n(DMA_SxCR) (x = 0..7). Updated definition of NDT[15:0] bits in Section 10.5.6: \nDMA stream x number of data register (DMA_SxNDTR) (x = 0..7).\nInterrupts:\nUpdated number of maskable interrupts to 82 in Section 12.1.1: NVIC featuress.\nUpdated Section 12.2: External interrupt/event controller (EXTI).\n" }, { "page_number": 1721, "page_indices": { "start_index": 3342916, "end_index": 3344600 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1721 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090 Rev 21\n1721/1757\nRM0090\nRevision history\n1751\n19-Oct-2012\n2 \n(continued)\nADC:\nChanged ADCCLK frequency to 30 MHz in Section 13.5: Channel-wise \nprogrammable sampling timee.\nAdded recovery from ADC sequence in Section 13.8.1: Using the DMA and Section \n13.8.2: Managing a sequence of conversions without using the DMA.\nUpdated AWDIE in Section 13.13.2: ADC control register 1 (ADC_CR1). Added \nread and write access in Section 13.13: ADC registers.\nAdvanced control timers (TIM1 and TIM8):\nUpdated 16-bit prescaler range in Section 17.2: TIM1 and TIM8 main features.\nUpdated OC1 block diagram in Figure 114: Output stage of capture/compare \nchannel (channel 1 to 3).\nUpdated update event generation in Upcounting mode and Downcounting mode in \nSection 17.3.2: Counter modes and Section 17.3.3: Repetition counter.\nUpdated bits that control the dead-time generation in Section 17.3.11: \nComplementary outputs and dead-time insertion.\nUpdated ways to generate a break in Section 17.3.12: Using the break function.\nChanged OCxREF to ETR in the example given in Section 17.3.13: Clearing the \nOCxREF signal on an external event and changed\nOCREF_CLR to ETRF in Figure 124: Clearing TIMx OCxREF.\nUpdated configuration for example of counter operation in encoder\ninterface mode in Section 17.3.16: Encoder interface mode.\nAdded register access in Section 17.4: TIM1 and TIM8 registers.\nChanged definition of ARR[15:0] bits in Section 17.4.12: TIM1 and TIM8 auto-\nreload register (TIMx_ARR).\nUpdated BKE definition in Section 17.4.18: TIM1 and TIM8 break and dead-time \nregister (TIMx_BDTR).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1722, "page_indices": { "start_index": 3344600, "end_index": 3346364 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1722 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Revision history\nRM0090\n1722/1757\nRM0090 Rev 21\n19-Oct-2012\n2 \n(continued)\nGeneral purpose timers (TIM2 to TIM5):\nRemoved all references to “repetition counter”.\nAdded Figure 134: General-purpose timer block diagram.\nUpdated 16-bit prescaler range in Section 18.2: TIM2 to TIM5 main features.\nExternal clock mode 2 ETR restricted to TIM2 to TIM4 in\nSection 18.3.3: Clock selection and Section 18.3.6: PWM input mode.\nUpdated Section 18.3.9: PWM mode and Section 18.3.11: Clearing the OCxREF \nsignal on an external event.\nUpdated Figure 174: Master/Slave timer example to change ITR1 to\nITR0.\nUpdated read and write access to registers in Section 18.4: TIM2 to TIM5 \nregisterss.\nRestored bits 15 to 8 of TIMx_SMCR as well as Table 98: TIMx internal trigger \nconnection in Section 14.4.3.\nRemoved note 1 related to OC1M bits in Section 18.4.13: TIMx capture/compare \nregister 1 (TIMx_CCR1).\nUpdated TIMx_CCER bit description for TIM2 to TIM5 in\nSection 18.4.9: TIMx capture/compare enable register (TIMx_CCER).\nGeneral purpose timers (TIM9 to TIM14):\nUpdated 16-bit prescaler range in Section 19.2.1: TIM9/TIM12 main features and \nSection 19.2.2: TIM10/TIM11 and TIM13/TIM14 main features.\nUpdated Figure 181: General-purpose timer block diagram (TIM10/11/13/14)) to \nremove TRGO trigger controller output.\nAdded register access in Section 19.4: TIM9 and TIM12 registers\nand Section 19.5: TIM10/11/13/14 registers.\nBasic timers (TIM6 and TIM7):\nRemoved all references to “repetition counter”.\nUpdated 16-bit prescaler range in Section 20.2: TIM6 and TIM7 main features.\nHASH:\nUpdated Section 25.3.1: Duration of the processing.\nRNG:\nUpdated Section 24.1: RNG introduction.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1723, "page_indices": { "start_index": 3346364, "end_index": 3348417 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1723 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090 Rev 21\n1723/1757\nRM0090\nRevision history\n1751\n19-Oct-2012\n2 \n(continued)\nRTC:\nUpdated Figure 237: RTC block diagram.\nAdded formula to compute fck_apre in Figure 26.3.1: Clock and prescalers.\nUpdated Section 26.3.9: RTC reference clock detection.\nUpdated Section : RTC register write protection.\nAdded RTC_SSR shadow register in Section 26.3.6: Reading the calendar.\nUpdated description of DC[4:0] bits in Section 26.6.7: RTC calibration register \n(RTC_CALIBR).\nRenamed RTC_BKxR into RTC_BKPxR in Table 121: RTC register map and reset \nvalues.\nAdded power-on reset value and changed reset value to system\nreset value in Section 26.6.11: RTC sub second register (RTC_SSR).\nUpdated definition of ALARMOUTTYPE in Section 26.6.17: RTC tamper and \nalternate function configuration register (RTC_TAFCR).\nI2C:\nModified Section 27.3.8: DMA requests.\nUpdated bit 14 description in Section 27.6.3: I2C Own address register 1 \n(I2C_OAR1)).\nUpdated definition of PE bit and note related to SWRST bit; moved\nnote related to STOP bit to the whole register in Section 27.6.1: I2C Control register \n1 (I2C_CR1).\nUSART:\nSection 30.6.6: Control register 3 (USART_CR3)): removed notes\nrelated to UART5 in DMAT and DMAR description.\nUpdated TTable 142: Error calculation for programmed baud rates at fPCLK = 42 \nMHz or fPCLK = 84 Hz, oversampling by 16 and\nTable 143: Error calculation for programmed baud rates at fPCLK = 42 MHz or \nfPCLK = 84 MHz, oversampling by 8.\nSPI/I2S:\nUpdated Section 28.1: SPI introduction.\nChanged I2S simplex communication/mode to half-duplex communication/mode. \nUpdated flags in reception/transmission modes in Section 28.2.2: I2S features. \nAdded Frame error flag in Table 128: I2S interrupt requests. \nAdded register access in Section 28.5: SPI and I2S registers.\nUpdated ERRIE definition in Section 28.5.2: SPI control register 2 (SPI_CR2).\nRenamed TIFRFE to FRE and definition updated in Section 28.5.3: SPI status \nregister (SPI_SR).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1724, "page_indices": { "start_index": 3348417, "end_index": 3350078 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1724 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Revision history\nRM0090\n1724/1757\nRM0090 Rev 21\n19-Oct-2012\n2 \n(continued)\nSDIO:\nUpdated value and description for bits [45:40] and [7:1] in Table 176: R4 response. \nUpdated value at bits [45:40] in Table 178: R5 response.\nCAN:\nUpdated Figure 335: Dual CAN block diagram.\nModified definition of CAN2SB bits in Section : CAN filter master register \n(CAN_FMR).\nAdded register access in Section 32.9: CAN registers\nETHERNET:\nUpdated standard for precision networked clock synchronization in Section 33.1: \nEthernet introduction and Section 33.2.1: MAC core features.\nUpdated CR bit definition in Section : Ethernet MAC MII address register \n(ETH_MACMIIAR).\nReplace RTPR by PM bit in Table 192: Source address filtering.\nUSB OTG FS\nUpdated remote wake-up signaling bit and the resume\ninterrupt in Section : Suspended state.\nAdded peripheral register access in Section 34.16: OTG_FS control and status \nregisterss.\nUpdated INEPTXSA description in OTG_FS_DIEPTXFx.\nChanged PHYSEL from bit 7 to bit 6 of the OTG_FS_GUSBCFG\nregister.\nUSB OTG HS\nUpdated remote wake-up signaling bit and the resume\ninterrupt in Section : Suspended state.\nAdded peripheral register access in Section 35.12: OTG_HS control and status \nregisters.\nUpdated OTG_HS_CID reset value. \nUpdated INEPTXSA description in OTG_HS_DIEPTXFx.\nUpdated FSLSPCS for LS host mode, added PHYSEL in Section : OTG_HS host \nconfiguration register (OTG_HS_HCFG).\nRenamed PHYSEL into PHSEL and changed from bit 7 to bit 6 of\nthe OTG_HS_GUSBCFG register.\nUpdated OTG_HS_DIEPEACHMSK1 and OTG_HS_DOEPEACHMSK1 reset \nvalues.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1725, "page_indices": { "start_index": 3350078, "end_index": 3351995 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1725 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090 Rev 21\n1725/1757\nRM0090\nRevision history\n1751\n19-Oct-2012\n2 \n(continued)\nFSMC:\nUpdated step b) in Section 36.3.1: Supported memories and transactions.\nUpdated Table 196: FSMC_BTRx bit fields.\nChanged Clock divide ration min in Table 246: Programmable NAND/PC Card \naccess parameters.\nUpdated case of synchronous accesses in Section 36.5: NOR Flash/PSRAM \ncontroller.\nChanged minimum value for ADDSET to 0 in Table 203, Table 206, Table 207, \nTable 209, and Table 210.\nMove note from Figure 437: Mode1 write accesses and Figure 436: Mode1 read \naccesses. Move note from Figure 439: ModeA write accesses to Figure 438: \nModeA read accesses.\nUpdated Section : WAIT management in asynchronous accesses.\nAdded register access in Section 36.5.6: NOR/PSRAM control registers and \nSection 36.6.2: NAND Flash / PC Card supported memories and transactions.\nRemoved caution note in Section 36.6.1: External memory interface signalss.\nUpdated Table 249: 16-bit PC Card.\nUpdated step 3 in Section 36.6.4: NAND Flash operations.\nUpdated Figure 455: Access to non ‘CE don’t care’ NAND-Flash and note below in \nSection 36.6.5: NAND Flash prewait functionality. \nUpdated access to I/O Space in Section 36.6.7: PC Card/CompactFlash \noperationss. Updated Table 251: 16-bit PC-Card signals and access type. Updated \nBUSTURN bit definition in Section : SRAM/NOR-Flash chip-select timing registers \n1..4 (FSMC_BTR1..4)). Changed bits 16 to 19 to BUSTURN in Section : \nSRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4)\nDEBUG: \nUpdated Section 38.4.3: Internal pull-up and pull-down on JTAG pins.\nElectronic signature\nUpdated Section 24: Device electronic signature introduction. \nUpdated REV_ID[15:0] to add revision Z in Section 24.1: Unique device ID register \n(96 bits).\nUpdated address and example in Section 24.2: Flash size.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1726, "page_indices": { "start_index": 3351995, "end_index": 3354587 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1726 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Revision history\nRM0090\n1726/1757\nRM0090 Rev 21\n13-Nov-2012\n3\nAdded STM32F42x and STM32F43x devices.\nRemoved reference du Flash programming manual on cover page. Added Section \n2.3.2: Flash memory overview and Section 3: Embedded Flash memory interface. \nChange RTC_50Hz into RTC_REFIN in Section 8.3.2: I/O pin multiplexer and \nmapping. Modified RTC alternate function naming in Section 8: General-purpose \nI/Os (GPIO) and Section 26: Real-time clock (RTC).\nUpdated max. input frequency in Section 26.3.1: Clock and prescalers.\nChanged bit access type from ‘rw’ to ‘w’ and bit description updated in Section \n10.5.3: DMA low interrupt flag clear register (DMA_LIFCR) and Section 10.5.4: \nDMA high interrupt flag clear register (DMA_HIFCR). \nUpdated Figure 18: Frequency measurement with TIM5 in Input capture mode.\nUpdated Section : Signals synchronization in Section 36: Flexible static memory \ncontroller (FSMC)\nSection 34: USB on-the-go full-speed (OTG_FS): updated Section Figure 389.: \nUSB host-only connection, Section : VBUS valid, and Section : Host detection of a \nperipheral connection.\nSection 35: USB on-the-go high-speed (OTG_HS): updated Section : VBUS valid, \nand Section : Detection of peripheral connection by the host.\n19-Feb-2013\n4\nUpdated Section 2: Memory and bus architecture.\nUpdated Figure 1: System architecture for STM32F405xx/07xx and \nSTM32F415xx/17xx devices, and Figure 1: System architecture for \nSTM32F405xx/07xx and STM32F415xx/17xx devices. Updated Table 4: Memory \nmapping vs. Boot mode/physical remap. Updated Figure 5: Sequential 32-bit \ninstruction execution. removed note 1 from Table 13: Maximum program/erase \nparallelism. \nPWR:\nUpdated Figure 7: Power supply overview.\nUpdated Section 5.1.3: Voltage regulator.\nAdded ADCDC1 bit in Section 5.5.1: PWR power control register (PWR_CR) for \nSTM32F42xxx and STM32F43xxx.\nSYSCFG:\nAdded ADCxDC2 bit in Section 8.2.3: SYSCFG peripheral mode configuration \nregister (SYSCFG_PMC) for STM32F42xxx and STM32F43xxx.\nADC:\nUpdated Section 13.9.3: Interleaved mode, Section 13.9.4: Alternate trigger mode, \nand Section 13.9.5: Combined regular/injected simultaneous mode to describe \ncase of interrupted conversion.\nUpdated Section : Temperature sensor, VREFINT and VBAT internal channels, \nSection 13.10: Temperature sensor, and Section 13.11: Battery charge monitoring.\nRTC:\nUpdated BKP[31:0] bit description in Section 26.6.20: RTC backup registers \n(RTC_BKPxR).\nI2C:\nUpdated Section 27.3.5: Programmable noise filter.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1727, "page_indices": { "start_index": 3354587, "end_index": 3355752 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1727 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090 Rev 21\n1727/1757\nRM0090\nRevision history\n1751\n19-Feb-2013\n4 \n(continued)\nFSMC: \nUpdated write FIFO size in Section 36.1: FSMC main features.\nUpdated Figure 434: FSMC block diagram.\nUpdated Section 36.5.4: NOR Flash/PSRAM controller asynchronous transactions.\nModified differences between Mode B and mode 1 in Section : Mode 2/B - NOR \nFlash.\nModified differences between Mode C and mode 1 in Section : Mode C - NOR \nFlash - OE toggling.\nModified differences between Mode D and mode 1 in Section : Mode D - \nasynchronous access with extended address.\nUpdated NWAIT signal in Figure 449: Asynchronous wait during a read access, \nFigure 450: Asynchronous wait during a write access, Figure 451: Wait \nconfigurations, Figure 452: Synchronous multiplexed read mode - NOR, PSRAM \n(CRAM), and Figure 453: Synchronous multiplexed write mode - PSRAM (CRAM).\nUpdated Table 195 to Table 214.\nUpdated Section : SRAM/NOR-Flash chip-select control registers 1..4 \n(FSMC_BCR1..4).\nDEBUG\nUpdated Figure 485: Block diagram of STM32 MCU and Cortex®-M4 with FPU-\nlevel debug support.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1728, "page_indices": { "start_index": 3355752, "end_index": 3357602 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1728 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Revision history\nRM0090\n1728/1757\nRM0090 Rev 21\n15-Sep-2013\n5\nAdded STM32F429xx and STM32F439xx part numbers.\nReplaced FSMC by FMC added Chrom-ART Accelerator, LCD-TFT and SAI \ninterface.\nUpdated Figure 2: System architecture for STM32F42xxx and STM32F43xxx \ndevices.\nPWR:\nUpdated Section 5.2.2: Brownout reset (BOR).\nAdded note related to CSS enabling in Entering Stop mode sections in Section \n5.3.4: Stop mode (STM32F405xx/07xx and STM32F415xx/17xx) and Section 5.3.5: \nStop mode (STM32F42xxx and STM32F43xxx). Updated Stop mode entry in Table \n27 and Table 29.\nUpdated WUF bit defienition in PWR_CSR registers. Changed CWUF and CSBF \naccess type to ‘w’ in PWR_CR register. \nRCC: Updated LSEBYP bit definition in RCC_BDCR register.\nGPIOs:\nUpdated description of OSPEEDR bits. Removed frequency value in description of \nOSPEEDR bits.Corrected typos: \"IDRy[15:0]\" replaced with \"IDRy\" in \"GPIOx_IDR\" \nregister, \"ODRy[15:0]\" replaced with \"ODRy\" in \"GPIOx_ODR\" register and \n\"OTy[1:0]\" replaced with \"OTy\" in \"GPIOx_OTYPER\" register.\nDCMI: Updated Section 15.4: DCMI clocks.\nIWDG: Corrected Figure 213: Independent watchdog block diagram.\nRTC: \nReplaced all occurrences of “power-on reset” with “backup domain reset”. Added \ncaution note under Table 121: RTC register map and reset values. Changed SHPF \nbit type to ‘r’ in Section 26.6.4: RTC initialization and status register (RTC_ISR)..\nSPI: Updated definition of ERRIE bit in Section 28.5.2: SPI control register 2 \n(SPI_CR2).\nUART: \nUpdated Section 30.3.8: LIN (local interconnection network) mode.\nRemoved note in Section 30.3.13: Continuous communication using DMA. \nETHERNET:\nModified ETH_MACA0HR (and ETH_DMABMR reset values.\nUpdated definitions of TSTS bit in ETH_MACSR, and TSTTR in ETH_PTPTSSR.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1729, "page_indices": { "start_index": 3357602, "end_index": 3358886 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1729 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090 Rev 21\n1729/1757\nRM0090\nRevision history\n1751\n15-Sep-2013\n5 \n(continued)\nUSB OTG-FS:\nRemoved note related to VDD range limitation below Figure 387: OTG A-B device \nconnection and Figure 388: USB peripheral-only connection.\nFSMC:\nUpdated Table 229, Table 232, Table 235, Table 239.\nReplaced all occurences of DATALAT by DATLAT and SRAM/CRAM by \nSRAM/PSRAM in the whole section. \nUpdated Section 36.1: FSMC main features. Changed bits 27 to 20 of \nFSMC_BWTR1..4 to reserved.\nUpdated Section 36.6.7: PC Card/CompactFlash operations. \nUpdated WREN bit in Table 231, Table 232, Table 233, Table 236, Table 239, Table \n242, Table 245, and Table 249. \nUpdated Section 36.5.4: NOR Flash/PSRAM controller asynchronous transactions, \nSection : SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4), \nSection : SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) and \nSection : SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4).\nUpdated definition of PWID in Section : PC Card/NAND Flash control registers 2..4 \n(FSMC_PCR2..4).\nFMC: \nUpdated TRDC definition in Section : SDRAM Timing registers 1,2 \n(FMC_SDTR1,2).\nDEBUG: updated Figure 487: JTAG TAP connections.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1730, "page_indices": { "start_index": 3358886, "end_index": 3360216 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1730 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Revision history\nRM0090\n1730/1757\nRM0090 Rev 21\n03-Feb-2014\n6\nAdded note related to over-drive mode unavailable in 1.8 to 2.1 V VDD range in \nSection 3.5.1: Relation between CPU clock frequency and Flash memory read \ntime.\nUpdated maximum CPU frequency in Section 3.5.2: Adaptive real-time memory \naccelerator (ART Accelerator™).\nPWR: \nUpdated Run mode/ over-drive mode in Section 5.1.4: Voltage regulator for \nSTM32F42xxx and STM32F43xxx.\nRCC for STM32F42/43xx: \nChanged APB1/2 and AHB maximum frequencies.xw\nGPIOs: \nUpdated Figure 27: Selecting an alternate function on STM32F42xxx and \nSTM32F43xxx.\nDMA: \nUpdated Section 10.3.7: Pointer incrementation and Section 10.3.11: Single and \nburst transfers.. \nINTERRUPTS AND EVENTS:\nUpdated Table 62: Vector table for STM32F42xxx and STM32F43xxx.\nADC: \nUpdated Section 13.3.10: Discontinuous mode/Section : Regular group.\nDCMI: \nUpdated Section 15.5.2: DCMI physical interface.\nLTDC: \nUpdated resolution in note below Figure 82: LCD-TFT Synchronous timings.\nTIM1 and 8: \nAdded note related to IC1F in Section 17.4.7: TIM1 and TIM8 capture/compare \nmode register 1 (TIMx_CCMR1).\nTIM2 to 5: \nUpdated note related to IC1F in Section 18.4.7: TIMx capture/compare mode \nregister 1 (TIMx_CCMR1).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1731, "page_indices": { "start_index": 3360216, "end_index": 3361692 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1731 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090 Rev 21\n1731/1757\nRM0090\nRevision history\n1751\n03-Feb-2014\n6 \n(continued)\nTIM9 to 14: \nUpdated note related to IC1F in Section 19.5.5: TIM10/11/13/14 capture/compare \nmode register 1 (TIMx_CCMR1).\nRTC: \nUpdated Section 26.3.11: RTC smooth digital calibration.\nChanged ALRBIE to ALRBE (bit 9) in Section 26.6.3: RTC control register \n(RTC_CR).\nI2C: \nIntroduced Sm (standard mode) and Fm (fast mode) acronyms. \nFSMC: \nUpdated BUSTURN definition in Table 245: FSMC_BTRx bit fields.\nFMC:\nAdded Mobile LPSDR SDRAM.\nUpdated Section : SDRAM initialization and Section : SDRAM controller read cycle \nand Figure 476: NAND Flash/PC Card controller waveforms for common memory \naccess. \nUpdated Section : SRAM/NOR-Flash chip-select control registers 1..4 \n(FMC_BCR1..4), Section : SRAM/NOR-Flash chip-select timing registers 1..4 \n(FMC_BTR1..4), Section : SRAM/NOR-Flash write timing registers 1..4 \n(FMC_BWTR1..4), Section : SDRAM Timing registers 1,2 (FMC_SDTR1,2) and \nSection : SDRAM Refresh Timer register (FMC_SDRTR).\nRemoved mention “default valeur after reset” in Section : Common memory space \ntiming register 2..4 (FMC_PMEM2..4), Section : Attribute memory space timing \nregisters 2..4 (FMC_PATT2..4), and Section : I/O space timing register 4 \n(FMC_PIO4).\nUpdated BUSTURN definition in Table 288: FMC_BTRx bit fields.\nUpdated REV_ID bits in Section 38.6.1: MCU device ID code.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1732, "page_indices": { "start_index": 3361692, "end_index": 3363567 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1732 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Revision history\nRM0090\n1732/1757\nRM0090 Rev 21\n15-May-2014\n7\nEmbedded Flash memory interface:\nUpdated Section : Physical remap in STM32F42xxx and STM32F43xxx. Updated \nbank 2 selection in Section 2.4: Boot configuration. Updated notes related to MERx \nand SER bits in Section : Mass Erase. Updated Section 3.7.5: Proprietary code \nreadout protection (PCROP). Updated FLASH_OPTCR register reset value for \nSTM32F42/43xx in Section 3.9.10: Flash option control register (FLASH_OPTCR) \nfor STM32F42xxx and STM32F43xxx and Section 3.9.11: Flash option control \nregister (FLASH_OPTCR1) for STM32F42xxx and STM32F43xxx.\nRCC (STM32F42/43xx): \nUpdated PPLN caution note in Section 6.3.2: RCC PLL configuration register \n(RCC_PLLCFGR)\nSYSCFG\nUpdated MEM_MODE in Section 9.3.1: SYSCFG memory remap register \n(SYSCFG_MEMRMP)\nLTDC: \nChanged resolution do XGA (1024x768) in Section 16.2: LTDC main features, \nSection 16.4.1: LTDC Global configuration parameters, and updated Section \n16.7.3: LTDC Active Width Configuration Register (LTDC_AWCR).\nRTC\nAdded note in Section 26.3.14: Calibration clock output.\nTIMER 1/8: \nRemoved note related to IC1F bits in Section 17.4.7: TIM1 and TIM8 \ncapture/compare mode register 1 (TIMx_CCMR1), \nTIM2 to 5: \nReplaced IC2S by CC2S. \nUpdated Figure 161: Output stage of capture/compare channel (channel 1). \nRemoved note related to IC1F bits in Section 18.4.7: TIMx capture/compare mode \nregister 1 (TIMx_CCMR1).\nTIM9 to 14: \nRemoved note related to IC1F bits in Section 19.5.5: TIM10/11/13/14 \ncapture/compare mode register 1 (TIMx_CCMR1).\nUSB OTG-HS:\nUpdated DSPD definition in Section : OTG_HS device configuration register \n(OTG_HS_DCFG).\nFSMC\nUpdated DATLAT bits definition in Section : SRAM/NOR-Flash chip-select timing \nregisters 1..4 (FSMC_BTR1..4).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1733, "page_indices": { "start_index": 3363567, "end_index": 3364073 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1733 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090 Rev 21\n1733/1757\nRM0090\nRevision history\n1751\n15-May-2014\n7 \n(continued)\nFMC\nUpdated Figure 474: Synchronous multiplexed read mode waveforms - NOR, \nPSRAM (CRAM). Updated DATLAT bits definition in Section : SRAM/NOR-Flash \nchip-select timing registers 1..4 (FMC_BTR1..4). \nUpdated FMC_BWTRx register address offsets in Table 297: FMC register map.\nDEBUG\nAdded revision code ‘3’ in Section : DBGMCU_IDCODE.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1734, "page_indices": { "start_index": 3364073, "end_index": 3365676 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1734 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Revision history\nRM0090\n1734/1757\nRM0090 Rev 21\n14-Oct-2014\n8\nMemory and bus architecture: \nUpdated Table 3: Memory mapping vs. Boot mode/physical remap in \nSTM32F405xx/07xx and STM32F415xx/17xx and Table 4: Memory mapping vs. \nBoot mode/physical remap in STM32F42xxx and STM32F43xxx.\nRCC (STM32F40/41xx) and RCC (STM32F42/43xx): \nRemoved all references to Flash programming manual. Changed \nRCC_AHB1LPENR, RCC_APB1LPENR, RCC_APB2LPENR, RCC_PLLI2SCFGR \nand RCC_APB2LPENR reset values.\nUpdated access type to “r” for bits 24 to 31 in RCC_CSR. \nGPIOs:\nUpdated Figure 27: Selecting an alternate function on STM32F42xxx and \nSTM32F43xxx.\nIWDG\nUpdate note in Table 107: Min/max IWDG timeout period (in ms) at 32 kHz (LSI).\nCRYPTO and HASH\nRemoved STM32F405/407xx and STM32F42xx from the whole sections. \nRemoved STM32F405/407xx and STM32F42xx from the whole section. \nTIM10/11/13/14\nAdded TIMx_DIER description in Section 19.5: TIM10/11/13/14 registers.\nETHERNET:\nUpdated Table 187: Clock range.\nUSB OTG FS:\nRemoved TRDT formula in Section 34.17.7: Worst case response time and added \nTable 203: TRDT values.\nUSB OTG HS:\nRemoved TRDT formula in Section 35.13.8: Worst case response time and added \nTable 213: TRDT values.\nFSMC:\nUpdated EXTMOD definition in Section : SRAM/NOR-Flash chip-select control \nregisters 1..4 (FSMC_BCR1..4).\nUpdated ADDSET definition in Section : SRAM/NOR-Flash chip-select timing \nregisters 1..4 (FSMC_BTR1..4) and Section : SRAM/NOR-Flash write timing \nregisters 1..4 (FSMC_BWTR1..4).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1735, "page_indices": { "start_index": 3365676, "end_index": 3366331 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1735 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090 Rev 21\n1735/1757\nRM0090\nRevision history\n1751\n14-Oct-2014\n8 \n(continued)\nFMC:\nModified step 7 in Section : SDRAM initialization.\nModified SDRAM refresh rate equations and example in Section : SDRAM Refresh \nTimer register (FMC_SDRTR) and updated definition of COUNT bits. \nUpdated EXTMOD definition in Section : SRAM/NOR-Flash chip-select control \nregisters 1..4 (FMC_BCR1..4).\nUpdated ADDSET definition in Section : SRAM/NOR-Flash chip-select timing \nregisters 1..4 (FMC_BTR1..4) and Section : SRAM/NOR-Flash write timing \nregisters 1..4 (FMC_BWTR1..4).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1736, "page_indices": { "start_index": 3366331, "end_index": 3368183 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1736 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Revision history\nRM0090\n1736/1757\nRM0090 Rev 21\n16-Mar-2015\n9\nPWR: \nUpdated Section 5.1.2: Battery backup domain.\nUpdated Table 23: Low-power mode summary to add Return from ISR as entry \ncondition. \nAdded Section : Entering low-power mode and Section : Exiting low-power mode.\nUpdated Section : Entering Sleep mode, Section : Exiting Sleep mode, Table 24: \nSleep-now entry and exit and Table 25: Sleep-on-exit entry and exit.\nUpdated Section : Entering Stop mode (for STM32F405xx/07xx and \nSTM32F415xx/17xx), Section : Exiting Stop mode (for STM32F405xx/07xx and \nSTM32F415xx/17xx) and Table 27: Stop mode entry and exit (for \nSTM32F405xx/07xx and STM32F415xx/17xx). Updated Section : Entering Stop \nmode (STM32F42xxx and STM32F43xxx), Section : Exiting Stop mode \n(STM32F42xxx and STM32F43xxx) and Table 29: Stop mode entry and exit \n(STM32F42xxx and STM32F43xxx).\nUpdated Section : Entering Standby mode, Section : Exiting Standby mode and \nTable 30: Standby mode entry and exit.\nRCC:\nUpdated bits 24 to 31 access type in Section 7.3.21: RCC clock control & status \nregister (RCC_CSR). \nGPIOs:\nAdded port A reset value in Section 8.4.3: GPIO port output speed register \n(GPIOx_OSPEEDR) (x = A..I/J/K).\nDMA:\nUpdate FTH[1:0] description in Section 10.5.10: DMA stream x FIFO control \nregister (DMA_SxFCR) (x = 0..7).\nTIM2/5:\nRegister format changed to 32 bits instead of 16 in Section 18.4.10: TIMx counter \n(TIMx_CNT) and Section 18.4.12: TIMx auto-reload register (TIMx_ARR).\nTIM9 to 14: \nUpdated Table 101: TIMx internal trigger connection\nWWDG:\nUpdated Figure 214: Watchdog block diagram and Section 22.4: How to program \nthe watchdog timeout. \nUpdated Figure 215: Window watchdog timing diagram\nRNG:\nReplaced PLL48CLK by RNG_CLK in the whole section. \nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1737, "page_indices": { "start_index": 3368183, "end_index": 3369132 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1737 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090 Rev 21\n1737/1757\nRM0090\nRevision history\n1751\n16-Mar-2015\n9 \n(continued)\nI2C2: \nUpdated FREQ[5:0] description in Section 27.6.2: I2C Control register 2 \n(I2C_CR2). \nUSART:\nRemoved note related to RXNEIE in Section : Reception using DMA\nFSMC:\nUpdated Figure 474: Synchronous multiplexed read mode waveforms - NOR, \nPSRAM (CRAM).\nUSB OTG FS\nUpdated Table 203: TRDT values\nFMC\nUpdated FMC_NL in Figure 456: FMC block diagram.\nUpdated ‘Memory wait’ and ‘Memory data bus high-z’ parameters in Table 289: \nProgrammable NAND Flash/PC Card access parameters.\nUpdated Section : Common memory space timing register 2..4 (FMC_PMEM2..4).\nUpdated Figure 476: NAND Flash/PC Card controller waveforms for common \nmemory access.\nDEBUG:\nUpdated REV_ID[15:0) and JTAG ID code in Section 38.6.1: MCU device ID code \nand Section 38.6.2: Boundary scan TAP, respectively\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1738, "page_indices": { "start_index": 3369132, "end_index": 3371235 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1738 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Revision history\nRM0090\n1738/1757\nRM0090 Rev 21\n28-Jul-2015\n10\nEmbedded Flash memory interface\nUpdated Section 3.7.5: Proprietary code readout protection (PCROP),\nPower controller (PWR)\nAdded the last sentence in Subsection: Entering low-power mode of Section 5.3: \nLow-power modes,\nAdded the bullet points about the interrupt in mode entry in Table 24: Sleep-now \nentry and exit, Table 25: Sleep-on-exit entry and exit, Table 27: Stop mode entry \nand exit (for STM32F405xx/07xx and STM32F415xx/17xx), Table 29: Stop mode \nentry and exit (STM32F42xxx and STM32F43xxx)\nAdded the last point to Mode entry, on return from ISR in Table 30: Standby mode \nentry and exit,\nAdded the note in Section: Entering sleep mode in Section 5.3.3: Sleep mode.\nGeneral-purpose I/Os (GPIO)\nUpdated OSPEED[1:0] definition of GPIOx_OSPEEDR register in Section 8.4.3: \nGPIO port output speed register (GPIOx_OSPEEDR) (x = A..I/J/K)\nLCD-TFT Controller (LTDC)\nCorrected the bit field for WHSTPOS in the second bullet point in Section: Window \nin Section 16.4.2: Layer programmable parameters.\nAdvanced-control timers (TIM1&TIM8)\nAdded the note in Section 17.3.20: Timer synchronization,\nUpdated ETF[3:0] description in Section 17.4.3: TIM1 and TIM8 slave mode control \nregister (TIMx_SMCR),\nUpdated IC1F[3:0] description in Section 17.4.7: TIM1 and TIM8 capture/compare \nmode register 1 (TIMx_CCMR1),\nAdded the note to MMS2 bit description in Section 17.4.8: TIM1 and TIM8 \ncapture/compare mode register 2 (TIMx_CCMR2),\nAdded the note to SMS[2:0] bit description in Section 17.4.3: TIM1 and TIM8 slave \nmode control register (TIMx_SMCR).\nGeneral-purpose timers (TIM2 to TIM5)\nAdded the note in Section 18.3.15: Timer synchronization,\nUpdated SMS[2:0] description in Section 18.4.3: TIMx slave mode control register \n(TIMx_SMCR),\nAdded the note to MMS2 bit description in Section 18.4.2: TIMx control register 2 \n(TIMx_CR2),\nAdded the note to SMS[2:0] bit description in Section 18.4.3: TIMx slave mode \ncontrol register (TIMx_SMCR).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1739, "page_indices": { "start_index": 3371235, "end_index": 3372833 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1739 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090 Rev 21\n1739/1757\nRM0090\nRevision history\n1751\n28-Jul-2015\n10 \n(Continued)\nGeneral-purpose timers (TIM9 to TIM14)\nAdded the note in Section 19.3.12: Timer synchronization (TIM9/12),\nAdded the note to MMS2 bit description,\nAdded the note to SMS[2:0] bit description in Section 19.4.2: TIM9/12 slave mode \ncontrol register (TIMx_SMCR).\nWindow watchdog (WWDG)\nUpdated.Figure 214: Watchdog block diagram\nController area network (bxCAN)\nReplaced tCAN with tq,\nFlexible static memory controller (FSMC)\nAdded the paragraph about Cross boundary page for Cellular RAM 1.5 in Section \n36.5.5: Synchronous transactions,\nUpdated MEMHIZx, MEMHOLDx, MEMSETx bit field descriptions for \nFSMC_PME2..4 register in Section 36.5.5: Synchronous transactions,\nUpdated ATTSET, ATTHOLD, ATTHIZ bit field descriptions for FSMC_PATT2..4 \nregister in Section 36.5.5: Synchronous transactions,\nUpdated IRS and IFS bit descriptions for FMC_SR2..4 in Section 36.5.5: \nSynchronous transactions,\nRenamed ADDSET as ADDSET[3:0] and MTYP as MTYP[1:0],\nAddition of CPSIZE in FSMC_BCRx bit fields in Table 226: FSMC_BCRx bit fields, \nTable 228: FSMC_BCRx bit fields, Table 231: FSMC_BCRx bit fields, Table 234: \nFSMC_BCRx bit fields, Table 237: FSMC_BCRx bit fields, Table 240: FSMC_BCRx \nbit fields, Table 242: FSMC_BCRx bit fields,\nAdded CPIZE[2:0] in FMC_BCR1...4 registers in ,Section 36.5.6: NOR/PSRAM \ncontrol registers Section NOR/PSRAM control re\nAdded CPSIZE[2:0] for FMC_BCRx registers in Section 36.6.9: FSMC register \nmap.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1740, "page_indices": { "start_index": 3372833, "end_index": 3374410 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1740 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Revision history\nRM0090\n1740/1757\nRM0090 Rev 21\n28-Jul-2015\n10 \n(Continued)\nFlexible memory controller (FMC)\nAdded the paragraph about Cross boundary page for Cellular RAM 1.5 in Section \n37.5.5: Synchronous transactions,\nUpdated BUSTURN bit field description for FMC_BTR1..4 register in Section \n37.5.6: NOR/PSRAM controller registers,\nUpdated MEMHIZx, MEMHOLDx, MEMSETx bit field descriptions for \nFMC_PME2..4 register in Section 37.6.8: NAND Flash/PC Card controller registers,\nUpdated ATTSET, ATTHOLD, ATTHIZ bit field descriptions for FMC_PATT2..4 \nregister in Section 37.6.8: NAND Flash/PC Card controller registers,\nUpdated IRS and IFS bit descriptions for FMC_SR2..4 in Section 37.6.8: NAND \nFlash/PC Card controller registers,\nUpdated the section SDRAM initialization with the last item in the numbered list in \nSection 37.7.5: SDRAM controller registers,\nRenamed ADDSET as ADDSET[3:0] and MTYP as MTYP[1:0],\nAddition of CPSIZE in Table 269: FMC_BCRx bit fields, Table 271: FMC_BCRx bit \nfields, Table 274: FMC_BCRx bit fields, Table 277: FMC_BCRx bit fields, Table 280: \nFMC_BCRx bit fields, Table 283: FMC_BCRx bit fields, Table 285: FMC_BCRx bit \nfields, Table 287: FMC_BCRx bit fields,\nAdded the paragraph about Cross boundary page for Cellular RAM 1.5 in Section \n37.5.5: Synchronous transactions,\nAdded CPIZE[2:0] in FMC_BCR1...4 registers in Section 37.5.6: NOR/PSRAM \ncontroller registers, \nAdded CPSIZE[2:0] for FMC_BCRx registers in Section 37.8: FMC register map.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1741, "page_indices": { "start_index": 3374410, "end_index": 3376125 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1741 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090 Rev 21\n1741/1757\nRM0090\nRevision history\n1751\n20-Oct-2015\n11\nReset and clock controller (RCC)\nUpdated STM32F405/407/415/417xx Figure 21: Clock tree.\nUpdated \nGeneral purpose I/O (GPIOs)\nChanged definition of OSPEEDR bits in Section 8.4.3: GPIO port output speed \nregister (GPIOx_OSPEEDR) (x = A..I/J/K).\nLCD-TFT display controller (LTDC):\nChanged LRDC_IER into LTDC_IER in Section 16.5: LTDC interrupts. \nUpdated AHBP[11:0], AAV[11:0 and TOTALW[11:0 in Table 92: LTDC register map \nand reset values.\nController area network (bxCAN):\nUpdated Section 32.3.4: Acceptance filters and Section 32.7.4: Identifier filtering.\nFlexible static memory controller (FSMC)\nUpdated BUSTURN description in Section : SRAM/NOR-Flash write timing \nregisters 1..4 (FSMC_BWTR1..4) and Section : SRAM/NOR-Flash chip-select \ntiming registers 1..4 (FSMC_BTR1..4)\nUpdated note related to IRS and IFS bits in Section : FIFO status and interrupt \nregister 2..4 (FSMC_SR2..4).\nFlexible memory controller (FMC)\nUpdated paragraph related to the cacheable read FIFO in Section : SDRAM \ncontroller read cycle.\nUpdated BUSTURN description in Section : SRAM/NOR-Flash write timing \nregisters 1..4 (FMC_BWTR1..4) and Section : SRAM/NOR-Flash chip-select timing \nregisters 1..4 (FMC_BTR1..4).\nUpdated note related to IRS and IFS bits in Section : FIFO status and interrupt \nregister 2..4 (FMC_SR2..4).\nReal-time clock (RTC2)\nUpdated WUCKSEL prescaler input in Figure 237: RTC block diagram.\nUpdated 3rd step in Section : Programming the wakeup timer.\nUpdated WUTWF bit definition in Section 26.6.4: RTC initialization and status \nregister (RTC_ISR).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1742, "page_indices": { "start_index": 3376125, "end_index": 3378253 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1742 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Revision history\nRM0090\n1742/1757\nRM0090 Rev 21\n17-May-2016\n12\n Flash memory interface\nRemoved note related to boot from Bank 2 in Section 2.4: Boot configuration.\nUpdated notes in Section 3.7.3: Read protection (RDP).\nChanged number of LATENCY bits in Section 3.9.2: Flash access control register \n(FLASH_ACR) for STM32F42xxx and STM32F43xxx\nIn Table 9: 1 Mbyte dual bank Flash memory organization (STM32F42xxx and \nSTM32F43xxx): updated sector 19 size and option bytes (bank 2) address range.\nPower control (PWR) \nRemoved reference to low-power mode in Section 5.1.4: Voltage regulator for \nSTM32F42xxx and STM32F43xxx, Section : Entering Stop mode (STM32F42xxx \nand STM32F43xxx) and Section : Exiting Stop mode (STM32F42xxx and \nSTM32F43xxx).\nAnalog-to-digital converter (ADC)\nAdded note related to ADC_HTR and ADC_LTR register programming in Section \n13.13.7: ADC watchdog higher threshold register (ADC_HTR) and Section 13.13.8: \nADC watchdog lower threshold register (ADC_LTR).\nChrom-Art Accelerator™ controller (DMA2D)\nUpdated Section 11.3.12: DMA2D transfer control (start, suspend, abort and \ncompletion).\nSection 11.5.8: DMA2D foreground PFC control register (DMA2D_FGPFCCR): \nupdated START bit access type\nSection 11.5.10: DMA2D background PFC control register (DMA2D_BGPFCCR): \nupdated START bit access and description. \nLCD-TFT controller (LTDC)\nUpdated Section 16.3.2: LTDC reset and clocks. \nModified LCD_DE description in Table 89: LCD-TFT pins and signal interface.\nModified Section 16.7.15: LTDC Layerx Window Horizontal Position Configuration \nRegister (LTDC_LxWHPCR) (where x=1..2) and Section 16.7.16: LTDC Layerx \nWindow Vertical Position Configuration Register (LTDC_LxWVPCR) (where \nx=1..2).\nGeneral-purpose timers (TIM2 to TIM5)\nUpdated Section 18.4.11: TIMx prescaler (TIMx_PSC).\nGeneral-purpose timers (TIM9 to TIM14)\nAdded OPM bit in Section 19.5.1: TIM10/11/13/14 control register 1 (TIMx_CR1).\nUpdated Section 19.4.9: TIM9/12 prescaler (TIMx_PSC) and Section 19.5.8: \nTIM10/11/13/14 prescaler (TIMx_PSC).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1743, "page_indices": { "start_index": 3378253, "end_index": 3380263 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1743 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090 Rev 21\n1743/1757\nRM0090\nRevision history\n1751\n17-May-2016\n12 \n(continued)\nGeneral-purpose timers (TIM6 and TIM7)\nUpdated Section 20.4.7: TIM6 and TIM7 prescaler (TIMx_PSC).\nReal-time clock (RTC)\nUpdated conditions for running under System reset in Section 26.3.7: Resetting the \nRTC.\nUpdated Section 26.3.14: Calibration clock output.\nAdded note related to TSE in Section 26.6.3: RTC control register (RTC_CR). \nUpdated caution note related to TAMP1TRG in Section 26.6.17: RTC tamper and \nalternate function configuration register (RTC_TAFCR) register.\nUniversal synchronous asynchronous receiver transmitter (USART)\nReplaced all occurrences of nCTS by CTS, nRTS by RTS and SCLK by CK.\nFlexible static memory controller (FSMC)\nUpdated Section 36.3: AHB interface.\nAdded note related to the hold phase delay below Figure 454: NAND/PC Card \ncontroller timing for common memory access. \nUpdated Section 36.6.5: NAND Flash prewait functionality.\nUpdated BUSTURN description in Section : SRAM/NOR-Flash chip-select timing \nregisters 1..4 (FSMC_BTR1..4).\nUpdated MEMHOLDx in Section : Common memory space timing register 2..4 \n(FSMC_PMEM2..4) and ATTHOLD in Section : Attribute memory space timing \nregisters 2..4 (FSMC_PATT2..4).\nFlexible memory controller (FMC)\nUpdated Section 37.3: AHB interface.\nAdded note related to the hold phase delay below Figure 476: NAND Flash/PC \nCard controller waveforms for common memory access. \nUpdated Section 37.6.5: NAND Flash prewait functionality.\nUpdated BUSTURN description in Section : SRAM/NOR-Flash chip-select timing \nregisters 1..4 (FMC_BTR1..4).\nUpdated MEMHOLDx in Section : Common memory space timing register 2..4 \n(FMC_PMEM2..4) and ATTHOLD in Section : Attribute memory space timing \nregisters 2..4 (FMC_PATT2..4).\nDebug (DBG)\nUpdated value to be programmed to the ETM Trace Start/stop register to enable the \ntrace in Section 38.15.4: ETM configuration example.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1744, "page_indices": { "start_index": 3380263, "end_index": 3382193 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1744 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Revision history\nRM0090\n1744/1757\nRM0090 Rev 21\n20-Sep-2016\n13\nAnalog-to-digital converter (ADC) \nUpdated DMA mode 1 and DMA mode 3 description in Section 13.9: Multi ADC \nmode.\nLCD-TFT controller\nUpdated values to be programmed to LTDC_SSCR in Section : Example of \nSynchronous timings configuration\nUpdated Section 16.4.2: Layer programmable parameters/Windowing. \nAdvanced-control timers (TIM1 and TIM8)\nUpdated Section 17.3.21: Debug mode.\nExtended Section 17.4.20: TIM1 and TIM8 DMA address for full transfer \n(TIMx_DMAR) to 32 bits. \nUpdated Table 95: Output control bits for complementary OCx and OCxN channels \nwith break feature output state for MOE = 0.\nUpdated TIM1 and TIM8 auto-reload register (TIMx_ARR) reset value. \nUpdated TIMx_CCR1/2/3/4 description when CC1 channel is configured as inputs \nand changed bit access type to rw/ro.\nGeneral-purpose timers (TIM2 to TIM5)\nUpdated TIMx auto-reload register (TIMx_ARR) reset value.\nUpdated TIMx_CCR1/2/3/4 description when CC1 channel is configured as inputs \nand changed bit access type to rw/ro.\nGeneral-purpose timers (TIM9 to TIM14)\nUpdated TIM9/12 auto-reload register (TIMx_ARR) and TIM10/11/13/14 auto-\nreload register (TIMx_ARR) reset value.\nUpdated TIMx_CCR1 description when CC1 channel is configured as inputs and \nchanged bit access type to rw/ro.\nBasic timers (TIM6 to TIM7)\nUpdated TIM6 and TIM7 auto-reload register (TIMx_ARR).\nSecure digital input/output interface (SDIO)\nUpdated Section 31.1: SDIO main features up to 50 MHz.\nUpdated Section 31.3: SDIO functional description SDIO_CK description.\nUpdated note removing 48 MHz in Section 31.9.1: SDIO power control register \n(SDIO_POWER), Section 31.9.2: SDI clock control register (SDIO_CLKCR), \nSection 31.9.4: SDIO command register (SDIO_CMD) and Section 31.9.9: SDIO \ndata control register (SDIO_DCTRL).\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1745, "page_indices": { "start_index": 3382193, "end_index": 3384444 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1745 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090 Rev 21\n1745/1757\nRM0090\nRevision history\n1751\n20-Sep-2016\n13 \n(continued)\nFMC\nUpdate BUSTURN bit description in Section : SRAM/NOR-Flash chip-select timing \nregisters 1..4 (FMC_BTR1..4) and Section : SRAM/NOR-Flash write timing \nregisters 1..4 (FMC_BWTR1..4). \nDebug support\nSpecified behavior of timers with complementary outputs in Section 38.16.2: Debug \nsupport for timers, watchdog, bxCAN and I2C. \nUpdated DBG_TIMx_STOP bit description in Section 38.16.4: Debug MCU APB1 \nfreeze register (DBGMCU_APB1_FZ) and Section 38.16.4: Debug MCU APB1 \nfreeze register (DBGMCU_APB1_FZ).\nElectronic signature\nUpdated Section 24.1: Unique device ID register (96 bits).\n21-Apr-2017\n14\nUpdated:\n– Section 5.5.2: PWR power control/status register (PWR_CSR) for STM32F42xxx \nand STM32F43xxx\n– Section 6.3.14: RCC APB2 peripheral clock enable register (RCC_APB2ENR)\n– Section 14.3.5: DAC output voltage\n– Section 38.6.1: MCU device ID code\n– Figure 237: RTC block diagram\nDeleted:\n– Section 7.3.15: RCC APB2 peripheral clock enable register(RCC_APB2ENR)\n18-Jul-2017\n15\nUpdated:\n– Section 3.9.10: Flash option control register (FLASH_OPTCR) for STM32F42xxx \nand STM32F43xxx\n– OTG_FS USB configuration register (OTG_FS_GUSBCFG)\n– Table 142: Error calculation for programmed baud rates at fPCLK = 42 MHz or \nfPCLK = 84 Hz, oversampling by 16 and Table 143: Error calculation for \nprogrammed baud rates at fPCLK = 42 MHz or fPCLK = 84 MHz, oversampling \nby 8.\n23-Apr-2018\n16\nUpdated:\n– Section 30.6.1: Status register (USART_SR)\n– Section 34.16.4: Device-mode registers\n– Section 34.17.6: Operational model\n– Section 35.12.4: Device-mode registers\n– Section 34: USB on-the-go full-speed (OTG_FS)\n– Table 199: Host-mode control and status registers (CSRs)\n– Table 205: OTG_FS register map and reset values\n– Table 210: Device-mode control and status registers\n– Table 215: OTG_HS register map and reset values\nAdded: \n– Figure 412: SOF trigger output to TIM2 ITR1 connection\n– RXOLNY register changed from SPI_CR2 to SPI_CR1 in Section 28.3.4: \nConfiguring the SPI for half-duplex communication and Unidirectional receive-\nonly procedure (BIDIMODE=0 and RXONLY=1)\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1746, "page_indices": { "start_index": 3384444, "end_index": 3385045 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1746 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Revision history\nRM0090\n1746/1757\nRM0090 Rev 21\n07-Jun-2018\n17\nUpdated:\n– Figure 16: Clock tree (STM32F42xxx an STM32F43xxx) and Figure 21: Clock \ntree (STM32F405xx/07xx and STM32F415xx/17xx)\n– Figure 27: Selecting an alternate function on STM32F42xxx and STM32F43xxx\n– Table 61: Vector table for STM32F405xx/07xx and STM32F415xx/17xx and Table \n62: Vector table for STM32F42xxx and STM32F43xxx\n– Section 29.17.5: SAI xInterrupt mask register (SAI_xIM) where x is A or B\n– Section 38.6.1: MCU device ID code\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1747, "page_indices": { "start_index": 3385045, "end_index": 3387404 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1747 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090 Rev 21\n1747/1757\nRM0090\nRevision history\n1751\n25-Feb-2019\n18\nSection 6: Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)\nUpdated OTGHSULPILPEN bit description in RCC AHB1 peripheral clock enable in \nlow power mode register (RCC_AHB1LPENR) and OTGHSULPIEN bit description \nin RCC AHB1 peripheral clock register (RCC_AHB1ENR).\nSection 7: Reset and clock control for STM32F405xx/07xx and \nSTM32F415xx/17xx(RCC):\nUpdated RCC APB2 peripheral clock enabled in low power mode register \n(RCC_APB2LPENR) reset value.\nUpdated OTGHSULPILPEN bit description in RCC AHB1 peripheral clock enable in \nlow power mode register (RCC_AHB1LPENR) and OTGHSULPIEN bit description \nin RCC AHB1 peripheral clock enable register (RCC_AHB1ENR).\nSection 13: Analog-to-digital converter (ADC)\nUpdate Section : Dual ADC mode.\nSection 17: Advanced-control timers (TIM1 and TIM8)\nUpdated Figure 113: Capture/compare channel 1 main circuit.\nFigure 19: General-purpose timers (TIM9 to TIM14)\nUpdated Figure 194: Capture/compare channel 1 main circuit.\nSection 34: USB on-the-go full-speed (OTG_FS)\nUpdated Section : SETUP and OUT data transfers and Updated Section : IN data \ntransfers. Modified Table 200: Device-mode control and status registers.\nSection 35: USB on-the-go high-speed (OTG_HS)\nUpdated Table 208: Core global control and status registers (CSRs) and Table 210: \nDevice-mode control and status registers.\nUpdated Section : OTG_HS device IN endpoint transmit FIFO size register \n(OTG_HS_DIEPTXFx) (x = 1..5, where x is the FIFO_number), Section : OTG \ndevice endpoint-x control register (OTG_HS_DIEPCTLx) (x = 0..5, where x = \nEndpoint_number), Section : OTG_HS device endpoint-x control register \n(OTG_HS_DOEPCTLx) (x = 1..5, where x = Endpoint_number), Section : OTG_HS \ndevice endpoint-x interrupt register (OTG_HS_DIEPINTx) (x = 0..5, where x = \nEndpoint_number), Section : OTG_HS device endpoint-x interrupt register \n(OTG_HS_DOEPINTx) (x = 0..5, where x = Endpoint_number), Section : OTG_HS \ndevice endpoint-x DMA address register (OTG_HS_DIEPDMAx / \nOTG_HS_DOEPDMAx) (x = 0..5, where x = Endpoint_number).\nUpdated Section : SETUP and OUT data transfers and Section : IN data transfers.\nSection 38: Debug support (DBG)\nUpdated REV_ID in DBGMCU_CR register.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1748, "page_indices": { "start_index": 3387404, "end_index": 3389540 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1748 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Revision history\nRM0090\n1748/1757\nRM0090 Rev 21\n25-Feb-2021\n19\nUpdated:\n– Section 2: Memory and bus architecture:\n– Figure 1: System architecture for STM32F405xx/07xx and STM32F415xx/17xx \ndevices\n– Figure 2: System architecture for STM32F42xxx and STM32F43xxx devices\n– Section 3: Embedded Flash memory interface:\n– Table 16: Description of the option bytes (STM32F405xx/07xx and \nSTM32F415xx/17xx)\n– Table 17: Description of the option bytes (STM32F42xxx and STM32F43xxx)\n– Section 12: Interrupts and events:\n– Table 61: Vector table for STM32F405xx/07xx and STM32F415xx/17xx\n– Table 62: Vector table for STM32F42xxx and STM32F43xxx\n– Section 13: Analog-to-digital converter (ADC):\n– Section 13.3.5: Continuous conversion mode\n– Section 13.8.1: Using the DMA\n– Section 13.10: Temperature sensor\n– Section 17: Advanced-control timers (TIM1 and TIM8):\n– Figure 86: Advanced-control timer block diagram\n– Section 17.4.9: TIM1 and TIM8 capture/compare enable register (TIMx_CCER)\n– Section 27: Inter-integrated circuit (I2C) interface:\n– Section 27.6.2: I2C Control register 2 (I2C_CR2)\n– Section 27.6.8: I2C Clock control register (I2C_CCR)\n– Section 31: Secure digital input/output interface (SDIO):\n– Section 31.9.2: SDI clock control register (SDIO_CLKCR)\n– Section 32: Controller area network (bxCAN):\n– Section 32.4.1: Initialization mode\n– Section 33: Ethernet (ETH): media access control (MAC) with DMA controller:\n– Section : TxDMA operation: default (non-OSF) mode\n– Section : Normal Tx DMA descriptors\n– Section 35: USB on-the-go high-speed (OTG_HS):\n– Section : Host port power\n– Section : OTG_HS core interrupt register (OTG_HS_GINTSTS)\n– Section : OTG_HS all endpoints interrupt mask register (OTG_HS_DAINTMSK)\n– Table 215: OTG_HS register map and reset values\n– Section 35.13.2: Host initialization\n– Figure 416: Transmit FIFO write task\n– Figure 417: Receive FIFO read task\n– Figure 426: Receive FIFO packet read in slave mode\n– Figure 427: Processing a SETUP packet\n– Section 38: Debug support (DBG):\n– Section : DBGMCU_IDCODE\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1749, "page_indices": { "start_index": 3389540, "end_index": 3392007 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1749 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090 Rev 21\n1749/1757\nRM0090\nRevision history\n1751\n05-Feb-2024\n20\nSection : Introduction:\n– Mentioned that the microcontrollers include ST state-of-the-art patented \ntechnology\n– Added errata sheets in the list of reference documents. \nSection 2: Memory and bus architecture\n– Section 2.3.1: Embedded SRAM, updated the SRAM that can be accessed \nthrough System or I-Code/D-Code bus.\nSection 3.4: Embedded flash memory in STM32F42xxx and STM32F43xxx\n– Updated Bank 2 section 14 base address in Table 12: Flash module - 2 Mbyte \ndual bank organization (STM32F42xxx and STM32F43xxx).\n– Specified that dual bank organization is not available on 512 Kbyte devices, and \nadded Table 16: 512 Kbyte single bank flash memory organization \n(STM32F42xxx and STM32F43xxx).\n– Updated Section 3.8.2: Program/erase parallelism.\n– In Section 3.9.3: Read protection (RDP), added note concerning RDP when \ndebugger is connected through JTAG/SWD. \nSection 5: Power controller (PWR)\n– Updated Figure 12: Power-on reset/power-down reset waveform.\n– Updated no external battery use case in Section 5.1.2: Battery backup domain.\n– Updated DBP bit description in PWR power control register (PWR_CR) for \nSTM32F405xx/07xx and STM32F415xx/17xx and PWR power control register \n(PWR_CR) for STM32F42xxx and STM32F43xxx.\n– Updated BRE bit description in PWR power control/status register (PWR_CSR) \nfor STM32F405xx/07xx and STM32F415xx/17xx and PWR power control/status \nregister (PWR_CSR) for STM32F42xxx and STM32F43xxx.\nSection 6: Reset and clock control for STM32F42xxx and STM32F43xxx and \nNA(RCC)\n– Updated Section 6.1.1: System reset and Section 6.1.3: Backup domain reset.\n– Updated ethernet PTP clock in Figure 16: Clock tree.\n– Added note regarding backup domain reset in BDRST bit of RCC Backup domain \ncontrol register (RCC_BDCR).\n– Added register reset values in Table 38: RCC register map and reset values for \nSTM32F42xxx and STM32F43xxx\nSection 7: Reset and clock control for STM32F405xx/07xx and \nSTM32F415xx/17xx(RCC)\n– Updated Section 7.1.1: System reset and Section 7.1.3: Backup domain reset.\n– Updated ethernet PTP clock in Figure 21: Clock tree\n– Added note regarding backup domain reset in BDRST bit of RCC Backup domain \ncontrol register (RCC_BDCR).\n– Added register reset values in Table 39: RCC register map and reset values for \nSTM32F405xx/07xx and STM32F415xx/17xx\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1750, "page_indices": { "start_index": 3392007, "end_index": 3393877 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1750 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Revision history\nRM0090\n1750/1757\nRM0090 Rev 21\n05-Feb-2024\n20 \n(continued)\nSection 10: DMA controller (DMA)\nUpdated DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7) address \noffset.\nSection 12: Interrupts and events\nChanged Pending register (EXTI_PR) reset value to 0x0000 0000.\nSection 17: Advanced-control timers (TIM1 and TIM8)\nUpdated Section 17.3.7: PWM input mode.\nUpdated SMS in Section 17.4.3: TIM1 and TIM8 slave mode control register \n(TIMx_SMCR).\nUpdated OC1PE in Section 17.4.7: TIM1 and TIM8 capture/compare mode register \n1 (TIMx_CCMR1).\nSection 22: Window watchdog (WWDG)\nUpdated tWWDG equation in Section 22.4: How to program the watchdog timeout.\nSection 26: Real-time clock (RTC)\n– Updated HSE clock in Figure 237: RTC block diagram (NA devices).\n– Updated Section 26.3.6: Reading the calendar.\nSection 29: Serial audio interface (SAI)\n– In the whole section, replaced TDM by free protocol mode.\n– In Section 29.18.4: SAI x frame configuration register (SAI_XFRCR) where x is A \nor B, specified that FRL[7:0] must be configured when the audio block is \ndisabled.\nSection 34: USB on-the-go full-speed (OTG_FS)\n– Updated Figure 392: Device-mode FIFO address mapping and AHB FIFO \naccess mapping.\n– Modified OTG_FS USB configuration register \n(OTG_FS_GUSBCFG)OTG_FS_GUSBCFG reset value.\nSection 33: Ethernet (ETH): media access control (MAC) with DMA controller\nUpdated bits that control the checksum in Section : Transmit checksum offload\nSection 38: Debug support (DBG)\nRemoved note on APB bridge write buffer after Table 302: Flexible SWJ-DP pin \nassignment\nUpdated REV_ID[15:0] in Section : DBGMCU_IDCODE\nSection 39: Device electronic signature\nUpdated Section 39.1: Unique device ID register (96 bits)\nAdded Section 40: Important security notice.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1751, "page_indices": { "start_index": 3393877, "end_index": 3394201 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1751 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090 Rev 21\n1751/1757\nRM0090\nRevision history\n1751\n07-Jun-2024\n21\nUpdated the note in Bit[11:0] description of Section 27.6.8: I2C Clock control \nregister (I2C_CCR).\nFixed typo in Section 12.1.3: Interrupt and exception vectors.\nTable 316. Document revision history (continued)\nDate\nVersion\nChanges\n" }, { "page_number": 1752, "page_indices": { "start_index": 3394201, "end_index": 3400044 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1752 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Index\nRM0090\n1752/1751\nRM0090 Rev 21\nIndex\nA\nADC_CCR . . . . . . . . . . . . . . . . . . . . . . . . . . .430\nADC_CDR . . . . . . . . . . . . . . . . . . . . . . . . . . .433\nADC_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .419\nADC_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .421\nADC_CSR . . . . . . . . . . . . . . . . . . . . . . . . . . .429\nADC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . .428\nADC_HTR . . . . . . . . . . . . . . . . . . . . . . . . . . .424\nADC_JDRx . . . . . . . . . . . . . . . . . . . . . . . . . . .428\nADC_JOFRx . . . . . . . . . . . . . . . . . . . . . . . . .424\nADC_JSQR . . . . . . . . . . . . . . . . . . . . . . . . . .427\nADC_LTR . . . . . . . . . . . . . . . . . . . . . . . . . . . .425\nADC_SMPR1 . . . . . . . . . . . . . . . . . . . . . . . . .423\nADC_SMPR2 . . . . . . . . . . . . . . . . . . . . . . . . .423\nADC_SQR1 . . . . . . . . . . . . . . . . . . . . . . . . . .425\nADC_SQR2 . . . . . . . . . . . . . . . . . . . . . . . . . .426\nADC_SQR3 . . . . . . . . . . . . . . . . . . . . . . . . . .426\nADC_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .418\nC\nCAN_BTR . . . . . . . . . . . . . . . . . . . . . . . . . .1109\nCAN_ESR . . . . . . . . . . . . . . . . . . . . . . . . . .1108\nCAN_FA1R . . . . . . . . . . . . . . . . . . . . . . . . .1119\nCAN_FFA1R . . . . . . . . . . . . . . . . . . . . . . . .1119\nCAN_FiRx . . . . . . . . . . . . . . . . . . . . . . . . . .1120\nCAN_FM1R . . . . . . . . . . . . . . . . . . . . . . . . .1118\nCAN_FMR . . . . . . . . . . . . . . . . . . . . . . . . . .1117\nCAN_FS1R . . . . . . . . . . . . . . . . . . . . . . . . .1118\nCAN_IER . . . . . . . . . . . . . . . . . . . . . . . . . . .1106\nCAN_MCR . . . . . . . . . . . . . . . . . . . . . . . . . .1100\nCAN_MSR . . . . . . . . . . . . . . . . . . . . . . . . . .1102\nCAN_RDHxR . . . . . . . . . . . . . . . . . . . . . . . .1116\nCAN_RDLxR . . . . . . . . . . . . . . . . . . . . . . . .1116\nCAN_RDTxR . . . . . . . . . . . . . . . . . . . . . . . .1115\nCAN_RF0R . . . . . . . . . . . . . . . . . . . . . . . . .1105\nCAN_RF1R . . . . . . . . . . . . . . . . . . . . . . . . .1106\nCAN_RIxR . . . . . . . . . . . . . . . . . . . . . . . . . .1114\nCAN_TDHxR . . . . . . . . . . . . . . . . . . . . . . . .1113\nCAN_TDLxR . . . . . . . . . . . . . . . . . . . . . . . .1113\nCAN_TDTxR . . . . . . . . . . . . . . . . . . . . . . . .1112\nCAN_TIxR . . . . . . . . . . . . . . . . . . . . . . . . . .1111\nCAN_TSR . . . . . . . . . . . . . . . . . . . . . . . . . .1103\nCRC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . .115\nCRC_IDR . . . . . . . . . . . . . . . . . . . . . . . . . . . .115\nCRYP_CR . . . . . . . . . . . . . . . . . . . . . . .751, 753\nCRYP_DIN . . . . . . . . . . . . . . . . . . . . . . . . . . .757\nCRYP_DMACR . . . . . . . . . . . . . . . . . . . . . . .759\nCRYP_DOUT . . . . . . . . . . . . . . . . . . . . . . . . 758\nCRYP_IMSCR . . . . . . . . . . . . . . . . . . . . . . . . 759\nCRYP_IV0LR . . . . . . . . . . . . . . . . . . . . . . . . 763\nCRYP_IV0RR . . . . . . . . . . . . . . . . . . . . . . . . 763\nCRYP_IV1LR . . . . . . . . . . . . . . . . . . . . . . . . 764\nCRYP_IV1RR . . . . . . . . . . . . . . . . . . . . . . . . 764\nCRYP_K0LR . . . . . . . . . . . . . . . . . . . . . . . . . 761\nCRYP_K0RR . . . . . . . . . . . . . . . . . . . . . . . . . 761\nCRYP_K1LR . . . . . . . . . . . . . . . . . . . . . . . . . 762\nCRYP_K1RR . . . . . . . . . . . . . . . . . . . . . . . . . 762\nCRYP_K2LR . . . . . . . . . . . . . . . . . . . . . . . . . 762\nCRYP_K2RR . . . . . . . . . . . . . . . . . . . . . . . . . 762\nCRYP_K3LR . . . . . . . . . . . . . . . . . . . . . . . . . 762\nCRYP_K3RR . . . . . . . . . . . . . . . . . . . . . . . . . 763\nCRYP_MISR . . . . . . . . . . . . . . . . . . . . . . . . . 760\nCRYP_RISR . . . . . . . . . . . . . . . . . . . . . . . . . 760\nCRYP_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . 756\nD\nDAC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448\nDAC_DHR12L1 . . . . . . . . . . . . . . . . . . . . . . . 452\nDAC_DHR12L2 . . . . . . . . . . . . . . . . . . . . . . . 453\nDAC_DHR12LD . . . . . . . . . . . . . . . . . . . . . . 454\nDAC_DHR12R1 . . . . . . . . . . . . . . . . . . . . . . 451\nDAC_DHR12R2 . . . . . . . . . . . . . . . . . . . . . . 453\nDAC_DHR12RD . . . . . . . . . . . . . . . . . . . . . . 454\nDAC_DHR8R1 . . . . . . . . . . . . . . . . . . . . . . . 452\nDAC_DHR8R2 . . . . . . . . . . . . . . . . . . . . . . . 453\nDAC_DHR8RD . . . . . . . . . . . . . . . . . . . . . . . 455\nDAC_DOR1 . . . . . . . . . . . . . . . . . . . . . . . . . . 455\nDAC_DOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 455\nDAC_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456\nDAC_SWTRIGR . . . . . . . . . . . . . . . . . . . . . . 451\nDBGMCU_APB1_FZ . . . . . . . . . . . . . . . . . . 1708\nDBGMCU_APB2_FZ . . . . . . . . . . . . . . . . . . 1709\nDBGMCU_CR . . . . . . . . . . . . . . . . . . . . . . . 1706\nDBGMCU_IDCODE . . . . . . . . . . . . . . . . . . 1693\nDCMI_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . 470\nDCMI_CWSIZE . . . . . . . . . . . . . . . . . . . . . . . 480\nDCMI_CWSTRT . . . . . . . . . . . . . . . . . . . . . . 480\nDCMI_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . 481\nDCMI_ESCR . . . . . . . . . . . . . . . . . . . . . . . . . 478\nDCMI_ESUR . . . . . . . . . . . . . . . . . . . . . . . . . 479\nDCMI_ICR . . . . . . . . . . . . . . . . . . . . . . . . . . . 477\nDCMI_IER . . . . . . . . . . . . . . . . . . . . . . . . . . . 475\nDCMI_MIS . . . . . . . . . . . . . . . . . . . . . . . . . . . 476\nDCMI_RIS . . . . . . . . . . . . . . . . . . . . . . . . . . . 474\nDCMI_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . 473\n" }, { "page_number": 1753, "page_indices": { "start_index": 3400044, "end_index": 3405801 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1753 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090\nIndex\nRM0090 Rev 21\n1753/1751\nDMA_HIFCR . . . . . . . . . . . . . . . . . . . . . . . . .330\nDMA_HISR . . . . . . . . . . . . . . . . . . . . . . . . . . .329\nDMA_LIFCR . . . . . . . . . . . . . . . . . . . . . . . . . .330\nDMA_LISR . . . . . . . . . . . . . . . . . . . . . . . . . . .328\nDMA_SxCR . . . . . . . . . . . . . . . . . . . . . . . . . .331\nDMA_SxFCR . . . . . . . . . . . . . . . . . . . . . . . . .336\nDMA_SxM0AR . . . . . . . . . . . . . . . . . . . . . . . .335\nDMA_SxM1AR . . . . . . . . . . . . . . . . . . . . . . . .335\nDMA_SxNDTR . . . . . . . . . . . . . . . . . . . . . . . .334\nDMA_SxPAR . . . . . . . . . . . . . . . . . . . . . . . . .335\nE\nETH_DMABMR . . . . . . . . . . . . . . . . . . . . . .1226\nETH_DMACHRBAR . . . . . . . . . . . . . . . . . . .1239\nETH_DMACHRDR . . . . . . . . . . . . . . . . . . . .1238\nETH_DMACHTBAR . . . . . . . . . . . . . . . . . . .1238\nETH_DMACHTDR . . . . . . . . . . . . . . . . . . . .1238\nETH_DMAIER . . . . . . . . . . . . . . . . . . . . . . .1235\nETH_DMAMFBOCR . . . . . . . . . . . . . . . . . .1237\nETH_DMAOMR . . . . . . . . . . . . . . . . . . . . . .1232\nETH_DMARDLAR . . . . . . . . . . . . . . . . . . . .1228\nETH_DMARPDR . . . . . . . . . . . . . . . . . . . . .1228\nETH_DMARSWTR . . . . . . . . . . . . . . . . . . . .1237\nETH_DMASR . . . . . . . . . . . . . . . . . . . . . . . .1229\nETH_DMATDLAR . . . . . . . . . . . . . . . . . . . .1229\nETH_DMATPDR . . . . . . . . . . . . . . . . . . . . .1227\nETH_MACA0HR . . . . . . . . . . . . . . . . . . . . .1208\nETH_MACA0LR . . . . . . . . . . . . . . . . . . . . . .1209\nETH_MACA1HR . . . . . . . . . . . . . . . . . . . . .1209\nETH_MACA1LR . . . . . . . . . . . . . . . . . . . . . .1210\nETH_MACA2HR . . . . . . . . . . . . . . . . . . . . .1210\nETH_MACA2LR . . . . . . . . . . . . . . . . . . . . . .1211\nETH_MACA3HR . . . . . . . . . . . . . . . . . . . . .1212\nETH_MACA3LR . . . . . . . . . . . . . . . . . . . . . .1212\nETH_MACCR . . . . . . . . . . . . . . . . . . . . . . . .1194\nETH_MACDBGR . . . . . . . . . . . . . . . . . . . . .1205\nETH_MACFCR . . . . . . . . . . . . . . . . . . . . . . .1201\nETH_MACFFR . . . . . . . . . . . . . . . . . . . . . . .1197\nETH_MACHTHR . . . . . . . . . . . . . . . . . . . . .1198\nETH_MACHTLR . . . . . . . . . . . . . . . . . . . . . .1199\nETH_MACIMR . . . . . . . . . . . . . . . . . . . . . . .1208\nETH_MACMIIAR . . . . . . . . . . . . . . . . . . . . .1199\nETH_MACMIIDR . . . . . . . . . . . . . . . . . . . . .1200\nETH_MACPMTCSR . . . . . . . . . . . . . . . . . . .1204\nETH_MACRWUFFR . . . . . . . . . . . . . . . . . .1203\nETH_MACSR . . . . . . . . . . . . . . . . . . . . . . . .1207\nETH_MACVLANTR . . . . . . . . . . . . . . . . . . .1202\nETH_MMCCR . . . . . . . . . . . . . . . . . . . . . . .1213\nETH_MMCRFAECR . . . . . . . . . . . . . . . . . . .1218\nETH_MMCRFCECR . . . . . . . . . . . . . . . . . .1217\nETH_MMCRGUFCR . . . . . . . . . . . . . . . . . .1218\nETH_MMCRIMR . . . . . . . . . . . . . . . . . . . . . 1215\nETH_MMCRIR . . . . . . . . . . . . . . . . . . . . . . 1213\nETH_MMCTGFCR . . . . . . . . . . . . . . . . . . . 1217\nETH_MMCTGFMSCCR . . . . . . . . . . . . . . . 1217\nETH_MMCTGFSCCR . . . . . . . . . . . . . . . . . 1216\nETH_MMCTIMR . . . . . . . . . . . . . . . . . . . . . 1216\nETH_MMCTIR . . . . . . . . . . . . . . . . . . . . . . . 1214\nETH_PTPPPSCR . . . . . . . . . . . . . . . . . . . . 1225\nETH_PTPSSIR . . . . . . . . . . . . . . . . . . . . . . 1221\nETH_PTPTSAR . . . . . . . . . . . . . . . . . . . . . . 1223\nETH_PTPTSCR . . . . . . . . . . . . . . . . . . . . . 1218\nETH_PTPTSHR . . . . . . . . . . . . . . . . . . . . . 1221\nETH_PTPTSHUR . . . . . . . . . . . . . . . . . . . . 1222\nETH_PTPTSLR . . . . . . . . . . . . . . . . . . . . . . 1222\nETH_PTPTSLUR . . . . . . . . . . . . . . . . . . . . 1223\nETH_PTPTSSR . . . . . . . . . . . . . . . . . . . . . . 1224\nETH_PTPTTHR . . . . . . . . . . . . . . . . . . . . . . 1224\nETH_PTPTTLR . . . . . . . . . . . . . . . . . . . . . . 1224\nEXTI_EMR . . . . . . . . . . . . . . . . . . . . . . . . . . 387\nEXTI_FTSR . . . . . . . . . . . . . . . . . . . . . . . . . . 388\nEXTI_IMR . . . . . . . . . . . . . . . . . . . . . . . . . . . 387\nEXTI_PR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389\nEXTI_RTSR . . . . . . . . . . . . . . . . . . . . . . . . . . 388\nEXTI_SWIER . . . . . . . . . . . . . . . . . . . . . . . . . 389\nF\nFLITF_FCR . . . . . . . . . . . . . . . . . . . . . . 104, 106\nFLITF_FKEYR . . . . . . . . . . . . . . . . . . . . . . . . 101\nFLITF_FOPTCR . . . . . . . . . . . . . . 107, 109, 111\nFLITF_FOPTKEYR . . . . . . . . . . . . . . . . . . . . 101\nFLITF_FSR . . . . . . . . . . . . . . . . . . . . . . 102-103\nFSMC_BCR1..4 . . . . . . . . . . . . . . . . . 1580, 1643\nFSMC_BTR1..4 . . . . . . . . . . . . . . . . . 1583, 1645\nFSMC_BWTR1..4 . . . . . . . . . . . . . . . 1586, 1649\nFSMC_PCR2..4 . . . . . . . . . . . . . . . . . . . . . . 1596\nFSMC_PMEM2..4 . . . . . . . . . . . . . . . . . . . . 1598\nFSMC_SR2..4 . . . . . . . . . . . . . . . . . . . . . . . 1597\nG\nGPIOx_AFRH . . . . . . . . . . . . . . . . . . . . . . . . 289\nGPIOx_AFRL . . . . . . . . . . . . . . . . . . . . . . . . 288\nGPIOx_BSRR . . . . . . . . . . . . . . . . . . . . . . . . 287\nGPIOx_IDR . . . . . . . . . . . . . . . . . . . . . . . . . . 286\nGPIOx_LCKR . . . . . . . . . . . . . . . . . . . . . . . . 287\nGPIOx_MODER . . . . . . . . . . . . . . . . . . . . . . 284\nGPIOx_ODR . . . . . . . . . . . . . . . . . . . . . . . . . 286\nGPIOx_OSPEEDR . . . . . . . . . . . . . . . . . . . . 285\nGPIOx_OTYPER . . . . . . . . . . . . . . . . . . . . . . 284\nGPIOx_PUPDR . . . . . . . . . . . . . . . . . . . . . . . 285\n" }, { "page_number": 1754, "page_indices": { "start_index": 3405801, "end_index": 3411570 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1754 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Index\nRM0090\n1754/1751\nRM0090 Rev 21\nH\nHASH_CR . . . . . . . . . . . . . . . . . . . . . . .785, 788\nHASH_CSRx . . . . . . . . . . . . . . . . . . . . . . . . .797\nHASH_DIN . . . . . . . . . . . . . . . . . . . . . . . . . . .791\nHASH_HR0 . . . . . . . . . . . . . . . . . . . . . . . . . .793\nHASH_HR1 . . . . . . . . . . . . . . . . . . . . . . 793-794\nHASH_HR2 . . . . . . . . . . . . . . . . . . . . . . 793-794\nHASH_HR3 . . . . . . . . . . . . . . . . . . . . . . . . . .794\nHASH_HR4 . . . . . . . . . . . . . . . . . . . . . . . . . .794\nHASH_IMR . . . . . . . . . . . . . . . . . . . . . . . . . . .795\nHASH_SR . . . . . . . . . . . . . . . . . . . . . . . . . . .796\nHASH_STR . . . . . . . . . . . . . . . . . . . . . . . . . .792\nI\nI2C_CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . .873\nI2C_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .863\nI2C_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .865\nI2C_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .868\nI2C_OAR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .867\nI2C_OAR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .867\nI2C_SR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .868\nI2C_SR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .871\nI2C_TRISE . . . . . . . . . . . . . . . . . . . . . . . . . . .874\nIWDG_KR . . . . . . . . . . . . . . . . . . . . . . . . . . .713\nIWDG_PR . . . . . . . . . . . . . . . . . . . . . . . . . . .713\nIWDG_RLR . . . . . . . . . . . . . . . . . . . . . . . . . .714\nIWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . . .714\nO\nOTG_FS_CID . . . . . . . . . . . . . . . . . . . . . . . .1293\nOTG_FS_DAINT . . . . . . . . . . . . . . . . . . . . .1310\nOTG_FS_DAINTMSK . . . . . . . . . . . . . . . . .1311\nOTG_FS_DCFG . . . . . . . . . . . . . . . . . . . . . .1305\nOTG_FS_DCTL . . . . . . . . . . . . . . . . . . . . . .1306\nOTG_FS_DIEPCTL0 . . . . . . . . . . . . . . . . . .1312\nOTG_FS_DIEPCTLx . . . . . . . . . . . . . . . . . .1314\nOTG_FS_DIEPEMPMSK . . . . . . . . . . . . . . .1312\nOTG_FS_DIEPINTx . . . . . . . . . . . . . . . . . . .1321\nOTG_FS_DIEPMSK . . . . . . . . . . . . . . . . . . .1308\nOTG_FS_DIEPTSIZ0 . . . . . . . . . . . . . . . . . .1323\nOTG_FS_DIEPTSIZx . . . . . . . . . . . . . . . . . .1326\nOTG_FS_DIEPTXF0 . . . . . . . . . . . . . . . . . .1291\nOTG_FS_DIEPTXFx . . . . . . . . . . . . . . . . . .1294\nOTG_FS_DOEPCTL0 . . . . . . . . . . . . . . . . .1317\nOTG_FS_DOEPCTLx . . . . . . . . . . . . . . . . .1318\nOTG_FS_DOEPINTx . . . . . . . . . . . . . . . . . .1322\nOTG_FS_DOEPMSK . . . . . . . . . . . . . . . . . .1309\nOTG_FS_DOEPTSIZ0 . . . . . . . . . . . . . . . . .1325\nOTG_FS_DOEPTSIZx . . . . . . . . . . . . . . . . .1327\nOTG_FS_DSTS . . . . . . . . . . . . . . . . . . . . . .1307\nOTG_FS_DTXFSTSx . . . . . . . . . . . . . . . . . 1327\nOTG_FS_DVBUSDIS . . . . . . . . . . . . . . . . . 1311\nOTG_FS_DVBUSPULSE . . . . . . . . . . . . . . 1311\nOTG_FS_GAHBCFG . . . . . . . . . . . . . . . . . 1277\nOTG_FS_GCCFG . . . . . . . . . . . . . . . . . . . . 1292\nOTG_FS_GINTMSK . . . . . . . . . . . . . . . . . . 1286\nOTG_FS_GINTSTS . . . . . . . . . . . . . . . . . . 1282\nOTG_FS_GOTGCTL . . . . . . . . . . . . . . . . . . 1274\nOTG_FS_GOTGINT . . . . . . . . . . . . . . . . . . 1275\nOTG_FS_GRSTCTL . . . . . . . . . . . . . . . . . . 1280\nOTG_FS_GRXFSIZ . . . . . . . . . . . . . . . . . . 1290\nOTG_FS_GRXSTSP . . . . . . . . . . . . . . . . . . 1289\nOTG_FS_GRXSTSR . . . . . . . . . . . . . . . . . . 1289\nOTG_FS_GUSBCFG . . . . . . . . . . . . . . . . . 1278\nOTG_FS_HAINT . . . . . . . . . . . . . . . . . . . . . 1297\nOTG_FS_HAINTMSK . . . . . . . . . . . . . . . . . 1298\nOTG_FS_HCCHARx . . . . . . . . . . . . . . . . . . 1301\nOTG_FS_HCFG . . . . . . . . . . . . . . . . . . . . . 1295\nOTG_FS_HCINTMSKx . . . . . . . . . . . . . . . . 1303\nOTG_FS_HCINTx . . . . . . . . . . . . . . . . . . . . 1302\nOTG_FS_HCTSIZx . . . . . . . . . . . . . . . . . . . 1304\nOTG_FS_HFIR . . . . . . . . . . . . . . . . . . . . . . 1295\nOTG_FS_HFNUM . . . . . . . . . . . . . . . . . . . . 1296\nOTG_FS_HNPTXFSIZ . . . . . . . . . . . . . . . . 1291\nOTG_FS_HNPTXSTS . . . . . . . . . . . . . . . . . 1291\nOTG_FS_HPRT . . . . . . . . . . . . . . . . . . . . . 1298\nOTG_FS_HPTXFSIZ . . . . . . . . . . . . . . . . . . 1294\nOTG_FS_HPTXSTS . . . . . . . . . . . . . . . . . . 1296\nOTG_FS_PCGCCTL . . . . . . . . . . . . . . . . . . 1328\nOTG_HS_CID . . . . . . . . . . . . . . . . . . . . . . . 1432\nOTG_HS_DAINT . . . . . . . . . . . . . . . . . . . . . 1453\nOTG_HS_DAINTMSK . . . . . . . . . . . . . . . . . 1454\nOTG_HS_DCFG . . . . . . . . . . . . . . . . . . . . . 1446\nOTG_HS_DCTL . . . . . . . . . . . . . . . . . . . . . 1448\nOTG_HS_DEACHINT . . . . . . . . . . . . . . . . . 1457\nOTG_HS_DEACHINTMSK . . . . . . . . . . . . . 1458\nOTG_HS_DIEPCTLx . . . . . . . . . . . . . . . . . . 1460\nOTG_HS_DIEPDMAx . . . . . . . . . . . . . . . . . 1474\nOTG_HS_DIEPEACHMSK1 . . . . . . . . . . . . 1458\nOTG_HS_DIEPEMPMSK . . . . . . . . . . . . . . 1457\nOTG_HS_DIEPINTx . . . . . . . . . . . . . . . . . . 1467\nOTG_HS_DIEPMSK . . . . . . . . . . . . . . . . . . 1451\nOTG_HS_DIEPTSIZ0 . . . . . . . . . . . . . . . . . 1470\nOTG_HS_DIEPTSIZx . . . . . . . . . . . . . . . . . 1472\nOTG_HS_DIEPTXFx . . . . . . . . . . . . . . . . . . 1433\nOTG_HS_DOEPCTL0 . . . . . . . . . . . . . . . . . 1463\nOTG_HS_DOEPCTLx . . . . . . . . . . . . . . . . . 1464\nOTG_HS_DOEPDMAx . . . . . . . . . . . . . . . . 1474\nOTG_HS_DOEPEACHMSK1 . . . . . . . . . . . 1459\nOTG_HS_DOEPINTx . . . . . . . . . . . . . . . . . 1469\nOTG_HS_DOEPMSK . . . . . . . . . . . . . . . . . 1452\nOTG_HS_DOEPTSIZ0 . . . . . . . . . . . . . . . . 1471\n" }, { "page_number": 1755, "page_indices": { "start_index": 3411570, "end_index": 3417384 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1755 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090\nIndex\nRM0090 Rev 21\n1755/1751\nOTG_HS_DOEPTSIZx . . . . . . . . . . . . . . . . .1473\nOTG_HS_DSTS . . . . . . . . . . . . . . . . . . . . . .1450\nOTG_HS_DTHRCTL . . . . . . . . . . . . . . . . . .1456\nOTG_HS_DTXFSTSx . . . . . . . . . . . . . . . . .1473\nOTG_HS_DVBUSDIS . . . . . . . . . . . . . . . . .1454\nOTG_HS_DVBUSPULSE . . . . . . . . . . . . . .1455\nOTG_HS_GAHBCFG . . . . . . . . . . . . . . . . . .1414\nOTG_HS_GCCFG . . . . . . . . . . . . . . . . . . . .1431\nOTG_HS_GINTMSK . . . . . . . . . . . . . . . . . .1425\nOTG_HS_GINTSTS . . . . . . . . . . . . . . . . . . .1421\nOTG_HS_GNPTXFSIZ . . . . . . . . . . . . . . . .1430\nOTG_HS_GNPTXSTS . . . . . . . . . . . . . . . . .1430\nOTG_HS_GOTGCTL . . . . . . . . . . . . . . . . . .1411\nOTG_HS_GOTGINT . . . . . . . . . . . . . . . . . .1412\nOTG_HS_GRSTCTL . . . . . . . . . . . . . . . . . .1418\nOTG_HS_GRXFSIZ . . . . . . . . . . . . . . . . . . .1429\nOTG_HS_GRXSTSP . . . . . . . . . . . . . . . . . .1428\nOTG_HS_GRXSTSR . . . . . . . . . . . . . . . . . .1428\nOTG_HS_GUSBCFG . . . . . . . . . . . . . . . . . .1415\nOTG_HS_HAINT . . . . . . . . . . . . . . . . . . . . .1437\nOTG_HS_HAINTMSK . . . . . . . . . . . . . . . . .1437\nOTG_HS_HCCHARx . . . . . . . . . . . . . . . . . .1440\nOTG_HS_HCDMAx . . . . . . . . . . . . . . . . . . .1446\nOTG_HS_HCFG . . . . . . . . . . . . . . . . . . . . .1433\nOTG_HS_HCINTMSKx . . . . . . . . . . . . . . . .1444\nOTG_HS_HCINTx . . . . . . . . . . . . . . . . . . . .1443\nOTG_HS_HCSPLTx . . . . . . . . . . . . . . . . . .1442\nOTG_HS_HCTSIZx . . . . . . . . . . . . . . . . . . .1445\nOTG_HS_HFIR . . . . . . . . . . . . . . . . . . . . . .1435\nOTG_HS_HFNUM . . . . . . . . . . . . . . . . . . . .1435\nOTG_HS_HPRT . . . . . . . . . . . . . . . . . . . . . .1438\nOTG_HS_HPTXFSIZ . . . . . . . . . . . . . . . . . .1432\nOTG_HS_HPTXSTS . . . . . . . . . . . . . . . . . .1436\nOTG_HS_PCGCCTL . . . . . . . . . . . . . . . . . .1475\nOTG_HS_TX0FSIZ . . . . . . . . . . . . . . . . . . .1430\nP\nPWR_CR . . . . . . . . . . . . . . . . . . . . . . . .142, 146\nPWR_CSR . . . . . . . . . . . . . . . . . . . . . . .143, 149\nR\nRCC_AHB1ENR . . . . . . . . . . . . . . . . . .182, 244\nRCC_AHB1LPENR . . . . . . . . . . . . . . . .191, 252\nRCC_AHB1RSTR . . . . . . . . . . . . . . . . .172, 235\nRCC_AHB2ENR . . . . . . . . . . . . . . . . . .184, 246\nRCC_AHB2LPENR . . . . . . . . . . . . . . . .194, 254\nRCC_AHB2RSTR . . . . . . . . . . . . . . . . .175, 238\nRCC_AHB3ENR . . . . . . . . . . . . . . . . . .185, 247\nRCC_AHB3LPENR . . . . . . . . . . . . . . . .195, 255\nRCC_AHB3RSTR . . . . . . . . . . . . . . . . .176, 239\nRCC_APB1ENR . . . . . . . . . . . . . . . . . . .185, 247\nRCC_APB1LPENR . . . . . . . . . . . . . . . . 195, 256\nRCC_APB1RSTR . . . . . . . . . . . . . . . . . 176, 239\nRCC_APB2ENR . . . . . . . . . . . . . . . . . . 189, 250\nRCC_APB2LPENR . . . . . . . . . . . . . . . . 199, 259\nRCC_APB2RSTR . . . . . . . . . . . . . . . . . 180, 242\nRCC_BDCR . . . . . . . . . . . . . . . . . . . . . 201, 261\nRCC_CFGR . . . . . . . . . . . . . . . . . . . . . 167, 230\nRCC_CIR . . . . . . . . . . . . . . . . . . . . . . . 169, 232\nRCC_CR . . . . . . . . . . . . . . . . . . . . . . . . 163, 226\nRCC_CSR . . . . . . . . . . . . . . . . . . . . . . . 202, 262\nRCC_PLLCFGR . . . . . .165, 205, 208, 228, 265\nRCC_SSCGR . . . . . . . . . . . . . . . . . . . . 204, 264\nRNG_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772\nRNG_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773\nRNG_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772\nRTC_ALRMAR . . . . . . . . . . . . . . . . . . . . . . . 828\nRTC_ALRMBR . . . . . . . . . . . . . . . . . . . . . . . 829\nRTC_ALRMBSSR . . . . . . . . . . . . . . . . . . . . . 838\nRTC_BKxR . . . . . . . . . . . . . . . . . . . . . . . . . . 839\nRTC_CALIBR . . . . . . . . . . . . . . . . . . . . . . . . 827\nRTC_CALR . . . . . . . . . . . . . . . . . . . . . . . . . . 833\nRTC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821\nRTC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820\nRTC_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823\nRTC_PRER . . . . . . . . . . . . . . . . . . . . . . . . . . 826\nRTC_SHIFTR . . . . . . . . . . . . . . . . . . . . . . . . 831\nRTC_SSR . . . . . . . . . . . . . . . . . . . . . . . . . . . 830\nRTC_TR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819\nRTC_TSDR . . . . . . . . . . . . . . . . . . . . . . . . . . 832\nRTC_TSSSR . . . . . . . . . . . . . . . . . . . . . . . . . 833\nRTC_TSTR . . . . . . . . . . . . . . . . . . . . . . . . . . 831\nRTC_WPR . . . . . . . . . . . . . . . . . . . . . . . . . . . 830\nRTC_WUTR . . . . . . . . . . . . . . . . . . . . . . . . . 826\nS\nSDIO_CLKCR . . . . . . . . . . . . . . . . . . . . . . . 1064\nSDIO_DCOUNT . . . . . . . . . . . . . . . . . . . . . 1070\nSDIO_DCTRL . . . . . . . . . . . . . . . . . . . . . . . 1069\nSDIO_DLEN . . . . . . . . . . . . . . . . . . . . . . . . 1068\nSDIO_DTIMER . . . . . . . . . . . . . . . . . . . . . . 1067\nSDIO_FIFO . . . . . . . . . . . . . . . . . . . . . . . . . 1077\nSDIO_FIFOCNT . . . . . . . . . . . . . . . . . . . . . 1076\nSDIO_ICR . . . . . . . . . . . . . . . . . . . . . . . . . . 1072\nSDIO_MASK . . . . . . . . . . . . . . . . . . . . . . . . 1074\nSDIO_POWER . . . . . . . . . . . . . . . . . . . . . . 1063\nSDIO_RESPCMD . . . . . . . . . . . . . . . . . . . . 1066\nSDIO_RESPx . . . . . . . . . . . . . . . . . . . . . . . 1067\nSDIO_STA . . . . . . . . . . . . . . . . . . . . . . . . . . 1071\nSPI_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919\nSPI_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921\nSPI_CRCPR . . . . . . . . . . . . . . . . . . . . . . . . . 924\n" }, { "page_number": 1756, "page_indices": { "start_index": 3417384, "end_index": 3420045 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1756 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "Index\nRM0090\n1756/1751\nRM0090 Rev 21\nSPI_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .923\nSPI_I2SCFGR . . . . . . . . . . . . . . . . . . . . . . . .925\nSPI_I2SPR . . . . . . . . . . . . . . . . . . . . . . . . . . .927\nSPI_RXCRCR . . . . . . . . . . . . . . . . . . . . . . . .924\nSPI_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .922\nSPI_TXCRCR . . . . . . . . . . . . . . . . . . . . . . . .925\nSYSCFG_EXTICR1 . . . . . . . . . . . . . . . .294, 300\nSYSCFG_EXTICR2 . . . . . . . . . . . . . . . .294, 301\nSYSCFG_EXTICR3 . . . . . . . . . . . . . . . .295, 301\nSYSCFG_EXTICR4 . . . . . . . . . . . . . . . .296, 302\nSYSCFG_MEMRMP . . . . . . . . . . . . . . .292, 297\nT\nTIM2_OR . . . . . . . . . . . . . . . . . . . . . . . . . . . .649\nTIM5_OR . . . . . . . . . . . . . . . . . . . . . . . . . . . .650\nTIMx_ARR . . . . . . . . . . . . . . 645, 685, 695, 709\nTIMx_BDTR . . . . . . . . . . . . . . . . . . . . . . . . . .586\nTIMx_CCER . . . . . . . . . . . . . 579, 643, 684, 694\nTIMx_CCMR1 . . . . . . . . . . . 575, 639, 681, 691\nTIMx_CCMR2 . . . . . . . . . . . . . . . . . . . .577, 642\nTIMx_CCR1 . . . . . . . . . . . . . 584, 646, 686, 696\nTIMx_CCR2 . . . . . . . . . . . . . . . . . 585, 646, 686\nTIMx_CCR3 . . . . . . . . . . . . . . . . . . . . . .585, 647\nTIMx_CCR4 . . . . . . . . . . . . . . . . . . . . . .586, 647\nTIMx_CNT . . . . . . . . . . 583, 645, 685, 695, 708\nTIMx_CR1 . . . . . . . . . . 564, 630, 675, 689, 705\nTIMx_CR2 . . . . . . . . . . . . . . . . . . 565, 632, 707\nTIMx_DCR . . . . . . . . . . . . . . . . . . . . . . .588, 648\nTIMx_DIER . . . . . . . . . . 570, 635, 677, 690, 707\nTIMx_DMAR . . . . . . . . . . . . . . . . . . . . . .589, 649\nTIMx_EGR . . . . . . . . . . 573, 638, 680, 691, 708\nTIMx_PSC . . . . . . . . . . 583, 645, 685, 695, 709\nTIMx_RCR . . . . . . . . . . . . . . . . . . . . . . . . . . .584\nTIMx_SMCR . . . . . . . . . . . . . . . . . 568, 633, 676\nTIMx_SR . . . . . . . . . . . 572, 636, 679, 690, 708\nU\nUSART_BRR . . . . . . . . . . . . . . . . . . . . . . . .1013\nUSART_CR1 . . . . . . . . . . . . . . . . . . . . . . . .1013\nUSART_CR2 . . . . . . . . . . . . . . . . . . . . . . . .1016\nUSART_CR3 . . . . . . . . . . . . . . . . . . . . . . . .1017\nUSART_DR . . . . . . . . . . . . . . . . . . . . . . . . .1013\nUSART_GTPR . . . . . . . . . . . . . . . . . . . . . . .1020\nUSART_SR . . . . . . . . . . . . . . . . . . . . . . . . .1010\nW\nWWDG_CFR . . . . . . . . . . . . . . . . . . . . . . . . .721\nWWDG_CR . . . . . . . . . . . . . . . . . . . . . . . . . .720\nWWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . .721\n" }, { "page_number": 1757, "page_indices": { "start_index": 3420045, "end_index": 3421348 }, "page_meta": { "width": 595.0, "height": 842.0, "rotation": 0, "number": 1757 }, "toc_details": [ [ 1, "41 Revision history", 1720 ] ], "page_content": "RM0090 Rev 21\n1757/1757\nRM0090\n1757\nIMPORTANT NOTICE – READ CAREFULLY\nSTMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and \nimprovements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on \nST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order \nacknowledgment.\nPurchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or \nthe design of purchasers’ products.\nNo license, express or implied, to any intellectual property right is granted by ST herein.\nResale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.\nST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other \nproduct or service names are the property of their respective owners.\nInformation in this document supersedes and replaces information previously supplied in any prior versions of this document.\n© 2024 STMicroelectronics – All rights reserved\n" } ] }