---
DESIGN_NAME: rcAdder
SYNTH_POWER_DEFINE: USE_POWER_PINS
FP_PDN_CHECK_NODES: false
# FP_PDN_MULTILAYER: false
# RT_MAX_LAYER: met3
# FP_PDN_CORE_RING: true
# FP_PDN_HORIZONTAL_LAYER: met3
# FP_PDN_VERTICAL_LAYER: met4

CLOCK_PORT: clk
CLOCK_PERIOD: 25
VERILOG_FILES:
- dir::rtl/rcAdder.sv
- dir::rtl/fullAdder.sv
FP_CORE_UTIL: 40

# DESIGN_IS_CORE: false
# FP_SIZING: "absolute"
# DIE_AREA: [0, 0, 50, 50]

FP_PDN_CORE_RING: true
FP_PDN_CORE_RING_VWIDTH: 3.1
FP_PDN_CORE_RING_HWIDTH: 3.1
FP_PDN_CORE_RING_VOFFSET: 12.45
FP_PDN_CORE_RING_HOFFSET: 12.45
FP_PDN_CORE_RING_VSPACING: 1.7
FP_PDN_CORE_RING_HSPACING: 1.7

GRT_ANTENNA_ITERS: 10
RUN_HEURISTIC_DIODE_INSERTION: true
HEURISTIC_ANTENNA_THRESHOLD: 200
DESIGN_REPAIR_MAX_WIRE_LENGTH: 800
DEFAULT_CORNER: max_ss_100C_1v60
RUN_POST_GRT_DESIGN_REPAIR: true